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-rw-r--r--dts/include/dt-bindings/clock/actions,s900-cmu.h129
-rw-r--r--dts/include/dt-bindings/clock/aspeed-clock.h4
-rw-r--r--dts/include/dt-bindings/clock/axg-aoclkc.h26
-rw-r--r--dts/include/dt-bindings/clock/bcm-sr.h24
-rw-r--r--dts/include/dt-bindings/clock/gxbb-clkc.h2
-rw-r--r--dts/include/dt-bindings/clock/histb-clock.h8
-rw-r--r--dts/include/dt-bindings/clock/imx6qdl-clock.h4
-rw-r--r--dts/include/dt-bindings/clock/imx6sx-clock.h6
-rw-r--r--dts/include/dt-bindings/clock/imx6ul-clock.h33
-rw-r--r--dts/include/dt-bindings/clock/imx7d-clock.h4
-rw-r--r--dts/include/dt-bindings/clock/meson8b-clkc.h1
-rw-r--r--dts/include/dt-bindings/clock/mt2701-clk.h20
-rw-r--r--dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h44
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-msm8998.h208
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-sdm845.h239
-rw-r--r--dts/include/dt-bindings/clock/qcom,rpmh.h22
-rw-r--r--dts/include/dt-bindings/clock/qcom,videocc-sdm845.h35
-rw-r--r--dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h36
-rw-r--r--dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h62
-rw-r--r--dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h24
20 files changed, 898 insertions, 33 deletions
diff --git a/dts/include/dt-bindings/clock/actions,s900-cmu.h b/dts/include/dt-bindings/clock/actions,s900-cmu.h
new file mode 100644
index 0000000..7c12515
--- /dev/null
+++ b/dts/include/dt-bindings/clock/actions,s900-cmu.h
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree binding constants for Actions Semi S900 Clock Management Unit
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
+#define __DT_BINDINGS_CLOCK_S900_CMU_H
+
+#define CLK_NONE 0
+
+/* fixed rate clocks */
+#define CLK_LOSC 1
+#define CLK_HOSC 2
+
+/* pll clocks */
+#define CLK_CORE_PLL 3
+#define CLK_DEV_PLL 4
+#define CLK_DDR_PLL 5
+#define CLK_NAND_PLL 6
+#define CLK_DISPLAY_PLL 7
+#define CLK_DSI_PLL 8
+#define CLK_ASSIST_PLL 9
+#define CLK_AUDIO_PLL 10
+
+/* system clock */
+#define CLK_CPU 15
+#define CLK_DEV 16
+#define CLK_NOC 17
+#define CLK_NOC_MUX 18
+#define CLK_NOC_DIV 19
+#define CLK_AHB 20
+#define CLK_APB 21
+#define CLK_DMAC 22
+
+/* peripheral device clock */
+#define CLK_GPIO 23
+
+#define CLK_BISP 24
+#define CLK_CSI0 25
+#define CLK_CSI1 26
+
+#define CLK_DE0 27
+#define CLK_DE1 28
+#define CLK_DE2 29
+#define CLK_DE3 30
+#define CLK_DSI 32
+
+#define CLK_GPU 33
+#define CLK_GPU_CORE 34
+#define CLK_GPU_MEM 35
+#define CLK_GPU_SYS 36
+
+#define CLK_HDE 37
+#define CLK_I2C0 38
+#define CLK_I2C1 39
+#define CLK_I2C2 40
+#define CLK_I2C3 41
+#define CLK_I2C4 42
+#define CLK_I2C5 43
+#define CLK_I2SRX 44
+#define CLK_I2STX 45
+#define CLK_IMX 46
+#define CLK_LCD 47
+#define CLK_NAND0 48
+#define CLK_NAND1 49
+#define CLK_PWM0 50
+#define CLK_PWM1 51
+#define CLK_PWM2 52
+#define CLK_PWM3 53
+#define CLK_PWM4 54
+#define CLK_PWM5 55
+#define CLK_SD0 56
+#define CLK_SD1 57
+#define CLK_SD2 58
+#define CLK_SD3 59
+#define CLK_SENSOR 60
+#define CLK_SPEED_SENSOR 61
+#define CLK_SPI0 62
+#define CLK_SPI1 63
+#define CLK_SPI2 64
+#define CLK_SPI3 65
+#define CLK_THERMAL_SENSOR 66
+#define CLK_UART0 67
+#define CLK_UART1 68
+#define CLK_UART2 69
+#define CLK_UART3 70
+#define CLK_UART4 71
+#define CLK_UART5 72
+#define CLK_UART6 73
+#define CLK_VCE 74
+#define CLK_VDE 75
+
+#define CLK_USB3_480MPLL0 76
+#define CLK_USB3_480MPHY0 77
+#define CLK_USB3_5GPHY 78
+#define CLK_USB3_CCE 79
+#define CLK_USB3_MAC 80
+
+#define CLK_TIMER 83
+
+#define CLK_HDMI_AUDIO 84
+
+#define CLK_24M 85
+
+#define CLK_EDP 86
+
+#define CLK_24M_EDP 87
+#define CLK_EDP_PLL 88
+#define CLK_EDP_LINK 89
+
+#define CLK_USB2H0_PLLEN 90
+#define CLK_USB2H0_PHY 91
+#define CLK_USB2H0_CCE 92
+#define CLK_USB2H1_PLLEN 93
+#define CLK_USB2H1_PHY 94
+#define CLK_USB2H1_CCE 95
+
+#define CLK_DDR0 96
+#define CLK_DDR1 97
+#define CLK_DMM 98
+
+#define CLK_ETH_MAC 99
+#define CLK_RMII_REF 100
+
+#define CLK_NR_CLKS (CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
diff --git a/dts/include/dt-bindings/clock/aspeed-clock.h b/dts/include/dt-bindings/clock/aspeed-clock.h
index d3558d8..4476184 100644
--- a/dts/include/dt-bindings/clock/aspeed-clock.h
+++ b/dts/include/dt-bindings/clock/aspeed-clock.h
@@ -38,6 +38,7 @@
#define ASPEED_CLK_MAC 32
#define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34
+#define ASPEED_CLK_24M 35
#define ASPEED_RESET_XDMA 0
#define ASPEED_RESET_MCTP 1
@@ -45,8 +46,9 @@
#define ASPEED_RESET_JTAG_MASTER 3
#define ASPEED_RESET_MIC 4
#define ASPEED_RESET_PWM 5
-#define ASPEED_RESET_PCIVGA 6
+#define ASPEED_RESET_PECI 6
#define ASPEED_RESET_I2C 7
#define ASPEED_RESET_AHB 8
+#define ASPEED_RESET_CRT1 9
#endif
diff --git a/dts/include/dt-bindings/clock/axg-aoclkc.h b/dts/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 0000000..6195501
--- /dev/null
+++ b/dts/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE 0
+#define CLKID_AO_I2C_MASTER 1
+#define CLKID_AO_I2C_SLAVE 2
+#define CLKID_AO_UART1 3
+#define CLKID_AO_UART2 4
+#define CLKID_AO_IR_BLASTER 5
+#define CLKID_AO_SAR_ADC 6
+#define CLKID_AO_CLK81 7
+#define CLKID_AO_SAR_ADC_SEL 8
+#define CLKID_AO_SAR_ADC_DIV 9
+#define CLKID_AO_SAR_ADC_CLK 10
+#define CLKID_AO_ALT_XTAL 11
+
+#endif
diff --git a/dts/include/dt-bindings/clock/bcm-sr.h b/dts/include/dt-bindings/clock/bcm-sr.h
index cff6c6f..419011b 100644
--- a/dts/include/dt-bindings/clock/bcm-sr.h
+++ b/dts/include/dt-bindings/clock/bcm-sr.h
@@ -35,7 +35,7 @@
/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
#define BCM_SR_GENPLL0 0
-#define BCM_SR_GENPLL0_SATA_CLK 1
+#define BCM_SR_GENPLL0_125M_CLK 1
#define BCM_SR_GENPLL0_SCR_CLK 2
#define BCM_SR_GENPLL0_250M_CLK 3
#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
@@ -50,9 +50,11 @@
/* GENPLL 2 clock channel ID NITRO MHB*/
#define BCM_SR_GENPLL2 0
#define BCM_SR_GENPLL2_NIC_CLK 1
-#define BCM_SR_GENPLL2_250_NITRO_CLK 2
+#define BCM_SR_GENPLL2_TS_500_CLK 2
#define BCM_SR_GENPLL2_125_NITRO_CLK 3
#define BCM_SR_GENPLL2_CHIMP_CLK 4
+#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5
+#define BCM_SR_GENPLL2_FS4_CLK 6
/* GENPLL 3 HSLS clock channel ID */
#define BCM_SR_GENPLL3 0
@@ -62,11 +64,16 @@
/* GENPLL 4 SCR clock channel ID */
#define BCM_SR_GENPLL4 0
#define BCM_SR_GENPLL4_CCN_CLK 1
+#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2
+#define BCM_SR_GENPLL4_NOC_CLK 3
+#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4
+#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
/* GENPLL 5 FS4 clock channel ID */
#define BCM_SR_GENPLL5 0
-#define BCM_SR_GENPLL5_FS_CLK 1
-#define BCM_SR_GENPLL5_SPU_CLK 2
+#define BCM_SR_GENPLL5_FS4_HF_CLK 1
+#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2
+#define BCM_SR_GENPLL5_RAID_AE_CLK 3
/* GENPLL 6 NITRO clock channel ID */
#define BCM_SR_GENPLL6 0
@@ -74,13 +81,16 @@
/* LCPLL0 clock channel ID */
#define BCM_SR_LCPLL0 0
-#define BCM_SR_LCPLL0_SATA_REF_CLK 1
-#define BCM_SR_LCPLL0_USB_REF_CLK 2
-#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
+#define BCM_SR_LCPLL0_SATA_REFP_CLK 1
+#define BCM_SR_LCPLL0_SATA_REFN_CLK 2
+#define BCM_SR_LCPLL0_SATA_350_CLK 3
+#define BCM_SR_LCPLL0_SATA_500_CLK 4
/* LCPLL1 clock channel ID */
#define BCM_SR_LCPLL1 0
#define BCM_SR_LCPLL1_WAN_CLK 1
+#define BCM_SR_LCPLL1_USB_REF_CLK 2
+#define BCM_SR_LCPLL1_CRMU_TS_CLK 3
/* LCPLL PCIE clock channel ID */
#define BCM_SR_LCPLL_PCIE 0
diff --git a/dts/include/dt-bindings/clock/gxbb-clkc.h b/dts/include/dt-bindings/clock/gxbb-clkc.h
index 8ba99a5..7a892be 100644
--- a/dts/include/dt-bindings/clock/gxbb-clkc.h
+++ b/dts/include/dt-bindings/clock/gxbb-clkc.h
@@ -125,5 +125,7 @@
#define CLKID_VAPB_1 138
#define CLKID_VAPB_SEL 139
#define CLKID_VAPB 140
+#define CLKID_VDEC_1 153
+#define CLKID_VDEC_HEVC 156
#endif /* __GXBB_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/histb-clock.h b/dts/include/dt-bindings/clock/histb-clock.h
index fab30b3..136de24 100644
--- a/dts/include/dt-bindings/clock/histb-clock.h
+++ b/dts/include/dt-bindings/clock/histb-clock.h
@@ -62,6 +62,14 @@
#define HISTB_USB2_PHY1_REF_CLK 40
#define HISTB_USB2_PHY2_REF_CLK 41
#define HISTB_COMBPHY0_CLK 42
+#define HISTB_USB3_BUS_CLK 43
+#define HISTB_USB3_UTMI_CLK 44
+#define HISTB_USB3_PIPE_CLK 45
+#define HISTB_USB3_SUSPEND_CLK 46
+#define HISTB_USB3_BUS_CLK1 47
+#define HISTB_USB3_UTMI_CLK1 48
+#define HISTB_USB3_PIPE_CLK1 49
+#define HISTB_USB3_SUSPEND_CLK1 50
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1
diff --git a/dts/include/dt-bindings/clock/imx6qdl-clock.h b/dts/include/dt-bindings/clock/imx6qdl-clock.h
index da59fd9..7ad171b 100644
--- a/dts/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/dts/include/dt-bindings/clock/imx6qdl-clock.h
@@ -271,6 +271,8 @@
#define IMX6QDL_CLK_PRE_AXI 258
#define IMX6QDL_CLK_MLB_SEL 259
#define IMX6QDL_CLK_MLB_PODF 260
-#define IMX6QDL_CLK_END 261
+#define IMX6QDL_CLK_EPIT1 261
+#define IMX6QDL_CLK_EPIT2 262
+#define IMX6QDL_CLK_END 263
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/dts/include/dt-bindings/clock/imx6sx-clock.h b/dts/include/dt-bindings/clock/imx6sx-clock.h
index 36f0324..cd2d6c5 100644
--- a/dts/include/dt-bindings/clock/imx6sx-clock.h
+++ b/dts/include/dt-bindings/clock/imx6sx-clock.h
@@ -275,6 +275,10 @@
#define IMX6SX_PLL6_BYPASS 262
#define IMX6SX_PLL7_BYPASS 263
#define IMX6SX_CLK_SPDIF_GCLK 264
-#define IMX6SX_CLK_CLK_END 265
+#define IMX6SX_CLK_LVDS2_SEL 265
+#define IMX6SX_CLK_LVDS2_OUT 266
+#define IMX6SX_CLK_LVDS2_IN 267
+#define IMX6SX_CLK_ANACLK2 268
+#define IMX6SX_CLK_CLK_END 269
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/dts/include/dt-bindings/clock/imx6ul-clock.h b/dts/include/dt-bindings/clock/imx6ul-clock.h
index ee9f1a5..9564597 100644
--- a/dts/include/dt-bindings/clock/imx6ul-clock.h
+++ b/dts/include/dt-bindings/clock/imx6ul-clock.h
@@ -235,20 +235,27 @@
#define IMX6UL_CLK_CSI_PODF 222
#define IMX6UL_CLK_PLL3_120M 223
#define IMX6UL_CLK_KPP 224
+#define IMX6UL_CLK_CKO1_SEL 225
+#define IMX6UL_CLK_CKO1_PODF 226
+#define IMX6UL_CLK_CKO1 227
+#define IMX6UL_CLK_CKO2_SEL 228
+#define IMX6UL_CLK_CKO2_PODF 229
+#define IMX6UL_CLK_CKO2 230
+#define IMX6UL_CLK_CKO 231
/* For i.MX6ULL */
-#define IMX6ULL_CLK_ESAI_PRED 225
-#define IMX6ULL_CLK_ESAI_PODF 226
-#define IMX6ULL_CLK_ESAI_EXTAL 227
-#define IMX6ULL_CLK_ESAI_MEM 228
-#define IMX6ULL_CLK_ESAI_IPG 229
-#define IMX6ULL_CLK_DCP_CLK 230
-#define IMX6ULL_CLK_EPDC_PRE_SEL 231
-#define IMX6ULL_CLK_EPDC_SEL 232
-#define IMX6ULL_CLK_EPDC_PODF 233
-#define IMX6ULL_CLK_EPDC_ACLK 234
-#define IMX6ULL_CLK_EPDC_PIX 235
-#define IMX6ULL_CLK_ESAI_SEL 236
-#define IMX6UL_CLK_END 237
+#define IMX6ULL_CLK_ESAI_PRED 232
+#define IMX6ULL_CLK_ESAI_PODF 233
+#define IMX6ULL_CLK_ESAI_EXTAL 234
+#define IMX6ULL_CLK_ESAI_MEM 235
+#define IMX6ULL_CLK_ESAI_IPG 236
+#define IMX6ULL_CLK_DCP_CLK 237
+#define IMX6ULL_CLK_EPDC_PRE_SEL 238
+#define IMX6ULL_CLK_EPDC_SEL 239
+#define IMX6ULL_CLK_EPDC_PODF 240
+#define IMX6ULL_CLK_EPDC_ACLK 241
+#define IMX6ULL_CLK_EPDC_PIX 242
+#define IMX6ULL_CLK_ESAI_SEL 243
+#define IMX6UL_CLK_END 244
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/dts/include/dt-bindings/clock/imx7d-clock.h b/dts/include/dt-bindings/clock/imx7d-clock.h
index b2325d3..0d67f53 100644
--- a/dts/include/dt-bindings/clock/imx7d-clock.h
+++ b/dts/include/dt-bindings/clock/imx7d-clock.h
@@ -168,7 +168,7 @@
#define IMX7D_SPDIF_ROOT_SRC 155
#define IMX7D_SPDIF_ROOT_CG 156
#define IMX7D_SPDIF_ROOT_DIV 157
-#define IMX7D_ENET1_REF_ROOT_CLK 158
+#define IMX7D_ENET1_IPG_ROOT_CLK 158
#define IMX7D_ENET1_REF_ROOT_SRC 159
#define IMX7D_ENET1_REF_ROOT_CG 160
#define IMX7D_ENET1_REF_ROOT_DIV 161
@@ -176,7 +176,7 @@
#define IMX7D_ENET1_TIME_ROOT_SRC 163
#define IMX7D_ENET1_TIME_ROOT_CG 164
#define IMX7D_ENET1_TIME_ROOT_DIV 165
-#define IMX7D_ENET2_REF_ROOT_CLK 166
+#define IMX7D_ENET2_IPG_ROOT_CLK 166
#define IMX7D_ENET2_REF_ROOT_SRC 167
#define IMX7D_ENET2_REF_ROOT_CG 168
#define IMX7D_ENET2_REF_ROOT_DIV 169
diff --git a/dts/include/dt-bindings/clock/meson8b-clkc.h b/dts/include/dt-bindings/clock/meson8b-clkc.h
index dea9d46..a60f47b 100644
--- a/dts/include/dt-bindings/clock/meson8b-clkc.h
+++ b/dts/include/dt-bindings/clock/meson8b-clkc.h
@@ -102,5 +102,6 @@
#define CLKID_MPLL0 93
#define CLKID_MPLL1 94
#define CLKID_MPLL2 95
+#define CLKID_NAND_CLK 112
#endif /* __MESON8B_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/mt2701-clk.h b/dts/include/dt-bindings/clock/mt2701-clk.h
index 24e93df..9ac2f2b 100644
--- a/dts/include/dt-bindings/clock/mt2701-clk.h
+++ b/dts/include/dt-bindings/clock/mt2701-clk.h
@@ -171,13 +171,12 @@
#define CLK_TOP_8BDAC 151
#define CLK_TOP_WBG_DIG_416M 152
#define CLK_TOP_DPI 153
-#define CLK_TOP_HDMITX_CLKDIG_CTS 154
-#define CLK_TOP_DSI0_LNTC_DSI 155
-#define CLK_TOP_AUD_EXT1 156
-#define CLK_TOP_AUD_EXT2 157
-#define CLK_TOP_NFI1X_PAD 158
-#define CLK_TOP_AXISEL_D4 159
-#define CLK_TOP_NR 160
+#define CLK_TOP_DSI0_LNTC_DSI 154
+#define CLK_TOP_AUD_EXT1 155
+#define CLK_TOP_AUD_EXT2 156
+#define CLK_TOP_NFI1X_PAD 157
+#define CLK_TOP_AXISEL_D4 158
+#define CLK_TOP_NR 159
/* APMIXEDSYS */
@@ -194,7 +193,8 @@
#define CLK_APMIXED_HADDS2PLL 11
#define CLK_APMIXED_AUD2PLL 12
#define CLK_APMIXED_TVD2PLL 13
-#define CLK_APMIXED_NR 14
+#define CLK_APMIXED_HDMI_REF 14
+#define CLK_APMIXED_NR 15
/* DDRPHY */
@@ -431,6 +431,10 @@
#define CLK_ETHSYS_CRYPTO 8
#define CLK_ETHSYS_NR 9
+/* G3DSYS */
+#define CLK_G3DSYS_CORE 1
+#define CLK_G3DSYS_NR 2
+
/* BDP */
#define CLK_BDP_BRG_BA 1
diff --git a/dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
new file mode 100644
index 0000000..f215226
--- /dev/null
+++ b/dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Nuvoton NPCM7xx Clock Generator binding
+ * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
+ *
+ * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
+#define __DT_BINDINGS_CLOCK_NPCM7XX_H
+
+
+#define NPCM7XX_CLK_CPU 0
+#define NPCM7XX_CLK_GFX_PIXEL 1
+#define NPCM7XX_CLK_MC 2
+#define NPCM7XX_CLK_ADC 3
+#define NPCM7XX_CLK_AHB 4
+#define NPCM7XX_CLK_TIMER 5
+#define NPCM7XX_CLK_UART 6
+#define NPCM7XX_CLK_MMC 7
+#define NPCM7XX_CLK_SPI3 8
+#define NPCM7XX_CLK_PCI 9
+#define NPCM7XX_CLK_AXI 10
+#define NPCM7XX_CLK_APB4 11
+#define NPCM7XX_CLK_APB3 12
+#define NPCM7XX_CLK_APB2 13
+#define NPCM7XX_CLK_APB1 14
+#define NPCM7XX_CLK_APB5 15
+#define NPCM7XX_CLK_CLKOUT 16
+#define NPCM7XX_CLK_GFX 17
+#define NPCM7XX_CLK_SU 18
+#define NPCM7XX_CLK_SU48 19
+#define NPCM7XX_CLK_SDHC 20
+#define NPCM7XX_CLK_SPI0 21
+#define NPCM7XX_CLK_SPIX 22
+
+#define NPCM7XX_CLK_REFCLK 23
+#define NPCM7XX_CLK_SYSBYPCK 24
+#define NPCM7XX_CLK_MCBYPCK 25
+
+#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1)
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,gcc-msm8998.h b/dts/include/dt-bindings/clock/qcom,gcc-msm8998.h
new file mode 100644
index 0000000..58a242e
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 8
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 9
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 10
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 11
+#define BLSP1_UART1_APPS_CLK_SRC 12
+#define BLSP1_UART2_APPS_CLK_SRC 13
+#define BLSP1_UART3_APPS_CLK_SRC 14
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 15
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 16
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 17
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 18
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 19
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 20
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 21
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 22
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC 23
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC 24
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC 25
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC 26
+#define BLSP2_UART1_APPS_CLK_SRC 27
+#define BLSP2_UART2_APPS_CLK_SRC 28
+#define BLSP2_UART3_APPS_CLK_SRC 29
+#define GCC_AGGRE1_NOC_XO_CLK 30
+#define GCC_AGGRE1_UFS_AXI_CLK 31
+#define GCC_AGGRE1_USB3_AXI_CLK 32
+#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33
+#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34
+#define GCC_BIMC_HMSS_AXI_CLK 35
+#define GCC_BIMC_MSS_Q6_AXI_CLK 36
+#define GCC_BLSP1_AHB_CLK 37
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 38
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 39
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 40
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 41
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 42
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 43
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 44
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 45
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 46
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 47
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 48
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 49
+#define GCC_BLSP1_SLEEP_CLK 50
+#define GCC_BLSP1_UART1_APPS_CLK 51
+#define GCC_BLSP1_UART2_APPS_CLK 52
+#define GCC_BLSP1_UART3_APPS_CLK 53
+#define GCC_BLSP2_AHB_CLK 54
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 55
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 56
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 57
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 58
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 59
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 60
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 61
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 62
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK 63
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK 64
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK 65
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK 66
+#define GCC_BLSP2_SLEEP_CLK 67
+#define GCC_BLSP2_UART1_APPS_CLK 68
+#define GCC_BLSP2_UART2_APPS_CLK 69
+#define GCC_BLSP2_UART3_APPS_CLK 70
+#define GCC_CFG_NOC_USB3_AXI_CLK 71
+#define GCC_GP1_CLK 72
+#define GCC_GP2_CLK 73
+#define GCC_GP3_CLK 74
+#define GCC_GPU_BIMC_GFX_CLK 75
+#define GCC_GPU_BIMC_GFX_SRC_CLK 76
+#define GCC_GPU_CFG_AHB_CLK 77
+#define GCC_GPU_SNOC_DVM_GFX_CLK 78
+#define GCC_HMSS_AHB_CLK 79
+#define GCC_HMSS_AT_CLK 80
+#define GCC_HMSS_DVM_BUS_CLK 81
+#define GCC_HMSS_RBCPR_CLK 82
+#define GCC_HMSS_TRIG_CLK 83
+#define GCC_LPASS_AT_CLK 84
+#define GCC_LPASS_TRIG_CLK 85
+#define GCC_MMSS_NOC_CFG_AHB_CLK 86
+#define GCC_MMSS_QM_AHB_CLK 87
+#define GCC_MMSS_QM_CORE_CLK 88
+#define GCC_MMSS_SYS_NOC_AXI_CLK 89
+#define GCC_MSS_AT_CLK 90
+#define GCC_PCIE_0_AUX_CLK 91
+#define GCC_PCIE_0_CFG_AHB_CLK 92
+#define GCC_PCIE_0_MSTR_AXI_CLK 93
+#define GCC_PCIE_0_PIPE_CLK 94
+#define GCC_PCIE_0_SLV_AXI_CLK 95
+#define GCC_PCIE_PHY_AUX_CLK 96
+#define GCC_PDM2_CLK 97
+#define GCC_PDM_AHB_CLK 98
+#define GCC_PDM_XO4_CLK 99
+#define GCC_PRNG_AHB_CLK 100
+#define GCC_SDCC2_AHB_CLK 101
+#define GCC_SDCC2_APPS_CLK 102
+#define GCC_SDCC4_AHB_CLK 103
+#define GCC_SDCC4_APPS_CLK 104
+#define GCC_TSIF_AHB_CLK 105
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106
+#define GCC_TSIF_REF_CLK 107
+#define GCC_UFS_AHB_CLK 108
+#define GCC_UFS_AXI_CLK 109
+#define GCC_UFS_ICE_CORE_CLK 110
+#define GCC_UFS_PHY_AUX_CLK 111
+#define GCC_UFS_RX_SYMBOL_0_CLK 112
+#define GCC_UFS_RX_SYMBOL_1_CLK 113
+#define GCC_UFS_TX_SYMBOL_0_CLK 114
+#define GCC_UFS_UNIPRO_CORE_CLK 115
+#define GCC_USB30_MASTER_CLK 116
+#define GCC_USB30_MOCK_UTMI_CLK 117
+#define GCC_USB30_SLEEP_CLK 118
+#define GCC_USB3_PHY_AUX_CLK 119
+#define GCC_USB3_PHY_PIPE_CLK 120
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121
+#define GP1_CLK_SRC 122
+#define GP2_CLK_SRC 123
+#define GP3_CLK_SRC 124
+#define GPLL0 125
+#define GPLL0_OUT_EVEN 126
+#define GPLL0_OUT_MAIN 127
+#define GPLL0_OUT_ODD 128
+#define GPLL0_OUT_TEST 129
+#define GPLL1 130
+#define GPLL1_OUT_EVEN 131
+#define GPLL1_OUT_MAIN 132
+#define GPLL1_OUT_ODD 133
+#define GPLL1_OUT_TEST 134
+#define GPLL2 135
+#define GPLL2_OUT_EVEN 136
+#define GPLL2_OUT_MAIN 137
+#define GPLL2_OUT_ODD 138
+#define GPLL2_OUT_TEST 139
+#define GPLL3 140
+#define GPLL3_OUT_EVEN 141
+#define GPLL3_OUT_MAIN 142
+#define GPLL3_OUT_ODD 143
+#define GPLL3_OUT_TEST 144
+#define GPLL4 145
+#define GPLL4_OUT_EVEN 146
+#define GPLL4_OUT_MAIN 147
+#define GPLL4_OUT_ODD 148
+#define GPLL4_OUT_TEST 149
+#define GPLL6 150
+#define GPLL6_OUT_EVEN 151
+#define GPLL6_OUT_MAIN 152
+#define GPLL6_OUT_ODD 153
+#define GPLL6_OUT_TEST 154
+#define HMSS_AHB_CLK_SRC 155
+#define HMSS_RBCPR_CLK_SRC 156
+#define PCIE_AUX_CLK_SRC 157
+#define PDM2_CLK_SRC 158
+#define SDCC2_APPS_CLK_SRC 159
+#define SDCC4_APPS_CLK_SRC 160
+#define TSIF_REF_CLK_SRC 161
+#define UFS_AXI_CLK_SRC 162
+#define USB30_MASTER_CLK_SRC 163
+#define USB30_MOCK_UTMI_CLK_SRC 164
+#define USB3_PHY_AUX_CLK_SRC 165
+
+#define PCIE_0_GDSC 0
+#define UFS_GDSC 1
+#define USB_30_GDSC 2
+
+#define GCC_BLSP1_QUP1_BCR 0
+#define GCC_BLSP1_QUP2_BCR 1
+#define GCC_BLSP1_QUP3_BCR 2
+#define GCC_BLSP1_QUP4_BCR 3
+#define GCC_BLSP1_QUP5_BCR 4
+#define GCC_BLSP1_QUP6_BCR 5
+#define GCC_BLSP2_QUP1_BCR 6
+#define GCC_BLSP2_QUP2_BCR 7
+#define GCC_BLSP2_QUP3_BCR 8
+#define GCC_BLSP2_QUP4_BCR 9
+#define GCC_BLSP2_QUP5_BCR 10
+#define GCC_BLSP2_QUP6_BCR 11
+#define GCC_PCIE_0_BCR 12
+#define GCC_PDM_BCR 13
+#define GCC_SDCC2_BCR 14
+#define GCC_SDCC4_BCR 15
+#define GCC_TSIF_BCR 16
+#define GCC_UFS_BCR 17
+#define GCC_USB_30_BCR 18
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h b/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h
new file mode 100644
index 0000000..aca6126
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+
+/* GCC clock registers */
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
+#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
+#define GCC_BOOT_ROM_AHB_CLK 5
+#define GCC_CAMERA_AHB_CLK 6
+#define GCC_CAMERA_AXI_CLK 7
+#define GCC_CAMERA_XO_CLK 8
+#define GCC_CE1_AHB_CLK 9
+#define GCC_CE1_AXI_CLK 10
+#define GCC_CE1_CLK 11
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
+#define GCC_CPUSS_AHB_CLK 14
+#define GCC_CPUSS_AHB_CLK_SRC 15
+#define GCC_CPUSS_RBCPR_CLK 16
+#define GCC_CPUSS_RBCPR_CLK_SRC 17
+#define GCC_DDRSS_GPU_AXI_CLK 18
+#define GCC_DISP_AHB_CLK 19
+#define GCC_DISP_AXI_CLK 20
+#define GCC_DISP_GPLL0_CLK_SRC 21
+#define GCC_DISP_GPLL0_DIV_CLK_SRC 22
+#define GCC_DISP_XO_CLK 23
+#define GCC_GP1_CLK 24
+#define GCC_GP1_CLK_SRC 25
+#define GCC_GP2_CLK 26
+#define GCC_GP2_CLK_SRC 27
+#define GCC_GP3_CLK 28
+#define GCC_GP3_CLK_SRC 29
+#define GCC_GPU_CFG_AHB_CLK 30
+#define GCC_GPU_GPLL0_CLK_SRC 31
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
+#define GCC_GPU_MEMNOC_GFX_CLK 33
+#define GCC_GPU_SNOC_DVM_GFX_CLK 34
+#define GCC_MSS_AXIS2_CLK 35
+#define GCC_MSS_CFG_AHB_CLK 36
+#define GCC_MSS_GPLL0_DIV_CLK_SRC 37
+#define GCC_MSS_MFAB_AXIS_CLK 38
+#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39
+#define GCC_MSS_SNOC_AXI_CLK 40
+#define GCC_PCIE_0_AUX_CLK 41
+#define GCC_PCIE_0_AUX_CLK_SRC 42
+#define GCC_PCIE_0_CFG_AHB_CLK 43
+#define GCC_PCIE_0_CLKREF_CLK 44
+#define GCC_PCIE_0_MSTR_AXI_CLK 45
+#define GCC_PCIE_0_PIPE_CLK 46
+#define GCC_PCIE_0_SLV_AXI_CLK 47
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
+#define GCC_PCIE_1_AUX_CLK 49
+#define GCC_PCIE_1_AUX_CLK_SRC 50
+#define GCC_PCIE_1_CFG_AHB_CLK 51
+#define GCC_PCIE_1_CLKREF_CLK 52
+#define GCC_PCIE_1_MSTR_AXI_CLK 53
+#define GCC_PCIE_1_PIPE_CLK 54
+#define GCC_PCIE_1_SLV_AXI_CLK 55
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56
+#define GCC_PCIE_PHY_AUX_CLK 57
+#define GCC_PCIE_PHY_REFGEN_CLK 58
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59
+#define GCC_PDM2_CLK 60
+#define GCC_PDM2_CLK_SRC 61
+#define GCC_PDM_AHB_CLK 62
+#define GCC_PDM_XO4_CLK 63
+#define GCC_PRNG_AHB_CLK 64
+#define GCC_QMIP_CAMERA_AHB_CLK 65
+#define GCC_QMIP_DISP_AHB_CLK 66
+#define GCC_QMIP_VIDEO_AHB_CLK 67
+#define GCC_QUPV3_WRAP0_S0_CLK 68
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69
+#define GCC_QUPV3_WRAP0_S1_CLK 70
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71
+#define GCC_QUPV3_WRAP0_S2_CLK 72
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73
+#define GCC_QUPV3_WRAP0_S3_CLK 74
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75
+#define GCC_QUPV3_WRAP0_S4_CLK 76
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77
+#define GCC_QUPV3_WRAP0_S5_CLK 78
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79
+#define GCC_QUPV3_WRAP0_S6_CLK 80
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81
+#define GCC_QUPV3_WRAP0_S7_CLK 82
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83
+#define GCC_QUPV3_WRAP1_S0_CLK 84
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85
+#define GCC_QUPV3_WRAP1_S1_CLK 86
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87
+#define GCC_QUPV3_WRAP1_S2_CLK 88
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89
+#define GCC_QUPV3_WRAP1_S3_CLK 90
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91
+#define GCC_QUPV3_WRAP1_S4_CLK 92
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93
+#define GCC_QUPV3_WRAP1_S5_CLK 94
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95
+#define GCC_QUPV3_WRAP1_S6_CLK 96
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97
+#define GCC_QUPV3_WRAP1_S7_CLK 98
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103
+#define GCC_SDCC2_AHB_CLK 104
+#define GCC_SDCC2_APPS_CLK 105
+#define GCC_SDCC2_APPS_CLK_SRC 106
+#define GCC_SDCC4_AHB_CLK 107
+#define GCC_SDCC4_APPS_CLK 108
+#define GCC_SDCC4_APPS_CLK_SRC 109
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 110
+#define GCC_TSIF_AHB_CLK 111
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112
+#define GCC_TSIF_REF_CLK 113
+#define GCC_TSIF_REF_CLK_SRC 114
+#define GCC_UFS_CARD_AHB_CLK 115
+#define GCC_UFS_CARD_AXI_CLK 116
+#define GCC_UFS_CARD_AXI_CLK_SRC 117
+#define GCC_UFS_CARD_CLKREF_CLK 118
+#define GCC_UFS_CARD_ICE_CORE_CLK 119
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120
+#define GCC_UFS_CARD_PHY_AUX_CLK 121
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127
+#define GCC_UFS_MEM_CLKREF_CLK 128
+#define GCC_UFS_PHY_AHB_CLK 129
+#define GCC_UFS_PHY_AXI_CLK 130
+#define GCC_UFS_PHY_AXI_CLK_SRC 131
+#define GCC_UFS_PHY_ICE_CORE_CLK 132
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133
+#define GCC_UFS_PHY_PHY_AUX_CLK 134
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140
+#define GCC_USB30_PRIM_MASTER_CLK 141
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 142
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144
+#define GCC_USB30_PRIM_SLEEP_CLK 145
+#define GCC_USB30_SEC_MASTER_CLK 146
+#define GCC_USB30_SEC_MASTER_CLK_SRC 147
+#define GCC_USB30_SEC_MOCK_UTMI_CLK 148
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149
+#define GCC_USB30_SEC_SLEEP_CLK 150
+#define GCC_USB3_PRIM_CLKREF_CLK 151
+#define GCC_USB3_PRIM_PHY_AUX_CLK 152
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 155
+#define GCC_USB3_SEC_CLKREF_CLK 156
+#define GCC_USB3_SEC_PHY_AUX_CLK 157
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158
+#define GCC_USB3_SEC_PHY_PIPE_CLK 159
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
+#define GCC_VIDEO_AHB_CLK 162
+#define GCC_VIDEO_AXI_CLK 163
+#define GCC_VIDEO_XO_CLK 164
+#define GPLL0 165
+#define GPLL0_OUT_EVEN 166
+#define GPLL0_OUT_MAIN 167
+#define GCC_GPU_IREF_CLK 168
+#define GCC_SDCC1_AHB_CLK 169
+#define GCC_SDCC1_APPS_CLK 170
+#define GCC_SDCC1_ICE_CORE_CLK 171
+#define GCC_SDCC1_APPS_CLK_SRC 172
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 173
+#define GCC_APC_VS_CLK 174
+#define GCC_GPU_VS_CLK 175
+#define GCC_MSS_VS_CLK 176
+#define GCC_VDDA_VS_CLK 177
+#define GCC_VDDCX_VS_CLK 178
+#define GCC_VDDMX_VS_CLK 179
+#define GCC_VS_CTRL_AHB_CLK 180
+#define GCC_VS_CTRL_CLK 181
+#define GCC_VS_CTRL_CLK_SRC 182
+#define GCC_VSENSOR_CLK_SRC 183
+#define GPLL4 184
+
+/* GCC Resets */
+#define GCC_MMSS_BCR 0
+#define GCC_PCIE_0_BCR 1
+#define GCC_PCIE_1_BCR 2
+#define GCC_PCIE_PHY_BCR 3
+#define GCC_PDM_BCR 4
+#define GCC_PRNG_BCR 5
+#define GCC_QUPV3_WRAPPER_0_BCR 6
+#define GCC_QUPV3_WRAPPER_1_BCR 7
+#define GCC_QUSB2PHY_PRIM_BCR 8
+#define GCC_QUSB2PHY_SEC_BCR 9
+#define GCC_SDCC2_BCR 10
+#define GCC_SDCC4_BCR 11
+#define GCC_TSIF_BCR 12
+#define GCC_UFS_CARD_BCR 13
+#define GCC_UFS_PHY_BCR 14
+#define GCC_USB30_PRIM_BCR 15
+#define GCC_USB30_SEC_BCR 16
+#define GCC_USB3_PHY_PRIM_BCR 17
+#define GCC_USB3PHY_PHY_PRIM_BCR 18
+#define GCC_USB3_DP_PHY_PRIM_BCR 19
+#define GCC_USB3_PHY_SEC_BCR 20
+#define GCC_USB3PHY_PHY_SEC_BCR 21
+#define GCC_USB3_DP_PHY_SEC_BCR 22
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
+#define GCC_PCIE_0_PHY_BCR 24
+#define GCC_PCIE_1_PHY_BCR 25
+
+/* GCC GDSCRs */
+#define PCIE_0_GDSC 0
+#define PCIE_1_GDSC 1
+#define UFS_CARD_GDSC 2
+#define UFS_PHY_GDSC 3
+#define USB30_PRIM_GDSC 4
+#define USB30_SEC_GDSC 5
+#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6
+#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,rpmh.h b/dts/include/dt-bindings/clock/qcom,rpmh.h
new file mode 100644
index 0000000..f48fbd6
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,rpmh.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
+#define _DT_BINDINGS_CLK_MSM_RPMH_H
+
+/* RPMh controlled clocks */
+#define RPMH_CXO_CLK 0
+#define RPMH_CXO_CLK_A 1
+#define RPMH_LN_BB_CLK2 2
+#define RPMH_LN_BB_CLK2_A 3
+#define RPMH_LN_BB_CLK3 4
+#define RPMH_LN_BB_CLK3_A 5
+#define RPMH_RF_CLK1 6
+#define RPMH_RF_CLK1_A 7
+#define RPMH_RF_CLK2 8
+#define RPMH_RF_CLK2_A 9
+#define RPMH_RF_CLK3 10
+#define RPMH_RF_CLK3_A 11
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,videocc-sdm845.h b/dts/include/dt-bindings/clock/qcom,videocc-sdm845.h
new file mode 100644
index 0000000..1b86816
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+
+/* VIDEO_CC clock registers */
+#define VIDEO_CC_APB_CLK 0
+#define VIDEO_CC_AT_CLK 1
+#define VIDEO_CC_QDSS_TRIG_CLK 2
+#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3
+#define VIDEO_CC_VCODEC0_AXI_CLK 4
+#define VIDEO_CC_VCODEC0_CORE_CLK 5
+#define VIDEO_CC_VCODEC1_AXI_CLK 6
+#define VIDEO_CC_VCODEC1_CORE_CLK 7
+#define VIDEO_CC_VENUS_AHB_CLK 8
+#define VIDEO_CC_VENUS_CLK_SRC 9
+#define VIDEO_CC_VENUS_CTL_AXI_CLK 10
+#define VIDEO_CC_VENUS_CTL_CORE_CLK 11
+#define VIDEO_PLL0 12
+
+/* VIDEO_CC Resets */
+#define VIDEO_CC_VENUS_BCR 0
+#define VIDEO_CC_VCODEC0_BCR 1
+#define VIDEO_CC_VCODEC1_BCR 2
+#define VIDEO_CC_INTERFACE_BCR 3
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC 0
+#define VCODEC0_GDSC 1
+#define VCODEC1_GDSC 2
+
+#endif
diff --git a/dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h
new file mode 100644
index 0000000..34cba49
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77470 CPG Core Clocks */
+#define R8A77470_CLK_Z2 0
+#define R8A77470_CLK_ZTR 1
+#define R8A77470_CLK_ZTRD2 2
+#define R8A77470_CLK_ZT 3
+#define R8A77470_CLK_ZX 4
+#define R8A77470_CLK_ZS 5
+#define R8A77470_CLK_HP 6
+#define R8A77470_CLK_B 7
+#define R8A77470_CLK_LB 8
+#define R8A77470_CLK_P 9
+#define R8A77470_CLK_CL 10
+#define R8A77470_CLK_CP 11
+#define R8A77470_CLK_M2 12
+#define R8A77470_CLK_ZB3 13
+#define R8A77470_CLK_SDH 14
+#define R8A77470_CLK_SD0 15
+#define R8A77470_CLK_SD1 16
+#define R8A77470_CLK_SD2 17
+#define R8A77470_CLK_MP 18
+#define R8A77470_CLK_QSPI 19
+#define R8A77470_CLK_CPEX 20
+#define R8A77470_CLK_RCAN 21
+#define R8A77470_CLK_R 22
+#define R8A77470_CLK_OSC 23
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h
new file mode 100644
index 0000000..a596a48
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77990 CPG Core Clocks */
+#define R8A77990_CLK_Z2 0
+#define R8A77990_CLK_ZR 1
+#define R8A77990_CLK_ZG 2
+#define R8A77990_CLK_ZTR 3
+#define R8A77990_CLK_ZT 4
+#define R8A77990_CLK_ZX 5
+#define R8A77990_CLK_S0D1 6
+#define R8A77990_CLK_S0D3 7
+#define R8A77990_CLK_S0D6 8
+#define R8A77990_CLK_S0D12 9
+#define R8A77990_CLK_S0D24 10
+#define R8A77990_CLK_S1D1 11
+#define R8A77990_CLK_S1D2 12
+#define R8A77990_CLK_S1D4 13
+#define R8A77990_CLK_S2D1 14
+#define R8A77990_CLK_S2D2 15
+#define R8A77990_CLK_S2D4 16
+#define R8A77990_CLK_S3D1 17
+#define R8A77990_CLK_S3D2 18
+#define R8A77990_CLK_S3D4 19
+#define R8A77990_CLK_S0D6C 20
+#define R8A77990_CLK_S3D1C 21
+#define R8A77990_CLK_S3D2C 22
+#define R8A77990_CLK_S3D4C 23
+#define R8A77990_CLK_LB 24
+#define R8A77990_CLK_CL 25
+#define R8A77990_CLK_ZB3 26
+#define R8A77990_CLK_ZB3D2 27
+#define R8A77990_CLK_CR 28
+#define R8A77990_CLK_CRD2 29
+#define R8A77990_CLK_SD0H 30
+#define R8A77990_CLK_SD0 31
+#define R8A77990_CLK_SD1H 32
+#define R8A77990_CLK_SD1 33
+#define R8A77990_CLK_SD3H 34
+#define R8A77990_CLK_SD3 35
+#define R8A77990_CLK_RPC 36
+#define R8A77990_CLK_RPCD2 37
+#define R8A77990_CLK_ZA2 38
+#define R8A77990_CLK_ZA8 39
+#define R8A77990_CLK_Z2D 40
+#define R8A77990_CLK_CANFD 41
+#define R8A77990_CLK_MSO 42
+#define R8A77990_CLK_R 43
+#define R8A77990_CLK_OSC 44
+#define R8A77990_CLK_LV0 45
+#define R8A77990_CLK_LV1 46
+#define R8A77990_CLK_CSI0 47
+#define R8A77990_CLK_CP 48
+#define R8A77990_CLK_CPEX 49
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h
new file mode 100644
index 0000000..7613613
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+
+#define CLK_AR100 0
+
+#define CLK_R_APB1 2
+
+#define CLK_R_APB1_TIMER 4
+#define CLK_R_APB1_TWD 5
+#define CLK_R_APB1_PWM 6
+#define CLK_R_APB2_UART 7
+#define CLK_R_APB2_I2C 8
+#define CLK_R_APB1_IR 9
+#define CLK_R_APB1_W1 10
+
+#define CLK_IR 11
+#define CLK_W1 12
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */