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-rw-r--r--dts/Bindings/arm/altera/socfpga-sdram-edac.txt15
-rw-r--r--dts/Bindings/arm/amlogic.txt8
-rw-r--r--dts/Bindings/arm/atmel-at91.txt45
-rw-r--r--dts/Bindings/arm/bcm/bcm63138.txt9
-rw-r--r--dts/Bindings/arm/cavium-thunder.txt10
-rw-r--r--dts/Bindings/arm/cpus.txt9
-rw-r--r--dts/Bindings/arm/exynos/power_domain.txt13
-rw-r--r--dts/Bindings/arm/geniatech.txt5
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.txt23
-rw-r--r--dts/Bindings/arm/idle-states.txt679
-rw-r--r--dts/Bindings/arm/l2cc.txt10
-rw-r--r--dts/Bindings/arm/mediatek.txt6
-rw-r--r--dts/Bindings/arm/omap/mpu.txt3
-rw-r--r--dts/Bindings/arm/omap/omap.txt12
-rw-r--r--dts/Bindings/arm/psci.txt14
-rw-r--r--dts/Bindings/arm/samsung/exynos-adc.txt18
-rw-r--r--dts/Bindings/arm/shmobile.txt71
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra20-flowctrl.txt12
-rw-r--r--dts/Bindings/ata/qcom-sata.txt48
-rw-r--r--dts/Bindings/bus/bcma.txt32
-rw-r--r--dts/Bindings/clock/arm-integrator.txt2
-rw-r--r--dts/Bindings/clock/at91-clock.txt14
-rw-r--r--dts/Bindings/clock/exynos3250-clock.txt10
-rw-r--r--dts/Bindings/clock/gpio-gate-clock.txt21
-rw-r--r--dts/Bindings/clock/maxim,max77686.txt16
-rw-r--r--dts/Bindings/clock/maxim,max77802.txt44
-rw-r--r--dts/Bindings/clock/pxa-clock.txt16
-rw-r--r--dts/Bindings/clock/renesas,cpg-mstp-clocks.txt3
-rw-r--r--dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt1
-rw-r--r--dts/Bindings/clock/sunxi.txt4
-rw-r--r--dts/Bindings/cpufreq/cpufreq-dt.txt (renamed from dts/Bindings/cpufreq/cpufreq-cpu0.txt)8
-rw-r--r--dts/Bindings/crypto/fsl-sec6.txt2
-rw-r--r--dts/Bindings/dma/qcom_adm.txt62
-rw-r--r--dts/Bindings/dma/xilinx/xilinx_dma.txt65
-rw-r--r--dts/Bindings/drm/tilcdc/panel.txt7
-rw-r--r--dts/Bindings/extcon/extcon-rt8973a.txt25
-rw-r--r--dts/Bindings/gpio/gpio-dsp-keystone.txt39
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt39
-rw-r--r--dts/Bindings/gpio/gpio-restart.txt54
-rw-r--r--dts/Bindings/gpio/gpio-xgene.txt22
-rw-r--r--dts/Bindings/gpio/mrvl-gpio.txt15
-rw-r--r--dts/Bindings/hwmon/ntc_thermistor.txt3
-rw-r--r--dts/Bindings/i2c/i2c-axxia.txt30
-rw-r--r--dts/Bindings/i2c/i2c-exynos5.txt2
-rw-r--r--dts/Bindings/i2c/i2c-hix5hd2.txt24
-rw-r--r--dts/Bindings/i2c/ti,bq32k.txt18
-rw-r--r--dts/Bindings/i2c/trivial-devices.txt3
-rw-r--r--dts/Bindings/iio/adc/rockchip-saradc.txt24
-rw-r--r--dts/Bindings/iio/adc/vf610-adc.txt2
-rw-r--r--dts/Bindings/iio/dac/max5821.txt14
-rw-r--r--dts/Bindings/input/ti,drv260x.txt50
-rw-r--r--dts/Bindings/input/ti,drv2667.txt17
-rw-r--r--dts/Bindings/input/ti,palmas-pwrbutton.txt36
-rw-r--r--dts/Bindings/interrupt-controller/atmel,aic.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt86
-rw-r--r--dts/Bindings/interrupt-controller/renesas,intc-irqpin.txt8
-rw-r--r--dts/Bindings/interrupt-controller/renesas,irqc.txt32
-rw-r--r--dts/Bindings/interrupt-controller/ti,keystone-irq.txt36
-rw-r--r--dts/Bindings/iommu/arm,smmu.txt1
-rw-r--r--dts/Bindings/leds/register-bit-led.txt99
-rw-r--r--dts/Bindings/mailbox/omap-mailbox.txt108
-rw-r--r--dts/Bindings/media/hix5hd2-ir.txt25
-rw-r--r--dts/Bindings/memory-controllers/synopsys.txt11
-rw-r--r--dts/Bindings/mfd/arizona.txt7
-rw-r--r--dts/Bindings/mfd/atmel-gpbr.txt15
-rw-r--r--dts/Bindings/mfd/hi6421.txt38
-rw-r--r--dts/Bindings/mfd/max14577.txt146
-rw-r--r--dts/Bindings/mfd/qcom,spmi-pmic.txt64
-rw-r--r--dts/Bindings/mfd/qcom-pm8xxx.txt (renamed from dts/Bindings/mfd/qcom,pm8xxx.txt)1
-rw-r--r--dts/Bindings/mfd/rk808.txt177
-rw-r--r--dts/Bindings/mfd/rn5t618.txt36
-rw-r--r--dts/Bindings/mfd/s2mps11.txt2
-rw-r--r--dts/Bindings/mfd/stmpe.txt1
-rw-r--r--dts/Bindings/mfd/twl4030-power.txt9
-rw-r--r--dts/Bindings/mmc/mmc.txt2
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt6
-rw-r--r--dts/Bindings/mmc/tmio_mmc.txt3
-rw-r--r--dts/Bindings/mtd/atmel-nand.txt2
-rw-r--r--dts/Bindings/mtd/gpmc-nand.txt6
-rw-r--r--dts/Bindings/mtd/mtd-physmap.txt4
-rw-r--r--dts/Bindings/net/apm-xgene-enet.txt4
-rw-r--r--dts/Bindings/net/broadcom-mdio-unimac.txt39
-rw-r--r--dts/Bindings/net/broadcom-sf2.txt78
-rw-r--r--dts/Bindings/net/can/m_can.txt67
-rw-r--r--dts/Bindings/net/can/rcar_can.txt43
-rw-r--r--dts/Bindings/net/cpsw.txt6
-rw-r--r--dts/Bindings/net/dsa/dsa.txt17
-rw-r--r--dts/Bindings/net/emac_rockchip.txt50
-rw-r--r--dts/Bindings/net/fsl-fec.txt6
-rw-r--r--dts/Bindings/net/marvell-pxa168.txt36
-rw-r--r--dts/Bindings/net/meson-dwmac.txt25
-rw-r--r--dts/Bindings/net/micrel.txt6
-rw-r--r--dts/Bindings/net/nfc/st21nfcb.txt2
-rw-r--r--dts/Bindings/net/nfc/trf7970a.txt8
-rw-r--r--dts/Bindings/net/qca-qca7000-spi.txt47
-rw-r--r--dts/Bindings/net/samsung-sxgbe.txt2
-rw-r--r--dts/Bindings/net/socfpga-dwmac.txt4
-rw-r--r--dts/Bindings/net/sti-dwmac.txt91
-rw-r--r--dts/Bindings/net/stmmac.txt2
-rw-r--r--dts/Bindings/panel/auo,b101xtn01.txt7
-rw-r--r--dts/Bindings/pci/designware-pcie.txt3
-rw-r--r--dts/Bindings/pci/fsl,imx6q-pcie.txt4
-rw-r--r--dts/Bindings/pci/fsl,pci.txt27
-rw-r--r--dts/Bindings/pci/host-generic-pci.txt2
-rw-r--r--dts/Bindings/pci/nvidia,tegra20-pcie.txt25
-rw-r--r--dts/Bindings/pci/pci-keystone.txt63
-rw-r--r--dts/Bindings/pci/xgene-pci.txt57
-rw-r--r--dts/Bindings/pci/xilinx-pcie.txt62
-rw-r--r--dts/Bindings/phy/phy-bindings.txt2
-rw-r--r--dts/Bindings/phy/phy-stih407-usb.txt30
-rw-r--r--dts/Bindings/phy/phy-stih41x-usb.txt24
-rw-r--r--dts/Bindings/phy/qcom-dwc3-usb-phy.txt39
-rw-r--r--dts/Bindings/phy/rcar-gen2-phy.txt51
-rw-r--r--dts/Bindings/phy/samsung-phy.txt7
-rw-r--r--dts/Bindings/pinctrl/atmel,at91-pinctrl.txt22
-rw-r--r--dts/Bindings/pinctrl/nvidia,tegra124-pinmux.txt14
-rw-r--r--dts/Bindings/pinctrl/pinctrl-bindings.txt50
-rw-r--r--dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/qcom,apq8084-pinctrl.txt179
-rw-r--r--dts/Bindings/pinctrl/rockchip,pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/ti,omap-pinctrl.txt13
-rw-r--r--dts/Bindings/power/power_domain.txt49
-rw-r--r--dts/Bindings/power/reset/ltc2952-poweroff.txt26
-rw-r--r--dts/Bindings/power/reset/st-reset.txt11
-rw-r--r--dts/Bindings/power/reset/syscon-reboot.txt23
-rw-r--r--dts/Bindings/power/rockchip-io-domain.txt83
-rw-r--r--dts/Bindings/power_supply/charger-manager.txt2
-rw-r--r--dts/Bindings/regmap/regmap.txt47
-rw-r--r--dts/Bindings/regulator/da9210.txt4
-rw-r--r--dts/Bindings/regulator/da9211.txt63
-rw-r--r--dts/Bindings/regulator/fan53555.txt23
-rw-r--r--dts/Bindings/regulator/isl9305.txt36
-rw-r--r--dts/Bindings/regulator/max1586-regulator.txt28
-rw-r--r--dts/Bindings/regulator/max77802.txt53
-rw-r--r--dts/Bindings/regulator/pwm-regulator.txt27
-rw-r--r--dts/Bindings/regulator/sky81452-regulator.txt16
-rw-r--r--dts/Bindings/rng/apm,rng.txt17
-rw-r--r--dts/Bindings/rtc/dallas,ds1339.txt18
-rw-r--r--dts/Bindings/rtc/s3c-rtc.txt3
-rw-r--r--dts/Bindings/rtc/sun6i-rtc.txt17
-rw-r--r--dts/Bindings/serial/cirrus,clps711x-uart.txt7
-rw-r--r--dts/Bindings/serial/mtk-uart.txt22
-rw-r--r--dts/Bindings/serial/of-serial.txt2
-rw-r--r--dts/Bindings/serial/via,vt8500-uart.txt17
-rw-r--r--dts/Bindings/serial/vt8500-uart.txt3
-rw-r--r--dts/Bindings/soc/ti/keystone-navigator-dma.txt111
-rw-r--r--dts/Bindings/soc/ti/keystone-navigator-qmss.txt232
-rw-r--r--dts/Bindings/sound/adi,ssm2602.txt19
-rw-r--r--dts/Bindings/sound/cs35l32.txt62
-rw-r--r--dts/Bindings/sound/es8328.txt38
-rw-r--r--dts/Bindings/sound/fsl,esai.txt3
-rw-r--r--dts/Bindings/sound/fsl,ssi.txt8
-rw-r--r--dts/Bindings/sound/fsl-asoc-card.txt82
-rw-r--r--dts/Bindings/sound/fsl-sai.txt30
-rw-r--r--dts/Bindings/sound/imx-audio-es8328.txt60
-rw-r--r--dts/Bindings/sound/nvidia,tegra-audio-max98090.txt1
-rw-r--r--dts/Bindings/sound/rt5677.txt59
-rw-r--r--dts/Bindings/sound/simple-card.txt4
-rw-r--r--dts/Bindings/sound/ssm4567.txt15
-rw-r--r--dts/Bindings/sound/st,sta350.txt2
-rw-r--r--dts/Bindings/spi/fsl-imx-cspi.txt5
-rw-r--r--dts/Bindings/spi/sh-msiof.txt23
-rw-r--r--dts/Bindings/spi/spi-davinci.txt30
-rw-r--r--dts/Bindings/spi/spi-fsl-dspi.txt7
-rw-r--r--dts/Bindings/spi/spi-orion.txt2
-rw-r--r--dts/Bindings/spi/spi-rspi.txt10
-rw-r--r--dts/Bindings/staging/imx-drm/ldb.txt15
-rw-r--r--dts/Bindings/timer/amlogic,meson6-timer.txt15
-rw-r--r--dts/Bindings/timer/renesas,cmt.txt44
-rw-r--r--dts/Bindings/timer/renesas,mtu2.txt7
-rw-r--r--dts/Bindings/timer/renesas,tmu.txt7
-rw-r--r--dts/Bindings/ufs/ufshcd-pltfrm.txt41
-rw-r--r--dts/Bindings/usb/ci-hdrc-imx.txt2
-rw-r--r--dts/Bindings/usb/dwc2.txt5
-rw-r--r--dts/Bindings/usb/dwc3-st.txt68
-rw-r--r--dts/Bindings/usb/ehci-st.txt39
-rw-r--r--dts/Bindings/usb/mxs-phy.txt1
-rw-r--r--dts/Bindings/usb/ohci-st.txt37
-rw-r--r--dts/Bindings/usb/qcom,dwc3.txt66
-rw-r--r--dts/Bindings/usb/renesas_usbhs.txt24
-rw-r--r--dts/Bindings/usb/udc-xilinx.txt18
-rw-r--r--dts/Bindings/usb/usb3503.txt4
-rw-r--r--dts/Bindings/usb/usbmisc-imx.txt1
-rw-r--r--dts/Bindings/vendor-prefixes.txt17
-rw-r--r--dts/Bindings/video/adi,adv7123.txt50
-rw-r--r--dts/Bindings/video/atmel,lcdc.txt7
-rw-r--r--dts/Bindings/video/exynos_dsim.txt1
-rw-r--r--dts/Bindings/video/fsl,imx-fb.txt2
-rw-r--r--dts/Bindings/video/renesas,du.txt84
-rw-r--r--dts/Bindings/video/samsung-fimd.txt1
-rw-r--r--dts/Bindings/video/thine,thc63lvdm83d50
-rw-r--r--dts/Bindings/video/vga-connector.txt36
-rw-r--r--dts/Bindings/xillybus/xillybus.txt (renamed from dts/Bindings/staging/xillybus.txt)0
-rw-r--r--dts/include/dt-bindings/clock/exynos3250.h27
-rw-r--r--dts/include/dt-bindings/clock/exynos4.h12
-rw-r--r--dts/include/dt-bindings/clock/hix5hd2-clock.h27
-rw-r--r--dts/include/dt-bindings/clock/imx6qdl-clock.h35
-rw-r--r--dts/include/dt-bindings/clock/imx6sl-clock.h30
-rw-r--r--dts/include/dt-bindings/clock/imx6sx-clock.h25
-rw-r--r--dts/include/dt-bindings/clock/maxim,max77686.h23
-rw-r--r--dts/include/dt-bindings/clock/maxim,max77802.h22
-rw-r--r--dts/include/dt-bindings/clock/pxa-clock.h77
-rw-r--r--dts/include/dt-bindings/clock/r8a7740-clock.h77
-rw-r--r--dts/include/dt-bindings/clock/r8a7790-clock.h1
-rw-r--r--dts/include/dt-bindings/clock/r8a7791-clock.h1
-rw-r--r--dts/include/dt-bindings/clock/r8a7794-clock.h80
-rw-r--r--dts/include/dt-bindings/clock/rk3188-cru-common.h1
-rw-r--r--dts/include/dt-bindings/clock/rk3288-cru.h82
-rw-r--r--dts/include/dt-bindings/clock/rockchip,rk808.h11
-rw-r--r--dts/include/dt-bindings/clock/tegra124-car.h6
-rw-r--r--dts/include/dt-bindings/clock/vf610-clock.h5
-rw-r--r--dts/include/dt-bindings/input/ti-drv260x.h36
-rw-r--r--dts/include/dt-bindings/pinctrl/at91.h5
-rw-r--r--dts/include/dt-bindings/pinctrl/rockchip.h2
-rw-r--r--dts/include/dt-bindings/sound/cs35l32.h26
-rw-r--r--dts/src/arm/am335x-bone-common.dtsi8
-rw-r--r--dts/src/arm/am335x-bone.dts5
-rw-r--r--dts/src/arm/am335x-boneblack.dts5
-rw-r--r--dts/src/arm/am33xx.dtsi18
-rw-r--r--dts/src/arm/am4372.dtsi13
-rw-r--r--dts/src/arm/armada-370-db.dts6
-rw-r--r--dts/src/arm/armada-370-mirabox.dts6
-rw-r--r--dts/src/arm/armada-370-netgear-rn102.dts10
-rw-r--r--dts/src/arm/armada-370-netgear-rn104.dts12
-rw-r--r--dts/src/arm/armada-370-rd.dts47
-rw-r--r--dts/src/arm/armada-370-xp.dtsi4
-rw-r--r--dts/src/arm/armada-370.dtsi23
-rw-r--r--dts/src/arm/armada-375.dtsi6
-rw-r--r--dts/src/arm/armada-xp-netgear-rn2120.dts6
-rw-r--r--dts/src/arm/at91-sama5d4ek.dts260
-rw-r--r--dts/src/arm/at91sam9263.dtsi12
-rw-r--r--dts/src/arm/at91sam9g20.dtsi4
-rw-r--r--dts/src/arm/at91sam9g45.dtsi47
-rw-r--r--dts/src/arm/at91sam9m10g45ek.dts4
-rw-r--r--dts/src/arm/at91sam9n12.dtsi2
-rw-r--r--dts/src/arm/at91sam9n12ek.dts2
-rw-r--r--dts/src/arm/at91sam9rl.dtsi4
-rw-r--r--dts/src/arm/at91sam9x5.dtsi4
-rw-r--r--dts/src/arm/bcm2835-rpi-b.dts8
-rw-r--r--dts/src/arm/bcm2835.dtsi1
-rw-r--r--dts/src/arm/bcm63138.dtsi134
-rw-r--r--dts/src/arm/bcm963138dvt.dts30
-rw-r--r--dts/src/arm/berlin2q-marvell-dmp.dts4
-rw-r--r--dts/src/arm/berlin2q.dtsi17
-rw-r--r--dts/src/arm/cros-adc-thermistors.dtsi44
-rw-r--r--dts/src/arm/da850-evm.dts72
-rw-r--r--dts/src/arm/da850.dtsi19
-rw-r--r--dts/src/arm/dra7-evm.dts29
-rw-r--r--dts/src/arm/dra7.dtsi25
-rw-r--r--dts/src/arm/dra72-evm.dts120
-rw-r--r--dts/src/arm/dra72x.dtsi5
-rw-r--r--dts/src/arm/dra74x.dtsi6
-rw-r--r--dts/src/arm/exynos3250.dtsi41
-rw-r--r--dts/src/arm/exynos4412-odroid-common.dtsi8
-rw-r--r--dts/src/arm/exynos4412-origen.dts8
-rw-r--r--dts/src/arm/exynos4412-trats2.dts8
-rw-r--r--dts/src/arm/exynos4x12-pinctrl.dtsi2
-rw-r--r--dts/src/arm/exynos5250-arndale.dts22
-rw-r--r--dts/src/arm/exynos5250-cros-common.dtsi164
-rw-r--r--dts/src/arm/exynos5250-smdk5250.dts18
-rw-r--r--dts/src/arm/exynos5250-snow.dts195
-rw-r--r--dts/src/arm/exynos5250.dtsi15
-rw-r--r--dts/src/arm/exynos5260-xyref5260.dts18
-rw-r--r--dts/src/arm/exynos5410-smdk5410.dts18
-rw-r--r--dts/src/arm/exynos5420-arndale-octa.dts23
-rw-r--r--dts/src/arm/exynos5420-peach-pit.dts490
-rw-r--r--dts/src/arm/exynos5420-smdk5420.dts16
-rw-r--r--dts/src/arm/exynos5420.dtsi4
-rw-r--r--dts/src/arm/exynos5800-peach-pi.dts480
-rw-r--r--dts/src/arm/hip04-d01.dts32
-rw-r--r--dts/src/arm/hip04.dtsi267
-rw-r--r--dts/src/arm/imx1-ads.dts152
-rw-r--r--dts/src/arm/imx1-apf9328.dts129
-rw-r--r--dts/src/arm/imx1-pinfunc.h302
-rw-r--r--dts/src/arm/imx1.dtsi266
-rw-r--r--dts/src/arm/imx23-evk.dts4
-rw-r--r--dts/src/arm/imx25-pinfunc.h33
-rw-r--r--dts/src/arm/imx25.dtsi4
-rw-r--r--dts/src/arm/imx27-apf27dev.dts17
-rw-r--r--dts/src/arm/imx28-apf28dev.dts4
-rw-r--r--dts/src/arm/imx28-apx4devkit.dts4
-rw-r--r--dts/src/arm/imx28-cfa10049.dts4
-rw-r--r--dts/src/arm/imx28-cfa10055.dts4
-rw-r--r--dts/src/arm/imx28-cfa10056.dts4
-rw-r--r--dts/src/arm/imx28-cfa10057.dts4
-rw-r--r--dts/src/arm/imx28-cfa10058.dts4
-rw-r--r--dts/src/arm/imx28-evk.dts4
-rw-r--r--dts/src/arm/imx28-m28cu3.dts4
-rw-r--r--dts/src/arm/imx28-m28evk.dts4
-rw-r--r--dts/src/arm/imx28-tx28.dts107
-rw-r--r--dts/src/arm/imx28.dtsi43
-rw-r--r--dts/src/arm/imx35.dtsi1
-rw-r--r--dts/src/arm/imx50.dtsi2
-rw-r--r--dts/src/arm/imx51.dtsi3
-rw-r--r--dts/src/arm/imx53-smd.dts2
-rw-r--r--dts/src/arm/imx53.dtsi20
-rw-r--r--dts/src/arm/imx6dl-gw552x.dts20
-rw-r--r--dts/src/arm/imx6dl-hummingboard.dts203
-rw-r--r--dts/src/arm/imx6q-gw5400-a.dts203
-rw-r--r--dts/src/arm/imx6q-gw552x.dts24
-rw-r--r--dts/src/arm/imx6q-hummingboard.dts21
-rw-r--r--dts/src/arm/imx6qdl-gw51xx.dtsi192
-rw-r--r--dts/src/arm/imx6qdl-gw52xx.dtsi314
-rw-r--r--dts/src/arm/imx6qdl-gw53xx.dtsi338
-rw-r--r--dts/src/arm/imx6qdl-gw54xx.dtsi278
-rw-r--r--dts/src/arm/imx6qdl-gw552x.dtsi267
-rw-r--r--dts/src/arm/imx6qdl-hummingboard.dtsi200
-rw-r--r--dts/src/arm/imx6qdl-nitrogen6x.dtsi38
-rw-r--r--dts/src/arm/imx6qdl-phytec-pfla02.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-sabresd.dtsi45
-rw-r--r--dts/src/arm/imx6qdl.dtsi24
-rw-r--r--dts/src/arm/imx6sl-evk.dts104
-rw-r--r--dts/src/arm/imx6sl.dtsi31
-rw-r--r--dts/src/arm/imx6sx-sdb.dts93
-rw-r--r--dts/src/arm/imx6sx.dtsi9
-rw-r--r--dts/src/arm/k2e-clocks.dtsi6
-rw-r--r--dts/src/arm/k2e.dtsi13
-rw-r--r--dts/src/arm/k2hk.dtsi56
-rw-r--r--dts/src/arm/k2l.dtsi46
-rw-r--r--dts/src/arm/keystone.dtsi10
-rw-r--r--dts/src/arm/kirkwood-mv88f6281gtw-ge.dts16
-rw-r--r--dts/src/arm/kirkwood-rd88f6281-a.dts43
-rw-r--r--dts/src/arm/kirkwood-rd88f6281-a0.dts26
-rw-r--r--dts/src/arm/kirkwood-rd88f6281-z0.dts (renamed from dts/src/arm/kirkwood-rd88f6281-a1.dts)18
-rw-r--r--dts/src/arm/kirkwood-rd88f6281.dtsi27
-rw-r--r--dts/src/arm/kirkwood.dtsi4
-rw-r--r--dts/src/arm/meson.dtsi110
-rw-r--r--dts/src/arm/meson6-atv1200.dts66
-rw-r--r--dts/src/arm/meson6.dtsi78
-rw-r--r--dts/src/arm/mt6589-aquaris5.dts5
-rw-r--r--dts/src/arm/mt6589.dtsi4
-rw-r--r--dts/src/arm/omap2.dtsi1
-rw-r--r--dts/src/arm/omap2420-n810.dts7
-rw-r--r--dts/src/arm/omap2420-n8x0-common.dtsi6
-rw-r--r--dts/src/arm/omap2420.dtsi8
-rw-r--r--dts/src/arm/omap2430.dtsi4
-rw-r--r--dts/src/arm/omap3-beagle-xm.dts4
-rw-r--r--dts/src/arm/omap3-gta04.dtsi (renamed from dts/src/arm/omap3-gta04.dts)150
-rw-r--r--dts/src/arm/omap3-gta04a3.dts48
-rw-r--r--dts/src/arm/omap3-gta04a4.dts13
-rw-r--r--dts/src/arm/omap3-gta04a5.dts17
-rw-r--r--dts/src/arm/omap3-ha-common.dtsi88
-rw-r--r--dts/src/arm/omap3-ha-lcd.dts165
-rw-r--r--dts/src/arm/omap3-ha.dts28
-rw-r--r--dts/src/arm/omap3-ldp.dts5
-rw-r--r--dts/src/arm/omap3-n900.dts57
-rw-r--r--dts/src/arm/omap3-overo-common-peripherals.dtsi5
-rw-r--r--dts/src/arm/omap3-tao3530.dtsi337
-rw-r--r--dts/src/arm/omap3-thunder.dts129
-rw-r--r--dts/src/arm/omap3.dtsi8
-rw-r--r--dts/src/arm/omap4-panda-common.dtsi3
-rw-r--r--dts/src/arm/omap4-panda-es.dts5
-rw-r--r--dts/src/arm/omap4-panda.dts5
-rw-r--r--dts/src/arm/omap4.dtsi15
-rw-r--r--dts/src/arm/omap5-cm-t54.dts277
-rw-r--r--dts/src/arm/omap5-sbc-t54.dts8
-rw-r--r--dts/src/arm/omap5.dtsi46
-rw-r--r--dts/src/arm/pxa27x.dtsi20
-rw-r--r--dts/src/arm/pxa2xx.dtsi4
-rw-r--r--dts/src/arm/qcom-apq8064-cm-qs600.dts59
-rw-r--r--dts/src/arm/qcom-apq8064-ifc6410.dts43
-rw-r--r--dts/src/arm/qcom-apq8064.dtsi183
-rw-r--r--dts/src/arm/qcom-apq8074-dragonboard.dts21
-rw-r--r--dts/src/arm/qcom-apq8084-ifc6540.dts23
-rw-r--r--dts/src/arm/qcom-apq8084-mtp.dts6
-rw-r--r--dts/src/arm/qcom-apq8084.dtsi51
-rw-r--r--dts/src/arm/qcom-ipq8064-ap148.dts93
-rw-r--r--dts/src/arm/qcom-ipq8064-v1.0.dtsi1
-rw-r--r--dts/src/arm/qcom-ipq8064.dtsi283
-rw-r--r--dts/src/arm/qcom-msm8660-surf.dts42
-rw-r--r--dts/src/arm/qcom-msm8660.dtsi93
-rw-r--r--dts/src/arm/qcom-msm8960-cdp.dts27
-rw-r--r--dts/src/arm/qcom-msm8960.dtsi87
-rw-r--r--dts/src/arm/qcom-msm8974-sony-xperia-honami.dts17
-rw-r--r--dts/src/arm/qcom-msm8974.dtsi15
-rw-r--r--dts/src/arm/r7s72100-genmai.dts4
-rw-r--r--dts/src/arm/r7s72100.dtsi10
-rw-r--r--dts/src/arm/r8a73a4.dtsi6
-rw-r--r--dts/src/arm/r8a7740-armadillo800eva-reference.dts283
-rw-r--r--dts/src/arm/r8a7740-armadillo800eva.dts276
-rw-r--r--dts/src/arm/r8a7740.dtsi220
-rw-r--r--dts/src/arm/r8a7778.dtsi6
-rw-r--r--dts/src/arm/r8a7779-marzen.dts4
-rw-r--r--dts/src/arm/r8a7779.dtsi58
-rw-r--r--dts/src/arm/r8a7790-lager.dts44
-rw-r--r--dts/src/arm/r8a7790.dtsi159
-rw-r--r--dts/src/arm/r8a7791-henninger.dts35
-rw-r--r--dts/src/arm/r8a7791-koelsch.dts41
-rw-r--r--dts/src/arm/r8a7791.dtsi140
-rw-r--r--dts/src/arm/r8a7794-alt.dts47
-rw-r--r--dts/src/arm/r8a7794.dtsi531
-rw-r--r--dts/src/arm/rk3066a-bqcurie2.dts15
-rw-r--r--dts/src/arm/rk3066a.dtsi67
-rw-r--r--dts/src/arm/rk3188-radxarock.dts90
-rw-r--r--dts/src/arm/rk3188.dtsi91
-rw-r--r--dts/src/arm/rk3288-evb-act8846.dts10
-rw-r--r--dts/src/arm/rk3288-evb-rk808.dts132
-rw-r--r--dts/src/arm/rk3288-evb.dtsi87
-rw-r--r--dts/src/arm/rk3288.dtsi380
-rw-r--r--dts/src/arm/rk3xxx.dtsi126
-rw-r--r--dts/src/arm/sama5d3.dtsi37
-rw-r--r--dts/src/arm/sama5d3_can.dtsi2
-rw-r--r--dts/src/arm/sama5d3xcm.dtsi30
-rw-r--r--dts/src/arm/sama5d3xmb.dtsi4
-rw-r--r--dts/src/arm/sama5d4.dtsi1240
-rw-r--r--dts/src/arm/sh7372.dtsi1
-rw-r--r--dts/src/arm/sh73a0-kzm9g-reference.dts8
-rw-r--r--dts/src/arm/sh73a0.dtsi36
-rw-r--r--dts/src/arm/socfpga.dtsi11
-rw-r--r--dts/src/arm/socfpga_arria5.dtsi11
-rw-r--r--dts/src/arm/socfpga_arria5_socdk.dts7
-rw-r--r--dts/src/arm/socfpga_cyclone5.dtsi13
-rw-r--r--dts/src/arm/socfpga_cyclone5_socdk.dts4
-rw-r--r--dts/src/arm/socfpga_vt.dts9
-rw-r--r--dts/src/arm/spear1310.dtsi18
-rw-r--r--dts/src/arm/spear1340.dtsi6
-rw-r--r--dts/src/arm/sun4i-a10.dtsi19
-rw-r--r--dts/src/arm/sun5i-a10s.dtsi19
-rw-r--r--dts/src/arm/sun5i-a13-hsg-h702.dts130
-rw-r--r--dts/src/arm/sun5i-a13.dtsi19
-rw-r--r--dts/src/arm/sun6i-a31.dtsi56
-rw-r--r--dts/src/arm/sun7i-a20-hummingbird.dts236
-rw-r--r--dts/src/arm/sun7i-a20-olinuxino-lime.dts137
-rw-r--r--dts/src/arm/sun7i-a20.dtsi104
-rw-r--r--dts/src/arm/sun8i-a23-ippo-q8h-v5.dts41
-rw-r--r--dts/src/arm/sun8i-a23.dtsi237
-rw-r--r--dts/src/arm/sunxi-common-regulators.dtsi7
-rw-r--r--dts/src/arm/tegra114.dtsi5
-rw-r--r--dts/src/arm/tegra124-jetson-tk1.dts98
-rw-r--r--dts/src/arm/tegra124-nyan-big.dts1136
-rw-r--r--dts/src/arm/tegra124-venice2.dts18
-rw-r--r--dts/src/arm/tegra124.dtsi100
-rw-r--r--dts/src/arm/tegra20.dtsi5
-rw-r--r--dts/src/arm/tegra30.dtsi5
-rw-r--r--dts/src/arm/vexpress-v2m-rs1.dtsi36
-rw-r--r--dts/src/arm/vexpress-v2m.dtsi36
-rw-r--r--dts/src/arm/vexpress-v2p-ca15_a7.dts23
-rw-r--r--dts/src/arm/vexpress-v2p-ca9.dts31
-rw-r--r--dts/src/arm/vf610-colibri-eval-v3.dts46
-rw-r--r--dts/src/arm/vf610-colibri.dtsi (renamed from dts/src/arm/vf610-colibri.dts)22
-rw-r--r--dts/src/arm/vf610-twr.dts26
-rw-r--r--dts/src/arm/vf610.dtsi60
-rw-r--r--dts/src/arm/zynq-7000.dtsi19
-rw-r--r--dts/src/arm/zynq-parallella.dts27
-rw-r--r--dts/src/arm/zynq-zc702.dts18
-rw-r--r--dts/src/arm/zynq-zc706.dts12
-rw-r--r--dts/src/arm/zynq-zed.dts14
-rw-r--r--dts/src/arm64/apm-mustang.dts16
-rw-r--r--dts/src/arm64/apm-storm.dtsi237
-rw-r--r--dts/src/arm64/thunder-88xx.dts67
-rw-r--r--dts/src/arm64/thunder-88xx.dtsi401
-rw-r--r--dts/src/powerpc/fsl/t2081si-post.dtsi4
-rw-r--r--dts/src/powerpc/fsl/t4240si-post.dtsi4
-rw-r--r--dts/src/powerpc/t1040rdb.dts48
-rw-r--r--dts/src/powerpc/t1042rdb.dts48
-rw-r--r--dts/src/powerpc/t1042rdb_pi.dts57
-rw-r--r--dts/src/powerpc/t104xrdb.dtsi156
-rw-r--r--dts/testcase-data/testcases.dts35
458 files changed, 21734 insertions, 2333 deletions
diff --git a/dts/Bindings/arm/altera/socfpga-sdram-edac.txt b/dts/Bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 0000000..d0ce01d
--- /dev/null
+++ b/dts/Bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+The EDAC accesses a range of registers in the SDRAM controller.
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- altr,sdr-syscon : phandle of the sdr module
+- interrupts : Should contain the SDRAM ECC IRQ in the
+ appropriate format for the IRQ controller.
+
+Example:
+ sdramedac {
+ compatible = "altr,sdram-edac";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <0 39 4>;
+ };
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
new file mode 100644
index 0000000..7eece72
--- /dev/null
+++ b/dts/Bindings/arm/amlogic.txt
@@ -0,0 +1,8 @@
+Amlogic MesonX device tree bindings
+-------------------------------------------
+
+Boards with the Amlogic Meson6 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "amlogic,meson6";
diff --git a/dts/Bindings/arm/atmel-at91.txt b/dts/Bindings/arm/atmel-at91.txt
index 16f60b4..562cda9 100644
--- a/dts/Bindings/arm/atmel-at91.txt
+++ b/dts/Bindings/arm/atmel-at91.txt
@@ -1,6 +1,43 @@
Atmel AT91 device tree bindings.
================================
+Boards with a SoC of the Atmel AT91 or SMART family shall have the following
+properties:
+
+Required root node properties:
+compatible: must be one of:
+ * "atmel,at91rm9200"
+
+ * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with
+ the specific SoC family or compatible:
+ o "atmel,at91sam9260"
+ o "atmel,at91sam9261"
+ o "atmel,at91sam9263"
+ o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific
+ SoC compatible:
+ - "atmel,at91sam9g15"
+ - "atmel,at91sam9g25"
+ - "atmel,at91sam9g35"
+ - "atmel,at91sam9x25"
+ - "atmel,at91sam9x35"
+ o "atmel,at91sam9g20"
+ o "atmel,at91sam9g45"
+ o "atmel,at91sam9n12"
+ o "atmel,at91sam9rl"
+ * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
+ SoC family:
+ o "atmel,sama5d3" shall be extended with the specific SoC compatible:
+ - "atmel,sama5d31"
+ - "atmel,sama5d33"
+ - "atmel,sama5d34"
+ - "atmel,sama5d35"
+ - "atmel,sama5d36"
+ o "atmel,sama5d4" shall be extended with the specific SoC compatible:
+ - "atmel,sama5d41"
+ - "atmel,sama5d42"
+ - "atmel,sama5d43"
+ - "atmel,sama5d44"
+
PIT Timer required properties:
- compatible: Should be "atmel,at91sam9260-pit"
- reg: Should contain registers location and length
@@ -61,8 +98,8 @@ RAMC SDRAM/DDR Controller required properties:
- compatible: Should be "atmel,at91rm9200-sdramc",
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
+ "atmel,sama5d3-ddramc",
- reg: Should contain registers location and length
- For at91sam9263 and at91sam9g45 you must specify 2 entries.
Examples:
@@ -71,12 +108,6 @@ Examples:
reg = <0xffffe800 0x200>;
};
- ramc0: ramc@ffffe400 {
- compatible = "atmel,at91sam9g45-ddramc";
- reg = <0xffffe400 0x200
- 0xffffe600 0x200>;
- };
-
SHDWC Shutdown Controller
required properties:
diff --git a/dts/Bindings/arm/bcm/bcm63138.txt b/dts/Bindings/arm/bcm/bcm63138.txt
new file mode 100644
index 0000000..bd49987
--- /dev/null
+++ b/dts/Bindings/arm/bcm/bcm63138.txt
@@ -0,0 +1,9 @@
+Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
+-----------------------------------------------------------
+
+Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
+following properties:
+
+Required root node property:
+
+compatible: should be "brcm,bcm63138"
diff --git a/dts/Bindings/arm/cavium-thunder.txt b/dts/Bindings/arm/cavium-thunder.txt
new file mode 100644
index 0000000..6f63a58
--- /dev/null
+++ b/dts/Bindings/arm/cavium-thunder.txt
@@ -0,0 +1,10 @@
+Cavium Thunder platform device tree bindings
+--------------------------------------------
+
+Boards with Cavium's Thunder SoC shall have following properties.
+
+Root Node
+---------
+Required root node properties:
+
+ - compatible = "cavium,thunder-88xx";
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index 298e2f6..fc44634 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -166,6 +166,7 @@ nodes to be present and contain the properties described below.
"arm,cortex-r5"
"arm,cortex-r7"
"brcm,brahma-b15"
+ "cavium,thunder"
"faraday,fa526"
"intel,sa110"
"intel,sa1100"
@@ -219,6 +220,12 @@ nodes to be present and contain the properties described below.
Value type: <phandle>
Definition: Specifies the ACC[2] node associated with this CPU.
+ - cpu-idle-states
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition:
+ # List of phandles to idle state nodes supported
+ by this cpu [3].
Example 1 (dual-cluster big.LITTLE system 32-bit):
@@ -415,3 +422,5 @@ cpus {
--
[1] arm/msm/qcom,saw2.txt
[2] arm/msm/qcom,kpss-acc.txt
+[3] ARM Linux kernel documentation - idle states bindings
+ Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/dts/Bindings/arm/exynos/power_domain.txt b/dts/Bindings/arm/exynos/power_domain.txt
index 8b4f7b7..abde1ea 100644
--- a/dts/Bindings/arm/exynos/power_domain.txt
+++ b/dts/Bindings/arm/exynos/power_domain.txt
@@ -8,6 +8,8 @@ Required Properties:
* samsung,exynos4210-pd - for exynos4210 type power domain.
- reg: physical base address of the controller and length of memory mapped
region.
+- #power-domain-cells: number of cells in power domain specifier;
+ must be 0.
Optional Properties:
- clocks: List of clock handles. The parent clocks of the input clocks to the
@@ -29,6 +31,7 @@ Example:
lcd0: power-domain-lcd0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x10>;
+ #power-domain-cells = <0>;
};
mfc_pd: power-domain@10044060 {
@@ -37,12 +40,8 @@ Example:
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
<&clock CLK_MOUT_USER_ACLK333>;
clock-names = "oscclk", "pclk0", "clk0";
+ #power-domain-cells = <0>;
};
-Example of the node using power domain:
-
- node {
- /* ... */
- samsung,power-domain = <&lcd0>;
- /* ... */
- };
+See Documentation/devicetree/bindings/power/power_domain.txt for description
+of consumer-side bindings.
diff --git a/dts/Bindings/arm/geniatech.txt b/dts/Bindings/arm/geniatech.txt
new file mode 100644
index 0000000..74ccba4
--- /dev/null
+++ b/dts/Bindings/arm/geniatech.txt
@@ -0,0 +1,5 @@
+Geniatech platforms device tree bindings
+-------------------------------------------
+
+Geniatech ATV1200
+ - compatible = "geniatech,atv1200"
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt
index 934f000..f717c7b 100644
--- a/dts/Bindings/arm/hisilicon/hisilicon.txt
+++ b/dts/Bindings/arm/hisilicon/hisilicon.txt
@@ -5,6 +5,11 @@ Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";
+HiP04 D01 Board
+Required root node properties:
+ - compatible = "hisilicon,hip04-d01";
+
+
Hisilicon system controller
Required properties:
@@ -55,3 +60,21 @@ Example:
compatible = "hisilicon,pctrl";
reg = <0xfca09000 0x1000>;
};
+
+-----------------------------------------------------------------------
+Fabric:
+
+Required Properties:
+- compatible: "hisilicon,hip04-fabric";
+- reg: Address and size of Fabric
+
+-----------------------------------------------------------------------
+Bootwrapper boot method (software protocol on SMP):
+
+Required Properties:
+- compatible: "hisilicon,hip04-bootwrapper";
+- boot-method: Address and size of boot method.
+ [0]: bootwrapper physical address
+ [1]: bootwrapper size
+ [2]: relocation physical address
+ [3]: relocation size
diff --git a/dts/Bindings/arm/idle-states.txt b/dts/Bindings/arm/idle-states.txt
new file mode 100644
index 0000000..37375c7
--- /dev/null
+++ b/dts/Bindings/arm/idle-states.txt
@@ -0,0 +1,679 @@
+==========================================
+ARM idle states binding description
+==========================================
+
+==========================================
+1 - Introduction
+==========================================
+
+ARM systems contain HW capable of managing power consumption dynamically,
+where cores can be put in different low-power states (ranging from simple
+wfi to power gating) according to OS PM policies. The CPU states representing
+the range of dynamic idle states that a processor can enter at run-time, can be
+specified through device tree bindings representing the parameters required
+to enter/exit specific idle states on a given processor.
+
+According to the Server Base System Architecture document (SBSA, [3]), the
+power states an ARM CPU can be put into are identified by the following list:
+
+- Running
+- Idle_standby
+- Idle_retention
+- Sleep
+- Off
+
+The power states described in the SBSA document define the basic CPU states on
+top of which ARM platforms implement power management schemes that allow an OS
+PM implementation to put the processor in different idle states (which include
+states listed above; "off" state is not an idle state since it does not have
+wake-up capabilities, hence it is not considered in this document).
+
+Idle state parameters (eg entry latency) are platform specific and need to be
+characterized with bindings that provide the required information to OS PM
+code so that it can build the required tables and use them at runtime.
+
+The device tree binding definition for ARM idle states is the subject of this
+document.
+
+===========================================
+2 - idle-states definitions
+===========================================
+
+Idle states are characterized for a specific system through a set of
+timing and energy related properties, that underline the HW behaviour
+triggered upon idle states entry and exit.
+
+The following diagram depicts the CPU execution phases and related timing
+properties required to enter and exit an idle state:
+
+..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
+ | | | | |
+
+ |<------ entry ------->|
+ | latency |
+ |<- exit ->|
+ | latency |
+ |<-------- min-residency -------->|
+ |<------- wakeup-latency ------->|
+
+ Diagram 1: CPU idle state execution phases
+
+EXEC: Normal CPU execution.
+
+PREP: Preparation phase before committing the hardware to idle mode
+ like cache flushing. This is abortable on pending wake-up
+ event conditions. The abort latency is assumed to be negligible
+ (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
+ goes back to EXEC. This phase is optional. If not abortable,
+ this should be included in the ENTRY phase instead.
+
+ENTRY: The hardware is committed to idle mode. This period must run
+ to completion up to IDLE before anything else can happen.
+
+IDLE: This is the actual energy-saving idle period. This may last
+ between 0 and infinite time, until a wake-up event occurs.
+
+EXIT: Period during which the CPU is brought back to operational
+ mode (EXEC).
+
+entry-latency: Worst case latency required to enter the idle state. The
+exit-latency may be guaranteed only after entry-latency has passed.
+
+min-residency: Minimum period, including preparation and entry, for a given
+idle state to be worthwhile energywise.
+
+wakeup-latency: Maximum delay between the signaling of a wake-up event and the
+CPU being able to execute normal code again. If not specified, this is assumed
+to be entry-latency + exit-latency.
+
+These timing parameters can be used by an OS in different circumstances.
+
+An idle CPU requires the expected min-residency time to select the most
+appropriate idle state based on the expected expiry time of the next IRQ
+(ie wake-up) that causes the CPU to return to the EXEC phase.
+
+An operating system scheduler may need to compute the shortest wake-up delay
+for CPUs in the system by detecting how long will it take to get a CPU out
+of an idle state, eg:
+
+wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
+
+In other words, the scheduler can make its scheduling decision by selecting
+(eg waking-up) the CPU with the shortest wake-up latency.
+The wake-up latency must take into account the entry latency if that period
+has not expired. The abortable nature of the PREP period can be ignored
+if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
+the worst case since it depends on the CPU operating conditions, ie caches
+state).
+
+An OS has to reliably probe the wakeup-latency since some devices can enforce
+latency constraints guarantees to work properly, so the OS has to detect the
+worst case wake-up latency it can incur if a CPU is allowed to enter an
+idle state, and possibly to prevent that to guarantee reliable device
+functioning.
+
+The min-residency time parameter deserves further explanation since it is
+expressed in time units but must factor in energy consumption coefficients.
+
+The energy consumption of a cpu when it enters a power state can be roughly
+characterised by the following graph:
+
+ |
+ |
+ |
+ e |
+ n | /---
+ e | /------
+ r | /------
+ g | /-----
+ y | /------
+ | ----
+ | /|
+ | / |
+ | / |
+ | / |
+ | / |
+ | / |
+ |/ |
+ -----|-------+----------------------------------
+ 0| 1 time(ms)
+
+ Graph 1: Energy vs time example
+
+The graph is split in two parts delimited by time 1ms on the X-axis.
+The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
+and denotes the energy costs incurred whilst entering and leaving the idle
+state.
+The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
+shallower slope and essentially represents the energy consumption of the idle
+state.
+
+min-residency is defined for a given idle state as the minimum expected
+residency time for a state (inclusive of preparation and entry) after
+which choosing that state become the most energy efficient option. A good
+way to visualise this, is by taking the same graph above and comparing some
+states energy consumptions plots.
+
+For sake of simplicity, let's consider a system with two idle states IDLE1,
+and IDLE2:
+
+ |
+ |
+ |
+ | /-- IDLE1
+ e | /---
+ n | /----
+ e | /---
+ r | /-----/--------- IDLE2
+ g | /-------/---------
+ y | ------------ /---|
+ | / /---- |
+ | / /--- |
+ | / /---- |
+ | / /--- |
+ | --- |
+ | / |
+ | / |
+ |/ | time
+ ---/----------------------------+------------------------
+ |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
+ |
+ IDLE2-min-residency
+
+ Graph 2: idle states min-residency example
+
+In graph 2 above, that takes into account idle states entry/exit energy
+costs, it is clear that if the idle state residency time (ie time till next
+wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
+choice energywise.
+
+This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
+than IDLE2.
+
+However, the lower power consumption (ie shallower energy curve slope) of idle
+state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
+efficient.
+
+The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
+shallower states in a system with multiple idle states) is defined
+IDLE2-min-residency and corresponds to the time when energy consumption of
+IDLE1 and IDLE2 states breaks even.
+
+The definitions provided in this section underpin the idle states
+properties specification that is the subject of the following sections.
+
+===========================================
+3 - idle-states node
+===========================================
+
+ARM processor idle states are defined within the idle-states node, which is
+a direct child of the cpus node [1] and provides a container where the
+processor idle states, defined as device tree nodes, are listed.
+
+- idle-states node
+
+ Usage: Optional - On ARM systems, it is a container of processor idle
+ states nodes. If the system does not provide CPU
+ power management capabilities or the processor just
+ supports idle_standby an idle-states node is not
+ required.
+
+ Description: idle-states node is a container node, where its
+ subnodes describe the CPU idle states.
+
+ Node name must be "idle-states".
+
+ The idle-states node's parent node must be the cpus node.
+
+ The idle-states node's child nodes can be:
+
+ - one or more state nodes
+
+ Any other configuration is considered invalid.
+
+ An idle-states node defines the following properties:
+
+ - entry-method
+ Value type: <stringlist>
+ Usage and definition depend on ARM architecture version.
+ # On ARM v8 64-bit this property is required and must
+ be one of:
+ - "psci" (see bindings in [2])
+ # On ARM 32-bit systems this property is optional
+
+The nodes describing the idle states (state) can only be defined within the
+idle-states node, any other configuration is considered invalid and therefore
+must be ignored.
+
+===========================================
+4 - state node
+===========================================
+
+A state node represents an idle state description and must be defined as
+follows:
+
+- state node
+
+ Description: must be child of the idle-states node
+
+ The state node name shall follow standard device tree naming
+ rules ([5], 2.2.1 "Node names"), in particular state nodes which
+ are siblings within a single common parent must be given a unique name.
+
+ The idle state entered by executing the wfi instruction (idle_standby
+ SBSA,[3][4]) is considered standard on all ARM platforms and therefore
+ must not be listed.
+
+ With the definitions provided above, the following list represents
+ the valid properties for a state node:
+
+ - compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must be "arm,idle-state".
+
+ - local-timer-stop
+ Usage: See definition
+ Value type: <none>
+ Definition: if present the CPU local timer control logic is
+ lost on state entry, otherwise it is retained.
+
+ - entry-latency-us
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency in
+ microseconds required to enter the idle state.
+ The exit-latency-us duration may be guaranteed
+ only after entry-latency-us has passed.
+
+ - exit-latency-us
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency
+ in microseconds required to exit the idle state.
+
+ - min-residency-us
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing minimum residency duration
+ in microseconds, inclusive of preparation and
+ entry, for this idle state to be considered
+ worthwhile energy wise (refer to section 2 of
+ this document for a complete description).
+
+ - wakeup-latency-us:
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing maximum delay between the
+ signaling of a wake-up event and the CPU being
+ able to execute normal code again. If omitted,
+ this is assumed to be equal to:
+
+ entry-latency-us + exit-latency-us
+
+ It is important to supply this value on systems
+ where the duration of PREP phase (see diagram 1,
+ section 2) is non-neglibigle.
+ In such systems entry-latency-us + exit-latency-us
+ will exceed wakeup-latency-us by this duration.
+
+ In addition to the properties listed above, a state node may require
+ additional properties specifics to the entry-method defined in the
+ idle-states node, please refer to the entry-method bindings
+ documentation for properties definitions.
+
+===========================================
+4 - Examples
+===========================================
+
+Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU4: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU5: cpu@10001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU6: cpu@10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU7: cpu@10101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU8: cpu@100000000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU9: cpu@100000001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU10: cpu@100000100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU11: cpu@100000101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU12: cpu@100010000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU13: cpu@100010001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU14: cpu@100010100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU15: cpu@100010101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_RETENTION_0_0: cpu-retention-0-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <20>;
+ exit-latency-us = <40>;
+ min-residency-us = <80>;
+ };
+
+ CLUSTER_RETENTION_0: cluster-retention-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <250>;
+ wakeup-latency-us = <130>;
+ };
+
+ CPU_SLEEP_0_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <250>;
+ exit-latency-us = <500>;
+ min-residency-us = <950>;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1100>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+
+ CPU_RETENTION_1_0: cpu-retention-1-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <20>;
+ exit-latency-us = <40>;
+ min-residency-us = <90>;
+ };
+
+ CLUSTER_RETENTION_1: cluster-retention-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <270>;
+ wakeup-latency-us = <100>;
+ };
+
+ CPU_SLEEP_1_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <70>;
+ exit-latency-us = <100>;
+ min-residency-us = <300>;
+ wakeup-latency-us = <150>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <500>;
+ exit-latency-us = <1200>;
+ min-residency-us = <3500>;
+ wakeup-latency-us = <1300>;
+ };
+ };
+
+};
+
+Example 2 (ARM 32-bit, 8-cpu system, two clusters):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x2>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x3>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ idle-states {
+ CPU_SLEEP_0_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <200>;
+ exit-latency-us = <100>;
+ min-residency-us = <400>;
+ wakeup-latency-us = <250>;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <500>;
+ exit-latency-us = <1500>;
+ min-residency-us = <2500>;
+ wakeup-latency-us = <1700>;
+ };
+
+ CPU_SLEEP_1_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <500>;
+ min-residency-us = <900>;
+ wakeup-latency-us = <600>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <800>;
+ exit-latency-us = <2000>;
+ min-residency-us = <6500>;
+ wakeup-latency-us = <2300>;
+ };
+ };
+
+};
+
+===========================================
+5 - References
+===========================================
+
+[1] ARM Linux Kernel documentation - CPUs bindings
+ Documentation/devicetree/bindings/arm/cpus.txt
+
+[2] ARM Linux Kernel documentation - PSCI bindings
+ Documentation/devicetree/bindings/arm/psci.txt
+
+[3] ARM Server Base System Architecture (SBSA)
+ http://infocenter.arm.com/help/index.jsp
+
+[4] ARM Architecture Reference Manuals
+ http://infocenter.arm.com/help/index.jsp
+
+[5] ePAPR standard
+ https://www.power.org/documentation/epapr-version-1-1/
diff --git a/dts/Bindings/arm/l2cc.txt b/dts/Bindings/arm/l2cc.txt
index af527ee..292ef7c 100644
--- a/dts/Bindings/arm/l2cc.txt
+++ b/dts/Bindings/arm/l2cc.txt
@@ -2,6 +2,10 @@
ARM cores often have a separate level 2 cache controller. There are various
implementations of the L2 cache controller with compatible programming models.
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the ePAPR v1.1 specification which can be found at:
+https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
+
The ARM L2 cache representation in the device tree should be done as follows:
Required properties:
@@ -44,6 +48,12 @@ Optional properties:
I/O coherent mode. Valid only when the arm,pl310-cache compatible
string is used.
- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+ if this is not specified, the line size is assumed to be equal to the
+ cache block size
- cache-id-part: cache id part number to be used if it is not present
on hardware
- wt-override: If present then L2 is forced to Write through mode
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index d6ac71f..fa25226 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -6,3 +6,9 @@ Required root node property:
compatible: must contain "mediatek,mt6589"
+
+Supported boards:
+
+- bq Aquaris5 smart phone:
+ Required root node properties:
+ - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
diff --git a/dts/Bindings/arm/omap/mpu.txt b/dts/Bindings/arm/omap/mpu.txt
index 83f405b..763695d 100644
--- a/dts/Bindings/arm/omap/mpu.txt
+++ b/dts/Bindings/arm/omap/mpu.txt
@@ -10,6 +10,9 @@ Required properties:
Should be "ti,omap5-mpu" for OMAP5
- ti,hwmods: "mpu"
+Optional properties:
+- sram: Phandle to the ocmcram node
+
Examples:
- For an OMAP5 SMP system:
diff --git a/dts/Bindings/arm/omap/omap.txt b/dts/Bindings/arm/omap/omap.txt
index 0edc903..ddd9bcd 100644
--- a/dts/Bindings/arm/omap/omap.txt
+++ b/dts/Bindings/arm/omap/omap.txt
@@ -85,6 +85,18 @@ SoCs:
- DRA722
compatible = "ti,dra722", "ti,dra72", "ti,dra7"
+- AM5728
+ compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
+
+- AM5726
+ compatible = "ti,am5726", "ti,dra742", "ti,dra74", "ti,dra7"
+
+- AM5718
+ compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7"
+
+- AM5716
+ compatible = "ti,am5716", "ti,dra722", "ti,dra72", "ti,dra7"
+
- AM4372
compatible = "ti,am4372", "ti,am43"
diff --git a/dts/Bindings/arm/psci.txt b/dts/Bindings/arm/psci.txt
index b4a58f3..5aa40ed 100644
--- a/dts/Bindings/arm/psci.txt
+++ b/dts/Bindings/arm/psci.txt
@@ -50,6 +50,16 @@ Main node optional properties:
- migrate : Function ID for MIGRATE operation
+Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
+state nodes, as per bindings in [1]) must specify the following properties:
+
+- arm,psci-suspend-param
+ Usage: Required for state nodes[1] if the corresponding
+ idle-states node entry-method property is set
+ to "psci".
+ Value type: <u32>
+ Definition: power_state parameter to pass to the PSCI
+ suspend call.
Example:
@@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
migrate = <0x95c10003>;
};
-
Case 2: PSCI v0.2 only
psci {
@@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
...
};
+
+[1] Kernel documentation - ARM idle states bindings
+ Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/dts/Bindings/arm/samsung/exynos-adc.txt b/dts/Bindings/arm/samsung/exynos-adc.txt
index adc61b0..709efaa 100644
--- a/dts/Bindings/arm/samsung/exynos-adc.txt
+++ b/dts/Bindings/arm/samsung/exynos-adc.txt
@@ -11,13 +11,25 @@ New driver handles the following
Required properties:
- compatible: Must be "samsung,exynos-adc-v1"
- for exynos4412/5250 controllers.
+ for exynos4412/5250 and s5pv210 controllers.
Must be "samsung,exynos-adc-v2" for
future controllers.
Must be "samsung,exynos3250-adc" for
controllers compatible with ADC of Exynos3250.
-- reg: Contains ADC register address range (base address and
- length) and the address of the phy enable register.
+ Must be "samsung,s3c2410-adc" for
+ the ADC in s3c2410 and compatibles
+ Must be "samsung,s3c2416-adc" for
+ the ADC in s3c2416 and compatibles
+ Must be "samsung,s3c2440-adc" for
+ the ADC in s3c2440 and compatibles
+ Must be "samsung,s3c2443-adc" for
+ the ADC in s3c2443 and compatibles
+ Must be "samsung,s3c6410-adc" for
+ the ADC in s3c6410 and compatibles
+- reg: List of ADC register address range
+ - The base address and range of ADC register
+ - The base address and range of ADC_PHY register (every
+ SoC except for s3c24xx/s3c64xx ADC)
- interrupts: Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
new file mode 100644
index 0000000..51147cb
--- /dev/null
+++ b/dts/Bindings/arm/shmobile.txt
@@ -0,0 +1,71 @@
+Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
+--------------------------------------------------------------------
+
+SoCs:
+
+ - Emma Mobile EV2
+ compatible = "renesas,emev2"
+ - RZ/A1H (R7S72100)
+ compatible = "renesas,r7s72100"
+ - SH-Mobile AP4 (R8A73720/SH7372)
+ compatible = "renesas,sh7372"
+ - SH-Mobile AG5 (R8A73A00/SH73A0)
+ compatible = "renesas,sh73a0"
+ - R-Mobile APE6 (R8A73A40)
+ compatible = "renesas,r8a73a4"
+ - R-Mobile A1 (R8A77400)
+ compatible = "renesas,r8a7740"
+ - R-Car M1A (R8A77781)
+ compatible = "renesas,r8a7778"
+ - R-Car H1 (R8A77790)
+ compatible = "renesas,r8a7779"
+ - R-Car H2 (R8A77900)
+ compatible = "renesas,r8a7790"
+ - R-Car M2-W (R8A77910)
+ compatible = "renesas,r8a7791"
+ - R-Car V2H (R8A77920)
+ compatible = "renesas,r8a7792"
+ - R-Car M2-N (R8A77930)
+ compatible = "renesas,r8a7793"
+ - R-Car E2 (R8A77940)
+ compatible = "renesas,r8a7794"
+
+
+Boards:
+
+ - Alt
+ compatible = "renesas,alt", "renesas,r8a7794"
+ - APE6-EVM
+ compatible = "renesas,ape6evm", "renesas,r8a73a4"
+ - APE6-EVM - Reference Device Tree Implementation
+ compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"
+ - Atmark Techno Armadillo-800 EVA
+ compatible = "renesas,armadillo800eva"
+ - BOCK-W
+ compatible = "renesas,bockw", "renesas,r8a7778"
+ - BOCK-W - Reference Device Tree Implementation
+ compatible = "renesas,bockw-reference", "renesas,r8a7778"
+ - Genmai (RTK772100BC00000BR)
+ compatible = "renesas,genmai", "renesas,r7s72100"
+ - Gose
+ compatible = "renesas,gose", "renesas,r8a7793"
+ - Henninger
+ compatible = "renesas,henninger", "renesas,r8a7791"
+ - Koelsch (RTP0RC7791SEB00010S)
+ compatible = "renesas,koelsch", "renesas,r8a7791"
+ - Kyoto Microcomputer Co. KZM-A9-Dual
+ compatible = "renesas,kzm9d", "renesas,emev2"
+ - Kyoto Microcomputer Co. KZM-A9-GT
+ compatible = "renesas,kzm9g", "renesas,sh73a0"
+ - Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation
+ compatible = "renesas,kzm9g-reference", "renesas,sh73a0"
+ - Lager (RTP0RC7790SEB00010S)
+ compatible = "renesas,lager", "renesas,r8a7790"
+ - Mackerel (R0P7372LC0016RL, AP4 EVM 2nd)
+ compatible = "renesas,mackerel"
+ - Marzen
+ compatible = "renesas,marzen", "renesas,r8a7779"
+
+Note: Reference Device Tree Implementations are temporary implementations
+ to ease the migration from platform devices to Device Tree, and are
+ intended to be removed in the future.
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/dts/Bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
new file mode 100644
index 0000000..ccf0add
--- /dev/null
+++ b/dts/Bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
@@ -0,0 +1,12 @@
+NVIDIA Tegra Flow Controller
+
+Required properties:
+- compatible: Should be "nvidia,tegra<chip>-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+ flow-controller@60007000 {
+ compatible = "nvidia,tegra20-flowctrl";
+ reg = <0x60007000 0x1000>;
+ };
diff --git a/dts/Bindings/ata/qcom-sata.txt b/dts/Bindings/ata/qcom-sata.txt
new file mode 100644
index 0000000..094de91
--- /dev/null
+++ b/dts/Bindings/ata/qcom-sata.txt
@@ -0,0 +1,48 @@
+* Qualcomm AHCI SATA Controller
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible : compatible list, must contain "generic-ahci"
+- interrupts : <interrupt mapping for SATA IRQ>
+- reg : <registers mapping>
+- phys : Must contain exactly one entry as specified
+ in phy-bindings.txt
+- phy-names : Must be "sata-phy"
+
+Required properties for "qcom,ipq806x-ahci" compatible:
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Shall be:
+ "slave_iface" - Fabric port AHB clock for SATA
+ "iface" - AHB clock
+ "core" - core clock
+ "rxoob" - RX out-of-band clock
+ "pmalive" - Power Module Alive clock
+- assigned-clocks : Shall be:
+ SATA_RXOOB_CLK
+ SATA_PMALIVE_CLK
+- assigned-clock-rates : Shall be:
+ 100Mhz (100000000) for SATA_RXOOB_CLK
+ 100Mhz (100000000) for SATA_PMALIVE_CLK
+
+Example:
+ sata@29000000 {
+ compatible = "qcom,ipq806x-ahci", "generic-ahci";
+ reg = <0x29000000 0x180>;
+
+ interrupts = <0 209 0x0>;
+
+ clocks = <&gcc SFAB_SATA_S_H_CLK>,
+ <&gcc SATA_H_CLK>,
+ <&gcc SATA_A_CLK>,
+ <&gcc SATA_RXOOB_CLK>,
+ <&gcc SATA_PMALIVE_CLK>;
+ clock-names = "slave_iface", "iface", "core",
+ "rxoob", "pmalive";
+ assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
+ assigned-clock-rates = <100000000>, <100000000>;
+
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ };
diff --git a/dts/Bindings/bus/bcma.txt b/dts/Bindings/bus/bcma.txt
new file mode 100644
index 0000000..62a4834
--- /dev/null
+++ b/dts/Bindings/bus/bcma.txt
@@ -0,0 +1,32 @@
+Driver for ARM AXI Bus with Broadcom Plugins (bcma)
+
+Required properties:
+
+- compatible : brcm,bus-axi
+
+- reg : iomem address range of chipcommon core
+
+The cores on the AXI bus are automatically detected by bcma with the
+memory ranges they are using and they get registered afterwards.
+
+The top-level axi bus may contain children representing attached cores
+(devices). This is needed since some hardware details can't be auto
+detected (e.g. IRQ numbers). Also some of the cores may be responsible
+for extra things, e.g. ChipCommon providing access to the GPIO chip.
+
+Example:
+
+ axi@18000000 {
+ compatible = "brcm,bus-axi";
+ reg = <0x18000000 0x1000>;
+ ranges = <0x00000000 0x18000000 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chipcommon {
+ reg = <0x00000000 0x1000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
diff --git a/dts/Bindings/clock/arm-integrator.txt b/dts/Bindings/clock/arm-integrator.txt
index ecc6952..11f5f95 100644
--- a/dts/Bindings/clock/arm-integrator.txt
+++ b/dts/Bindings/clock/arm-integrator.txt
@@ -1,6 +1,6 @@
Clock bindings for ARM Integrator and Versatile Core Module clocks
-Auxilary Oscillator Clock
+Auxiliary Oscillator Clock
This is a configurable clock fed from a 24 MHz chrystal,
used for generating e.g. video clocks. It is located on the
diff --git a/dts/Bindings/clock/at91-clock.txt b/dts/Bindings/clock/at91-clock.txt
index b3d544c..7a4d492 100644
--- a/dts/Bindings/clock/at91-clock.txt
+++ b/dts/Bindings/clock/at91-clock.txt
@@ -74,6 +74,9 @@ Required properties:
"atmel,at91sam9x5-clk-utmi":
at91 utmi clock
+ "atmel,sama5d4-clk-h32mx":
+ at91 h32mx clock
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
@@ -447,3 +450,14 @@ For example:
#clock-cells = <0>;
clocks = <&main>;
};
+
+Required properties for 32 bits bus Matrix clock (h32mx clock):
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the master clock source phandle.
+
+For example:
+ h32ck: h32mxck {
+ #clock-cells = <0>;
+ compatible = "atmel,sama5d4-clk-h32mx";
+ clocks = <&mck>;
+ };
diff --git a/dts/Bindings/clock/exynos3250-clock.txt b/dts/Bindings/clock/exynos3250-clock.txt
index aadc9c5..f57d9dd 100644
--- a/dts/Bindings/clock/exynos3250-clock.txt
+++ b/dts/Bindings/clock/exynos3250-clock.txt
@@ -7,6 +7,8 @@ Required Properties:
- compatible: should be one of the following.
- "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
+ - "samsung,exynos3250-cmu-dmc" - controller compatible with
+ Exynos3250 SoC for Dynamic Memory Controller domain.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -20,7 +22,7 @@ All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos3250.h header and can be used in device
tree sources.
-Example 1: An example of a clock controller node is listed below.
+Example 1: Examples of clock controller nodes are listed below.
cmu: clock-controller@10030000 {
compatible = "samsung,exynos3250-cmu";
@@ -28,6 +30,12 @@ Example 1: An example of a clock controller node is listed below.
#clock-cells = <1>;
};
+ cmu_dmc: clock-controller@105C0000 {
+ compatible = "samsung,exynos3250-cmu-dmc";
+ reg = <0x105C0000 0x2000>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
diff --git a/dts/Bindings/clock/gpio-gate-clock.txt b/dts/Bindings/clock/gpio-gate-clock.txt
new file mode 100644
index 0000000..d3379ff
--- /dev/null
+++ b/dts/Bindings/clock/gpio-gate-clock.txt
@@ -0,0 +1,21 @@
+Binding for simple gpio gated clock.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "gpio-gate-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- enable-gpios : GPIO reference for enabling and disabling the clock.
+
+Optional properties:
+- clocks: Maximum of one parent clock is supported.
+
+Example:
+ clock {
+ compatible = "gpio-gate-clock";
+ clocks = <&parentclk>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/Bindings/clock/maxim,max77686.txt b/dts/Bindings/clock/maxim,max77686.txt
index 96ce71b..9c40739 100644
--- a/dts/Bindings/clock/maxim,max77686.txt
+++ b/dts/Bindings/clock/maxim,max77686.txt
@@ -9,13 +9,21 @@ The MAX77686 contains three 32.768khz clock outputs that can be controlled
Following properties should be presend in main device node of the MFD chip.
Required properties:
-- #clock-cells: simple one-cell clock specifier format is used, where the
- only cell is used as an index of the clock inside the provider. Following
- indices are allowed:
+
+- #clock-cells: from common clock binding; shall be set to 1.
+
+Optional properties:
+- clock-output-names: From common clock binding.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Following indices are allowed:
- 0: 32khz_ap clock,
- 1: 32khz_cp clock,
- 2: 32khz_pmic clock.
+Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77686.h
+header and can be used in device tree sources.
+
Example: Node of the MFD chip
max77686: max77686@09 {
@@ -34,5 +42,5 @@ Example: Clock consumer node
compatible = "bar,foo";
/* ... */
clock-names = "my-clock";
- clocks = <&max77686 2>;
+ clocks = <&max77686 MAX77686_CLK_PMIC>;
};
diff --git a/dts/Bindings/clock/maxim,max77802.txt b/dts/Bindings/clock/maxim,max77802.txt
new file mode 100644
index 0000000..c6dc783
--- /dev/null
+++ b/dts/Bindings/clock/maxim,max77802.txt
@@ -0,0 +1,44 @@
+Binding for Maxim MAX77802 32k clock generator block
+
+This is a part of device tree bindings of MAX77802 multi-function device.
+More information can be found in bindings/mfd/max77802.txt file.
+
+The MAX77802 contains two 32.768khz clock outputs that can be controlled
+(gated/ungated) over I2C.
+
+Following properties should be present in main device node of the MFD chip.
+
+Required properties:
+- #clock-cells: From common clock binding; shall be set to 1.
+
+Optional properties:
+- clock-output-names: From common clock binding.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Following indices are allowed:
+ - 0: 32khz_ap clock,
+ - 1: 32khz_cp clock.
+
+Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77802.h
+header and can be used in device tree sources.
+
+Example: Node of the MFD chip
+
+ max77802: max77802@09 {
+ compatible = "maxim,max77802";
+ interrupt-parent = <&wakeup_eint>;
+ interrupts = <26 0>;
+ reg = <0x09>;
+ #clock-cells = <1>;
+
+ /* ... */
+ };
+
+Example: Clock consumer node
+
+ foo@0 {
+ compatible = "bar,foo";
+ /* ... */
+ clock-names = "my-clock";
+ clocks = <&max77802 MAX77802_CLK_32K_AP>;
+ };
diff --git a/dts/Bindings/clock/pxa-clock.txt b/dts/Bindings/clock/pxa-clock.txt
new file mode 100644
index 0000000..4b4a902
--- /dev/null
+++ b/dts/Bindings/clock/pxa-clock.txt
@@ -0,0 +1,16 @@
+* Clock bindings for Marvell PXA chips
+
+Required properties:
+- compatible: Should be "marvell,pxa-clocks"
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell (see include/.../pxa-clock.h).
+
+Examples:
+
+pxa2xx_clks: pxa2xx_clks@41300004 {
+ compatible = "marvell,pxa-clocks";
+ #clock-cells = <1>;
+ status = "okay";
+};
diff --git a/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt b/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt
index 8a92b5f..a5f5223 100644
--- a/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -11,9 +11,12 @@ Required Properties:
- compatible: Must be one of the following
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
+ - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+ - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
+ - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
- reg: Base address and length of the I/O mapped registers used by the MSTP
clocks. The first register is the clock control register and is mandatory.
diff --git a/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 7b41c2f..e6ad35b 100644
--- a/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Must be one of
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
+ - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
- "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
- reg: Base address and length of the memory resource used by the CPG
diff --git a/dts/Bindings/clock/sunxi.txt b/dts/Bindings/clock/sunxi.txt
index d3a5c3c..ed116df 100644
--- a/dts/Bindings/clock/sunxi.txt
+++ b/dts/Bindings/clock/sunxi.txt
@@ -46,7 +46,11 @@ Required properties:
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+ "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
+ "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
+ "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
+ "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
diff --git a/dts/Bindings/cpufreq/cpufreq-cpu0.txt b/dts/Bindings/cpufreq/cpufreq-dt.txt
index 366690c..e41c98f 100644
--- a/dts/Bindings/cpufreq/cpufreq-cpu0.txt
+++ b/dts/Bindings/cpufreq/cpufreq-dt.txt
@@ -1,8 +1,8 @@
-Generic CPU0 cpufreq driver
+Generic cpufreq driver
-It is a generic cpufreq driver for CPU0 frequency management. It
-supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
-systems which share clock and voltage across all CPUs.
+It is a generic DT based cpufreq driver for frequency management. It supports
+both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share
+clock and voltage across all CPUs.
Both required and optional properties listed below must be defined
under node /cpus/cpu@0.
diff --git a/dts/Bindings/crypto/fsl-sec6.txt b/dts/Bindings/crypto/fsl-sec6.txt
index c0a20cd..baf8a3c 100644
--- a/dts/Bindings/crypto/fsl-sec6.txt
+++ b/dts/Bindings/crypto/fsl-sec6.txt
@@ -1,5 +1,5 @@
SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
-Currently Freescale powerpc chip C29X is embeded with SEC 6.
+Currently Freescale powerpc chip C29X is embedded with SEC 6.
SEC 6 device tree binding include:
-SEC 6 Node
-Job Ring Node
diff --git a/dts/Bindings/dma/qcom_adm.txt b/dts/Bindings/dma/qcom_adm.txt
new file mode 100644
index 0000000..9bcab91
--- /dev/null
+++ b/dts/Bindings/dma/qcom_adm.txt
@@ -0,0 +1,62 @@
+QCOM ADM DMA Controller
+
+Required properties:
+- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
+- reg: Address range for DMA registers
+- interrupts: Should contain one interrupt shared by all channels
+- #dma-cells: must be <2>. First cell denotes the channel number. Second cell
+ denotes CRCI (client rate control interface) flow control assignment.
+- clocks: Should contain the core clock and interface clock.
+- clock-names: Must contain "core" for the core clock and "iface" for the
+ interface clock.
+- resets: Must contain an entry for each entry in reset names.
+- reset-names: Must include the following entries:
+ - clk
+ - c0
+ - c1
+ - c2
+- qcom,ee: indicates the security domain identifier used in the secure world.
+
+Example:
+ adm_dma: dma@18300000 {
+ compatible = "qcom,adm";
+ reg = <0x18300000 0x100000>;
+ interrupts = <0 170 0>;
+ #dma-cells = <2>;
+
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
+ clock-names = "core", "iface";
+
+ resets = <&gcc ADM0_RESET>,
+ <&gcc ADM0_C0_RESET>,
+ <&gcc ADM0_C1_RESET>,
+ <&gcc ADM0_C2_RESET>;
+ reset-names = "clk", "c0", "c1", "c2";
+ qcom,ee = <0>;
+ };
+
+DMA clients must use the format descripted in the dma.txt file, using a three
+cell specifier for each channel.
+
+Each dmas request consists of 3 cells:
+ 1. phandle pointing to the DMA controller
+ 2. channel number
+ 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0.
+ The CRCI is used for flow control. It identifies the peripheral device that
+ is the source/destination for the transferred data.
+
+Example:
+
+ spi4: spi@1a280000 {
+ status = "ok";
+ spi-max-frequency = <50000000>;
+
+ pinctrl-0 = <&spi_pins>;
+ pinctrl-names = "default";
+
+ cs-gpios = <&qcom_pinmux 20 0>;
+
+ dmas = <&adm_dma 6 9>,
+ <&adm_dma 5 10>;
+ dma-names = "rx", "tx";
+ };
diff --git a/dts/Bindings/dma/xilinx/xilinx_dma.txt b/dts/Bindings/dma/xilinx/xilinx_dma.txt
new file mode 100644
index 0000000..2291c40
--- /dev/null
+++ b/dts/Bindings/dma/xilinx/xilinx_dma.txt
@@ -0,0 +1,65 @@
+Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
+target devices. It can be configured to have one channel or two channels.
+If configured as two channels, one is to transmit to the device and another
+is to receive from the device.
+
+Required properties:
+- compatible: Should be "xlnx,axi-dma-1.00.a"
+- #dma-cells: Should be <1>, see "dmas" property below
+- reg: Should contain DMA registers location and length.
+- dma-channel child node: Should have atleast one channel and can have upto
+ two channels per device. This node specifies the properties of each
+ DMA channel (see child node properties below).
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+ the hardware.
+
+Required child node properties:
+- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
+ "xlnx,axi-dma-s2mm-channel".
+- interrupts: Should contain per channel DMA interrupts.
+- xlnx,datawidth: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+ Realignment Engine.
+
+Example:
+++++++++
+
+axi_dma_0: axidma@40400000 {
+ compatible = "xlnx,axi-dma-1.00.a";
+ #dma_cells = <1>;
+ reg = < 0x40400000 0x10000 >;
+ dma-channel@40400000 {
+ compatible = "xlnx,axi-dma-mm2s-channel";
+ interrupts = < 0 59 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+ dma-channel@40400030 {
+ compatible = "xlnx,axi-dma-s2mm-channel";
+ interrupts = < 0 58 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per "dmas" entry
+
+Example:
+++++++++
+
+dmatest_0: dmatest@0 {
+ compatible ="xlnx,axi-dma-test-1.00.a";
+ dmas = <&axi_dma_0 0
+ &axi_dma_0 1>;
+ dma-names = "dma0", "dma1";
+} ;
diff --git a/dts/Bindings/drm/tilcdc/panel.txt b/dts/Bindings/drm/tilcdc/panel.txt
index 9301c33..4ab9e23 100644
--- a/dts/Bindings/drm/tilcdc/panel.txt
+++ b/dts/Bindings/drm/tilcdc/panel.txt
@@ -18,6 +18,10 @@ Required properties:
Documentation/devicetree/bindings/video/display-timing.txt for display
timing binding details.
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+- enable-gpios: GPIO pin to enable or disable the panel
+
Recommended properties:
- pinctrl-names, pinctrl-0: the pincontrol settings to configure
muxing properly for pins that connect to TFP410 device
@@ -29,6 +33,9 @@ Example:
compatible = "ti,tilcdc,panel";
pinctrl-names = "default";
pinctrl-0 = <&bone_lcd3_cape_lcd_pins>;
+ backlight = <&backlight>;
+ enable-gpios = <&gpio3 19 0>;
+
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
diff --git a/dts/Bindings/extcon/extcon-rt8973a.txt b/dts/Bindings/extcon/extcon-rt8973a.txt
new file mode 100644
index 0000000..6dede7d
--- /dev/null
+++ b/dts/Bindings/extcon/extcon-rt8973a.txt
@@ -0,0 +1,25 @@
+
+* Richtek RT8973A - Micro USB Switch device
+
+The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A
+is a USB port accessory detector and switch that is optimized to protect low
+voltage system from abnormal high input voltage (up to 28V) and supports high
+speed USB operation. Also, RT8973A support 'auto-configuration' mode.
+If auto-configuration mode is enabled, RT8973A would control internal h/w patch
+for USB D-/D+ switching.
+
+Required properties:
+- compatible: Should be "richtek,rt8973a-muic"
+- reg: Specifies the I2C slave address of the MUIC block. It should be 0x14
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+ the interrupts from rt8973a are delivered to.
+- interrupts: Interrupt specifiers for detection interrupt sources.
+
+Example:
+
+ rt8973a@14 {
+ compatible = "richtek,rt8973a-muic";
+ interrupt-parent = <&gpx1>;
+ interrupts = <5 0>;
+ reg = <0x14>;
+ };
diff --git a/dts/Bindings/gpio/gpio-dsp-keystone.txt b/dts/Bindings/gpio/gpio-dsp-keystone.txt
new file mode 100644
index 0000000..6c7e6c7
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-dsp-keystone.txt
@@ -0,0 +1,39 @@
+Keystone 2 DSP GPIO controller bindings
+
+HOST OS userland running on ARM can send interrupts to DSP cores using
+the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
+This is one of the component used by the IPC mechanism used on Keystone SOCs.
+
+For example TCI6638K2K SoC has 8 DSP GPIO controllers:
+ - 8 for C66x CorePacx CPUs 0-7
+
+Keystone 2 DSP GPIO controller has specific features:
+- each GPIO can be configured only as output pin;
+- setting GPIO value to 1 causes IRQ generation on target DSP core;
+- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
+ pending.
+
+Required Properties:
+- compatible: should be "ti,keystone-dsp-gpio"
+- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
+ access device state control registers and the offset of device's specific
+ registers within device state control registers range.
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be 2.
+
+Please refer to gpio.txt in this directory for details of the common GPIO
+bindings used by client devices.
+
+Example:
+ dspgpio0: keystone_dsp_gpio@02620240 {
+ compatible = "ti,keystone-dsp-gpio";
+ ti,syscon-dev = <&devctrl 0x240>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ dsp0: dsp0 {
+ compatible = "linux,rproc-user";
+ ...
+ kick-gpio = <&dspgpio0 27>;
+ };
diff --git a/dts/Bindings/gpio/gpio-pca953x.txt b/dts/Bindings/gpio/gpio-pca953x.txt
new file mode 100644
index 0000000..b9a42f2
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-pca953x.txt
@@ -0,0 +1,39 @@
+* NXP PCA953x I2C GPIO multiplexer
+
+Required properties:
+ - compatible: Has to contain one of the following:
+ nxp,pca9505
+ nxp,pca9534
+ nxp,pca9535
+ nxp,pca9536
+ nxp,pca9537
+ nxp,pca9538
+ nxp,pca9539
+ nxp,pca9554
+ nxp,pca9555
+ nxp,pca9556
+ nxp,pca9557
+ nxp,pca9574
+ nxp,pca9575
+ nxp,pca9698
+ maxim,max7310
+ maxim,max7312
+ maxim,max7313
+ maxim,max7315
+ ti,pca6107
+ ti,tca6408
+ ti,tca6416
+ ti,tca6424
+ exar,xra1202
+
+Example:
+
+
+ gpio@20 {
+ compatible = "nxp,pca9505";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9505>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ };
diff --git a/dts/Bindings/gpio/gpio-restart.txt b/dts/Bindings/gpio/gpio-restart.txt
new file mode 100644
index 0000000..af3701b
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-restart.txt
@@ -0,0 +1,54 @@
+Drive a GPIO line that can be used to restart the system from a restart
+handler.
+
+This binding supports level and edge triggered reset. At driver load
+time, the driver will request the given gpio line and install a restart
+handler. If the optional properties 'open-source' is not found, the GPIO line
+will be driven in the inactive state. Otherwise its not driven until
+the restart is initiated.
+
+When the system is restarted, the restart handler will be invoked in
+priority order. The gpio is configured as an output, and driven active,
+triggering a level triggered reset condition. This will also cause an
+inactive->active edge condition, triggering positive edge triggered
+reset. After a delay specified by active-delay, the GPIO is set to
+inactive, thus causing an active->inactive edge, triggering negative edge
+triggered reset. After a delay specified by inactive-delay, the GPIO
+is driven active again. After a delay specified by wait-delay, the
+restart handler completes allowing other restart handlers to be attempted.
+
+Required properties:
+- compatible : should be "gpio-restart".
+- gpios : The GPIO to set high/low, see "gpios property" in
+ Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be
+ low to reset the board set it to "Active Low", otherwise set
+ gpio to "Active High".
+
+Optional properties:
+- open-source : Treat the GPIO as being open source and defer driving
+ it to when the restart is initiated. If this optional property is not
+ specified, the GPIO is initialized as an output in its inactive state.
+- priority : A priority ranging from 0 to 255 (default 128) according to
+ the following guidelines:
+ 0: Restart handler of last resort, with limited restart
+ capabilities
+ 128: Default restart handler; use if no other restart handler is
+ expected to be available, and/or if restart functionality is
+ sufficient to restart the entire system
+ 255: Highest priority restart handler, will preempt all other
+ restart handlers
+- active-delay: Delay (default 100) to wait after driving gpio active [ms]
+- inactive-delay: Delay (default 100) to wait after driving gpio inactive [ms]
+- wait-delay: Delay (default 3000) to wait after completing restart
+ sequence [ms]
+
+Examples:
+
+gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 4 0>;
+ priority = <128>;
+ active-delay = <100>;
+ inactive-delay = <100>;
+ wait-delay = <3000>;
+};
diff --git a/dts/Bindings/gpio/gpio-xgene.txt b/dts/Bindings/gpio/gpio-xgene.txt
new file mode 100644
index 0000000..86dbb05
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-xgene.txt
@@ -0,0 +1,22 @@
+APM X-Gene SoC GPIO controller bindings
+
+This is a gpio controller that is part of the flash controller.
+This gpio controller controls a total of 48 gpios.
+
+Required properties:
+- compatible: "apm,xgene-gpio" for X-Gene GPIO controller
+- reg: Physical base address and size of the controller's registers
+- #gpio-cells: Should be two.
+ - first cell is the pin number
+ - second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+- gpio-controller: Marks the device node as a GPIO controller.
+
+Example:
+ gpio0: gpio0@1701c000 {
+ compatible = "apm,xgene-gpio";
+ reg = <0x0 0x1701c000 0x0 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
diff --git a/dts/Bindings/gpio/mrvl-gpio.txt b/dts/Bindings/gpio/mrvl-gpio.txt
index 6641626..b2afdb2 100644
--- a/dts/Bindings/gpio/mrvl-gpio.txt
+++ b/dts/Bindings/gpio/mrvl-gpio.txt
@@ -19,7 +19,7 @@ Required properties:
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be one. It is the pin number.
-Example:
+Example for a MMP platform:
gpio: gpio@d4019000 {
compatible = "marvell,mmp-gpio";
@@ -32,6 +32,19 @@ Example:
#interrupt-cells = <1>;
};
+Example for a PXA3xx platform:
+
+ gpio: gpio@40e00000 {
+ compatible = "intel,pxa3xx-gpio";
+ reg = <0x40e00000 0x10000>;
+ interrupt-names = "gpio0", "gpio1", "gpio_mux";
+ interrupts = <8 9 10>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ };
+
* Marvell Orion GPIO Controller
Required properties:
diff --git a/dts/Bindings/hwmon/ntc_thermistor.txt b/dts/Bindings/hwmon/ntc_thermistor.txt
index 2391e5c..fcca8e7 100644
--- a/dts/Bindings/hwmon/ntc_thermistor.txt
+++ b/dts/Bindings/hwmon/ntc_thermistor.txt
@@ -25,6 +25,9 @@ Requires node properties:
- "io-channels" Channel node of ADC to be used for
conversion.
+Optional node properties:
+- "#thermal-sensor-cells" Used to expose itself to thermal fw.
+
Read more about iio bindings at
Documentation/devicetree/bindings/iio/iio-bindings.txt
diff --git a/dts/Bindings/i2c/i2c-axxia.txt b/dts/Bindings/i2c/i2c-axxia.txt
new file mode 100644
index 0000000..2296d78
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-axxia.txt
@@ -0,0 +1,30 @@
+LSI Axxia I2C
+
+Required properties :
+- compatible : Must be "lsi,api2c"
+- reg : Offset and length of the register set for the device
+- interrupts : the interrupt specifier
+- #address-cells : Must be <1>;
+- #size-cells : Must be <0>;
+- clock-names : Must contain "i2c".
+- clocks: Must contain an entry for each name in clock-names. See the common
+ clock bindings.
+
+Optional properties :
+- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
+ the default 100 kHz frequency will be used. As only Normal and Fast modes
+ are supported, possible values are 100000 and 400000.
+
+Example :
+
+i2c@02010084000 {
+ compatible = "lsi,api2c";
+ device_type = "i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x20 0x10084000 0x00 0x1000>;
+ interrupts = <0 19 4>;
+ clocks = <&clk_per>;
+ clock-names = "i2c";
+ clock-frequency = <400000>;
+};
diff --git a/dts/Bindings/i2c/i2c-exynos5.txt b/dts/Bindings/i2c/i2c-exynos5.txt
index d4745e3..2dbc0b6 100644
--- a/dts/Bindings/i2c/i2c-exynos5.txt
+++ b/dts/Bindings/i2c/i2c-exynos5.txt
@@ -12,6 +12,8 @@ Required properties:
on Exynos5250 and Exynos5420 SoCs.
-> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
on Exynos5260 SoCs.
+ -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available
+ on Exynos7 SoCs.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/dts/Bindings/i2c/i2c-hix5hd2.txt b/dts/Bindings/i2c/i2c-hix5hd2.txt
new file mode 100644
index 0000000..f98b374
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-hix5hd2.txt
@@ -0,0 +1,24 @@
+I2C for Hisilicon hix5hd2 chipset platform
+
+Required properties:
+- compatible: Must be "hisilicon,hix5hd2-i2c"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks: phandles to input clocks.
+
+Optional properties:
+- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
+- Child nodes conforming to i2c bus binding
+
+Examples:
+I2C0@f8b10000 {
+ compatible = "hisilicon,hix5hd2-i2c";
+ reg = <0xf8b10000 0x1000>;
+ interrupts = <0 38 4>;
+ clocks = <&clock HIX5HD2_I2C0_RST>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+}
diff --git a/dts/Bindings/i2c/ti,bq32k.txt b/dts/Bindings/i2c/ti,bq32k.txt
new file mode 100644
index 0000000..e204906
--- /dev/null
+++ b/dts/Bindings/i2c/ti,bq32k.txt
@@ -0,0 +1,18 @@
+* TI BQ32000 I2C Serial Real-Time Clock
+
+Required properties:
+- compatible: Should contain "ti,bq32000".
+- reg: I2C address for chip
+
+Optional properties:
+- trickle-resistor-ohms : Selected resistor for trickle charger
+ Values usable are 1120 and 20180
+ Should be given if trickle charger should be enabled
+- trickle-diode-disable : Do not use internal trickle charger diode
+ Should be given if internal trickle charger diode should be disabled
+Example:
+ bq32000: rtc@68 {
+ compatible = "ti,bq32000";
+ trickle-resistor-ohms = <1120>;
+ reg = <0x68>;
+ };
diff --git a/dts/Bindings/i2c/trivial-devices.txt b/dts/Bindings/i2c/trivial-devices.txt
index 6af570e..fbde415 100644
--- a/dts/Bindings/i2c/trivial-devices.txt
+++ b/dts/Bindings/i2c/trivial-devices.txt
@@ -35,7 +35,6 @@ catalyst,24c32 i2c serial eeprom
cirrus,cs42l51 Cirrus Logic CS42L51 audio codec
dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock
dallas,ds1338 I2C RTC with 56-Byte NV RAM
-dallas,ds1339 I2C Serial Real-Time Clock
dallas,ds1340 I2C RTC with Trickle Charger
dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
dallas,ds1631 High-Precision Digital Thermometer
@@ -44,7 +43,7 @@ dallas,ds1775 Tiny Digital Thermometer and Thermostat
dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
dallas,ds75 Digital Thermometer and Thermostat
-dialog,da9053 DA9053: flexible system level PMIC with multicore support
+dlg,da9053 DA9053: flexible system level PMIC with multicore support
epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
diff --git a/dts/Bindings/iio/adc/rockchip-saradc.txt b/dts/Bindings/iio/adc/rockchip-saradc.txt
new file mode 100644
index 0000000..5d3ec1d
--- /dev/null
+++ b/dts/Bindings/iio/adc/rockchip-saradc.txt
@@ -0,0 +1,24 @@
+Rockchip Successive Approximation Register (SAR) A/D Converter bindings
+
+Required properties:
+- compatible: Should be "rockchip,saradc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: The interrupt number to the cpu. The interrupt specifier format
+ depends on the interrupt controller.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for
+ the peripheral clock.
+- vref-supply: The regulator supply ADC reference voltage.
+- #io-channel-cells: Should be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: saradc@2006c000 {
+ compatible = "rockchip,saradc";
+ reg = <0x2006c000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ #io-channel-cells = <1>;
+ vref-supply = <&vcc18>;
+ };
diff --git a/dts/Bindings/iio/adc/vf610-adc.txt b/dts/Bindings/iio/adc/vf610-adc.txt
index dcebff1..1a4a43d 100644
--- a/dts/Bindings/iio/adc/vf610-adc.txt
+++ b/dts/Bindings/iio/adc/vf610-adc.txt
@@ -9,7 +9,7 @@ Required properties:
- interrupts: Should contain the interrupt for the device
- clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock.
- clock-names: Must contain "adc", matching entry in the clocks property.
-- vref-supply: The regulator supply ADC refrence voltage.
+- vref-supply: The regulator supply ADC reference voltage.
Example:
adc0: adc@4003b000 {
diff --git a/dts/Bindings/iio/dac/max5821.txt b/dts/Bindings/iio/dac/max5821.txt
new file mode 100644
index 0000000..54276ce
--- /dev/null
+++ b/dts/Bindings/iio/dac/max5821.txt
@@ -0,0 +1,14 @@
+Maxim max5821 DAC device driver
+
+Required properties:
+ - compatible: Must be "maxim,max5821"
+ - reg: Should contain the DAC I2C address
+ - vref-supply: Phandle to the vref power supply
+
+Example:
+
+ max5821@38 {
+ compatible = "maxim,max5821";
+ reg = <0x38>;
+ vref-supply = <&reg_max5821>;
+ };
diff --git a/dts/Bindings/input/ti,drv260x.txt b/dts/Bindings/input/ti,drv260x.txt
new file mode 100644
index 0000000..ee09c8f
--- /dev/null
+++ b/dts/Bindings/input/ti,drv260x.txt
@@ -0,0 +1,50 @@
+* Texas Instruments - drv260x Haptics driver family
+
+Required properties:
+ - compatible - One of:
+ "ti,drv2604" - DRV2604
+ "ti,drv2605" - DRV2605
+ "ti,drv2605l" - DRV2605L
+ - reg - I2C slave address
+ - vbat-supply - Required supply regulator
+ - mode - Power up mode of the chip (defined in include/dt-bindings/input/ti-drv260x.h)
+ DRV260X_LRA_MODE - Linear Resonance Actuator mode (Piezoelectric)
+ DRV260X_LRA_NO_CAL_MODE - This is a LRA Mode but there is no calibration
+ sequence during init. And the device is configured for real
+ time playback mode (RTP mode).
+ DRV260X_ERM_MODE - Eccentric Rotating Mass mode (Rotary vibrator)
+ - library-sel - These are ROM based waveforms pre-programmed into the IC.
+ This should be set to set the library to use at power up.
+ (defined in include/dt-bindings/input/ti-drv260x.h)
+ DRV260X_LIB_EMPTY - Do not use a pre-programmed library
+ DRV260X_ERM_LIB_A - Pre-programmed Library
+ DRV260X_ERM_LIB_B - Pre-programmed Library
+ DRV260X_ERM_LIB_C - Pre-programmed Library
+ DRV260X_ERM_LIB_D - Pre-programmed Library
+ DRV260X_ERM_LIB_E - Pre-programmed Library
+ DRV260X_ERM_LIB_F - Pre-programmed Library
+ DRV260X_LIB_LRA - Pre-programmed LRA Library
+
+Optional properties:
+ - enable-gpio - gpio pin to enable/disable the device.
+ - vib-rated-mv - The rated voltage of the actuator in millivolts.
+ If this is not set then the value will be defaulted to
+ 3.2 v.
+ - vib-overdrive-mv - The overdrive voltage of the actuator in millivolts.
+ If this is not set then the value will be defaulted to
+ 3.2 v.
+Example:
+
+haptics: haptics@5a {
+ compatible = "ti,drv2605l";
+ reg = <0x5a>;
+ vbat-supply = <&vbat>;
+ enable-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ mode = <DRV260X_LRA_MODE>;
+ library-sel = <DRV260X_LIB_LRA>;
+ vib-rated-mv = <3200>;
+ vib-overdriver-mv = <3200>;
+}
+
+For more product information please see the link below:
+http://www.ti.com/product/drv2605
diff --git a/dts/Bindings/input/ti,drv2667.txt b/dts/Bindings/input/ti,drv2667.txt
new file mode 100644
index 0000000..996382c
--- /dev/null
+++ b/dts/Bindings/input/ti,drv2667.txt
@@ -0,0 +1,17 @@
+* Texas Instruments - drv2667 Haptics driver
+
+Required properties:
+ - compatible - "ti,drv2667" - DRV2667
+ - reg - I2C slave address
+ - vbat-supply - Required supply regulator
+
+Example:
+
+haptics: haptics@59 {
+ compatible = "ti,drv2667";
+ reg = <0x59>;
+ vbat-supply = <&vbat>;
+};
+
+For more product information please see the link below:
+http://www.ti.com/product/drv2667
diff --git a/dts/Bindings/input/ti,palmas-pwrbutton.txt b/dts/Bindings/input/ti,palmas-pwrbutton.txt
new file mode 100644
index 0000000..a3dde8c
--- /dev/null
+++ b/dts/Bindings/input/ti,palmas-pwrbutton.txt
@@ -0,0 +1,36 @@
+Texas Instruments Palmas family power button module
+
+This module is part of the Palmas family of PMICs. For more details
+about the whole chip see:
+Documentation/devicetree/bindings/mfd/palmas.txt.
+
+This module provides a simple power button event via an Interrupt.
+
+Required properties:
+- compatible: should be one of the following
+ - "ti,palmas-pwrbutton": For Palmas compatible power on button
+- interrupt-parent: Parent interrupt device, must be handle of palmas node.
+- interrupts: Interrupt number of power button submodule on device.
+
+Optional Properties:
+
+- ti,palmas-long-press-seconds: Duration in seconds which the power
+ button should be kept pressed for Palmas to power off automatically.
+ NOTE: This depends on OTP support and POWERHOLD signal configuration
+ on platform. Valid values are 6, 8, 10 and 12.
+- ti,palmas-pwron-debounce-milli-seconds: Duration in milliseconds
+ which the power button should be kept pressed for Palmas to register
+ a press for debouncing purposes. NOTE: This depends on specific
+ Palmas variation capability. Valid values are 15, 100, 500 and 1000.
+
+Example:
+
+&palmas {
+ palmas_pwr_button: pwrbutton {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps659038>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ ti,palmas-long-press-seconds = <12>;
+ ti,palmas-pwron-debounce-milli-seconds = <15>;
+ };
+};
diff --git a/dts/Bindings/interrupt-controller/atmel,aic.txt b/dts/Bindings/interrupt-controller/atmel,aic.txt
index 2742e9c..f292917 100644
--- a/dts/Bindings/interrupt-controller/atmel,aic.txt
+++ b/dts/Bindings/interrupt-controller/atmel,aic.txt
@@ -2,7 +2,7 @@
Required properties:
- compatible: Should be "atmel,<chip>-aic"
- <chip> can be "at91rm9200" or "sama5d3"
+ <chip> can be "at91rm9200", "sama5d3" or "sama5d4"
- interrupt-controller: Identifies the node as an interrupt controller.
- interrupt-parent: For single AIC system, it is an empty property.
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
diff --git a/dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
new file mode 100644
index 0000000..ff812a8
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
@@ -0,0 +1,86 @@
+Broadcom BCM7120-style Level 2 interrupt controller
+
+This interrupt controller hardware is a second level interrupt controller that
+is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
+platforms. It can be found on BCM7xxx products starting with BCM7120.
+
+Such an interrupt controller has the following hardware design:
+
+- outputs multiple interrupts signals towards its interrupt controller parent
+
+- controls how some of the interrupts will be flowing, whether they will
+ directly output an interrupt signal towards the interrupt controller parent,
+ or if they will output an interrupt signal at this 2nd level interrupt
+ controller, in particular for UARTs
+
+- not all 32-bits within the interrupt controller actually map to an interrupt
+
+The typical hardware layout for this controller is represented below:
+
+2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
+
+0 -----[ MUX ] ------------|==========> GIC interrupt 75
+ \-----------\
+ |
+1 -----[ MUX ] --------)---|==========> GIC interrupt 76
+ \------------|
+ |
+2 -----[ MUX ] --------)---|==========> GIC interrupt 77
+ \------------|
+ |
+3 ---------------------|
+4 ---------------------|
+5 ---------------------|
+7 ---------------------|---|===========> GIC interrupt 66
+9 ---------------------|
+10 --------------------|
+11 --------------------/
+
+6 ------------------------\
+ |===========> GIC interrupt 64
+8 ------------------------/
+
+12 ........................ X
+13 ........................ X (not connected)
+..
+31 ........................ X
+
+Required properties:
+
+- compatible: should be "brcm,bcm7120-l2-intc"
+- reg: specifies the base physical address and size of the registers
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+ source, should be 1.
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+ this one is cascaded from
+- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
+ node, valid values depend on the type of parent interrupt controller
+- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
+ are wired to this 2nd level interrupt controller, and how they match their
+ respective interrupt parents. Should match exactly the number of interrupts
+ specified in the 'interrupts' property.
+
+Optional properties:
+
+- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
+ wakeup source for system suspend/resume.
+
+- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the
+ interrupts which have a mux gate, typically UARTs. Setting these bits will
+ make their respective interrupts outputs bypass this 2nd level interrupt
+ controller completely, it completely transparent for the interrupt controller
+ parent
+
+Example:
+
+irq0_intc: interrupt-controller@f0406800 {
+ compatible = "brcm,bcm7120-l2-intc";
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <1>;
+ reg = <0xf0406800 0x8>;
+ interrupt-controller;
+ interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+ brcm,int-map-mask = <0xeb8>, <0x140>;
+ brcm,int-fwd-mask = <0x7>;
+};
diff --git a/dts/Bindings/interrupt-controller/renesas,intc-irqpin.txt b/dts/Bindings/interrupt-controller/renesas,intc-irqpin.txt
index 1f8b0c5..c73acd0 100644
--- a/dts/Bindings/interrupt-controller/renesas,intc-irqpin.txt
+++ b/dts/Bindings/interrupt-controller/renesas,intc-irqpin.txt
@@ -2,7 +2,13 @@ DT bindings for the R-/SH-Mobile irqpin controller
Required properties:
-- compatible: has to be "renesas,intc-irqpin"
+- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
+ as fallback.
+ Examples with soctypes are:
+ - "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
+ - "renesas,intc-irqpin-r8a7778" (R-Car M1A)
+ - "renesas,intc-irqpin-r8a7779" (R-Car H1)
+ - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
interrupts.txt in this directory
diff --git a/dts/Bindings/interrupt-controller/renesas,irqc.txt b/dts/Bindings/interrupt-controller/renesas,irqc.txt
new file mode 100644
index 0000000..1a88e62
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/renesas,irqc.txt
@@ -0,0 +1,32 @@
+DT bindings for the R-Mobile/R-Car interrupt controller
+
+Required properties:
+
+- compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.
+ Examples with soctypes are:
+ - "renesas,irqc-r8a73a4" (R-Mobile AP6)
+ - "renesas,irqc-r8a7790" (R-Car H2)
+ - "renesas,irqc-r8a7791" (R-Car M2-W)
+ - "renesas,irqc-r8a7792" (R-Car V2H)
+ - "renesas,irqc-r8a7793" (R-Car M2-N)
+ - "renesas,irqc-r8a7794" (R-Car E2)
+- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
+ interrupts.txt in this directory
+
+Optional properties:
+
+- any properties, listed in interrupts.txt, and any standard resource allocation
+ properties
+
+Example:
+
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7790", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/interrupt-controller/ti,keystone-irq.txt b/dts/Bindings/interrupt-controller/ti,keystone-irq.txt
new file mode 100644
index 0000000..d9bb106
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/ti,keystone-irq.txt
@@ -0,0 +1,36 @@
+Keystone 2 IRQ controller IP
+
+On Keystone SOCs, DSP cores can send interrupts to ARM
+host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
+The IRQ handler running on HOST OS can identify DSP signal source by
+analyzing SRCCx bits in IPCARx registers. This is one of the component
+used by the IPC mechanism used on Keystone SOCs.
+
+Required Properties:
+- compatible: should be "ti,keystone-irq"
+- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
+ access device control registers and the offset inside
+ device control registers range.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode interrupt
+ source should be 1.
+- interrupts: interrupt reference to primary interrupt controller
+
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
+Example:
+ kirq0: keystone_irq0@026202a0 {
+ compatible = "ti,keystone-irq";
+ ti,syscon-dev = <&devctrl 0x2a0>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ dsp0: dsp0 {
+ compatible = "linux,rproc-user";
+ ...
+ interrupt-parent = <&kirq0>;
+ interrupts = <10 2>;
+ };
diff --git a/dts/Bindings/iommu/arm,smmu.txt b/dts/Bindings/iommu/arm,smmu.txt
index 2d0f7cd..0676050 100644
--- a/dts/Bindings/iommu/arm,smmu.txt
+++ b/dts/Bindings/iommu/arm,smmu.txt
@@ -14,6 +14,7 @@ conditions.
"arm,smmu-v1"
"arm,smmu-v2"
"arm,mmu-400"
+ "arm,mmu-401"
"arm,mmu-500"
depending on the particular implementation and/or the
diff --git a/dts/Bindings/leds/register-bit-led.txt b/dts/Bindings/leds/register-bit-led.txt
new file mode 100644
index 0000000..379cefd
--- /dev/null
+++ b/dts/Bindings/leds/register-bit-led.txt
@@ -0,0 +1,99 @@
+Device Tree Bindings for Register Bit LEDs
+
+Register bit leds are used with syscon multifunctional devices
+where single bits in a certain register can turn on/off a
+single LED. The register bit LEDs appear as children to the
+syscon device, with the proper compatible string. For the
+syscon bindings see:
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Each LED is represented as a sub-node of the syscon device. Each
+node's name represents the name of the corresponding LED.
+
+LED sub-node properties:
+
+Required properties:
+- compatible : must be "register-bit-led"
+- offset : register offset to the register controlling this LED
+- mask : bit mask for the bit controlling this LED in the register
+ typically 0x01, 0x02, 0x04 ...
+
+Optional properties:
+- label : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+- linux,default-trigger : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+- default-state: (optional) The initial state of the LED. Valid
+ values are "on", "off", and "keep". If the LED is already on or off
+ and the default-state property is set the to same value, then no
+ glitch should be produced where the LED momentarily turns off (or
+ on). The "keep" setting will keep the LED at whatever its current
+ state is, without producing a glitch. The default is off if this
+ property is not present.
+
+Example:
+
+syscon: syscon@10000000 {
+ compatible = "arm,realview-pb1176-syscon", "syscon";
+ reg = <0x10000000 0x1000>;
+
+ led@08.0 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x01>;
+ label = "versatile:0";
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+ led@08.1 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x02>;
+ label = "versatile:1";
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+ led@08.2 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x04>;
+ label = "versatile:2";
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+ led@08.3 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x08>;
+ label = "versatile:3";
+ default-state = "off";
+ };
+ led@08.4 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x10>;
+ label = "versatile:4";
+ default-state = "off";
+ };
+ led@08.5 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x20>;
+ label = "versatile:5";
+ default-state = "off";
+ };
+ led@08.6 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x40>;
+ label = "versatile:6";
+ default-state = "off";
+ };
+ led@08.7 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x80>;
+ label = "versatile:7";
+ default-state = "off";
+ };
+};
diff --git a/dts/Bindings/mailbox/omap-mailbox.txt b/dts/Bindings/mailbox/omap-mailbox.txt
new file mode 100644
index 0000000..48edc4b
--- /dev/null
+++ b/dts/Bindings/mailbox/omap-mailbox.txt
@@ -0,0 +1,108 @@
+OMAP2+ Mailbox Driver
+=====================
+
+The OMAP mailbox hardware facilitates communication between different processors
+using a queued mailbox interrupt mechanism. The IP block is external to the
+various processor subsystems and is connected on an interconnect bus. The
+communication is achieved through a set of registers for message storage and
+interrupt configuration registers.
+
+Each mailbox IP block has a certain number of h/w fifo queues and output
+interrupt lines. An output interrupt line is routed to an interrupt controller
+within a processor subsystem, and there can be more than one line going to a
+specific processor's interrupt controller. The interrupt line connections are
+fixed for an instance and are dictated by the IP integration into the SoC
+(excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
+programmable through a set of interrupt configuration registers, and have a rx
+and tx interrupt source per h/w fifo. Communication between different processors
+is achieved through the appropriate programming of the rx and tx interrupt
+sources on the appropriate interrupt lines.
+
+The number of h/w fifo queues and interrupt lines dictate the usable registers.
+All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
+instance. DRA7xx has multiple instances with different number of h/w fifo queues
+and interrupt lines between different instances. The interrupt lines can also be
+routed to different processor sub-systems on DRA7xx as they are routed through
+the Crossbar, a kind of interrupt router/multiplexer.
+
+Mailbox Device Node:
+====================
+A Mailbox device node is used to represent a Mailbox IP instance within a SoC.
+The sub-mailboxes are represented as child nodes of this parent node.
+
+Required properties:
+--------------------
+- compatible: Should be one of the following,
+ "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
+ "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
+ "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
+ AM43xx and DRA7xx SoCs
+- reg: Contains the mailbox register address range (base
+ address and length)
+- interrupts: Contains the interrupt information for the mailbox
+ device. The format is dependent on which interrupt
+ controller the OMAP device uses
+- ti,hwmods: Name of the hwmod associated with the mailbox
+- ti,mbox-num-users: Number of targets (processor devices) that the mailbox
+ device can interrupt
+- ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
+
+Child Nodes:
+============
+A child node is used for representing the actual sub-mailbox device that is
+used for the communication between the host processor and a remote processor.
+Each child node should have a unique node name across all the different
+mailbox device nodes.
+
+Required properties:
+--------------------
+- ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
+- ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
+
+Sub-mailbox Descriptor Data
+---------------------------
+Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
+data that represent the following:
+ Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
+ (ti,mbox-tx) or for receiving (ti,mbox-rx)
+ Cell #2 (irq_id) - irq identifier index number to use from the parent's
+ interrupts data. Should be 0 for most of the cases, a
+ positive index value is seen only on mailboxes that have
+ multiple interrupt lines connected to the MPU processor.
+ Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
+ associated with generating a tx/rx fifo interrupt.
+
+Example:
+--------
+
+/* OMAP4 */
+mailbox: mailbox@4a0f4000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4a0f4000 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox";
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+ mbox_ipu: mbox_ipu {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <1 0 0>;
+ };
+ mbox_dsp: mbox_dsp {
+ ti,mbox-tx = <3 0 0>;
+ ti,mbox-rx = <2 0 0>;
+ };
+};
+
+/* AM33xx */
+mailbox: mailbox@480C8000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x480C8000 0x200>;
+ interrupts = <77>;
+ ti,hwmods = "mailbox";
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <8>;
+ mbox_wkupm3: wkup_m3 {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <0 0 3>;
+ };
+};
diff --git a/dts/Bindings/media/hix5hd2-ir.txt b/dts/Bindings/media/hix5hd2-ir.txt
new file mode 100644
index 0000000..fb5e760
--- /dev/null
+++ b/dts/Bindings/media/hix5hd2-ir.txt
@@ -0,0 +1,25 @@
+Device-Tree bindings for hix5hd2 ir IP
+
+Required properties:
+ - compatible: Should contain "hisilicon,hix5hd2-ir".
+ - reg: Base physical address of the controller and length of memory
+ mapped region.
+ - interrupts: interrupt-specifier for the sole interrupt generated by
+ the device. The interrupt specifier format depends on the interrupt
+ controller parent.
+ - clocks: clock phandle and specifier pair.
+ - hisilicon,power-syscon: phandle of syscon used to control power.
+
+Optional properties:
+ - linux,rc-map-name : Remote control map name.
+
+Example node:
+
+ ir: ir@f8001000 {
+ compatible = "hisilicon,hix5hd2-ir";
+ reg = <0xf8001000 0x1000>;
+ interrupts = <0 47 4>;
+ clocks = <&clock HIX5HD2_FIXED_24M>;
+ hisilicon,power-syscon = <&sysctrl>;
+ linux,rc-map-name = "rc-tivo";
+ };
diff --git a/dts/Bindings/memory-controllers/synopsys.txt b/dts/Bindings/memory-controllers/synopsys.txt
new file mode 100644
index 0000000..f9c6454
--- /dev/null
+++ b/dts/Bindings/memory-controllers/synopsys.txt
@@ -0,0 +1,11 @@
+Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
+
+Required properties:
+ - compatible: Should be 'xlnx,zynq-ddrc-a05'
+ - reg: Base address and size of the controllers memory area
+
+Example:
+ memory-controller@f8006000 {
+ compatible = "xlnx,zynq-ddrc-a05";
+ reg = <0xf8006000 0x1000>;
+ };
diff --git a/dts/Bindings/mfd/arizona.txt b/dts/Bindings/mfd/arizona.txt
index 5c7e723..7bd1273 100644
--- a/dts/Bindings/mfd/arizona.txt
+++ b/dts/Bindings/mfd/arizona.txt
@@ -42,6 +42,13 @@ Optional properties:
the chip default will be used. If present exactly five values must
be specified.
+ - wlf,inmode : A list of INn_MODE register values, where n is the number
+ of input signals. Valid values are 0 (Differential), 1 (Single-ended) and
+ 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default.
+ If present, values must be specified less than or equal to the number of
+ input singals. If values less than the number of input signals, elements
+ that has not been specifed are set to 0 by default.
+
- DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if
they are being externally supplied. As covered in
Documentation/devicetree/bindings/regulator/regulator.txt
diff --git a/dts/Bindings/mfd/atmel-gpbr.txt b/dts/Bindings/mfd/atmel-gpbr.txt
new file mode 100644
index 0000000..a285695
--- /dev/null
+++ b/dts/Bindings/mfd/atmel-gpbr.txt
@@ -0,0 +1,15 @@
+* Device tree bindings for Atmel GPBR (General Purpose Backup Registers)
+
+The GPBR are a set of battery-backed registers.
+
+Required properties:
+- compatible: "atmel,at91sam9260-gpbr", "syscon"
+- reg: contains offset/length value of the GPBR memory
+ region.
+
+Example:
+
+gpbr: gpbr@fffffd50 {
+ compatible = "atmel,at91sam9260-gpbr", "syscon";
+ reg = <0xfffffd50 0x10>;
+};
diff --git a/dts/Bindings/mfd/hi6421.txt b/dts/Bindings/mfd/hi6421.txt
new file mode 100644
index 0000000..0d5a446
--- /dev/null
+++ b/dts/Bindings/mfd/hi6421.txt
@@ -0,0 +1,38 @@
+* HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
+
+Required parent device properties:
+- compatible : contains "hisilicon,hi6421-pmic";
+- reg : register range space of hi6421;
+
+Supported Hi6421 sub-devices include:
+
+Device IRQ Names Supply Names Description
+------ --------- ------------ -----------
+regulators : None : None : Regulators
+
+Required child device properties:
+None.
+
+Example:
+ hi6421 {
+ compatible = "hisilicon,hi6421-pmic";
+ reg = <0xfcc00000 0x0180>; /* 0x60 << 2 */
+
+ regulators {
+ // supply for MLC NAND/ eMMC
+ hi6421_vout0_reg: hi6421_vout0 {
+ regulator-name = "VOUT0";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ // supply for 26M Oscillator
+ hi6421_vout1_reg: hi6421_vout1 {
+ regulator-name = "VOUT1";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/max14577.txt b/dts/Bindings/mfd/max14577.txt
new file mode 100644
index 0000000..236264c
--- /dev/null
+++ b/dts/Bindings/mfd/max14577.txt
@@ -0,0 +1,146 @@
+Maxim MAX14577/77836 Multi-Function Device
+
+MAX14577 is a Multi-Function Device with Micro-USB Interface Circuit, Li+
+Battery Charger and SFOUT LDO output for powering USB devices. It is
+interfaced to host controller using I2C.
+
+MAX77836 additionally contains PMIC (with two LDO regulators) and Fuel Gauge.
+
+
+Required properties:
+- compatible : Must be "maxim,max14577" or "maxim,max77836".
+- reg : I2C slave address for the max14577 chip (0x25 for max14577/max77836)
+- interrupts : IRQ line for the chip.
+- interrupt-parent : The parent interrupt controller.
+
+
+Required nodes:
+ - charger :
+ Node for configuring the charger driver.
+ Required properties:
+ - compatible : "maxim,max14577-charger"
+ or "maxim,max77836-charger"
+ - maxim,fast-charge-uamp : Current in uA for Fast Charge;
+ Valid values:
+ - for max14577: 90000 - 950000;
+ - for max77836: 45000 - 475000;
+ - maxim,eoc-uamp : Current in uA for End-Of-Charge mode;
+ Valid values:
+ - for max14577: 50000 - 200000;
+ - for max77836: 5000 - 100000;
+ - maxim,ovp-uvolt : OverVoltage Protection Threshold in uV;
+ In an overvoltage condition, INT asserts and charging
+ stops. Valid values:
+ - 6000000, 6500000, 7000000, 7500000;
+ - maxim,constant-uvolt : Battery Constant Voltage in uV;
+ Valid values:
+ - 4000000 - 4280000 (step by 20000);
+ - 4350000;
+
+
+Optional nodes:
+- max14577-muic/max77836-muic :
+ Node used only by extcon consumers.
+ Required properties:
+ - compatible : "maxim,max14577-muic" or "maxim,max77836-muic"
+
+- regulators :
+ Required properties:
+ - compatible : "maxim,max14577-regulator"
+ or "maxim,max77836-regulator"
+
+ May contain a sub-node per regulator from the list below. Each
+ sub-node should contain the constraints and initialization information
+ for that regulator. See regulator.txt for a description of standard
+ properties for these sub-nodes.
+
+ List of valid regulator names:
+ - for max14577: CHARGER, SAFEOUT.
+ - for max77836: CHARGER, SAFEOUT, LDO1, LDO2.
+
+ The SAFEOUT is a fixed voltage regulator so there is no need to specify
+ voltages for it.
+
+
+Example:
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+max14577@25 {
+ compatible = "maxim,max14577";
+ reg = <0x25>;
+ interrupt-parent = <&gpx1>;
+ interrupts = <5 IRQ_TYPE_NONE>;
+
+ muic: max14577-muic {
+ compatible = "maxim,max14577-muic";
+ };
+
+ regulators {
+ compatible = "maxim,max14577-regulator";
+
+ SAFEOUT {
+ regulator-name = "SAFEOUT";
+ };
+ CHARGER {
+ regulator-name = "CHARGER";
+ regulator-min-microamp = <90000>;
+ regulator-max-microamp = <950000>;
+ regulator-boot-on;
+ };
+ };
+
+ charger {
+ compatible = "maxim,max14577-charger";
+
+ maxim,constant-uvolt = <4350000>;
+ maxim,fast-charge-uamp = <450000>;
+ maxim,eoc-uamp = <50000>;
+ maxim,ovp-uvolt = <6500000>;
+ };
+};
+
+
+max77836@25 {
+ compatible = "maxim,max77836";
+ reg = <0x25>;
+ interrupt-parent = <&gpx1>;
+ interrupts = <5 IRQ_TYPE_NONE>;
+
+ muic: max77836-muic {
+ compatible = "maxim,max77836-muic";
+ };
+
+ regulators {
+ compatible = "maxim,max77836-regulator";
+
+ SAFEOUT {
+ regulator-name = "SAFEOUT";
+ };
+ CHARGER {
+ regulator-name = "CHARGER";
+ regulator-min-microamp = <90000>;
+ regulator-max-microamp = <950000>;
+ regulator-boot-on;
+ };
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+ LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3950000>;
+ };
+ };
+
+ charger {
+ compatible = "maxim,max77836-charger";
+
+ maxim,constant-uvolt = <4350000>;
+ maxim,fast-charge-uamp = <225000>;
+ maxim,eoc-uamp = <7500>;
+ maxim,ovp-uvolt = <6500000>;
+ };
+};
diff --git a/dts/Bindings/mfd/qcom,spmi-pmic.txt b/dts/Bindings/mfd/qcom,spmi-pmic.txt
new file mode 100644
index 0000000..7182b88
--- /dev/null
+++ b/dts/Bindings/mfd/qcom,spmi-pmic.txt
@@ -0,0 +1,64 @@
+ Qualcomm SPMI PMICs multi-function device bindings
+
+The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084
+PMICs. These PMICs use a QPNP scheme through SPMI interface.
+QPNP is effectively a partitioning scheme for dividing the SPMI extended
+register space up into logical pieces, and set of fixed register
+locations/definitions within these regions, with some of these regions
+specifically used for interrupt handling.
+
+The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are
+interfaced to the chip via the SPMI (System Power Management Interface) bus.
+Support for multiple independent functions are implemented by splitting the
+16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes
+each. A function can consume one or more of these fixed-size register regions.
+
+Required properties:
+- compatible: Should contain one of:
+ "qcom,pm8941"
+ "qcom,pm8841"
+ "qcom,pma8084"
+ or generalized "qcom,spmi-pmic".
+- reg: Specifies the SPMI USID slave address for this device.
+ For more information see:
+ Documentation/devicetree/bindings/spmi/spmi.txt
+
+Required properties for peripheral child nodes:
+- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name.
+
+Optional properties for peripheral child nodes:
+- interrupts: Interrupts are specified as a 4-tuple. For more information
+ see:
+ Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
+- interrupt-names: Corresponding interrupt name to the interrupts property
+
+Each child node of SPMI slave id represents a function of the PMIC. In the
+example below the rtc device node represents a peripheral of pm8941
+SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
+
+Example:
+
+ spmi {
+ compatible = "qcom,spmi-pmic-arb";
+
+ pm8941@0 {
+ compatible = "qcom,pm8941", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+
+ rtc {
+ compatible = "qcom,rtc";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "alarm";
+ };
+ };
+
+ pm8941@1 {
+ compatible = "qcom,pm8941", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+
+ regulator {
+ compatible = "qcom,regulator";
+ regulator-name = "8941_boost";
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/qcom,pm8xxx.txt b/dts/Bindings/mfd/qcom-pm8xxx.txt
index 03518dc..f24f334 100644
--- a/dts/Bindings/mfd/qcom,pm8xxx.txt
+++ b/dts/Bindings/mfd/qcom-pm8xxx.txt
@@ -61,6 +61,7 @@ The below bindings specify the set of valid subnodes.
Definition: must be one of:
"qcom,pm8058-rtc"
"qcom,pm8921-rtc"
+ "qcom,pm8941-rtc"
- reg:
Usage: required
diff --git a/dts/Bindings/mfd/rk808.txt b/dts/Bindings/mfd/rk808.txt
new file mode 100644
index 0000000..9e6e259
--- /dev/null
+++ b/dts/Bindings/mfd/rk808.txt
@@ -0,0 +1,177 @@
+RK808 Power Management Integrated Circuit
+
+Required properties:
+- compatible: "rockchip,rk808"
+- reg: I2C slave address
+- interrupt-parent: The parent interrupt controller.
+- interrupts: the interrupt outputs of the controller.
+- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
+ outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
+
+Optional properties:
+- clock-output-names: From common clock binding to override the
+ default output clock name
+- rockchip,system-power-controller: Telling whether or not this pmic is controlling
+ the system power.
+- vcc1-supply: The input supply for DCDC_REG1
+- vcc2-supply: The input supply for DCDC_REG2
+- vcc3-supply: The input supply for DCDC_REG3
+- vcc4-supply: The input supply for DCDC_REG4
+- vcc6-supply: The input supply for LDO_REG1 and LDO_REG2
+- vcc7-supply: The input supply for LDO_REG3 and LDO_REG7
+- vcc8-supply: The input supply for SWITCH_REG1
+- vcc9-supply: The input supply for LDO_REG4 and LDO_REG5
+- vcc10-supply: The input supply for LDO_REG6
+- vcc11-supply: The input supply for LDO_REG8
+- vcc12-supply: The input supply for SWITCH_REG2
+
+Regulators: All the regulators of RK808 to be instantiated shall be
+listed in a child node named 'regulators'. Each regulator is represented
+by a child node of the 'regulators' node.
+
+ regulator-name {
+ /* standard regulator bindings here */
+ };
+
+Following regulators of the RK808 PMIC block are supported. Note that
+the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
+number as described in RK808 datasheet.
+
+ - DCDC_REGn
+ - valid values for n are 1 to 4.
+ - LDO_REGn
+ - valid values for n are 1 to 8.
+ - SWITCH_REGn
+ - valid values for n are 1 to 2
+
+Standard regulator bindings are used inside regulator subnodes. Check
+ Documentation/devicetree/bindings/regulator/regulator.txt
+for more details
+
+Example:
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ clock-output-names = "xin32k", "rk808-clkout2";
+ interrupt-parent = <&gpio0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ reg = <0x1b>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ vcc8-supply = <&vcc_18>;
+ vcc9-supply = <&vcc_io>;
+ vcc10-supply = <&vcc_io>;
+ vcc12-supply = <&vcc_io>;
+ vddio-supply = <&vccio_pmu>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd_arm";
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd_gpu";
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ };
+
+ vccio_pmu: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_pmu";
+ };
+
+ vcc_tp: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_tp";
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ };
+
+ vcc18_lcd: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_lcd";
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ };
+
+ vcca_codec: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcca_codec";
+ };
+
+ vcc_wl: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_wl";
+ };
+
+ vcc_lcd: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_lcd";
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/rn5t618.txt b/dts/Bindings/mfd/rn5t618.txt
new file mode 100644
index 0000000..937785a
--- /dev/null
+++ b/dts/Bindings/mfd/rn5t618.txt
@@ -0,0 +1,36 @@
+* Ricoh RN5T618 PMIC
+
+Ricoh RN5T618 is a power management IC which integrates 3 step-down
+DCDC converters, 7 low-dropout regulators, a Li-ion battery charger,
+fuel gauge, ADC, GPIOs and a watchdog timer. It can be controlled
+through a I2C interface.
+
+Required properties:
+ - compatible: should be "ricoh,rn5t618"
+ - reg: the I2C slave address of the device
+
+Sub-nodes:
+ - regulators: the node is required if the regulator functionality is
+ needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, LDO1,
+ LDO2, LDO3, LDO4, LDO5, LDORTC1 and LDORTC2.
+ The common bindings for each individual regulator can be found in:
+ Documentation/devicetree/bindings/regulator/regulator.txt
+
+Example:
+
+ pmic@32 {
+ compatible = "ricoh,rn5t618";
+ reg = <0x32>;
+
+ regulators {
+ DCDC1 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ DCDC2 {
+ regulator-min-microvolt = <1175000>;
+ regulator-max-microvolt = <1175000>;
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/s2mps11.txt b/dts/Bindings/mfd/s2mps11.txt
index ba2d7f0..0e4026a 100644
--- a/dts/Bindings/mfd/s2mps11.txt
+++ b/dts/Bindings/mfd/s2mps11.txt
@@ -47,7 +47,7 @@ sub-node should be of the format as listed below.
regulator-ramp-delay for BUCKs = [6250/12500/25000(default)/50000] uV/us
- BUCK[2/3/4/6] supports disabling ramp delay on hardware, so explictly
+ BUCK[2/3/4/6] supports disabling ramp delay on hardware, so explicitly
regulator-ramp-delay = <0> can be used for them to disable ramp delay.
In the absence of the regulator-ramp-delay property, the default ramp
delay will be used.
diff --git a/dts/Bindings/mfd/stmpe.txt b/dts/Bindings/mfd/stmpe.txt
index 56edb55..3fb68bf 100644
--- a/dts/Bindings/mfd/stmpe.txt
+++ b/dts/Bindings/mfd/stmpe.txt
@@ -13,6 +13,7 @@ Optional properties:
- interrupt-parent : Specifies which IRQ controller we're connected to
- wakeup-source : Marks the input device as wakable
- st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
+ - irq-gpio : If present, which GPIO to use for event IRQ
Example:
diff --git a/dts/Bindings/mfd/twl4030-power.txt b/dts/Bindings/mfd/twl4030-power.txt
index b9ee7b9..3d19963 100644
--- a/dts/Bindings/mfd/twl4030-power.txt
+++ b/dts/Bindings/mfd/twl4030-power.txt
@@ -23,8 +23,13 @@ down during off-idle. Note that this does not work on all boards
depending on how the external oscillator is wired.
Optional properties:
-- ti,use_poweroff: With this flag, the chip will initiates an ACTIVE-to-OFF or
- SLEEP-to-OFF transition when the system poweroffs.
+
+- ti,system-power-controller: This indicates that TWL4030 is the
+ power supply master of the system. With this flag, the chip will
+ initiate an ACTIVE-to-OFF or SLEEP-to-OFF transition when the
+ system poweroffs.
+
+- ti,use_poweroff: Deprecated name for ti,system-power-controller
Example:
&i2c1 {
diff --git a/dts/Bindings/mmc/mmc.txt b/dts/Bindings/mmc/mmc.txt
index 431716e..b52628b 100644
--- a/dts/Bindings/mmc/mmc.txt
+++ b/dts/Bindings/mmc/mmc.txt
@@ -40,6 +40,8 @@ Optional properties:
- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
+- dsr: Value the card's (optional) Driver Stage Register (DSR) should be
+ programmed with. Valid range: [0 .. 0xffff].
*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
polarity properties, we have to fix the meaning of the "normal" and "inverted"
diff --git a/dts/Bindings/mmc/rockchip-dw-mshc.txt b/dts/Bindings/mmc/rockchip-dw-mshc.txt
index c559f3f..c327c2d 100644
--- a/dts/Bindings/mmc/rockchip-dw-mshc.txt
+++ b/dts/Bindings/mmc/rockchip-dw-mshc.txt
@@ -10,12 +10,14 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
Required Properties:
* compatible: should be
- - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following
+ - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
+ before RK3288
+ - "rockchip,rk3288-dw-mshc": for Rockchip RK3288
Example:
rkdwmmc0@12200000 {
- compatible = "rockchip,rk2928-dw-mshc";
+ compatible = "rockchip,rk3288-dw-mshc";
reg = <0x12200000 0x1000>;
interrupts = <0 75 0>;
#address-cells = <1>;
diff --git a/dts/Bindings/mmc/tmio_mmc.txt b/dts/Bindings/mmc/tmio_mmc.txt
index fa0f327..400b640 100644
--- a/dts/Bindings/mmc/tmio_mmc.txt
+++ b/dts/Bindings/mmc/tmio_mmc.txt
@@ -19,6 +19,9 @@ Required properties:
"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
"renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC
+ "renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC
+ "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC
+ "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
Optional properties:
- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
diff --git a/dts/Bindings/mtd/atmel-nand.txt b/dts/Bindings/mtd/atmel-nand.txt
index c472883..6edc3b6 100644
--- a/dts/Bindings/mtd/atmel-nand.txt
+++ b/dts/Bindings/mtd/atmel-nand.txt
@@ -36,6 +36,7 @@ Optional properties:
- reg : should specify the address and size used for NFC command registers,
NFC registers and NFC Sram. NFC Sram address and size can be absent
if don't want to use it.
+ - clocks: phandle to the peripheral clock
- Optional properties:
- atmel,write-by-sram: boolean to enable NFC write by sram.
@@ -98,6 +99,7 @@ nand0: nand@40000000 {
compatible = "atmel,sama5d3-nfc";
#address-cells = <1>;
#size-cells = <1>;
+ clocks = <&hsmc_clk>
reg = <
0x70000000 0x10000000 /* NFC Command Registers */
0xffffc000 0x00000070 /* NFC HSMC regs */
diff --git a/dts/Bindings/mtd/gpmc-nand.txt b/dts/Bindings/mtd/gpmc-nand.txt
index ee654e9..fb733c4 100644
--- a/dts/Bindings/mtd/gpmc-nand.txt
+++ b/dts/Bindings/mtd/gpmc-nand.txt
@@ -110,8 +110,8 @@ on various other factors also like;
Other factor which governs the selection of ecc-scheme is oob-size.
Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
so the device should have enough free bytes available its OOB/Spare
- area to accomodate ECC for entire page. In general following expression
- helps in determining if given device can accomodate ECC syndrome:
+ area to accommodate ECC for entire page. In general following expression
+ helps in determining if given device can accommodate ECC syndrome:
"2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE"
where
OOBSIZE number of bytes in OOB/spare area
@@ -133,5 +133,5 @@ on various other factors also like;
Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and
trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
- which can be accomodate in the OOB/Spare area of this device
+ which can be accommodated in the OOB/Spare area of this device
(OOBSIZE=128). So this device can use BCH16 ecc-scheme.
diff --git a/dts/Bindings/mtd/mtd-physmap.txt b/dts/Bindings/mtd/mtd-physmap.txt
index 61c5ec8..6b9f680 100644
--- a/dts/Bindings/mtd/mtd-physmap.txt
+++ b/dts/Bindings/mtd/mtd-physmap.txt
@@ -4,8 +4,8 @@ Flash chips (Memory Technology Devices) are often used for solid state
file systems on embedded devices.
- compatible : should contain the specific model of mtd chip(s)
- used, if known, followed by either "cfi-flash", "jedec-flash"
- or "mtd-ram".
+ used, if known, followed by either "cfi-flash", "jedec-flash",
+ "mtd-ram" or "mtd-rom".
- reg : Address range(s) of the mtd chip(s)
It's possible to (optionally) define multiple "reg" tuples so that
non-identical chips can be described in one node.
diff --git a/dts/Bindings/net/apm-xgene-enet.txt b/dts/Bindings/net/apm-xgene-enet.txt
index ebcad25..cfcc527 100644
--- a/dts/Bindings/net/apm-xgene-enet.txt
+++ b/dts/Bindings/net/apm-xgene-enet.txt
@@ -3,7 +3,7 @@ APM X-Gene SoC Ethernet nodes
Ethernet nodes are defined to describe on-chip ethernet interfaces in
APM X-Gene SoC.
-Required properties:
+Required properties for all the ethernet interfaces:
- compatible: Should be "apm,xgene-enet"
- reg: Address and length of the register set for the device. It contains the
information of registers in the same order as described by reg-names
@@ -15,6 +15,8 @@ Required properties:
- clocks: Reference to the clock entry.
- local-mac-address: MAC address assigned to this device
- phy-connection-type: Interface type between ethernet device and PHY device
+
+Required properties for ethernet interfaces that have external PHY:
- phy-handle: Reference to a PHY node connected to this device
- mdio: Device tree subnode with the following required properties:
diff --git a/dts/Bindings/net/broadcom-mdio-unimac.txt b/dts/Bindings/net/broadcom-mdio-unimac.txt
new file mode 100644
index 0000000..ab0bb42
--- /dev/null
+++ b/dts/Bindings/net/broadcom-mdio-unimac.txt
@@ -0,0 +1,39 @@
+* Broadcom UniMAC MDIO bus controller
+
+Required properties:
+- compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2",
+ "brcm,genet-mdio-v3", "brcm,genet-mdio-v4" or "brcm,unimac-mdio"
+- reg: address and length of the regsiter set for the device, first one is the
+ base register, and the second one is optional and for indirect accesses to
+ larger than 16-bits MDIO transactions
+- reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
+- #size-cells: must be 1
+- #address-cells: must be 0
+
+Optional properties:
+- interrupts: must be one if the interrupt is shared with the Ethernet MAC or
+ Ethernet switch this MDIO block is integrated from, or must be two, if there
+ are two separate interrupts, first one must be "mdio done" and second must be
+ for "mdio error"
+- interrupt-names: must be "mdio_done_error" when there is a share interrupt fed
+ to this hardware block, or must be "mdio_done" for the first interrupt and
+ "mdio_error" for the second when there are separate interrupts
+
+Child nodes of this MDIO bus controller node are standard Ethernet PHY device
+nodes as described in Documentation/devicetree/bindings/net/phy.txt
+
+Example:
+
+mdio@403c0 {
+ compatible = "brcm,unimac-mdio";
+ reg = <0x403c0 0x8 0x40300 0x18>;
+ reg-names = "mdio", "mdio_indir_rw";
+ #size-cells = <1>;
+ #address-cells = <0>;
+
+ ...
+ phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
diff --git a/dts/Bindings/net/broadcom-sf2.txt b/dts/Bindings/net/broadcom-sf2.txt
new file mode 100644
index 0000000..30d4875
--- /dev/null
+++ b/dts/Bindings/net/broadcom-sf2.txt
@@ -0,0 +1,78 @@
+* Broadcom Starfighter 2 integrated swich
+
+Required properties:
+
+- compatible: should be "brcm,bcm7445-switch-v4.0"
+- reg: addresses and length of the register sets for the device, must be 6
+ pairs of register addresses and lengths
+- interrupts: interrupts for the devices, must be two interrupts
+- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt
+- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt
+- #size-cells: must be 0
+- #address-cells: must be 2, see dsa/dsa.txt
+
+Subnodes:
+
+The integrated switch subnode should be specified according to the binding
+described in dsa/dsa.txt.
+
+Optional properties:
+
+- reg-names: litteral names for the device base register addresses, when present
+ must be: "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb"
+
+- interrupt-names: litternal names for the device interrupt lines, when present
+ must be: "switch_0" and "switch_1"
+
+- brcm,num-gphy: specify the maximum number of integrated gigabit PHYs in the
+ switch
+
+- brcm,num-rgmii-ports: specify the maximum number of RGMII interfaces supported
+ by the switch
+
+- brcm,fcb-pause-override: boolean property, if present indicates that the switch
+ supports Failover Control Block pause override capability
+
+- brcm,acb-packets-inflight: boolean property, if present indicates that the switch
+ Admission Control Block supports reporting the number of packets in-flight in a
+ switch queue
+
+Example:
+
+switch_top@f0b00000 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0 0xf0b00000 0x40804>;
+
+ ethernet_switch@0 {
+ compatible = "brcm,bcm7445-switch-v4.0";
+ #size-cells = <0>;
+ #address-cells = <2>;
+ reg = <0x0 0x40000
+ 0x40000 0x110
+ 0x40340 0x30
+ 0x40380 0x30
+ 0x40400 0x34
+ 0x40600 0x208>;
+ interrupts = <0 0x18 0
+ 0 0x19 0>;
+ brcm,num-gphy = <1>;
+ brcm,num-rgmii-ports = <2>;
+ brcm,fcb-pause-override;
+ brcm,acb-packets-inflight;
+
+ ...
+ switch@0 {
+ reg = <0 0>;
+ #size-cells = <0>;
+ #address-cells <1>;
+
+ port@0 {
+ label = "gphy";
+ reg = <0>;
+ };
+ ...
+ };
+ };
+};
diff --git a/dts/Bindings/net/can/m_can.txt b/dts/Bindings/net/can/m_can.txt
new file mode 100644
index 0000000..9e33177
--- /dev/null
+++ b/dts/Bindings/net/can/m_can.txt
@@ -0,0 +1,67 @@
+Bosch MCAN controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible : Should be "bosch,m_can" for M_CAN controllers
+- reg : physical base address and size of the M_CAN
+ registers map and Message RAM
+- reg-names : Should be "m_can" and "message_ram"
+- interrupts : Should be the interrupt number of M_CAN interrupt
+ line 0 and line 1, could be same if sharing
+ the same interrupt.
+- interrupt-names : Should contain "int0" and "int1"
+- clocks : Clocks used by controller, should be host clock
+ and CAN clock.
+- clock-names : Should contain "hclk" and "cclk"
+- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
+- pinctrl-names : Names corresponding to the numbered pinctrl states
+- bosch,mram-cfg : Message RAM configuration data.
+ Multiple M_CAN instances can share the same Message
+ RAM and each element(e.g Rx FIFO or Tx Buffer and etc)
+ number in Message RAM is also configurable,
+ so this property is telling driver how the shared or
+ private Message RAM are used by this M_CAN controller.
+
+ The format should be as follows:
+ <offset sidf_elems xidf_elems rxf0_elems rxf1_elems
+ rxb_elems txe_elems txb_elems>
+ The 'offset' is an address offset of the Message RAM
+ where the following elements start from. This is
+ usually set to 0x0 if you're using a private Message
+ RAM. The remain cells are used to specify how many
+ elements are used for each FIFO/Buffer.
+
+ M_CAN includes the following elements according to user manual:
+ 11-bit Filter 0-128 elements / 0-128 words
+ 29-bit Filter 0-64 elements / 0-128 words
+ Rx FIFO 0 0-64 elements / 0-1152 words
+ Rx FIFO 1 0-64 elements / 0-1152 words
+ Rx Buffers 0-64 elements / 0-1152 words
+ Tx Event FIFO 0-32 elements / 0-64 words
+ Tx Buffers 0-32 elements / 0-576 words
+
+ Please refer to 2.4.1 Message RAM Configuration in
+ Bosch M_CAN user manual for details.
+
+Example:
+SoC dtsi:
+m_can1: can@020e8000 {
+ compatible = "bosch,m_can";
+ reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <0 114 0x04>,
+ <0 114 0x04>;
+ interrupt-names = "int0", "int1";
+ clocks = <&clks IMX6SX_CLK_CANFD>,
+ <&clks IMX6SX_CLK_CANFD>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
+ status = "disabled";
+};
+
+Board dts:
+&m_can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_m_can1>;
+ status = "enabled";
+};
diff --git a/dts/Bindings/net/can/rcar_can.txt b/dts/Bindings/net/can/rcar_can.txt
new file mode 100644
index 0000000..002d844
--- /dev/null
+++ b/dts/Bindings/net/can/rcar_can.txt
@@ -0,0 +1,43 @@
+Renesas R-Car CAN controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible: "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
+ "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
+ "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
+ "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC.
+- reg: physical base address and size of the R-Car CAN register map.
+- interrupts: interrupt specifier for the sole interrupt.
+- clocks: phandles and clock specifiers for 3 CAN clock inputs.
+- clock-names: 3 clock input name strings: "clkp1", "clkp2", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Optional properties:
+- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
+ <0x0> (default) : Peripheral clock (clkp1)
+ <0x1> : Peripheral clock (clkp2)
+ <0x3> : Externally input clock
+
+Example
+-------
+
+SoC common .dtsi file:
+
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7791";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
+ <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ status = "disabled";
+ };
+
+Board specific .dts file:
+
+&can0 {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/dts/Bindings/net/cpsw.txt b/dts/Bindings/net/cpsw.txt
index ae2b8b7..33fe846 100644
--- a/dts/Bindings/net/cpsw.txt
+++ b/dts/Bindings/net/cpsw.txt
@@ -24,15 +24,17 @@ Optional properties:
- ti,hwmods : Must be "cpgmac0"
- no_bd_ram : Must be 0 or 1
- dual_emac : Specifies Switch to act as Dual EMAC
+- syscon : Phandle to the system control device node, which is
+ the control module device of the am33x
Slave Properties:
Required properties:
- phy_id : Specifies slave phy id
- phy-mode : See ethernet.txt file in the same directory
-- mac-address : See ethernet.txt file in the same directory
Optional properties:
- dual_emac_res_vlan : Specifies VID to be used to segregate the ports
+- mac-address : See ethernet.txt file in the same directory
Note: "ti,hwmods" field is used to fetch the base address and irq
resources from TI, omap hwmod data base during device registration.
@@ -57,6 +59,7 @@ Examples:
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
+ syscon = <&cm>;
cpsw_emac0: slave@0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
@@ -85,6 +88,7 @@ Examples:
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
+ syscon = <&cm>;
cpsw_emac0: slave@0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
diff --git a/dts/Bindings/net/dsa/dsa.txt b/dts/Bindings/net/dsa/dsa.txt
index 49f4f7a..a62c889 100644
--- a/dts/Bindings/net/dsa/dsa.txt
+++ b/dts/Bindings/net/dsa/dsa.txt
@@ -39,6 +39,22 @@ Optionnal property:
This property is only used when switches are being
chained/cascaded together.
+- phy-handle : Phandle to a PHY on an external MDIO bus, not the
+ switch internal one. See
+ Documentation/devicetree/bindings/net/ethernet.txt
+ for details.
+
+- phy-mode : String representing the connection to the designated
+ PHY node specified by the 'phy-handle' property. See
+ Documentation/devicetree/bindings/net/ethernet.txt
+ for details.
+
+Optional subnodes:
+- fixed-link : Fixed-link subnode describing a link to a non-MDIO
+ managed entity. See
+ Documentation/devicetree/bindings/net/fixed-link.txt
+ for details.
+
Example:
dsa@0 {
@@ -58,6 +74,7 @@ Example:
port@0 {
reg = <0>;
label = "lan1";
+ phy-handle = <&phy0>;
};
port@1 {
diff --git a/dts/Bindings/net/emac_rockchip.txt b/dts/Bindings/net/emac_rockchip.txt
new file mode 100644
index 0000000..8dc1c79
--- /dev/null
+++ b/dts/Bindings/net/emac_rockchip.txt
@@ -0,0 +1,50 @@
+* ARC EMAC 10/100 Ethernet platform driver for Rockchip Rk3066/RK3188 SoCs
+
+Required properties:
+- compatible: Should be "rockchip,rk3066-emac" or "rockchip,rk3188-emac"
+ according to the target SoC.
+- reg: Address and length of the register set for the device
+- interrupts: Should contain the EMAC interrupts
+- rockchip,grf: phandle to the syscon grf used to control speed and mode
+ for emac.
+- phy: see ethernet.txt file in the same directory.
+- phy-mode: see ethernet.txt file in the same directory.
+
+Optional properties:
+- phy-supply: phandle to a regulator if the PHY needs one
+
+Clock handling:
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Shall be "hclk" for the host clock needed to calculate and set
+ polling period of EMAC and "macref" for the reference clock needed to transfer
+ data to and from the phy.
+
+Child nodes of the driver are the individual PHY devices connected to the
+MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
+
+Examples:
+
+ethernet@10204000 {
+ compatible = "rockchip,rk3188-emac";
+ reg = <0xc0fc2000 0x3c>;
+ interrupts = <6>;
+ mac-address = [ 00 11 22 33 44 55 ];
+
+ clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
+ clock-names = "hclk", "macref";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+
+ rockchip,grf = <&grf>;
+
+ phy = <&phy0>;
+ phy-mode = "rmii";
+ phy-supply = <&vcc_rmii>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
diff --git a/dts/Bindings/net/fsl-fec.txt b/dts/Bindings/net/fsl-fec.txt
index 8a2c7b5..0c8775c 100644
--- a/dts/Bindings/net/fsl-fec.txt
+++ b/dts/Bindings/net/fsl-fec.txt
@@ -16,6 +16,12 @@ Optional properties:
- phy-handle : phandle to the PHY device connected to this device.
- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
Use instead of phy-handle.
+- fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
+ hw multi queues. Should specify the tx queue number, otherwise set tx queue
+ number to 1.
+- fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
+ hw multi queues. Should specify the rx queue number, otherwise set rx queue
+ number to 1.
Optional subnodes:
- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
diff --git a/dts/Bindings/net/marvell-pxa168.txt b/dts/Bindings/net/marvell-pxa168.txt
new file mode 100644
index 0000000..845a148
--- /dev/null
+++ b/dts/Bindings/net/marvell-pxa168.txt
@@ -0,0 +1,36 @@
+* Marvell PXA168 Ethernet Controller
+
+Required properties:
+- compatible: should be "marvell,pxa168-eth".
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device.
+- clocks: pointer to the clock for the device.
+
+Optional properties:
+- port-id: Ethernet port number. Should be '0','1' or '2'.
+- #address-cells: must be 1 when using sub-nodes.
+- #size-cells: must be 0 when using sub-nodes.
+- phy-handle: see ethernet.txt file in the same directory.
+- local-mac-address: see ethernet.txt file in the same directory.
+
+Sub-nodes:
+Each PHY can be represented as a sub-node. This is not mandatory.
+
+Sub-nodes required properties:
+- reg: the MDIO address of the PHY.
+
+Example:
+
+ eth0: ethernet@f7b90000 {
+ compatible = "marvell,pxa168-eth";
+ reg = <0xf7b90000 0x10000>;
+ clocks = <&chip CLKID_GETH0>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <&ethphy0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
diff --git a/dts/Bindings/net/meson-dwmac.txt b/dts/Bindings/net/meson-dwmac.txt
new file mode 100644
index 0000000..ec633d7
--- /dev/null
+++ b/dts/Bindings/net/meson-dwmac.txt
@@ -0,0 +1,25 @@
+* Amlogic Meson DWMAC Ethernet controller
+
+The device inherits all the properties of the dwmac/stmmac devices
+described in the file net/stmmac.txt with the following changes.
+
+Required properties:
+
+- compatible: should be "amlogic,meson6-dwmac" along with "snps,dwmac"
+ and any applicable more detailed version number
+ described in net/stmmac.txt
+
+- reg: should contain a register range for the dwmac controller and
+ another one for the Amlogic specific configuration
+
+Example:
+
+ ethmac: ethernet@c9410000 {
+ compatible = "amlogic,meson6-dwmac", "snps,dwmac";
+ reg = <0xc9410000 0x10000
+ 0xc1108108 0x4>;
+ interrupts = <0 8 1>;
+ interrupt-names = "macirq";
+ clocks = <&clk81>;
+ clock-names = "stmmaceth";
+ }
diff --git a/dts/Bindings/net/micrel.txt b/dts/Bindings/net/micrel.txt
index 98a3e61..e1d99b9 100644
--- a/dts/Bindings/net/micrel.txt
+++ b/dts/Bindings/net/micrel.txt
@@ -16,3 +16,9 @@ Optional properties:
KSZ8051: register 0x1f, bits 5..4
See the respective PHY datasheet for the mode values.
+
+ - clocks, clock-names: contains clocks according to the common clock bindings.
+
+ supported clocks:
+ - KSZ8021, KSZ8031: "rmii-ref": The RMII refence input clock. Used
+ to determine the XI input clock.
diff --git a/dts/Bindings/net/nfc/st21nfcb.txt b/dts/Bindings/net/nfc/st21nfcb.txt
index 3b58ae4..9005608 100644
--- a/dts/Bindings/net/nfc/st21nfcb.txt
+++ b/dts/Bindings/net/nfc/st21nfcb.txt
@@ -26,7 +26,7 @@ Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2):
clock-frequency = <400000>;
interrupt-parent = <&gpio5>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/Bindings/net/nfc/trf7970a.txt b/dts/Bindings/net/nfc/trf7970a.txt
index 1e43613..7c89ca2 100644
--- a/dts/Bindings/net/nfc/trf7970a.txt
+++ b/dts/Bindings/net/nfc/trf7970a.txt
@@ -13,6 +13,11 @@ Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
- autosuspend-delay: Specify autosuspend delay in milliseconds.
+- vin-voltage-override: Specify voltage of VIN pin in microvolts.
+- irq-status-read-quirk: Specify that the trf7970a being used has the
+ "IRQ Status Read" erratum.
+- en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF"
+ erratum.
Example (for ARM-based BeagleBone with TRF7970A on SPI1):
@@ -30,7 +35,10 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1):
ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>,
<&gpio2 5 GPIO_ACTIVE_LOW>;
vin-supply = <&ldo3_reg>;
+ vin-voltage-override = <5000000>;
autosuspend-delay = <30000>;
+ irq-status-read-quirk;
+ en2-rf-quirk;
status = "okay";
};
};
diff --git a/dts/Bindings/net/qca-qca7000-spi.txt b/dts/Bindings/net/qca-qca7000-spi.txt
new file mode 100644
index 0000000..c74989c
--- /dev/null
+++ b/dts/Bindings/net/qca-qca7000-spi.txt
@@ -0,0 +1,47 @@
+* Qualcomm QCA7000 (Ethernet over SPI protocol)
+
+Note: The QCA7000 is useable as a SPI device. In this case it must be defined
+as a child of a SPI master in the device tree.
+
+Required properties:
+- compatible : Should be "qca,qca7000"
+- reg : Should specify the SPI chip select
+- interrupts : The first cell should specify the index of the source interrupt
+ and the second cell should specify the trigger type as rising edge
+- spi-cpha : Must be set
+- spi-cpol: Must be set
+
+Optional properties:
+- interrupt-parent : Specify the pHandle of the source interrupt
+- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at.
+ Numbers smaller than 1000000 or greater than 16000000 are invalid. Missing
+ the property will set the SPI frequency to 8000000 Hertz.
+- local-mac-address: 6 bytes, MAC address
+- qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode.
+ In this mode the SPI master must toggle the chip select between each data
+ word. In burst mode these gaps aren't necessary, which is faster.
+ This setting depends on how the QCA7000 is setup via GPIO pin strapping.
+ If the property is missing the driver defaults to burst mode.
+
+Example:
+
+/* Freescale i.MX28 SPI master*/
+ssp2: spi@80014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+
+ qca7000: ethernet@0 {
+ compatible = "qca,qca7000";
+ reg = <0x0>;
+ interrupt-parent = <&gpio3>; /* GPIO Bank 3 */
+ interrupts = <25 0x1>; /* Index: 25, rising edge */
+ spi-cpha; /* SPI mode: CPHA=1 */
+ spi-cpol; /* SPI mode: CPOL=1 */
+ spi-max-frequency = <8000000>; /* freq: 8 MHz */
+ local-mac-address = [ A0 B0 C0 D0 E0 F0 ];
+ };
+};
diff --git a/dts/Bindings/net/samsung-sxgbe.txt b/dts/Bindings/net/samsung-sxgbe.txt
index 989f6c9..888c250 100644
--- a/dts/Bindings/net/samsung-sxgbe.txt
+++ b/dts/Bindings/net/samsung-sxgbe.txt
@@ -17,7 +17,7 @@ Required properties:
- samsung,pbl: Integer, Programmable Burst Length.
Supported values are 1, 2, 4, 8, 16, or 32.
- samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
- This is an interger and represents allowable DMA bursts when fixed burst.
+ This is an integer and represents allowable DMA bursts when fixed burst.
Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled.
When fixed length is needed for burst mode, it can be set within allowable
range.
diff --git a/dts/Bindings/net/socfpga-dwmac.txt b/dts/Bindings/net/socfpga-dwmac.txt
index 2a60cd3..3a9d679 100644
--- a/dts/Bindings/net/socfpga-dwmac.txt
+++ b/dts/Bindings/net/socfpga-dwmac.txt
@@ -12,6 +12,10 @@ Required properties:
- altr,sysmgr-syscon : Should be the phandle to the system manager node that
encompasses the glue register, the register offset, and the register shift.
+Optional properties:
+altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
+ DWMAC controller is connected emac splitter.
+
Example:
gmac0: ethernet@ff700000 {
diff --git a/dts/Bindings/net/sti-dwmac.txt b/dts/Bindings/net/sti-dwmac.txt
index 3dd3d0b..6762a6b 100644
--- a/dts/Bindings/net/sti-dwmac.txt
+++ b/dts/Bindings/net/sti-dwmac.txt
@@ -1,58 +1,65 @@
STMicroelectronics SoC DWMAC glue layer controller
+This file documents differences between the core properties in
+Documentation/devicetree/bindings/net/stmmac.txt
+and what is needed on STi platforms to program the stmmac glue logic.
+
The device node has following properties.
Required properties:
- - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
- "st,stid127-dwmac".
- - reg : Offset of the glue configuration register map in system
+ - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
+ "st,stih407-dwmac", "st,stid127-dwmac".
+ - reg : Offset of the glue configuration register map in system
configuration regmap pointed by st,syscon property and size.
-
- - reg-names : Should be "sti-ethconf".
-
- - st,syscon : Should be phandle to system configuration node which
+ - st,syscon : Should be phandle to system configuration node which
encompases this glue registers.
+ - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
+ register available on STiH407 SoC.
+ - sti-ethconf: this is the gmac glue logic register to enable the GMAC,
+ select among the different modes and program the clk retiming.
+ - pinctrl-0: pin-control for all the MII mode supported.
- - st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
- wired up in from different sources. One via TXCLK pin and other via CLK_125
- pin. This wiring is totally board dependent. However the retiming glue
- logic should be configured accordingly. Possible values for this property
-
- "txclk" - if 125Mhz clock is wired up via txclk line.
- "clk_125" - if 125Mhz clock is wired up via clk_125 line.
-
- This property is only valid for Giga bit setup( GMII, RGMII), and it is
- un-used for non-giga bit (MII and RMII) setups. Also note that internal
- clockgen can not generate stable 125Mhz clock.
-
- - st,ext-phyclk: This boolean property indicates who is generating the clock
- for tx and rx. This property is only valid for RMII case where the clock can
- be generated from the MAC or PHY.
-
- - clock-names: should be "sti-ethclk".
- - clocks: Should point to ethernet clockgen which can generate phyclk.
-
+Optional properties:
+ - resets : phandle pointing to the system reset controller with correct
+ reset line index for ethernet reset.
+ - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
+ MAC can generate it.
+ - st,tx-retime-src: This specifies which clk is wired up to the mac for
+ retimeing tx lines. This is totally board dependent and can take one of the
+ posssible values from "txclk", "clk_125" or "clkgen".
+ If not passed, the internal clock will be used by default.
+ - sti-ethclk: this is the phy clock.
+ - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
+ to program the clk retiming.
+ - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
+ STiH407.
Example:
-ethernet0: dwmac@fe810000 {
- device_type = "network";
- compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
- reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
- reg-names = "stmmaceth", "sti-ethconf";
- interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
- interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
- phy-mode = "mii";
+ethernet0: dwmac@9630000 {
+ device_type = "network";
+ status = "disabled";
+ compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+ reg = <0x9630000 0x8000>, <0x80 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
- st,syscon = <&syscfg_rear>;
+ st,syscon = <&syscfg_sbc_reg>;
+ st,gmac_en;
+ resets = <&softreset STIH407_ETH1_SOFTRESET>;
+ reset-names = "stmmaceth";
- snps,pbl = <32>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
+ <GIC_SPI 99 IRQ_TYPE_NONE>,
+ <GIC_SPI 100 IRQ_TYPE_NONE>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
snps,mixed-burst;
- resets = <&softreset STIH416_ETH0_SOFTRESET>;
- reset-names = "stmmaceth";
- pinctrl-0 = <&pinctrl_mii0>;
- pinctrl-names = "default";
- clocks = <&CLK_S_GMAC0_PHY>;
- clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1>;
+
+ clock-names = "stmmaceth", "sti-ethclk";
+ clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>,
+ <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>;
};
diff --git a/dts/Bindings/net/stmmac.txt b/dts/Bindings/net/stmmac.txt
index e45ac3f..c41afd9 100644
--- a/dts/Bindings/net/stmmac.txt
+++ b/dts/Bindings/net/stmmac.txt
@@ -58,5 +58,5 @@ Examples:
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
clocks = <&clock>;
- clock-names = "stmmaceth">;
+ clock-names = "stmmaceth";
};
diff --git a/dts/Bindings/panel/auo,b101xtn01.txt b/dts/Bindings/panel/auo,b101xtn01.txt
new file mode 100644
index 0000000..889d511
--- /dev/null
+++ b/dts/Bindings/panel/auo,b101xtn01.txt
@@ -0,0 +1,7 @@
+AU Optronics Corporation 10.1" WXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,b101xtn01"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/pci/designware-pcie.txt b/dts/Bindings/pci/designware-pcie.txt
index ed0d9b9..9f4faa8 100644
--- a/dts/Bindings/pci/designware-pcie.txt
+++ b/dts/Bindings/pci/designware-pcie.txt
@@ -23,3 +23,6 @@ Required properties:
Optional properties:
- reset-gpio: gpio pin number of power good signal
+- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
+ specify this property, to keep backwards compatibility a range of 0x00-0xff
+ is assumed if not present)
diff --git a/dts/Bindings/pci/fsl,imx6q-pcie.txt b/dts/Bindings/pci/fsl,imx6q-pcie.txt
index 9455fd0..6fbba53 100644
--- a/dts/Bindings/pci/fsl,imx6q-pcie.txt
+++ b/dts/Bindings/pci/fsl,imx6q-pcie.txt
@@ -17,7 +17,9 @@ Example:
pcie@0x01000000 {
compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
- reg = <0x01ffc000 0x4000>;
+ reg = <0x01ffc000 0x04000>,
+ <0x01f00000 0x80000>;
+ reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
diff --git a/dts/Bindings/pci/fsl,pci.txt b/dts/Bindings/pci/fsl,pci.txt
new file mode 100644
index 0000000..d8ac4a7
--- /dev/null
+++ b/dts/Bindings/pci/fsl,pci.txt
@@ -0,0 +1,27 @@
+* Bus Enumeration by Freescale PCI-X Agent
+
+Typically any Freescale PCI-X bridge hardware strapped into Agent mode
+is prevented from enumerating the bus. The PrPMC form-factor requires
+all mezzanines to be PCI-X Agents, but one per system may still
+enumerate the bus.
+
+The property defined below will allow a PCI-X bridge to be used for bus
+enumeration despite being strapped into Agent mode.
+
+Required properties:
+- fsl,pci-agent-force-enum : There is no value associated with this
+ property. The property itself is treated as a boolean.
+
+Example:
+
+ /* PCI-X bridge known to be PrPMC Monarch */
+ pci0: pci@ef008000 {
+ fsl,pci-agent-force-enum;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
+ ...
+ ...
+ };
diff --git a/dts/Bindings/pci/host-generic-pci.txt b/dts/Bindings/pci/host-generic-pci.txt
index f0b0436..cf3e205 100644
--- a/dts/Bindings/pci/host-generic-pci.txt
+++ b/dts/Bindings/pci/host-generic-pci.txt
@@ -55,7 +55,7 @@ For CAM, this 24-bit offset is:
cfg_offset(bus, device, function, register) =
bus << 16 | device << 11 | function << 8 | register
-Whilst ECAM extends this by 4 bits to accomodate 4k of function space:
+Whilst ECAM extends this by 4 bits to accommodate 4k of function space:
cfg_offset(bus, device, function, register) =
bus << 20 | device << 15 | function << 12 | register
diff --git a/dts/Bindings/pci/nvidia,tegra20-pcie.txt b/dts/Bindings/pci/nvidia,tegra20-pcie.txt
index 0823362..d763e04 100644
--- a/dts/Bindings/pci/nvidia,tegra20-pcie.txt
+++ b/dts/Bindings/pci/nvidia,tegra20-pcie.txt
@@ -1,7 +1,10 @@
NVIDIA Tegra PCIe controller
Required properties:
-- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
+- compatible: Must be one of:
+ - "nvidia,tegra20-pcie"
+ - "nvidia,tegra30-pcie"
+ - "nvidia,tegra124-pcie"
- device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller
registers. Must contain an entry for each entry in the reg-names property.
@@ -57,6 +60,11 @@ Required properties:
- afi
- pcie_x
+Required properties on Tegra124 and later:
+- phys: Must contain an entry for each entry in phy-names.
+- phy-names: Must include the following entries:
+ - pcie
+
Power supplies for Tegra20:
- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
@@ -84,6 +92,21 @@ Power supplies for Tegra30:
- avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
+Power supplies for Tegra124:
+- Required:
+ - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
+ - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
+ - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
+ supply 1.05 V.
+ - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
+ Must supply 3.3 V.
+ - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
+ Must supply 3.3 V.
+ - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
+ supply 2.8-3.3 V.
+ - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
+ supply 1.05 V.
+
Root ports are defined as subnodes of the PCIe controller node.
Required properties:
diff --git a/dts/Bindings/pci/pci-keystone.txt b/dts/Bindings/pci/pci-keystone.txt
new file mode 100644
index 0000000..54eae29
--- /dev/null
+++ b/dts/Bindings/pci/pci-keystone.txt
@@ -0,0 +1,63 @@
+TI Keystone PCIe interface
+
+Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
+It shares common functions with PCIe Designware core driver and inherit
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt
+
+Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
+for the details of Designware DT bindings. Additional properties are
+described here as well as properties that are not applicable.
+
+Required Properties:-
+
+compatibility: "ti,keystone-pcie"
+reg: index 1 is the base address and length of DW application registers.
+ index 2 is the base address and length of PCI device ID register.
+
+pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
+ interrupt-cells: should be set to 1
+ interrupt-parent: Parent interrupt controller phandle
+ interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
+
+ Example:
+ pcie_msi_intc: msi-interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
+ };
+
+pcie_intc: Interrupt controller device node for Legacy IRQ chip
+ interrupt-cells: should be set to 1
+ interrupt-parent: Parent interrupt controller phandle
+ interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
+
+ Example:
+ pcie_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
+ };
+
+Optional properties:-
+ phys: phandle to Generic Keystone SerDes phy for PCI
+ phy-names: name of the Generic Keystine SerDes phy for PCI
+ - If boot loader already does PCI link establishment, then phys and
+ phy-names shouldn't be present.
+
+Designware DT Properties not applicable for Keystone PCI
+
+1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
+
diff --git a/dts/Bindings/pci/xgene-pci.txt b/dts/Bindings/pci/xgene-pci.txt
new file mode 100644
index 0000000..1070b06
--- /dev/null
+++ b/dts/Bindings/pci/xgene-pci.txt
@@ -0,0 +1,57 @@
+* AppliedMicro X-Gene PCIe interface
+
+Required properties:
+- device_type: set to "pci"
+- compatible: should contain "apm,xgene-pcie" to identify the core.
+- reg: A list of physical base address and length for each set of controller
+ registers. Must contain an entry for each entry in the reg-names
+ property.
+- reg-names: Must include the following entries:
+ "csr": controller configuration registers.
+ "cfg": pcie configuration space registers.
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- ranges: ranges for the outbound memory, I/O regions.
+- dma-ranges: ranges for the inbound memory regions.
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map: standard PCI properties
+ to define the mapping of the PCIe interface to interrupt
+ numbers.
+- clocks: from common clock binding: handle to pci clock.
+
+Optional properties:
+- status: Either "ok" or "disabled".
+- dma-coherent: Present if dma operations are coherent
+
+Example:
+
+SoC specific DT Entry:
+
+ pcie0: pcie@1f2b0000 {
+ status = "disabled";
+ device_type = "pci";
+ compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
+ 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+ reg-names = "csr", "cfg";
+ ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
+ 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
+ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
+ 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
+ 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
+ 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
+ dma-coherent;
+ clocks = <&pcie0clk 0>;
+ };
+
+
+Board specific DT Entry:
+ &pcie0 {
+ status = "ok";
+ };
diff --git a/dts/Bindings/pci/xilinx-pcie.txt b/dts/Bindings/pci/xilinx-pcie.txt
new file mode 100644
index 0000000..3e2c88d
--- /dev/null
+++ b/dts/Bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be "pci"
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
++++++++++++++++++++++++++++++++
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+++++++++
+
+ pci_express: axi-pcie@50000000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ reg = < 0x50000000 0x10000000 >;
+ device_type = "pci";
+ interrupts = < 0 52 4 >;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 1>,
+ <0 0 0 2 &pcie_intc 2>,
+ <0 0 0 3 &pcie_intc 3>,
+ <0 0 0 4 &pcie_intc 4>;
+ ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ }
+ };
diff --git a/dts/Bindings/phy/phy-bindings.txt b/dts/Bindings/phy/phy-bindings.txt
index 2aa1840..1293c32 100644
--- a/dts/Bindings/phy/phy-bindings.txt
+++ b/dts/Bindings/phy/phy-bindings.txt
@@ -27,7 +27,7 @@ phys: phy {
};
That node describes an IP block (PHY provider) that implements 2 different PHYs.
-In order to differentiate between these 2 PHYs, an additonal specifier should be
+In order to differentiate between these 2 PHYs, an additional specifier should be
given while trying to get a reference to it.
PHY user node
diff --git a/dts/Bindings/phy/phy-stih407-usb.txt b/dts/Bindings/phy/phy-stih407-usb.txt
new file mode 100644
index 0000000..1ef8228
--- /dev/null
+++ b/dts/Bindings/phy/phy-stih407-usb.txt
@@ -0,0 +1,30 @@
+ST STiH407 USB PHY controller
+
+This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and USB3
+host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC family from STMicroelectronics.
+
+Required properties:
+- compatible : should be "st,stih407-usb2-phy"
+- reg : contain the offset and length of the system configuration registers
+ used as glue logic to control & parameter phy
+- reg-names : the names of the system configuration registers in "reg", should be "param" and "reg"
+- st,syscfg : sysconfig register to manage phy parameter at driver level
+- resets : list of phandle and reset specifier pairs. There should be two entries, one
+ for the whole phy and one for the port
+- reset-names : list of reset signal names. Should be "global" and "port"
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+
+Example:
+
+usb2_picophy0: usbpicophy@f8 {
+ compatible = "st,stih407-usb2-phy";
+ reg = <0xf8 0x04>, /* syscfg 5062 */
+ <0xf4 0x04>; /* syscfg 5061 */
+ reg-names = "param", "ctrl";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY0_RESET>;
+ reset-names = "global", "port";
+};
diff --git a/dts/Bindings/phy/phy-stih41x-usb.txt b/dts/Bindings/phy/phy-stih41x-usb.txt
new file mode 100644
index 0000000..00944a0
--- /dev/null
+++ b/dts/Bindings/phy/phy-stih41x-usb.txt
@@ -0,0 +1,24 @@
+STMicroelectronics STiH41x USB PHY binding
+------------------------------------------
+
+This file contains documentation for the usb phy found in STiH415/6 SoCs from
+STMicroelectronics.
+
+Required properties:
+- compatible : should be "st,stih416-usb-phy" or "st,stih415-usb-phy"
+- st,syscfg : should be a phandle of the syscfg node
+- clock-names : must contain "osc_phy"
+- clocks : must contain an entry for each name in clock-names.
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- #phy-cells : must be 0 for this phy
+See: Documentation/devicetree/bindings/phy/phy-bindings.txt
+
+Example:
+
+usb2_phy: usb2phy@0 {
+ compatible = "st,stih416-usb-phy";
+ #phy-cell = <0>;
+ st,syscfg = <&syscfg_rear>;
+ clocks = <&clk_sysin>;
+ clock-names = "osc_phy";
+};
diff --git a/dts/Bindings/phy/qcom-dwc3-usb-phy.txt b/dts/Bindings/phy/qcom-dwc3-usb-phy.txt
new file mode 100644
index 0000000..86f2dbe
--- /dev/null
+++ b/dts/Bindings/phy/qcom-dwc3-usb-phy.txt
@@ -0,0 +1,39 @@
+Qualcomm DWC3 HS AND SS PHY CONTROLLER
+--------------------------------------
+
+DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
+controllers. Each DWC3 PHY controller should have its own node.
+
+Required properties:
+- compatible: should contain one of the following:
+ - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
+ - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
+- reg: offset and length of the DWC3 PHY controller register set
+- #phy-cells: must be zero
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+ clock-names.
+- clock-names: Should contain "ref" for the PHY reference clock
+
+Optional clocks:
+ "xo" External reference clock
+
+Example:
+ phy@100f8800 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
+
+ phy@100f8830 {
+ compatible = "qcom,dwc3-ss-usb-phy";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
diff --git a/dts/Bindings/phy/rcar-gen2-phy.txt b/dts/Bindings/phy/rcar-gen2-phy.txt
new file mode 100644
index 0000000..00fc52a
--- /dev/null
+++ b/dts/Bindings/phy/rcar-gen2-phy.txt
@@ -0,0 +1,51 @@
+* Renesas R-Car generation 2 USB PHY
+
+This file provides information on what the device node for the R-Car generation
+2 USB PHY contains.
+
+Required properties:
+- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
+ "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
+- reg: offset and length of the register block.
+- #address-cells: number of address cells for the USB channel subnodes, must
+ be <1>.
+- #size-cells: number of size cells for the USB channel subnodes, must be <0>.
+- clocks: clock phandle and specifier pair.
+- clock-names: string, clock input name, must be "usbhs".
+
+The USB PHY device tree node should have the subnodes corresponding to the USB
+channels. These subnodes must contain the following properties:
+- reg: the USB controller selector; see the table below for the values.
+- #phy-cells: see phy-bindings.txt in the same directory, must be <1>.
+
+The phandle's argument in the PHY specifier is the USB controller selector for
+the USB channel; see the selector meanings below:
+
++-----------+---------------+---------------+
+|\ Selector | | |
++ --------- + 0 | 1 |
+| Channel \| | |
++-----------+---------------+---------------+
+| 0 | PCI EHCI/OHCI | HS-USB |
+| 2 | PCI EHCI/OHCI | xHCI |
++-----------+---------------+---------------+
+
+Example (Lager board):
+
+ usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7790";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+ clock-names = "usbhs";
+
+ usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/phy/samsung-phy.txt b/dts/Bindings/phy/samsung-phy.txt
index 7a6feea..15e0f2c 100644
--- a/dts/Bindings/phy/samsung-phy.txt
+++ b/dts/Bindings/phy/samsung-phy.txt
@@ -17,8 +17,11 @@ Samsung EXYNOS SoC series Display Port PHY
-------------------------------------------------
Required properties:
-- compatible : should be "samsung,exynos5250-dp-video-phy";
-- reg : offset and length of the Display Port PHY register set;
+- compatible : should be one of the following supported values:
+ - "samsung,exynos5250-dp-video-phy"
+ - "samsung,exynos5420-dp-video-phy"
+- samsung,pmu-syscon: phandle for PMU system controller interface, used to
+ control pmu registers for power isolation.
- #phy-cells : from the generic PHY bindings, must be 0;
Samsung S5P/EXYNOS SoC series USB PHY
diff --git a/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt b/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt
index 02ab5ab..b7a93e8 100644
--- a/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -19,6 +19,7 @@ such as pull-up, multi drive, etc.
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
+ or "atmel,sama5d3-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
@@ -85,13 +86,20 @@ Required properties for pin configuration node:
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
Bits used for CONFIG:
-PULL_UP (1 << 0): indicate this pin need a pull up.
-MULTIDRIVE (1 << 1): indicate this pin need to be configured as multidrive.
-DEGLITCH (1 << 2): indicate this pin need deglitch.
-PULL_DOWN (1 << 3): indicate this pin need a pull down.
-DIS_SCHMIT (1 << 4): indicate this pin need to disable schmit trigger.
-DEBOUNCE (1 << 16): indicate this pin need debounce.
-DEBOUNCE_VAL (0x3fff << 17): debounce val.
+PULL_UP (1 << 0): indicate this pin needs a pull up.
+MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
+ Multi-drive is equivalent to open-drain type output.
+DEGLITCH (1 << 2): indicate this pin needs deglitch.
+PULL_DOWN (1 << 3): indicate this pin needs a pull down.
+DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger.
+DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
+ following values:
+ 00 - No change (reset state value kept)
+ 01 - Low
+ 10 - Medium
+ 11 - High
+DEBOUNCE (1 << 16): indicate this pin needs debounce.
+DEBOUNCE_VAL (0x3fff << 17): debounce value.
NOTE:
Some requirements for using atmel,at91rm9200-pinctrl binding:
diff --git a/dts/Bindings/pinctrl/nvidia,tegra124-pinmux.txt b/dts/Bindings/pinctrl/nvidia,tegra124-pinmux.txt
index 6464bf7..189814e 100644
--- a/dts/Bindings/pinctrl/nvidia,tegra124-pinmux.txt
+++ b/dts/Bindings/pinctrl/nvidia,tegra124-pinmux.txt
@@ -10,6 +10,7 @@ Required properties:
- reg: Should contain a list of base address and size pairs for:
-- first entry - the drive strength and pad control registers.
-- second entry - the pinmux registers
+ -- third entry - the MIPI_PAD_CTRL register
Tegra124 adds the following optional properties for pin configuration subnodes.
The macros for options are defined in the
@@ -91,6 +92,12 @@ Valid values for pin and group names are:
dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
+ MIPI pad control groups:
+
+ These support only the nvidia,function property.
+
+ dsi_b
+
Valid values for nvidia,functions are:
blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
@@ -101,14 +108,15 @@ Valid values for nvidia,functions are:
sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
- dp, rtck, sys, clk tmds.
+ dp, rtck, sys, clk tmds, csi, dsi_b
Example:
pinmux: pinmux {
compatible = "nvidia,tegra124-pinmux";
- reg = <0x70000868 0x164 /* Pad control registers */
- 0x70003000 0x434>; /* PinMux registers */
+ reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
+ <0x0 0x70003000 0x0 0x434>, /* Mux registers */
+ <0x0 0x70000820 0x0 0x8>; /* MIPI pad control */
};
Example pinmux entries:
diff --git a/dts/Bindings/pinctrl/pinctrl-bindings.txt b/dts/Bindings/pinctrl/pinctrl-bindings.txt
index fa40a17..98eb94d 100644
--- a/dts/Bindings/pinctrl/pinctrl-bindings.txt
+++ b/dts/Bindings/pinctrl/pinctrl-bindings.txt
@@ -127,6 +127,24 @@ whether there is any interaction between the child and intermediate parent
nodes, is again defined entirely by the binding for the individual pin
controller device.
+== Generic pin multiplexing node content ==
+
+pin multiplexing nodes:
+
+function - the mux function to select
+groups - the list of groups to select with this function
+
+Example:
+
+state_0_node_a {
+ function = "uart0";
+ groups = "u0rxtx", "u0rtscts";
+};
+state_1_node_a {
+ function = "spi0";
+ groups = "spi0pins";
+};
+
== Generic pin configuration node content ==
Many data items that are represented in a pin configuration node are common
@@ -139,8 +157,12 @@ structure of the DT nodes that contain these properties.
Supported generic properties are:
pins - the list of pins that properties in the node
- apply to
-function - the mux function to select
+ apply to (either this or "group" has to be
+ specified)
+group - the group to apply the properties to, if the driver
+ supports configuration of whole groups rather than
+ individual pins (either this or "pins" has to be
+ specified)
bias-disable - disable any pin bias
bias-high-impedance - high impedance mode ("third-state", "floating")
bias-bus-hold - latch weakly
@@ -163,6 +185,21 @@ output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
slew-rate - set the slew rate
+For example:
+
+state_0_node_a {
+ pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+ bias-pull-up;
+};
+state_1_node_a {
+ pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
+ output-high;
+};
+state_2_node_a {
+ group = "foo-group";
+ bias-pull-up;
+};
+
Some of the generic properties take arguments. For those that do, the
arguments are described below.
@@ -170,15 +207,6 @@ arguments are described below.
binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
-- function takes a list of function names/IDs as a required argument. The
- specific binding for the hardware defines:
- - Whether the entries are integers or strings, and their meaning.
- - Whether only a single entry is allowed (which is applied to all entries
- in the pins property), or whether there may alternatively be one entry per
- entry in the pins property, in which case the list lengths must match, and
- for each list index i, the function at list index i is applied to the pin
- at list index i.
-
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.
diff --git a/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt b/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt
index 92fae82..2fb90b3 100644
--- a/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt
+++ b/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt
@@ -50,7 +50,7 @@ Valid values for function are:
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
- riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
+ riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold
Example:
diff --git a/dts/Bindings/pinctrl/qcom,apq8084-pinctrl.txt b/dts/Bindings/pinctrl/qcom,apq8084-pinctrl.txt
new file mode 100644
index 0000000..ffafa19
--- /dev/null
+++ b/dts/Bindings/pinctrl/qcom,apq8084-pinctrl.txt
@@ -0,0 +1,179 @@
+Qualcomm APQ8084 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+MSM8960 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,apq8084-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode. Valid pins are:
+ gpio0-gpio146,
+ sdc1_clk,
+ sdc1_cmd,
+ sdc1_data
+ sdc2_clk,
+ sdc2_cmd,
+ sdc2_data
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+ adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
+ blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
+ blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
+ blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
+ blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
+ blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
+ blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
+ blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
+ blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
+ blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
+ blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
+ cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
+ cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+ edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
+ gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
+ hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
+ ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
+ pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
+ qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
+ sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
+ spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
+ tsif2, uim, uim_batt_alarm
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+ Not valid for sdc pins.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+ Not valid for sdc pins.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl@fd510000 {
+ compatible = "qcom,apq8084-pinctrl";
+ reg = <0xfd510000 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 208 0>;
+
+ uart2: uart2-default {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ };
+
+ tx {
+ pins = "gpio4";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
diff --git a/dts/Bindings/pinctrl/rockchip,pinctrl.txt b/dts/Bindings/pinctrl/rockchip,pinctrl.txt
index 4658b69..388b213 100644
--- a/dts/Bindings/pinctrl/rockchip,pinctrl.txt
+++ b/dts/Bindings/pinctrl/rockchip,pinctrl.txt
@@ -2,8 +2,8 @@
The Rockchip Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
-multiplexing the PAD input/output signals. For each PAD there are up to
-4 muxing options with option 0 being the use as a GPIO.
+multiplexing the PAD input/output signals. For each PAD there are several
+muxing options with option 0 being the use as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
@@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes:
Required properties for pin configuration node:
- rockchip,pins: 3 integers array, represents a group of pins mux and config
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
- The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
+ The MUX 0 means gpio and MUX 1 to N mean the specific device function.
The phandle of a node containing the generic pinconfig options
to use, as described in pinctrl-bindings.txt in this directory.
diff --git a/dts/Bindings/pinctrl/ti,omap-pinctrl.txt b/dts/Bindings/pinctrl/ti,omap-pinctrl.txt
new file mode 100644
index 0000000..88c8027
--- /dev/null
+++ b/dts/Bindings/pinctrl/ti,omap-pinctrl.txt
@@ -0,0 +1,13 @@
+OMAP Pinctrl definitions
+
+Required properties:
+- compatible : Should be one of:
+ "ti,omap2420-padconf" - OMAP2420 compatible pinctrl
+ "ti,omap2430-padconf" - OMAP2430 compatible pinctrl
+ "ti,omap3-padconf" - OMAP3 compatible pinctrl
+ "ti,omap4-padconf" - OMAP4 compatible pinctrl
+ "ti,omap5-padconf" - OMAP5 compatible pinctrl
+ "ti,dra7-padconf" - DRA7 compatible pinctrl
+ "ti,am437-padconf" - AM437x compatible pinctrl
+
+See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details.
diff --git a/dts/Bindings/power/power_domain.txt b/dts/Bindings/power/power_domain.txt
new file mode 100644
index 0000000..98c1667
--- /dev/null
+++ b/dts/Bindings/power/power_domain.txt
@@ -0,0 +1,49 @@
+* Generic PM domains
+
+System on chip designs are often divided into multiple PM domains that can be
+used for power gating of selected IP blocks for power saving by reduced leakage
+current.
+
+This device tree binding can be used to bind PM domain consumer devices with
+their PM domains provided by PM domain providers. A PM domain provider can be
+represented by any node in the device tree and can provide one or more PM
+domains. A consumer node can refer to the provider by a phandle and a set of
+phandle arguments (so called PM domain specifiers) of length specified by the
+#power-domain-cells property in the PM domain provider node.
+
+==PM domain providers==
+
+Required properties:
+ - #power-domain-cells : Number of cells in a PM domain specifier;
+ Typically 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM domains (e.g. power controllers), but can be any value
+ as specified by device tree binding documentation of particular provider.
+
+Example:
+
+ power: power-controller@12340000 {
+ compatible = "foo,power-controller";
+ reg = <0x12340000 0x1000>;
+ #power-domain-cells = <1>;
+ };
+
+The node above defines a power controller that is a PM domain provider and
+expects one cell as its phandle argument.
+
+==PM domain consumers==
+
+Required properties:
+ - power-domains : A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle.
+
+Example:
+
+ leaky-device@12350000 {
+ compatible = "foo,i-leak-current";
+ reg = <0x12350000 0x1000>;
+ power-domains = <&power 0>;
+ };
+
+The node above defines a typical PM domain consumer device, which is located
+inside a PM domain with index 0 of a power controller represented by a node
+with the label "power".
diff --git a/dts/Bindings/power/reset/ltc2952-poweroff.txt b/dts/Bindings/power/reset/ltc2952-poweroff.txt
new file mode 100644
index 0000000..0c94c63
--- /dev/null
+++ b/dts/Bindings/power/reset/ltc2952-poweroff.txt
@@ -0,0 +1,26 @@
+Binding for the LTC2952 PowerPath controller
+
+This chip is used to externally trigger a system shut down. Once the trigger has
+been sent, the chips' watchdog has to be reset to gracefully shut down.
+If the Linux systems decides to shut down it powers off the platform via the
+kill signal.
+
+Required properties:
+
+- compatible: Must contain: "lltc,ltc2952"
+- trigger-gpios: phandle + gpio-specifier for the GPIO connected to the
+ chip's trigger line
+- watchdog-gpios: phandle + gpio-specifier for the GPIO connected to the
+ chip's watchdog line
+- kill-gpios: phandle + gpio-specifier for the GPIO connected to the
+ chip's kill line
+
+Example:
+
+ltc2952 {
+ compatible = "lltc,ltc2952";
+
+ trigger-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ watchdog-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ kill-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/Bindings/power/reset/st-reset.txt b/dts/Bindings/power/reset/st-reset.txt
new file mode 100644
index 0000000..809af54
--- /dev/null
+++ b/dts/Bindings/power/reset/st-reset.txt
@@ -0,0 +1,11 @@
+*Device-Tree bindings for ST SW reset functionality
+
+Required properties:
+- compatible: should be "st,<chip>-restart".
+- st,syscfg: should be a phandle of the syscfg node.
+
+Example node:
+ restart {
+ compatible = "st,stih416-restart";
+ st,syscfg = <&syscfg_sbc>;
+ };
diff --git a/dts/Bindings/power/reset/syscon-reboot.txt b/dts/Bindings/power/reset/syscon-reboot.txt
new file mode 100644
index 0000000..1190631
--- /dev/null
+++ b/dts/Bindings/power/reset/syscon-reboot.txt
@@ -0,0 +1,23 @@
+Generic SYSCON mapped register reset driver
+
+This is a generic reset driver using syscon to map the reset register.
+The reset is generally performed with a write to the reset register
+defined by the register map pointed by syscon reference plus the offset
+with the mask defined in the reboot node.
+
+Required properties:
+- compatible: should contain "syscon-reboot"
+- regmap: this is phandle to the register map node
+- offset: offset in the register map for the reboot register (in bytes)
+- mask: the reset value written to the reboot register (32 bit access)
+
+Default will be little endian mode, 32 bit access only.
+
+Examples:
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&regmapnode>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
diff --git a/dts/Bindings/power/rockchip-io-domain.txt b/dts/Bindings/power/rockchip-io-domain.txt
new file mode 100644
index 0000000..6fbf6e7
--- /dev/null
+++ b/dts/Bindings/power/rockchip-io-domain.txt
@@ -0,0 +1,83 @@
+Rockchip SRAM for IO Voltage Domains:
+-------------------------------------
+
+IO domain voltages on some Rockchip SoCs are variable but need to be
+kept in sync between the regulators and the SoC using a special
+register.
+
+A specific example using rk3288:
+- If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
+ bit 7 of GRF_IO_VSEL needs to be 0. If the regulator hooked up to
+ that same pin is 1.8V then bit 7 of GRF_IO_VSEL needs to be 1.
+
+Said another way, this driver simply handles keeping bits in the SoC's
+general register file (GRF) in sync with the actual value of a voltage
+hooked up to the pins.
+
+Note that this driver specifically doesn't include:
+- any logic for deciding what voltage we should set regulators to
+- any logic for deciding whether regulators (or internal SoC blocks)
+ should have power or not have power
+
+If there were some other software that had the smarts of making
+decisions about regulators, it would work in conjunction with this
+driver. When that other software adjusted a regulator's voltage then
+this driver would handle telling the SoC about it. A good example is
+vqmmc for SD. In that case the dw_mmc driver simply is told about a
+regulator. It changes the regulator between 3.3V and 1.8V at the
+right time. This driver notices the change and makes sure that the
+SoC is on the same page.
+
+
+Required properties:
+- compatible: should be one of:
+ - "rockchip,rk3188-io-voltage-domain" for rk3188
+ - "rockchip,rk3288-io-voltage-domain" for rk3288
+- rockchip,grf: phandle to the syscon managing the "general register files"
+
+
+You specify supplies using the standard regulator bindings by including
+a phandle the the relevant regulator. All specified supplies must be able
+to report their voltage. The IO Voltage Domain for any non-specified
+supplies will be not be touched.
+
+Possible supplies for rk3188:
+- ap0-supply: The supply connected to AP0_VCC.
+- ap1-supply: The supply connected to AP1_VCC.
+- cif-supply: The supply connected to CIF_VCC.
+- flash-supply: The supply connected to FLASH_VCC.
+- lcdc0-supply: The supply connected to LCD0_VCC.
+- lcdc1-supply: The supply connected to LCD1_VCC.
+- vccio0-supply: The supply connected to VCCIO0.
+- vccio1-supply: The supply connected to VCCIO1.
+ Sometimes also labeled VCCIO1 and VCCIO2.
+
+Possible supplies for rk3288:
+- audio-supply: The supply connected to APIO4_VDD.
+- bb-supply: The supply connected to APIO5_VDD.
+- dvp-supply: The supply connected to DVPIO_VDD.
+- flash0-supply: The supply connected to FLASH0_VDD. Typically for eMMC
+- flash1-supply: The supply connected to FLASH1_VDD. Also known as SDIO1.
+- gpio30-supply: The supply connected to APIO1_VDD.
+- gpio1830 The supply connected to APIO2_VDD.
+- lcdc-supply: The supply connected to LCDC_VDD.
+- sdcard-supply: The supply connected to SDMMC0_VDD.
+- wifi-supply: The supply connected to APIO3_VDD. Also known as SDIO0.
+
+
+Example:
+
+ io-domains {
+ compatible = "rockchip,rk3288-io-voltage-domain";
+ rockchip,grf = <&grf>;
+
+ audio-supply = <&vcc18_codec>;
+ bb-supply = <&vcc33_io>;
+ dvp-supply = <&vcc_18>;
+ flash0-supply = <&vcc18_flashio>;
+ gpio1830-supply = <&vcc33_io>;
+ gpio30-supply = <&vcc33_pmuio>;
+ lcdc-supply = <&vcc33_lcd>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vcc18_wl>;
+ };
diff --git a/dts/Bindings/power_supply/charger-manager.txt b/dts/Bindings/power_supply/charger-manager.txt
index 2b33750..ec4fe9d 100644
--- a/dts/Bindings/power_supply/charger-manager.txt
+++ b/dts/Bindings/power_supply/charger-manager.txt
@@ -24,7 +24,7 @@ Optional properties :
- cm-thermal-zone : name of external thermometer's thermal zone
- cm-battery-* : threshold battery temperature for charging
-cold : critical cold temperature of battery for charging
- -cold-in-minus : flag that cold temerature is in minus degree
+ -cold-in-minus : flag that cold temperature is in minus degrees
-hot : critical hot temperature of battery for charging
-temp-diff : temperature difference to allow recharging
- cm-dis/charging-max = limits of charging duration
diff --git a/dts/Bindings/regmap/regmap.txt b/dts/Bindings/regmap/regmap.txt
new file mode 100644
index 0000000..b494f8b
--- /dev/null
+++ b/dts/Bindings/regmap/regmap.txt
@@ -0,0 +1,47 @@
+Device-Tree binding for regmap
+
+The endianness mode of CPU & Device scenarios:
+Index Device Endianness properties
+---------------------------------------------------
+1 BE 'big-endian'
+2 LE 'little-endian'
+
+For one device driver, which will run in different scenarios above
+on different SoCs using the devicetree, we need one way to simplify
+this.
+
+Required properties:
+- {big,little}-endian: these are boolean properties, if absent
+ meaning that the CPU and the Device are in the same endianness mode,
+ these properties are for register values and all the buffers only.
+
+Examples:
+Scenario 1 : CPU in LE mode & device in LE mode.
+dev: dev@40031000 {
+ compatible = "name";
+ reg = <0x40031000 0x1000>;
+ ...
+};
+
+Scenario 2 : CPU in LE mode & device in BE mode.
+dev: dev@40031000 {
+ compatible = "name";
+ reg = <0x40031000 0x1000>;
+ ...
+ big-endian;
+};
+
+Scenario 3 : CPU in BE mode & device in BE mode.
+dev: dev@40031000 {
+ compatible = "name";
+ reg = <0x40031000 0x1000>;
+ ...
+};
+
+Scenario 4 : CPU in BE mode & device in LE mode.
+dev: dev@40031000 {
+ compatible = "name";
+ reg = <0x40031000 0x1000>;
+ ...
+ little-endian;
+};
diff --git a/dts/Bindings/regulator/da9210.txt b/dts/Bindings/regulator/da9210.txt
index f120f22..3297c53 100644
--- a/dts/Bindings/regulator/da9210.txt
+++ b/dts/Bindings/regulator/da9210.txt
@@ -2,7 +2,7 @@
Required properties:
-- compatible: must be "diasemi,da9210"
+- compatible: must be "dlg,da9210"
- reg: the i2c slave address of the regulator. It should be 0x68.
Any standard regulator properties can be used to configure the single da9210
@@ -11,7 +11,7 @@ DCDC.
Example:
da9210@68 {
- compatible = "diasemi,da9210";
+ compatible = "dlg,da9210";
reg = <0x68>;
regulator-min-microvolt = <900000>;
diff --git a/dts/Bindings/regulator/da9211.txt b/dts/Bindings/regulator/da9211.txt
new file mode 100644
index 0000000..240019a
--- /dev/null
+++ b/dts/Bindings/regulator/da9211.txt
@@ -0,0 +1,63 @@
+* Dialog Semiconductor DA9211/DA9213 Voltage Regulator
+
+Required properties:
+- compatible: "dlg,da9211" or "dlg,da9213".
+- reg: I2C slave address, usually 0x68.
+- interrupts: the interrupt outputs of the controller
+- regulators: A node that houses a sub-node for each regulator within the
+ device. Each sub-node is identified using the node's name, with valid
+ values listed below. The content of each sub-node is defined by the
+ standard binding for regulators; see regulator.txt.
+ BUCKA and BUCKB.
+
+Optional properties:
+- Any optional property defined in regulator.txt
+
+Example 1) DA9211
+
+ pmic: da9211@68 {
+ compatible = "dlg,da9211";
+ reg = <0x68>;
+ interrupts = <3 27>;
+
+ regulators {
+ BUCKA {
+ regulator-name = "VBUCKA";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <2000000>;
+ regulator-max-microamp = <5000000>;
+ };
+ BUCKB {
+ regulator-name = "VBUCKB";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <2000000>;
+ regulator-max-microamp = <5000000>;
+ };
+ };
+ };
+
+Example 2) DA92113
+ pmic: da9213@68 {
+ compatible = "dlg,da9213";
+ reg = <0x68>;
+ interrupts = <3 27>;
+
+ regulators {
+ BUCKA {
+ regulator-name = "VBUCKA";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <6000000>;
+ };
+ BUCKB {
+ regulator-name = "VBUCKB";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <6000000>;
+ };
+ };
+ };
diff --git a/dts/Bindings/regulator/fan53555.txt b/dts/Bindings/regulator/fan53555.txt
new file mode 100644
index 0000000..54a3f2c
--- /dev/null
+++ b/dts/Bindings/regulator/fan53555.txt
@@ -0,0 +1,23 @@
+Binding for Fairchild FAN53555 regulators
+
+Required properties:
+ - compatible: one of "fcs,fan53555", "silergy,syr827", "silergy,syr828"
+ - reg: I2C address
+
+Optional properties:
+ - fcs,suspend-voltage-selector: declare which of the two available
+ voltage selector registers should be used for the suspend
+ voltage. The other one is used for the runtime voltage setting
+ Possible values are either <0> or <1>
+ - vin-supply: regulator supplying the vin pin
+
+Example:
+
+ regulator@40 {
+ compatible = "fcs,fan53555";
+ regulator-name = "fan53555";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&parent_reg>;
+ fcs,suspend-voltage-selector = <1>;
+ };
diff --git a/dts/Bindings/regulator/isl9305.txt b/dts/Bindings/regulator/isl9305.txt
new file mode 100644
index 0000000..a626fc1
--- /dev/null
+++ b/dts/Bindings/regulator/isl9305.txt
@@ -0,0 +1,36 @@
+Intersil ISL9305/ISL9305H voltage regulator
+
+Required properties:
+
+- compatible: "isl,isl9305" or "isl,isl9305h"
+- reg: I2C slave address, usually 0x68.
+- regulators: A node that houses a sub-node for each regulator within the
+ device. Each sub-node is identified using the node's name, with valid
+ values being "dcd1", "dcd2", "ldo1" and "ldo2". The content of each sub-node
+ is defined by the standard binding for regulators; see regulator.txt.
+- VINDCD1-supply: A phandle to a regulator node supplying VINDCD1.
+ VINDCD2-supply: A phandle to a regulator node supplying VINDCD2.
+ VINLDO1-supply: A phandle to a regulator node supplying VINLDO1.
+ VINLDO2-supply: A phandle to a regulator node supplying VINLDO2.
+
+Optional properties:
+- Per-regulator optional properties are defined in regulator.txt
+
+Example
+
+ pmic: isl9305@68 {
+ compatible = "isl,isl9305";
+ reg = <0x68>;
+
+ VINDCD1-supply = <&system_power>;
+ VINDCD2-supply = <&system_power>;
+ VINLDO1-supply = <&system_power>;
+ VINLDO2-supply = <&system_power>;
+
+ regulators {
+ dcd1 {
+ regulator-name = "VDD_DSP";
+ regulator-always-on;
+ };
+ };
+ };
diff --git a/dts/Bindings/regulator/max1586-regulator.txt b/dts/Bindings/regulator/max1586-regulator.txt
new file mode 100644
index 0000000..c050c17
--- /dev/null
+++ b/dts/Bindings/regulator/max1586-regulator.txt
@@ -0,0 +1,28 @@
+Maxim MAX1586 voltage regulator
+
+Required properties:
+- compatible: must be "maxim,max1586"
+- reg: I2C slave address, usually 0x14
+- v3-gain: integer specifying the V3 gain as per datasheet
+ (1 + R24/R25 + R24/185.5kOhm)
+- any required generic properties defined in regulator.txt
+
+Example:
+
+ i2c_master {
+ max1586@14 {
+ compatible = "maxim,max1586";
+ reg = <0x14>;
+ v3-gain = <1000000>;
+
+ regulators {
+ vcc_core: v3 {
+ regulator-name = "vcc_core";
+ regulator-compatible = "Output_V3";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1705000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/regulator/max77802.txt b/dts/Bindings/regulator/max77802.txt
new file mode 100644
index 0000000..5aeaffc
--- /dev/null
+++ b/dts/Bindings/regulator/max77802.txt
@@ -0,0 +1,53 @@
+Binding for Maxim MAX77802 regulators
+
+This is a part of device tree bindings of MAX77802 multi-function device.
+More information can be found in bindings/mfd/max77802.txt file.
+
+The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout (LDO)
+regulators that can be controlled over I2C.
+
+Following properties should be present in main device node of the MFD chip.
+
+Optional node:
+- regulators : The regulators of max77802 have to be instantiated
+ under subnode named "regulators" using the following format.
+
+ regulator-name {
+ standard regulator constraints....
+ };
+ refer Documentation/devicetree/bindings/regulator/regulator.txt
+
+The regulator node name should be initialized with a string to get matched
+with their hardware counterparts as follow. The valid names are:
+
+ -LDOn : for LDOs, where n can lie in ranges 1-15, 17-21, 23-30
+ and 32-35.
+ example: LDO1, LDO2, LDO35.
+ -BUCKn : for BUCKs, where n can lie in range 1 to 10.
+ example: BUCK1, BUCK5, BUCK10.
+Example:
+
+ max77802@09 {
+ compatible = "maxim,max77802";
+ interrupt-parent = <&wakeup_eint>;
+ interrupts = <26 0>;
+ reg = <0x09>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ regulators {
+ ldo11_reg: LDO11 {
+ regulator-name = "vdd_ldo11";
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-always-on;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
diff --git a/dts/Bindings/regulator/pwm-regulator.txt b/dts/Bindings/regulator/pwm-regulator.txt
new file mode 100644
index 0000000..ce91f61
--- /dev/null
+++ b/dts/Bindings/regulator/pwm-regulator.txt
@@ -0,0 +1,27 @@
+pwm regulator bindings
+
+Required properties:
+- compatible: Should be "pwm-regulator"
+- pwms: OF device-tree PWM specification (see PWM binding pwm.txt)
+- voltage-table: voltage and duty table, include 2 members in each set of
+ brackets, first one is voltage(unit: uv), the next is duty(unit: percent)
+
+Any property defined as part of the core regulator binding defined in
+regulator.txt can also be used.
+
+Example:
+ pwm_regulator {
+ compatible = "pwm-regulator;
+ pwms = <&pwm1 0 8448 0>;
+
+ voltage-table = <1114000 0>,
+ <1095000 10>,
+ <1076000 20>,
+ <1056000 30>,
+ <1036000 40>,
+ <1016000 50>;
+
+ regulator-min-microvolt = <1016000>;
+ regulator-max-microvolt = <1114000>;
+ regulator-name = "vdd_logic";
+ };
diff --git a/dts/Bindings/regulator/sky81452-regulator.txt b/dts/Bindings/regulator/sky81452-regulator.txt
new file mode 100644
index 0000000..882455e
--- /dev/null
+++ b/dts/Bindings/regulator/sky81452-regulator.txt
@@ -0,0 +1,16 @@
+SKY81452 voltage regulator
+
+Required properties:
+- any required generic properties defined in regulator.txt
+
+Optional properties:
+- any available generic properties defined in regulator.txt
+
+Example:
+
+ regulator {
+ /* generic regulator properties */
+ regulator-name = "touch_en";
+ regulator-min-microvolt = <4500000>;
+ regulator-max-microvolt = <8000000>;
+ };
diff --git a/dts/Bindings/rng/apm,rng.txt b/dts/Bindings/rng/apm,rng.txt
new file mode 100644
index 0000000..4dde4b0
--- /dev/null
+++ b/dts/Bindings/rng/apm,rng.txt
@@ -0,0 +1,17 @@
+APM X-Gene SoC random number generator.
+
+Required properties:
+
+- compatible : should be "apm,xgene-rng"
+- reg : specifies base physical address and size of the registers map
+- clocks : phandle to clock-controller plus clock-specifier pair
+- interrupts : specify the fault interrupt for the RNG device
+
+Example:
+
+ rng: rng@10520000 {
+ compatible = "apm,xgene-rng";
+ reg = <0x0 0x10520000 0x0 0x100>;
+ interrupts = <0x0 0x41 0x4>;
+ clocks = <&rngpkaclk 0>;
+ };
diff --git a/dts/Bindings/rtc/dallas,ds1339.txt b/dts/Bindings/rtc/dallas,ds1339.txt
new file mode 100644
index 0000000..916f576
--- /dev/null
+++ b/dts/Bindings/rtc/dallas,ds1339.txt
@@ -0,0 +1,18 @@
+* Dallas DS1339 I2C Serial Real-Time Clock
+
+Required properties:
+- compatible: Should contain "dallas,ds1339".
+- reg: I2C address for chip
+
+Optional properties:
+- trickle-resistor-ohms : Selected resistor for trickle charger
+ Values usable for ds1339 are 250, 2000, 4000
+ Should be given if trickle charger should be enabled
+- trickle-diode-disable : Do not use internal trickle charger diode
+ Should be given if internal trickle charger diode should be disabled
+Example:
+ ds1339: rtc@68 {
+ compatible = "dallas,ds1339";
+ trickle-resistor-ohms = <250>;
+ reg = <0x68>;
+ };
diff --git a/dts/Bindings/rtc/s3c-rtc.txt b/dts/Bindings/rtc/s3c-rtc.txt
index 7ac7259..ab757b8 100644
--- a/dts/Bindings/rtc/s3c-rtc.txt
+++ b/dts/Bindings/rtc/s3c-rtc.txt
@@ -3,7 +3,10 @@
Required properties:
- compatible: should be one of the following.
* "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc.
+ * "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc.
+ * "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc.
* "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
+ * "samsung,exynos3250-rtc" - for controllers compatible with exynos3250 rtc.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: Two interrupt numbers to the cpu should be specified. First
diff --git a/dts/Bindings/rtc/sun6i-rtc.txt b/dts/Bindings/rtc/sun6i-rtc.txt
new file mode 100644
index 0000000..f007e42
--- /dev/null
+++ b/dts/Bindings/rtc/sun6i-rtc.txt
@@ -0,0 +1,17 @@
+* sun6i Real Time Clock
+
+RTC controller for the Allwinner A31
+
+Required properties:
+- compatible : Should be "allwinner,sun6i-a31-rtc"
+- reg : physical base address of the controller and length of
+ memory mapped region.
+- interrupts : IRQ lines for the RTC alarm 0 and alarm 1, in that order.
+
+Example:
+
+rtc: rtc@01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <0 40 4>, <0 41 4>;
+};
diff --git a/dts/Bindings/serial/cirrus,clps711x-uart.txt b/dts/Bindings/serial/cirrus,clps711x-uart.txt
index 12f3cf8..caaeb25 100644
--- a/dts/Bindings/serial/cirrus,clps711x-uart.txt
+++ b/dts/Bindings/serial/cirrus,clps711x-uart.txt
@@ -8,7 +8,8 @@ Required properties:
- syscon: Phandle to SYSCON node, which contain UART control bits.
Optional properties:
-- uart-use-ms: Indicate the UART has modem signal (DCD, DSR, CTS).
+- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
+ line respectively.
Note: Each UART port should have an alias correctly numbered
in "aliases" node.
@@ -24,5 +25,7 @@ Example:
interrupts = <12 13>;
clocks = <&clks 11>;
syscon = <&syscon1>;
- uart-use-ms;
+ cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
new file mode 100644
index 0000000..48358a3
--- /dev/null
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -0,0 +1,22 @@
+* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
+
+Required properties:
+- compatible should contain:
+ * "mediatek,mt6589-uart" for MT6589 compatible UARTS
+ * "mediatek,mt6582-uart" for MT6582 compatible UARTS
+ * "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577)
+
+- reg: The base address of the UART register bank.
+
+- interrupts: A single interrupt specifier.
+
+- clocks: Clock driving the hardware.
+
+Example:
+
+ uart0: serial@11006000 {
+ compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
+ reg = <0x11006000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
diff --git a/dts/Bindings/serial/of-serial.txt b/dts/Bindings/serial/of-serial.txt
index 7705477..8c4fd03 100644
--- a/dts/Bindings/serial/of-serial.txt
+++ b/dts/Bindings/serial/of-serial.txt
@@ -14,6 +14,7 @@ Required properties:
- "altr,16550-FIFO32"
- "altr,16550-FIFO64"
- "altr,16550-FIFO128"
+ - "fsl,16550-FIFO64"
- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
@@ -37,7 +38,6 @@ Optional properties:
- auto-flow-control: one way to enable automatic flow control support. The
driver is allowed to detect support for the capability even without this
property.
-- has-hw-flow-control: the hardware has flow control capability.
Example:
diff --git a/dts/Bindings/serial/via,vt8500-uart.txt b/dts/Bindings/serial/via,vt8500-uart.txt
deleted file mode 100644
index 5feef1e..0000000
--- a/dts/Bindings/serial/via,vt8500-uart.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-VIA/Wondermedia VT8500 UART Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-uart"
-- reg : Should contain 1 register ranges(address and length)
-- interrupts : UART interrupt
-- clocks : phandle to the uart source clock (usually a 24Mhz fixed clock)
-
-Example:
-
- uart@d8210000 {
- compatible = "via,vt8500-uart";
- reg = <0xd8210000 0x1040>;
- interrupts = <47>;
- clocks = <&ref24>;
- };
diff --git a/dts/Bindings/serial/vt8500-uart.txt b/dts/Bindings/serial/vt8500-uart.txt
index 795c393..2b64e61 100644
--- a/dts/Bindings/serial/vt8500-uart.txt
+++ b/dts/Bindings/serial/vt8500-uart.txt
@@ -1,7 +1,8 @@
* VIA VT8500 and WonderMedia WM8xxx UART Controller
Required properties:
-- compatible: should be "via,vt8500-uart"
+- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
+ including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
- reg: base physical address of the controller and length of memory mapped
region.
diff --git a/dts/Bindings/soc/ti/keystone-navigator-dma.txt b/dts/Bindings/soc/ti/keystone-navigator-dma.txt
new file mode 100644
index 0000000..337c4ea
--- /dev/null
+++ b/dts/Bindings/soc/ti/keystone-navigator-dma.txt
@@ -0,0 +1,111 @@
+Keystone Navigator DMA Controller
+
+This document explains the device tree bindings for the packet dma
+on keystone devices. The Keystone Navigator DMA driver sets up the dma
+channels and flows for the QMSS(Queue Manager SubSystem) who triggers
+the actual data movements across clients using destination queues. Every
+client modules like NETCP(Network Coprocessor), SRIO(Serial Rapid IO),
+CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
+an internal packet DMA module which is used as an infrastructure DMA
+with zero copy.
+
+Navigator DMA cloud layout:
+ ------------------
+ | Navigator DMAs |
+ ------------------
+ |
+ |-> DMA instance #0
+ |
+ |-> DMA instance #1
+ .
+ .
+ |
+ |-> DMA instance #n
+
+Navigator DMA properties:
+Required properties:
+ - compatible: Should be "ti,keystone-navigator-dma"
+ - clocks: phandle to dma instances clocks. The clock handles can be as
+ many as the dma instances. The order should be maintained as per
+ the dma instances.
+ - ti,navigator-cloud-address: Should contain base address for the multi-core
+ navigator cloud and number of addresses depends on SOC integration
+ configuration.. Navigator cloud global address needs to be programmed
+ into DMA and the DMA uses it as the physical addresses to reach queue
+ managers. Note that these addresses though points to queue managers,
+ they are relevant only from DMA perspective. The QMSS may not choose to
+ use them since it has a different address space view to reach all
+ its components.
+
+DMA instance properties:
+Required properties:
+ - reg: Should contain register location and length of the following dma
+ register regions. Register regions should be specified in the following
+ order.
+ - Global control register region (global).
+ - Tx DMA channel configuration register region (txchan).
+ - Rx DMA channel configuration register region (rxchan).
+ - Tx DMA channel Scheduler configuration register region (txsched).
+ - Rx DMA flow configuration register region (rxflow).
+
+Optional properties:
+ - reg-names: Names for the register regions.
+ - ti,enable-all: Enable all DMA channels vs clients opening specific channels
+ what they need. This property is useful for the userspace fast path
+ case where the linux drivers enables the channels used by userland
+ stack.
+ - ti,loop-back: To loopback Tx streaming I/F to Rx streaming I/F. Used for
+ infrastructure transfers.
+ - ti,rx-retry-timeout: Number of dma cycles to wait before retry on buffer
+ starvation.
+
+Example:
+
+ knav_dmas: knav_dmas@0 {
+ compatible = "ti,keystone-navigator-dma";
+ clocks = <&papllclk>, <&clkxge>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,navigator-cloud-address = <0x23a80000 0x23a90000
+ 0x23aa0000 0x23ab0000>;
+
+ dma_gbe: dma_gbe@0 {
+ reg = <0x2004000 0x100>,
+ <0x2004400 0x120>,
+ <0x2004800 0x300>,
+ <0x2004c00 0x120>,
+ <0x2005000 0x400>;
+ reg-names = "global", "txchan", "rxchan",
+ "txsched", "rxflow";
+ };
+
+ dma_xgbe: dma_xgbe@0 {
+ reg = <0x2fa1000 0x100>,
+ <0x2fa1400 0x200>,
+ <0x2fa1800 0x200>,
+ <0x2fa1c00 0x200>,
+ <0x2fa2000 0x400>;
+ reg-names = "global", "txchan", "rxchan",
+ "txsched", "rxflow";
+ };
+ };
+
+Navigator DMA client:
+Required properties:
+ - ti,navigator-dmas: List of one or more DMA specifiers, each consisting of
+ - A phandle pointing to DMA instance node
+ - A DMA channel number as a phandle arg.
+ - ti,navigator-dma-names: Contains dma channel name for each DMA specifier in
+ the 'ti,navigator-dmas' property.
+
+Example:
+
+ netcp: netcp@2090000 {
+ ..
+ ti,navigator-dmas = <&dma_gbe 22>,
+ <&dma_gbe 23>,
+ <&dma_gbe 8>;
+ ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
+ ..
+ };
diff --git a/dts/Bindings/soc/ti/keystone-navigator-qmss.txt b/dts/Bindings/soc/ti/keystone-navigator-qmss.txt
new file mode 100644
index 0000000..d8e8cdb
--- /dev/null
+++ b/dts/Bindings/soc/ti/keystone-navigator-qmss.txt
@@ -0,0 +1,232 @@
+* Texas Instruments Keystone Navigator Queue Management SubSystem driver
+
+The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
+the main hardware sub system which forms the backbone of the Keystone
+multi-core Navigator. QMSS consist of queue managers, packed-data structure
+processors(PDSP), linking RAM, descriptor pools and infrastructure
+Packet DMA.
+The Queue Manager is a hardware module that is responsible for accelerating
+management of the packet queues. Packets are queued/de-queued by writing or
+reading descriptor address to a particular memory mapped location. The PDSPs
+perform QMSS related functions like accumulation, QoS, or event management.
+Linking RAM registers are used to link the descriptors which are stored in
+descriptor RAM. Descriptor RAM is configurable as internal or external memory.
+The QMSS driver manages the PDSP setups, linking RAM regions,
+queue pool management (allocation, push, pop and notify) and descriptor
+pool management.
+
+
+Required properties:
+- compatible : Must be "ti,keystone-navigator-qmss";
+- clocks : phandle to the reference clock for this device.
+- queue-range : <start number> total range of queue numbers for the device.
+- linkram0 : <address size> for internal link ram, where size is the total
+ link ram entries.
+- linkram1 : <address size> for external link ram, where size is the total
+ external link ram entries. If the address is specified as "0"
+ driver will allocate memory.
+- qmgrs : child node describing the individual queue managers on the
+ SoC. On keystone 1 devices there should be only one node.
+ On keystone 2 devices there can be more than 1 node.
+ -- managed-queues : the actual queues managed by each queue manager
+ instance, specified as <"base queue #" "# of queues">.
+ -- reg : Address and size of the register set for the device.
+ Register regions should be specified in the following
+ order
+ - Queue Peek region.
+ - Queue status RAM.
+ - Queue configuration region.
+ - Descriptor memory setup region.
+ - Queue Management/Queue Proxy region for queue Push.
+ - Queue Management/Queue Proxy region for queue Pop.
+- queue-pools : child node classifying the queue ranges into pools.
+ Queue ranges are grouped into 3 type of pools:
+ - qpend : pool of qpend(interruptible) queues
+ - general-purpose : pool of general queues, primarly used
+ as free descriptor queues or the
+ transmit DMA queues.
+ - accumulator : pool of queues on PDSP accumulator channel
+ Each range can have the following properties:
+ -- qrange : number of queues to use per queue range, specified as
+ <"base queue #" "# of queues">.
+ -- interrupts : Optional property to specify the interrupt mapping
+ for interruptible queues. The driver additionaly sets
+ the interrupt affinity hint based on the cpu mask.
+ -- qalloc-by-id : Optional property to specify that the queues in this
+ range can only be allocated by queue id.
+ -- accumulator : Accumulator channel specification. Any of the PDSPs in
+ QMSS can be loaded with the accumulator firmware. The
+ accumulator firmware’s job is to poll a select number of
+ queues looking for descriptors that have been pushed
+ into them. Descriptors are popped from the queue and
+ placed in a buffer provided by the host. When the list
+ becomes full or a programmed time period expires, the
+ accumulator triggers an interrupt to the host to read
+ the buffer for descriptor information. This firmware
+ comes in 16, 32, and 48 channel builds. Each of these
+ channels can be configured to monitor 32 contiguous
+ queues. Accumulator channel property is specified as:
+ <pdsp-id, channel, entries, pacing mode, latency>
+ pdsp-id : QMSS PDSP running accumulator firmware
+ on which the channel has to be
+ configured
+ channel : Accumulator channel number
+ entries : Size of the accumulator descriptor list
+ pacing mode : Interrupt pacing mode
+ 0 : None, i.e interrupt on list full only
+ 1 : Time delay since last interrupt
+ 2 : Time delay since first new packet
+ 3 : Time delay since last new packet
+ latency : time to delay the interrupt, specified
+ in microseconds.
+ -- multi-queue : Optional property to specify that the channel has to
+ monitor upto 32 queues starting at the base queue #.
+- descriptor-regions : child node describing the memory regions for keystone
+ navigator packet DMA descriptors. The memory for
+ descriptors will be allocated by the driver.
+ -- id : region number in QMSS.
+ -- region-spec : specifies the number of descriptors in the
+ region, specified as
+ <"# of descriptors" "descriptor size">.
+ -- link-index : start index, i.e. index of the first
+ descriptor in the region.
+
+Optional properties:
+- dma-coherent : Present if DMA operations are coherent.
+- pdsps : child node describing the PDSP configuration.
+ -- firmware : firmware to be loaded on the PDSP.
+ -- id : the qmss pdsp that will run the firmware.
+ -- reg : Address and size of the register set for the PDSP.
+ Register regions should be specified in the following
+ order
+ - PDSP internal RAM region.
+ - PDSP control/status region registers.
+ - QMSS interrupt distributor registers.
+ - PDSP command interface region.
+
+Example:
+
+qmss: qmss@2a40000 {
+ compatible = "ti,keystone-qmss";
+ dma-coherent;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&chipclk13>;
+ ranges;
+ queue-range = <0 0x4000>;
+ linkram0 = <0x100000 0x8000>;
+ linkram1 = <0x0 0x10000>;
+
+ qmgrs {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ qmgr0 {
+ managed-queues = <0 0x2000>;
+ reg = <0x2a40000 0x20000>,
+ <0x2a06000 0x400>,
+ <0x2a02000 0x1000>,
+ <0x2a03000 0x1000>,
+ <0x23a80000 0x20000>,
+ <0x2a80000 0x20000>;
+ };
+
+ qmgr1 {
+ managed-queues = <0x2000 0x2000>;
+ reg = <0x2a60000 0x20000>,
+ <0x2a06400 0x400>,
+ <0x2a04000 0x1000>,
+ <0x2a05000 0x1000>,
+ <0x23aa0000 0x20000>,
+ <0x2aa0000 0x20000>;
+ };
+ };
+ queue-pools {
+ qpend {
+ qpend-0 {
+ qrange = <658 8>;
+ interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
+ 0 43 0xf04 0 44 0xf04 0 45 0xf04
+ 0 46 0xf04 0 47 0xf04>;
+ };
+ qpend-1 {
+ qrange = <8704 16>;
+ interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
+ 0 51 0xf04 0 52 0xf04 0 53 0xf04
+ 0 54 0xf04 0 55 0xf04 0 56 0xf04
+ 0 57 0xf04 0 58 0xf04 0 59 0xf04
+ 0 60 0xf04 0 61 0xf04 0 62 0xf04
+ 0 63 0xf04>;
+ qalloc-by-id;
+ };
+ qpend-2 {
+ qrange = <8720 16>;
+ interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
+ 0 59 0xf04 0 68 0xf04 0 69 0xf04
+ 0 70 0xf04 0 71 0xf04 0 72 0xf04
+ 0 73 0xf04 0 74 0xf04 0 75 0xf04
+ 0 76 0xf04 0 77 0xf04 0 78 0xf04
+ 0 79 0xf04>;
+ };
+ };
+ general-purpose {
+ gp-0 {
+ qrange = <4000 64>;
+ };
+ netcp-tx {
+ qrange = <640 9>;
+ qalloc-by-id;
+ };
+ };
+ accumulator {
+ acc-0 {
+ qrange = <128 32>;
+ accumulator = <0 36 16 2 50>;
+ interrupts = <0 215 0xf01>;
+ multi-queue;
+ qalloc-by-id;
+ };
+ acc-1 {
+ qrange = <160 32>;
+ accumulator = <0 37 16 2 50>;
+ interrupts = <0 216 0xf01>;
+ multi-queue;
+ };
+ acc-2 {
+ qrange = <192 32>;
+ accumulator = <0 38 16 2 50>;
+ interrupts = <0 217 0xf01>;
+ multi-queue;
+ };
+ acc-3 {
+ qrange = <224 32>;
+ accumulator = <0 39 16 2 50>;
+ interrupts = <0 218 0xf01>;
+ multi-queue;
+ };
+ };
+ };
+ descriptor-regions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ region-12 {
+ id = <12>;
+ region-spec = <8192 128>; /* num_desc desc_size */
+ link-index = <0x4000>;
+ };
+ };
+ pdsps {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pdsp0@0x2a10000 {
+ firmware = "keystone/qmss_pdsp_acc48_k2_le_1_0_0_8.fw";
+ reg = <0x2a10000 0x1000>,
+ <0x2a0f000 0x100>,
+ <0x2a0c000 0x3c8>,
+ <0x2a20000 0x4000>;
+ id = <0>;
+ };
+ };
+}; /* qmss */
diff --git a/dts/Bindings/sound/adi,ssm2602.txt b/dts/Bindings/sound/adi,ssm2602.txt
new file mode 100644
index 0000000..3b3302f
--- /dev/null
+++ b/dts/Bindings/sound/adi,ssm2602.txt
@@ -0,0 +1,19 @@
+Analog Devices SSM2602, SSM2603 and SSM2604 I2S audio CODEC devices
+
+SSM2602 support both I2C and SPI as the configuration interface,
+the selection is made by the MODE strap-in pin.
+SSM2603 and SSM2604 only support I2C as the configuration interface.
+
+Required properties:
+
+ - compatible : One of "adi,ssm2602", "adi,ssm2603" or "adi,ssm2604"
+
+ - reg : the I2C address of the device for I2C, the chip select
+ number for SPI.
+
+ Example:
+
+ ssm2602: ssm2602@1a {
+ compatible = "adi,ssm2602";
+ reg = <0x1a>;
+ };
diff --git a/dts/Bindings/sound/cs35l32.txt b/dts/Bindings/sound/cs35l32.txt
new file mode 100644
index 0000000..1417d3f
--- /dev/null
+++ b/dts/Bindings/sound/cs35l32.txt
@@ -0,0 +1,62 @@
+CS35L32 audio CODEC
+
+Required properties:
+
+ - compatible : "cirrus,cs35l32"
+
+ - reg : the I2C address of the device for I2C. Address is determined by the level
+ of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41.
+
+ - VA-supply, VP-supply : power supplies for the device,
+ as covered in Documentation/devicetree/bindings/regulator/regulator.txt.
+
+Optional properties:
+
+ - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
+ deasserted before communication to the codec starts.
+
+ - cirrus,boost-manager : Boost voltage control.
+ 0 = Automatically managed. Boost-converter output voltage is the higher
+ of the two: Class G or adaptive LED voltage.
+ 1 = Automatically managed irrespective of audio, adapting for low-power
+ dissipation when LEDs are ON, and operating in Fixed-Boost Bypass Mode
+ if LEDs are OFF (VBST = VP).
+ 2 = (Default) Boost voltage fixed in Bypass Mode (VBST = VP).
+ 3 = Boost voltage fixed at 5 V.
+
+ - cirrus,sdout-datacfg : Data configuration for dual CS35L32 applications only.
+ Determines the data packed in a two-CS35L32 configuration.
+ 0 = Left/right channels VMON[11:0], IMON[11:0], VPMON[7:0].
+ 1 = Left/right channels VMON[11:0], IMON[11:0], STATUS.
+ 2 = (Default) left/right channels VMON[15:0], IMON [15:0].
+ 3 = Left/right channels VPMON[7:0], STATUS.
+
+ - cirrus,sdout-share : SDOUT sharing. Determines whether one or two CS35L32
+ devices are on board sharing SDOUT.
+ 0 = (Default) One IC.
+ 1 = Two IC's.
+
+ - cirrus,battery-recovery : Low battery nominal recovery threshold, rising VP.
+ 0 = 3.1V
+ 1 = 3.2V
+ 2 = 3.3V (Default)
+ 3 = 3.4V
+
+ - cirrus,battery-threshold : Low battery nominal threshold, falling VP.
+ 0 = 3.1V
+ 1 = 3.2V
+ 2 = 3.3V
+ 3 = 3.4V (Default)
+ 4 = 3.5V
+ 5 = 3.6V
+
+Example:
+
+codec: codec@40 {
+ compatible = "cirrus,cs35l32";
+ reg = <0x40>;
+ reset-gpios = <&gpio 10 0>;
+ cirrus,boost-manager = <0x03>;
+ cirrus,sdout-datacfg = <0x02>;
+ VA-supply = <&reg_audio>;
+};
diff --git a/dts/Bindings/sound/es8328.txt b/dts/Bindings/sound/es8328.txt
new file mode 100644
index 0000000..30ea8a3
--- /dev/null
+++ b/dts/Bindings/sound/es8328.txt
@@ -0,0 +1,38 @@
+Everest ES8328 audio CODEC
+
+This device supports both I2C and SPI.
+
+Required properties:
+
+ - compatible : "everest,es8328"
+ - DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V
+ - AVDD-supply : Regulator providing analog supply voltage 3.3V
+ - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
+ - IPVDD-supply : Regulator providing analog output voltage 3.3V
+ - clocks : A 22.5792 or 11.2896 MHz clock
+ - reg : the I2C address of the device for I2C, the chip select number for SPI
+
+Pins on the device (for linking into audio routes):
+
+ * LOUT1
+ * LOUT2
+ * ROUT1
+ * ROUT2
+ * LINPUT1
+ * RINPUT1
+ * LINPUT2
+ * RINPUT2
+ * Mic Bias
+
+
+Example:
+
+codec: es8328@11 {
+ compatible = "everest,es8328";
+ DVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_3p3v>;
+ PVDD-supply = <&reg_3p3v>;
+ HPVDD-supply = <&reg_3p3v>;
+ clocks = <&clks 169>;
+ reg = <0x11>;
+};
diff --git a/dts/Bindings/sound/fsl,esai.txt b/dts/Bindings/sound/fsl,esai.txt
index aeb8c4a..52f5b6b 100644
--- a/dts/Bindings/sound/fsl,esai.txt
+++ b/dts/Bindings/sound/fsl,esai.txt
@@ -7,7 +7,8 @@ other DSPs. It has up to six transmitters and four receivers.
Required properties:
- - compatible : Compatible list, must contain "fsl,imx35-esai".
+ - compatible : Compatible list, must contain "fsl,imx35-esai" or
+ "fsl,vf610-esai"
- reg : Offset and length of the register set for the device.
diff --git a/dts/Bindings/sound/fsl,ssi.txt b/dts/Bindings/sound/fsl,ssi.txt
index 3aa4a8f..5b76be4 100644
--- a/dts/Bindings/sound/fsl,ssi.txt
+++ b/dts/Bindings/sound/fsl,ssi.txt
@@ -58,13 +58,7 @@ Optional properties:
Documentation/devicetree/bindings/dma/dma.txt.
- dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq
is not defined.
-- fsl,mode: The operating mode for the SSI interface.
- "i2s-slave" - I2S mode, SSI is clock slave
- "i2s-master" - I2S mode, SSI is clock master
- "lj-slave" - left-justified mode, SSI is clock slave
- "lj-master" - l.j. mode, SSI is clock master
- "rj-slave" - right-justified mode, SSI is clock slave
- "rj-master" - r.j., SSI is clock master
+- fsl,mode: The operating mode for the AC97 interface only.
"ac97-slave" - AC97 mode, SSI is clock slave
"ac97-master" - AC97 mode, SSI is clock master
diff --git a/dts/Bindings/sound/fsl-asoc-card.txt b/dts/Bindings/sound/fsl-asoc-card.txt
new file mode 100644
index 0000000..a96774c
--- /dev/null
+++ b/dts/Bindings/sound/fsl-asoc-card.txt
@@ -0,0 +1,82 @@
+Freescale Generic ASoC Sound Card with ASRC support
+
+The Freescale Generic ASoC Sound Card can be used, ideally, for all Freescale
+SoCs connecting with external CODECs.
+
+The idea of this generic sound card is a bit like ASoC Simple Card. However,
+for Freescale SoCs (especially those released in recent years), most of them
+have ASRC (Documentation/devicetree/bindings/sound/fsl,asrc.txt) inside. And
+this is a specific feature that might be painstakingly controlled and merged
+into the Simple Card.
+
+So having this generic sound card allows all Freescale SoC users to benefit
+from the simplification of a new card support and the capability of the wide
+sample rates support through ASRC.
+
+Note: The card is initially designed for those sound cards who use I2S and
+ PCM DAI formats. However, it'll be also possible to support those non
+ I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as long
+ as the driver has been properly upgraded.
+
+
+The compatible list for this generic sound card currently:
+ "fsl,imx-audio-cs42888"
+
+ "fsl,imx-audio-wm8962"
+ (compatible with Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt)
+
+ "fsl,imx-audio-sgtl5000"
+ (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)
+
+Required properties:
+
+ - compatible : Contains one of entries in the compatible list.
+
+ - model : The user-visible name of this sound complex
+
+ - audio-cpu : The phandle of an CPU DAI controller
+
+ - audio-codec : The phandle of an audio codec
+
+ - audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the
+ connection's sink, the second being the connection's
+ source. There're a few pre-designed board connectors:
+ * Line Out Jack
+ * Line In Jack
+ * Headphone Jack
+ * Mic Jack
+ * Ext Spk
+ * AMIC (stands for Analog Microphone Jack)
+ * DMIC (stands for Digital Microphone Jack)
+
+ Note: The "Mic Jack" and "AMIC" are redundant while
+ coexsiting in order to support the old bindings
+ of wm8962 and sgtl5000.
+
+Optional properties:
+
+ - audio-asrc : The phandle of ASRC. It can be absent if there's no
+ need to add ASRC support via DPCM.
+
+Example:
+sound-cs42888 {
+ compatible = "fsl,imx-audio-cs42888";
+ model = "cs42888-audio";
+ audio-cpu = <&esai>;
+ audio-asrc = <&asrc>;
+ audio-codec = <&cs42888>;
+ audio-routing =
+ "Line Out Jack", "AOUT1L",
+ "Line Out Jack", "AOUT1R",
+ "Line Out Jack", "AOUT2L",
+ "Line Out Jack", "AOUT2R",
+ "Line Out Jack", "AOUT3L",
+ "Line Out Jack", "AOUT3R",
+ "Line Out Jack", "AOUT4L",
+ "Line Out Jack", "AOUT4R",
+ "AIN1L", "Line In Jack",
+ "AIN1R", "Line In Jack",
+ "AIN2L", "Line In Jack",
+ "AIN2R", "Line In Jack";
+};
diff --git a/dts/Bindings/sound/fsl-sai.txt b/dts/Bindings/sound/fsl-sai.txt
index 0f4e238..4956b14 100644
--- a/dts/Bindings/sound/fsl-sai.txt
+++ b/dts/Bindings/sound/fsl-sai.txt
@@ -18,12 +18,26 @@ Required properties:
- pinctrl-names: Must contain a "default" entry.
- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
See ../pinctrl/pinctrl-bindings.txt for details of the property values.
-- big-endian-regs: If this property is absent, the little endian mode will
- be in use as default, or the big endian mode will be in use for all the
- device registers.
-- big-endian-data: If this property is absent, the little endian mode will
- be in use as default, or the big endian mode will be in use for all the
- fifo data.
+- big-endian: Boolean property, required if all the FTM_PWM registers
+ are big-endian rather than little-endian.
+- lsb-first: Configures whether the LSB or the MSB is transmitted first for
+ the fifo data. If this property is absent, the MSB is transmitted first as
+ default, or the LSB is transmitted first.
+- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
+ that SAI will work in the synchronous mode (sync Tx with Rx) which means
+ both the transimitter and receiver will send and receive data by following
+ receiver's bit clocks and frame sync clocks.
+- fsl,sai-asynchronous: This is a boolean property. If present, indicating
+ that SAI will work in the asynchronous mode, which means both transimitter
+ and receiver will send and receive data by following their own bit clocks
+ and frame sync clocks separately.
+
+Note:
+- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
+ default synchronous mode (sync Rx with Tx) will be used, which means both
+ transimitter and receiver will send and receive data by following clocks
+ of transimitter.
+- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
Example:
sai2: sai@40031000 {
@@ -38,6 +52,6 @@ sai2: sai@40031000 {
dma-names = "tx", "rx";
dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
- big-endian-regs;
- big-endian-data;
+ big-endian;
+ lsb-first;
};
diff --git a/dts/Bindings/sound/imx-audio-es8328.txt b/dts/Bindings/sound/imx-audio-es8328.txt
new file mode 100644
index 0000000..07b68ab
--- /dev/null
+++ b/dts/Bindings/sound/imx-audio-es8328.txt
@@ -0,0 +1,60 @@
+Freescale i.MX audio complex with ES8328 codec
+
+Required properties:
+- compatible : "fsl,imx-audio-es8328"
+- model : The user-visible name of this sound complex
+- ssi-controller : The phandle of the i.MX SSI controller
+- jack-gpio : Optional GPIO for headphone jack
+- audio-amp-supply : Power regulator for speaker amps
+- audio-codec : The phandle of the ES8328 audio codec
+- audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the
+ connection's sink, the second being the connection's
+ source. Valid names could be power supplies, ES8328
+ pins, and the jacks on the board:
+
+ Power supplies:
+ * audio-amp
+
+ ES8328 pins:
+ * LOUT1
+ * LOUT2
+ * ROUT1
+ * ROUT2
+ * LINPUT1
+ * LINPUT2
+ * RINPUT1
+ * RINPUT2
+ * Mic PGA
+
+ Board connectors:
+ * Headphone
+ * Speaker
+ * Mic Jack
+- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
+- mux-ext-port : The external port of the i.MX audio muxer (AUDMIX)
+
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+
+Example:
+
+sound {
+ compatible = "fsl,imx-audio-es8328";
+ model = "imx-audio-es8328";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ jack-gpio = <&gpio5 15 0>;
+ audio-amp-supply = <&reg_audio_amp>;
+ audio-routing =
+ "Speaker", "LOUT2",
+ "Speaker", "ROUT2",
+ "Speaker", "audio-amp",
+ "Headphone", "ROUT1",
+ "Headphone", "LOUT1",
+ "LINPUT1", "Mic Jack",
+ "RINPUT1", "Mic Jack",
+ "Mic Jack", "Mic Bias";
+ mux-int-port = <1>;
+ mux-ext-port = <3>;
+};
diff --git a/dts/Bindings/sound/nvidia,tegra-audio-max98090.txt b/dts/Bindings/sound/nvidia,tegra-audio-max98090.txt
index 9c7c55c..c949abc 100644
--- a/dts/Bindings/sound/nvidia,tegra-audio-max98090.txt
+++ b/dts/Bindings/sound/nvidia,tegra-audio-max98090.txt
@@ -25,6 +25,7 @@ Required properties:
Optional properties:
- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
+- nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in
Example:
diff --git a/dts/Bindings/sound/rt5677.txt b/dts/Bindings/sound/rt5677.txt
new file mode 100644
index 0000000..0701b83
--- /dev/null
+++ b/dts/Bindings/sound/rt5677.txt
@@ -0,0 +1,59 @@
+RT5677 audio CODEC
+
+This device supports I2C only.
+
+Required properties:
+
+- compatible : "realtek,rt5677".
+
+- reg : The I2C address of the device.
+
+- interrupts : The CODEC's interrupt output.
+
+- gpio-controller : Indicates this device is a GPIO controller.
+
+- #gpio-cells : Should be two. The first cell is the pin number and the
+ second cell is used to specify optional parameters (currently unused).
+
+Optional properties:
+
+- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
+
+- realtek,in1-differential
+- realtek,in2-differential
+- realtek,lout1-differential
+- realtek,lout2-differential
+- realtek,lout3-differential
+ Boolean. Indicate MIC1/2 input and LOUT1/2/3 outputs are differential,
+ rather than single-ended.
+
+Pins on the device (for linking into audio routes):
+
+ * IN1P
+ * IN1N
+ * IN2P
+ * IN2N
+ * MICBIAS1
+ * DMIC1
+ * DMIC2
+ * DMIC3
+ * DMIC4
+ * LOUT1
+ * LOUT2
+ * LOUT3
+
+Example:
+
+rt5677 {
+ compatible = "realtek,rt5677";
+ reg = <0x2c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ realtek,pow-ldo2-gpio =
+ <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+ realtek,in1-differential = "true";
+};
diff --git a/dts/Bindings/sound/simple-card.txt b/dts/Bindings/sound/simple-card.txt
index c2e9841..c3cba60 100644
--- a/dts/Bindings/sound/simple-card.txt
+++ b/dts/Bindings/sound/simple-card.txt
@@ -17,6 +17,10 @@ Optional properties:
source.
- simple-audio-card,mclk-fs : Multiplication factor between stream rate and codec
mclk.
+- simple-audio-card,hp-det-gpio : Reference to GPIO that signals when
+ headphones are attached.
+- simple-audio-card,mic-det-gpio : Reference to GPIO that signals when
+ a microphone is attached.
Optional subnodes:
diff --git a/dts/Bindings/sound/ssm4567.txt b/dts/Bindings/sound/ssm4567.txt
new file mode 100644
index 0000000..ec3d9e7
--- /dev/null
+++ b/dts/Bindings/sound/ssm4567.txt
@@ -0,0 +1,15 @@
+Analog Devices SSM4567 audio amplifier
+
+This device supports I2C only.
+
+Required properties:
+ - compatible : Must be "adi,ssm4567"
+ - reg : the I2C address of the device. This will either be 0x34 (LR_SEL/ADDR connected to AGND),
+ 0x35 (LR_SEL/ADDR connected to IOVDD) or 0x36 (LR_SEL/ADDR open).
+
+Example:
+
+ ssm4567: ssm4567@34 {
+ compatible = "adi,ssm4567";
+ reg = <0x34>;
+ };
diff --git a/dts/Bindings/sound/st,sta350.txt b/dts/Bindings/sound/st,sta350.txt
index b7e71bf..307398e 100644
--- a/dts/Bindings/sound/st,sta350.txt
+++ b/dts/Bindings/sound/st,sta350.txt
@@ -33,7 +33,7 @@ Optional properties:
0: Channel 1
1: Channel 2
2: Channel 3
- If parameter is missing, channel 1 is choosen.
+ If parameter is missing, channel 1 is chosen.
This properties have to be specified as '/bits/ 8' values.
- st,thermal-warning-recover:
diff --git a/dts/Bindings/spi/fsl-imx-cspi.txt b/dts/Bindings/spi/fsl-imx-cspi.txt
index 4256a6d..aad527b 100644
--- a/dts/Bindings/spi/fsl-imx-cspi.txt
+++ b/dts/Bindings/spi/fsl-imx-cspi.txt
@@ -7,6 +7,9 @@ Required properties:
- interrupts : Should contain CSPI/eCSPI interrupt
- fsl,spi-num-chipselects : Contains the number of the chipselect
- cs-gpios : Specifies the gpio pins to be used for chipselects.
+- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request names should include "tx" and "rx" if present.
Example:
@@ -19,4 +22,6 @@ ecspi@70010000 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */
<&gpio3 25 0>; /* GPIO3_25 */
+ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
+ dma-names = "rx", "tx";
};
diff --git a/dts/Bindings/spi/sh-msiof.txt b/dts/Bindings/spi/sh-msiof.txt
index f24baf3..d11c372 100644
--- a/dts/Bindings/spi/sh-msiof.txt
+++ b/dts/Bindings/spi/sh-msiof.txt
@@ -6,8 +6,17 @@ Required properties:
"renesas,sh-mobile-msiof" for SH Mobile series.
Examples with soctypes are:
"renesas,msiof-r8a7790" (R-Car H2)
- "renesas,msiof-r8a7791" (R-Car M2)
-- reg : Offset and length of the register set for the device
+ "renesas,msiof-r8a7791" (R-Car M2-W)
+ "renesas,msiof-r8a7792" (R-Car V2H)
+ "renesas,msiof-r8a7793" (R-Car M2-N)
+ "renesas,msiof-r8a7794" (R-Car E2)
+- reg : A list of offsets and lengths of the register sets for
+ the device.
+ If only one register set is present, it is to be used
+ by both the CPU and the DMA engine.
+ If two register sets are present, the first is to be
+ used by the CPU, and the second is to be used by the
+ DMA engine.
- interrupt-parent : The phandle for the interrupt controller that
services interrupts for this device
- interrupts : Interrupt specifier
@@ -17,12 +26,16 @@ Required properties:
Optional properties:
- clocks : Must contain a reference to the functional clock.
- num-cs : Total number of chip-selects (default is 1)
+- dmas : Must contain a list of two references to DMA
+ specifiers, one for transmission, and one for
+ reception.
+- dma-names : Must contain a list of two DMA names, "tx" and "rx".
Optional properties, deprecated for soctype-specific bindings:
- renesas,tx-fifo-size : Overrides the default tx fifo size given in words
(default is 64)
- renesas,rx-fifo-size : Overrides the default rx fifo size given in words
- (default is 64, or 256 on R-Car H2 and M2)
+ (default is 64, or 256 on R-Car Gen2)
Pinctrl properties might be needed, too. See
Documentation/devicetree/bindings/pinctrl/renesas,*.
@@ -31,9 +44,11 @@ Example:
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7791";
- reg = <0 0xe6e20000 0 0x0064>;
+ reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
+ dmas = <&dmac0 0x51>, <&dmac0 0x52>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
diff --git a/dts/Bindings/spi/spi-davinci.txt b/dts/Bindings/spi/spi-davinci.txt
index f80887b..12ecfe9 100644
--- a/dts/Bindings/spi/spi-davinci.txt
+++ b/dts/Bindings/spi/spi-davinci.txt
@@ -1,5 +1,10 @@
Davinci SPI controller device bindings
+Links on DM:
+Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
+dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
+OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
+
Required properties:
- #address-cells: number of cells required to define a chip select
address on the SPI bus. Should be set to 1.
@@ -24,6 +29,30 @@ Optional:
cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
where first three are internal CS and last two are GPIO CS.
+Optional properties for slave devices:
+SPI slave nodes can contain the following properties.
+Not all SPI Peripherals from Texas Instruments support this.
+Please check SPI peripheral documentation for a device before using these.
+
+- ti,spi-wdelay : delay between transmission of words
+ (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module
+ clock periods.
+
+ delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period
+
+Below is timing diagram which shows functional meaning of
+"ti,spi-wdelay" parameter.
+
+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
+SPI_CLK | | | | | | | | | | | | | | | |
+ +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-
+
+SPI_SOMI/SIMO+-----------------+ +-----------
+ +----------+ word1 +---------------------------+word2
+ +-----------------+ +-----------
+ WDELAY
+ <-------------------------->
+
Example of a NOR flash slave device (n25q032) connected to DaVinci
SPI controller device over the SPI bus.
@@ -43,6 +72,7 @@ spi0:spi@20BF0000 {
compatible = "st,m25p32";
spi-max-frequency = <25000000>;
reg = <0>;
+ ti,spi-wdelay = <8>;
partition@0 {
label = "u-boot-spl";
diff --git a/dts/Bindings/spi/spi-fsl-dspi.txt b/dts/Bindings/spi/spi-fsl-dspi.txt
index 5376de4..cbbe16e 100644
--- a/dts/Bindings/spi/spi-fsl-dspi.txt
+++ b/dts/Bindings/spi/spi-fsl-dspi.txt
@@ -10,7 +10,12 @@ Required properties:
- pinctrl-names: must contain a "default" entry.
- spi-num-chipselects : the number of the chipselect signals.
- bus-num : the slave chip chipselect signal number.
-- big-endian : if DSPI modudle is big endian, the bool will be set in node.
+
+Optional property:
+- big-endian: If present the dspi device's registers are implemented
+ in big endian mode, otherwise in native mode(same with CPU), for more
+ detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
+
Example:
dspi0@4002c000 {
diff --git a/dts/Bindings/spi/spi-orion.txt b/dts/Bindings/spi/spi-orion.txt
index a3ff50f..50c3a3d 100644
--- a/dts/Bindings/spi/spi-orion.txt
+++ b/dts/Bindings/spi/spi-orion.txt
@@ -1,7 +1,7 @@
Marvell Orion SPI device
Required properties:
-- compatible : should be "marvell,orion-spi".
+- compatible : should be "marvell,orion-spi" or "marvell,armada-370-spi".
- reg : offset and length of the register set for the device
- cell-index : Which of multiple SPI controllers is this.
Optional properties:
diff --git a/dts/Bindings/spi/spi-rspi.txt b/dts/Bindings/spi/spi-rspi.txt
index d57d82a..8f4169f 100644
--- a/dts/Bindings/spi/spi-rspi.txt
+++ b/dts/Bindings/spi/spi-rspi.txt
@@ -11,7 +11,10 @@ Required properties:
- "renesas,rspi-sh7757" (SH)
- "renesas,rspi-r7s72100" (RZ/A1H)
- "renesas,qspi-r8a7790" (R-Car H2)
- - "renesas,qspi-r8a7791" (R-Car M2)
+ - "renesas,qspi-r8a7791" (R-Car M2-W)
+ - "renesas,qspi-r8a7792" (R-Car V2H)
+ - "renesas,qspi-r8a7793" (R-Car M2-N)
+ - "renesas,qspi-r8a7794" (R-Car E2)
- reg : Address start and address range size of the device
- interrupts : A list of interrupt-specifiers, one for each entry in
interrupt-names.
@@ -30,6 +33,9 @@ Required properties:
Optional properties:
- clocks : Must contain a reference to the functional clock.
+- dmas : Must contain a list of two references to DMA specifiers,
+ one for transmission, and one for reception.
+- dma-names : Must contain a list of two DMA names, "tx" and "rx".
Pinctrl properties might be needed, too. See
Documentation/devicetree/bindings/pinctrl/renesas,*.
@@ -58,4 +64,6 @@ Examples:
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>;
+ dma-names = "tx", "rx";
};
diff --git a/dts/Bindings/staging/imx-drm/ldb.txt b/dts/Bindings/staging/imx-drm/ldb.txt
index 578a1fc..443bcb6 100644
--- a/dts/Bindings/staging/imx-drm/ldb.txt
+++ b/dts/Bindings/staging/imx-drm/ldb.txt
@@ -56,6 +56,9 @@ Required properties:
- fsl,data-width : should be <18> or <24>
- port: A port node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
+ On i.MX5, the internal two-input-multiplexer is used.
+ Due to hardware limitations, only one port (port@[0,1])
+ can be used for each channel (lvds-channel@[0,1], respectively)
On i.MX6, there should be four ports (port@[0-3]) that correspond
to the four LVDS multiplexer inputs.
@@ -78,6 +81,8 @@ ldb: ldb@53fa8008 {
"di0", "di1";
lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
@@ -86,7 +91,9 @@ ldb: ldb@53fa8008 {
/* ... */
};
- port {
+ port@0 {
+ reg = <0>;
+
lvds0_in: endpoint {
remote-endpoint = <&ipu_di0_lvds0>;
};
@@ -94,6 +101,8 @@ ldb: ldb@53fa8008 {
};
lvds-channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
@@ -102,7 +111,9 @@ ldb: ldb@53fa8008 {
/* ... */
};
- port {
+ port@1 {
+ reg = <1>;
+
lvds1_in: endpoint {
remote-endpoint = <&ipu_di1_lvds1>;
};
diff --git a/dts/Bindings/timer/amlogic,meson6-timer.txt b/dts/Bindings/timer/amlogic,meson6-timer.txt
new file mode 100644
index 0000000..a092053
--- /dev/null
+++ b/dts/Bindings/timer/amlogic,meson6-timer.txt
@@ -0,0 +1,15 @@
+Amlogic Meson6 SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "amlogic,meson6-timer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer
+
+Example:
+
+timer@c1109940 {
+ compatible = "amlogic,meson6-timer";
+ reg = <0xc1109940 0x14>;
+ interrupts = <0 10 1>;
+};
diff --git a/dts/Bindings/timer/renesas,cmt.txt b/dts/Bindings/timer/renesas,cmt.txt
index a17418b..1a05c1b 100644
--- a/dts/Bindings/timer/renesas,cmt.txt
+++ b/dts/Bindings/timer/renesas,cmt.txt
@@ -11,15 +11,47 @@ datasheets.
Required Properties:
- - compatible: must contain one of the following.
- - "renesas,cmt-32" for the 32-bit CMT
+ - compatible: must contain one or more of the following:
+ - "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT
+ (CMT0)
+ - "renesas,cmt-32-sh7372" for the sh7372 32-bit CMT
+ (CMT0)
+ - "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT
+ (CMT0)
+ - "renesas,cmt-32" for all 32-bit CMT without fast clock support
(CMT0 on sh7372, sh73a0 and r8a7740)
- - "renesas,cmt-32-fast" for the 32-bit CMT with fast clock support
+ This is a fallback for the above renesas,cmt-32-* entries.
+
+ - "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast
+ clock support (CMT[234])
+ - "renesas,cmt-32-fast-sh7372" for the sh7372 32-bit CMT with fast
+ clock support (CMT[234])
+ - "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast
+ clock support (CMT[234])
+ - "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support
(CMT[234] on sh7372, sh73a0 and r8a7740)
- - "renesas,cmt-48" for the 48-bit CMT
+ This is a fallback for the above renesas,cmt-32-fast-* entries.
+
+ - "renesas,cmt-48-sh7372" for the sh7372 48-bit CMT
+ (CMT1)
+ - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT
+ (CMT1)
+ - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT
+ (CMT1)
+ - "renesas,cmt-48" for all non-second generation 48-bit CMT
(CMT1 on sh7372, sh73a0 and r8a7740)
- - "renesas,cmt-48-gen2" for the second generation 48-bit CMT
+ This is a fallback for the above renesas,cmt-48-* entries.
+
+ - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT
+ (CMT[01])
+ - "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT
+ (CMT[01])
+ - "renesas,cmt-48-r8a7791" for the r8a7791 48-bit CMT
+ (CMT[01])
+ - "renesas,cmt-48-gen2" for all second generation 48-bit CMT
(CMT[01] on r8a73a4, r8a7790 and r8a7791)
+ This is a fallback for the renesas,cmt-48-r8a73a4,
+ renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries.
- reg: base address and length of the registers block for the timer module.
- interrupts: interrupt-specifier for the timer, one per channel.
@@ -36,7 +68,7 @@ Example: R8A7790 (R-Car H2) CMT0 node
them channels 0 and 1 in the documentation.
cmt0: timer@ffca0000 {
- compatible = "renesas,cmt-48-gen2";
+ compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
<0 142 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/Bindings/timer/renesas,mtu2.txt b/dts/Bindings/timer/renesas,mtu2.txt
index 917453f..d9a8d5a 100644
--- a/dts/Bindings/timer/renesas,mtu2.txt
+++ b/dts/Bindings/timer/renesas,mtu2.txt
@@ -8,7 +8,10 @@ are independent. The MTU2 hardware supports five channels indexed from 0 to 4.
Required Properties:
- - compatible: must contain "renesas,mtu2"
+ - compatible: must be one or more of the following:
+ - "renesas,mtu2-r7s72100" for the r7s72100 MTU2
+ - "renesas,mtu2" for any MTU2
+ This is a fallback for the above renesas,mtu2-* entries
- reg: base address and length of the registers block for the timer module.
@@ -26,7 +29,7 @@ Required Properties:
Example: R7S72100 (RZ/A1H) MTU2 node
mtu2: timer@fcff0000 {
- compatible = "renesas,mtu2";
+ compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>,
<0 146 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/Bindings/timer/renesas,tmu.txt b/dts/Bindings/timer/renesas,tmu.txt
index 425d0c5..7db89fb 100644
--- a/dts/Bindings/timer/renesas,tmu.txt
+++ b/dts/Bindings/timer/renesas,tmu.txt
@@ -8,7 +8,10 @@ are independent. The TMU hardware supports up to three channels.
Required Properties:
- - compatible: must contain "renesas,tmu"
+ - compatible: must contain one or more of the following:
+ - "renesas,tmu-r8a7779" for the r8a7779 TMU
+ - "renesas,tmu" for any TMU.
+ This is a fallback for the above renesas,tmu-* entries
- reg: base address and length of the registers block for the timer module.
@@ -27,7 +30,7 @@ Optional Properties:
Example: R8A7779 (R-Car H1) TMU0 node
tmu0: timer@ffd80000 {
- compatible = "renesas,tmu";
+ compatible = "renesas,tmu-r8a7779", "renesas,tmu";
reg = <0xffd80000 0x30>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
<0 33 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/Bindings/ufs/ufshcd-pltfrm.txt b/dts/Bindings/ufs/ufshcd-pltfrm.txt
index 20468b2..5357919 100644
--- a/dts/Bindings/ufs/ufshcd-pltfrm.txt
+++ b/dts/Bindings/ufs/ufshcd-pltfrm.txt
@@ -8,9 +8,50 @@ Required properties:
- interrupts : <interrupt mapping for UFS host controller IRQ>
- reg : <registers mapping>
+Optional properties:
+- vdd-hba-supply : phandle to UFS host controller supply regulator node
+- vcc-supply : phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
+ or 2.7-3.6V. This boolean property when set, specifies
+ to use low voltage range of 1.7-1.95V. Note for external
+ UFS cards this property is invalid and valid VCC range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
+- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
+- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
+
+- clocks : List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+- freq-table-hz : Array of <min max> operating frequencies stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
Example:
ufshc@0xfc598000 {
compatible = "jedec,ufs-1.1";
reg = <0xfc598000 0x800>;
interrupts = <0 28 0>;
+
+ vdd-hba-supply = <&xxx_reg0>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&xxx_reg1>;
+ vcc-supply-1p8;
+ vccq-supply = <&xxx_reg2>;
+ vccq2-supply = <&xxx_reg3>;
+ vcc-max-microamp = 500000;
+ vccq-max-microamp = 200000;
+ vccq2-max-microamp = 200000;
+
+ clocks = <&core 0>, <&ref 0>, <&iface 0>;
+ clock-names = "core_clk", "ref_clk", "iface_clk";
+ freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;
};
diff --git a/dts/Bindings/usb/ci-hdrc-imx.txt b/dts/Bindings/usb/ci-hdrc-imx.txt
index 1bae71e..38a5480 100644
--- a/dts/Bindings/usb/ci-hdrc-imx.txt
+++ b/dts/Bindings/usb/ci-hdrc-imx.txt
@@ -19,6 +19,7 @@ Optional properties:
- disable-over-current: disable over current detect
- external-vbus-divider: enables off-chip resistor divider for Vbus
- maximum-speed: limit the maximum connection speed to "full-speed".
+- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
Examples:
usb@02184000 { /* USB OTG */
@@ -30,4 +31,5 @@ usb@02184000 { /* USB OTG */
disable-over-current;
external-vbus-divider;
maximum-speed = "full-speed";
+ tpl-support;
};
diff --git a/dts/Bindings/usb/dwc2.txt b/dts/Bindings/usb/dwc2.txt
index 467ddd1..482f815 100644
--- a/dts/Bindings/usb/dwc2.txt
+++ b/dts/Bindings/usb/dwc2.txt
@@ -4,6 +4,9 @@ Platform DesignWare HS OTG USB 2.0 controller
Required properties:
- compatible : One of:
- brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+ - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
+ - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
+ - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
@@ -15,6 +18,8 @@ Optional properties:
- phys: phy provider specifier
- phy-names: shall be "usb2-phy"
Refer to phy/phy-bindings.txt for generic phy consumer properties
+- dr_mode: shall be one of "host", "peripheral" and "otg"
+ Refer to usb/generic.txt
Example:
diff --git a/dts/Bindings/usb/dwc3-st.txt b/dts/Bindings/usb/dwc3-st.txt
new file mode 100644
index 0000000..f9d7025
--- /dev/null
+++ b/dts/Bindings/usb/dwc3-st.txt
@@ -0,0 +1,68 @@
+ST DWC3 glue logic
+
+This file documents the parameters for the dwc3-st driver.
+This driver controls the glue logic used to configure the dwc3 core on
+STiH407 based platforms.
+
+Required properties:
+ - compatible : must be "st,stih407-dwc3"
+ - reg : glue logic base address and USB syscfg ctrl register offset
+ - reg-names : should be "reg-glue" and "syscfg-reg"
+ - st,syscon : should be phandle to system configuration node which
+ encompasses the glue registers
+ - resets : list of phandle and reset specifier pairs. There should be two entries, one
+ for the powerdown and softreset lines of the usb3 IP
+ - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+ with 'reg' property
+
+ - pinctl-names : A pinctrl state named "default" must be defined
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+ - pinctrl-0 : Pin control group
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+ - ranges : allows valid 1:1 translation between child's address space and
+ parent's address space
+
+Sub-nodes:
+The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
+example below. The DT binding details of dwc3 can be found in:
+Documentation/devicetree/bindings/usb/dwc3.txt
+
+NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value
+is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
+or "device".
+
+[1] Documentation/devicetree/bindings/usb/generic.txt
+
+Example:
+
+st_dwc3: dwc3@8f94000 {
+ status = "disabled";
+ compatible = "st,stih407-dwc3";
+ reg = <0x08f94000 0x1000>, <0x110 0x4>;
+ reg-names = "reg-glue", "syscfg-reg";
+ st,syscfg = <&syscfg_core>;
+ resets = <&powerdown STIH407_USB3_POWERDOWN>,
+ <&softreset STIH407_MIPHY2_SOFTRESET>;
+ reset-names = "powerdown",
+ "softreset";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ ranges;
+
+ dwc3: dwc3@9900000 {
+ compatible = "snps,dwc3";
+ reg = <0x09900000 0x100000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
+ dr_mode = "host";
+ phys-names = "usb2-phy", "usb3-phy";
+ phys = <&usb2_picophy2>, <&phy_port2 MIPHY_TYPE_USB>;
+ };
+};
diff --git a/dts/Bindings/usb/ehci-st.txt b/dts/Bindings/usb/ehci-st.txt
new file mode 100644
index 0000000..fb45fa5
--- /dev/null
+++ b/dts/Bindings/usb/ehci-st.txt
@@ -0,0 +1,39 @@
+ST USB EHCI controller
+
+Required properties:
+ - compatible : must be "st,st-ehci-300x"
+ - reg : physical base addresses of the controller and length of memory mapped
+ region
+ - interrupts : one EHCI interrupt should be described here
+ - pinctrl-names : a pinctrl state named "default" must be defined
+ - pinctrl-0 : phandle referencing pin configuration of the USB controller
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+ - clocks : phandle list of usb clocks
+ - clock-names : should be "ic" for interconnect clock and "clk48"
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+ - phys : phandle for the PHY device
+ - phy-names : should be "usb"
+ - resets : phandle + reset specifier pairs to the powerdown and softreset lines
+ of the USB IP
+ - reset-names : should be "power" and "softreset"
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+
+Example:
+
+ ehci1: usb@0xfe203e00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0xfe203e00 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&clk_s_a1_ls 0>;
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB1_POWERDOWN>,
+ <&softreset STIH416_USB1_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
diff --git a/dts/Bindings/usb/mxs-phy.txt b/dts/Bindings/usb/mxs-phy.txt
index 96681c9..379b84a 100644
--- a/dts/Bindings/usb/mxs-phy.txt
+++ b/dts/Bindings/usb/mxs-phy.txt
@@ -5,6 +5,7 @@ Required properties:
* "fsl,imx23-usbphy" for imx23 and imx28
* "fsl,imx6q-usbphy" for imx6dq and imx6dl
* "fsl,imx6sl-usbphy" for imx6sl
+ * "fsl,vf610-usbphy" for Vybrid vf610
* "fsl,imx6sx-usbphy" for imx6sx
"fsl,imx23-usbphy" is still a fallback for other strings
- reg: Should contain registers location and length
diff --git a/dts/Bindings/usb/ohci-st.txt b/dts/Bindings/usb/ohci-st.txt
new file mode 100644
index 0000000..6d83937
--- /dev/null
+++ b/dts/Bindings/usb/ohci-st.txt
@@ -0,0 +1,37 @@
+ST USB OHCI controller
+
+Required properties:
+
+ - compatible : must be "st,st-ohci-300x"
+ - reg : physical base addresses of the controller and length of memory mapped
+ region
+ - interrupts : one OHCI controller interrupt should be described here
+ - clocks : phandle list of usb clocks
+ - clock-names : should be "ic" for interconnect clock and "clk48"
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+ - phys : phandle for the PHY device
+ - phy-names : should be "usb"
+
+ - resets : phandle to the powerdown and reset controller for the USB IP
+ - reset-names : should be "power" and "softreset".
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+
+Example:
+
+ ohci0: usb@0xfe1ffc00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0xfe1ffc00 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB0_POWERDOWN>,
+ <&softreset STIH416_USB0_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
diff --git a/dts/Bindings/usb/qcom,dwc3.txt b/dts/Bindings/usb/qcom,dwc3.txt
new file mode 100644
index 0000000..ca164e7
--- /dev/null
+++ b/dts/Bindings/usb/qcom,dwc3.txt
@@ -0,0 +1,66 @@
+Qualcomm SuperSpeed DWC3 USB SoC controller
+
+Required properties:
+- compatible: should contain "qcom,dwc3"
+- clocks: A list of phandle + clock-specifier pairs for the
+ clocks listed in clock-names
+- clock-names: Should contain the following:
+ "core" Master/Core clock, have to be >= 125 MHz for SS
+ operation and >= 60MHz for HS operation
+
+Optional clocks:
+ "iface" System bus AXI clock. Not present on all platforms
+ "sleep" Sleep clock, used when USB3 core goes into low
+ power mode (U3).
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+Phy documentation is provided in the following places:
+Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
+
+Example device nodes:
+
+ hs_phy: phy@100f8800 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
+
+ ss_phy: phy@100f8830 {
+ compatible = "qcom,dwc3-ss-usb-phy";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
+
+ usb3_0: usb30@0 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ status = "ok";
+
+ dwc3@10000000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000000 0xcd00>;
+ interrupts = <0 205 0x4>;
+ phys = <&hs_phy>, <&ss_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ dr_mode = "host";
+ };
+ };
+
diff --git a/dts/Bindings/usb/renesas_usbhs.txt b/dts/Bindings/usb/renesas_usbhs.txt
new file mode 100644
index 0000000..b08c903
--- /dev/null
+++ b/dts/Bindings/usb/renesas_usbhs.txt
@@ -0,0 +1,24 @@
+Renesas Electronics USBHS driver
+
+Required properties:
+ - compatible: Must contain one of the following:
+ - "renesas,usbhs-r8a7790"
+ - "renesas,usbhs-r8a7791"
+ - reg: Base address and length of the register for the USBHS
+ - interrupts: Interrupt specifier for the USBHS
+ - clocks: A list of phandle + clock specifier pairs
+
+Optional properties:
+ - renesas,buswait: Integer to use BUSWAIT register
+ - renesas,enable-gpio: A gpio specifier to check GPIO determining if USB
+ function should be enabled
+ - phys: phandle + phy specifier pair
+ - phy-names: must be "usb"
+
+Example:
+ usbhs: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7790";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+ };
diff --git a/dts/Bindings/usb/udc-xilinx.txt b/dts/Bindings/usb/udc-xilinx.txt
new file mode 100644
index 0000000..47b4e39
--- /dev/null
+++ b/dts/Bindings/usb/udc-xilinx.txt
@@ -0,0 +1,18 @@
+Xilinx USB2 device controller
+
+Required properties:
+- compatible : Should be "xlnx,usb2-device-4.00.a"
+- reg : Physical base address and size of the USB2
+ device registers map.
+- interrupts : Should contain single irq line of USB2 device
+ controller
+- xlnx,has-builtin-dma : if DMA is included
+
+Example:
+ axi-usb2-device@42e00000 {
+ compatible = "xlnx,usb2-device-4.00.a";
+ interrupts = <0x0 0x39 0x1>;
+ reg = <0x42e00000 0x10000>;
+ xlnx,has-builtin-dma;
+ };
+
diff --git a/dts/Bindings/usb/usb3503.txt b/dts/Bindings/usb/usb3503.txt
index 221ac0d..52493b1 100644
--- a/dts/Bindings/usb/usb3503.txt
+++ b/dts/Bindings/usb/usb3503.txt
@@ -8,8 +8,8 @@ Optional properties:
if I2C is used.
- connect-gpios: Should specify GPIO for connect.
- disabled-ports: Should specify the ports unused.
- '1' or '2' or '3' are availe for this property to describe the port
- number. 1~3 property values are possible to be desribed.
+ '1' or '2' or '3' are available for this property to describe the port
+ number. 1~3 property values are possible to be described.
Do not describe this property if all ports have to be enabled.
- intn-gpios: Should specify GPIO for interrupt.
- reset-gpios: Should specify GPIO for reset.
diff --git a/dts/Bindings/usb/usbmisc-imx.txt b/dts/Bindings/usb/usbmisc-imx.txt
index 97ce94e..c101a4b 100644
--- a/dts/Bindings/usb/usbmisc-imx.txt
+++ b/dts/Bindings/usb/usbmisc-imx.txt
@@ -4,6 +4,7 @@ Required properties:
- #index-cells: Cells used to descibe usb controller index. Should be <1>
- compatible: Should be one of below:
"fsl,imx6q-usbmisc" for imx6q
+ "fsl,vf610-usbmisc" for Vybrid vf610
- reg: Should contain registers location and length
Examples:
diff --git a/dts/Bindings/vendor-prefixes.txt b/dts/Bindings/vendor-prefixes.txt
index ac7269f..723999d 100644
--- a/dts/Bindings/vendor-prefixes.txt
+++ b/dts/Bindings/vendor-prefixes.txt
@@ -14,6 +14,7 @@ allwinner Allwinner Technology Co., Ltd.
altr Altera Corp.
amcc Applied Micro Circuits Corporation (APM, formally AMCC)
amd Advanced Micro Devices (AMD), Inc.
+amlogic Amlogic, Inc.
ams AMS AG
amstaos AMS-Taos Inc.
apm Applied Micro Circuits Corporation (APM)
@@ -29,6 +30,7 @@ calxeda Calxeda
capella Capella Microsystems, Inc
cavium Cavium, Inc.
cdns Cadence Design Systems Inc.
+chipidea Chipidea, Inc
chrp Common Hardware Reference Platform
chunghwa Chunghwa Picture Tubes Ltd.
cirrus Cirrus Logic, Inc.
@@ -38,24 +40,30 @@ dallas Maxim Integrated Products (formerly Dallas Semiconductor)
davicom DAVICOM Semiconductor, Inc.
denx Denx Software Engineering
digi Digi International Inc.
+dlg Dialog Semiconductor
dlink D-Link Corporation
dmo Data Modul AG
ebv EBV Elektronik
edt Emerging Display Technologies
emmicro EM Microelectronic
+energymicro Silicon Laboratories (formerly Energy Micro AS)
epcos EPCOS AG
epfl Ecole Polytechnique Fédérale de Lausanne
epson Seiko Epson Corp.
est ESTeem Wireless Modems
eukrea Eukréa Electromatique
+everest Everest Semiconductor Co. Ltd.
excito Excito
+fcs Fairchild Semiconductor
fsl Freescale Semiconductor
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+geniatech Geniatech, Inc.
globalscale Globalscale Technologies, Inc.
gmt Global Mixed-mode Technology, Inc.
google Google, Inc.
gumstix Gumstix, Inc.
+gw Gateworks Corporation
haoyu Haoyu Microelectronic Co. Ltd.
hisilicon Hisilicon Limited.
honeywell Honeywell
@@ -65,6 +73,7 @@ ibm International Business Machines (IBM)
idt Integrated Device Technologies, Inc.
iom Iomega Corporation
img Imagination Technologies Ltd.
+innolux Innolux Corporation
intel Intel Corporation
intercontrol Inter Control Group
isee ISEE 2007 S.L.
@@ -83,6 +92,7 @@ maxim Maxim Integrated Products
mediatek MediaTek Inc.
micrel Micrel Inc.
microchip Microchip Technology Inc.
+mitsubishi Mitsubishi Electric Corporation
mosaixtech Mosaix Technologies, Inc.
moxa Moxa
mpl MPL AG
@@ -124,21 +134,25 @@ sil Silicon Image
silabs Silicon Laboratories
simtek
sii Seiko Instruments, Inc.
+silergy Silergy Corp.
sirf SiRF Technology, Inc.
+sitronix Sitronix Technology Corporation
smsc Standard Microsystems Corporation
snps Synopsys, Inc.
solidrun SolidRun
+sony Sony Corporation
spansion Spansion Inc.
st STMicroelectronics
ste ST-Ericsson
stericsson ST-Ericsson
synology Synology, Inc.
+thine THine Electronics, Inc.
ti Texas Instruments
tlm Trusted Logic Mobility
toradex Toradex AG
toshiba Toshiba Corporation
toumaz Toumaz
-usi Universal Scientifc Industrial Co., Ltd.
+usi Universal Scientific Industrial Co., Ltd.
v3 V3 Semiconductor
variscite Variscite Ltd.
via VIA Technologies, Inc.
@@ -147,6 +161,7 @@ winbond Winbond Electronics corp.
wlf Wolfson Microelectronics
wm Wondermedia Technologies, Inc.
xes Extreme Engineering Solutions (X-ES)
+xillybus Xillybus Ltd.
xlnx Xilinx
zyxel ZyXEL Communications Corp.
zarlink Zarlink Semiconductor
diff --git a/dts/Bindings/video/adi,adv7123.txt b/dts/Bindings/video/adi,adv7123.txt
new file mode 100644
index 0000000..a6b2b2b
--- /dev/null
+++ b/dts/Bindings/video/adi,adv7123.txt
@@ -0,0 +1,50 @@
+Analog Device ADV7123 Video DAC
+-------------------------------
+
+The ADV7123 is a digital-to-analog converter that outputs VGA signals from a
+parallel video input.
+
+Required properties:
+
+- compatible: Should be "adi,adv7123"
+
+Optional properties:
+
+- psave-gpios: Power save control GPIO
+
+Required nodes:
+
+The ADV7123 has two video ports. Their connections are modeled using the OF
+graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 for DPI input
+- Video port 1 for VGA output
+
+
+Example
+-------
+
+ adv7123: encoder@0 {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adv7123_in: endpoint@0 {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ adv7123_out: endpoint@0 {
+ remote-endpoint = <&vga_connector_in>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/video/atmel,lcdc.txt b/dts/Bindings/video/atmel,lcdc.txt
index b75af94..f059dd0 100644
--- a/dts/Bindings/video/atmel,lcdc.txt
+++ b/dts/Bindings/video/atmel,lcdc.txt
@@ -20,6 +20,9 @@ Required nodes:
- default-mode: a videomode within the display with timing parameters
as specified below.
+Optional properties:
+- lcd-supply: Regulator for LCD supply voltage.
+
Example:
fb0: fb@0x00500000 {
@@ -39,8 +42,8 @@ Atmel LCDC Display
-----------------------------------------------------
Required properties (as per of_videomode_helper):
- - atmel,dmacon: dma controler configuration
- - atmel,lcdcon2: lcd controler configuration
+ - atmel,dmacon: dma controller configuration
+ - atmel,lcdcon2: lcd controller configuration
- atmel,guard-time: lcd guard time (Delay in frame periods)
- bits-per-pixel: lcd panel bit-depth.
diff --git a/dts/Bindings/video/exynos_dsim.txt b/dts/Bindings/video/exynos_dsim.txt
index 31036c6..e74243b 100644
--- a/dts/Bindings/video/exynos_dsim.txt
+++ b/dts/Bindings/video/exynos_dsim.txt
@@ -2,6 +2,7 @@ Exynos MIPI DSI Master
Required properties:
- compatible: value should be one of the following
+ "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
- reg: physical base address and length of the registers set for the device
diff --git a/dts/Bindings/video/fsl,imx-fb.txt b/dts/Bindings/video/fsl,imx-fb.txt
index 0329f60..8c8c2f4 100644
--- a/dts/Bindings/video/fsl,imx-fb.txt
+++ b/dts/Bindings/video/fsl,imx-fb.txt
@@ -20,7 +20,7 @@ Optional properties:
register is not modified as recommended by the datasheet.
- fsl,lpccr: Contrast Control Register value. This property provides the
default value for the contrast control register.
- If that property is ommited, the register is zeroed.
+ If that property is omitted, the register is zeroed.
- fsl,lscr1: LCDC Sharp Configuration Register value.
Example:
diff --git a/dts/Bindings/video/renesas,du.txt b/dts/Bindings/video/renesas,du.txt
new file mode 100644
index 0000000..5102830
--- /dev/null
+++ b/dts/Bindings/video/renesas,du.txt
@@ -0,0 +1,84 @@
+* Renesas R-Car Display Unit (DU)
+
+Required Properties:
+
+ - compatible: must be one of the following.
+ - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
+ - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
+ - "renesas,du-r8a7791" for R8A7791 (R-Car M2) compatible DU
+
+ - reg: A list of base address and length of each memory resource, one for
+ each entry in the reg-names property.
+ - reg-names: Name of the memory resources. The DU requires one memory
+ resource for the DU core (named "du") and one memory resource for each
+ LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
+ index).
+
+ - interrupt-parent: phandle of the parent interrupt controller.
+ - interrupts: Interrupt specifiers for the DU interrupts.
+
+ - clocks: A list of phandles + clock-specifier pairs, one for each entry in
+ the clock-names property.
+ - clock-names: Name of the clocks. This property is model-dependent.
+ - R8A7779 uses a single functional clock. The clock doesn't need to be
+ named.
+ - R8A7790 and R8A7791 use one functional clock per channel and one clock
+ per LVDS encoder. The functional clocks must be named "du.x" with "x"
+ being the channel numerical index. The LVDS clocks must be named
+ "lvds.x" with "x" being the LVDS encoder numerical index.
+
+Required nodes:
+
+The connections to the DU output video ports are modeled using the OF graph
+bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+The following table lists for each supported model the port number
+corresponding to each DU output.
+
+ Port 0 Port1 Port2
+-----------------------------------------------------------------------------
+ R8A7779 (H1) DPAD 0 DPAD 1 -
+ R8A7790 (H2) DPAD LVDS 0 LVDS 1
+ R8A7791 (M2) DPAD LVDS 0 -
+
+
+Example: R8A7790 (R-Car H2) DU
+
+ du: du@feb00000 {
+ compatible = "renesas,du-r8a7790";
+ reg = <0 0xfeb00000 0 0x70000>,
+ <0 0xfeb90000 0 0x1c>,
+ <0 0xfeb94000 0 0x1c>;
+ reg-names = "du", "lvds.0", "lvds.1";
+ interrupt-parent = <&gic>;
+ interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
+ <0 268 IRQ_TYPE_LEVEL_HIGH>,
+ <0 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7790_CLK_DU0>,
+ <&mstp7_clks R8A7790_CLK_DU1>,
+ <&mstp7_clks R8A7790_CLK_DU2>,
+ <&mstp7_clks R8A7790_CLK_LVDS0>,
+ <&mstp7_clks R8A7790_CLK_LVDS1>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ port@2 {
+ reg = <2>;
+ du_out_lvds1: endpoint {
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/video/samsung-fimd.txt b/dts/Bindings/video/samsung-fimd.txt
index ecc899b..4e6c77c 100644
--- a/dts/Bindings/video/samsung-fimd.txt
+++ b/dts/Bindings/video/samsung-fimd.txt
@@ -9,6 +9,7 @@ Required properties:
"samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
"samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
+ "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
"samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
diff --git a/dts/Bindings/video/thine,thc63lvdm83d b/dts/Bindings/video/thine,thc63lvdm83d
new file mode 100644
index 0000000..527e236
--- /dev/null
+++ b/dts/Bindings/video/thine,thc63lvdm83d
@@ -0,0 +1,50 @@
+THine Electronics THC63LVDM83D LVDS serializer
+----------------------------------------------
+
+The THC63LVDM83D is an LVDS serializer designed to support pixel data
+transmission between a host and a flat panel.
+
+Required properties:
+
+- compatible: Should be "thine,thc63lvdm83d"
+
+Optional properties:
+
+- pwdn-gpios: Power down control GPIO
+
+Required nodes:
+
+The THC63LVDM83D has two video ports. Their connections are modeled using the
+OFgraph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 for CMOS/TTL input
+- Video port 1 for LVDS output
+
+
+Example
+-------
+
+ lvds_enc: encoder@0 {
+ compatible = "thine,thc63lvdm83d";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_enc_in: endpoint@0 {
+ remote-endpoint = <&rgb_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_enc_out: endpoint@0 {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/video/vga-connector.txt b/dts/Bindings/video/vga-connector.txt
new file mode 100644
index 0000000..c727f29
--- /dev/null
+++ b/dts/Bindings/video/vga-connector.txt
@@ -0,0 +1,36 @@
+VGA Connector
+=============
+
+Required properties:
+
+- compatible: "vga-connector"
+
+Optional properties:
+
+- label: a symbolic name for the connector corresponding to a hardware label
+- ddc-i2c-bus: phandle to the I2C bus that is connected to VGA DDC
+
+Required nodes:
+
+The VGA connector internal connections are modeled using the OF graph bindings
+specified in Documentation/devicetree/bindings/graph.txt.
+
+The VGA connector has a single port that must be connected to a video source
+port.
+
+
+Example
+-------
+
+vga0: connector@0 {
+ compatible = "vga-connector";
+ label = "vga";
+
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ vga_connector_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+};
diff --git a/dts/Bindings/staging/xillybus.txt b/dts/Bindings/xillybus/xillybus.txt
index 9e316dc..9e316dc 100644
--- a/dts/Bindings/staging/xillybus.txt
+++ b/dts/Bindings/xillybus/xillybus.txt
diff --git a/dts/include/dt-bindings/clock/exynos3250.h b/dts/include/dt-bindings/clock/exynos3250.h
index b535e9d..961b9c1 100644
--- a/dts/include/dt-bindings/clock/exynos3250.h
+++ b/dts/include/dt-bindings/clock/exynos3250.h
@@ -255,4 +255,31 @@
*/
#define CLK_NR_CLKS 248
+/*
+ * CMU DMC
+ */
+
+#define CLK_FOUT_BPLL 1
+#define CLK_FOUT_EPLL 2
+
+/* Muxes */
+#define CLK_MOUT_MPLL_MIF 8
+#define CLK_MOUT_BPLL 9
+#define CLK_MOUT_DPHY 10
+#define CLK_MOUT_DMC_BUS 11
+#define CLK_MOUT_EPLL 12
+
+/* Dividers */
+#define CLK_DIV_DMC 16
+#define CLK_DIV_DPHY 17
+#define CLK_DIV_DMC_PRE 18
+#define CLK_DIV_DMCP 19
+#define CLK_DIV_DMCD 20
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_DMC 21
+
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
diff --git a/dts/include/dt-bindings/clock/exynos4.h b/dts/include/dt-bindings/clock/exynos4.h
index 459bd2b..34fe28c 100644
--- a/dts/include/dt-bindings/clock/exynos4.h
+++ b/dts/include/dt-bindings/clock/exynos4.h
@@ -115,11 +115,11 @@
#define CLK_SMMU_MFCR 275
#define CLK_G3D 276
#define CLK_G2D 277
-#define CLK_ROTATOR 278 /* Exynos4210 only */
-#define CLK_MDMA 279 /* Exynos4210 only */
-#define CLK_SMMU_G2D 280 /* Exynos4210 only */
-#define CLK_SMMU_ROTATOR 281 /* Exynos4210 only */
-#define CLK_SMMU_MDMA 282 /* Exynos4210 only */
+#define CLK_ROTATOR 278
+#define CLK_MDMA 279
+#define CLK_SMMU_G2D 280
+#define CLK_SMMU_ROTATOR 281
+#define CLK_SMMU_MDMA 282
#define CLK_FIMD0 283
#define CLK_MIE0 284
#define CLK_MDNIE0 285 /* Exynos4412 only */
@@ -234,6 +234,8 @@
#define CLK_MOUT_G3D1 393
#define CLK_MOUT_G3D 394
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
+#define CLK_MOUT_HDMI 396
+#define CLK_MOUT_MIXER 397
/* gate clocks - ppmu */
#define CLK_PPMULEFT 400
diff --git a/dts/include/dt-bindings/clock/hix5hd2-clock.h b/dts/include/dt-bindings/clock/hix5hd2-clock.h
index aad579a..fd29c17 100644
--- a/dts/include/dt-bindings/clock/hix5hd2-clock.h
+++ b/dts/include/dt-bindings/clock/hix5hd2-clock.h
@@ -46,6 +46,7 @@
#define HIX5HD2_SFC_MUX 64
#define HIX5HD2_MMC_MUX 65
#define HIX5HD2_FEPHY_MUX 66
+#define HIX5HD2_SD_MUX 67
/* gate clocks */
#define HIX5HD2_SFC_RST 128
@@ -53,6 +54,32 @@
#define HIX5HD2_MMC_CIU_CLK 130
#define HIX5HD2_MMC_BIU_CLK 131
#define HIX5HD2_MMC_CIU_RST 132
+#define HIX5HD2_FWD_BUS_CLK 133
+#define HIX5HD2_FWD_SYS_CLK 134
+#define HIX5HD2_MAC0_PHY_CLK 135
+#define HIX5HD2_SD_CIU_CLK 136
+#define HIX5HD2_SD_BIU_CLK 137
+#define HIX5HD2_SD_CIU_RST 138
+#define HIX5HD2_WDG0_CLK 139
+#define HIX5HD2_WDG0_RST 140
+#define HIX5HD2_I2C0_CLK 141
+#define HIX5HD2_I2C0_RST 142
+#define HIX5HD2_I2C1_CLK 143
+#define HIX5HD2_I2C1_RST 144
+#define HIX5HD2_I2C2_CLK 145
+#define HIX5HD2_I2C2_RST 146
+#define HIX5HD2_I2C3_CLK 147
+#define HIX5HD2_I2C3_RST 148
+#define HIX5HD2_I2C4_CLK 149
+#define HIX5HD2_I2C4_RST 150
+#define HIX5HD2_I2C5_CLK 151
+#define HIX5HD2_I2C5_RST 152
+
+/* complex */
+#define HIX5HD2_MAC0_CLK 192
+#define HIX5HD2_MAC1_CLK 193
+#define HIX5HD2_SATA_CLK 194
+#define HIX5HD2_USB_CLK 195
#define HIX5HD2_NR_CLKS 256
#endif /* __DTS_HIX5HD2_CLOCK_H */
diff --git a/dts/include/dt-bindings/clock/imx6qdl-clock.h b/dts/include/dt-bindings/clock/imx6qdl-clock.h
index 654151e..ddaef86 100644
--- a/dts/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/dts/include/dt-bindings/clock/imx6qdl-clock.h
@@ -128,7 +128,7 @@
#define IMX6Q_CLK_ECSPI5 116
#define IMX6DL_CLK_I2C4 116
#define IMX6QDL_CLK_ENET 117
-#define IMX6QDL_CLK_ESAI 118
+#define IMX6QDL_CLK_ESAI_EXTAL 118
#define IMX6QDL_CLK_GPT_IPG 119
#define IMX6QDL_CLK_GPT_IPG_PER 120
#define IMX6QDL_CLK_GPU2D_CORE 121
@@ -218,7 +218,36 @@
#define IMX6QDL_CLK_LVDS2_SEL 205
#define IMX6QDL_CLK_LVDS1_GATE 206
#define IMX6QDL_CLK_LVDS2_GATE 207
-#define IMX6QDL_CLK_ESAI_AHB 208
-#define IMX6QDL_CLK_END 209
+#define IMX6QDL_CLK_ESAI_IPG 208
+#define IMX6QDL_CLK_ESAI_MEM 209
+#define IMX6QDL_CLK_ASRC_IPG 210
+#define IMX6QDL_CLK_ASRC_MEM 211
+#define IMX6QDL_CLK_LVDS1_IN 212
+#define IMX6QDL_CLK_LVDS2_IN 213
+#define IMX6QDL_CLK_ANACLK1 214
+#define IMX6QDL_CLK_ANACLK2 215
+#define IMX6QDL_PLL1_BYPASS_SRC 216
+#define IMX6QDL_PLL2_BYPASS_SRC 217
+#define IMX6QDL_PLL3_BYPASS_SRC 218
+#define IMX6QDL_PLL4_BYPASS_SRC 219
+#define IMX6QDL_PLL5_BYPASS_SRC 220
+#define IMX6QDL_PLL6_BYPASS_SRC 221
+#define IMX6QDL_PLL7_BYPASS_SRC 222
+#define IMX6QDL_CLK_PLL1 223
+#define IMX6QDL_CLK_PLL2 224
+#define IMX6QDL_CLK_PLL3 225
+#define IMX6QDL_CLK_PLL4 226
+#define IMX6QDL_CLK_PLL5 227
+#define IMX6QDL_CLK_PLL6 228
+#define IMX6QDL_CLK_PLL7 229
+#define IMX6QDL_PLL1_BYPASS 230
+#define IMX6QDL_PLL2_BYPASS 231
+#define IMX6QDL_PLL3_BYPASS 232
+#define IMX6QDL_PLL4_BYPASS 233
+#define IMX6QDL_PLL5_BYPASS 234
+#define IMX6QDL_PLL6_BYPASS 235
+#define IMX6QDL_PLL7_BYPASS 236
+#define IMX6QDL_CLK_GPT_3M 237
+#define IMX6QDL_CLK_END 238
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/dts/include/dt-bindings/clock/imx6sl-clock.h b/dts/include/dt-bindings/clock/imx6sl-clock.h
index b91dd46..9ce4e42 100644
--- a/dts/include/dt-bindings/clock/imx6sl-clock.h
+++ b/dts/include/dt-bindings/clock/imx6sl-clock.h
@@ -146,6 +146,34 @@
#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
#define IMX6SL_CLK_SPBA 134
#define IMX6SL_CLK_ENET 135
-#define IMX6SL_CLK_END 136
+#define IMX6SL_CLK_LVDS1_SEL 136
+#define IMX6SL_CLK_LVDS1_OUT 137
+#define IMX6SL_CLK_LVDS1_IN 138
+#define IMX6SL_CLK_ANACLK1 139
+#define IMX6SL_PLL1_BYPASS_SRC 140
+#define IMX6SL_PLL2_BYPASS_SRC 141
+#define IMX6SL_PLL3_BYPASS_SRC 142
+#define IMX6SL_PLL4_BYPASS_SRC 143
+#define IMX6SL_PLL5_BYPASS_SRC 144
+#define IMX6SL_PLL6_BYPASS_SRC 145
+#define IMX6SL_PLL7_BYPASS_SRC 146
+#define IMX6SL_CLK_PLL1 147
+#define IMX6SL_CLK_PLL2 148
+#define IMX6SL_CLK_PLL3 149
+#define IMX6SL_CLK_PLL4 150
+#define IMX6SL_CLK_PLL5 151
+#define IMX6SL_CLK_PLL6 152
+#define IMX6SL_CLK_PLL7 153
+#define IMX6SL_PLL1_BYPASS 154
+#define IMX6SL_PLL2_BYPASS 155
+#define IMX6SL_PLL3_BYPASS 156
+#define IMX6SL_PLL4_BYPASS 157
+#define IMX6SL_PLL5_BYPASS 158
+#define IMX6SL_PLL6_BYPASS 159
+#define IMX6SL_PLL7_BYPASS 160
+#define IMX6SL_CLK_SSI1_IPG 161
+#define IMX6SL_CLK_SSI2_IPG 162
+#define IMX6SL_CLK_SSI3_IPG 163
+#define IMX6SL_CLK_END 164
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/dts/include/dt-bindings/clock/imx6sx-clock.h b/dts/include/dt-bindings/clock/imx6sx-clock.h
index 421d8bb..9957091 100644
--- a/dts/include/dt-bindings/clock/imx6sx-clock.h
+++ b/dts/include/dt-bindings/clock/imx6sx-clock.h
@@ -251,6 +251,29 @@
#define IMX6SX_CLK_SAI2_IPG 238
#define IMX6SX_CLK_ESAI_IPG 239
#define IMX6SX_CLK_ESAI_MEM 240
-#define IMX6SX_CLK_CLK_END 241
+#define IMX6SX_CLK_LVDS1_IN 241
+#define IMX6SX_CLK_ANACLK1 242
+#define IMX6SX_PLL1_BYPASS_SRC 243
+#define IMX6SX_PLL2_BYPASS_SRC 244
+#define IMX6SX_PLL3_BYPASS_SRC 245
+#define IMX6SX_PLL4_BYPASS_SRC 246
+#define IMX6SX_PLL5_BYPASS_SRC 247
+#define IMX6SX_PLL6_BYPASS_SRC 248
+#define IMX6SX_PLL7_BYPASS_SRC 249
+#define IMX6SX_CLK_PLL1 250
+#define IMX6SX_CLK_PLL2 251
+#define IMX6SX_CLK_PLL3 252
+#define IMX6SX_CLK_PLL4 253
+#define IMX6SX_CLK_PLL5 254
+#define IMX6SX_CLK_PLL6 255
+#define IMX6SX_CLK_PLL7 256
+#define IMX6SX_PLL1_BYPASS 257
+#define IMX6SX_PLL2_BYPASS 258
+#define IMX6SX_PLL3_BYPASS 259
+#define IMX6SX_PLL4_BYPASS 260
+#define IMX6SX_PLL5_BYPASS 261
+#define IMX6SX_PLL6_BYPASS 262
+#define IMX6SX_PLL7_BYPASS 263
+#define IMX6SX_CLK_CLK_END 264
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/dts/include/dt-bindings/clock/maxim,max77686.h b/dts/include/dt-bindings/clock/maxim,max77686.h
new file mode 100644
index 0000000..7b28b09
--- /dev/null
+++ b/dts/include/dt-bindings/clock/maxim,max77686.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77686 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77686_CLK_AP 0
+#define MAX77686_CLK_CP 1
+#define MAX77686_CLK_PMIC 2
+
+/* Total number of clocks. */
+#define MAX77686_CLKS_NUM (MAX77686_CLK_PMIC + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */
diff --git a/dts/include/dt-bindings/clock/maxim,max77802.h b/dts/include/dt-bindings/clock/maxim,max77802.h
new file mode 100644
index 0000000..997312e
--- /dev/null
+++ b/dts/include/dt-bindings/clock/maxim,max77802.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP 0
+#define MAX77802_CLK_32K_CP 1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */
diff --git a/dts/include/dt-bindings/clock/pxa-clock.h b/dts/include/dt-bindings/clock/pxa-clock.h
new file mode 100644
index 0000000..e65803b
--- /dev/null
+++ b/dts/include/dt-bindings/clock/pxa-clock.h
@@ -0,0 +1,77 @@
+/*
+ * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre
+ * Copyright (C) 2014 Robert Jarzmik
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__
+#define __DT_BINDINGS_CLOCK_PXA2XX_H__
+
+#define CLK_NONE 0
+#define CLK_1WIRE 1
+#define CLK_AC97 2
+#define CLK_AC97CONF 3
+#define CLK_ASSP 4
+#define CLK_BOOT 5
+#define CLK_BTUART 6
+#define CLK_CAMERA 7
+#define CLK_CIR 8
+#define CLK_CORE 9
+#define CLK_DMC 10
+#define CLK_FFUART 11
+#define CLK_FICP 12
+#define CLK_GPIO 13
+#define CLK_HSIO2 14
+#define CLK_HWUART 15
+#define CLK_I2C 16
+#define CLK_I2S 17
+#define CLK_IM 18
+#define CLK_INC 19
+#define CLK_ISC 20
+#define CLK_KEYPAD 21
+#define CLK_LCD 22
+#define CLK_MEMC 23
+#define CLK_MEMSTK 24
+#define CLK_MINI_IM 25
+#define CLK_MINI_LCD 26
+#define CLK_MMC 27
+#define CLK_MMC1 28
+#define CLK_MMC2 29
+#define CLK_MMC3 30
+#define CLK_MSL 31
+#define CLK_MSL0 32
+#define CLK_MVED 33
+#define CLK_NAND 34
+#define CLK_NSSP 35
+#define CLK_OSTIMER 36
+#define CLK_PWM0 37
+#define CLK_PWM1 38
+#define CLK_PWM2 39
+#define CLK_PWM3 40
+#define CLK_PWRI2C 41
+#define CLK_PXA300_GCU 42
+#define CLK_PXA320_GCU 43
+#define CLK_SMC 44
+#define CLK_SSP 45
+#define CLK_SSP1 46
+#define CLK_SSP2 47
+#define CLK_SSP3 48
+#define CLK_SSP4 49
+#define CLK_STUART 50
+#define CLK_TOUCH 51
+#define CLK_TPM 52
+#define CLK_UDC 53
+#define CLK_USB 54
+#define CLK_USB2 55
+#define CLK_USBH 56
+#define CLK_USBHOST 57
+#define CLK_USIM 58
+#define CLK_USIM1 59
+#define CLK_USMI0 60
+#define CLK_MAX 61
+
+#endif
diff --git a/dts/include/dt-bindings/clock/r8a7740-clock.h b/dts/include/dt-bindings/clock/r8a7740-clock.h
new file mode 100644
index 0000000..f6b4b0f
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7740-clock.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
+#define __DT_BINDINGS_CLOCK_R8A7740_H__
+
+/* CPG */
+#define R8A7740_CLK_SYSTEM 0
+#define R8A7740_CLK_PLLC0 1
+#define R8A7740_CLK_PLLC1 2
+#define R8A7740_CLK_PLLC2 3
+#define R8A7740_CLK_R 4
+#define R8A7740_CLK_USB24S 5
+#define R8A7740_CLK_I 6
+#define R8A7740_CLK_ZG 7
+#define R8A7740_CLK_B 8
+#define R8A7740_CLK_M1 9
+#define R8A7740_CLK_HP 10
+#define R8A7740_CLK_HPP 11
+#define R8A7740_CLK_USBP 12
+#define R8A7740_CLK_S 13
+#define R8A7740_CLK_ZB 14
+#define R8A7740_CLK_M3 15
+#define R8A7740_CLK_CP 16
+
+/* MSTP1 */
+#define R8A7740_CLK_CEU21 28
+#define R8A7740_CLK_CEU20 27
+#define R8A7740_CLK_TMU0 25
+#define R8A7740_CLK_LCDC1 17
+#define R8A7740_CLK_IIC0 16
+#define R8A7740_CLK_TMU1 11
+#define R8A7740_CLK_LCDC0 0
+
+/* MSTP2 */
+#define R8A7740_CLK_SCIFA6 30
+#define R8A7740_CLK_SCIFA7 22
+#define R8A7740_CLK_DMAC1 18
+#define R8A7740_CLK_DMAC2 17
+#define R8A7740_CLK_DMAC3 16
+#define R8A7740_CLK_USBDMAC 14
+#define R8A7740_CLK_SCIFA5 7
+#define R8A7740_CLK_SCIFB 6
+#define R8A7740_CLK_SCIFA0 4
+#define R8A7740_CLK_SCIFA1 3
+#define R8A7740_CLK_SCIFA2 2
+#define R8A7740_CLK_SCIFA3 1
+#define R8A7740_CLK_SCIFA4 0
+
+/* MSTP3 */
+#define R8A7740_CLK_CMT1 29
+#define R8A7740_CLK_FSI 28
+#define R8A7740_CLK_IIC1 23
+#define R8A7740_CLK_USBF 20
+#define R8A7740_CLK_SDHI0 14
+#define R8A7740_CLK_SDHI1 13
+#define R8A7740_CLK_MMC 12
+#define R8A7740_CLK_GETHER 9
+#define R8A7740_CLK_TPU0 4
+
+/* MSTP4 */
+#define R8A7740_CLK_USBH 16
+#define R8A7740_CLK_SDHI2 15
+#define R8A7740_CLK_USBFUNC 7
+#define R8A7740_CLK_USBPHY 6
+
+/* SUBCK* */
+#define R8A7740_CLK_SUBCK 9
+#define R8A7740_CLK_SUBCK2 10
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a7790-clock.h b/dts/include/dt-bindings/clock/r8a7790-clock.h
index f929a79..8ea7ab0 100644
--- a/dts/include/dt-bindings/clock/r8a7790-clock.h
+++ b/dts/include/dt-bindings/clock/r8a7790-clock.h
@@ -26,6 +26,7 @@
#define R8A7790_CLK_MSIOF0 0
/* MSTP1 */
+#define R8A7790_CLK_JPU 6
#define R8A7790_CLK_TMU1 11
#define R8A7790_CLK_TMU3 21
#define R8A7790_CLK_TMU2 22
diff --git a/dts/include/dt-bindings/clock/r8a7791-clock.h b/dts/include/dt-bindings/clock/r8a7791-clock.h
index f0d4d10..58c3f49 100644
--- a/dts/include/dt-bindings/clock/r8a7791-clock.h
+++ b/dts/include/dt-bindings/clock/r8a7791-clock.h
@@ -25,6 +25,7 @@
#define R8A7791_CLK_MSIOF0 0
/* MSTP1 */
+#define R8A7791_CLK_JPU 6
#define R8A7791_CLK_TMU1 11
#define R8A7791_CLK_TMU3 21
#define R8A7791_CLK_TMU2 22
diff --git a/dts/include/dt-bindings/clock/r8a7794-clock.h b/dts/include/dt-bindings/clock/r8a7794-clock.h
new file mode 100644
index 0000000..9ac1043
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7794-clock.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_H__
+
+/* CPG */
+#define R8A7794_CLK_MAIN 0
+#define R8A7794_CLK_PLL0 1
+#define R8A7794_CLK_PLL1 2
+#define R8A7794_CLK_PLL3 3
+#define R8A7794_CLK_LB 4
+#define R8A7794_CLK_QSPI 5
+#define R8A7794_CLK_SDH 6
+#define R8A7794_CLK_SD0 7
+#define R8A7794_CLK_Z 8
+
+/* MSTP0 */
+#define R8A7794_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7794_CLK_TMU1 11
+#define R8A7794_CLK_TMU3 21
+#define R8A7794_CLK_TMU2 22
+#define R8A7794_CLK_CMT0 24
+#define R8A7794_CLK_TMU0 25
+
+/* MSTP2 */
+#define R8A7794_CLK_SCIFA2 2
+#define R8A7794_CLK_SCIFA1 3
+#define R8A7794_CLK_SCIFA0 4
+#define R8A7794_CLK_MSIOF2 5
+#define R8A7794_CLK_SCIFB0 6
+#define R8A7794_CLK_SCIFB1 7
+#define R8A7794_CLK_MSIOF1 8
+#define R8A7794_CLK_SCIFB2 16
+
+/* MSTP3 */
+#define R8A7794_CLK_CMT1 29
+
+/* MSTP5 */
+#define R8A7794_CLK_THERMAL 22
+#define R8A7794_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7794_CLK_HSCIF2 13
+#define R8A7794_CLK_SCIF5 14
+#define R8A7794_CLK_SCIF4 15
+#define R8A7794_CLK_HSCIF1 16
+#define R8A7794_CLK_HSCIF0 17
+#define R8A7794_CLK_SCIF3 18
+#define R8A7794_CLK_SCIF2 19
+#define R8A7794_CLK_SCIF1 20
+#define R8A7794_CLK_SCIF0 21
+
+/* MSTP8 */
+#define R8A7794_CLK_ETHER 13
+
+/* MSTP9 */
+#define R8A7794_CLK_GPIO6 5
+#define R8A7794_CLK_GPIO5 7
+#define R8A7794_CLK_GPIO4 8
+#define R8A7794_CLK_GPIO3 9
+#define R8A7794_CLK_GPIO2 10
+#define R8A7794_CLK_GPIO1 11
+#define R8A7794_CLK_GPIO0 12
+
+/* MSTP11 */
+#define R8A7794_CLK_SCIFA3 6
+#define R8A7794_CLK_SCIFA4 7
+#define R8A7794_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
diff --git a/dts/include/dt-bindings/clock/rk3188-cru-common.h b/dts/include/dt-bindings/clock/rk3188-cru-common.h
index 750ee60..6a37050 100644
--- a/dts/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/dts/include/dt-bindings/clock/rk3188-cru-common.h
@@ -20,6 +20,7 @@
#define PLL_GPLL 4
#define CORE_PERI 5
#define CORE_L2C 6
+#define ARMCLK 7
/* sclk gates (special clocks) */
#define SCLK_UART0 64
diff --git a/dts/include/dt-bindings/clock/rk3288-cru.h b/dts/include/dt-bindings/clock/rk3288-cru.h
index ebcb460..100a08c 100644
--- a/dts/include/dt-bindings/clock/rk3288-cru.h
+++ b/dts/include/dt-bindings/clock/rk3288-cru.h
@@ -19,6 +19,7 @@
#define PLL_CPLL 3
#define PLL_GPLL 4
#define PLL_NPLL 5
+#define ARMCLK 6
/* sclk gates (special clocks) */
#define SCLK_GPU 64
@@ -61,6 +62,15 @@
#define SCLK_LCDC_PWM1 101
#define SCLK_MAC_RX 102
#define SCLK_MAC_TX 103
+#define SCLK_EDP_24M 104
+#define SCLK_EDP 105
+#define SCLK_RGA 106
+#define SCLK_ISP 107
+#define SCLK_ISP_JPE 108
+#define SCLK_HDMI_HDCP 109
+#define SCLK_HDMI_CEC 110
+#define SCLK_HEVC_CABAC 111
+#define SCLK_HEVC_CORE 112
#define DCLK_VOP0 190
#define DCLK_VOP1 191
@@ -75,6 +85,16 @@
#define ACLK_VOP1 198
#define ACLK_CRYPTO 199
#define ACLK_RGA 200
+#define ACLK_RGA_NIU 201
+#define ACLK_IEP 202
+#define ACLK_VIO0_NIU 203
+#define ACLK_VIP 204
+#define ACLK_ISP 205
+#define ACLK_VIO1_NIU 206
+#define ACLK_HEVC 207
+#define ACLK_VCODEC 208
+#define ACLK_CPU 209
+#define ACLK_PERI 210
/* pclk gates */
#define PCLK_GPIO0 320
@@ -112,6 +132,15 @@
#define PCLK_PS2C 352
#define PCLK_TIMER 353
#define PCLK_TZPC 354
+#define PCLK_EDP_CTRL 355
+#define PCLK_MIPI_DSI0 356
+#define PCLK_MIPI_DSI1 357
+#define PCLK_MIPI_CSI 358
+#define PCLK_LVDS_PHY 359
+#define PCLK_HDMI_CTRL 360
+#define PCLK_VIO2_H2P 361
+#define PCLK_CPU 362
+#define PCLK_PERI 363
/* hclk gates */
#define HCLK_GPS 448
@@ -137,8 +166,16 @@
#define HCLK_IEP 468
#define HCLK_ISP 469
#define HCLK_RGA 470
+#define HCLK_VIO_AHB_ARBI 471
+#define HCLK_VIO_NIU 472
+#define HCLK_VIP 473
+#define HCLK_VIO2_H2P 474
+#define HCLK_HEVC 475
+#define HCLK_VCODEC 476
+#define HCLK_CPU 477
+#define HCLK_PERI 478
-#define CLK_NR_CLKS (HCLK_RGA + 1)
+#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_CORE0 0
@@ -276,3 +313,46 @@
#define SRST_USBHOST1_CON 140
#define SRST_USB_ADP 141
#define SRST_ACC_EFUSE 142
+
+#define SRST_CORESIGHT 144
+#define SRST_PD_CORE_AHB_NOC 145
+#define SRST_PD_CORE_APB_NOC 146
+#define SRST_PD_CORE_MP_AXI 147
+#define SRST_GIC 148
+#define SRST_LCDC_PWM0 149
+#define SRST_LCDC_PWM1 150
+#define SRST_VIO0_H2P_BRG 151
+#define SRST_VIO1_H2P_BRG 152
+#define SRST_RGA_H2P_BRG 153
+#define SRST_HEVC 154
+#define SRST_TSADC 159
+
+#define SRST_DDRPHY0 160
+#define SRST_DDRPHY0_APB 161
+#define SRST_DDRCTRL0 162
+#define SRST_DDRCTRL0_APB 163
+#define SRST_DDRPHY0_CTRL 164
+#define SRST_DDRPHY1 165
+#define SRST_DDRPHY1_APB 166
+#define SRST_DDRCTRL1 167
+#define SRST_DDRCTRL1_APB 168
+#define SRST_DDRPHY1_CTRL 169
+#define SRST_DDRMSCH0 170
+#define SRST_DDRMSCH1 171
+#define SRST_CRYPTO 174
+#define SRST_C2C_HOST 175
+
+#define SRST_LCDC1_AXI 176
+#define SRST_LCDC1_AHB 177
+#define SRST_LCDC1_DCLK 178
+#define SRST_UART0 179
+#define SRST_UART1 180
+#define SRST_UART2 181
+#define SRST_UART3 182
+#define SRST_UART4 183
+#define SRST_SIMC 186
+#define SRST_PS2C 187
+#define SRST_TSP 188
+#define SRST_TSP_CLKIN0 189
+#define SRST_TSP_CLKIN1 190
+#define SRST_TSP_27M 191
diff --git a/dts/include/dt-bindings/clock/rockchip,rk808.h b/dts/include/dt-bindings/clock/rockchip,rk808.h
new file mode 100644
index 0000000..1a87343
--- /dev/null
+++ b/dts/include/dt-bindings/clock/rockchip,rk808.h
@@ -0,0 +1,11 @@
+/*
+ * This header provides constants clk index RK808 pmic clkout
+ */
+#ifndef _CLK_ROCKCHIP_RK808
+#define _CLK_ROCKCHIP_RK808
+
+/* CLOCKOUT index */
+#define RK808_CLKOUT0 0
+#define RK808_CLKOUT1 1
+
+#endif
diff --git a/dts/include/dt-bindings/clock/tegra124-car.h b/dts/include/dt-bindings/clock/tegra124-car.h
index 8a4c589..6bac637 100644
--- a/dts/include/dt-bindings/clock/tegra124-car.h
+++ b/dts/include/dt-bindings/clock/tegra124-car.h
@@ -337,6 +337,10 @@
#define TEGRA124_CLK_DSIB_MUX 310
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_XUSB_SS_DIV2 312
-#define TEGRA124_CLK_CLK_MAX 313
+
+#define TEGRA124_CLK_PLL_M_UD 313
+#define TEGRA124_CLK_PLL_C_UD 314
+
+#define TEGRA124_CLK_CLK_MAX 315
#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/dts/include/dt-bindings/clock/vf610-clock.h b/dts/include/dt-bindings/clock/vf610-clock.h
index 00953d9..d6b56b2 100644
--- a/dts/include/dt-bindings/clock/vf610-clock.h
+++ b/dts/include/dt-bindings/clock/vf610-clock.h
@@ -166,6 +166,9 @@
#define VF610_CLK_DMAMUX3 153
#define VF610_CLK_FLEXCAN0_EN 154
#define VF610_CLK_FLEXCAN1_EN 155
-#define VF610_CLK_END 156
+#define VF610_CLK_PLL7_MAIN 156
+#define VF610_CLK_USBPHY0 157
+#define VF610_CLK_USBPHY1 158
+#define VF610_CLK_END 159
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/dts/include/dt-bindings/input/ti-drv260x.h b/dts/include/dt-bindings/input/ti-drv260x.h
new file mode 100644
index 0000000..2626e6d
--- /dev/null
+++ b/dts/include/dt-bindings/input/ti-drv260x.h
@@ -0,0 +1,36 @@
+/*
+ * DRV260X haptics driver family
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Copyright: (C) 2014 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_TI_DRV260X_H
+#define _DT_BINDINGS_TI_DRV260X_H
+
+/* Calibration Types */
+#define DRV260X_LRA_MODE 0x00
+#define DRV260X_LRA_NO_CAL_MODE 0x01
+#define DRV260X_ERM_MODE 0x02
+
+/* Library Selection */
+#define DRV260X_LIB_EMPTY 0x00
+#define DRV260X_ERM_LIB_A 0x01
+#define DRV260X_ERM_LIB_B 0x02
+#define DRV260X_ERM_LIB_C 0x03
+#define DRV260X_ERM_LIB_D 0x04
+#define DRV260X_ERM_LIB_E 0x05
+#define DRV260X_LIB_LRA 0x06
+#define DRV260X_ERM_LIB_F 0x07
+
+#endif
diff --git a/dts/include/dt-bindings/pinctrl/at91.h b/dts/include/dt-bindings/pinctrl/at91.h
index 0fee6ff..bbca3d0 100644
--- a/dts/include/dt-bindings/pinctrl/at91.h
+++ b/dts/include/dt-bindings/pinctrl/at91.h
@@ -20,6 +20,11 @@
#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
+#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
+
#define AT91_PIOA 0
#define AT91_PIOB 1
#define AT91_PIOC 2
diff --git a/dts/include/dt-bindings/pinctrl/rockchip.h b/dts/include/dt-bindings/pinctrl/rockchip.h
index cd5788b..743e66a 100644
--- a/dts/include/dt-bindings/pinctrl/rockchip.h
+++ b/dts/include/dt-bindings/pinctrl/rockchip.h
@@ -28,5 +28,7 @@
#define RK_FUNC_GPIO 0
#define RK_FUNC_1 1
#define RK_FUNC_2 2
+#define RK_FUNC_3 3
+#define RK_FUNC_4 4
#endif
diff --git a/dts/include/dt-bindings/sound/cs35l32.h b/dts/include/dt-bindings/sound/cs35l32.h
new file mode 100644
index 0000000..0c6d6a3
--- /dev/null
+++ b/dts/include/dt-bindings/sound/cs35l32.h
@@ -0,0 +1,26 @@
+#ifndef __DT_CS35L32_H
+#define __DT_CS35L32_H
+
+#define CS35L32_BOOST_MGR_AUTO 0
+#define CS35L32_BOOST_MGR_AUTO_AUDIO 1
+#define CS35L32_BOOST_MGR_BYPASS 2
+#define CS35L32_BOOST_MGR_FIXED 3
+
+#define CS35L32_DATA_CFG_LR_VP 0
+#define CS35L32_DATA_CFG_LR_STAT 1
+#define CS35L32_DATA_CFG_LR 2
+#define CS35L32_DATA_CFG_LR_VPSTAT 3
+
+#define CS35L32_BATT_THRESH_3_1V 0
+#define CS35L32_BATT_THRESH_3_2V 1
+#define CS35L32_BATT_THRESH_3_3V 2
+#define CS35L32_BATT_THRESH_3_4V 3
+
+#define CS35L32_BATT_RECOV_3_1V 0
+#define CS35L32_BATT_RECOV_3_2V 1
+#define CS35L32_BATT_RECOV_3_3V 2
+#define CS35L32_BATT_RECOV_3_4V 3
+#define CS35L32_BATT_RECOV_3_5V 4
+#define CS35L32_BATT_RECOV_3_6V 5
+
+#endif /* __DT_CS35L32_H */
diff --git a/dts/src/arm/am335x-bone-common.dtsi b/dts/src/arm/am335x-bone-common.dtsi
index bde1777..6cc25ed 100644
--- a/dts/src/arm/am335x-bone-common.dtsi
+++ b/dts/src/arm/am335x-bone-common.dtsi
@@ -7,9 +7,6 @@
*/
/ {
- model = "TI AM335x BeagleBone";
- compatible = "ti,am335x-bone", "ti,am33xx";
-
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
@@ -227,6 +224,7 @@
&tps {
regulators {
dcdc1_reg: regulator@0 {
+ regulator-name = "vdds_dpr";
regulator-always-on;
};
@@ -249,18 +247,22 @@
};
ldo1_reg: regulator@3 {
+ regulator-name = "vio,vrtc,vdds";
regulator-always-on;
};
ldo2_reg: regulator@4 {
+ regulator-name = "vdd_3v3aux";
regulator-always-on;
};
ldo3_reg: regulator@5 {
+ regulator-name = "vdd_1v8";
regulator-always-on;
};
ldo4_reg: regulator@6 {
+ regulator-name = "vdd_3v3a";
regulator-always-on;
};
};
diff --git a/dts/src/arm/am335x-bone.dts b/dts/src/arm/am335x-bone.dts
index 94ee427..83d40f7 100644
--- a/dts/src/arm/am335x-bone.dts
+++ b/dts/src/arm/am335x-bone.dts
@@ -10,6 +10,11 @@
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
+/ {
+ model = "TI AM335x BeagleBone";
+ compatible = "ti,am335x-bone", "ti,am33xx";
+};
+
&ldo3_reg {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
diff --git a/dts/src/arm/am335x-boneblack.dts b/dts/src/arm/am335x-boneblack.dts
index 305975d..901739f 100644
--- a/dts/src/arm/am335x-boneblack.dts
+++ b/dts/src/arm/am335x-boneblack.dts
@@ -10,6 +10,11 @@
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
+/ {
+ model = "TI AM335x BeagleBone Black";
+ compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+};
+
&ldo3_reg {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
diff --git a/dts/src/arm/am33xx.dtsi b/dts/src/arm/am33xx.dtsi
index 3a0a161..8318105 100644
--- a/dts/src/arm/am33xx.dtsi
+++ b/dts/src/arm/am33xx.dtsi
@@ -132,11 +132,15 @@
};
};
+ cm: syscon@44e10000 {
+ compatible = "ti,am33xx-controlmodule", "syscon";
+ reg = <0x44e10000 0x800>;
+ };
+
intc: interrupt-controller@48200000 {
- compatible = "ti,omap2-intc";
+ compatible = "ti,am33xx-intc";
interrupt-controller;
#interrupt-cells = <1>;
- ti,intc-size = <128>;
reg = <0x48200000 0x1000>;
};
@@ -354,6 +358,10 @@
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
+ mbox_wkupm3: wkup_m3 {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <0 0 3>;
+ };
};
timer1: timer@44e31000 {
@@ -696,6 +704,7 @@
*/
interrupts = <40 41 42 43>;
ranges;
+ syscon = <&cm>;
status = "disabled";
davinci_mdio: mdio@4a101000 {
@@ -726,9 +735,8 @@
};
ocmcram: ocmcram@40300000 {
- compatible = "ti,am3352-ocmcram";
- reg = <0x40300000 0x10000>;
- ti,hwmods = "ocmcram";
+ compatible = "mmio-sram";
+ reg = <0x40300000 0x10000>; /* 64k */
};
wkup_m3: wkup_m3@44d00000 {
diff --git a/dts/src/arm/am4372.dtsi b/dts/src/arm/am4372.dtsi
index 8689949..46660ff 100644
--- a/dts/src/arm/am4372.dtsi
+++ b/dts/src/arm/am4372.dtsi
@@ -58,10 +58,12 @@
};
am43xx_pinmux: pinmux@44e10800 {
- compatible = "pinctrl-single";
+ compatible = "ti,am437-padconf", "pinctrl-single";
reg = <0x44e10800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
@@ -168,6 +170,10 @@
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
+ mbox_wkupm3: wkup_m3 {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <0 0 3>;
+ };
};
timer1: timer@44e31000 {
@@ -885,6 +891,11 @@
clock-names = "fck";
};
};
+
+ ocmcram: ocmcram@40300000 {
+ compatible = "mmio-sram";
+ reg = <0x40300000 0x40000>; /* 256k */
+ };
};
};
diff --git a/dts/src/arm/armada-370-db.dts b/dts/src/arm/armada-370-db.dts
index 416f4e5..a495e58 100644
--- a/dts/src/arm/armada-370-db.dts
+++ b/dts/src/arm/armada-370-db.dts
@@ -43,6 +43,8 @@
};
mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
@@ -53,11 +55,15 @@
};
ethernet@70000 {
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
diff --git a/dts/src/arm/armada-370-mirabox.dts b/dts/src/arm/armada-370-mirabox.dts
index 097df7d..2b6d24e 100644
--- a/dts/src/arm/armada-370-mirabox.dts
+++ b/dts/src/arm/armada-370-mirabox.dts
@@ -91,6 +91,8 @@
};
mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
@@ -100,11 +102,15 @@
};
};
ethernet@70000 {
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
diff --git a/dts/src/arm/armada-370-netgear-rn102.dts b/dts/src/arm/armada-370-netgear-rn102.dts
index d6d572e..3aebd93 100644
--- a/dts/src/arm/armada-370-netgear-rn102.dts
+++ b/dts/src/arm/armada-370-netgear-rn102.dts
@@ -101,12 +101,16 @@
};
mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
};
ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
@@ -122,7 +126,7 @@
status = "okay";
isl12057: isl12057@68 {
- compatible = "isl,isl12057";
+ compatible = "isil,isl12057";
reg = <0x68>;
};
@@ -143,6 +147,10 @@
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
+ /* Use Hardware BCH ECC */
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
partition@0 {
label = "u-boot";
reg = <0x0000000 0x180000>; /* 1.5MB */
diff --git a/dts/src/arm/armada-370-netgear-rn104.dts b/dts/src/arm/armada-370-netgear-rn104.dts
index c5fe8b5..c2f414b 100644
--- a/dts/src/arm/armada-370-netgear-rn104.dts
+++ b/dts/src/arm/armada-370-netgear-rn104.dts
@@ -86,6 +86,8 @@
};
mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
@@ -96,12 +98,16 @@
};
ethernet@70000 {
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
@@ -117,7 +123,7 @@
status = "okay";
isl12057: isl12057@68 {
- compatible = "isl,isl12057";
+ compatible = "isil,isl12057";
reg = <0x68>;
};
@@ -145,6 +151,10 @@
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
+ /* Use Hardware BCH ECC */
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
partition@0 {
label = "u-boot";
reg = <0x0000000 0x180000>; /* 1.5MB */
diff --git a/dts/src/arm/armada-370-rd.dts b/dts/src/arm/armada-370-rd.dts
index 4169f40..f57a8f8 100644
--- a/dts/src/arm/armada-370-rd.dts
+++ b/dts/src/arm/armada-370-rd.dts
@@ -9,6 +9,15 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
*/
/dts-v1/;
@@ -30,7 +39,7 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
@@ -50,6 +59,18 @@
};
internal-regs {
+ pinctrl {
+ fan_pins: fan-pins {
+ marvell,pins = "mpp8";
+ marvell,function = "gpio";
+ };
+
+ led_pins: led-pins {
+ marvell,pins = "mpp32";
+ marvell,function = "gpio";
+ };
+ };
+
serial@12000 {
status = "okay";
};
@@ -59,6 +80,8 @@
};
mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
@@ -74,6 +97,8 @@
phy-mode = "sgmii";
};
ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
@@ -106,6 +131,26 @@
};
};
+ gpio-fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <0 0 3000 1>;
+ pinctrl-0 = <&fan_pins>;
+ pinctrl-names = "default";
+ };
+
+ gpio_leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ sw_led {
+ label = "370rd:green:sw";
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ };
+ };
+
nand@d0000 {
status = "okay";
num-cs = <1>;
diff --git a/dts/src/arm/armada-370-xp.dtsi b/dts/src/arm/armada-370-xp.dtsi
index 23227e0..83286ec 100644
--- a/dts/src/arm/armada-370-xp.dtsi
+++ b/dts/src/arm/armada-370-xp.dtsi
@@ -110,7 +110,7 @@
};
spi0: spi@10600 {
- compatible = "marvell,orion-spi";
+ compatible = "marvell,armada-370-spi", "marvell,orion-spi";
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
@@ -121,7 +121,7 @@
};
spi1: spi@10680 {
- compatible = "marvell,orion-spi";
+ compatible = "marvell,armada-370-spi", "marvell,orion-spi";
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/armada-370.dtsi b/dts/src/arm/armada-370.dtsi
index 21b588b..6b3c23b 100644
--- a/dts/src/arm/armada-370.dtsi
+++ b/dts/src/arm/armada-370.dtsi
@@ -151,6 +151,25 @@
"mpp62", "mpp60", "mpp58";
marvell,function = "audio";
};
+
+ mdio_pins: mdio-pins {
+ marvell,pins = "mpp17", "mpp18";
+ marvell,function = "ge";
+ };
+
+ ge0_rgmii_pins: ge0-rgmii-pins {
+ marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11", "mpp12",
+ "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "ge0";
+ };
+
+ ge1_rgmii_pins: ge1-rgmii-pins {
+ marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
+ "mpp23", "mpp24", "mpp25", "mpp26",
+ "mpp27", "mpp28", "mpp29", "mpp30";
+ marvell,function = "ge1";
+ };
};
gpio0: gpio@18100 {
@@ -206,6 +225,10 @@
status = "okay";
};
+ sscg@18330 {
+ reg = <0x18330 0x4>;
+ };
+
interrupt-controller@20000 {
reg = <0x20a00 0x1d0>, <0x21870 0x58>;
};
diff --git a/dts/src/arm/armada-375.dtsi b/dts/src/arm/armada-375.dtsi
index c1e49e7..de65714 100644
--- a/dts/src/arm/armada-375.dtsi
+++ b/dts/src/arm/armada-375.dtsi
@@ -185,6 +185,12 @@
};
};
+ rtc@10300 {
+ compatible = "marvell,orion-rtc";
+ reg = <0x10300 0x20>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
spi0: spi@10600 {
compatible = "marvell,orion-spi";
reg = <0x10600 0x50>;
diff --git a/dts/src/arm/armada-xp-netgear-rn2120.dts b/dts/src/arm/armada-xp-netgear-rn2120.dts
index 0cf999a..7d8f328 100644
--- a/dts/src/arm/armada-xp-netgear-rn2120.dts
+++ b/dts/src/arm/armada-xp-netgear-rn2120.dts
@@ -174,7 +174,7 @@
status = "okay";
isl12057: isl12057@68 {
- compatible = "isl,isl12057";
+ compatible = "isil,isl12057";
reg = <0x68>;
};
@@ -223,6 +223,10 @@
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
+ /* Use Hardware BCH ECC */
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
partition@0 {
label = "u-boot";
reg = <0x0000000 0x180000>; /* 1.5MB */
diff --git a/dts/src/arm/at91-sama5d4ek.dts b/dts/src/arm/at91-sama5d4ek.dts
new file mode 100644
index 0000000..b5b8400
--- /dev/null
+++ b/dts/src/arm/at91-sama5d4ek.dts
@@ -0,0 +1,260 @@
+/*
+ * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
+ *
+ * Copyright (C) 2014 Atmel,
+ * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+
+/ {
+ model = "Atmel SAMA5D4-EK";
+ compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
+ };
+
+ memory {
+ reg = <0x20000000 0x20000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ main_clock: clock@0 {
+ compatible = "atmel,osc", "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ ahb {
+ apb {
+ lcd_bus@f0000000 {
+ status = "okay";
+
+ lcd@f0000000 {
+ status = "okay";
+ };
+
+ lcdovl1@f0000140 {
+ status = "okay";
+ };
+
+ lcdovl2@f0000240 {
+ status = "okay";
+ };
+
+ lcdheo1@f0000340 {
+ status = "okay";
+ };
+ };
+
+ adc0: adc@fc034000 {
+ /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
+ atmel,adc-vref = <3300>;
+ /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
+ status = "okay"; /* Enable ADC IIO support */
+ };
+
+ mmc0: mmc@f8000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
+ slot@1 {
+ reg = <1>;
+ bus-width = <4>;
+ cd-gpios = <&pioE 5 0>;
+ };
+ };
+
+ spi0: spi@f8010000 {
+ cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
+ status = "okay";
+ m25p80@0 {
+ compatible = "atmel,at25df321a";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
+
+ i2c0: i2c@f8014000 {
+ status = "okay";
+ };
+
+ macb0: ethernet@f8020000 {
+ phy-mode = "rmii";
+ status = "okay";
+ };
+
+ mmc1: mmc@fc000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+ status = "okay";
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ cd-gpios = <&pioE 6 0>;
+ };
+ };
+
+ usart2: serial@fc008000 {
+ status = "okay";
+ };
+
+ usart3: serial@fc00c000 {
+ status = "okay";
+ };
+
+ usart4: serial@fc010000 {
+ status = "okay";
+ };
+
+ watchdog@fc068640 {
+ status = "okay";
+ };
+
+ pinctrl@fc06a000 {
+ board {
+ pinctrl_mmc0_cd: mmc0_cd {
+ atmel,pins =
+ <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+ pinctrl_mmc1_cd: mmc1_cd {
+ atmel,pins =
+ <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+ pinctrl_usba_vbus: usba_vbus {
+ atmel,pins =
+ <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+ };
+ pinctrl_key_gpio: key_gpio_0 {
+ atmel,pins =
+ <AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
+ };
+ };
+ };
+ };
+
+ usb0: gadget@00400000 {
+ atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+ };
+
+ usb1: ohci@00500000 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */
+ &pioE 11 GPIO_ACTIVE_LOW
+ &pioE 12 GPIO_ACTIVE_LOW
+ >;
+ status = "okay";
+ };
+
+ usb2: ehci@00600000 {
+ status = "okay";
+ };
+
+ nand0: nand@80000000 {
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ atmel,has-pmecc;
+ status = "okay";
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
+
+ bootloaderenv@c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio>;
+
+ pb_user1 {
+ label = "pb_user1";
+ gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
+ linux,code = <0x100>;
+ gpio-key,wakeup;
+ };
+ };
+};
diff --git a/dts/src/arm/at91sam9263.dtsi b/dts/src/arm/at91sam9263.dtsi
index bb23c2d..d68b3c4 100644
--- a/dts/src/arm/at91sam9263.dtsi
+++ b/dts/src/arm/at91sam9263.dtsi
@@ -345,10 +345,14 @@
};
};
- ramc: ramc@ffffe200 {
+ ramc0: ramc@ffffe200 {
compatible = "atmel,at91sam9260-sdramc";
- reg = <0xffffe200 0x200
- 0xffffe800 0x200>;
+ reg = <0xffffe200 0x200>;
+ };
+
+ ramc1: ramc@ffffe800 {
+ compatible = "atmel,at91sam9260-sdramc";
+ reg = <0xffffe800 0x200>;
};
pit: timer@fffffd30 {
@@ -834,6 +838,7 @@
compatible = "atmel,hsmci";
reg = <0xfff80000 0x600>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mci0_clk>;
@@ -845,6 +850,7 @@
compatible = "atmel,hsmci";
reg = <0xfff84000 0x600>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mci1_clk>;
diff --git a/dts/src/arm/at91sam9g20.dtsi b/dts/src/arm/at91sam9g20.dtsi
index 4e0abbd..a50ee58 100644
--- a/dts/src/arm/at91sam9g20.dtsi
+++ b/dts/src/arm/at91sam9g20.dtsi
@@ -22,6 +22,10 @@
compatible = "atmel,at91sam9g20-i2c";
};
+ ssc0: ssc@fffbc000 {
+ compatible = "atmel,at91sam9rl-ssc";
+ };
+
adc0: adc@fffe0000 {
atmel,adc-startup-time = <40>;
};
diff --git a/dts/src/arm/at91sam9g45.dtsi b/dts/src/arm/at91sam9g45.dtsi
index 932a669..d3f6513 100644
--- a/dts/src/arm/at91sam9g45.dtsi
+++ b/dts/src/arm/at91sam9g45.dtsi
@@ -96,8 +96,14 @@
ramc0: ramc@ffffe400 {
compatible = "atmel,at91sam9g45-ddramc";
- reg = <0xffffe400 0x200
- 0xffffe600 0x200>;
+ reg = <0xffffe400 0x200>;
+ clocks = <&ddrck>;
+ clock-names = "ddrck";
+ };
+
+ ramc1: ramc@ffffe600 {
+ compatible = "atmel,at91sam9g45-ddramc";
+ reg = <0xffffe600 0x200>;
clocks = <&ddrck>;
clock-names = "ddrck";
};
@@ -159,7 +165,7 @@
compatible = "atmel,at91rm9200-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
atmel,clk-output-range = <0 133333333>;
atmel,clk-divisors = <1 2 4 3>;
};
@@ -175,7 +181,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
- clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
prog0: prog0 {
#clock-cells = <0>;
@@ -1159,6 +1165,39 @@
atmel,can-isoc;
};
};
+
+ sckc@fffffd50 {
+ compatible = "atmel,at91sam9x5-sckc";
+ reg = <0xfffffd50 0x4>;
+
+ slow_osc: slow_osc {
+ compatible = "atmel,at91sam9x5-clk-slow-osc";
+ #clock-cells = <0>;
+ atmel,startup-time-usec = <1200000>;
+ clocks = <&slow_xtal>;
+ };
+
+ slow_rc_osc: slow_rc_osc {
+ compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+ #clock-cells = <0>;
+ atmel,startup-time-usec = <75>;
+ clock-frequency = <32768>;
+ clock-accuracy = <50000000>;
+ };
+
+ clk32k: slck {
+ compatible = "atmel,at91sam9x5-clk-slow";
+ #clock-cells = <0>;
+ clocks = <&slow_rc_osc &slow_osc>;
+ };
+ };
+
+ rtc@fffffdb0 {
+ compatible = "atmel,at91rm9200-rtc";
+ reg = <0xfffffdb0 0x30>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ status = "disabled";
+ };
};
fb0: fb@0x00500000 {
diff --git a/dts/src/arm/at91sam9m10g45ek.dts b/dts/src/arm/at91sam9m10g45ek.dts
index 96ccc7d..d8dd226 100644
--- a/dts/src/arm/at91sam9m10g45ek.dts
+++ b/dts/src/arm/at91sam9m10g45ek.dts
@@ -160,6 +160,10 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_leds>;
};
+
+ rtc@fffffdb0 {
+ status = "okay";
+ };
};
fb0: fb@0x00500000 {
diff --git a/dts/src/arm/at91sam9n12.dtsi b/dts/src/arm/at91sam9n12.dtsi
index 2bfac31..68eb9ad 100644
--- a/dts/src/arm/at91sam9n12.dtsi
+++ b/dts/src/arm/at91sam9n12.dtsi
@@ -87,6 +87,8 @@
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
+ clocks = <&ddrck>;
+ clock-names = "ddrck";
};
pmc: pmc@fffffc00 {
diff --git a/dts/src/arm/at91sam9n12ek.dts b/dts/src/arm/at91sam9n12ek.dts
index 83d7237..13bb24e 100644
--- a/dts/src/arm/at91sam9n12ek.dts
+++ b/dts/src/arm/at91sam9n12ek.dts
@@ -136,6 +136,8 @@
};
usb0: ohci@00500000 {
+ num-ports = <1>;
+ atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
diff --git a/dts/src/arm/at91sam9rl.dtsi b/dts/src/arm/at91sam9rl.dtsi
index ab56c8b..f0b4352 100644
--- a/dts/src/arm/at91sam9rl.dtsi
+++ b/dts/src/arm/at91sam9rl.dtsi
@@ -204,7 +204,7 @@
};
ssc0: ssc@fffc0000 {
- compatible = "atmel,at91rm9200-ssc";
+ compatible = "atmel,at91sam9rl-ssc";
reg = <0xfffc0000 0x4000>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
@@ -213,7 +213,7 @@
};
ssc1: ssc@fffc4000 {
- compatible = "atmel,at91rm9200-ssc";
+ compatible = "atmel,at91sam9rl-ssc";
reg = <0xfffc4000 0x4000>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
diff --git a/dts/src/arm/at91sam9x5.dtsi b/dts/src/arm/at91sam9x5.dtsi
index e1a5c70..726274f 100644
--- a/dts/src/arm/at91sam9x5.dtsi
+++ b/dts/src/arm/at91sam9x5.dtsi
@@ -95,6 +95,8 @@
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
+ clocks = <&ddrck>;
+ clock-names = "ddrck";
};
pmc: pmc@fffffc00 {
@@ -966,7 +968,7 @@
adc0: adc@f804c000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "atmel,at91sam9260-adc";
+ compatible = "atmel,at91sam9x5-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&adc_clk>,
diff --git a/dts/src/arm/bcm2835-rpi-b.dts b/dts/src/arm/bcm2835-rpi-b.dts
index 2a3b1c1..58a0d60 100644
--- a/dts/src/arm/bcm2835-rpi-b.dts
+++ b/dts/src/arm/bcm2835-rpi-b.dts
@@ -23,7 +23,7 @@
&gpio {
pinctrl-names = "default";
- pinctrl-0 = <&gpioout &alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>;
gpioout: gpioout {
brcm,pins = <6>;
@@ -39,6 +39,12 @@
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <7>; /* alt3 */
};
+
+ /* I2S interface */
+ alt2: alt2 {
+ brcm,pins = <28 29 30 31>;
+ brcm,function = <6>; /* alt2 */
+ };
};
&i2c0 {
diff --git a/dts/src/arm/bcm2835.dtsi b/dts/src/arm/bcm2835.dtsi
index b8473c4..3342cb1 100644
--- a/dts/src/arm/bcm2835.dtsi
+++ b/dts/src/arm/bcm2835.dtsi
@@ -99,6 +99,7 @@
dmas = <&dma 2>,
<&dma 3>;
dma-names = "tx", "rx";
+ status = "disabled";
};
spi: spi@7e204000 {
diff --git a/dts/src/arm/bcm63138.dtsi b/dts/src/arm/bcm63138.dtsi
new file mode 100644
index 0000000..f3bb2dd
--- /dev/null
+++ b/dts/src/arm/bcm63138.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Broadcom BCM63138 DSL SoCs Device Tree
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm63138";
+ model = "Broadcom BCM63138 DSL SoC";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ uart0 = &serial0;
+ uart1 = &serial1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <1>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ };
+
+ periph_clk: periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "periph";
+ };
+ };
+
+ /* ARM bus */
+ axi@80000000 {
+ compatible = "simple-bus";
+ ranges = <0 0x80000000 0x784000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ L2: cache-controller@1d000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1d000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ cache-sets = <16>;
+ cache-size = <0x80000>;
+ interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ scu: scu@1e000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x1e000 0x100>;
+ };
+
+ gic: interrupt-controller@1e100 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x1f000 0x1000
+ 0x1e100 0x100>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ };
+
+ global_timer: timer@1e200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x1e200 0x20>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ local_timer: local-timer@1e600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x1e600 0x20>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ twd_watchdog: watchdog@1e620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x1e620 0x20>;
+ interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ /* Legacy UBUS base */
+ ubus@fffe8000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xfffe8000 0x8100>;
+
+ serial0: serial@600 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x600 0x1b>;
+ interrupts = <GIC_SPI 32 0>;
+ clocks = <&periph_clk>;
+ clock-names = "periph";
+ status = "disabled";
+ };
+
+ serial1: serial@620 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x620 0x1b>;
+ interrupts = <GIC_SPI 33 0>;
+ clocks = <&periph_clk>;
+ clock-names = "periph";
+ status = "disabled";
+ };
+ };
+};
diff --git a/dts/src/arm/bcm963138dvt.dts b/dts/src/arm/bcm963138dvt.dts
new file mode 100644
index 0000000..69c9339
--- /dev/null
+++ b/dts/src/arm/bcm963138dvt.dts
@@ -0,0 +1,30 @@
+/*
+ * Broadcom BCM63138 Reference Board DTS
+ */
+
+/dts-v1/;
+
+#include "bcm63138.dtsi"
+
+/ {
+ compatible = "brcm,BCM963138DVT", "brcm,bcm63138";
+ model = "Broadcom BCM963138DVT";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = &serial0;
+ };
+
+ memory {
+ reg = <0x0 0x08000000>;
+ };
+
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/berlin2q-marvell-dmp.dts b/dts/src/arm/berlin2q-marvell-dmp.dts
index a357ce0..ea1f99b 100644
--- a/dts/src/arm/berlin2q-marvell-dmp.dts
+++ b/dts/src/arm/berlin2q-marvell-dmp.dts
@@ -45,3 +45,7 @@
&uart0 {
status = "okay";
};
+
+&eth0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/berlin2q.dtsi b/dts/src/arm/berlin2q.dtsi
index 400c40f..891d56b 100644
--- a/dts/src/arm/berlin2q.dtsi
+++ b/dts/src/arm/berlin2q.dtsi
@@ -114,6 +114,23 @@
#interrupt-cells = <3>;
};
+ eth0: ethernet@b90000 {
+ compatible = "marvell,pxa168-eth";
+ reg = <0xb90000 0x10000>;
+ clocks = <&chip CLKID_GETH0>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ /* set by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <&ethphy0>;
+ status = "disabled";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+
cpu-ctrl@dd0000 {
compatible = "marvell,berlin-cpu-ctrl";
reg = <0xdd0000 0x10000>;
diff --git a/dts/src/arm/cros-adc-thermistors.dtsi b/dts/src/arm/cros-adc-thermistors.dtsi
new file mode 100644
index 0000000..acd4fe1
--- /dev/null
+++ b/dts/src/arm/cros-adc-thermistors.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Thermistor dts fragment for devices that use Thermistors as
+ * children of the IIO based ADC.
+ *
+ * Currently, used by Exynos5420 based Peach PIT and
+ * Exynos5800 based Peach PI.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&adc {
+ ncp15wb473@3 {
+ compatible = "murata,ncp15wb473";
+ pullup-uv = <1800000>;
+ pullup-ohm = <47000>;
+ pulldown-ohm = <0>;
+ io-channels = <&adc 3>;
+ };
+ ncp15wb473@4 {
+ compatible = "murata,ncp15wb473";
+ pullup-uv = <1800000>;
+ pullup-ohm = <47000>;
+ pulldown-ohm = <0>;
+ io-channels = <&adc 4>;
+ };
+ ncp15wb473@5 {
+ compatible = "murata,ncp15wb473";
+ pullup-uv = <1800000>;
+ pullup-ohm = <47000>;
+ pulldown-ohm = <0>;
+ io-channels = <&adc 5>;
+ };
+ ncp15wb473@6 {
+ compatible = "murata,ncp15wb473";
+ pullup-uv = <1800000>;
+ pullup-ohm = <47000>;
+ pulldown-ohm = <0>;
+ io-channels = <&adc 6>;
+ };
+};
diff --git a/dts/src/arm/da850-evm.dts b/dts/src/arm/da850-evm.dts
index 1e11e5a..4f935ad 100644
--- a/dts/src/arm/da850-evm.dts
+++ b/dts/src/arm/da850-evm.dts
@@ -17,6 +17,18 @@
soc {
pmx_core: pinmux@1c14120 {
status = "okay";
+
+ mcasp0_pins: pinmux_mcasp0_pins {
+ pinctrl-single,bits = <
+ /*
+ * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
+ * AFSR, AMUTE
+ */
+ 0x00 0x11111111 0xffffffff
+ /* AXR11, AXR12 */
+ 0x04 0x00011000 0x000ff000
+ >;
+ };
};
serial0: serial@1c42000 {
status = "okay";
@@ -39,6 +51,20 @@
tps: tps@48 {
reg = <0x48>;
};
+ tlv320aic3106: tlv320aic3106@18 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x18>;
+ status = "okay";
+
+ /* Regulators */
+ IOVDD-supply = <&vdcdc2_reg>;
+ /* Derived from VBAT: Baseboard 3.3V / 1.8V */
+ AVDD-supply = <&vbat>;
+ DRVDD-supply = <&vbat>;
+ DVDD-supply = <&vbat>;
+ };
+
};
wdt: wdt@1c21000 {
status = "okay";
@@ -117,6 +143,33 @@
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DA850/OMAP-L138 EVM";
+ simple-audio-card,widgets =
+ "Line", "Line In",
+ "Line", "Line Out";
+ simple-audio-card,routing =
+ "LINE1L", "Line In",
+ "LINE1R", "Line In",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&link0_codec>;
+ simple-audio-card,frame-master = <&link0_codec>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp0>;
+ system-clock-frequency = <24576000>;
+ };
+
+ link0_codec: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ system-clock-frequency = <24576000>;
+ };
+ };
};
/include/ "tps6507x.dtsi"
@@ -170,3 +223,22 @@
};
};
};
+
+&mcasp0 {
+ #sound-dai-cells = <0>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcasp0_pins>;
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 1
+ 2 0 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
diff --git a/dts/src/arm/da850.dtsi b/dts/src/arm/da850.dtsi
index b695548..0bd98cd 100644
--- a/dts/src/arm/da850.dtsi
+++ b/dts/src/arm/da850.dtsi
@@ -150,6 +150,12 @@
};
};
+ edma0: edma@01c00000 {
+ compatible = "ti,edma3";
+ reg = <0x0 0x10000>;
+ interrupts = <11 13 12>;
+ #dma-cells = <1>;
+ };
serial0: serial@1c42000 {
compatible = "ns16550a";
reg = <0x42000 0x100>;
@@ -270,6 +276,19 @@
ti,davinci-gpio-unbanked = <0>;
status = "disabled";
};
+
+ mcasp0: mcasp@01d00000 {
+ compatible = "ti,da830-mcasp-audio";
+ reg = <0x100000 0x2000>,
+ <0x102000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <54>;
+ interrupt-names = "common";
+ status = "disabled";
+ dmas = <&edma0 1>,
+ <&edma0 0>;
+ dma-names = "tx", "rx";
+ };
};
nand_cs3@62000000 {
compatible = "ti,davinci-nand";
diff --git a/dts/src/arm/dra7-evm.dts b/dts/src/arm/dra7-evm.dts
index e03fbf3..c6ce625 100644
--- a/dts/src/arm/dra7-evm.dts
+++ b/dts/src/arm/dra7-evm.dts
@@ -323,6 +323,8 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
+ interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <&dra7_pmx_core 0x3e0>;
};
&uart2 {
@@ -447,22 +449,19 @@
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <40>;
- gpmc,cs-wr-off-ns = <40>;
+ gpmc,cs-rd-off-ns = <80>;
+ gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
- gpmc,adv-rd-off-ns = <30>;
- gpmc,adv-wr-off-ns = <30>;
- gpmc,we-on-ns = <5>;
- gpmc,we-off-ns = <25>;
- gpmc,oe-on-ns = <2>;
- gpmc,oe-off-ns = <20>;
- gpmc,access-ns = <20>;
- gpmc,wr-access-ns = <40>;
- gpmc,rd-cycle-ns = <40>;
- gpmc,wr-cycle-ns = <40>;
- gpmc,wait-pin = <0>;
- gpmc,wait-on-read;
- gpmc,wait-on-write;
+ gpmc,adv-rd-off-ns = <60>;
+ gpmc,adv-wr-off-ns = <60>;
+ gpmc,we-on-ns = <10>;
+ gpmc,we-off-ns = <50>;
+ gpmc,oe-on-ns = <4>;
+ gpmc,oe-off-ns = <40>;
+ gpmc,access-ns = <40>;
+ gpmc,wr-access-ns = <80>;
+ gpmc,rd-cycle-ns = <80>;
+ gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi
index d678152..9cc9843 100644
--- a/dts/src/arm/dra7.dtsi
+++ b/dts/src/arm/dra7.dtsi
@@ -89,6 +89,7 @@
prm: prm@4ae06000 {
compatible = "ti,dra7-prm";
reg = <0x4ae06000 0x3000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
@@ -217,10 +218,12 @@
};
dra7_pmx_core: pinmux@4a003400 {
- compatible = "pinctrl-single";
+ compatible = "ti,dra7-padconf", "pinctrl-single";
reg = <0x4a003400 0x0464>;
#address-cells = <1>;
#size-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
@@ -328,7 +331,7 @@
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
reg = <0x4806a000 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
@@ -337,7 +340,7 @@
uart2: serial@4806c000 {
compatible = "ti,omap4-uart";
reg = <0x4806c000 0x100>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
@@ -346,7 +349,7 @@
uart3: serial@48020000 {
compatible = "ti,omap4-uart";
reg = <0x48020000 0x100>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
@@ -355,7 +358,7 @@
uart4: serial@4806e000 {
compatible = "ti,omap4-uart";
reg = <0x4806e000 0x100>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
status = "disabled";
@@ -364,7 +367,7 @@
uart5: serial@48066000 {
compatible = "ti,omap4-uart";
reg = <0x48066000 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
status = "disabled";
@@ -373,7 +376,7 @@
uart6: serial@48068000 {
compatible = "ti,omap4-uart";
reg = <0x48068000 0x100>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
status = "disabled";
@@ -382,7 +385,7 @@
uart7: serial@48420000 {
compatible = "ti,omap4-uart";
reg = <0x48420000 0x100>;
- interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart7";
clock-frequency = <48000000>;
status = "disabled";
@@ -391,7 +394,7 @@
uart8: serial@48422000 {
compatible = "ti,omap4-uart";
reg = <0x48422000 0x100>;
- interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart8";
clock-frequency = <48000000>;
status = "disabled";
@@ -400,7 +403,7 @@
uart9: serial@48424000 {
compatible = "ti,omap4-uart";
reg = <0x48424000 0x100>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart9";
clock-frequency = <48000000>;
status = "disabled";
@@ -409,7 +412,7 @@
uart10: serial@4ae2b000 {
compatible = "ti,omap4-uart";
reg = <0x4ae2b000 0x100>;
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart10";
clock-frequency = <48000000>;
status = "disabled";
diff --git a/dts/src/arm/dra72-evm.dts b/dts/src/arm/dra72-evm.dts
index 5147023..4107428 100644
--- a/dts/src/arm/dra72-evm.dts
+++ b/dts/src/arm/dra72-evm.dts
@@ -19,6 +19,126 @@
};
};
+&dra7_pmx_core {
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
+ 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+
+ tps65917: tps65917@58 {
+ compatible = "ti,tps65917";
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,system-power-controller;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ regulators {
+ smps1_reg: smps1 {
+ /* VDD_MPU */
+ regulator-name = "smps1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps2_reg: smps2 {
+ /* VDD_CORE */
+ regulator-name = "smps2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1030000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_GPU IVA DSPEVE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDDS1V8 */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDD_DDR */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> SDIO */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ ldo2_reg: ldo2 {
+ /* LDO2_OUT --> TP1017 (UNUSED) */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHY */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+};
+
&uart1 {
status = "okay";
};
diff --git a/dts/src/arm/dra72x.dtsi b/dts/src/arm/dra72x.dtsi
index f1ec22f..e5a3d23 100644
--- a/dts/src/arm/dra72x.dtsi
+++ b/dts/src/arm/dra72x.dtsi
@@ -22,4 +22,9 @@
reg = <0>;
};
};
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
+ };
};
diff --git a/dts/src/arm/dra74x.dtsi b/dts/src/arm/dra74x.dtsi
index a4e8bb9..3be544c 100644
--- a/dts/src/arm/dra74x.dtsi
+++ b/dts/src/arm/dra74x.dtsi
@@ -38,4 +38,10 @@
reg = <1>;
};
};
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
+ };
};
diff --git a/dts/src/arm/exynos3250.dtsi b/dts/src/arm/exynos3250.dtsi
index 1d52de6..693a327 100644
--- a/dts/src/arm/exynos3250.dtsi
+++ b/dts/src/arm/exynos3250.dtsi
@@ -132,6 +132,12 @@
reg = <0x10020000 0x4000>;
};
+ mipi_phy: video-phy@10020710 {
+ compatible = "samsung,s5pv210-mipi-video-phy";
+ reg = <0x10020710 8>;
+ #phy-cells = <1>;
+ };
+
pd_cam: cam-power-domain@10023C00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x20>;
@@ -163,8 +169,14 @@
#clock-cells = <1>;
};
+ cmu_dmc: clock-controller@105C0000 {
+ compatible = "samsung,exynos3250-cmu-dmc";
+ reg = <0x105C0000 0x2000>;
+ #clock-cells = <1>;
+ };
+
rtc: rtc@10070000 {
- compatible = "samsung,s3c6410-rtc";
+ compatible = "samsung,exynos3250-rtc";
reg = <0x10070000 0x100>;
interrupts = <0 73 0>, <0 74 0>;
status = "disabled";
@@ -216,6 +228,33 @@
interrupts = <0 240 0>;
};
+ fimd: fimd@11c00000 {
+ compatible = "samsung,exynos3250-fimd";
+ reg = <0x11c00000 0x30000>;
+ interrupt-names = "fifo", "vsync", "lcd_sys";
+ interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
+ clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
+ clock-names = "sclk_fimd", "fimd";
+ samsung,power-domain = <&pd_lcd0>;
+ samsung,sysreg = <&sys_reg>;
+ status = "disabled";
+ };
+
+ dsi_0: dsi@11C80000 {
+ compatible = "samsung,exynos3250-mipi-dsi";
+ reg = <0x11C80000 0x10000>;
+ interrupts = <0 83 0>;
+ samsung,phy-type = <0>;
+ samsung,power-domain = <&pd_lcd0>;
+ phys = <&mipi_phy 1>;
+ phy-names = "dsim";
+ clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
+ clock-names = "bus_clk", "pll_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
mshc_0: mshc@12510000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12510000 0x1000>;
diff --git a/dts/src/arm/exynos4412-odroid-common.dtsi b/dts/src/arm/exynos4412-odroid-common.dtsi
index adadaf9..c697ff0 100644
--- a/dts/src/arm/exynos4412-odroid-common.dtsi
+++ b/dts/src/arm/exynos4412-odroid-common.dtsi
@@ -54,17 +54,13 @@
status = "okay";
num-slots = <1>;
- supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
+ cap-mmc-highspeed;
};
watchdog@10060000 {
diff --git a/dts/src/arm/exynos4412-origen.dts b/dts/src/arm/exynos4412-origen.dts
index e925c9f..de15114 100644
--- a/dts/src/arm/exynos4412-origen.dts
+++ b/dts/src/arm/exynos4412-origen.dts
@@ -137,17 +137,13 @@
status = "okay";
num-slots = <1>;
- supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
+ cap-mmc-highspeed;
};
codec@13400000 {
diff --git a/dts/src/arm/exynos4412-trats2.dts b/dts/src/arm/exynos4412-trats2.dts
index 11967f4..5e066cd 100644
--- a/dts/src/arm/exynos4412-trats2.dts
+++ b/dts/src/arm/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
mmc@12550000 {
num-slots = <1>;
- supports-highspeed;
broken-cd;
non-removable;
card-detect-delay = <200>;
@@ -532,11 +531,8 @@
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
pinctrl-names = "default";
status = "okay";
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
+ cap-mmc-highspeed;
};
serial@13800000 {
diff --git a/dts/src/arm/exynos4x12-pinctrl.dtsi b/dts/src/arm/exynos4x12-pinctrl.dtsi
index 99b26df..0865a2e 100644
--- a/dts/src/arm/exynos4x12-pinctrl.dtsi
+++ b/dts/src/arm/exynos4x12-pinctrl.dtsi
@@ -675,7 +675,7 @@
sd4_bus8: sd4-bus-width8 {
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
samsung,pin-function = <4>;
- samsung,pin-pud = <4>;
+ samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
diff --git a/dts/src/arm/exynos5250-arndale.dts b/dts/src/arm/exynos5250-arndale.dts
index d0de1f5..3acd97e 100644
--- a/dts/src/arm/exynos5250-arndale.dts
+++ b/dts/src/arm/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
mmc_0: mmc@12200000 {
status = "okay";
num-slots = <1>;
- supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
@@ -410,17 +409,13 @@
vmmc-supply = <&mmc_reg>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
+ cap-mmc-highspeed;
};
mmc_2: mmc@12220000 {
status = "okay";
num-slots = <1>;
- supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@@ -428,12 +423,9 @@
vmmc-supply = <&mmc_reg>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- disable-wp;
- };
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
};
i2s0: i2s@03830000 {
@@ -570,8 +562,4 @@
connect-gpios = <&gpd1 7 1>;
};
};
-
- usb@12110000 {
- usb-phy = <&usb2_phy>;
- };
};
diff --git a/dts/src/arm/exynos5250-cros-common.dtsi b/dts/src/arm/exynos5250-cros-common.dtsi
deleted file mode 100644
index e603e9c..0000000
--- a/dts/src/arm/exynos5250-cros-common.dtsi
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Common device tree include for all Exynos 5250 boards based off of Daisy.
- *
- * Copyright (c) 2012 Google, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/ {
- aliases {
- };
-
- memory {
- reg = <0x40000000 0x80000000>;
- };
-
- chosen {
- };
-
- pinctrl@11400000 {
- /*
- * Disabled pullups since external part has its own pullups and
- * double-pulling gets us out of spec in some cases.
- */
- i2c2_bus: i2c2-bus {
- samsung,pin-pud = <0>;
- };
- };
-
- i2c@12C60000 {
- status = "okay";
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <378000>;
- };
-
- i2c@12C70000 {
- status = "okay";
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <378000>;
- };
-
- i2c@12C80000 {
- status = "okay";
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <66000>;
-
- hdmiddc@50 {
- compatible = "samsung,exynos4210-hdmiddc";
- reg = <0x50>;
- };
- };
-
- i2c@12C90000 {
- status = "okay";
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <66000>;
- };
-
- i2c@12CA0000 {
- status = "okay";
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <66000>;
- };
-
- i2c@12CB0000 {
- status = "okay";
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <66000>;
- };
-
- i2c@12CD0000 {
- status = "okay";
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <66000>;
- };
-
- i2c@12CE0000 {
- status = "okay";
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <378000>;
-
- hdmiphy: hdmiphy@38 {
- compatible = "samsung,exynos4212-hdmiphy";
- reg = <0x38>;
- };
- };
-
- mmc@12200000 {
- num-slots = <1>;
- supports-highspeed;
- broken-cd;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
- pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
- };
-
- mmc@12220000 {
- num-slots = <1>;
- supports-highspeed;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
- pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- wp-gpios = <&gpc2 1 0>;
- };
- };
-
- mmc@12230000 {
- num-slots = <1>;
- supports-highspeed;
- broken-cd;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
- /* See board-specific dts files for pin setup */
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- };
- };
-
- spi_1: spi@12d30000 {
- status = "okay";
- samsung,spi-src-clk = <0>;
- num-cs = <1>;
- };
-
- hdmi {
- hpd-gpio = <&gpx3 7 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_hpd_irq>;
- phy = <&hdmiphy>;
- ddc = <&i2c_2>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- power {
- label = "Power";
- gpios = <&gpx1 3 1>;
- linux,code = <116>; /* KEY_POWER */
- gpio-key,wakeup;
- };
- };
-};
diff --git a/dts/src/arm/exynos5250-smdk5250.dts b/dts/src/arm/exynos5250-smdk5250.dts
index b4b35ad..6a0f4c0 100644
--- a/dts/src/arm/exynos5250-smdk5250.dts
+++ b/dts/src/arm/exynos5250-smdk5250.dts
@@ -284,7 +284,6 @@
mmc@12200000 {
status = "okay";
num-slots = <1>;
- supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
@@ -292,29 +291,22 @@
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
+ cap-mmc-highspeed;
};
mmc@12220000 {
status = "okay";
num-slots = <1>;
- supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- disable-wp;
- };
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
};
spi_1: spi@12d30000 {
diff --git a/dts/src/arm/exynos5250-snow.dts b/dts/src/arm/exynos5250-snow.dts
index f2b8c41..e51fcef 100644
--- a/dts/src/arm/exynos5250-snow.dts
+++ b/dts/src/arm/exynos5250-snow.dts
@@ -9,8 +9,8 @@
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "exynos5250.dtsi"
-#include "exynos5250-cros-common.dtsi"
/ {
model = "Google Snow";
@@ -20,6 +20,13 @@
i2c104 = &i2c_104;
};
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ chosen {
+ };
+
rtc@101E0000 {
status = "okay";
};
@@ -93,6 +100,13 @@
gpio-keys {
compatible = "gpio-keys";
+ power {
+ label = "Power";
+ gpios = <&gpx1 3 1>;
+ linux,code = <116>; /* KEY_POWER */
+ gpio-key,wakeup;
+ };
+
lid-switch {
label = "Lid";
gpios = <&gpx3 5 1>;
@@ -181,7 +195,7 @@
dcdc3 {
ti,enable-ext-control;
};
- fet1 {
+ fet1: fet1 {
regulator-name = "vcd_led";
ti,overcurrent-wait = <3>;
};
@@ -204,7 +218,7 @@
regulator-always-on;
ti,overcurrent-wait = <3>;
};
- fet6 {
+ fet6: fet6 {
regulator-name = "lcd_vdd";
ti,overcurrent-wait = <3>;
};
@@ -226,26 +240,6 @@
};
};
- mmc@12200000 {
- status = "okay";
- };
-
- mmc@12220000 {
- status = "okay";
- };
-
- /*
- * On Snow we've got SIP WiFi and so can keep drive strengths low to
- * reduce EMI.
- */
- mmc@12230000 {
- status = "okay";
- slot@0 {
- pinctrl-names = "default";
- pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
- };
- };
-
i2c@12CD0000 {
max98095: codec@11 {
compatible = "maxim,max98095";
@@ -253,6 +247,15 @@
pinctrl-0 = <&max98095_en>;
pinctrl-names = "default";
};
+
+ ptn3460: lvds-bridge@20 {
+ compatible = "nxp,ptn3460";
+ reg = <0x20>;
+ powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
+ edid-emulation = <5>;
+ panel = <&panel>;
+ };
};
i2s0: i2s@03830000 {
@@ -294,17 +297,24 @@
};
hdmi {
+ hpd-gpio = <&gpx3 7 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_hpd_irq>;
+ phy = <&hdmiphy>;
+ ddc = <&i2c_2>;
hdmi-en-supply = <&tps65090_fet7>;
vdd-supply = <&ldo8_reg>;
vdd_osc-supply = <&ldo10_reg>;
vdd_pll-supply = <&ldo8_reg>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
default-brightness-level = <7>;
+ enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
+ power-supply = <&fet1>;
pinctrl-0 = <&pwm0_out>;
pinctrl-names = "default";
};
@@ -314,6 +324,12 @@
samsung,invert-vclk;
};
+ panel: panel {
+ compatible = "auo,b116xw03";
+ power-supply = <&fet6>;
+ backlight = <&backlight>;
+ };
+
dp-controller@145B0000 {
status = "okay";
pinctrl-names = "default";
@@ -325,26 +341,15 @@
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx0 7 0>;
-
- display-timings {
- native-mode = <&timing1>;
-
- timing1: timing@1 {
- clock-frequency = <70589280>;
- hactive = <1366>;
- vactive = <768>;
- hfront-porch = <40>;
- hback-porch = <40>;
- hsync-len = <32>;
- vback-porch = <10>;
- vfront-porch = <12>;
- vsync-len = <6>;
- };
- };
+ bridge = <&ptn3460>;
};
};
&i2c_0 {
+ status = "okay";
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <378000>;
+
max77686@09 {
compatible = "maxim,max77686";
interrupt-parent = <&gpx3>;
@@ -491,6 +496,10 @@
};
&i2c_1 {
+ status = "okay";
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <378000>;
+
trackpad {
reg = <0x67>;
compatible = "cypress,cyapa";
@@ -500,6 +509,106 @@
};
};
+/*
+ * Disabled pullups since external part has its own pullups and
+ * double-pulling gets us out of spec in some cases.
+ */
+&i2c2_bus {
+ samsung,pin-pud = <0>;
+};
+
+&i2c_2 {
+ status = "okay";
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <66000>;
+
+ hdmiddc@50 {
+ compatible = "samsung,exynos4210-hdmiddc";
+ reg = <0x50>;
+ };
+};
+
+&i2c_3 {
+ status = "okay";
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_4 {
+ status = "okay";
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_5 {
+ status = "okay";
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_7 {
+ status = "okay";
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_8 {
+ status = "okay";
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <378000>;
+
+ hdmiphy: hdmiphy@38 {
+ compatible = "samsung,exynos4212-hdmiphy";
+ reg = <0x38>;
+ };
+};
+
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+};
+
+&mmc_2 {
+ status = "okay";
+ num-slots = <1>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+ bus-width = <4>;
+ wp-gpios = <&gpc2 1 0>;
+ cap-sd-highspeed;
+};
+
+/*
+ * On Snow we've got SIP WiFi and so can keep drive strengths low to
+ * reduce EMI.
+ */
+&mmc_3 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+};
+
&pinctrl_0 {
max77686_irq: max77686-irq {
samsung,pins = "gpx3-2";
@@ -509,4 +618,10 @@
};
};
+&spi_1 {
+ status = "okay";
+ samsung,spi-src-clk = <0>;
+ num-cs = <1>;
+};
+
#include "cros-ec-keyboard.dtsi"
diff --git a/dts/src/arm/exynos5250.dtsi b/dts/src/arm/exynos5250.dtsi
index 492e1ef..f21b9aa 100644
--- a/dts/src/arm/exynos5250.dtsi
+++ b/dts/src/arm/exynos5250.dtsi
@@ -603,21 +603,6 @@
};
};
- usb2_phy: usbphy@12130000 {
- compatible = "samsung,exynos5250-usb2phy";
- reg = <0x12130000 0x100>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
- clock-names = "ext_xtal", "usbhost";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usbphy-sys {
- reg = <0x10040704 0x8>,
- <0x10050230 0x4>;
- };
- };
-
usb2_phy_gen: phy@12130000 {
compatible = "samsung,exynos5250-usb2-phy";
reg = <0x12130000 0x100>;
diff --git a/dts/src/arm/exynos5260-xyref5260.dts b/dts/src/arm/exynos5260-xyref5260.dts
index 8c84ab2..a803b60 100644
--- a/dts/src/arm/exynos5260-xyref5260.dts
+++ b/dts/src/arm/exynos5260-xyref5260.dts
@@ -69,7 +69,7 @@
num-slots = <1>;
broken-cd;
bypass-smu;
- supports-highspeed;
+ cap-mmc-highspeed;
supports-hs200-mode; /* 200 Mhz */
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
@@ -77,27 +77,19 @@
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
};
&mmc_2 {
status = "okay";
num-slots = <1>;
- supports-highspeed;
+ cap-sd-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- disable-wp;
- };
+ bus-width = <4>;
+ disable-wp;
};
diff --git a/dts/src/arm/exynos5410-smdk5410.dts b/dts/src/arm/exynos5410-smdk5410.dts
index 7275bbd..be3e025 100644
--- a/dts/src/arm/exynos5410-smdk5410.dts
+++ b/dts/src/arm/exynos5410-smdk5410.dts
@@ -40,33 +40,25 @@
&mmc_0 {
status = "okay";
num-slots = <1>;
- supports-highspeed;
+ cap-mmc-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
};
&mmc_2 {
status = "okay";
num-slots = <1>;
- supports-highspeed;
+ cap-sd-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- disable-wp;
- };
+ bus-width = <4>;
+ disable-wp;
};
&uart0 {
diff --git a/dts/src/arm/exynos5420-arndale-octa.dts b/dts/src/arm/exynos5420-arndale-octa.dts
index 434fd9d..aa7a7d7 100644
--- a/dts/src/arm/exynos5420-arndale-octa.dts
+++ b/dts/src/arm/exynos5420-arndale-octa.dts
@@ -50,7 +50,6 @@
mmc@12200000 {
status = "okay";
broken-cd;
- supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
@@ -58,28 +57,22 @@
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
vmmc-supply = <&ldo10_reg>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
+ cap-mmc-highspeed;
};
mmc@12220000 {
status = "okay";
- supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
- vmmc-supply = <&ldo10_reg>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- };
+ vmmc-supply = <&ldo19_reg>;
+ vqmmc-supply = <&ldo13_reg>;
+ bus-width = <4>;
+ cap-sd-highspeed;
};
hsi2c_4: i2c@12CA0000 {
@@ -375,3 +368,7 @@
};
};
};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+};
diff --git a/dts/src/arm/exynos5420-peach-pit.dts b/dts/src/arm/exynos5420-peach-pit.dts
index 228a6b1..82cdb74 100644
--- a/dts/src/arm/exynos5420-peach-pit.dts
+++ b/dts/src/arm/exynos5420-peach-pit.dts
@@ -11,6 +11,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos5420.dtsi"
/ {
@@ -30,11 +31,12 @@
i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
default-brightness-level = <7>;
+ power-supply = <&tps65090_fet1>;
pinctrl-0 = <&pwm0_out>;
pinctrl-names = "default";
};
@@ -100,6 +102,17 @@
regulator-boot-on;
regulator-always-on;
};
+
+ panel: panel {
+ compatible = "auo,b116xw03";
+ power-supply = <&tps65090_fet6>;
+ backlight = <&backlight>;
+ };
+};
+
+&adc {
+ status = "okay";
+ vdd-supply = <&ldo9_reg>;
};
&dp {
@@ -113,22 +126,7 @@
samsung,link-rate = <0x06>;
samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx2 6 0>;
-
- display-timings {
- native-mode = <&timing1>;
-
- timing1: timing@1 {
- clock-frequency = <70589280>;
- hactive = <1366>;
- vactive = <768>;
- hfront-porch = <40>;
- hback-porch = <40>;
- hsync-len = <32>;
- vback-porch = <10>;
- vfront-porch = <12>;
- vsync-len = <6>;
- };
- };
+ bridge = <&ps8625>;
};
&fimd {
@@ -142,10 +140,348 @@
pinctrl-names = "default";
pinctrl-0 = <&hdmi_hpd_irq>;
ddc = <&i2c_2>;
+
+ hdmi-en-supply = <&tps65090_fet7>;
+ vdd-supply = <&ldo8_reg>;
+ vdd_osc-supply = <&ldo10_reg>;
+ vdd_pll-supply = <&ldo8_reg>;
+};
+
+&hsi2c_4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ max77802-pmic@9 {
+ compatible = "maxim,max77802";
+ interrupt-parent = <&gpx3>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&max77802_irq>, <&pmic_selb>,
+ <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>;
+ wakeup-source;
+ reg = <0x9>;
+ #clock-cells = <1>;
+
+ inb1-supply = <&tps65090_dcdc2>;
+ inb2-supply = <&tps65090_dcdc1>;
+ inb3-supply = <&tps65090_dcdc2>;
+ inb4-supply = <&tps65090_dcdc2>;
+ inb5-supply = <&tps65090_dcdc1>;
+ inb6-supply = <&tps65090_dcdc2>;
+ inb7-supply = <&tps65090_dcdc1>;
+ inb8-supply = <&tps65090_dcdc1>;
+ inb9-supply = <&tps65090_dcdc1>;
+ inb10-supply = <&tps65090_dcdc1>;
+
+ inl1-supply = <&buck5_reg>;
+ inl2-supply = <&buck7_reg>;
+ inl3-supply = <&buck9_reg>;
+ inl4-supply = <&buck9_reg>;
+ inl5-supply = <&buck9_reg>;
+ inl6-supply = <&tps65090_dcdc2>;
+ inl7-supply = <&buck9_reg>;
+ inl9-supply = <&tps65090_dcdc2>;
+ inl10-supply = <&buck7_reg>;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "vdd_kfc";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "vdd_1v35";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "vdd_emmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "vdd_2v";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck10_reg: BUCK10 {
+ regulator-name = "vdd_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "vdd_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "vdd_1v2_2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "vdd_1v8_3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vqmmc_sdcard: ldo4_reg: LDO4 {
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "vdd_1v8_5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "vdd_1v8_6";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "vdd_1v8_7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "vdd_ldo8";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "vdd_ldo9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "vdd_ldo10";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "vdd_ldo11";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "vdd_ldo12";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "vdd_ldo13";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "vdd_ldo14";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "vdd_ldo15";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "vdd_g3ds";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ };
+
+ ldo18_reg: LDO18 {
+ regulator-name = "ldo_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "ldo_19";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "ldo_20";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "ldo_21";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-name = "ldo_23";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo24_reg: LDO24 {
+ regulator-name = "ldo_24";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "ldo_25";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-name = "ldo_26";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo27_reg: LDO27 {
+ regulator-name = "ldo_27";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo28_reg: LDO28 {
+ regulator-name = "ldo_28";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo29_reg: LDO29 {
+ regulator-name = "ldo_29";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo30_reg: LDO30 {
+ regulator-name = "vdd_mifs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo32_reg: LDO32 {
+ regulator-name = "ldo_32";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo33_reg: LDO33 {
+ regulator-name = "ldo_33";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo34_reg: LDO34 {
+ regulator-name = "ldo_34";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo35_reg: LDO35 {
+ regulator-name = "ldo_35";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
+ };
};
&hsi2c_7 {
status = "okay";
+ clock-frequency = <400000>;
max98090: codec@10 {
compatible = "maxim,max98090";
@@ -155,6 +491,44 @@
pinctrl-names = "default";
pinctrl-0 = <&max98090_irq>;
};
+
+ light-sensor@44 {
+ compatible = "isil,isl29018";
+ reg = <0x44>;
+ vcc-supply = <&tps65090_fet5>;
+ };
+
+ ps8625: lvds-bridge@48 {
+ compatible = "parade,ps8625";
+ reg = <0x48>;
+ sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>;
+ lane-count = <2>;
+ panel = <&panel>;
+ use-external-pwm;
+ };
+};
+
+&hsi2c_8 {
+ status = "okay";
+ clock-frequency = <333000>;
+
+ /* Atmel mXT336S */
+ trackpad@4b {
+ compatible = "atmel,maxtouch";
+ reg = <0x4b>;
+ interrupt-parent = <&gpx1>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_irq>;
+ linux,gpio-keymap = <KEY_RESERVED
+ KEY_RESERVED
+ KEY_RESERVED /* GPIO0 */
+ KEY_RESERVED /* GPIO1 */
+ KEY_RESERVED /* GPIO2 */
+ BTN_LEFT>; /* GPIO3 */
+ };
};
&hsi2c_9 {
@@ -187,7 +561,7 @@
num-slots = <1>;
broken-cd;
caps2-mmc-hs200-1_8v;
- supports-highspeed;
+ cap-mmc-highspeed;
non-removable;
card-detect-delay = <200>;
clock-frequency = <400000000>;
@@ -196,17 +570,13 @@
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
};
&mmc_2 {
status = "okay";
num-slots = <1>;
- supports-highspeed;
+ cap-sd-highspeed;
card-detect-delay = <200>;
clock-frequency = <400000000>;
samsung,dw-mshc-ciu-div = <3>;
@@ -214,11 +584,7 @@
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- };
+ bus-width = <4>;
};
@@ -249,6 +615,13 @@
samsung,pin-drv = <0>;
};
+ trackpad_irq: trackpad-irq {
+ samsung,pins = "gpx1-1";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
power_key_irq: power-key-irq {
samsung,pins = "gpx1-2";
samsung,pin-function = <0>;
@@ -277,12 +650,42 @@
samsung,pin-drv = <0>;
};
+ max77802_irq: max77802-irq {
+ samsung,pins = "gpx3-1";
+ samsung,pin-function = <0>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
hdmi_hpd_irq: hdmi-hpd-irq {
samsung,pins = "gpx3-7";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
+
+ pmic_dvs_1: pmic-dvs-1 {
+ samsung,pins = "gpy7-6";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&pinctrl_2 {
+ pmic_dvs_2: pmic-dvs-2 {
+ samsung,pins = "gpj4-2";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ pmic_dvs_3: pmic-dvs-3 {
+ samsung,pins = "gpj4-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
};
&pinctrl_3 {
@@ -312,6 +715,14 @@
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
+
+ pmic_selb: pmic-selb {
+ samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5",
+ "gph0-6";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
};
&rtc {
@@ -365,12 +776,12 @@
vsys2-supply = <&vbat>;
vsys3-supply = <&vbat>;
infet1-supply = <&vbat>;
- infet2-supply = <&vbat>;
- infet3-supply = <&vbat>;
- infet4-supply = <&vbat>;
- infet5-supply = <&vbat>;
- infet6-supply = <&vbat>;
- infet7-supply = <&vbat>;
+ infet2-supply = <&tps65090_dcdc1>;
+ infet3-supply = <&tps65090_dcdc2>;
+ infet4-supply = <&tps65090_dcdc2>;
+ infet5-supply = <&tps65090_dcdc2>;
+ infet6-supply = <&tps65090_dcdc2>;
+ infet7-supply = <&tps65090_dcdc1>;
vsys-l1-supply = <&vbat>;
vsys-l2-supply = <&vbat>;
@@ -427,6 +838,14 @@
status = "okay";
};
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+};
+
&usbdrd_phy0 {
vbus-supply = <&usb300_vbus_reg>;
};
@@ -445,3 +864,4 @@
};
#include "cros-ec-keyboard.dtsi"
+#include "cros-adc-thermistors.dtsi"
diff --git a/dts/src/arm/exynos5420-smdk5420.dts b/dts/src/arm/exynos5420-smdk5420.dts
index 6052aa9..8be3d7b 100644
--- a/dts/src/arm/exynos5420-smdk5420.dts
+++ b/dts/src/arm/exynos5420-smdk5420.dts
@@ -76,34 +76,26 @@
mmc@12200000 {
status = "okay";
broken-cd;
- supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
+ cap-mmc-highspeed;
};
mmc@12220000 {
status = "okay";
- supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- };
+ bus-width = <4>;
+ cap-sd-highspeed;
};
dp-controller@145B0000 {
diff --git a/dts/src/arm/exynos5420.dtsi b/dts/src/arm/exynos5420.dtsi
index bfe056d..8617a03 100644
--- a/dts/src/arm/exynos5420.dtsi
+++ b/dts/src/arm/exynos5420.dtsi
@@ -815,7 +815,7 @@
#size-cells = <1>;
ranges;
- dwc3 {
+ usbdrd_dwc3_0: dwc3 {
compatible = "snps,dwc3";
reg = <0x12000000 0x10000>;
interrupts = <0 72 0>;
@@ -841,7 +841,7 @@
#size-cells = <1>;
ranges;
- dwc3 {
+ usbdrd_dwc3_1: dwc3 {
compatible = "snps,dwc3";
reg = <0x12400000 0x10000>;
interrupts = <0 73 0>;
diff --git a/dts/src/arm/exynos5800-peach-pi.dts b/dts/src/arm/exynos5800-peach-pi.dts
index f3ee48b..7bb1c8d 100644
--- a/dts/src/arm/exynos5800-peach-pi.dts
+++ b/dts/src/arm/exynos5800-peach-pi.dts
@@ -11,6 +11,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos5800.dtsi"
/ {
@@ -28,11 +29,13 @@
i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
default-brightness-level = <7>;
+ enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>;
+ power-supply = <&tps65090_fet1>;
pinctrl-0 = <&pwm0_out>;
pinctrl-names = "default";
};
@@ -98,6 +101,17 @@
regulator-boot-on;
regulator-always-on;
};
+
+ panel: panel {
+ compatible = "auo,b133htn01";
+ power-supply = <&tps65090_fet6>;
+ backlight = <&backlight>;
+ };
+};
+
+&adc {
+ status = "okay";
+ vdd-supply = <&ldo9_reg>;
};
&dp {
@@ -111,22 +125,7 @@
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx2 6 0>;
-
- display-timings {
- native-mode = <&timing1>;
-
- timing1: timing@1 {
- clock-frequency = <150660000>;
- hactive = <1920>;
- vactive = <1080>;
- hfront-porch = <60>;
- hback-porch = <172>;
- hsync-len = <80>;
- vback-porch = <25>;
- vfront-porch = <10>;
- vsync-len = <10>;
- };
- };
+ panel = <&panel>;
};
&fimd {
@@ -140,10 +139,348 @@
pinctrl-names = "default";
pinctrl-0 = <&hdmi_hpd_irq>;
ddc = <&i2c_2>;
+
+ hdmi-en-supply = <&tps65090_fet7>;
+ vdd-supply = <&ldo8_reg>;
+ vdd_osc-supply = <&ldo10_reg>;
+ vdd_pll-supply = <&ldo8_reg>;
+};
+
+&hsi2c_4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ max77802-pmic@9 {
+ compatible = "maxim,max77802";
+ interrupt-parent = <&gpx3>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&max77802_irq>, <&pmic_selb>,
+ <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>;
+ wakeup-source;
+ reg = <0x9>;
+ #clock-cells = <1>;
+
+ inb1-supply = <&tps65090_dcdc2>;
+ inb2-supply = <&tps65090_dcdc1>;
+ inb3-supply = <&tps65090_dcdc2>;
+ inb4-supply = <&tps65090_dcdc2>;
+ inb5-supply = <&tps65090_dcdc1>;
+ inb6-supply = <&tps65090_dcdc2>;
+ inb7-supply = <&tps65090_dcdc1>;
+ inb8-supply = <&tps65090_dcdc1>;
+ inb9-supply = <&tps65090_dcdc1>;
+ inb10-supply = <&tps65090_dcdc1>;
+
+ inl1-supply = <&buck5_reg>;
+ inl2-supply = <&buck7_reg>;
+ inl3-supply = <&buck9_reg>;
+ inl4-supply = <&buck9_reg>;
+ inl5-supply = <&buck9_reg>;
+ inl6-supply = <&tps65090_dcdc2>;
+ inl7-supply = <&buck9_reg>;
+ inl9-supply = <&tps65090_dcdc2>;
+ inl10-supply = <&buck7_reg>;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "vdd_kfc";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "vdd_1v35";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "vdd_emmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "vdd_2v";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck10_reg: BUCK10 {
+ regulator-name = "vdd_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "vdd_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "vdd_1v2_2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "vdd_1v8_3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vqmmc_sdcard: ldo4_reg: LDO4 {
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "vdd_1v8_5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "vdd_1v8_6";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "vdd_1v8_7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "vdd_ldo8";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "vdd_ldo9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "vdd_ldo10";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "vdd_ldo11";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "vdd_ldo12";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "vdd_ldo13";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "vdd_ldo14";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "vdd_ldo15";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "vdd_g3ds";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ };
+
+ ldo18_reg: LDO18 {
+ regulator-name = "ldo_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "ldo_19";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "ldo_20";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "ldo_21";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-name = "ldo_23";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo24_reg: LDO24 {
+ regulator-name = "ldo_24";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "ldo_25";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-name = "ldo_26";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo27_reg: LDO27 {
+ regulator-name = "ldo_27";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo28_reg: LDO28 {
+ regulator-name = "ldo_28";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo29_reg: LDO29 {
+ regulator-name = "ldo_29";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo30_reg: LDO30 {
+ regulator-name = "vdd_mifs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo32_reg: LDO32 {
+ regulator-name = "ldo_32";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo33_reg: LDO33 {
+ regulator-name = "ldo_33";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo34_reg: LDO34 {
+ regulator-name = "ldo_34";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo35_reg: LDO35 {
+ regulator-name = "ldo_35";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
+ };
};
&hsi2c_7 {
status = "okay";
+ clock-frequency = <400000>;
max98091: codec@10 {
compatible = "maxim,max98091";
@@ -153,6 +490,33 @@
pinctrl-names = "default";
pinctrl-0 = <&max98091_irq>;
};
+
+ light-sensor@44 {
+ compatible = "isil,isl29018";
+ reg = <0x44>;
+ vcc-supply = <&tps65090_fet5>;
+ };
+};
+
+&hsi2c_8 {
+ status = "okay";
+ clock-frequency = <333000>;
+ /* Atmel mXT540S */
+ trackpad@4b {
+ compatible = "atmel,maxtouch";
+ reg = <0x4b>;
+ interrupt-parent = <&gpx1>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_irq>;
+ linux,gpio-keymap = <KEY_RESERVED
+ KEY_RESERVED
+ KEY_RESERVED /* GPIO 0 */
+ KEY_RESERVED /* GPIO 1 */
+ BTN_LEFT /* GPIO 2 */
+ KEY_RESERVED>; /* GPIO 3 */
+ };
};
&hsi2c_9 {
@@ -185,7 +549,7 @@
num-slots = <1>;
broken-cd;
caps2-mmc-hs200-1_8v;
- supports-highspeed;
+ cap-mmc-highspeed;
non-removable;
card-detect-delay = <200>;
clock-frequency = <400000000>;
@@ -194,17 +558,13 @@
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
+ bus-width = <8>;
};
&mmc_2 {
status = "okay";
num-slots = <1>;
- supports-highspeed;
+ cap-sd-highspeed;
card-detect-delay = <200>;
clock-frequency = <400000000>;
samsung,dw-mshc-ciu-div = <3>;
@@ -212,11 +572,7 @@
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- };
+ bus-width = <4>;
};
@@ -247,6 +603,13 @@
samsung,pin-drv = <0>;
};
+ trackpad_irq: trackpad-irq {
+ samsung,pins = "gpx1-1";
+ samsung,pin-function = <0xf>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
power_key_irq: power-key-irq {
samsung,pins = "gpx1-2";
samsung,pin-function = <0>;
@@ -275,12 +638,42 @@
samsung,pin-drv = <0>;
};
+ max77802_irq: max77802-irq {
+ samsung,pins = "gpx3-1";
+ samsung,pin-function = <0>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
hdmi_hpd_irq: hdmi-hpd-irq {
samsung,pins = "gpx3-7";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
+
+ pmic_dvs_1: pmic-dvs-1 {
+ samsung,pins = "gpy7-6";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&pinctrl_2 {
+ pmic_dvs_2: pmic-dvs-2 {
+ samsung,pins = "gpj4-2";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ pmic_dvs_3: pmic-dvs-3 {
+ samsung,pins = "gpj4-3";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
};
&pinctrl_3 {
@@ -310,6 +703,14 @@
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
+
+ pmic_selb: pmic-selb {
+ samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5",
+ "gph0-6";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
};
&rtc {
@@ -363,12 +764,12 @@
vsys2-supply = <&vbat>;
vsys3-supply = <&vbat>;
infet1-supply = <&vbat>;
- infet2-supply = <&vbat>;
- infet3-supply = <&vbat>;
- infet4-supply = <&vbat>;
- infet5-supply = <&vbat>;
- infet6-supply = <&vbat>;
- infet7-supply = <&vbat>;
+ infet2-supply = <&tps65090_dcdc1>;
+ infet3-supply = <&tps65090_dcdc2>;
+ infet4-supply = <&tps65090_dcdc2>;
+ infet5-supply = <&tps65090_dcdc2>;
+ infet6-supply = <&tps65090_dcdc2>;
+ infet7-supply = <&tps65090_dcdc1>;
vsys-l1-supply = <&vbat>;
vsys-l2-supply = <&vbat>;
@@ -425,6 +826,14 @@
status = "okay";
};
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+};
+
&usbdrd_phy0 {
vbus-supply = <&usb300_vbus_reg>;
};
@@ -443,3 +852,4 @@
};
#include "cros-ec-keyboard.dtsi"
+#include "cros-adc-thermistors.dtsi"
diff --git a/dts/src/arm/hip04-d01.dts b/dts/src/arm/hip04-d01.dts
new file mode 100644
index 0000000..40a9e33
--- /dev/null
+++ b/dts/src/arm/hip04-d01.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2013-2014 Linaro Ltd.
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "hip04.dtsi"
+
+/ {
+ /* memory bus is 64-bit */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Hisilicon D01 Development Board";
+ compatible = "hisilicon,hip04-d01";
+
+ memory@00000000,10000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000 0x00000000 0xc0000000>,
+ <0x00000004 0xc0000000 0x00000003 0x40000000>;
+ };
+
+ soc {
+ uart0: uart@4007000 {
+ status = "ok";
+ };
+ };
+};
diff --git a/dts/src/arm/hip04.dtsi b/dts/src/arm/hip04.dtsi
new file mode 100644
index 0000000..93b6c90
--- /dev/null
+++ b/dts/src/arm/hip04.dtsi
@@ -0,0 +1,267 @@
+/*
+ * Hisilicon Ltd. HiP04 SoC
+ *
+ * Copyright (C) 2013-2014 Hisilicon Ltd.
+ * Copyright (C) 2013-2014 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ /* memory bus is 64-bit */
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ bootwrapper {
+ compatible = "hisilicon,hip04-bootwrapper";
+ boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ core2 {
+ cpu = <&CPU2>;
+ };
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+ core1 {
+ cpu = <&CPU5>;
+ };
+ core2 {
+ cpu = <&CPU6>;
+ };
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ cluster2 {
+ core0 {
+ cpu = <&CPU8>;
+ };
+ core1 {
+ cpu = <&CPU9>;
+ };
+ core2 {
+ cpu = <&CPU10>;
+ };
+ core3 {
+ cpu = <&CPU11>;
+ };
+ };
+ cluster3 {
+ core0 {
+ cpu = <&CPU12>;
+ };
+ core1 {
+ cpu = <&CPU13>;
+ };
+ core2 {
+ cpu = <&CPU14>;
+ };
+ core3 {
+ cpu = <&CPU15>;
+ };
+ };
+ };
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ };
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ };
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ };
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ };
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x100>;
+ };
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x101>;
+ };
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x102>;
+ };
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x103>;
+ };
+ CPU8: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x200>;
+ };
+ CPU9: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x201>;
+ };
+ CPU10: cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x202>;
+ };
+ CPU11: cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x203>;
+ };
+ CPU12: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x300>;
+ };
+ CPU13: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x301>;
+ };
+ CPU14: cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x302>;
+ };
+ CPU15: cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x303>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ clk_50m: clk_50m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ clk_168m: clk_168m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <168000000>;
+ };
+
+ soc {
+ /* It's a 32-bit SoC. */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0 0 0xe0000000 0x10000000>;
+
+ gic: interrupt-controller@c01000 {
+ compatible = "hisilicon,hip04-intc";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <1 9 0xf04>;
+
+ reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
+ <0xc04000 0x2000>, <0xc06000 0x2000>;
+ };
+
+ sysctrl: sysctrl {
+ compatible = "hisilicon,sysctrl";
+ reg = <0x3e00000 0x00100000>;
+ };
+
+ fabric: fabric {
+ compatible = "hisilicon,hip04-fabric";
+ reg = <0x302a000 0x1000>;
+ };
+
+ dual_timer0: dual_timer@3000000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x3000000 0x1000>;
+ interrupts = <0 224 4>;
+ clocks = <&clk_50m>, <&clk_50m>;
+ clock-names = "apb_pclk";
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <0 64 4>,
+ <0 65 4>,
+ <0 66 4>,
+ <0 67 4>,
+ <0 68 4>,
+ <0 69 4>,
+ <0 70 4>,
+ <0 71 4>,
+ <0 72 4>,
+ <0 73 4>,
+ <0 74 4>,
+ <0 75 4>,
+ <0 76 4>,
+ <0 77 4>,
+ <0 78 4>,
+ <0 79 4>;
+ };
+
+ uart0: uart@4007000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x4007000 0x1000>;
+ interrupts = <0 381 4>;
+ clocks = <&clk_168m>;
+ clock-names = "uartclk";
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sata0: sata@a000000 {
+ compatible = "hisilicon,hisi-ahci";
+ reg = <0xa000000 0x1000000>;
+ interrupts = <0 372 4>;
+ };
+
+ };
+};
diff --git a/dts/src/arm/imx1-ads.dts b/dts/src/arm/imx1-ads.dts
new file mode 100644
index 0000000..af4eee5
--- /dev/null
+++ b/dts/src/arm/imx1-ads.dts
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx1.dtsi"
+
+/ {
+ model = "Freescale MX1 ADS";
+ compatible = "fsl,imx1ads", "fsl,imx1";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ reg = <0x08000000 0x04000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32 {
+ compatible = "fsl,imx-clk32", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+ };
+};
+
+&cspi1 {
+ pinctrl-0 = <&pinctrl_cspi1>;
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&i2c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c>;
+ status = "okay";
+
+ extgpio0: pcf8575@22 {
+ compatible = "nxp,pcf8575";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ extgpio1: pcf8575@24 {
+ compatible = "nxp,pcf8575";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim>;
+ status = "okay";
+
+ nor: nor@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0x00000000 0x02000000>;
+ bank-width = <4>;
+ fsl,weim-cs-timing = <0x00003e00 0x00000801>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&iomuxc {
+ imx1-ads {
+ pinctrl_cspi1: cspi1grp {
+ fsl,pins = <
+ MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
+ MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
+ MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
+ MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
+ MX1_PAD_SPI1_SS__GPIO3_15 0x0
+ >;
+ };
+
+ pinctrl_i2c: i2cgrp {
+ fsl,pins = <
+ MX1_PAD_I2C_SCL__I2C_SCL 0x0
+ MX1_PAD_I2C_SDA__I2C_SDA 0x0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX1_PAD_UART1_TXD__UART1_TXD 0x0
+ MX1_PAD_UART1_RXD__UART1_RXD 0x0
+ MX1_PAD_UART1_CTS__UART1_CTS 0x0
+ MX1_PAD_UART1_RTS__UART1_RTS 0x0
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX1_PAD_UART2_TXD__UART2_TXD 0x0
+ MX1_PAD_UART2_RXD__UART2_RXD 0x0
+ MX1_PAD_UART2_CTS__UART2_CTS 0x0
+ MX1_PAD_UART2_RTS__UART2_RTS 0x0
+ >;
+ };
+
+ pinctrl_weim: weimgrp {
+ fsl,pins = <
+ MX1_PAD_A0__A0 0x0
+ MX1_PAD_A16__A16 0x0
+ MX1_PAD_A17__A17 0x0
+ MX1_PAD_A18__A18 0x0
+ MX1_PAD_A19__A19 0x0
+ MX1_PAD_A20__A20 0x0
+ MX1_PAD_A21__A21 0x0
+ MX1_PAD_A22__A22 0x0
+ MX1_PAD_A23__A23 0x0
+ MX1_PAD_A24__A24 0x0
+ MX1_PAD_BCLK__BCLK 0x0
+ MX1_PAD_CS4__CS4 0x0
+ MX1_PAD_DTACK__DTACK 0x0
+ MX1_PAD_ECB__ECB 0x0
+ MX1_PAD_LBA__LBA 0x0
+ >;
+ };
+ };
+};
diff --git a/dts/src/arm/imx1-apf9328.dts b/dts/src/arm/imx1-apf9328.dts
new file mode 100644
index 0000000..07d92fb
--- /dev/null
+++ b/dts/src/arm/imx1-apf9328.dts
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx1.dtsi"
+
+/ {
+ model = "Armadeus APF9328";
+ compatible = "armadeus,imx1-apf9328", "fsl,imx1";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ reg = <0x08000000 0x00800000>;
+ };
+};
+
+&i2c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim>;
+ status = "okay";
+
+ nor: nor@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0x00000000 0x02000000>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ eth: eth@4,c00000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth>;
+ compatible = "davicom,dm9000";
+ reg = <
+ 4 0x00c00000 0x2
+ 4 0x00c00002 0x2
+ >;
+ interrupt-parent = <&gpio2>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
+ };
+};
+
+&iomuxc {
+ imx1-apf9328 {
+ pinctrl_eth: ethgrp {
+ fsl,pins = <
+ MX1_PAD_SIM_SVEN__GPIO2_14 0x0
+ >;
+ };
+
+ pinctrl_i2c: i2cgrp {
+ fsl,pins = <
+ MX1_PAD_I2C_SCL__I2C_SCL 0x0
+ MX1_PAD_I2C_SDA__I2C_SDA 0x0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX1_PAD_UART1_TXD__UART1_TXD 0x0
+ MX1_PAD_UART1_RXD__UART1_RXD 0x0
+ MX1_PAD_UART1_CTS__UART1_CTS 0x0
+ MX1_PAD_UART1_RTS__UART1_RTS 0x0
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX1_PAD_UART2_TXD__UART2_TXD 0x0
+ MX1_PAD_UART2_RXD__UART2_RXD 0x0
+ MX1_PAD_UART2_CTS__UART2_CTS 0x0
+ MX1_PAD_UART2_RTS__UART2_RTS 0x0
+ >;
+ };
+
+ pinctrl_weim: weimgrp {
+ fsl,pins = <
+ MX1_PAD_A0__A0 0x0
+ MX1_PAD_A16__A16 0x0
+ MX1_PAD_A17__A17 0x0
+ MX1_PAD_A18__A18 0x0
+ MX1_PAD_A19__A19 0x0
+ MX1_PAD_A20__A20 0x0
+ MX1_PAD_A21__A21 0x0
+ MX1_PAD_A22__A22 0x0
+ MX1_PAD_A23__A23 0x0
+ MX1_PAD_A24__A24 0x0
+ MX1_PAD_BCLK__BCLK 0x0
+ MX1_PAD_CS4__CS4 0x0
+ MX1_PAD_DTACK__DTACK 0x0
+ MX1_PAD_ECB__ECB 0x0
+ MX1_PAD_LBA__LBA 0x0
+ >;
+ };
+ };
+};
diff --git a/dts/src/arm/imx1-pinfunc.h b/dts/src/arm/imx1-pinfunc.h
new file mode 100644
index 0000000..22bec8b
--- /dev/null
+++ b/dts/src/arm/imx1-pinfunc.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DTS_IMX1_PINFUNC_H
+#define __DTS_IMX1_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <pin mux_id>
+ * mux_id consists of
+ * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+ *
+ * function: 0 - Primary function
+ * 1 - Alternate function
+ * 2 - GPIO
+ * direction: 0 - Input
+ * 1 - Output
+ * gpio_oconf: 0 - A_IN
+ * 1 - B_IN
+ * 2 - A_OUT
+ * 3 - Data Register
+ * gpio_iconfa/b: 0 - GPIO_IN
+ * 1 - Interrupt Status Register
+ * 2 - 0
+ * 3 - 1
+ *
+ * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
+ * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ * number on the specific port (between 0 and 31).
+ */
+
+#define MX1_PAD_A24__A24 0x00 0x004
+#define MX1_PAD_A24__GPIO1_0 0x00 0x032
+#define MX1_PAD_A24__SPI2_CLK 0x00 0x006
+#define MX1_PAD_TIN__TIN 0x01 0x000
+#define MX1_PAD_TIN__GPIO1_1 0x01 0x032
+#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022
+#define MX1_PAD_PWMO__PWMO 0x02 0x004
+#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032
+#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004
+#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032
+#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000
+#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032
+#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000
+#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032
+#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000
+#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032
+#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000
+#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032
+#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000
+#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032
+#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000
+#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032
+#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000
+#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032
+#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000
+#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032
+#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000
+#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032
+#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000
+#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032
+#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000
+#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032
+#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000
+#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032
+#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004
+#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032
+#define MX1_PAD_DTACK__DTACK 0x11 0x000
+#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032
+#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002
+#define MX1_PAD_DTACK__A25 0x11 0x016
+#define MX1_PAD_BCLK__BCLK 0x12 0x004
+#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032
+#define MX1_PAD_LBA__LBA 0x13 0x004
+#define MX1_PAD_LBA__GPIO1_19 0x13 0x032
+#define MX1_PAD_ECB__ECB 0x14 0x000
+#define MX1_PAD_ECB__GPIO1_20 0x14 0x032
+#define MX1_PAD_A0__A0 0x15 0x004
+#define MX1_PAD_A0__GPIO1_21 0x15 0x032
+#define MX1_PAD_CS4__CS4 0x16 0x004
+#define MX1_PAD_CS4__GPIO1_22 0x16 0x032
+#define MX1_PAD_CS5__CS5 0x17 0x004
+#define MX1_PAD_CS5__GPIO1_23 0x17 0x032
+#define MX1_PAD_A16__A16 0x18 0x004
+#define MX1_PAD_A16__GPIO1_24 0x18 0x032
+#define MX1_PAD_A17__A17 0x19 0x004
+#define MX1_PAD_A17__GPIO1_25 0x19 0x032
+#define MX1_PAD_A18__A18 0x1a 0x004
+#define MX1_PAD_A18__GPIO1_26 0x1a 0x032
+#define MX1_PAD_A19__A19 0x1b 0x004
+#define MX1_PAD_A19__GPIO1_27 0x1b 0x032
+#define MX1_PAD_A20__A20 0x1c 0x004
+#define MX1_PAD_A20__GPIO1_28 0x1c 0x032
+#define MX1_PAD_A21__A21 0x1d 0x004
+#define MX1_PAD_A21__GPIO1_29 0x1d 0x032
+#define MX1_PAD_A22__A22 0x1e 0x004
+#define MX1_PAD_A22__GPIO1_30 0x1e 0x032
+#define MX1_PAD_A23__A23 0x1f 0x004
+#define MX1_PAD_A23__GPIO1_31 0x1f 0x032
+#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000
+#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001
+#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032
+#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000
+#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001
+#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032
+#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000
+#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001
+#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032
+#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000
+#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001
+#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032
+#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004
+#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005
+#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032
+#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000
+#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005
+#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032
+#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004
+#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001
+#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032
+#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000
+#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001
+#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032
+#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000
+#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001
+#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032
+#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000
+#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005
+#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032
+#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004
+#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001
+#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032
+#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004
+#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001
+#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032
+#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004
+#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032
+#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004
+#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032
+#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000
+#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032
+#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004
+#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032
+#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000
+#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032
+#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000
+#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032
+#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004
+#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032
+#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004
+#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032
+#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004
+#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032
+#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000
+#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032
+#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004
+#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032
+#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000
+#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032
+#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000
+#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032
+#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000
+#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032
+#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000
+#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032
+#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004
+#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032
+#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000
+#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032
+#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000
+#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032
+#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004
+#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032
+#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000
+#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032
+#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004
+#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032
+#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000
+#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032
+#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000
+#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032
+#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004
+#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032
+#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000
+#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032
+#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000
+#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032
+#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004
+#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032
+#define MX1_PAD_BT13__BT13 0x53 0x004
+#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001
+#define MX1_PAD_BT13__GPIO3_19 0x53 0x032
+#define MX1_PAD_BT12__BT12 0x54 0x004
+#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001
+#define MX1_PAD_BT12__GPIO3_20 0x54 0x032
+#define MX1_PAD_BT11__BT11 0x55 0x004
+#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001
+#define MX1_PAD_BT11__GPIO3_21 0x55 0x032
+#define MX1_PAD_BT10__BT10 0x56 0x004
+#define MX1_PAD_BT10__SSI2_TX 0x56 0x001
+#define MX1_PAD_BT10__GPIO3_22 0x56 0x032
+#define MX1_PAD_BT9__BT9 0x57 0x004
+#define MX1_PAD_BT9__SSI2_RX 0x57 0x001
+#define MX1_PAD_BT9__GPIO3_23 0x57 0x032
+#define MX1_PAD_BT8__BT8 0x58 0x004
+#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001
+#define MX1_PAD_BT8__GPIO3_24 0x58 0x032
+#define MX1_PAD_BT8__UART3_RI 0x58 0x016
+#define MX1_PAD_BT7__BT7 0x59 0x004
+#define MX1_PAD_BT7__GPIO3_25 0x59 0x032
+#define MX1_PAD_BT7__UART3_DSR 0x59 0x016
+#define MX1_PAD_BT6__BT6 0x5a 0x004
+#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032
+#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016
+#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022
+#define MX1_PAD_BT5__BT5 0x5b 0x000
+#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032
+#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016
+#define MX1_PAD_BT4__BT4 0x5c 0x000
+#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032
+#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016
+#define MX1_PAD_BT3__BT3 0x5d 0x000
+#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032
+#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022
+#define MX1_PAD_BT2__BT2 0x5e 0x004
+#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032
+#define MX1_PAD_BT2__UART3_TX 0x5e 0x016
+#define MX1_PAD_BT1__BT1 0x5f 0x000
+#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032
+#define MX1_PAD_BT1__UART3_RX 0x5f 0x022
+#define MX1_PAD_LSCLK__LSCLK 0x66 0x004
+#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032
+#define MX1_PAD_REV__REV 0x67 0x004
+#define MX1_PAD_REV__UART2_DTR 0x67 0x001
+#define MX1_PAD_REV__GPIO4_7 0x67 0x032
+#define MX1_PAD_REV__SPI2_CLK 0x67 0x006
+#define MX1_PAD_CLS__CLS 0x68 0x004
+#define MX1_PAD_CLS__UART2_DCD 0x68 0x005
+#define MX1_PAD_CLS__GPIO4_8 0x68 0x032
+#define MX1_PAD_CLS__SPI2_SS 0x68 0x002
+#define MX1_PAD_PS__PS 0x69 0x004
+#define MX1_PAD_PS__UART2_RI 0x69 0x005
+#define MX1_PAD_PS__GPIO4_9 0x69 0x032
+#define MX1_PAD_PS__SPI2_RXD 0x69 0x022
+#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004
+#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005
+#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032
+#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006
+#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004
+#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032
+#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012
+#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004
+#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032
+#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004
+#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032
+#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004
+#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032
+#define MX1_PAD_LD0__LD0 0x6f 0x004
+#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032
+#define MX1_PAD_LD1__LD1 0x70 0x004
+#define MX1_PAD_LD1__GPIO4_16 0x70 0x032
+#define MX1_PAD_LD2__LD2 0x71 0x004
+#define MX1_PAD_LD2__GPIO4_17 0x71 0x032
+#define MX1_PAD_LD3__LD3 0x72 0x004
+#define MX1_PAD_LD3__GPIO4_18 0x72 0x032
+#define MX1_PAD_LD4__LD4 0x73 0x004
+#define MX1_PAD_LD4__GPIO4_19 0x73 0x032
+#define MX1_PAD_LD5__LD5 0x74 0x004
+#define MX1_PAD_LD5__GPIO4_20 0x74 0x032
+#define MX1_PAD_LD6__LD6 0x75 0x004
+#define MX1_PAD_LD6__GPIO4_21 0x75 0x032
+#define MX1_PAD_LD7__LD7 0x76 0x004
+#define MX1_PAD_LD7__GPIO4_22 0x76 0x032
+#define MX1_PAD_LD8__LD8 0x77 0x004
+#define MX1_PAD_LD8__GPIO4_23 0x77 0x032
+#define MX1_PAD_LD9__LD9 0x78 0x004
+#define MX1_PAD_LD9__GPIO4_24 0x78 0x032
+#define MX1_PAD_LD10__LD10 0x79 0x004
+#define MX1_PAD_LD10__GPIO4_25 0x79 0x032
+#define MX1_PAD_LD11__LD11 0x7a 0x004
+#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032
+#define MX1_PAD_LD12__LD12 0x7b 0x004
+#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032
+#define MX1_PAD_LD13__LD13 0x7c 0x004
+#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032
+#define MX1_PAD_LD14__LD14 0x7d 0x004
+#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032
+#define MX1_PAD_LD15__LD15 0x7e 0x004
+#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032
+#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000
+#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032
+#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006
+
+#endif
diff --git a/dts/src/arm/imx1.dtsi b/dts/src/arm/imx1.dtsi
new file mode 100644
index 0000000..22f5d1d
--- /dev/null
+++ b/dts/src/arm/imx1.dtsi
@@ -0,0 +1,266 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include "imx1-pinfunc.h"
+
+#include <dt-bindings/clock/imx1-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ i2c0 = &i2c;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ spi0 = &cspi1;
+ spi1 = &cspi2;
+ };
+
+ aitc: aitc-interrupt-controller@00223000 {
+ compatible = "fsl,imx1-aitc", "fsl,avic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x00223000 0x1000>;
+ };
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,arm920t";
+ operating-points = <200000 1900000>;
+ clock-latency = <62500>;
+ clocks = <&clks IMX1_CLK_MCU>;
+ voltage-tolerance = <5>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&aitc>;
+ ranges;
+
+ aipi@00200000 {
+ compatible = "fsl,aipi-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x00200000 0x10000>;
+ ranges;
+
+ gpt1: timer@00202000 {
+ compatible = "fsl,imx1-gpt";
+ reg = <0x00202000 0x1000>;
+ interrupts = <59>;
+ clocks = <&clks IMX1_CLK_HCLK>,
+ <&clks IMX1_CLK_PER1>;
+ clock-names = "ipg", "per";
+ };
+
+ gpt2: timer@00203000 {
+ compatible = "fsl,imx1-gpt";
+ reg = <0x00203000 0x1000>;
+ interrupts = <58>;
+ clocks = <&clks IMX1_CLK_HCLK>,
+ <&clks IMX1_CLK_PER1>;
+ clock-names = "ipg", "per";
+ };
+
+ fb: fb@00205000 {
+ compatible = "fsl,imx1-fb";
+ reg = <0x00205000 0x1000>;
+ interrupts = <14>;
+ clocks = <&clks IMX1_CLK_DUMMY>,
+ <&clks IMX1_CLK_DUMMY>,
+ <&clks IMX1_CLK_PER2>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ uart1: serial@00206000 {
+ compatible = "fsl,imx1-uart";
+ reg = <0x00206000 0x1000>;
+ interrupts = <30 29 26>;
+ clocks = <&clks IMX1_CLK_HCLK>,
+ <&clks IMX1_CLK_PER1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial@00207000 {
+ compatible = "fsl,imx1-uart";
+ reg = <0x00207000 0x1000>;
+ interrupts = <24 23 20>;
+ clocks = <&clks IMX1_CLK_HCLK>,
+ <&clks IMX1_CLK_PER1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ pwm: pwm@00208000 {
+ #pwm-cells = <2>;
+ compatible = "fsl,imx1-pwm";
+ reg = <0x00208000 0x1000>;
+ interrupts = <34>;
+ clocks = <&clks IMX1_CLK_DUMMY>,
+ <&clks IMX1_CLK_PER1>;
+ clock-names = "ipg", "per";
+ };
+
+ dma: dma@00209000 {
+ compatible = "fsl,imx1-dma";
+ reg = <0x00209000 0x1000>;
+ interrupts = <61 60>;
+ clocks = <&clks IMX1_CLK_HCLK>,
+ <&clks IMX1_CLK_DMA_GATE>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <1>;
+ };
+
+ uart3: serial@0020a000 {
+ compatible = "fsl,imx1-uart";
+ reg = <0x0020a000 0x1000>;
+ interrupts = <54 4 1>;
+ clocks = <&clks IMX1_CLK_UART3_GATE>,
+ <&clks IMX1_CLK_PER1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+
+ aipi@00210000 {
+ compatible = "fsl,aipi-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x00210000 0x10000>;
+ ranges;
+
+ cspi1: cspi@00213000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx1-cspi";
+ reg = <0x00213000 0x1000>;
+ interrupts = <41>;
+ clocks = <&clks IMX1_CLK_DUMMY>,
+ <&clks IMX1_CLK_PER1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c: i2c@00217000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx1-i2c";
+ reg = <0x00217000 0x1000>;
+ interrupts = <39>;
+ clocks = <&clks IMX1_CLK_HCLK>;
+ status = "disabled";
+ };
+
+ cspi2: cspi@00219000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx1-cspi";
+ reg = <0x00219000 0x1000>;
+ interrupts = <40>;
+ clocks = <&clks IMX1_CLK_DUMMY>,
+ <&clks IMX1_CLK_PER1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ clks: ccm@0021b000 {
+ compatible = "fsl,imx1-ccm";
+ reg = <0x0021b000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ iomuxc: iomuxc@0021c000 {
+ compatible = "fsl,imx1-iomuxc";
+ reg = <0x0021c000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio1: gpio@0021c000 {
+ compatible = "fsl,imx1-gpio";
+ reg = <0x0021c000 0x100>;
+ interrupts = <11>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@0021c100 {
+ compatible = "fsl,imx1-gpio";
+ reg = <0x0021c100 0x100>;
+ interrupts = <12>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@0021c200 {
+ compatible = "fsl,imx1-gpio";
+ reg = <0x0021c200 0x100>;
+ interrupts = <13>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@0021c300 {
+ compatible = "fsl,imx1-gpio";
+ reg = <0x0021c300 0x100>;
+ interrupts = <62>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ };
+
+ weim: weim@00220000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,imx1-weim";
+ reg = <0x00220000 0x1000>;
+ clocks = <&clks IMX1_CLK_DUMMY>;
+ ranges = <
+ 0 0 0x10000000 0x02000000
+ 1 0 0x12000000 0x01000000
+ 2 0 0x13000000 0x01000000
+ 3 0 0x14000000 0x01000000
+ 4 0 0x15000000 0x01000000
+ 5 0 0x16000000 0x01000000
+ >;
+ status = "disabled";
+ };
+
+ esram: esram@00300000 {
+ compatible = "mmio-sram";
+ reg = <0x00300000 0x20000>;
+ };
+ };
+};
diff --git a/dts/src/arm/imx23-evk.dts b/dts/src/arm/imx23-evk.dts
index a33f66c..57e2997 100644
--- a/dts/src/arm/imx23-evk.dts
+++ b/dts/src/arm/imx23-evk.dts
@@ -60,10 +60,10 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a>;
lcd-supply = <&reg_lcd_3v3>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
diff --git a/dts/src/arm/imx25-pinfunc.h b/dts/src/arm/imx25-pinfunc.h
index 9238a95..88eebb1 100644
--- a/dts/src/arm/imx25-pinfunc.h
+++ b/dts/src/arm/imx25-pinfunc.h
@@ -247,6 +247,7 @@
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
+#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x11 0x000
#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
@@ -260,6 +261,7 @@
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
+#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
@@ -269,31 +271,46 @@
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
+#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
+#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
+#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x12 0x001
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
+#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001
#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
+#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
+#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001
#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
+#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
+#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001
+#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
+#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001
+#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
+#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001
+#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
+#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001
+#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
@@ -303,18 +320,24 @@
#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000
#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x12 0x000
#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001
+#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
@@ -328,6 +351,7 @@
#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
+#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000
#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
@@ -342,6 +366,7 @@
#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
+#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
@@ -349,14 +374,17 @@
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
+#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001
#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
+#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x11 0x001
#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x11 0x001
#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
@@ -457,14 +485,15 @@
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
-#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
-#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000
+#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
+#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
+#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
diff --git a/dts/src/arm/imx25.dtsi b/dts/src/arm/imx25.dtsi
index c174039..58d3c3c 100644
--- a/dts/src/arm/imx25.dtsi
+++ b/dts/src/arm/imx25.dtsi
@@ -239,6 +239,7 @@
};
ssi2: ssi@50014000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50014000 0x4000>;
interrupts = <11>;
@@ -274,6 +275,7 @@
};
ssi1: ssi@50034000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50034000 0x4000>;
interrupts = <12>;
@@ -453,7 +455,7 @@
};
sdma: sdma@53fd4000 {
- compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
+ compatible = "fsl,imx25-sdma";
reg = <0x53fd4000 0x4000>;
clocks = <&clks 112>, <&clks 68>;
clock-names = "ipg", "ahb";
diff --git a/dts/src/arm/imx27-apf27dev.dts b/dts/src/arm/imx27-apf27dev.dts
index 2b6d489..da306c5 100644
--- a/dts/src/arm/imx27-apf27dev.dts
+++ b/dts/src/arm/imx27-apf27dev.dts
@@ -67,6 +67,16 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
status = "okay";
+
+ adc@0 {
+ compatible = "maxim,max1027";
+ reg = <0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max1027>;
+ spi-max-frequency = <10000000>;
+ };
};
&cspi2 {
@@ -189,6 +199,13 @@
>;
};
+ pinctrl_max1027: max1027 {
+ fsl,pins = <
+ MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
+ MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
+ >;
+ };
+
pinctrl_pwm: pwmgrp {
fsl,pins = <
MX27_PAD_PWMO__PWMO 0x0
diff --git a/dts/src/arm/imx28-apf28dev.dts b/dts/src/arm/imx28-apf28dev.dts
index 221cac4..1f38a05 100644
--- a/dts/src/arm/imx28-apf28dev.dts
+++ b/dts/src/arm/imx28-apf28dev.dts
@@ -83,10 +83,10 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_16bit_pins_a
&lcdif_pins_apf28dev>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
diff --git a/dts/src/arm/imx28-apx4devkit.dts b/dts/src/arm/imx28-apx4devkit.dts
index e1ce917..1092b76 100644
--- a/dts/src/arm/imx28-apx4devkit.dts
+++ b/dts/src/arm/imx28-apx4devkit.dts
@@ -94,10 +94,10 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_apx4>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
diff --git a/dts/src/arm/imx28-cfa10049.dts b/dts/src/arm/imx28-cfa10049.dts
index 7d51459..ef944b6 100644
--- a/dts/src/arm/imx28-cfa10049.dts
+++ b/dts/src/arm/imx28-cfa10049.dts
@@ -177,10 +177,10 @@
pinctrl-0 = <&lcdif_18bit_pins_cfa10049
&lcdif_pins_cfa10049
&lcdif_pins_cfa10049_pullup>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <18>;
diff --git a/dts/src/arm/imx28-cfa10055.dts b/dts/src/arm/imx28-cfa10055.dts
index c3900e7..6a34114 100644
--- a/dts/src/arm/imx28-cfa10055.dts
+++ b/dts/src/arm/imx28-cfa10055.dts
@@ -92,10 +92,10 @@
pinctrl-0 = <&lcdif_18bit_pins_cfa10055
&lcdif_pins_cfa10055
&lcdif_pins_cfa10055_pullup>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <18>;
diff --git a/dts/src/arm/imx28-cfa10056.dts b/dts/src/arm/imx28-cfa10056.dts
index cef959a..ba6495c 100644
--- a/dts/src/arm/imx28-cfa10056.dts
+++ b/dts/src/arm/imx28-cfa10056.dts
@@ -64,10 +64,10 @@
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_cfa10056
&lcdif_pins_cfa10056_pullup >;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
diff --git a/dts/src/arm/imx28-cfa10057.dts b/dts/src/arm/imx28-cfa10057.dts
index c4e00ce..5df0b24 100644
--- a/dts/src/arm/imx28-cfa10057.dts
+++ b/dts/src/arm/imx28-cfa10057.dts
@@ -78,10 +78,10 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_18bit_pins_cfa10057
&lcdif_pins_cfa10057>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <18>;
diff --git a/dts/src/arm/imx28-cfa10058.dts b/dts/src/arm/imx28-cfa10058.dts
index 7c9cc78..f5c6dce 100644
--- a/dts/src/arm/imx28-cfa10058.dts
+++ b/dts/src/arm/imx28-cfa10058.dts
@@ -51,10 +51,10 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_cfa10058>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
diff --git a/dts/src/arm/imx28-evk.dts b/dts/src/arm/imx28-evk.dts
index e4cc44c..09664fc 100644
--- a/dts/src/arm/imx28-evk.dts
+++ b/dts/src/arm/imx28-evk.dts
@@ -124,10 +124,10 @@
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_evk>;
lcd-supply = <&reg_lcd_3v3>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
diff --git a/dts/src/arm/imx28-m28cu3.dts b/dts/src/arm/imx28-m28cu3.dts
index 9348ce5..2df63be 100644
--- a/dts/src/arm/imx28-m28cu3.dts
+++ b/dts/src/arm/imx28-m28cu3.dts
@@ -115,10 +115,10 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_m28>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display0 {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
diff --git a/dts/src/arm/imx28-m28evk.dts b/dts/src/arm/imx28-m28evk.dts
index b3c09ae..e35cc6b 100644
--- a/dts/src/arm/imx28-m28evk.dts
+++ b/dts/src/arm/imx28-m28evk.dts
@@ -81,10 +81,10 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_m28>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display {
+ display0: display0 {
bits-per-pixel = <16>;
bus-width = <18>;
diff --git a/dts/src/arm/imx28-tx28.dts b/dts/src/arm/imx28-tx28.dts
index e14bd86..a5b27c8 100644
--- a/dts/src/arm/imx28-tx28.dts
+++ b/dts/src/arm/imx28-tx28.dts
@@ -21,12 +21,15 @@
aliases {
can0 = &can0;
can1 = &can1;
- display = &display;
+ display = &display0;
ds1339 = &ds1339;
gpio5 = &gpio5;
lcdif = &lcdif;
lcdif_23bit_pins = &tx28_lcdif_23bit_pins;
lcdif_24bit_pins = &lcdif_24bit_pins_a;
+ reg_can_xcvr = &reg_can_xcvr;
+ spi_gpio = &spi_gpio;
+ spi_mxs = &ssp3;
stk5led = &user_led;
usbotg = &usb0;
};
@@ -37,7 +40,7 @@
onewire {
compatible = "w1-gpio";
- gpios = <&gpio2 7 0>;
+ gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -52,7 +55,7 @@
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio0 18 0>;
+ gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -62,7 +65,7 @@
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 27 0>;
+ gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -90,7 +93,7 @@
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 0 0>;
+ gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
};
@@ -101,7 +104,7 @@
regulator-name = "LCD POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 31 0>;
+ gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -111,7 +114,7 @@
regulator-name = "LCD RESET";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio3 30 0>;
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
startup-delay-us = <300000>;
enable-active-high;
regulator-always-on;
@@ -143,7 +146,7 @@
user_led: user {
label = "Heartbeat";
- gpios = <&gpio4 10 0>;
+ gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
@@ -172,16 +175,16 @@
matrix_keypad: matrix-keypad@0 {
compatible = "gpio-matrix-keypad";
col-gpios = <
- &gpio5 0 0
- &gpio5 1 0
- &gpio5 2 0
- &gpio5 3 0
+ &gpio5 0 GPIO_ACTIVE_HIGH
+ &gpio5 1 GPIO_ACTIVE_HIGH
+ &gpio5 2 GPIO_ACTIVE_HIGH
+ &gpio5 3 GPIO_ACTIVE_HIGH
>;
row-gpios = <
- &gpio5 4 0
- &gpio5 5 0
- &gpio5 6 0
- &gpio5 7 0
+ &gpio5 4 GPIO_ACTIVE_HIGH
+ &gpio5 5 GPIO_ACTIVE_HIGH
+ &gpio5 6 GPIO_ACTIVE_HIGH
+ &gpio5 7 GPIO_ACTIVE_HIGH
>;
/* sample keymap */
linux,keymap = <
@@ -203,6 +206,44 @@
col-scan-delay-us = <5000>;
linux,no-autorepeat;
};
+
+ spi_gpio: spi-gpio {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tx28_spi_gpio_pins>;
+
+ gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>;
+ gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+ gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ num-chipselects = <3>;
+ cs-gpios = <
+ &gpio2 27 GPIO_ACTIVE_LOW
+ &gpio3 8 GPIO_ACTIVE_LOW
+ &gpio3 9 GPIO_ACTIVE_LOW
+ >;
+ /* enable this and disable ssp3 below, if you need full duplex SPI transfer */
+ status = "disabled";
+
+ spi@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <57600000>;
+ };
+
+ spi@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency = <57600000>;
+ };
+
+ spi@2 {
+ compatible = "spidev";
+ reg = <2>;
+ spi-max-frequency = <57600000>;
+ };
+ };
};
/* 2nd TX-Std UART - (A)UART1 */
@@ -284,8 +325,8 @@
pinctrl-0 = <&tx28_edt_ft5x06_pins>;
interrupt-parent = <&gpio2>;
interrupts = <5 0>;
- reset-gpios = <&gpio2 6 1>;
- wake-gpios = <&gpio4 9 0>;
+ reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
};
touchscreen: tsc2007@48 {
@@ -295,7 +336,7 @@
pinctrl-0 = <&tx28_tsc2007_pins>;
interrupt-parent = <&gpio3>;
interrupts = <20 0>;
- pendown-gpio = <&gpio3 20 1>;
+ pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
ti,x-plate-ohms = /bits/ 16 <660>;
};
@@ -309,10 +350,10 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>;
lcd-supply = <&reg_lcd>;
- display = <&display>;
+ display = <&display0>;
status = "okay";
- display: display@0 {
+ display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
@@ -558,6 +599,20 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
+ tx28_spi_gpio_pins: spi-gpiogrp {
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_RX__GPIO_3_8
+ MX28_PAD_AUART2_TX__GPIO_3_9
+ MX28_PAD_SSP3_SCK__GPIO_2_24
+ MX28_PAD_SSP3_MOSI__GPIO_2_25
+ MX28_PAD_SSP3_MISO__GPIO_2_26
+ MX28_PAD_SSP3_SS0__GPIO_2_27
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
tx28_tsc2007_pins: tx28-tsc2007-pins {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
@@ -619,17 +674,23 @@
clock-frequency = <57600000>;
status = "okay";
- spidev0: spi@0 {
+ spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <57600000>;
};
- spidev1: spi@1 {
+ spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <57600000>;
};
+
+ spi@2 {
+ compatible = "spidev";
+ reg = <2>;
+ spi-max-frequency = <57600000>;
+ };
};
&usb0 {
diff --git a/dts/src/arm/imx28.dtsi b/dts/src/arm/imx28.dtsi
index a95cc53..47f68ac 100644
--- a/dts/src/arm/imx28.dtsi
+++ b/dts/src/arm/imx28.dtsi
@@ -489,6 +489,38 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
+ mmc1_4bit_pins_a: mmc1-4bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D00__SSP1_D0
+ MX28_PAD_GPMI_D01__SSP1_D1
+ MX28_PAD_GPMI_D02__SSP1_D2
+ MX28_PAD_GPMI_D03__SSP1_D3
+ MX28_PAD_GPMI_RDY1__SSP1_CMD
+ MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
+ MX28_PAD_GPMI_WRN__SSP1_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc1_cd_cfg: mmc1-cd-cfg {
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
+ >;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc1_sck_cfg: mmc1-sck-cfg {
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_WRN__SSP1_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+
mmc2_4bit_pins_a: mmc2-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
@@ -553,6 +585,17 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
+ i2c1_pins_b: i2c1@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_CTS__I2C1_SCL
+ MX28_PAD_AUART2_RTS__I2C1_SDA
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
saif0_pins_a: saif0@0 {
reg = <0>;
fsl,pinmux-ids = <
diff --git a/dts/src/arm/imx35.dtsi b/dts/src/arm/imx35.dtsi
index 442e216..6932928 100644
--- a/dts/src/arm/imx35.dtsi
+++ b/dts/src/arm/imx35.dtsi
@@ -114,6 +114,7 @@
};
ssi1: ssi@43fa0000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
reg = <0x43fa0000 0x4000>;
interrupts = <11>;
diff --git a/dts/src/arm/imx50.dtsi b/dts/src/arm/imx50.dtsi
index c0e0f60..620b0f0 100644
--- a/dts/src/arm/imx50.dtsi
+++ b/dts/src/arm/imx50.dtsi
@@ -145,6 +145,7 @@
};
ssi2: ssi@50014000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx50-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
@@ -454,6 +455,7 @@
};
ssi1: ssi@63fcc000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>;
diff --git a/dts/src/arm/imx51.dtsi b/dts/src/arm/imx51.dtsi
index 17c05a6..92660e1 100644
--- a/dts/src/arm/imx51.dtsi
+++ b/dts/src/arm/imx51.dtsi
@@ -210,6 +210,7 @@
};
ssi2: ssi@70014000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>;
interrupts = <30>;
@@ -499,6 +500,7 @@
};
ssi1: ssi@83fcc000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fcc000 0x4000>;
interrupts = <29>;
@@ -554,6 +556,7 @@
};
ssi3: ssi@83fe8000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fe8000 0x4000>;
interrupts = <96>;
diff --git a/dts/src/arm/imx53-smd.dts b/dts/src/arm/imx53-smd.dts
index 5ec1590..1d32557 100644
--- a/dts/src/arm/imx53-smd.dts
+++ b/dts/src/arm/imx53-smd.dts
@@ -265,7 +265,7 @@
};
pmic: dialog@48 {
- compatible = "dialog,da9053", "dialog,da9052";
+ compatible = "dlg,da9053", "dlg,da9052";
reg = <0x48>;
};
};
diff --git a/dts/src/arm/imx53.dtsi b/dts/src/arm/imx53.dtsi
index c6c58c1..f91725b 100644
--- a/dts/src/arm/imx53.dtsi
+++ b/dts/src/arm/imx53.dtsi
@@ -221,6 +221,7 @@
};
ssi2: ssi@50014000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx53-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
@@ -423,10 +424,14 @@
status = "disabled";
lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0>;
status = "disabled";
- port {
+ port@0 {
+ reg = <0>;
+
lvds0_in: endpoint {
remote-endpoint = <&ipu_di0_lvds0>;
};
@@ -434,10 +439,14 @@
};
lvds-channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
status = "disabled";
- port {
+ port@1 {
+ reg = <1>;
+
lvds1_in: endpoint {
remote-endpoint = <&ipu_di1_lvds1>;
};
@@ -661,6 +670,7 @@
};
ssi1: ssi@63fcc000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>;
@@ -688,6 +698,7 @@
};
ssi3: ssi@63fe8000 {
+ #sound-dai-cells = <0>;
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x63fe8000 0x4000>;
@@ -744,5 +755,10 @@
reg = <0xf8000000 0x20000>;
clocks = <&clks IMX5_CLK_OCRAM>;
};
+
+ pmu {
+ compatible = "arm,cortex-a8-pmu";
+ interrupts = <77>;
+ };
};
};
diff --git a/dts/src/arm/imx6dl-gw552x.dts b/dts/src/arm/imx6dl-gw552x.dts
new file mode 100644
index 0000000..a4b700c
--- /dev/null
+++ b/dts/src/arm/imx6dl-gw552x.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw552x.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X";
+ compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/dts/src/arm/imx6dl-hummingboard.dts b/dts/src/arm/imx6dl-hummingboard.dts
index 7159854..44a0e67 100644
--- a/dts/src/arm/imx6dl-hummingboard.dts
+++ b/dts/src/arm/imx6dl-hummingboard.dts
@@ -1,206 +1,13 @@
/*
- * Copyright (C) 2013,2014 Russell King
+ * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
+ * Based on dt work by Russell King
*/
/dts-v1/;
#include "imx6dl.dtsi"
-#include "imx6qdl-microsom.dtsi"
-#include "imx6qdl-microsom-ar8035.dtsi"
+#include "imx6qdl-hummingboard.dtsi"
/ {
- model = "SolidRun HummingBoard DL/Solo";
- compatible = "solidrun,hummingboard", "fsl,imx6dl";
-
- chosen {
- stdout-path = &uart1;
- };
-
- ir_recv: ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio1 2 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
- };
-
- regulators {
- compatible = "simple-bus";
-
- reg_3p3v: 3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- reg_usbh1_vbus: usb-h1-vbus {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 0 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
- regulator-name = "usb_h1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usbotg_vbus: usb-otg-vbus {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 22 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
- regulator-name = "usb_otg_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
- };
-
- sound-spdif {
- compatible = "fsl,imx-audio-spdif";
- model = "On-board SPDIF";
- /* IMX6 doesn't implement this yet */
- spdif-controller = <&spdif>;
- spdif-out;
- };
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
- status = "okay";
-};
-
-&hdmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
- ddc-i2c-bus = <&i2c2>;
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
-
- /*
- * Not fitted on Carrier-1 board... yet
- status = "okay";
-
- rtc: pcf8523@68 {
- compatible = "nxp,pcf8523";
- reg = <0x68>;
- };
- */
-};
-
-&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
- status = "okay";
-};
-
-&iomuxc {
- hummingboard {
- pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
- fsl,pins = <
- MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
- MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
- >;
- };
-
- pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
- >;
- };
-
- pinctrl_hummingboard_hdmi: hummingboard-hdmi {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
- >;
- };
-
- pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_hummingboard_spdif: hummingboard-spdif {
- fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
- };
-
- pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
- fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
- };
-
- pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
- /*
- * Similar to pinctrl_usbotg_2, but we want it
- * pulled down for a fixed host connection.
- */
- fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
- };
-
- pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
- fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
- };
-
- pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
- fsl,pins = <
-