diff options
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/at91/atmel-sfr.h | 7 | ||||
| -rw-r--r-- | include/soc/bcm283x/wdt.h | 41 | ||||
| -rw-r--r-- | include/soc/fsl/caam.h | 17 | ||||
| -rw-r--r-- | include/soc/fsl/fsl_ddr_sdram.h | 157 | ||||
| -rw-r--r-- | include/soc/fsl/fsl_udc.h | 8 | ||||
| -rw-r--r-- | include/soc/fsl/immap_lsch2.h | 171 | ||||
| -rw-r--r-- | include/soc/fsl/immap_lsch3.h | 306 | ||||
| -rw-r--r-- | include/soc/fsl/scfg.h | 19 | ||||
| -rw-r--r-- | include/soc/imx/clk-fracn-gppll.h | 144 | ||||
| -rw-r--r-- | include/soc/imx/ddr.h | 171 | ||||
| -rw-r--r-- | include/soc/imx/gpmi-nand.h | 147 | ||||
| -rw-r--r-- | include/soc/imx/imx-nand-bcb.h | 13 | ||||
| -rw-r--r-- | include/soc/imx8m/clk-early.h | 2 | ||||
| -rw-r--r-- | include/soc/imx8m/ddr.h | 139 | ||||
| -rw-r--r-- | include/soc/imx8m/featctrl.h | 39 | ||||
| -rw-r--r-- | include/soc/imx9/ddr.h | 18 | ||||
| -rw-r--r-- | include/soc/imx9/flash_header.h | 88 | ||||
| -rw-r--r-- | include/soc/stm32/gpio.h | 4 | ||||
| -rw-r--r-- | include/soc/stm32/reboot.h | 18 | ||||
| -rw-r--r-- | include/soc/ti/k3-sec-proxy.h | 25 | ||||
| -rw-r--r-- | include/soc/ti/ti_sci_protocol.h | 657 |
21 files changed, 1977 insertions, 214 deletions
diff --git a/include/soc/at91/atmel-sfr.h b/include/soc/at91/atmel-sfr.h index 482337af06..1a909a3e06 100644 --- a/include/soc/at91/atmel-sfr.h +++ b/include/soc/at91/atmel-sfr.h @@ -1,19 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Atmel SFR (Special Function Registers) register offsets and bit definitions. * * Copyright (C) 2016 Atmel * * Author: Ludovic Desroches <ludovic.desroches@atmel.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _LINUX_MFD_SYSCON_ATMEL_SFR_H #define _LINUX_MFD_SYSCON_ATMEL_SFR_H #define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */ +#define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */ /* 0x08 ~ 0x0c: Reserved */ #define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */ #define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */ @@ -21,6 +19,7 @@ #define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ /* Field definitions */ +#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24) #define AT91_OHCIICR_SUSPEND_A BIT(8) #define AT91_OHCIICR_SUSPEND_B BIT(9) #define AT91_OHCIICR_SUSPEND_C BIT(10) diff --git a/include/soc/bcm283x/wdt.h b/include/soc/bcm283x/wdt.h new file mode 100644 index 0000000000..2002647b9c --- /dev/null +++ b/include/soc/bcm283x/wdt.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Pengutronix, Lucas Stach <l.stach@pengutronix.de> + * + * Based on code from Carlo Caione <carlo@carlocaione.org> + */ + +#ifndef __BCM2835_WDT_H +#define __BCM2835_WDT_H + +#define PM_RSTC 0x1c +#define PM_RSTS 0x20 +#define PM_WDOG 0x24 + +#define PM_WDOG_RESET 0000000000 +#define PM_PASSWORD 0x5a000000 +#define PM_WDOG_TIME_SET 0x000fffff +#define PM_RSTC_WRCFG_CLR 0xffffffcf +#define PM_RSTC_WRCFG_SET 0x00000030 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 +#define PM_RSTC_RESET 0x00000102 + +#define PM_RSTS_HADPOR_SET 0x00001000 +#define PM_RSTS_HADSRH_SET 0x00000400 +#define PM_RSTS_HADSRF_SET 0x00000200 +#define PM_RSTS_HADSRQ_SET 0x00000100 +#define PM_RSTS_HADWRH_SET 0x00000040 +#define PM_RSTS_HADWRF_SET 0x00000020 +#define PM_RSTS_HADWRQ_SET 0x00000010 +#define PM_RSTS_HADDRH_SET 0x00000004 +#define PM_RSTS_HADDRF_SET 0x00000002 +#define PM_RSTS_HADDRQ_SET 0x00000001 + +#define PM_RSTS_HADDR_SET \ + (PM_RSTS_HADDRQ_SET | PM_RSTS_HADDRF_SET | PM_RSTS_HADDRH_SET) +#define PM_RSTS_HADWR_SET \ + (PM_RSTS_HADWRQ_SET | PM_RSTS_HADWRF_SET | PM_RSTS_HADWRH_SET) +#define PM_RSTS_HADSR_SET \ + (PM_RSTS_HADSRQ_SET | PM_RSTS_HADSRF_SET | PM_RSTS_HADSRH_SET) + +#endif diff --git a/include/soc/fsl/caam.h b/include/soc/fsl/caam.h new file mode 100644 index 0000000000..a919a114e8 --- /dev/null +++ b/include/soc/fsl/caam.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +#ifndef __SOC_FSL_CAAM_H_ +#define __SOC_FSL_CAAM_H_ + +#include <linux/compiler.h> +#include <linux/types.h> + +struct caam_ctrl; + +int early_caam_init(struct caam_ctrl __iomem *caam, bool is_imx); + +static inline int imx_early_caam_init(struct caam_ctrl __iomem *caam) +{ + return early_caam_init(caam, true); +} + +#endif diff --git a/include/soc/fsl/fsl_ddr_sdram.h b/include/soc/fsl/fsl_ddr_sdram.h index 80508ef5d5..c20bc027fe 100644 --- a/include/soc/fsl/fsl_ddr_sdram.h +++ b/include/soc/fsl/fsl_ddr_sdram.h @@ -8,6 +8,7 @@ #define FSL_DDR_MEMCTL_H #include <ddr_spd.h> +#include <ddr_dimms.h> #include <soc/fsl/fsl_immap.h> struct common_timing_params { @@ -418,97 +419,6 @@ typedef struct memctl_options_s { #define EDC_ECC 2 #define EDC_AC_PARITY 4 -/* Parameters for a DDR dimm computed from the SPD */ -struct dimm_params { - - /* DIMM organization parameters */ - char mpart[19]; /* guaranteed null terminated */ - - unsigned int n_ranks; - unsigned int die_density; - unsigned long long rank_density; - unsigned long long capacity; - unsigned int data_width; - unsigned int primary_sdram_width; - unsigned int ec_sdram_width; - unsigned int registered_dimm; - unsigned int package_3ds; /* number of dies in 3DS DIMM */ - unsigned int device_width; /* x4, x8, x16 components */ - - /* SDRAM device parameters */ - unsigned int n_row_addr; - unsigned int n_col_addr; - unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ - unsigned int bank_addr_bits; /* DDR4 */ - unsigned int bank_group_bits; /* DDR4 */ - unsigned int n_banks_per_sdram_device; /* !DDR4 */ - unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ - - /* used in computing base address of DIMMs */ - unsigned long long base_address; - /* mirrored DIMMs */ - unsigned int mirrored_dimm; /* only for ddr3 */ - - /* DIMM timing parameters */ - - int mtb_ps; /* medium timebase ps */ - int ftb_10th_ps; /* fine timebase, in 1/10 ps */ - int taa_ps; /* minimum CAS latency time */ - int tfaw_ps; /* four active window delay */ - - /* - * SDRAM clock periods - * The range for these are 1000-10000 so a short should be sufficient - */ - int tckmin_x_ps; - int tckmin_x_minus_1_ps; - int tckmin_x_minus_2_ps; - int tckmax_ps; - - /* SPD-defined CAS latencies */ - unsigned int caslat_x; - unsigned int caslat_x_minus_1; - unsigned int caslat_x_minus_2; - - unsigned int caslat_lowest_derated; /* Derated CAS latency */ - - /* basic timing parameters */ - int trcd_ps; - int trp_ps; - int tras_ps; - - int trfc1_ps; /* DDR4 */ - int trfc2_ps; /* DDR4 */ - int trfc4_ps; /* DDR4 */ - int trrds_ps; /* DDR4 */ - int trrdl_ps; /* DDR4 */ - int tccdl_ps; /* DDR4 */ - int trfc_slr_ps; /* DDR4 */ - int twr_ps; /* !DDR4, maximum = 63750 ps */ - int trfc_ps; /* max = 255 ns + 256 ns + .75 ns - = 511750 ps */ - int trrd_ps; /* !DDR4, maximum = 63750 ps */ - int twtr_ps; /* !DDR4, maximum = 63750 ps */ - int trtp_ps; /* !DDR4, byte 38, spd->trtp */ - - int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - int refresh_rate_ps; - int extended_op_srt; - - int tis_ps; /* DDR1, DDR2, byte 32, spd->ca_setup */ - int tih_ps; /* DDR1, DDR2, byte 33, spd->ca_hold */ - int tds_ps; /* DDR1, DDR2, byte 34, spd->data_setup */ - int tdh_ps; /* DDR1, DDR2, byte 35, spd->data_hold */ - int tdqsq_max_ps; /* DDR1, DDR2, byte 44, spd->tdqsq */ - int tqhs_ps; /* DDR1, DDR2, byte 45, spd->tqhs */ - - /* DDR3 & DDR4 RDIMM */ - unsigned char rcw[16]; /* Register Control Word 0-15 */ - unsigned int dq_mapping[18]; /* DDR4 */ - unsigned int dq_mapping_ors; /* DDR4 */ -}; - struct fsl_ddr_controller { int num; unsigned long ddr_freq; @@ -539,21 +449,54 @@ struct fsl_ddr_info { unsigned long long mem_base; }; -phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo); -void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step); - -#ifdef CONFIG_SYS_FSL_DDR_LE -#define ddr_in32(a) in_le32(a) -#define ddr_out32(a, v) out_le32(a, v) -#define ddr_setbits32(a, v) setbits_le32(a, v) -#define ddr_clrbits32(a, v) clrbits_le32(a, v) -#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) -#else -#define ddr_in32(a) in_be32(a) -#define ddr_out32(a, v) out_be32(a, v) -#define ddr_setbits32(a, v) setbits_be32(a, v) -#define ddr_clrbits32(a, v) clrbits_be32(a, v) -#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) -#endif +phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo, bool little_endian); +void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step, bool little_endian); + +enum ddr_endianess { + DDR_ENDIANESS_LE, + DDR_ENDIANESS_BE, +}; + +extern enum ddr_endianess ddr_endianess; + +static inline u32 ddr_in32(void __iomem *reg) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + return in_le32(reg); + else + return in_be32(reg); +} + +static inline void ddr_out32(void __iomem *reg, u32 val) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + out_le32(reg, val); + else + out_be32(reg, val); +} + +static inline void ddr_setbits32(void __iomem *reg, u32 set) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + setbits_le32(reg, set); + else + setbits_be32(reg, set); +} + +static inline void ddr_clrbits32(void __iomem *reg, u32 clr) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + clrbits_le32(reg, clr); + else + clrbits_be32(reg, clr); +} + +static inline void ddr_clrsetbits32(void __iomem *reg, u32 clr, u32 set) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + clrsetbits_le32(reg, clr, set); + else + clrsetbits_be32(reg, clr, set); +} #endif diff --git a/include/soc/fsl/fsl_udc.h b/include/soc/fsl/fsl_udc.h index 0b409a9f6b..c1abe222ba 100644 --- a/include/soc/fsl/fsl_udc.h +++ b/include/soc/fsl/fsl_udc.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __FSL_UDC_H #define __FSL_UDC_H @@ -380,6 +382,12 @@ struct ep_td_struct { int imx_barebox_load_usb(void __iomem *dr, void *dest); int imx_barebox_start_usb(void __iomem *dr, void *dest); +int imx6_barebox_load_usb(void *dest); +int imx6_barebox_start_usb(void *dest); + +int imx7_barebox_load_usb(void *dest); +int imx7_barebox_start_usb(void *dest); + int imx8mm_barebox_load_usb(void *dest); int imx8mm_barebox_start_usb(void *dest); diff --git a/include/soc/fsl/immap_lsch2.h b/include/soc/fsl/immap_lsch2.h index 1b74c77908..6a7dad3d5d 100644 --- a/include/soc/fsl/immap_lsch2.h +++ b/include/soc/fsl/immap_lsch2.h @@ -6,6 +6,9 @@ #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ #define __ARCH_FSL_LSCH2_IMMAP_H__ +#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) +#define SOC_MAJOR_VER_1_0 0x1 + #define gur_in32(a) in_be32(a) #define gur_out32(a, v) out_be32(a, v) @@ -214,7 +217,67 @@ struct ccsr_gur { u32 dcfg_ccsr_reserved1; }; -#define SCFG_QSPI_CLKSEL 0x40100000 +/* LS102XA Device Configuration and Pin Control */ +struct ls102xa_ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_02c[0x70-0x2c]; + u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u8 res_084[0x94-0x84]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_09c[0xa4-0x9c]; + u32 svr; /* System version */ + u8 res_0a8[0xb0-0xa8]; + u32 rstcr; /* Reset control */ + u32 rstrqpblsr; /* Reset request preboot loader status */ + u8 res_0b8[0xc0-0xb8]; + u32 rstrqmr1; /* Reset request mask */ + u8 res_0c4[0xc8-0xc4]; + u32 rstrqsr1; /* Reset request status */ + u8 res_0cc[0xd4-0xcc]; + u32 rstrqwdtmrl; /* Reset request WDT mask */ + u8 res_0d8[0xdc-0xd8]; + u32 rstrqwdtsrl; /* Reset request WDT status */ + u8 res_0e0[0xe4-0xe0]; + u32 brrl; /* Boot release */ + u8 res_0e8[0x100-0xe8]; + u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 + u8 res_140[0x200-0x140]; + u32 scratchrw[4]; /* Scratch Read/Write */ + u8 res_210[0x300-0x210]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 crstsr; + u8 res_404[0x550-0x404]; + u32 sataliodnr; + u8 res_554[0x604-0x554]; + u32 pamubypenr; + u32 dmacr1; + u8 res_60c[0x740-0x60c]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[1]; /* Core Cluster n Topology Register */ + u8 res_848[0xe60-0x848]; + u32 ddrclkdr; + u8 res_e60[0xe68-0xe64]; + u32 ifcclkdr; + u8 res_e68[0xe80-0xe6c]; + u32 sdhcpcr; +}; + #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 @@ -238,15 +301,26 @@ struct ccsr_gur { #define SCFG_USB_PHY2 0x08500000 #define SCFG_USB_PHY3 0x08510000 #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c -#define USB_PHY_RX_EQ_VAL_1 0x0000 -#define USB_PHY_RX_EQ_VAL_2 0x0080 -#define USB_PHY_RX_EQ_VAL_3 0x0380 -#define USB_PHY_RX_EQ_VAL_4 0x0b80 + +#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 +#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 +#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 +#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 +#define SCFG_ENDIANCR_LE 0x80000000 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 +#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 +#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 +#define SCFG_SNPCNFGCR_EDMASNP 0x00020000 +#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 +#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 +#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 +#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 /* RGMIIPCR bit definitions*/ #define SCFG_RGMIIPCR_EN_AUTO BIT(3) @@ -353,4 +427,89 @@ struct ccsr_scfg { u32 pex3msir; }; -#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ +/* LS102XA Supplemental Configuration Unit */ +struct ls102xa_ccsr_scfg { + u32 dpslpcr; + u32 resv0[2]; + u32 etsecclkdpslpcr; + u32 resv1[5]; + u32 fuseovrdcr; + u32 pixclkcr; + u32 resv2[5]; + u32 spimsicr; + u32 resv3[6]; + u32 pex1pmwrcr; + u32 pex1pmrdsr; + u32 resv4[3]; + u32 usb3prm1cr; + u32 usb4prm2cr; + u32 pex1rdmsgpldlsbsr; + u32 pex1rdmsgpldmsbsr; + u32 pex2rdmsgpldlsbsr; + u32 pex2rdmsgpldmsbsr; + u32 pex1rdmmsgrqsr; + u32 pex2rdmmsgrqsr; + u32 spimsiclrcr; + u32 pexmscportsr[2]; + u32 pex2pmwrcr; + u32 resv5[24]; + u32 mac1_streamid; + u32 mac2_streamid; + u32 mac3_streamid; + u32 pex1_streamid; + u32 pex2_streamid; + u32 dma_streamid; + u32 sata_streamid; + u32 usb3_streamid; + u32 qe_streamid; + u32 sdhc_streamid; + u32 adma_streamid; + u32 letechsftrstcr; + u32 core0_sft_rst; + u32 core1_sft_rst; + u32 resv6[1]; + u32 usb_hi_addr; + u32 etsecclkadjcr; + u32 sai_clk; + u32 resv7[1]; + u32 dcu_streamid; + u32 usb2_streamid; + u32 ftm_reset; + u32 altcbar; + u32 qspi_cfg; + u32 pmcintecr; + u32 pmcintlecr; + u32 pmcintsr; + u32 qos1; + u32 qos2; + u32 qos3; + u32 cci_cfg; + u32 endiancr; + u32 etsecdmamcr; + u32 usb3prm3cr; + u32 resv9[1]; + u32 debug_streamid; + u32 resv10[5]; + u32 snpcnfgcr; + u32 hrstcr; + u32 intpcr; + u32 resv12[20]; + u32 scfgrevcr; + u32 coresrencr; + u32 pex2pmrdsr; + u32 eddrtqcfg; + u32 ddrc2cr; + u32 ddrc3cr; + u32 ddrc4cr; + u32 ddrgcr; + u32 resv13[120]; + u32 qeioclkcr; + u32 etsecmcr; + u32 sdhciovserlcr; + u32 resv14[61]; + u32 sparecr[8]; + u32 resv15[248]; + u32 core0sftrstsr; + u32 clusterpmcr; +}; +#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/include/soc/fsl/immap_lsch3.h b/include/soc/fsl/immap_lsch3.h new file mode 100644 index 0000000000..f25a6e46be --- /dev/null +++ b/include/soc/fsl/immap_lsch3.h @@ -0,0 +1,306 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * LayerScape Internal Memory Map + * + * Copyright 2017-2020 NXP + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __ARCH_FSL_LSCH3_IMMAP_H_ +#define __ARCH_FSL_LSCH3_IMMAP_H_ + +#define LSCH3_IMMR 0x01000000 + +// LSCH3_2: ls1028a, lx2162a, lx2160a +#define LSCH3_DDR_ADDR (LSCH3_IMMR + 0x00080000) +#define LSCH3_DDR2_ADDR (LSCH3_IMMR + 0x00090000) +#define LSCH3_DDR3_ADDR 0x08210000 +#define LSCH3_GUTS_ADDR (LSCH3_IMMR + 0x00E00000) +#define LSCH3_PMU_ADDR (LSCH3_IMMR + 0x00E30000) +#define LSCH3_RST_ADDR_LX21XXA (LSCH3_IMMR + 0x00e88180) +#define LSCH3_RST_ADDR (LSCH3_IMMR + 0x00E60000) +#define LSCH3_CH3_CLK_GRPA_ADDR (LSCH3_IMMR + 0x00300000) +#define LSCH3_CH3_CLK_GRPB_ADDR (LSCH3_IMMR + 0x00310000) +#define LSCH3_CH3_CLK_CTRL_ADDR (LSCH3_IMMR + 0x00370000) +#define LSCH3_QSPI_ADDR_LSCH3 (LSCH3_IMMR + 0x010c0000) +#define LSCH3_FSPI_ADDR (LSCH3_IMMR + 0x010c0000) +#define LSCH3_ESDHC1_BASE_ADDR (LSCH3_IMMR + 0x01140000) +#define LSCH3_ESDHC2_BASE_ADDR (LSCH3_IMMR + 0x01150000) +#define LSCH3_IFC_ADDR (LSCH3_IMMR + 0x01240000) +#define LSCH3_NS16550_COM1 (LSCH3_IMMR + 0x011C0500) +#define LSCH3_NS16550_COM2 (LSCH3_IMMR + 0x011C0600) +#define LSCH3_EDMA_ADDR (LSCH3_IMMR + 0x012c0000) +#define LSCH3_TIMER_ADDR (LSCH3_IMMR + 0x013e0000) +#define LSCH3_XHCI_USB1_ADDR (LSCH3_IMMR + 0x02100000) +#define LSCH3_XHCI_USB2_ADDR (LSCH3_IMMR + 0x02110000) +#define LSCH3_AHCI1_ADDR (LSCH3_IMMR + 0x02200000) +#define LSCH3_AHCI2_ADDR (LSCH3_IMMR + 0x02210000) +#define LSCH3_AHCI3_ADDR (LSCH3_IMMR + 0x02220000) +#define LSCH3_AHCI4_ADDR (LSCH3_IMMR + 0x02230000) +#define LSCH3_CCI400_ADDR (LSCH3_IMMR + 0x03090000) +#define LSCH3_SEC_ADDR (LSCH3_IMMR + 0x07000000) +#define LSCH3_SEC_JR0_ADDR (LSCH3_IMMR + 0x07010000) +#define LSCH3_SEC_JR1_ADDR (LSCH3_IMMR + 0x07020000) +#define LSCH3_SEC_JR2_ADDR (LSCH3_IMMR + 0x07030000) +#define LSCH3_SEC_JR3_ADDR (LSCH3_IMMR + 0x07040000) +#define LSCH3_QDMA_ADDR (LSCH3_IMMR + 0x07380000) +#define LSCH3_DISPLAY_ADDR (LSCH3_IMMR + 0x0e080000) +#define LSCH3_GPU_ADDR (LSCH3_IMMR + 0x0e0c0000) +#define LSCH3_PMU_CLTBENR (LSCH3_PMU_ADDR + 0x18A0) +#define LSCH3_PCTBENR_OFFSET (LSCH3_PMU_ADDR + 0x8A0) +#define LSCH3_SVR (LSCH3_GUTS_ADDR + 0xA4) + +#define LSCH3_WRIOP1_ADDR (LSCH3_IMMR + 0x7B80000) +#define LSCH3_WRIOP1_MDIO1 (LSCH3_WRIOP1_ADDR + 0x16000) +#define LSCH3_WRIOP1_MDIO2 (LSCH3_WRIOP1_ADDR + 0x17000) +#define LSCH3_SERDES_ADDR (LSCH3_IMMR + 0xEA0000) + +#define LSCH3_DCSR_DDR_ADDR 0x70012c000ULL +#define LSCH3_DCSR_DDR2_ADDR 0x70012d000ULL +#define LSCH3_DCSR_DDR3_ADDR 0x700132000ULL + +#define LSCH3_I2C1_BASE_ADDR (LSCH3_IMMR + 0x01000000) +#define LSCH3_I2C2_BASE_ADDR (LSCH3_IMMR + 0x01010000) +#define LSCH3_I2C3_BASE_ADDR (LSCH3_IMMR + 0x01020000) +#define LSCH3_I2C4_BASE_ADDR (LSCH3_IMMR + 0x01030000) +#define LSCH3_I2C5_BASE_ADDR (LSCH3_IMMR + 0x01040000) +#define LSCH3_I2C6_BASE_ADDR (LSCH3_IMMR + 0x01050000) +#define LSCH3_I2C7_BASE_ADDR (LSCH3_IMMR + 0x01060000) +#define LSCH3_I2C8_BASE_ADDR (LSCH3_IMMR + 0x01070000) + +/* EDMA */ +#define LSCH3_EDMA_BASE_ADDR (LSCH3_IMMR + 0x012c0000) + +/* MMU 500 */ +#define LSCH3_SMMU_SCR0 (SMMU_BASE + 0x0) +#define LSCH3_SMMU_SCR1 (SMMU_BASE + 0x4) +#define LSCH3_SMMU_SCR2 (SMMU_BASE + 0x8) +#define LSCH3_SMMU_SACR (SMMU_BASE + 0x10) +#define LSCH3_SMMU_IDR0 (SMMU_BASE + 0x20) +#define LSCH3_SMMU_IDR1 (SMMU_BASE + 0x24) + +#define LSCH3_SMMU_NSCR0 (SMMU_BASE + 0x400) +#define LSCH3_SMMU_NSCR2 (SMMU_BASE + 0x408) +#define LSCH3_SMMU_NSACR (SMMU_BASE + 0x410) + +/* Device Configuration */ +#define LSCH3_DCFG_BASE 0x01e00000 +#define LSCH3_DCFG_PORSR1 0x000 +#define LSCH3_DCFG_PORSR1_RCW_SRC 0xff800000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_SDHC1 0x04000000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_SDHC2 0x04800000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_I2C 0x05000000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_FSPI_NOR 0x07800000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 +#define LSCH3_DCFG_RCWSR12 0x12c +#define LSCH3_DCFG_RCWSR12_SDHC_SHIFT 24 +#define LSCH3_DCFG_RCWSR12_SDHC_MASK 0x7 +#define LSCH3_DCFG_RCWSR13 0x130 +#define LSCH3_DCFG_RCWSR13_SDHC_SHIFT 3 +#define LSCH3_DCFG_RCWSR13_SDHC_MASK 0x7 +#define LSCH3_DCFG_RCWSR13_DSPI (0 << 8) +#define LSCH3_DCFG_RCWSR15 0x138 +#define LSCH3_DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 + +#define LSCH3_DCFG_DCSR_BASE 0X700100000ULL +#define LSCH3_DCFG_DCSR_PORCR1 0x000 + +/* Supplemental Configuration */ +#define LSCH3_SCFG_BASE 0x01fc0000 +#define LSCH3_SCFG_USB3PRM1CR 0x000 +#define LSCH3_SCFG_USB3PRM1CR_INIT 0x27672b2a +#define LSCH3_SCFG_USB_TXVREFTUNE 0x9 +#define LSCH3_SCFG_USB_SQRXTUNE_MASK 0x7 +#define LSCH3_SCFG_QSPICLKCTLR 0x10 + +#define LSCH3_DCSR_BASE 0x700000000ULL +#define LSCH3_DCSR_USB_PHY1 0x4600000 +#define LSCH3_DCSR_USB_PHY2 0x4610000 +#define LSCH3_DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C +#define LSCH3_DCSR_USB_IOCR1 0x108004 +#define LSCH3_DCSR_USB_PCSTXSWINGFULL 0x71 + +#ifndef __ASSEMBLY__ + +/* Global Utilities Block */ +struct lsch3_ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; /* General-purpose POR configuration 2 */ + u32 gpporcr3; + u32 gpporcr4; + u8 res_030[0x60-0x30]; + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_064[0x70-0x64]; + u32 devdisr; /* Device disable control 1 */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u8 res_088[0x94-0x88]; + u32 coredisr; /* Device disable control 7 */ + u8 res_098[0xa0-0x98]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u8 res_0a8[0x100-0xa8]; + u32 rcwsr[30]; /* Reset control word status */ + u8 res_178[0x200-0x178]; + u32 scratchrw[16]; /* Scratch Read/Write */ + u8 res_240[0x300-0x240]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 bootlocptrl; /* Boot location pointer low-order addr */ + u32 bootlocptrh; /* Boot location pointer high-order addr */ + u8 res_408[0x520-0x408]; + u32 usb1_amqr; + u32 usb2_amqr; + u8 res_528[0x530-0x528]; /* add more registers when needed */ + u32 sdmm1_amqr; + u32 sdmm2_amqr; + u8 res_538[0x550 - 0x538]; /* add more registers when needed */ + u32 sata1_amqr; + u32 sata2_amqr; + u32 sata3_amqr; + u32 sata4_amqr; + u8 res_560[0x570 - 0x560]; /* add more registers when needed */ + u32 misc1_amqr; + u8 res_574[0x590-0x574]; /* add more registers when needed */ + u32 spare1_amqr; + u32 spare2_amqr; + u32 spare3_amqr; + u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */ + u32 gencr[7]; /* General Control Registers */ + u8 res_63c[0x640-0x63c]; /* add more registers when needed */ + u32 cgensr1; /* Core General Status Register */ + u8 res_644[0x660-0x644]; /* add more registers when needed */ + u32 cgencr1; /* Core General Control Register */ + u8 res_664[0x740-0x664]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[4]; /* Core cluster n Topology Register */ + u8 res_864[0x920-0x864]; /* add more registers when needed */ + u32 ioqoscr[8]; /*I/O Quality of Services Register */ + u32 uccr; + u8 res_944[0x960-0x944]; /* add more registers when needed */ + u32 ftmcr; + u8 res_964[0x990-0x964]; /* add more registers when needed */ + u32 coredisablesr; + u8 res_994[0xa00-0x994]; /* add more registers when needed */ + u32 sdbgcr; /*Secure Debug Confifuration Register */ + u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */ + u32 ipbrr1; + u32 ipbrr2; + u8 res_858[0x1000-0xc00]; +}; + +struct rng4tst { + u32 rtmctl; /* misc. control register */ + u32 rtscmisc; /* statistical check misc. register */ + u32 rtpkrrng; /* poker range register */ + union { + u32 rtpkrmax; /* PRGM=1: poker max. limit register */ + u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ + }; + u32 rtsdctl; /* seed control register */ + union { + u32 rtsblim; /* PRGM=1: sparse bit limit register */ + u32 rttotsam; /* PRGM=0: total samples register */ + }; + u32 rtfreqmin; /* frequency count min. limit register */ + union { + u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ + u32 rtfreqcnt; /* PRGM=0: freq. count register */ + }; + u32 rsvd1[40]; + u32 rdsta; /*RNG DRNG Status Register*/ + u32 rsvd2[15]; +}; + +struct version_regs { + u32 crca; /* CRCA_VERSION */ + u32 afha; /* AFHA_VERSION */ + u32 kfha; /* KFHA_VERSION */ + u32 pkha; /* PKHA_VERSION */ + u32 aesa; /* AESA_VERSION */ + u32 mdha; /* MDHA_VERSION */ + u32 desa; /* DESA_VERSION */ + u32 snw8a; /* SNW8A_VERSION */ + u32 snw9a; /* SNW9A_VERSION */ + u32 zuce; /* ZUCE_VERSION */ + u32 zuca; /* ZUCA_VERSION */ + u32 ccha; /* CCHA_VERSION */ + u32 ptha; /* PTHA_VERSION */ + u32 rng; /* RNG_VERSION */ + u32 trng; /* TRNG_VERSION */ + u32 aaha; /* AAHA_VERSION */ + u32 rsvd[10]; + u32 sr; /* SR_VERSION */ + u32 dma; /* DMA_VERSION */ + u32 ai; /* AI_VERSION */ + u32 qi; /* QI_VERSION */ + u32 jr; /* JR_VERSION */ + u32 deco; /* DECO_VERSION */ +}; + +struct ccsr_sec { + u32 res0; + u32 mcfgr; /* Master CFG Register */ + u8 res1[0x4]; + u32 scfgr; + struct { + u32 ms; /* Job Ring LIODN Register, MS */ + u32 ls; /* Job Ring LIODN Register, LS */ + } jrliodnr[4]; + u8 res2[0x2c]; + u32 jrstartr; /* Job Ring Start Register */ + struct { + u32 ms; /* RTIC LIODN Register, MS */ + u32 ls; /* RTIC LIODN Register, LS */ + } rticliodnr[4]; + u8 res3[0x1c]; + u32 decorr; /* DECO Request Register */ + struct { + u32 ms; /* DECO LIODN Register, MS */ + u32 ls; /* DECO LIODN Register, LS */ + } decoliodnr[16]; + u32 dar; /* DECO Avail Register */ + u32 drr; /* DECO Reset Register */ + u8 res5[0x4d8]; + struct rng4tst rng; /* RNG Registers */ + u8 res6[0x780]; + struct version_regs vreg; /* version registers since era 10 */ + u8 res7[0xa0]; + u32 crnr_ms; /* CHA Revision Number Register, MS */ + u32 crnr_ls; /* CHA Revision Number Register, LS */ + u32 ctpr_ms; /* Compile Time Parameters Register, MS */ + u32 ctpr_ls; /* Compile Time Parameters Register, LS */ + u8 res8[0x10]; + u32 far_ms; /* Fault Address Register, MS */ + u32 far_ls; /* Fault Address Register, LS */ + u32 falr; /* Fault Address LIODN Register */ + u32 fadr; /* Fault Address Detail Register */ + u8 res9[0x4]; + u32 csta; /* CAAM Status Register */ + u32 smpart; /* Secure Memory Partition Parameters */ + u32 smvid; /* Secure Memory Version ID */ + u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ + u32 ccbvid; /* CHA Cluster Block Version ID Register */ + u32 chavid_ms; /* CHA Version ID Register, MS */ + u32 chavid_ls; /* CHA Version ID Register, LS */ + u32 chanum_ms; /* CHA Number Register, MS */ + u32 chanum_ls; /* CHA Number Register, LS */ + u32 secvid_ms; /* SEC Version ID Register, MS */ + u32 secvid_ls; /* SEC Version ID Register, LS */ + u8 res10[0x6f020]; + u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ + u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ + u8 res11[0x8ffd8]; +}; + +#endif /*__ASSEMBLY__ */ +#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/include/soc/fsl/scfg.h b/include/soc/fsl/scfg.h new file mode 100644 index 0000000000..bea184218e --- /dev/null +++ b/include/soc/fsl/scfg.h @@ -0,0 +1,19 @@ +#ifndef __SOC_FSL_SCFG_H +#define __SOC_FSL_SCFG_H + +#include <soc/fsl/scfg.h> +#include <linux/compiler.h> + +enum scfg_endianess { + SCFG_ENDIANESS_INVALID, + SCFG_ENDIANESS_LITTLE, + SCFG_ENDIANESS_BIG, +}; + +void scfg_clrsetbits32(void __iomem *addr, u32 clear, u32 set); +void scfg_clrbits32(void __iomem *addr, u32 clear); +void scfg_setbits32(void __iomem *addr, u32 set); +void scfg_out16(void __iomem *addr, u16 val); +void scfg_init(enum scfg_endianess endianess); + +#endif /* __SOC_FSL_SCFG_H */ diff --git a/include/soc/imx/clk-fracn-gppll.h b/include/soc/imx/clk-fracn-gppll.h new file mode 100644 index 0000000000..15ab9e67ec --- /dev/null +++ b/include/soc/imx/clk-fracn-gppll.h @@ -0,0 +1,144 @@ +#ifndef __SOC_IMX_CLK_FRACN_GPGPPLL_H +#define __SOC_IMX_CLK_FRACN_GPGPPLL_H + +#include <linux/bitfield.h> +#include <linux/iopoll.h> + +#define GPPLL_CTRL 0x0 +#define HW_CTRL_SEL BIT(16) +#define CLKMUX_BYPASS BIT(2) +#define CLKMUX_EN BIT(1) +#define POWERUP_MASK BIT(0) + +#define GPPLL_ANA_PRG 0x10 +#define GPPLL_SPREAD_SPECTRUM 0x30 + +#define GPPLL_NUMERATOR 0x40 +#define GPPLL_MFN_MASK GENMASK(31, 2) + +#define GPPLL_DENOMINATOR 0x50 +#define GPPLL_MFD_MASK GENMASK(29, 0) + +#define GPPLL_DIV 0x60 +#define GPPLL_MFI_MASK GENMASK(24, 16) +#define GPPLL_RDIV_MASK GENMASK(15, 13) +#define GPPLL_ODIV_MASK GENMASK(7, 0) + +#define GPPLL_DFS_CTRL(x) (0x70 + (x) * 0x10) + +#define GPPLL_STATUS 0xF0 +#define GPPLL_LOCK_STATUS BIT(0) + +#define GPPLL_DFS_STATUS 0xF4 + +#define GPPLL_LOCK_TIMEOUT_US 200 + +#define CLK_FRACN_GPPLL_INTEGER BIT(0) +#define CLK_FRACN_GPPLL_FRACN BIT(1) + +/* NOTE: Rate table should be kept sorted in descending order. */ +struct imx_fracn_gppll_rate_table { + unsigned int rate; + unsigned int mfi; + unsigned int mfn; + unsigned int mfd; + unsigned int rdiv; + unsigned int odiv; +}; + +struct imx_fracn_gppll_clk { + const struct imx_fracn_gppll_rate_table *rate_table; + int rate_count; + int flags; +}; + +struct clk *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk); +struct clk *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, + void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk); + +extern struct imx_fracn_gppll_clk imx_fracn_gppll; +extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer; + +static inline int fracn_gppll_wait_lock(void __iomem *base) +{ + u32 val; + + return readl_poll_timeout(base + GPPLL_STATUS, val, + val & GPPLL_LOCK_STATUS, GPPLL_LOCK_TIMEOUT_US); +} + +static inline const struct imx_fracn_gppll_rate_table *imx_get_gppll_settings( + const struct imx_fracn_gppll_rate_table *rate_table, int n_table, unsigned long rate) +{ + int i; + + for (i = 0; i < n_table; i++) + if (rate == rate_table[i].rate) + return &rate_table[i]; + + return NULL; +} + +static inline int fracn_gppll_set_rate(void __iomem *base, unsigned int flags, + const struct imx_fracn_gppll_rate_table *table, int n_table, + unsigned long drate) +{ + const struct imx_fracn_gppll_rate_table *rate; + u32 tmp, pll_div, ana_mfn; + int ret; + + rate = imx_get_gppll_settings(table, n_table, drate); + + /* Hardware control select disable. PLL is control by register */ + tmp = readl_relaxed(base + GPPLL_CTRL); + tmp &= ~HW_CTRL_SEL; + writel_relaxed(tmp, base + GPPLL_CTRL); + + /* Disable output */ + tmp = readl_relaxed(base + GPPLL_CTRL); + tmp &= ~CLKMUX_EN; + writel_relaxed(tmp, base + GPPLL_CTRL); + + /* Power Down */ + tmp &= ~POWERUP_MASK; + writel_relaxed(tmp, base + GPPLL_CTRL); + + /* Disable BYPASS */ + tmp &= ~CLKMUX_BYPASS; + writel_relaxed(tmp, base + GPPLL_CTRL); + + pll_div = FIELD_PREP(GPPLL_RDIV_MASK, rate->rdiv) | rate->odiv | + FIELD_PREP(GPPLL_MFI_MASK, rate->mfi); + writel_relaxed(pll_div, base + GPPLL_DIV); + if (flags & CLK_FRACN_GPPLL_FRACN) { + writel_relaxed(rate->mfd, base + GPPLL_DENOMINATOR); + writel_relaxed(FIELD_PREP(GPPLL_MFN_MASK, rate->mfn), base + GPPLL_NUMERATOR); + } + + /* Wait for 5us according to fracn mode pll doc */ + udelay(5); + + /* Enable Powerup */ + tmp |= POWERUP_MASK; + writel_relaxed(tmp, base + GPPLL_CTRL); + + /* Wait Lock */ + ret = fracn_gppll_wait_lock(base); + if (ret) + return ret; + + /* Enable output */ + tmp |= CLKMUX_EN; + writel_relaxed(tmp, base + GPPLL_CTRL); + + ana_mfn = readl_relaxed(base + GPPLL_STATUS); + ana_mfn = FIELD_GET(GPPLL_MFN_MASK, ana_mfn); + + WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n"); + + return 0; +} + +#endif /* __SOC_IMX_CLK_FRACN_GPGPPLL_H */ diff --git a/include/soc/imx/ddr.h b/include/soc/imx/ddr.h new file mode 100644 index 0000000000..0225ac0e03 --- /dev/null +++ b/include/soc/imx/ddr.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __SOC_IMX_DDR_H +#define __SOC_IMX_DDR_H + +/* user data type */ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +enum dram_type { +#define DRAM_TYPE_MASK 0x00ff + DRAM_TYPE_LPDDR4 = 0 << 0, + DRAM_TYPE_DDR4 = 1 << 0, +}; + +static inline enum dram_type get_dram_type(unsigned type) +{ + return type & DRAM_TYPE_MASK; +} + +enum ddrc_type { +#define DDRC_TYPE_MASK 0xff00 + DDRC_TYPE_MM = 0 << 8, + DDRC_TYPE_MN = 1 << 8, + DDRC_TYPE_MQ = 2 << 8, + DDRC_TYPE_MP = 3 << 8, +}; + +static inline enum ddrc_type get_ddrc_type(unsigned type) +{ + return type & DDRC_TYPE_MASK; +} + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_fsp_cfg { + struct dram_cfg_param ddrc_cfg[20]; + struct dram_cfg_param mr_cfg[10]; + unsigned int bypass; +}; + +struct dram_fsp_msg { + unsigned int drate; + enum fw_type fw_type; + struct dram_cfg_param *fsp_cfg; + unsigned int fsp_cfg_num; +}; + +#define __deprecated_dram_timing_info \ + __attribute__((deprecated("board-specific data here is ignored in favor of the defaults." \ + " You can probably remove the array"))) + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* fsp config */ + struct dram_fsp_cfg *fsp_cfg; + unsigned int fsp_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr __deprecated_dram_timing_info; + unsigned int ddrphy_trained_csr_num __deprecated_dram_timing_info; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; +}; + +struct dram_controller { + enum ddrc_type ddrc_type; + enum dram_type dram_type; + void __iomem *phy_base; + u32 (*phy_remap)(u32 paddr_apb_from_ctlr); + void (*get_trained_CDD)(struct dram_controller *dram, u32 fsp); + void (*set_dfi_clk)(struct dram_controller *dram, unsigned int drate_mhz); + bool imx8m_ddr_old_spreadsheet; +}; + +void ddr_get_firmware_lpddr4(void); +void ddr_get_firmware_ddr(void); + +static inline void ddr_get_firmware(enum dram_type dram_type) +{ + if (dram_type == DRAM_TYPE_LPDDR4) + ddr_get_firmware_lpddr4(); + else + ddr_get_firmware_ddr(); +} + +int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *timing_info); +void ddrphy_trained_csr_save(struct dram_controller *dram, struct dram_cfg_param *param, + unsigned int num); +void *dram_config_save(struct dram_controller *dram, struct dram_timing_info *info, + unsigned long base); + +/* utils function for ddr phy training */ +int wait_ddrphy_training_complete(struct dram_controller *dram); + +#define reg32_write(a, v) writel(v, a) +#define reg32_read(a) readl(a) + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +static inline void *dwc_ddrphy_apb_addr(struct dram_controller *dram, unsigned int addr) +{ + if (dram->phy_remap) + addr = dram->phy_remap(addr); + else + addr *= 4; + + return dram->phy_base + addr; +} + +static inline void dwc_ddrphy_apb_wr(struct dram_controller *dram, unsigned int addr, u32 data) +{ + reg32_write(dwc_ddrphy_apb_addr(dram, addr), data); +} + +static inline u32 dwc_ddrphy_apb_rd(struct dram_controller *dram, unsigned int addr) +{ + return reg32_read(dwc_ddrphy_apb_addr(dram, addr)); +} + +extern struct dram_cfg_param ddrphy_trained_csr[]; +extern uint32_t ddrphy_trained_csr_num; + +enum ddrc_phy_firmware_offset { + DDRC_PHY_IMEM = 0x00050000U, + DDRC_PHY_DMEM = 0x00054000U, +}; + +void ddr_load_train_code(struct dram_controller *dram, enum dram_type dram_type, + enum fw_type fw_type); + +void ddrc_phy_load_firmware(struct dram_controller *dram, + enum ddrc_phy_firmware_offset, + const u16 *, size_t); + +static inline bool dram_is_lpddr4(enum dram_type dram_type) +{ + return IS_ENABLED(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) && + dram_type == DRAM_TYPE_LPDDR4; +} + +static inline bool dram_is_ddr4(enum dram_type dram_type) +{ + return IS_ENABLED(CONFIG_FIRMWARE_IMX_DDR4_PMU_TRAIN) && + dram_type == DRAM_TYPE_DDR4; +} + +#define DDRC_PHY_REG(x) ((x) * 4) + +#endif /* __SOC_IMX_DDR_H */ diff --git a/include/soc/imx/gpmi-nand.h b/include/soc/imx/gpmi-nand.h new file mode 100644 index 0000000000..a552513e0d --- /dev/null +++ b/include/soc/imx/gpmi-nand.h @@ -0,0 +1,147 @@ +#ifndef __SOC_IMX_GPMI_NAND_H +#define __SOC_IMX_GPMI_NAND_H + +#include <linux/bitfield.h> + +#define GPMI_CTRL0 0x00000000 +#define GPMI_CTRL0_SFTRST BIT(31) +#define GPMI_CTRL0_RUN BIT(29) +#define GPMI_CTRL0_DEV_IRQ_EN BIT(28) +#define GPMI_CTRL0_UDMA BIT(26) +#define GPMI_CTRL0_COMMAND_MODE GENMASK(25, 24) +#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) +#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) +#define GPMI_CTRL0_WORD_LENGTH (1 << 23) +#define GPMI_CTRL0_CS GENMASK(22, 20) +#define GPMI_CTRL0_ADDRESS GENMASK(19, 17) +#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) +#define GPMI_CTRL0_ADDRESS_INCREMENT BIT(16) +#define GPMI_CTRL0_XFER_COUNT GENMASK(15, 0) + +#define GPMI_CTRL1 0x00000060 +#define GPMI_CTRL1_SET 0x00000064 +#define GPMI_CTRL1_CLR 0x00000068 +#define GPMI_CTRL1_DECOUPLE_CS BIT(24) +#define GPMI_CTRL1_WRN_DLY(d) (((d) & 0x3) << 22) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN BIT(20) +#define GPMI_CTRL1_GANGED_RDYBUSY BIT(19) +#define GPMI_CTRL1_BCH_MODE BIT(18) +#define GPMI_CTRL1_DLL_ENABLE BIT(17) +#define GPMI_CTRL1_HALF_PERIOD BIT(16) +#define GPMI_CTRL1_RDN_DELAY(d) (((d) & 0xf) << 12) +#define GPMI_CTRL1_DMA2ECC_MODE BIT(11) +#define GPMI_CTRL1_DEV_IRQ BIT(10) +#define GPMI_CTRL1_TIMEOUT_IRQ BIT(9) +#define GPMI_CTRL1_BURST_EN BIT(8) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST BIT(7) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY GENMASK(6, 4) +#define GPMI_CTRL1_DEV_RESET BIT(3) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY BIT(2) +#define GPMI_CTRL1_CAMERA_MODE BIT(1) +#define GPMI_CTRL1_GPMI_MODE BIT(0) + +#define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0 +#define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1 +#define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2 +#define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3 + +#define GPMI_TIMING0 0x00000070 + +#define GPMI_TIMING0_ADDRESS_SETUP(d) (((d) & 0xff) << 16) +#define GPMI_TIMING0_DATA_HOLD(d) (((d) & 0xff) << 8) +#define GPMI_TIMING0_DATA_SETUP(d) (((d) & 0xff) << 0) + +#define GPMI_TIMING1 0x00000080 +#define GPMI_TIMING1_BUSY_TIMEOUT(d) (((d) & 0xffff) << 16) + +#define GPMI_ECCCTRL_HANDLE GENMASK(31, 16) +#define GPMI_ECCCTRL_ECC_CMD GENMASK(14, 13) +#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) +#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) +#define GPMI_ECCCTRL_RANDOMIZER_ENABLE BIT(11) +#define GPMI_ECCCTRL_RANDOMIZER_TYPE0 0 +#define GPMI_ECCCTRL_RANDOMIZER_TYPE1 (1 << 9) +#define GPMI_ECCCTRL_RANDOMIZER_TYPE2 (2 << 9) +#define GPMI_ECCCTRL_ENABLE_ECC BIT(12) +#define GPMI_ECCCTRL_BUFFER_MASK GENMASK(8, 0) +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff + +#define GPMI_STAT 0x000000b0 +#define GPMI_STAT_READY_BUSY_OFFSET 24 + +#define GPMI_DEBUG 0x000000c0 +#define GPMI_DEBUG_READY0_OFFSET 28 + +#define GPMI_VERSION 0x000000d0 +#define GPMI_VERSION_MINOR_OFFSET 16 +#define GPMI_VERSION_TYPE_MX23 0x0300 + +#define BCH_CTRL 0x00000000 +#define BCH_CTRL_COMPLETE_IRQ BIT(0) +#define BCH_CTRL_COMPLETE_IRQ_EN BIT(8) + +#define BCH_LAYOUTSELECT 0x00000070 + +#define BCH_FLASH0LAYOUT0 0x00000080 +#define BCH_FLASHLAYOUT0_NBLOCKS GENMASK(31, 24) +#define BCH_FLASHLAYOUT0_META_SIZE GENMASK(23, 16) +#define BCH_FLASHLAYOUT0_ECC0 GENMASK(15, 12) +#define IMX6_BCH_FLASHLAYOUT0_ECC0 GENMASK(15, 11) +#define BCH_FLASHLAYOUT0_DATA0_SIZE GENMASK(9, 0) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 BIT(10) + +#define BCH_FLASH0LAYOUT1 0x00000090 +#define BCH_FLASHLAYOUT1_PAGE_SIZE GENMASK(31, 16) +#define BCH_FLASHLAYOUT1_ECCN GENMASK(15, 12) +#define IMX6_BCH_FLASHLAYOUT1_ECCN GENMASK(15, 11) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 BIT(10) +#define BCH_FLASHLAYOUT1_DATAN_SIZE GENMASK(9, 0) + +#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 + +#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 +#define MXS_NAND_METADATA_SIZE 10 + +#define MXS_NAND_COMMAND_BUFFER_SIZE 32 + +#define MXS_NAND_BCH_TIMEOUT 10000 + +#define BCH62_WRITESIZE 1024 +#define BCH62_OOBSIZE 838 +#define BCH62_PAGESIZE (BCH62_WRITESIZE + BCH62_OOBSIZE) + +/* + * Some SoCs like the i.MX7 use a special layout in the FCB block. + * We can read/write that by adjusting the BCH engine to that layout. + * Particularly we have pages consisting of 8 chunks with 128 bytes + * of data and 100.75 bytes of ECC data each. + */ +static void mxs_nand_mode_fcb_62bit(void __iomem *bch_regs) +{ + u32 fl0, fl1; + + /* 8 ecc_chunks */ + fl0 = FIELD_PREP(BCH_FLASHLAYOUT0_NBLOCKS, 7); + /* 32 bytes for metadata */ + fl0 |= FIELD_PREP(BCH_FLASHLAYOUT0_META_SIZE, 32); + /* using ECC62 level to be performed */ + fl0 |= FIELD_PREP(IMX6_BCH_FLASHLAYOUT0_ECC0, 0x1f); + /* 0x20 * 4 bytes of the data0 block */ + fl0 |= FIELD_PREP(BCH_FLASHLAYOUT0_DATA0_SIZE, 0x20); + writel(fl0, bch_regs + BCH_FLASH0LAYOUT0); + + /* 1024 for data + 838 for OOB */ + fl1 = FIELD_PREP(BCH_FLASHLAYOUT1_PAGE_SIZE, BCH62_PAGESIZE); + /* using ECC62 level to be performed */ + fl1 |= FIELD_PREP(IMX6_BCH_FLASHLAYOUT1_ECCN, 0x1f); + /* 0x20 * 4 bytes of the data0 block */ + fl1 |= FIELD_PREP(BCH_FLASHLAYOUT1_DATAN_SIZE, 0x20); + writel(fl1, bch_regs + BCH_FLASH0LAYOUT1); +} + +#endif /* __SOC_IMX_GPMI_NAND_H */ diff --git a/include/soc/imx/imx-nand-bcb.h b/include/soc/imx/imx-nand-bcb.h index b60205bd59..c5481e602e 100644 --- a/include/soc/imx/imx-nand-bcb.h +++ b/include/soc/imx/imx-nand-bcb.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __MACH_IMX_NAND_BCB_H #define __MACH_IMX_NAND_BCB_H @@ -75,6 +77,17 @@ struct fcb_block { uint32_t DISBBM; /* the flag to enable (1)/disable(0) bi swap */ uint32_t BBMarkerPhysicalOffsetInSpareData; /* The swap position of main area in spare area */ + + /* iMX7 only */ + uint32_t onfi_sync_enable; /* enable Onfi nand sync support */ + uint32_t onfi_sync_speed; /* Speed for Onfi nand sync mode */ + uint32_t onfi_sync_nand_data; /* parameters for Onfi nand sync mode timing */ + uint32_t reserved[6]; + uint32_t disbbm_search; /* disable bad block search function when reading the firmware, only using DBBT */ + uint32_t disbbm_search_limit; /* ???randomizer type 2 enable ???*/ + uint32_t reserved1[15]; /* reserved for future use */ + uint32_t read_retry_enable; /* enable read retry for DBBT and firmware */ + uint32_t reserved2[1]; /*reserved, keep at 0 */ }; #endif /* __MACH_IMX_NAND_BCB_H */ diff --git a/include/soc/imx8m/clk-early.h b/include/soc/imx8m/clk-early.h index 1e1ca59543..c2034e54f0 100644 --- a/include/soc/imx8m/clk-early.h +++ b/include/soc/imx8m/clk-early.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __SOC_IMX8M_CLK_EARLY_H #define __SOC_IMX8M_CLK_EARLY_H diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h index 9ae7cb8776..5df07772b3 100644 --- a/include/soc/imx8m/ddr.h +++ b/include/soc/imx8m/ddr.h @@ -8,12 +8,10 @@ #include <io.h> #include <asm/types.h> -#include <soc/imx8m/ddr.h> +#include <mach/imx/imx8m-regs.h> +#include <soc/imx/ddr.h> -#define DDRC_DDR_SS_GPR0 0x3d000000 -#define DDRC_IPS_BASE_ADDR_0 0x3f400000 -#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) -#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) MX8M_DDRC_PHY_BASE_ADDR #define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) @@ -321,118 +319,65 @@ #define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) #define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) -#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000)) +#define DDRC_IPS_BASE_ADDR(X) MX8M_DDRC_IPS_BASE_ADDR(X) -/* user data type */ -enum fw_type { - FW_1D_IMAGE, - FW_2D_IMAGE, -}; +int imx8m_ddr_init(struct dram_controller *dram, struct dram_timing_info *dram_timing); -enum dram_type { - DRAM_TYPE_LPDDR4, - DRAM_TYPE_DDR4, -}; +extern struct dram_controller imx8m_dram_controller; -struct dram_cfg_param { - unsigned int reg; - unsigned int val; -}; - -struct dram_fsp_msg { - unsigned int drate; - enum fw_type fw_type; - struct dram_cfg_param *fsp_cfg; - unsigned int fsp_cfg_num; -}; - -struct dram_timing_info { - enum dram_type dram_type; - /* umctl2 config */ - struct dram_cfg_param *ddrc_cfg; - unsigned int ddrc_cfg_num; - /* ddrphy config */ - struct dram_cfg_param *ddrphy_cfg; - unsigned int ddrphy_cfg_num; - /* ddr fsp train info */ - struct dram_fsp_msg *fsp_msg; - unsigned int fsp_msg_num; - /* ddr phy trained CSR */ - struct dram_cfg_param *ddrphy_trained_csr; - unsigned int ddrphy_trained_csr_num; - /* ddr phy PIE */ - struct dram_cfg_param *ddrphy_pie; - unsigned int ddrphy_pie_num; - /* initialized drate table */ - unsigned int fsp_table[4]; -}; - -extern struct dram_timing_info dram_timing; +static inline int imx8mm_ddr_init(struct dram_timing_info *dram_timing, + enum dram_type dram_type) +{ + imx8m_dram_controller.ddrc_type = DDRC_TYPE_MM; + imx8m_dram_controller.dram_type = dram_type; -enum ddrc_type { - DDRC_TYPE_MM, - DDRC_TYPE_MN, - DDRC_TYPE_MQ, - DDRC_TYPE_MP, -}; + ddr_get_firmware(dram_type); -int imx8mm_ddr_init(struct dram_timing_info *timing_info); -int imx8mn_ddr_init(struct dram_timing_info *timing_info); -int imx8mq_ddr_init(struct dram_timing_info *timing_info); -int imx8mp_ddr_init(struct dram_timing_info *timing_info); -int ddr_cfg_phy(struct dram_timing_info *timing_info, enum ddrc_type type); -void load_lpddr4_phy_pie(void); -void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); -void dram_config_save(struct dram_timing_info *info, unsigned long base); + return imx8m_ddr_init(&imx8m_dram_controller, dram_timing); +} -/* utils function for ddr phy training */ -int wait_ddrphy_training_complete(void); -void ddrphy_init_set_dfi_clk(unsigned int drate, enum ddrc_type type); -void ddrphy_init_read_msg_block(enum fw_type type); +static inline int imx8mn_ddr_init(struct dram_timing_info *dram_timing, + enum dram_type dram_type) +{ + imx8m_dram_controller.ddrc_type = DDRC_TYPE_MN; + imx8m_dram_controller.dram_type = dram_type; -void update_umctl2_rank_space_setting(unsigned int pstat_num, - enum ddrc_type type); -void get_trained_CDD(unsigned int fsp); + ddr_get_firmware(dram_type); -#define reg32_write(a, v) writel(v, a) -#define reg32_read(a) readl(a) + return imx8m_ddr_init(&imx8m_dram_controller, dram_timing); +} -static inline void reg32setbit(unsigned long addr, u32 bit) +static inline int imx8mq_ddr_init(struct dram_timing_info *dram_timing, + enum dram_type dram_type) { - setbits_le32(addr, (1 << bit)); -} + imx8m_dram_controller.ddrc_type = DDRC_TYPE_MQ; + imx8m_dram_controller.dram_type = dram_type; -#define dwc_ddrphy_apb_wr(addr, data) \ - reg32_write(IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)) + 4 * (addr), data) -#define dwc_ddrphy_apb_rd(addr) \ - reg32_read(IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)) + 4 * (addr)) + ddr_get_firmware(dram_type); -extern struct dram_cfg_param ddrphy_trained_csr[]; -extern uint32_t ddrphy_trained_csr_num; + return imx8m_ddr_init(&imx8m_dram_controller, dram_timing); +} -enum ddrc_phy_firmware_offset { - DDRC_PHY_IMEM = 0x00050000U, - DDRC_PHY_DMEM = 0x00054000U, -}; +static inline int imx8mp_ddr_init(struct dram_timing_info *dram_timing, + enum dram_type dram_type) +{ + imx8m_dram_controller.ddrc_type = DDRC_TYPE_MP; + imx8m_dram_controller.dram_type = dram_type; -void ddr_load_train_code(enum dram_type dram_type, enum fw_type type); + ddr_get_firmware(dram_type); -void ddrc_phy_load_firmware(void __iomem *, - enum ddrc_phy_firmware_offset, - const u16 *, size_t); + return imx8m_ddr_init(&imx8m_dram_controller, dram_timing); +} -static inline bool dram_is_lpddr4(enum dram_type type) +static inline int imx8m_wait_ddrphy_training_complete(void) { - return IS_ENABLED(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) && - type == DRAM_TYPE_LPDDR4; + return wait_ddrphy_training_complete(&imx8m_dram_controller); } -static inline bool dram_is_ddr4(enum dram_type type) +static inline void imx8m_ddr_load_train_code(enum dram_type dram_type, + enum fw_type fw_type) { - return IS_ENABLED(CONFIG_FIRMWARE_IMX_DDR4_PMU_TRAIN) && - type == DRAM_TYPE_DDR4; + ddr_load_train_code(&imx8m_dram_controller, dram_type, fw_type); } -#define DDRC_PHY_REG(x) ((x) * 4) - #endif diff --git a/include/soc/imx8m/featctrl.h b/include/soc/imx8m/featctrl.h new file mode 100644 index 0000000000..380e417778 --- /dev/null +++ b/include/soc/imx8m/featctrl.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix */ + +#ifndef __IMX8M_FEATCTRL_H_ +#define __IMX8M_FEATCTRL_H_ + +#include <linux/types.h> + +struct imx8m_featctrl_data { + struct { + u32 vpu_bitmask; + u32 cpu_bitmask; + } tester3; + struct { + u32 vpu_bitmask; + u32 gpu_bitmask; + u32 mipi_dsi_bitmask; + u32 isp_bitmask; + u32 cpu_bitmask; + u32 npu_bitmask; + u32 lvds_bitmask; + u32 dsp_bitmask; + } tester4; +}; + +struct device; + +#ifdef CONFIG_IMX8M_FEATCTRL +int imx8m_feat_ctrl_init(struct device *dev, u32 tester3, u32 tester4, + const struct imx8m_featctrl_data *data); +#else +static inline int imx8m_feat_ctrl_init(struct device *dev, u32 tester3, u32 tester4, + const struct imx8m_featctrl_data *data) +{ + return -ENODEV; +} +#endif + +#endif diff --git a/include/soc/imx9/ddr.h b/include/soc/imx9/ddr.h new file mode 100644 index 0000000000..6435ce9d6d --- /dev/null +++ b/include/soc/imx9/ddr.h @@ -0,0 +1,18 @@ +#ifndef __SOC_IMX9_DDR_H +#define __SOC_IMX9_DDR_H + +#include <io.h> +#include <asm/types.h> +#include <soc/imx/ddr.h> + +int imx9_ddr_init(struct dram_timing_info *dram_timing, enum dram_type dram_type); + +static inline int imx93_ddr_init(struct dram_timing_info *dram_timing, + enum dram_type dram_type) +{ + ddr_get_firmware(dram_type); + + return imx9_ddr_init(dram_timing, dram_type); +} + +#endif /* __SOC_IMX9_DDR_H */ diff --git a/include/soc/imx9/flash_header.h b/include/soc/imx9/flash_header.h new file mode 100644 index 0000000000..51819929dd --- /dev/null +++ b/include/soc/imx9/flash_header.h @@ -0,0 +1,88 @@ +#ifndef SOC_IMX_FLASH_HEADER_H +#define SOC_IMX_FLASH_HEADER_H + +#define HASH_MAX_LEN 64 +#define IV_MAX_LEN 32 +#define MAX_NUM_IMGS 8 +#define MAX_NUM_OF_CONTAINER 3 +#define MAX_HW_CFG_SIZE_V2 359 + +struct img_flags { + char type; + char core_id; + char hash_type; + bool encrypted; + uint16_t boot_flags; +}; + +struct sig_blk_hdr { + uint8_t version; + uint16_t length; + uint8_t tag; + uint16_t srk_table_offset; + uint16_t cert_offset; + uint16_t blob_offset; + uint16_t signature_offset; + uint32_t reserved; +} __attribute__((packed)); + +struct boot_img { + uint32_t offset; + uint32_t size; + uint64_t dst; + uint64_t entry; + uint32_t hab_flags; + uint32_t meta; + uint8_t hash[HASH_MAX_LEN]; + uint8_t iv[IV_MAX_LEN]; +} __attribute__((packed)); + +struct flash_header_v3 { + uint8_t version; + uint16_t length; + uint8_t tag; + uint32_t flags; + uint16_t sw_version; + uint8_t fuse_version; + uint8_t num_images; + uint16_t sig_blk_offset; + uint16_t reserved; + struct boot_img img[MAX_NUM_IMGS]; + struct sig_blk_hdr sig_blk_hdr; + uint32_t sigblk_size; + uint32_t padding; +} __attribute__((packed)); + +struct ivt_header { + uint8_t tag; + uint16_t length; + uint8_t version; +} __attribute__((packed)); + +struct write_dcd_command { + uint8_t tag; + uint16_t length; + uint8_t param; +} __attribute__((packed)); + +struct dcd_addr_data { + uint32_t addr; + uint32_t value; +}; + +struct dcd_v2_cmd { + struct write_dcd_command write_dcd_command; /*4*/ + struct dcd_addr_data addr_data[MAX_HW_CFG_SIZE_V2]; /*2872*/ +} __attribute__((packed)); + +struct dcd_v2 { + struct ivt_header header; /*4*/ + struct dcd_v2_cmd dcd_cmd; /*2876*/ +} __attribute__((packed)) ; /*2880*/ + +struct imx_header_v3 { + struct flash_header_v3 fhdr[MAX_NUM_OF_CONTAINER]; + struct dcd_v2 dcd_table; +} __attribute__((packed)); + +#endif /* SOC_IMX_FLASH_HEADER_H */ diff --git a/include/soc/stm32/gpio.h b/include/soc/stm32/gpio.h index 13b492a693..448fb19e2e 100644 --- a/include/soc/stm32/gpio.h +++ b/include/soc/stm32/gpio.h @@ -25,6 +25,10 @@ #define STM32_PIN_AF(x) ((x) + 1) #define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1) +#define STM32_PINMODE_GPIO 0 +#define STM32_PINMODE_AF 2 +#define STM32_PINMODE_ANALOG 3 + #define STM32_GPIO_PINS_PER_BANK 16 enum stm32_pin_bias { STM32_PIN_NO_BIAS, STM32_PIN_PULL_UP, STM32_PIN_PULL_DOWN }; diff --git a/include/soc/stm32/reboot.h b/include/soc/stm32/reboot.h new file mode 100644 index 0000000000..c067c27229 --- /dev/null +++ b/include/soc/stm32/reboot.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __SOC_STM32_REBOOT_H_ +#define __SOC_STM32_REBOOT_H_ + +#include <linux/compiler.h> + +struct device; + +#ifdef CONFIG_RESET_STM32 +void stm32mp_system_restart_init(struct device *rcc); +#else +static inline void stm32mp_system_restart_init(struct device *rcc) +{ +} +#endif + +#endif diff --git a/include/soc/ti/k3-sec-proxy.h b/include/soc/ti/k3-sec-proxy.h new file mode 100644 index 0000000000..f34854ceeb --- /dev/null +++ b/include/soc/ti/k3-sec-proxy.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Texas Instruments' K3 Secure proxy + * + * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + * + */ + +#ifndef K3_SEC_PROXY_H +#define K3_SEC_PROXY_H + +/** + * struct k3_sec_proxy_msg - Secure proxy message structure + * @len: Length of data in the Buffer + * @buf: Buffer pointer + * + * This is the structure for data used in mbox_send() and mbox_recv(). + */ +struct k3_sec_proxy_msg { + size_t len; + u32 *buf; +}; + +#endif /* K3_SEC_PROXY_H */ diff --git a/include/soc/ti/ti_sci_protocol.h b/include/soc/ti/ti_sci_protocol.h new file mode 100644 index 0000000000..ec69f07b8e --- /dev/null +++ b/include/soc/ti/ti_sci_protocol.h @@ -0,0 +1,657 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Texas Instruments System Control Interface Protocol + * Based on include/linux/soc/ti/ti_sci_protocol.h from Linux. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Nishanth Menon + * Lokesh Vutla <lokeshvutla@ti.com> + */ + +#ifndef __TISCI_PROTOCOL_H +#define __TISCI_PROTOCOL_H + +#include <linux/bitops.h> +#include <linux/err.h> + +/** + * struct ti_sci_version_info - version information structure + * @abi_major: Major ABI version. Change here implies risk of backward + * compatibility break. + * @abi_minor: Minor ABI version. Change here implies new feature addition, + * or compatible change in ABI. + * @firmware_revision: Firmware revision (not usually used). + * @firmware_description: Firmware description (not usually used). + */ +struct ti_sci_version_info { + u8 abi_major; + u8 abi_minor; + u16 firmware_revision; + char firmware_description[32]; +}; + +struct ti_sci_handle; + +/** + * struct ti_sci_board_ops - Board config operations + * @board_config: Command to set the board configuration + * Returns 0 for successful exclusive request, else returns + * corresponding error message. + * @board_config_rm: Command to set the board resource management + * configuration + * Returns 0 for successful exclusive request, else returns + * corresponding error message. + * @board_config_security: Command to set the board security configuration + * Returns 0 for successful exclusive request, else returns + * corresponding error message. + * @board_config_pm: Command to trigger and set the board power and clock + * management related configuration + * Returns 0 for successful exclusive request, else returns + * corresponding error message. + */ +struct ti_sci_board_ops { + int (*board_config)(const struct ti_sci_handle *handle, + u64 addr, u32 size); + int (*board_config_rm)(const struct ti_sci_handle *handle, + u64 addr, u32 size); + int (*board_config_security)(const struct ti_sci_handle *handle, + u64 addr, u32 size); + int (*board_config_pm)(const struct ti_sci_handle *handle, + u64 addr, u32 size); +}; + +/** + * struct ti_sci_dev_ops - Device control operations + * @get_device: Command to request for device managed by TISCI + * Returns 0 for successful exclusive request, else returns + * corresponding error message. + * @idle_device: Command to idle a device managed by TISCI + * Returns 0 for successful exclusive request, else returns + * corresponding error message. + * @put_device: Command to release a device managed by TISCI + * Returns 0 for successful release, else returns corresponding + * error message. + * @is_valid: Check if the device ID is a valid ID. + * Returns 0 if the ID is valid, else returns corresponding error. + * @get_context_loss_count: Command to retrieve context loss counter - this + * increments every time the device looses context. Overflow + * is possible. + * - count: pointer to u32 which will retrieve counter + * Returns 0 for successful information request and count has + * proper data, else returns corresponding error message. + * @is_idle: Reports back about device idle state + * - req_state: Returns requested idle state + * Returns 0 for successful information request and req_state and + * current_state has proper data, else returns corresponding error + * message. + * @is_stop: Reports back about device stop state + * - req_state: Returns requested stop state + * - current_state: Returns current stop state + * Returns 0 for successful information request and req_state and + * current_state has proper data, else returns corresponding error + * message. + * @is_on: Reports back about device ON(or active) state + * - req_state: Returns requested ON state + * - current_state: Returns current ON state + * Returns 0 for successful information request and req_state and + * current_state has proper data, else returns corresponding error + * message. + * @is_transitioning: Reports back if the device is in the middle of transition + * of state. + * -current_state: Returns 'true' if currently transitioning. + * @set_device_resets: Command to configure resets for device managed by TISCI. + * -reset_state: Device specific reset bit field + * Returns 0 for successful request, else returns + * corresponding error message. + * @get_device_resets: Command to read state of resets for device managed + * by TISCI. + * -reset_state: pointer to u32 which will retrieve resets + * Returns 0 for successful request, else returns + * corresponding error message. + * @release_exclusive_devices: Command to release all the exclusive devices + * attached to this host. This should be used very carefully + * and only at the end of execution of your software. + * + * NOTE: for all these functions, the following parameters are generic in + * nature: + * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * -id: Device Identifier + * + * Request for the device - NOTE: the client MUST maintain integrity of + * usage count by balancing get_device with put_device. No refcounting is + * managed by driver for that purpose. + */ +struct ti_sci_dev_ops { + int (*get_device)(const struct ti_sci_handle *handle, u32 id); + int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id); + int (*idle_device)(const struct ti_sci_handle *handle, u32 id); + int (*idle_device_exclusive)(const struct ti_sci_handle *handle, + u32 id); + int (*put_device)(const struct ti_sci_handle *handle, u32 id); + int (*is_valid)(const struct ti_sci_handle *handle, u32 id); + int (*get_context_loss_count)(const struct ti_sci_handle *handle, + u32 id, u32 *count); + int (*is_idle)(const struct ti_sci_handle *handle, u32 id, + bool *requested_state); + int (*is_stop)(const struct ti_sci_handle *handle, u32 id, + bool *req_state, bool *current_state); + int (*is_on)(const struct ti_sci_handle *handle, u32 id, + bool *req_state, bool *current_state); + int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id, + bool *current_state); + int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id, + u32 reset_state); + int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id, + u32 *reset_state); + int (*release_exclusive_devices)(const struct ti_sci_handle *handle); +}; + +/** + * struct ti_sci_clk_ops - Clock control operations + * @get_clock: Request for activation of clock and manage by processor + * - needs_ssc: 'true' if Spread Spectrum clock is desired. + * - can_change_freq: 'true' if frequency change is desired. + * - enable_input_term: 'true' if input termination is desired. + * @idle_clock: Request for Idling a clock managed by processor + * @put_clock: Release the clock to be auto managed by TISCI + * @is_auto: Is the clock being auto managed + * - req_state: state indicating if the clock is auto managed + * @is_on: Is the clock ON + * - req_state: if the clock is requested to be forced ON + * - current_state: if the clock is currently ON + * @is_off: Is the clock OFF + * - req_state: if the clock is requested to be forced OFF + * - current_state: if the clock is currently Gated + * @set_parent: Set the clock source of a specific device clock + * - parent_id: Parent clock identifier to set. + * @get_parent: Get the current clock source of a specific device clock + * - parent_id: Parent clock identifier which is the parent. + * @get_num_parents: Get the number of parents of the current clock source + * - num_parents: returns the number of parent clocks. + * @get_best_match_freq: Find a best matching frequency for a frequency + * range. + * - match_freq: Best matching frequency in Hz. + * @set_freq: Set the Clock frequency + * @get_freq: Get the Clock frequency + * - current_freq: Frequency in Hz that the clock is at. + * + * NOTE: for all these functions, the following parameters are generic in + * nature: + * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * -did: Device identifier this request is for + * -cid: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * -min_freq: The minimum allowable frequency in Hz. This is the minimum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * -target_freq: The target clock frequency in Hz. A frequency will be + * processed as close to this target frequency as possible. + * -max_freq: The maximum allowable frequency in Hz. This is the maximum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * + * Request for the clock - NOTE: the client MUST maintain integrity of + * usage count by balancing get_clock with put_clock. No refcounting is + * managed by driver for that purpose. + */ +struct ti_sci_clk_ops { + int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid, + bool needs_ssc, bool can_change_freq, + bool enable_input_term); + int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid); + int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid); + int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u8 cid, + bool *req_state); + int (*is_on)(const struct ti_sci_handle *handle, u32 did, u8 cid, + bool *req_state, bool *current_state); + int (*is_off)(const struct ti_sci_handle *handle, u32 did, u8 cid, + bool *req_state, bool *current_state); + int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid, + u8 parent_id); + int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid, + u8 *parent_id); + int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did, + u8 cid, u8 *num_parents); + int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did, + u8 cid, u64 min_freq, u64 target_freq, + u64 max_freq, u64 *match_freq); + int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid, + u64 min_freq, u64 target_freq, u64 max_freq); + int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid, + u64 *current_freq); +}; + +/** + * struct ti_sci_rm_core_ops - Resource management core operations + * @get_range: Get a range of resources belonging to ti sci host. + * @get_rage_from_shost: Get a range of resources belonging to + * specified host id. + * - s_host: Host processing entity to which the + * resources are allocated + * + * NOTE: for these functions, all the parameters are consolidated and defined + * as below: + * - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * - dev_id: TISCI device ID. + * - subtype: Resource assignment subtype that is being requested + * from the given device. + * - range_start: Start index of the resource range + * - range_end: Number of resources in the range + */ +struct ti_sci_rm_core_ops { + int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id, + u8 subtype, u16 *range_start, u16 *range_num); + int (*get_range_from_shost)(const struct ti_sci_handle *handle, + u32 dev_id, u8 subtype, u8 s_host, + u16 *range_start, u16 *range_num); +}; + +/** + * struct ti_sci_core_ops - SoC Core Operations + * @reboot_device: Reboot the SoC + * Returns 0 for successful request(ideally should never return), + * else returns corresponding error value. + * @query_msmc: Query the size of available msmc + * Return 0 for successful query else appropriate error value. + */ +struct ti_sci_core_ops { + int (*reboot_device)(const struct ti_sci_handle *handle); + int (*query_msmc)(const struct ti_sci_handle *handle, + u64 *msmc_start, u64 *msmc_end); +}; + +/** + * struct ti_sci_proc_ops - Processor specific operations. + * + * @proc_request: Request for controlling a physical processor. + * The requesting host should be in the processor access list. + * @proc_release: Relinquish a physical processor control + * @proc_handover: Handover a physical processor control to another host + * in the permitted list. + * @set_proc_boot_cfg: Base configuration of the processor + * @set_proc_boot_ctrl: Setup limited control flags in specific cases. + * @proc_auth_boot_image: + * @get_proc_boot_status: Get the state of physical processor + * @proc_shutdown_no_wait: Shutdown a core without requesting or waiting for a + * response. + * + * NOTE: for all these functions, the following parameters are generic in + * nature: + * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * -pid: Processor ID + * + */ +struct ti_sci_proc_ops { + int (*proc_request)(const struct ti_sci_handle *handle, u8 pid); + int (*proc_release)(const struct ti_sci_handle *handle, u8 pid); + int (*proc_handover)(const struct ti_sci_handle *handle, u8 pid, + u8 hid); + int (*set_proc_boot_cfg)(const struct ti_sci_handle *handle, u8 pid, + u64 bv, u32 cfg_set, u32 cfg_clr); + int (*set_proc_boot_ctrl)(const struct ti_sci_handle *handle, u8 pid, + u32 ctrl_set, u32 ctrl_clr); + int (*proc_auth_boot_image)(const struct ti_sci_handle *handle, + u64 *image_addr, u32 *image_size); + int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid, + u64 *bv, u32 *cfg_flags, u32 *ctrl_flags, + u32 *sts_flags); + int (*proc_shutdown_no_wait)(const struct ti_sci_handle *handle, + u8 pid); +}; + +#define TI_SCI_RING_MODE_RING (0) +#define TI_SCI_RING_MODE_MESSAGE (1) +#define TI_SCI_RING_MODE_CREDENTIALS (2) +#define TI_SCI_RING_MODE_QM (3) + +#define TI_SCI_MSG_UNUSED_SECONDARY_HOST TI_SCI_RM_NULL_U8 + +/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0) +/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1) + /* RA config.count parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2) +/* RA config.mode parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3) +/* RA config.size parameter is valid for RM ring configure TI_SCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4) +/* RA config.order_id parameter is valid for RM ring configure TISCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5) + +#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \ + (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \ + TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \ + TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \ + TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \ + TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID) + +/** + * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations + * @config: configure the SoC Navigator Subsystem Ring Accelerator ring + */ +struct ti_sci_rm_ringacc_ops { + int (*config)(const struct ti_sci_handle *handle, + u32 valid_params, u16 nav_id, u16 index, + u32 addr_lo, u32 addr_hi, u32 count, u8 mode, + u8 size, u8 order_id + ); +}; + +/** + * struct ti_sci_rm_psil_ops - PSI-L thread operations + * @pair: pair PSI-L source thread to a destination thread. + * If the src_thread is mapped to UDMA tchan, the corresponding channel's + * TCHAN_THRD_ID register is updated. + * If the dst_thread is mapped to UDMA rchan, the corresponding channel's + * RCHAN_THRD_ID register is updated. + * @unpair: unpair PSI-L source thread from a destination thread. + * If the src_thread is mapped to UDMA tchan, the corresponding channel's + * TCHAN_THRD_ID register is cleared. + * If the dst_thread is mapped to UDMA rchan, the corresponding channel's + * RCHAN_THRD_ID register is cleared. + */ +struct ti_sci_rm_psil_ops { + int (*pair)(const struct ti_sci_handle *handle, u32 nav_id, + u32 src_thread, u32 dst_thread); + int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id, + u32 src_thread, u32 dst_thread); +}; + +/* UDMAP channel types */ +#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2 +#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */ +#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10 +#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11 +#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12 +#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13 + +/* UDMAP channel atypes */ +#define TI_SCI_RM_UDMAP_ATYPE_PHYS 0 +#define TI_SCI_RM_UDMAP_ATYPE_INTERMEDIATE 1 +#define TI_SCI_RM_UDMAP_ATYPE_VIRTUAL 2 + +/* UDMAP channel scheduling priorities */ +#define TI_SCI_RM_UDMAP_SCHED_PRIOR_HIGH 0 +#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDHIGH 1 +#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDLOW 2 +#define TI_SCI_RM_UDMAP_SCHED_PRIOR_LOW 3 + +#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0 +#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2 + +#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1 +#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2 +#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3 + +#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0 +#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1 + +/* UDMAP TX/RX channel valid_params common declarations */ +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14) + +/** + * Configures a Navigator Subsystem UDMAP transmit channel + * + * Configures a Navigator Subsystem UDMAP transmit channel registers. + * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req + */ +struct ti_sci_msg_rm_udmap_tx_ch_cfg { + u32 valid_params; +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16) + u16 nav_id; + u16 index; + u8 tx_pause_on_err; + u8 tx_filt_einfo; + u8 tx_filt_pswords; + u8 tx_atype; + u8 tx_chan_type; + u8 tx_supr_tdpkt; + u16 tx_fetch_size; + u8 tx_credit_count; + u16 txcq_qnum; + u8 tx_priority; + u8 tx_qos; + u8 tx_orderid; + u16 fdepth; + u8 tx_sched_priority; + u8 tx_burst_size; + u8 tx_tdtype; + u8 extended_ch_type; +}; + +/** + * Configures a Navigator Subsystem UDMAP receive channel + * + * Configures a Navigator Subsystem UDMAP receive channel registers. + * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req + */ +struct ti_sci_msg_rm_udmap_rx_ch_cfg { + u32 valid_params; +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12) + u16 nav_id; + u16 index; + u16 rx_fetch_size; + u16 rxcq_qnum; + u8 rx_priority; + u8 rx_qos; + u8 rx_orderid; + u8 rx_sched_priority; + u16 flowid_start; + u16 flowid_cnt; + u8 rx_pause_on_err; + u8 rx_atype; + u8 rx_chan_type; + u8 rx_ignore_short; + u8 rx_ignore_long; + u8 rx_burst_size; +}; + +/** + * Configures a Navigator Subsystem UDMAP receive flow + * + * Configures a Navigator Subsystem UDMAP receive flow's registers. + * See @tis_ci_msg_rm_udmap_flow_cfg_req + */ +struct ti_sci_msg_rm_udmap_flow_cfg { + u32 valid_params; +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17) +#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18) + u16 nav_id; + u16 flow_index; + u8 rx_einfo_present; + u8 rx_psinfo_present; + u8 rx_error_handling; + u8 rx_desc_type; + u16 rx_sop_offset; + u16 rx_dest_qnum; + u8 rx_src_tag_hi; + u8 rx_src_tag_lo; + u8 rx_dest_tag_hi; + u8 rx_dest_tag_lo; + u8 rx_src_tag_hi_sel; + u8 rx_src_tag_lo_sel; + u8 rx_dest_tag_hi_sel; + u8 rx_dest_tag_lo_sel; + u16 rx_fdq0_sz0_qnum; + u16 rx_fdq1_qnum; + u16 rx_fdq2_qnum; + u16 rx_fdq3_qnum; + u8 rx_ps_location; +}; + +/** + * struct ti_sci_rm_udmap_ops - UDMA Management operations + * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel. + * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel. + * @rx_flow_cfg: configure SoC Navigator Subsystem UDMA receive flow. + */ +struct ti_sci_rm_udmap_ops { + int (*tx_ch_cfg)(const struct ti_sci_handle *handle, + const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params); + int (*rx_ch_cfg)(const struct ti_sci_handle *handle, + const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params); + int (*rx_flow_cfg)( + const struct ti_sci_handle *handle, + const struct ti_sci_msg_rm_udmap_flow_cfg *params); +}; + +/** + * struct ti_sci_msg_fwl_region_cfg - Request and Response for firewalls settings + * + * @fwl_id: Firewall ID in question + * @region: Region or channel number to set config info + * This field is unused in case of a simple firewall and must be initialized + * to zero. In case of a region based firewall, this field indicates the + * region in question. (index starting from 0) In case of a channel based + * firewall, this field indicates the channel in question (index starting + * from 0) + * @n_permission_regs: Number of permission registers to set + * @control: Contents of the firewall CONTROL register to set + * @permissions: Contents of the firewall PERMISSION register to set + * @start_address: Contents of the firewall START_ADDRESS register to set + * @end_address: Contents of the firewall END_ADDRESS register to set + */ +struct ti_sci_msg_fwl_region { + u16 fwl_id; + u16 region; + u32 n_permission_regs; + u32 control; + u32 permissions[3]; + u64 start_address; + u64 end_address; +} __packed; + +/** + * \brief Request and Response for firewall owner change + * + * @fwl_id: Firewall ID in question + * @region: Region or channel number to set config info + * This field is unused in case of a simple firewall and must be initialized + * to zero. In case of a region based firewall, this field indicates the + * region in question. (index starting from 0) In case of a channel based + * firewall, this field indicates the channel in question (index starting + * from 0) + * @n_permission_regs: Number of permission registers <= 3 + * @control: Control register value for this region + * @owner_index: New owner index to change to. Owner indexes are setup in DMSC firmware boot configuration data + * @owner_privid: New owner priv-id, used to lookup owner_index is not known, must be set to zero otherwise + * @owner_permission_bits: New owner permission bits + */ +struct ti_sci_msg_fwl_owner { + u16 fwl_id; + u16 region; + u8 owner_index; + u8 owner_privid; + u16 owner_permission_bits; +} __packed; + +/** + * struct ti_sci_fwl_ops - Firewall specific operations + * @set_fwl_region: Request for configuring the firewall permissions. + * @get_fwl_region: Request for retrieving the firewall permissions. + * @change_fwl_owner: Request for a change of firewall owner. + */ +struct ti_sci_fwl_ops { + int (*set_fwl_region)(const struct ti_sci_handle *handle, const struct ti_sci_msg_fwl_region *region); + int (*get_fwl_region)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_region *region); + int (*change_fwl_owner)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_owner *owner); +}; + +/** + * struct ti_sci_ops - Function support for TI SCI + * @board_ops: Miscellaneous operations + * @dev_ops: Device specific operations + * @clk_ops: Clock specific operations + * @core_ops: Core specific operations + * @proc_ops: Processor specific operations + * @ring_ops: Ring Accelerator Management operations + * @fw_ops: Firewall specific operations + */ +struct ti_sci_ops { + struct ti_sci_board_ops board_ops; + struct ti_sci_dev_ops dev_ops; + struct ti_sci_clk_ops clk_ops; + struct ti_sci_core_ops core_ops; + struct ti_sci_proc_ops proc_ops; + struct ti_sci_rm_core_ops rm_core_ops; + struct ti_sci_rm_ringacc_ops rm_ring_ops; + struct ti_sci_rm_psil_ops rm_psil_ops; + struct ti_sci_rm_udmap_ops rm_udmap_ops; + struct ti_sci_fwl_ops fwl_ops; +}; + +/** + * struct ti_sci_handle - Handle returned to TI SCI clients for usage. + * @ops: operations that are made available to TI SCI clients + * @version: structure containing version information + */ +struct ti_sci_handle { + struct ti_sci_ops ops; + struct ti_sci_version_info version; +}; + +#define TI_SCI_RESOURCE_NULL 0xffff + +/** + * struct ti_sci_resource_desc - Description of TI SCI resource instance range. + * @start: Start index of the resource. + * @num: Number of resources. + * @res_map: Bitmap to manage the allocation of these resources. + */ +struct ti_sci_resource_desc { + u16 start; + u16 num; + unsigned long *res_map; +}; + +/** + * struct ti_sci_resource - Structure representing a resource assigned + * to a device. + * @sets: Number of sets available from this resource type + * @desc: Array of resource descriptors. + */ +struct ti_sci_resource { + u16 sets; + struct ti_sci_resource_desc *desc; +}; + +const struct ti_sci_handle *ti_sci_get_handle(struct device *dev); + +#endif /* __TISCI_PROTOCOL_H */ |