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* RISC-V: StarFive: J7100: set /soc/dma-noncoherentAhmad Fatoum2024-01-111-0/+1
| | | | | | | | | | With upcoming changes, cache handling will be skipped on RISC-V, because arch is cache-coherent by default. StarFive JH7100 has non-coherent DMA masters though, so note that in the DT. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240110160112.4134162-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: select OF_OVERLAY where appropriateAhmad Fatoum2023-06-131-0/+1
| | | | | | | | | | Both Qemu Virt and riscvemu depend on OF_OVERLAY to apply overlays, but don't care for symbols in the barebox DT (and thus don't need OF_OVERLAY_LIVE). Reflect this in the Kconfig. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230612125331.1085059-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: drop CONFIG_HAS_ASM_DEBUG_LLSascha Hauer2023-03-031-6/+6
| | | | | | | | | | | When CONFIG_HAS_ASM_DEBUG_LL is set then include/debug_ll.h includes asm/debug_ll.h, otherwise it includes mach/debug_ll.h. Drop this option and instead always include asm/debug_ll.h and include mach/debug_ll.h from there if necessary. This also adds the missing asm/debug_ll.h for architectures which previously did not have that file. Link: https://lore.barebox.org/20230302111606.1054037-6-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add Allwinner Sun20i D1 Nezha supportMarco Felsch2022-10-071-0/+16
| | | | | | | | Add Allwinner sun20i SoC and D1-Nezha board support. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20221005111214.148844-7-m.felsch@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: add SPDX-License-Identifier for Kbuild/KconfigAhmad Fatoum2022-01-051-0/+2
| | | | | | | | | | | | | | | To verify only Kconfig/Makefile is touched: git show --numstat --format=oneline HEAD | grep -v 'Kconfig\|Makefile' will print only arch/powerpc/Kbuild. To verify nothing unexpected is added: git show -U0 | grep '^-[^-]\|^+[^+]' | sort -u Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: qemu-virt: add overlay for environment and stateAhmad Fatoum2021-12-071-0/+10
| | | | | | | | | Like we do on ARM, let's add state and environment to RISC-V QEMU Virt as well. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20211125161042.3829996-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: virt: add DEBUG_LL supportAhmad Fatoum2021-12-071-0/+1
| | | | | | | | | | While we have PBL console support, console isn't available during early barebox startup. Implement DEBUG_LL for Qemu RISC-V Virt to make such early debugging easier. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20211125160657.3828643-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: virt: support poweroff/restart on tinyemuAhmad Fatoum2021-10-071-0/+8
| | | | | | | | | | | | QEMU Virt on RISC-V has syscon-reboot and syscon-poweroff compatible devices and describes them in the device tree. TinyEMU's Virt machine is different and has a HTIF based poweroff and no dedicated reset mechanism. Add board support for the HTIF poweroff and use a poor man's reset that jumps back to the reset vector. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210916093532.21699-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add LiteX SoC and linux-on-litex-vexriscv supportAntony Pavlov2021-10-071-0/+14
| | | | | | | | | | | | | | LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. See https://github.com/enjoy-digital/litex and https://github.com/litex-hub/linux-on-litex-vexriscv for details. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210817101104.114945-8-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: boards: beaglev: make it possible to use nmonAntony Pavlov2021-07-091-0/+1
| | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Link: https://lore.barebox.org/20210708083035.40814-4-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: StarFive: add board support for BeagleV StarlightAhmad Fatoum2021-06-241-0/+18
| | | | | | | | | With the different drivers now in place, we have everything to start a barebox image. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-30-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* reset: add StarFive reset controller driverAhmad Fatoum2021-06-241-0/+1
| | | | | | | | | | | | | | | | The StarFive SoC has a single reset controller, which seems to control reset of all clocks and peripherals. It differs from the ones supported by the Linux reset-simple driver in that it has a dedicated status registers that needs to be polled to verify the reset has completed. Also special is that most resets (> 70) are synchronous. As the reset status poll would just time out without the clock, have the reset controller enable the clock as part of the reset. OS can decide later, which clocks to disable again. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-24-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* soc: starfive: add support for JH7100 incoherent interconnectAhmad Fatoum2021-06-241-0/+5
| | | | | | | | | | | | | | | | The preproduction JH7100 used in the BeagleV beta does not ensure cache coherence between CPU and some DMA masters like the Ethernet MAC. Fix this for streaming DMA mappings by implementing cache cleaning and discarding. The Flush64 primitive can be used for both as it will invalidate after flushing and not write-back clean lines. Coherent DMA mapping will be implemented using allocation from uncached SRAM in a follow-up commit. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-14-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: soc: sifive: add basic L2 cache controller driverAhmad Fatoum2021-06-241-0/+5
| | | | | | | | | | | | | | SiFive SoCs are cache coherent with respect to other DMA masters, so there is no need to explicitly flush cache lines. Incoming StarFive SoC uses SiFive CPU and L2 cache controller, but is cache-incoherent and thus needs the maintenance for DMA. Add a basic driver that exports the cache flush function for SoC-specific drivers to use. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-13-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: support incoherent I-CacheAhmad Fatoum2021-06-241-0/+2
| | | | | | | | | | | | | | | | | SiFive SoCs have separate I-Caches that require self-modifying code like barebox' relocation and PBL extraction code to do cache maintenance. Implement sync_caches_for_execution and use it where appropriate. The underlying fence.i primitive is part of the Zifencei (load/store fence) ISA extension. As we can't be sure it's always available, the exception handler will skip over the instruction if the CPU trips over it. Alternatively, if CONFIG_HAS_CACHE=n, the instruction won't be emitted at all. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: socs: add Kconfig entry for StarFive JH7100Ahmad Fatoum2021-06-241-0/+22
| | | | | | | | | | | | The JH7100 is the StarFive SoC with SiFive CPUs in the pre-production BeagleV. Th JH7110 in later boards will be cache-coherent, but the JH7100 will need some workarounds. Add Kconfig symbols, so newly introduced symbols can depend on them. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: extend multi-image to support both S- and M-ModeAhmad Fatoum2021-06-211-0/+2
| | | | | | | | | | | | | | | | | | We can't currently mix S-Mode and M-Mode images in the same build and there's no straight-forward way to determine which mode we are in. Move the decision on which mode barebox is targeted at out of Kconfig and into the PBL. PBL code can call either barebox_riscv_supervisor_entry or barebox_riscv_machine_entry to signal to barebox proper which mode it's running in. Currently the only user of this information is the RISC-V timer clocksource driver. Any new code that does IS_ENABLED(CONFIG_RISCV_SBI) or IS_ENABLED(CONFIG_RISCV_M_MODE) should also be adapted to use riscv_mode(). Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: virt: select only one timerAhmad Fatoum2021-06-211-1/+0
| | | | | | | | | S-Mode should use the riscv timer, so no need to select CLINT timer for virt. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: sifive: add HiFive board supportAhmad Fatoum2021-05-171-0/+19
| | | | | | | | | | | | | | | | | With the recently added SiFive support, we now have enough functionality to boot a HiFive board to shell: qemu-system-riscv64 -M sifive_u serial_stdio \ -kernel./images/barebox-hifive-unleashed.img Some more drivers need to be ported for this to be useful: - sifive,spi0 needed for talking to SD-Card - clocksource The riscv-timer seems to be 10x too fast Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210427202309.32077-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: erizo: drop mach-erizo directoryAhmad Fatoum2021-05-101-1/+1
| | | | | | | | With the recent changes, we can now delete mach-erizo. Do so. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210427202309.32077-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: erizo: restrict to RV32IAhmad Fatoum2021-05-031-1/+1
| | | | | | | | | | | Erizo is a RISC-V 32-bit softcore. Because ARCH_RV32I can be selected independently, a 64-bit barebox images could be built, but the image produced would be useless. Avoid this by not showing the SOC_ERIZO prompt when compiling for 64-bit. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210427202309.32077-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: support multi-image for all machinesAhmad Fatoum2021-05-031-0/+24
We already got rid of arch/riscv/mach-virt. Now do the same for arch/riscv/mach-erizo. This will enable us to build images for all RISC-V boards at once. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210427202309.32077-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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