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relocate_to_current_adr() will do a sync_caches_for_execution() after
concluding. The method used for icache synchronization depends on the
CPU being used. Allwinner D1 support added the assumption that any
code running in S-Mode will have populated sscratch with the flags
before calling riscv_vendor_id(). This is not the case for
barebox-dt-2nd, which does relocation before riscv_set_flags().
Quick fix this by calling riscv_set_flags manually.
Cc: Marco Felsch <m.felsch@pengutronix.de>
Fixes: c986c565b023 ("RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20230411071436.1630752-3-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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CONFIG_INITCALL_DEBUG can be very useful to debug early barebox hangs,
but it doesn't help when the hang happens just before. In this case,
enable the early barebox proper debug messages.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20221212164212.2358450-2-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We observed on ARM miscompilation because get_runtime_offset() was
cached before relocation, while address computation of symbol happened
after, effectively adding the base address twice to the symbol offset.
New runtime_address() hides origin of the symbol going into the address
calculation and thereby thwarts this optimization. Employ it in RISC-V
code as well to avoid such issues as experienced on ARM.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20221020131510.3734338-4-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Use the dedicated scratch register for setting the pbl flags. Each mode
has it's own scratch register so we are not conflicting with M-mode
running firmware e.g. OpenSBI. Using the scratch register has two main
advantages:
1st) It can be used in PBL and non-PBL use-case.
2nd) It is not affected by the relocation code.
This commit prepares barebox to add support for the special cache ops
used by several T-Head CPUs.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20221005111214.148844-4-m.felsch@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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While data = compressed_dtb + 1 has the equivalent effect of skipping
over the struct barebox_boarddata_compressed_dtb header, using a
flexible array member aids code readability, so use that instead.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220713095730.1878941-5-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The generic DT image for RISC-V mimics a kernel image and specifies
a load offset that it expects to be honoured. The stack should then
grow down from the load address. This didn't work as intended though
with riscv64-linux-gnu-gcc (Debian 10.2.1-6), because of the entry
point's __naked attribute: local variables overwrote the first bytes
of the entry point. Fix this by using a noinline nonnaked function.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210916093514.21267-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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After migrating to PBL we can't use nmon assembler macro
in C code anymore. Some changes are introduced to invoke
nmon from PBL C code:
* use 'lla' macro instruction instead of 'la';
* don't touch the 'ra' register, use 'a2' instead;
* add wrapper C function for nmon.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210708083035.40814-2-antonynpavlov@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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SiFive SoCs have separate I-Caches that require self-modifying code
like barebox' relocation and PBL extraction code to do cache
maintenance. Implement sync_caches_for_execution and use it where
appropriate.
The underlying fence.i primitive is part of the Zifencei
(load/store fence) ISA extension. As we can't be sure it's always
available, the exception handler will skip over the instruction
if the CPU trips over it. Alternatively, if CONFIG_HAS_CACHE=n,
the instruction won't be emitted at all.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210619045055.779-12-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add S- and M-Mode support for dumping registers when catching unexpected
CPU exceptions. Load access faults when data_abort_mask is active will
be skipped over. This allows outputting xxx when doing md /dev/mem for
non-accessible space.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210619045055.779-11-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Unlike other architectures we support, Linux must apparently be
booted on all cores by the bootloader. To achieve this, the bootloaders
running on the multiple cores synchronize via IPIs.
We will get there eventually, but for now, let's restrict barebox
to boot Linux on a single core. S-Mode firmware is passed hart (core) id
in a0. This is propagated via the thread pointer register, which is
unused by GCC and made available as:
- cpuinfo output when running in S-Mode
- $global.hartid
- a0 when booting via bootm
- /chosen/boot-hartid fixup: will come in handy when we gain EFI
loading support
- single /cpus/*/reg: All other CPU nodes are deleted via fixup
For M-Mode, we can query hart id via CSR. It's unknown whether erizo
supports it and we don't yet have exception support to handle it not
being available, so changes are only done for S-Mode for now.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210619045055.779-6-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We can't currently mix S-Mode and M-Mode images in the same build
and there's no straight-forward way to determine which mode we are in.
Move the decision on which mode barebox is targeted at out of Kconfig
and into the PBL. PBL code can call either barebox_riscv_supervisor_entry
or barebox_riscv_machine_entry to signal to barebox proper which mode
it's running in. Currently the only user of this information is the
RISC-V timer clocksource driver.
Any new code that does IS_ENABLED(CONFIG_RISCV_SBI) or
IS_ENABLED(CONFIG_RISCV_M_MODE) should also be adapted to use riscv_mode().
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210619045055.779-4-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Virt machine has a ns16550a UART at address 0x10000000. As we reuse
the generic DT image for this platform, we can't use either DEBUG_LL or
pbl_console as we would need to hardcode information on what UART is
available where, which wouldn't be correct for other boards.
However, if we parse the board compatible, we could match it with the
appropriate PBL console implementation without sacrificing portability.
Do so.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20210410110638.2106658-3-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Like on ARM, the PBL common code does not relocate the piggy data and
instead keeps pointers into the old image's location.
For relocate_to_current_adr, this doesn't matter, because both
destination and source address are the same, but when running from ROM
or flash relocate_to_adr will only copy up to __bss_start, so
determining the piggy data bounds _must_ happen before relocation.
We did so, but input_data_len, which references the image end was
executed after relocation unearthing two bugs at once:
- The compiler cached input_data_end from before relocation, so
the runtime offset wasn't being added
- Even with runtime offset added, we were pointing at the new
address, but the old piggy data wasn't copied there (On erizo,
it's still in ROM)
Fix these by evaluating the bounds before relocation and add a comment,
why it needs to be there. The same comment will also be added at the
code's origin in the ARM architecture support.
Reported-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.pengutronix.de/20210403070332.3642879-1-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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RISC-V PBL code currently reserves the last 2M of the memory for
firmware and places the stack before that. This serves virt, as qemu
places the FDT here, but negatively impacts normal targets with embedded
device tree as it increases fragmentation.
Add code to the generic DT entry point that cuts of a number of MiB from
the end of RAM, so the PBL arrives at a stack top that doesn't overlap
FDT.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This barebox image implements the same header as Linux and receives
the device tree in the same register. It can be booted from barebox
or loaded by Qemu -kernel option.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Given that we only support a single RISC-V board, this puts us in
a good position to make this a multi-image-only architecture.
This commit adds the necessary bits. It's highly inspired by the ARM PBL
support. Notable difference is that for relocations to be generated, it
was necessary to compile with -fpic. The relocation code assumes the
relocation entries to preprocessed. This is done at build-time by
means of the prelink-riscv script imported from U-Boot.
Actual migration to -fpic and prelinking is done along with porting
erizo in a follow-up commit.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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In preparation for migrating to PBL for RISC-V platforms, move the only
existing board support to a new arch/riscv/boards/ directory.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The different architectures duplicate some code around unflattening and
registering the device tree. Add common functions to reduce this
duplication.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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nmon is a tiny (<1024 bytes) monitor program
for the RV32I processors.
It can operate with NO working RAM at all!
It uses only the processor registers and NS16550-compatible
UART port for operation, so it can be used for a memory
controller setup code debugging.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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