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* ARM: zynqmp: add update handlerMichael Tretter2021-06-253-0/+70
| | | | | | | | | | | | The ZynqMP boots from an SDHCI device by reading a boot.bin file from the FAT16/32 partition, which is the first partition in the MBR. The update handler copies a boot.bin image to this partition, which might be board specific. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-5-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* dts: zcu104: add Barebox environmentMichael Tretter2021-06-251-0/+10
| | | | | | | | | | Use the same partition on the SD-card that is used by the ROM loader to find the BOOT.BIN (which contains the FSBL and Barebox) to store the Barebox environment. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-4-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zynqmp: set reset sourceMichael Tretter2021-06-252-0/+73
| | | | | | | | | | | | The reset reason is available in the APB register set on the ZynqMP. Read the reset reason and set the reset source accordingly. There might be multiple bits set in the APB register. Use the MSB for determining the actual reset source. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-2-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/testing'Sascha Hauer2021-06-161-0/+2
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| * openrisc: set default KBUILD_IMAGEAhmad Fatoum2021-06-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | For non-multi-image configuration, KBUILD_IMAGE is taken as the image to install. It was so far not set for openRISC. Define it, so it can be used by the make install stage, e.g. to collect artifacts after a CI run. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210604084704.17410-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/rockchip'Sascha Hauer2021-06-1616-124/+76
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| * | ARM: rockchip: radxa-rock: build defaultenvSascha Hauer2021-06-027-0/+4
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Rockchip: Merge defconfig filesSascha Hauer2021-06-022-100/+3
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: rockchip: Allow to build for multiple SoCsSascha Hauer2021-06-027-24/+69
| |/ | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/overlapping-memory-banks'Sascha Hauer2021-06-1612-62/+49
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| * | ARM: report probe error at arm_add_mem_device() callsites on failureAhmad Fatoum2021-06-024-37/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Failure to add one memory bank shouldn't prevent the driver from trying to add other memory banks, but the user should be informed as this points at a misconfiguration. Have the probe functions eventually fail with -EBUSY in such a case. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210531071239.30653-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: <asm/memory.h>: propagate error codes from arm_add_mem_device()Ahmad Fatoum2021-06-021-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox_add_memory_bank() can fail if the to-be-added memory region has been requested before. This can happen most easily on i.MX and STM32MP1 boards: - The /memory node in the device tree requests a region - The DDR controller driver requests an overlapping region after reading back RAM configuration. This most often leads to error messages down the road, but it can be difficult to pinpoint the cause. Propagate the error code from arm_add_mem_device(), so DDR controller drivers can fail their probe on error. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210531071239.30653-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | of: warn about of_add_memory_bank errorsAhmad Fatoum2021-06-021-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that errors from of_probe are propagated to the respective initcalls registering the device tree, propagate of_add_memory_bank errors as well. This ensures that clashes of device-tree added regions with previous ones don't go unnoticed. This can e.g. be the case if a device tree happens to have both /memory@X { }; and /memory { }; nodes. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210531071239.30653-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | of: propagate errors inside barebox_register_{of, fdt} into initcallsAhmad Fatoum2021-06-027-19/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errors during device tree registration, while uncommon, are really annoying, because the system may limp along and it's not clear where the misbehavior originates from. Failing the initcall of the device tree would improve user experience in that error case. There is intentionally no early exit on error cases to give barebox a chance to probe the serial driver to actually report errors when DEBUG_LL is disabled. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210531071239.30653-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/mmc'Sascha Hauer2021-06-161-0/+2
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| * | | ARM: zynqmp: defconfig: enable MCI_ARASANMichael Tretter2021-06-161-0/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | The ZynqMP has an arasan SD controller. Enable it in the respective defconfig. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210616073957.1872965-6-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2021-06-1649-417/+2914
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| * | | ARM: dts: protonic: define state partitionOleksij Rempel2021-06-091-1/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define one common state partition for all Protonic related boards Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.barebox.org/20210607121354.31183-1-o.rempel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: imx_v8_defconfig: enable EHCILucas Stach2021-05-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX8MM USB host controller uses the standard EHCI interface. Enable support in the defconfig to make this work out of the box. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.barebox.org/20210528133041.1109923-4-l.stach@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: imx_v8_defconfig: enable PRT8MM boardLucas Stach2021-05-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.barebox.org/20210528133041.1109923-3-l.stach@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: protonic: add initial support for the Protonic PRT8MM family of boardsDavid Jander2021-05-3112-0/+2483
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is a low-cost 7" touchscreen virtual terminal for agricultural applications. There is no upstream Linux DT yet, so we add a minimal DT for use with the bootloader in this patch. Signed-off-by: David Jander <david@protonic.nl> [lst: fixed and cleaned up for upstream] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.barebox.org/20210528133041.1109923-2-l.stach@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: sabresd: Add support for i.MX6QP board variantSascha Hauer2021-05-266-3/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SabreSD comes with different SoC variants. This patch adds support for the i.MX6QP based board. the DCD data has been taken from U-Boot 2021.04 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210415140313.29161-1-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210526064249.25378-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: Update sabresdb dcd data from U-BootSascha Hauer2021-05-261-91/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DCD data for the SabreSD board goes back to 2013. This updates the DCD data with the values from U-Boot-2021.04 which are likely better maintained. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: webasto-ccbv2: Add variant with 512MB RAMHolger Assmann2021-05-253-2/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add variant for 512MB RAM board. Two firmware files will be generated - one for 256MB and 512MB respectively; the choice for shipment has to be done and depends on the underlying hardware. Signed-off-by: Holger Assmann <h.assmann@pengutronix.de> v4 ARM: webasto-ccbv2: Add variant with 512MB RAM Link: https://lore.barebox.org/20210521144313.14990-1-h.assmann@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | arm: imx: Replace license and copyright boilerplate by SPDX identifiersUwe Kleine-König2021-05-2527-320/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Converts the files that licensecheck can determine to be licensed under GPL-2.0-only or GPL-2.0-or-later and also convert their copyright statements to SPDX. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.barebox.org/20210522143431.824057-1-u.kleine-koenig@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/compiler-warnings'Sascha Hauer2021-06-168-17/+18
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| * | | | powerpc: law: use signed type to allow error checkingSascha Hauer2021-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unsigned idx is checked for >= 0 which is always true and < 0 which is never true. Use a signed type instead. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210517185424.32145-16-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: module: Remove always false checkSascha Hauer2021-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rel->r_offset < 0 is always false because r_offset is unsigned. Remove check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210517185424.32145-13-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: phytec-phycard-omap3: Fix checking of unsigned variable being negativeSascha Hauer2021-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'char' can be unsigned, make it signed explicitly to let the check for being smaller than 0 work.. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210517185424.32145-11-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: layerscape: Fix wrong error checkSascha Hauer2021-05-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The return value of get_fman_port_icid() is assigned to an unsigned variable which is then error checked for being smaller than 0. Convert the variable to a signed type to make this work. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210517185424.32145-10-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX bbu-external-nand: Do not modify imageSascha Hauer2021-05-181-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct bbu_data::image is const, so do not modify the image, but create a copy instead. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210517185424.32145-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: xload-gpmi: Fix compiler warningSascha Hauer2021-05-181-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'pdesc' is a pointer casted to a 32bit value. This rightfully issues a compiler warning when being compiled with a 64bit toolchain. This code is compiled on 64bit systems, but the hardware won't be used there. Just silence the warning by casting the pointer to unsigned long. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210517185424.32145-6-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: socfpga: Fix timeout testsSascha Hauer2021-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A timeout is never detected as timeout is tested for being smaller than 0 which never happens for an unsigned variable. Change to a signed type. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210517185424.32145-3-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | arm: friendlyarm-tiny210: Remove dead codeSascha Hauer2021-05-181-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pin_usage[] is an empty array, no need to iterate over it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210517185424.32145-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | Merge branch 'for-next/arm'Sascha Hauer2021-06-1619-1/+1939
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| * | | | ARM: beaglebone: init MPU speed to 800MhzMarc Reilly2021-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sets the core processor speed to 800Mhz (from 500). Doing this helps speed the boot up a bit until the CPU freq govenor takes over. Signed-off-by: Marc Reilly <marc@cpdesign.com.au> Link: https://lore.barebox.org/20210613222639.13190-4-marc@cpdesign.com.au Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: am33xx: add define for 800Mhz MPU PLL pointMarc Reilly2021-06-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Reilly <marc@cpdesign.com.au> Link: https://lore.barebox.org/20210613222639.13190-3-marc@cpdesign.com.au Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: SoCFPGA: add Terasic DE10-Nano board supportGwenhael Goavec-Merou2021-06-0217-0/+1937
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Terasic DE10-Nano board is based on CycloneV SoCFPGA (5CSEBA6) with What has been tested to work: - SD card - Gigabit network - FPGA (FPPx16 & FPPx32) Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com> Link: https://lore.barebox.org/20210531194019.951-1-gwenj@trabucayre.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / | | ARM: at91: xload-mmc: fix typo in sama5d3_atmci_start_image()Oleksij Rempel2021-06-021-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | Use SAMA5D3_ID_PIOD instead of SAMA5D2_ID_PIOD Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.barebox.org/20210601084233.7948-1-o.rempel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | / ARM: i.MX: nitrogen6x: delete wrong memory node from dtsSascha Hauer2021-05-251-0/+2
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | The nitrogen6x comes in different memory configurations. Remove the hardcoded 1G memory node from the upstream device tree. This fixes booting the 2G variants which otherwise complain with: CRITICAL: mmu: Critical Error: Can't request SDRAM region for ttb at 8ffe4000 Reported-by: Michael Olbrich <m.olbrich@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Michael Olbrich <m.olbrich@pengutronix.de> Link: https://lore.barebox.org/20210525055007.9207-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: protonic: vicut1: disable on-die termination to fix PHY bootstrappingOleksij Rempel2021-05-251-1/+0
|/ | | | | | | | | | | | | | | | | | | If on-die termination is enabled, the RXC pin of iMX6 will be pulled high. Since we already have an 10K pull-down on board, the RXC level on PHY reset will be ~800mV, which is mostly interpreted as 1. On some reboots we get 0 instead and kernel can't detect the PHY properly. Since the default 0x020e07ac value is 0, it is sufficient to remove this entry from the affected imxcfg files. Since we get stable 0 on pin PHYADDR[2], the PHY address is changed from 4 to 0. Reported-by: Robin van der Gracht <robin@protonic.nl> Fixes: 00adc1e33ef8 ("ARM: add imx6 based Protonic boads") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.barebox.org/20210518083707.15428-1-o.rempel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/x86'Sascha Hauer2021-05-176-1/+59
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| * watchdog: add support for Intel TCO watchdog timerAhmad Fatoum2021-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Variants of the iTCO are integrated into many Intel southbridges. They are most often accessed via PCI. Add a driver for the variant found in the q35 QEMU machine. It should be straight forward to extend the itco_chipset_info array to support more variants in future as the need arises. To test, use: qemu-system-x86_64 -M q35 -global ICH9-LPC.noreboot=false The last option corresponds to a pin strap option, which can't be influenced from within the VM. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20210416062436.332665-5-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * pci: add EFI PCI root bridge IO protocol driverAhmad Fatoum2021-05-032-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UEFI specifies two protocols for abstracting both the PCI host bus controller and for PCI devices. The protocol for PCI devices provides function pointers for accessing IO Port, Memory and PCI configuration space, among others. The protocol for bus controllers provides the ability to read the root bridge's PCI configuration space and to query resources. In barebox, we would want to reuse existing PCI drivers unmodified, so we utilize the root bridge protocol, unlike most other EFI payloads. We still utilize the PCI (device) IO protocol, but not for core functionality: EFI has already enumerated the bus for us and allocated the EFI handles. It thus makes sense to have the new pci device have the EFI handle as parent and the controller as grand parent instead of being sibling with the EFI handles. This is done with an early PCI fixup that patches the device's parent pointer after consulting the PCI IO GetLocation. Driver is written from scratch and hasn't seen heavy usage yet, so it should be used with care. It was written while consulting the UEFI 2.1D specification. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20210416062436.332665-4-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: support PCI BIOS preassigned busesAhmad Fatoum2021-05-032-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running under UEFI, barebox should no redo PCI enumeration, because the UEFI implementation will likely already have drivers that won't cope with e.g. BAR addresses changing. The user-visible effect of this is that likely the framebuffer will stop working because the UEFI driver won't be able to access it any longer. Support this configuration by changing the PCI code to consult the new pcibios_assign_all_busses(). When it's true, there is no change to previous behavior. When it's false, reconfiguration is omitted and instead current configuration is read back from the bus. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20210416062436.332665-3-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * x86: add DMA supportAhmad Fatoum2021-05-032-1/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both interconnect and PCI are cache coherent on x86, so we shouldn't need any special CPU barriers for DMA. Indeed, Linux defined neither ARCH_HAS_SYNC_DMA_FOR_CPU nor ARCH_HAS_SYNC_DMA_FOR_DEVICE on x86. It thus seems that the only reordering we need to take care of is compiler-induced reordering. The Linux memory model that barebox adheres to as well demands that all accesses to shared data are volatile. volatile accesses are already guarnateed to not be reordered against each other, so we don't even need an explicit barrier(), which is already the case on other architectures that have a disabled MMU. Cc: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20210416062436.332665-2-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/riscv'Sascha Hauer2021-05-1729-208/+525
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| * | RISC-V: add Linux kernel boot supportAhmad Fatoum2021-05-172-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel RISC-V header has the same structure as on ARM64. The barebox header for the architecture also follows the same structure. Add the architecture-specific glue for barebox to be able to boot both RISC-V Linux and barebox. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210504104513.2640-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: asm: barebox-riscv-head: use load-offset of 0Ahmad Fatoum2021-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Incoming RISC-V bootm implementation will use the same bootm handler for booting both kernel and barebox. For this to work, the load offset in the header needs to make sense. As non-generic DT barebox images have enough knowledge about the platform to know where to place the stack, they don't require a load offset, thus set it to zero. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210504104513.2640-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | bootm: move ARM64 Linux image parsing to common directoryAhmad Fatoum2021-05-171-69/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux on RISC-V adopts the same structure as on ARM64 for both 32- and 64-bit kernel images and it's likely future architectures will as well. In preparation for adding RISC-V Linux boot support, move the bulk of the code to a common location for reusability. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210504104513.2640-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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