summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
* ARM: i.MX: fix compilation with BBU disabledSascha Hauer2018-08-081-1/+1
| | | | | | Make a static inline wrapper actually static inline. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mmu: fix cache flushing when replacing a section with a PTELucas Stach2018-07-271-45/+32
| | | | | | | | | | | | | | When replacing a section with a PTE, we must make sure that the newly initialized PTE entries are flushed from the cache before changing the entry in the TTB. Otherwise a L1 TLB miss causes the hardware pagetable walker to walk into a PTE with undefined content, causing exactly that behaviour. Move all the necessary cache flushing to arm_create_pte(), to avoid any caller getting this wrong in the future. Fixes: e3e54c644180 (ARM: mmu: Implement on-demand PTE allocation) Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* i.MX: iomuxv3: restore NO_PAD_CTRL semanticAlexander Kurz2018-07-131-3/+5
| | | | | | | | | | | | | A NO_PAD_CTRL flag used to keep a pad configuration untouched. With commit 094820a63bfd ("i.MX: iomuxv3: Use helper functions in iomux-v3.h") the NO_PAD_CTRL semantic changed to set a pad configurations to zero, which breaks non-DT boards, where NO_PAD_CTRL is freqently used to keep a boot-up default pad configuration, which often is non zero. Restore the old semantic, dont write PAD_CTRL when NO_PAD_CTRL is set. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MMU: fix arch_remap_range() across section boundariesSascha Hauer2018-07-121-1/+1
| | | | | | | | | | | Fixes: e3e54c6441 ARM: mmu: Implement on-demand PTE allocation PGD_FLAGS_WC_V7 lacks the PMD_TYPE_SECT and PMD_SECT_BUFFERABLE flags. Without them a dma_alloc_writecombine() creates an invalid section when it crosses a section boundary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
* Merge branch 'for-next/vfxxx'Sascha Hauer2018-07-098-498/+468
|\
| * VFxxx: DCD: Remove read leveling and gate training delaysAndrey Smirnov2018-06-133-45/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read leveling delays are being specified as zero, so they are as good as disabled and can be safely dropped. Gate training delay is specified as 4/128 tCK for both data slices. This setting, when applied to Data Byte 1, makes that slice unusable* during POR startup which is somehow is mitigated by double-reset hack in DCD. Dropping gate training delays allows both VF610 Tower board and ZII VF610 Dev board to sucessfully PoR-boot without the need for double resetting of the DDRMC. * The board fails to boot. When examined via JTAG in such a state only even bytes of DDR memory are functional. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: DCD: Remove CR97, CR98 and CR99Andrey Smirnov2018-06-131-3/+0
| | | | | | | | | | | | | | | | | | There's no point enabling write leveling DQS adjustement, while setting offsets for both slices to zero. This code is effectively a no-op, so drop it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: DCD: Drop initialization of CR139 - CR148Andrey Smirnov2018-06-131-8/+0
| | | | | | | | | | | | | | | | | | | | All of those registers contain paramters applicable only to write leveling, gate training and read leveling procedures. They should have no effect on normal mode of operations, so remove them from the common settings file. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: DCD: Remove CR151 initializationAndrey Smirnov2018-06-131-1/+0
| | | | | | | | | | | | | | | | CR151 contains parameters specific to HW gate training and read leveling which are not an officially supported featre of the HW. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: Reconcile shared DDR IOMUX DCD with schematicAndrey Smirnov2018-06-131-19/+19
| | | | | | | | | | | | | | | | | | The only differential signals coming out of DDRMC to the memory chip are CLK, DQS0 and DQS1. There rest of the pins are not, so there should be no reason to configure them as such. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: Initialize IOMUXC_DUMMY_DDRBYTE1/2 in default DDR DCDAndrey Smirnov2018-06-132-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although upstream U-Boot does not initialize this register in vf610-twr code (it does so in code for Phytec's PCM052) multiple revisions of VFxxx Controller Reference Manual state: 5.2.6.1 DUMMY PADS (DDR/QuadSPI) There are two dummy pads that are useful for timing calibration of DDR. These pads are internal only, but there corresponding IOMUX register need to be programmed for correct operation of DDR. These registers are: * IOMUXC_DUMMY_DDRBYTE1 (0x400482DC) * IOMUXC_DUMMY_DDRBYTE2 (0x400482E0) DDR: Dummy pads for DDR must be configured before any DDR I/O transactions are done. These pads simulate the input delay of the I/O buffers from the DRAM devices and DDR configures the delays accordingly. Although current DCD works as is, add writes for those registers for the sake of completness. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: zii-vf610-dev: Drop most custom DDRMC DCD codeAndrey Smirnov2018-06-131-8/+0
| | | | | | | | | | | | | | | | | | Both zii-vf610-dev and vf610-twr boards have same DDR layout. Since provenance of those custom settings is unclear, drop them in favor of what vf610-twr board does. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: Reconcile shared DDR DCD with memory datasheetAndrey Smirnov2018-06-132-5/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the settings for VFxxx boards appear to be in violation of the parameters specified by DDR chip's datasheet, so fix the code to reconcile the differences. The changes are: In vf610-ddr-cr-default.imxcfg: - CR31: t_XSDLL is 468, should be 512 - CR161 t_ODTH8 (R & W) is 2, should be 6 In flash-header-zii-vf610-dev.imxcfg: - CR12: WRLAT is 5, CL is 3,should be 5 and 6 - CR13: t_RC is 6, should be 21 - CR14: use default, more conservative t_FAW of 20 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: Reconcile shared DDR DCD configuration with U-BootAndrey Smirnov2018-06-132-6/+3
| | | | | | | | | | | | | | | | | | | | U-Boot was originally used as a source of DCD for VFxxx, so update our settings against latest upstream (sha1: b8aa55cb6414e512cce30bb7db3268eea934466d) to reconcile the differences. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: Add common DCD header for common DDR configurationAndrey Smirnov2018-06-134-164/+196
| | | | | | | | | | | | | | | | | | A number of VFxxx boards copy DDR layout/design of vf610-twr board and they all share DDR settings. Move those settings to a common file to avoid code duplication. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: Add common header for DDR clock setting DCDAndrey Smirnov2018-06-133-77/+48
| | | | | | | | | | | | | | | | | | | | VFxxx support code in Barebox is written assuming a particular clock setup in mind and all of the supported boards use it. Move the DCD code responsible for that setup to a shared file to avoid code duplication. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: Add common DDR PHY DCD headerAndrey Smirnov2018-06-134-50/+70
| | | | | | | | | | | | | | | | | | A number of VFxxx boards copy DDR layout/design of vf610-twr board and they all share DDR PHY settings. Move those settings to a common file to avoid code duplication. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: Add common header for DDR IOMUX DCD configurationAndrey Smirnov2018-06-134-100/+119
| | | | | | | | | | | | | | | | | | A number of VFxxx boards copy DDR layout/design of vf610-twr board and they all share IOMUX settings. Move those settings to a common file to avoid code duplication. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * VFxxx: Remove stale code from DCD filesAndrey Smirnov2018-06-132-71/+0
| | | | | | | | | | | | | | | | | | Remove various bits of debug code, commented DCD commands and separators as a small clean-up in preparation for commits that would follow. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/riscv'Sascha Hauer2018-07-096-120/+3
|\ \
| * | MIPS: Use generic GCC library routines from lib/Antony Pavlov2018-06-296-120/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a port of Linux kernel commit | commit 740129b36faf049e6845819144542a0455e1e285 | Author: Antony Pavlov <antonynpavlov@gmail.com> | Date: Wed Apr 11 08:50:19 2018 +0100 | | MIPS: Use generic GCC library routines from lib/ Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/misc'Sascha Hauer2018-07-094-1/+81
|\ \ \
| * | | mvebu: create bbu handler for kwb images and use it on cuboxUwe Kleine-König2018-06-134-1/+81
| | |/ | |/| | | | | | | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/mips'Sascha Hauer2018-07-0914-31/+160
|\ \ \
| * | | MIPS: don't include generated header files into MIPS asm filesAntony Pavlov2018-07-021-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch came out of discussions in the 'MIPS parallel build breakage' e-mail thread: http://lists.infradead.org/pipermail/barebox/2018-March/032251.html Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: dts: fix dtc unit_address_vs_reg warningAntony Pavlov2018-06-255-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unit number is added to the /memory nodes to fix this dtc warning: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: dts: drop skeleton.dtsiAntony Pavlov2018-06-258-23/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on feedback from Sascha: http://lists.infradead.org/pipermail/barebox/2018-April/032694.html " skeleton.dtsi should no longer be used " Several reasons to remove skeleton.dtsi are explained in the linux commit 3ebee5a2e141 ("arm64: dts: kill skeleton.dtsi"). Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: dts: dpt-module: add Atheros ART partitionOleksij Rempel2018-06-141-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | and define it as source of MAC address for ag71xx driver Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: dts: tl_wdr4300: add Atheros ART partitionOleksij Rempel2018-06-141-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | and define it as source of MAC address for ag71xx driver Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: ath79: provide driver for Atheros ART partitionOleksij Rempel2018-06-142-0/+113
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | this partition contains calibration data for WiFi and some board specific data, like MAC address. For now we care only about MAC. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/kill-oftree-f'Sascha Hauer2018-07-094-5/+18
|\ \ \ | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | Documentation: explain new way to boot using ATAGsSascha Hauer2018-06-113-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | oftree -f is gone and now global.bootm.boot_atag must be set to true if boot using ATAGs is desired. Update the documentation accordingly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: bootm: Add option boot using ATAGsSascha Hauer2018-06-111-5/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we can only force legacy boot using ATAGs by executing 'oftree -f'. Said command is going away as often this command is not safe to call. Add an alternative way using the global.bootm.boot_atag environment variable. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/imx8mq'Sascha Hauer2018-07-0917-0/+2144
|\ \ \ \
| * | | | ARM: Introduce imx_v8_defconfigAndrey Smirnov2018-06-151-0/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to imx_v7_defconfig, add imx_v8_defconfig as a default configuration encompassing all ARMv8 based i.MX SoCs. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX8: Add i.MX8mq EVK supportSascha Hauer2018-06-1512-0/+1862
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Specify HAVE_PBL_IMAGE for CPU_64Andrey Smirnov2018-06-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX8: Add DDRC PHY support codeAndrey Smirnov2018-06-153-0/+174
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DDRC PHY support code needed to upload DDR training firwmare as well as to wait for the training process to complete. Those are needed to support board specific DDR initialization code. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/imx'Sascha Hauer2018-07-0923-358/+646
|\ \ \ \
| * | | | ARM: dts: rdu2: Make use of "zii,eeprom-name"Andrey Smirnov2018-07-051-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert RAVE SP EEPROMs to use "zii,eeprom-name" instead of aliases in order to minimize differences with upstream Linux DT. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: dts: rdu1: Make use of "zii,eeprom-name"Andrey Smirnov2018-07-051-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert RAVE SP EEPROMs to use "zii,eeprom-name" instead of aliases in order to minimize differences with upstream Linux DT. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: dts: rdu1: Add node for backlight deviceAndrey Smirnov2018-07-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: dts: rdu1: Specify "boot-source" NVMEM cellAndrey Smirnov2018-07-021-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: dts: rdu1: Add nodes for RAVE SP EEPROMAndrey Smirnov2018-07-021-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: Add support for ZII RDU1 boardAndrey Smirnov2018-07-029-0/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ZII RDU1 is a i.MX51 based, Babbagde board derivative supported by upstream kernel. This commit add support for it to Barebox. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: babbage: Make PMIC initialization shareableAndrey Smirnov2018-07-026-115/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some board designs copy i.MX51 Babbadge board's PMIC design and so require exactly the same initialization. Move correspoding code into a separate file so it can be shared. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: bbu: support partitions starting at i.MX headerSascha Hauer2018-07-022-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX header is at an offset in the boot device, usually 0x400 bytes. This patch adds a flag to support the case that the partition the image is written to starts at that offset rather than 0x0. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: bbu: reimplement IMX_INTERNAL_FLAG_KEEP_DOSPART flagSascha Hauer2018-07-022-45/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reimplements the IMX_INTERNAL_FLAG_KEEP_DOSPART flag and makes it more generic. Until now we only kept a dos partition table over the update. Beginning with i.MX8 we may also want to preserve a GPT, so we have to extend the preserved area. It might also be the case that not (only) a partition table is stored in the initial area of a device, but also other unrelated data, so it's better to just keep the initial area that is unused by the i.MX ROM. It's also good to export the flag to allow boards to specify the initial area shall be preserved. When a board wants to set the flag for a mtd like device then it has to check for suitable erase sizes beforehand. We do not check this (yet). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: bbu: remove handler specific flags variableSascha Hauer2018-07-021-18/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we can store flags in the generic handler flags we no longer need our own variable. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: rdu2: Fetch MAC address info from RAVE SP EEPROMAndrey Smirnov2018-06-292-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RDU2 stores MAC addresses for its Ethernet interfaces in main RAVE SP EEPROM. Add code to properly integrate it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-26 18:05:08 +0000