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| * | | | | ARM: mmu: Make sure DMA coherent memory is zeroed outAndrey Smirnov2019-01-214-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to avoid passing random/junky values to DMA/HW as well as to allow simplifying memory initialization in individual drivers, change dma_alloc_coherent() to guarantee that memory it returns is properly zeroed out. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: mmu: Share code for arm_mmu_not_initialized_error()Andrey Smirnov2019-01-213-22/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: mmu: Share sanity checking code in mmu_init()Andrey Smirnov2019-01-214-30/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Share sanity checking code in mmu_init() as well as code to detect if MMU is on or not on both ARM and ARM64. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: mmu: Share code for dma_sync_single_for_cpu()Andrey Smirnov2019-01-213-14/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both ARM and ARM64 have identical code for dma_sync_single_for_cpu(). Move it to mmu-common.c so it can be shared. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: mmu: Share code for dma_alloc_coherent()Andrey Smirnov2019-01-216-39/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both ARM and ARM64 implement almost identical algorithms in dma_alloc_coherent(). Move the code to mmu-common.c, so it can be shared. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM64: mmu: Invalidate memory before remapping as DMA coherentAndrey Smirnov2019-01-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although there are known problems caused by this, it seems prudent to invalidate the region of memory we are about remap as uncached. Additionaliy this matches how dma_alloc_coherent() is implemented on ARM. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: mmu: Share code for dma_free_coherent()Andrey Smirnov2019-01-213-16/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that AArch64 version is calling arch_remap_range() it is identical to ARM version in mmu.c. Move the definition to mmu-common.c to avoid duplication. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM64: mmu: Merge create_sections() and map_region() togetherAndrey Smirnov2019-01-211-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since map_region() is never called without being followed by tlb_invalidate(), merge it with create_sections() to simplify the code. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM64: mmu: Use arch_remap_range() internallyAndrey Smirnov2019-01-211-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of calling map_region() explicitly, call arch_regmap_range() instead to simplify the code. This also ensures that tlb_invalidate() gets called when dma_free_coherent() is invoked. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: mmu: Share code for dma_(un)map_single()Andrey Smirnov2019-01-214-33/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both ARM and ARM64 define DMA mapping/unmapping functions that are exactly the same. Introduce mmu-common.c and move the code there so it can be shared. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: mmu: Simplify the use of dma_inv_range()Andrey Smirnov2019-01-211-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the use of dma_inv_range() by changing its signature to accept pointer to start of the data and data size. This change allows us to avoid a whole bunch of repetitive arithmetic currently done by all of the callers. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: mmu: Drop custom virt_to_phys/phys_to_virtAndrey Smirnov2019-01-213-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neither ARM nor ARM64 define any address mapping functions that differ from default provided for no-MMU configuration. Drop all the extra code and just rely on functions provided in asm/io.h Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARN: boards: Remove duplicate includesAlexander Shiyan2019-01-2110-13/+0
| | |/ / / | |/| | | | | | | | | | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | Merge branch 'for-next/arm'Sascha Hauer2019-02-1319-42/+13
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| * | | | | ARM: zynqmp: select macb driverThomas Haemmerle2019-01-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | macb supports Xilinx ZynqMP GEM, so select HAS_MACB by default. Signed-off-by: Thomas Haemmerle <thomas.haemmerle1988@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: zii-vf610-dev: boot initrd from SDVivien Didelot2019-01-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As for tftp, make use of the initramfs if one is present on the SD card. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: zii-vf610-dev: fix boot from SDVivien Didelot2019-01-243-19/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 5f99a8d40305 ("dts: VFxxx: Add aliases for ESDHC controllers"), the SD card slot has a consistent name across all ZII Dev platforms, including CFU1. They all use mmc1 instead of mci0 or mci1. This allows us to completely drop the init scripts from the default ZII VF610 Dev environment, and fix the boot/sd script. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: zynq: fix "'IO_SPACE_LIMIT' redefined" warningAntony Pavlov2019-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes the following compiler's warning: In file included from include/common.h:33:0, from arch/arm/mach-zynq/zynq.c:18: arch/arm/include/asm/io.h:4:0: warning: "IO_SPACE_LIMIT" redefined #define IO_SPACE_LIMIT 0 In file included from arch/arm/mach-zynq/zynq.c:17:0: include/asm-generic/io.h:92:0: note: this is the location of the previous definition #define IO_SPACE_LIMIT 0xffff Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARN: boards: Remove duplicate includesAlexander Shiyan2019-01-1810-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARN: Remove duplicate includesAlexander Shiyan2019-01-183-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: Makefile: Drop unnecessary imxcfg-y settingsSascha Hauer2019-01-161-3/+0
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For boards built with multiimage support imxcfg-y is not needed. Remove it for these boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | Revert "images: Drop unnecessary fix_size"Sascha Hauer2019-02-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5c0e16591d9471a345b77a41fde76de34f301f6b. The fix_size scripts is not necessary for newer ARM toolchains, it is however necessary for the older ARM toolchains (gcc-5 and older). The original reason to drop fix_size was that it doesn't work on MIPS. With this patch we add the -i flag so that we ignore unknown images and can succesfully build MIPS images. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | arm: dts: am335x-phytec: Use phy-handle instead of phy_idTeresa Remmet2019-02-133-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update am335x-phytec som device trees and use phy-handle instead of phy_id. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | arm: mach-omap: am335x_generic: Enable nodes by alias where neededTeresa Remmet2019-02-131-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the interconnet target module hierarchy the node names used to enable boot devices are not unique any more. Find those nodes by alias now. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | arm: configs: am33xx_mlo_defconfig: Enable ti-sysc bus driverTeresa Remmet2019-02-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | arm: configs: omap_defconfig: Enable ti-sysc bus driverTeresa Remmet2019-02-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | ARM: rpi: avoid NULL dereference on unknown rev.Tomaz Solc2019-02-121-1/+4
| |/ / / |/| | | | | | | | | | | | | | | | | | | | | | | "model" pointer is NULL if current board revision isn't in the list of known boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | ARM: aarch64: Avoid relocations in runtime-offset.SAndrey Smirnov2019-02-011-1/+13
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since get_runtime_offset() is executed as a part of reloaction logic, it cannot have code dependend on any kind of relocation. Unfortunately, current codebase violates this rule and linkadr: .quad get_runtime_offset ends up producing R_AARCH64_RELATIVE relocation that has to be resolved at runtime. From tiral and error experimentation it seems that the simplest way to do this is to drop "a" (allocatable) attribute fom the section directive in runtime-offset.S With "a" (see first entry): aarch64-linux-gnu-objdump -R images/start_zii_imx8mq_dev.pbl images/start_zii_imx8mq_dev.pbl: file format elf64-littleaarch64 DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE 00000000000000b0 R_AARCH64_RELATIVE *ABS*+0x00000000000000a0 0000000000004258 R_AARCH64_RELATIVE *ABS*+0x0000000000028118 0000000000004260 R_AARCH64_RELATIVE *ABS*+0x0000000000028128 00000000000042e0 R_AARCH64_RELATIVE *ABS* 00000000000042e8 R_AARCH64_RELATIVE *ABS*+0x0000000000028118 00000000000042f0 R_AARCH64_RELATIVE *ABS*+0x00000000000042c8 Without "a": aarch64-linux-gnu-objdump -R images/start_zii_imx8mq_dev.pbl images/start_zii_imx8mq_dev.pbl: file format elf64-littleaarch64 DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE 0000000000004258 R_AARCH64_RELATIVE *ABS*+0x0000000000028100 0000000000004260 R_AARCH64_RELATIVE *ABS*+0x0000000000028110 00000000000042e0 R_AARCH64_RELATIVE *ABS* 00000000000042e8 R_AARCH64_RELATIVE *ABS*+0x0000000000028100 00000000000042f0 R_AARCH64_RELATIVE *ABS*+0x00000000000042c8 Note that on recent toolchains (tested on 8.1.1), this problem is masked by the fact that .quad get_runtime_offset will be initialized with link-time value of "get_runtime_offset" in addition to having a R_AARCH64_RELATIVE relocation. 00000000000000a0 <get_runtime_offset>: a0: 10000000 adr x0, a0 <get_runtime_offset> a4: 58000061 ldr x1, b0 <linkadr> a8: eb010000 subs x0, x0, x1 ac: d65f03c0 ret 00000000000000b0 <linkadr>: b0: 000000a0 .word 0x000000a0 b4: 00000000 .word 0x00000000 _However_, older toolchains (tested on 5.5.0), will only issue a R_AARCH64_RELATIVE, so memory location will contain only zeroes: 00000000000000a0 <get_runtime_offset>: a0: 10000000 adr x0, a0 <get_runtime_offset> a4: 58000061 ldr x1, b0 <linkadr> a8: eb010000 subs x0, x0, x1 ac: d65f03c0 ret 00000000000000b0 <linkadr>: ... This leads to an very early crash and complete boot failure in the latter case. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | MIPS: malta: Typo fixAlexander Shiyan2019-01-211-1/+1
|/ / | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | images: Drop unnecessary fix_sizeSascha Hauer2019-01-161-1/+1
| | | | | | | | | | | | | | | | Now that we compile the compressed binary into the decompressor we no longer need fix_size but can use the linker to fill in the image size into the binary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: imx8mq: Add back memory controller nodeLucas Stach2019-01-162-2/+3
|/ | | | | | | | This was lost during conversion to use upstream device tree. Fixes: 29841dfa4b ("ARM: imx8mq: use upstream devicetree") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/ultrascale'Sascha Hauer2019-01-1514-0/+184
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| * zynqmp: enable macb Ethernet supportThomas Hämmerle2019-01-091-0/+1
| | | | | | | | | | Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: add support for Xilinx ZCU104 boardMichael Tretter2018-12-1012-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP) and the Xilinx ZCU104 board. Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL) already took care of initializing the RAM. Also for debug_ll, the UART is expected to be already setup correctly. Thus, you have to add the Barebox binary to a boot image as described in "Chapter 11: Boot and Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual". Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: aarch64: add ENTRY_PROC macro for arm64Michael Tretter2018-12-101-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | arm64 has no __naked__ attribute and the compiler adds a function prologue for saving x29 and x30 to the stack for all C functions. This includes functions defined using the ENTRY_FUNCTION macro. Therefore, the stack needs to be setup before entering a C function, which is not possible if the entry is a C function. Provide a macro to implement the entry in assembly to be able to setup the stack before entering the low level entry function. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: aarch64: compile with general-regs-onlyMichael Tretter2018-12-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Without this flag, gcc generates code to save the Q/V registers to the stack for handling the va_list in pr_print(). Saving the registers is useless, as the registers are never restored, but accessing the registers to save them hangs the CPU. Follow the Linux arch/arm64/Makefile and use the general-regs-only flag to prevent usage of floating point and Advanced SIMD register. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: lib64: .gitignore barebox.ldsMichael Tretter2018-12-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e1287b1a8b27 ("arm: rework lib directory to support arm64") restructured the lib directory and added the lib64 directory. It moved the existing .gitignore to the lib32 directory but didn't add a new .gitignore for lib64. Thus building Barebox for arm64 results in stray barebox.lds files. Copy the .gitignore from lib32 to lib64. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/risc-V'Sascha Hauer2019-01-1535-0/+1215
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| * | RISC-V: add erizo_generic_defconfigAntony Pavlov2019-01-071-0/+51
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: erizo: add nmon image creationAntony Pavlov2019-01-071-0/+11
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: erizo: enable nmonAntony Pavlov2019-01-071-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: erizo: add DEBUG_LL supportAntony Pavlov2019-01-072-0/+34
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: add nmon nano-monitorAntony Pavlov2019-01-073-0/+266
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nmon is a tiny (<1024 bytes) monitor program for the RV32I processors. It can operate with NO working RAM at all! It uses only the processor registers and NS16550-compatible UART port for operation, so it can be used for a memory controller setup code debugging. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: add low-level debug macros for ns16550Antony Pavlov2019-01-071-0/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds macros for ns16550 port initialization and single char output. The macros can be used in MIPS asm pbl code. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: add Erizo SoC supportAntony Pavlov2019-01-077-0/+89
| | | | | | | | | | | | | | | | | | | | | Erizo is an opensource hardware SoC for FPGA. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | Add initial RISC-V architecture supportAntony Pavlov2019-01-0727-0/+581
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/nvstore'Sascha Hauer2019-01-151-6/+0
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| * | | ARM: i.MX6 dtsi: remove compatible for snvs_lpgpr nodeSascha Hauer2018-12-071-6/+0
| | |/ | |/| | | | | | | | | | | | | | | | This is already in the upstream dtsi file, so we no longer need it in the barebox dtsi file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/mtd'Sascha Hauer2019-01-151-0/+2
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| * | | mtd: atmel_nand: Add per board ECC setupLadislav Michl2018-12-141-0/+2
| | |/ | |/| | | | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>