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* PCI: layerscape: Allow to share stream_ids per host controllerSascha Hauer2020-01-201-41/+89
| | | | | | | | | | | | | | | | | | Normally every device gets its own stream_id. The stream_ids are communicated to the kernel in the device tree and are also configured in the controllers LUT table. This only works when all PCI devices are known in the bootloader which may not always be the case. For example, when a PCI device is a FPGA and its firmware is only loaded under Linux, then the device is not known to barebox and thus not assigned a stream_id. With global.layerscape_pcie.share_stream_ids set to true all devices on a host controller get the same stream_id assigned. This setup is completely device agnostic and thus also works when not all devices are known to barebox. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: layerscape: Fixup iommu-map propertiesSascha Hauer2020-01-141-1/+38
| | | | | | The iommu-map properties are needed for proper PCI support under Linux. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: layerscape: rename variableSascha Hauer2020-01-141-8/+8
| | | | | | | Rename 'arr' to 'msi_map' which is a better name when we add another array in the next patch. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: copy over some Linux PCI helpersAhmad Fatoum2019-12-091-0/+26
| | | | | | | | Linux PCI drivers, like the incoming 8250_pci, make use of these helpers. Port them over from Linux v5.4. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: Add layerscape PCIe driverSascha Hauer2019-11-273-0/+492
| | | | | | | | This adds support for the designware based PCIe controller found on Layerscape SoCs. The driver is based on Linux-5.4. The device tree fixups have been taken from U-Boot 2019.10. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Return directly when num-lanes is not foundSascha Hauer2019-11-271-2/+4
| | | | | | | | | | | | | | | | | Port of Linux commit 66de33f09fd97201847de7e1e2ec8a117242e1d6 The num-lanes is optional since it is not needed on some platforms that bring up the link in firmware. The link programming is based on the num-lanes properties (which is optional); if it is not present code must return instead of fiddling with the lanes value to print an error message. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Sync register definitions with Linux-5.4Sascha Hauer2019-11-271-34/+51
| | | | | | | Update the dwc register definitions with Linux-5.4 to make further syncinf with the Linux driver easier. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: rename readl/writel_dbi ops to read/write_dbiSascha Hauer2019-11-272-12/+12
| | | | | | | | struct dw_pcie_ops read/writel_dbi functions can read values of any size, so with readl/writel they are misnamed. Rename them to read/write which also matches the kernel driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Cleanup DBI,ATU read and write APIsSascha Hauer2019-11-272-17/+43
| | | | | | | | | | | | | | | | | | | | Port of Linux commit 7bc082d7e97009f252bd432de5d476b0bcf3b266 Cleanup DBI read and write APIs by removing leading "__" (underscore) from their names as there is no reason to have leading underscores in the first place in the function definition. Remove dbi/dbi2 base address parameters as the same behaviour can be obtained through read and write APIs. Since dw_pcie_{readl/writel}_dbi() APIs can't be used for ATU read/write as ATU base address could be different from DBI base address, implement ATU read/write APIs using ATU base address without using dw_pcie_{readl/writel}_dbi() APIs. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: imx6: Share PHY debug register definitionsSascha Hauer2019-11-273-9/+14
| | | | | | | | | | | | | | | | | | | | | Port of Linux commit 60ef4b072ba089440531287f72740d94ed1e8dd1 Both pcie-designware.c and pci-imx6.c contain custom definitions for PHY debug registers R0/R1 and on top of that there's already a definition for R0 in pcie-designware.h. Move all of the definitions to pcie-designware.h. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Fix ATU identification for designware version >= 4.80Sascha Hauer2019-11-272-6/+9
| | | | | | | | | | | | | | | | | | | | | Port of Linux commit 2aadcb0cd39198833fabe1c45084f78686e71a6c Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which have not populated the version member, the old method of identification will still be used. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Enable iATU unroll for endpoint tooSascha Hauer2019-11-272-19/+19
| | | | | | | | | | | | | | | Port of Linux commit a9f4c2d2f99ec85ebc734a5bfb21a2cf93c169ad iatu_unroll_enabled flag is set only for Designware in host mode. However iATU unroll can be applicable for endpoint mode too. Set iatu_unroll_enabled flag in dw_pcie_setup() which is common for both host mode and endpoint mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Make use of BIT() in constant definitionsSascha Hauer2019-11-272-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Port of Linux commit 0e11faa48b07a063289d65363015a3d51ca4c337 Avoid using explicit left shifts and convert various definitions to use BIT() instead. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [lorenzo.pieralisi@arm.com: fixed PORT_LOGIC_SPEED_CHANGE redefinition] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Add dw_pcie_disable_atu()Sascha Hauer2019-11-272-0/+28
| | | | | | | This adds dw_pcie_disable_atu() taken from Linux-5.4. This is needed by the upcoming Layerscape driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Make use of IS_ALIGNED()Sascha Hauer2019-11-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Port of Linux commit 4f8bbd2f8e7c4f3112506bf7362aed3a5495d51b Make the intent a bit more clear as well as get rid of explicit arithmetic by using IS_ALIGNED() to determine if "addr" is aligned to "size". No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Don't hard-code DBI/ATU offsetSascha Hauer2019-11-273-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of Linux commit 6d6b05e3d5337f645a411cdf72f1a083e495acb8 The DWC PCIe core contains various separate register spaces: DBI, DBI2, ATU, DMA, etc. The relationship between the addresses of these register spaces is entirely determined by the implementation of the IP block, not by the IP block design itself. Hence, the DWC driver must not make assumptions that one register space can be accessed at a fixed offset from any other register space. To avoid such assumptions, introduce an explicit/separate register pointer for the ATU register space. In particular, the current assumption is not valid for NVIDIA's T194 SoC. The ATU register space is only used on systems that require unrolled ATU access. This property is detected at run-time for host controllers, and when this is detected, this patch provides a default value for atu_base that matches the previous assumption re: register layout. An alternative would be to update all drivers for HW that requires unrolled access to explicitly set atu_base. However, it's hard to tell which drivers would require atu_base to be set. The unrolled property is not detected for endpoint systems, and so any endpoint driver that requires unrolled access must explicitly set the iatu_unroll_enabled flag (none do at present), and so a check is added to require the driver to also set atu_base while at it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Acked-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2019-03-071-1/+1
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| * PCI: dwc: tune down link up messagesLucas Stach2019-03-071-1/+1
| | | | | | | | | | | | | | | | | | This function may be called repeatedly while establishing the link, so printing a message each time a working link is found can add quite a bit of noise. Tune those messages down to the debug level. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQAndrey Smirnov2019-02-271-0/+16
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 29d6b80bc36be62ae38ed8ac3f7a426975fe7dfa The PCIe IP block has an additional clock, "pcie_aux", that needs to be controlled by the driver. Add code to support it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/pci'Sascha Hauer2019-02-135-114/+74
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| * PCI: Consify pci_ops in struct pci_controllerAndrey Smirnov2019-01-163-4/+4
| | | | | | | | | | | | Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Convert ->res_start() to return resource_size_tAndrey Smirnov2019-01-161-2/+4
| | | | | | | | | | | | | | | | | | | | On 64-bit machines int doesn't cover full address space, so convert .res_start to both accept resource_size_t as a parameter and return it as result. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Assume 1:1 mapping if .res_start callback is NULLAndrey Smirnov2019-01-163-13/+5
| | | | | | | | | | | | | | | | | | | | Save a bit of no-op boilerplate by converting pci_iomap() to treat absense of .res_start callback as an indicator that 1:1 mapping is being used. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Simplify alloc_pci_dev()Andrey Smirnov2019-01-161-7/+1
| | | | | | | | | | | | | | | | Use xzalloc() to allocate PCI device and drop OOM checking code. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Drop "rom_address" from struct pci_devAndrey Smirnov2019-01-161-7/+0
| | | | | | | | | | | | | | | | This field is not being used in Barebox. Drop it. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Drop "ops" from struct pci_busAndrey Smirnov2019-01-162-5/+3
| | | | | | | | | | | | | | | | | | Drop "ops" from struct pci_bus, since the same struct can be accessed via host->pci_ops. No functional change intended. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Drop "resources" from struct pci_busAndrey Smirnov2019-01-161-1/+0
| | | | | | | | | | | | | | | | | | This field is not used by Barebox. Remove it. No functional change intended. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Drop "slots" from struct pci_busAndrey Smirnov2019-01-161-1/+0
| | | | | | | | | | | | | | | | | | This field is not used by Barebox. Remove it. No functional change intended. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Make pci_scan_bus staticAndrey Smirnov2019-01-161-1/+3
| | | | | | | | | | | | | | | | | | Pci_scan_bus is not used anyhwere outside pci.c. Mark in static to reflect that. No functional change intended. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Remove unused variables/codeAndrey Smirnov2019-01-161-5/+0
| | | | | | | | | | | | | | | | | | Both host_head and host_tail are not used anywhere in the codebase and look like a leftover. Remove them. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Store and reuse BAR offsetsAndrey Smirnov2019-01-161-8/+8
| | | | | | | | | | | | | | | | | | Save and reuse BAR offsets in dedicated constants instead of repeating the same expression multiple times. No functional change intended. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Simplify resource setup code in setup_device()Andrey Smirnov2019-01-161-57/+43
| | | | | | | | | | | | | | | | | | | | Simplify resource setup code in setup_device() by factoring out all of the common code and moving it outside the if main if statement. No functional change intended. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Remove superfluous parens in setup_device()Andrey Smirnov2019-01-161-1/+1
| | | | | | | | | | | | | | | | | | Remove superfluous parens in setup_device(). No functional change intended. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Replace magic number in setup_device()Andrey Smirnov2019-01-161-1/+1
| | | | | | | | | | | | | | | | | | User PCI_BASE_ADDRESS_SPACE_IO instead of explicit magic number. No functional change intended. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * PCI: Switch to using %pa to print memory addressesAndrey Smirnov2019-01-161-8/+8
| | | | | | | | | | | | | | | | | | Switch to using %pa to print memory addresses in order to be able to support both 64 and 32 bit builds. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2019-02-131-1/+1
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| * | treewide: Remove trailing whitespaces and tabsAlexander Shiyan2019-01-211-1/+1
| |/ | | | | | | | | | | | | Just a cleanup over barebox tree Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Add support for i.MX8MQAndrey Smirnov2019-02-112-10/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 2d8ed461dbc9bc734185db92d2b9d1bb7b586b30 Add code needed to support i.MX8MQ variant. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flagAndrey Smirnov2019-02-111-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 4c458bb347ae016e75f6c61dab95ce530f4ff6fc Both i.MX7D and i.MX8MQ have the same behaviour when it comes to clearing DIRECT_SPEED_CHANGE bit when no speed change occurs, so to handle variants correctly add a flag instead of checking the IP block variant. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [lorenzo.pieralisi@arm.com: updated log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Mark PHY functions as i.MX6 specificAndrey Smirnov2019-02-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 2f532d07f0cce72f88a4a0532ae11be6a2745697 PCIe PHY IP block on i.MX7D differs from the one used on i.MX6 family, so none of the code in the current implementation of imx6_setup_phy_mpll() or imx6_pcie_reset_phy() is applicable. Introduce IMX6_PCIE_FLAG_IMX6_PHY and check for it in the aforementioned functions to make sure they are only executed on appropriate PCIe IP variants. Tested-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [lorenzo.pieralisi@arm.com: updated log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Introduce drvdataAndrey Smirnov2019-02-111-14/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit e8e4d4e95701a10691c53165c55789e5e50ba3f5 Introduce driver data struct. This will simplify handling of device specific differences. Signed-off-by: Stefan Agner <stefan@agner.ch> [andrew.smirnov@gmail.com reformatted drvdata, to simplify future diffs] Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: dwc: Fix pointer width cast problemAndrey Smirnov2019-02-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | Casting to u32 works well on 32-bit builds, but causes problem when compiled on 64-bit machines. Switch it to cast to "unsigned long", so that it would have appropriate width in both cases. While at it, replace explicit casts to void * with IOMEM. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Port imx6_pcie_ltssm_enable()Andrey Smirnov2019-01-181-9/+18
| | | | | | | | | | | | | | Port imx6_pcie_ltssm_enable() from Linux kernel driver. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Drop unnecessary root_bus_nr settingAndrey Smirnov2019-01-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 39f712e989c5e591c58b65b62981b85027ba3103 Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Fix spelling mistake: "contol" -> "control"Andrey Smirnov2019-01-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 7221547e55b7929e4d46983f6f3ca15f36ee4dac Trivial fix to spelling mistake in dev_err message Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <hongxing.Zhu@nxp.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Do not switch speed if Gen2 is disabledAndrey Smirnov2019-01-181-27/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 93b226f9c65a951a91617f87ba1f05f14e59f26f Save a bit of time and avoid going through link speed change procedure in configuration where link max speed is limited to Gen1 in DT. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Do not wait for speed change on i.MX7Andrey Smirnov2019-01-181-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit e6dcd87fff69a9d454104b65569074855cf95b1e As can be seen from [1]: "...the different behavior between iMX6Q PCIe and iMX7D PCIe maybe caused by the different controller version. Regarding to the DOC description, the DIRECT_SPEED_CHANGE should be cleared after the speed change from GEN1 to GEN2. Unfortunately, when GEN1 device is used, the behavior is not documented. So, IC design guys run the simulation and find out the following behaviors: 1. DIRECT_SPEED_CHANGE will be cleared in 7D after speed change from GEN1 to GEN2. This matches doc’s description 2. set MAX link speed(PCIE_CAP_TARGET_LINK_SPEED=0x01) as GEN1 and re-run the simulation, DIRECT_SPEED_CHANGE will not be cleared; remain as 1, this matches your result, but function test is passed, so this bit should not affect the normal PCIe function." imx6_pcie_wait_for_speed_change() will report false failures for Gen1 -> Gen1 speed transition, so avoid doing that check and just rely on imx6_pcie_wait_for_link() only. [1] https://community.nxp.com/message/867943 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Allow probe deferral by reset GPIOAndrey Smirnov2019-01-181-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit bde4a5a00e761f55be92f62378cf5024ced79ee3 Some designs implement reset GPIO via a GPIO expander connected to a peripheral bus. One such example would be i.MX7 Sabre board where said GPIO is provided by SPI shift register connected to a bitbanged SPI bus. To support such designs, allow reset GPIO request to defer probing of the driver. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PCI: imx6: Add code to support i.MX7DAndrey Smirnov2019-01-182-46/+124
|/ | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 9b3fe6796d7c0e0c2b87243ce0c7f4744c54efad Add various bits of code needed to support i.MX7D variant of the IP. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Cc: yurovsky@gmail.com Cc: Mark Rutland <mark.rutland@arm.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Constify dw_pcie_host_ops structuresAndrey Smirnov2019-01-082-2/+2
| | | | | | | | | | | | | | | Port of a Linux commit 4ab2e7c0df6b8bbc6c8ea1617b737d33c2510012 The dw_pcie_host_ops structures are never modified. Constify these structures such that these can be write-protected. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-15 23:19:55 +0000