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The reset controller driver enables the necessary clocks before resetting,
so it makes no sense to build the driver without clock support.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20220816052823.3680080-1-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Import the Linux v5.13 state of the SCMI reset protocol driver.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220220124736.3052502-14-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We will gut the STM32 reset controller parts in a follow-up commit,
because that will be handled together with clocking in a single RCC
driver. This will leave only restart and reset reason support in the
driver, so move it to drivers/power/reset, so it's not out-of-place.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220220124736.3052502-11-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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RCC reset will eventually get more involved when we add SCMI support.
Linux already has reset and clock control in the same driver.
As we now have a simple driver that can toggle resets on the STM32 MCUs
as well, we can drop the now duplicate support from the dedicated
STM32 reset driver.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220131075338.1869305-2-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Incoming STM32 MCU support will leverage this driver, so port it over
from Linux v5.16.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220131075338.1869305-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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"GPL-2.0-only" was introduced in SPDX 2.0, and the old identifier
"GPL-2.0" is now considered deprecated; see <https://spdx.org/licenses>.
Fixes: 28f4a6a4df76f0f1581d (2021-10-30, "drivers: add missing SPDX-License-Identifier")
Signed-off-by: Roland Hieber <rhi@pengutronix.de>
Link: https://lore.barebox.org/20211117113851.2022669-2-rhi@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds the suitable SPDX-License-Identifier to all files in drivers/
that previously lacked one.
To aid manual inspection, following heuristics can be used:
* No changes outside of comments/whitespace:
git show -U0 HEAD | rg -v '^(@@|diff|index)|[-+]([-+]|//|#|[\s/]\*)'
* -or-later come in pairs:
git show --inter-hunk-context=19 HEAD | \
perl -0777 -F'/^@/gm' -ne 'for (@F) { @m = /later/g; print if @m & 1 }'
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20211030175632.2276077-4-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The StarFive SoC has a single reset controller, which seems to control
reset of all clocks and peripherals. It differs from the ones supported
by the Linux reset-simple driver in that it has a dedicated status
registers that needs to be polled to verify the reset has completed.
Also special is that most resets (> 70) are synchronous. As the reset
status poll would just time out without the clock, have the reset
controller enable the clock as part of the reset. OS can decide later,
which clocks to disable again.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210619045055.779-24-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The i2c, MCI and reset controller peripherals are STM32-specific.
There is no reason to ask uses on oldconfig about it, thus make them
depend on ARCH_STM32MP || COMPILE_TEST.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We don't have a config SOC_IMX7D, but have an ARCH_IMX7. Fix this.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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On the STM32MP, reset of the I2C, SPI and USB IPs occurs over the RCC.
This driver adds support for the controller, so it may be reused by
other drivers.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Port of a Linux commit abf97755ae31aaaf35156438dd3036e96f66da83
Add reset controller driver exposing various reset faculties,
implemented by System Reset Controller IP block.
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Linux commit 26fce0557fa639fb7bbc33e31a57cff7df25c3a0 was squashed
here as well:
reset: imx7: Fix always writing bits as 0
Right now the only user of reset-imx7 is pci-imx6 and the
reset_control_assert and deassert calls on pciephy_reset don't toggle
the PCIEPHY_BTN and PCIEPHY_G_RST bits as expected. Fix this by writing
1 or 0 respectively.
The reference manual is not very clear regarding SRC_PCIEPHY_RCR but for
other registers like MIPIPHY and HSICPHY the bits are explicitly
documented as "1 means assert, 0 means deassert".
The values are still reversed for IMX7_RESET_PCIE_CTRL_APPS_EN.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add stripped sown version of the reset controller
framework from the Linux kernel.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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