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* Merge branch 'for-next/state'Sascha Hauer2015-12-082-61/+69
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| * state: disable load commandEnrico Jorns2015-11-271-1/+0
| | | | | | | | | | | | | | | | | | Explicitly loading environment is not required as it will be loaded if available during device probing Signed-off-by: Enrico Jorns <ejo@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * state: use name of device node as name if alias is not availableMarc Kleine-Budde2015-11-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | Wihtout this patch, when using more than one state device an alias is mandatory, otherwise the there will be two state devices with the name state. This patch fixes the limitation by using the device node's name if no alias is defined. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * state: make use of of_find_path_by_node() and add return -EPROBE_DEFER if ↵Marc Kleine-Budde2015-11-271-22/+9
| | | | | | | | | | | | | | | | device is not available Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * of_path: add of_find_path_by_node()Marc Kleine-Budde2015-11-271-1/+16
| | | | | | | | | | | | | | | | | | This patch adds the function of_find_path_by_node(), which is similar to of_find_path(), but it translates a device tree node into a barebox device path directly. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * of_path: of_find_path() factor out device detection logic into separate functionMarc Kleine-Budde2015-11-271-37/+44
| | | | | | | | | | | | | | | | This patch factors out the device detection logic into separate function, so that it can be used from another function. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/socfpga'Sascha Hauer2015-12-081-11/+35
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| * | firmware: socfpga: Add parameter "programmed" to fpgamgr driverTrent Piepho2015-11-111-11/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This boolean parameter tells you if the FPGA is programmed or not. It can be accessed from the shell as "$fpga.programmed". One could use this to not program the FPGA if it's already programmed. There is an annoying limitation of the way barebox puts parameters into the shell env: it requires they have no periods in the device name. It uses the first period to divide the variable name into a device and parameter name, which doesn't work correctly if the device name has a period in it. Since the names of any devices created from the OF device tree have a period in them, this is a problem. So what I did here was create a new device. Its parent will be the OF device for the fpgamgr and it will in turn be the parent of the firmware cdev. Previously the cdev's parent was the OF device. This device won't have period in the name and the parameter is attached to it. Even without the period limitation, doing this gives a nicer name "fpga.programmed" instead of "ff706000.fpgamgr.programmed". The fpgamgr code had a pointer to the OF device in its private state. I changed this to be a struct for the new "fpga" device, which is then used in all the places the former pointer was (nothing but dev_dbg, etc. calls). Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/reset'Sascha Hauer2015-12-081-4/+99
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| * | | reset: Add gpio reset supportSascha Hauer2015-11-231-1/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a device has the reset-gpios property we can support this through the reset controller API, so drivers do not have to open code the support for this property each time themselves as done a few dozen times in the kernel. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | reset: Allow dummy reset linesSascha Hauer2015-11-231-3/+20
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Treat NULL as a dummy reset line which is returned by the reset core when there is no reset line connected to a device (that is, no reset is described in the device tree). With this consumers can just use the reset functions without having to check for existence. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/omap'Sascha Hauer2015-12-083-0/+206
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| * | | driver: watchdog: Add support for omap_wdtTeresa Remmet2015-11-233-0/+206
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Add support for OMAP Watchdog driver. Based on omap_wdt Linux driver (v4.3-rc1). Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/net'Sascha Hauer2015-12-085-20/+49
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| * | | net: tap: fix whitespacesAntony Pavlov2015-12-041-3/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | net: tap: make locally used functions staticAntony Pavlov2015-12-041-5/+5
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | net: usb: asix: fix 'no previous prototype' warningAntony Pavlov2015-11-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Here is the warning message: drivers/net/usb/asix.c:427:5: warning: no previous prototype for 'asix_rx_fixup_internal' [-Wmissing-prototypes] int asix_rx_fixup_internal(struct usbnet *dev, void *buf, int len, ^ Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | net: usb: asix: make rx_fixup ax_skb buffer alignedAntony Pavlov2015-11-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ax_skb receive buffer unalignment leads to consequent unalignment data access in network stack routines, especially in net_checksum(). By-turn unalignment data accesses lead to performance penalty. Moreover on classic MIPS CPUs without hardware unalignment access support this leads to undesirable exceptions. At the moment barebox on MIPS can't parry these unalignment access exceptions, so the Asix USB Ethernet chips, that need receive fixup workaround, are completely unusable on MIPS without this patch. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | net: fec: fix indentation and whitspacesStefan Christ2015-11-191-4/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | net: fec: implement dtb property phy-reset-durationStefan Christ2015-11-191-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement device tree property phy-reset-duration to adjust length of phy reset. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | net: fec: set phy reset time to 1msStefan Christ2015-11-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the device tree bindings in dts/Bindings/net/fsl-fec.txt the default phy-reset time is 1ms. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | net: rtl8169: get rid of DMA_ADDRESS_BROKENLucas Stach2015-11-131-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't assume a 1:1 virt to phys mapping, but use the real physical address returned by the dma alloc function. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | net: designware: Don't hang in reset with powered down phyTrent Piepho2015-11-131-1/+24
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dw MAC requires that all clock domains to be running for it to finish a MAC reset. This include the clock provided by the PHY. If the PHY is powered down, bit BMCR_PDOWN set, then it won't be generating a clock. And so the MAC never comes out of reset. On shutdown, Linux will put the PHY in powerdown mode, so it can easily be the case that the PHY is powered down on boot. See Linux kernel commit 2d871aa07136fe6e576bde63072cf33e2c664e95. Currently the MAC reset is done before the phy is probed. We can't power up the phy until it's probed, so the resets must be in the opposite order. The MAC reset is in device init but the PHY probe is in device open. Device init is done first, always, while open is done later, and only if the device is used. Rather than move the phy probe to init, this moves the MAC reset to open. It seems better to speed up boots that doesn't use ethernet by skipping MAC reset than to slow them down by adding PHY probe. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/mtd'Sascha Hauer2015-12-083-17/+265
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| * | | mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08USebastian Hesselbarth2015-11-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds optimized timings for Samsung K9K8G08U 1Gb NAND flash. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XPSebastian Hesselbarth2015-11-232-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell PXA3xx and Armada 370/XP share the same NAND controller IP with some minor differences. With support for controller IP v2, now allow to build the driver on Armada 370/XP. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Add support for NDCB3 registerSebastian Hesselbarth2015-11-231-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer versions of PXA3xx NAND controller support a 4th Command Buffer register. Add the required HWFLAGS and additional write to NDCB0. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Add support for HW BCH ECCSebastian Hesselbarth2015-11-231-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for HW BCH ECC for those HW versions that support it. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECCSebastian Hesselbarth2015-11-231-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for 8bit HW ECC modes supported by later IP versions. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECCSebastian Hesselbarth2015-11-231-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for 4bit HW ECC modes supported by later IP versions. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versionsSebastian Hesselbarth2015-11-231-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell PXA3xx NAND flash controller IP has been reused in later SoCs with additional HW features. Add HW BCH ECC as the first known HW difference. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Prepare for different HW ECC strengthsSebastian Hesselbarth2015-11-231-7/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer versions of Marvell PXA3xx NFC also support BCH and therefore higher ECC strengths than 1. Prepare for different ECC strength by factoring out ECC init into separate functions by strength. Also, add a new host variable that indicates BCH ECC. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Get ecc parameters from DTSebastian Hesselbarth2015-11-231-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With DT helpers for ECC step size and strength, now use them on Marvell NAND driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Fix num-cs property parsingSebastian Hesselbarth2015-11-231-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "num-cs" property does not encode flashes CS line but number of available CS signals. Fix wrong property parsing to ->cs by adding proper ->num_cs variable to host struct. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Protect mrvl_nand_probe_dtSebastian Hesselbarth2015-11-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parsing DT nodes if CONFIG_OFTREE isn't enabled is pointless, also we should prefer potential platform_data passed earlier. Protect mrvl_nand_probe_dt by bailing out early if either CONFIG_OFTREE is not enabled or dev's platform_data is non-NULL. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Use Auto Read Status on program/eraseSebastian Hesselbarth2015-11-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell NAND controller allows to enable an Auto Read Status feature that will automatically monitor NAND status during Erase and Program operations. Ready bit in status register will be set after the controller is sure the NAND device has finished the operation and saves us from guessing the real timeout values. Using the Auto Read Status feature prevents timeout issues on the two operations with none or wrong timing register setup. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00Sebastian Hesselbarth2015-11-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If OOB data is not required on page program, we have to clear the corresponding data with 0xff instead of 0x00. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand_mrvl_nfc: Use common clock for core clockSebastian Hesselbarth2015-11-231-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With PXA3xx now providing a common clock for the NAND clock, use it and get rid of the mach/clock.h. This will allow Marvell Armada 370/XP to reuse the same driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: nand: Clarify Marvell Orion Kconfig promptSebastian Hesselbarth2015-11-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kconfig prompt for Marvell Orion SoCs is missing a "Marvell" prefix, add it to the prompt. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | of: mtd: Import of_get_nand_ecc_{step_size, strength} from LinuxSebastian Hesselbarth2015-11-231-0/+34
| |/ / | | | | | | | | | | | | | | | | | | | | | This imports DT helpers for MTD ECC step size and strength from Linux kernel. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/mmc'Sascha Hauer2015-12-082-31/+38
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| * | | mci: dw_mmc: Add support for high speed modesTrent Piepho2015-11-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Synopsys DesignWare core supports 52 MHz MMC mode and 50 MHz SD mode, so add the cap flags so they are used. This works on socfpga. The other user of this driver is Rockchip and the datasheet I found for the RK30xx indicated it supported highspeed modes as well. The Linux kernel has DT properties, e.g. "cap-mmc-highspeed", but none of the drivers in barebox support this at all. They all specify flags in their code. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mci: dw_mmc: Delete devname in platform_dataTrent Piepho2015-11-191-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nothing used it. Also delete the local mci alias pointer to host->mci in dw_mmc_probe(). It only saved a few characters and all the references but one are using host->mci. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mci: dw_mmc: socfpga: Supply bus-width in platform_dataTrent Piepho2015-11-191-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since there is no OF support in the xloader on socfpga it uses the platform_data system. There needs to be a way to supply the equivalent of the DT property bus-width this way to support devices that need to use a smaller bus. So that we don't need to put every flag that might get added to the MMC_CAP list into platform_data, just put the bus width ones into platform_data. The socfpga dts sources specify a bus-width of 4 so use that in the platform_data for socfpga. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mci: core: bus-width property should override driver defaultTrent Piepho2015-11-191-16/+22
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OF code for parsing bus-width would only add the specified width to those the driver might have already set capability flags for. Because of this, if the driver had set 8 or 4 bit width, it wasn't possible for the DT to specify that fewer pins were used on the board and a smaller width was necessary. Change this so the width in the DT overrides whatever widths the driver says it supports. There is no reason to have an incorrect device tree and it makes far more sense for the DT to override the driver default than for the driver default to override the DT. The widths the driver puts in host_caps before calling mci_of_parse() are considered the default if the DT doesn't specify bus-width. This should cause the least amount of change to existing boards, as despite a comment that no bus-width meant to use 1 bit, using the driver default is what was really happening. Unfortunately, half of existing drivers default to the largest width they support while the other half default to the smallest. Boards should just stick the width in the device tree. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/mips'Sascha Hauer2015-12-081-2/+2
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| * | | driver: make all dev_request_mem_region_* routines MIPS compatibleYegor Yefremov2015-12-011-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | Use IOMEM() macro in all dev_request_mem_region_* routines to allow the proper mapping on all platforms. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2015-12-083-6/+98
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| * | | spi: i.MX: optimize transfers for ECSPI v2.3Sascha Hauer2015-11-301-1/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of writing one word to the txfifo and then wait until one is received in the rxfifo we can write while the txfifos are not full and read as long the rxfifos contain data. This makes transfers for the m25p80 driver around 7 times faster here. Unlike the last version this time we only optimize the common case with 8 bits per word and SPI_LSB_FIRST cleared. The other cases would require more bit shuffling of the data. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | video: i.MX IPUv3: Set ldb clocks correctlySascha Hauer2015-11-301-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocks for the LVDS display bridge have a fixed /3.5 and a configurable /1,/2 divider in their path. The configurable divider has to be explicitly configured for single/dual channel support, so we can't rely on clock rate parent propagation here. Clear the CLK_SET_RATE_PARENT flag for the configurable divider and configure the clock explicitly in the ldb driver. Tested on a custom i.MX6 board, currently untested on i.MX53. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 13:59:52 +0000