207 files changed, 80796 insertions, 80857 deletions

diff --git a/kernelconfig b/kernelconfig
index 72894d1..e13436e 100644
--- a/kernelconfig
+++ b/kernelconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm 3.7.0-rc6 Kernel Configuration
+# Linux/arm 3.7.0-20121218 Kernel Configuration
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -1534,7 +1534,16 @@ CONFIG_LIBERTAS_DEBUG=y
 # CONFIG_P54_COMMON is not set
 # CONFIG_RT2X00 is not set
 # CONFIG_RTL8192CU is not set
-# CONFIG_WL_TI is not set
+CONFIG_WL_TI=y
+CONFIG_WL1251=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE=m
+CONFIG_WLCORE_SPI=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_WL12XX_PLATFORM_DATA=y
 # CONFIG_ZD1211RW is not set
 # CONFIG_MWIFIEX is not set
 
@@ -1649,7 +1658,7 @@ CONFIG_TOUCHSCREEN_WM9713=y
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_TOUCHSCREEN_TSC_SERIO is not set
 # CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_TOUCHSCREEN_TSC2007=m
 # CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_TOUCHSCREEN_ST1232 is not set
 # CONFIG_TOUCHSCREEN_TPS6507X is not set
@@ -1835,7 +1844,6 @@ CONFIG_PINMUX=y
 CONFIG_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
 CONFIG_PINCTRL_SINGLE=y
-# CONFIG_PINCTRL_SAMSUNG is not set
 # CONFIG_PINCTRL_EXYNOS4 is not set
 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
@@ -2711,6 +2719,8 @@ CONFIG_BACKLIGHT_LM3639=m
 # CONFIG_BACKLIGHT_LP855X is not set
 # CONFIG_BACKLIGHT_PANDORA is not set
 CONFIG_BACKLIGHT_TPS65217=y
+# CONFIG_BACKLIGHT_TLC59108 is not set
+CONFIG_NXP_TDA998X_OLD=y
 
 #
 # Console display driver support
@@ -3248,13 +3258,14 @@ CONFIG_DMA_VIRTUAL_CHANNELS=y
 #
 # DMA Clients
 #
-CONFIG_NET_DMA=y
+# CONFIG_NET_DMA is not set
 CONFIG_ASYNC_TX_DMA=y
 CONFIG_DMATEST=m
 # CONFIG_AUXDISPLAY is not set
 CONFIG_UIO=y
 CONFIG_UIO_PDRV=y
 CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_PRUSS=m
 CONFIG_VIRTIO=m
 
 #
diff --git a/patches/linux-3.2.16/0000-arago-beaglebone.patch b/patches/linux-3.2.16/0000-arago-beaglebone.patch
deleted file mode 100644
index 3c5ac3c..0000000
--- a/patches/linux-3.2.16/0000-arago-beaglebone.patch
+++ /dev/null
@@ -1,79756 +0,0 @@
-diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt
-index 771d48d..208a2d4 100644
---- a/Documentation/arm/memory.txt
-+++ b/Documentation/arm/memory.txt
-@@ -51,15 +51,14 @@ ffc00000	ffefffff	DMA memory mapping region.  Memory returned
- ff000000	ffbfffff	Reserved for future expansion of DMA
- 				mapping region.
- 
--VMALLOC_END	feffffff	Free for platform use, recommended.
--				VMALLOC_END must be aligned to a 2MB
--				boundary.
--
- VMALLOC_START	VMALLOC_END-1	vmalloc() / ioremap() space.
- 				Memory returned by vmalloc/ioremap will
- 				be dynamically placed in this region.
--				VMALLOC_START may be based upon the value
--				of the high_memory variable.
-+				Machine specific static mappings are also
-+				located here through iotable_init().
-+				VMALLOC_START is based upon the value
-+				of the high_memory variable, and VMALLOC_END
-+				is equal to 0xff000000.
- 
- PAGE_OFFSET	high_memory-1	Kernel direct-mapped RAM region.
- 				This maps the platforms RAM, and typically
-diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
-index 52916b4..9b4b82a 100644
---- a/Documentation/devicetree/bindings/arm/gic.txt
-+++ b/Documentation/devicetree/bindings/arm/gic.txt
-@@ -42,6 +42,10 @@ Optional
- - interrupts	: Interrupt source of the parent interrupt controller. Only
-   present on secondary GICs.
- 
-+- cpu-offset	: per-cpu offset within the distributor and cpu interface
-+  regions, used when the GIC doesn't have banked registers. The offset is
-+  cpu-offset * cpu-nr.
-+
- Example:
- 
- 	intc: interrupt-controller@fff11000 {
-diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt
-new file mode 100644
-index 0000000..266716b
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/vic.txt
-@@ -0,0 +1,29 @@
-+* ARM Vectored Interrupt Controller
-+
-+One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
-+system for interrupt routing.  For multiple controllers they can either be
-+nested or have the outputs wire-OR'd together.
-+
-+Required properties:
-+
-+- compatible : should be one of
-+	"arm,pl190-vic"
-+	"arm,pl192-vic"
-+- interrupt-controller : Identifies the node as an interrupt controller
-+- #interrupt-cells : The number of cells to define the interrupts.  Must be 1 as
-+  the VIC has no configuration options for interrupt sources.  The cell is a u32
-+  and defines the interrupt number.
-+- reg : The register bank for the VIC.
-+
-+Optional properties:
-+
-+- interrupts : Interrupt source for parent controllers if the VIC is nested.
-+
-+Example:
-+
-+	vic0: interrupt-controller@60000 {
-+		compatible = "arm,pl192-vic";
-+		interrupt-controller;
-+		#interrupt-cells = <1>;
-+		reg = <0x60000 0x1000>;
-+	};
-diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt
-new file mode 100644
-index 0000000..342eedd
---- /dev/null
-+++ b/Documentation/devicetree/bindings/serial/omap_serial.txt
-@@ -0,0 +1,10 @@
-+OMAP UART controller
-+
-+Required properties:
-+- compatible : should be "ti,omap2-uart" for OMAP2 controllers
-+- compatible : should be "ti,omap3-uart" for OMAP3 controllers
-+- compatible : should be "ti,omap4-uart" for OMAP4 controllers
-+- ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
-+
-+Optional properties:
-+- clock-frequency : frequency of the clock input to the UART
-diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
-index 3d84912..a7e4ac1 100644
---- a/Documentation/feature-removal-schedule.txt
-+++ b/Documentation/feature-removal-schedule.txt
-@@ -535,6 +535,20 @@ Why:    In 3.0, we can now autodetect internal 3G device and already have
- 	information log when acer-wmi initial.
- Who:    Lee, Chun-Yi <jlee@novell.com>
- 
-+---------------------------
-+
-+What:	/sys/devices/platform/_UDC_/udc/_UDC_/is_dualspeed file and
-+	is_dualspeed line in /sys/devices/platform/ci13xxx_*/udc/device file.
-+When:	3.8
-+Why:	The is_dualspeed file is superseded by maximum_speed in the same
-+	directory and is_dualspeed line in device file is superseded by
-+	max_speed line in the same file.
-+
-+	The maximum_speed/max_speed specifies maximum speed supported by UDC.
-+	To check if dualspeeed is supported, check if the value is >= 3.
-+	Various possible speeds are defined in <linux/usb/ch9.h>.
-+Who:	Michal Nazarewicz <mina86@mina86.com>
-+
- ----------------------------
- 
- What:	The XFS nodelaylog mount option
-diff --git a/Documentation/pwm.txt b/Documentation/pwm.txt
-new file mode 100644
-index 0000000..7112e66
---- /dev/null
-+++ b/Documentation/pwm.txt
-@@ -0,0 +1,259 @@
-+                       Generic PWM Device API
-+
-+                          February 1, 2010
-+                            Bill Gatliff
-+                        <bgat@billgatliff.com>
-+
-+
-+
-+The code in drivers/pwm and include/linux/pwm/ implements an API for
-+applications involving pulse-width-modulation signals.  This document
-+describes how the API implementation facilitates both PWM-generating
-+devices, and users of those devices.
-+
-+
-+
-+Motivation
-+
-+The primary goals for implementing the "generic PWM API" are to
-+consolidate the various PWM implementations within a consistent and
-+redundancy-reducing framework, and to facilitate the use of
-+hotpluggable PWM devices.
-+
-+Previous PWM-related implementations within the Linux kernel achieved
-+their consistency via cut-and-paste, but did not need to (and didn't)
-+facilitate more than one PWM-generating device within the system---
-+hotplug or otherwise.  The Generic PWM Device API might be most
-+appropriately viewed as an update to those implementations, rather
-+than a complete rewrite.
-+
-+
-+
-+Challenges
-+
-+One of the difficulties in implementing a generic PWM framework is the
-+fact that pulse-width-modulation applications involve real-world
-+signals, which often must be carefully managed to prevent destruction
-+of hardware that is linked to those signals.  A DC motor that
-+experiences a brief interruption in the PWM signal controlling it
-+might destructively overheat; it could suddenly change speed, losing
-+synchronization with a sensor; it could even suddenly change direction
-+or torque, breaking the mechanical device connected to it.
-+
-+(A generic PWM device framework is not directly responsible for
-+preventing the above scenarios: that responsibility lies with the
-+hardware designer, and the application and driver authors.  But it
-+must to the greatest extent possible make it easy to avoid such
-+problems).
-+
-+A generic PWM device framework must accommodate the substantial
-+differences between available PWM-generating hardware devices, without
-+becoming sub-optimal for any of them.
-+
-+Finally, a generic PWM device framework must be relatively
-+lightweight, computationally speaking.  Some PWM users demand
-+high-speed outputs, plus the ability to regulate those outputs
-+quickly.  A device framework must be able to "keep up" with such
-+hardware, while still leaving time to do real work.
-+
-+The Generic PWM Device API is an attempt to meet all of the above
-+requirements.  At its initial publication, the API was already in use
-+managing small DC motors, sensors and solenoids through a
-+custom-designed, optically-isolated H-bridge driver.
-+
-+
-+
-+Functional Overview
-+
-+The Generic PWM Device API framework is implemented in
-+include/linux/pwm/pwm.h and drivers/pwm/pwm.c.  The functions therein
-+use information from pwm_device, pwm_channel and pwm_channel_config
-+structures to invoke services in PWM peripheral device drivers.
-+Consult drivers/pwm/atmel-pwm.c for an example driver.
-+
-+There are two classes of adopters of the PWM framework:
-+
-+  "Users" -- those wishing to employ the API merely to produce PWM
-+  signals; once they have identified the appropriate physical output
-+  on the platform in question, they don't care about the details of
-+  the underlying hardware
-+
-+  "Driver authors" -- those wishing to bind devices that can generate
-+  PWM signals to the Generic PWM Device API, so that the services of
-+  those devices become available to users. Assuming the hardware can
-+  support the needs of a user, driver authors don't care about the
-+  details of the user's application
-+
-+Generally speaking, users will first invoke pwm_request() to obtain a
-+handle to a PWM device.  They will then pass that handle to functions
-+like pwm_duty_ns() and pwm_period_ns() to set the duty cycle and
-+period of the PWM signal, respectively.  They will also invoke
-+pwm_start() and pwm_stop() to turn the signal on and off.
-+
-+The Generic PWM API framework also provides a sysfs interface to PWM
-+devices, which is adequate for basic application needs and testing.
-+
-+Driver authors fill out a pwm_device structure, which describes the
-+capabilities of the PWM hardware being constructed--- including the
-+number of distinct output "channels" the peripheral offers.  They then
-+invoke pwm_register() (usually from within their device's probe()
-+handler) to make the PWM API aware of their device.  The framework
-+will call back to the methods described in the pwm_device structure as
-+users begin to configure and utilize the hardware.
-+
-+Note that PWM signals can be produced by a variety of peripherals,
-+beyond the true "PWM hardware" offered by many system-on-chip devices.
-+Other possibilities include timer/counters with compare-match
-+capabilities, carefully-programmed synchronous serial ports
-+(e.g. SPI), and GPIO pins driven by kernel interval timers.  With a
-+proper pwm_device structure, these devices and pseudo-devices can all
-+be accommodated by the Generic PWM Device API framework.
-+
-+
-+
-+Using the API to Generate PWM Signals -- Basic Functions for Users
-+
-+
-+pwm_request() -- Returns a pwm_channel pointer, which is subsequently
-+passed to the other user-related PWM functions.  Once requested, a PWM
-+channel is marked as in-use and subsequent requests prior to
-+pwm_free() will fail.
-+
-+The names used to refer to PWM devices are defined by driver authors.
-+Typically they are platform device bus identifiers, and this
-+convention is encouraged for consistency.
-+
-+
-+pwm_free() -- Marks a PWM channel as no longer in use.  The PWM device
-+is stopped before it is released by the API.
-+
-+
-+pwm_period_ns() -- Specifies the PWM signal's period, in nanoseconds.
-+
-+
-+pwm_duty_ns() -- Specifies the PWM signal's active duration, in nanoseconds.
-+
-+
-+pwm_duty_percent() -- Specifies the PWM signal's active duration, as a
-+percentage of the current period of the signal.  NOTE: this value is
-+not recalculated if the period of the signal is subsequently changed.
-+
-+
-+pwm_start(), pwm_stop() -- Turns the PWM signal on and off.  Except
-+where stated otherwise by a driver author, signals are stopped at the
-+end of the current period, at which time the output is set to its
-+inactive state.
-+
-+
-+pwm_polarity() -- Defines whether the PWM signal output's active
-+region is "1" or "0".  A 10% duty-cycle, polarity=1 signal will
-+conventionally be at 5V (or 3.3V, or 1000V, or whatever the platform
-+hardware does) for 10% of the period.  The same configuration of a
-+polarity=0 signal will be at 5V (or 3.3V, or ...) for 90% of the
-+period.
-+
-+
-+
-+Using the API to Generate PWM Signals -- Advanced Functions
-+
-+
-+pwm_config() -- Passes a pwm_channel_config structure to the
-+associated device driver.  This function is invoked by pwm_start(),
-+pwm_duty_ns(), etc. and is one of two main entry points to the PWM
-+driver for the hardware being used.  The configuration change is
-+guaranteed atomic if multiple configuration changes are specified.
-+This function might sleep, depending on what the device driver has to
-+do to satisfy the request.  All PWM device drivers must support this
-+entry point.
-+
-+
-+pwm_config_nosleep() -- Passes a pwm_channel_config structure to the
-+associated device driver.  If the driver must sleep in order to
-+implement the requested configuration change, -EWOULDBLOCK is
-+returned.  Users may call this function from interrupt handlers, for
-+example.  This is the other main entry point into the PWM hardware
-+driver, but not all device drivers support this entry point.
-+
-+
-+pwm_synchronize(), pwm_unsynchronize() -- "Synchronizes" two or more
-+PWM channels, if the underlying hardware permits.  (If it doesn't, the
-+framework facilitates emulating this capability but it is not yet
-+implemented).  Synchronized channels will start and stop
-+simultaneously when any single channel in the group is started or
-+stopped.  Use pwm_unsynchronize(..., NULL) to completely detach a
-+channel from any other synchronized channels.  By default, all PWM
-+channels are unsynchronized.
-+
-+
-+pwm_set_handler() -- Defines an end-of-period callback.  The indicated
-+function will be invoked in a worker thread at the end of each PWM
-+period, and can subsequently invoke pwm_config(), etc.  Must be used
-+with extreme care for high-speed PWM outputs.  Set the handler
-+function to NULL to un-set the handler.
-+
-+
-+
-+Implementing a PWM Device API Driver -- Functions for Driver Authors
-+
-+
-+Fill out the appropriate fields in a pwm_device structure, and submit
-+to pwm_register():
-+
-+
-+bus_id -- the plain-text name of the device.  Users will bind to a
-+channel on the device using this name plus the channel number.  For
-+example, the Atmel PWMC's bus_id is "atmel_pwmc", the same as used by
-+the platform device driver (recommended).  The first device registered
-+thereby receives bus_id "atmel_pwmc.0", which is what you put in
-+pwm_device.bus_id.  Channels are then named "atmel_pwmc.0:[0-3]".
-+(Hint: just use pdev->dev.bus_id in your probe() method).
-+
-+
-+nchan -- the number of distinct output channels provided by the device.
-+
-+
-+request -- (optional) Invoked each time a user requests a channel.
-+Use to turn on clocks, clean up register states, etc.  The framework
-+takes care of device locking/unlocking; you will see only successful
-+requests.
-+
-+
-+free -- (optional) Callback for each time a user relinquishes a
-+channel.  The framework will have already stopped, unsynchronized and
-+un-handled the channel.  Use to turn off clocks, etc. as necessary.
-+
-+
-+synchronize, unsynchronize -- (optional) Callbacks to
-+synchronize/unsynchronize channels.  Some devices provide this
-+capability in hardware; for others, it can be emulated (see
-+atmel_pwmc.c's sync_mask for an example).
-+
-+
-+set_callback -- (optional) Invoked when a user requests a handler.  If
-+the hardware supports an end-of-period interrupt, invoke the function
-+indicated during your interrupt handler.  The callback function itself
-+is always internal to the API, and does not map directly to the user's
-+callback function.
-+
-+
-+config -- Invoked to change the device configuration, always from a
-+sleep-capable context.  All the changes indicated must be performed
-+atomically, ideally synchronized to an end-of-period event (so that
-+you avoid short or long output pulses).  You may sleep, etc. as
-+necessary within this function.
-+
-+
-+config_nosleep -- (optional) Invoked to change device configuration
-+from within a context that is not allowed to sleep.  If you cannot
-+perform the requested configuration changes without sleeping, return
-+-EWOULDBLOCK.
-+
-+
-+
-+Acknowledgements
-+
-+
-+The author expresses his gratitude to the countless developers who
-+have reviewed and submitted feedback on the various versions of the
-+Generic PWM Device API code, and those who have submitted drivers and
-+applications that use the framework.  You know who you are.  ;)
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index ab3740e..6cd71ec 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -938,6 +938,7 @@ config ARCH_OMAP
- 	select ARCH_REQUIRE_GPIOLIB
- 	select ARCH_HAS_CPUFREQ
- 	select CLKSRC_MMIO
-+	select GENERIC_ALLOCATOR
- 	select GENERIC_CLOCKEVENTS
- 	select HAVE_SCHED_CLOCK
- 	select ARCH_HAS_HOLES_MEMORYMODEL
-diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
-index c5213e7..0a9ac1b 100644
---- a/arch/arm/Kconfig.debug
-+++ b/arch/arm/Kconfig.debug
-@@ -271,4 +271,10 @@ config ARM_KPROBES_TEST
- 	help
- 	  Perform tests of kprobes API and instruction set simulation.
- 
-+config DEBUG_JTAG_ENABLE
-+	bool "Enable JTAG clock for debugger connectivity"
-+	help
-+	 Say Y here if you want to enable the JTAG clock to enable
-+	 connectivity to a debugger
-+
- endmenu
-diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
-new file mode 100644
-index 0000000..f2ab4ea
---- /dev/null
-+++ b/arch/arm/boot/dts/omap2.dtsi
-@@ -0,0 +1,67 @@
-+/*
-+ * Device Tree Source for OMAP2 SoC
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This file is licensed under the terms of the GNU General Public License
-+ * version 2.  This program is licensed "as is" without any warranty of any
-+ * kind, whether express or implied.
-+ */
-+
-+/include/ "skeleton.dtsi"
-+
-+/ {
-+	compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
-+
-+	aliases {
-+		serial0 = &uart1;
-+		serial1 = &uart2;
-+		serial2 = &uart3;
-+	};
-+
-+	cpus {
-+		cpu@0 {
-+			compatible = "arm,arm1136jf-s";
-+		};
-+	};
-+
-+	soc {
-+		compatible = "ti,omap-infra";
-+		mpu {
-+			compatible = "ti,omap2-mpu";
-+			ti,hwmods = "mpu";
-+		};
-+	};
-+
-+	ocp {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		ranges;
-+		ti,hwmods = "l3_main";
-+
-+		intc: interrupt-controller@1 {
-+			compatible = "ti,omap2-intc";
-+			interrupt-controller;
-+			#interrupt-cells = <1>;
-+		};
-+
-+		uart1: serial@4806a000 {
-+			compatible = "ti,omap2-uart";
-+			ti,hwmods = "uart1";
-+			clock-frequency = <48000000>;
-+		};
-+
-+		uart2: serial@4806c000 {
-+			compatible = "ti,omap2-uart";
-+			ti,hwmods = "uart2";
-+			clock-frequency = <48000000>;
-+		};
-+
-+		uart3: serial@4806e000 {
-+			compatible = "ti,omap2-uart";
-+			ti,hwmods = "uart3";
-+			clock-frequency = <48000000>;
-+		};
-+	};
-+};
-diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
-index 9486be6..9f72cd4 100644
---- a/arch/arm/boot/dts/omap3-beagle.dts
-+++ b/arch/arm/boot/dts/omap3-beagle.dts
-@@ -13,15 +13,6 @@
- 	model = "TI OMAP3 BeagleBoard";
- 	compatible = "ti,omap3-beagle", "ti,omap3";
- 
--	/*
--	 * Since the initial device tree board file does not create any
--	 * devices (MMC, network...), the only way to boot is to provide a
--	 * ramdisk.
--	 */
--	chosen {
--		bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
--	};
--
- 	memory {
- 		device_type = "memory";
- 		reg = <0x80000000 0x20000000>; /* 512 MB */
-diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
-index d202bb5..216c331 100644
---- a/arch/arm/boot/dts/omap3.dtsi
-+++ b/arch/arm/boot/dts/omap3.dtsi
-@@ -13,6 +13,13 @@
- / {
- 	compatible = "ti,omap3430", "ti,omap3";
- 
-+	aliases {
-+		serial0 = &uart1;
-+		serial1 = &uart2;
-+		serial2 = &uart3;
-+		serial3 = &uart4;
-+	};
-+
- 	cpus {
- 		cpu@0 {
- 			compatible = "arm,cortex-a8";
-@@ -59,5 +66,29 @@
- 			interrupt-controller;
- 			#interrupt-cells = <1>;
- 		};
-+
-+		uart1: serial@0x4806a000 {
-+			compatible = "ti,omap3-uart";
-+			ti,hwmods = "uart1";
-+			clock-frequency = <48000000>;
-+		};
-+
-+		uart2: serial@0x4806c000 {
-+			compatible = "ti,omap3-uart";
-+			ti,hwmods = "uart2";
-+			clock-frequency = <48000000>;
-+		};
-+
-+		uart3: serial@0x49020000 {
-+			compatible = "ti,omap3-uart";
-+			ti,hwmods = "uart3";
-+			clock-frequency = <48000000>;
-+		};
-+
-+		uart4: serial@0x49042000 {
-+			compatible = "ti,omap3-uart";
-+			ti,hwmods = "uart4";
-+			clock-frequency = <48000000>;
-+		};
- 	};
- };
-diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
-index c702657..9755ad5 100644
---- a/arch/arm/boot/dts/omap4-panda.dts
-+++ b/arch/arm/boot/dts/omap4-panda.dts
-@@ -13,15 +13,6 @@
- 	model = "TI OMAP4 PandaBoard";
- 	compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
- 
--	/*
--	 * Since the initial device tree board file does not create any
--	 * devices (MMC, network...), the only way to boot is to provide a
--	 * ramdisk.
--	 */
--	chosen {
--		bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
--	};
--
- 	memory {
- 		device_type = "memory";
- 		reg = <0x80000000 0x40000000>; /* 1 GB */
-diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
-index 066e28c..63c6b2b 100644
---- a/arch/arm/boot/dts/omap4-sdp.dts
-+++ b/arch/arm/boot/dts/omap4-sdp.dts
-@@ -13,15 +13,6 @@
- 	model = "TI OMAP4 SDP board";
- 	compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
- 
--	/*
--	 * Since the initial device tree board file does not create any
--	 * devices (MMC, network...), the only way to boot is to provide a
--	 * ramdisk.
--	 */
--	chosen {
--		bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
--	};
--
- 	memory {
- 		device_type = "memory";
- 		reg = <0x80000000 0x40000000>; /* 1 GB */
-diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
-index 4c61c82..e8fe75f 100644
---- a/arch/arm/boot/dts/omap4.dtsi
-+++ b/arch/arm/boot/dts/omap4.dtsi
-@@ -21,6 +21,10 @@
- 	interrupt-parent = <&gic>;
- 
- 	aliases {
-+		serial0 = &uart1;
-+		serial1 = &uart2;
-+		serial2 = &uart3;
-+		serial3 = &uart4;
- 	};
- 
- 	cpus {
-@@ -99,5 +103,29 @@
- 			reg = <0x48241000 0x1000>,
- 			      <0x48240100 0x0100>;
- 		};
-+
-+		uart1: serial@0x4806a000 {
-+			compatible = "ti,omap4-uart";
-+			ti,hwmods = "uart1";
-+			clock-frequency = <48000000>;
-+		};
-+
-+		uart2: serial@0x4806c000 {
-+			compatible = "ti,omap4-uart";
-+			ti,hwmods = "uart2";
-+			clock-frequency = <48000000>;
-+		};
-+
-+		uart3: serial@0x48020000 {
-+			compatible = "ti,omap4-uart";
-+			ti,hwmods = "uart3";
-+			clock-frequency = <48000000>;
-+		};
-+
-+		uart4: serial@0x4806e000 {
-+			compatible = "ti,omap4-uart";
-+			ti,hwmods = "uart4";
-+			clock-frequency = <48000000>;
-+		};
- 	};
- };
-diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
-index 74df9ca..81a933e 100644
---- a/arch/arm/common/Kconfig
-+++ b/arch/arm/common/Kconfig
-@@ -1,8 +1,14 @@
- config ARM_GIC
- 	select IRQ_DOMAIN
-+	select MULTI_IRQ_HANDLER
-+	bool
-+
-+config GIC_NON_BANKED
- 	bool
- 
- config ARM_VIC
-+	select IRQ_DOMAIN
-+	select MULTI_IRQ_HANDLER
- 	bool
- 
- config ARM_VIC_NR
-diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
-index 6ea9b6f..40bc575 100644
---- a/arch/arm/common/Makefile
-+++ b/arch/arm/common/Makefile
-@@ -17,3 +17,4 @@ obj-$(CONFIG_ARCH_IXP2000)	+= uengine.o
- obj-$(CONFIG_ARCH_IXP23XX)	+= uengine.o
- obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
- obj-$(CONFIG_ARM_TIMER_SP804)	+= timer-sp.o
-+obj-$(CONFIG_OMAP3_EDMA)	+= edma.o
-diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
-new file mode 100644
-index 0000000..fe00c92
---- /dev/null
-+++ b/arch/arm/common/edma.c
-@@ -0,0 +1,1740 @@
-+/*
-+ * EDMA3 Driver
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/err.h>
-+#include <linux/pm_runtime.h>
-+
-+#include <mach/edma.h>
-+
-+/* Offsets matching "struct edmacc_param" */
-+#define PARM_OPT		0x00
-+#define PARM_SRC		0x04
-+#define PARM_A_B_CNT		0x08
-+#define PARM_DST		0x0c
-+#define PARM_SRC_DST_BIDX	0x10
-+#define PARM_LINK_BCNTRLD	0x14
-+#define PARM_SRC_DST_CIDX	0x18
-+#define PARM_CCNT		0x1c
-+
-+#define PARM_SIZE		0x20
-+
-+/* Offsets for EDMA CC global channel registers and their shadows */
-+#define SH_ER		0x00	/* 64 bits */
-+#define SH_ECR		0x08	/* 64 bits */
-+#define SH_ESR		0x10	/* 64 bits */
-+#define SH_CER		0x18	/* 64 bits */
-+#define SH_EER		0x20	/* 64 bits */
-+#define SH_EECR		0x28	/* 64 bits */
-+#define SH_EESR		0x30	/* 64 bits */
-+#define SH_SER		0x38	/* 64 bits */
-+#define SH_SECR		0x40	/* 64 bits */
-+#define SH_IER		0x50	/* 64 bits */
-+#define SH_IECR		0x58	/* 64 bits */
-+#define SH_IESR		0x60	/* 64 bits */
-+#define SH_IPR		0x68	/* 64 bits */
-+#define SH_ICR		0x70	/* 64 bits */
-+#define SH_IEVAL	0x78
-+#define SH_QER		0x80
-+#define SH_QEER		0x84
-+#define SH_QEECR	0x88
-+#define SH_QEESR	0x8c
-+#define SH_QSER		0x90
-+#define SH_QSECR	0x94
-+#define SH_SIZE		0x200
-+
-+/* Offsets for EDMA CC global registers */
-+#define EDMA_REV	0x0000
-+#define EDMA_CCCFG	0x0004
-+#define EDMA_QCHMAP	0x0200	/* 8 registers */
-+#define EDMA_DMAQNUM	0x0240	/* 8 registers (4 on OMAP-L1xx) */
-+#define EDMA_QDMAQNUM	0x0260
-+#define EDMA_QUETCMAP	0x0280
-+#define EDMA_QUEPRI	0x0284
-+#define EDMA_EMR	0x0300	/* 64 bits */
-+#define EDMA_EMCR	0x0308	/* 64 bits */
-+#define EDMA_QEMR	0x0310
-+#define EDMA_QEMCR	0x0314
-+#define EDMA_CCERR	0x0318
-+#define EDMA_CCERRCLR	0x031c
-+#define EDMA_EEVAL	0x0320
-+#define EDMA_DRAE	0x0340	/* 4 x 64 bits*/
-+#define EDMA_QRAE	0x0380	/* 4 registers */
-+#define EDMA_QUEEVTENTRY	0x0400	/* 2 x 16 registers */
-+#define EDMA_QSTAT	0x0600	/* 2 registers */
-+#define EDMA_QWMTHRA	0x0620
-+#define EDMA_QWMTHRB	0x0624
-+#define EDMA_CCSTAT	0x0640
-+
-+#define EDMA_M		0x1000	/* global channel registers */
-+#define EDMA_ECR	0x1008
-+#define EDMA_ECRH	0x100C
-+#define EDMA_SHADOW0	0x2000	/* 4 regions shadowing global channels */
-+#define EDMA_PARM	0x4000	/* 128 param entries */
-+
-+#define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))
-+
-+#define EDMA_DCHMAP	0x0100  /* 64 registers */
-+#define CHMAP_EXIST	BIT(24)
-+
-+
-+/*function that maps the cross bar events to channels */
-+int (*xbar_event_to_channel_map)(unsigned event, unsigned *channel,
-+			struct event_to_channel_map *xbar_event_map) = NULL;
-+
-+/*****************************************************************************/
-+
-+static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
-+
-+static inline unsigned int edma_read(unsigned ctlr, int offset)
-+{
-+	return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
-+}
-+
-+static inline void edma_write(unsigned ctlr, int offset, int val)
-+{
-+	__raw_writel(val, edmacc_regs_base[ctlr] + offset);
-+}
-+static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
-+		unsigned or)
-+{
-+	unsigned val = edma_read(ctlr, offset);
-+	val &= and;
-+	val |= or;
-+	edma_write(ctlr, offset, val);
-+}
-+static inline void edma_and(unsigned ctlr, int offset, unsigned and)
-+{
-+	unsigned val = edma_read(ctlr, offset);
-+	val &= and;
-+	edma_write(ctlr, offset, val);
-+}
-+static inline void edma_or(unsigned ctlr, int offset, unsigned or)
-+{
-+	unsigned val = edma_read(ctlr, offset);
-+	val |= or;
-+	edma_write(ctlr, offset, val);
-+}
-+static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
-+{
-+	return edma_read(ctlr, offset + (i << 2));
-+}
-+static inline unsigned int edma_read_array2(unsigned ctlr, int offset, int i,
-+		int j)
-+{
-+	return edma_read(ctlr, offset + ((i*2 + j) << 2));
-+}
-+static inline void edma_write_array(unsigned ctlr, int offset, int i,
-+		unsigned val)
-+{
-+	edma_write(ctlr, offset + (i << 2), val);
-+}
-+static inline void edma_modify_array(unsigned ctlr, int offset, int i,
-+		unsigned and, unsigned or)
-+{
-+	edma_modify(ctlr, offset + (i << 2), and, or);
-+}
-+static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
-+{
-+	edma_or(ctlr, offset + (i << 2), or);
-+}
-+static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
-+		unsigned or)
-+{
-+	edma_or(ctlr, offset + ((i*2 + j) << 2), or);
-+}
-+static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
-+		unsigned val)
-+{
-+	edma_write(ctlr, offset + ((i*2 + j) << 2), val);
-+}
-+static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
-+{
-+	return edma_read(ctlr, EDMA_SHADOW0 + offset);
-+}
-+static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
-+		int i)
-+{
-+	return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
-+}
-+static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
-+{
-+	edma_write(ctlr, EDMA_SHADOW0 + offset, val);
-+}
-+static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
-+		unsigned val)
-+{
-+	edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
-+}
-+static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
-+		int param_no)
-+{
-+	return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
-+}
-+static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
-+		unsigned val)
-+{
-+	edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
-+}
-+static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
-+		unsigned and, unsigned or)
-+{
-+	edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
-+}
-+static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
-+		unsigned and)
-+{
-+	edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
-+}
-+static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
-+		unsigned or)
-+{
-+	edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
-+}
-+
-+static inline void set_bits(int offset, int len, unsigned long *p)
-+{
-+	for (; len > 0; len--)
-+		set_bit(offset + (len - 1), p);
-+}
-+
-+static inline void clear_bits(int offset, int len, unsigned long *p)
-+{
-+	for (; len > 0; len--)
-+		clear_bit(offset + (len - 1), p);
-+}
-+
-+/*****************************************************************************/
-+
-+struct edma *edma_cc[EDMA_MAX_CC];
-+static int arch_num_cc;
-+
-+/* dummy param set used to (re)initialize parameter RAM slots */
-+static const struct edmacc_param dummy_paramset = {
-+	.link_bcntrld = 0xffff,
-+	.ccnt = 1,
-+};
-+
-+/*****************************************************************************/
-+
-+static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
-+		enum dma_event_q queue_no)
-+{
-+	int bit = (ch_no & 0x7) * 4;
-+
-+	/* default to low priority queue */
-+	if (queue_no == EVENTQ_DEFAULT)
-+		queue_no = edma_cc[ctlr]->default_queue;
-+
-+	queue_no &= 7;
-+	edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
-+			~(0x7 << bit), queue_no << bit);
-+}
-+
-+static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
-+{
-+	int bit = queue_no * 4;
-+	edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
-+}
-+
-+static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
-+		int priority)
-+{
-+	int bit = queue_no * 4;
-+	edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
-+			((priority & 0x7) << bit));
-+}
-+
-+/**
-+ * map_dmach_param - Maps channel number to param entry number
-+ *
-+ * This maps the dma channel number to param entry numberter. In
-+ * other words using the DMA channel mapping registers a param entry
-+ * can be mapped to any channel
-+ *
-+ * Callers are responsible for ensuring the channel mapping logic is
-+ * included in that particular EDMA variant (Eg : dm646x)
-+ *
-+ */
-+static void __init map_dmach_param(unsigned ctlr)
-+{
-+	int i;
-+	for (i = 0; i < EDMA_MAX_DMACH; i++)
-+		edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
-+}
-+
-+static inline void
-+setup_dma_interrupt(unsigned lch,
-+	void (*callback)(unsigned channel, u16 ch_status, void *data),
-+	void *data)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(lch);
-+	lch = EDMA_CHAN_SLOT(lch);
-+
-+	if (!callback)
-+		edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
-+				BIT(lch & 0x1f));
-+
-+	edma_cc[ctlr]->intr_data[lch].callback = callback;
-+	edma_cc[ctlr]->intr_data[lch].data = data;
-+
-+	if (callback) {
-+		edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
-+				BIT(lch & 0x1f));
-+		edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
-+				BIT(lch & 0x1f));
-+	}
-+}
-+
-+static int irq2ctlr(int irq)
-+{
-+	if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
-+		return 0;
-+	else if (irq >= edma_cc[1]->irq_res_start &&
-+		irq <= edma_cc[1]->irq_res_end)
-+		return 1;
-+
-+	return -1;
-+}
-+
-+/******************************************************************************
-+ *
-+ * DMA interrupt handler
-+ *
-+ *****************************************************************************/
-+static irqreturn_t dma_irq_handler(int irq, void *data)
-+{
-+	int i;
-+	int ctlr;
-+	unsigned int cnt = 0;
-+
-+	ctlr = irq2ctlr(irq);
-+	if (ctlr < 0)
-+		return IRQ_NONE;
-+
-+	dev_dbg(data, "dma_irq_handler\n");
-+
-+	if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) &&
-+	    (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
-+		return IRQ_NONE;
-+
-+	while (1) {
-+		int j;
-+		if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
-+				edma_shadow0_read_array(ctlr, SH_IER, 0))
-+			j = 0;
-+		else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
-+				edma_shadow0_read_array(ctlr, SH_IER, 1))
-+			j = 1;
-+		else
-+			break;
-+		dev_dbg(data, "IPR%d %08x\n", j,
-+				edma_shadow0_read_array(ctlr, SH_IPR, j));
-+		for (i = 0; i < 32; i++) {
-+			int k = (j << 5) + i;
-+			if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
-+					&& (edma_shadow0_read_array(ctlr,
-+							SH_IER, j) & BIT(i))) {
-+				/* Clear the corresponding IPR bits */
-+				edma_shadow0_write_array(ctlr, SH_ICR, j,
-+							BIT(i));
-+				if (edma_cc[ctlr]->intr_data[k].callback)
-+					edma_cc[ctlr]->intr_data[k].callback(
-+						k, DMA_COMPLETE,
-+						edma_cc[ctlr]->intr_data[k].
-+						data);
-+			}
-+		}
-+		cnt++;
-+		if (cnt > 10)
-+			break;
-+	}
-+	edma_shadow0_write(ctlr, SH_IEVAL, 1);
-+	return IRQ_HANDLED;
-+}
-+
-+/******************************************************************************
-+ *
-+ * DMA error interrupt handler
-+ *
-+ *****************************************************************************/
-+static irqreturn_t dma_ccerr_handler(int irq, void *data)
-+{
-+	int i;
-+	int ctlr;
-+	unsigned int cnt = 0;
-+
-+	ctlr = irq2ctlr(irq);
-+	if (ctlr < 0)
-+		return IRQ_NONE;
-+
-+	dev_dbg(data, "dma_ccerr_handler\n");
-+
-+	if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
-+	    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
-+	    (edma_read(ctlr, EDMA_QEMR) == 0) &&
-+	    (edma_read(ctlr, EDMA_CCERR) == 0))
-+		return IRQ_NONE;
-+
-+	while (1) {
-+		int j = -1;
-+		if (edma_read_array(ctlr, EDMA_EMR, 0))
-+			j = 0;
-+		else if (edma_read_array(ctlr, EDMA_EMR, 1))
-+			j = 1;
-+		if (j >= 0) {
-+			dev_dbg(data, "EMR%d %08x\n", j,
-+					edma_read_array(ctlr, EDMA_EMR, j));
-+			for (i = 0; i < 32; i++) {
-+				int k = (j << 5) + i;
-+				if (edma_read_array(ctlr, EDMA_EMR, j) &
-+							BIT(i)) {
-+					/* Clear the corresponding EMR bits */
-+					edma_write_array(ctlr, EDMA_EMCR, j,
-+							BIT(i));
-+					/* Clear any SER */
-+					edma_shadow0_write_array(ctlr, SH_SECR,
-+								j, BIT(i));
-+					if (edma_cc[ctlr]->intr_data[k].
-+								callback) {
-+						edma_cc[ctlr]->intr_data[k].
-+						callback(k,
-+						DMA_CC_ERROR,
-+						edma_cc[ctlr]->intr_data
-+						[k].data);
-+					}
-+				}
-+			}
-+		} else if (edma_read(ctlr, EDMA_QEMR)) {
-+			dev_dbg(data, "QEMR %02x\n",
-+				edma_read(ctlr, EDMA_QEMR));
-+			for (i = 0; i < 8; i++) {
-+				if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
-+					/* Clear the corresponding IPR bits */
-+					edma_write(ctlr, EDMA_QEMCR, BIT(i));
-+					edma_shadow0_write(ctlr, SH_QSECR,
-+								BIT(i));
-+
-+					/* NOTE:  not reported!! */
-+				}
-+			}
-+		} else if (edma_read(ctlr, EDMA_CCERR)) {
-+			dev_dbg(data, "CCERR %08x\n",
-+				edma_read(ctlr, EDMA_CCERR));
-+			/* FIXME:  CCERR.BIT(16) ignored!  much better
-+			 * to just write CCERRCLR with CCERR value...
-+			 */
-+			for (i = 0; i < 8; i++) {
-+				if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
-+					/* Clear the corresponding IPR bits */
-+					edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
-+
-+					/* NOTE:  not reported!! */
-+				}
-+			}
-+		}
-+		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
-+		    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
-+		    (edma_read(ctlr, EDMA_QEMR) == 0) &&
-+		    (edma_read(ctlr, EDMA_CCERR) == 0))
-+			break;
-+		cnt++;
-+		if (cnt > 10)
-+			break;
-+	}
-+	edma_write(ctlr, EDMA_EEVAL, 1);
-+	return IRQ_HANDLED;
-+}
-+
-+/*-----------------------------------------------------------------------*/
-+
-+static int reserve_contiguous_slots(int ctlr, unsigned int id,
-+				     unsigned int num_slots,
-+				     unsigned int start_slot)
-+{
-+	int i, j;
-+	unsigned int count = num_slots;
-+	int stop_slot = start_slot;
-+	DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
-+
-+	for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
-+		j = EDMA_CHAN_SLOT(i);
-+		if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
-+			/* Record our current beginning slot */
-+			if (count == num_slots)
-+				stop_slot = i;
-+
-+			count--;
-+			set_bit(j, tmp_inuse);
-+
-+			if (count == 0)
-+				break;
-+		} else {
-+			clear_bit(j, tmp_inuse);
-+
-+			if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
-+				stop_slot = i;
-+				break;
-+			} else {
-+				count = num_slots;
-+			}
-+		}
-+	}
-+
-+	/*
-+	 * We have to clear any bits that we set
-+	 * if we run out parameter RAM slots, i.e we do find a set
-+	 * of contiguous parameter RAM slots but do not find the exact number
-+	 * requested as we may reach the total number of parameter RAM slots
-+	 */
-+	if (i == edma_cc[ctlr]->num_slots)
-+		stop_slot = i;
-+
-+	for (j = start_slot; j < stop_slot; j++)
-+		if (test_bit(j, tmp_inuse))
-+			clear_bit(j, edma_cc[ctlr]->edma_inuse);
-+
-+	if (count)
-+		return -EBUSY;
-+
-+	for (j = i - num_slots + 1; j <= i; ++j)
-+		memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
-+			&dummy_paramset, PARM_SIZE);
-+
-+	return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
-+}
-+
-+static int prepare_unused_channel_list(struct device *dev, void *data)
-+{
-+	struct platform_device *pdev = to_platform_device(dev);
-+	int i, ctlr;
-+
-+	for (i = 0; i < pdev->num_resources; i++) {
-+		if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
-+				(int)pdev->resource[i].start >= 0) {
-+			ctlr = EDMA_CTLR(pdev->resource[i].start);
-+			/* confirm the range */
-+			if (EDMA_CHAN_SLOT(pdev->resource[i].start <
-+							EDMA_MAX_DMACH))
-+				clear_bit(
-+					EDMA_CHAN_SLOT(pdev->resource[i].start),
-+						edma_cc[ctlr]->edma_unused);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/*-----------------------------------------------------------------------*/
-+
-+static bool unused_chan_list_done;
-+
-+/* Resource alloc/free:  dma channels, parameter RAM slots */
-+
-+/**
-+ * edma_alloc_channel - allocate DMA channel and paired parameter RAM
-+ * @channel: specific channel to allocate; negative for "any unmapped channel"
-+ * @callback: optional; to be issued on DMA completion or errors
-+ * @data: passed to callback
-+ * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
-+ *	Controller (TC) executes requests using this channel.  Use
-+ *	EVENTQ_DEFAULT unless you really need a high priority queue.
-+ *
-+ * This allocates a DMA channel and its associated parameter RAM slot.
-+ * The parameter RAM is initialized to hold a dummy transfer.
-+ *
-+ * Normal use is to pass a specific channel number as @channel, to make
-+ * use of hardware events mapped to that channel.  When the channel will
-+ * be used only for software triggering or event chaining, channels not
-+ * mapped to hardware events (or mapped to unused events) are preferable.
-+ *
-+ * DMA transfers start from a channel using edma_start(), or by
-+ * chaining.  When the transfer described in that channel's parameter RAM
-+ * slot completes, that slot's data may be reloaded through a link.
-+ *
-+ * DMA errors are only reported to the @callback associated with the
-+ * channel driving that transfer, but transfer completion callbacks can
-+ * be sent to another channel under control of the TCC field in
-+ * the option word of the transfer's parameter RAM set.  Drivers must not
-+ * use DMA transfer completion callbacks for channels they did not allocate.
-+ * (The same applies to TCC codes used in transfer chaining.)
-+ *
-+ * Returns the number of the channel, else negative errno.
-+ */
-+int edma_alloc_channel(int channel,
-+		void (*callback)(unsigned channel, u16 ch_status, void *data),
-+		void *data,
-+		enum dma_event_q eventq_no)
-+{
-+	unsigned i, done = 0, ctlr = 0;
-+	int ret = 0;
-+
-+	if (!unused_chan_list_done) {
-+		/*
-+		 * Scan all the platform devices to find out the EDMA channels
-+		 * used and clear them in the unused list, making the rest
-+		 * available for ARM usage.
-+		 */
-+		ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
-+				prepare_unused_channel_list);
-+		if (ret < 0)
-+			return ret;
-+
-+		unused_chan_list_done = true;
-+	}
-+
-+	if (channel >= 0) {
-+			ctlr = EDMA_CTLR(channel);
-+			channel = EDMA_CHAN_SLOT(channel);
-+			if (xbar_event_to_channel_map) {
-+				ret = xbar_event_to_channel_map(channel,
-+						&channel, edma_cc[ctlr]->
-+						xbar_event_mapping);
-+				if (ret != 0)
-+					return ret;
-+			}
-+	}
-+
-+	if (channel < 0) {
-+		for (i = 0; i < arch_num_cc; i++) {
-+			channel = 0;
-+			for (;;) {
-+				channel = find_next_bit(edma_cc[i]->edma_unused,
-+						edma_cc[i]->num_channels,
-+						channel);
-+				if (channel == edma_cc[i]->num_channels)
-+					break;
-+				if (!test_and_set_bit(channel,
-+						edma_cc[i]->edma_inuse)) {
-+					done = 1;
-+					ctlr = i;
-+					break;
-+				}
-+				channel++;
-+			}
-+			if (done)
-+				break;
-+		}
-+		if (!done)
-+			return -ENOMEM;
-+	} else if (channel >= edma_cc[ctlr]->num_channels) {
-+		return -EINVAL;
-+	} else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
-+		return -EBUSY;
-+	}
-+
-+	/* ensure access through shadow region 0 */
-+	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
-+
-+	/* ensure no events are pending */
-+	edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
-+	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
-+			&dummy_paramset, PARM_SIZE);
-+
-+	if (callback)
-+		setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
-+					callback, data);
-+
-+	map_dmach_queue(ctlr, channel, eventq_no);
-+
-+	return EDMA_CTLR_CHAN(ctlr, channel);
-+}
-+EXPORT_SYMBOL(edma_alloc_channel);
-+
-+
-+/**
-+ * edma_free_channel - deallocate DMA channel
-+ * @channel: dma channel returned from edma_alloc_channel()
-+ *
-+ * This deallocates the DMA channel and associated parameter RAM slot
-+ * allocated by edma_alloc_channel().
-+ *
-+ * Callers are responsible for ensuring the channel is inactive, and
-+ * will not be reactivated by linking, chaining, or software calls to
-+ * edma_start().
-+ */
-+void edma_free_channel(unsigned channel)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(channel);
-+	channel = EDMA_CHAN_SLOT(channel);
-+
-+	if (channel >= edma_cc[ctlr]->num_channels)
-+		return;
-+
-+	setup_dma_interrupt(channel, NULL, NULL);
-+	/* REVISIT should probably take out of shadow region 0 */
-+
-+	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
-+			&dummy_paramset, PARM_SIZE);
-+	clear_bit(channel, edma_cc[ctlr]->edma_inuse);
-+}
-+EXPORT_SYMBOL(edma_free_channel);
-+
-+/**
-+ * edma_alloc_slot - allocate DMA parameter RAM
-+ * @slot: specific slot to allocate; negative for "any unused slot"
-+ *
-+ * This allocates a parameter RAM slot, initializing it to hold a
-+ * dummy transfer.  Slots allocated using this routine have not been
-+ * mapped to a hardware DMA channel, and will normally be used by
-+ * linking to them from a slot associated with a DMA channel.
-+ *
-+ * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
-+ * slots may be allocated on behalf of DSP firmware.
-+ *
-+ * Returns the number of the slot, else negative errno.
-+ */
-+int edma_alloc_slot(unsigned ctlr, int slot)
-+{
-+	if (slot >= 0)
-+		slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot < 0) {
-+		slot = edma_cc[ctlr]->num_channels;
-+		for (;;) {
-+			slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
-+					edma_cc[ctlr]->num_slots, slot);
-+			if (slot == edma_cc[ctlr]->num_slots)
-+				return -ENOMEM;
-+			if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
-+				break;
-+		}
-+	} else if (slot < edma_cc[ctlr]->num_channels ||
-+			slot >= edma_cc[ctlr]->num_slots) {
-+		return -EINVAL;
-+	} else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
-+		return -EBUSY;
-+	}
-+
-+	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
-+			&dummy_paramset, PARM_SIZE);
-+
-+	return EDMA_CTLR_CHAN(ctlr, slot);
-+}
-+EXPORT_SYMBOL(edma_alloc_slot);
-+
-+/**
-+ * edma_free_slot - deallocate DMA parameter RAM
-+ * @slot: parameter RAM slot returned from edma_alloc_slot()
-+ *
-+ * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
-+ * Callers are responsible for ensuring the slot is inactive, and will
-+ * not be activated.
-+ */
-+void edma_free_slot(unsigned slot)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot < edma_cc[ctlr]->num_channels ||
-+		slot >= edma_cc[ctlr]->num_slots)
-+		return;
-+
-+	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
-+			&dummy_paramset, PARM_SIZE);
-+	clear_bit(slot, edma_cc[ctlr]->edma_inuse);
-+}
-+EXPORT_SYMBOL(edma_free_slot);
-+
-+
-+/**
-+ * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
-+ * The API will return the starting point of a set of
-+ * contiguous parameter RAM slots that have been requested
-+ *
-+ * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
-+ * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
-+ * @count: number of contiguous Paramter RAM slots
-+ * @slot  - the start value of Parameter RAM slot that should be passed if id
-+ * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
-+ *
-+ * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
-+ * contiguous Parameter RAM slots from parameter RAM 64 in the case of
-+ * DaVinci SOCs and 32 in the case of DA8xx SOCs.
-+ *
-+ * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
-+ * set of contiguous parameter RAM slots from the "slot" that is passed as an
-+ * argument to the API.
-+ *
-+ * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
-+ * starts looking for a set of contiguous parameter RAMs from the "slot"
-+ * that is passed as an argument to the API. On failure the API will try to
-+ * find a set of contiguous Parameter RAM slots from the remaining Parameter
-+ * RAM slots
-+ */
-+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
-+{
-+	/*
-+	 * The start slot requested should be greater than
-+	 * the number of channels and lesser than the total number
-+	 * of slots
-+	 */
-+	if ((id != EDMA_CONT_PARAMS_ANY) &&
-+		(slot < edma_cc[ctlr]->num_channels ||
-+		slot >= edma_cc[ctlr]->num_slots))
-+		return -EINVAL;
-+
-+	/*
-+	 * The number of parameter RAM slots requested cannot be less than 1
-+	 * and cannot be more than the number of slots minus the number of
-+	 * channels
-+	 */
-+	if (count < 1 || count >
-+		(edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
-+		return -EINVAL;
-+
-+	switch (id) {
-+	case EDMA_CONT_PARAMS_ANY:
-+		return reserve_contiguous_slots(ctlr, id, count,
-+						 edma_cc[ctlr]->num_channels);
-+	case EDMA_CONT_PARAMS_FIXED_EXACT:
-+	case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
-+		return reserve_contiguous_slots(ctlr, id, count, slot);
-+	default:
-+		return -EINVAL;
-+	}
-+
-+}
-+EXPORT_SYMBOL(edma_alloc_cont_slots);
-+
-+/**
-+ * edma_free_cont_slots - deallocate DMA parameter RAM slots
-+ * @slot: first parameter RAM of a set of parameter RAM slots to be freed
-+ * @count: the number of contiguous parameter RAM slots to be freed
-+ *
-+ * This deallocates the parameter RAM slots allocated by
-+ * edma_alloc_cont_slots.
-+ * Callers/applications need to keep track of sets of contiguous
-+ * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
-+ * API.
-+ * Callers are responsible for ensuring the slots are inactive, and will
-+ * not be activated.
-+ */
-+int edma_free_cont_slots(unsigned slot, int count)
-+{
-+	unsigned ctlr, slot_to_free;
-+	int i;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot < edma_cc[ctlr]->num_channels ||
-+		slot >= edma_cc[ctlr]->num_slots ||
-+		count < 1)
-+		return -EINVAL;
-+
-+	for (i = slot; i < slot + count; ++i) {
-+		ctlr = EDMA_CTLR(i);
-+		slot_to_free = EDMA_CHAN_SLOT(i);
-+
-+		memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
-+			&dummy_paramset, PARM_SIZE);
-+		clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(edma_free_cont_slots);
-+
-+/*-----------------------------------------------------------------------*/
-+
-+/* Parameter RAM operations (i) -- read/write partial slots */
-+
-+/**
-+ * edma_set_src - set initial DMA source address in parameter RAM slot
-+ * @slot: parameter RAM slot being configured
-+ * @src_port: physical address of source (memory, controller FIFO, etc)
-+ * @addressMode: INCR, except in very rare cases
-+ * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
-+ *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
-+ *
-+ * Note that the source address is modified during the DMA transfer
-+ * according to edma_set_src_index().
-+ */
-+void edma_set_src(unsigned slot, dma_addr_t src_port,
-+				enum address_mode mode, enum fifo_width width)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot < edma_cc[ctlr]->num_slots) {
-+		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-+
-+		if (mode) {
-+			/* set SAM and program FWID */
-+			i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
-+		} else {
-+			/* clear SAM */
-+			i &= ~SAM;
-+		}
-+		edma_parm_write(ctlr, PARM_OPT, slot, i);
-+
-+		/* set the source port address
-+		   in source register of param structure */
-+		edma_parm_write(ctlr, PARM_SRC, slot, src_port);
-+	}
-+}
-+EXPORT_SYMBOL(edma_set_src);
-+
-+/**
-+ * edma_set_dest - set initial DMA destination address in parameter RAM slot
-+ * @slot: parameter RAM slot being configured
-+ * @dest_port: physical address of destination (memory, controller FIFO, etc)
-+ * @addressMode: INCR, except in very rare cases
-+ * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
-+ *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
-+ *
-+ * Note that the destination address is modified during the DMA transfer
-+ * according to edma_set_dest_index().
-+ */
-+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
-+				 enum address_mode mode, enum fifo_width width)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot < edma_cc[ctlr]->num_slots) {
-+		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-+
-+		if (mode) {
-+			/* set DAM and program FWID */
-+			i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
-+		} else {
-+			/* clear DAM */
-+			i &= ~DAM;
-+		}
-+		edma_parm_write(ctlr, PARM_OPT, slot, i);
-+		/* set the destination port address
-+		   in dest register of param structure */
-+		edma_parm_write(ctlr, PARM_DST, slot, dest_port);
-+	}
-+}
-+EXPORT_SYMBOL(edma_set_dest);
-+
-+/**
-+ * edma_get_position - returns the current transfer points
-+ * @slot: parameter RAM slot being examined
-+ * @src: pointer to source port position
-+ * @dst: pointer to destination port position
-+ *
-+ * Returns current source and destination addresses for a particular
-+ * parameter RAM slot.  Its channel should not be active when this is called.
-+ */
-+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
-+{
-+	struct edmacc_param temp;
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
-+	if (src != NULL)
-+		*src = temp.src;
-+	if (dst != NULL)
-+		*dst = temp.dst;
-+}
-+EXPORT_SYMBOL(edma_get_position);
-+
-+/**
-+ * edma_set_src_index - configure DMA source address indexing
-+ * @slot: parameter RAM slot being configured
-+ * @src_bidx: byte offset between source arrays in a frame
-+ * @src_cidx: byte offset between source frames in a block
-+ *
-+ * Offsets are specified to support either contiguous or discontiguous
-+ * memory transfers, or repeated access to a hardware register, as needed.
-+ * When accessing hardware registers, both offsets are normally zero.
-+ */
-+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot < edma_cc[ctlr]->num_slots) {
-+		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
-+				0xffff0000, src_bidx);
-+		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
-+				0xffff0000, src_cidx);
-+	}
-+}
-+EXPORT_SYMBOL(edma_set_src_index);
-+
-+/**
-+ * edma_set_dest_index - configure DMA destination address indexing
-+ * @slot: parameter RAM slot being configured
-+ * @dest_bidx: byte offset between destination arrays in a frame
-+ * @dest_cidx: byte offset between destination frames in a block
-+ *
-+ * Offsets are specified to support either contiguous or discontiguous
-+ * memory transfers, or repeated access to a hardware register, as needed.
-+ * When accessing hardware registers, both offsets are normally zero.
-+ */
-+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot < edma_cc[ctlr]->num_slots) {
-+		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
-+				0x0000ffff, dest_bidx << 16);
-+		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
-+				0x0000ffff, dest_cidx << 16);
-+	}
-+}
-+EXPORT_SYMBOL(edma_set_dest_index);
-+
-+/**
-+ * edma_set_transfer_params - configure DMA transfer parameters
-+ * @slot: parameter RAM slot being configured
-+ * @acnt: how many bytes per array (at least one)
-+ * @bcnt: how many arrays per frame (at least one)
-+ * @ccnt: how many frames per block (at least one)
-+ * @bcnt_rld: used only for A-Synchronized transfers; this specifies
-+ *	the value to reload into bcnt when it decrements to zero
-+ * @sync_mode: ASYNC or ABSYNC
-+ *
-+ * See the EDMA3 documentation to understand how to configure and link
-+ * transfers using the fields in PaRAM slots.  If you are not doing it
-+ * all at once with edma_write_slot(), you will use this routine
-+ * plus two calls each for source and destination, setting the initial
-+ * address and saying how to index that address.
-+ *
-+ * An example of an A-Synchronized transfer is a serial link using a
-+ * single word shift register.  In that case, @acnt would be equal to
-+ * that word size; the serial controller issues a DMA synchronization
-+ * event to transfer each word, and memory access by the DMA transfer
-+ * controller will be word-at-a-time.
-+ *
-+ * An example of an AB-Synchronized transfer is a device using a FIFO.
-+ * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
-+ * The controller with the FIFO issues DMA synchronization events when
-+ * the FIFO threshold is reached, and the DMA transfer controller will
-+ * transfer one frame to (or from) the FIFO.  It will probably use
-+ * efficient burst modes to access memory.
-+ */
-+void edma_set_transfer_params(unsigned slot,
-+		u16 acnt, u16 bcnt, u16 ccnt,
-+		u16 bcnt_rld, enum sync_dimension sync_mode)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot < edma_cc[ctlr]->num_slots) {
-+		edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
-+				0x0000ffff, bcnt_rld << 16);
-+		if (sync_mode == ASYNC)
-+			edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
-+		else
-+			edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
-+		/* Set the acount, bcount, ccount registers */
-+		edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
-+		edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
-+	}
-+}
-+EXPORT_SYMBOL(edma_set_transfer_params);
-+
-+/**
-+ * edma_link - link one parameter RAM slot to another
-+ * @from: parameter RAM slot originating the link
-+ * @to: parameter RAM slot which is the link target
-+ *
-+ * The originating slot should not be part of any active DMA transfer.
-+ */
-+void edma_link(unsigned from, unsigned to)
-+{
-+	unsigned ctlr_from, ctlr_to;
-+
-+	ctlr_from = EDMA_CTLR(from);
-+	from = EDMA_CHAN_SLOT(from);
-+	ctlr_to = EDMA_CTLR(to);
-+	to = EDMA_CHAN_SLOT(to);
-+
-+	if (from >= edma_cc[ctlr_from]->num_slots)
-+		return;
-+	if (to >= edma_cc[ctlr_to]->num_slots)
-+		return;
-+	edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
-+				PARM_OFFSET(to));
-+}
-+EXPORT_SYMBOL(edma_link);
-+
-+/**
-+ * edma_unlink - cut link from one parameter RAM slot
-+ * @from: parameter RAM slot originating the link
-+ *
-+ * The originating slot should not be part of any active DMA transfer.
-+ * Its link is set to 0xffff.
-+ */
-+void edma_unlink(unsigned from)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(from);
-+	from = EDMA_CHAN_SLOT(from);
-+
-+	if (from >= edma_cc[ctlr]->num_slots)
-+		return;
-+	edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
-+}
-+EXPORT_SYMBOL(edma_unlink);
-+
-+/*-----------------------------------------------------------------------*/
-+
-+/* Parameter RAM operations (ii) -- read/write whole parameter sets */
-+
-+/**
-+ * edma_write_slot - write parameter RAM data for slot
-+ * @slot: number of parameter RAM slot being modified
-+ * @param: data to be written into parameter RAM slot
-+ *
-+ * Use this to assign all parameters of a transfer at once.  This
-+ * allows more efficient setup of transfers than issuing multiple
-+ * calls to set up those parameters in small pieces, and provides
-+ * complete control over all transfer options.
-+ */
-+void edma_write_slot(unsigned slot, const struct edmacc_param *param)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot >= edma_cc[ctlr]->num_slots)
-+		return;
-+	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
-+			PARM_SIZE);
-+}
-+EXPORT_SYMBOL(edma_write_slot);
-+
-+/**
-+ * edma_read_slot - read parameter RAM data from slot
-+ * @slot: number of parameter RAM slot being copied
-+ * @param: where to store copy of parameter RAM data
-+ *
-+ * Use this to read data from a parameter RAM slot, perhaps to
-+ * save them as a template for later reuse.
-+ */
-+void edma_read_slot(unsigned slot, struct edmacc_param *param)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(slot);
-+	slot = EDMA_CHAN_SLOT(slot);
-+
-+	if (slot >= edma_cc[ctlr]->num_slots)
-+		return;
-+	memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
-+			PARM_SIZE);
-+}
-+EXPORT_SYMBOL(edma_read_slot);
-+
-+/*-----------------------------------------------------------------------*/
-+
-+/* Various EDMA channel control operations */
-+
-+/**
-+ * edma_pause - pause dma on a channel
-+ * @channel: on which edma_start() has been called
-+ *
-+ * This temporarily disables EDMA hardware events on the specified channel,
-+ * preventing them from triggering new transfers on its behalf
-+ */
-+void edma_pause(unsigned channel)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(channel);
-+	channel = EDMA_CHAN_SLOT(channel);
-+
-+	if (channel < edma_cc[ctlr]->num_channels) {
-+		unsigned int mask = BIT(channel & 0x1f);
-+
-+		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
-+	}
-+}
-+EXPORT_SYMBOL(edma_pause);
-+
-+/**
-+ * edma_resume - resumes dma on a paused channel
-+ * @channel: on which edma_pause() has been called
-+ *
-+ * This re-enables EDMA hardware events on the specified channel.
-+ */
-+void edma_resume(unsigned channel)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(channel);
-+	channel = EDMA_CHAN_SLOT(channel);
-+
-+	if (channel < edma_cc[ctlr]->num_channels) {
-+		unsigned int mask = BIT(channel & 0x1f);
-+
-+		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
-+	}
-+}
-+EXPORT_SYMBOL(edma_resume);
-+
-+/**
-+ * edma_start - start dma on a channel
-+ * @channel: channel being activated
-+ *
-+ * Channels with event associations will be triggered by their hardware
-+ * events, and channels without such associations will be triggered by
-+ * software.  (At this writing there is no interface for using software
-+ * triggers except with channels that don't support hardware triggers.)
-+ *
-+ * Returns zero on success, else negative errno.
-+ */
-+int edma_start(unsigned channel)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(channel);
-+	channel = EDMA_CHAN_SLOT(channel);
-+
-+	if (channel < edma_cc[ctlr]->num_channels) {
-+		int j = channel >> 5;
-+		unsigned int mask = BIT(channel & 0x1f);
-+
-+		/* EDMA channels without event association */
-+		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
-+			pr_debug("EDMA: ESR%d %08x\n", j,
-+				edma_shadow0_read_array(ctlr, SH_ESR, j));
-+			edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
-+			return 0;
-+		}
-+
-+		/* EDMA channel with event association */
-+		pr_debug("EDMA: ER%d %08x\n", j,
-+			edma_shadow0_read_array(ctlr, SH_ER, j));
-+		/* Clear any pending event or error */
-+		edma_write_array(ctlr, EDMA_ECR, j, mask);
-+		edma_write_array(ctlr, EDMA_EMCR, j, mask);
-+		/* Clear any SER */
-+		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-+		edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
-+		pr_debug("EDMA: EER%d %08x\n", j,
-+			edma_shadow0_read_array(ctlr, SH_EER, j));
-+		return 0;
-+	}
-+
-+	return -EINVAL;
-+}
-+EXPORT_SYMBOL(edma_start);
-+
-+/**
-+ * edma_stop - stops dma on the channel passed
-+ * @channel: channel being deactivated
-+ *
-+ * When @lch is a channel, any active transfer is paused and
-+ * all pending hardware events are cleared.  The current transfer
-+ * may not be resumed, and the channel's Parameter RAM should be
-+ * reinitialized before being reused.
-+ */
-+void edma_stop(unsigned channel)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(channel);
-+	channel = EDMA_CHAN_SLOT(channel);
-+
-+	if (channel < edma_cc[ctlr]->num_channels) {
-+		int j = channel >> 5;
-+		unsigned int mask = BIT(channel & 0x1f);
-+
-+		edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
-+		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
-+		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-+		edma_write_array(ctlr, EDMA_EMCR, j, mask);
-+
-+		pr_debug("EDMA: EER%d %08x\n", j,
-+				edma_shadow0_read_array(ctlr, SH_EER, j));
-+
-+		/* REVISIT:  consider guarding against inappropriate event
-+		 * chaining by overwriting with dummy_paramset.
-+		 */
-+	}
-+}
-+EXPORT_SYMBOL(edma_stop);
-+
-+/******************************************************************************
-+ *
-+ * It cleans ParamEntry qand bring back EDMA to initial state if media has
-+ * been removed before EDMA has finished.It is usedful for removable media.
-+ * Arguments:
-+ *      ch_no     - channel no
-+ *
-+ * Return: zero on success, or corresponding error no on failure
-+ *
-+ * FIXME this should not be needed ... edma_stop() should suffice.
-+ *
-+ *****************************************************************************/
-+
-+void edma_clean_channel(unsigned channel)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(channel);
-+	channel = EDMA_CHAN_SLOT(channel);
-+
-+	if (channel < edma_cc[ctlr]->num_channels) {
-+		int j = (channel >> 5);
-+		unsigned int mask = BIT(channel & 0x1f);
-+
-+		pr_debug("EDMA: EMR%d %08x\n", j,
-+				edma_read_array(ctlr, EDMA_EMR, j));
-+		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
-+		/* Clear the corresponding EMR bits */
-+		edma_write_array(ctlr, EDMA_EMCR, j, mask);
-+		/* Clear any SER */
-+		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-+		edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
-+	}
-+}
-+EXPORT_SYMBOL(edma_clean_channel);
-+
-+/*
-+ * edma_clear_event - clear an outstanding event on the DMA channel
-+ * Arguments:
-+ *	channel - channel number
-+ */
-+void edma_clear_event(unsigned channel)
-+{
-+	unsigned ctlr;
-+
-+	ctlr = EDMA_CTLR(channel);
-+	channel = EDMA_CHAN_SLOT(channel);
-+
-+	if (channel >= edma_cc[ctlr]->num_channels)
-+		return;
-+	if (channel < 32)
-+		edma_write(ctlr, EDMA_ECR, BIT(channel));
-+	else
-+		edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
-+}
-+EXPORT_SYMBOL(edma_clear_event);
-+
-+/*-----------------------------------------------------------------------*/
-+
-+static int __init edma_probe(struct platform_device *pdev)
-+{
-+	struct edma_soc_info	*info = pdev->dev.platform_data;
-+	const s8		(*queue_priority_mapping)[2];
-+	const s8		(*queue_tc_mapping)[2];
-+	int			i, j, off, ln, found = 0;
-+	int			status = -1;
-+	const s16		(*rsv_chans)[2];
-+	const s16		(*rsv_slots)[2];
-+	int			irq[EDMA_MAX_CC] = {0, 0};
-+	int			err_irq[EDMA_MAX_CC] = {0, 0};
-+	struct resource		*r[EDMA_MAX_CC] = {NULL};
-+	resource_size_t		len[EDMA_MAX_CC];
-+	char			res_name[10];
-+	char			irq_name[10];
-+
-+	if (!info)
-+		return -ENODEV;
-+
-+	pm_runtime_enable(&pdev->dev);
-+	pm_runtime_get_sync(&pdev->dev);
-+
-+	for (j = 0; j < EDMA_MAX_CC; j++) {
-+		sprintf(res_name, "edma_cc%d", j);
-+		r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+						res_name);
-+		if (!r[j]) {
-+			if (found)
-+				break;
-+			else
-+				return -ENODEV;
-+		} else {
-+			found = 1;
-+		}
-+
-+		len[j] = resource_size(r[j]);
-+
-+		r[j] = request_mem_region(r[j]->start, len[j],
-+			dev_name(&pdev->dev));
-+		if (!r[j]) {
-+			status = -EBUSY;
-+			goto fail1;
-+		}
-+
-+		edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
-+		if (!edmacc_regs_base[j]) {
-+			status = -EBUSY;
-+			goto fail1;
-+		}
-+
-+		edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
-+		if (!edma_cc[j]) {
-+			status = -ENOMEM;
-+			goto fail1;
-+		}
-+
-+		edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
-+							EDMA_MAX_DMACH);
-+		edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
-+							EDMA_MAX_PARAMENTRY);
-+		edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
-+		edma_cc[j]->num_region = min_t(unsigned, info[j].n_region,
-+							EDMA_MAX_REGION);
-+
-+		edma_cc[j]->bkp_prm_set = kzalloc((sizeof(struct edmacc_param) *
-+						edma_cc[j]->num_slots),
-+						GFP_KERNEL);
-+		if (!edma_cc[j]->bkp_prm_set) {
-+			status = -ENOMEM;
-+			dev_err(&pdev->dev, "err: mem alloc bkp_prm_set\n");
-+			goto fail1;
-+		}
-+
-+		edma_cc[j]->bkp_ch_map = kzalloc((sizeof(unsigned int) *
-+						edma_cc[j]->num_channels),
-+						GFP_KERNEL);
-+		if (!edma_cc[j]->bkp_ch_map) {
-+			status = -ENOMEM;
-+			dev_err(&pdev->dev, "err: mem alloc bkp_ch_map\n");
-+			goto fail1;
-+		}
-+
-+		edma_cc[j]->bkp_que_num = kzalloc((sizeof(unsigned int) * 8),
-+								GFP_KERNEL);
-+		if (!edma_cc[j]->bkp_que_num) {
-+			status = -ENOMEM;
-+			dev_err(&pdev->dev, "err: mem alloc bkp_que_num\n");
-+			goto fail1;
-+		}
-+
-+		edma_cc[j]->bkp_drae = kzalloc((sizeof(unsigned int) *
-+							edma_cc[j]->num_region),
-+							GFP_KERNEL);
-+		if (!edma_cc[j]->bkp_drae) {
-+			status = -ENOMEM;
-+			dev_err(&pdev->dev, "err: mem alloc bkp_drae\n");
-+			goto fail1;
-+		}
-+
-+		edma_cc[j]->bkp_draeh = kzalloc((sizeof(unsigned int) *
-+							edma_cc[j]->num_region),
-+							GFP_KERNEL);
-+		if (!edma_cc[j]->bkp_draeh) {
-+			status = -ENOMEM;
-+			dev_err(&pdev->dev, "err: mem alloc bkp_draeh\n");
-+			goto fail1;
-+		}
-+
-+		edma_cc[j]->bkp_qrae = kzalloc((sizeof(unsigned int) *
-+							edma_cc[j]->num_region),
-+							GFP_KERNEL);
-+		if (!edma_cc[j]->bkp_qrae) {
-+			status = -ENOMEM;
-+			dev_err(&pdev->dev, "err: mem alloc bkp_qrae\n");
-+			goto fail1;
-+		}
-+
-+		edma_cc[j]->default_queue = info[j].default_queue;
-+		if (!edma_cc[j]->default_queue)
-+			edma_cc[j]->default_queue = EVENTQ_1;
-+
-+		dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
-+			edmacc_regs_base[j]);
-+
-+		for (i = 0; i < edma_cc[j]->num_slots; i++)
-+			memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
-+					&dummy_paramset, PARM_SIZE);
-+
-+		/* Mark all channels as unused */
-+		memset(edma_cc[j]->edma_unused, 0xff,
-+			sizeof(edma_cc[j]->edma_unused));
-+
-+		/* Clear the reserved channels in unused list */
-+		rsv_chans = info[j].rsv_chans;
-+		if (rsv_chans) {
-+			for (i = 0; rsv_chans[i][0] != -1; i++) {
-+				off = rsv_chans[i][0];
-+				ln = rsv_chans[i][1];
-+				/* confirm the range */
-+				if ((off+ln) < EDMA_MAX_DMACH)
-+					clear_bits(off, ln,
-+						edma_cc[j]->edma_unused);
-+			}
-+		}
-+
-+		/* Set the reserved channels/slots in inuse list */
-+		rsv_slots = info[j].rsv_slots;
-+		if (rsv_slots) {
-+			for (i = 0; rsv_slots[i][0] != -1; i++) {
-+				off = rsv_slots[i][0];
-+				ln = rsv_slots[i][1];
-+				set_bits(off, ln, edma_cc[j]->edma_inuse);
-+			}
-+		}
-+
-+		sprintf(irq_name, "edma%d", j);
-+		irq[j] = platform_get_irq_byname(pdev, irq_name);
-+		edma_cc[j]->irq_res_start = irq[j];
-+		status = request_irq(irq[j], dma_irq_handler, 0, "edma",
-+					&pdev->dev);
-+		if (status < 0) {
-+			dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
-+				irq[j], status);
-+			goto fail;
-+		}
-+
-+		sprintf(irq_name, "edma%d_err", j);
-+		err_irq[j] = platform_get_irq_byname(pdev, irq_name);
-+		edma_cc[j]->irq_res_end = err_irq[j];
-+		status = request_irq(err_irq[j], dma_ccerr_handler, 0,
-+					"edma_error", &pdev->dev);
-+		if (status < 0) {
-+			dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
-+				err_irq[j], status);
-+			goto fail;
-+		}
-+
-+		/* Everything lives on transfer controller 1 until otherwise
-+		 * specified. This way, long transfers on the low priority queue
-+		 * started by the codec engine will not cause audio defects.
-+		 */
-+		for (i = 0; i < edma_cc[j]->num_channels; i++)
-+			map_dmach_queue(j, i, EVENTQ_1);
-+
-+		queue_tc_mapping = info[j].queue_tc_mapping;
-+		queue_priority_mapping = info[j].queue_priority_mapping;
-+
-+		/* Event queue to TC mapping */
-+		for (i = 0; queue_tc_mapping[i][0] != -1; i++)
-+			map_queue_tc(j, queue_tc_mapping[i][0],
-+					queue_tc_mapping[i][1]);
-+
-+		/* Event queue priority mapping */
-+		for (i = 0; queue_priority_mapping[i][0] != -1; i++)
-+			assign_priority_to_queue(j,
-+						queue_priority_mapping[i][0],
-+						queue_priority_mapping[i][1]);
-+
-+		/* Map the channel to param entry if channel mapping logic
-+		 * exist
-+		 */
-+		if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
-+			map_dmach_param(j);
-+
-+		for (i = 0; i < info[j].n_region; i++) {
-+			edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
-+			edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
-+			edma_write_array(j, EDMA_QRAE, i, 0x0);
-+		}
-+
-+		edma_cc[j]->is_xbar = info[j].is_xbar;
-+
-+		if (edma_cc[j]->is_xbar) {
-+			edma_cc[j]->num_events = info[j].n_events;
-+			edma_cc[j]->xbar_event_mapping =
-+						info[j].xbar_event_mapping;
-+			xbar_event_to_channel_map = info[j].map_xbar_channel;
-+		}
-+
-+		arch_num_cc++;
-+	}
-+
-+	return 0;
-+
-+fail:
-+	for (i = 0; i < EDMA_MAX_CC; i++) {
-+		if (err_irq[i])
-+			free_irq(err_irq[i], &pdev->dev);
-+		if (irq[i])
-+			free_irq(irq[i], &pdev->dev);
-+	}
-+fail1:
-+	for (i = 0; i < EDMA_MAX_CC; i++) {
-+		if (r[i])
-+			release_mem_region(r[i]->start, len[i]);
-+		if (edmacc_regs_base[i])
-+			iounmap(edmacc_regs_base[i]);
-+		kfree(edma_cc[i]);
-+	}
-+	pm_runtime_put_sync(&pdev->dev);
-+	pm_runtime_disable(&pdev->dev);
-+	return status;
-+}
-+
-+#ifdef CONFIG_PM
-+static int edma3_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < arch_num_cc; i++) {
-+		/* backup channel data */
-+		for (j = 0; j < edma_cc[i]->num_channels; j++) {
-+			edma_cc[i]->bkp_ch_map[j] = edma_read_array(i,
-+							EDMA_DCHMAP, j);
-+		}
-+
-+		/* backup DMA Queue Number */
-+		for (j = 0; j < 8; j++) {
-+			edma_cc[i]->bkp_que_num[j] = edma_read_array(i,
-+							EDMA_DMAQNUM, j);
-+		}
-+
-+		for (j = 0; j < edma_cc[i]->num_region; j++) {
-+			/* backup DMA DMA Region Access Enable data */
-+			edma_cc[i]->bkp_drae[j] = edma_read_array2(i,
-+							EDMA_DRAE, j, 0);
-+			edma_cc[i]->bkp_draeh[j] = edma_read_array2(i,
-+							EDMA_DRAE, j, 1);
-+
-+			/* backup DMA QDMA Region Access Enable data */
-+			edma_cc[i]->bkp_qrae[j] = edma_read_array(i,
-+							EDMA_QRAE, j);
-+		}
-+
-+		/* backup DMA shadow Event Set data */
-+		edma_cc[i]->bkp_sh_esr = edma_shadow0_read_array(i, SH_ESR, 0);
-+		edma_cc[i]->bkp_sh_esrh = edma_shadow0_read_array(i, SH_ESR, 1);
-+
-+		/* backup DMA Shadow Event Enable Set data */
-+		edma_cc[i]->bkp_sh_eesr = edma_shadow0_read_array(i,
-+							SH_EER, 0);
-+		edma_cc[i]->bkp_sh_eesrh = edma_shadow0_read_array(i,
-+							SH_EER, 1);
-+
-+		/* backup DMA Shadow Interrupt Enable Set data */
-+		edma_cc[i]->bkp_sh_iesr = edma_shadow0_read_array(i,
-+							SH_IER, 0);
-+		edma_cc[i]->bkp_sh_iesrh = edma_shadow0_read_array(i,
-+							SH_IER, 1);
-+
-+		edma_cc[i]->bkp_que_tc_map = edma_read(i, EDMA_QUETCMAP);
-+
-+		/* backup DMA Queue Priority data */
-+		edma_cc[i]->bkp_que_pri = edma_read(i, EDMA_QUEPRI);
-+
-+		/* backup paramset */
-+		for (j = 0; j < edma_cc[i]->num_slots; j++) {
-+			memcpy_fromio(&edma_cc[i]->bkp_prm_set[j],
-+				edmacc_regs_base[i] + PARM_OFFSET(j),
-+				PARM_SIZE);
-+		}
-+	}
-+
-+	pm_runtime_put_sync(&pdev->dev);
-+
-+	return 0;
-+}
-+
-+static int edma3_resume(struct platform_device *pdev)
-+{
-+	int i, j;
-+
-+	pm_runtime_get_sync(&pdev->dev);
-+
-+	for (i = 0; i < arch_num_cc; i++) {
-+
-+		/* restore channel data */
-+		for (j = 0; j < edma_cc[i]->num_channels; j++) {
-+			edma_write_array(i, EDMA_DCHMAP, j,
-+						edma_cc[i]->bkp_ch_map[j]);
-+		}
-+
-+		/* restore DMA Queue Number */
-+		for (j = 0; j < 8; j++) {
-+			edma_write_array(i, EDMA_DMAQNUM, j,
-+						edma_cc[i]->bkp_que_num[j]);
-+		}
-+
-+		for (j = 0; j < edma_cc[i]->num_region; j++) {
-+			/* restore DMA DMA Region Access Enable data */
-+			edma_write_array2(i, EDMA_DRAE, j, 0,
-+						edma_cc[i]->bkp_drae[j]);
-+			edma_write_array2(i, EDMA_DRAE, j, 1,
-+						edma_cc[i]->bkp_draeh[j]);
-+
-+			/* restore DMA QDMA Region Access Enable data */
-+			edma_write_array(i, EDMA_QRAE, j,
-+						edma_cc[i]->bkp_qrae[j]);
-+		}
-+
-+		/* restore DMA shadow Event Set data */
-+		edma_shadow0_write_array(i, SH_ESR, 0, edma_cc[i]->bkp_sh_esr);
-+		edma_shadow0_write_array(i, SH_ESR, 1, edma_cc[i]->bkp_sh_esrh);
-+
-+		/* restore DMA Shadow Event Enable Set data */
-+		edma_shadow0_write_array(i, SH_EESR, 0,
-+						edma_cc[i]->bkp_sh_eesr);
-+		edma_shadow0_write_array(i, SH_EESR, 1,
-+						edma_cc[i]->bkp_sh_eesrh);
-+
-+		/* restore DMA Shadow Interrupt Enable Set data */
-+		edma_shadow0_write_array(i, SH_IESR, 0,
-+						edma_cc[i]->bkp_sh_iesr);
-+		edma_shadow0_write_array(i, SH_IESR, 1,
-+						edma_cc[i]->bkp_sh_iesrh);
-+
-+		edma_write(i, EDMA_QUETCMAP, edma_cc[i]->bkp_que_tc_map);
-+
-+		/* restore DMA Queue Priority data */
-+		edma_write(i, EDMA_QUEPRI, edma_cc[i]->bkp_que_pri);
-+
-+		/* restore paramset */
-+		for (j = 0; j < edma_cc[i]->num_slots; j++) {
-+			memcpy_toio(edmacc_regs_base[i] + PARM_OFFSET(j),
-+				&edma_cc[i]->bkp_prm_set[j], PARM_SIZE);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+#else
-+#define edma3_suspend	NULL
-+#define edma3_resume		NULL
-+#endif
-+
-+static struct platform_driver edma_driver = {
-+	.driver.name	= "edma",
-+	.suspend	= edma3_suspend,
-+	.resume		= edma3_resume,
-+};
-+
-+static int __init edma_init(void)
-+{
-+	return platform_driver_probe(&edma_driver, edma_probe);
-+}
-+subsys_initcall(edma_init);
-diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
-index 410a546..b2dc2dd 100644
---- a/arch/arm/common/gic.c
-+++ b/arch/arm/common/gic.c
-@@ -40,13 +40,36 @@
- #include <linux/slab.h>
- 
- #include <asm/irq.h>
-+#include <asm/exception.h>
- #include <asm/mach/irq.h>
- #include <asm/hardware/gic.h>
- 
--static DEFINE_RAW_SPINLOCK(irq_controller_lock);
-+union gic_base {
-+	void __iomem *common_base;
-+	void __percpu __iomem **percpu_base;
-+};
- 
--/* Address of GIC 0 CPU interface */
--void __iomem *gic_cpu_base_addr __read_mostly;
-+struct gic_chip_data {
-+	unsigned int irq_offset;
-+	union gic_base dist_base;
-+	union gic_base cpu_base;
-+#ifdef CONFIG_CPU_PM
-+	u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
-+	u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
-+	u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
-+	u32 __percpu *saved_ppi_enable;
-+	u32 __percpu *saved_ppi_conf;
-+#endif
-+#ifdef CONFIG_IRQ_DOMAIN
-+	struct irq_domain domain;
-+#endif
-+	unsigned int gic_irqs;
-+#ifdef CONFIG_GIC_NON_BANKED
-+	void __iomem *(*get_base)(union gic_base *);
-+#endif
-+};
-+
-+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
- 
- /*
-  * Supported arch specific GIC irq extension.
-@@ -67,16 +90,48 @@ struct irq_chip gic_arch_extn = {
- 
- static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
- 
-+#ifdef CONFIG_GIC_NON_BANKED
-+static void __iomem *gic_get_percpu_base(union gic_base *base)
-+{
-+	return *__this_cpu_ptr(base->percpu_base);
-+}
-+
-+static void __iomem *gic_get_common_base(union gic_base *base)
-+{
-+	return base->common_base;
-+}
-+
-+static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
-+{
-+	return data->get_base(&data->dist_base);
-+}
-+
-+static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
-+{
-+	return data->get_base(&data->cpu_base);
-+}
-+
-+static inline void gic_set_base_accessor(struct gic_chip_data *data,
-+					 void __iomem *(*f)(union gic_base *))
-+{
-+	data->get_base = f;
-+}
-+#else
-+#define gic_data_dist_base(d)	((d)->dist_base.common_base)
-+#define gic_data_cpu_base(d)	((d)->cpu_base.common_base)
-+#define gic_set_base_accessor(d,f)
-+#endif
-+
- static inline void __iomem *gic_dist_base(struct irq_data *d)
- {
- 	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
--	return gic_data->dist_base;
-+	return gic_data_dist_base(gic_data);
- }
- 
- static inline void __iomem *gic_cpu_base(struct irq_data *d)
- {
- 	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
--	return gic_data->cpu_base;
-+	return gic_data_cpu_base(gic_data);
- }
- 
- static inline unsigned int gic_irq(struct irq_data *d)
-@@ -215,6 +270,32 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
- #define gic_set_wake	NULL
- #endif
- 
-+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
-+{
-+	u32 irqstat, irqnr;
-+	struct gic_chip_data *gic = &gic_data[0];
-+	void __iomem *cpu_base = gic_data_cpu_base(gic);
-+
-+	do {
-+		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
-+		irqnr = irqstat & ~0x1c00;
-+
-+		if (likely(irqnr > 15 && irqnr < 1021)) {
-+			irqnr = irq_domain_to_irq(&gic->domain, irqnr);
-+			handle_IRQ(irqnr, regs);
-+			continue;
-+		}
-+		if (irqnr < 16) {
-+			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
-+#ifdef CONFIG_SMP
-+			handle_IPI(irqnr, regs);
-+#endif
-+			continue;
-+		}
-+		break;
-+	} while (1);
-+}
-+
- static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
- {
- 	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
-@@ -225,7 +306,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
- 	chained_irq_enter(chip, desc);
- 
- 	raw_spin_lock(&irq_controller_lock);
--	status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
-+	status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
- 	raw_spin_unlock(&irq_controller_lock);
- 
- 	gic_irq = (status & 0x3ff);
-@@ -270,7 +351,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
- 	u32 cpumask;
- 	unsigned int gic_irqs = gic->gic_irqs;
- 	struct irq_domain *domain = &gic->domain;
--	void __iomem *base = gic->dist_base;
-+	void __iomem *base = gic_data_dist_base(gic);
- 	u32 cpu = 0;
- 
- #ifdef CONFIG_SMP
-@@ -330,8 +411,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
- 
- static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
- {
--	void __iomem *dist_base = gic->dist_base;
--	void __iomem *base = gic->cpu_base;
-+	void __iomem *dist_base = gic_data_dist_base(gic);
-+	void __iomem *base = gic_data_cpu_base(gic);
- 	int i;
- 
- 	/*
-@@ -368,7 +449,7 @@ static void gic_dist_save(unsigned int gic_nr)
- 		BUG();
- 
- 	gic_irqs = gic_data[gic_nr].gic_irqs;
--	dist_base = gic_data[gic_nr].dist_base;
-+	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
- 
- 	if (!dist_base)
- 		return;
-@@ -403,7 +484,7 @@ static void gic_dist_restore(unsigned int gic_nr)
- 		BUG();
- 
- 	gic_irqs = gic_data[gic_nr].gic_irqs;
--	dist_base = gic_data[gic_nr].dist_base;
-+	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
- 
- 	if (!dist_base)
- 		return;
-@@ -439,8 +520,8 @@ static void gic_cpu_save(unsigned int gic_nr)
- 	if (gic_nr >= MAX_GIC_NR)
- 		BUG();
- 
--	dist_base = gic_data[gic_nr].dist_base;
--	cpu_base = gic_data[gic_nr].cpu_base;
-+	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-+	cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
- 
- 	if (!dist_base || !cpu_base)
- 		return;
-@@ -465,8 +546,8 @@ static void gic_cpu_restore(unsigned int gic_nr)
- 	if (gic_nr >= MAX_GIC_NR)
- 		BUG();
- 
--	dist_base = gic_data[gic_nr].dist_base;
--	cpu_base = gic_data[gic_nr].cpu_base;
-+	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-+	cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
- 
- 	if (!dist_base || !cpu_base)
- 		return;
-@@ -491,6 +572,11 @@ static int gic_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
- 	int i;
- 
- 	for (i = 0; i < MAX_GIC_NR; i++) {
-+#ifdef CONFIG_GIC_NON_BANKED
-+		/* Skip over unused GICs */
-+		if (!gic_data[i].get_base)
-+			continue;
-+#endif
- 		switch (cmd) {
- 		case CPU_PM_ENTER:
- 			gic_cpu_save(i);
-@@ -564,8 +650,9 @@ const struct irq_domain_ops gic_irq_domain_ops = {
- #endif
- };
- 
--void __init gic_init(unsigned int gic_nr, int irq_start,
--	void __iomem *dist_base, void __iomem *cpu_base)
-+void __init gic_init_bases(unsigned int gic_nr, int irq_start,
-+			   void __iomem *dist_base, void __iomem *cpu_base,
-+			   u32 percpu_offset)
- {
- 	struct gic_chip_data *gic;
- 	struct irq_domain *domain;
-@@ -575,8 +662,36 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
- 
- 	gic = &gic_data[gic_nr];
- 	domain = &gic->domain;
--	gic->dist_base = dist_base;
--	gic->cpu_base = cpu_base;
-+#ifdef CONFIG_GIC_NON_BANKED
-+	if (percpu_offset) { /* Frankein-GIC without banked registers... */
-+		unsigned int cpu;
-+
-+		gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
-+		gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
-+		if (WARN_ON(!gic->dist_base.percpu_base ||
-+			    !gic->cpu_base.percpu_base)) {
-+			free_percpu(gic->dist_base.percpu_base);
-+			free_percpu(gic->cpu_base.percpu_base);
-+			return;
-+		}
-+
-+		for_each_possible_cpu(cpu) {
-+			unsigned long offset = percpu_offset * cpu_logical_map(cpu);
-+			*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
-+			*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
-+		}
-+
-+		gic_set_base_accessor(gic, gic_get_percpu_base);
-+	} else
-+#endif
-+	{			/* Normal, sane GIC... */
-+		WARN(percpu_offset,
-+		     "GIC_NON_BANKED not enabled, ignoring %08x offset!",
-+		     percpu_offset);
-+		gic->dist_base.common_base = dist_base;
-+		gic->cpu_base.common_base = cpu_base;
-+		gic_set_base_accessor(gic, gic_get_common_base);
-+	}
- 
- 	/*
- 	 * For primary GICs, skip over SGIs.
-@@ -584,8 +699,6 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
- 	 */
- 	domain->hwirq_base = 32;
- 	if (gic_nr == 0) {
--		gic_cpu_base_addr = cpu_base;
--
- 		if ((irq_start & 31) > 0) {
- 			domain->hwirq_base = 16;
- 			if (irq_start != -1)
-@@ -597,7 +710,7 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
- 	 * Find out how many interrupts are supported.
- 	 * The GIC only supports up to 1020 interrupt sources.
- 	 */
--	gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
-+	gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
- 	gic_irqs = (gic_irqs + 1) * 32;
- 	if (gic_irqs > 1020)
- 		gic_irqs = 1020;
-@@ -645,7 +758,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
- 	dsb();
- 
- 	/* this always happens on GIC0 */
--	writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
-+	writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
- }
- #endif
- 
-@@ -656,6 +769,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
- {
- 	void __iomem *cpu_base;
- 	void __iomem *dist_base;
-+	u32 percpu_offset;
- 	int irq;
- 	struct irq_domain *domain = &gic_data[gic_cnt].domain;
- 
-@@ -668,9 +782,12 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
- 	cpu_base = of_iomap(node, 1);
- 	WARN(!cpu_base, "unable to map gic cpu registers\n");
- 
-+	if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
-+		percpu_offset = 0;
-+
- 	domain->of_node = of_node_get(node);
- 
--	gic_init(gic_cnt, -1, dist_base, cpu_base);
-+	gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
- 
- 	if (parent) {
- 		irq = irq_of_parse_and_map(node, 0);
-diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
-index 01f18a4..6ed41ec 100644
---- a/arch/arm/common/vic.c
-+++ b/arch/arm/common/vic.c
-@@ -19,17 +19,22 @@
-  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-  */
- 
-+#include <linux/export.h>
- #include <linux/init.h>
- #include <linux/list.h>
- #include <linux/io.h>
-+#include <linux/irqdomain.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
- #include <linux/syscore_ops.h>
- #include <linux/device.h>
- #include <linux/amba/bus.h>
- 
-+#include <asm/exception.h>
- #include <asm/mach/irq.h>
- #include <asm/hardware/vic.h>
- 
--#ifdef CONFIG_PM
- /**
-  * struct vic_device - VIC PM device
-  * @irq: The IRQ number for the base of the VIC.
-@@ -40,6 +45,7 @@
-  * @int_enable: Save for VIC_INT_ENABLE.
-  * @soft_int: Save for VIC_INT_SOFT.
-  * @protect: Save for VIC_PROTECT.
-+ * @domain: The IRQ domain for the VIC.
-  */
- struct vic_device {
- 	void __iomem	*base;
-@@ -50,13 +56,13 @@ struct vic_device {
- 	u32		int_enable;
- 	u32		soft_int;
- 	u32		protect;
-+	struct irq_domain domain;
- };
- 
- /* we cannot allocate memory when VICs are initially registered */
- static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
- 
- static int vic_id;
--#endif /* CONFIG_PM */
- 
- /**
-  * vic_init2 - common initialisation code
-@@ -156,39 +162,50 @@ static int __init vic_pm_init(void)
- 	return 0;
- }
- late_initcall(vic_pm_init);
-+#endif /* CONFIG_PM */
- 
- /**
-- * vic_pm_register - Register a VIC for later power management control
-+ * vic_register() - Register a VIC.
-  * @base: The base address of the VIC.
-  * @irq: The base IRQ for the VIC.
-  * @resume_sources: bitmask of interrupts allowed for resume sources.
-+ * @node: The device tree node associated with the VIC.
-  *
-  * Register the VIC with the system device tree so that it can be notified
-  * of suspend and resume requests and ensure that the correct actions are
-  * taken to re-instate the settings on resume.
-+ *
-+ * This also configures the IRQ domain for the VIC.
-  */
--static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
-+static void __init vic_register(void __iomem *base, unsigned int irq,
-+				u32 resume_sources, struct device_node *node)
- {
- 	struct vic_device *v;
- 
--	if (vic_id >= ARRAY_SIZE(vic_devices))
-+	if (vic_id >= ARRAY_SIZE(vic_devices)) {
- 		printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
--	else {
--		v = &vic_devices[vic_id];
--		v->base = base;
--		v->resume_sources = resume_sources;
--		v->irq = irq;
--		vic_id++;
-+		return;
- 	}
-+
-+	v = &vic_devices[vic_id];
-+	v->base = base;
-+	v->resume_sources = resume_sources;
-+	v->irq = irq;
-+	vic_id++;
-+
-+	v->domain.irq_base = irq;
-+	v->domain.nr_irq = 32;
-+#ifdef CONFIG_OF_IRQ
-+	v->domain.of_node = of_node_get(node);
-+	v->domain.ops = &irq_domain_simple_ops;
-+#endif /* CONFIG_OF */
-+	irq_domain_add(&v->domain);
- }
--#else
--static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
--#endif /* CONFIG_PM */
- 
- static void vic_ack_irq(struct irq_data *d)
- {
- 	void __iomem *base = irq_data_get_irq_chip_data(d);
--	unsigned int irq = d->irq & 31;
-+	unsigned int irq = d->hwirq;
- 	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
- 	/* moreover, clear the soft-triggered, in case it was the reason */
- 	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
-@@ -197,14 +214,14 @@ static void vic_ack_irq(struct irq_data *d)
- static void vic_mask_irq(struct irq_data *d)
- {
- 	void __iomem *base = irq_data_get_irq_chip_data(d);
--	unsigned int irq = d->irq & 31;
-+	unsigned int irq = d->hwirq;
- 	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
- }
- 
- static void vic_unmask_irq(struct irq_data *d)
- {
- 	void __iomem *base = irq_data_get_irq_chip_data(d);
--	unsigned int irq = d->irq & 31;
-+	unsigned int irq = d->hwirq;
- 	writel(1 << irq, base + VIC_INT_ENABLE);
- }
- 
-@@ -226,7 +243,7 @@ static struct vic_device *vic_from_irq(unsigned int irq)
- static int vic_set_wake(struct irq_data *d, unsigned int on)
- {
- 	struct vic_device *v = vic_from_irq(d->irq);
--	unsigned int off = d->irq & 31;
-+	unsigned int off = d->hwirq;
- 	u32 bit = 1 << off;
- 
- 	if (!v)
-@@ -330,15 +347,9 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
- 	vic_set_irq_sources(base, irq_start, vic_sources);
- }
- 
--/**
-- * vic_init - initialise a vectored interrupt controller
-- * @base: iomem base address
-- * @irq_start: starting interrupt number, must be muliple of 32
-- * @vic_sources: bitmask of interrupt sources to allow
-- * @resume_sources: bitmask of interrupt sources to allow for resume
-- */
--void __init vic_init(void __iomem *base, unsigned int irq_start,
--		     u32 vic_sources, u32 resume_sources)
-+static void __init __vic_init(void __iomem *base, unsigned int irq_start,
-+			      u32 vic_sources, u32 resume_sources,
-+			      struct device_node *node)
- {
- 	unsigned int i;
- 	u32 cellid = 0;
-@@ -375,5 +386,81 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
- 
- 	vic_set_irq_sources(base, irq_start, vic_sources);
- 
--	vic_pm_register(base, irq_start, resume_sources);
-+	vic_register(base, irq_start, resume_sources, node);
-+}
-+
-+/**
-+ * vic_init() - initialise a vectored interrupt controller
-+ * @base: iomem base address
-+ * @irq_start: starting interrupt number, must be muliple of 32
-+ * @vic_sources: bitmask of interrupt sources to allow
-+ * @resume_sources: bitmask of interrupt sources to allow for resume
-+ */
-+void __init vic_init(void __iomem *base, unsigned int irq_start,
-+		     u32 vic_sources, u32 resume_sources)
-+{
-+	__vic_init(base, irq_start, vic_sources, resume_sources, NULL);
-+}
-+
-+#ifdef CONFIG_OF
-+int __init vic_of_init(struct device_node *node, struct device_node *parent)
-+{
-+	void __iomem *regs;
-+	int irq_base;
-+
-+	if (WARN(parent, "non-root VICs are not supported"))
-+		return -EINVAL;
-+
-+	regs = of_iomap(node, 0);
-+	if (WARN_ON(!regs))
-+		return -EIO;
-+
-+	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
-+	if (WARN_ON(irq_base < 0))
-+		goto out_unmap;
-+
-+	__vic_init(regs, irq_base, ~0, ~0, node);
-+
-+	return 0;
-+
-+ out_unmap:
-+	iounmap(regs);
-+
-+	return -EIO;
-+}
-+#endif /* CONFIG OF */
-+
-+/*
-+ * Handle each interrupt in a single VIC.  Returns non-zero if we've
-+ * handled at least one interrupt.  This does a single read of the
-+ * status register and handles all interrupts in order from LSB first.
-+ */
-+static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
-+{
-+	u32 stat, irq;
-+	int handled = 0;
-+
-+	stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
-+	while (stat) {
-+		irq = ffs(stat) - 1;
-+		handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
-+		stat &= ~(1 << irq);
-+		handled = 1;
-+	}
-+
-+	return handled;
-+}
-+
-+/*
-+ * Keep iterating over all registered VIC's until there are no pending
-+ * interrupts.
-+ */
-+asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
-+{
-+	int i, handled;
-+
-+	do {
-+		for (i = 0, handled = 0; i < vic_id; ++i)
-+			handled |= handle_one_vic(&vic_devices[i], regs);
-+	} while (handled);
- }
-diff --git a/arch/arm/configs/am335x_evm_defconfig b/arch/arm/configs/am335x_evm_defconfig
-new file mode 100644
-index 0000000..56d8b10
---- /dev/null
-+++ b/arch/arm/configs/am335x_evm_defconfig
-@@ -0,0 +1,2602 @@
-+#
-+# Automatically generated file; DO NOT EDIT.
-+# Linux/arm 3.2.0 Kernel Configuration
-+#
-+CONFIG_ARM=y
-+CONFIG_HAVE_PWM=y
-+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-+CONFIG_HAVE_SCHED_CLOCK=y
-+CONFIG_GENERIC_GPIO=y
-+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+CONFIG_KTIME_SCALAR=y
-+CONFIG_HAVE_PROC_CPU=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_ARCH_HAS_CPUFREQ=y
-+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_NEED_DMA_MAP_STATE=y
-+CONFIG_VECTORS_BASE=0xffff0000
-+CONFIG_ARM_PATCH_PHYS_VIRT=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+CONFIG_HAVE_IRQ_WORK=y
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_CROSS_COMPILE=""
-+CONFIG_LOCALVERSION=""
-+CONFIG_LOCALVERSION_AUTO=y
-+CONFIG_HAVE_KERNEL_GZIP=y
-+CONFIG_HAVE_KERNEL_LZMA=y
-+CONFIG_HAVE_KERNEL_LZO=y
-+CONFIG_KERNEL_GZIP=y
-+# CONFIG_KERNEL_LZMA is not set
-+# CONFIG_KERNEL_LZO is not set
-+CONFIG_DEFAULT_HOSTNAME="(none)"
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_POSIX_MQUEUE_SYSCTL=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-+# CONFIG_FHANDLE is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+CONFIG_HAVE_GENERIC_HARDIRQS=y
-+
-+#
-+# IRQ subsystem
-+#
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_HAVE_SPARSE_IRQ=y
-+CONFIG_GENERIC_IRQ_SHOW=y
-+CONFIG_GENERIC_IRQ_CHIP=y
-+CONFIG_IRQ_DOMAIN=y
-+# CONFIG_SPARSE_IRQ is not set
-+
-+#
-+# RCU Subsystem
-+#
-+CONFIG_TINY_RCU=y
-+# CONFIG_PREEMPT_RCU is not set
-+# CONFIG_RCU_TRACE is not set
-+# CONFIG_TREE_RCU_TRACE is not set
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_LOG_BUF_SHIFT=16
-+# CONFIG_CGROUPS is not set
-+CONFIG_NAMESPACES=y
-+CONFIG_UTS_NS=y
-+CONFIG_IPC_NS=y
-+CONFIG_USER_NS=y
-+CONFIG_PID_NS=y
-+CONFIG_NET_NS=y
-+# CONFIG_SCHED_AUTOGROUP is not set
-+# CONFIG_SYSFS_DEPRECATED is not set
-+# CONFIG_RELAY is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_RD_GZIP=y
-+CONFIG_RD_BZIP2=y
-+CONFIG_RD_LZMA=y
-+CONFIG_RD_XZ=y
-+CONFIG_RD_LZO=y
-+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-+CONFIG_SYSCTL=y
-+CONFIG_ANON_INODES=y
-+# CONFIG_EXPERT is not set
-+CONFIG_UID16=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+CONFIG_BASE_FULL=y
-+CONFIG_FUTEX=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_AIO=y
-+# CONFIG_EMBEDDED is not set
-+CONFIG_HAVE_PERF_EVENTS=y
-+CONFIG_PERF_USE_VMALLOC=y
-+
-+#
-+# Kernel Performance Events And Counters
-+#
-+# CONFIG_PERF_EVENTS is not set
-+# CONFIG_PERF_COUNTERS is not set
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_COMPAT_BRK=y
-+CONFIG_SLAB=y
-+# CONFIG_SLUB is not set
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=y
-+CONFIG_HAVE_OPROFILE=y
-+# CONFIG_KPROBES is not set
-+CONFIG_HAVE_KPROBES=y
-+CONFIG_HAVE_KRETPROBES=y
-+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-+CONFIG_HAVE_CLK=y
-+CONFIG_HAVE_DMA_API_DEBUG=y
-+
-+#
-+# GCOV-based kernel profiling
-+#
-+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+CONFIG_BASE_SMALL=0
-+CONFIG_MODULES=y
-+CONFIG_MODULE_FORCE_LOAD=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODULE_FORCE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_BLOCK=y
-+CONFIG_LBDAF=y
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_BSGLIB is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+CONFIG_IOSCHED_DEADLINE=y
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+# CONFIG_INLINE_SPIN_TRYLOCK is not set
-+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-+# CONFIG_INLINE_SPIN_LOCK is not set
-+# CONFIG_INLINE_SPIN_LOCK_BH is not set
-+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-+CONFIG_INLINE_SPIN_UNLOCK=y
-+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
-+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-+# CONFIG_INLINE_READ_TRYLOCK is not set
-+# CONFIG_INLINE_READ_LOCK is not set
-+# CONFIG_INLINE_READ_LOCK_BH is not set
-+# CONFIG_INLINE_READ_LOCK_IRQ is not set
-+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-+CONFIG_INLINE_READ_UNLOCK=y
-+# CONFIG_INLINE_READ_UNLOCK_BH is not set
-+CONFIG_INLINE_READ_UNLOCK_IRQ=y
-+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-+# CONFIG_INLINE_WRITE_TRYLOCK is not set
-+# CONFIG_INLINE_WRITE_LOCK is not set
-+# CONFIG_INLINE_WRITE_LOCK_BH is not set
-+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-+CONFIG_INLINE_WRITE_UNLOCK=y
-+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
-+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
-+CONFIG_FREEZER=y
-+
-+#
-+# System Type
-+#
-+CONFIG_MMU=y
-+# CONFIG_ARCH_INTEGRATOR is not set
-+# CONFIG_ARCH_REALVIEW is not set
-+# CONFIG_ARCH_VERSATILE is not set
-+# CONFIG_ARCH_VEXPRESS is not set
-+# CONFIG_ARCH_AT91 is not set
-+# CONFIG_ARCH_BCMRING is not set
-+# CONFIG_ARCH_HIGHBANK is not set
-+# CONFIG_ARCH_CLPS711X is not set
-+# CONFIG_ARCH_CNS3XXX is not set
-+# CONFIG_ARCH_GEMINI is not set
-+# CONFIG_ARCH_PRIMA2 is not set
-+# CONFIG_ARCH_EBSA110 is not set
-+# CONFIG_ARCH_EP93XX is not set
-+# CONFIG_ARCH_FOOTBRIDGE is not set
-+# CONFIG_ARCH_MXC is not set
-+# CONFIG_ARCH_MXS is not set
-+# CONFIG_ARCH_NETX is not set
-+# CONFIG_ARCH_H720X is not set
-+# CONFIG_ARCH_IOP13XX is not set
-+# CONFIG_ARCH_IOP32X is not set
-+# CONFIG_ARCH_IOP33X is not set
-+# CONFIG_ARCH_IXP23XX is not set
-+# CONFIG_ARCH_IXP2000 is not set
-+# CONFIG_ARCH_IXP4XX is not set
-+# CONFIG_ARCH_DOVE is not set
-+# CONFIG_ARCH_KIRKWOOD is not set
-+# CONFIG_ARCH_LPC32XX is not set
-+# CONFIG_ARCH_MV78XX0 is not set
-+# CONFIG_ARCH_ORION5X is not set
-+# CONFIG_ARCH_MMP is not set
-+# CONFIG_ARCH_KS8695 is not set
-+# CONFIG_ARCH_W90X900 is not set
-+# CONFIG_ARCH_TEGRA is not set
-+# CONFIG_ARCH_PICOXCELL is not set
-+# CONFIG_ARCH_PNX4008 is not set
-+# CONFIG_ARCH_PXA is not set
-+# CONFIG_ARCH_MSM is not set
-+# CONFIG_ARCH_SHMOBILE is not set
-+# CONFIG_ARCH_RPC is not set
-+# CONFIG_ARCH_SA1100 is not set
-+# CONFIG_ARCH_S3C2410 is not set
-+# CONFIG_ARCH_S3C64XX is not set
-+# CONFIG_ARCH_S5P64X0 is not set
-+# CONFIG_ARCH_S5PC100 is not set
-+# CONFIG_ARCH_S5PV210 is not set
-+# CONFIG_ARCH_EXYNOS is not set
-+# CONFIG_ARCH_SHARK is not set
-+# CONFIG_ARCH_TCC_926 is not set
-+# CONFIG_ARCH_U300 is not set
-+# CONFIG_ARCH_U8500 is not set
-+# CONFIG_ARCH_NOMADIK is not set
-+# CONFIG_ARCH_DAVINCI is not set
-+CONFIG_ARCH_OMAP=y
-+# CONFIG_PLAT_SPEAR is not set
-+# CONFIG_ARCH_VT8500 is not set
-+# CONFIG_ARCH_ZYNQ is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_KEYBOARD_GPIO_POLLED is not set
-+
-+#
-+# TI OMAP Common Features
-+#
-+# CONFIG_ARCH_OMAP1 is not set
-+CONFIG_ARCH_OMAP2PLUS=y
-+
-+#
-+# OMAP Feature Selections
-+#
-+# CONFIG_OMAP_SMARTREFLEX is not set
-+CONFIG_OMAP_RESET_CLOCKS=y
-+CONFIG_OMAP_MUX=y
-+CONFIG_OMAP_MUX_DEBUG=y
-+CONFIG_OMAP_MUX_WARNINGS=y
-+# CONFIG_OMAP_MCBSP is not set
-+CONFIG_OMAP_MBOX_FWK=y
-+CONFIG_OMAP_MBOX_KFIFO_SIZE=256
-+# CONFIG_OMAP_32K_TIMER is not set
-+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
-+CONFIG_OMAP_DM_TIMER=y
-+CONFIG_OMAP_PM_NOOP=y
-+CONFIG_MACH_OMAP_GENERIC=y
-+
-+#
-+# TI OMAP2/3/4 Specific Features
-+#
-+CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
-+# CONFIG_ARCH_OMAP2 is not set
-+CONFIG_ARCH_OMAP3=y
-+# CONFIG_ARCH_OMAP4 is not set
-+# CONFIG_SOC_OMAP3430 is not set
-+CONFIG_SOC_OMAPTI81XX=y
-+CONFIG_SOC_OMAPAM33XX=y
-+CONFIG_OMAP_PACKAGE_CBB=y
-+
-+#
-+# OMAP Board Type
-+#
-+CONFIG_MACH_OMAP3_BEAGLE=y
-+# CONFIG_MACH_DEVKIT8000 is not set
-+# CONFIG_MACH_OMAP_LDP is not set
-+# CONFIG_MACH_OMAP3530_LV_SOM is not set
-+# CONFIG_MACH_OMAP3_TORPEDO is not set
-+# CONFIG_MACH_ENCORE is not set
-+# CONFIG_MACH_OVERO is not set
-+# CONFIG_MACH_OMAP3EVM is not set
-+# CONFIG_MACH_OMAP3517EVM is not set
-+# CONFIG_MACH_CRANEBOARD is not set
-+# CONFIG_MACH_OMAP3_PANDORA is not set
-+# CONFIG_MACH_OMAP3_TOUCHBOOK is not set
-+# CONFIG_MACH_OMAP_3430SDP is not set
-+# CONFIG_MACH_NOKIA_RM680 is not set
-+# CONFIG_MACH_NOKIA_RX51 is not set
-+# CONFIG_MACH_OMAP_ZOOM2 is not set
-+# CONFIG_MACH_OMAP_ZOOM3 is not set
-+# CONFIG_MACH_CM_T35 is not set
-+# CONFIG_MACH_CM_T3517 is not set
-+# CONFIG_MACH_IGEP0020 is not set
-+# CONFIG_MACH_IGEP0030 is not set
-+# CONFIG_MACH_SBC3530 is not set
-+# CONFIG_MACH_OMAP_3630SDP is not set
-+CONFIG_MACH_TI8168EVM=y
-+CONFIG_MACH_TI8148EVM=y
-+CONFIG_MACH_AM335XEVM=y
-+CONFIG_MACH_AM335XIAEVM=y
-+# CONFIG_OMAP3_EMU is not set
-+# CONFIG_OMAP3_SDRC_AC_TIMING is not set
-+CONFIG_OMAP3_EDMA=y
-+
-+#
-+# System MMU
-+#
-+
-+#
-+# Processor Type
-+#
-+CONFIG_CPU_V7=y
-+CONFIG_CPU_32v6K=y
-+CONFIG_CPU_32v7=y
-+CONFIG_CPU_ABRT_EV7=y
-+CONFIG_CPU_PABRT_V7=y
-+CONFIG_CPU_CACHE_V7=y
-+CONFIG_CPU_CACHE_VIPT=y
-+CONFIG_CPU_COPY_V6=y
-+CONFIG_CPU_TLB_V7=y
-+CONFIG_CPU_HAS_ASID=y
-+CONFIG_CPU_CP15=y
-+CONFIG_CPU_CP15_MMU=y
-+
-+#
-+# Processor Features
-+#
-+CONFIG_ARM_THUMB=y
-+CONFIG_ARM_THUMBEE=y
-+# CONFIG_SWP_EMULATE is not set
-+# CONFIG_CPU_ICACHE_DISABLE is not set
-+# CONFIG_CPU_DCACHE_DISABLE is not set
-+# CONFIG_CPU_BPREDICT_DISABLE is not set
-+CONFIG_ARM_L1_CACHE_SHIFT_6=y
-+CONFIG_ARM_L1_CACHE_SHIFT=6
-+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-+CONFIG_MULTI_IRQ_HANDLER=y
-+# CONFIG_ARM_ERRATA_430973 is not set
-+# CONFIG_ARM_ERRATA_458693 is not set
-+# CONFIG_ARM_ERRATA_460075 is not set
-+# CONFIG_ARM_ERRATA_720789 is not set
-+# CONFIG_ARM_ERRATA_743622 is not set
-+# CONFIG_ARM_ERRATA_751472 is not set
-+# CONFIG_ARM_ERRATA_754322 is not set
-+
-+#
-+# Bus support
-+#
-+# CONFIG_PCI_SYSCALL is not set
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Kernel Features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_VMSPLIT_3G=y
-+# CONFIG_VMSPLIT_2G is not set
-+# CONFIG_VMSPLIT_1G is not set
-+CONFIG_PAGE_OFFSET=0xC0000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_HZ=100
-+# CONFIG_THUMB2_KERNEL is not set
-+CONFIG_AEABI=y
-+CONFIG_OABI_COMPAT=y
-+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-+CONFIG_HAVE_ARCH_PFN_VALID=y
-+# CONFIG_HIGHMEM is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+CONFIG_HAVE_MEMBLOCK=y
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_COMPACTION is not set
-+# CONFIG_PHYS_ADDR_T_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_KSM is not set
-+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-+CONFIG_NEED_PER_CPU_KM=y
-+# CONFIG_CLEANCACHE is not set
-+CONFIG_FORCE_MAX_ZONEORDER=11
-+# CONFIG_LEDS is not set
-+CONFIG_ALIGNMENT_TRAP=y
-+# CONFIG_UACCESS_WITH_MEMCPY is not set
-+# CONFIG_SECCOMP is not set
-+# CONFIG_CC_STACKPROTECTOR is not set
-+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-+
-+#
-+# Boot options
-+#
-+CONFIG_USE_OF=y
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+# CONFIG_ARM_APPENDED_DTB is not set
-+CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO0,115200"
-+CONFIG_CMDLINE_FROM_BOOTLOADER=y
-+# CONFIG_CMDLINE_EXTEND is not set
-+# CONFIG_CMDLINE_FORCE is not set
-+# CONFIG_XIP_KERNEL is not set
-+# CONFIG_KEXEC is not set
-+# CONFIG_CRASH_DUMP is not set
-+# CONFIG_AUTO_ZRELADDR is not set
-+
-+#
-+# CPU Power Management
-+#
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+CONFIG_CPU_FREQ_STAT=y
-+CONFIG_CPU_FREQ_STAT_DETAILS=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+
-+#
-+# ARM CPU frequency scaling drivers
-+#
-+CONFIG_CPU_IDLE=y
-+CONFIG_CPU_IDLE_GOV_LADDER=y
-+CONFIG_CPU_IDLE_GOV_MENU=y
-+
-+#
-+# Floating point emulation
-+#
-+
-+#
-+# At least one emulation must be selected
-+#
-+CONFIG_FPE_NWFPE=y
-+# CONFIG_FPE_NWFPE_XP is not set
-+# CONFIG_FPE_FASTFPE is not set
-+CONFIG_VFP=y
-+CONFIG_VFPv3=y
-+CONFIG_NEON=y
-+
-+#
-+# Userspace binary formats
-+#
-+CONFIG_BINFMT_ELF=y
-+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-+CONFIG_HAVE_AOUT=y
-+# CONFIG_BINFMT_AOUT is not set
-+CONFIG_BINFMT_MISC=y
-+
-+#
-+# Power management options
-+#
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_PM_SLEEP=y
-+CONFIG_PM_RUNTIME=y
-+CONFIG_PM=y
-+CONFIG_PM_DEBUG=y
-+CONFIG_PM_ADVANCED_DEBUG=y
-+# CONFIG_PM_TEST_SUSPEND is not set
-+CONFIG_CAN_PM_TRACE=y
-+# CONFIG_APM_EMULATION is not set
-+CONFIG_ARCH_HAS_OPP=y
-+CONFIG_PM_OPP=y
-+CONFIG_PM_CLK=y
-+CONFIG_CPU_PM=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+CONFIG_ARM_CPU_SUSPEND=y
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+# CONFIG_NET_KEY is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_BOOTP=y
-+CONFIG_IP_PNP_RARP=y
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE_DEMUX is not set
-+# CONFIG_IP_MROUTE is not set
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+# CONFIG_INET_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_BEET is not set
-+# CONFIG_INET_LRO is not set
-+# CONFIG_INET_DIAG is not set
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IPV6 is not set
-+# CONFIG_NETLABEL is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-+CONFIG_NETFILTER=y
-+# CONFIG_NETFILTER_DEBUG is not set
-+CONFIG_NETFILTER_ADVANCED=y
-+
-+#
-+# Core Netfilter Configuration
-+#
-+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
-+# CONFIG_NETFILTER_NETLINK_LOG is not set
-+CONFIG_NF_CONNTRACK=y
-+# CONFIG_NF_CONNTRACK_MARK is not set
-+# CONFIG_NF_CONNTRACK_EVENTS is not set
-+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
-+# CONFIG_NF_CT_PROTO_DCCP is not set
-+# CONFIG_NF_CT_PROTO_SCTP is not set
-+# CONFIG_NF_CT_PROTO_UDPLITE is not set
-+# CONFIG_NF_CONNTRACK_AMANDA is not set
-+# CONFIG_NF_CONNTRACK_FTP is not set
-+# CONFIG_NF_CONNTRACK_H323 is not set
-+# CONFIG_NF_CONNTRACK_IRC is not set
-+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
-+# CONFIG_NF_CONNTRACK_SNMP is not set
-+# CONFIG_NF_CONNTRACK_PPTP is not set
-+# CONFIG_NF_CONNTRACK_SANE is not set
-+# CONFIG_NF_CONNTRACK_SIP is not set
-+# CONFIG_NF_CONNTRACK_TFTP is not set
-+# CONFIG_NF_CT_NETLINK is not set
-+CONFIG_NETFILTER_XTABLES=y
-+
-+#
-+# Xtables combined modules
-+#
-+# CONFIG_NETFILTER_XT_MARK is not set
-+# CONFIG_NETFILTER_XT_CONNMARK is not set
-+
-+#
-+# Xtables targets
-+#
-+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
-+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
-+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
-+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
-+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
-+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
-+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
-+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
-+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
-+
-+#
-+# Xtables matches
-+#
-+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
-+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
-+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
-+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
-+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
-+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
-+# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
-+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
-+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
-+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
-+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
-+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
-+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
-+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
-+# CONFIG_NETFILTER_XT_MATCH_HL is not set
-+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
-+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
-+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
-+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
-+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
-+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
-+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
-+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
-+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
-+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
-+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
-+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
-+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
-+# CONFIG_NETFILTER_XT_MATCH_STATE is not set
-+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
-+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
-+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
-+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
-+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
-+# CONFIG_IP_VS is not set
-+
-+#
-+# IP: Netfilter Configuration
-+#
-+CONFIG_NF_DEFRAG_IPV4=y
-+CONFIG_NF_CONNTRACK_IPV4=y
-+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-+# CONFIG_IP_NF_QUEUE is not set
-+CONFIG_IP_NF_IPTABLES=y
-+# CONFIG_IP_NF_MATCH_AH is not set
-+# CONFIG_IP_NF_MATCH_ECN is not set
-+# CONFIG_IP_NF_MATCH_TTL is not set
-+CONFIG_IP_NF_FILTER=y
-+# CONFIG_IP_NF_TARGET_REJECT is not set
-+CONFIG_IP_NF_TARGET_LOG=y
-+# CONFIG_IP_NF_TARGET_ULOG is not set
-+CONFIG_NF_NAT=y
-+CONFIG_NF_NAT_NEEDED=y
-+CONFIG_IP_NF_TARGET_MASQUERADE=y
-+# CONFIG_IP_NF_TARGET_NETMAP is not set
-+# CONFIG_IP_NF_TARGET_REDIRECT is not set
-+# CONFIG_NF_NAT_FTP is not set
-+# CONFIG_NF_NAT_IRC is not set
-+# CONFIG_NF_NAT_TFTP is not set
-+# CONFIG_NF_NAT_AMANDA is not set
-+# CONFIG_NF_NAT_PPTP is not set
-+# CONFIG_NF_NAT_H323 is not set
-+# CONFIG_NF_NAT_SIP is not set
-+# CONFIG_IP_NF_MANGLE is not set
-+# CONFIG_IP_NF_RAW is not set
-+# CONFIG_IP_NF_SECURITY is not set
-+# CONFIG_IP_NF_ARPTABLES is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_RDS is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_L2TP is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_NET_DSA is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_PHONET is not set
-+# CONFIG_IEEE802154 is not set
-+# CONFIG_NET_SCHED is not set
-+# CONFIG_DCB is not set
-+CONFIG_DNS_RESOLVER=y
-+# CONFIG_BATMAN_ADV is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+CONFIG_CAN=y
-+CONFIG_CAN_RAW=y
-+CONFIG_CAN_BCM=y
-+# CONFIG_CAN_GW is not set
-+
-+#
-+# CAN Device Drivers
-+#
-+# CONFIG_CAN_VCAN is not set
-+# CONFIG_CAN_SLCAN is not set
-+CONFIG_CAN_DEV=y
-+CONFIG_CAN_CALC_BITTIMING=y
-+# CONFIG_CAN_TI_HECC is not set
-+# CONFIG_CAN_MCP251X is not set
-+# CONFIG_CAN_SJA1000 is not set
-+# CONFIG_CAN_C_CAN is not set
-+CONFIG_CAN_D_CAN=y
-+CONFIG_CAN_D_CAN_PLATFORM=y
-+
-+#
-+# CAN USB interfaces
-+#
-+# CONFIG_CAN_EMS_USB is not set
-+# CONFIG_CAN_ESD_USB2 is not set
-+# CONFIG_CAN_SOFTING is not set
-+# CONFIG_CAN_DEBUG_DEVICES is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+CONFIG_WIRELESS=y
-+CONFIG_WIRELESS_EXT=y
-+CONFIG_WEXT_CORE=y
-+CONFIG_WEXT_PROC=y
-+CONFIG_WEXT_PRIV=y
-+# CONFIG_CFG80211 is not set
-+CONFIG_WIRELESS_EXT_SYSFS=y
-+# CONFIG_LIB80211 is not set
-+
-+#
-+# CFG80211 needs to be enabled for MAC80211
-+#
-+# CONFIG_WIMAX is not set
-+CONFIG_RFKILL=y
-+CONFIG_RFKILL_INPUT=y
-+# CONFIG_RFKILL_REGULATOR is not set
-+# CONFIG_RFKILL_GPIO is not set
-+# CONFIG_NET_9P is not set
-+# CONFIG_CAIF is not set
-+# CONFIG_CEPH_LIB is not set
-+# CONFIG_NFC is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+# CONFIG_DEVTMPFS is not set
-+CONFIG_STANDALONE=y
-+CONFIG_PREVENT_FIRMWARE_BUILD=y
-+CONFIG_FW_LOADER=y
-+CONFIG_FIRMWARE_IN_KERNEL=y
-+CONFIG_EXTRA_FIRMWARE="am335x-pm-firmware.bin"
-+CONFIG_EXTRA_FIRMWARE_DIR="firmware"
-+# CONFIG_SYS_HYPERVISOR is not set
-+CONFIG_REGMAP=y
-+CONFIG_REGMAP_I2C=y
-+CONFIG_REGMAP_SPI=y
-+
-+#
-+# CBUS support
-+#
-+# CONFIG_CBUS is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_TESTS is not set
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AFS_PARTS is not set
-+# CONFIG_MTD_OF_PARTS is not set
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_SM_FTL is not set
-+CONFIG_MTD_OOPS=y
-+# CONFIG_MTD_SWAP is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+# CONFIG_MTD_CFI_AMDSTD is not set
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PHYSMAP is not set
-+# CONFIG_MTD_PHYSMAP_OF is not set
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_DATAFLASH is not set
-+CONFIG_MTD_M25P80=y
-+CONFIG_M25PXX_USE_FAST_READ=y
-+# CONFIG_MTD_SST25L is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_DOCG3 is not set
-+CONFIG_MTD_NAND_ECC=y
-+# CONFIG_MTD_NAND_ECC_SMC is not set
-+CONFIG_MTD_NAND=y
-+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-+# CONFIG_MTD_NAND_ECC_BCH is not set
-+# CONFIG_MTD_SM_COMMON is not set
-+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-+# CONFIG_MTD_NAND_GPIO is not set
-+CONFIG_MTD_NAND_OMAP2=y
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+# CONFIG_MTD_NAND_PLATFORM is not set
-+# CONFIG_MTD_ALAUDA is not set
-+CONFIG_MTD_ONENAND=y
-+# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
-+# CONFIG_MTD_ONENAND_GENERIC is not set
-+CONFIG_MTD_ONENAND_OMAP2=y
-+# CONFIG_MTD_ONENAND_OTP is not set
-+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
-+# CONFIG_MTD_ONENAND_SIM is not set
-+
-+#
-+# LPDDR flash memory drivers
-+#
-+# CONFIG_MTD_LPDDR is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+# CONFIG_MTD_UBI_DEBUG is not set
-+CONFIG_DTC=y
-+CONFIG_OF=y
-+
-+#
-+# Device Tree and Open Firmware support
-+#
-+CONFIG_PROC_DEVICETREE=y
-+CONFIG_OF_FLATTREE=y
-+CONFIG_OF_EARLY_FLATTREE=y
-+CONFIG_OF_ADDRESS=y
-+CONFIG_OF_IRQ=y
-+CONFIG_OF_DEVICE=y
-+CONFIG_OF_GPIO=y
-+CONFIG_OF_I2C=y
-+CONFIG_OF_NET=y
-+CONFIG_OF_SPI=y
-+CONFIG_OF_MDIO=y
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+
-+#
-+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
-+#
-+# CONFIG_BLK_DEV_NBD is not set
-+# CONFIG_BLK_DEV_UB is not set
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=16384
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+# CONFIG_MG_DISK is not set
-+# CONFIG_BLK_DEV_RBD is not set
-+CONFIG_SENSORS_LIS3LV02D=y
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_AD525X_DPOT is not set
-+# CONFIG_ATMEL_PWM is not set
-+# CONFIG_ICS932S401 is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_APDS9802ALS is not set
-+# CONFIG_ISL29003 is not set
-+# CONFIG_ISL29020 is not set
-+CONFIG_SENSORS_TSL2550=y
-+# CONFIG_SENSORS_BH1780 is not set
-+# CONFIG_SENSORS_BH1770 is not set
-+# CONFIG_SENSORS_APDS990X is not set
-+# CONFIG_HMC6352 is not set
-+# CONFIG_DS1682 is not set
-+# CONFIG_TI_DAC7512 is not set
-+# CONFIG_BMP085 is not set
-+# CONFIG_USB_SWITCH_FSA9480 is not set
-+# CONFIG_C2PORT is not set
-+
-+#
-+# EEPROM support
-+#
-+CONFIG_EEPROM_AT24=y
-+# CONFIG_EEPROM_AT25 is not set
-+# CONFIG_EEPROM_LEGACY is not set
-+# CONFIG_EEPROM_MAX6875 is not set
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_EEPROM_93XX46 is not set
-+# CONFIG_IWMC3200TOP is not set
-+
-+#
-+# Texas Instruments shared transport line discipline
-+#
-+# CONFIG_TI_ST is not set
-+# CONFIG_SENSORS_LIS3_SPI is not set
-+CONFIG_SENSORS_LIS3_I2C=y
-+
-+#
-+# Altera FPGA firmware download module
-+#
-+# CONFIG_ALTERA_STAPL is not set
-+
-+#
-+# SCSI device support
-+#
-+CONFIG_SCSI_MOD=y
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=y
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
-+# CONFIG_SCSI_NETLINK is not set
-+CONFIG_SCSI_PROC_FS=y
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=y
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+# CONFIG_BLK_DEV_SR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+CONFIG_SCSI_MULTI_LUN=y
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+CONFIG_SCSI_SCAN_ASYNC=y
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+CONFIG_SCSI_LOWLEVEL=y
-+# CONFIG_ISCSI_TCP is not set
-+# CONFIG_ISCSI_BOOT_SYSFS is not set
-+# CONFIG_LIBFC is not set
-+# CONFIG_LIBFCOE is not set
-+# CONFIG_SCSI_DEBUG is not set
-+# CONFIG_SCSI_DH is not set
-+# CONFIG_SCSI_OSD_INITIATOR is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+# CONFIG_TARGET_CORE is not set
-+CONFIG_NETDEVICES=y
-+CONFIG_NET_CORE=y
-+# CONFIG_BONDING is not set
-+# CONFIG_DUMMY is not set
-+# CONFIG_EQUALIZER is not set
-+CONFIG_MII=y
-+# CONFIG_MACVLAN is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+
-+#
-+# CAIF transport drivers
-+#
-+CONFIG_ETHERNET=y
-+CONFIG_NET_VENDOR_BROADCOM=y
-+# CONFIG_B44 is not set
-+CONFIG_NET_VENDOR_CHELSIO=y
-+# CONFIG_DM9000 is not set
-+# CONFIG_DNET is not set
-+CONFIG_NET_VENDOR_FARADAY=y
-+# CONFIG_FTMAC100 is not set
-+# CONFIG_FTGMAC100 is not set
-+CONFIG_NET_VENDOR_INTEL=y
-+CONFIG_NET_VENDOR_I825XX=y
-+CONFIG_NET_VENDOR_MARVELL=y
-+CONFIG_NET_VENDOR_MICREL=y
-+# CONFIG_KS8851 is not set
-+# CONFIG_KS8851_MLL is not set
-+CONFIG_NET_VENDOR_MICROCHIP=y
-+# CONFIG_ENC28J60 is not set
-+CONFIG_NET_VENDOR_NATSEMI=y
-+CONFIG_NET_VENDOR_8390=y
-+# CONFIG_AX88796 is not set
-+# CONFIG_ETHOC is not set
-+CONFIG_NET_VENDOR_SEEQ=y
-+# CONFIG_SEEQ8005 is not set
-+CONFIG_NET_VENDOR_SMSC=y
-+CONFIG_SMC91X=y
-+# CONFIG_SMC911X is not set
-+CONFIG_SMSC911X=y
-+# CONFIG_SMSC911X_ARCH_HOOKS is not set
-+CONFIG_NET_VENDOR_STMICRO=y
-+# CONFIG_STMMAC_ETH is not set
-+CONFIG_NET_VENDOR_TI=y
-+# CONFIG_TI_DAVINCI_EMAC is not set
-+CONFIG_TI_DAVINCI_MDIO=y
-+CONFIG_TI_DAVINCI_CPDMA=y
-+CONFIG_TI_CPSW=y
-+CONFIG_TLK110_WORKAROUND=y
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+CONFIG_SMSC_PHY=y
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_NATIONAL_PHY is not set
-+# CONFIG_STE10XP is not set
-+# CONFIG_LSI_ET1011C_PHY is not set
-+# CONFIG_MICREL_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+# CONFIG_PPP is not set
-+# CONFIG_SLIP is not set
-+
-+#
-+# USB Network Adapters
-+#
-+# CONFIG_USB_CATC is not set
-+# CONFIG_USB_KAWETH is not set
-+# CONFIG_USB_PEGASUS is not set
-+# CONFIG_USB_RTL8150 is not set
-+CONFIG_USB_USBNET=y
-+# CONFIG_USB_NET_AX8817X is not set
-+CONFIG_USB_NET_CDCETHER=y
-+CONFIG_USB_NET_CDC_EEM=y
-+CONFIG_USB_NET_CDC_NCM=y
-+CONFIG_USB_NET_DM9601=y
-+# CONFIG_USB_NET_SMSC75XX is not set
-+# CONFIG_USB_NET_SMSC95XX is not set
-+# CONFIG_USB_NET_GL620A is not set
-+# CONFIG_USB_NET_NET1080 is not set
-+# CONFIG_USB_NET_PLUSB is not set
-+# CONFIG_USB_NET_MCS7830 is not set
-+# CONFIG_USB_NET_RNDIS_HOST is not set
-+# CONFIG_USB_NET_CDC_SUBSET is not set
-+# CONFIG_USB_NET_ZAURUS is not set
-+# CONFIG_USB_NET_CX82310_ETH is not set
-+# CONFIG_USB_NET_KALMIA is not set
-+# CONFIG_USB_HSO is not set
-+# CONFIG_USB_NET_INT51X1 is not set
-+# CONFIG_USB_IPHETH is not set
-+# CONFIG_USB_SIERRA_NET is not set
-+# CONFIG_USB_VL600 is not set
-+CONFIG_WLAN=y
-+CONFIG_USB_ZD1201=y
-+# CONFIG_HOSTAP is not set
-+CONFIG_WL12XX_PLATFORM_DATA=y
-+
-+#
-+# Enable WiMAX (Networking options) to see the WiMAX drivers
-+#
-+# CONFIG_WAN is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=y
-+# CONFIG_INPUT_SPARSEKMAP is not set
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=y
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=y
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ADP5588 is not set
-+# CONFIG_KEYBOARD_ADP5589 is not set
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_QT1070 is not set
-+# CONFIG_KEYBOARD_QT2160 is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+CONFIG_KEYBOARD_GPIO=y
-+# CONFIG_KEYBOARD_TCA6416 is not set
-+CONFIG_KEYBOARD_MATRIX=y
-+# CONFIG_KEYBOARD_MAX7359 is not set
-+# CONFIG_KEYBOARD_MCS is not set
-+# CONFIG_KEYBOARD_MPR121 is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_OPENCORES is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_TWL4030 is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+CONFIG_INPUT_MOUSE=y
-+CONFIG_MOUSE_PS2=y
-+CONFIG_MOUSE_PS2_ALPS=y
-+CONFIG_MOUSE_PS2_LOGIPS2PP=y
-+CONFIG_MOUSE_PS2_SYNAPTICS=y
-+CONFIG_MOUSE_PS2_TRACKPOINT=y
-+# CONFIG_MOUSE_PS2_ELANTECH is not set
-+# CONFIG_MOUSE_PS2_SENTELIC is not set
-+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+# CONFIG_MOUSE_GPIO is not set
-+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+# CONFIG_TOUCHSCREEN_ADS7846 is not set
-+# CONFIG_TOUCHSCREEN_AD7877 is not set
-+# CONFIG_TOUCHSCREEN_AD7879 is not set
-+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-+# CONFIG_TOUCHSCREEN_BU21013 is not set
-+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-+# CONFIG_TOUCHSCREEN_EETI is not set
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-+# CONFIG_TOUCHSCREEN_MAX11801 is not set
-+# CONFIG_TOUCHSCREEN_MCS5000 is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+CONFIG_TOUCHSCREEN_TI_TSCADC=y
-+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-+# CONFIG_TOUCHSCREEN_TSC2005 is not set
-+# CONFIG_TOUCHSCREEN_TSC2007 is not set
-+# CONFIG_TOUCHSCREEN_W90X900 is not set
-+# CONFIG_TOUCHSCREEN_ST1232 is not set
-+# CONFIG_TOUCHSCREEN_TPS6507X is not set
-+CONFIG_INPUT_MISC=y
-+# CONFIG_INPUT_AD714X is not set
-+# CONFIG_INPUT_BMA150 is not set
-+# CONFIG_INPUT_MMA8450 is not set
-+# CONFIG_INPUT_MPU3050 is not set
-+# CONFIG_INPUT_ATI_REMOTE2 is not set
-+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-+# CONFIG_INPUT_KXTJ9 is not set
-+# CONFIG_INPUT_POWERMATE is not set
-+# CONFIG_INPUT_YEALINK is not set
-+# CONFIG_INPUT_CM109 is not set
-+# CONFIG_INPUT_TWL4030_PWRBUTTON is not set
-+# CONFIG_INPUT_TWL4030_VIBRA is not set
-+# CONFIG_INPUT_TWL6040_VIBRA is not set
-+# CONFIG_INPUT_UINPUT is not set
-+# CONFIG_INPUT_PCF8574 is not set
-+# CONFIG_INPUT_PWM_BEEPER is not set
-+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-+# CONFIG_INPUT_ADXL34X is not set
-+# CONFIG_INPUT_CMA3000 is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_SERPORT is not set
-+CONFIG_SERIO_LIBPS2=y
-+# CONFIG_SERIO_RAW is not set
-+# CONFIG_SERIO_ALTERA_PS2 is not set
-+# CONFIG_SERIO_PS2MULT is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_VT_CONSOLE_SLEEP=y
-+CONFIG_HW_CONSOLE=y
-+CONFIG_VT_HW_CONSOLE_BINDING=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+# CONFIG_N_GSM is not set
-+# CONFIG_TRACE_SINK is not set
-+CONFIG_DEVKMEM=y
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+# CONFIG_SERIAL_MAX3100 is not set
-+# CONFIG_SERIAL_MAX3107 is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_SERIAL_OMAP=y
-+CONFIG_SERIAL_OMAP_CONSOLE=y
-+# CONFIG_SERIAL_TIMBERDALE is not set
-+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-+# CONFIG_SERIAL_ALTERA_UART is not set
-+# CONFIG_SERIAL_IFX6X60 is not set
-+# CONFIG_SERIAL_XILINX_PS_UART is not set
-+# CONFIG_HVC_DCC is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+# CONFIG_RAMOOPS is not set
-+CONFIG_I2C=y
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_COMPAT=y
-+CONFIG_I2C_CHARDEV=y
-+# CONFIG_I2C_MUX is not set
-+CONFIG_I2C_HELPER_AUTO=y
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
-+# CONFIG_I2C_GPIO is not set
-+# CONFIG_I2C_OCORES is not set
-+CONFIG_I2C_OMAP=y
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_PXA_PCI is not set
-+# CONFIG_I2C_SIMTEC is not set
-+# CONFIG_I2C_XILINX is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_DIOLAN_U2C is not set
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+# CONFIG_I2C_TINY_USB is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_STUB is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+CONFIG_SPI=y
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+# CONFIG_SPI_ALTERA is not set
-+# CONFIG_SPI_BITBANG is not set
-+# CONFIG_SPI_GPIO is not set
-+# CONFIG_SPI_OC_TINY is not set
-+CONFIG_SPI_OMAP24XX=y
-+# CONFIG_SPI_PXA2XX_PCI is not set
-+# CONFIG_SPI_XILINX is not set
-+# CONFIG_SPI_DESIGNWARE is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_SPIDEV is not set
-+# CONFIG_SPI_TLE62X0 is not set
-+
-+#
-+# PPS support
-+#
-+# CONFIG_PPS is not set
-+
-+#
-+# PPS generators support
-+#
-+
-+#
-+# PTP clock support
-+#
-+
-+#
-+# Enable Device Drivers -> PPS to see the PTP clock options.
-+#
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# Memory mapped GPIO drivers:
-+#
-+# CONFIG_GPIO_GENERIC_PLATFORM is not set
-+# CONFIG_GPIO_IT8761E is not set
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7300 is not set
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+# CONFIG_GPIO_SX150X is not set
-+# CONFIG_GPIO_TWL4030 is not set
-+# CONFIG_GPIO_ADP5588 is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_GPIO_MC33880 is not set
-+# CONFIG_GPIO_74X164 is not set
-+
-+#
-+# AC97 GPIO expanders:
-+#
-+
-+#
-+# MODULbus GPIO expanders:
-+#
-+CONFIG_GPIO_TPS65910=y
-+CONFIG_GENERIC_PWM=y
-+CONFIG_DAVINCI_EHRPWM=y
-+CONFIG_ECAP_PWM=y
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+CONFIG_HWMON=y
-+# CONFIG_HWMON_VID is not set
-+# CONFIG_HWMON_DEBUG_CHIP is not set
-+
-+#
-+# Native drivers
-+#
-+# CONFIG_SENSORS_AD7314 is not set
-+# CONFIG_SENSORS_AD7414 is not set
-+# CONFIG_SENSORS_AD7418 is not set
-+# CONFIG_SENSORS_ADCXX is not set
-+# CONFIG_SENSORS_ADM1021 is not set
-+# CONFIG_SENSORS_ADM1025 is not set
-+# CONFIG_SENSORS_ADM1026 is not set
-+# CONFIG_SENSORS_ADM1029 is not set
-+# CONFIG_SENSORS_ADM1031 is not set
-+# CONFIG_SENSORS_ADM9240 is not set
-+# CONFIG_SENSORS_ADT7411 is not set
-+# CONFIG_SENSORS_ADT7462 is not set
-+# CONFIG_SENSORS_ADT7470 is not set
-+# CONFIG_SENSORS_ADT7475 is not set
-+# CONFIG_SENSORS_ASC7621 is not set
-+# CONFIG_SENSORS_ATXP1 is not set
-+# CONFIG_SENSORS_DS620 is not set
-+# CONFIG_SENSORS_DS1621 is not set
-+# CONFIG_SENSORS_F71805F is not set
-+# CONFIG_SENSORS_F71882FG is not set
-+# CONFIG_SENSORS_F75375S is not set
-+# CONFIG_SENSORS_G760A is not set
-+# CONFIG_SENSORS_GL518SM is not set
-+# CONFIG_SENSORS_GL520SM is not set
-+# CONFIG_SENSORS_GPIO_FAN is not set
-+# CONFIG_SENSORS_IT87 is not set
-+# CONFIG_SENSORS_JC42 is not set
-+# CONFIG_SENSORS_LINEAGE is not set
-+# CONFIG_SENSORS_LM63 is not set
-+# CONFIG_SENSORS_LM70 is not set
-+# CONFIG_SENSORS_LM73 is not set
-+CONFIG_SENSORS_LM75=y
-+# CONFIG_SENSORS_LM77 is not set
-+# CONFIG_SENSORS_LM78 is not set
-+# CONFIG_SENSORS_LM80 is not set
-+# CONFIG_SENSORS_LM83 is not set
-+# CONFIG_SENSORS_LM85 is not set
-+# CONFIG_SENSORS_LM87 is not set
-+# CONFIG_SENSORS_LM90 is not set
-+# CONFIG_SENSORS_LM92 is not set
-+# CONFIG_SENSORS_LM93 is not set
-+# CONFIG_SENSORS_LTC4151 is not set
-+# CONFIG_SENSORS_LTC4215 is not set
-+# CONFIG_SENSORS_LTC4245 is not set
-+# CONFIG_SENSORS_LTC4261 is not set
-+# CONFIG_SENSORS_LM95241 is not set
-+# CONFIG_SENSORS_LM95245 is not set
-+# CONFIG_SENSORS_MAX1111 is not set
-+# CONFIG_SENSORS_MAX16065 is not set
-+# CONFIG_SENSORS_MAX1619 is not set
-+# CONFIG_SENSORS_MAX1668 is not set
-+# CONFIG_SENSORS_MAX6639 is not set
-+# CONFIG_SENSORS_MAX6642 is not set
-+# CONFIG_SENSORS_MAX6650 is not set
-+# CONFIG_SENSORS_NTC_THERMISTOR is not set
-+# CONFIG_SENSORS_PC87360 is not set
-+# CONFIG_SENSORS_PC87427 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_PMBUS is not set
-+# CONFIG_SENSORS_SHT15 is not set
-+# CONFIG_SENSORS_SHT21 is not set
-+# CONFIG_SENSORS_SMM665 is not set
-+# CONFIG_SENSORS_DME1737 is not set
-+# CONFIG_SENSORS_EMC1403 is not set
-+# CONFIG_SENSORS_EMC2103 is not set
-+# CONFIG_SENSORS_EMC6W201 is not set
-+# CONFIG_SENSORS_SMSC47M1 is not set
-+# CONFIG_SENSORS_SMSC47M192 is not set
-+# CONFIG_SENSORS_SMSC47B397 is not set
-+# CONFIG_SENSORS_SCH56XX_COMMON is not set
-+# CONFIG_SENSORS_SCH5627 is not set
-+# CONFIG_SENSORS_SCH5636 is not set
-+# CONFIG_SENSORS_ADS1015 is not set
-+# CONFIG_SENSORS_ADS7828 is not set
-+# CONFIG_SENSORS_ADS7871 is not set
-+# CONFIG_SENSORS_AMC6821 is not set
-+# CONFIG_SENSORS_THMC50 is not set
-+# CONFIG_SENSORS_TMP102 is not set
-+# CONFIG_SENSORS_TMP401 is not set
-+# CONFIG_SENSORS_TMP421 is not set
-+# CONFIG_SENSORS_VT1211 is not set
-+# CONFIG_SENSORS_W83781D is not set
-+# CONFIG_SENSORS_W83791D is not set
-+# CONFIG_SENSORS_W83792D is not set
-+# CONFIG_SENSORS_W83793 is not set
-+# CONFIG_SENSORS_W83795 is not set
-+# CONFIG_SENSORS_W83L785TS is not set
-+# CONFIG_SENSORS_W83L786NG is not set
-+# CONFIG_SENSORS_W83627HF is not set
-+# CONFIG_SENSORS_W83627EHF is not set
-+# CONFIG_THERMAL is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_CORE is not set
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+# CONFIG_DW_WATCHDOG is not set
-+CONFIG_OMAP_WATCHDOG=y
-+# CONFIG_TWL4030_WATCHDOG is not set
-+# CONFIG_MAX63XX_WATCHDOG is not set
-+
-+#
-+# USB-based Watchdog Cards
-+#
-+# CONFIG_USBPCWATCHDOG is not set
-+CONFIG_SSB_POSSIBLE=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+# CONFIG_SSB is not set
-+CONFIG_BCMA_POSSIBLE=y
-+
-+#
-+# Broadcom specific AMBA
-+#
-+# CONFIG_BCMA is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+CONFIG_MFD_CORE=y
-+# CONFIG_MFD_88PM860X is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_MFD_ASIC3 is not set
-+# CONFIG_HTC_EGPIO is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_HTC_I2CPLD is not set
-+# CONFIG_TPS6105X is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_TPS6507X is not set
-+CONFIG_MFD_TPS65217=y
-+# CONFIG_MFD_TPS6586X is not set
-+CONFIG_MFD_TPS65910=y
-+# CONFIG_MFD_TPS65912_I2C is not set
-+# CONFIG_MFD_TPS65912_SPI is not set
-+CONFIG_TWL4030_CORE=y
-+# CONFIG_TWL4030_MADC is not set
-+CONFIG_TWL4030_POWER=y
-+# CONFIG_MFD_TWL4030_AUDIO is not set
-+# CONFIG_TWL6030_PWM is not set
-+# CONFIG_TWL6040_CORE is not set
-+# CONFIG_MFD_STMPE is not set
-+# CONFIG_MFD_TC3589X is not set
-+# CONFIG_MFD_TMIO is not set
-+# CONFIG_MFD_T7L66XB is not set
-+# CONFIG_MFD_TC6387XB is not set
-+# CONFIG_MFD_TC6393XB is not set
-+# CONFIG_PMIC_DA903X is not set
-+# CONFIG_PMIC_ADP5520 is not set
-+# CONFIG_MFD_MAX8925 is not set
-+# CONFIG_MFD_MAX8997 is not set
-+# CONFIG_MFD_MAX8998 is not set
-+# CONFIG_MFD_WM8400 is not set
-+# CONFIG_MFD_WM831X_I2C is not set
-+# CONFIG_MFD_WM831X_SPI is not set
-+# CONFIG_MFD_WM8350_I2C is not set
-+# CONFIG_MFD_WM8994 is not set
-+# CONFIG_MFD_PCF50633 is not set
-+# CONFIG_MFD_MC13XXX is not set
-+# CONFIG_ABX500_CORE is not set
-+# CONFIG_EZX_PCAP is not set
-+# CONFIG_MFD_WL1273_CORE is not set
-+# CONFIG_MFD_AAT2870_CORE is not set
-+CONFIG_REGULATOR=y
-+# CONFIG_REGULATOR_DEBUG is not set
-+CONFIG_REGULATOR_DUMMY=y
-+CONFIG_REGULATOR_FIXED_VOLTAGE=y
-+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-+# CONFIG_REGULATOR_GPIO is not set
-+# CONFIG_REGULATOR_BQ24022 is not set
-+# CONFIG_REGULATOR_MAX1586 is not set
-+# CONFIG_REGULATOR_MAX8649 is not set
-+# CONFIG_REGULATOR_MAX8660 is not set
-+# CONFIG_REGULATOR_MAX8952 is not set
-+# CONFIG_REGULATOR_TWL4030 is not set
-+# CONFIG_REGULATOR_LP3971 is not set
-+# CONFIG_REGULATOR_LP3972 is not set
-+# CONFIG_REGULATOR_TPS65023 is not set
-+# CONFIG_REGULATOR_TPS6507X is not set
-+CONFIG_REGULATOR_TPS65217=y
-+# CONFIG_REGULATOR_ISL6271A is not set
-+# CONFIG_REGULATOR_AD5398 is not set
-+# CONFIG_REGULATOR_TPS6524X is not set
-+CONFIG_REGULATOR_TPS65910=y
-+CONFIG_MEDIA_SUPPORT=y
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_MEDIA_CONTROLLER is not set
-+CONFIG_VIDEO_DEV=y
-+CONFIG_VIDEO_V4L2_COMMON=y
-+# CONFIG_DVB_CORE is not set
-+CONFIG_VIDEO_MEDIA=y
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_RC_CORE is not set
-+# CONFIG_MEDIA_ATTACH is not set
-+CONFIG_MEDIA_TUNER=y
-+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-+CONFIG_MEDIA_TUNER_SIMPLE=y
-+CONFIG_MEDIA_TUNER_TDA8290=y
-+CONFIG_MEDIA_TUNER_TDA827X=y
-+CONFIG_MEDIA_TUNER_TDA18271=y
-+CONFIG_MEDIA_TUNER_TDA9887=y
-+CONFIG_MEDIA_TUNER_TEA5761=y
-+CONFIG_MEDIA_TUNER_TEA5767=y
-+CONFIG_MEDIA_TUNER_MT20XX=y
-+CONFIG_MEDIA_TUNER_XC2028=y
-+CONFIG_MEDIA_TUNER_XC5000=y
-+CONFIG_MEDIA_TUNER_XC4000=y
-+CONFIG_MEDIA_TUNER_MC44S803=y
-+CONFIG_VIDEO_V4L2=y
-+CONFIG_VIDEO_CAPTURE_DRIVERS=y
-+# CONFIG_VIDEO_ADV_DEBUG is not set
-+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-+
-+#
-+# Encoders, decoders, sensors and other helper chips
-+#
-+
-+#
-+# Audio decoders, processors and mixers
-+#
-+# CONFIG_VIDEO_TVAUDIO is not set
-+# CONFIG_VIDEO_TDA7432 is not set
-+# CONFIG_VIDEO_TDA9840 is not set
-+# CONFIG_VIDEO_TEA6415C is not set
-+# CONFIG_VIDEO_TEA6420 is not set
-+# CONFIG_VIDEO_MSP3400 is not set
-+# CONFIG_VIDEO_CS5345 is not set
-+# CONFIG_VIDEO_CS53L32A is not set
-+# CONFIG_VIDEO_TLV320AIC23B is not set
-+# CONFIG_VIDEO_WM8775 is not set
-+# CONFIG_VIDEO_WM8739 is not set
-+# CONFIG_VIDEO_VP27SMPX is not set
-+
-+#
-+# RDS decoders
-+#
-+# CONFIG_VIDEO_SAA6588 is not set
-+
-+#
-+# Video decoders
-+#
-+# CONFIG_VIDEO_ADV7180 is not set
-+# CONFIG_VIDEO_BT819 is not set
-+# CONFIG_VIDEO_BT856 is not set
-+# CONFIG_VIDEO_BT866 is not set
-+# CONFIG_VIDEO_KS0127 is not set
-+# CONFIG_VIDEO_SAA7110 is not set
-+# CONFIG_VIDEO_SAA711X is not set
-+# CONFIG_VIDEO_SAA7191 is not set
-+# CONFIG_VIDEO_TVP514X is not set
-+# CONFIG_VIDEO_TVP5150 is not set
-+# CONFIG_VIDEO_TVP7002 is not set
-+# CONFIG_VIDEO_VPX3220 is not set
-+
-+#
-+# Video and audio decoders
-+#
-+# CONFIG_VIDEO_SAA717X is not set
-+# CONFIG_VIDEO_CX25840 is not set
-+
-+#
-+# MPEG video encoders
-+#
-+# CONFIG_VIDEO_CX2341X is not set
-+
-+#
-+# Video encoders
-+#
-+# CONFIG_VIDEO_SAA7127 is not set
-+# CONFIG_VIDEO_SAA7185 is not set
-+# CONFIG_VIDEO_ADV7170 is not set
-+# CONFIG_VIDEO_ADV7175 is not set
-+# CONFIG_VIDEO_ADV7343 is not set
-+# CONFIG_VIDEO_AK881X is not set
-+
-+#
-+# Camera sensor devices
-+#
-+# CONFIG_VIDEO_OV7670 is not set
-+# CONFIG_VIDEO_MT9V011 is not set
-+# CONFIG_VIDEO_TCM825X is not set
-+# CONFIG_VIDEO_SR030PC30 is not set
-+
-+#
-+# Flash devices
-+#
-+
-+#
-+# Video improvement chips
-+#
-+# CONFIG_VIDEO_UPD64031A is not set
-+# CONFIG_VIDEO_UPD64083 is not set
-+
-+#
-+# Miscelaneous helper chips
-+#
-+# CONFIG_VIDEO_THS7303 is not set
-+# CONFIG_VIDEO_M52790 is not set
-+# CONFIG_VIDEO_VIVI is not set
-+# CONFIG_VIDEO_VPFE_CAPTURE is not set
-+# CONFIG_VIDEO_OMAP2_VOUT is not set
-+# CONFIG_VIDEO_CPIA2 is not set
-+# CONFIG_SOC_CAMERA is not set
-+CONFIG_V4L_USB_DRIVERS=y
-+CONFIG_USB_VIDEO_CLASS=y
-+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-+# CONFIG_USB_GSPCA is not set
-+# CONFIG_VIDEO_PVRUSB2 is not set
-+# CONFIG_VIDEO_HDPVR is not set
-+# CONFIG_VIDEO_EM28XX is not set
-+# CONFIG_VIDEO_USBVISION is not set
-+# CONFIG_USB_ET61X251 is not set
-+# CONFIG_USB_SN9C102 is not set
-+# CONFIG_USB_PWC is not set
-+# CONFIG_USB_ZR364XX is not set
-+# CONFIG_USB_STKWEBCAM is not set
-+# CONFIG_USB_S2255 is not set
-+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
-+# CONFIG_RADIO_ADAPTERS is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_DRM is not set
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_WMT_GE_ROPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+# CONFIG_FB_TMIO is not set
-+# CONFIG_FB_SMSCUFX is not set
-+# CONFIG_FB_UDL is not set
-+CONFIG_FB_DA8XX=y
-+CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE=5
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_FB_METRONOME is not set
-+# CONFIG_FB_BROADSHEET is not set
-+# CONFIG_FB_OMAP is not set
-+# CONFIG_OMAP2_DSS is not set
-+CONFIG_BACKLIGHT_LCD_SUPPORT=y
-+CONFIG_LCD_CLASS_DEVICE=y
-+# CONFIG_LCD_L4F00242T03 is not set
-+# CONFIG_LCD_LMS283GF05 is not set
-+# CONFIG_LCD_LTV350QV is not set
-+# CONFIG_LCD_TDO24M is not set
-+# CONFIG_LCD_VGG2432A4 is not set
-+# CONFIG_LCD_PLATFORM is not set
-+# CONFIG_LCD_S6E63M0 is not set
-+# CONFIG_LCD_LD9040 is not set
-+# CONFIG_LCD_AMS369FG06 is not set
-+CONFIG_BACKLIGHT_CLASS_DEVICE=y
-+# CONFIG_BACKLIGHT_GENERIC is not set
-+CONFIG_BACKLIGHT_PWM=y
-+# CONFIG_BACKLIGHT_ADP8860 is not set
-+# CONFIG_BACKLIGHT_ADP8870 is not set
-+CONFIG_BACKLIGHT_TLC59108=y
-+
-+#
-+# Display device support
-+#
-+CONFIG_DISPLAY_SUPPORT=y
-+
-+#
-+# Display hardware drivers
-+#
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-+# CONFIG_FONTS is not set
-+CONFIG_FONT_8x8=y
-+CONFIG_FONT_8x16=y
-+CONFIG_LOGO=y
-+CONFIG_LOGO_LINUX_MONO=y
-+CONFIG_LOGO_LINUX_VGA16=y
-+CONFIG_LOGO_LINUX_CLUT224=y
-+CONFIG_SOUND=y
-+# CONFIG_SOUND_OSS_CORE is not set
-+CONFIG_SND=y
-+CONFIG_SND_TIMER=y
-+CONFIG_SND_PCM=y
-+CONFIG_SND_HWDEP=y
-+CONFIG_SND_RAWMIDI=y
-+CONFIG_SND_JACK=y
-+# CONFIG_SND_SEQUENCER is not set
-+# CONFIG_SND_MIXER_OSS is not set
-+# CONFIG_SND_PCM_OSS is not set
-+# CONFIG_SND_HRTIMER is not set
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+CONFIG_SND_SUPPORT_OLD_API=y
-+CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+# CONFIG_SND_RAWMIDI_SEQ is not set
-+# CONFIG_SND_OPL3_LIB_SEQ is not set
-+# CONFIG_SND_OPL4_LIB_SEQ is not set
-+# CONFIG_SND_SBAWE_SEQ is not set
-+# CONFIG_SND_EMU10K1_SEQ is not set
-+CONFIG_SND_DRIVERS=y
-+# CONFIG_SND_DUMMY is not set
-+# CONFIG_SND_ALOOP is not set
-+# CONFIG_SND_MTPAV is not set
-+# CONFIG_SND_SERIAL_U16550 is not set
-+# CONFIG_SND_MPU401 is not set
-+CONFIG_SND_ARM=y
-+CONFIG_SND_SPI=y
-+CONFIG_SND_USB=y
-+CONFIG_SND_USB_AUDIO=y
-+# CONFIG_SND_USB_UA101 is not set
-+# CONFIG_SND_USB_CAIAQ is not set
-+# CONFIG_SND_USB_6FIRE is not set
-+CONFIG_SND_SOC=y
-+# CONFIG_SND_SOC_CACHE_LZO is not set
-+CONFIG_SND_AM33XX_SOC=y
-+CONFIG_SND_DAVINCI_SOC_MCASP=y
-+CONFIG_SND_AM335X_SOC_EVM=y
-+# CONFIG_SND_OMAP_SOC is not set
-+CONFIG_SND_SOC_I2C_AND_SPI=y
-+# CONFIG_SND_SOC_ALL_CODECS is not set
-+CONFIG_SND_SOC_TLV320AIC3X=y
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HIDRAW is not set
-+
-+#
-+# USB Input Devices
-+#
-+CONFIG_USB_HID=y
-+# CONFIG_HID_PID is not set
-+# CONFIG_USB_HIDDEV is not set
-+
-+#
-+# Special HID drivers
-+#
-+CONFIG_HID_A4TECH=y
-+# CONFIG_HID_ACRUX is not set
-+CONFIG_HID_APPLE=y
-+CONFIG_HID_BELKIN=y
-+CONFIG_HID_CHERRY=y
-+CONFIG_HID_CHICONY=y
-+# CONFIG_HID_PRODIKEYS is not set
-+CONFIG_HID_CYPRESS=y
-+# CONFIG_HID_DRAGONRISE is not set
-+# CONFIG_HID_EMS_FF is not set
-+CONFIG_HID_EZKEY=y
-+# CONFIG_HID_HOLTEK is not set
-+# CONFIG_HID_KEYTOUCH is not set
-+CONFIG_HID_KYE=y
-+# CONFIG_HID_UCLOGIC is not set
-+# CONFIG_HID_WALTOP is not set
-+# CONFIG_HID_GYRATION is not set
-+# CONFIG_HID_TWINHAN is not set
-+CONFIG_HID_KENSINGTON=y
-+# CONFIG_HID_LCPOWER is not set
-+CONFIG_HID_LOGITECH=y
-+CONFIG_HID_LOGITECH_DJ=m
-+# CONFIG_LOGITECH_FF is not set
-+# CONFIG_LOGIRUMBLEPAD2_FF is not set
-+# CONFIG_LOGIG940_FF is not set
-+# CONFIG_LOGIWHEELS_FF is not set
-+CONFIG_HID_MICROSOFT=y
-+CONFIG_HID_MONTEREY=y
-+# CONFIG_HID_MULTITOUCH is not set
-+# CONFIG_HID_NTRIG is not set
-+# CONFIG_HID_ORTEK is not set
-+# CONFIG_HID_PANTHERLORD is not set
-+# CONFIG_HID_PETALYNX is not set
-+# CONFIG_HID_PICOLCD is not set
-+# CONFIG_HID_PRIMAX is not set
-+# CONFIG_HID_QUANTA is not set
-+# CONFIG_HID_ROCCAT is not set
-+# CONFIG_HID_SAMSUNG is not set
-+# CONFIG_HID_SONY is not set
-+# CONFIG_HID_SPEEDLINK is not set
-+# CONFIG_HID_SUNPLUS is not set
-+# CONFIG_HID_GREENASIA is not set
-+# CONFIG_HID_SMARTJOYPLUS is not set
-+# CONFIG_HID_TOPSEED is not set
-+# CONFIG_HID_THRUSTMASTER is not set
-+# CONFIG_HID_ZEROPLUS is not set
-+# CONFIG_HID_ZYDACRON is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_COMMON=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB_ARCH_HAS_XHCI is not set
-+CONFIG_USB=y
-+# CONFIG_USB_DEBUG is not set
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+
-+#
-+# Miscellaneous USB options
-+#
-+CONFIG_USB_DEVICEFS=y
-+CONFIG_USB_DEVICE_CLASS=y
-+# CONFIG_USB_DYNAMIC_MINORS is not set
-+CONFIG_USB_SUSPEND=y
-+CONFIG_USB_OTG=y
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_DWC3 is not set
-+# CONFIG_USB_MON is not set
-+# CONFIG_USB_WUSB is not set
-+# CONFIG_USB_WUSB_CBAF is not set
-+
-+#
-+# USB Host Controller Drivers
-+#
-+# CONFIG_USB_C67X00_HCD is not set
-+# CONFIG_USB_EHCI_HCD is not set
-+# CONFIG_USB_OXU210HP_HCD is not set
-+# CONFIG_USB_ISP116X_HCD is not set
-+# CONFIG_USB_ISP1760_HCD is not set
-+# CONFIG_USB_ISP1362_HCD is not set
-+# CONFIG_USB_OHCI_HCD is not set
-+# CONFIG_USB_SL811_HCD is not set
-+# CONFIG_USB_R8A66597_HCD is not set
-+# CONFIG_USB_HWA_HCD is not set
-+CONFIG_USB_MUSB_HDRC=y
-+
-+#
-+# Platform Glue Layer
-+#
-+# CONFIG_USB_MUSB_TUSB6010_GLUE is not set
-+# CONFIG_USB_MUSB_OMAP2PLUS_GLUE is not set
-+# CONFIG_USB_MUSB_AM35X_GLUE is not set
-+CONFIG_USB_MUSB_TI81XX_GLUE=y
-+# CONFIG_USB_MUSB_DAVINCI is not set
-+# CONFIG_USB_MUSB_DA8XX is not set
-+# CONFIG_USB_MUSB_TUSB6010 is not set
-+# CONFIG_USB_MUSB_OMAP2PLUS is not set
-+# CONFIG_USB_MUSB_AM35X is not set
-+CONFIG_USB_MUSB_TI81XX=y
-+# CONFIG_USB_MUSB_BLACKFIN is not set
-+# CONFIG_USB_MUSB_UX500 is not set
-+CONFIG_USB_TI_CPPI41_DMA_HW=y
-+# CONFIG_MUSB_PIO_ONLY is not set
-+# CONFIG_USB_INVENTRA_DMA is not set
-+# CONFIG_USB_TI_CPPI_DMA is not set
-+CONFIG_USB_TI_CPPI41_DMA=y
-+# CONFIG_USB_TUSB_OMAP_DMA is not set
-+# CONFIG_USB_UX500_DMA is not set
-+# CONFIG_USB_RENESAS_USBHS is not set
-+
-+#
-+# USB Device Class drivers
-+#
-+# CONFIG_USB_ACM is not set
-+# CONFIG_USB_PRINTER is not set
-+# CONFIG_USB_WDM is not set
-+# CONFIG_USB_TMC is not set
-+
-+#
-+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-+#
-+
-+#
-+# also be needed; see USB_STORAGE Help for more info
-+#
-+CONFIG_USB_STORAGE=y
-+# CONFIG_USB_STORAGE_DEBUG is not set
-+# CONFIG_USB_STORAGE_REALTEK is not set
-+# CONFIG_USB_STORAGE_DATAFAB is not set
-+# CONFIG_USB_STORAGE_FREECOM is not set
-+# CONFIG_USB_STORAGE_ISD200 is not set
-+# CONFIG_USB_STORAGE_USBAT is not set
-+# CONFIG_USB_STORAGE_SDDR09 is not set
-+# CONFIG_USB_STORAGE_SDDR55 is not set
-+# CONFIG_USB_STORAGE_JUMPSHOT is not set
-+# CONFIG_USB_STORAGE_ALAUDA is not set
-+# CONFIG_USB_STORAGE_ONETOUCH is not set
-+# CONFIG_USB_STORAGE_KARMA is not set
-+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
-+# CONFIG_USB_UAS is not set
-+# CONFIG_USB_LIBUSUAL is not set
-+
-+#
-+# USB Imaging devices
-+#
-+# CONFIG_USB_MDC800 is not set
-+# CONFIG_USB_MICROTEK is not set
-+
-+#
-+# USB port drivers
-+#
-+# CONFIG_USB_SERIAL is not set
-+
-+#
-+# USB Miscellaneous drivers
-+#
-+# CONFIG_USB_EMI62 is not set
-+# CONFIG_USB_EMI26 is not set
-+# CONFIG_USB_ADUTUX is not set
-+# CONFIG_USB_SEVSEG is not set
-+# CONFIG_USB_RIO500 is not set
-+# CONFIG_USB_LEGOTOWER is not set
-+# CONFIG_USB_LCD is not set
-+# CONFIG_USB_LED is not set
-+# CONFIG_USB_CYPRESS_CY7C63 is not set
-+# CONFIG_USB_CYTHERM is not set
-+# CONFIG_USB_IDMOUSE is not set
-+# CONFIG_USB_FTDI_ELAN is not set
-+# CONFIG_USB_APPLEDISPLAY is not set
-+# CONFIG_USB_SISUSBVGA is not set
-+# CONFIG_USB_LD is not set
-+# CONFIG_USB_TRANCEVIBRATOR is not set
-+# CONFIG_USB_IOWARRIOR is not set
-+# CONFIG_USB_TEST is not set
-+# CONFIG_USB_ISIGHTFW is not set
-+# CONFIG_USB_YUREX is not set
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+CONFIG_USB_GADGET_VBUS_DRAW=2
-+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-+# CONFIG_USB_FUSB300 is not set
-+# CONFIG_USB_OMAP is not set
-+# CONFIG_USB_R8A66597 is not set
-+CONFIG_USB_GADGET_MUSB_HDRC=y
-+# CONFIG_USB_M66592 is not set
-+# CONFIG_USB_NET2272 is not set
-+# CONFIG_USB_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+# CONFIG_USB_ZERO is not set
-+# CONFIG_USB_AUDIO is not set
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+# CONFIG_USB_ETH_EEM is not set
-+# CONFIG_USB_G_NCM is not set
-+# CONFIG_USB_GADGETFS is not set
-+# CONFIG_USB_FUNCTIONFS is not set
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_MASS_STORAGE=m
-+# CONFIG_USB_G_SERIAL is not set
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+# CONFIG_USB_G_ACM_MS is not set
-+# CONFIG_USB_G_MULTI is not set
-+# CONFIG_USB_G_HID is not set
-+# CONFIG_USB_G_DBGP is not set
-+# CONFIG_USB_G_WEBCAM is not set
-+
-+#
-+# OTG and related infrastructure
-+#
-+CONFIG_USB_OTG_UTILS=y
-+# CONFIG_USB_GPIO_VBUS is not set
-+# CONFIG_USB_ULPI is not set
-+# CONFIG_TWL6030_USB is not set
-+CONFIG_NOP_USB_XCEIV=y
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+CONFIG_MMC_UNSAFE_RESUME=y
-+# CONFIG_MMC_CLKGATE is not set
-+
-+#
-+# MMC/SD/SDIO Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_MINORS=8
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD/SDIO Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+# CONFIG_MMC_SDHCI_PXAV3 is not set
-+# CONFIG_MMC_SDHCI_PXAV2 is not set
-+# CONFIG_MMC_OMAP is not set
-+CONFIG_MMC_OMAP_HS=y
-+# CONFIG_MMC_SPI is not set
-+# CONFIG_MMC_DW is not set
-+# CONFIG_MMC_VUB300 is not set
-+# CONFIG_MMC_USHC is not set
-+# CONFIG_MEMSTICK is not set
-+# CONFIG_NEW_LEDS is not set
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_DS3232 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_ISL12022 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_BQ32K is not set
-+# CONFIG_RTC_DRV_TWL4030 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+# CONFIG_RTC_DRV_RX8581 is not set
-+# CONFIG_RTC_DRV_RX8025 is not set
-+# CONFIG_RTC_DRV_EM3027 is not set
-+# CONFIG_RTC_DRV_RV3029C2 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T93 is not set
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_DS1390 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+# CONFIG_RTC_DRV_DS3234 is not set
-+# CONFIG_RTC_DRV_PCF2123 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_CMOS is not set
-+# CONFIG_RTC_DRV_DS1286 is not set
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T35 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_MSM6242 is not set
-+# CONFIG_RTC_DRV_BQ4802 is not set
-+# CONFIG_RTC_DRV_RP5C01 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_RTC_DRV_OMAP=y
-+# CONFIG_DMADEVICES is not set
-+# CONFIG_AUXDISPLAY is not set
-+# CONFIG_UIO is not set
-+
-+#
-+# Virtio drivers
-+#
-+# CONFIG_VIRTIO_BALLOON is not set
-+# CONFIG_VIRTIO_MMIO is not set
-+# CONFIG_STAGING is not set
-+CONFIG_CLKDEV_LOOKUP=y
-+
-+#
-+# Hardware Spinlock drivers
-+#
-+CONFIG_CLKSRC_MMIO=y
-+# CONFIG_IOMMU_SUPPORT is not set
-+# CONFIG_VIRT_DRIVERS is not set
-+# CONFIG_PM_DEVFREQ is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_GFS2_FS is not set
-+# CONFIG_BTRFS_FS is not set
-+# CONFIG_NILFS2_FS is not set
-+CONFIG_FS_POSIX_ACL=y
-+CONFIG_FILE_LOCKING=y
-+CONFIG_FSNOTIFY=y
-+CONFIG_DNOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_FANOTIFY is not set
-+CONFIG_QUOTA=y
-+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
-+CONFIG_PRINT_QUOTA_WARNING=y
-+# CONFIG_QUOTA_DEBUG is not set
-+CONFIG_QUOTA_TREE=y
-+# CONFIG_QFMT_V1 is not set
-+CONFIG_QFMT_V2=y
-+CONFIG_QUOTACTL=y
-+# CONFIG_AUTOFS4_FS is not set
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# Caches
-+#
-+# CONFIG_FSCACHE is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_TMPFS_XATTR is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+# CONFIG_CONFIGFS_FS is not set
-+CONFIG_MISC_FILESYSTEMS=y
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_ECRYPT_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+# CONFIG_JFFS2_FS is not set
-+CONFIG_UBIFS_FS=y
-+# CONFIG_UBIFS_FS_XATTR is not set
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_LOGFS is not set
-+CONFIG_CRAMFS=y
-+# CONFIG_SQUASHFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_PSTORE is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+# CONFIG_NFS_V4_1 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFS_USE_LEGACY_DNS is not set
-+CONFIG_NFS_USE_KERNEL_DNS=y
-+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_ACL_SUPPORT=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+CONFIG_SUNRPC_GSS=y
-+# CONFIG_CEPH_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_ACORN_PARTITION is not set
-+# CONFIG_OSF_PARTITION is not set
-+# CONFIG_AMIGA_PARTITION is not set
-+# CONFIG_ATARI_PARTITION is not set
-+# CONFIG_MAC_PARTITION is not set
-+CONFIG_MSDOS_PARTITION=y
-+# CONFIG_BSD_DISKLABEL is not set
-+# CONFIG_MINIX_SUBPARTITION is not set
-+# CONFIG_SOLARIS_X86_PARTITION is not set
-+# CONFIG_UNIXWARE_DISKLABEL is not set
-+# CONFIG_LDM_PARTITION is not set
-+# CONFIG_SGI_PARTITION is not set
-+# CONFIG_ULTRIX_PARTITION is not set
-+# CONFIG_SUN_PARTITION is not set
-+# CONFIG_KARMA_PARTITION is not set
-+# CONFIG_EFI_PARTITION is not set
-+# CONFIG_SYSV68_PARTITION is not set
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=y
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=y
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+# CONFIG_NLS_UTF8 is not set
-+
-+#
-+# Kernel hacking
-+#
-+CONFIG_PRINTK_TIME=y
-+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_STRIP_ASM_SYMS is not set
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+# CONFIG_DEBUG_SECTION_MISMATCH is not set
-+# CONFIG_DEBUG_KERNEL is not set
-+# CONFIG_HARDLOCKUP_DETECTOR is not set
-+# CONFIG_SPARSE_RCU_POINTER is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+CONFIG_DEBUG_MEMORY_INIT=y
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-+CONFIG_HAVE_FUNCTION_TRACER=y
-+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-+CONFIG_HAVE_DYNAMIC_FTRACE=y
-+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-+CONFIG_HAVE_C_RECORDMCOUNT=y
-+CONFIG_RING_BUFFER=y
-+CONFIG_RING_BUFFER_ALLOW_SWAP=y
-+CONFIG_TRACING_SUPPORT=y
-+# CONFIG_FTRACE is not set
-+CONFIG_DYNAMIC_DEBUG=y
-+# CONFIG_DMA_API_DEBUG is not set
-+# CONFIG_ATOMIC64_SELFTEST is not set
-+# CONFIG_SAMPLES is not set
-+CONFIG_HAVE_ARCH_KGDB=y
-+# CONFIG_TEST_KSTRTOX is not set
-+# CONFIG_STRICT_DEVMEM is not set
-+# CONFIG_ARM_UNWIND is not set
-+# CONFIG_DEBUG_USER is not set
-+CONFIG_DEBUG_JTAG_ENABLE=y
-+
-+#
-+# Security options
-+#
-+CONFIG_KEYS=y
-+# CONFIG_ENCRYPTED_KEYS is not set
-+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
-+# CONFIG_SECURITY_DMESG_RESTRICT is not set
-+CONFIG_SECURITY=y
-+# CONFIG_SECURITYFS is not set
-+# CONFIG_SECURITY_NETWORK is not set
-+# CONFIG_SECURITY_PATH is not set
-+# CONFIG_SECURITY_TOMOYO is not set
-+# CONFIG_SECURITY_APPARMOR is not set
-+# CONFIG_IMA is not set
-+# CONFIG_EVM is not set
-+CONFIG_DEFAULT_SECURITY_DAC=y
-+CONFIG_DEFAULT_SECURITY=""
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_ALGAPI2=y
-+CONFIG_CRYPTO_AEAD2=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_BLKCIPHER2=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_HASH2=y
-+CONFIG_CRYPTO_RNG2=y
-+CONFIG_CRYPTO_PCOMP2=y
-+CONFIG_CRYPTO_MANAGER=y
-+CONFIG_CRYPTO_MANAGER2=y
-+# CONFIG_CRYPTO_USER is not set
-+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+CONFIG_CRYPTO_WORKQUEUE=y
-+# CONFIG_CRYPTO_CRYPTD is not set
-+# CONFIG_CRYPTO_AUTHENC is not set
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+# CONFIG_CRYPTO_CBC is not set
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=y
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+# CONFIG_CRYPTO_HMAC is not set
-+# CONFIG_CRYPTO_XCBC is not set
-+# CONFIG_CRYPTO_VMAC is not set
-+
-+#
-+# Digest
-+#
-+CONFIG_CRYPTO_CRC32C=y
-+# CONFIG_CRYPTO_GHASH is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+# CONFIG_CRYPTO_MD5 is not set
-+CONFIG_CRYPTO_MICHAEL_MIC=y
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+# CONFIG_CRYPTO_SHA1 is not set
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+CONFIG_CRYPTO_AES=y
-+# CONFIG_CRYPTO_ANUBIS is not set
-+CONFIG_CRYPTO_ARC4=y
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+# CONFIG_CRYPTO_DES is not set
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+# CONFIG_CRYPTO_ZLIB is not set
-+CONFIG_CRYPTO_LZO=y
-+
-+#
-+# Random Number Generation
-+#
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_CRYPTO_USER_API_HASH is not set
-+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-+# CONFIG_CRYPTO_HW is not set
-+# CONFIG_BINARY_PRINTF is not set
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+CONFIG_CRC_CCITT=y
-+CONFIG_CRC16=y
-+CONFIG_CRC_T10DIF=y
-+CONFIG_CRC_ITU_T=y
-+CONFIG_CRC32=y
-+CONFIG_CRC7=y
-+CONFIG_LIBCRC32C=y
-+# CONFIG_CRC8 is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+CONFIG_XZ_DEC=y
-+CONFIG_XZ_DEC_X86=y
-+CONFIG_XZ_DEC_POWERPC=y
-+CONFIG_XZ_DEC_IA64=y
-+CONFIG_XZ_DEC_ARM=y
-+CONFIG_XZ_DEC_ARMTHUMB=y
-+CONFIG_XZ_DEC_SPARC=y
-+CONFIG_XZ_DEC_BCJ=y
-+# CONFIG_XZ_DEC_TEST is not set
-+CONFIG_DECOMPRESS_GZIP=y
-+CONFIG_DECOMPRESS_BZIP2=y
-+CONFIG_DECOMPRESS_LZMA=y
-+CONFIG_DECOMPRESS_XZ=y
-+CONFIG_DECOMPRESS_LZO=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-+CONFIG_NLATTR=y
-+CONFIG_AVERAGE=y
-+# CONFIG_CORDIC is not set
-diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
-index 945a34f..dde2a1a 100644
---- a/arch/arm/configs/omap1_defconfig
-+++ b/arch/arm/configs/omap1_defconfig
-@@ -48,7 +48,6 @@ CONFIG_MACH_SX1=y
- CONFIG_MACH_NOKIA770=y
- CONFIG_MACH_AMS_DELTA=y
- CONFIG_MACH_OMAP_GENERIC=y
--CONFIG_OMAP_ARM_182MHZ=y
- # CONFIG_ARM_THUMB is not set
- CONFIG_PCCARD=y
- CONFIG_OMAP_CF=y
-diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
-index d5f00d7..6c716aa 100644
---- a/arch/arm/configs/omap2plus_defconfig
-+++ b/arch/arm/configs/omap2plus_defconfig
-@@ -21,7 +21,8 @@ CONFIG_MODVERSIONS=y
- CONFIG_MODULE_SRCVERSION_ALL=y
- # CONFIG_BLK_DEV_BSG is not set
- CONFIG_ARCH_OMAP=y
--CONFIG_OMAP_RESET_CLOCKS=y
-+# CONFIG_OMAP_RESET_CLOCKS is not set
-+# CONFIG_OMAP_32K_TIMER is not set
- CONFIG_OMAP_MUX_DEBUG=y
- CONFIG_ARM_THUMBEE=y
- CONFIG_ARM_ERRATA_411920=y
-@@ -81,6 +82,8 @@ CONFIG_MTD_UBI=y
- CONFIG_BLK_DEV_LOOP=y
- CONFIG_BLK_DEV_RAM=y
- CONFIG_BLK_DEV_RAM_SIZE=16384
-+CONFIG_MISC_DEVICES=y
-+CONFIG_EEPROM_AT24=y
- CONFIG_SCSI=y
- CONFIG_BLK_DEV_SD=y
- CONFIG_SCSI_MULTI_LUN=y
-@@ -89,6 +92,9 @@ CONFIG_MD=y
- CONFIG_NETDEVICES=y
- CONFIG_SMSC_PHY=y
- CONFIG_NET_ETHERNET=y
-+CONFIG_TI_DAVINCI_MDIO=y
-+CONFIG_TI_DAVINCI_CPDMA=y
-+CONFIG_TI_CPSW=y
- CONFIG_SMC91X=y
- CONFIG_SMSC911X=y
- CONFIG_KS8851=y
-@@ -108,6 +114,7 @@ CONFIG_KEYBOARD_GPIO=y
- CONFIG_KEYBOARD_TWL4030=y
- CONFIG_INPUT_TOUCHSCREEN=y
- CONFIG_TOUCHSCREEN_ADS7846=y
-+CONFIG_TOUCHSCREEN_TI_TSCADC=y
- CONFIG_INPUT_MISC=y
- CONFIG_INPUT_TWL4030_PWRBUTTON=y
- CONFIG_VT_HW_CONSOLE_BINDING=y
-@@ -151,14 +158,23 @@ CONFIG_PANEL_TPO_TD043MTEA1=m
- CONFIG_PANEL_ACX565AKM=m
- CONFIG_BACKLIGHT_LCD_SUPPORT=y
- CONFIG_LCD_CLASS_DEVICE=y
-+CONFIG_BACKLIGHT_CLASS_DEVICE=y
-+# CONFIG_BACKLIGHT_GENERIC is not set
-+# CONFIG_BACKLIGHT_ADP8860 is not set
-+CONFIG_BACKLIGHT_TLC59108=y
- CONFIG_LCD_PLATFORM=y
- CONFIG_DISPLAY_SUPPORT=y
-+CONFIG_FB_DA8XX=y
-+CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE=4
- CONFIG_FRAMEBUFFER_CONSOLE=y
- CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
- CONFIG_FONTS=y
- CONFIG_FONT_8x8=y
- CONFIG_FONT_8x16=y
- CONFIG_LOGO=y
-+CONFIG_LOGO_LINUX_MONO=y
-+CONFIG_LOGO_LINUX_VGA16=y
-+CONFIG_LOGO_LINUX_CLUT224=y
- CONFIG_SOUND=m
- CONFIG_SND=m
- CONFIG_SND_MIXER_OSS=m
-@@ -225,6 +241,9 @@ CONFIG_PROVE_LOCKING=y
- CONFIG_DEBUG_SPINLOCK_SLEEP=y
- # CONFIG_DEBUG_BUGVERBOSE is not set
- CONFIG_DEBUG_INFO=y
-+ONFIG_DEBUG_LL=y
-+CONFIG_DEBUG_LL_UART_NONE=y
-+CONFIG_EARLY_PRINTK=y
- # CONFIG_RCU_CPU_STALL_DETECTOR is not set
- CONFIG_SECURITY=y
- CONFIG_CRYPTO_MICHAEL_MIC=y
-diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
-new file mode 100644
-index 0000000..a0ada3e
---- /dev/null
-+++ b/arch/arm/include/asm/cti.h
-@@ -0,0 +1,179 @@
-+#ifndef __ASMARM_CTI_H
-+#define __ASMARM_CTI_H
-+
-+#include	<asm/io.h>
-+
-+/* The registers' definition is from section 3.2 of
-+ * Embedded Cross Trigger Revision: r0p0
-+ */
-+#define		CTICONTROL		0x000
-+#define		CTISTATUS		0x004
-+#define		CTILOCK			0x008
-+#define		CTIPROTECTION		0x00C
-+#define		CTIINTACK		0x010
-+#define		CTIAPPSET		0x014
-+#define		CTIAPPCLEAR		0x018
-+#define		CTIAPPPULSE		0x01c
-+#define		CTIINEN			0x020
-+#define		CTIOUTEN		0x0A0
-+#define		CTITRIGINSTATUS		0x130
-+#define		CTITRIGOUTSTATUS	0x134
-+#define		CTICHINSTATUS		0x138
-+#define		CTICHOUTSTATUS		0x13c
-+#define		CTIPERIPHID0		0xFE0
-+#define		CTIPERIPHID1		0xFE4
-+#define		CTIPERIPHID2		0xFE8
-+#define		CTIPERIPHID3		0xFEC
-+#define		CTIPCELLID0		0xFF0
-+#define		CTIPCELLID1		0xFF4
-+#define		CTIPCELLID2		0xFF8
-+#define		CTIPCELLID3		0xFFC
-+
-+/* The below are from section 3.6.4 of
-+ * CoreSight v1.0 Architecture Specification
-+ */
-+#define		LOCKACCESS		0xFB0
-+#define		LOCKSTATUS		0xFB4
-+
-+/* write this value to LOCKACCESS will unlock the module, and
-+ * other value will lock the module
-+ */
-+#define		LOCKCODE		0xC5ACCE55
-+
-+/**
-+ * struct cti - cross trigger interface struct
-+ * @base: mapped virtual address for the cti base
-+ * @irq: irq number for the cti
-+ * @trig_out_for_irq: triger out number which will cause
-+ *	the @irq happen
-+ *
-+ * cti struct used to operate cti registers.
-+ */
-+struct cti {
-+	void __iomem *base;
-+	int irq;
-+	int trig_out_for_irq;
-+};
-+
-+/**
-+ * cti_init - initialize the cti instance
-+ * @cti: cti instance
-+ * @base: mapped virtual address for the cti base
-+ * @irq: irq number for the cti
-+ * @trig_out: triger out number which will cause
-+ *	the @irq happen
-+ *
-+ * called by machine code to pass the board dependent
-+ * @base, @irq and @trig_out to cti.
-+ */
-+static inline void cti_init(struct cti *cti,
-+	void __iomem *base, int irq, int trig_out)
-+{
-+	cti->base = base;
-+	cti->irq  = irq;
-+	cti->trig_out_for_irq = trig_out;
-+}
-+
-+/**
-+ * cti_map_trigger - use the @chan to map @trig_in to @trig_out
-+ * @cti: cti instance
-+ * @trig_in: trigger in number
-+ * @trig_out: trigger out number
-+ * @channel: channel number
-+ *
-+ * This function maps one trigger in of @trig_in to one trigger
-+ * out of @trig_out using the channel @chan.
-+ */
-+static inline void cti_map_trigger(struct cti *cti,
-+	int trig_in, int trig_out, int chan)
-+{
-+	void __iomem *base = cti->base;
-+	unsigned long val;
-+
-+	val = __raw_readl(base + CTIINEN + trig_in * 4);
-+	val |= BIT(chan);
-+	__raw_writel(val, base + CTIINEN + trig_in * 4);
-+
-+	val = __raw_readl(base + CTIOUTEN + trig_out * 4);
-+	val |= BIT(chan);
-+	__raw_writel(val, base + CTIOUTEN + trig_out * 4);
-+}
-+
-+/**
-+ * cti_enable - enable the cti module
-+ * @cti: cti instance
-+ *
-+ * enable the cti module
-+ */
-+static inline void cti_enable(struct cti *cti)
-+{
-+	__raw_writel(0x1, cti->base + CTICONTROL);
-+}
-+
-+/**
-+ * cti_disable - disable the cti module
-+ * @cti: cti instance
-+ *
-+ * enable the cti module
-+ */
-+static inline void cti_disable(struct cti *cti)
-+{
-+	__raw_writel(0, cti->base + CTICONTROL);
-+}
-+
-+/**
-+ * cti_irq_ack - clear the cti irq
-+ * @cti: cti instance
-+ *
-+ * clear the cti irq
-+ */
-+static inline void cti_irq_ack(struct cti *cti)
-+{
-+	void __iomem *base = cti->base;
-+	unsigned long val;
-+
-+	val = __raw_readl(base + CTIINTACK);
-+	val |= BIT(cti->trig_out_for_irq);
-+	__raw_writel(val, base + CTIINTACK);
-+}
-+
-+/**
-+ * cti_unlock - unlock cti module
-+ * @cti: cti instance
-+ *
-+ * unlock the cti module, or else any writes to the cti
-+ * module is not allowed.
-+ */
-+static inline void cti_unlock(struct cti *cti)
-+{
-+	void __iomem *base = cti->base;
-+	unsigned long val;
-+
-+	val = __raw_readl(base + LOCKSTATUS);
-+
-+	if (val & 1) {
-+		val = LOCKCODE;
-+		__raw_writel(val, base + LOCKACCESS);
-+	}
-+}
-+
-+/**
-+ * cti_lock - lock cti module
-+ * @cti: cti instance
-+ *
-+ * lock the cti module, so any writes to the cti
-+ * module will be not allowed.
-+ */
-+static inline void cti_lock(struct cti *cti)
-+{
-+	void __iomem *base = cti->base;
-+	unsigned long val;
-+
-+	val = __raw_readl(base + LOCKSTATUS);
-+
-+	if (!(val & 1)) {
-+		val = ~LOCKCODE;
-+		__raw_writel(val, base + LOCKACCESS);
-+	}
-+}
-+#endif
-diff --git a/arch/arm/include/asm/entry-macro-vic2.S b/arch/arm/include/asm/entry-macro-vic2.S
-deleted file mode 100644
-index 3ceb85e..0000000
---- a/arch/arm/include/asm/entry-macro-vic2.S
-+++ /dev/null
-@@ -1,57 +0,0 @@
--/* arch/arm/include/asm/entry-macro-vic2.S
-- *
-- * Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S
-- *
-- * Copyright 2008 Openmoko, Inc.
-- * Copyright 2008 Simtec Electronics
-- *	http://armlinux.simtec.co.uk/
-- *	Ben Dooks <ben@simtec.co.uk>
-- *
-- * Low-level IRQ helper macros for a device with two VICs
-- *
-- * This file is licensed under  the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
--*/
--
--/* This should be included from <mach/entry-macro.S> with the necessary
-- * defines for virtual addresses and IRQ bases for the two vics.
-- *
-- * The code needs the following defined:
-- *	IRQ_VIC0_BASE	IRQ number of VIC0's first IRQ
-- *	IRQ_VIC1_BASE	IRQ number of VIC1's first IRQ
-- *	VA_VIC0		Virtual address of VIC0
-- *	VA_VIC1		Virtual address of VIC1
-- *
-- * Note, code assumes VIC0's virtual address is an ARM immediate constant
-- * away from VIC1.
--*/
--
--#include <asm/hardware/vic.h>
--
--	.macro	disable_fiq
--	.endm
--
--	.macro	get_irqnr_preamble, base, tmp
--	ldr	\base, =VA_VIC0
--	.endm
--
--	.macro	arch_ret_to_user, tmp1, tmp2
--	.endm
--
--	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--
--	@ check the vic0
--	mov	\irqnr, #IRQ_VIC0_BASE + 31
--	ldr	\irqstat, [ \base, # VIC_IRQ_STATUS ]
--	teq	\irqstat, #0
--
--	@ otherwise try vic1
--	addeq	\tmp, \base, #(VA_VIC1 - VA_VIC0)
--	addeq	\irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE)
--	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
--	teqeq	\irqstat, #0
--
--	clzne	\irqstat, \irqstat
--	subne	\irqnr, \irqnr, \irqstat
--	.endm
-diff --git a/arch/arm/include/asm/hardware/asp.h b/arch/arm/include/asm/hardware/asp.h
-new file mode 100644
-index 0000000..0d5c0bf
---- /dev/null
-+++ b/arch/arm/include/asm/hardware/asp.h
-@@ -0,0 +1,143 @@
-+/*
-+ * <asm/hardware/asp.h> - DaVinci Audio Serial Port support
-+ */
-+#ifndef __ASM_HARDWARE_MCASP_H
-+#define __ASM_HARDWARE_MCASP_H
-+
-+#include <mach/irqs.h>
-+#include <mach/edma.h>
-+
-+/* Bases of dm644x and dm355 register banks */
-+#define DAVINCI_ASP0_BASE	0x01E02000
-+#define DAVINCI_ASP1_BASE	0x01E04000
-+
-+/* Bases of dm365 register banks */
-+#define DAVINCI_DM365_ASP0_BASE	0x01D02000
-+
-+/* Bases of dm646x register banks */
-+#define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
-+#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
-+
-+/* Bases of da850/da830 McASP0  register banks */
-+#define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
-+
-+/* Bases of da830 McASP1 register banks */
-+#define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
-+
-+/* EDMA channels of dm644x and dm355 */
-+#define DAVINCI_DMA_ASP0_TX	2
-+#define DAVINCI_DMA_ASP0_RX	3
-+#define DAVINCI_DMA_ASP1_TX	8
-+#define DAVINCI_DMA_ASP1_RX	9
-+
-+/* EDMA channels of dm646x */
-+#define	DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
-+#define	DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
-+#define	DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
-+
-+/* EDMA channels of da850/da830 McASP0 */
-+#define	DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
-+#define	DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
-+
-+/* EDMA channels of da830 McASP1 */
-+#define	DAVINCI_DA830_DMA_MCASP1_AREVT	2
-+#define	DAVINCI_DA830_DMA_MCASP1_AXEVT	3
-+
-+/* Interrupts */
-+#define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
-+#define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
-+#define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
-+#define DAVINCI_ASP1_TX_INT	IRQ_MBXINT
-+
-+struct snd_platform_data {
-+	u32 tx_dma_offset;
-+	u32 rx_dma_offset;
-+	enum dma_event_q asp_chan_q;	/* event queue number for ASP channel */
-+	enum dma_event_q ram_chan_q;	/* event queue number for RAM channel */
-+	unsigned int codec_fmt;
-+	/*
-+	 * Allowing this is more efficient and eliminates left and right swaps
-+	 * caused by underruns, but will swap the left and right channels
-+	 * when compared to previous behavior.
-+	 */
-+	unsigned enable_channel_combine:1;
-+	unsigned sram_size_playback;
-+	unsigned sram_size_capture;
-+
-+	/*
-+	 * If McBSP peripheral gets the clock from an external pin,
-+	 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
-+	 * and MCBSP_CLKS.
-+	 * Depending on different hardware connections it is possible
-+	 * to use this setting to change the behaviour of McBSP
-+	 * driver. The dm365_clk_input_pin enum is available for dm365
-+	 */
-+	int clk_input_pin;
-+
-+	/*
-+	 * This flag works when both clock and FS are outputs for the cpu
-+	 * and makes clock more accurate (FS is not symmetrical and the
-+	 * clock is very fast.
-+	 * The clock becoming faster is named
-+	 * i2s continuous serial clock (I2S_SCK) and it is an externally
-+	 * visible bit clock.
-+	 *
-+	 * first line : WordSelect
-+	 * second line : ContinuousSerialClock
-+	 * third line: SerialData
-+	 *
-+	 * SYMMETRICAL APPROACH:
-+	 *   _______________________          LEFT
-+	 * _|         RIGHT         |______________________|
-+	 *     _   _         _   _   _   _         _   _
-+	 *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
-+	 *     _   _         _   _   _   _         _   _
-+	 *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
-+	 *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
-+	 *
-+	 * ACCURATE CLOCK APPROACH:
-+	 *   ______________          LEFT
-+	 * _|     RIGHT    |_______________________________|
-+	 *     _         _   _         _   _   _   _   _   _
-+	 *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
-+	 *     _         _   _          _      dummy cycles
-+	 *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
-+	 *    \_/       \_/ \_/        \_/
-+	 *
-+	 */
-+	bool i2s_accurate_sck;
-+
-+	/* McASP specific fields */
-+	int tdm_slots;
-+	u8 op_mode;
-+	u8 num_serializer;
-+	u8 *serial_dir;
-+	u8 version;
-+	u8 txnumevt;
-+	u8 rxnumevt;
-+};
-+
-+enum {
-+	MCASP_VERSION_1 = 0,	/* DM646x */
-+	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
-+	MCASP_VERSION_3,	/* AM33xx */
-+};
-+
-+enum dm365_clk_input_pin {
-+	MCBSP_CLKR = 0,		/* DM365 */
-+	MCBSP_CLKS,
-+};
-+
-+#define INACTIVE_MODE	0
-+#define TX_MODE		1
-+#define RX_MODE		2
-+
-+#define DAVINCI_MCASP_IIS_MODE	0
-+#define DAVINCI_MCASP_DIT_MODE	1
-+
-+#if (defined(CONFIG_SOC_OMAPAM33XX) && (defined(CONFIG_SND_AM33XX_SOC) \
-+				|| (defined(CONFIG_SND_AM33XX_SOC_MODULE))))
-+#define davinci_gen_pool omap_gen_pool
-+#endif
-+
-+#endif /* __ASM_HARDWARE_MCASP_H */
-diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
-deleted file mode 100644
-index 74ebc80..0000000
---- a/arch/arm/include/asm/hardware/entry-macro-gic.S
-+++ /dev/null
-@@ -1,60 +0,0 @@
--/*
-- * arch/arm/include/asm/hardware/entry-macro-gic.S
-- *
-- * Low-level IRQ helper macros for GIC
-- *
-- * This file is licensed under  the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-- */
--
--#include <asm/hardware/gic.h>
--
--#ifndef HAVE_GET_IRQNR_PREAMBLE
--	.macro	get_irqnr_preamble, base, tmp
--	ldr	\base, =gic_cpu_base_addr
--	ldr	\base, [\base]
--	.endm
--#endif
--
--/*
-- * The interrupt numbering scheme is defined in the
-- * interrupt controller spec.  To wit:
-- *
-- * Interrupts 0-15 are IPI
-- * 16-31 are local.  We allow 30 to be used for the watchdog.
-- * 32-1020 are global
-- * 1021-1022 are reserved
-- * 1023 is "spurious" (no interrupt)
-- *
-- * A simple read from the controller will tell us the number of the highest
-- * priority enabled interrupt.  We then just need to check whether it is in the
-- * valid range for an IRQ (30-1020 inclusive).
-- */
--
--	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
--
--	ldr     \irqstat, [\base, #GIC_CPU_INTACK]
--	/* bits 12-10 = src CPU, 9-0 = int # */
--
--	ldr	\tmp, =1021
--	bic     \irqnr, \irqstat, #0x1c00
--	cmp     \irqnr, #15
--	cmpcc	\irqnr, \irqnr
--	cmpne	\irqnr, \tmp
--	cmpcs	\irqnr, \irqnr
--	.endm
--
--/* We assume that irqstat (the raw value of the IRQ acknowledge
-- * register) is preserved from the macro above.
-- * If there is an IPI, we immediately signal end of interrupt on the
-- * controller, since this requires the original irqstat value which
-- * we won't easily be able to recreate later.
-- */
--
--	.macro test_for_ipi, irqnr, irqstat, base, tmp
--	bic	\irqnr, \irqstat, #0x1c00
--	cmp	\irqnr, #16
--	strcc	\irqstat, [\base, #GIC_CPU_EOI]
--	cmpcs	\irqnr, \irqnr
--	.endm
-diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
-index 3e91f22..4bdfe00 100644
---- a/arch/arm/include/asm/hardware/gic.h
-+++ b/arch/arm/include/asm/hardware/gic.h
-@@ -36,30 +36,22 @@
- #include <linux/irqdomain.h>
- struct device_node;
- 
--extern void __iomem *gic_cpu_base_addr;
- extern struct irq_chip gic_arch_extn;
- 
--void gic_init(unsigned int, int, void __iomem *, void __iomem *);
-+void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
-+		    u32 offset);
- int gic_of_init(struct device_node *node, struct device_node *parent);
- void gic_secondary_init(unsigned int);
-+void gic_handle_irq(struct pt_regs *regs);
- void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
- void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
- 
--struct gic_chip_data {
--	void __iomem *dist_base;
--	void __iomem *cpu_base;
--#ifdef CONFIG_CPU_PM
--	u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
--	u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
--	u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
--	u32 __percpu *saved_ppi_enable;
--	u32 __percpu *saved_ppi_conf;
--#endif
--#ifdef CONFIG_IRQ_DOMAIN
--	struct irq_domain domain;
--#endif
--	unsigned int gic_irqs;
--};
-+static inline void gic_init(unsigned int nr, int start,
-+			    void __iomem *dist , void __iomem *cpu)
-+{
-+	gic_init_bases(nr, start, dist, cpu, 0);
-+}
-+
- #endif
- 
- #endif
-diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
-index 5d72550..f42ebd6 100644
---- a/arch/arm/include/asm/hardware/vic.h
-+++ b/arch/arm/include/asm/hardware/vic.h
-@@ -41,7 +41,15 @@
- #define VIC_PL192_VECT_ADDR		0xF00
- 
- #ifndef __ASSEMBLY__
-+#include <linux/compiler.h>
-+#include <linux/types.h>
-+
-+struct device_node;
-+struct pt_regs;
-+
- void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
--#endif
-+int vic_of_init(struct device_node *node, struct device_node *parent);
-+void vic_handle_irq(struct pt_regs *regs);
- 
-+#endif /* __ASSEMBLY__ */
- #endif
-diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
-index 2b0efc3..bcb0c88 100644
---- a/arch/arm/include/asm/mach/arch.h
-+++ b/arch/arm/include/asm/mach/arch.h
-@@ -31,10 +31,10 @@ struct machine_desc {
- 	unsigned int		video_start;	/* start of video RAM	*/
- 	unsigned int		video_end;	/* end of video RAM	*/
- 
--	unsigned int		reserve_lp0 :1;	/* never has lp0	*/
--	unsigned int		reserve_lp1 :1;	/* never has lp1	*/
--	unsigned int		reserve_lp2 :1;	/* never has lp2	*/
--	unsigned int		soft_reboot :1;	/* soft reboot		*/
-+	unsigned char		reserve_lp0 :1;	/* never has lp0	*/
-+	unsigned char		reserve_lp1 :1;	/* never has lp1	*/
-+	unsigned char		reserve_lp2 :1;	/* never has lp2	*/
-+	char			restart_mode;	/* default restart mode	*/
- 	void			(*fixup)(struct tag *, char **,
- 					 struct meminfo *);
- 	void			(*reserve)(void);/* reserve mem blocks	*/
-@@ -46,6 +46,7 @@ struct machine_desc {
- #ifdef CONFIG_MULTI_IRQ_HANDLER
- 	void			(*handle_irq)(struct pt_regs *);
- #endif
-+	void			(*restart)(char, const char *);
- };
- 
- /*
-diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
-index 0f8e382..99cfe36 100644
---- a/arch/arm/include/asm/perf_event.h
-+++ b/arch/arm/include/asm/perf_event.h
-@@ -32,7 +32,4 @@ enum arm_perf_pmu_ids {
- extern enum arm_perf_pmu_ids
- armpmu_get_pmu_id(void);
- 
--extern int
--armpmu_get_max_events(void);
--
- #endif /* __ARM_PERF_EVENT_H__ */
-diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
-index 9451dce..bcae9b8 100644
---- a/arch/arm/include/asm/pgtable.h
-+++ b/arch/arm/include/asm/pgtable.h
-@@ -21,7 +21,6 @@
- #else
- 
- #include <asm/memory.h>
--#include <mach/vmalloc.h>
- #include <asm/pgtable-hwdef.h>
- 
- #include <asm/pgtable-2level.h>
-@@ -33,14 +32,16 @@
-  * any out-of-bounds memory accesses will hopefully be caught.
-  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
-  * area for the same reason. ;)
-- *
-- * Note that platforms may override VMALLOC_START, but they must provide
-- * VMALLOC_END.  VMALLOC_END defines the (exclusive) limit of this space,
-- * which may not overlap IO space.
-  */
--#ifndef VMALLOC_START
- #define VMALLOC_OFFSET		(8*1024*1024)
- #define VMALLOC_START		(((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
-+#define VMALLOC_END		0xff000000UL
-+
-+/* This is a temporary hack until shmobile's DMA area size is sorted out */
-+#ifdef CONFIG_ARCH_SHMOBILE
-+#warning "SH-Mobile's consistent DMA size conflicts with VMALLOC_END by 144MB"
-+#undef VMALLOC_END
-+#define VMALLOC_END		0xF6000000UL
- #endif
- 
- #define LIBRARY_TEXT_START	0x0c000000
-diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
-index 665ef2c..90114fa 100644
---- a/arch/arm/include/asm/pmu.h
-+++ b/arch/arm/include/asm/pmu.h
-@@ -27,13 +27,22 @@ enum arm_pmu_type {
- /*
-  * struct arm_pmu_platdata - ARM PMU platform data
-  *
-- * @handle_irq: an optional handler which will be called from the interrupt and
-- * passed the address of the low level handler, and can be used to implement
-- * any platform specific handling before or after calling it.
-+ * @handle_irq: an optional handler which will be called from the
-+ *	interrupt and passed the address of the low level handler,
-+ *	and can be used to implement any platform specific handling
-+ *	before or after calling it.
-+ * @enable_irq: an optional handler which will be called after
-+ *	request_irq and be used to handle some platform specific
-+ *	irq enablement
-+ * @disable_irq: an optional handler which will be called before
-+ *	free_irq and be used to handle some platform specific
-+ *	irq disablement
-  */
- struct arm_pmu_platdata {
- 	irqreturn_t (*handle_irq)(int irq, void *dev,
- 				  irq_handler_t pmu_handler);
-+	void (*enable_irq)(int irq);
-+	void (*disable_irq)(int irq);
- };
- 
- #ifdef CONFIG_CPU_HAS_PMU
-diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
-index 984014b..fe7de75 100644
---- a/arch/arm/include/asm/system.h
-+++ b/arch/arm/include/asm/system.h
-@@ -101,6 +101,7 @@ extern int __pure cpu_architecture(void);
- extern void cpu_init(void);
- 
- void arm_machine_restart(char mode, const char *cmd);
-+void soft_restart(unsigned long);
- extern void (*arm_pm_restart)(char str, const char *cmd);
- 
- #define UDBG_UNDEFINED	(1 << 0)
-diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
-index b145f16..3a456c6 100644
---- a/arch/arm/kernel/entry-armv.S
-+++ b/arch/arm/kernel/entry-armv.S
-@@ -36,12 +36,11 @@
- #ifdef CONFIG_MULTI_IRQ_HANDLER
- 	ldr	r1, =handle_arch_irq
- 	mov	r0, sp
--	ldr	r1, [r1]
- 	adr	lr, BSYM(9997f)
--	teq	r1, #0
--	movne	pc, r1
--#endif
-+	ldr	pc, [r1]
-+#else
- 	arch_irq_handler_default
-+#endif
- 9997:
- 	.endm
- 
-diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
-index e59bbd4..29620b6 100644
---- a/arch/arm/kernel/machine_kexec.c
-+++ b/arch/arm/kernel/machine_kexec.c
-@@ -16,7 +16,7 @@
- extern const unsigned char relocate_new_kernel[];
- extern const unsigned int relocate_new_kernel_size;
- 
--extern void setup_mm_for_reboot(char mode);
-+extern void setup_mm_for_reboot(void);
- 
- extern unsigned long kexec_start_address;
- extern unsigned long kexec_indirection_page;
-@@ -113,7 +113,7 @@ void machine_kexec(struct kimage *image)
- 		kexec_reinit();
- 	local_irq_disable();
- 	local_fiq_disable();
--	setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
-+	setup_mm_for_reboot();
- 	flush_cache_all();
- 	outer_flush_all();
- 	outer_disable();
-diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
-index ecebb89..56173ae 100644
---- a/arch/arm/kernel/perf_event.c
-+++ b/arch/arm/kernel/perf_event.c
-@@ -59,8 +59,7 @@ armpmu_get_pmu_id(void)
- }
- EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
- 
--int
--armpmu_get_max_events(void)
-+int perf_num_counters(void)
- {
- 	int max_events = 0;
- 
-@@ -69,12 +68,6 @@ armpmu_get_max_events(void)
- 
- 	return max_events;
- }
--EXPORT_SYMBOL_GPL(armpmu_get_max_events);
--
--int perf_num_counters(void)
--{
--	return armpmu_get_max_events();
--}
- EXPORT_SYMBOL_GPL(perf_num_counters);
- 
- #define HW_OP_UNSUPPORTED		0xFFFF
-@@ -374,6 +367,8 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
- {
- 	int i, irq, irqs;
- 	struct platform_device *pmu_device = armpmu->plat_device;
-+	struct arm_pmu_platdata *plat =
-+		dev_get_platdata(&pmu_device->dev);
- 
- 	irqs = min(pmu_device->num_resources, num_possible_cpus());
- 
-@@ -381,8 +376,11 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
- 		if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
- 			continue;
- 		irq = platform_get_irq(pmu_device, i);
--		if (irq >= 0)
-+		if (irq >= 0) {
-+			if (plat && plat->disable_irq)
-+				plat->disable_irq(irq);
- 			free_irq(irq, armpmu);
-+		}
- 	}
- 
- 	release_pmu(armpmu->type);
-@@ -442,7 +440,8 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
- 				irq);
- 			armpmu_release_hardware(armpmu);
- 			return err;
--		}
-+		} else if (plat && plat->enable_irq)
-+			plat->enable_irq(irq);
- 
- 		cpumask_set_cpu(i, &armpmu->active_irqs);
- 	}
-diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
-index 0ad3c6f..b78af0c 100644
---- a/arch/arm/kernel/perf_event_v6.c
-+++ b/arch/arm/kernel/perf_event_v6.c
-@@ -65,13 +65,15 @@ enum armv6_counters {
-  * accesses/misses in hardware.
-  */
- static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
--	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV6_PERFCTR_CPU_CYCLES,
--	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV6_PERFCTR_INSTR_EXEC,
--	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
--	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV6_PERFCTR_BR_MISPREDICT,
--	[PERF_COUNT_HW_BUS_CYCLES]	    = HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_CPU_CYCLES]		= ARMV6_PERFCTR_CPU_CYCLES,
-+	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV6_PERFCTR_INSTR_EXEC,
-+	[PERF_COUNT_HW_CACHE_REFERENCES]	= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_CACHE_MISSES]		= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= ARMV6_PERFCTR_BR_EXEC,
-+	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV6_PERFCTR_BR_MISPREDICT,
-+	[PERF_COUNT_HW_BUS_CYCLES]		= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= ARMV6_PERFCTR_IBUF_STALL,
-+	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= ARMV6_PERFCTR_LSU_FULL_STALL,
- };
- 
- static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-@@ -218,13 +220,15 @@ enum armv6mpcore_perf_types {
-  * accesses/misses in hardware.
-  */
- static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
--	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
--	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
--	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
--	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
--	[PERF_COUNT_HW_BUS_CYCLES]	    = HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_CPU_CYCLES]		= ARMV6MPCORE_PERFCTR_CPU_CYCLES,
-+	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV6MPCORE_PERFCTR_INSTR_EXEC,
-+	[PERF_COUNT_HW_CACHE_REFERENCES]	= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_CACHE_MISSES]		= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= ARMV6MPCORE_PERFCTR_BR_EXEC,
-+	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
-+	[PERF_COUNT_HW_BUS_CYCLES]		= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= ARMV6MPCORE_PERFCTR_IBUF_STALL,
-+	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
- };
- 
- static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
-index 1049319..2127ca3 100644
---- a/arch/arm/kernel/perf_event_v7.c
-+++ b/arch/arm/kernel/perf_event_v7.c
-@@ -28,165 +28,87 @@ static struct arm_pmu armv7pmu;
-  * they are not available.
-  */
- enum armv7_perf_types {
--	ARMV7_PERFCTR_PMNC_SW_INCR		= 0x00,
--	ARMV7_PERFCTR_IFETCH_MISS		= 0x01,
--	ARMV7_PERFCTR_ITLB_MISS			= 0x02,
--	ARMV7_PERFCTR_DCACHE_REFILL		= 0x03,	/* L1 */
--	ARMV7_PERFCTR_DCACHE_ACCESS		= 0x04,	/* L1 */
--	ARMV7_PERFCTR_DTLB_REFILL		= 0x05,
--	ARMV7_PERFCTR_DREAD			= 0x06,
--	ARMV7_PERFCTR_DWRITE			= 0x07,
--	ARMV7_PERFCTR_INSTR_EXECUTED		= 0x08,
--	ARMV7_PERFCTR_EXC_TAKEN			= 0x09,
--	ARMV7_PERFCTR_EXC_EXECUTED		= 0x0A,
--	ARMV7_PERFCTR_CID_WRITE			= 0x0B,
--	/* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
-+	ARMV7_PERFCTR_PMNC_SW_INCR			= 0x00,
-+	ARMV7_PERFCTR_L1_ICACHE_REFILL			= 0x01,
-+	ARMV7_PERFCTR_ITLB_REFILL			= 0x02,
-+	ARMV7_PERFCTR_L1_DCACHE_REFILL			= 0x03,
-+	ARMV7_PERFCTR_L1_DCACHE_ACCESS			= 0x04,
-+	ARMV7_PERFCTR_DTLB_REFILL			= 0x05,
-+	ARMV7_PERFCTR_MEM_READ				= 0x06,
-+	ARMV7_PERFCTR_MEM_WRITE				= 0x07,
-+	ARMV7_PERFCTR_INSTR_EXECUTED			= 0x08,
-+	ARMV7_PERFCTR_EXC_TAKEN				= 0x09,
-+	ARMV7_PERFCTR_EXC_EXECUTED			= 0x0A,
-+	ARMV7_PERFCTR_CID_WRITE				= 0x0B,
-+
-+	/*
-+	 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
- 	 * It counts:
--	 *  - all branch instructions,
-+	 *  - all (taken) branch instructions,
- 	 *  - instructions that explicitly write the PC,
- 	 *  - exception generating instructions.
- 	 */
--	ARMV7_PERFCTR_PC_WRITE			= 0x0C,
--	ARMV7_PERFCTR_PC_IMM_BRANCH		= 0x0D,
--	ARMV7_PERFCTR_PC_PROC_RETURN		= 0x0E,
--	ARMV7_PERFCTR_UNALIGNED_ACCESS		= 0x0F,
-+	ARMV7_PERFCTR_PC_WRITE				= 0x0C,
-+	ARMV7_PERFCTR_PC_IMM_BRANCH			= 0x0D,
-+	ARMV7_PERFCTR_PC_PROC_RETURN			= 0x0E,
-+	ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS		= 0x0F,
-+	ARMV7_PERFCTR_PC_BRANCH_MIS_PRED		= 0x10,
-+	ARMV7_PERFCTR_CLOCK_CYCLES			= 0x11,
-+	ARMV7_PERFCTR_PC_BRANCH_PRED			= 0x12,
- 
- 	/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
--	ARMV7_PERFCTR_PC_BRANCH_MIS_PRED	= 0x10,
--	ARMV7_PERFCTR_CLOCK_CYCLES		= 0x11,
--	ARMV7_PERFCTR_PC_BRANCH_PRED		= 0x12,
--	ARMV7_PERFCTR_MEM_ACCESS		= 0x13,
--	ARMV7_PERFCTR_L1_ICACHE_ACCESS		= 0x14,
--	ARMV7_PERFCTR_L1_DCACHE_WB		= 0x15,
--	ARMV7_PERFCTR_L2_DCACHE_ACCESS		= 0x16,
--	ARMV7_PERFCTR_L2_DCACHE_REFILL		= 0x17,
--	ARMV7_PERFCTR_L2_DCACHE_WB		= 0x18,
--	ARMV7_PERFCTR_BUS_ACCESS		= 0x19,
--	ARMV7_PERFCTR_MEMORY_ERROR		= 0x1A,
--	ARMV7_PERFCTR_INSTR_SPEC		= 0x1B,
--	ARMV7_PERFCTR_TTBR_WRITE		= 0x1C,
--	ARMV7_PERFCTR_BUS_CYCLES		= 0x1D,
--
--	ARMV7_PERFCTR_CPU_CYCLES		= 0xFF
-+	ARMV7_PERFCTR_MEM_ACCESS			= 0x13,
-+	ARMV7_PERFCTR_L1_ICACHE_ACCESS			= 0x14,
-+	ARMV7_PERFCTR_L1_DCACHE_WB			= 0x15,
-+	ARMV7_PERFCTR_L2_CACHE_ACCESS			= 0x16,
-+	ARMV7_PERFCTR_L2_CACHE_REFILL			= 0x17,
-+	ARMV7_PERFCTR_L2_CACHE_WB			= 0x18,
-+	ARMV7_PERFCTR_BUS_ACCESS			= 0x19,
-+	ARMV7_PERFCTR_MEM_ERROR				= 0x1A,
-+	ARMV7_PERFCTR_INSTR_SPEC			= 0x1B,
-+	ARMV7_PERFCTR_TTBR_WRITE			= 0x1C,
-+	ARMV7_PERFCTR_BUS_CYCLES			= 0x1D,
-+
-+	ARMV7_PERFCTR_CPU_CYCLES			= 0xFF
- };
- 
- /* ARMv7 Cortex-A8 specific event types */
- enum armv7_a8_perf_types {
--	ARMV7_PERFCTR_WRITE_BUFFER_FULL		= 0x40,
--	ARMV7_PERFCTR_L2_STORE_MERGED		= 0x41,
--	ARMV7_PERFCTR_L2_STORE_BUFF		= 0x42,
--	ARMV7_PERFCTR_L2_ACCESS			= 0x43,
--	ARMV7_PERFCTR_L2_CACH_MISS		= 0x44,
--	ARMV7_PERFCTR_AXI_READ_CYCLES		= 0x45,
--	ARMV7_PERFCTR_AXI_WRITE_CYCLES		= 0x46,
--	ARMV7_PERFCTR_MEMORY_REPLAY		= 0x47,
--	ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY	= 0x48,
--	ARMV7_PERFCTR_L1_DATA_MISS		= 0x49,
--	ARMV7_PERFCTR_L1_INST_MISS		= 0x4A,
--	ARMV7_PERFCTR_L1_DATA_COLORING		= 0x4B,
--	ARMV7_PERFCTR_L1_NEON_DATA		= 0x4C,
--	ARMV7_PERFCTR_L1_NEON_CACH_DATA		= 0x4D,
--	ARMV7_PERFCTR_L2_NEON			= 0x4E,
--	ARMV7_PERFCTR_L2_NEON_HIT		= 0x4F,
--	ARMV7_PERFCTR_L1_INST			= 0x50,
--	ARMV7_PERFCTR_PC_RETURN_MIS_PRED	= 0x51,
--	ARMV7_PERFCTR_PC_BRANCH_FAILED		= 0x52,
--	ARMV7_PERFCTR_PC_BRANCH_TAKEN		= 0x53,
--	ARMV7_PERFCTR_PC_BRANCH_EXECUTED	= 0x54,
--	ARMV7_PERFCTR_OP_EXECUTED		= 0x55,
--	ARMV7_PERFCTR_CYCLES_INST_STALL		= 0x56,
--	ARMV7_PERFCTR_CYCLES_INST		= 0x57,
--	ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL	= 0x58,
--	ARMV7_PERFCTR_CYCLES_NEON_INST_STALL	= 0x59,
--	ARMV7_PERFCTR_NEON_CYCLES		= 0x5A,
--
--	ARMV7_PERFCTR_PMU0_EVENTS		= 0x70,
--	ARMV7_PERFCTR_PMU1_EVENTS		= 0x71,
--	ARMV7_PERFCTR_PMU_EVENTS		= 0x72,
-+	ARMV7_A8_PERFCTR_L2_CACHE_ACCESS		= 0x43,
-+	ARMV7_A8_PERFCTR_L2_CACHE_REFILL		= 0x44,
-+	ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS		= 0x50,
-+	ARMV7_A8_PERFCTR_STALL_ISIDE			= 0x56,
- };
- 
- /* ARMv7 Cortex-A9 specific event types */
- enum armv7_a9_perf_types {
--	ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC	= 0x40,
--	ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC	= 0x41,
--	ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC	= 0x42,
--
--	ARMV7_PERFCTR_COHERENT_LINE_MISS	= 0x50,
--	ARMV7_PERFCTR_COHERENT_LINE_HIT		= 0x51,
--
--	ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES	= 0x60,
--	ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES	= 0x61,
--	ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES	= 0x62,
--	ARMV7_PERFCTR_STREX_EXECUTED_PASSED	= 0x63,
--	ARMV7_PERFCTR_STREX_EXECUTED_FAILED	= 0x64,
--	ARMV7_PERFCTR_DATA_EVICTION		= 0x65,
--	ARMV7_PERFCTR_ISSUE_STAGE_NO_INST	= 0x66,
--	ARMV7_PERFCTR_ISSUE_STAGE_EMPTY		= 0x67,
--	ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE	= 0x68,
--
--	ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS	= 0x6E,
--
--	ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST	= 0x70,
--	ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST	= 0x71,
--	ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST	= 0x72,
--	ARMV7_PERFCTR_FP_EXECUTED_INST		= 0x73,
--	ARMV7_PERFCTR_NEON_EXECUTED_INST	= 0x74,
--
--	ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES	= 0x80,
--	ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES	= 0x81,
--	ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES	= 0x82,
--	ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES	= 0x83,
--	ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES	= 0x84,
--	ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES	= 0x85,
--	ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES	= 0x86,
--
--	ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES	= 0x8A,
--	ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES	= 0x8B,
--
--	ARMV7_PERFCTR_ISB_INST			= 0x90,
--	ARMV7_PERFCTR_DSB_INST			= 0x91,
--	ARMV7_PERFCTR_DMB_INST			= 0x92,
--	ARMV7_PERFCTR_EXT_INTERRUPTS		= 0x93,
--
--	ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED	= 0xA0,
--	ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED	= 0xA1,
--	ARMV7_PERFCTR_PLE_FIFO_FLUSH		= 0xA2,
--	ARMV7_PERFCTR_PLE_RQST_COMPLETED	= 0xA3,
--	ARMV7_PERFCTR_PLE_FIFO_OVERFLOW		= 0xA4,
--	ARMV7_PERFCTR_PLE_RQST_PROG		= 0xA5
-+	ARMV7_A9_PERFCTR_INSTR_CORE_RENAME		= 0x68,
-+	ARMV7_A9_PERFCTR_STALL_ICACHE			= 0x60,
-+	ARMV7_A9_PERFCTR_STALL_DISPATCH			= 0x66,
- };
- 
- /* ARMv7 Cortex-A5 specific event types */
- enum armv7_a5_perf_types {
--	ARMV7_PERFCTR_IRQ_TAKEN			= 0x86,
--	ARMV7_PERFCTR_FIQ_TAKEN			= 0x87,
--
--	ARMV7_PERFCTR_EXT_MEM_RQST		= 0xc0,
--	ARMV7_PERFCTR_NC_EXT_MEM_RQST		= 0xc1,
--	ARMV7_PERFCTR_PREFETCH_LINEFILL		= 0xc2,
--	ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP	= 0xc3,
--	ARMV7_PERFCTR_ENTER_READ_ALLOC		= 0xc4,
--	ARMV7_PERFCTR_READ_ALLOC		= 0xc5,
--
--	ARMV7_PERFCTR_STALL_SB_FULL		= 0xc9,
-+	ARMV7_A5_PERFCTR_PREFETCH_LINEFILL		= 0xc2,
-+	ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP		= 0xc3,
- };
- 
- /* ARMv7 Cortex-A15 specific event types */
- enum armv7_a15_perf_types {
--	ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS	= 0x40,
--	ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS	= 0x41,
--	ARMV7_PERFCTR_L1_DCACHE_READ_REFILL	= 0x42,
--	ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL	= 0x43,
-+	ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ		= 0x40,
-+	ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE	= 0x41,
-+	ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ		= 0x42,
-+	ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE	= 0x43,
- 
--	ARMV7_PERFCTR_L1_DTLB_READ_REFILL	= 0x4C,
--	ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL	= 0x4D,
-+	ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ		= 0x4C,
-+	ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE		= 0x4D,
- 
--	ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS	= 0x50,
--	ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS	= 0x51,
--	ARMV7_PERFCTR_L2_DCACHE_READ_REFILL	= 0x52,
--	ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL	= 0x53,
-+	ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ		= 0x50,
-+	ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE		= 0x51,
-+	ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ		= 0x52,
-+	ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE		= 0x53,
- 
--	ARMV7_PERFCTR_SPEC_PC_WRITE		= 0x76,
-+	ARMV7_A15_PERFCTR_PC_WRITE_SPEC			= 0x76,
- };
- 
- /*
-@@ -197,13 +119,15 @@ enum armv7_a15_perf_types {
-  * accesses/misses in hardware.
-  */
- static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
--	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,
--	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,
--	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
--	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
--	[PERF_COUNT_HW_BUS_CYCLES]	    = ARMV7_PERFCTR_CLOCK_CYCLES,
-+	[PERF_COUNT_HW_CPU_CYCLES]		= ARMV7_PERFCTR_CPU_CYCLES,
-+	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV7_PERFCTR_INSTR_EXECUTED,
-+	[PERF_COUNT_HW_CACHE_REFERENCES]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+	[PERF_COUNT_HW_CACHE_MISSES]		= ARMV7_PERFCTR_L1_DCACHE_REFILL,
-+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= ARMV7_PERFCTR_PC_WRITE,
-+	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+	[PERF_COUNT_HW_BUS_CYCLES]		= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= ARMV7_A8_PERFCTR_STALL_ISIDE,
-+	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= HW_OP_UNSUPPORTED,
- };
- 
- static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-@@ -217,12 +141,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 		 * combined.
- 		 */
- 		[C(OP_READ)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_DCACHE_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DCACHE_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_DCACHE_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DCACHE_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -231,12 +155,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	},
- 	[C(L1I)] = {
- 		[C(OP_READ)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_INST,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_INST_MISS,
-+			[C(RESULT_ACCESS)]	= ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_INST,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_INST_MISS,
-+			[C(RESULT_ACCESS)]	= ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -245,12 +169,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	},
- 	[C(LL)] = {
- 		[C(OP_READ)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L2_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L2_CACH_MISS,
-+			[C(RESULT_ACCESS)]	= ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L2_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L2_CACH_MISS,
-+			[C(RESULT_ACCESS)]	= ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -274,11 +198,11 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	[C(ITLB)] = {
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -287,14 +211,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	},
- 	[C(BPU)] = {
- 		[C(OP_READ)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_WRITE,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- 		},
- 		[C(OP_WRITE)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_WRITE,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -321,14 +243,15 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-  * Cortex-A9 HW events mapping
-  */
- static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
--	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,
--	[PERF_COUNT_HW_INSTRUCTIONS]	    =
--					ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
--	[PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_DCACHE_ACCESS,
--	[PERF_COUNT_HW_CACHE_MISSES]	    = ARMV7_PERFCTR_DCACHE_REFILL,
--	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
--	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
--	[PERF_COUNT_HW_BUS_CYCLES]	    = ARMV7_PERFCTR_CLOCK_CYCLES,
-+	[PERF_COUNT_HW_CPU_CYCLES]		= ARMV7_PERFCTR_CPU_CYCLES,
-+	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
-+	[PERF_COUNT_HW_CACHE_REFERENCES]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+	[PERF_COUNT_HW_CACHE_MISSES]		= ARMV7_PERFCTR_L1_DCACHE_REFILL,
-+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= ARMV7_PERFCTR_PC_WRITE,
-+	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+	[PERF_COUNT_HW_BUS_CYCLES]		= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= ARMV7_A9_PERFCTR_STALL_ICACHE,
-+	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= ARMV7_A9_PERFCTR_STALL_DISPATCH,
- };
- 
- static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-@@ -342,12 +265,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 		 * combined.
- 		 */
- 		[C(OP_READ)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_DCACHE_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DCACHE_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_DCACHE_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DCACHE_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -357,11 +280,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	[C(L1I)] = {
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -399,11 +322,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	[C(ITLB)] = {
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -412,14 +335,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	},
- 	[C(BPU)] = {
- 		[C(OP_READ)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_WRITE,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- 		},
- 		[C(OP_WRITE)] = {
--			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_WRITE,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -446,13 +367,15 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-  * Cortex-A5 HW events mapping
-  */
- static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
--	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,
--	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,
--	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
--	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
--	[PERF_COUNT_HW_BUS_CYCLES]	    = HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_CPU_CYCLES]		= ARMV7_PERFCTR_CPU_CYCLES,
-+	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV7_PERFCTR_INSTR_EXECUTED,
-+	[PERF_COUNT_HW_CACHE_REFERENCES]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+	[PERF_COUNT_HW_CACHE_MISSES]		= ARMV7_PERFCTR_L1_DCACHE_REFILL,
-+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= ARMV7_PERFCTR_PC_WRITE,
-+	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+	[PERF_COUNT_HW_BUS_CYCLES]		= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= HW_OP_UNSUPPORTED,
- };
- 
- static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-@@ -460,42 +383,34 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 					[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
- 	[C(L1D)] = {
- 		[C(OP_READ)] = {
--			[C(RESULT_ACCESS)]
--					= ARMV7_PERFCTR_DCACHE_ACCESS,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_DCACHE_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
--			[C(RESULT_ACCESS)]
--					= ARMV7_PERFCTR_DCACHE_ACCESS,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_DCACHE_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
--			[C(RESULT_ACCESS)]
--					= ARMV7_PERFCTR_PREFETCH_LINEFILL,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
-+			[C(RESULT_ACCESS)]	= ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
-+			[C(RESULT_MISS)]	= ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
- 		},
- 	},
- 	[C(L1I)] = {
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,
- 		},
- 		/*
- 		 * The prefetch counters don't differentiate between the I
- 		 * side and the D side.
- 		 */
- 		[C(OP_PREFETCH)] = {
--			[C(RESULT_ACCESS)]
--					= ARMV7_PERFCTR_PREFETCH_LINEFILL,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
-+			[C(RESULT_ACCESS)]	= ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
-+			[C(RESULT_MISS)]	= ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
- 		},
- 	},
- 	[C(LL)] = {
-@@ -529,11 +444,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	[C(ITLB)] = {
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -543,13 +458,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	[C(BPU)] = {
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -562,13 +475,15 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-  * Cortex-A15 HW events mapping
-  */
- static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
--	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,
--	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,
--	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_SPEC_PC_WRITE,
--	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
--	[PERF_COUNT_HW_BUS_CYCLES]	    = ARMV7_PERFCTR_BUS_CYCLES,
-+	[PERF_COUNT_HW_CPU_CYCLES]		= ARMV7_PERFCTR_CPU_CYCLES,
-+	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV7_PERFCTR_INSTR_EXECUTED,
-+	[PERF_COUNT_HW_CACHE_REFERENCES]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-+	[PERF_COUNT_HW_CACHE_MISSES]		= ARMV7_PERFCTR_L1_DCACHE_REFILL,
-+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
-+	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+	[PERF_COUNT_HW_BUS_CYCLES]		= ARMV7_PERFCTR_BUS_CYCLES,
-+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= HW_OP_UNSUPPORTED,
- };
- 
- static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-@@ -576,16 +491,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 					[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
- 	[C(L1D)] = {
- 		[C(OP_READ)] = {
--			[C(RESULT_ACCESS)]
--					= ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_L1_DCACHE_READ_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
-+			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
- 		},
- 		[C(OP_WRITE)] = {
--			[C(RESULT_ACCESS)]
--					= ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
-+			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -601,11 +512,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 		 */
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -614,16 +525,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	},
- 	[C(LL)] = {
- 		[C(OP_READ)] = {
--			[C(RESULT_ACCESS)]
--					= ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_L2_DCACHE_READ_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
-+			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
- 		},
- 		[C(OP_WRITE)] = {
--			[C(RESULT_ACCESS)]
--					= ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL,
-+			[C(RESULT_ACCESS)]	= ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
-+			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -633,13 +540,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	[C(DTLB)] = {
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_L1_DTLB_READ_REFILL,
-+			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL,
-+			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -649,11 +554,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	[C(ITLB)] = {
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
--			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-@@ -663,13 +568,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
- 	[C(BPU)] = {
- 		[C(OP_READ)] = {
- 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- 		},
- 		[C(OP_WRITE)] = {
- 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
--			[C(RESULT_MISS)]
--					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-+			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- 		},
- 		[C(OP_PREFETCH)] = {
- 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
-index 9fc2c95..71a21e6 100644
---- a/arch/arm/kernel/perf_event_xscale.c
-+++ b/arch/arm/kernel/perf_event_xscale.c
-@@ -48,13 +48,15 @@ enum xscale_counters {
- };
- 
- static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
--	[PERF_COUNT_HW_CPU_CYCLES]	    = XSCALE_PERFCTR_CCNT,
--	[PERF_COUNT_HW_INSTRUCTIONS]	    = XSCALE_PERFCTR_INSTRUCTION,
--	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
--	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
--	[PERF_COUNT_HW_BRANCH_MISSES]	    = XSCALE_PERFCTR_BRANCH_MISS,
--	[PERF_COUNT_HW_BUS_CYCLES]	    = HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_CPU_CYCLES]		= XSCALE_PERFCTR_CCNT,
-+	[PERF_COUNT_HW_INSTRUCTIONS]		= XSCALE_PERFCTR_INSTRUCTION,
-+	[PERF_COUNT_HW_CACHE_REFERENCES]	= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_CACHE_MISSES]		= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= XSCALE_PERFCTR_BRANCH,
-+	[PERF_COUNT_HW_BRANCH_MISSES]		= XSCALE_PERFCTR_BRANCH_MISS,
-+	[PERF_COUNT_HW_BUS_CYCLES]		= HW_OP_UNSUPPORTED,
-+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= XSCALE_PERFCTR_ICACHE_NO_DELIVER,
-+	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= HW_OP_UNSUPPORTED,
- };
- 
- static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
-index 3d0c6fb..eeb3e16 100644
---- a/arch/arm/kernel/process.c
-+++ b/arch/arm/kernel/process.c
-@@ -57,7 +57,7 @@ static const char *isa_modes[] = {
-   "ARM" , "Thumb" , "Jazelle", "ThumbEE"
- };
- 
--extern void setup_mm_for_reboot(char mode);
-+extern void setup_mm_for_reboot(void);
- 
- static volatile int hlt_counter;
- 
-@@ -92,7 +92,7 @@ static int __init hlt_setup(char *__unused)
- __setup("nohlt", nohlt_setup);
- __setup("hlt", hlt_setup);
- 
--void arm_machine_restart(char mode, const char *cmd)
-+void soft_restart(unsigned long addr)
- {
- 	/* Disable interrupts first */
- 	local_irq_disable();
-@@ -103,7 +103,7 @@ void arm_machine_restart(char mode, const char *cmd)
- 	 * we may need it to insert some 1:1 mappings so that
- 	 * soft boot works.
- 	 */
--	setup_mm_for_reboot(mode);
-+	setup_mm_for_reboot();
- 
- 	/* Clean and invalidate caches */
- 	flush_cache_all();
-@@ -114,18 +114,17 @@ void arm_machine_restart(char mode, const char *cmd)
- 	/* Push out any further dirty data, and ensure cache is empty */
- 	flush_cache_all();
- 
--	/*
--	 * Now call the architecture specific reboot code.
--	 */
--	arch_reset(mode, cmd);
-+	cpu_reset(addr);
-+}
- 
--	/*
--	 * Whoops - the architecture was unable to reboot.
--	 * Tell the user!
--	 */
--	mdelay(1000);
--	printk("Reboot failed -- System halted\n");
--	while (1);
-+void arm_machine_restart(char mode, const char *cmd)
-+{
-+	/* Disable interrupts first */
-+	local_irq_disable();
-+	local_fiq_disable();
-+
-+	/* Call the architecture specific reboot code. */
-+	arch_reset(mode, cmd);
- }
- 
- /*
-@@ -253,7 +252,15 @@ void machine_power_off(void)
- void machine_restart(char *cmd)
- {
- 	machine_shutdown();
-+
- 	arm_pm_restart(reboot_mode, cmd);
-+
-+	/* Give a grace period for failure to restart of 1s */
-+	mdelay(1000);
-+
-+	/* Whoops - the platform was unable to reboot. Tell the user! */
-+	printk("Reboot failed -- System halted\n");
-+	while (1);
- }
- 
- void __show_regs(struct pt_regs *regs)
-diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
-index 8fc2c8f..cd18aa9 100644
---- a/arch/arm/kernel/setup.c
-+++ b/arch/arm/kernel/setup.c
-@@ -31,6 +31,7 @@
- #include <linux/memblock.h>
- #include <linux/bug.h>
- #include <linux/compiler.h>
-+#include <linux/sort.h>
- 
- #include <asm/unified.h>
- #include <asm/cpu.h>
-@@ -890,6 +891,12 @@ static struct machine_desc * __init setup_machine_tags(unsigned int nr)
- 	return mdesc;
- }
- 
-+static int __init meminfo_cmp(const void *_a, const void *_b)
-+{
-+	const struct membank *a = _a, *b = _b;
-+	long cmp = bank_pfn_start(a) - bank_pfn_start(b);
-+	return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
-+}
- 
- void __init setup_arch(char **cmdline_p)
- {
-@@ -902,14 +909,8 @@ void __init setup_arch(char **cmdline_p)
- 	machine_desc = mdesc;
- 	machine_name = mdesc->name;
- 
--#ifdef CONFIG_ZONE_DMA
--	if (mdesc->dma_zone_size) {
--		extern unsigned long arm_dma_zone_size;
--		arm_dma_zone_size = mdesc->dma_zone_size;
--	}
--#endif
--	if (mdesc->soft_reboot)
--		reboot_setup("s");
-+	if (mdesc->restart_mode)
-+		reboot_setup(&mdesc->restart_mode);
- 
- 	init_mm.start_code = (unsigned long) _text;
- 	init_mm.end_code   = (unsigned long) _etext;
-@@ -922,12 +923,16 @@ void __init setup_arch(char **cmdline_p)
- 
- 	parse_early_param();
- 
-+	sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
- 	sanity_check_meminfo();
- 	arm_memblock_init(&meminfo, mdesc);
- 
- 	paging_init(mdesc);
- 	request_standard_resources(mdesc);
- 
-+	if (mdesc->restart)
-+		arm_pm_restart = mdesc->restart;
-+
- 	unflatten_device_tree();
- 
- #ifdef CONFIG_SMP
-diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
-index 8c57dd3..3abe5da 100644
---- a/arch/arm/kernel/time.c
-+++ b/arch/arm/kernel/time.c
-@@ -112,7 +112,7 @@ void timer_tick(void)
- }
- #endif
- 
--#if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS)
-+#if defined(CONFIG_PM)
- static int timer_suspend(void)
- {
- 	if (system_timer->suspend)
-diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
-index 4298e78..4ca09ef 100644
---- a/arch/arm/mach-at91/include/mach/io.h
-+++ b/arch/arm/mach-at91/include/mach/io.h
-@@ -30,14 +30,6 @@
- 
- #ifndef __ASSEMBLY__
- 
--#ifndef CONFIG_ARCH_AT91X40
--#define __arch_ioremap	at91_ioremap
--#define __arch_iounmap	at91_iounmap
--#endif
--
--void __iomem *at91_ioremap(unsigned long phys, size_t size, unsigned int type);
--void at91_iounmap(volatile void __iomem *addr);
--
- static inline unsigned int at91_sys_read(unsigned int reg_offset)
- {
- 	void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-diff --git a/arch/arm/mach-at91/include/mach/vmalloc.h b/arch/arm/mach-at91/include/mach/vmalloc.h
-deleted file mode 100644
-index 8e4a1bd..0000000
---- a/arch/arm/mach-at91/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,28 +0,0 @@
--/*
-- * arch/arm/mach-at91/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2003 SAN People
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H
--
--#include <mach/hardware.h>
--
--#define VMALLOC_END		(AT91_VIRT_BASE & PGDIR_MASK)
--
--#endif
-diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
-index f5bbe0ef..39d8ea0 100644
---- a/arch/arm/mach-at91/setup.c
-+++ b/arch/arm/mach-at91/setup.c
-@@ -76,24 +76,6 @@ static struct map_desc at91_io_desc __initdata = {
- 	.type		= MT_DEVICE,
- };
- 
--void __iomem *at91_ioremap(unsigned long p, size_t size, unsigned int type)
--{
--	if (p >= AT91_BASE_SYS && p <= (AT91_BASE_SYS + SZ_16K - 1))
--		return (void __iomem *)AT91_IO_P2V(p);
--
--	return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
--}
--EXPORT_SYMBOL(at91_ioremap);
--
--void at91_iounmap(volatile void __iomem *addr)
--{
--	unsigned long virt = (unsigned long)addr;
--
--	if (virt >= VMALLOC_START && virt < VMALLOC_END)
--		__iounmap(addr);
--}
--EXPORT_SYMBOL(at91_iounmap);
--
- #define AT91_DBGU0	0xfffff200
- #define AT91_DBGU1	0xffffee00
- 
-diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
-index f4d4d6d..1a1a27d 100644
---- a/arch/arm/mach-bcmring/dma.c
-+++ b/arch/arm/mach-bcmring/dma.c
-@@ -1615,7 +1615,7 @@ DMA_MemType_t dma_mem_type(void *addr)
- {
- 	unsigned long addrVal = (unsigned long)addr;
- 
--	if (addrVal >= VMALLOC_END) {
-+	if (addrVal >= CONSISTENT_BASE) {
- 		/* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
- 
- 		/* dma_alloc_xxx pages are physically and virtually contiguous */
-diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
-deleted file mode 100644
-index 7397bd7..0000000
---- a/arch/arm/mach-bcmring/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,25 +0,0 @@
--/*
-- *
-- *  Copyright (C) 2000 Russell King.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--
--/*
-- * Move VMALLOC_END to 0xf0000000 so that the vm space can range from
-- * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
-- * larger physical memory designs better.
-- */
--#define VMALLOC_END       0xf0000000UL
-diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
-index 4a19731..f2f0256 100644
---- a/arch/arm/mach-clps711x/Makefile
-+++ b/arch/arm/mach-clps711x/Makefile
-@@ -4,7 +4,7 @@
- 
- # Object file lists.
- 
--obj-y			:= irq.o mm.o time.o
-+obj-y			:= common.o
- obj-m			:=
- obj-n			:=
- obj-			:=
-diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
-new file mode 100644
-index 0000000..ced2a4e
---- /dev/null
-+++ b/arch/arm/mach-clps711x/common.c
-@@ -0,0 +1,222 @@
-+/*
-+ *  linux/arch/arm/mach-clps711x/core.c
-+ *
-+ *  Core support for the CLPS711x-based machines.
-+ *
-+ *  Copyright (C) 2001,2011 Deep Blue Solutions Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/kernel.h>
-+#include <linux/mm.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/sched.h>
-+#include <linux/timex.h>
-+
-+#include <asm/sizes.h>
-+#include <mach/hardware.h>
-+#include <asm/irq.h>
-+#include <asm/leds.h>
-+#include <asm/pgtable.h>
-+#include <asm/page.h>
-+#include <asm/mach/map.h>
-+#include <asm/mach/time.h>
-+#include <asm/hardware/clps7111.h>
-+
-+/*
-+ * This maps the generic CLPS711x registers
-+ */
-+static struct map_desc clps711x_io_desc[] __initdata = {
-+	{
-+		.virtual	= CLPS7111_VIRT_BASE,
-+		.pfn		= __phys_to_pfn(CLPS7111_PHYS_BASE),
-+		.length		= SZ_1M,
-+		.type		= MT_DEVICE
-+	}
-+};
-+
-+void __init clps711x_map_io(void)
-+{
-+	iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
-+}
-+
-+static void int1_mask(struct irq_data *d)
-+{
-+	u32 intmr1;
-+
-+	intmr1 = clps_readl(INTMR1);
-+	intmr1 &= ~(1 << d->irq);
-+	clps_writel(intmr1, INTMR1);
-+}
-+
-+static void int1_ack(struct irq_data *d)
-+{
-+	u32 intmr1;
-+
-+	intmr1 = clps_readl(INTMR1);
-+	intmr1 &= ~(1 << d->irq);
-+	clps_writel(intmr1, INTMR1);
-+
-+	switch (d->irq) {
-+	case IRQ_CSINT:  clps_writel(0, COEOI);  break;
-+	case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
-+	case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
-+	case IRQ_RTCMI:  clps_writel(0, RTCEOI); break;
-+	case IRQ_TINT:   clps_writel(0, TEOI);   break;
-+	case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
-+	}
-+}
-+
-+static void int1_unmask(struct irq_data *d)
-+{
-+	u32 intmr1;
-+
-+	intmr1 = clps_readl(INTMR1);
-+	intmr1 |= 1 << d->irq;
-+	clps_writel(intmr1, INTMR1);
-+}
-+
-+static struct irq_chip int1_chip = {
-+	.irq_ack	= int1_ack,
-+	.irq_mask	= int1_mask,
-+	.irq_unmask	= int1_unmask,
-+};
-+
-+static void int2_mask(struct irq_data *d)
-+{
-+	u32 intmr2;
-+
-+	intmr2 = clps_readl(INTMR2);
-+	intmr2 &= ~(1 << (d->irq - 16));
-+	clps_writel(intmr2, INTMR2);
-+}
-+
-+static void int2_ack(struct irq_data *d)
-+{
-+	u32 intmr2;
-+
-+	intmr2 = clps_readl(INTMR2);
-+	intmr2 &= ~(1 << (d->irq - 16));
-+	clps_writel(intmr2, INTMR2);
-+
-+	switch (d->irq) {
-+	case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
-+	}
-+}
-+
-+static void int2_unmask(struct irq_data *d)
-+{
-+	u32 intmr2;
-+
-+	intmr2 = clps_readl(INTMR2);
-+	intmr2 |= 1 << (d->irq - 16);
-+	clps_writel(intmr2, INTMR2);
-+}
-+
-+static struct irq_chip int2_chip = {
-+	.irq_ack	= int2_ack,
-+	.irq_mask	= int2_mask,
-+	.irq_unmask	= int2_unmask,
-+};
-+
-+void __init clps711x_init_irq(void)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < NR_IRQS; i++) {
-+	        if (INT1_IRQS & (1 << i)) {
-+			irq_set_chip_and_handler(i, &int1_chip,
-+						 handle_level_irq);
-+			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-+		}
-+		if (INT2_IRQS & (1 << i)) {
-+			irq_set_chip_and_handler(i, &int2_chip,
-+						 handle_level_irq);
-+			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-+		}
-+	}
-+
-+	/*
-+	 * Disable interrupts
-+	 */
-+	clps_writel(0, INTMR1);
-+	clps_writel(0, INTMR2);
-+
-+	/*
-+	 * Clear down any pending interrupts
-+	 */
-+	clps_writel(0, COEOI);
-+	clps_writel(0, TC1EOI);
-+	clps_writel(0, TC2EOI);
-+	clps_writel(0, RTCEOI);
-+	clps_writel(0, TEOI);
-+	clps_writel(0, UMSEOI);
-+	clps_writel(0, SYNCIO);
-+	clps_writel(0, KBDEOI);
-+}
-+
-+/*
-+ * gettimeoffset() returns time since last timer tick, in usecs.
-+ *
-+ * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
-+ * 'tick' is usecs per jiffy.
-+ */
-+static unsigned long clps711x_gettimeoffset(void)
-+{
-+	unsigned long hwticks;
-+	hwticks = LATCH - (clps_readl(TC2D) & 0xffff);	/* since last underflow */
-+	return (hwticks * (tick_nsec / 1000)) / LATCH;
-+}
-+
-+/*
-+ * IRQ handler for the timer
-+ */
-+static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
-+{
-+	timer_tick();
-+	return IRQ_HANDLED;
-+}
-+
-+static struct irqaction clps711x_timer_irq = {
-+	.name		= "CLPS711x Timer Tick",
-+	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-+	.handler	= p720t_timer_interrupt,
-+};
-+
-+static void __init clps711x_timer_init(void)
-+{
-+	struct timespec tv;
-+	unsigned int syscon;
-+
-+	syscon = clps_readl(SYSCON1);
-+	syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
-+	clps_writel(syscon, SYSCON1);
-+
-+	clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
-+
-+	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
-+
-+	tv.tv_nsec = 0;
-+	tv.tv_sec = clps_readl(RTCDR);
-+	do_settimeofday(&tv);
-+}
-+
-+struct sys_timer clps711x_timer = {
-+	.init		= clps711x_timer_init,
-+	.offset		= clps711x_gettimeoffset,
-+};
-diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h
-index f916cd7..6c11993 100644
---- a/arch/arm/mach-clps711x/include/mach/system.h
-+++ b/arch/arm/mach-clps711x/include/mach/system.h
-@@ -34,7 +34,7 @@ static inline void arch_idle(void)
- 
- static inline void arch_reset(char mode, const char *cmd)
- {
--	cpu_reset(0);
-+	soft_restart(0);
- }
- 
- #endif
-diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h
-deleted file mode 100644
-index 467b961..0000000
---- a/arch/arm/mach-clps711x/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/*
-- *  arch/arm/mach-clps711x/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#define VMALLOC_END       0xd0000000UL
-diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
-deleted file mode 100644
-index c2eceee..0000000
---- a/arch/arm/mach-clps711x/irq.c
-+++ /dev/null
-@@ -1,143 +0,0 @@
--/*
-- *  linux/arch/arm/mach-clps711x/irq.c
-- *
-- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#include <linux/init.h>
--#include <linux/list.h>
--#include <linux/io.h>
--
--#include <asm/mach/irq.h>
--#include <mach/hardware.h>
--#include <asm/irq.h>
--
--#include <asm/hardware/clps7111.h>
--
--static void int1_mask(struct irq_data *d)
--{
--	u32 intmr1;
--
--	intmr1 = clps_readl(INTMR1);
--	intmr1 &= ~(1 << d->irq);
--	clps_writel(intmr1, INTMR1);
--}
--
--static void int1_ack(struct irq_data *d)
--{
--	u32 intmr1;
--
--	intmr1 = clps_readl(INTMR1);
--	intmr1 &= ~(1 << d->irq);
--	clps_writel(intmr1, INTMR1);
--
--	switch (d->irq) {
--	case IRQ_CSINT:  clps_writel(0, COEOI);  break;
--	case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
--	case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
--	case IRQ_RTCMI:  clps_writel(0, RTCEOI); break;
--	case IRQ_TINT:   clps_writel(0, TEOI);   break;
--	case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
--	}
--}
--
--static void int1_unmask(struct irq_data *d)
--{
--	u32 intmr1;
--
--	intmr1 = clps_readl(INTMR1);
--	intmr1 |= 1 << d->irq;
--	clps_writel(intmr1, INTMR1);
--}
--
--static struct irq_chip int1_chip = {
--	.irq_ack	= int1_ack,
--	.irq_mask	= int1_mask,
--	.irq_unmask	= int1_unmask,
--};
--
--static void int2_mask(struct irq_data *d)
--{
--	u32 intmr2;
--
--	intmr2 = clps_readl(INTMR2);
--	intmr2 &= ~(1 << (d->irq - 16));
--	clps_writel(intmr2, INTMR2);
--}
--
--static void int2_ack(struct irq_data *d)
--{
--	u32 intmr2;
--
--	intmr2 = clps_readl(INTMR2);
--	intmr2 &= ~(1 << (d->irq - 16));
--	clps_writel(intmr2, INTMR2);
--
--	switch (d->irq) {
--	case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
--	}
--}
--
--static void int2_unmask(struct irq_data *d)
--{
--	u32 intmr2;
--
--	intmr2 = clps_readl(INTMR2);
--	intmr2 |= 1 << (d->irq - 16);
--	clps_writel(intmr2, INTMR2);
--}
--
--static struct irq_chip int2_chip = {
--	.irq_ack	= int2_ack,
--	.irq_mask	= int2_mask,
--	.irq_unmask	= int2_unmask,
--};
--
--void __init clps711x_init_irq(void)
--{
--	unsigned int i;
--
--	for (i = 0; i < NR_IRQS; i++) {
--	        if (INT1_IRQS & (1 << i)) {
--	        	irq_set_chip_and_handler(i, &int1_chip,
--						 handle_level_irq);
--	        	set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
--		}
--		if (INT2_IRQS & (1 << i)) {
--			irq_set_chip_and_handler(i, &int2_chip,
--						 handle_level_irq);
--			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
--		}			
--	}
--
--	/*
--	 * Disable interrupts
--	 */
--	clps_writel(0, INTMR1);
--	clps_writel(0, INTMR2);
--
--	/*
--	 * Clear down any pending interrupts
--	 */
--	clps_writel(0, COEOI);
--	clps_writel(0, TC1EOI);
--	clps_writel(0, TC2EOI);
--	clps_writel(0, RTCEOI);
--	clps_writel(0, TEOI);
--	clps_writel(0, UMSEOI);
--	clps_writel(0, SYNCIO);
--	clps_writel(0, KBDEOI);
--}
-diff --git a/arch/arm/mach-clps711x/mm.c b/arch/arm/mach-clps711x/mm.c
-deleted file mode 100644
-index 9865921..0000000
---- a/arch/arm/mach-clps711x/mm.c
-+++ /dev/null
-@@ -1,48 +0,0 @@
--/*
-- *  linux/arch/arm/mach-clps711x/mm.c
-- *
-- *  Generic MM setup for the CLPS711x-based machines.
-- *
-- *  Copyright (C) 2001 Deep Blue Solutions Ltd
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#include <linux/kernel.h>
--#include <linux/mm.h>
--#include <linux/init.h>
--
--#include <asm/sizes.h>
--#include <mach/hardware.h>
--#include <asm/pgtable.h>
--#include <asm/page.h>
--#include <asm/mach/map.h>
--#include <asm/hardware/clps7111.h>
--
--/*
-- * This maps the generic CLPS711x registers
-- */
--static struct map_desc clps711x_io_desc[] __initdata = {
--	{
--		.virtual	= CLPS7111_VIRT_BASE,
--		.pfn		= __phys_to_pfn(CLPS7111_PHYS_BASE),
--		.length		= SZ_1M,
--		.type		= MT_DEVICE
--	}
--};
--
--void __init clps711x_map_io(void)
--{
--	iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
--}
-diff --git a/arch/arm/mach-clps711x/time.c b/arch/arm/mach-clps711x/time.c
-deleted file mode 100644
-index d581ef0..0000000
---- a/arch/arm/mach-clps711x/time.c
-+++ /dev/null
-@@ -1,84 +0,0 @@
--/*
-- *  linux/arch/arm/mach-clps711x/time.c
-- *
-- *  Copyright (C) 2001 Deep Blue Solutions Ltd.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#include <linux/timex.h>
--#include <linux/init.h>
--#include <linux/interrupt.h>
--#include <linux/irq.h>
--#include <linux/sched.h>
--#include <linux/io.h>
--
--#include <mach/hardware.h>
--#include <asm/irq.h>
--#include <asm/leds.h>
--#include <asm/hardware/clps7111.h>
--
--#include <asm/mach/time.h>
--
--
--/*
-- * gettimeoffset() returns time since last timer tick, in usecs.
-- *
-- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
-- * 'tick' is usecs per jiffy.
-- */
--static unsigned long clps711x_gettimeoffset(void)
--{
--	unsigned long hwticks;
--	hwticks = LATCH - (clps_readl(TC2D) & 0xffff);	/* since last underflow */
--	return (hwticks * (tick_nsec / 1000)) / LATCH;
--}
--
--/*
-- * IRQ handler for the timer
-- */
--static irqreturn_t
--p720t_timer_interrupt(int irq, void *dev_id)
--{
--	timer_tick();
--	return IRQ_HANDLED;
--}
--
--static struct irqaction clps711x_timer_irq = {
--	.name		= "CLPS711x Timer Tick",
--	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
--	.handler	= p720t_timer_interrupt,
--};
--
--static void __init clps711x_timer_init(void)
--{
--	struct timespec tv;
--	unsigned int syscon;
--
--	syscon = clps_readl(SYSCON1);
--	syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
--	clps_writel(syscon, SYSCON1);
--
--	clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
--
--	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
--
--	tv.tv_nsec = 0;
--	tv.tv_sec = clps_readl(RTCDR);
--	do_settimeofday(&tv);
--}
--
--struct sys_timer clps711x_timer = {
--	.init		= clps711x_timer_init,
--	.offset		= clps711x_gettimeoffset,
--};
-diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
-index 55f7b4b..594852f 100644
---- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -26,6 +26,7 @@
- #include <linux/mtd/partitions.h>
- #include <asm/setup.h>
- #include <asm/mach-types.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/mach/time.h>
-@@ -201,5 +202,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
- 	.map_io		= cns3420_map_io,
- 	.init_irq	= cns3xxx_init_irq,
- 	.timer		= &cns3xxx_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= cns3420_init,
- MACHINE_END
-diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
-index d87bfc3..01c57df 100644
---- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
-+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
-@@ -8,8 +8,6 @@
-  * published by the Free Software Foundation.
-  */
- 
--#include <asm/hardware/entry-macro-gic.S>
--
- 		.macro	disable_fiq
- 		.endm
- 
-diff --git a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
-deleted file mode 100644
-index 1dd231d..0000000
---- a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,11 +0,0 @@
--/*
-- * Copyright 2000 Russell King.
-- * Copyright 2003 ARM Limited
-- * Copyright 2008 Cavium Networks
-- *
-- * This file is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License, Version 2, as
-- * published by the Free Software Foundation.
-- */
--
--#define VMALLOC_END		0xd8000000UL
-diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
-index 495e313..2db78bd 100644
---- a/arch/arm/mach-davinci/Makefile
-+++ b/arch/arm/mach-davinci/Makefile
-@@ -4,7 +4,7 @@
- #
- 
- # Common objects
--obj-y 			:= time.o clock.o serial.o io.o psc.o \
-+obj-y 			:= time.o clock.o serial.o psc.o \
- 			   dma.o usb.o common.o sram.o aemif.o
- 
- obj-$(CONFIG_DAVINCI_MUX)		+= mux.o
-diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
-index 6659a90..f044671 100644
---- a/arch/arm/mach-davinci/board-da850-evm.c
-+++ b/arch/arm/mach-davinci/board-da850-evm.c
-@@ -32,7 +32,6 @@
- #include <linux/spi/spi.h>
- #include <linux/spi/flash.h>
- #include <linux/delay.h>
--#include <linux/wl12xx.h>
- 
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-@@ -794,11 +793,13 @@ static const short da850_evm_mmcsd0_pins[] __initconst = {
- 
- static void da850_panel_power_ctrl(int val)
- {
--	/* lcd backlight */
--	gpio_set_value(DA850_LCD_BL_PIN, val);
--
- 	/* lcd power */
- 	gpio_set_value(DA850_LCD_PWR_PIN, val);
-+
-+	mdelay(200);
-+
-+	/* lcd backlight */
-+	gpio_set_value(DA850_LCD_BL_PIN, val);
- }
- 
- static int da850_lcd_hw_init(void)
-@@ -818,12 +819,6 @@ static int da850_lcd_hw_init(void)
- 	gpio_direction_output(DA850_LCD_BL_PIN, 0);
- 	gpio_direction_output(DA850_LCD_PWR_PIN, 0);
- 
--	/* Switch off panel power and backlight */
--	da850_panel_power_ctrl(0);
--
--	/* Switch on panel power and backlight */
--	da850_panel_power_ctrl(1);
--
- 	return 0;
- }
- 
-@@ -1254,6 +1249,17 @@ static __init int da850_wl12xx_init(void)
- 
- #define DA850EVM_SATA_REFCLKPN_RATE	(100 * 1000 * 1000)
- 
-+#ifdef CONFIG_UIO_PRUSS
-+struct uio_pruss_pdata da8xx_pruss_uio_pdata = {
-+	.pintc_base	= 0x4000,
-+};
-+
-+	ret = da8xx_register_pruss_uio(&da8xx_pruss_uio_pdata);
-+	if (ret)
-+		pr_warning("%s: pruss_uio initialization failed: %d\n",
-+				__func__, ret);
-+#endif
-+
- static __init void da850_evm_init(void)
- {
- 	int ret;
-diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
-index a30c7c5..8e5c7b3 100644
---- a/arch/arm/mach-davinci/cpuidle.c
-+++ b/arch/arm/mach-davinci/cpuidle.c
-@@ -174,4 +174,3 @@ static int __init davinci_cpuidle_init(void)
- 						davinci_cpuidle_probe);
- }
- device_initcall(davinci_cpuidle_init);
--
-diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
-index b047f87..c7e9839 100644
---- a/arch/arm/mach-davinci/da850.c
-+++ b/arch/arm/mach-davinci/da850.c
-@@ -240,6 +240,12 @@ static struct clk tptc2_clk = {
- 	.flags		= ALWAYS_ENABLED,
- };
- 
-+static struct clk pruss_clk = {
-+	.name		= "pruss",
-+	.parent		= &pll0_sysclk2,
-+	.lpsc		= DA8XX_LPSC0_PRUSS,
-+};
-+
- static struct clk uart0_clk = {
- 	.name		= "uart0",
- 	.parent		= &pll0_sysclk2,
-@@ -411,6 +417,7 @@ static struct clk_lookup da850_clks[] = {
- 	CLK(NULL,		"tpcc1",	&tpcc1_clk),
- 	CLK(NULL,		"tptc2",	&tptc2_clk),
- 	CLK(NULL,		"uart0",	&uart0_clk),
-+	CLK(NULL,		"pruss",	&pruss_clk),
- 	CLK(NULL,		"uart1",	&uart1_clk),
- 	CLK(NULL,		"uart2",	&uart2_clk),
- 	CLK(NULL,		"aintc",	&aintc_clk),
-@@ -747,7 +754,7 @@ static struct map_desc da850_io_desc[] = {
- 	},
- 	{
- 		.virtual	= SRAM_VIRT,
--		.pfn		= __phys_to_pfn(DA8XX_ARM_RAM_BASE),
-+		.pfn		= __phys_to_pfn(DA8XX_SHARED_RAM_BASE),
- 		.length		= SZ_8K,
- 		.type		= MT_DEVICE
- 	},
-@@ -1119,8 +1126,9 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
- 	.gpio_irq		= IRQ_DA8XX_GPIO0,
- 	.serial_dev		= &da8xx_serial_device,
- 	.emac_pdata		= &da8xx_emac_pdata,
--	.sram_dma		= DA8XX_ARM_RAM_BASE,
--	.sram_len		= SZ_8K,
-+	.sram_phys		= DA8XX_ARM_RAM_BASE,
-+	.sram_dma		= DA8XX_SHARED_RAM_BASE,
-+	.sram_len		= SZ_128K,
- 	.reset_device		= &da8xx_wdt_device,
- };
- 
-diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
-index 68def71..b899238 100644
---- a/arch/arm/mach-davinci/devices-da8xx.c
-+++ b/arch/arm/mach-davinci/devices-da8xx.c
-@@ -519,6 +519,71 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
- 	}
- }
- 
-+#define DA8XX_PRUSS_MEM_BASE		0x01C30000
-+
-+static struct resource da8xx_pruss_resources[] = {
-+	{
-+		.start	= DA8XX_PRUSS_MEM_BASE,
-+		.end	= DA8XX_PRUSS_MEM_BASE + 0xFFFF,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	{
-+		.start	= IRQ_DA8XX_EVTOUT0,
-+		.end	= IRQ_DA8XX_EVTOUT0,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= IRQ_DA8XX_EVTOUT1,
-+		.end	= IRQ_DA8XX_EVTOUT1,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= IRQ_DA8XX_EVTOUT2,
-+		.end	= IRQ_DA8XX_EVTOUT2,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= IRQ_DA8XX_EVTOUT3,
-+		.end	= IRQ_DA8XX_EVTOUT3,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= IRQ_DA8XX_EVTOUT4,
-+		.end	= IRQ_DA8XX_EVTOUT4,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= IRQ_DA8XX_EVTOUT5,
-+		.end	= IRQ_DA8XX_EVTOUT5,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= IRQ_DA8XX_EVTOUT6,
-+		.end	= IRQ_DA8XX_EVTOUT6,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= IRQ_DA8XX_EVTOUT7,
-+		.end	= IRQ_DA8XX_EVTOUT7,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+;
-+
-+static struct platform_device da8xx_pruss_uio_dev = {
-+	.name		= "pruss_uio",
-+	.id		= -1,
-+	.num_resources	= ARRAY_SIZE(da8xx_pruss_resources),
-+	.resource	= da8xx_pruss_resources,
-+	.dev	 =	{
-+		.coherent_dma_mask = 0xffffffff,
-+	}
-+};
-+
-+int __init da8xx_register_pruss_uio(struct uio_pruss_pdata *config)
-+{
-+	da8xx_pruss_uio_dev.dev.platform_data = config;
-+	return platform_device_register(&da8xx_pruss_uio_dev);
-+
- static const struct display_panel disp_panel = {
- 	QVGA,
- 	16,
-@@ -541,6 +606,7 @@ static struct lcd_ctrl_config lcd_cfg = {
- 	.sync_edge		= 0,
- 	.sync_ctrl		= 1,
- 	.raster_order		= 0,
-+	.fifo_th		= 6,
- };
- 
- struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
-diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
-index fe520d4..07427f0 100644
---- a/arch/arm/mach-davinci/dm355.c
-+++ b/arch/arm/mach-davinci/dm355.c
-@@ -27,7 +27,7 @@
- #include <mach/time.h>
- #include <mach/serial.h>
- #include <mach/common.h>
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- #include <mach/spi.h>
- #include <mach/gpio-davinci.h>
- 
-@@ -851,7 +851,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
- 	.gpio_num		= 104,
- 	.gpio_irq		= IRQ_DM355_GPIOBNK0,
- 	.serial_dev		= &dm355_serial_device,
--	.sram_dma		= 0x00010000,
-+	.sram_phys		= 0x00010000,
- 	.sram_len		= SZ_32K,
- 	.reset_device		= &davinci_wdt_device,
- };
-diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
-index 679e168..ed9753d 100644
---- a/arch/arm/mach-davinci/dm365.c
-+++ b/arch/arm/mach-davinci/dm365.c
-@@ -30,7 +30,7 @@
- #include <mach/time.h>
- #include <mach/serial.h>
- #include <mach/common.h>
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- #include <mach/keyscan.h>
- #include <mach/spi.h>
- #include <mach/gpio-davinci.h>
-@@ -1081,7 +1081,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
- 	.gpio_unbanked		= 8,	/* really 16 ... skip muxed GPIOs */
- 	.serial_dev		= &dm365_serial_device,
- 	.emac_pdata		= &dm365_emac_pdata,
--	.sram_dma		= 0x00010000,
-+	.sram_phys		= 0x00010000,
- 	.sram_len		= SZ_32K,
- 	.reset_device		= &davinci_wdt_device,
- };
-diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
-index 3470983..df72a4e 100644
---- a/arch/arm/mach-davinci/dm644x.c
-+++ b/arch/arm/mach-davinci/dm644x.c
-@@ -765,7 +765,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
- 	.gpio_irq		= IRQ_GPIOBNK0,
- 	.serial_dev		= &dm644x_serial_device,
- 	.emac_pdata		= &dm644x_emac_pdata,
--	.sram_dma		= 0x00008000,
-+	.sram_phys		= 0x00008000,
- 	.sram_len		= SZ_16K,
- 	.reset_device		= &davinci_wdt_device,
- };
-diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
-index af27c13..4ab327a 100644
---- a/arch/arm/mach-davinci/dm646x.c
-+++ b/arch/arm/mach-davinci/dm646x.c
-@@ -852,7 +852,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
- 	.gpio_irq		= IRQ_DM646X_GPIOBNK0,
- 	.serial_dev		= &dm646x_serial_device,
- 	.emac_pdata		= &dm646x_emac_pdata,
--	.sram_dma		= 0x10010000,
-+	.sram_phys		= 0x10010000,
- 	.sram_len		= SZ_32K,
- 	.reset_device		= &davinci_wdt_device,
- };
-diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
-deleted file mode 100644
-index 9aa2409..0000000
---- a/arch/arm/mach-davinci/include/mach/asp.h
-+++ /dev/null
-@@ -1,137 +0,0 @@
--/*
-- * <mach/asp.h> - DaVinci Audio Serial Port support
-- */
--#ifndef __ASM_ARCH_DAVINCI_ASP_H
--#define __ASM_ARCH_DAVINCI_ASP_H
--
--#include <mach/irqs.h>
--#include <mach/edma.h>
--
--/* Bases of dm644x and dm355 register banks */
--#define DAVINCI_ASP0_BASE	0x01E02000
--#define DAVINCI_ASP1_BASE	0x01E04000
--
--/* Bases of dm365 register banks */
--#define DAVINCI_DM365_ASP0_BASE	0x01D02000
--
--/* Bases of dm646x register banks */
--#define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
--#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
--
--/* Bases of da850/da830 McASP0  register banks */
--#define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
--
--/* Bases of da830 McASP1 register banks */
--#define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
--
--/* EDMA channels of dm644x and dm355 */
--#define DAVINCI_DMA_ASP0_TX	2
--#define DAVINCI_DMA_ASP0_RX	3
--#define DAVINCI_DMA_ASP1_TX	8
--#define DAVINCI_DMA_ASP1_RX	9
--
--/* EDMA channels of dm646x */
--#define	DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
--#define	DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
--#define	DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
--
--/* EDMA channels of da850/da830 McASP0 */
--#define	DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
--#define	DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
--
--/* EDMA channels of da830 McASP1 */
--#define	DAVINCI_DA830_DMA_MCASP1_AREVT	2
--#define	DAVINCI_DA830_DMA_MCASP1_AXEVT	3
--
--/* Interrupts */
--#define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
--#define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
--#define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
--#define DAVINCI_ASP1_TX_INT	IRQ_MBXINT
--
--struct snd_platform_data {
--	u32 tx_dma_offset;
--	u32 rx_dma_offset;
--	enum dma_event_q asp_chan_q;	/* event queue number for ASP channel */
--	enum dma_event_q ram_chan_q;	/* event queue number for RAM channel */
--	unsigned int codec_fmt;
--	/*
--	 * Allowing this is more efficient and eliminates left and right swaps
--	 * caused by underruns, but will swap the left and right channels
--	 * when compared to previous behavior.
--	 */
--	unsigned enable_channel_combine:1;
--	unsigned sram_size_playback;
--	unsigned sram_size_capture;
--
--	/*
--	 * If McBSP peripheral gets the clock from an external pin,
--	 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
--	 * and MCBSP_CLKS.
--	 * Depending on different hardware connections it is possible
--	 * to use this setting to change the behaviour of McBSP
--	 * driver. The dm365_clk_input_pin enum is available for dm365
--	 */
--	int clk_input_pin;
--
--	/*
--	 * This flag works when both clock and FS are outputs for the cpu
--	 * and makes clock more accurate (FS is not symmetrical and the
--	 * clock is very fast.
--	 * The clock becoming faster is named
--	 * i2s continuous serial clock (I2S_SCK) and it is an externally
--	 * visible bit clock.
--	 *
--	 * first line : WordSelect
--	 * second line : ContinuousSerialClock
--	 * third line: SerialData
--	 *
--	 * SYMMETRICAL APPROACH:
--	 *   _______________________          LEFT
--	 * _|         RIGHT         |______________________|
--	 *     _   _         _   _   _   _         _   _
--	 *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
--	 *     _   _         _   _   _   _         _   _
--	 *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
--	 *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
--	 *
--	 * ACCURATE CLOCK APPROACH:
--	 *   ______________          LEFT
--	 * _|     RIGHT    |_______________________________|
--	 *     _         _   _         _   _   _   _   _   _
--	 *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
--	 *     _         _   _          _      dummy cycles
--	 *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
--	 *    \_/       \_/ \_/        \_/
--	 *
--	 */
--	bool i2s_accurate_sck;
--
--	/* McASP specific fields */
--	int tdm_slots;
--	u8 op_mode;
--	u8 num_serializer;
--	u8 *serial_dir;
--	u8 version;
--	u8 txnumevt;
--	u8 rxnumevt;
--};
--
--enum {
--	MCASP_VERSION_1 = 0,	/* DM646x */
--	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
--};
--
--enum dm365_clk_input_pin {
--	MCBSP_CLKR = 0,		/* DM365 */
--	MCBSP_CLKS,
--};
--
--#define INACTIVE_MODE	0
--#define TX_MODE		1
--#define RX_MODE		2
--
--#define DAVINCI_MCASP_IIS_MODE	0
--#define DAVINCI_MCASP_DIT_MODE	1
--
--#endif /* __ASM_ARCH_DAVINCI_ASP_H */
-diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
-index a57cba2..665d049 100644
---- a/arch/arm/mach-davinci/include/mach/common.h
-+++ b/arch/arm/mach-davinci/include/mach/common.h
-@@ -75,7 +75,7 @@ struct davinci_soc_info {
- 	int				gpio_ctlrs_num;
- 	struct platform_device		*serial_dev;
- 	struct emac_platform_data	*emac_pdata;
--	dma_addr_t			sram_dma;
-+	phys_addr_t			sram_phys;
- 	unsigned			sram_len;
- 	struct platform_device		*reset_device;
- 	void				(*reset)(struct platform_device *);
-diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
-index eaca7d8..f9a577d 100644
---- a/arch/arm/mach-davinci/include/mach/da8xx.h
-+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
-@@ -16,11 +16,12 @@
- #include <linux/platform_device.h>
- #include <linux/davinci_emac.h>
- #include <linux/spi/spi.h>
-+#include <linux/platform_data/uio_pruss.h>
- 
- #include <mach/serial.h>
- #include <mach/edma.h>
- #include <mach/i2c.h>
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- #include <mach/mmc.h>
- #include <mach/usb.h>
- #include <mach/pm.h>
-@@ -69,6 +70,7 @@ extern unsigned int da850_max_speed;
- #define DA8XX_AEMIF_CS3_BASE	0x62000000
- #define DA8XX_AEMIF_CTL_BASE	0x68000000
- #define DA8XX_ARM_RAM_BASE	0xffff0000
-+#define DA8XX_SHARED_RAM_BASE	0x80000000
- 
- void __init da830_init(void);
- void __init da850_init(void);
-@@ -81,6 +83,7 @@ int da8xx_register_watchdog(void);
- int da8xx_register_usb20(unsigned mA, unsigned potpgt);
- int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
- int da8xx_register_emac(void);
-+int da8xx_register_pruss_uio(struct uio_pruss_pdata *config);
- int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
- int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
- int da850_register_mmcsd1(struct davinci_mmc_config *config);
-diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
-index 36dff4a..a5829ea 100644
---- a/arch/arm/mach-davinci/include/mach/dm355.h
-+++ b/arch/arm/mach-davinci/include/mach/dm355.h
-@@ -12,7 +12,7 @@
- #define __ASM_ARCH_DM355_H
- 
- #include <mach/hardware.h>
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- #include <media/davinci/vpfe_capture.h>
- 
- #define DM355_ASYNC_EMIF_CONTROL_BASE	0x01E10000
-diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
-index 2563bf4..92d8db2 100644
---- a/arch/arm/mach-davinci/include/mach/dm365.h
-+++ b/arch/arm/mach-davinci/include/mach/dm365.h
-@@ -16,7 +16,7 @@
- #include <linux/platform_device.h>
- #include <linux/davinci_emac.h>
- #include <mach/hardware.h>
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- #include <mach/keyscan.h>
- #include <media/davinci/vpfe_capture.h>
- 
-diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
-index 5a1b26d..dd1bfa3 100644
---- a/arch/arm/mach-davinci/include/mach/dm644x.h
-+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
-@@ -24,7 +24,7 @@
- 
- #include <linux/davinci_emac.h>
- #include <mach/hardware.h>
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- #include <media/davinci/vpfe_capture.h>
- 
- #define DM644X_EMAC_BASE		(0x01C80000)
-diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
-index 2a00fe5..8294bc6 100644
---- a/arch/arm/mach-davinci/include/mach/dm646x.h
-+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
-@@ -12,7 +12,7 @@
- #define __ASM_ARCH_DM646X_H
- 
- #include <mach/hardware.h>
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- #include <linux/i2c.h>
- #include <linux/videodev2.h>
- #include <linux/davinci_emac.h>
-diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
-index d1b9549..b2267d1 100644
---- a/arch/arm/mach-davinci/include/mach/io.h
-+++ b/arch/arm/mach-davinci/include/mach/io.h
-@@ -21,12 +21,4 @@
- #define __mem_pci(a)		(a)
- #define __mem_isa(a)		(a)
- 
--#ifndef __ASSEMBLER__
--#define __arch_ioremap		davinci_ioremap
--#define __arch_iounmap		davinci_iounmap
--
--void __iomem *davinci_ioremap(unsigned long phys, size_t size,
--			      unsigned int type);
--void davinci_iounmap(volatile void __iomem *addr);
--#endif
- #endif /* __ASM_ARCH_IO_H */
-diff --git a/arch/arm/mach-davinci/include/mach/sram.h b/arch/arm/mach-davinci/include/mach/sram.h
-index 111f7cc..aa52009 100644
---- a/arch/arm/mach-davinci/include/mach/sram.h
-+++ b/arch/arm/mach-davinci/include/mach/sram.h
-@@ -10,18 +10,11 @@
- #ifndef __MACH_SRAM_H
- #define __MACH_SRAM_H
- 
-+#include <linux/genalloc.h>
-+
- /* ARBITRARY:  SRAM allocations are multiples of this 2^N size */
- #define SRAM_GRANULARITY	512
- 
--/*
-- * SRAM allocations return a CPU virtual address, or NULL on error.
-- * If a DMA address is requested and the SRAM supports DMA, its
-- * mapped address is also returned.
-- *
-- * Errors include SRAM memory not being available, and requesting
-- * DMA mapped SRAM on systems which don't allow that.
-- */
--extern void *sram_alloc(size_t len, dma_addr_t *dma);
--extern void sram_free(void *addr, size_t len);
-+extern struct gen_pool *davinci_gen_pool;
- 
- #endif /* __MACH_SRAM_H */
-diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h
-deleted file mode 100644
-index d49646a..0000000
---- a/arch/arm/mach-davinci/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,14 +0,0 @@
--/*
-- * DaVinci vmalloc definitions
-- *
-- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
-- *
-- * 2007 (c) MontaVista Software, Inc. This file is licensed under
-- * the terms of the GNU General Public License version 2. This program
-- * is licensed "as is" without any warranty of any kind, whether express
-- * or implied.
-- */
--#include <mach/hardware.h>
--
--/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
--#define VMALLOC_END	  (IO_VIRT - (2<<20))
-diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
-deleted file mode 100644
-index 8ea60a8..0000000
---- a/arch/arm/mach-davinci/io.c
-+++ /dev/null
-@@ -1,48 +0,0 @@
--/*
-- * DaVinci I/O mapping code
-- *
-- * Copyright (C) 2005-2006 Texas Instruments
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--
--#include <linux/module.h>
--#include <linux/io.h>
--
--#include <asm/tlb.h>
--#include <asm/mach/map.h>
--
--#include <mach/common.h>
--
--/*
-- * Intercept ioremap() requests for addresses in our fixed mapping regions.
-- */
--void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
--{
--	struct map_desc *desc = davinci_soc_info.io_desc;
--	int desc_num = davinci_soc_info.io_desc_num;
--	int i;
--
--	for (i = 0; i < desc_num; i++, desc++) {
--		unsigned long iophys = __pfn_to_phys(desc->pfn);
--		unsigned long iosize = desc->length;
--
--		if (p >= iophys && (p + size) <= (iophys + iosize))
--			return __io(desc->virtual + p - iophys);
--	}
--
--	return __arm_ioremap_caller(p, size, type,
--					__builtin_return_address(0));
--}
--EXPORT_SYMBOL(davinci_ioremap);
--
--void davinci_iounmap(volatile void __iomem *addr)
--{
--	unsigned long virt = (unsigned long)addr;
--
--	if (virt >= VMALLOC_START && virt < VMALLOC_END)
--		__iounmap(addr);
--}
--EXPORT_SYMBOL(davinci_iounmap);
-diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
-index 04c49f7..25b1d2a 100644
---- a/arch/arm/mach-davinci/pm.c
-+++ b/arch/arm/mach-davinci/pm.c
-@@ -18,6 +18,7 @@
- #include <asm/cacheflush.h>
- #include <asm/delay.h>
- #include <asm/io.h>
-+#include <asm/fncpy.h>
- 
- #include <mach/da8xx.h>
- #include <mach/sram.h>
-@@ -28,14 +29,9 @@
- #define DEEPSLEEP_SLEEPCOUNT_MASK	0xFFFF
- 
- static void (*davinci_sram_suspend) (struct davinci_pm_config *);
-+static void *davinci_sram_suspend_mem;
- static struct davinci_pm_config *pdata;
- 
--static void davinci_sram_push(void *dest, void *src, unsigned int size)
--{
--	memcpy(dest, src, size);
--	flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
--}
--
- static void davinci_pm_suspend(void)
- {
- 	unsigned val;
-@@ -124,14 +120,14 @@ static int __init davinci_pm_probe(struct platform_device *pdev)
- 		return -ENOENT;
- 	}
- 
--	davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
--	if (!davinci_sram_suspend) {
-+	davinci_sram_suspend_mem = (void *)gen_pool_alloc(davinci_gen_pool,
-+				davinci_cpu_suspend_sz);
-+	if (!davinci_sram_suspend_mem) {
- 		dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
- 		return -ENOMEM;
- 	}
--
--	davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
--						davinci_cpu_suspend_sz);
-+	davinci_sram_suspend = fncpy(davinci_sram_suspend_mem,
-+				&davinci_cpu_suspend, davinci_cpu_suspend_sz);
- 
- 	suspend_set_ops(&davinci_pm_ops);
- 
-@@ -140,7 +136,8 @@ static int __init davinci_pm_probe(struct platform_device *pdev)
- 
- static int __exit davinci_pm_remove(struct platform_device *pdev)
- {
--	sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
-+	gen_pool_free(davinci_gen_pool, (unsigned long)davinci_sram_suspend_mem,
-+		davinci_cpu_suspend_sz);
- 	return 0;
- }
- 
-diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
-index db0f778..2c53db2 100644
---- a/arch/arm/mach-davinci/sram.c
-+++ b/arch/arm/mach-davinci/sram.c
-@@ -10,40 +10,12 @@
-  */
- #include <linux/module.h>
- #include <linux/init.h>
--#include <linux/genalloc.h>
- 
- #include <mach/common.h>
- #include <mach/sram.h>
- 
--static struct gen_pool *sram_pool;
--
--void *sram_alloc(size_t len, dma_addr_t *dma)
--{
--	unsigned long vaddr;
--	dma_addr_t dma_base = davinci_soc_info.sram_dma;
--
--	if (dma)
--		*dma = 0;
--	if (!sram_pool || (dma && !dma_base))
--		return NULL;
--
--	vaddr = gen_pool_alloc(sram_pool, len);
--	if (!vaddr)
--		return NULL;
--
--	if (dma)
--		*dma = dma_base + (vaddr - SRAM_VIRT);
--	return (void *)vaddr;
--
--}
--EXPORT_SYMBOL(sram_alloc);
--
--void sram_free(void *addr, size_t len)
--{
--	gen_pool_free(sram_pool, (unsigned long) addr, len);
--}
--EXPORT_SYMBOL(sram_free);
--
-+struct gen_pool *davinci_gen_pool;
-+EXPORT_SYMBOL_GPL(davinci_gen_pool);
- 
- /*
-  * REVISIT This supports CPU and DMA access to/from SRAM, but it
-@@ -54,18 +26,19 @@ EXPORT_SYMBOL(sram_free);
- static int __init sram_init(void)
- {
- 	unsigned len = davinci_soc_info.sram_len;
--	int status = 0;
- 
--	if (len) {
--		len = min_t(unsigned, len, SRAM_SIZE);
--		sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
--		if (!sram_pool)
--			status = -ENOMEM;
--	}
--	if (sram_pool)
--		status = gen_pool_add(sram_pool, SRAM_VIRT, len, -1);
--	WARN_ON(status < 0);
--	return status;
-+	if (!len)
-+		return 0;
-+
-+	len = min_t(unsigned, len, SRAM_SIZE);
-+	davinci_gen_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
-+
-+	if (!davinci_gen_pool)
-+		return -ENOMEM;
-+
-+	WARN_ON(gen_pool_add_virt(davinci_gen_pool, SRAM_VIRT,
-+				  davinci_soc_info.sram_phys, len, -1));
-+
-+	return 0;
- }
- core_initcall(sram_init);
--
-diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
-index b20ec9a..ad1165d 100644
---- a/arch/arm/mach-dove/include/mach/dove.h
-+++ b/arch/arm/mach-dove/include/mach/dove.h
-@@ -11,8 +11,6 @@
- #ifndef __ASM_ARCH_DOVE_H
- #define __ASM_ARCH_DOVE_H
- 
--#include <mach/vmalloc.h>
--
- /*
-  * Marvell Dove address maps.
-  *
-diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h
-deleted file mode 100644
-index a28792c..0000000
---- a/arch/arm/mach-dove/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,5 +0,0 @@
--/*
-- * arch/arm/mach-dove/include/mach/vmalloc.h
-- */
--
--#define VMALLOC_END	0xfd800000UL
-diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
-index d0ce8ab..ce3ed24 100644
---- a/arch/arm/mach-ebsa110/core.c
-+++ b/arch/arm/mach-ebsa110/core.c
-@@ -283,7 +283,7 @@ MACHINE_START(EBSA110, "EBSA110")
- 	.atag_offset	= 0x400,
- 	.reserve_lp0	= 1,
- 	.reserve_lp2	= 1,
--	.soft_reboot	= 1,
-+	.restart_mode	= 's',
- 	.map_io		= ebsa110_map_io,
- 	.init_irq	= ebsa110_init_irq,
- 	.timer		= &ebsa110_timer,
-diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h
-index 9a26245..0d5df72 100644
---- a/arch/arm/mach-ebsa110/include/mach/system.h
-+++ b/arch/arm/mach-ebsa110/include/mach/system.h
-@@ -34,6 +34,6 @@ static inline void arch_idle(void)
- 	asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
- }
- 
--#define arch_reset(mode, cmd)	cpu_reset(0x80000000)
-+#define arch_reset(mode, cmd)	soft_restart(0x80000000)
- 
- #endif
-diff --git a/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
-deleted file mode 100644
-index ea141b7..0000000
---- a/arch/arm/mach-ebsa110/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,10 +0,0 @@
--/*
-- *  arch/arm/mach-ebsa110/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 1998 Russell King
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--#define VMALLOC_END       0xdf000000UL
-diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
-index 0713448..d9b0ea2 100644
---- a/arch/arm/mach-ep93xx/adssphere.c
-+++ b/arch/arm/mach-ep93xx/adssphere.c
-@@ -16,6 +16,7 @@
- 
- #include <mach/hardware.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
-@@ -36,6 +37,7 @@ MACHINE_START(ADSSPHERE, "ADS Sphere board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= adssphere_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
-index 70ef8c5..9bbae08 100644
---- a/arch/arm/mach-ep93xx/edb93xx.c
-+++ b/arch/arm/mach-ep93xx/edb93xx.c
-@@ -39,6 +39,7 @@
- #include <mach/ep93xx_spi.h>
- #include <mach/gpio-ep93xx.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
-@@ -250,6 +251,7 @@ MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= edb93xx_init_machine,
- MACHINE_END
-@@ -261,6 +263,7 @@ MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= edb93xx_init_machine,
- MACHINE_END
-@@ -272,6 +275,7 @@ MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= edb93xx_init_machine,
- MACHINE_END
-@@ -283,6 +287,7 @@ MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= edb93xx_init_machine,
- MACHINE_END
-@@ -294,6 +299,7 @@ MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= edb93xx_init_machine,
- MACHINE_END
-@@ -305,6 +311,7 @@ MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= edb93xx_init_machine,
- MACHINE_END
-@@ -316,6 +323,7 @@ MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= edb93xx_init_machine,
- MACHINE_END
-@@ -327,6 +335,7 @@ MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= edb93xx_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
-index 45ee205..1dd32a7 100644
---- a/arch/arm/mach-ep93xx/gesbc9312.c
-+++ b/arch/arm/mach-ep93xx/gesbc9312.c
-@@ -16,6 +16,7 @@
- 
- #include <mach/hardware.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
-@@ -36,6 +37,7 @@ MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= gesbc9312_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-ep93xx/include/mach/entry-macro.S b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
-index 96b85e2..9be6edc 100644
---- a/arch/arm/mach-ep93xx/include/mach/entry-macro.S
-+++ b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
-@@ -9,51 +9,9 @@
-  * the Free Software Foundation; either version 2 of the License, or (at
-  * your option) any later version.
-  */
--#include <mach/ep93xx-regs.h>
- 
- 		.macro	disable_fiq
- 		.endm
- 
--		.macro  get_irqnr_preamble, base, tmp
--		.endm
--
- 		.macro  arch_ret_to_user, tmp1, tmp2
- 		.endm
--
--		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--		ldr	\base, =(EP93XX_AHB_VIRT_BASE)
--		orr	\base, \base, #0x000b0000
--		mov	\irqnr, #0
--		ldr	\irqstat, [\base]		@ lower 32 interrupts
--		cmp	\irqstat, #0
--		bne	1001f
--
--		eor	\base, \base, #0x00070000
--		ldr	\irqstat, [\base]		@ upper 32 interrupts
--		cmp	\irqstat, #0
--		beq	1002f
--		mov	\irqnr, #0x20
--
--1001:
--		movs	\tmp, \irqstat, lsl #16
--		movne	\irqstat, \tmp
--		addeq	\irqnr, \irqnr, #16
--
--		movs	\tmp, \irqstat, lsl #8
--		movne	\irqstat, \tmp
--		addeq	\irqnr, \irqnr, #8
--
--		movs	\tmp, \irqstat, lsl #4
--		movne	\irqstat, \tmp
--		addeq	\irqnr, \irqnr, #4
--
--		movs	\tmp, \irqstat, lsl #2
--		movne	\irqstat, \tmp
--		addeq	\irqnr, \irqnr, #2
--
--		movs	\tmp, \irqstat, lsl #1
--		addeq	\irqnr, \irqnr, #1
--		orrs	\base, \base, #1
--
--1002:
--		.endm
-diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
-index 6d661fe..bdf6c4f 100644
---- a/arch/arm/mach-ep93xx/include/mach/system.h
-+++ b/arch/arm/mach-ep93xx/include/mach/system.h
-@@ -11,8 +11,6 @@ static inline void arch_idle(void)
- 
- static inline void arch_reset(char mode, const char *cmd)
- {
--	local_irq_disable();
--
- 	/*
- 	 * Set then clear the SWRST bit to initiate a software reset
- 	 */
-diff --git a/arch/arm/mach-ep93xx/include/mach/vmalloc.h b/arch/arm/mach-ep93xx/include/mach/vmalloc.h
-deleted file mode 100644
-index 1b3f25d..0000000
---- a/arch/arm/mach-ep93xx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,5 +0,0 @@
--/*
-- * arch/arm/mach-ep93xx/include/mach/vmalloc.h
-- */
--
--#define VMALLOC_END	0xfe800000UL
-diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
-index e72f736..a6dae6c 100644
---- a/arch/arm/mach-ep93xx/micro9.c
-+++ b/arch/arm/mach-ep93xx/micro9.c
-@@ -18,6 +18,7 @@
- 
- #include <mach/hardware.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
-@@ -80,6 +81,7 @@ MACHINE_START(MICRO9, "Contec Micro9-High")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= micro9_init_machine,
- MACHINE_END
-@@ -91,6 +93,7 @@ MACHINE_START(MICRO9M, "Contec Micro9-Mid")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= micro9_init_machine,
- MACHINE_END
-@@ -102,6 +105,7 @@ MACHINE_START(MICRO9L, "Contec Micro9-Lite")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= micro9_init_machine,
- MACHINE_END
-@@ -113,6 +117,7 @@ MACHINE_START(MICRO9S, "Contec Micro9-Slim")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= micro9_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
-index 52e090d..40121ba 100644
---- a/arch/arm/mach-ep93xx/simone.c
-+++ b/arch/arm/mach-ep93xx/simone.c
-@@ -25,6 +25,7 @@
- #include <mach/fb.h>
- #include <mach/gpio-ep93xx.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
-@@ -80,6 +81,7 @@ MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= simone_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
-index 8121e3a..ec7c63f 100644
---- a/arch/arm/mach-ep93xx/snappercl15.c
-+++ b/arch/arm/mach-ep93xx/snappercl15.c
-@@ -31,6 +31,7 @@
- #include <mach/fb.h>
- #include <mach/gpio-ep93xx.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
-@@ -177,6 +178,7 @@ MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
- 	.atag_offset	= 0x100,
- 	.map_io		= ep93xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer 		= &ep93xx_timer,
- 	.init_machine	= snappercl15_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
-index 8b2f143..760384e 100644
---- a/arch/arm/mach-ep93xx/ts72xx.c
-+++ b/arch/arm/mach-ep93xx/ts72xx.c
-@@ -23,6 +23,7 @@
- #include <mach/hardware.h>
- #include <mach/ts72xx.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/map.h>
- #include <asm/mach/arch.h>
-@@ -247,6 +248,7 @@ MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
- 	.atag_offset	= 0x100,
- 	.map_io		= ts72xx_map_io,
- 	.init_irq	= ep93xx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &ep93xx_timer,
- 	.init_machine	= ts72xx_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
-index cc8d4bd..699774c 100644
---- a/arch/arm/mach-exynos/cpu.c
-+++ b/arch/arm/mach-exynos/cpu.c
-@@ -15,6 +15,7 @@
- #include <asm/mach/irq.h>
- 
- #include <asm/proc-fns.h>
-+#include <asm/exception.h>
- #include <asm/hardware/cache-l2x0.h>
- #include <asm/hardware/gic.h>
- 
-@@ -33,8 +34,6 @@
- #include <mach/regs-irq.h>
- #include <mach/regs-pmu.h>
- 
--unsigned int gic_bank_offset __read_mostly;
--
- extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
- 			 unsigned int irq_start);
- extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
-@@ -202,27 +201,14 @@ void __init exynos4_init_clocks(int xtal)
- 	exynos4_setup_clocks();
- }
- 
--static void exynos4_gic_irq_fix_base(struct irq_data *d)
--{
--	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
--
--	gic_data->cpu_base = S5P_VA_GIC_CPU +
--			    (gic_bank_offset * smp_processor_id());
--
--	gic_data->dist_base = S5P_VA_GIC_DIST +
--			    (gic_bank_offset * smp_processor_id());
--}
--
- void __init exynos4_init_irq(void)
- {
- 	int irq;
-+	unsigned int gic_bank_offset;
- 
- 	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
- 
--	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
--	gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
--	gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
--	gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
-+	gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
- 
- 	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
- 
-diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
-index f5e9fd8..3ba4f54 100644
---- a/arch/arm/mach-exynos/include/mach/entry-macro.S
-+++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
-@@ -9,83 +9,8 @@
-  * warranty of any kind, whether express or implied.
- */
- 
--#include <mach/hardware.h>
--#include <mach/map.h>
--#include <asm/hardware/gic.h>
--
- 		.macro	disable_fiq
- 		.endm
- 
--		.macro  get_irqnr_preamble, base, tmp
--		mov	\tmp, #0
--
--		mrc	p15, 0, \base, c0, c0, 5
--		and	\base, \base, #3
--		cmp	\base, #0
--		beq	1f
--
--		ldr	\tmp, =gic_bank_offset
--		ldr	\tmp, [\tmp]
--		cmp	\base, #1
--		beq	1f
--
--		cmp	\base, #2
--		addeq	\tmp, \tmp, \tmp
--		addne	\tmp, \tmp, \tmp, LSL #1
--
--1:		ldr	\base, =gic_cpu_base_addr
--		ldr	\base, [\base]
--		add	\base, \base, \tmp
--		.endm
--
- 		.macro  arch_ret_to_user, tmp1, tmp2
- 		.endm
--
--		/*
--		 * The interrupt numbering scheme is defined in the
--		 * interrupt controller spec.  To wit:
--		 *
--		 * Interrupts 0-15 are IPI
--		 * 16-28 are reserved
--		 * 29-31 are local.  We allow 30 to be used for the watchdog.
--		 * 32-1020 are global
--		 * 1021-1022 are reserved
--		 * 1023 is "spurious" (no interrupt)
--		 *
--		 * For now, we ignore all local interrupts so only return an interrupt if it's
--		 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
--		 *
--		 * A simple read from the controller will tell us the number of the highest
--                 * priority enabled interrupt.  We then just need to check whether it is in the
--		 * valid range for an IRQ (30-1020 inclusive).
--		 */
--
--		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
--
--		ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
--
--		ldr	\tmp, =1021
--
--		bic     \irqnr, \irqstat, #0x1c00
--
--		cmp     \irqnr, #15
--		cmpcc	\irqnr, \irqnr
--		cmpne	\irqnr, \tmp
--		cmpcs	\irqnr, \irqnr
--		addne	\irqnr, \irqnr, #32
--
--		.endm
--
--		/* We assume that irqstat (the raw value of the IRQ acknowledge
--		 * register) is preserved from the macro above.
--		 * If there is an IPI, we immediately signal end of interrupt on the
--		 * controller, since this requires the original irqstat value which
--		 * we won't easily be able to recreate later.
--		 */
--
--		.macro test_for_ipi, irqnr, irqstat, base, tmp
--		bic	\irqnr, \irqstat, #0x1c00
--		cmp	\irqnr, #16
--		strcc	\irqstat, [\base, #GIC_CPU_EOI]
--		cmpcs	\irqnr, \irqnr
--		.endm
-diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
-deleted file mode 100644
-index 284330e..0000000
---- a/arch/arm/mach-exynos/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,22 +0,0 @@
--/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
-- *
-- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
-- *		http://www.samsung.com
-- *
-- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
-- *
-- * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- *
-- * EXYNOS4 vmalloc definition
--*/
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H __FILE__
--
--#define VMALLOC_END	0xF6000000UL
--
--#endif /* __ASM_ARCH_VMALLOC_H */
-diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
-index f0ca6c1..49da308 100644
---- a/arch/arm/mach-exynos/mach-armlex4210.c
-+++ b/arch/arm/mach-exynos/mach-armlex4210.c
-@@ -16,6 +16,7 @@
- #include <linux/smsc911x.h>
- 
- #include <asm/mach/arch.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- 
- #include <plat/cpu.h>
-@@ -210,6 +211,7 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
- 	.atag_offset	= 0x100,
- 	.init_irq	= exynos4_init_irq,
- 	.map_io		= armlex4210_map_io,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= armlex4210_machine_init,
- 	.timer		= &exynos4_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
-index 236bbe1..5acec11 100644
---- a/arch/arm/mach-exynos/mach-nuri.c
-+++ b/arch/arm/mach-exynos/mach-nuri.c
-@@ -32,6 +32,7 @@
- #include <media/v4l2-mediabus.h>
- 
- #include <asm/mach/arch.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- 
- #include <plat/adc.h>
-@@ -1333,6 +1334,7 @@ MACHINE_START(NURI, "NURI")
- 	.atag_offset	= 0x100,
- 	.init_irq	= exynos4_init_irq,
- 	.map_io		= nuri_map_io,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= nuri_machine_init,
- 	.timer		= &exynos4_timer,
- 	.reserve        = &nuri_reserve,
-diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
-index f80b563..5561b06 100644
---- a/arch/arm/mach-exynos/mach-origen.c
-+++ b/arch/arm/mach-exynos/mach-origen.c
-@@ -22,6 +22,7 @@
- #include <linux/lcd.h>
- 
- #include <asm/mach/arch.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- 
- #include <video/platform_lcd.h>
-@@ -694,6 +695,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
- 	.atag_offset	= 0x100,
- 	.init_irq	= exynos4_init_irq,
- 	.map_io		= origen_map_io,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= origen_machine_init,
- 	.timer		= &exynos4_timer,
- 	.reserve	= &origen_reserve,
-diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
-index fcf2e0e..722d82d 100644
---- a/arch/arm/mach-exynos/mach-smdk4x12.c
-+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
-@@ -21,6 +21,7 @@
- #include <linux/serial_core.h>
- 
- #include <asm/mach/arch.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- 
- #include <plat/backlight.h>
-@@ -287,6 +288,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
- 	.atag_offset	= 0x100,
- 	.init_irq	= exynos4_init_irq,
- 	.map_io		= smdk4x12_map_io,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= smdk4x12_machine_init,
- 	.timer		= &exynos4_timer,
- MACHINE_END
-@@ -297,6 +299,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
- 	.atag_offset	= 0x100,
- 	.init_irq	= exynos4_init_irq,
- 	.map_io		= smdk4x12_map_io,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= smdk4x12_machine_init,
- 	.timer		= &exynos4_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
-index cec2afa..edc60b6 100644
---- a/arch/arm/mach-exynos/mach-smdkv310.c
-+++ b/arch/arm/mach-exynos/mach-smdkv310.c
-@@ -21,6 +21,7 @@
- #include <linux/pwm_backlight.h>
- 
- #include <asm/mach/arch.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- 
- #include <video/platform_lcd.h>
-@@ -375,6 +376,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
- 	.atag_offset	= 0x100,
- 	.init_irq	= exynos4_init_irq,
- 	.map_io		= smdkv310_map_io,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= smdkv310_machine_init,
- 	.timer		= &exynos4_timer,
- 	.reserve	= &smdkv310_reserve,
-@@ -385,6 +387,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
- 	.atag_offset	= 0x100,
- 	.init_irq	= exynos4_init_irq,
- 	.map_io		= smdkv310_map_io,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= smdkv310_machine_init,
- 	.timer		= &exynos4_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
-index a2a177f..cfc7d50 100644
---- a/arch/arm/mach-exynos/mach-universal_c210.c
-+++ b/arch/arm/mach-exynos/mach-universal_c210.c
-@@ -24,6 +24,7 @@
- #include <linux/i2c/atmel_mxt_ts.h>
- 
- #include <asm/mach/arch.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- 
- #include <plat/regs-serial.h>
-@@ -1058,6 +1059,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
- 	.atag_offset	= 0x100,
- 	.init_irq	= exynos4_init_irq,
- 	.map_io		= universal_map_io,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= universal_machine_init,
- 	.timer		= &exynos4_timer,
- 	.reserve        = &universal_reserve,
-diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
-index 69ffb2f..60bc45e 100644
---- a/arch/arm/mach-exynos/platsmp.c
-+++ b/arch/arm/mach-exynos/platsmp.c
-@@ -32,7 +32,6 @@
- 
- #include <plat/cpu.h>
- 
--extern unsigned int gic_bank_offset;
- extern void exynos4_secondary_startup(void);
- 
- #define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
-@@ -65,31 +64,6 @@ static void __iomem *scu_base_addr(void)
- 
- static DEFINE_SPINLOCK(boot_lock);
- 
--static void __cpuinit exynos4_gic_secondary_init(void)
--{
--	void __iomem *dist_base = S5P_VA_GIC_DIST +
--				(gic_bank_offset * smp_processor_id());
--	void __iomem *cpu_base = S5P_VA_GIC_CPU +
--				(gic_bank_offset * smp_processor_id());
--	int i;
--
--	/*
--	 * Deal with the banked PPI and SGI interrupts - disable all
--	 * PPI interrupts, ensure all SGI interrupts are enabled.
--	 */
--	__raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
--	__raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
--
--	/*
--	 * Set priority on PPI and SGI interrupts
--	 */
--	for (i = 0; i < 32; i += 4)
--		__raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
--
--	__raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
--	__raw_writel(1, cpu_base + GIC_CPU_CTRL);
--}
--
- void __cpuinit platform_secondary_init(unsigned int cpu)
- {
- 	/*
-@@ -97,7 +71,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
- 	 * core (e.g. timer irq), then they will not have been enabled
- 	 * for us: do so
- 	 */
--	exynos4_gic_secondary_init();
-+	gic_secondary_init(0);
- 
- 	/*
- 	 * let the primary processor know we're out of the
-diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
-index d5f1785..60b6774 100644
---- a/arch/arm/mach-footbridge/cats-hw.c
-+++ b/arch/arm/mach-footbridge/cats-hw.c
-@@ -86,7 +86,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
- MACHINE_START(CATS, "Chalice-CATS")
- 	/* Maintainer: Philip Blundell */
- 	.atag_offset	= 0x100,
--	.soft_reboot	= 1,
-+	.restart_mode	= 's',
- 	.fixup		= fixup_cats,
- 	.map_io		= footbridge_map_io,
- 	.init_irq	= footbridge_init_irq,
-diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h
-index 0b29315..249f895 100644
---- a/arch/arm/mach-footbridge/include/mach/system.h
-+++ b/arch/arm/mach-footbridge/include/mach/system.h
-@@ -24,7 +24,7 @@ static inline void arch_reset(char mode, const char *cmd)
- 		/*
- 		 * Jump into the ROM
- 		 */
--		cpu_reset(0x41000000);
-+		soft_restart(0x41000000);
- 	} else {
- 		if (machine_is_netwinder()) {
- 			/* open up the SuperIO chip
-diff --git a/arch/arm/mach-footbridge/include/mach/vmalloc.h b/arch/arm/mach-footbridge/include/mach/vmalloc.h
-deleted file mode 100644
-index 40ba78e..0000000
---- a/arch/arm/mach-footbridge/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,10 +0,0 @@
--/*
-- *  arch/arm/mach-footbridge/include/mach/vmalloc.h
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--
--
--#define VMALLOC_END       0xf0000000UL
-diff --git a/arch/arm/mach-gemini/include/mach/vmalloc.h b/arch/arm/mach-gemini/include/mach/vmalloc.h
-deleted file mode 100644
-index 45371eb..0000000
---- a/arch/arm/mach-gemini/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,10 +0,0 @@
--/*
-- *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- */
--
--#define VMALLOC_END	0xf0000000UL
-diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h
-deleted file mode 100644
-index 8520b4a..0000000
---- a/arch/arm/mach-h720x/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,10 +0,0 @@
--/*
-- * arch/arm/mach-h720x/include/mach/vmalloc.h
-- */
--
--#ifndef __ARCH_ARM_VMALLOC_H
--#define __ARCH_ARM_VMALLOC_H
--
--#define VMALLOC_END       0xd0000000UL
--
--#endif
-diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
-index 88660d5..7266dd5 100644
---- a/arch/arm/mach-highbank/highbank.c
-+++ b/arch/arm/mach-highbank/highbank.c
-@@ -144,6 +144,7 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
- 	.map_io		= highbank_map_io,
- 	.init_irq	= highbank_init_irq,
- 	.timer		= &highbank_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= highbank_init,
- 	.dt_compat	= highbank_match,
- MACHINE_END
-diff --git a/arch/arm/mach-highbank/include/mach/entry-macro.S b/arch/arm/mach-highbank/include/mach/entry-macro.S
-index 73c1129..a14f9e6 100644
---- a/arch/arm/mach-highbank/include/mach/entry-macro.S
-+++ b/arch/arm/mach-highbank/include/mach/entry-macro.S
-@@ -1,5 +1,3 @@
--#include <asm/hardware/entry-macro-gic.S>
--
- 	.macro	disable_fiq
- 	.endm
- 
-diff --git a/arch/arm/mach-highbank/include/mach/vmalloc.h b/arch/arm/mach-highbank/include/mach/vmalloc.h
-deleted file mode 100644
-index 1969e95..0000000
---- a/arch/arm/mach-highbank/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1 +0,0 @@
--#define VMALLOC_END		0xFEE00000UL
-diff --git a/arch/arm/mach-integrator/include/mach/vmalloc.h b/arch/arm/mach-integrator/include/mach/vmalloc.h
-deleted file mode 100644
-index 2f5a2ba..0000000
---- a/arch/arm/mach-integrator/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/*
-- *  arch/arm/mach-integrator/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2000 Russell King.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#define VMALLOC_END       0xd0000000UL
-diff --git a/arch/arm/mach-iop13xx/include/mach/vmalloc.h b/arch/arm/mach-iop13xx/include/mach/vmalloc.h
-deleted file mode 100644
-index c534567..0000000
---- a/arch/arm/mach-iop13xx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,4 +0,0 @@
--#ifndef _VMALLOC_H_
--#define _VMALLOC_H_
--#define VMALLOC_END 	0xfa000000UL
--#endif
-diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
-index 059c783..2d88264 100644
---- a/arch/arm/mach-iop32x/include/mach/io.h
-+++ b/arch/arm/mach-iop32x/include/mach/io.h
-@@ -13,15 +13,8 @@
- 
- #include <asm/hardware/iop3xx.h>
- 
--extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
--	unsigned int mtype);
--extern void __iop3xx_iounmap(void __iomem *addr);
--
- #define IO_SPACE_LIMIT		0xffffffff
- #define __io(p)		((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
- #define __mem_pci(a)		(a)
- 
--#define __arch_ioremap	__iop3xx_ioremap
--#define __arch_iounmap	__iop3xx_iounmap
--
- #endif
-diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
-index a4b808f..b4f83e5 100644
---- a/arch/arm/mach-iop32x/include/mach/system.h
-+++ b/arch/arm/mach-iop32x/include/mach/system.h
-@@ -18,8 +18,6 @@ static inline void arch_idle(void)
- 
- static inline void arch_reset(char mode, const char *cmd)
- {
--	local_irq_disable();
--
- 	if (machine_is_n2100()) {
- 		gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
- 		gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
-@@ -30,5 +28,5 @@ static inline void arch_reset(char mode, const char *cmd)
- 	*IOP3XX_PCSR = 0x30;
- 
- 	/* Jump into ROM at address 0 */
--	cpu_reset(0);
-+	soft_restart(0);
- }
-diff --git a/arch/arm/mach-iop32x/include/mach/vmalloc.h b/arch/arm/mach-iop32x/include/mach/vmalloc.h
-deleted file mode 100644
-index c4862d4..0000000
---- a/arch/arm/mach-iop32x/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,5 +0,0 @@
--/*
-- * arch/arm/mach-iop32x/include/mach/vmalloc.h
-- */
--
--#define VMALLOC_END	0xfe000000UL
-diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
-index 39e893e..a8a66fc 100644
---- a/arch/arm/mach-iop33x/include/mach/io.h
-+++ b/arch/arm/mach-iop33x/include/mach/io.h
-@@ -13,15 +13,8 @@
- 
- #include <asm/hardware/iop3xx.h>
- 
--extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
--	unsigned int mtype);
--extern void __iop3xx_iounmap(void __iomem *addr);
--
- #define IO_SPACE_LIMIT		0xffffffff
- #define __io(p)		((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
- #define __mem_pci(a)		(a)
- 
--#define __arch_ioremap	__iop3xx_ioremap
--#define __arch_iounmap	__iop3xx_iounmap
--
- #endif
-diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h
-index f192a34..86d1b20 100644
---- a/arch/arm/mach-iop33x/include/mach/system.h
-+++ b/arch/arm/mach-iop33x/include/mach/system.h
-@@ -19,5 +19,5 @@ static inline void arch_reset(char mode, const char *cmd)
- 	*IOP3XX_PCSR = 0x30;
- 
- 	/* Jump into ROM at address 0 */
--	cpu_reset(0);
-+	soft_restart(0);
- }
-diff --git a/arch/arm/mach-iop33x/include/mach/vmalloc.h b/arch/arm/mach-iop33x/include/mach/vmalloc.h
-deleted file mode 100644
-index 48331dc..0000000
---- a/arch/arm/mach-iop33x/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,5 +0,0 @@
--/*
-- * arch/arm/mach-iop33x/include/mach/vmalloc.h
-- */
--
--#define VMALLOC_END	0xfe000000UL
-diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
-index de37099..810df7b 100644
---- a/arch/arm/mach-ixp2000/include/mach/system.h
-+++ b/arch/arm/mach-ixp2000/include/mach/system.h
-@@ -19,8 +19,6 @@ static inline void arch_idle(void)
- 
- static inline void arch_reset(char mode, const char *cmd)
- {
--	local_irq_disable();
--
- 	/*
- 	 * Reset flash banking register so that we are pointing at
- 	 * RedBoot bank.
-diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
-deleted file mode 100644
-index 61c8dae..0000000
---- a/arch/arm/mach-ixp2000/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/*
-- * arch/arm/mach-ixp2000/include/mach/vmalloc.h
-- *
-- * Author: Naeem Afzal <naeem.m.afzal@intel.com>
-- *
-- * Copyright 2002 Intel Corp.
-- *
-- *  This program is free software; you can redistribute  it and/or modify it
-- *  under  the terms of  the GNU General  Public License as published by the
-- *  Free Software Foundation;  either version 2 of the  License, or (at your
-- *  option) any later version.
-- *
-- * Just any arbitrary offset to the start of the vmalloc VM area: the
-- * current 8MB value just means that there will be a 8MB "hole" after the
-- * physical memory until the kernel virtual memory starts.  That means that
-- * any out-of-bounds memory accesses will hopefully be caught.
-- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
-- * area for the same reason. ;)
-- */
--#define VMALLOC_END	    0xfb000000UL
-diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
-index a1749d0..4ce4353 100644
---- a/arch/arm/mach-ixp23xx/include/mach/io.h
-+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
-@@ -20,33 +20,4 @@
- #define __io(p)		((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
- #define __mem_pci(a)	(a)
- 
--static inline void __iomem *
--ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
--{
--	if (addr >= IXP23XX_PCI_MEM_START &&
--		addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
--		if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
--			return NULL;
--
--		return (void __iomem *)
-- 			((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
--	}
--
--	return __arm_ioremap(addr, size, mtype);
--}
--
--static inline void
--ixp23xx_iounmap(void __iomem *addr)
--{
--	if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
--	    (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
--		return;
--
--	__iounmap(addr);
--}
--
--#define __arch_ioremap	ixp23xx_ioremap
--#define __arch_iounmap	ixp23xx_iounmap
--
--
- #endif
-diff --git a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
-deleted file mode 100644
-index 896c56a..0000000
---- a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,10 +0,0 @@
--/*
-- * arch/arm/mach-ixp23xx/include/mach/vmalloc.h
-- *
-- * Copyright (c) 2005 MontaVista Software, Inc.
-- *
-- * NPU mappings end at 0xf0000000 and we allocate 64MB for board
-- * specific static I/O.
-- */
--
--#define VMALLOC_END	(0xec000000UL)
-diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h
-index 54c0af7..24337d9 100644
---- a/arch/arm/mach-ixp4xx/include/mach/system.h
-+++ b/arch/arm/mach-ixp4xx/include/mach/system.h
-@@ -26,7 +26,7 @@ static inline void arch_reset(char mode, const char *cmd)
- {
- 	if ( 1 && mode == 's') {
- 		/* Jump into ROM at address 0 */
--		cpu_reset(0);
-+		soft_restart(0);
- 	} else {
- 		/* Use on-chip reset capability */
- 
-diff --git a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
-deleted file mode 100644
-index 9bcd64d..0000000
---- a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,5 +0,0 @@
--/*
-- * arch/arm/mach-ixp4xx/include/mach/vmalloc.h
-- */
--#define VMALLOC_END       (0xff000000UL)
--
-diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
-index 1aaddc3..49dd0cb 100644
---- a/arch/arm/mach-kirkwood/include/mach/io.h
-+++ b/arch/arm/mach-kirkwood/include/mach/io.h
-@@ -19,31 +19,6 @@ static inline void __iomem *__io(unsigned long addr)
- 					+ KIRKWOOD_PCIE_IO_VIRT_BASE);
- }
- 
--static inline void __iomem *
--__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
--{
--	void __iomem *retval;
--	unsigned long offs = paddr - KIRKWOOD_REGS_PHYS_BASE;
--	if (mtype == MT_DEVICE && size && offs < KIRKWOOD_REGS_SIZE &&
--	    size <= KIRKWOOD_REGS_SIZE && offs + size <= KIRKWOOD_REGS_SIZE) {
--		retval = (void __iomem *)KIRKWOOD_REGS_VIRT_BASE + offs;
--	} else {
--		retval = __arm_ioremap(paddr, size, mtype);
--	}
--
--	return retval;
--}
--
--static inline void
--__arch_iounmap(void __iomem *addr)
--{
--	if (addr < (void __iomem *)KIRKWOOD_REGS_VIRT_BASE ||
--	    addr >= (void __iomem *)(KIRKWOOD_REGS_VIRT_BASE + KIRKWOOD_REGS_SIZE))
--		__iounmap(addr);
--}
--
--#define __arch_ioremap		__arch_ioremap
--#define __arch_iounmap		__arch_iounmap
- #define __io(a)			__io(a)
- #define __mem_pci(a)		(a)
- 
-diff --git a/arch/arm/mach-kirkwood/include/mach/vmalloc.h b/arch/arm/mach-kirkwood/include/mach/vmalloc.h
-deleted file mode 100644
-index bf162ca..0000000
---- a/arch/arm/mach-kirkwood/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,5 +0,0 @@
--/*
-- * arch/arm/mach-kirkwood/include/mach/vmalloc.h
-- */
--
--#define VMALLOC_END	0xfe800000UL
-diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h
-index fb1dda9..ceb19c9 100644
---- a/arch/arm/mach-ks8695/include/mach/system.h
-+++ b/arch/arm/mach-ks8695/include/mach/system.h
-@@ -32,7 +32,7 @@ static void arch_reset(char mode, const char *cmd)
- 	unsigned int reg;
- 
- 	if (mode == 's')
--		cpu_reset(0);
-+		soft_restart(0);
- 
- 	/* disable timer0 */
- 	reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
-diff --git a/arch/arm/mach-ks8695/include/mach/vmalloc.h b/arch/arm/mach-ks8695/include/mach/vmalloc.h
-deleted file mode 100644
-index 744ac66..0000000
---- a/arch/arm/mach-ks8695/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,19 +0,0 @@
--/*
-- * arch/arm/mach-ks8695/include/mach/vmalloc.h
-- *
-- * Copyright (C) 2006 Ben Dooks
-- * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk>
-- *
-- * KS8695 vmalloc definition
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H
--
--#define VMALLOC_END	  (KS8695_IO_VA & PGDIR_MASK)
--
--#endif
-diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
-index df3b0de..d47f3b1 100644
---- a/arch/arm/mach-lpc32xx/include/mach/system.h
-+++ b/arch/arm/mach-lpc32xx/include/mach/system.h
-@@ -33,9 +33,6 @@ static inline void arch_reset(char mode, const char *cmd)
- 	case 'h':
- 		printk(KERN_CRIT "RESET: Rebooting system\n");
- 
--		/* Disable interrupts */
--		local_irq_disable();
--
- 		lpc32xx_watchdog_reset();
- 		break;
- 
-diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
-deleted file mode 100644
-index 720fa43..0000000
---- a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,24 +0,0 @@
--/*
-- * arch/arm/mach-lpc32xx/include/mach/vmalloc.h
-- *
-- * Author: Kevin Wells <kevin.wells@nxp.com>
-- *
-- * Copyright (C) 2010 NXP Semiconductors
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- */
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H
--
--#define VMALLOC_END	0xF0000000UL
--
--#endif
-diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
-index 1a8a25e..cb06379 100644
---- a/arch/arm/mach-mmp/include/mach/system.h
-+++ b/arch/arm/mach-mmp/include/mach/system.h
-@@ -19,8 +19,8 @@ static inline void arch_idle(void)
- static inline void arch_reset(char mode, const char *cmd)
- {
- 	if (cpu_is_pxa168())
--		cpu_reset(0xffff0000);
-+		soft_restart(0xffff0000);
- 	else
--		cpu_reset(0);
-+		soft_restart(0);
- }
- #endif /* __ASM_MACH_SYSTEM_H */
-diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h
-deleted file mode 100644
-index 1d0bac0..0000000
---- a/arch/arm/mach-mmp/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,5 +0,0 @@
--/*
-- * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
-- */
--
--#define VMALLOC_END	0xfe000000UL
-diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
-index 6dc1cbd..ed35981 100644
---- a/arch/arm/mach-msm/board-msm8960.c
-+++ b/arch/arm/mach-msm/board-msm8960.c
-@@ -99,6 +99,7 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
- 	.map_io = msm8960_map_io,
- 	.init_irq = msm8960_init_irq,
- 	.timer = &msm_timer,
-+	.handle_irq = gic_handle_irq,
- 	.init_machine = msm8960_sim_init,
- MACHINE_END
- 
-@@ -108,6 +109,7 @@ MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
- 	.map_io = msm8960_map_io,
- 	.init_irq = msm8960_init_irq,
- 	.timer = &msm_timer,
-+	.handle_irq = gic_handle_irq,
- 	.init_machine = msm8960_rumi3_init,
- MACHINE_END
- 
-diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
-index 44bf716..0a11342 100644
---- a/arch/arm/mach-msm/board-msm8x60.c
-+++ b/arch/arm/mach-msm/board-msm8x60.c
-@@ -108,6 +108,7 @@ MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
- 	.reserve = msm8x60_reserve,
- 	.map_io = msm8x60_map_io,
- 	.init_irq = msm8x60_init_irq,
-+	.handle_irq = gic_handle_irq,
- 	.init_machine = msm8x60_init,
- 	.timer = &msm_timer,
- MACHINE_END
-@@ -117,6 +118,7 @@ MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
- 	.reserve = msm8x60_reserve,
- 	.map_io = msm8x60_map_io,
- 	.init_irq = msm8x60_init_irq,
-+	.handle_irq = gic_handle_irq,
- 	.init_machine = msm8x60_init,
- 	.timer = &msm_timer,
- MACHINE_END
-@@ -126,6 +128,7 @@ MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
- 	.reserve = msm8x60_reserve,
- 	.map_io = msm8x60_map_io,
- 	.init_irq = msm8x60_init_irq,
-+	.handle_irq = gic_handle_irq,
- 	.init_machine = msm8x60_init,
- 	.timer = &msm_timer,
- MACHINE_END
-@@ -135,6 +138,7 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
- 	.reserve = msm8x60_reserve,
- 	.map_io = msm8x60_map_io,
- 	.init_irq = msm8x60_init_irq,
-+	.handle_irq = gic_handle_irq,
- 	.init_machine = msm8x60_init,
- 	.timer = &msm_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
-deleted file mode 100644
-index 717076f..0000000
---- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/*
-- * Low-level IRQ helper macros
-- *
-- * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
-- *
-- * This file is licensed under  the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-- */
--
--#include <asm/hardware/entry-macro-gic.S>
--
--	.macro	disable_fiq
--	.endm
--
--	.macro  arch_ret_to_user, tmp1, tmp2
--	.endm
-diff --git a/arch/arm/mach-msm/include/mach/entry-macro-vic.S b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
-deleted file mode 100644
-index 70563ed..0000000
---- a/arch/arm/mach-msm/include/mach/entry-macro-vic.S
-+++ /dev/null
-@@ -1,37 +0,0 @@
--/*
-- * Copyright (C) 2007 Google, Inc.
-- * Author: Brian Swetland <swetland@google.com>
-- *
-- * This software is licensed under the terms of the GNU General Public
-- * License version 2, as published by the Free Software Foundation, and
-- * may be copied, distributed, and modified under those terms.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- */
--
--#include <mach/msm_iomap.h>
--
--	.macro	disable_fiq
--	.endm
--
--	.macro	get_irqnr_preamble, base, tmp
--	@ enable imprecise aborts
--	cpsie	a
--	mov	\base, #MSM_VIC_BASE
--	.endm
--
--	.macro	arch_ret_to_user, tmp1, tmp2
--	.endm
--
--	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--	@ 0xD0 has irq# or old irq# if the irq has been handled
--	@ 0xD4 has irq# or -1 if none pending *but* if you just
--	@ read 0xD4 you never get the first irq for some reason
--	ldr	\irqnr, [\base, #0xD0]
--	ldr	\irqnr, [\base, #0xD4]
--	cmp	\irqnr, #0xffffffff
--	.endm
-diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
-index b16f082..41f7003 100644
---- a/arch/arm/mach-msm/include/mach/entry-macro.S
-+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
-@@ -16,8 +16,27 @@
-  *
-  */
- 
--#if defined(CONFIG_ARM_GIC)
--#include <mach/entry-macro-qgic.S>
--#else
--#include <mach/entry-macro-vic.S>
-+	.macro	disable_fiq
-+	.endm
-+
-+	.macro	arch_ret_to_user, tmp1, tmp2
-+	.endm
-+
-+#if !defined(CONFIG_ARM_GIC)
-+#include <mach/msm_iomap.h>
-+
-+	.macro	get_irqnr_preamble, base, tmp
-+	@ enable imprecise aborts
-+	cpsie	a
-+	mov	\base, #MSM_VIC_BASE
-+	.endm
-+
-+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-+	@ 0xD0 has irq# or old irq# if the irq has been handled
-+	@ 0xD4 has irq# or -1 if none pending *but* if you just
-+	@ read 0xD4 you never get the first irq for some reason
-+	ldr	\irqnr, [\base, #0xD0]
-+	ldr	\irqnr, [\base, #0xD4]
-+	cmp	\irqnr, #0xffffffff
-+	.endm
- #endif
-diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h
-deleted file mode 100644
-index d138448..0000000
---- a/arch/arm/mach-msm/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,22 +0,0 @@
--/* arch/arm/mach-msm/include/mach/vmalloc.h
-- *
-- * Copyright (C) 2007 Google, Inc.
-- *
-- * This software is licensed under the terms of the GNU General Public
-- * License version 2, as published by the Free Software Foundation, and
-- * may be copied, distributed, and modified under those terms.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- */
--
--#ifndef __ASM_ARCH_MSM_VMALLOC_H
--#define __ASM_ARCH_MSM_VMALLOC_H
--
--#define VMALLOC_END	  0xd0000000UL
--
--#endif
--
-diff --git a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
-deleted file mode 100644
-index ba26fe9..0000000
---- a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,5 +0,0 @@
--/*
-- * arch/arm/mach-mv78xx0/include/mach/vmalloc.h
-- */
--
--#define VMALLOC_END	0xfe000000UL
-diff --git a/arch/arm/mach-mxs/include/mach/vmalloc.h b/arch/arm/mach-mxs/include/mach/vmalloc.h
-deleted file mode 100644
-index 103b016..0000000
---- a/arch/arm/mach-mxs/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,22 +0,0 @@
--/*
-- *  Copyright (C) 2000 Russell King.
-- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- */
--
--#ifndef __MACH_MXS_VMALLOC_H__
--#define __MACH_MXS_VMALLOC_H__
--
--/* vmalloc ending address */
--#define VMALLOC_END       0xf4000000UL
--
--#endif /* __MACH_MXS_VMALLOC_H__ */
-diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
-index 20ec3bd..cab8836 100644
---- a/arch/arm/mach-mxs/system.c
-+++ b/arch/arm/mach-mxs/system.c
-@@ -53,7 +53,7 @@ void arch_reset(char mode, const char *cmd)
- 	mdelay(50);
- 
- 	/* We'll take a jump through zero as a poor second */
--	cpu_reset(0);
-+	soft_restart(0);
- }
- 
- static int __init mxs_arch_reset_init(void)
-diff --git a/arch/arm/mach-netx/include/mach/entry-macro.S b/arch/arm/mach-netx/include/mach/entry-macro.S
-index 844f1f9..6e9f1cb 100644
---- a/arch/arm/mach-netx/include/mach/entry-macro.S
-+++ b/arch/arm/mach-netx/include/mach/entry-macro.S
-@@ -18,22 +18,9 @@
-  * along with this program; if not, write to the Free Software
-  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-  */
--#include <mach/hardware.h>
- 
- 		.macro  disable_fiq
- 		.endm
- 
--		.macro  get_irqnr_preamble, base, tmp
--		ldr	\base, =io_p2v(0x001ff000)
--		.endm
--
- 		.macro  arch_ret_to_user, tmp1, tmp2
- 		.endm
--
--		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
--		ldr	\irqstat, [\base, #0]
--		clz	\irqnr, \irqstat
--		rsb     \irqnr, \irqnr, #31
--		cmp	\irqstat, #0
--		.endm
--
-diff --git a/arch/arm/mach-netx/include/mach/vmalloc.h b/arch/arm/mach-netx/include/mach/vmalloc.h
-deleted file mode 100644
-index 871f1ef..0000000
---- a/arch/arm/mach-netx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,19 +0,0 @@
--/*
-- *  arch/arm/mach-netx/include/mach/vmalloc.h
-- *
-- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2
-- * as published by the Free Software Foundation.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#define VMALLOC_END       0xd0000000UL
-diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
-index 90903dd..ef8cf35 100644
---- a/arch/arm/mach-netx/nxdb500.c
-+++ b/arch/arm/mach-netx/nxdb500.c
-@@ -28,6 +28,7 @@
- #include <mach/hardware.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-+#include <asm/hardware/vic.h>
- #include <mach/netx-regs.h>
- #include <mach/eth.h>
- 
-@@ -203,6 +204,7 @@ MACHINE_START(NXDB500, "Hilscher nxdb500")
- 	.atag_offset	= 0x100,
- 	.map_io		= netx_map_io,
- 	.init_irq	= netx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &netx_timer,
- 	.init_machine	= nxdb500_init,
- MACHINE_END
-diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
-index c63384a..588558b 100644
---- a/arch/arm/mach-netx/nxdkn.c
-+++ b/arch/arm/mach-netx/nxdkn.c
-@@ -28,6 +28,7 @@
- #include <mach/hardware.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-+#include <asm/hardware/vic.h>
- #include <mach/netx-regs.h>
- #include <mach/eth.h>
- 
-@@ -96,6 +97,7 @@ MACHINE_START(NXDKN, "Hilscher nxdkn")
- 	.atag_offset	= 0x100,
- 	.map_io		= netx_map_io,
- 	.init_irq	= netx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &netx_timer,
- 	.init_machine	= nxdkn_init,
- MACHINE_END
-diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
-index 8f548ec..cfcbb50 100644
---- a/arch/arm/mach-netx/nxeb500hmi.c
-+++ b/arch/arm/mach-netx/nxeb500hmi.c
-@@ -28,6 +28,7 @@
- #include <mach/hardware.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-+#include <asm/hardware/vic.h>
- #include <mach/netx-regs.h>
- #include <mach/eth.h>
- 
-@@ -180,6 +181,7 @@ MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
- 	.atag_offset	= 0x100,
- 	.map_io		= netx_map_io,
- 	.init_irq	= netx_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &netx_timer,
- 	.init_machine	= nxeb500hmi_init,
- MACHINE_END
-diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
-index 0cbb74c..f98259c 100644
---- a/arch/arm/mach-nomadik/board-nhk8815.c
-+++ b/arch/arm/mach-nomadik/board-nhk8815.c
-@@ -21,6 +21,7 @@
- #include <linux/mtd/onenand.h>
- #include <linux/mtd/partitions.h>
- #include <linux/io.h>
-+#include <asm/hardware/vic.h>
- #include <asm/sizes.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-@@ -280,6 +281,7 @@ MACHINE_START(NOMADIK, "NHK8815")
- 	.atag_offset	= 0x100,
- 	.map_io		= cpu8815_map_io,
- 	.init_irq	= cpu8815_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &nomadik_timer,
- 	.init_machine	= nhk8815_platform_init,
- MACHINE_END
-diff --git a/arch/arm/mach-nomadik/include/mach/entry-macro.S b/arch/arm/mach-nomadik/include/mach/entry-macro.S
-index 49f1aa3..98ea1c1 100644
---- a/arch/arm/mach-nomadik/include/mach/entry-macro.S
-+++ b/arch/arm/mach-nomadik/include/mach/entry-macro.S
-@@ -6,38 +6,8 @@
-  * warranty of any kind, whether express or implied.
-  */
- 
--#include <mach/hardware.h>
--#include <mach/irqs.h>
--
- 	.macro	disable_fiq
- 	.endm
- 
--	.macro	get_irqnr_preamble, base, tmp
--	ldr	\base, =IO_ADDRESS(NOMADIK_IC_BASE)
--	.endm
--
- 	.macro	arch_ret_to_user, tmp1, tmp2
- 	.endm
--
--	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--
--	/* This stanza gets the irq mask from one of two status registers */
--	mov	\irqnr, #0
--	ldr	\irqstat, [\base, #VIC_REG_IRQSR0]	@ get masked status
--	cmp	\irqstat, #0
--	bne	1001f
--	add	\irqnr, \irqnr, #32
--	ldr	\irqstat, [\base, #VIC_REG_IRQSR1]	@ get masked status
--
--1001:	tst	\irqstat, #15
--	bne	1002f
--	add	\irqnr, \irqnr, #4
--	movs	\irqstat, \irqstat, lsr #4
--	bne	1001b
--1002:	tst	\irqstat, #1
--	bne	1003f
--	add	\irqnr, \irqnr, #1
--	movs	\irqstat, \irqstat, lsr #1
--	bne	1002b
--1003:	/* EQ will be set if no irqs pending */
--	.endm
-diff --git a/arch/arm/mach-nomadik/include/mach/vmalloc.h b/arch/arm/mach-nomadik/include/mach/vmalloc.h
-deleted file mode 100644
-index f83d574..0000000
---- a/arch/arm/mach-nomadik/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,2 +0,0 @@
--
--#define VMALLOC_END       0xe8000000UL
-diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
-index 73f287d..4f8d66f 100644
---- a/arch/arm/mach-omap1/Kconfig
-+++ b/arch/arm/mach-omap1/Kconfig
-@@ -168,70 +168,6 @@ config MACH_OMAP_GENERIC
-           custom OMAP boards. Say Y here if you have a custom
-           board.
- 
--comment "OMAP CPU Speed"
--	depends on ARCH_OMAP1
--
--config OMAP_ARM_216MHZ
--	bool "OMAP ARM 216 MHz CPU (1710 only)"
--        depends on ARCH_OMAP1 && ARCH_OMAP16XX
--        help
--          Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N.
--
--config OMAP_ARM_195MHZ
--	bool "OMAP ARM 195 MHz CPU"
--	depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
--	help
--          Enable 195MHz clock for OMAP CPU. If unsure, say N.
--
--config OMAP_ARM_192MHZ
--	bool "OMAP ARM 192 MHz CPU"
--	depends on ARCH_OMAP1 && ARCH_OMAP16XX
--	help
--          Enable 192MHz clock for OMAP CPU. If unsure, say N.
--
--config OMAP_ARM_182MHZ
--	bool "OMAP ARM 182 MHz CPU"
--	depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
--	help
--          Enable 182MHz clock for OMAP CPU. If unsure, say N.
--
--config OMAP_ARM_168MHZ
--	bool "OMAP ARM 168 MHz CPU"
--	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
--	help
--          Enable 168MHz clock for OMAP CPU. If unsure, say N.
--
--config OMAP_ARM_150MHZ
--	bool "OMAP ARM 150 MHz CPU"
--	depends on ARCH_OMAP1 && ARCH_OMAP15XX
--	help
--	  Enable 150MHz clock for OMAP CPU. If unsure, say N.
--
--config OMAP_ARM_120MHZ
--	bool "OMAP ARM 120 MHz CPU"
--	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
--	help
--          Enable 120MHz clock for OMAP CPU. If unsure, say N.
--
--config OMAP_ARM_96MHZ
--	bool "OMAP ARM 96 MHz CPU"
--	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
--	help
--          Enable 96MHz clock for OMAP CPU. If unsure, say N.
--
--config OMAP_ARM_60MHZ
--	bool "OMAP ARM 60 MHz CPU"
--	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
--        default y
--	help
--          Enable 60MHz clock for OMAP CPU. If unsure, say Y.
--
--config OMAP_ARM_30MHZ
--	bool "OMAP ARM 30 MHz CPU"
--	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
--	help
--          Enable 30MHz clock for OMAP CPU. If unsure, say N.
--
- endmenu
- 
- endif
-diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
-index b0f15d2..af791196 100644
---- a/arch/arm/mach-omap1/board-ams-delta.c
-+++ b/arch/arm/mach-omap1/board-ams-delta.c
-@@ -35,7 +35,7 @@
- #include <plat/mux.h>
- #include <plat/usb.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <mach/camera.h>
- 
- #include <mach/ams-delta-fiq.h>
-diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
-index 2317827..b9c4c0f 100644
---- a/arch/arm/mach-omap1/board-fsample.c
-+++ b/arch/arm/mach-omap1/board-fsample.c
-@@ -32,7 +32,7 @@
- #include <plat/flash.h>
- #include <plat/fpga.h>
- #include <plat/keypad.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/board.h>
- 
- /* fsample is pretty close to p2-sample */
-diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
-index dc5b75d..7f41d7a 100644
---- a/arch/arm/mach-omap1/board-generic.c
-+++ b/arch/arm/mach-omap1/board-generic.c
-@@ -25,7 +25,7 @@
- #include <plat/mux.h>
- #include <plat/usb.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- 
- /* assume no Mini-AB port */
- 
-diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
-index b334b14..7933b97 100644
---- a/arch/arm/mach-omap1/board-h2.c
-+++ b/arch/arm/mach-omap1/board-h2.c
-@@ -43,7 +43,7 @@
- #include <plat/irda.h>
- #include <plat/usb.h>
- #include <plat/keypad.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/flash.h>
- 
- #include "board-h2.h"
-diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
-index 74ebe72..04be2f8 100644
---- a/arch/arm/mach-omap1/board-h3.c
-+++ b/arch/arm/mach-omap1/board-h3.c
-@@ -45,7 +45,7 @@
- #include <plat/usb.h>
- #include <plat/keypad.h>
- #include <plat/dma.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/flash.h>
- 
- #include "board-h3.h"
-diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
-index 3e91baa..46fcfeb 100644
---- a/arch/arm/mach-omap1/board-htcherald.c
-+++ b/arch/arm/mach-omap1/board-htcherald.c
-@@ -41,7 +41,7 @@
- #include <asm/mach/arch.h>
- 
- #include <plat/omap7xx.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/board.h>
- #include <plat/keypad.h>
- #include <plat/usb.h>
-diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
-index 273153d..f99d11d 100644
---- a/arch/arm/mach-omap1/board-innovator.c
-+++ b/arch/arm/mach-omap1/board-innovator.c
-@@ -37,7 +37,7 @@
- #include <plat/tc.h>
- #include <plat/usb.h>
- #include <plat/keypad.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/mmc.h>
- 
- /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
-diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
-index 6798b84..f0dfc51 100644
---- a/arch/arm/mach-omap1/board-nokia770.c
-+++ b/arch/arm/mach-omap1/board-nokia770.c
-@@ -12,6 +12,8 @@
- #include <linux/init.h>
- #include <linux/mutex.h>
- #include <linux/platform_device.h>
-+#include <linux/platform_data/cbus.h>
-+#include <linux/irq.h>
- #include <linux/input.h>
- #include <linux/clk.h>
- #include <linux/omapfb.h>
-@@ -30,7 +32,7 @@
- #include <plat/usb.h>
- #include <plat/board.h>
- #include <plat/keypad.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/hwa742.h>
- #include <plat/lcd_mipid.h>
- #include <plat/mmc.h>
-@@ -82,6 +84,104 @@ static struct platform_device nokia770_kp_device = {
- 	.resource	= nokia770_kp_resources,
- };
- 
-+#if defined(CONFIG_CBUS) || defined(CONFIG_CBUS_MODULE)
-+
-+static struct cbus_host_platform_data nokia770_cbus_data = {
-+	.clk_gpio	= OMAP_MPUIO(11),
-+	.dat_gpio	= OMAP_MPUIO(10),
-+	.sel_gpio	= OMAP_MPUIO(9),
-+};
-+
-+static struct platform_device nokia770_cbus_device = {
-+	.name		= "cbus",
-+	.id		= -1,
-+	.dev		= {
-+		.platform_data = &nokia770_cbus_data,
-+	},
-+};
-+
-+static struct resource retu_resource[] = {
-+	{
-+		.start	= -EINVAL, /* set later */
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+};
-+
-+static struct platform_device retu_device = {
-+	.name		= "retu",
-+	.id		= -1,
-+	.resource	= retu_resource,
-+	.num_resources	= ARRAY_SIZE(retu_resource),
-+	.dev		= {
-+		.parent	= &nokia770_cbus_device.dev,
-+	},
-+};
-+
-+static struct resource tahvo_resource[] = {
-+	{
-+		.start	= -EINVAL, /* set later */
-+		.flags	= IORESOURCE_IRQ,
-+	}
-+};
-+
-+static struct platform_device tahvo_device = {
-+	.name		= "tahvo",
-+	.id		= -1,
-+	.resource	= tahvo_resource,
-+	.num_resources	= ARRAY_SIZE(tahvo_resource),
-+	.dev		= {
-+		.parent	= &nokia770_cbus_device.dev,
-+	},
-+};
-+
-+static void __init nokia770_cbus_init(void)
-+{
-+	int		ret;
-+
-+	platform_device_register(&nokia770_cbus_device);
-+
-+	ret = gpio_request(62, "RETU irq");
-+	if (ret < 0) {
-+		pr_err("retu: Unable to reserve IRQ GPIO\n");
-+		return;
-+	}
-+
-+	ret = gpio_direction_input(62);
-+	if (ret < 0) {
-+		pr_err("retu: Unable to change gpio direction\n");
-+		gpio_free(62);
-+		return;
-+	}
-+
-+	irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_RISING);
-+	retu_resource[0].start = gpio_to_irq(62);
-+	platform_device_register(&retu_device);
-+
-+	ret = gpio_request(40, "TAHVO irq");
-+	if (ret) {
-+		pr_err("tahvo: Unable to reserve IRQ GPIO\n");
-+		gpio_free(62);
-+		return;
-+	}
-+
-+	ret = gpio_direction_input(40);
-+	if (ret) {
-+		pr_err("tahvo: Unable to change direction\n");
-+		gpio_free(62);
-+		gpio_free(40);
-+		return;
-+	}
-+
-+	tahvo_resource[0].start = gpio_to_irq(40);
-+	platform_device_register(&tahvo_device);
-+}
-+
-+#else
-+static inline void __init nokia770_cbus_init(void)
-+{
-+}
-+#endif
-+
- static struct platform_device *nokia770_devices[] __initdata = {
- 	&nokia770_kp_device,
- };
-@@ -239,6 +339,7 @@ static void __init omap_nokia770_init(void)
- 	/* Unmask SleepX signal */
- 	omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
- 
-+	nokia770_cbus_init();
- 	platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
- 	spi_register_board_info(nokia770_spi_board_info,
- 				ARRAY_SIZE(nokia770_spi_board_info));
-diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
-index c385927..a409dfc 100644
---- a/arch/arm/mach-omap1/board-osk.c
-+++ b/arch/arm/mach-omap1/board-osk.c
-@@ -51,7 +51,7 @@
- #include <plat/usb.h>
- #include <plat/mux.h>
- #include <plat/tc.h>
--#include <plat/common.h>
-+#include "common.h"
- 
- /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
- #define OMAP_OSK_ETHR_START		0x04800300
-diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
-index f9c44cb..105292d 100644
---- a/arch/arm/mach-omap1/board-palmte.c
-+++ b/arch/arm/mach-omap1/board-palmte.c
-@@ -41,7 +41,7 @@
- #include <plat/board.h>
- #include <plat/irda.h>
- #include <plat/keypad.h>
--#include <plat/common.h>
-+#include "common.h"
- 
- #define PALMTE_USBDETECT_GPIO	0
- #define PALMTE_USB_OR_DC_GPIO	1
-diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
-index 11a9853..387a900 100644
---- a/arch/arm/mach-omap1/board-palmtt.c
-+++ b/arch/arm/mach-omap1/board-palmtt.c
-@@ -39,7 +39,7 @@
- #include <plat/board.h>
- #include <plat/irda.h>
- #include <plat/keypad.h>
--#include <plat/common.h>
-+#include "common.h"
- 
- #include <linux/spi/spi.h>
- #include <linux/spi/ads7846.h>
-diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
-index 4206157..df6d15e 100644
---- a/arch/arm/mach-omap1/board-palmz71.c
-+++ b/arch/arm/mach-omap1/board-palmz71.c
-@@ -41,7 +41,7 @@
- #include <plat/board.h>
- #include <plat/irda.h>
- #include <plat/keypad.h>
--#include <plat/common.h>
-+#include "common.h"
- 
- #include <linux/spi/spi.h>
- #include <linux/spi/ads7846.h>
-diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
-index 203ae07..57ecd7e 100644
---- a/arch/arm/mach-omap1/board-perseus2.c
-+++ b/arch/arm/mach-omap1/board-perseus2.c
-@@ -32,7 +32,7 @@
- #include <plat/fpga.h>
- #include <plat/flash.h>
- #include <plat/keypad.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/board.h>
- 
- static const unsigned int p2_keymap[] = {
-diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
-index 092a4c0..774ae39 100644
---- a/arch/arm/mach-omap1/board-sx1.c
-+++ b/arch/arm/mach-omap1/board-sx1.c
-@@ -40,7 +40,7 @@
- #include <plat/usb.h>
- #include <plat/tc.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/keypad.h>
- #include <plat/board-sx1.h>
- 
-diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
-index 61ed6cd..7721c14 100644
---- a/arch/arm/mach-omap1/board-voiceblue.c
-+++ b/arch/arm/mach-omap1/board-voiceblue.c
-@@ -34,7 +34,7 @@
- #include <asm/mach/map.h>
- 
- #include <plat/board-voiceblue.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/flash.h>
- #include <plat/mux.h>
- #include <plat/tc.h>
-diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
-index 84ef704..0c50df0 100644
---- a/arch/arm/mach-omap1/clock.c
-+++ b/arch/arm/mach-omap1/clock.c
-@@ -197,11 +197,10 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
- 	ref_rate = ck_ref_p->rate;
- 
- 	for (ptr = omap1_rate_table; ptr->rate; ptr++) {
--		if (ptr->xtal != ref_rate)
-+		if (!(ptr->flags & cpu_mask))
- 			continue;
- 
--		/* DPLL1 cannot be reprogrammed without risking system crash */
--		if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
-+		if (ptr->xtal != ref_rate)
- 			continue;
- 
- 		/* Can check only after xtal frequency check */
-@@ -215,12 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
- 	/*
- 	 * In most cases we should not need to reprogram DPLL.
- 	 * Reprogramming the DPLL is tricky, it must be done from SRAM.
--	 * (on 730, bit 13 must always be 1)
- 	 */
--	if (cpu_is_omap7xx())
--		omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
--	else
--		omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
-+	omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
- 
- 	/* XXX Do we need to recalculate the tree below DPLL1 at this point? */
- 	ck_dpll1_p->rate = ptr->pll_rate;
-@@ -290,6 +285,9 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
- 	highest_rate = -EINVAL;
- 
- 	for (ptr = omap1_rate_table; ptr->rate; ptr++) {
-+		if (!(ptr->flags & cpu_mask))
-+			continue;
-+
- 		if (ptr->xtal != ref_rate)
- 			continue;
- 
-diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
-index 16b1423..3d04f4f 100644
---- a/arch/arm/mach-omap1/clock.h
-+++ b/arch/arm/mach-omap1/clock.h
-@@ -111,4 +111,7 @@ extern const struct clkops clkops_dummy;
- extern const struct clkops clkops_uart_16xx;
- extern const struct clkops clkops_generic;
- 
-+/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
-+extern u32 cpu_mask;
-+
- #endif
-diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
-index 9ff90a7..94699a8 100644
---- a/arch/arm/mach-omap1/clock_data.c
-+++ b/arch/arm/mach-omap1/clock_data.c
-@@ -25,6 +25,7 @@
- #include <plat/clock.h>
- #include <plat/cpu.h>
- #include <plat/clkdev_omap.h>
-+#include <plat/sram.h>	/* for omap_sram_reprogram_clock() */
- #include <plat/usb.h>   /* for OTG_BASE */
- 
- #include "clock.h"
-@@ -778,12 +779,14 @@ static void __init omap1_show_rates(void)
- 		arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
- }
- 
-+u32 cpu_mask;
-+
- int __init omap1_clk_init(void)
- {
- 	struct omap_clk *c;
- 	const struct omap_clock_config *info;
- 	int crystal_type = 0; /* Default 12 MHz */
--	u32 reg, cpu_mask;
-+	u32 reg;
- 
- #ifdef CONFIG_DEBUG_LL
- 	/*
-@@ -808,6 +811,8 @@ int __init omap1_clk_init(void)
- 		clk_preinit(c->lk.clk);
- 
- 	cpu_mask = 0;
-+	if (cpu_is_omap1710())
-+		cpu_mask |= CK_1710;
- 	if (cpu_is_omap16xx())
- 		cpu_mask |= CK_16XX;
- 	if (cpu_is_omap1510())
-@@ -931,17 +936,13 @@ void __init omap1_clk_late_init(void)
- {
- 	unsigned long rate = ck_dpll1.rate;
- 
--	if (rate >= OMAP1_DPLL1_SANE_VALUE)
--		return;
--
--	/* System booting at unusable rate, force reprogramming of DPLL1 */
--	ck_dpll1_p->rate = 0;
--
- 	/* Find the highest supported frequency and enable it */
- 	if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
- 		pr_err("System frequencies not set, using default. Check your config.\n");
--		omap_writew(0x2290, DPLL_CTL);
--		omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL);
-+		/*
-+		 * Reprogramming the DPLL is tricky, it must be done from SRAM.
-+		 */
-+		omap_sram_reprogram_clock(0x2290, 0x0005);
- 		ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
- 	}
- 	propagate_rate(&ck_dpll1);
-diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
-new file mode 100644
-index 0000000..52c4eda
---- /dev/null
-+++ b/arch/arm/mach-omap1/common.h
-@@ -0,0 +1,61 @@
-+/*
-+ *
-+ * Header for code common to all OMAP1 machines.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the  GNU General Public License along
-+ * with this program; if not, write  to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H
-+#define __ARCH_ARM_MACH_OMAP1_COMMON_H
-+
-+#include <plat/common.h>
-+
-+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-+void omap7xx_map_io(void);
-+#else
-+static inline void omap7xx_map_io(void)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_ARCH_OMAP15XX
-+void omap15xx_map_io(void);
-+#else
-+static inline void omap15xx_map_io(void)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_ARCH_OMAP16XX
-+void omap16xx_map_io(void);
-+#else
-+static inline void omap16xx_map_io(void)
-+{
-+}
-+#endif
-+
-+void omap1_init_early(void);
-+void omap1_init_irq(void);
-+
-+extern struct sys_timer omap1_timer;
-+extern bool omap_32k_timer_init(void);
-+
-+#endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
-diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
-index 475cb2f..1d76a63 100644
---- a/arch/arm/mach-omap1/devices.c
-+++ b/arch/arm/mach-omap1/devices.c
-@@ -22,7 +22,7 @@
- #include <mach/hardware.h>
- #include <asm/mach/map.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/tc.h>
- #include <plat/board.h>
- #include <plat/mux.h>
-diff --git a/arch/arm/mach-omap1/include/mach/vmalloc.h b/arch/arm/mach-omap1/include/mach/vmalloc.h
-deleted file mode 100644
-index 22ec4a4..0000000
---- a/arch/arm/mach-omap1/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/*
-- *  arch/arm/mach-omap1/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2000 Russell King.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- */
--#define VMALLOC_END	0xd8000000UL
-diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
-index 7969cfd..8e55b6f 100644
---- a/arch/arm/mach-omap1/io.c
-+++ b/arch/arm/mach-omap1/io.c
-@@ -121,7 +121,6 @@ void __init omap16xx_map_io(void)
- void omap1_init_early(void)
- {
- 	omap_check_revision();
--	omap_ioremap_init();
- 
- 	/* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
- 	 * on a Posted Write in the TIPB Bridge".
-diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h
-index 07074d7..79a6838 100644
---- a/arch/arm/mach-omap1/opp.h
-+++ b/arch/arm/mach-omap1/opp.h
-@@ -21,6 +21,7 @@ struct mpu_rate {
- 	unsigned long		pll_rate;
- 	__u16			ckctl_val;
- 	__u16			dpllctl_val;
-+	u32			flags;
- };
- 
- extern struct mpu_rate omap1_rate_table[];
-diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
-index 75a5465..9cd4ddb 100644
---- a/arch/arm/mach-omap1/opp_data.c
-+++ b/arch/arm/mach-omap1/opp_data.c
-@@ -10,6 +10,7 @@
-  * published by the Free Software Foundation.
-  */
- 
-+#include <plat/clkdev_omap.h>
- #include "opp.h"
- 
- /*-------------------------------------------------------------------------
-@@ -20,40 +21,34 @@ struct mpu_rate omap1_rate_table[] = {
- 	 * NOTE: Comment order here is different from bits in CKCTL value:
- 	 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
- 	 */
--#if defined(CONFIG_OMAP_ARM_216MHZ)
--	{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
--#endif
--#if defined(CONFIG_OMAP_ARM_195MHZ)
--	{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
--#endif
--#if defined(CONFIG_OMAP_ARM_192MHZ)
--	{ 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
--	{ 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
--	{  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
--	{  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
--	{  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
--#endif
--#if defined(CONFIG_OMAP_ARM_182MHZ)
--	{ 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
--#endif
--#if defined(CONFIG_OMAP_ARM_168MHZ)
--	{ 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
--#endif
--#if defined(CONFIG_OMAP_ARM_150MHZ)
--	{ 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
--#endif
--#if defined(CONFIG_OMAP_ARM_120MHZ)
--	{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
--#endif
--#if defined(CONFIG_OMAP_ARM_96MHZ)
--	{  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
--#endif
--#if defined(CONFIG_OMAP_ARM_60MHZ)
--	{  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
--#endif
--#if defined(CONFIG_OMAP_ARM_30MHZ)
--	{  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
--#endif
-+	{ 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
-+			CK_1710 },
-+	{ 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
-+			CK_7XX },
-+	{ 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
-+			CK_16XX },
-+	{ 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
-+			CK_16XX },
-+	{  96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
-+			CK_16XX },
-+	{  48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */
-+			CK_16XX },
-+	{  24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */
-+			CK_16XX },
-+	{ 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */
-+			CK_7XX },
-+	{ 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */
-+			CK_16XX|CK_7XX },
-+	{ 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */
-+			CK_1510 },
-+	{ 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */
-+			CK_16XX|CK_1510|CK_310|CK_7XX },
-+	{  96000000, 12000000,  96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */
-+			CK_16XX|CK_1510|CK_310|CK_7XX },
-+	{  60000000, 12000000,  60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */
-+			CK_16XX|CK_1510|CK_310|CK_7XX },
-+	{  30000000, 12000000,  60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */
-+			CK_16XX|CK_1510|CK_310|CK_7XX },
- 	{ 0, 0, 0, 0, 0 },
- };
- 
-diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
-index 89ea20c..b551a62 100644
---- a/arch/arm/mach-omap1/pm.c
-+++ b/arch/arm/mach-omap1/pm.c
-@@ -584,6 +584,9 @@ static void omap_pm_init_proc(void)
- #endif /* DEBUG && CONFIG_PROC_FS */
- 
- static void (*saved_idle)(void) = NULL;
-+static void omap1_dummy_idle(void)
-+{
-+}
- 
- /*
-  *	omap_pm_prepare - Do preliminary suspend work.
-@@ -593,7 +596,7 @@ static int omap_pm_prepare(void)
- {
- 	/* We cannot sleep in idle until we have resumed */
- 	saved_idle = pm_idle;
--	pm_idle = NULL;
-+	pm_idle = omap1_dummy_idle;
- 
- 	return 0;
- }
-diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
-index a183777..485a21d 100644
---- a/arch/arm/mach-omap1/time.c
-+++ b/arch/arm/mach-omap1/time.c
-@@ -54,7 +54,7 @@
- #include <asm/mach/irq.h>
- #include <asm/mach/time.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #ifdef CONFIG_OMAP_MPU_TIMER
- 
-diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
-index 96604a5..9a54ef4 100644
---- a/arch/arm/mach-omap1/timer32k.c
-+++ b/arch/arm/mach-omap1/timer32k.c
-@@ -52,7 +52,7 @@
- #include <asm/irq.h>
- #include <asm/mach/irq.h>
- #include <asm/mach/time.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/dmtimer.h>
- 
- /*
-diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
-index e1293aa..e44e942 100644
---- a/arch/arm/mach-omap2/Kconfig
-+++ b/arch/arm/mach-omap2/Kconfig
-@@ -25,6 +25,7 @@ config ARCH_OMAP2
- 	depends on ARCH_OMAP2PLUS
- 	default y
- 	select CPU_V6
-+	select MULTI_IRQ_HANDLER
- 
- config ARCH_OMAP3
- 	bool "TI OMAP3"
-@@ -36,6 +37,7 @@ config ARCH_OMAP3
- 	select ARCH_HAS_OPP
- 	select PM_OPP if PM
- 	select ARM_CPU_SUSPEND if PM
-+	select MULTI_IRQ_HANDLER
- 
- config ARCH_OMAP4
- 	bool "TI OMAP4"
-@@ -74,8 +76,13 @@ config SOC_OMAP3430
- 	default y
- 	select ARCH_OMAP_OTG
- 
--config SOC_OMAPTI816X
--	bool "TI816X support"
-+config SOC_OMAPTI81XX
-+	bool "TI81XX support"
-+	depends on ARCH_OMAP3
-+	default y
-+
-+config SOC_OMAPAM33XX
-+	bool "AM33XX support"
- 	depends on ARCH_OMAP3
- 	default y
- 
-@@ -109,7 +116,6 @@ comment "OMAP Board Type"
- config MACH_OMAP_GENERIC
- 	bool "Generic OMAP2+ board"
- 	depends on ARCH_OMAP2PLUS
--	select USE_OF
- 	default y
- 	help
- 	  Support for generic TI OMAP2+ boards using Flattened Device Tree.
-@@ -177,6 +183,12 @@ config MACH_OMAP3_TORPEDO
- 	 for full description please see the products webpage at
- 	 http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
- 
-+config MACH_ENCORE
-+        bool "Barnes & Noble Encore (Nook Color)"
-+        depends on ARCH_OMAP3
-+	default y
-+        select OMAP_PACKAGE_CBP
-+
- config MACH_OVERO
- 	bool "Gumstix Overo board"
- 	depends on ARCH_OMAP3
-@@ -312,7 +324,22 @@ config MACH_OMAP_3630SDP
- 
- config MACH_TI8168EVM
- 	bool "TI8168 Evaluation Module"
--	depends on SOC_OMAPTI816X
-+	depends on SOC_OMAPTI81XX
-+	default y
-+
-+config MACH_TI8148EVM
-+	bool "TI8148 Evaluation Module"
-+	depends on SOC_OMAPTI81XX
-+	default y
-+
-+config MACH_AM335XEVM
-+	bool "AM335X Evaluation Module"
-+	depends on SOC_OMAPAM33XX
-+	default y
-+
-+config MACH_AM335XIAEVM
-+	bool "AM335X IA Evaluation Module"
-+	depends on SOC_OMAPAM33XX
- 	default y
- 
- config MACH_OMAP_4430SDP
-@@ -331,6 +358,12 @@ config MACH_OMAP4_PANDA
- 	select OMAP_PACKAGE_CBS
- 	select REGULATOR_FIXED_VOLTAGE
- 
-+config MACH_PCM049
-+	bool "OMAP4 based phyCORE OMAP4"
-+	depends on ARCH_OMAP4
-+	default y
-+	select OMAP_PACKAGE_CBS
-+
- config OMAP3_EMU
- 	bool "OMAP3 debugging peripherals"
- 	depends on ARCH_OMAP3
-@@ -351,6 +384,35 @@ config OMAP3_SDRC_AC_TIMING
- 	  wish to say no.  Selecting yes without understanding what is
- 	  going on could result in system crashes;
- 
-+config OMAP4_ERRATA_I688
-+	bool "OMAP4 errata: Async Bridge Corruption"
-+	depends on ARCH_OMAP4
-+	select ARCH_HAS_BARRIERS
-+	help
-+	  If a data is stalled inside asynchronous bridge because of back
-+	  pressure, it may be accepted multiple times, creating pointer
-+	  misalignment that will corrupt next transfers on that data path
-+	  until next reset of the system (No recovery procedure once the
-+	  issue is hit, the path remains consistently broken). Async bridge
-+	  can be found on path between MPU to EMIF and MPU to L3 interconnect.
-+	  This situation can happen only when the idle is initiated by a
-+	  Master Request Disconnection (which is trigged by software when
-+	  executing WFI on CPU).
-+	  The work-around for this errata needs all the initiators connected
-+	  through async bridge must ensure that data path is properly drained
-+	  before issuing WFI. This condition will be met if one Strongly ordered
-+	  access is performed to the target right before executing the WFI.
-+	  In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
-+	  IO barrier ensure that there is no synchronisation loss on initiators
-+	  operating on both interconnect port simultaneously.
-+
-+config OMAP3_EDMA
-+	bool "OMAP3 EDMA support"
-+	default n
-+	depends on ARCH_OMAP3
-+	help
-+	  Select this option if EDMA is used
-+
- endmenu
- 
- endif
-diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
-index b009f17..f275e74 100644
---- a/arch/arm/mach-omap2/Makefile
-+++ b/arch/arm/mach-omap2/Makefile
-@@ -11,10 +11,11 @@ hwmod-common				= omap_hwmod.o \
- 					  omap_hwmod_common_data.o
- clock-common				= clock.o clock_common_data.o \
- 					  clkt_dpll.o clkt_clksel.o
-+secure-common                          = omap-smc.o omap-secure.o
- 
--obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
--obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common)
--obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common)
-+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-+obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
- 
- obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
- 
-@@ -24,11 +25,13 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
- obj-$(CONFIG_SMP)			+= omap-smp.o omap-headsmp.o
- obj-$(CONFIG_LOCAL_TIMERS)		+= timer-mpu.o
- obj-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
--obj-$(CONFIG_ARCH_OMAP4)		+= omap44xx-smc.o omap4-common.o
-+obj-$(CONFIG_ARCH_OMAP4)		+= omap4-common.o omap-wakeupgen.o \
-+					   sleep44xx.o
- 
- plus_sec := $(call as-instr,.arch_extension sec,+sec)
- AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)
--AFLAGS_omap44xx-smc.o			:=-Wa,-march=armv7-a$(plus_sec)
-+AFLAGS_omap-smc.o			:=-Wa,-march=armv7-a$(plus_sec)
-+AFLAGS_sleep44xx.o			:=-Wa,-march=armv7-a$(plus_sec)
- 
- # Functions loaded to SRAM
- obj-$(CONFIG_SOC_OMAP2420)		+= sram242x.o
-@@ -44,6 +47,7 @@ obj-$(CONFIG_SOC_OMAP2420)		+= mux2420.o
- obj-$(CONFIG_SOC_OMAP2430)		+= mux2430.o
- obj-$(CONFIG_ARCH_OMAP3)		+= mux34xx.o
- obj-$(CONFIG_ARCH_OMAP4)		+= mux44xx.o
-+obj-$(CONFIG_SOC_OMAPAM33XX)           += mux33xx.o
- 
- # SMS/SDRC
- obj-$(CONFIG_ARCH_OMAP2)		+= sdrc2xxx.o
-@@ -62,13 +66,17 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
- obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
- obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o \
- 					   cpuidle34xx.o
--obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o
-+obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o \
-+					   cpuidle44xx.o
-+obj-$(CONFIG_SOC_OMAPAM33XX)		+= cpuidle33xx.o pm33xx.o \
-+					   sleep33xx.o
- obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
- obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
- obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
- 
- AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
- AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a$(plus_sec)
-+AFLAGS_sleep33xx.o			:=-Wa,-march=armv7-a$(plus_sec)
- 
- ifeq ($(CONFIG_PM_VERBOSE),y)
- CFLAGS_pm_bus.o				+= -DDEBUG
-@@ -77,16 +85,19 @@ endif
- endif
- 
- # PRCM
-+obj-y					+= prm_common.o
- obj-$(CONFIG_ARCH_OMAP2)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
- obj-$(CONFIG_ARCH_OMAP3)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
- 					   vc3xxx_data.o vp3xxx_data.o
-+obj-$(CONFIG_SOC_OMAPAM33XX)		+= cminst44xx.o
-+
- # XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
- # will be removed once the OMAP4 part of the codebase is converted to
- # use OMAP4-specific PRCM functions.
- obj-$(CONFIG_ARCH_OMAP4)		+= prcm.o cm2xxx_3xxx.o cminst44xx.o \
- 					   cm44xx.o prcm_mpu44xx.o \
- 					   prminst44xx.o vc44xx_data.o \
--					   vp44xx_data.o
-+					   vp44xx_data.o prm44xx.o
- 
- # OMAP voltage domains
- voltagedomain-common			:= voltage.o vc.o vp.o
-@@ -94,6 +105,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= $(voltagedomain-common) \
- 					   voltagedomains2xxx_data.o
- obj-$(CONFIG_ARCH_OMAP3)		+= $(voltagedomain-common) \
- 					   voltagedomains3xxx_data.o
-+obj-$(CONFIG_SOC_OMAPAM33XX)		+= $(voltagedomain-common) \
-+					   voltagedomains33xx_data.o
- obj-$(CONFIG_ARCH_OMAP4)		+= $(voltagedomain-common) \
- 					   voltagedomains44xx_data.o
- 
-@@ -107,6 +120,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(powerdomain-common) \
- 					   powerdomain2xxx_3xxx.o \
- 					   powerdomains3xxx_data.o \
- 					   powerdomains2xxx_3xxx_data.o
-+obj-$(CONFIG_SOC_OMAPAM33XX)		+= prminst44xx.o \
-+					   powerdomain44xx.o \
-+					   powerdomains33xx_data.o
- obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common) \
- 					   powerdomain44xx.o \
- 					   powerdomains44xx_data.o
-@@ -121,6 +137,8 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clockdomain.o \
- 					   clockdomain2xxx_3xxx.o \
- 					   clockdomains2xxx_3xxx_data.o \
- 					   clockdomains3xxx_data.o
-+obj-$(CONFIG_SOC_OMAPAM33XX)		+= clockdomain44xx.o \
-+					   clockdomains33xx_data.o
- obj-$(CONFIG_ARCH_OMAP4)		+= clockdomain.o \
- 					   clockdomain44xx.o \
- 					   clockdomains44xx_data.o
-@@ -139,6 +157,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(clock-common) clock3xxx.o \
- 					   clock3517.o clock36xx.o \
- 					   dpll3xxx.o clock3xxx_data.o \
- 					   clkt_iclk.o
-+obj-$(CONFIG_SOC_OMAPAM33XX)		+= clock33xx_data.o
- obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) clock44xx_data.o \
- 					   dpll3xxx.o dpll44xx.o
- 
-@@ -160,6 +179,7 @@ obj-$(CONFIG_SOC_OMAP2430)		+= omap_hwmod_2xxx_ipblock_data.o \
- obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_ipblock_data.o \
- 					   omap_hwmod_2xxx_3xxx_interconnect_data.o \
- 					   omap_hwmod_3xxx_data.o
-+obj-$(CONFIG_SOC_OMAPAM33XX)		+= omap_hwmod_33xx_data.o
- obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
- 
- # EMU peripherals
-@@ -232,6 +252,9 @@ obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o
- 
- obj-$(CONFIG_MACH_SBC3530)		+= board-omap3stalker.o
- obj-$(CONFIG_MACH_TI8168EVM)		+= board-ti8168evm.o
-+obj-$(CONFIG_MACH_TI8148EVM)		+= board-ti8168evm.o
-+obj-$(CONFIG_MACH_AM335XEVM)		+= board-am335xevm.o
-+obj-$(CONFIG_MACH_AM335XIAEVM)		+= board-am335xevm.o
- 
- # Platform specific device init code
- 
-diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
-index d704f0a..d88143f 100644
---- a/arch/arm/mach-omap2/board-2430sdp.c
-+++ b/arch/arm/mach-omap2/board-2430sdp.c
-@@ -34,7 +34,7 @@
- #include <asm/mach/map.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/gpmc.h>
- #include <plat/usb.h>
- #include <plat/gpmc-smc91x.h>
-@@ -301,6 +301,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
- 	.map_io		= omap243x_map_io,
- 	.init_early	= omap2430_init_early,
- 	.init_irq	= omap2_init_irq,
-+	.handle_irq	= omap2_intc_handle_irq,
- 	.init_machine	= omap_2430sdp_init,
- 	.timer		= &omap2_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
-index 77142c1..109b434 100644
---- a/arch/arm/mach-omap2/board-3430sdp.c
-+++ b/arch/arm/mach-omap2/board-3430sdp.c
-@@ -33,7 +33,7 @@
- #include <plat/mcspi.h>
- #include <plat/board.h>
- #include <plat/usb.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/dma.h>
- #include <plat/gpmc.h>
- #include <video/omapdss.h>
-@@ -475,106 +475,8 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
- static struct omap_board_mux board_mux[] __initdata = {
- 	{ .reg_offset = OMAP_MUX_TERMINATOR },
- };
--
--static struct omap_device_pad serial1_pads[] __initdata = {
--	/*
--	 * Note that off output enable is an active low
--	 * signal. So setting this means pin is a
--	 * input enabled in off mode
--	 */
--	OMAP_MUX_STATIC("uart1_cts.uart1_cts",
--			 OMAP_PIN_INPUT |
--			 OMAP_PIN_OFF_INPUT_PULLDOWN |
--			 OMAP_OFFOUT_EN |
--			 OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart1_rts.uart1_rts",
--			 OMAP_PIN_OUTPUT |
--			 OMAP_OFF_EN |
--			 OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart1_rx.uart1_rx",
--			 OMAP_PIN_INPUT |
--			 OMAP_PIN_OFF_INPUT_PULLDOWN |
--			 OMAP_OFFOUT_EN |
--			 OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart1_tx.uart1_tx",
--			 OMAP_PIN_OUTPUT |
--			 OMAP_OFF_EN |
--			 OMAP_MUX_MODE0),
--};
--
--static struct omap_device_pad serial2_pads[] __initdata = {
--	OMAP_MUX_STATIC("uart2_cts.uart2_cts",
--			 OMAP_PIN_INPUT_PULLUP |
--			 OMAP_PIN_OFF_INPUT_PULLDOWN |
--			 OMAP_OFFOUT_EN |
--			 OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart2_rts.uart2_rts",
--			 OMAP_PIN_OUTPUT |
--			 OMAP_OFF_EN |
--			 OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart2_rx.uart2_rx",
--			 OMAP_PIN_INPUT |
--			 OMAP_PIN_OFF_INPUT_PULLDOWN |
--			 OMAP_OFFOUT_EN |
--			 OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart2_tx.uart2_tx",
--			 OMAP_PIN_OUTPUT |
--			 OMAP_OFF_EN |
--			 OMAP_MUX_MODE0),
--};
--
--static struct omap_device_pad serial3_pads[] __initdata = {
--	OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
--			 OMAP_PIN_INPUT_PULLDOWN |
--			 OMAP_PIN_OFF_INPUT_PULLDOWN |
--			 OMAP_OFFOUT_EN |
--			 OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
--			 OMAP_PIN_OUTPUT |
--			 OMAP_OFF_EN |
--			 OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
--			 OMAP_PIN_INPUT |
--			 OMAP_PIN_OFF_INPUT_PULLDOWN |
--			 OMAP_OFFOUT_EN |
--			 OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
--			 OMAP_PIN_OUTPUT |
--			 OMAP_OFF_EN |
--			 OMAP_MUX_MODE0),
--};
--
--static struct omap_board_data serial1_data __initdata = {
--	.id		= 0,
--	.pads		= serial1_pads,
--	.pads_cnt	= ARRAY_SIZE(serial1_pads),
--};
--
--static struct omap_board_data serial2_data __initdata = {
--	.id		= 1,
--	.pads		= serial2_pads,
--	.pads_cnt	= ARRAY_SIZE(serial2_pads),
--};
--
--static struct omap_board_data serial3_data __initdata = {
--	.id		= 2,
--	.pads		= serial3_pads,
--	.pads_cnt	= ARRAY_SIZE(serial3_pads),
--};
--
--static inline void board_serial_init(void)
--{
--	omap_serial_init_port(&serial1_data);
--	omap_serial_init_port(&serial2_data);
--	omap_serial_init_port(&serial3_data);
--}
- #else
- #define board_mux	NULL
--
--static inline void board_serial_init(void)
--{
--	omap_serial_init();
--}
- #endif
- 
- /*
-@@ -711,7 +613,7 @@ static void __init omap_3430sdp_init(void)
- 	else
- 		gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
- 	omap_ads7846_init(1, gpio_pendown, 310, NULL);
--	board_serial_init();
-+	omap_serial_init();
- 	omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
- 	usb_musb_init(NULL);
- 	board_smc91x_init();
-@@ -728,6 +630,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3430_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap_3430sdp_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
-index f552305..7969dd9 100644
---- a/arch/arm/mach-omap2/board-3630sdp.c
-+++ b/arch/arm/mach-omap2/board-3630sdp.c
-@@ -16,7 +16,7 @@
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/board.h>
- #include <plat/gpmc-smc91x.h>
- #include <plat/usb.h>
-@@ -215,6 +215,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3630_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap_sdp_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
-index 02cd29a..44610d8 100644
---- a/arch/arm/mach-omap2/board-4430sdp.c
-+++ b/arch/arm/mach-omap2/board-4430sdp.c
-@@ -27,13 +27,13 @@
- #include <linux/leds_pwm.h>
- 
- #include <mach/hardware.h>
--#include <mach/omap4-common.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/usb.h>
- #include <plat/mmc.h>
- #include <plat/omap4-keypad.h>
-@@ -373,11 +373,17 @@ static struct platform_device sdp4430_vbat = {
- 	},
- };
- 
-+static struct platform_device sdp4430_dmic_codec = {
-+	.name	= "dmic-codec",
-+	.id	= -1,
-+};
-+
- static struct platform_device *sdp4430_devices[] __initdata = {
- 	&sdp4430_gpio_keys_device,
- 	&sdp4430_leds_gpio,
- 	&sdp4430_leds_pwm,
- 	&sdp4430_vbat,
-+	&sdp4430_dmic_codec,
- };
- 
- static struct omap_musb_board_data musb_board_data = {
-@@ -405,6 +411,7 @@ static struct omap2_hsmmc_info mmc[] = {
- 	{
- 		.mmc		= 5,
- 		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
-+		.pm_caps	= MMC_PM_KEEP_POWER,
- 		.gpio_cd	= -EINVAL,
- 		.gpio_wp	= -EINVAL,
- 		.ocr_mask	= MMC_VDD_165_195,
-@@ -843,74 +850,8 @@ static struct omap_board_mux board_mux[] __initdata = {
- 	{ .reg_offset = OMAP_MUX_TERMINATOR },
- };
- 
--static struct omap_device_pad serial2_pads[] __initdata = {
--	OMAP_MUX_STATIC("uart2_cts.uart2_cts",
--			 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart2_rts.uart2_rts",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart2_rx.uart2_rx",
--			 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart2_tx.uart2_tx",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--};
--
--static struct omap_device_pad serial3_pads[] __initdata = {
--	OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
--			 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
--			 OMAP_PIN_INPUT | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--};
--
--static struct omap_device_pad serial4_pads[] __initdata = {
--	OMAP_MUX_STATIC("uart4_rx.uart4_rx",
--			 OMAP_PIN_INPUT | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart4_tx.uart4_tx",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--};
--
--static struct omap_board_data serial2_data __initdata = {
--	.id		= 1,
--	.pads		= serial2_pads,
--	.pads_cnt	= ARRAY_SIZE(serial2_pads),
--};
--
--static struct omap_board_data serial3_data __initdata = {
--	.id		= 2,
--	.pads		= serial3_pads,
--	.pads_cnt	= ARRAY_SIZE(serial3_pads),
--};
--
--static struct omap_board_data serial4_data __initdata = {
--	.id		= 3,
--	.pads		= serial4_pads,
--	.pads_cnt	= ARRAY_SIZE(serial4_pads),
--};
--
--static inline void board_serial_init(void)
--{
--	struct omap_board_data bdata;
--	bdata.flags	= 0;
--	bdata.pads	= NULL;
--	bdata.pads_cnt	= 0;
--	bdata.id	= 0;
--	/* pass dummy data for UART1 */
--	omap_serial_init_port(&bdata);
--
--	omap_serial_init_port(&serial2_data);
--	omap_serial_init_port(&serial3_data);
--	omap_serial_init_port(&serial4_data);
--}
- #else
- #define board_mux	NULL
--
--static inline void board_serial_init(void)
--{
--	omap_serial_init();
--}
-  #endif
- 
- static void omap4_sdp4430_wifi_mux_init(void)
-@@ -960,7 +901,7 @@ static void __init omap_4430sdp_init(void)
- 	omap4_i2c_init();
- 	omap_sfh7741prox_init();
- 	platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
--	board_serial_init();
-+	omap_serial_init();
- 	omap_sdrc_init(NULL, NULL);
- 	omap4_sdp4430_wifi_init();
- 	omap4_twl6030_hsmmc_init(mmc);
-@@ -990,6 +931,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
- 	.map_io		= omap4_map_io,
- 	.init_early	= omap4430_init_early,
- 	.init_irq	= gic_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= omap_4430sdp_init,
- 	.timer		= &omap4_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-am335xevm.c b/arch/arm/mach-omap2/board-am335xevm.c
-new file mode 100644
-index 0000000..08a0425
---- /dev/null
-+++ b/arch/arm/mach-omap2/board-am335xevm.c
-@@ -0,0 +1,3158 @@
-+/*
-+ * Code for AM335X EVM.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/i2c.h>
-+#include <linux/module.h>
-+#include <linux/i2c/at24.h>
-+#include <linux/phy.h>
-+#include <linux/gpio.h>
-+#include <linux/leds.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/flash.h>
-+#include <linux/gpio_keys.h>
-+#include <linux/input.h>
-+#include <linux/input/matrix_keypad.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/nand.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/wl12xx.h>
-+#include <linux/ethtool.h>
-+#include <linux/mfd/tps65910.h>
-+#include <linux/mfd/tps65217.h>
-+#include <linux/pwm_backlight.h>
-+#include <linux/reboot.h>
-+#include <linux/pwm/pwm.h>
-+#include <linux/w1-gpio.h>
-+#include <linux/can/platform/mcp251x.h>
-+
-+/* LCD controller is similar to DA850 */
-+#include <video/da8xx-fb.h>
-+
-+#include <mach/hardware.h>
-+#include <mach/board-am335xevm.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/map.h>
-+#include <asm/hardware/asp.h>
-+
-+#include <plat/irqs.h>
-+#include <plat/board.h>
-+#include <plat/common.h>
-+#include <plat/lcdc.h>
-+#include <plat/usb.h>
-+#include <plat/mmc.h>
-+#include <plat/emif.h>
-+#include <plat/nand.h>
-+
-+#include "board-flash.h"
-+#include "cpuidle33xx.h"
-+#include "mux.h"
-+#include "devices.h"
-+#include "hsmmc.h"
-+
-+/* Convert GPIO signal to GPIO pin number */
-+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
-+
-+/* TLK PHY IDs */
-+#define TLK110_PHY_ID		0x2000A201
-+#define TLK110_PHY_MASK		0xfffffff0
-+
-+/* BBB PHY IDs */
-+#define BBB_PHY_ID		0x7c0f1
-+#define BBB_PHY_MASK		0xfffffffe
-+
-+/* TLK110 PHY register offsets */
-+#define TLK110_COARSEGAIN_REG	0x00A3
-+#define TLK110_LPFHPF_REG	0x00AC
-+#define TLK110_SPAREANALOG_REG	0x00B9
-+#define TLK110_VRCR_REG		0x00D0
-+#define TLK110_SETFFE_REG	0x0107
-+#define TLK110_FTSP_REG		0x0154
-+#define TLK110_ALFATPIDL_REG	0x002A
-+#define TLK110_PSCOEF21_REG	0x0096
-+#define TLK110_PSCOEF3_REG	0x0097
-+#define TLK110_ALFAFACTOR1_REG	0x002C
-+#define TLK110_ALFAFACTOR2_REG	0x0023
-+#define TLK110_CFGPS_REG	0x0095
-+#define TLK110_FTSPTXGAIN_REG	0x0150
-+#define TLK110_SWSCR3_REG	0x000B
-+#define TLK110_SCFALLBACK_REG	0x0040
-+#define TLK110_PHYRCR_REG	0x001F
-+
-+/* TLK110 register writes values */
-+#define TLK110_COARSEGAIN_VAL	0x0000
-+#define TLK110_LPFHPF_VAL	0x8000
-+#define TLK110_SPANALOG_VAL	0x0000
-+#define TLK110_VRCR_VAL		0x0008
-+#define TLK110_SETFFE_VAL	0x0605
-+#define TLK110_FTSP_VAL		0x0255
-+#define TLK110_ALFATPIDL_VAL	0x7998
-+#define TLK110_PSCOEF21_VAL	0x3A20
-+#define TLK110_PSCOEF3_VAL	0x003F
-+#define TLK110_ALFACTOR1_VAL	0xFF80
-+#define TLK110_ALFACTOR2_VAL	0x021C
-+#define TLK110_CFGPS_VAL	0x0000
-+#define TLK110_FTSPTXGAIN_VAL	0x6A88
-+#define TLK110_SWSCR3_VAL	0x0000
-+#define TLK110_SCFALLBACK_VAL	0xC11D
-+#define TLK110_PHYRCR_VAL	0x4000
-+
-+#if defined(CONFIG_TLK110_WORKAROUND) || \
-+		defined(CONFIG_TLK110_WORKAROUND_MODULE)
-+#define am335x_tlk110_phy_init()\
-+	do {	\
-+		phy_register_fixup_for_uid(TLK110_PHY_ID,\
-+					TLK110_PHY_MASK,\
-+					am335x_tlk110_phy_fixup);\
-+	} while (0);
-+#else
-+#define am335x_tlk110_phy_init() do { } while (0);
-+#endif
-+
-+static const struct display_panel disp_panel = {
-+	WVGA,
-+	32,
-+	32,
-+	COLOR_ACTIVE,
-+};
-+
-+/* LCD backlight platform Data */
-+#define AM335X_BACKLIGHT_MAX_BRIGHTNESS        100
-+#define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS    50
-+#define AM335X_PWM_PERIOD_NANO_SECONDS        (1000000 * 5)
-+
-+#define PWM_DEVICE_ID   "ecap.0"
-+
-+static struct platform_pwm_backlight_data am335x_backlight_data = {
-+	.pwm_id         = PWM_DEVICE_ID,
-+	.ch             = -1,
-+	.lth_brightness	= 21,
-+	.max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
-+	.dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
-+	.pwm_period_ns  = AM335X_PWM_PERIOD_NANO_SECONDS,
-+};
-+
-+static struct lcd_ctrl_config lcd_cfg = {
-+	&disp_panel,
-+	.ac_bias		= 255,
-+	.ac_bias_intrpt		= 0,
-+	.dma_burst_sz		= 16,
-+	.bpp			= 32,
-+	.fdd			= 0x80,
-+	.tft_alt_mode		= 0,
-+	.stn_565_mode		= 0,
-+	.mono_8bit_mode		= 0,
-+	.invert_line_clock	= 1,
-+	.invert_frm_clock	= 1,
-+	.sync_edge		= 0,
-+	.sync_ctrl		= 1,
-+	.raster_order		= 0,
-+};
-+
-+struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
-+	.manu_name		= "ThreeFive",
-+	.controller_data	= &lcd_cfg,
-+	.type			= "TFC_S9700RTWV35TR_01B",
-+};
-+
-+#include "common.h"
-+
-+static const struct display_panel bbtoys7_panel = {
-+	WVGA,
-+	16,
-+	16,
-+	COLOR_ACTIVE,
-+};
-+
-+#define BBTOYS7LCD_PWM_DEVICE_ID   "ehrpwm.1:0"
-+
-+static struct platform_pwm_backlight_data bbtoys7lcd_backlight_data = {
-+	.pwm_id         = BBTOYS7LCD_PWM_DEVICE_ID,
-+	.ch             = -1,
-+	.max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
-+	.dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
-+	.pwm_period_ns  = AM335X_PWM_PERIOD_NANO_SECONDS,
-+};
-+
-+static struct lcd_ctrl_config bbtoys7_cfg = {
-+	&bbtoys7_panel,
-+	.ac_bias		= 255,
-+	.ac_bias_intrpt		= 0,
-+	.dma_burst_sz		= 16,
-+	.bpp			= 16,
-+	.fdd			= 0x80,
-+	.tft_alt_mode		= 0,
-+	.stn_565_mode		= 0,
-+	.mono_8bit_mode		= 0,
-+	.invert_line_clock	= 1,
-+	.invert_frm_clock	= 1,
-+	.sync_edge		= 0,
-+	.sync_ctrl		= 1,
-+	.raster_order		= 0,
-+};
-+
-+struct da8xx_lcdc_platform_data bbtoys7_pdata = {
-+	.manu_name		= "ThreeFive",
-+	.controller_data	= &bbtoys7_cfg,
-+	.type			= "TFC_S9700RTWV35TR_01B",
-+};
-+
-+static struct lcd_ctrl_config bbtoys35_cfg = {
-+	&bbtoys7_panel,
-+	.ac_bias		= 255,
-+	.ac_bias_intrpt		= 0,
-+	.dma_burst_sz		= 16,
-+	.bpp			= 16,
-+	.fdd			= 0x80,
-+	.tft_alt_mode		= 0,
-+	.stn_565_mode		= 0,
-+	.mono_8bit_mode		= 0,
-+	.invert_line_clock	= 1,
-+	.invert_frm_clock	= 1,
-+	.sync_edge		= 0,
-+	.sync_ctrl		= 1,
-+	.raster_order		= 0,
-+};
-+
-+struct da8xx_lcdc_platform_data bbtoys35_pdata = {
-+	.manu_name		= "BBToys",
-+	.controller_data	= &bbtoys35_cfg,
-+	.type			= "CDTech_S035Q01",
-+};
-+
-+static const struct display_panel dvi_panel = {
-+	WVGA,
-+	16,
-+	16,
-+	COLOR_ACTIVE,
-+};
-+
-+static struct lcd_ctrl_config dvi_cfg = {
-+	&dvi_panel,
-+	.ac_bias		= 255,
-+	.ac_bias_intrpt		= 0,
-+	.dma_burst_sz		= 16,
-+	.bpp			= 16,
-+	.fdd			= 0x80,
-+	.tft_alt_mode		= 0,
-+	.stn_565_mode		= 0,
-+	.mono_8bit_mode		= 0,
-+	.invert_line_clock	= 1,
-+	.invert_frm_clock	= 1,
-+	.sync_edge		= 0,
-+	.sync_ctrl		= 1,
-+	.raster_order		= 0,
-+};
-+
-+struct da8xx_lcdc_platform_data dvi_pdata = {
-+	.manu_name		= "BBToys",
-+	.controller_data	= &dvi_cfg,
-+	.type			= "1024x768@60",
-+};
-+
-+/* TSc controller */
-+#include <linux/input/ti_tscadc.h>
-+#include <linux/lis3lv02d.h>
-+
-+/* TSc controller */
-+static struct tsc_data am335x_touchscreen_data  = {
-+	.wires  = 4,
-+	.x_plate_resistance = 200,
-+	.mode = TI_TSCADC_TSCMODE,
-+};
-+
-+static struct tsc_data bone_touchscreen_data  = {
-+	.mode = TI_TSCADC_GENMODE,
-+};
-+
-+static u8 am335x_iis_serializer_direction1[] = {
-+	INACTIVE_MODE,	INACTIVE_MODE,	TX_MODE,	RX_MODE,
-+	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
-+	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
-+	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
-+};
-+
-+static struct snd_platform_data am335x_evm_snd_data1 = {
-+	.tx_dma_offset	= 0x46400000,	/* McASP1 */
-+	.rx_dma_offset	= 0x46400000,
-+	.op_mode	= DAVINCI_MCASP_IIS_MODE,
-+	.num_serializer	= ARRAY_SIZE(am335x_iis_serializer_direction1),
-+	.tdm_slots	= 2,
-+	.serial_dir	= am335x_iis_serializer_direction1,
-+	.asp_chan_q	= EVENTQ_2,
-+	.version	= MCASP_VERSION_3,
-+	.txnumevt	= 1,
-+	.rxnumevt	= 1,
-+};
-+
-+static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
-+	{
-+		.mmc            = 1,
-+		.caps           = MMC_CAP_4_BIT_DATA,
-+		.gpio_cd        = GPIO_TO_PIN(0, 6),
-+		.gpio_wp        = GPIO_TO_PIN(3, 18),
-+		.ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
-+	},
-+	{
-+		.mmc            = 0,	/* will be set at runtime */
-+	},
-+	{
-+		.mmc            = 0,	/* will be set at runtime */
-+	},
-+	{}      /* Terminator */
-+};
-+
-+
-+#ifdef CONFIG_OMAP_MUX
-+static struct omap_board_mux board_mux[] __initdata = {
-+	AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
-+			AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
-+	AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
-+			AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
-+	{ .reg_offset = OMAP_MUX_TERMINATOR },
-+};
-+#else
-+#define	board_mux	NULL
-+#endif
-+
-+/* module pin mux structure */
-+struct pinmux_config {
-+	const char *string_name; /* signal name format */
-+	int val; /* Options for the mux register value */
-+};
-+
-+struct evm_dev_cfg {
-+	void (*device_init)(int evm_id, int profile);
-+
-+/*
-+* If the device is required on both baseboard & daughter board (ex i2c),
-+* specify DEV_ON_BASEBOARD
-+*/
-+#define DEV_ON_BASEBOARD	0
-+#define DEV_ON_DGHTR_BRD	1
-+	u32 device_on;
-+
-+	u32 profile;	/* Profiles (0-7) in which the module is present */
-+};
-+
-+/* AM335X - CPLD Register Offsets */
-+#define	CPLD_DEVICE_HDR	0x00 /* CPLD Header */
-+#define	CPLD_DEVICE_ID	0x04 /* CPLD identification */
-+#define	CPLD_DEVICE_REV	0x0C /* Revision of the CPLD code */
-+#define	CPLD_CFG_REG	0x10 /* Configuration Register */
-+
-+static struct i2c_client *cpld_client;
-+static u32 am335x_evm_id;
-+static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
-+};
-+
-+/*
-+* EVM Config held in On-Board eeprom device.
-+*
-+* Header Format
-+*
-+*  Name			Size	Contents
-+*			(Bytes)
-+*-------------------------------------------------------------
-+*  Header		4	0xAA, 0x55, 0x33, 0xEE
-+*
-+*  Board Name		8	Name for board in ASCII.
-+*				example "A33515BB" = "AM335X
-+				Low Cost EVM board"
-+*
-+*  Version		4	Hardware version code for board in
-+*				in ASCII. "1.0A" = rev.01.0A
-+*
-+*  Serial Number	12	Serial number of the board. This is a 12
-+*				character string which is WWYY4P16nnnn, where
-+*				WW = 2 digit week of the year of production
-+*				YY = 2 digit year of production
-+*				nnnn = incrementing board number
-+*
-+*  Configuration option	32	Codes(TBD) to show the configuration
-+*				setup on this board.
-+*
-+*  Available		32720	Available space for other non-volatile
-+*				data.
-+*/
-+struct am335x_evm_eeprom_config {
-+	u32	header;
-+	u8	name[8];
-+	char	version[4];
-+	u8	serial[12];
-+	u8	opt[32];
-+};
-+
-+/*
-+* EVM Config held in daughter board eeprom device.
-+*
-+* Header Format
-+*
-+*  Name			Size		Contents
-+*			(Bytes)
-+*-------------------------------------------------------------
-+*  Header		4	0xAA, 0x55, 0x33, 0xEE
-+*
-+*  Board Name		8	Name for board in ASCII.
-+*				example "A335GPBD" = "AM335x
-+*				General Purpose Daughterboard"
-+*
-+*  Version		4	Hardware version code for board in
-+*				in ASCII. "1.0A" = rev.01.0A
-+*  Serial Number	12	Serial number of the board. This is a 12
-+*				character string which is: WWYY4P13nnnn, where
-+*				WW = 2 digit week of the year of production
-+*				YY = 2 digit year of production
-+*				nnnn = incrementing board number
-+*  Configuration Option	32	Codes to show the configuration
-+*				setup on this board.
-+*  CPLD Version	8		CPLD code version for board in ASCII
-+*				"CPLD1.0A" = rev. 01.0A of the CPLD
-+*  Available	32700		Available space for other non-volatile
-+*				codes/data
-+*/
-+
-+struct am335x_eeprom_config1 {
-+	u32	header;
-+	u8	name[8];
-+	char	version[4];
-+	u8	serial[12];
-+	u8	opt[32];
-+	u8	cpld_ver[8];
-+};
-+
-+static struct am335x_evm_eeprom_config config;
-+static struct am335x_eeprom_config1 config1;
-+static bool daughter_brd_detected;
-+
-+struct beaglebone_cape_eeprom_config {
-+	u32	header;
-+	char  format_revision[2];
-+	char	name[32];
-+	char	version[4];
-+	char	manufacturer[16];
-+	char	partnumber[16];
-+	u16  numpins;
-+	char	serial[12];
-+	u8	muxdata[170];
-+	u16  current_3v3;
-+	u16  current_vdd5v;
-+	u16  current_sys5v;
-+	u16  dc;
-+};
-+
-+static struct beaglebone_cape_eeprom_config cape_config;
-+static bool beaglebone_cape_detected;
-+
-+/* keep track of ADC pin usage */
-+static int capecount = 0;
-+static bool beaglebone_tsadcpins_free = 1;
-+
-+
-+#define GP_EVM_REV_IS_1_0		0x1
-+#define GP_EVM_REV_IS_1_0A		0x1
-+#define GP_EVM_REV_IS_1_1A		0x2
-+#define GP_EVM_REV_IS_UNKNOWN		0xFF
-+#define GP_EVM_ACTUALLY_BEAGLEBONE  0xBB
-+static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
-+
-+unsigned int gigabit_enable = 1;
-+
-+#define EEPROM_MAC_ADDRESS_OFFSET	60 /* 4+8+4+12+32 */
-+#define EEPROM_NO_OF_MAC_ADDR		3
-+static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
-+
-+#define AM335X_EEPROM_HEADER		0xEE3355AA
-+
-+/* current profile if exists else PROFILE_0 on error */
-+static u32 am335x_get_profile_selection(void)
-+{
-+	int val = 0;
-+
-+	if (!cpld_client)
-+		/* error checking is not done in func's calling this routine.
-+		so return profile 0 on error */
-+		return 0;
-+
-+	val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
-+	if (val < 0)
-+		return 0;	/* default to Profile 0 on Error */
-+	else
-+		return val & 0x7;
-+}
-+
-+static struct pinmux_config haptics_pin_mux[] = {
-+	{"gpmc_ad9.ehrpwm2B",		OMAP_MUX_MODE4 |
-+		AM33XX_PIN_OUTPUT},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for LCDC */
-+static struct pinmux_config lcdc_pin_mux[] = {
-+	{"lcd_data0.lcd_data0",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data1.lcd_data1",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data2.lcd_data2",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data3.lcd_data3",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data4.lcd_data4",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data5.lcd_data5",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data6.lcd_data6",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data7.lcd_data7",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data8.lcd_data8",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data9.lcd_data9",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data10.lcd_data10",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data11.lcd_data11",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data12.lcd_data12",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data13.lcd_data13",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data14.lcd_data14",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"lcd_data15.lcd_data15",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+						       | AM33XX_PULL_DISA},
-+	{"gpmc_ad8.lcd_data16",		OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_ad9.lcd_data17",		OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_ad10.lcd_data18",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_ad11.lcd_data19",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_ad12.lcd_data20",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_ad13.lcd_data21",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_ad14.lcd_data22",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_ad15.lcd_data23",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"lcd_vsync.lcd_vsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"lcd_hsync.lcd_hsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"lcd_pclk.lcd_pclk",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for Beagleboardtoys DVI cape */
-+static struct pinmux_config dvi_pin_mux[] = {
-+	{"lcd_data0.lcd_data0",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data1.lcd_data1",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data2.lcd_data2",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data3.lcd_data3",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data4.lcd_data4",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data5.lcd_data5",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data6.lcd_data6",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data7.lcd_data7",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data8.lcd_data8",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data9.lcd_data9",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data10.lcd_data10",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data11.lcd_data11",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data12.lcd_data12",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data13.lcd_data13",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data14.lcd_data14",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_data15.lcd_data15",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+        | AM33XX_PULL_DISA},
-+	{"lcd_vsync.lcd_vsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"lcd_hsync.lcd_hsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"lcd_pclk.lcd_pclk",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, // USR0 LED
-+	{"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, // USR1 LED
-+	{"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, // DVI PDn
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for Beagleboardtoys 7" LCD cape */
-+static struct pinmux_config bbtoys7_pin_mux[] = {
-+	{"lcd_data0.lcd_data0",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data1.lcd_data1",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data2.lcd_data2",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data3.lcd_data3",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data4.lcd_data4",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data5.lcd_data5",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data6.lcd_data6",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data7.lcd_data7",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data8.lcd_data8",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data9.lcd_data9",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data10.lcd_data10",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data11.lcd_data11",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data12.lcd_data12",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data13.lcd_data13",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data14.lcd_data14",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_data15.lcd_data15",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
-+		| AM33XX_PULL_DISA},
-+	{"lcd_vsync.lcd_vsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"lcd_hsync.lcd_hsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"lcd_pclk.lcd_pclk",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"ecap0_in_pwm0_out.gpio0_7", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, // AVDD_EN
-+	{"gpmc_a2.ehrpwm1A", OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT}, // Backlight
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config w1_gpio_pin_mux[] = {
-+	{"gpmc_ad3.gpio1_3",	OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config tsc_pin_mux[] = {
-+	{"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{"ain4.ain4",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{"ain5.ain5",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{"ain6.ain6",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{"ain7.ain7",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
-+	{NULL, 0},
-+};
-+
-+/* Pin mux for nand flash module */
-+static struct pinmux_config nand_pin_mux[] = {
-+	{"gpmc_ad0.gpmc_ad0",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad1.gpmc_ad1",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad2.gpmc_ad2",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad3.gpmc_ad3",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad4.gpmc_ad4",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad5.gpmc_ad5",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad6.gpmc_ad6",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad7.gpmc_ad7",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_wpn.gpmc_wpn",	  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_csn0.gpmc_csn0",	  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
-+	{"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
-+	{"gpmc_oen_ren.gpmc_oen_ren",	 OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
-+	{"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
-+	{"gpmc_ben0_cle.gpmc_ben0_cle",	 OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for SPI fash */
-+static struct pinmux_config spi0_pin_mux[] = {
-+	{"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
-+							| AM33XX_INPUT_EN},
-+	{"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
-+							| AM33XX_INPUT_EN},
-+	{"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
-+							| AM33XX_INPUT_EN},
-+	{"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
-+							| AM33XX_INPUT_EN},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for SPI flash */
-+static struct pinmux_config spi1_pin_mux[] = {
-+	{"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
-+		| AM33XX_INPUT_EN},
-+	{"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
-+		| AM33XX_PULL_UP | AM33XX_INPUT_EN},
-+	{"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
-+		| AM33XX_INPUT_EN},
-+	{"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
-+		| AM33XX_PULL_UP | AM33XX_INPUT_EN},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for rgmii1 */
-+static struct pinmux_config rgmii1_pin_mux[] = {
-+	{"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for rgmii2 */
-+static struct pinmux_config rgmii2_pin_mux[] = {
-+	{"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for mii1 */
-+static struct pinmux_config mii1_pin_mux[] = {
-+	{"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for rmii1 */
-+static struct pinmux_config rmii1_pin_mux[] = {
-+	{"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
-+	{"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config i2c1_pin_mux[] = {
-+	{"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
-+					AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
-+	{"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
-+					AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config i2c2_pin_mux[] = {
-+	{"uart1_ctsn.i2c2_sda",    OMAP_MUX_MODE3 | AM33XX_SLEWCTRL_SLOW |
-+					AM33XX_PIN_INPUT_PULLUP},
-+	{"uart1_rtsn.i2c2_scl",   OMAP_MUX_MODE3 | AM33XX_SLEWCTRL_SLOW |
-+					AM33XX_PIN_INPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for mcasp1 */
-+static struct pinmux_config mcasp1_pin_mux[] = {
-+	{"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
-+						AM33XX_PIN_INPUT_PULLDOWN},
-+	{NULL, 0},
-+};
-+
-+
-+/* Module pin mux for mmc0 */
-+static struct pinmux_config mmc0_pin_mux[] = {
-+	{"mmc0_dat3.mmc0_dat3",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_dat2.mmc0_dat2",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_dat1.mmc0_dat1",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_dat0.mmc0_dat0",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_clk.mmc0_clk",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_cmd.mmc0_cmd",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
-+	{"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config mmc0_no_cd_pin_mux[] = {
-+	{"mmc0_dat3.mmc0_dat3",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_dat2.mmc0_dat2",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_dat1.mmc0_dat1",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_dat0.mmc0_dat0",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_clk.mmc0_clk",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mmc0_cmd.mmc0_cmd",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for mmc1 */
-+static struct pinmux_config mmc1_pin_mux[] = {
-+	{"gpmc_ad7.mmc1_dat7",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad6.mmc1_dat6",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad5.mmc1_dat5",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad4.mmc1_dat4",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad3.mmc1_dat3",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad2.mmc1_dat2",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad1.mmc1_dat1",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ad0.mmc1_dat0",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_csn1.mmc1_clk",	OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_csn2.mmc1_cmd",	OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_csn0.gpio1_29",	OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for uart3 */
-+static struct pinmux_config uart3_pin_mux[] = {
-+	{"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
-+	{"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config d_can_gp_pin_mux[] = {
-+	{"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
-+	{"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config d_can_ia_pin_mux[] = {
-+	{"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
-+	{"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config tt3201_pin_mux[] = {
-+	{"uart1_rxd.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT },
-+	{"uart1_txd.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP },
-+	{"mcasp0_fsr.gpio3_19", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP },
-+	{"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP },
-+	{"ecap0_in_pwm0_out.spi1_cs1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT_PULLUP },
-+	{NULL, 0},
-+};
-+
-+/* Module pin mux for uart2 */
-+static struct pinmux_config uart2_pin_mux[] = {
-+	{"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
-+						AM33XX_PIN_INPUT_PULLUP},
-+	{"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
-+						AM33XX_PULL_DISA |
-+						AM33XX_SLEWCTRL_SLOW},
-+	{NULL, 0},
-+};
-+
-+
-+/*
-+* @pin_mux - single module pin-mux structure which defines pin-mux
-+*			details for all its pins.
-+*/
-+static void setup_pin_mux(struct pinmux_config *pin_mux)
-+{
-+	int i;
-+
-+	for (i = 0; pin_mux->string_name != NULL; pin_mux++)
-+		omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
-+
-+}
-+
-+/* Matrix GPIO Keypad Support for profile-0 only: TODO */
-+
-+/* pinmux for keypad device */
-+static struct pinmux_config matrix_keypad_pin_mux[] = {
-+	{"gpmc_a5.gpio1_21",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_a6.gpio1_22",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+	{"gpmc_a9.gpio1_25",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{NULL, 0},
-+};
-+
-+/* Keys mapping */
-+static const uint32_t am335x_evm_matrix_keys[] = {
-+	KEY(0, 0, KEY_MENU),
-+	KEY(1, 0, KEY_BACK),
-+	KEY(2, 0, KEY_LEFT),
-+
-+	KEY(0, 1, KEY_RIGHT),
-+	KEY(1, 1, KEY_ENTER),
-+	KEY(2, 1, KEY_DOWN),
-+};
-+
-+const struct matrix_keymap_data am335x_evm_keymap_data = {
-+	.keymap      = am335x_evm_matrix_keys,
-+	.keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
-+};
-+
-+static const unsigned int am335x_evm_keypad_row_gpios[] = {
-+	GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
-+};
-+
-+static const unsigned int am335x_evm_keypad_col_gpios[] = {
-+	GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
-+};
-+
-+static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
-+	.keymap_data       = &am335x_evm_keymap_data,
-+	.row_gpios         = am335x_evm_keypad_row_gpios,
-+	.num_row_gpios     = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
-+	.col_gpios         = am335x_evm_keypad_col_gpios,
-+	.num_col_gpios     = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
-+	.active_low        = false,
-+	.debounce_ms       = 5,
-+	.col_scan_delay_us = 2,
-+};
-+
-+static struct platform_device am335x_evm_keyboard = {
-+	.name  = "matrix-keypad",
-+	.id    = -1,
-+	.dev   = {
-+		.platform_data = &am335x_evm_keypad_platform_data,
-+	},
-+};
-+
-+static void matrix_keypad_init(int evm_id, int profile)
-+{
-+	int err;
-+
-+	setup_pin_mux(matrix_keypad_pin_mux);
-+	err = platform_device_register(&am335x_evm_keyboard);
-+	if (err) {
-+		pr_err("failed to register matrix keypad (2x3) device\n");
-+	}
-+}
-+
-+
-+/* pinmux for keypad device */
-+static struct pinmux_config volume_keys_pin_mux[] = {
-+	{"spi0_sclk.gpio0_2",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"spi0_d0.gpio0_3",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{NULL, 0},
-+};
-+
-+/* Configure GPIOs for Volume Keys */
-+static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
-+	{
-+		.code                   = KEY_VOLUMEUP,
-+		.gpio                   = GPIO_TO_PIN(0, 2),
-+		.active_low             = true,
-+		.desc                   = "volume-up",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+	{
-+		.code                   = KEY_VOLUMEDOWN,
-+		.gpio                   = GPIO_TO_PIN(0, 3),
-+		.active_low             = true,
-+		.desc                   = "volume-down",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+};
-+
-+static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
-+	.buttons        = am335x_evm_volume_gpio_buttons,
-+	.nbuttons       = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
-+};
-+
-+static struct platform_device am335x_evm_volume_keys = {
-+	.name   = "gpio-keys",
-+	.id     = -1,
-+	.dev    = {
-+		.platform_data  = &am335x_evm_volume_gpio_key_info,
-+	},
-+};
-+
-+static void volume_keys_init(int evm_id, int profile)
-+{
-+	int err;
-+
-+	setup_pin_mux(volume_keys_pin_mux);
-+	err = platform_device_register(&am335x_evm_volume_keys);
-+	if (err)
-+		pr_err("failed to register matrix keypad (2x3) device\n");
-+}
-+
-+/* pinmux for lcd7 keys */
-+static struct pinmux_config lcd7_keys_pin_mux[] = {
-+	{"gpmc_a0.gpio1_16",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"gpmc_a1.gpio1_17",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"gpmc_a3.gpio1_19",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"mcasp0_axr0.gpio3_16",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"mcasp0_fsr.gpio3_19",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{NULL, 0},
-+};
-+
-+/* Configure GPIOs for lcd7 keys */
-+static struct gpio_keys_button beaglebone_lcd7_gpio_keys[] = {
-+	{
-+		.code                   = KEY_LEFT,
-+		.gpio                   = GPIO_TO_PIN(1, 16),
-+		.active_low             = true,
-+		.desc                   = "left",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+	{
-+		.code                   = KEY_RIGHT,
-+		.gpio                   = GPIO_TO_PIN(1, 17),
-+		.active_low             = true,
-+		.desc                   = "right",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+	{
-+		.code                   = KEY_UP,
-+		.gpio                   = GPIO_TO_PIN(1, 19),
-+		.active_low             = true,
-+		.desc                   = "up",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+	{
-+		.code                   = KEY_DOWN,
-+		.gpio                   = GPIO_TO_PIN(3, 16),
-+		.active_low             = true,
-+		.desc                   = "down",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+	{
-+		.code                   = KEY_ENTER,
-+		.gpio                   = GPIO_TO_PIN(3, 19),
-+		.active_low             = true,
-+		.desc                   = "enter",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+};
-+
-+static struct gpio_keys_platform_data beaglebone_lcd7_gpio_key_info = {
-+	.buttons        = beaglebone_lcd7_gpio_keys,
-+	.nbuttons       = ARRAY_SIZE(beaglebone_lcd7_gpio_keys),
-+};
-+
-+static struct platform_device beaglebone_lcd7_keys = {
-+	.name   = "gpio-keys",
-+	.id     = -1,
-+	.dev    = {
-+		.platform_data  = &beaglebone_lcd7_gpio_key_info,
-+	},
-+};
-+
-+static void beaglebone_lcd7_keys_init(int evm_id, int profile)
-+{
-+	int err;
-+	setup_pin_mux(lcd7_keys_pin_mux);
-+	err = platform_device_register(&beaglebone_lcd7_keys);
-+	if (err)
-+		pr_err("failed to register gpio keys for LCD7 cape\n");
-+}
-+
-+/* pinmux for lcd3 keys */
-+static struct pinmux_config lcd3_keys_pin_mux[] = {
-+	{"gpmc_a0.gpio1_16",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"gpmc_a1.gpio1_17",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"mcasp0_fsr.gpio3_19",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"gpmc_ben1.gpio1_28",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"ecap0_in_pwm0_out.gpio0_7",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{NULL, 0},
-+};
-+
-+/* Configure GPIOs for lcd3 keys */
-+static struct gpio_keys_button beaglebone_lcd3_gpio_keys[] = {
-+	{
-+		.code                   = KEY_LEFT,
-+		.gpio                   = GPIO_TO_PIN(1, 16),
-+		.active_low             = true,
-+		.desc                   = "left",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+	{
-+		.code                   = KEY_RIGHT,
-+		.gpio                   = GPIO_TO_PIN(1, 17),
-+		.active_low             = true,
-+		.desc                   = "right",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+	{
-+		.code                   = KEY_UP,
-+		.gpio                   = GPIO_TO_PIN(3, 19),
-+		.active_low             = true,
-+		.desc                   = "up",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+	{
-+		.code                   = KEY_DOWN,
-+		.gpio                   = GPIO_TO_PIN(1, 28),
-+		.active_low             = true,
-+		.desc                   = "down",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+	{
-+		.code                   = KEY_ENTER,
-+		.gpio                   = GPIO_TO_PIN(0, 7),
-+		.active_low             = true,
-+		.desc                   = "down",
-+		.type                   = EV_KEY,
-+		.wakeup                 = 1,
-+	},
-+};
-+
-+static struct gpio_keys_platform_data beaglebone_lcd3_gpio_key_info = {
-+	.buttons        = beaglebone_lcd3_gpio_keys,
-+	.nbuttons       = ARRAY_SIZE(beaglebone_lcd3_gpio_keys),
-+};
-+
-+static struct platform_device beaglebone_lcd3_keys = {
-+	.name   = "gpio-keys",
-+	.id     = -1,
-+	.dev    = {
-+		.platform_data  = &beaglebone_lcd3_gpio_key_info,
-+	},
-+};
-+
-+static void beaglebone_lcd3_keys_init(int evm_id, int profile)
-+{
-+	int err;
-+	setup_pin_mux(lcd3_keys_pin_mux);
-+	err = platform_device_register(&beaglebone_lcd3_keys);
-+	if (err)
-+		pr_err("failed to register gpio keys for LCD3 cape\n");
-+}
-+
-+/*
-+* @evm_id - evm id which needs to be configured
-+* @dev_cfg - single evm structure which includes
-+*				all module inits, pin-mux defines
-+* @profile - if present, else PROFILE_NONE
-+* @dghtr_brd_flg - Whether Daughter board is present or not
-+*/
-+static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
-+	int profile)
-+{
-+	int i;
-+
-+	/*
-+	* Only General Purpose & Industrial Auto Motro Control
-+	* EVM has profiles. So check if this evm has profile.
-+	* If not, ignore the profile comparison
-+	*/
-+
-+	/*
-+	* If the device is on baseboard, directly configure it. Else (device on
-+	* Daughter board), check if the daughter card is detected.
-+	*/
-+	if (profile == PROFILE_NONE) {
-+		for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
-+			if (dev_cfg->device_on == DEV_ON_BASEBOARD)
-+				dev_cfg->device_init(evm_id, profile);
-+			else if (daughter_brd_detected == true)
-+				dev_cfg->device_init(evm_id, profile);
-+		}
-+	} else {
-+		for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
-+			if (dev_cfg->profile & profile) {
-+				if (dev_cfg->device_on == DEV_ON_BASEBOARD)
-+					dev_cfg->device_init(evm_id, profile);
-+				else if (daughter_brd_detected == true)
-+					dev_cfg->device_init(evm_id, profile);
-+			}
-+		}
-+	}
-+}
-+
-+
-+/* pinmux for usb0 drvvbus */
-+static struct pinmux_config usb0_pin_mux[] = {
-+	{"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{NULL, 0},
-+};
-+
-+/* pinmux for usb1 drvvbus */
-+static struct pinmux_config usb1_pin_mux[] = {
-+	{"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{NULL, 0},
-+};
-+
-+/* pinmux for profibus */
-+static struct pinmux_config profibus_pin_mux[] = {
-+	{"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
-+	{"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
-+	{"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
-+	{NULL, 0},
-+};
-+
-+#define BEAGLEBONE_W1_GPIO GPIO_TO_PIN(1, 3)
-+
-+static struct w1_gpio_platform_data bone_w1_gpio_pdata = {
-+	.pin		= BEAGLEBONE_W1_GPIO,
-+	.is_open_drain	= 0,
-+};
-+
-+static struct platform_device bone_w1_device = {
-+	.name			= "w1-gpio",
-+	.id			= -1,
-+	.dev.platform_data	= &bone_w1_gpio_pdata,
-+};
-+
-+/* LEDS - gpio1_21 -> gpio1_24 */
-+
-+#define BEAGLEBONE_USR1_LED  GPIO_TO_PIN(1, 21)
-+#define BEAGLEBONE_USR2_LED  GPIO_TO_PIN(1, 22)
-+#define BEAGLEBONE_USR3_LED  GPIO_TO_PIN(1, 23)
-+#define BEAGLEBONE_USR4_LED  GPIO_TO_PIN(1, 24)
-+
-+static struct gpio_led bone_gpio_leds[] = {
-+	{
-+		.name			= "beaglebone::usr0",
-+		.default_trigger	= "heartbeat",
-+		.gpio			= BEAGLEBONE_USR1_LED,
-+	},
-+	{
-+		.name			= "beaglebone::usr1",
-+		.default_trigger	= "mmc0",
-+		.gpio			= BEAGLEBONE_USR2_LED,
-+	},
-+	{
-+		.name			= "beaglebone::usr2",
-+		.gpio			= BEAGLEBONE_USR3_LED,
-+	},
-+	{
-+		.name           = "beaglebone::usr3",
-+		.gpio           = BEAGLEBONE_USR4_LED,
-+	},
-+};
-+
-+static struct gpio_led_platform_data bone_gpio_led_info = {
-+	.leds		= bone_gpio_leds,
-+	.num_leds	= ARRAY_SIZE(bone_gpio_leds),
-+};
-+
-+static struct platform_device bone_leds_gpio = {
-+	.name	= "leds-gpio",
-+	.id	= -1,
-+	.dev	= {
-+		.platform_data	= &bone_gpio_led_info,
-+	},
-+};
-+
-+
-+#define BEAGLEBONEDVI_USR0_LED  GPIO_TO_PIN(1, 18)
-+#define BEAGLEBONEDVI_USR1_LED  GPIO_TO_PIN(1, 19)
-+
-+static struct gpio_led dvi_gpio_leds[] = {
-+	{
-+		.name			= "beaglebone::usr0",
-+		.default_trigger	= "heartbeat",
-+		.gpio			= BEAGLEBONE_USR1_LED,
-+	},
-+	{
-+		.name			= "beaglebone::usr1",
-+		.default_trigger	= "mmc0",
-+		.gpio			= BEAGLEBONE_USR2_LED,
-+	},
-+	{
-+		.name			= "beaglebone::usr2",
-+		.gpio			= BEAGLEBONE_USR3_LED,
-+	},
-+	{
-+		.name           = "beaglebone::usr3",
-+		.gpio           = BEAGLEBONE_USR4_LED,
-+	},
-+	{
-+		.name			= "dvi::usr0",
-+		.default_trigger	= "heartbeat",
-+		.gpio			= BEAGLEBONEDVI_USR0_LED,
-+	},
-+	{
-+		.name			= "dvi::usr1",
-+		.default_trigger	= "mmc0",
-+		.gpio			= BEAGLEBONEDVI_USR1_LED,
-+	},
-+};
-+
-+static struct gpio_led_platform_data dvi_gpio_led_info = {
-+	.leds		= dvi_gpio_leds,
-+	.num_leds	= ARRAY_SIZE(dvi_gpio_leds),
-+};
-+
-+static struct platform_device dvi_leds_gpio = {
-+	.name	= "leds-gpio",
-+	.id	= -1,
-+	.dev	= {
-+		.platform_data	= &dvi_gpio_led_info,
-+	},
-+};
-+
-+static struct pinmux_config bone_pin_mux[] = {
-+	/* User LED gpios (gpio1_21 to gpio1_24) */
-+    {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+    {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+    {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+    {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+    /* Grounding gpio1_6 (pin 3 Conn A) signals bone tester to start diag tests */
-+    {"gpmc_ad6.gpio1_6", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
-+};
-+
-+/* Module pin mux for eCAP0 */
-+static struct pinmux_config ecap0_pin_mux[] = {
-+	{"ecap0_in_pwm0_out.ecap0_in_pwm0_out",
-+		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{NULL, 0},
-+};
-+
-+static int ehrpwm_backlight_enable;
-+static int backlight_enable;
-+
-+#define AM335XEVM_WLAN_PMENA_GPIO	GPIO_TO_PIN(1, 30)
-+#define AM335XEVM_WLAN_IRQ_GPIO		GPIO_TO_PIN(3, 17)
-+
-+struct wl12xx_platform_data am335xevm_wlan_data = {
-+	.irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
-+	.board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
-+};
-+
-+/* Module pin mux for wlan and bluetooth */
-+static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
-+	{"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
-+	{"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config uart1_wl12xx_pin_mux[] = {
-+	{"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
-+	{"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
-+	{"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-+	{"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
-+	{NULL, 0},
-+};
-+
-+static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
-+	{"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+	{"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+	{NULL, 0},
-+ };
-+
-+static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
-+	{"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+	{"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-+	{"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-+	{NULL, 0},
-+ };
-+
-+static void enable_ecap0(int evm_id, int profile)
-+{
-+	backlight_enable = true;
-+	setup_pin_mux(ecap0_pin_mux);
-+}
-+
-+/* Setup pwm-backlight */
-+static struct platform_device am335x_backlight = {
-+	.name           = "pwm-backlight",
-+	.id             = -1,
-+	.dev            = {
-+		.platform_data  = &am335x_backlight_data,
-+	}
-+};
-+
-+static struct pwmss_platform_data  pwm_pdata[3] = {
-+	{
-+		.version = PWM_VERSION_1,
-+	},
-+	{
-+		.version = PWM_VERSION_1,
-+	},
-+	{
-+		.version = PWM_VERSION_1,
-+	},
-+};
-+
-+static int __init ecap0_init(void)
-+{
-+	int status = 0;
-+
-+	if (backlight_enable) {
-+		am33xx_register_ecap(0, &pwm_pdata[0]);
-+		platform_device_register(&am335x_backlight);
-+	}
-+	return status;
-+}
-+late_initcall(ecap0_init);
-+
-+static void enable_ehrpwm1(int evm_id, int profile)
-+{
-+	ehrpwm_backlight_enable = true;
-+	am33xx_register_ehrpwm(1, &pwm_pdata[1]);
-+}
-+
-+/* Setup pwm-backlight for bbtoys7lcd */
-+static struct platform_device bbtoys7lcd_backlight = {
-+	.name           = "pwm-backlight",
-+	.id             = -1,
-+	.dev            = {
-+		.platform_data  = &bbtoys7lcd_backlight_data,
-+	}
-+};
-+
-+static int __init ehrpwm1_init(void)
-+{
-+	int status = 0;
-+	if (ehrpwm_backlight_enable) {
-+		platform_device_register(&bbtoys7lcd_backlight);
-+	}
-+	return status;
-+}
-+late_initcall(ehrpwm1_init);
-+
-+static int __init conf_disp_pll(int rate)
-+{
-+	struct clk *disp_pll;
-+	int ret = -EINVAL;
-+
-+	disp_pll = clk_get(NULL, "dpll_disp_ck");
-+	if (IS_ERR(disp_pll)) {
-+		pr_err("Cannot clk_get disp_pll\n");
-+		goto out;
-+	}
-+
-+	ret = clk_set_rate(disp_pll, rate);
-+	clk_put(disp_pll);
-+out:
-+	return ret;
-+}
-+
-+static void lcdc_init(int evm_id, int profile)
-+{
-+
-+	setup_pin_mux(lcdc_pin_mux);
-+
-+	if (conf_disp_pll(300000000)) {
-+		pr_info("Failed configure display PLL, not attempting to"
-+				"register LCDC\n");
-+		return;
-+	}
-+
-+	if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
-+		pr_info("Failed to register LCDC device\n");
-+	return;
-+}
-+
-+#define BEAGLEBONE_LCD_AVDD_EN GPIO_TO_PIN(0, 7)
-+
-+static void bbtoys7lcd_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(bbtoys7_pin_mux);
-+	gpio_request(BEAGLEBONE_LCD_AVDD_EN, "BONE_LCD_AVDD_EN");
-+	gpio_direction_output(BEAGLEBONE_LCD_AVDD_EN, 1);
-+
-+	// we are being stupid and setting pixclock from here instead of da8xx-fb.c
-+	if (conf_disp_pll(300000000)) {
-+		pr_info("Failed to set pixclock to 300000000, not attempting to"
-+				"register LCD cape\n");
-+		return;
-+	}
-+	
-+	if (am33xx_register_lcdc(&bbtoys7_pdata))
-+		pr_info("Failed to register Beagleboardtoys 7\" LCD cape device\n");
-+		
-+	return;
-+}
-+
-+static void bbtoys35lcd_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(bbtoys7_pin_mux);
-+	
-+	// we are being stupid and setting pixclock from here instead of da8xx-fb.c
-+	if (conf_disp_pll(16000000)) {
-+		pr_info("Failed to set pixclock to 16000000, not attempting to"
-+				"register LCD cape\n");
-+		return;
-+	}
-+	
-+	if (am33xx_register_lcdc(&bbtoys35_pdata))
-+		pr_info("Failed to register Beagleboardtoys 3.5\" LCD cape device\n");
-+	
-+	return;
-+}
-+
-+#define BEAGLEBONEDVI_PDn  GPIO_TO_PIN(1, 7)
-+
-+static void dvi_init(int evm_id, int profile)
-+{
-+    setup_pin_mux(dvi_pin_mux);
-+	gpio_request(BEAGLEBONEDVI_PDn, "DVI_PDn");
-+	gpio_direction_output(BEAGLEBONEDVI_PDn, 1);
-+
-+	// we are being stupid and setting pixclock from here instead of da8xx-fb.c
-+	if (conf_disp_pll(560000000)) {
-+		pr_info("Failed to set pixclock to 56000000, not attempting to"
-+				"register DVI adapter\n");
-+		return;
-+	}
-+	
-+	if (am33xx_register_lcdc(&dvi_pdata))
-+		pr_info("Failed to register BeagleBoardToys DVI cape\n");
-+	return;
-+}
-+
-+static void tsc_init(int evm_id, int profile)
-+{
-+	int err;
-+
-+	if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
-+		am335x_touchscreen_data.analog_input = 1;
-+		pr_info("TSC connected to beta GP EVM\n");
-+	}
-+	if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
-+		am335x_touchscreen_data.analog_input = 0;
-+		pr_info("TSC connected to alpha GP EVM\n");
-+	}
-+	if( gp_evm_revision == GP_EVM_ACTUALLY_BEAGLEBONE) {
-+		am335x_touchscreen_data.analog_input = 1;
-+		pr_info("TSC connected to BeagleBone\n");;	
-+	}
-+	setup_pin_mux(tsc_pin_mux);
-+
-+	err = am33xx_register_tsc(&am335x_touchscreen_data);
-+	if (err)
-+		pr_err("failed to register touchscreen device\n");
-+}
-+
-+static void bone_tsc_init(int evm_id, int profile)
-+{
-+	int err;
-+	setup_pin_mux(tsc_pin_mux);
-+	err = am33xx_register_tsc(&bone_touchscreen_data);
-+	if (err)
-+		pr_err("failed to register touchscreen device\n");
-+}
-+
-+
-+static void boneleds_init(int evm_id, int profile )
-+{
-+	int err;
-+	setup_pin_mux(bone_pin_mux);
-+	err = platform_device_register(&bone_leds_gpio);
-+	if (err)
-+		pr_err("failed to register BeagleBone LEDS\n");
-+}
-+
-+static void dvileds_init(int evm_id, int profile )
-+{
-+	int err;
-+	err = platform_device_register(&dvi_leds_gpio);
-+	if (err)
-+		pr_err("failed to register BeagleBone DVI cape LEDS\n");
-+}
-+
-+static void bonew1_gpio_init(int evm_id, int profile )
-+{
-+	int err;
-+	setup_pin_mux(w1_gpio_pin_mux);
-+	err = platform_device_register(&bone_w1_device);
-+	if (err)
-+		pr_err("failed to register w1-gpio\n");
-+	else
-+		pr_info("w1-gpio connected to P8_6\n");
-+}
-+
-+static void rgmii1_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(rgmii1_pin_mux);
-+	return;
-+}
-+
-+static void rgmii2_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(rgmii2_pin_mux);
-+	return;
-+}
-+
-+static void mii1_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(mii1_pin_mux);
-+	return;
-+}
-+
-+static void rmii1_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(rmii1_pin_mux);
-+	return;
-+}
-+
-+static void usb0_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(usb0_pin_mux);
-+	return;
-+}
-+
-+static void usb1_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(usb1_pin_mux);
-+	return;
-+}
-+
-+/* setup uart3 */
-+static void uart3_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(uart3_pin_mux);
-+	return;
-+}
-+
-+/* setup uart2 */
-+static void uart2_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(uart2_pin_mux);
-+	return;
-+}
-+
-+/* setup haptics */
-+#define HAPTICS_MAX_FREQ 250
-+static void haptics_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(haptics_pin_mux);
-+	pwm_pdata[2].chan_attrib[1].max_freq = HAPTICS_MAX_FREQ;
-+	am33xx_register_ehrpwm(2, &pwm_pdata[2]);
-+}
-+
-+/* NAND partition information */
-+static struct mtd_partition am335x_nand_partitions[] = {
-+/* All the partition sizes are listed in terms of NAND block size */
-+	{
-+		.name           = "SPL",
-+		.offset         = 0,			/* Offset = 0x0 */
-+		.size           = SZ_128K,
-+	},
-+	{
-+		.name           = "SPL.backup1",
-+		.offset         = MTDPART_OFS_APPEND,	/* Offset = 0x20000 */
-+		.size           = SZ_128K,
-+	},
-+	{
-+		.name           = "SPL.backup2",
-+		.offset         = MTDPART_OFS_APPEND,	/* Offset = 0x40000 */
-+		.size           = SZ_128K,
-+	},
-+	{
-+		.name           = "SPL.backup3",
-+		.offset         = MTDPART_OFS_APPEND,	/* Offset = 0x60000 */
-+		.size           = SZ_128K,
-+	},
-+	{
-+		.name           = "U-Boot",
-+		.offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
-+		.size           = 15 * SZ_128K,
-+	},
-+	{
-+		.name           = "U-Boot Env",
-+		.offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
-+		.size           = 1 * SZ_128K,
-+	},
-+	{
-+		.name           = "Kernel",
-+		.offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
-+		.size           = 40 * SZ_128K,
-+	},
-+	{
-+		.name           = "File System",
-+		.offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
-+		.size           = MTDPART_SIZ_FULL,
-+	},
-+};
-+
-+/* SPI 0/1 Platform Data */
-+/* SPI flash information */
-+static struct mtd_partition am335x_spi_partitions[] = {
-+	/* All the partition sizes are listed in terms of erase size */
-+	{
-+		.name       = "SPL",
-+		.offset     = 0,			/* Offset = 0x0 */
-+		.size       = SZ_128K,
-+	},
-+	{
-+		.name       = "U-Boot",
-+		.offset     = MTDPART_OFS_APPEND,	/* Offset = 0x20000 */
-+		.size       = 2 * SZ_128K,
-+	},
-+	{
-+		.name       = "U-Boot Env",
-+		.offset     = MTDPART_OFS_APPEND,	/* Offset = 0x60000 */
-+		.size       = 2 * SZ_4K,
-+	},
-+	{
-+		.name       = "Kernel",
-+		.offset     = MTDPART_OFS_APPEND,	/* Offset = 0x62000 */
-+		.size       = 28 * SZ_128K,
-+	},
-+	{
-+		.name       = "File System",
-+		.offset     = MTDPART_OFS_APPEND,	/* Offset = 0x3E2000 */
-+		.size       = MTDPART_SIZ_FULL,		/* size ~= 4.1 MiB */
-+	}
-+};
-+
-+static const struct flash_platform_data am335x_spi_flash = {
-+	.type      = "w25q64",
-+	.name      = "spi_flash",
-+	.parts     = am335x_spi_partitions,
-+	.nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
-+};
-+
-+/*
-+ * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
-+ * So setup Max speed to be less than that of Controller speed
-+ */
-+static struct spi_board_info am335x_spi0_slave_info[] = {
-+	{
-+		.modalias      = "m25p80",
-+		.platform_data = &am335x_spi_flash,
-+		.irq           = -1,
-+		.max_speed_hz  = 24000000,
-+		.bus_num       = 1,
-+		.chip_select   = 0,
-+	},
-+};
-+
-+static struct spi_board_info am335x_spi1_slave_info[] = {
-+	{
-+		.modalias      = "m25p80",
-+		.platform_data = &am335x_spi_flash,
-+		.irq           = -1,
-+		.max_speed_hz  = 12000000,
-+		.bus_num       = 2,
-+		.chip_select   = 0,
-+	},
-+};
-+
-+static struct gpmc_timings am335x_nand_timings = {
-+	.sync_clk = 0,
-+
-+	.cs_on = 0,
-+	.cs_rd_off = 44,
-+	.cs_wr_off = 44,
-+
-+	.adv_on = 6,
-+	.adv_rd_off = 34,
-+	.adv_wr_off = 44,
-+	.we_off = 40,
-+	.oe_off = 54,
-+
-+	.access = 64,
-+	.rd_cycle = 82,
-+	.wr_cycle = 82,
-+
-+	.wr_access = 40,
-+	.wr_data_mux_bus = 0,
-+};
-+
-+static void evm_nand_init(int evm_id, int profile)
-+{
-+	struct omap_nand_platform_data *pdata;
-+	struct gpmc_devices_info gpmc_device[2] = {
-+		{ NULL, 0 },
-+		{ NULL, 0 },
-+	};
-+
-+	setup_pin_mux(nand_pin_mux);
-+	pdata = omap_nand_init(am335x_nand_partitions,
-+		ARRAY_SIZE(am335x_nand_partitions), 0, 0,
-+		&am335x_nand_timings);
-+	if (!pdata)
-+		return;
-+	pdata->ecc_opt =OMAP_ECC_BCH8_CODE_HW;
-+	pdata->elm_used = true;
-+	gpmc_device[0].pdata = pdata;
-+	gpmc_device[0].flag = GPMC_DEVICE_NAND;
-+
-+	omap_init_gpmc(gpmc_device, sizeof(gpmc_device));
-+	omap_init_elm();
-+}
-+
-+/* TPS65217 voltage regulator support */
-+
-+/* 1.8V */
-+static struct regulator_consumer_supply tps65217_dcdc1_consumers[] = {
-+	{
-+		.supply = "vdds_osc",
-+	},
-+	{
-+		.supply = "vdds_pll_ddr",
-+	},
-+	{
-+		.supply = "vdds_pll_mpu",
-+	},
-+	{
-+		.supply = "vdds_pll_core_lcd",
-+	},
-+	{
-+		.supply = "vdds_sram_mpu_bb",
-+	},
-+	{
-+		.supply = "vdds_sram_core_bg",
-+	},
-+	{
-+		.supply = "vdda_usb0_1p8v",
-+	},
-+	{
-+		.supply = "vdds_ddr",
-+	},
-+	{
-+		.supply = "vdds",
-+	},
-+	{
-+		.supply = "vdds_hvx_1p8v",
-+	},
-+	{
-+		.supply = "vdda_adc",
-+	},
-+	{
-+		.supply = "ddr2",
-+	},
-+};
-+
-+/* 1.1V */
-+static struct regulator_consumer_supply tps65217_dcdc2_consumers[] = {
-+	{
-+		.supply = "vdd_mpu",
-+	},
-+};
-+
-+/* 1.1V */
-+static struct regulator_consumer_supply tps65217_dcdc3_consumers[] = {
-+	{
-+		.supply = "vdd_core",
-+	},
-+};
-+
-+/* 1.8V LDO */
-+static struct regulator_consumer_supply tps65217_ldo1_consumers[] = {
-+	{
-+		.supply = "vdds_rtc",
-+	},
-+};
-+
-+/* 3.3V LDO */
-+static struct regulator_consumer_supply tps65217_ldo2_consumers[] = {
-+	{
-+		.supply = "vdds_any_pn",
-+	},
-+};
-+
-+/* 3.3V LDO */
-+static struct regulator_consumer_supply tps65217_ldo3_consumers[] = {
-+	{
-+		.supply = "vdds_hvx_ldo3_3p3v",
-+	},
-+	{
-+		.supply = "vdda_usb0_3p3v",
-+	},
-+};
-+
-+/* 3.3V LDO */
-+static struct regulator_consumer_supply tps65217_ldo4_consumers[] = {
-+	{
-+		.supply = "vdds_hvx_ldo4_3p3v",
-+	},
-+};
-+
-+static struct regulator_init_data tps65217_regulator_data[] = {
-+	/* dcdc1 */
-+	{
-+		.constraints = {
-+			.min_uV = 900000,
-+			.max_uV = 1800000,
-+			.boot_on = 1,
-+			.always_on = 1,
-+		},
-+		.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc1_consumers),
-+		.consumer_supplies = tps65217_dcdc1_consumers,
-+	},
-+
-+	/* dcdc2 */
-+	{
-+		.constraints = {
-+			.min_uV = 900000,
-+			.max_uV = 3300000,
-+			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
-+				REGULATOR_CHANGE_STATUS),
-+			.boot_on = 1,
-+			.always_on = 1,
-+		},
-+		.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc2_consumers),
-+		.consumer_supplies = tps65217_dcdc2_consumers,
-+	},
-+
-+	/* dcdc3 */
-+	{
-+		.constraints = {
-+			.min_uV = 900000,
-+			.max_uV = 1500000,
-+			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
-+				REGULATOR_CHANGE_STATUS),
-+			.boot_on = 1,
-+			.always_on = 1,
-+		},
-+		.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc3_consumers),
-+		.consumer_supplies = tps65217_dcdc3_consumers,
-+	},
-+
-+	/* ldo1 */
-+	{
-+		.constraints = {
-+			.min_uV = 1000000,
-+			.max_uV = 3300000,
-+			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
-+			.boot_on = 1,
-+			.always_on = 1,
-+		},
-+		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo1_consumers),
-+		.consumer_supplies = tps65217_ldo1_consumers,
-+	},
-+
-+	/* ldo2 */
-+	{
-+		.constraints = {
-+			.min_uV = 900000,
-+			.max_uV = 3300000,
-+			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
-+				REGULATOR_CHANGE_STATUS),
-+			.boot_on = 1,
-+			.always_on = 1,
-+		},
-+		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo2_consumers),
-+		.consumer_supplies = tps65217_ldo2_consumers,
-+	},
-+
-+	/* ldo3 */
-+	{
-+		.constraints = {
-+			.min_uV = 1800000,
-+			.max_uV = 3300000,
-+			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
-+				REGULATOR_CHANGE_STATUS),
-+			.boot_on = 1,
-+			.always_on = 1,
-+		},
-+		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo3_consumers),
-+		.consumer_supplies = tps65217_ldo3_consumers,
-+	},
-+
-+	/* ldo4 */
-+	{
-+		.constraints = {
-+			.min_uV = 1800000,
-+			.max_uV = 3300000,
-+			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
-+				REGULATOR_CHANGE_STATUS),
-+			.boot_on = 1,
-+			.always_on = 1,
-+		},
-+		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo4_consumers),
-+		.consumer_supplies = tps65217_ldo4_consumers,
-+	},
-+};
-+
-+static struct tps65217_board beaglebone_tps65217_info = {
-+	.tps65217_init_data = &tps65217_regulator_data[0],
-+};
-+
-+static struct lis3lv02d_platform_data lis331dlh_pdata = {
-+	.click_flags = LIS3_CLICK_SINGLE_X |
-+			LIS3_CLICK_SINGLE_Y |
-+			LIS3_CLICK_SINGLE_Z,
-+	.wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
-+			LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
-+			LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
-+	.irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
-+	.wakeup_thresh	= 10,
-+	.click_thresh_x = 10,
-+	.click_thresh_y = 10,
-+	.click_thresh_z = 10,
-+	.g_range	= 2,
-+	.st_min_limits[0] = 120,
-+	.st_min_limits[1] = 120,
-+	.st_min_limits[2] = 140,
-+	.st_max_limits[0] = 550,
-+	.st_max_limits[1] = 550,
-+	.st_max_limits[2] = 750,
-+};
-+
-+static struct i2c_board_info am335x_i2c_boardinfo1[] = {
-+	{
-+		I2C_BOARD_INFO("tlv320aic3x", 0x1b),
-+	},
-+	{
-+		I2C_BOARD_INFO("lis331dlh", 0x18),
-+		.platform_data = &lis331dlh_pdata,
-+	},
-+	{
-+		I2C_BOARD_INFO("tsl2550", 0x39),
-+	},
-+	{
-+		I2C_BOARD_INFO("tmp275", 0x48),
-+	},
-+};
-+
-+static void i2c1_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(i2c1_pin_mux);
-+	omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
-+			ARRAY_SIZE(am335x_i2c_boardinfo1));
-+	return;
-+}
-+
-+static struct mcp251x_platform_data mcp251x_info = {
-+	.oscillator_frequency = 16000000,
-+};
-+
-+static struct spi_board_info tt3201_spi_info[] = {
-+	{
-+		.modalias	= "mcp2515",
-+		.max_speed_hz	= 10000000,
-+		.bus_num	= 2,
-+		.chip_select	= 0,
-+		.mode		= SPI_MODE_0,
-+		.platform_data	= &mcp251x_info,
-+	},
-+	{
-+		.modalias	= "mcp2515",
-+		.max_speed_hz	= 10000000,
-+		.bus_num	= 2,
-+		.chip_select	= 1,
-+		.mode		= SPI_MODE_0,
-+		.platform_data	= &mcp251x_info,
-+	},
-+};
-+
-+static void tt3201_init(int evm_id, int profile)
-+{
-+	pr_info("TowerTech TT3201 CAN Cape\n");
-+
-+	setup_pin_mux(spi1_pin_mux);
-+	setup_pin_mux(tt3201_pin_mux);
-+
-+	tt3201_spi_info[0].irq = gpio_to_irq(GPIO_TO_PIN(3, 19));
-+	tt3201_spi_info[1].irq = gpio_to_irq(GPIO_TO_PIN(3, 21));
-+
-+	spi_register_board_info(tt3201_spi_info,
-+		ARRAY_SIZE(tt3201_spi_info));
-+
-+	am33xx_d_can_init(1);
-+}
-+static void beaglebone_cape_setup(struct memory_accessor *mem_acc, void *context)
-+{
-+	capecount++;
-+	int ret;
-+	char tmp[32];
-+	char name[32];
-+	char version[4];
-+	char manufacturer[32];
-+
-+	/* get cape specific data */
-+	ret = mem_acc->read(mem_acc, (char *)&cape_config, 0, sizeof(cape_config));
-+	if (ret != sizeof(cape_config)) {
-+		pr_warning("BeagleBone cape EEPROM: could not read eeprom at address 0x%x\n", capecount + 0x53);
-+		if ((capecount > 3) && (beaglebone_tsadcpins_free == 1)) {
-+			pr_info("BeagleBone cape: exporting ADC pins to sysfs\n");
-+			bone_tsc_init(0,0);
-+			beaglebone_tsadcpins_free = 0;
-+		}
-+		return;
-+	}
-+
-+	if (cape_config.header != AM335X_EEPROM_HEADER) {
-+		pr_warning("BeagleBone Cape EEPROM: wrong header 0x%x, expected 0x%x\n",
-+			cape_config.header, AM335X_EEPROM_HEADER);
-+		goto out;
-+	}
-+
-+	pr_info("BeagleBone cape EEPROM: found eeprom at address 0x%x\n", capecount + 0x53);
-+	snprintf(name, sizeof(cape_config.name) + 1, "%s", cape_config.name);
-+	snprintf(version, sizeof(cape_config.version) + 1, "%s", cape_config.version);
-+	snprintf(manufacturer, sizeof(cape_config.manufacturer) + 1, "%s", cape_config.manufacturer);
-+	pr_info("BeagleBone cape: %s %s, revision %s\n", manufacturer, name, version);
-+	snprintf(tmp, sizeof(cape_config.partnumber) + 1, "%s", cape_config.partnumber);
-+	pr_info("BeagleBone cape partnumber: %s\n", tmp);   
-+
-+	if (!strncmp("BB-BONE-DVID-01", cape_config.partnumber, 15)) {
-+			pr_info("BeagleBone cape: initializing DVI cape\n");
-+			dvi_init(0,0);
-+	}
-+	if (!strncmp("BB-BONE-LCD7-01", cape_config.partnumber, 15)) {
-+		pr_info("BeagleBone cape: initializing LCD cape\n");
-+		bbtoys7lcd_init(0,0);
-+		pr_info("BeagleBone cape: initializing LCD cape touchscreen\n");
-+		tsc_init(0,0);
-+		pr_info("BeagleBone cape: Registering PWM backlight for LCD cape\n");
-+		enable_ehrpwm1(0,0);
-+		beaglebone_tsadcpins_free = 0;
-+		pr_info("BeagleBone cape: Registering gpio-keys for LCD cape\n");
-+		beaglebone_lcd7_keys_init(0,0);
-+	}
-+	
-+	if (!strncmp("BB-BONE-LCD3-01", cape_config.partnumber, 15)) {
-+		pr_info("BeagleBone cape: initializing LCD cape\n");
-+		bbtoys35lcd_init(0,0);
-+		pr_info("BeagleBone cape: initializing LCD cape touchscreen\n");
-+		tsc_init(0,0);
-+		beaglebone_tsadcpins_free = 0;
-+		pr_info("BeagleBone cape: Registering gpio-keys for LCD cape\n");
-+		beaglebone_lcd3_keys_init(0,0);
-+	}
-+	
-+	if (!strncmp("BB-BONE-VGA-01", cape_config.partnumber, 14)) {
-+		pr_info("BeagleBone cape: initializing VGA cape\n");
-+		dvi_init(0,0);
-+	}
-+	
-+	if (!strncmp("BB-BONE-BATT-01", cape_config.partnumber, 15)) {
-+		pr_info("BeagleBone cape: initializing battery cape\n");
-+		// gpio1_6, P9_15 lowbat output
-+		// AIN4, P9_33 vbat
-+		//foo_init(0,0);
-+	}
-+	
-+	if (!strncmp("BB-BONE-SERL", cape_config.partnumber, 12)) {
-+		pr_info("BeagleBone cape: initializing serial cape\n");
-+		// 01 -> CAN
-+		// 02 -> Profibus
-+		// 03 -> RS232
-+		// 04 -> RS485
-+		//foo_init(0,0);
-+	}
-+	
-+	if (!strncmp("TT3201-001", cape_config.partnumber, 10)) {
-+		pr_info("BeagleBone cape: initializing CAN cape\n");
-+		tt3201_init(0,0);
-+	}
-+	
-+	if ((capecount > 3) && (beaglebone_tsadcpins_free == 1)) {
-+		pr_info("BeagleBone cape: exporting ADC pins to sysfs\n");
-+		bone_tsc_init(0,0);
-+		beaglebone_tsadcpins_free = 0;
-+	}
-+	
-+	return;
-+out:
-+	/*
-+	 * If the EEPROM hasn't been programed or an incorrect header
-+	 * or board name are read, assume this is an old beaglebone board
-+	 * (< Rev A3)
-+	 */
-+	pr_err("Could not detect BeagleBone cape properly\n");
-+	beaglebone_cape_detected = false;
-+
-+}
-+
-+static struct at24_platform_data cape_eeprom_info = {
-+        .byte_len       = (256*1024) / 8,
-+        .page_size      = 64,
-+        .flags          = AT24_FLAG_ADDR16,
-+        .context        = (void *)NULL,
-+		.setup		  = beaglebone_cape_setup,
-+};
-+
-+static struct i2c_board_info __initdata cape_i2c_boardinfo[] = {
-+        {
-+                I2C_BOARD_INFO("24c256", 0x54),
-+                .platform_data  = &cape_eeprom_info,
-+        },
-+        {
-+                I2C_BOARD_INFO("24c256", 0x55),
-+                .platform_data  = &cape_eeprom_info,
-+        },
-+        {
-+                I2C_BOARD_INFO("24c256", 0x56),
-+                .platform_data  = &cape_eeprom_info,
-+        },
-+        {
-+                I2C_BOARD_INFO("24c256", 0x57),
-+                .platform_data  = &cape_eeprom_info,
-+        },
-+};
-+
-+static void i2c2_init(int evm_id, int profile)
-+{
-+        setup_pin_mux(i2c2_pin_mux);
-+        omap_register_i2c_bus(3, 100, cape_i2c_boardinfo,
-+                        ARRAY_SIZE(cape_i2c_boardinfo));
-+        return;
-+}
-+
-+
-+/* Setup McASP 1 */
-+static void mcasp1_init(int evm_id, int profile)
-+{
-+	/* Configure McASP */
-+	setup_pin_mux(mcasp1_pin_mux);
-+	am335x_register_mcasp(&am335x_evm_snd_data1, 1);
-+	return;
-+}
-+
-+static void mmc1_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(mmc1_pin_mux);
-+
-+	am335x_mmc[1].mmc = 2;
-+	am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
-+	am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
-+	am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
-+	am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
-+
-+	/* mmc will be initialized when mmc0_init is called */
-+	return;
-+}
-+
-+static void mmc2_wl12xx_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(mmc2_wl12xx_pin_mux);
-+
-+	am335x_mmc[1].mmc = 3;
-+	am335x_mmc[1].name = "wl1271";
-+	am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
-+				| MMC_PM_KEEP_POWER;
-+	am335x_mmc[1].nonremovable = true;
-+	am335x_mmc[1].gpio_cd = -EINVAL;
-+	am335x_mmc[1].gpio_wp = -EINVAL;
-+	am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
-+
-+	/* mmc will be initialized when mmc0_init is called */
-+	return;
-+}
-+
-+static void uart1_wl12xx_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(uart1_wl12xx_pin_mux);
-+}
-+
-+static void wl12xx_bluetooth_enable(void)
-+{
-+	int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
-+		"bt_en\n");
-+	if (status < 0)
-+		pr_err("Failed to request gpio for bt_enable");
-+
-+	pr_info("Configure Bluetooth Enable pin...\n");
-+	gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
-+}
-+
-+static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
-+{
-+	if (on) {
-+		gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
-+		mdelay(70);
-+	}
-+	else
-+		gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
-+
-+	return 0;
-+}
-+
-+static void wl12xx_init(int evm_id, int profile)
-+{
-+	struct device *dev;
-+	struct omap_mmc_platform_data *pdata;
-+	int ret;
-+
-+	/* Register WLAN and BT enable pins based on the evm board revision */
-+	if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
-+		am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
-+		am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
-+	}
-+	else {
-+		am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
-+		am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
-+	}
-+
-+	wl12xx_bluetooth_enable();
-+
-+	if (wl12xx_set_platform_data(&am335xevm_wlan_data))
-+		pr_err("error setting wl12xx data\n");
-+
-+	dev = am335x_mmc[1].dev;
-+	if (!dev) {
-+		pr_err("wl12xx mmc device initialization failed\n");
-+		goto out;
-+	}
-+
-+	pdata = dev->platform_data;
-+	if (!pdata) {
-+		pr_err("Platfrom data of wl12xx device not set\n");
-+		goto out;
-+	}
-+
-+	ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
-+		GPIOF_OUT_INIT_LOW, "wlan_en");
-+	if (ret) {
-+		pr_err("Error requesting wlan enable gpio: %d\n", ret);
-+		goto out;
-+	}
-+
-+	if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
-+		setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
-+	else
-+		setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
-+
-+	pdata->slots[0].set_power = wl12xx_set_power;
-+out:
-+	return;
-+}
-+
-+static void d_can_init(int evm_id, int profile)
-+{
-+	switch (evm_id) {
-+	case IND_AUT_MTR_EVM:
-+		if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
-+			setup_pin_mux(d_can_ia_pin_mux);
-+			/* Instance Zero */
-+			am33xx_d_can_init(0);
-+		}
-+		break;
-+	case GEN_PURP_EVM:
-+		if (profile == PROFILE_1) {
-+			setup_pin_mux(d_can_gp_pin_mux);
-+			/* Instance One */
-+			am33xx_d_can_init(1);
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+static void mmc0_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(mmc0_pin_mux);
-+
-+	omap2_hsmmc_init(am335x_mmc);
-+	return;
-+}
-+
-+static struct i2c_board_info tps65217_i2c_boardinfo[] = {
-+	{
-+		I2C_BOARD_INFO("tps65217", TPS65217_I2C_ID),
-+		.platform_data  = &beaglebone_tps65217_info,
-+	},
-+};
-+
-+static void tps65217_init(int evm_id, int profile)
-+{
-+	struct i2c_adapter *adapter;
-+	struct i2c_client *client;
-+
-+	/* I2C1 adapter request */
-+	adapter = i2c_get_adapter(1);
-+	if (!adapter) {
-+		pr_err("failed to get adapter i2c1\n");
-+		return;
-+	}
-+
-+	client = i2c_new_device(adapter, tps65217_i2c_boardinfo);
-+	if (!client)
-+		pr_err("failed to register tps65217 to i2c1\n");
-+
-+	i2c_put_adapter(adapter);
-+}
-+
-+static void mmc0_no_cd_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(mmc0_no_cd_pin_mux);
-+
-+	omap2_hsmmc_init(am335x_mmc);
-+	return;
-+}
-+
-+
-+/* setup spi0 */
-+static void spi0_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(spi0_pin_mux);
-+	spi_register_board_info(am335x_spi0_slave_info,
-+			ARRAY_SIZE(am335x_spi0_slave_info));
-+	return;
-+}
-+
-+/* setup spi1 */
-+static void spi1_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(spi1_pin_mux);
-+	spi_register_board_info(am335x_spi1_slave_info,
-+			ARRAY_SIZE(am335x_spi1_slave_info));
-+	return;
-+}
-+
-+
-+static int beaglebone_phy_fixup(struct phy_device *phydev)
-+{
-+	phydev->supported &= ~(SUPPORTED_100baseT_Half |
-+				SUPPORTED_100baseT_Full);
-+
-+	return 0;
-+}
-+
-+#if defined(CONFIG_TLK110_WORKAROUND) || \
-+			defined(CONFIG_TLK110_WORKAROUND_MODULE)
-+static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
-+{
-+	unsigned int val;
-+
-+	/* This is done as a workaround to support TLK110 rev1.0 phy */
-+	val = phy_read(phydev, TLK110_COARSEGAIN_REG);
-+	phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
-+
-+	val = phy_read(phydev, TLK110_LPFHPF_REG);
-+	phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
-+
-+	val = phy_read(phydev, TLK110_SPAREANALOG_REG);
-+	phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
-+
-+	val = phy_read(phydev, TLK110_VRCR_REG);
-+	phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
-+
-+	val = phy_read(phydev, TLK110_SETFFE_REG);
-+	phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
-+
-+	val = phy_read(phydev, TLK110_FTSP_REG);
-+	phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
-+
-+	val = phy_read(phydev, TLK110_ALFATPIDL_REG);
-+	phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
-+
-+	val = phy_read(phydev, TLK110_PSCOEF21_REG);
-+	phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
-+
-+	val = phy_read(phydev, TLK110_PSCOEF3_REG);
-+	phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
-+
-+	val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
-+	phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
-+
-+	val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
-+	phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
-+
-+	val = phy_read(phydev, TLK110_CFGPS_REG);
-+	phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
-+
-+	val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
-+	phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
-+
-+	val = phy_read(phydev, TLK110_SWSCR3_REG);
-+	phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
-+
-+	val = phy_read(phydev, TLK110_SCFALLBACK_REG);
-+	phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
-+
-+	val = phy_read(phydev, TLK110_PHYRCR_REG);
-+	phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
-+
-+	return 0;
-+}
-+#endif
-+
-+static void profibus_init(int evm_id, int profile)
-+{
-+	setup_pin_mux(profibus_pin_mux);
-+	return;
-+}
-+
-+/* Low-Cost EVM */
-+static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
-+	{rgmii1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{NULL, 0, 0},
-+};
-+
-+/* General Purpose EVM */
-+static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
-+	{enable_ecap0,	DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
-+						PROFILE_2 | PROFILE_7) },
-+	{lcdc_init,	DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
-+						PROFILE_2 | PROFILE_7) },
-+	{tsc_init,	DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
-+						PROFILE_2 | PROFILE_7) },
-+	{rgmii1_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{rgmii2_init,	DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
-+						PROFILE_4 | PROFILE_6) },
-+	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{evm_nand_init, DEV_ON_DGHTR_BRD,
-+		(PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
-+	{i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
-+	{mcasp1_init,	DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
-+	{mmc1_init,	DEV_ON_DGHTR_BRD, PROFILE_2},
-+	{mmc2_wl12xx_init,	DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
-+								PROFILE_5)},
-+	{mmc0_init,	DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
-+	{mmc0_no_cd_init,	DEV_ON_BASEBOARD, PROFILE_5},
-+	{spi0_init,	DEV_ON_DGHTR_BRD, PROFILE_2},
-+	{uart1_wl12xx_init,	DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
-+								PROFILE_5)},
-+	{wl12xx_init,	DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
-+	{d_can_init,	DEV_ON_DGHTR_BRD, PROFILE_1},
-+	{matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
-+	{volume_keys_init,  DEV_ON_DGHTR_BRD, PROFILE_0},
-+	{uart2_init,	DEV_ON_DGHTR_BRD, PROFILE_3},
-+	{haptics_init,	DEV_ON_DGHTR_BRD, (PROFILE_4)},
-+	{NULL, 0, 0},
-+};
-+
-+/* Industrial Auto Motor Control EVM */
-+static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
-+	{mii1_init,	DEV_ON_DGHTR_BRD, PROFILE_ALL},
-+	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
-+	{evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
-+	{spi1_init,	DEV_ON_DGHTR_BRD, PROFILE_ALL},
-+	{uart3_init,	DEV_ON_DGHTR_BRD, PROFILE_ALL},
-+	{i2c1_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{mmc0_no_cd_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{NULL, 0, 0},
-+};
-+
-+/* IP-Phone EVM */
-+static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
-+	{enable_ecap0,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
-+	{lcdc_init,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
-+	{tsc_init,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
-+	{rgmii1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{rgmii2_init,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
-+	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
-+	{i2c1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{mcasp1_init,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
-+	{mmc0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{NULL, 0, 0},
-+};
-+
-+/* Beaglebone < Rev A3 */
-+static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
-+	{rmii1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{i2c2_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{mmc0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{boneleds_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{NULL, 0, 0},
-+};
-+
-+/* Beaglebone Rev A3 and after */
-+static struct evm_dev_cfg beaglebone_dev_cfg[] = {
-+	{tps65217_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{mii1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{i2c2_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{mmc0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
-+	{boneleds_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{bonew1_gpio_init, DEV_ON_BASEBOARD, PROFILE_ALL},
-+	{NULL, 0, 0},
-+};
-+
-+static void setup_low_cost_evm(void)
-+{
-+	pr_info("The board is a AM335x Low Cost EVM.\n");
-+
-+	_configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
-+}
-+
-+static void setup_general_purpose_evm(void)
-+{
-+	u32 prof_sel = am335x_get_profile_selection();
-+	pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
-+
-+	if (!strncmp("1.1A", config.version, 4)) {
-+		pr_info("EVM version is %s\n", config.version);
-+		gp_evm_revision = GP_EVM_REV_IS_1_1A;
-+	} else if (!strncmp("1.0", config.version, 3)) {
-+		gp_evm_revision = GP_EVM_REV_IS_1_0;
-+	} else {
-+		pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
-+		gp_evm_revision = GP_EVM_REV_IS_1_1A;
-+	}
-+
-+	if (gp_evm_revision == GP_EVM_REV_IS_1_0)
-+		gigabit_enable = 0;
-+	else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
-+		gigabit_enable = 1;
-+
-+	_configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
-+}
-+
-+static void setup_ind_auto_motor_ctrl_evm(void)
-+{
-+	u32 prof_sel = am335x_get_profile_selection();
-+
-+	pr_info("The board is an industrial automation EVM in profile %d\n",
-+		prof_sel);
-+
-+	/* Only Profile 0 is supported */
-+	if ((1L << prof_sel) != PROFILE_0) {
-+		pr_err("AM335X: Only Profile 0 is supported\n");
-+		pr_err("Assuming profile 0 & continuing\n");
-+		prof_sel = PROFILE_0;
-+	}
-+
-+	_configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
-+		PROFILE_0);
-+
-+	/* Fillup global evmid */
-+	am33xx_evmid_fillup(IND_AUT_MTR_EVM);
-+
-+	/* Initialize TLK110 PHY registers for phy version 1.0 */
-+	am335x_tlk110_phy_init();
-+
-+
-+}
-+
-+static void setup_ip_phone_evm(void)
-+{
-+	pr_info("The board is an IP phone EVM\n");
-+
-+	_configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
-+}
-+
-+/* BeagleBone < Rev A3 */
-+static void setup_beaglebone_old(void)
-+{
-+	pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
-+
-+	/* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
-+	am335x_mmc[0].gpio_wp = -EINVAL;
-+
-+	_configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
-+
-+	phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
-+					beaglebone_phy_fixup);
-+
-+	/* Fill up global evmid */
-+	am33xx_evmid_fillup(BEAGLE_BONE_OLD);
-+}
-+
-+/* BeagleBone after Rev A3 */
-+static void setup_beaglebone(void)
-+{
-+	pr_info("The board is a AM335x Beaglebone.\n");
-+	gp_evm_revision = GP_EVM_ACTUALLY_BEAGLEBONE;
-+
-+	/* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
-+	am335x_mmc[0].gpio_wp = -EINVAL;
-+
-+	_configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
-+
-+	/* TPS65217 regulator has full constraints */
-+	regulator_has_full_constraints();
-+
-+	/* Fill up global evmid */
-+	am33xx_evmid_fillup(BEAGLE_BONE_A3);
-+}
-+
-+
-+static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
-+{
-+	int ret;
-+
-+	/*
-+	 * Read from the EEPROM to see the presence of daughter board.
-+	 * If present, print the cpld version.
-+	 */
-+
-+	ret = m->read(m, (char *)&config1, 0, sizeof(config1));
-+	if (ret == sizeof(config1)) {
-+		pr_info("Detected a daughter card on AM335x EVM..");
-+		daughter_brd_detected = true;
-+	}
-+	 else {
-+		pr_info("No daughter card found\n");
-+		daughter_brd_detected = false;
-+		return;
-+	}
-+
-+	if (!strncmp("CPLD", config1.cpld_ver, 4))
-+		pr_info("CPLD version: %s\n", config1.cpld_ver);
-+	else
-+		pr_err("Unknown CPLD version found\n");
-+}
-+
-+static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
-+{
-+	int ret;
-+	char tmp[10];
-+
-+	/* 1st get the MAC address from EEPROM */
-+	ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
-+		EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
-+
-+	if (ret != sizeof(am335x_mac_addr)) {
-+		pr_warning("AM335X: EVM Config read fail: %d\n", ret);
-+		return;
-+	}
-+
-+	/* Fillup global mac id */
-+	am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
-+				&am335x_mac_addr[1][0]);
-+
-+	/* get board specific data */
-+	ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
-+	if (ret != sizeof(config)) {
-+		pr_err("AM335X EVM config read fail, read %d bytes\n", ret);
-+		pr_err("This likely means that there either is no/or a failed EEPROM\n");
-+		goto out;
-+	}
-+
-+	if (config.header != AM335X_EEPROM_HEADER) {
-+		pr_err("AM335X: wrong header 0x%x, expected 0x%x\n",
-+			config.header, AM335X_EEPROM_HEADER);
-+		goto out;
-+	}
-+
-+	if (strncmp("A335", config.name, 4)) {
-+		pr_err("Board %s\ndoesn't look like an AM335x board\n",
-+			config.name);
-+		goto out;
-+	}
-+
-+	snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
-+	pr_info("Board name: %s\n", tmp);
-+	snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
-+	pr_info("Board version: %s\n", tmp);
-+
-+	if (!strncmp("A335BONE", config.name, 8)) {
-+		daughter_brd_detected = false;
-+		if(!strncmp("00A1", config.version, 4) ||
-+		   !strncmp("00A2", config.version, 4))
-+			setup_beaglebone_old();
-+		else
-+			setup_beaglebone();
-+	} else {
-+		/* only 6 characters of options string used for now */
-+		snprintf(tmp, 7, "%s", config.opt);
-+		pr_info("SKU: %s\n", tmp);
-+
-+		if (!strncmp("SKU#00", config.opt, 6))
-+			setup_low_cost_evm();
-+		else if (!strncmp("SKU#01", config.opt, 6))
-+			setup_general_purpose_evm();
-+		else if (!strncmp("SKU#02", config.opt, 6))
-+			setup_ind_auto_motor_ctrl_evm();
-+		else if (!strncmp("SKU#03", config.opt, 6))
-+			setup_ip_phone_evm();
-+		else
-+			goto out;
-+	}
-+	/* Initialize cpsw after board detection is completed as board
-+	 * information is required for configuring phy address and hence
-+	 * should be call only after board detection
-+	 */
-+	am33xx_cpsw_init(gigabit_enable);
-+
-+	return;
-+
-+out:
-+	/*
-+	 * If the EEPROM hasn't been programed or an incorrect header
-+	 * or board name are read then the hardware details are unknown.
-+	 * Notify the user and call machine_halt to stop the boot process.
-+	 */
-+	pr_err("The error message above indicates that there is an issue with\n"
-+		   "the EEPROM or the EEPROM contents.  After verifying the EEPROM\n"
-+		   "contents, if any, refer to the %s function in the\n"
-+		   "%s file to modify the board\n"
-+		   "initialization code to match the hardware configuration\n",
-+		   __func__ , __FILE__);
-+	machine_halt();
-+}
-+
-+static struct at24_platform_data am335x_daughter_board_eeprom_info = {
-+	.byte_len       = (256*1024) / 8,
-+	.page_size      = 64,
-+	.flags          = AT24_FLAG_ADDR16,
-+	.setup          = am335x_setup_daughter_board,
-+	.context        = (void *)NULL,
-+};
-+
-+static struct at24_platform_data am335x_baseboard_eeprom_info = {
-+	.byte_len       = (256*1024) / 8,
-+	.page_size      = 64,
-+	.flags          = AT24_FLAG_ADDR16,
-+	.setup          = am335x_evm_setup,
-+	.context        = (void *)NULL,
-+};
-+
-+static struct regulator_init_data am335x_dummy = {
-+	.constraints.always_on	= true,
-+};
-+
-+static struct regulator_consumer_supply am335x_vdd1_supply[] = {
-+	REGULATOR_SUPPLY("vdd_mpu", NULL),
-+};
-+
-+static struct regulator_init_data am335x_vdd1 = {
-+	.constraints = {
-+		.min_uV			= 600000,
-+		.max_uV			= 1500000,
-+		.valid_modes_mask	= REGULATOR_MODE_NORMAL,
-+		.valid_ops_mask		= REGULATOR_CHANGE_VOLTAGE,
-+		.always_on		= 1,
-+	},
-+	.num_consumer_supplies	= ARRAY_SIZE(am335x_vdd1_supply),
-+	.consumer_supplies	= am335x_vdd1_supply,
-+};
-+
-+static struct regulator_consumer_supply am335x_vdd2_supply[] = {
-+	REGULATOR_SUPPLY("vdd_core", NULL),
-+};
-+
-+static struct regulator_init_data am335x_vdd2 = {
-+	.constraints = {
-+		.min_uV			= 600000,
-+		.max_uV			= 1500000,
-+		.valid_modes_mask	= REGULATOR_MODE_NORMAL,
-+		.valid_ops_mask		= REGULATOR_CHANGE_VOLTAGE,
-+		.always_on		= 1,
-+	},
-+	.num_consumer_supplies	= ARRAY_SIZE(am335x_vdd2_supply),
-+	.consumer_supplies	= am335x_vdd2_supply,
-+};
-+
-+static struct tps65910_board am335x_tps65910_info = {
-+	.tps65910_pmic_init_data[TPS65910_REG_VRTC]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VIO]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VDD1]	= &am335x_vdd1,
-+	.tps65910_pmic_init_data[TPS65910_REG_VDD2]	= &am335x_vdd2,
-+	.tps65910_pmic_init_data[TPS65910_REG_VDD3]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VDIG1]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VDIG2]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VPLL]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VDAC]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VAUX1]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VAUX2]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VAUX33]	= &am335x_dummy,
-+	.tps65910_pmic_init_data[TPS65910_REG_VMMC]	= &am335x_dummy,
-+};
-+
-+/*
-+* Daughter board Detection.
-+* Every board has a ID memory (EEPROM) on board. We probe these devices at
-+* machine init, starting from daughter board and ending with baseboard.
-+* Assumptions :
-+*	1. probe for i2c devices are called in the order they are included in
-+*	   the below struct. Daughter boards eeprom are probed 1st. Baseboard
-+*	   eeprom probe is called last.
-+*/
-+static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
-+	{
-+		/* Daughter Board EEPROM */
-+		I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
-+		.platform_data  = &am335x_daughter_board_eeprom_info,
-+	},
-+	{
-+		/* Baseboard board EEPROM */
-+		I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
-+		.platform_data  = &am335x_baseboard_eeprom_info,
-+	},
-+	{
-+		I2C_BOARD_INFO("cpld_reg", 0x35),
-+	},
-+	{
-+		I2C_BOARD_INFO("tlc59108", 0x40),
-+	},
-+	{
-+		I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
-+		.platform_data  = &am335x_tps65910_info,
-+	},
-+};
-+
-+static struct omap_musb_board_data musb_board_data = {
-+	.interface_type	= MUSB_INTERFACE_ULPI,
-+	/*
-+	 * mode[0:3] = USB0PORT's mode
-+	 * mode[4:7] = USB1PORT's mode
-+	 * AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
-+	 */
-+	.mode           = (MUSB_HOST << 4) | MUSB_OTG,
-+	.power		= 500,
-+	.instances	= 1,
-+};
-+
-+static int cpld_reg_probe(struct i2c_client *client,
-+	    const struct i2c_device_id *id)
-+{
-+	cpld_client = client;
-+	return 0;
-+}
-+
-+static int __devexit cpld_reg_remove(struct i2c_client *client)
-+{
-+	cpld_client = NULL;
-+	return 0;
-+}
-+
-+static const struct i2c_device_id cpld_reg_id[] = {
-+	{ "cpld_reg", 0 },
-+	{ }
-+};
-+
-+static struct i2c_driver cpld_reg_driver = {
-+	.driver = {
-+		.name	= "cpld_reg",
-+	},
-+	.probe		= cpld_reg_probe,
-+	.remove		= cpld_reg_remove,
-+	.id_table	= cpld_reg_id,
-+};
-+
-+static void evm_init_cpld(void)
-+{
-+	i2c_add_driver(&cpld_reg_driver);
-+}
-+
-+static void __init am335x_evm_i2c_init(void)
-+{
-+	/* Initially assume Low Cost EVM Config */
-+	am335x_evm_id = LOW_COST_EVM;
-+
-+	evm_init_cpld();
-+
-+	omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
-+				ARRAY_SIZE(am335x_i2c_boardinfo));
-+}
-+
-+static struct resource am335x_rtc_resources[] = {
-+	{
-+		.start		= AM33XX_RTC_BASE,
-+		.end		= AM33XX_RTC_BASE + SZ_4K - 1,
-+		.flags		= IORESOURCE_MEM,
-+	},
-+	{ /* timer irq */
-+		.start		= AM33XX_IRQ_RTC_TIMER,
-+		.end		= AM33XX_IRQ_RTC_TIMER,
-+		.flags		= IORESOURCE_IRQ,
-+	},
-+	{ /* alarm irq */
-+		.start		= AM33XX_IRQ_RTC_ALARM,
-+		.end		= AM33XX_IRQ_RTC_ALARM,
-+		.flags		= IORESOURCE_IRQ,
-+	},
-+};
-+
-+static struct platform_device am335x_rtc_device = {
-+	.name           = "omap_rtc",
-+	.id             = -1,
-+	.num_resources	= ARRAY_SIZE(am335x_rtc_resources),
-+	.resource	= am335x_rtc_resources,
-+};
-+
-+static int am335x_rtc_init(void)
-+{
-+	void __iomem *base;
-+	struct clk *clk;
-+
-+	clk = clk_get(NULL, "rtc_fck");
-+	if (IS_ERR(clk)) {
-+		pr_err("rtc : Failed to get RTC clock\n");
-+		return -1;
-+	}
-+
-+	if (clk_enable(clk)) {
-+		pr_err("rtc: Clock Enable Failed\n");
-+		return -1;
-+	}
-+
-+	base = ioremap(AM33XX_RTC_BASE, SZ_4K);
-+
-+	if (WARN_ON(!base))
-+		return -ENOMEM;
-+
-+	/* Unlock the rtc's registers */
-+	writel(0x83e70b13, base + 0x6c);
-+	writel(0x95a4f1e0, base + 0x70);
-+
-+	/*
-+	 * Enable the 32K OSc
-+	 * TODO: Need a better way to handle this
-+	 * Since we want the clock to be running before mmc init
-+	 * we need to do it before the rtc probe happens
-+	 */
-+	writel(0x48, base + 0x54);
-+
-+	iounmap(base);
-+
-+	return  platform_device_register(&am335x_rtc_device);
-+}
-+
-+/* Enable clkout2 */
-+static struct pinmux_config clkout2_pin_mux[] = {
-+	{"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
-+	{NULL, 0},
-+};
-+
-+static void __init clkout2_enable(void)
-+{
-+	struct clk *ck_32;
-+
-+	ck_32 = clk_get(NULL, "clkout2_ck");
-+	if (IS_ERR(ck_32)) {
-+		pr_err("Cannot clk_get ck_32\n");
-+		return;
-+	}
-+
-+	clk_enable(ck_32);
-+
-+	setup_pin_mux(clkout2_pin_mux);
-+}
-+
-+void __iomem *am33xx_emif_base;
-+
-+void __iomem * __init am33xx_get_mem_ctlr(void)
-+{
-+
-+	am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
-+
-+	if (!am33xx_emif_base)
-+		pr_warning("%s: Unable to map DDR2 controller",	__func__);
-+
-+	return am33xx_emif_base;
-+}
-+
-+void __iomem *am33xx_get_ram_base(void)
-+{
-+	return am33xx_emif_base;
-+}
-+
-+static struct resource am33xx_cpuidle_resources[] = {
-+	{
-+		.start		= AM33XX_EMIF0_BASE,
-+		.end		= AM33XX_EMIF0_BASE + SZ_32K - 1,
-+		.flags		= IORESOURCE_MEM,
-+	},
-+};
-+
-+/* AM33XX devices support DDR2 power down */
-+static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
-+	.ddr2_pdown	= 1,
-+};
-+
-+static struct platform_device am33xx_cpuidle_device = {
-+	.name			= "cpuidle-am33xx",
-+	.num_resources		= ARRAY_SIZE(am33xx_cpuidle_resources),
-+	.resource		= am33xx_cpuidle_resources,
-+	.dev = {
-+		.platform_data	= &am33xx_cpuidle_pdata,
-+	},
-+};
-+
-+static void __init am33xx_cpuidle_init(void)
-+{
-+	int ret;
-+
-+	am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
-+
-+	ret = platform_device_register(&am33xx_cpuidle_device);
-+
-+	if (ret)
-+		pr_warning("AM33XX cpuidle registration failed\n");
-+
-+}
-+
-+static void __init am335x_evm_init(void)
-+{
-+	am33xx_cpuidle_init();
-+	am33xx_mux_init(board_mux);
-+	omap_serial_init();
-+	am335x_rtc_init();
-+	clkout2_enable();
-+	am335x_evm_i2c_init();
-+	omap_sdrc_init(NULL, NULL);
-+	usb_musb_init(&musb_board_data);
-+	omap_board_config = am335x_evm_config;
-+	omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
-+	/* Create an alias for icss clock */
-+	if (clk_add_alias("pruss", NULL, "pruss_uart_gclk", NULL))
-+		pr_warn("failed to create an alias: icss_uart_gclk --> pruss\n");
-+	/* Create an alias for gfx/sgx clock */
-+	if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
-+		pr_warn("failed to create an alias: gfx_fclk --> sgx_ck\n");
-+}
-+
-+static void __init am335x_evm_map_io(void)
-+{
-+	omap2_set_globals_am33xx();
-+	omapam33xx_map_common_io();
-+}
-+
-+MACHINE_START(AM335XEVM, "am335xevm")
-+	/* Maintainer: Texas Instruments */
-+	.atag_offset	= 0x100,
-+	.map_io		= am335x_evm_map_io,
-+	.init_early	= am33xx_init_early,
-+	.init_irq	= ti81xx_init_irq,
-+	.handle_irq     = omap3_intc_handle_irq,
-+	.timer		= &omap3_am33xx_timer,
-+	.init_machine	= am335x_evm_init,
-+MACHINE_END
-+
-+MACHINE_START(AM335XIAEVM, "am335xiaevm")
-+	/* Maintainer: Texas Instruments */
-+	.atag_offset	= 0x100,
-+	.map_io		= am335x_evm_map_io,
-+	.init_irq	= ti81xx_init_irq,
-+	.init_early	= am33xx_init_early,
-+	.timer		= &omap3_am33xx_timer,
-+	.init_machine	= am335x_evm_init,
-+MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
-index 7834536..7e90f93 100644
---- a/arch/arm/mach-omap2/board-am3517crane.c
-+++ b/arch/arm/mach-omap2/board-am3517crane.c
-@@ -27,7 +27,7 @@
- #include <asm/mach/map.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/usb.h>
- 
- #include "mux.h"
-@@ -98,6 +98,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
- 	.map_io		= omap3_map_io,
- 	.init_early	= am35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= am3517_crane_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
-index d314f03..3a44f07 100644
---- a/arch/arm/mach-omap2/board-am3517evm.c
-+++ b/arch/arm/mach-omap2/board-am3517evm.c
-@@ -24,6 +24,7 @@
- #include <linux/i2c/pca953x.h>
- #include <linux/can/platform/ti_hecc.h>
- #include <linux/davinci_emac.h>
-+#include <linux/mmc/host.h>
- 
- #include <mach/hardware.h>
- #include <mach/am35xx.h>
-@@ -32,7 +33,7 @@
- #include <asm/mach/map.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/usb.h>
- #include <video/omapdss.h>
- #include <video/omap-panel-generic-dpi.h>
-@@ -40,6 +41,7 @@
- 
- #include "mux.h"
- #include "control.h"
-+#include "hsmmc.h"
- 
- #define AM35XX_EVM_MDIO_FREQUENCY	(1000000)
- 
-@@ -455,6 +457,23 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
- static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
- };
- 
-+static struct omap2_hsmmc_info mmc[] = {
-+	{
-+		.mmc		= 1,
-+		.caps		= MMC_CAP_4_BIT_DATA,
-+		.gpio_cd	= 127,
-+		.gpio_wp	= 126,
-+	},
-+	{
-+		.mmc		= 2,
-+		.caps		= MMC_CAP_4_BIT_DATA,
-+		.gpio_cd	= 128,
-+		.gpio_wp	= 129,
-+	},
-+	{}      /* Terminator */
-+};
-+
-+
- static void __init am3517_evm_init(void)
- {
- 	omap_board_config = am3517_evm_config;
-@@ -483,6 +502,9 @@ static void __init am3517_evm_init(void)
- 
- 	/* MUSB */
- 	am3517_evm_musb_init();
-+
-+	/* MMC init function */
-+	omap2_hsmmc_init(mmc);
- }
- 
- MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
-@@ -491,6 +513,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
- 	.map_io		= omap3_map_io,
- 	.init_early	= am35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= am3517_evm_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
-index de8134b..5a66480 100644
---- a/arch/arm/mach-omap2/board-apollon.c
-+++ b/arch/arm/mach-omap2/board-apollon.c
-@@ -37,7 +37,7 @@
- #include <plat/led.h>
- #include <plat/usb.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/gpmc.h>
- 
- #include <video/omapdss.h>
-@@ -354,6 +354,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
- 	.map_io		= omap242x_map_io,
- 	.init_early	= omap2420_init_early,
- 	.init_irq	= omap2_init_irq,
-+	.handle_irq	= omap2_intc_handle_irq,
- 	.init_machine	= omap_apollon_init,
- 	.timer		= &omap2_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
-index bd1bcac..4cc2f04 100644
---- a/arch/arm/mach-omap2/board-cm-t35.c
-+++ b/arch/arm/mach-omap2/board-cm-t35.c
-@@ -37,7 +37,7 @@
- #include <asm/mach/map.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/nand.h>
- #include <plat/gpmc.h>
- #include <plat/usb.h>
-@@ -53,7 +53,8 @@
- #include "hsmmc.h"
- #include "common-board-devices.h"
- 
--#define CM_T35_GPIO_PENDOWN	57
-+#define CM_T35_GPIO_PENDOWN		57
-+#define SB_T35_USB_HUB_RESET_GPIO	167
- 
- #define CM_T35_SMSC911X_CS	5
- #define CM_T35_SMSC911X_GPIO	163
-@@ -279,7 +280,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
- 
- static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
- 	.turbo_mode	= 0,
--	.single_channel	= 1,	/* 0: slave, 1: master */
- };
- 
- static struct tdo24m_platform_data tdo24m_config = {
-@@ -339,8 +339,10 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
- 	REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
- };
- 
--static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
--	REGULATOR_SUPPLY("vdvi", "omapdss"),
-+static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
-+	REGULATOR_SUPPLY("vcc", "spi1.0"),
-+	REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-+	REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
- };
- 
- /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
-@@ -373,6 +375,19 @@ static struct regulator_init_data cm_t35_vsim = {
- 	.consumer_supplies	= cm_t35_vsim_supply,
- };
- 
-+static struct regulator_init_data cm_t35_vio = {
-+	.constraints = {
-+		.min_uV			= 1800000,
-+		.max_uV			= 1800000,
-+		.apply_uV		= true,
-+		.valid_modes_mask	= REGULATOR_MODE_NORMAL
-+					| REGULATOR_MODE_STANDBY,
-+		.valid_ops_mask		= REGULATOR_CHANGE_MODE,
-+	},
-+	.num_consumer_supplies	= ARRAY_SIZE(cm_t35_vio_supplies),
-+	.consumer_supplies	= cm_t35_vio_supplies,
-+};
-+
- static uint32_t cm_t35_keymap[] = {
- 	KEY(0, 0, KEY_A),	KEY(0, 1, KEY_B),	KEY(0, 2, KEY_LEFT),
- 	KEY(1, 0, KEY_UP),	KEY(1, 1, KEY_ENTER),	KEY(1, 2, KEY_DOWN),
-@@ -421,6 +436,23 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
- 	.reset_gpio_port[2]  = -EINVAL
- };
- 
-+static void cm_t35_init_usbh(void)
-+{
-+	int err;
-+
-+	err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
-+			       GPIOF_OUT_INIT_LOW, "usb hub rst");
-+	if (err) {
-+		pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
-+	} else {
-+		udelay(10);
-+		gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
-+		msleep(1);
-+	}
-+
-+	usbhs_init(&usbhs_bdata);
-+}
-+
- static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
- 				 unsigned ngpio)
- {
-@@ -456,17 +488,14 @@ static struct twl4030_platform_data cm_t35_twldata = {
- 	.gpio		= &cm_t35_gpio_data,
- 	.vmmc1		= &cm_t35_vmmc1,
- 	.vsim		= &cm_t35_vsim,
-+	.vio		= &cm_t35_vio,
- };
- 
- static void __init cm_t35_init_i2c(void)
- {
- 	omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
--			TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
--
--	cm_t35_twldata.vpll2->constraints.name = "VDVI";
--	cm_t35_twldata.vpll2->num_consumer_supplies =
--						ARRAY_SIZE(cm_t35_vdvi_supply);
--	cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
-+			      TWL_COMMON_REGULATOR_VDAC |
-+			      TWL_COMMON_PDATA_AUDIO);
- 
- 	omap3_pmic_init("tps65930", &cm_t35_twldata);
- }
-@@ -570,24 +599,28 @@ static void __init cm_t3x_common_dss_mux_init(int mux_mode)
- 
- static void __init cm_t35_init_mux(void)
- {
--	omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
--	cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-+	int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
-+
-+	omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
-+	omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
-+	omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
-+	omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
-+	omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
-+	omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
-+	cm_t3x_common_dss_mux_init(mux_mode);
- }
- 
- static void __init cm_t3730_init_mux(void)
- {
--	omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
--	omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
--	cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-+	int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
-+
-+	omap_mux_init_signal("sys_boot0", mux_mode);
-+	omap_mux_init_signal("sys_boot1", mux_mode);
-+	omap_mux_init_signal("sys_boot3", mux_mode);
-+	omap_mux_init_signal("sys_boot4", mux_mode);
-+	omap_mux_init_signal("sys_boot5", mux_mode);
-+	omap_mux_init_signal("sys_boot6", mux_mode);
-+	cm_t3x_common_dss_mux_init(mux_mode);
- }
- #else
- static inline void cm_t35_init_mux(void) {}
-@@ -612,7 +645,7 @@ static void __init cm_t3x_common_init(void)
- 	cm_t35_init_display();
- 
- 	usb_musb_init(NULL);
--	usbhs_init(&usbhs_bdata);
-+	cm_t35_init_usbh();
- }
- 
- static void __init cm_t35_init(void)
-@@ -634,6 +667,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= cm_t35_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-@@ -644,6 +678,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
- 	.map_io         = omap3_map_io,
- 	.init_early     = omap3630_init_early,
- 	.init_irq       = omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine   = cm_t3730_init,
- 	.timer          = &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
-index 3f4dc66..efc5ced 100644
---- a/arch/arm/mach-omap2/board-cm-t3517.c
-+++ b/arch/arm/mach-omap2/board-cm-t3517.c
-@@ -39,7 +39,7 @@
- #include <asm/mach/map.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/usb.h>
- #include <plat/nand.h>
- #include <plat/gpmc.h>
-@@ -299,6 +299,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
- 	.map_io		= omap3_map_io,
- 	.init_early	= am35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= cm_t3517_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
-index 90154e4..0a00ce6 100644
---- a/arch/arm/mach-omap2/board-devkit8000.c
-+++ b/arch/arm/mach-omap2/board-devkit8000.c
-@@ -41,7 +41,7 @@
- #include <asm/mach/flash.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/gpmc.h>
- #include <plat/nand.h>
- #include <plat/usb.h>
-@@ -59,6 +59,7 @@
- 
- #include "mux.h"
- #include "hsmmc.h"
-+#include "board-flash.h"
- #include "common-board-devices.h"
- 
- #define OMAP_DM9000_GPIO_IRQ	25
-@@ -646,8 +647,9 @@ static void __init devkit8000_init(void)
- 
- 	usb_musb_init(NULL);
- 	usbhs_init(&usbhs_bdata);
--	omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
--			     ARRAY_SIZE(devkit8000_nand_partitions));
-+	omap_nand_init(devkit8000_nand_partitions,
-+		ARRAY_SIZE(devkit8000_nand_partitions), GPMC_CS_NUM + 1,
-+		NAND_BUSWIDTH_16, NULL);
- 
- 	/* Ensure SDRC pins are mux'd for self-refresh */
- 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
-@@ -660,6 +662,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= devkit8000_init,
- 	.timer		= &omap3_secure_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
-index 30a6f52..915ec79 100644
---- a/arch/arm/mach-omap2/board-flash.c
-+++ b/arch/arm/mach-omap2/board-flash.c
-@@ -104,11 +104,8 @@ __init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
- }
- #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
- 
--#if defined(CONFIG_MTD_NAND_OMAP2) || \
--		defined(CONFIG_MTD_NAND_OMAP2_MODULE)
--
- /* Note that all values in this struct are in nanoseconds */
--static struct gpmc_timings nand_timings = {
-+struct gpmc_timings nand_default_timings = {
- 
- 	.sync_clk = 0,
- 
-@@ -131,22 +128,24 @@ static struct gpmc_timings nand_timings = {
- 	.wr_data_mux_bus = 0,
- };
- 
--static struct omap_nand_platform_data board_nand_data = {
--	.gpmc_t		= &nand_timings,
-+#if defined(CONFIG_MTD_NAND_OMAP2) || \
-+		defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-+
-+static struct omap_nand_platform_data omap_nand_data = {
-+	.gpmc_t		= &nand_default_timings,
- };
- 
--void
--__init board_nand_init(struct mtd_partition *nand_parts,
--			u8 nr_parts, u8 cs, int nand_type)
-+struct omap_nand_platform_data *
-+__init omap_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
-+				int nand_type, struct gpmc_timings *gpmc_t)
- {
--	board_nand_data.cs		= cs;
--	board_nand_data.parts		= nand_parts;
--	board_nand_data.nr_parts	= nr_parts;
--	board_nand_data.devsize		= nand_type;
--
--	board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
--	board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
--	gpmc_nand_init(&board_nand_data);
-+	omap_nand_data.cs		= cs;
-+	omap_nand_data.parts		= nand_parts;
-+	omap_nand_data.nr_parts		= nr_parts;
-+	omap_nand_data.devsize		= nand_type;
-+	omap_nand_data.gpmc_t		= gpmc_t;
-+
-+	return &omap_nand_data;
- }
- #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
- 
-@@ -242,6 +241,7 @@ void board_flash_init(struct flash_partitions partition_info[],
- 	if (nandcs > GPMC_CS_NUM)
- 		pr_err("NAND: Unable to find configuration in GPMC\n");
- 	else
--		board_nand_init(partition_info[2].parts,
--			partition_info[2].nr_parts, nandcs, nand_type);
-+		omap_nand_init(partition_info[2].parts,
-+			partition_info[2].nr_parts, nandcs,
-+			nand_type, &nand_default_timings);
- }
-diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
-index d25503a..93c02cc 100644
---- a/arch/arm/mach-omap2/board-flash.h
-+++ b/arch/arm/mach-omap2/board-flash.h
-@@ -39,11 +39,15 @@ static inline void board_flash_init(struct flash_partitions part[],
- 
- #if defined(CONFIG_MTD_NAND_OMAP2) || \
- 		defined(CONFIG_MTD_NAND_OMAP2_MODULE)
--extern void board_nand_init(struct mtd_partition *nand_parts,
--					u8 nr_parts, u8 cs, int nand_type);
-+extern struct gpmc_timings nand_default_timings;
-+extern struct omap_nand_platform_data *
-+__init omap_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
-+				int nand_type, struct gpmc_timings *gpmc_t);
- #else
--static inline void board_nand_init(struct mtd_partition *nand_parts,
--					u8 nr_parts, u8 cs, int nand_type)
-+static inline struct omap_nand_platform_data *
-+omap_nand_init(struct mtd_partition *nand_parts,
-+		u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
- {
-+	return NULL;
- }
- #endif
-diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
-index fb55fa3d..f2389e4 100644
---- a/arch/arm/mach-omap2/board-generic.c
-+++ b/arch/arm/mach-omap2/board-generic.c
-@@ -17,11 +17,11 @@
- #include <linux/i2c/twl.h>
- 
- #include <mach/hardware.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach/arch.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
--#include <mach/omap4-common.h>
-+#include "common.h"
- #include "common-board-devices.h"
- 
- /*
-@@ -70,7 +70,6 @@ static void __init omap_generic_init(void)
- 	if (node)
- 		irq_domain_add_simple(node, 0);
- 
--	omap_serial_init();
- 	omap_sdrc_init(NULL, NULL);
- 
- 	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
-@@ -104,6 +103,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
- 	.map_io		= omap242x_map_io,
- 	.init_early	= omap2420_init_early,
- 	.init_irq	= omap2_init_irq,
-+	.handle_irq	= omap2_intc_handle_irq,
- 	.init_machine	= omap_generic_init,
- 	.timer		= &omap2_timer,
- 	.dt_compat	= omap242x_boards_compat,
-@@ -122,6 +122,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
- 	.map_io		= omap243x_map_io,
- 	.init_early	= omap2430_init_early,
- 	.init_irq	= omap2_init_irq,
-+	.handle_irq	= omap2_intc_handle_irq,
- 	.init_machine	= omap_generic_init,
- 	.timer		= &omap2_timer,
- 	.dt_compat	= omap243x_boards_compat,
-@@ -140,6 +141,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3430_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap3_init,
- 	.timer		= &omap3_timer,
- 	.dt_compat	= omap3_boards_compat,
-@@ -158,6 +160,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
- 	.map_io		= omap4_map_io,
- 	.init_early	= omap4430_init_early,
- 	.init_irq	= gic_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= omap4_init,
- 	.timer		= &omap4_timer,
- 	.dt_compat	= omap4_boards_compat,
-diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
-index 8b351d9..ec40183 100644
---- a/arch/arm/mach-omap2/board-h4.c
-+++ b/arch/arm/mach-omap2/board-h4.c
-@@ -34,7 +34,7 @@
- 
- #include <plat/usb.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/menelaus.h>
- #include <plat/dma.h>
- #include <plat/gpmc.h>
-@@ -396,6 +396,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
- 	.map_io		= omap242x_map_io,
- 	.init_early	= omap2420_init_early,
- 	.init_irq	= omap2_init_irq,
-+	.handle_irq	= omap2_intc_handle_irq,
- 	.init_machine	= omap_h4_init,
- 	.timer		= &omap2_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
-index d0a3f78..5949f6a 100644
---- a/arch/arm/mach-omap2/board-igep0020.c
-+++ b/arch/arm/mach-omap2/board-igep0020.c
-@@ -28,7 +28,7 @@
- #include <asm/mach/arch.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/gpmc.h>
- #include <plat/usb.h>
- #include <video/omapdss.h>
-@@ -672,6 +672,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= igep_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-@@ -682,6 +683,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= igep_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
-index e179da0..09e9235 100644
---- a/arch/arm/mach-omap2/board-ldp.c
-+++ b/arch/arm/mach-omap2/board-ldp.c
-@@ -36,7 +36,7 @@
- 
- #include <plat/mcspi.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/gpmc.h>
- #include <mach/board-zoom.h>
- 
-@@ -421,8 +421,8 @@ static void __init omap_ldp_init(void)
- 	omap_serial_init();
- 	omap_sdrc_init(NULL, NULL);
- 	usb_musb_init(NULL);
--	board_nand_init(ldp_nand_partitions,
--		ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
-+	omap_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
-+				ZOOM_NAND_CS, 0, &nand_default_timings);
- 
- 	omap2_hsmmc_init(mmc);
- 	ldp_display_init();
-@@ -434,6 +434,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3430_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap_ldp_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
-index e9d5f4a..b521198 100644
---- a/arch/arm/mach-omap2/board-n8x0.c
-+++ b/arch/arm/mach-omap2/board-n8x0.c
-@@ -15,8 +15,11 @@
- #include <linux/delay.h>
- #include <linux/gpio.h>
- #include <linux/init.h>
-+#include <linux/irq.h>
- #include <linux/io.h>
- #include <linux/stddef.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/cbus.h>
- #include <linux/i2c.h>
- #include <linux/spi/spi.h>
- #include <linux/usb/musb.h>
-@@ -26,7 +29,7 @@
- #include <asm/mach-types.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/menelaus.h>
- #include <mach/irqs.h>
- #include <plat/mcspi.h>
-@@ -46,7 +49,7 @@ static struct device *mmc_device;
- #define TUSB6010_GPIO_ENABLE	0
- #define TUSB6010_DMACHAN	0x3f
- 
--#ifdef CONFIG_USB_MUSB_TUSB6010
-+#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
- /*
-  * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
-  * 1.5 V voltage regulators of PM companion chip. Companion chip will then
-@@ -137,7 +140,6 @@ static void __init n8x0_usb_init(void) {}
- 
- static struct omap2_mcspi_device_config p54spi_mcspi_config = {
- 	.turbo_mode	= 0,
--	.single_channel = 1,
- };
- 
- static struct spi_board_info n800_spi_board_info[] __initdata = {
-@@ -193,6 +195,105 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
- };
- #endif
- 
-+#if defined(CONFIG_CBUS) || defined(CONFIG_CBUS_MODULE)
-+
-+static struct cbus_host_platform_data n8x0_cbus_data = {
-+	.clk_gpio	= 66,
-+	.dat_gpio	= 65,
-+	.sel_gpio	= 64,
-+};
-+
-+static struct platform_device n8x0_cbus_device = {
-+	.name		= "cbus",
-+	.id		= -1,
-+	.dev		= {
-+		.platform_data = &n8x0_cbus_data,
-+	},
-+};
-+
-+static struct resource retu_resource[] = {
-+	{
-+		.start	= -EINVAL, /* set later */
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+};
-+
-+static struct platform_device retu_device = {
-+	.name		= "retu",
-+	.id		= -1,
-+	.resource	= retu_resource,
-+	.num_resources	= ARRAY_SIZE(retu_resource),
-+	.dev		= {
-+		.parent	= &n8x0_cbus_device.dev,
-+	},
-+};
-+
-+static struct resource tahvo_resource[] = {
-+	{
-+		.start	= -EINVAL, /* set later */
-+		.flags	= IORESOURCE_IRQ,
-+	}
-+};
-+
-+static struct platform_device tahvo_device = {
-+	.name		= "tahvo",
-+	.id		= -1,
-+	.resource	= tahvo_resource,
-+	.num_resources	= ARRAY_SIZE(tahvo_resource),
-+	.dev		= {
-+		.parent	= &n8x0_cbus_device.dev,
-+	},
-+};
-+
-+static void __init n8x0_cbus_init(void)
-+{
-+	int		ret;
-+
-+	platform_device_register(&n8x0_cbus_device);
-+
-+	ret = gpio_request(108, "RETU irq");
-+	if (ret < 0) {
-+		pr_err("retu: Unable to reserve IRQ GPIO\n");
-+		return;
-+	}
-+
-+	ret = gpio_direction_input(108);
-+	if (ret < 0) {
-+		pr_err("retu: Unable to change gpio direction\n");
-+		gpio_free(108);
-+		return;
-+	}
-+
-+	irq_set_irq_type(gpio_to_irq(108), IRQ_TYPE_EDGE_RISING);
-+	retu_resource[0].start = gpio_to_irq(108);
-+	platform_device_register(&retu_device);
-+
-+	ret = gpio_request(111, "TAHVO irq");
-+	if (ret) {
-+		pr_err("tahvo: Unable to reserve IRQ GPIO\n");
-+		gpio_free(108);
-+		return;
-+	}
-+
-+	/* Set the pin as input */
-+	ret = gpio_direction_input(111);
-+	if (ret) {
-+		pr_err("tahvo: Unable to change direction\n");
-+		gpio_free(108);
-+		gpio_free(111);
-+		return;
-+	}
-+
-+	tahvo_resource[0].start = gpio_to_irq(111);
-+	platform_device_register(&tahvo_device);
-+}
-+
-+#else
-+static inline void __init n8x0_cbus_init(void)
-+{
-+}
-+#endif
-+
- #if defined(CONFIG_MENELAUS) &&						\
- 	(defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
- 
-@@ -644,15 +745,15 @@ static inline void board_serial_init(void)
- 	bdata.pads_cnt = 0;
- 
- 	bdata.id = 0;
--	omap_serial_init_port(&bdata);
-+	omap_serial_init_port(&bdata, NULL);
- 
- 	bdata.id = 1;
--	omap_serial_init_port(&bdata);
-+	omap_serial_init_port(&bdata, NULL);
- 
- 	bdata.id = 2;
- 	bdata.pads = serial2_pads;
- 	bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
--	omap_serial_init_port(&bdata);
-+	omap_serial_init_port(&bdata, NULL);
- }
- 
- #else
-@@ -667,6 +768,8 @@ static inline void board_serial_init(void)
- static void __init n8x0_init_machine(void)
- {
- 	omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
-+	n8x0_cbus_init();
-+
- 	/* FIXME: add n810 spi devices */
- 	spi_register_board_info(n800_spi_board_info,
- 				ARRAY_SIZE(n800_spi_board_info));
-@@ -689,6 +792,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
- 	.map_io		= omap242x_map_io,
- 	.init_early	= omap2420_init_early,
- 	.init_irq	= omap2_init_irq,
-+	.handle_irq	= omap2_intc_handle_irq,
- 	.init_machine	= n8x0_init_machine,
- 	.timer		= &omap2_timer,
- MACHINE_END
-@@ -699,6 +803,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
- 	.map_io		= omap242x_map_io,
- 	.init_early	= omap2420_init_early,
- 	.init_irq	= omap2_init_irq,
-+	.handle_irq	= omap2_intc_handle_irq,
- 	.init_machine	= n8x0_init_machine,
- 	.timer		= &omap2_timer,
- MACHINE_END
-@@ -709,6 +814,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
- 	.map_io		= omap242x_map_io,
- 	.init_early	= omap2420_init_early,
- 	.init_irq	= omap2_init_irq,
-+	.handle_irq	= omap2_intc_handle_irq,
- 	.init_machine	= n8x0_init_machine,
- 	.timer		= &omap2_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index 4a71cb7..f17ae3d 100644
---- a/arch/arm/mach-omap2/board-omap3beagle.c
-+++ b/arch/arm/mach-omap2/board-omap3beagle.c
-@@ -40,7 +40,7 @@
- #include <asm/mach/flash.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <video/omapdss.h>
- #include <video/omap-panel-dvi.h>
- #include <plat/gpmc.h>
-@@ -51,6 +51,7 @@
- #include "mux.h"
- #include "hsmmc.h"
- #include "pm.h"
-+#include "board-flash.h"
- #include "common-board-devices.h"
- 
- /*
-@@ -538,8 +539,9 @@ static void __init omap3_beagle_init(void)
- 
- 	usb_musb_init(NULL);
- 	usbhs_init(&usbhs_bdata);
--	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
--			     ARRAY_SIZE(omap3beagle_nand_partitions));
-+	omap_nand_init(omap3beagle_nand_partitions,
-+		ARRAY_SIZE(omap3beagle_nand_partitions), GPMC_CS_NUM + 1,
-+		NAND_BUSWIDTH_16, NULL);
- 
- 	/* Ensure msecure is mux'd to be able to set the RTC. */
- 	omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
-@@ -559,6 +561,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap3_beagle_init,
- 	.timer		= &omap3_secure_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-omap3encore.c b/arch/arm/mach-omap2/board-omap3encore.c
-new file mode 100644
-index 0000000..ab60e3e
---- /dev/null
-+++ b/arch/arm/mach-omap2/board-omap3encore.c
-@@ -0,0 +1,344 @@
-+/*
-+ * Support for Barns&Noble Nook Color
-+ *
-+ * Loosely based on mach-omap2/board-zoom.c
-+ * Copyright (C) 2008-2010 Texas Instruments Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * June 2011 Oleg Drokin <green@linuxhacker.ru> - Port to mainline
-+ *
-+ */
-+
-+#include <linux/gpio.h>
-+#include <linux/gpio_keys.h>
-+#include <linux/i2c/twl.h>
-+#include <linux/regulator/machine.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+
-+#include <plat/usb.h>
-+#include <plat/mux.h>
-+#include <plat/mmc.h>
-+
-+#include "common.h"
-+#include "mux.h"
-+#include "hsmmc.h"
-+#include "sdram-hynix-h8mbx00u0mer-0em.h"
-+
-+/* Encore-specific device-info and i2c addresses. */
-+/* Battery, bus 1 */
-+#define MAX17042_I2C_SLAVE_ADDRESS	0x36
-+#define MAX17042_GPIO_FOR_IRQ		100
-+
-+/*addition of MAXIM8903/TI GPIO mapping WRT schematics */
-+#define MAX8903_UOK_GPIO_FOR_IRQ	115
-+#define MAX8903_DOK_GPIO_FOR_IRQ	114
-+#define MAX8903_GPIO_CHG_EN		110
-+#define MAX8903_GPIO_CHG_STATUS		111
-+#define MAX8903_GPIO_CHG_FLT		101
-+#define MAX8903_GPIO_CHG_IUSB		102
-+#define MAX8903_GPIO_CHG_USUS		104
-+#define MAX8903_GPIO_CHG_ILM		61
-+
-+/* TI WLAN */
-+#define ENCORE_WIFI_PMENA_GPIO		22
-+#define ENCORE_WIFI_IRQ_GPIO		15
-+#define ENCORE_WIFI_EN_POW		16
-+
-+/* Accelerometer i2c bus 1*/
-+#define KXTF9_I2C_SLAVE_ADDRESS		0x0F
-+#define KXTF9_GPIO_FOR_PWR		34
-+#define KXTF9_GPIO_FOR_IRQ		113
-+
-+/* Touch screen i2c bus 2*/
-+#define CYTTSP_I2C_SLAVEADDRESS		34
-+#define ENCORE_CYTTSP_GPIO		99
-+#define ENCORE_CYTTSP_RESET_GPIO	46
-+
-+/* Audio codec, i2c bus 2 */
-+#define AUDIO_CODEC_POWER_ENABLE_GPIO	103
-+#define AUDIO_CODEC_RESET_GPIO		37
-+#define AUDIO_CODEC_IRQ_GPIO		59
-+#define AIC3100_I2CSLAVEADDRESS		0x18
-+
-+
-+/* Different HW revisions */
-+#define BOARD_ENCORE_REV_EVT1A		0x1
-+#define BOARD_ENCORE_REV_EVT1B		0x2
-+#define BOARD_ENCORE_REV_EVT2		0x3
-+#define BOARD_ENCORE_REV_DVT		0x4
-+#define BOARD_ENCORE_REV_PVT		0x5
-+#define BOARD_ENCORE_REV_UNKNOWN	0x6
-+
-+static inline int is_encore_board_evt2(void)
-+{
-+	return system_rev >= BOARD_ENCORE_REV_EVT2;
-+}
-+
-+static inline int is_encore_board_evt1b(void)
-+{
-+	return system_rev == BOARD_ENCORE_REV_EVT1B;
-+}
-+
-+static int encore_twl4030_keymap[] = {
-+	KEY(1, 0, KEY_VOLUMEUP),
-+	KEY(2, 0, KEY_VOLUMEDOWN),
-+};
-+
-+static struct matrix_keymap_data encore_twl4030_keymap_data = {
-+	.keymap			= encore_twl4030_keymap,
-+	.keymap_size		= ARRAY_SIZE(encore_twl4030_keymap),
-+};
-+
-+static struct twl4030_keypad_data encore_kp_twl4030_data = {
-+	.rows			= 8,
-+	.cols			= 8,
-+	.keymap_data		= &encore_twl4030_keymap_data,
-+	.rep			= 1,
-+};
-+
-+/* HOME key code for HW > EVT2A */
-+static struct gpio_keys_button encore_gpio_buttons[] = {
-+	{
-+		.code			= KEY_POWER,
-+		.gpio			= 14,
-+		.desc			= "POWER",
-+		.active_low		= 0,
-+		.wakeup			= 1,
-+	},
-+	{
-+		.code			= KEY_HOME,
-+		.gpio			= 48,
-+		.desc			= "HOME",
-+		.active_low		= 1,
-+		.wakeup			= 1,
-+	},
-+};
-+
-+static struct gpio_keys_platform_data encore_gpio_key_info = {
-+	.buttons	= encore_gpio_buttons,
-+	.nbuttons	= ARRAY_SIZE(encore_gpio_buttons),
-+};
-+
-+static struct platform_device encore_keys_gpio = {
-+	.name	= "gpio-keys",
-+	.id	= -1,
-+	.dev	= {
-+		.platform_data	= &encore_gpio_key_info,
-+	},
-+};
-+
-+static struct platform_device *encore_devices[] __initdata = {
-+	&encore_keys_gpio,
-+};
-+
-+static struct twl4030_usb_data encore_usb_data = {
-+	.usb_mode	= T2_USB_MODE_ULPI,
-+};
-+
-+static struct regulator_consumer_supply encore_vmmc1_supply[] = {
-+	REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
-+};
-+
-+static struct regulator_consumer_supply encore_vdda_dac_supply[] = {
-+	REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
-+};
-+
-+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
-+static struct regulator_init_data encore_vmmc1 = {
-+	.constraints = {
-+		.min_uV			= 1850000,
-+		.max_uV			= 3150000,
-+		.valid_modes_mask	= REGULATOR_MODE_NORMAL
-+					| REGULATOR_MODE_STANDBY,
-+		.valid_ops_mask		= REGULATOR_CHANGE_VOLTAGE
-+					| REGULATOR_CHANGE_MODE
-+					| REGULATOR_CHANGE_STATUS,
-+	},
-+	.num_consumer_supplies  = ARRAY_SIZE(encore_vmmc1_supply),
-+	.consumer_supplies      = encore_vmmc1_supply,
-+};
-+
-+static struct regulator_init_data encore_vdac = {
-+	.constraints = {
-+		.min_uV                 = 1800000,
-+		.max_uV                 = 1800000,
-+		.valid_modes_mask       = REGULATOR_MODE_NORMAL
-+					| REGULATOR_MODE_STANDBY,
-+		.valid_ops_mask         = REGULATOR_CHANGE_MODE
-+					| REGULATOR_CHANGE_STATUS,
-+	},
-+	.num_consumer_supplies  = ARRAY_SIZE(encore_vdda_dac_supply),
-+	.consumer_supplies      = encore_vdda_dac_supply,
-+};
-+
-+/*
-+ * The order is reverted in this table so that internal eMMC is presented
-+ * as first mmc card for compatibility with existing installations and
-+ * for common sense reasons
-+ */
-+static struct omap2_hsmmc_info mmc[] __initdata = {
-+	{
-+		.name		= "internal",
-+		.mmc		= 2,
-+		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-+		.gpio_cd	= -EINVAL,
-+		.gpio_wp	= -EINVAL,
-+		.nonremovable	= true,
-+		.power_saving	= true,
-+		.ocr_mask	= MMC_VDD_165_195, /* 1.85V */
-+	},
-+	{
-+		.name		= "external",
-+		.mmc		= 1,
-+		.caps		= MMC_CAP_4_BIT_DATA,
-+		.gpio_cd	= -EINVAL,
-+		.gpio_wp	= -EINVAL,
-+		.power_saving	= true,
-+	},
-+	{
-+		.name		= "internal",
-+		.mmc		= 3,
-+		.caps		= MMC_CAP_4_BIT_DATA,
-+		.gpio_cd	= -EINVAL,
-+		.gpio_wp	= -EINVAL,
-+		.nonremovable	= true,
-+		.power_saving	= true,
-+	},
-+	{}      /* Terminator */
-+};
-+
-+static int encore_hsmmc_card_detect(struct device *dev, int slot)
-+{
-+	struct omap_mmc_platform_data *mmc = dev->platform_data;
-+
-+	/* Encore board EVT2 and later has pin high when card is present */
-+	return gpio_get_value_cansleep(mmc->slots[0].switch_pin);
-+}
-+
-+static int encore_twl4030_hsmmc_late_init(struct device *dev)
-+{
-+	int ret = 0;
-+	struct platform_device *pdev = container_of(dev,
-+						struct platform_device, dev);
-+	struct omap_mmc_platform_data *pdata = dev->platform_data;
-+
-+	if (is_encore_board_evt2()) {
-+		/* Setting MMC1 (external) Card detect */
-+		if (pdev->id == 0)
-+			pdata->slots[0].card_detect = encore_hsmmc_card_detect;
-+	}
-+
-+	return ret;
-+}
-+
-+static __init void encore_hsmmc_set_late_init(struct device *dev)
-+{
-+	struct omap_mmc_platform_data *pdata;
-+
-+	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
-+	if (!dev)
-+		return;
-+
-+	pdata = dev->platform_data;
-+	pdata->init = encore_twl4030_hsmmc_late_init;
-+}
-+
-+static int __ref encore_twl_gpio_setup(struct device *dev,
-+		unsigned gpio, unsigned ngpio)
-+{
-+	struct omap2_hsmmc_info *c;
-+	/*
-+	 * gpio + 0 is "mmc0_cd" (input/IRQ),
-+	 * gpio + 1 is "mmc1_cd" (input/IRQ)
-+	 */
-+	mmc[1].gpio_cd = gpio + 0;
-+	mmc[0].gpio_cd = gpio + 1;
-+	omap2_hsmmc_init(mmc);
-+	for (c = mmc; c->mmc; c++)
-+		encore_hsmmc_set_late_init(c->dev);
-+
-+	return 0;
-+}
-+
-+static struct twl4030_gpio_platform_data encore_gpio_data = {
-+	.gpio_base	= OMAP_MAX_GPIO_LINES,
-+	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-+	.irq_end	= TWL4030_GPIO_IRQ_END,
-+	.setup		= encore_twl_gpio_setup,
-+};
-+
-+static struct twl4030_madc_platform_data encore_madc_data = {
-+	.irq_line	= 1,
-+};
-+
-+static struct twl4030_platform_data __refdata encore_twldata = {
-+	.irq_base	= TWL4030_IRQ_BASE,
-+	.irq_end	= TWL4030_IRQ_END,
-+
-+	.madc		= &encore_madc_data,
-+	.usb		= &encore_usb_data,
-+	.gpio		= &encore_gpio_data,
-+	.keypad		= &encore_kp_twl4030_data,
-+	.vmmc1		= &encore_vmmc1,
-+	.vdac		= &encore_vdac,
-+};
-+
-+static struct i2c_board_info __initdata encore_i2c_bus1_info[] = {
-+	{
-+		I2C_BOARD_INFO("tps65921", 0x48),
-+		.flags = I2C_CLIENT_WAKE,
-+		.irq = INT_34XX_SYS_NIRQ,
-+		.platform_data = &encore_twldata,
-+	},
-+};
-+
-+static struct i2c_board_info __initdata encore_i2c_bus2_info[] = {
-+};
-+
-+#ifdef CONFIG_OMAP_MUX
-+static struct omap_board_mux board_mux[] __initdata = {
-+	{ .reg_offset = OMAP_MUX_TERMINATOR },
-+};
-+#endif
-+
-+static struct omap_board_config_kernel encore_config[] __initdata = {
-+};
-+
-+static void __init omap_i2c_init(void)
-+{
-+	omap_register_i2c_bus(1, 100, encore_i2c_bus1_info,
-+			ARRAY_SIZE(encore_i2c_bus1_info));
-+	omap_register_i2c_bus(2, 400, encore_i2c_bus2_info,
-+			ARRAY_SIZE(encore_i2c_bus2_info));
-+}
-+
-+static void __init omap_encore_init(void)
-+{
-+	omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-+	omap_i2c_init();
-+	omap_serial_init();
-+	omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
-+				  h8mbx00u0mer0em_sdrc_params);
-+	usb_musb_init(NULL);
-+
-+	omap_board_config = encore_config;
-+	omap_board_config_size = ARRAY_SIZE(encore_config);
-+
-+	platform_add_devices(encore_devices, ARRAY_SIZE(encore_devices));
-+}
-+
-+MACHINE_START(ENCORE, "encore")
-+	.atag_offset	= 0x100,
-+	.reserve	= omap_reserve,
-+	.map_io		= omap3_map_io,
-+	.init_early	= omap3630_init_early,
-+	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
-+	.init_machine	= omap_encore_init,
-+	.timer		= &omap3_timer,
-+MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
-index ec00b2e..620056f 100644
---- a/arch/arm/mach-omap2/board-omap3evm.c
-+++ b/arch/arm/mach-omap2/board-omap3evm.c
-@@ -43,7 +43,7 @@
- 
- #include <plat/board.h>
- #include <plat/usb.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/mcspi.h>
- #include <video/omapdss.h>
- #include <video/omap-panel-dvi.h>
-@@ -637,7 +637,7 @@ static void __init omap3_evm_init(void)
- 	omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
- 
- 	/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
--	usb_nop_xceiv_register();
-+	usb_nop_xceiv_register(0);
- 
- 	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
- 		/* enable EHCI VBUS using GPIO22 */
-@@ -672,6 +672,12 @@ static void __init omap3_evm_init(void)
- 		pr_err("error setting wl12xx data\n");
- 	platform_device_register(&omap3evm_wlan_regulator);
- #endif
-+	/* NAND */
-+	omap_nand_init(omap3_evm_nand_partitions,
-+			ARRAY_SIZE(omap3_evm_nand_partitions),
-+			0, NAND_BUSWIDTH_16, &nand_default_timings);
-+	board_onenand_init(omap3_evm_onenand_partitions,
-+			ARRAY_SIZE(omap3_evm_onenand_partitions), 0);
- }
- 
- MACHINE_START(OMAP3EVM, "OMAP3 EVM")
-@@ -681,6 +687,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap3_evm_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
-index 7c0f193..5fa6bad 100644
---- a/arch/arm/mach-omap2/board-omap3logic.c
-+++ b/arch/arm/mach-omap2/board-omap3logic.c
-@@ -40,7 +40,7 @@
- 
- #include <plat/mux.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/gpmc-smsc911x.h>
- #include <plat/gpmc.h>
- #include <plat/sdrc.h>
-@@ -208,6 +208,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap3logic_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-@@ -217,6 +218,7 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap3logic_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
-index f7811f4..ef315c5 100644
---- a/arch/arm/mach-omap2/board-omap3pandora.c
-+++ b/arch/arm/mach-omap2/board-omap3pandora.c
-@@ -41,7 +41,7 @@
- #include <asm/mach/map.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <mach/hardware.h>
- #include <plat/mcspi.h>
- #include <plat/usb.h>
-@@ -606,6 +606,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap3pandora_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
-index ddb7d66..b21d70a 100644
---- a/arch/arm/mach-omap2/board-omap3stalker.c
-+++ b/arch/arm/mach-omap2/board-omap3stalker.c
-@@ -35,7 +35,7 @@
- #include <asm/mach/flash.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/gpmc.h>
- #include <plat/nand.h>
- #include <plat/usb.h>
-@@ -454,6 +454,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
- 	.map_io			= omap3_map_io,
- 	.init_early		= omap35xx_init_early,
- 	.init_irq		= omap3_init_irq,
-+	.handle_irq		= omap3_intc_handle_irq,
- 	.init_machine		= omap3_stalker_init,
- 	.timer			= &omap3_secure_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
-index a2d0d19..f55922e 100644
---- a/arch/arm/mach-omap2/board-omap3touchbook.c
-+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
-@@ -44,13 +44,14 @@
- #include <asm/mach/flash.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/gpmc.h>
- #include <plat/nand.h>
- #include <plat/usb.h>
- 
- #include "mux.h"
- #include "hsmmc.h"
-+#include "board-flash.h"
- #include "common-board-devices.h"
- 
- #include <asm/setup.h>
-@@ -366,8 +367,9 @@ static void __init omap3_touchbook_init(void)
- 	omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
- 	usb_musb_init(NULL);
- 	usbhs_init(&usbhs_bdata);
--	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions,
--			     ARRAY_SIZE(omap3touchbook_nand_partitions));
-+	omap_nand_init(omap3touchbook_nand_partitions,
-+		ARRAY_SIZE(omap3touchbook_nand_partitions), GPMC_CS_NUM + 1,
-+		NAND_BUSWIDTH_16, NULL);
- 
- 	/* Ensure SDRC pins are mux'd for self-refresh */
- 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
-@@ -381,6 +383,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3430_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap3_touchbook_init,
- 	.timer		= &omap3_secure_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
-index 51b1c93..9cc9564 100644
---- a/arch/arm/mach-omap2/board-omap4panda.c
-+++ b/arch/arm/mach-omap2/board-omap4panda.c
-@@ -30,14 +30,14 @@
- #include <linux/wl12xx.h>
- 
- #include <mach/hardware.h>
--#include <mach/omap4-common.h>
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <video/omapdss.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/usb.h>
- #include <plat/mmc.h>
- #include <video/omap-panel-dvi.h>
-@@ -365,74 +365,8 @@ static struct omap_board_mux board_mux[] __initdata = {
- 	{ .reg_offset = OMAP_MUX_TERMINATOR },
- };
- 
--static struct omap_device_pad serial2_pads[] __initdata = {
--	OMAP_MUX_STATIC("uart2_cts.uart2_cts",
--			 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart2_rts.uart2_rts",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart2_rx.uart2_rx",
--			 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart2_tx.uart2_tx",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--};
--
--static struct omap_device_pad serial3_pads[] __initdata = {
--	OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
--			 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
--			 OMAP_PIN_INPUT | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--};
--
--static struct omap_device_pad serial4_pads[] __initdata = {
--	OMAP_MUX_STATIC("uart4_rx.uart4_rx",
--			 OMAP_PIN_INPUT | OMAP_MUX_MODE0),
--	OMAP_MUX_STATIC("uart4_tx.uart4_tx",
--			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
--};
--
--static struct omap_board_data serial2_data __initdata = {
--	.id             = 1,
--	.pads           = serial2_pads,
--	.pads_cnt       = ARRAY_SIZE(serial2_pads),
--};
--
--static struct omap_board_data serial3_data __initdata = {
--	.id             = 2,
--	.pads           = serial3_pads,
--	.pads_cnt       = ARRAY_SIZE(serial3_pads),
--};
--
--static struct omap_board_data serial4_data __initdata = {
--	.id             = 3,
--	.pads           = serial4_pads,
--	.pads_cnt       = ARRAY_SIZE(serial4_pads),
--};
--
--static inline void board_serial_init(void)
--{
--	struct omap_board_data bdata;
--	bdata.flags     = 0;
--	bdata.pads      = NULL;
--	bdata.pads_cnt  = 0;
--	bdata.id        = 0;
--	/* pass dummy data for UART1 */
--	omap_serial_init_port(&bdata);
--
--	omap_serial_init_port(&serial2_data);
--	omap_serial_init_port(&serial3_data);
--	omap_serial_init_port(&serial4_data);
--}
- #else
- #define board_mux	NULL
--
--static inline void board_serial_init(void)
--{
--	omap_serial_init();
--}
- #endif
- 
- /* Display DVI */
-@@ -568,7 +502,7 @@ static void __init omap4_panda_init(void)
- 	omap4_panda_i2c_init();
- 	platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
- 	platform_device_register(&omap_vwlan_device);
--	board_serial_init();
-+	omap_serial_init();
- 	omap_sdrc_init(NULL, NULL);
- 	omap4_twl6030_hsmmc_init(mmc);
- 	omap4_ehci_init();
-@@ -583,6 +517,7 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
- 	.map_io		= omap4_map_io,
- 	.init_early	= omap4430_init_early,
- 	.init_irq	= gic_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= omap4_panda_init,
- 	.timer		= &omap4_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-omap4pcm049.c b/arch/arm/mach-omap2/board-omap4pcm049.c
-new file mode 100644
-index 0000000..3b39464b
---- /dev/null
-+++ b/arch/arm/mach-omap2/board-omap4pcm049.c
-@@ -0,0 +1,584 @@
-+/*
-+ * Board support file for Phytec phyCORE-OMAP4 Board.
-+ *
-+ * Copyright (C) 2011 Phytec Messtechnik GmbH
-+ *
-+ * Author: Jan Weitzel <armlinux@phytec.de>
-+ *
-+ * Based on mach-omap2/board-omap4panda.c
-+ *
-+ * Author: David Anders <x0132446@ti.com>
-+ *
-+ * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/leds.h>
-+#include <linux/gpio.h>
-+#include <linux/usb/otg.h>
-+#include <linux/i2c/twl.h>
-+#include <linux/i2c/at24.h>
-+#include <linux/mfd/stmpe.h>
-+#include <linux/leds-pca9532.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/regulator/fixed.h>
-+#include <linux/smsc911x.h>
-+
-+#include <mach/hardware.h>
-+#include <asm/hardware/gic.h>
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/map.h>
-+#include <video/omapdss.h>
-+
-+#include <plat/board.h>
-+#include <plat/usb.h>
-+#include <plat/gpmc.h>
-+#include <plat/gpmc-smsc911x.h>
-+#include <plat/mmc.h>
-+#include <video/omap-panel-generic-dpi.h>
-+
-+#include "common.h"
-+#include "hsmmc.h"
-+#include "control.h"
-+#include "mux.h"
-+#include "common-board-devices.h"
-+
-+#define OMAP4_PCM049_ETH_GPIO_IRQ	121
-+#define OMAP4_PCM049_ETH_CS		5
-+#define OMAP4_PCM049_STMPE811_GPIO_IRQ	117
-+#define OMAP4_PCM049_LCD_ENABLE		118
-+
-+static struct gpio_led gpio_leds[] = {
-+	{
-+		.name			= "modul:red:status1",
-+		.default_trigger	= "heartbeat",
-+		.gpio			= 152,
-+	},
-+	{
-+		.name			= "modul:green:status2",
-+		.default_trigger	= "mmc0",
-+		.gpio			= 153,
-+	},
-+};
-+
-+static struct gpio_led_platform_data gpio_led_info = {
-+	.leds		= gpio_leds,
-+	.num_leds	= ARRAY_SIZE(gpio_leds),
-+};
-+
-+static struct platform_device leds_gpio = {
-+	.name	= "leds-gpio",
-+	.id	= -1,
-+	.dev	= {
-+		.platform_data	= &gpio_led_info,
-+	},
-+};
-+
-+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
-+	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-+	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-+	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-+	.phy_reset  = false,
-+	.reset_gpio_port[0]  = -EINVAL,
-+	.reset_gpio_port[1]  = -EINVAL,
-+	.reset_gpio_port[2]  = -EINVAL
-+};
-+
-+static void __init omap4_ehci_init(void)
-+{
-+	struct clk *phy_ref_clk;
-+	/* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-+	phy_ref_clk = clk_get(NULL, "auxclk3_ck");
-+	if (IS_ERR(phy_ref_clk)) {
-+		pr_err("Cannot request auxclk3\n");
-+		return;
-+	}
-+	clk_set_rate(phy_ref_clk, 19200000);
-+	clk_enable(phy_ref_clk);
-+
-+	usbhs_init(&usbhs_bdata);
-+	return;
-+}
-+
-+static struct omap_musb_board_data musb_board_data = {
-+	.interface_type		= MUSB_INTERFACE_UTMI,
-+	.mode			= MUSB_OTG,
-+	.power			= 100,
-+};
-+
-+static struct omap2_hsmmc_info mmc[] = {
-+	{
-+		.mmc		= 1,
-+		.caps		= MMC_CAP_4_BIT_DATA,
-+		.gpio_wp	= -EINVAL,
-+		.gpio_cd	= -EINVAL,
-+	}, {
-+		.mmc		= 5,
-+		.caps		= MMC_CAP_4_BIT_DATA,
-+		.gpio_wp	= -EINVAL,
-+		.gpio_cd	= 30,	/* wk30 */
-+		.ocr_mask	= MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
-+	}, {}	/* Terminator */
-+};
-+
-+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-+static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
-+	.cs             = OMAP4_PCM049_ETH_CS,
-+	.gpio_irq       = OMAP4_PCM049_ETH_GPIO_IRQ,
-+	.gpio_reset     = -EINVAL,
-+	.flags          = SMSC911X_USE_16BIT,
-+};
-+
-+static inline void __init pcm049_init_smsc911x(void)
-+{
-+	omap_mux_init_gpio(OMAP4_PCM049_ETH_GPIO_IRQ, OMAP_PIN_INPUT);
-+	gpmc_smsc911x_init(&board_smsc911x_data);
-+}
-+#else
-+static inline void __init pcm049_init_smsc911x(void) { return; }
-+#endif
-+
-+static int omap4_twl6030_hsmmc_late_init(struct device *dev)
-+{
-+	int ret = 0;
-+	struct platform_device *pdev = container_of(dev,
-+				struct platform_device, dev);
-+	struct omap_mmc_platform_data *pdata = dev->platform_data;
-+
-+	/* Setting MMC1 Card detect Irq */
-+	if (pdev->id == 0) {
-+		ret = twl6030_mmc_card_detect_config();
-+		if (ret)
-+			dev_err(dev, "%s: Error card detect config(%d)\n",
-+				__func__, ret);
-+		pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
-+						MMCDETECT_INTR_OFFSET;
-+		pdata->slots[0].card_detect = twl6030_mmc_card_detect;
-+	}
-+	return ret;
-+}
-+
-+static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
-+{
-+	struct omap_mmc_platform_data *pdata;
-+
-+	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
-+	if (!dev) {
-+		pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n");
-+		return;
-+	}
-+	pdata = dev->platform_data;
-+
-+	pdata->init =	omap4_twl6030_hsmmc_late_init;
-+}
-+
-+static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
-+{
-+	struct omap2_hsmmc_info *c;
-+
-+	omap2_hsmmc_init(controllers);
-+	for (c = controllers; c->mmc; c++)
-+		omap4_twl6030_hsmmc_set_late_init(c->dev);
-+
-+	return 0;
-+}
-+
-+/* Fixed regulator for max1027 */
-+static struct regulator_consumer_supply pcm049_vcc_3v3_consumer_supply[] = {
-+	REGULATOR_SUPPLY("vcc", "4-0064"),
-+};
-+
-+struct regulator_init_data pcm049_vcc_3v3_initdata = {
-+	.consumer_supplies = pcm049_vcc_3v3_consumer_supply,
-+	.num_consumer_supplies = ARRAY_SIZE(pcm049_vcc_3v3_consumer_supply),
-+	.constraints = {
-+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
-+	},
-+};
-+
-+static struct fixed_voltage_config pcm049_vcc_3v3_config = {
-+	.supply_name		= "pcm049_vcc_3v3",
-+	.microvolts		= 3300000,
-+	.gpio			= -EINVAL,
-+	.enabled_at_boot	= 1,
-+	.init_data		= &pcm049_vcc_3v3_initdata,
-+};
-+
-+static struct platform_device pcm049_vcc_3v3_device = {
-+	.name	= "reg-fixed-voltage",
-+	.id	= 0,
-+	.dev	= {
-+		.platform_data = &pcm049_vcc_3v3_config,
-+	},
-+};
-+
-+static struct at24_platform_data board_eeprom = {
-+	.byte_len = 4096,
-+	.page_size = 32,
-+	.flags = AT24_FLAG_ADDR16,
-+};
-+
-+static struct stmpe_gpio_platform_data pba_gpio_stm_data = {
-+	.gpio_base = -1,
-+	.norequest_mask = STMPE_GPIO_NOREQ_811_TOUCH,
-+};
-+
-+static struct stmpe_ts_platform_data pba_ts_stm_pdata = {
-+	.sample_time = 4,
-+	.mod_12b = 1,
-+	.ref_sel = 0,
-+	.adc_freq = 1,
-+	.ave_ctrl = 3,
-+	.touch_det_delay = 3,
-+	.settling = 3,
-+	.fraction_z = 7,
-+	.i_drive = 0,
-+};
-+
-+static struct stmpe_platform_data pba_stm_pdata = {
-+	.blocks = STMPE_BLOCK_GPIO | STMPE_BLOCK_TOUCHSCREEN,
-+	.irq_base = TWL6030_IRQ_END,
-+	.irq_trigger = IRQF_TRIGGER_RISING,
-+	.irq_invert_polarity = true,
-+	.gpio = &pba_gpio_stm_data,
-+	.ts = &pba_ts_stm_pdata,
-+};
-+
-+static struct pca9532_platform_data pba_pca9532 = {
-+	.leds = {
-+		{
-+			.name = "board:red:free_use1",
-+			.state = PCA9532_OFF,
-+			.type = PCA9532_TYPE_LED,
-+		}, {
-+			.name = "board:yellow:free_use2",
-+			.state = PCA9532_OFF,
-+			.type = PCA9532_TYPE_LED,
-+		}, {
-+			.name = "board:yellow:free_use3",
-+			.state = PCA9532_OFF,
-+			.type = PCA9532_TYPE_LED,
-+		}, {
-+			.name = "board:green:free_use4",
-+			.state = PCA9532_OFF,
-+			.type = PCA9532_TYPE_LED,
-+		},
-+	},
-+	.psc = { 1, 1 },
-+	.pwm = { 1, 1 },
-+};
-+
-+static struct i2c_board_info __initdata pcm049_i2c_1_boardinfo[] = {
-+	{
-+		I2C_BOARD_INFO("at24", 0x57), /* E0=1, E1=1, E2=1 */
-+		.platform_data = &board_eeprom,
-+	},
-+};
-+
-+static struct i2c_board_info __initdata pcm049_i2c_3_boardinfo[] = {
-+};
-+
-+static struct i2c_board_info __initdata pcm049_i2c_4_boardinfo[] = {
-+	{
-+		I2C_BOARD_INFO("stmpe811", 0x41),	/* Touch controller */
-+		.irq = OMAP_GPIO_IRQ(OMAP4_PCM049_STMPE811_GPIO_IRQ),
-+		.platform_data = &pba_stm_pdata,
-+	}, {
-+		I2C_BOARD_INFO("max1037", 0x64),	/* A/D converter */
-+	}, {
-+		I2C_BOARD_INFO("pca9533", 0x62),	/* Leds pca9533 */
-+		.platform_data = &pba_pca9532,
-+	}
-+};
-+
-+static struct twl4030_platform_data pcm049_twldata;
-+
-+static int __init pcm049_i2c_init(void)
-+{
-+	/* I2C1 */
-+	omap4_pmic_get_config(&pcm049_twldata, TWL_COMMON_PDATA_USB,
-+			TWL_COMMON_REGULATOR_VDAC |
-+			TWL_COMMON_REGULATOR_VAUX2 |
-+			TWL_COMMON_REGULATOR_VAUX3 |
-+			TWL_COMMON_REGULATOR_VMMC |
-+			TWL_COMMON_REGULATOR_VPP |
-+			TWL_COMMON_REGULATOR_VANA |
-+			TWL_COMMON_REGULATOR_VCXIO |
-+			TWL_COMMON_REGULATOR_VUSB |
-+			TWL_COMMON_REGULATOR_CLK32KG);
-+	omap4_pmic_init("twl6030", &pcm049_twldata);
-+	i2c_register_board_info(1, pcm049_i2c_1_boardinfo,
-+				ARRAY_SIZE(pcm049_i2c_1_boardinfo));
-+
-+	/* I2C3 */
-+	omap_register_i2c_bus(3, 400, pcm049_i2c_3_boardinfo,
-+				ARRAY_SIZE(pcm049_i2c_3_boardinfo));
-+
-+	/* I2C4 */
-+	if (omap_mux_init_gpio(OMAP4_PCM049_STMPE811_GPIO_IRQ, OMAP_PIN_INPUT))
-+		printk(KERN_ERR "Failed to mux GPIO%d for STMPE811 IRQ\n",
-+			OMAP4_PCM049_STMPE811_GPIO_IRQ);
-+	else if (gpio_request(OMAP4_PCM049_STMPE811_GPIO_IRQ, "STMPE811 irq"))
-+		printk(KERN_ERR "Failed to request GPIO%d for STMPE811 IRQ\n",
-+			OMAP4_PCM049_STMPE811_GPIO_IRQ);
-+	else
-+		gpio_direction_input(OMAP4_PCM049_STMPE811_GPIO_IRQ);
-+
-+	omap_register_i2c_bus(4, 400, pcm049_i2c_4_boardinfo,
-+				ARRAY_SIZE(pcm049_i2c_4_boardinfo));
-+	return 0;
-+}
-+
-+#ifdef CONFIG_OMAP_MUX
-+static struct omap_board_mux board_mux[] __initdata = {
-+	OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-+	OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-+	OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-+	OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-+
-+	/* dispc2_data23 */
-+	OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data22 */
-+	OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data21 */
-+	OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data20 */
-+	OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data19 */
-+	OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data18 */
-+	OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data15 */
-+	OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data14 */
-+	OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data13 */
-+	OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data12 */
-+	OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data11 */
-+	OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data10 */
-+	OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data9 */
-+	OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data16 */
-+	OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data17 */
-+	OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_hsync */
-+	OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_pclk */
-+	OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_vsync */
-+	OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_de */
-+	OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data8 */
-+	OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data7 */
-+	OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data6 */
-+	OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data5 */
-+	OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data4 */
-+	OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data3 */
-+	OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data2 */
-+	OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data1 */
-+	OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+	/* dispc2_data0 */
-+	OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-+
-+	{ .reg_offset = OMAP_MUX_TERMINATOR },
-+};
-+
-+static struct omap_device_pad serial2_pads[] __initdata = {
-+	OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-+			 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-+	OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-+			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-+	OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-+			 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-+	OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-+			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-+};
-+
-+static struct omap_device_pad serial3_pads[] __initdata = {
-+	OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-+			 OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-+	OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-+			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-+	OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-+			 OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-+	OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-+			 OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-+};
-+
-+static struct omap_board_data serial2_data __initdata = {
-+	.id             = 1,
-+	.pads           = serial2_pads,
-+	.pads_cnt       = ARRAY_SIZE(serial2_pads),
-+};
-+
-+static struct omap_board_data serial3_data __initdata = {
-+	.id             = 2,
-+	.pads           = serial3_pads,
-+	.pads_cnt       = ARRAY_SIZE(serial3_pads),
-+};
-+
-+static inline void board_serial_init(void)
-+{
-+	omap_serial_init_port(&serial2_data, NULL);
-+	omap_serial_init_port(&serial3_data, NULL);
-+}
-+#else
-+#define board_mux	NULL
-+
-+static inline void board_serial_init(void)
-+{
-+	omap_serial_init();
-+}
-+#endif
-+
-+/* Display */
-+static int pcm049_panel_enable_lcd(struct omap_dss_device *dssdev)
-+{
-+	return gpio_direction_output(OMAP4_PCM049_LCD_ENABLE, 1);
-+}
-+
-+static void pcm049_panel_disable_lcd(struct omap_dss_device *dssdev)
-+{
-+	gpio_direction_output(OMAP4_PCM049_LCD_ENABLE, 0);
-+	return;
-+}
-+
-+/* Using generic display panel */
-+static struct panel_generic_dpi_data omap4_dpi_panel = {
-+	.name			= "pd050vl1",
-+	.platform_enable	= pcm049_panel_enable_lcd,
-+	.platform_disable	= pcm049_panel_disable_lcd,
-+};
-+
-+struct omap_dss_device pcm049_dpi_device = {
-+	.type			= OMAP_DISPLAY_TYPE_DPI,
-+	.name			= "dpi",
-+	.driver_name		= "generic_dpi_panel",
-+	.data			= &omap4_dpi_panel,
-+	.phy.dpi.data_lines	= 24,
-+	.channel		= OMAP_DSS_CHANNEL_LCD2,
-+};
-+
-+static void pcm049_dvi_mux_init(void)
-+{
-+	/* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
-+	omap_mux_init_signal("hdmi_hpd",
-+			OMAP_PIN_INPUT_PULLUP);
-+	omap_mux_init_signal("hdmi_cec",
-+			OMAP_PIN_INPUT_PULLUP);
-+	/* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
-+	omap_mux_init_signal("hdmi_ddc_scl",
-+			OMAP_PIN_INPUT_PULLUP);
-+	omap_mux_init_signal("hdmi_ddc_sda",
-+			OMAP_PIN_INPUT_PULLUP);
-+}
-+
-+static struct omap_dss_device  pcm049_dvi_device = {
-+	.name = "dvi",
-+	.driver_name = "hdmi_panel",
-+	.type = OMAP_DISPLAY_TYPE_HDMI,
-+	.clocks	= {
-+		.dispc	= {
-+			.dispc_fclk_src	= OMAP_DSS_CLK_SRC_FCK,
-+		},
-+		.hdmi	= {
-+			.regn	= 15,
-+			.regm2	= 1,
-+		},
-+	},
-+	.channel = OMAP_DSS_CHANNEL_DIGIT,
-+};
-+
-+static struct omap_dss_device *pcm049_dss_devices[] = {
-+	&pcm049_dpi_device,
-+	&pcm049_dvi_device,
-+};
-+
-+static struct omap_dss_board_info pcm049_dss_data = {
-+	.num_devices	= ARRAY_SIZE(pcm049_dss_devices),
-+	.devices	= pcm049_dss_devices,
-+	.default_device = &pcm049_dpi_device,
-+};
-+
-+void pcm049_display_init(void)
-+{
-+	omap_mux_init_gpio(OMAP4_PCM049_LCD_ENABLE, OMAP_PIN_OUTPUT);
-+
-+	if ((gpio_request(OMAP4_PCM049_LCD_ENABLE, "DISP_ENA") == 0) &&
-+		(gpio_direction_output(OMAP4_PCM049_LCD_ENABLE, 1) == 0)) {
-+		gpio_export(OMAP4_PCM049_LCD_ENABLE, 0);
-+		gpio_set_value(OMAP4_PCM049_LCD_ENABLE, 0);
-+	} else
-+		printk(KERN_ERR "could not obtain gpio for DISP_ENA");
-+	pcm049_dvi_mux_init();
-+	omap_display_init(&pcm049_dss_data);
-+}
-+
-+static struct platform_device *pcm049_devices[] __initdata = {
-+	&pcm049_vcc_3v3_device,
-+	&leds_gpio,
-+};
-+
-+#define	TWL_PHOENIX_DEV_ON	0x25
-+
-+static void pcm049_power_off(void)
-+{
-+	printk(KERN_INFO "Goodbye phyCORE OMAP4!\n");
-+	twl_i2c_write_u8(TWL6030_MODULE_ID0, 0x7, TWL_PHOENIX_DEV_ON);
-+}
-+
-+
-+static void __init pcm049_init(void)
-+{
-+	pm_power_off = pcm049_power_off;
-+	omap4_mux_init(board_mux, NULL, OMAP_PACKAGE_CBS);
-+	pcm049_init_smsc911x();
-+	pcm049_i2c_init();
-+	platform_add_devices(pcm049_devices, ARRAY_SIZE(pcm049_devices));
-+	board_serial_init();
-+	omap_sdrc_init(NULL, NULL);
-+	omap4_twl6030_hsmmc_init(mmc);
-+	omap4_ehci_init();
-+	usb_musb_init(&musb_board_data);
-+	pcm049_display_init();
-+}
-+
-+static void __init pcm049_map_io(void)
-+{
-+	omap2_set_globals_443x();
-+	omap44xx_map_common_io();
-+}
-+
-+MACHINE_START(PCM049, "phyCORE OMAP4")
-+	/* Maintainer: Jan Weitzel - Phytec Messtechnik GmbH */
-+	.atag_offset	= 0x100,
-+	.reserve	= omap_reserve,
-+	.map_io		= pcm049_map_io,
-+	.init_early	= omap4430_init_early,
-+	.init_irq	= gic_init_irq,
-+	.handle_irq	= gic_handle_irq,
-+	.init_machine	= pcm049_init,
-+	.timer		= &omap4_timer,
-+MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
-index 4cf7aea..d5619c5 100644
---- a/arch/arm/mach-omap2/board-overo.c
-+++ b/arch/arm/mach-omap2/board-overo.c
-@@ -43,7 +43,7 @@
- #include <asm/mach/map.h>
- 
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <video/omapdss.h>
- #include <video/omap-panel-generic-dpi.h>
- #include <video/omap-panel-dvi.h>
-@@ -57,6 +57,7 @@
- #include "mux.h"
- #include "sdram-micron-mt46h32m32lf-6.h"
- #include "hsmmc.h"
-+#include "board-flash.h"
- #include "common-board-devices.h"
- 
- #define OVERO_GPIO_BT_XGATE	15
-@@ -510,8 +511,8 @@ static void __init overo_init(void)
- 	omap_serial_init();
- 	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
- 				  mt46h32m32lf6_sdrc_params);
--	omap_nand_flash_init(0, overo_nand_partitions,
--			     ARRAY_SIZE(overo_nand_partitions));
-+	omap_nand_init(overo_nand_partitions,
-+		ARRAY_SIZE(overo_nand_partitions), GPMC_CS_NUM + 1, 0, NULL);
- 	usb_musb_init(NULL);
- 	usbhs_init(&usbhs_bdata);
- 	overo_spi_init();
-@@ -562,6 +563,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap35xx_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= overo_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
-index 616fb39..a79d49e 100644
---- a/arch/arm/mach-omap2/board-rm680.c
-+++ b/arch/arm/mach-omap2/board-rm680.c
-@@ -25,7 +25,7 @@
- #include <plat/mmc.h>
- #include <plat/usb.h>
- #include <plat/gpmc.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/onenand.h>
- 
- #include "mux.h"
-@@ -149,6 +149,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3630_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= rm680_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
-index c15c5c9..c142ad7 100644
---- a/arch/arm/mach-omap2/board-rx51-peripherals.c
-+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
-@@ -15,6 +15,7 @@
- #include <linux/input/matrix_keypad.h>
- #include <linux/spi/spi.h>
- #include <linux/wl12xx.h>
-+#include <linux/spi/tsc2005.h>
- #include <linux/i2c.h>
- #include <linux/i2c/twl.h>
- #include <linux/clk.h>
-@@ -27,7 +28,7 @@
- 
- #include <plat/mcspi.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/dma.h>
- #include <plat/gpmc.h>
- #include <plat/onenand.h>
-@@ -58,6 +59,9 @@
- 
- #define RX51_USB_TRANSCEIVER_RST_GPIO	67
- 
-+#define RX51_TSC2005_RESET_GPIO         104
-+#define RX51_TSC2005_IRQ_GPIO           100
-+
- /* list all spi devices here */
- enum {
- 	RX51_SPI_WL1251,
-@@ -66,6 +70,7 @@ enum {
- };
- 
- static struct wl12xx_platform_data wl1251_pdata;
-+static struct tsc2005_platform_data tsc2005_pdata;
- 
- #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
- static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
-@@ -133,17 +138,14 @@ static struct lp5523_platform_data rx51_lp5523_platform_data = {
- 
- static struct omap2_mcspi_device_config wl1251_mcspi_config = {
- 	.turbo_mode	= 0,
--	.single_channel	= 1,
- };
- 
- static struct omap2_mcspi_device_config mipid_mcspi_config = {
- 	.turbo_mode	= 0,
--	.single_channel	= 1,
- };
- 
- static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
- 	.turbo_mode	= 0,
--	.single_channel	= 1,
- };
- 
- static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
-@@ -167,10 +169,10 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
- 		.modalias		= "tsc2005",
- 		.bus_num		= 1,
- 		.chip_select		= 0,
--		/* .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),*/
-+		.irq			= OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
- 		.max_speed_hz		= 6000000,
- 		.controller_data	= &tsc2005_mcspi_config,
--		/* .platform_data = &tsc2005_config,*/
-+		.platform_data		= &tsc2005_pdata,
- 	},
- };
- 
-@@ -1086,6 +1088,42 @@ error:
- 	 */
- }
- 
-+static struct tsc2005_platform_data tsc2005_pdata = {
-+	.ts_pressure_max	= 2048,
-+	.ts_pressure_fudge	= 2,
-+	.ts_x_max		= 4096,
-+	.ts_x_fudge		= 4,
-+	.ts_y_max		= 4096,
-+	.ts_y_fudge		= 7,
-+	.ts_x_plate_ohm		= 280,
-+	.esd_timeout_ms		= 8000,
-+};
-+
-+static void rx51_tsc2005_set_reset(bool enable)
-+{
-+	gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
-+}
-+
-+static void __init rx51_init_tsc2005(void)
-+{
-+	int r;
-+
-+	r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ");
-+	if (r < 0) {
-+		printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ");
-+		rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0;
-+	}
-+
-+	r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
-+		"tsc2005 reset");
-+	if (r >= 0) {
-+		tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
-+	} else {
-+		printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
-+		tsc2005_pdata.esd_timeout_ms = 0;
-+	}
-+}
-+
- void __init rx51_peripherals_init(void)
- {
- 	rx51_i2c_init();
-@@ -1094,6 +1132,7 @@ void __init rx51_peripherals_init(void)
- 	board_smc91x_init();
- 	rx51_add_gpio_keys();
- 	rx51_init_wl1251();
-+	rx51_init_tsc2005();
- 	rx51_init_si4713();
- 	spi_register_board_info(rx51_peripherals_spi_board_info,
- 				ARRAY_SIZE(rx51_peripherals_spi_board_info));
-diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
-index 4af7c4b..4e3c096 100644
---- a/arch/arm/mach-omap2/board-rx51.c
-+++ b/arch/arm/mach-omap2/board-rx51.c
-@@ -25,7 +25,7 @@
- 
- #include <plat/mcspi.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/dma.h>
- #include <plat/gpmc.h>
- #include <plat/usb.h>
-@@ -127,6 +127,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3430_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= rx51_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
-index e6ee884..5b6ad6e 100644
---- a/arch/arm/mach-omap2/board-ti8168evm.c
-+++ b/arch/arm/mach-omap2/board-ti8168evm.c
-@@ -1,5 +1,5 @@
- /*
-- * Code for TI8168 EVM.
-+ * Code for TI8168/TI8148 EVM.
-  *
-  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
-  *
-@@ -22,30 +22,44 @@
- 
- #include <plat/irqs.h>
- #include <plat/board.h>
--#include <plat/common.h>
-+#include "common.h"
-+#include <plat/usb.h>
- 
--static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
-+static struct omap_musb_board_data musb_board_data = {
-+	.set_phy_power	= ti81xx_musb_phy_power,
-+	.interface_type	= MUSB_INTERFACE_ULPI,
-+	.mode           = MUSB_OTG,
-+	.power		= 500,
- };
- 
--static void __init ti8168_evm_init(void)
-+static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
-+};
-+
-+static void __init ti81xx_evm_init(void)
- {
- 	omap_serial_init();
- 	omap_sdrc_init(NULL, NULL);
--	omap_board_config = ti8168_evm_config;
--	omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
--}
--
--static void __init ti8168_evm_map_io(void)
--{
--	omapti816x_map_common_io();
-+	omap_board_config = ti81xx_evm_config;
-+	omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
-+	usb_musb_init(&musb_board_data);
- }
- 
- MACHINE_START(TI8168EVM, "ti8168evm")
- 	/* Maintainer: Texas Instruments */
- 	.atag_offset	= 0x100,
--	.map_io		= ti8168_evm_map_io,
--	.init_early	= ti816x_init_early,
--	.init_irq	= ti816x_init_irq,
-+	.map_io		= ti81xx_map_io,
-+	.init_early	= ti81xx_init_early,
-+	.init_irq	= ti81xx_init_irq,
-+	.timer		= &omap3_timer,
-+	.init_machine	= ti81xx_evm_init,
-+MACHINE_END
-+
-+MACHINE_START(TI8148EVM, "ti8148evm")
-+	/* Maintainer: Texas Instruments */
-+	.atag_offset	= 0x100,
-+	.map_io		= ti81xx_map_io,
-+	.init_early	= ti81xx_init_early,
-+	.init_irq	= ti81xx_init_irq,
- 	.timer		= &omap3_timer,
--	.init_machine	= ti8168_evm_init,
-+	.init_machine	= ti81xx_evm_init,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
-index d4683ba..2818290 100644
---- a/arch/arm/mach-omap2/board-zoom-display.c
-+++ b/arch/arm/mach-omap2/board-zoom-display.c
-@@ -117,7 +117,6 @@ static struct omap_dss_board_info zoom_dss_data = {
- 
- static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
- 	.turbo_mode		= 1,
--	.single_channel	= 1,  /* 0: slave, 1: master */
- };
- 
- static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
-diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
-index 6d0aa4f..8d7ce11 100644
---- a/arch/arm/mach-omap2/board-zoom-peripherals.c
-+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
-@@ -24,7 +24,7 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/usb.h>
- 
- #include <mach/board-zoom.h>
-diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
-index be6684d..fb6d606 100644
---- a/arch/arm/mach-omap2/board-zoom.c
-+++ b/arch/arm/mach-omap2/board-zoom.c
-@@ -21,7 +21,7 @@
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/board.h>
- #include <plat/usb.h>
- 
-@@ -114,8 +114,9 @@ static void __init omap_zoom_init(void)
- 		usbhs_init(&usbhs_bdata);
- 	}
- 
--	board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
--						ZOOM_NAND_CS, NAND_BUSWIDTH_16);
-+	omap_nand_init(zoom_nand_partitions,
-+			ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS,
-+			NAND_BUSWIDTH_16, &nand_default_timings);
- 	zoom_debugboard_init();
- 	zoom_peripherals_init();
- 
-@@ -135,6 +136,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3430_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap_zoom_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-@@ -145,6 +147,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
- 	.map_io		= omap3_map_io,
- 	.init_early	= omap3630_init_early,
- 	.init_irq	= omap3_init_irq,
-+	.handle_irq	= omap3_intc_handle_irq,
- 	.init_machine	= omap_zoom_init,
- 	.timer		= &omap3_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
-index e069a9b..a81abea 100644
---- a/arch/arm/mach-omap2/clkt_dpll.c
-+++ b/arch/arm/mach-omap2/clkt_dpll.c
-@@ -206,13 +206,9 @@ void omap2_init_dpll_parent(struct clk *clk)
- 		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
- 		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
- 			clk_reparent(clk, dd->clk_bypass);
--	} else if (cpu_is_omap34xx()) {
-+	} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- 		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
--		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
--			clk_reparent(clk, dd->clk_bypass);
--	} else if (cpu_is_omap44xx()) {
--		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
--		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-+		    v == OMAP3XXX_EN_DPLL_FRBYPASS ||
- 		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
- 			clk_reparent(clk, dd->clk_bypass);
- 	}
-@@ -252,13 +248,9 @@ u32 omap2_get_dpll_rate(struct clk *clk)
- 		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
- 		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
- 			return dd->clk_bypass->rate;
--	} else if (cpu_is_omap34xx()) {
-+	} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- 		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
--		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
--			return dd->clk_bypass->rate;
--	} else if (cpu_is_omap44xx()) {
--		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
--		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-+		    v == OMAP3XXX_EN_DPLL_FRBYPASS ||
- 		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
- 			return dd->clk_bypass->rate;
- 	}
-diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
-index 1f3481f..f57ed5b 100644
---- a/arch/arm/mach-omap2/clock.c
-+++ b/arch/arm/mach-omap2/clock.c
-@@ -35,7 +35,7 @@
- #include "cm-regbits-24xx.h"
- #include "cm-regbits-34xx.h"
- 
--u8 cpu_mask;
-+u16 cpu_mask;
- 
- /*
-  * clkdm_control: if true, then when a clock is enabled in the
-diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
-index 2311bc2..3f818ba 100644
---- a/arch/arm/mach-omap2/clock.h
-+++ b/arch/arm/mach-omap2/clock.h
-@@ -37,9 +37,6 @@
- 
- /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
- #define OMAP4XXX_EN_DPLL_MNBYPASS		0x4
--#define OMAP4XXX_EN_DPLL_LPBYPASS		0x5
--#define OMAP4XXX_EN_DPLL_FRBYPASS		0x6
--#define OMAP4XXX_EN_DPLL_LOCKED			0x7
- 
- /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
- #define DPLL_LOW_POWER_STOP	0x1
-@@ -132,7 +129,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
- 			       const char *core_ck_name,
- 			       const char *mpu_ck_name);
- 
--extern u8 cpu_mask;
-+extern u16 cpu_mask;
- 
- extern const struct clkops clkops_omap2_dflt_wait;
- extern const struct clkops clkops_dummy;
-diff --git a/arch/arm/mach-omap2/clock33xx.h b/arch/arm/mach-omap2/clock33xx.h
-new file mode 100644
-index 0000000..8409288
---- /dev/null
-+++ b/arch/arm/mach-omap2/clock33xx.h
-@@ -0,0 +1,37 @@
-+/*
-+ * AM33XX clock function prototypes and macros.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK33XX_H
-+#define __ARCH_ARM_MACH_OMAP2_CLOCK33XX_H
-+
-+#define AM33XX_MAX_DPLL_MULT  2047
-+#define AM33XX_MAX_DPLL_DIV   128
-+
-+
-+int am33xx_clk_init(void);
-+
-+/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
-+     physically present, in such a case HWMOD enabling of
-+     clock would be failure with default parent. And timer
-+     probe thinks clock is already enabled, this leads to
-+     crash upon accessing timer 3 & 6 registers in probe.
-+     Fix by setting parent of both these timers to master
-+     oscillator clock.
-+ */
-+static inline void am33xx_init_timer_parent(struct clk *clk)
-+{
-+	omap2_clksel_set_parent(clk, clk->parent);
-+}
-+#endif
-diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
-new file mode 100644
-index 0000000..a3d7776
---- /dev/null
-+++ b/arch/arm/mach-omap2/clock33xx_data.c
-@@ -0,0 +1,2233 @@
-+/*
-+ * AM33XX Clock data
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/clk.h>
-+#include <plat/clkdev_omap.h>
-+
-+#include "control.h"
-+#include "clock.h"
-+#include "clock33xx.h"
-+#include "cm.h"
-+#include "cm33xx.h"
-+#include "cm-regbits-33xx.h"
-+#include "prm.h"
-+
-+/* Modulemode control */
-+#define AM33XX_MODULEMODE_HWCTRL	0
-+#define AM33XX_MODULEMODE_SWCTRL	1
-+
-+/* Root clocks */
-+static struct clk clk_32768_ck = {
-+	.name		= "clk_32768_ck",
-+	.rate		= 32768,
-+	.ops		= &clkops_null,
-+};
-+
-+/* On-Chip 32KHz RC OSC */
-+static struct clk clk_rc32k_ck = {
-+	.name		= "clk_rc32k_ck",
-+	.rate		= 32000,
-+	.ops		= &clkops_null,
-+};
-+
-+/* Crystal input clks */
-+static struct clk virt_19_2m_ck = {
-+	.name		= "virt_19_2m_ck",
-+	.rate		= 19200000,
-+	.ops		= &clkops_null,
-+};
-+
-+static struct clk virt_24m_ck = {
-+	.name		= "virt_24m_ck",
-+	.rate		= 24000000,
-+	.ops		= &clkops_null,
-+};
-+
-+static struct clk virt_25m_ck = {
-+	.name		= "virt_25m_ck",
-+	.rate		= 25000000,
-+	.ops		= &clkops_null,
-+};
-+
-+static struct clk virt_26m_ck = {
-+	.name		= "virt_26m_ck",
-+	.rate		= 26000000,
-+	.ops		= &clkops_null,
-+};
-+
-+static struct clk tclkin_ck = {
-+	.name		= "tclkin_ck",
-+	.rate		= 12000000,
-+	.ops		= &clkops_null,
-+};
-+
-+static const struct clksel_rate div_1_0_rates[] = {
-+	{ .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
-+	{ .div = 0 },
-+};
-+
-+static const struct clksel_rate div_1_1_rates[] = {
-+	{ .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
-+	{ .div = 0 },
-+};
-+
-+static const struct clksel_rate div_1_2_rates[] = {
-+	{ .div = 1, .val = 2, .flags = RATE_IN_AM33XX },
-+	{ .div = 0 },
-+};
-+
-+static const struct clksel_rate div_1_3_rates[] = {
-+	{ .div = 1, .val = 3, .flags = RATE_IN_AM33XX },
-+	{ .div = 0 },
-+};
-+
-+static const struct clksel_rate div_1_4_rates[] = {
-+	{ .div = 1, .val = 4, .flags = RATE_IN_AM33XX },
-+	{ .div = 0 },
-+};
-+
-+static const struct clksel_rate div31_1to31_rates[] = {
-+	{ .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
-+	{ .div = 2, .val = 2, .flags = RATE_IN_AM33XX },
-+	{ .div = 3, .val = 3, .flags = RATE_IN_AM33XX },
-+	{ .div = 4, .val = 4, .flags = RATE_IN_AM33XX },
-+	{ .div = 5, .val = 5, .flags = RATE_IN_AM33XX },
-+	{ .div = 6, .val = 6, .flags = RATE_IN_AM33XX },
-+	{ .div = 7, .val = 7, .flags = RATE_IN_AM33XX },
-+	{ .div = 8, .val = 8, .flags = RATE_IN_AM33XX },
-+	{ .div = 9, .val = 9, .flags = RATE_IN_AM33XX },
-+	{ .div = 10, .val = 10, .flags = RATE_IN_AM33XX },
-+	{ .div = 11, .val = 11, .flags = RATE_IN_AM33XX },
-+	{ .div = 12, .val = 12, .flags = RATE_IN_AM33XX },
-+	{ .div = 13, .val = 13, .flags = RATE_IN_AM33XX },
-+	{ .div = 14, .val = 14, .flags = RATE_IN_AM33XX },
-+	{ .div = 15, .val = 15, .flags = RATE_IN_AM33XX },
-+	{ .div = 16, .val = 16, .flags = RATE_IN_AM33XX },
-+	{ .div = 17, .val = 17, .flags = RATE_IN_AM33XX },
-+	{ .div = 18, .val = 18, .flags = RATE_IN_AM33XX },
-+	{ .div = 19, .val = 19, .flags = RATE_IN_AM33XX },
-+	{ .div = 20, .val = 20, .flags = RATE_IN_AM33XX },
-+	{ .div = 21, .val = 21, .flags = RATE_IN_AM33XX },
-+	{ .div = 22, .val = 22, .flags = RATE_IN_AM33XX },
-+	{ .div = 23, .val = 23, .flags = RATE_IN_AM33XX },
-+	{ .div = 24, .val = 24, .flags = RATE_IN_AM33XX },
-+	{ .div = 25, .val = 25, .flags = RATE_IN_AM33XX },
-+	{ .div = 26, .val = 26, .flags = RATE_IN_AM33XX },
-+	{ .div = 27, .val = 27, .flags = RATE_IN_AM33XX },
-+	{ .div = 28, .val = 28, .flags = RATE_IN_AM33XX },
-+	{ .div = 29, .val = 29, .flags = RATE_IN_AM33XX },
-+	{ .div = 30, .val = 30, .flags = RATE_IN_AM33XX },
-+	{ .div = 31, .val = 31, .flags = RATE_IN_AM33XX },
-+	{ .div = 0 },
-+};
-+
-+/* Oscillator clock */
-+/* 19.2, 24, 25 or 26 MHz */
-+static const struct clksel sys_clkin_sel[] = {
-+	{ .parent = &virt_19_2m_ck, .rates = div_1_0_rates },
-+	{ .parent = &virt_24m_ck, .rates = div_1_1_rates },
-+	{ .parent = &virt_25m_ck, .rates = div_1_2_rates },
-+	{ .parent = &virt_26m_ck, .rates = div_1_3_rates },
-+	{ .parent = NULL },
-+};
-+
-+/* sys_clk_in */
-+static struct clk sys_clkin_ck = {
-+	.name		= "sys_clkin_ck",
-+	.parent		= &virt_24m_ck,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel_reg	= AM33XX_CTRL_REGADDR(0x40),	/* CONTROL_STATUS */
-+	.clksel_mask	= (0x3 << 22),
-+	.clksel		= sys_clkin_sel,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+/* DPLL_CORE */
-+static struct dpll_data dpll_core_dd = {
-+	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_CORE,
-+	.clk_bypass	= &sys_clkin_ck,
-+	.clk_ref	= &sys_clkin_ck,
-+	.control_reg	= AM33XX_CM_CLKMODE_DPLL_CORE,
-+	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-+	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_CORE,
-+	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-+	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-+	.enable_mask	= AM33XX_DPLL_EN_MASK,
-+	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-+	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
-+	.max_divider	= AM33XX_MAX_DPLL_DIV,
-+	.min_divider	= 1,
-+};
-+
-+/* CLKDCOLDO output */
-+static struct clk dpll_core_ck = {
-+	.name		= "dpll_core_ck",
-+	.parent		= &sys_clkin_ck,
-+	.dpll_data	= &dpll_core_dd,
-+	.init		= &omap2_init_dpll_parent,
-+	.ops		= &clkops_omap3_core_dpll_ops,
-+	.recalc		= &omap3_dpll_recalc,
-+};
-+
-+static struct clk dpll_core_x2_ck = {
-+	.name		= "dpll_core_x2_ck",
-+	.parent		= &dpll_core_ck,
-+	.flags		= CLOCK_CLKOUTX2,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap3_clkoutx2_recalc,
-+};
-+
-+
-+static const struct clksel dpll_core_m4_div[] = {
-+	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk dpll_core_m4_ck = {
-+	.name		= "dpll_core_m4_ck",
-+	.parent		= &dpll_core_x2_ck,
-+	.clksel		= dpll_core_m4_div,
-+	.clksel_reg	= AM33XX_CM_DIV_M4_DPLL_CORE,
-+	.clksel_mask	= AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+	.round_rate	= &omap2_clksel_round_rate,
-+	.set_rate	= &omap2_clksel_set_rate,
-+};
-+
-+static const struct clksel dpll_core_m5_div[] = {
-+	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk dpll_core_m5_ck = {
-+	.name		= "dpll_core_m5_ck",
-+	.parent		= &dpll_core_x2_ck,
-+	.clksel		= dpll_core_m5_div,
-+	.clksel_reg	= AM33XX_CM_DIV_M5_DPLL_CORE,
-+	.clksel_mask	= AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+	.round_rate	= &omap2_clksel_round_rate,
-+	.set_rate	= &omap2_clksel_set_rate,
-+};
-+
-+static const struct clksel dpll_core_m6_div[] = {
-+	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk dpll_core_m6_ck = {
-+	.name		= "dpll_core_m6_ck",
-+	.parent		= &dpll_core_x2_ck,
-+	.clksel		= dpll_core_m6_div,
-+	.clksel_reg	= AM33XX_CM_DIV_M6_DPLL_CORE,
-+	.clksel_mask	= AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+	.round_rate	= &omap2_clksel_round_rate,
-+	.set_rate	= &omap2_clksel_set_rate,
-+};
-+
-+static struct clk sysclk1_ck = {
-+	.name		= "sysclk1_ck",
-+	.parent		= &dpll_core_m4_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk sysclk2_ck = {
-+	.name		= "sysclk2_ck",
-+	.parent		= &dpll_core_m5_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk core_clk_out = {
-+	.name		= "core_clk_out",
-+	.parent		= &dpll_core_m4_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+/* DPLL_MPU */
-+static struct dpll_data dpll_mpu_dd = {
-+	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_MPU,
-+	.clk_bypass	= &sys_clkin_ck,
-+	.clk_ref	= &sys_clkin_ck,
-+	.control_reg	= AM33XX_CM_CLKMODE_DPLL_MPU,
-+	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-+	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_MPU,
-+	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-+	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-+	.enable_mask	= AM33XX_DPLL_EN_MASK,
-+	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-+	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
-+	.max_divider	= AM33XX_MAX_DPLL_DIV,
-+	.min_divider	= 1,
-+};
-+
-+/* CLKOUT: fdpll/M2 */
-+static struct clk dpll_mpu_ck = {
-+	.name		= "dpll_mpu_ck",
-+	.parent		= &sys_clkin_ck,
-+	.dpll_data	= &dpll_mpu_dd,
-+	.init		= &omap2_init_dpll_parent,
-+	.ops		= &clkops_omap3_noncore_dpll_ops,
-+	.recalc		= &omap3_dpll_recalc,
-+	.round_rate	= &omap2_dpll_round_rate,
-+	.set_rate	= &omap3_noncore_dpll_set_rate,
-+};
-+
-+/*
-+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
-+ * and ALT_CLK1/2)
-+ */
-+static const struct clksel dpll_mpu_m2_div[] = {
-+	{ .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk dpll_mpu_m2_ck = {
-+	.name		= "dpll_mpu_m2_ck",
-+	.parent		= &dpll_mpu_ck,
-+	.clksel		= dpll_mpu_m2_div,
-+	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_MPU,
-+	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+	.round_rate	= &omap2_clksel_round_rate,
-+	.set_rate	= &omap2_clksel_set_rate,
-+};
-+
-+static struct clk mpu_fck = {
-+	.name		= "mpu_fck",
-+	.clkdm_name	= "mpu_clkdm",
-+	.parent		= &dpll_mpu_m2_ck,
-+	.ops		= &clkops_omap2_dflt,
-+	.enable_reg	= AM33XX_CM_MPU_MPU_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.recalc		= &followparent_recalc,
-+	.flags		= ENABLE_ON_INIT,
-+};
-+
-+/* DPLL_DDR */
-+static struct dpll_data dpll_ddr_dd = {
-+	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DDR,
-+	.clk_bypass	= &sys_clkin_ck,
-+	.clk_ref	= &sys_clkin_ck,
-+	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DDR,
-+	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-+	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DDR,
-+	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-+	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-+	.enable_mask	= AM33XX_DPLL_EN_MASK,
-+	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-+	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
-+	.max_divider	= AM33XX_MAX_DPLL_DIV,
-+	.min_divider	= 1,
-+};
-+
-+/* CLKOUT: fdpll/M2 */
-+static struct clk dpll_ddr_ck = {
-+	.name		= "dpll_ddr_ck",
-+	.parent		= &sys_clkin_ck,
-+	.dpll_data	= &dpll_ddr_dd,
-+	.init		= &omap2_init_dpll_parent,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap3_dpll_recalc,
-+};
-+
-+/*
-+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
-+ * and ALT_CLK1/2)
-+ */
-+static const struct clksel dpll_ddr_m2_div[] = {
-+	{ .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk dpll_ddr_m2_ck = {
-+	.name		= "dpll_ddr_m2_ck",
-+	.parent		= &dpll_ddr_ck,
-+	.clksel		= dpll_ddr_m2_div,
-+	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_DDR,
-+	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+	.round_rate	= &omap2_clksel_round_rate,
-+	.set_rate	= &omap2_clksel_set_rate,
-+};
-+
-+static struct clk ddr_pll_clk = {
-+	.name		= "ddr_pll_clk",
-+	.parent		= &dpll_ddr_m2_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk emif_fck = {
-+	.name		= "emif_fck",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &ddr_pll_clk,
-+	.ops		= &clkops_omap2_dflt,
-+	.enable_reg	= AM33XX_CM_PER_EMIF_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 2,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+	.flags		= ENABLE_ON_INIT,
-+};
-+
-+/* DPLL_DISP */
-+static struct dpll_data dpll_disp_dd = {
-+	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DISP,
-+	.clk_bypass	= &sys_clkin_ck,
-+	.clk_ref	= &sys_clkin_ck,
-+	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DISP,
-+	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-+	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DISP,
-+	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-+	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-+	.enable_mask	= AM33XX_DPLL_EN_MASK,
-+	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-+	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
-+	.max_divider	= AM33XX_MAX_DPLL_DIV,
-+	.min_divider	= 1,
-+};
-+
-+/* CLKOUT: fdpll/M2 */
-+static struct clk dpll_disp_ck = {
-+	.name		= "dpll_disp_ck",
-+	.parent		= &sys_clkin_ck,
-+	.dpll_data	= &dpll_disp_dd,
-+	.init		= &omap2_init_dpll_parent,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap3_dpll_recalc,
-+	.round_rate	= &omap2_dpll_round_rate,
-+	.set_rate	= &omap3_noncore_dpll_set_rate,
-+};
-+
-+/*
-+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
-+ * and ALT_CLK1/2)
-+ */
-+static const struct clksel dpll_disp_m2_div[] = {
-+	{ .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk dpll_disp_m2_ck = {
-+	.name		= "dpll_disp_m2_ck",
-+	.parent		= &dpll_disp_ck,
-+	.clksel		= dpll_disp_m2_div,
-+	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_DISP,
-+	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+	.round_rate	= &omap2_clksel_round_rate,
-+	.set_rate	= &omap2_clksel_set_rate,
-+};
-+
-+static struct clk disp_pll_clk = {
-+	.name		= "disp_pll_clk",
-+	.parent		= &dpll_disp_m2_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+/* DPLL_PER */
-+static struct dpll_data dpll_per_dd = {
-+	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_PERIPH,
-+	.clk_bypass	= &sys_clkin_ck,
-+	.clk_ref	= &sys_clkin_ck,
-+	.control_reg	= AM33XX_CM_CLKMODE_DPLL_PER,
-+	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-+	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_PER,
-+	.mult_mask	= AM33XX_DPLL_MULT_PERIPH_MASK,
-+	.div1_mask	= AM33XX_DPLL_PER_DIV_MASK,
-+	.enable_mask	= AM33XX_DPLL_EN_MASK,
-+	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-+	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
-+	.max_divider	= AM33XX_MAX_DPLL_DIV,
-+	.min_divider	= 1,
-+	.flags		= DPLL_J_TYPE,
-+};
-+
-+/* CLKDCOLDO */
-+static struct clk dpll_per_ck = {
-+	.name		= "dpll_per_ck",
-+	.parent		= &sys_clkin_ck,
-+	.dpll_data	= &dpll_per_dd,
-+	.init		= &omap2_init_dpll_parent,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap3_dpll_recalc,
-+	.round_rate	= &omap2_dpll_round_rate,
-+	.set_rate	= &omap3_noncore_dpll_set_rate,
-+};
-+
-+/* CLKOUT: fdpll/M2 */
-+static const struct clksel dpll_per_m2_div[] = {
-+	{ .parent = &dpll_per_ck, .rates = div31_1to31_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk dpll_per_m2_ck = {
-+	.name		= "dpll_per_m2_ck",
-+	.parent		= &dpll_per_ck,
-+	.clksel		= dpll_per_m2_div,
-+	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_PER,
-+	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+	.round_rate	= &omap2_clksel_round_rate,
-+	.set_rate	= &omap2_clksel_set_rate,
-+};
-+
-+static struct clk per_192mhz_clk = {
-+	.name		= "per_192mhz_clk",
-+	.parent		= &dpll_per_m2_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk usb_pll_clk = {
-+	.name		= "usb_pll_clk",
-+	.parent		= &dpll_per_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk core_100mhz_ck = {
-+	.name		= "core_100mhz_ck",
-+	.parent		= &sysclk1_ck,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 2,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk l3_aon_gclk = {
-+	.name		= "l3_aon_gclk",
-+	.parent		= &sysclk1_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l4_wkup_aon_gclk = {
-+	.name		= "l4_wkup_aon_gclk",
-+	.clkdm_name	= "l4_wkup_aon_clkdm",
-+	.parent		= &sysclk1_ck,
-+	.enable_reg	= AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 2,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l3_gclk = {
-+	.name		= "l3_gclk",
-+	.parent		= &sysclk1_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l3_ick = {
-+	.name		= "l3_ick",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &l3_gclk,
-+	.enable_reg	= AM33XX_CM_PER_L3_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.flags		= ENABLE_ON_INIT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l3_instr_ick = {
-+	.name		= "l3_instr_ick",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &l3_gclk,
-+	.enable_reg	= AM33XX_CM_PER_L3_INSTR_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.flags		= ENABLE_ON_INIT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l4_wkup_gclk = {
-+	.name		= "l4_wkup_gclk",
-+	.parent		= &sysclk1_ck,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 2,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk l4hs_gclk = {
-+	.name		= "l4hs_gclk",
-+	.parent		= &sysclk1_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gfx_l3_gclk = {
-+	.name		= "gfx_l3_gclk",
-+	.clkdm_name	= "gfx_l3_clkdm",
-+	.parent		= &sysclk1_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk debug_clka_gclk = {
-+	.name		= "debug_clka_gclk",
-+	.parent		= &sysclk1_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l4_rtc_gclk = {
-+	.name		= "l4_rtc_gclk",
-+	.parent		= &sysclk1_ck,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 2,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk rtc_ick = {
-+	.name		= "rtc_ick",
-+	.parent		= &l4_rtc_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l3s_gclk = {
-+	.name		= "l3s_gclk",
-+	.parent		= &core_100mhz_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l4fw_gclk = {
-+	.name		= "l4fw_gclk",
-+	.parent		= &core_100mhz_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l4ls_gclk = {
-+	.name		= "l4ls_gclk",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &core_100mhz_ck,
-+	.enable_reg	= AM33XX_CM_PER_L4LS_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk clk_24mhz = {
-+	.name		= "clk_24mhz",
-+	.parent		= &per_192mhz_clk,
-+	.fixed_div	= 8,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk l4_cefuse_gclk = {
-+	.name		= "l4_cefsue_gclk",
-+	.parent		= &core_100mhz_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk cefuse_iclk = {
-+	.name		= "cefuse_iclk",
-+	.clkdm_name	= "l4_cefuse_clkdm",
-+	.parent		= &l4_cefuse_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk cefuse_fck = {
-+	.name		= "cefuse_fck",
-+	.clkdm_name	= "l4_cefuse_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.enable_reg	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk sysclk_div_ck = {
-+	.name		= "sysclk_div_ck",
-+	.parent		= &dpll_core_m4_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk adc_tsc_fck = {
-+	.name		= "adc_tsc_fck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk adc_tsc_ick = {
-+	.name		= "adc_tsc_ick",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &l4_wkup_gclk,
-+	.enable_reg	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk aes0_fck = {
-+	.name		= "aes0_fck",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &l3_gclk,
-+	.enable_reg	= AM33XX_CM_PER_AES0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+/*
-+ * clkdiv32 is generated from fixed division of 732.4219
-+ */
-+static struct clk clkdiv32k_ick = {
-+	.name		= "clkdiv32k_ick",
-+	.clkdm_name	= "clk_24mhz_clkdm",
-+	.rate		= 32768,
-+	.parent		= &clk_24mhz,
-+	.enable_reg	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+};
-+
-+static struct clk clk_32khz_ck = {
-+	.name		= "clk_32khz_ck",
-+	.clkdm_name	= "clk_24mhz_clkdm",
-+	.parent		= &clkdiv32k_ick,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk control_fck = {
-+	.name		= "control_fck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &l4_wkup_gclk,
-+	.enable_reg	= AM33XX_CM_WKUP_CONTROL_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk dcan0_ick = {
-+	.name		= "dcan0_ick",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk dcan0_fck = {
-+	.name		= "dcan0_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.enable_reg	= AM33XX_CM_PER_DCAN0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk dcan1_ick = {
-+	.name		= "dcan1_ick",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk dcan1_fck = {
-+	.name		= "dcan1_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.enable_reg	= AM33XX_CM_PER_DCAN1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk debugss_ick = {
-+	.name		= "debugss_ick",
-+	.clkdm_name	= "l3_aon_clkdm",
-+	.parent		= &l3_aon_gclk,
-+	.ops		= &clkops_omap2_dflt,
-+	.enable_reg	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk elm_fck = {
-+	.name		= "elm_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_ELM_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk emif_fw_fck = {
-+	.name		= "emif_fw_fck",
-+	.clkdm_name	= "l4fw_clkdm",
-+	.parent		= &l4fw_gclk,
-+	.enable_reg	= AM33XX_CM_PER_EMIF_FW_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk epwmss0_fck = {
-+	.name		= "epwmss0_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_EPWMSS0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk epwmss1_fck = {
-+	.name		= "epwmss1_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_EPWMSS1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk epwmss2_fck = {
-+	.name		= "epwmss2_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_EPWMSS2_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gpmc_fck = {
-+	.name		= "gpmc_fck",
-+	.clkdm_name	= "l3s_clkdm",
-+	.parent		= &l3s_gclk,
-+	.enable_reg	= AM33XX_CM_PER_GPMC_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk i2c1_ick = {
-+	.name		= "i2c1_ick",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &l4_wkup_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk i2c1_fck = {
-+	.name		= "i2c1_fck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_WKUP_I2C0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk i2c2_ick = {
-+	.name		= "i2c2_ick",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk i2c2_fck = {
-+	.name		= "i2c2_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_I2C1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk i2c3_ick = {
-+	.name		= "i2c3_ick",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk i2c3_fck = {
-+	.name		= "i2c3_fck",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_I2C2_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk ieee5000_fck = {
-+	.name		= "ieee5000_fck",
-+	.clkdm_name	= "l3s_clkdm",
-+	.parent		= &l3s_gclk,
-+	.enable_reg	= AM33XX_CM_PER_IEEE5000_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l4hs_ick = {
-+	.name		= "l4hs_ick",
-+	.clkdm_name	= "l4hs_clkdm",
-+	.parent		= &l4hs_gclk,
-+	.enable_reg	= AM33XX_CM_PER_L4HS_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.flags		= ENABLE_ON_INIT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l4wkup_ick = {
-+	.name		= "l4wkup_ick",
-+	.clkdm_name	= "l4_wkup_aon_clkdm",
-+	.parent		= &l4_wkup_aon_gclk,
-+	.enable_reg	= AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.flags		= ENABLE_ON_INIT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l4fw_ick = {
-+	.name		= "l4fw_ick",
-+	.clkdm_name	= "l4fw_clkdm",
-+	.parent		= &core_100mhz_ck,
-+	.enable_reg	= AM33XX_CM_PER_L4FW_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.flags		= ENABLE_ON_INIT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk l4ls_ick = {
-+	.name		= "l4ls_ick",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_L4LS_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.flags		= ENABLE_ON_INIT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mailbox0_fck = {
-+	.name		= "mailbox0_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_MAILBOX0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mcasp0_ick = {
-+	.name		= "mcasp0_ick",
-+	.parent		= &l3s_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mcasp0_fck = {
-+	.name		= "mcasp0_fck",
-+	.clkdm_name	= "l3s_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.enable_reg	= AM33XX_CM_PER_MCASP0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mcasp1_ick = {
-+	.name		= "mcasp1_ick",
-+	.parent		= &l3s_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mcasp1_fck = {
-+	.name		= "mcasp1_fck",
-+	.clkdm_name	= "l3s_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.enable_reg	= AM33XX_CM_PER_MCASP1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mlb_fck = {
-+	.name		= "mlb_fck",
-+	.ops		= &clkops_omap2_dflt,
-+	.enable_reg	= AM33XX_CM_PER_MLB_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &sysclk_div_ck,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mmu_fck = {
-+	.name		= "mmu_fck",
-+	.clkdm_name	= "gfx_l3_clkdm",
-+	.parent		= &gfx_l3_gclk,
-+	.ops		= &clkops_omap2_dflt,
-+	.enable_reg	= AM33XX_CM_GFX_MMUDATA_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk ocmcram_ick = {
-+	.name		= "ocmcram_ick",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &l3_gclk,
-+	.enable_reg	= AM33XX_CM_PER_OCMCRAM_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk ocpwp_fck = {
-+	.name		= "ocpwp_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_OCPWP_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk pka_fck = {
-+	.name		= "pka_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_PKA_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk rng_fck = {
-+	.name		= "rng_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_RNG_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk rtc_fck = {
-+	.name		= "rtc_fck",
-+	.clkdm_name	= "l4_rtc_clkdm",
-+	.parent		= &clk_32768_ck,
-+	.enable_reg	= AM33XX_CM_RTC_RTC_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk sha0_fck = {
-+	.name		= "sha0_fck",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &l3_gclk,
-+	.enable_reg	= AM33XX_CM_PER_SHA0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk smartreflex0_ick = {
-+	.name		= "smartreflex0_ick",
-+	.parent		= &l4_wkup_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk smartreflex0_fck = {
-+	.name		= "smartreflex0_fck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.enable_reg	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk smartreflex1_ick = {
-+	.name		= "smartreflex1_ick",
-+	.parent		= &l4_wkup_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk smartreflex1_fck = {
-+	.name		= "smartreflex1_fck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.enable_reg	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk spi0_ick = {
-+	.name		= "spi0_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk spi0_fck = {
-+	.name		= "spi0_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_SPI0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk spi1_ick = {
-+	.name		= "spi1_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk spi1_fck = {
-+	.name		= "spi1_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_SPI1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk spinlock_fck = {
-+	.name		= "spinlock_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_SPINLOCK_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk clk_32khz_timer = {
-+	.name		= "clk_32khz_timer",
-+	.parent		= &clk_32khz_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+/* Timers */
-+
-+/* Secure Timer: Used only to disable the clocks and for completeness */
-+static const struct clksel timer0_clkmux_sel[] = {
-+	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-+	{ .parent = &clk_32khz_ck, .rates = div_1_1_rates },
-+	{ .parent = &sys_clkin_ck, .rates = div_1_2_rates },
-+	{ .parent = &tclkin_ck, .rates = div_1_3_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk timer0_ick = {
-+	.name		= "timer0_ick",
-+	.parent		= &l4_wkup_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk timer0_fck = {
-+	.name		= "timer0_fck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &clk_rc32k_ck,
-+	.clksel		= timer0_clkmux_sel,
-+	.enable_reg	= AM33XX_CM_WKUP_TIMER0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CTRL_REGADDR(0x01BC),
-+	.clksel_mask	= (0x3 << 4),
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static const struct clksel timer1_clkmux_sel[] = {
-+	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-+	{ .parent = &clk_32khz_ck, .rates = div_1_1_rates },
-+	{ .parent = &tclkin_ck, .rates = div_1_2_rates },
-+	{ .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
-+	{ .parent = &clk_32768_ck, .rates = div_1_4_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk timer1_ick = {
-+	.name		= "timer1_ick",
-+	.parent		= &l4_wkup_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk timer1_fck = {
-+	.name		= "timer1_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= timer1_clkmux_sel,
-+	.enable_reg	= AM33XX_CM_WKUP_TIMER1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CLKSEL_TIMER1MS_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_2_MASK,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+static const struct clksel timer2_to_7_clk_sel[] = {
-+	{ .parent = &tclkin_ck, .rates = div_1_0_rates },
-+	{ .parent = &sys_clkin_ck, .rates = div_1_1_rates },
-+	{ .parent = &clk_32khz_timer, .rates = div_1_2_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk timer2_ick = {
-+	.name		= "timer2_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk timer2_fck = {
-+	.name		= "timer2_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= timer2_to_7_clk_sel,
-+	.enable_reg	= AM33XX_CM_PER_TIMER2_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CLKSEL_TIMER2_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+static struct clk timer3_ick = {
-+	.name		= "timer3_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk timer3_fck = {
-+	.name		= "timer3_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.init		= &am33xx_init_timer_parent,
-+	.clksel		= timer2_to_7_clk_sel,
-+	.enable_reg	= AM33XX_CM_PER_TIMER3_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CLKSEL_TIMER3_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+static struct clk timer4_ick = {
-+	.name		= "timer4_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk timer4_fck = {
-+	.name		= "timer4_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= timer2_to_7_clk_sel,
-+	.enable_reg	= AM33XX_CM_PER_TIMER4_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CLKSEL_TIMER4_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+static struct clk timer5_ick = {
-+	.name		= "timer5_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk timer5_fck = {
-+	.name		= "timer5_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= timer2_to_7_clk_sel,
-+	.enable_reg	= AM33XX_CM_PER_TIMER5_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CLKSEL_TIMER5_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+static struct clk timer6_ick = {
-+	.name		= "timer6_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk timer6_fck = {
-+	.name		= "timer6_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.init		= &am33xx_init_timer_parent,
-+	.clksel		= timer2_to_7_clk_sel,
-+	.enable_reg	= AM33XX_CM_PER_TIMER6_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CLKSEL_TIMER6_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+static struct clk timer7_ick = {
-+	.name		= "timer7_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk timer7_fck = {
-+	.name		= "timer7_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &sys_clkin_ck,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= timer2_to_7_clk_sel,
-+	.enable_reg	= AM33XX_CM_PER_TIMER7_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CLKSEL_TIMER7_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+static struct clk tpcc_ick = {
-+	.name		= "tpcc_ick",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &l3_gclk,
-+	.enable_reg	= AM33XX_CM_PER_TPCC_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk tptc0_ick = {
-+	.name		= "tptc0_ick",
-+	.parent		= &l3_gclk,
-+	.clkdm_name	= "l3_clkdm",
-+	.enable_reg	= AM33XX_CM_PER_TPTC0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk tptc1_ick = {
-+	.name		= "tptc1_ick",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &l3_gclk,
-+	.enable_reg	= AM33XX_CM_PER_TPTC1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk tptc2_ick = {
-+	.name		= "tptc2_ick",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &l3_gclk,
-+	.enable_reg	= AM33XX_CM_PER_TPTC2_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk uart1_ick = {
-+	.name		= "uart1_ick",
-+	.parent		= &l4_wkup_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk uart1_fck = {
-+	.name		= "uart1_fck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_WKUP_UART0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk uart2_ick = {
-+	.name		= "uart2_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk uart2_fck = {
-+	.name		= "uart2_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_UART1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk uart3_ick = {
-+	.name		= "uart3_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk uart3_fck = {
-+	.name		= "uart3_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_UART2_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk uart4_ick = {
-+	.name		= "uart4_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk uart4_fck = {
-+	.name		= "uart4_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_UART3_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk uart5_ick = {
-+	.name		= "uart5_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk uart5_fck = {
-+	.name		= "uart5_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_UART4_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk uart6_ick = {
-+	.name		= "uart6_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk uart6_fck = {
-+	.name		= "uart6_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_UART5_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.fixed_div	= 4,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk wkup_m3_fck = {
-+	.name		= "wkup_m3_fck",
-+	.clkdm_name	= "l4_wkup_aon_clkdm",
-+	.parent		= &l4_wkup_aon_gclk,
-+	.enable_reg	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk cpsw_250mhz_clk = {
-+	.name		= "cpsw_250mhz_clk",
-+	.clkdm_name	= "l4hs_clkdm",
-+	.parent		= &sysclk2_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk cpsw_125mhz_gclk = {
-+	.name		= "cpsw_125mhz_gclk",
-+	.clkdm_name	= "cpsw_125mhz_clkdm",
-+	.parent		= &sysclk2_ck,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 2,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+/*
-+ * TODO: As per clock tree @OPP50 /2 is used, but there is not register
-+ * to configure this. @ normal OPP, /5 is used - 250MHz/5 = 50MHz
-+ */
-+static struct clk cpsw_50mhz_clk = {
-+	.name		= "cpsw_50mhz_clk",
-+	.clkdm_name	= "l4hs_clkdm",
-+	.parent		= &sysclk2_ck,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 5,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk cpsw_5mhz_clk = {
-+	.name		= "cpsw_5mhz_clk",
-+	.clkdm_name	= "l4hs_clkdm",
-+	.parent		= &cpsw_50mhz_clk,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 10,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk cpgmac0_ick = {
-+	.name		= "cpgmac0_ick",
-+	.clkdm_name	= "cpsw_125mhz_clkdm",
-+	.ops		= &clkops_omap2_dflt,
-+	.enable_reg	= AM33XX_CM_PER_CPGMAC0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.parent		= &cpsw_125mhz_gclk,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
-+	{ .parent = &sysclk2_ck, .rates = div_1_0_rates },
-+	{ .parent = &sysclk1_ck, .rates = div_1_1_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk cpsw_cpts_rft_clk = {
-+	.name		= "cpsw_cpts_rft_clk",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &dpll_core_m5_ck,
-+	.clksel		= cpsw_cpts_rft_clkmux_sel,
-+	.clksel_reg	= AM33XX_CM_CPTS_RFT_CLKSEL,
-+	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk usbotg_ick = {
-+	.name		= "usbotg_ick",
-+	.clkdm_name	= "l3s_clkdm",
-+	.parent		= &l3s_gclk,
-+	.ops		= &clkops_omap2_dflt,
-+	.enable_reg	= AM33XX_CM_PER_USB0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk usbotg_fck = {
-+	.name		= "usbotg_fck",
-+	.clkdm_name	= "l3s_clkdm",
-+	.parent		= &usb_pll_clk,
-+	.enable_reg	= AM33XX_CM_CLKDCOLDO_DPLL_PER,
-+	.enable_bit	= AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+/* gpio */
-+static const struct clksel gpio0_dbclk_mux_sel[] = {
-+	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-+	{ .parent = &clk_32768_ck, .rates = div_1_1_rates },
-+	{ .parent = &clk_32khz_timer, .rates = div_1_2_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk gpio0_dbclk_mux_ck = {
-+	.name		= "gpio0_dbclk_mux_ck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &clk_rc32k_ck,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= gpio0_dbclk_mux_sel,
-+	.clksel_reg	= AM33XX_CLKSEL_GPIO0_DBCLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+static struct clk gpio0_dbclk = {
-+	.name		= "gpio0_dbclk",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &gpio0_dbclk_mux_ck,
-+	.enable_reg	= AM33XX_CM_WKUP_GPIO0_CLKCTRL,
-+	.enable_bit	= AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gpio0_ick = {
-+	.name		= "gpio0_ick",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &l4_wkup_gclk,
-+	.enable_reg	= AM33XX_CM_WKUP_GPIO0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gpio1_dbclk = {
-+	.name		= "gpio1_dbclk",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &clkdiv32k_ick,
-+	.enable_reg	= AM33XX_CM_PER_GPIO1_CLKCTRL,
-+	.enable_bit	= AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gpio1_ick = {
-+	.name		= "gpio1_ick",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_GPIO1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gpio2_dbclk = {
-+	.name		= "gpio2_dbclk",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &clkdiv32k_ick,
-+	.enable_reg	= AM33XX_CM_PER_GPIO2_CLKCTRL,
-+	.enable_bit	= AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gpio2_ick = {
-+	.name		= "gpio2_ick",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_GPIO2_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gpio3_dbclk = {
-+	.name		= "gpio3_dbclk",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &clkdiv32k_ick,
-+	.enable_reg	= AM33XX_CM_PER_GPIO3_CLKCTRL,
-+	.enable_bit	= AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gpio3_ick = {
-+	.name		= "gpio3_ick",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &l4ls_gclk,
-+	.enable_reg	= AM33XX_CM_PER_GPIO3_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static const struct clksel pruss_ocp_clk_mux_sel[] = {
-+	{ .parent = &l3_gclk, .rates = div_1_0_rates },
-+	{ .parent = &disp_pll_clk, .rates = div_1_1_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk pruss_ocp_gclk = {
-+	.name		= "pruss_ocp_gclk",
-+	.parent		= &l3_gclk,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= pruss_ocp_clk_mux_sel,
-+	.clksel_reg	= AM33XX_CLKSEL_PRUSS_OCP_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk pruss_iep_gclk = {
-+	.name		= "pruss_iep_gclk",
-+	.clkdm_name	= "pruss_ocp_clkdm",
-+	.parent		= &l3_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk pruss_uart_gclk = {
-+	.name		= "pruss_uart_gclk",
-+	.clkdm_name	= "pruss_ocp_clkdm",
-+	.parent		= &per_192mhz_clk,
-+	.enable_reg	= AM33XX_CM_PER_PRUSS_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk lcdc_ick = {
-+	.name		= "lcdc_ick",
-+	.clkdm_name	= "l3_clkdm",
-+	.parent		= &sysclk1_ck,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static const struct clksel lcd_clk_mux_sel[] = {
-+	{ .parent = &disp_pll_clk, .rates = div_1_0_rates },
-+	{ .parent = &sysclk2_ck, .rates = div_1_1_rates },
-+	{ .parent = &per_192mhz_clk, .rates = div_1_2_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk lcd_gclk = {
-+	.name		= "lcd_gclk",
-+	.parent		= &disp_pll_clk,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= lcd_clk_mux_sel,
-+	.clksel_reg	= AM33XX_CLKSEL_LCDC_PIXEL_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk lcdc_fck = {
-+	.name		= "lcdc_fck",
-+	.clkdm_name	= "lcdc_clkdm",
-+	.parent		= &lcd_gclk,
-+	.enable_reg	= AM33XX_CM_PER_LCDC_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mmc_clk = {
-+	.name		= "mmc_clk",
-+	.parent		= &per_192mhz_clk,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 2,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static struct clk mmc0_ick = {
-+	.name		= "mmc0_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mmc0_fck = {
-+	.name		= "mmc0_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &mmc_clk,
-+	.enable_reg	= AM33XX_CM_PER_MMC0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mmc1_ick = {
-+	.name		= "mmc1_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mmc1_fck = {
-+	.name		= "mmc1_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.parent		= &mmc_clk,
-+	.enable_reg	= AM33XX_CM_PER_MMC1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mmc2_ick = {
-+	.name		= "mmc2_ick",
-+	.parent		= &l4ls_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk mmc2_fck = {
-+	.name		= "mmc2_fck",
-+	.clkdm_name	= "l3s_clkdm",
-+	.parent		= &mmc_clk,
-+	.enable_reg	= AM33XX_CM_PER_MMC2_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static const struct clksel gfx_clksel_sel[] = {
-+	{ .parent = &sysclk1_ck, .rates = div_1_0_rates },
-+	{ .parent = &per_192mhz_clk, .rates = div_1_1_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk gfx_fclk_clksel_ck = {
-+	.name		= "gfx_fclk_clksel_ck",
-+	.parent		= &sysclk1_ck,
-+	.clksel		= gfx_clksel_sel,
-+	.ops		= &clkops_null,
-+	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
-+	.clksel_mask	= AM33XX_CLKSEL_GFX_FCLK_MASK,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+static const struct clksel_rate div_1_0_2_1_rates[] = {
-+	{ .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
-+	{ .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
-+	{ .div = 0 },
-+};
-+
-+static const struct clksel gfx_div_sel[] = {
-+	{ .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk gfx_ick = {
-+	.name		= "gfx_ick",
-+	.clkdm_name	= "gfx_l3_clkdm",
-+	.parent		= &gfx_l3_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk gfx_fclk = {
-+	.name		= "gfx_fclk",
-+	.clkdm_name	= "gfx_l3_clkdm",
-+	.parent		= &gfx_fclk_clksel_ck,
-+	.clksel		= gfx_div_sel,
-+	.enable_reg	= AM33XX_CM_GFX_GFX_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-+	.recalc		= &omap2_clksel_recalc,
-+	.round_rate	= &omap2_clksel_round_rate,
-+	.set_rate	= &omap2_clksel_set_rate,
-+	.ops		= &clkops_omap2_dflt,
-+};
-+
-+static const struct clksel sysclkout_pre_sel[] = {
-+	{ .parent = &clk_32768_ck, .rates = div_1_0_rates },
-+	{ .parent = &l3_gclk, .rates = div_1_1_rates },
-+	{ .parent = &ddr_pll_clk, .rates = div_1_2_rates },
-+	{ .parent = &per_192mhz_clk, .rates = div_1_3_rates },
-+	{ .parent = &lcd_gclk, .rates = div_1_4_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk sysclkout_pre_ck = {
-+	.name		= "sysclkout_pre_ck",
-+	.parent		= &clk_32768_ck,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= sysclkout_pre_sel,
-+	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
-+	.clksel_mask	= AM33XX_CLKOUT2SOURCE_MASK,
-+	.ops		= &clkops_null,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+/* Divide by 8 clock rates with default clock is 1/1*/
-+static const struct clksel_rate div8_rates[] = {
-+	{ .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
-+	{ .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
-+	{ .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
-+	{ .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
-+	{ .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
-+	{ .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
-+	{ .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
-+	{ .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
-+	{ .div = 0 },
-+};
-+
-+static const struct clksel clkout2_div[] = {
-+	{ .parent = &sysclkout_pre_ck, .rates = div8_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk clkout2_ck = {
-+	.name		= "clkout2_ck",
-+	.parent		= &sysclkout_pre_ck,
-+	.ops		= &clkops_omap2_dflt,
-+	.clksel		= clkout2_div,
-+	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
-+	.clksel_mask	= AM33XX_CLKOUT2DIV_MASK,
-+	.enable_reg	= AM33XX_CM_CLKOUT_CTRL,
-+	.enable_bit	= AM33XX_CLKOUT2EN_SHIFT,
-+	.recalc		= &omap2_clksel_recalc,
-+	.round_rate	= &omap2_clksel_round_rate,
-+	.set_rate	= &omap2_clksel_set_rate,
-+};
-+
-+static struct clk vtp_clk = {
-+	.name		= "vtp_clk",
-+	.parent		= &sys_clkin_ck,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 2,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
-+static const struct clksel wdt_clkmux_sel[] = {
-+	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-+	{ .parent = &clk_32khz_ck, .rates = div_1_1_rates },
-+	{ .parent = NULL },
-+};
-+
-+static struct clk wdt0_ick = {
-+	.name		= "wdt0_ick",
-+	.parent		= &l4_wkup_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk wdt0_fck = {
-+	.name		= "wdt0_fck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &clk_rc32k_ck,
-+	.clksel		= wdt_clkmux_sel,
-+	.enable_reg	= AM33XX_CM_WKUP_WDT0_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk wdt1_ick = {
-+	.name		= "wdt1_ick",
-+	.parent		= &l4_wkup_gclk,
-+	.ops		= &clkops_null,
-+	.recalc		= &followparent_recalc,
-+};
-+
-+static struct clk wdt1_fck = {
-+	.name		= "wdt1_fck",
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.parent		= &clk_rc32k_ck,
-+	.init		= &omap2_init_clksel_parent,
-+	.clksel		= wdt_clkmux_sel,
-+	.enable_reg	= AM33XX_CM_WKUP_WDT1_CLKCTRL,
-+	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
-+	.clksel_reg	= AM33XX_CLKSEL_WDT1_CLK,
-+	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-+	.ops		= &clkops_omap2_dflt,
-+	.recalc		= &omap2_clksel_recalc,
-+};
-+
-+/*
-+ * Provides clock definitions for enabling bits for Time base module in
-+ * PWMSS ctrl register.
-+ */
-+
-+static struct clk ehrpwm0_tbclk = {
-+	.name		= "ehrpwm0_tbclk",
-+	.enable_reg	= AM33XX_CONTROL_PWMSS_CTRL,
-+	.enable_bit	= AM33XX_PWMSS0_TBCLKEN,
-+	.ops		= &clkops_omap2_dflt,
-+	.flags		= ENABLE_ON_INIT,
-+};
-+
-+static struct clk ehrpwm1_tbclk = {
-+	.name		= "ehrpwm1_tbclk",
-+	.enable_reg	= AM33XX_CONTROL_PWMSS_CTRL,
-+	.enable_bit	= AM33XX_PWMSS1_TBCLKEN,
-+	.ops		= &clkops_omap2_dflt,
-+	.flags		= ENABLE_ON_INIT,
-+};
-+
-+static struct clk ehrpwm2_tbclk = {
-+	.name		= "ehrpwm2_tbclk",
-+	.enable_reg	= AM33XX_CONTROL_PWMSS_CTRL,
-+	.enable_bit	= AM33XX_PWMSS2_TBCLKEN,
-+	.ops		= &clkops_omap2_dflt,
-+	.flags		= ENABLE_ON_INIT,
-+};
-+
-+
-+/*
-+ * clkdev
-+ */
-+static struct omap_clk am33xx_clks[] = {
-+	CLK(NULL,	"clk_32768_ck",		&clk_32768_ck,	CK_AM33XX),
-+	CLK(NULL,	"clk_32khz_ck",		&clk_32khz_ck,	CK_AM33XX),
-+	CLK(NULL,	"clk_rc32k_ck",		&clk_rc32k_ck,	CK_AM33XX),
-+	CLK(NULL,	"virt_19_2m_ck",	&virt_19_2m_ck,	CK_AM33XX),
-+	CLK(NULL,	"virt_24m_ck",		&virt_24m_ck,	CK_AM33XX),
-+	CLK(NULL,	"virt_25m_ck",		&virt_25m_ck,	CK_AM33XX),
-+	CLK(NULL,	"virt_26m_ck",		&virt_26m_ck,	CK_AM33XX),
-+	CLK(NULL,	"sys_clkin_ck",		&sys_clkin_ck,	CK_AM33XX),
-+	CLK(NULL,	"tclkin_ck",		&tclkin_ck,	CK_AM33XX),
-+	CLK(NULL,	"dpll_core_ck",		&dpll_core_ck,		CK_AM33XX),
-+	CLK(NULL,	"dpll_core_x2_ck",	&dpll_core_x2_ck,	CK_AM33XX),
-+	CLK(NULL,	"dpll_core_m4_ck",	&dpll_core_m4_ck,	CK_AM33XX),
-+	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck,	CK_AM33XX),
-+	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck,	CK_AM33XX),
-+	CLK(NULL,	"sysclk1_ck",		&sysclk1_ck,	CK_AM33XX),
-+	CLK(NULL,	"sysclk2_ck",		&sysclk2_ck,	CK_AM33XX),
-+	CLK(NULL,	"core_clk_out",		&core_clk_out,	CK_AM33XX),
-+	CLK(NULL,	"clk_32khz_timer",	&clk_32khz_timer, CK_AM33XX),
-+	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck,		CK_AM33XX),
-+	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck,	CK_AM33XX),
-+	CLK(NULL,	"mpu_ck",		&mpu_fck,	CK_AM33XX),
-+	CLK(NULL,	"dpll_ddr_ck",		&dpll_ddr_ck,		CK_AM33XX),
-+	CLK(NULL,	"dpll_ddr_m2_ck",	&dpll_ddr_m2_ck,	CK_AM33XX),
-+	CLK(NULL,	"ddr_pll_clk",		&ddr_pll_clk,	CK_AM33XX),
-+	CLK(NULL,	"emif_fck",		&emif_fck,	CK_AM33XX),
-+	CLK(NULL,	"emif_fw_fck",		&emif_fw_fck,	CK_AM33XX),
-+	CLK(NULL,	"dpll_disp_ck",		&dpll_disp_ck,		CK_AM33XX),
-+	CLK(NULL,	"dpll_disp_m2_ck",	&dpll_disp_m2_ck,	CK_AM33XX),
-+	CLK(NULL,	"disp_pll_clk",		&disp_pll_clk,		CK_AM33XX),
-+	CLK(NULL,	"dpll_per_ck",		&dpll_per_ck,	CK_AM33XX),
-+	CLK(NULL,	"dpll_per_m2_ck",	&dpll_per_m2_ck,	CK_AM33XX),
-+	CLK(NULL,	"per_192mhz_clk",	&per_192mhz_clk,	CK_AM33XX),
-+	CLK(NULL,	"usb_pll_clk",		&usb_pll_clk,		CK_AM33XX),
-+	CLK(NULL,	"core_100mhz_ck",	&core_100mhz_ck,	CK_AM33XX),
-+	CLK(NULL,	"l3_ick",		&l3_ick,	CK_AM33XX),
-+	CLK(NULL,	"l3_instr_ick",		&l3_instr_ick,	CK_AM33XX),
-+	CLK(NULL,	"adc_tsc_fck",		&adc_tsc_fck,	CK_AM33XX),
-+	CLK(NULL,	"adc_tsc_ick",		&adc_tsc_ick,	CK_AM33XX),
-+	CLK(NULL,	"aes0_fck",		&aes0_fck,	CK_AM33XX),
-+	CLK(NULL,	"l4_cefuse_gclk",	&l4_cefuse_gclk, CK_AM33XX),
-+	CLK(NULL,	"cefuse_fck",		&cefuse_fck,	CK_AM33XX),
-+	CLK(NULL,	"cefuse_iclk",		&cefuse_iclk,	CK_AM33XX),
-+	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick,	CK_AM33XX),
-+	CLK(NULL,	"control_fck",		&control_fck,	CK_AM33XX),
-+	CLK("cpsw.0",	NULL,			&cpgmac0_ick,	CK_AM33XX),
-+	CLK("d_can.0",	"fck",			&dcan0_fck,	CK_AM33XX),
-+	CLK("d_can.1",	"fck",			&dcan1_fck,	CK_AM33XX),
-+	CLK("d_can.0",	"ick",			&dcan0_ick,	CK_AM33XX),
-+	CLK("d_can.1",	"ick",			&dcan1_ick,	CK_AM33XX),
-+	CLK(NULL,	"debugss_ick",		&debugss_ick,	CK_AM33XX),
-+	CLK(NULL,	"elm_fck",		&elm_fck,	CK_AM33XX),
-+	CLK(NULL,	"epwmss0_fck",		&epwmss0_fck,	CK_AM33XX),
-+	CLK(NULL,	"epwmss1_fck",		&epwmss1_fck,	CK_AM33XX),
-+	CLK(NULL,	"epwmss2_fck",		&epwmss2_fck,	CK_AM33XX),
-+	CLK(NULL,	"gpio0_ick",		&gpio0_ick,	CK_AM33XX),
-+	CLK(NULL,	"gpio1_ick",		&gpio1_ick,	CK_AM33XX),
-+	CLK(NULL,	"gpio2_ick",		&gpio2_ick,	CK_AM33XX),
-+	CLK(NULL,	"gpio3_ick",		&gpio3_ick,	CK_AM33XX),
-+	CLK(NULL,	"gpmc_fck",		&gpmc_fck,	CK_AM33XX),
-+	CLK("omap_i2c.1",	"fck",		&i2c1_fck,	CK_AM33XX),
-+	CLK("omap_i2c.1",	"ick",		&i2c1_ick,	CK_AM33XX),
-+	CLK("omap_i2c.2",	"fck",		&i2c2_fck,	CK_AM33XX),
-+	CLK("omap_i2c.2",	"ick",		&i2c2_ick,	CK_AM33XX),
-+	CLK("omap_i2c.3",	"fck",		&i2c3_fck,	CK_AM33XX),
-+	CLK("omap_i2c.3",	"ick",		&i2c3_ick,	CK_AM33XX),
-+	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk,	CK_AM33XX),
-+	CLK(NULL,	"pruss_uart_gclk",	&pruss_uart_gclk,	CK_AM33XX),
-+	CLK(NULL,	"pruss_iep_gclk",	&pruss_iep_gclk,	CK_AM33XX),
-+	CLK(NULL,	"ieee5000_fck",		&ieee5000_fck,	CK_AM33XX),
-+	CLK(NULL,	"l4hs_ick",		&l4hs_ick,	CK_AM33XX),
-+	CLK(NULL,	"l4wkup_ick",		&l4wkup_ick,	CK_AM33XX),
-+	CLK(NULL,	"l4fw_ick",		&l4fw_ick,	CK_AM33XX),
-+	CLK(NULL,	"l4ls_ick",		&l4ls_ick,	CK_AM33XX),
-+	CLK("da8xx_lcdc.0",	NULL,		&lcdc_fck,	CK_AM33XX),
-+	CLK(NULL,	"mailbox0_fck",		&mailbox0_fck,	CK_AM33XX),
-+	CLK(NULL,	"mcasp1_ick",		&mcasp0_ick,	CK_AM33XX),
-+	CLK("davinci-mcasp.0",	NULL,		&mcasp0_fck,	CK_AM33XX),
-+	CLK(NULL,	"mcasp2_ick",		&mcasp1_ick,	CK_AM33XX),
-+	CLK("davinci-mcasp.1",	NULL,		&mcasp1_fck,	CK_AM33XX),
-+	CLK(NULL,	"mlb_fck",		&mlb_fck,	CK_AM33XX),
-+	CLK("omap_hsmmc.0",	"ick",		&mmc0_ick,	CK_AM33XX),
-+	CLK("omap_hsmmc.1",	"ick",		&mmc1_ick,	CK_AM33XX),
-+	CLK("omap_hsmmc.2",	"ick",		&mmc2_ick,	CK_AM33XX),
-+	CLK("omap_hsmmc.0",	"fck",		&mmc0_fck,	CK_AM33XX),
-+	CLK("omap_hsmmc.1",	"fck",		&mmc1_fck,	CK_AM33XX),
-+	CLK("omap_hsmmc.2",	"fck",		&mmc2_fck,	CK_AM33XX),
-+	CLK(NULL,	"mmu_fck",		&mmu_fck,	CK_AM33XX),
-+	CLK(NULL,	"ocmcram_ick",		&ocmcram_ick,	CK_AM33XX),
-+	CLK(NULL,	"ocpwp_fck",		&ocpwp_fck,	CK_AM33XX),
-+	CLK(NULL,	"pka_fck",		&pka_fck,	CK_AM33XX),
-+	CLK(NULL,	"rng_fck",		&rng_fck,	CK_AM33XX),
-+	CLK(NULL,	"rtc_fck",		&rtc_fck,	CK_AM33XX),
-+	CLK(NULL,	"rtc_ick",		&rtc_ick,	CK_AM33XX),
-+	CLK(NULL,	"sha0_fck",		&sha0_fck,	CK_AM33XX),
-+	CLK(NULL,	"smartreflex0_fck",	&smartreflex0_fck,	CK_AM33XX),
-+	CLK(NULL,	"smartreflex0_ick",	&smartreflex0_ick,	CK_AM33XX),
-+	CLK(NULL,	"smartreflex1_fck",	&smartreflex1_fck,	CK_AM33XX),
-+	CLK(NULL,	"smartreflex1_ick",	&smartreflex1_ick,	CK_AM33XX),
-+	CLK("omap2_mcspi.1",	"fck",		&spi0_fck,	CK_AM33XX),
-+	CLK("omap2_mcspi.2",	"fck",		&spi1_fck,	CK_AM33XX),
-+	CLK("omap2_mcspi.1",	"ick",		&spi0_ick,	CK_AM33XX),
-+	CLK("omap2_mcspi.2",	"ick",		&spi1_ick,	CK_AM33XX),
-+	CLK(NULL,	"spinlock_fck",		&spinlock_fck,	CK_AM33XX),
-+	CLK(NULL,	"gpt0_fck",		&timer0_fck,	CK_AM33XX),
-+	CLK(NULL,	"gpt1_fck",		&timer1_fck,	CK_AM33XX),
-+	CLK(NULL,	"gpt2_fck",		&timer2_fck,	CK_AM33XX),
-+	CLK(NULL,	"gpt3_fck",		&timer3_fck,	CK_AM33XX),
-+	CLK(NULL,	"gpt4_fck",		&timer4_fck,	CK_AM33XX),
-+	CLK(NULL,	"gpt5_fck",		&timer5_fck,	CK_AM33XX),
-+	CLK(NULL,	"gpt6_fck",		&timer6_fck,	CK_AM33XX),
-+	CLK(NULL,	"gpt7_fck",		&timer7_fck,	CK_AM33XX),
-+	CLK("da8xx_lcdc.0",	"lcdc_ick",	&lcdc_ick,	CK_AM33XX),
-+	CLK(NULL,	"tpcc_ick",		&tpcc_ick,	CK_AM33XX),
-+	CLK(NULL,	"tptc0_ick",		&tptc0_ick,	CK_AM33XX),
-+	CLK(NULL,	"tptc1_ick",		&tptc1_ick,	CK_AM33XX),
-+	CLK(NULL,	"tptc2_ick",		&tptc2_ick,	CK_AM33XX),
-+	CLK(NULL,	"uart1_fck",		&uart1_fck,	CK_AM33XX),
-+	CLK(NULL,	"uart2_fck",		&uart2_fck,	CK_AM33XX),
-+	CLK(NULL,	"uart3_fck",		&uart3_fck,	CK_AM33XX),
-+	CLK(NULL,	"uart4_fck",		&uart4_fck,	CK_AM33XX),
-+	CLK(NULL,	"uart5_fck",		&uart5_fck,	CK_AM33XX),
-+	CLK(NULL,	"uart6_fck",		&uart6_fck,	CK_AM33XX),
-+	CLK(NULL,	"uart1_ick",		&uart1_ick,	CK_AM33XX),
-+	CLK(NULL,	"uart2_ick",		&uart2_ick,	CK_AM33XX),
-+	CLK(NULL,	"uart3_ick",		&uart3_ick,	CK_AM33XX),
-+	CLK(NULL,	"uart4_ick",		&uart4_ick,	CK_AM33XX),
-+	CLK(NULL,	"uart5_ick",		&uart5_ick,	CK_AM33XX),
-+	CLK(NULL,	"uart6_ick",		&uart6_ick,	CK_AM33XX),
-+	CLK(NULL,	"usbotg_ick",		&usbotg_ick,	CK_AM33XX),
-+	CLK(NULL,	"usbotg_fck",		&usbotg_fck,	CK_AM33XX),
-+	CLK(NULL,	"wdt0_ick",		&wdt0_ick,	CK_AM33XX),
-+	CLK(NULL,	"wdt0_fck",		&wdt0_fck,	CK_AM33XX),
-+	CLK(NULL,	"wdt1_ick",		&wdt1_ick,	CK_AM33XX),
-+	CLK(NULL,	"wdt1_fck",		&wdt1_fck,	CK_AM33XX),
-+	CLK(NULL,	"wkup_m3_fck",		&wkup_m3_fck,	CK_AM33XX),
-+	CLK(NULL,	"l3_aon_gclk",		&l3_aon_gclk,		CK_AM33XX),
-+	CLK(NULL,	"l4_wkup_aon_gclk",	&l4_wkup_aon_gclk,	CK_AM33XX),
-+	CLK(NULL,	"l4_rtc_gclk",		&l4_rtc_gclk,		CK_AM33XX),
-+	CLK(NULL,	"l3_gclk",		&l3_gclk,		CK_AM33XX),
-+	CLK(NULL,	"gfx_l3_gclk",		&gfx_l3_gclk,		CK_AM33XX),
-+	CLK(NULL,	"l4_wkup_gclk",		&l4_wkup_gclk,		CK_AM33XX),
-+	CLK(NULL,	"l4hs_gclk",		&l4hs_gclk,		CK_AM33XX),
-+	CLK(NULL,	"l3s_gclk",		&l3s_gclk,		CK_AM33XX),
-+	CLK(NULL,	"l4fw_gclk",		&l4fw_gclk,		CK_AM33XX),
-+	CLK(NULL,	"l4ls_gclk",		&l4ls_gclk,		CK_AM33XX),
-+	CLK(NULL,	"debug_clka_gclk",	&debug_clka_gclk,	CK_AM33XX),
-+	CLK(NULL,	"clk_24mhz",		&clk_24mhz,		CK_AM33XX),
-+	CLK(NULL,	"sysclk_div_ck",	&sysclk_div_ck,		CK_AM33XX),
-+	CLK(NULL,	"cpsw_250mhz_clk",	&cpsw_250mhz_clk,	CK_AM33XX),
-+	CLK(NULL,	"cpsw_125mhz_gclk",	&cpsw_125mhz_gclk,	CK_AM33XX),
-+	CLK(NULL,	"cpsw_50mhz_clk",	&cpsw_50mhz_clk,	CK_AM33XX),
-+	CLK(NULL,	"cpsw_5mhz_clk",	&cpsw_5mhz_clk,		CK_AM33XX),
-+	CLK(NULL,	"cpsw_cpts_rft_clk",	&cpsw_cpts_rft_clk,	CK_AM33XX),
-+	CLK(NULL,	"gpio0_dbclk_mux_ck",	&gpio0_dbclk_mux_ck,	CK_AM33XX),
-+	CLK(NULL,	"gpio0_dbclk",		&gpio0_dbclk,		CK_AM33XX),
-+	CLK(NULL,	"gpio1_dbclk",		&gpio1_dbclk,		CK_AM33XX),
-+	CLK(NULL,	"gpio2_dbclk",		&gpio2_dbclk,		CK_AM33XX),
-+	CLK(NULL,	"gpio3_dbclk",		&gpio3_dbclk,		CK_AM33XX),
-+	CLK(NULL,	"lcd_gclk",		&lcd_gclk,		CK_AM33XX),
-+	CLK(NULL,	"mmc_clk",		&mmc_clk,		CK_AM33XX),
-+	CLK(NULL,	"gfx_fclk_clksel_ck",	&gfx_fclk_clksel_ck,	CK_AM33XX),
-+	CLK(NULL,	"gfx_fclk",		&gfx_fclk,		CK_AM33XX),
-+	CLK(NULL,	"gfx_ick",		&gfx_ick,		CK_AM33XX),
-+	CLK(NULL,	"sysclkout_pre_ck",	&sysclkout_pre_ck,	CK_AM33XX),
-+	CLK(NULL,	"clkout2_ck",		&clkout2_ck,		CK_AM33XX),
-+	CLK(NULL,	"gpt0_ick",		&timer0_ick,		CK_AM33XX),
-+	CLK(NULL,	"gpt1_ick",		&timer1_ick,		CK_AM33XX),
-+	CLK(NULL,	"gpt2_ick",		&timer2_ick,		CK_AM33XX),
-+	CLK(NULL,	"gpt3_ick",		&timer3_ick,		CK_AM33XX),
-+	CLK(NULL,	"gpt4_ick",		&timer4_ick,		CK_AM33XX),
-+	CLK(NULL,	"gpt5_ick",		&timer5_ick,		CK_AM33XX),
-+	CLK(NULL,	"gpt6_ick",		&timer6_ick,		CK_AM33XX),
-+	CLK(NULL,	"gpt7_ick",		&timer7_ick,		CK_AM33XX),
-+	CLK(NULL,	"vtp_clk",		&vtp_clk,		CK_AM33XX),
-+	CLK(NULL,	"ehrpwm0_tbclk",	&ehrpwm0_tbclk,	CK_AM33XX),
-+	CLK(NULL,	"ehrpwm1_tbclk",	&ehrpwm1_tbclk,	CK_AM33XX),
-+	CLK(NULL,	"ehrpwm2_tbclk",	&ehrpwm2_tbclk,	CK_AM33XX),
-+};
-+
-+int __init am33xx_clk_init(void)
-+{
-+	struct omap_clk *c;
-+	u32 cpu_clkflg;
-+
-+	if (cpu_is_am33xx()) {
-+		cpu_mask = RATE_IN_AM33XX;
-+		cpu_clkflg = CK_AM33XX;
-+	}
-+
-+	clk_init(&omap2_clk_functions);
-+
-+	for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
-+		clk_preinit(c->lk.clk);
-+
-+	for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
-+		if (c->cpu & cpu_clkflg) {
-+			clkdev_add(&c->lk);
-+			clk_register(c->lk.clk);
-+			omap2_init_clk_clkdm(c->lk.clk);
-+		}
-+
-+	recalculate_root_clocks();
-+
-+	/*
-+	 * Only enable those clocks we will need, let the drivers
-+	 * enable other clocks as necessary
-+	 */
-+	clk_enable_init_clocks();
-+
-+	return 0;
-+}
-diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
-index 5d0064a..7dbb218 100644
---- a/arch/arm/mach-omap2/clock3xxx_data.c
-+++ b/arch/arm/mach-omap2/clock3xxx_data.c
-@@ -27,6 +27,7 @@
- #include "clock34xx.h"
- #include "clock36xx.h"
- #include "clock3517.h"
-+#include "clock33xx.h"
- 
- #include "cm2xxx_3xxx.h"
- #include "cm-regbits-34xx.h"
-@@ -2480,6 +2481,16 @@ static struct clk uart4_fck = {
- 	.recalc		= &followparent_recalc,
- };
- 
-+static struct clk uart4_fck_am35xx = {
-+	.name           = "uart4_fck",
-+	.ops            = &clkops_omap2_dflt_wait,
-+	.parent         = &per_48m_fck,
-+	.enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-+	.enable_bit     = OMAP3430_EN_UART4_SHIFT,
-+	.clkdm_name     = "core_l4_clkdm",
-+	.recalc         = &followparent_recalc,
-+};
-+
- static struct clk gpt2_fck = {
- 	.name		= "gpt2_fck",
- 	.ops		= &clkops_omap2_dflt_wait,
-@@ -3287,7 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = {
- 	CLK(NULL,	"cpefuse_fck",	&cpefuse_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- 	CLK(NULL,	"ts_fck",	&ts_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- 	CLK(NULL,	"usbtll_fck",	&usbtll_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
--	CLK("usbhs-omap.0",	"usbtll_fck",	&usbtll_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-+	CLK("usbhs_omap",	"usbtll_fck",	&usbtll_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- 	CLK("omap-mcbsp.1",	"prcm_fck",	&core_96m_fck,	CK_3XXX),
- 	CLK("omap-mcbsp.5",	"prcm_fck",	&core_96m_fck,	CK_3XXX),
- 	CLK(NULL,	"core_96m_fck",	&core_96m_fck,	CK_3XXX),
-@@ -3323,7 +3334,7 @@ static struct omap_clk omap3xxx_clks[] = {
- 	CLK(NULL,	"pka_ick",	&pka_ick,	CK_34XX | CK_36XX),
- 	CLK(NULL,	"core_l4_ick",	&core_l4_ick,	CK_3XXX),
- 	CLK(NULL,	"usbtll_ick",	&usbtll_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
--	CLK("usbhs-omap.0",	"usbtll_ick",	&usbtll_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-+	CLK("usbhs_omap",	"usbtll_ick",	&usbtll_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- 	CLK("omap_hsmmc.2",	"ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- 	CLK(NULL,	"icr_ick",	&icr_ick,	CK_34XX | CK_36XX),
- 	CLK("omap-aes",	"ick",	&aes2_ick,	CK_34XX | CK_36XX),
-@@ -3369,20 +3380,18 @@ static struct omap_clk omap3xxx_clks[] = {
- 	CLK(NULL,	"cam_ick",	&cam_ick,	CK_34XX | CK_36XX),
- 	CLK(NULL,	"csi2_96m_fck",	&csi2_96m_fck,	CK_34XX | CK_36XX),
- 	CLK(NULL,	"usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
--	CLK("usbhs-omap.0",	"hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- 	CLK(NULL,	"usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
--	CLK("usbhs-omap.0",	"fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- 	CLK(NULL,	"usbhost_ick",	&usbhost_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
--	CLK("usbhs-omap.0",	"usbhost_ick",	&usbhost_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
--	CLK("usbhs-omap.0",	"utmi_p1_gfclk",	&dummy_ck,	CK_3XXX),
--	CLK("usbhs-omap.0",	"utmi_p2_gfclk",	&dummy_ck,	CK_3XXX),
--	CLK("usbhs-omap.0",	"xclk60mhsp1_ck",	&dummy_ck,	CK_3XXX),
--	CLK("usbhs-omap.0",	"xclk60mhsp2_ck",	&dummy_ck,	CK_3XXX),
--	CLK("usbhs-omap.0",	"usb_host_hs_utmi_p1_clk",	&dummy_ck,	CK_3XXX),
--	CLK("usbhs-omap.0",	"usb_host_hs_utmi_p2_clk",	&dummy_ck,	CK_3XXX),
--	CLK("usbhs-omap.0",	"usb_tll_hs_usb_ch0_clk",	&dummy_ck,	CK_3XXX),
--	CLK("usbhs-omap.0",	"usb_tll_hs_usb_ch1_clk",	&dummy_ck,	CK_3XXX),
--	CLK("usbhs-omap.0",	"init_60m_fclk",	&dummy_ck,	CK_3XXX),
-+	CLK("usbhs_omap",	"usbhost_ick",	&usbhost_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-+	CLK("usbhs_omap",	"utmi_p1_gfclk",	&dummy_ck,	CK_3XXX),
-+	CLK("usbhs_omap",	"utmi_p2_gfclk",	&dummy_ck,	CK_3XXX),
-+	CLK("usbhs_omap",	"xclk60mhsp1_ck",	&dummy_ck,	CK_3XXX),
-+	CLK("usbhs_omap",	"xclk60mhsp2_ck",	&dummy_ck,	CK_3XXX),
-+	CLK("usbhs_omap",	"usb_host_hs_utmi_p1_clk",	&dummy_ck,	CK_3XXX),
-+	CLK("usbhs_omap",	"usb_host_hs_utmi_p2_clk",	&dummy_ck,	CK_3XXX),
-+	CLK("usbhs_omap",	"usb_tll_hs_usb_ch0_clk",	&dummy_ck,	CK_3XXX),
-+	CLK("usbhs_omap",	"usb_tll_hs_usb_ch1_clk",	&dummy_ck,	CK_3XXX),
-+	CLK("usbhs_omap",	"init_60m_fclk",	&dummy_ck,	CK_3XXX),
- 	CLK(NULL,	"usim_fck",	&usim_fck,	CK_3430ES2PLUS | CK_36XX),
- 	CLK(NULL,	"gpt1_fck",	&gpt1_fck,	CK_3XXX),
- 	CLK(NULL,	"wkup_32k_fck",	&wkup_32k_fck,	CK_3XXX),
-@@ -3403,6 +3412,7 @@ static struct omap_clk omap3xxx_clks[] = {
- 	CLK(NULL,	"per_48m_fck",	&per_48m_fck,	CK_3XXX),
- 	CLK(NULL,	"uart3_fck",	&uart3_fck,	CK_3XXX),
- 	CLK(NULL,	"uart4_fck",	&uart4_fck,	CK_36XX),
-+	CLK(NULL,	"uart4_fck",	&uart4_fck_am35xx, CK_3505 | CK_3517),
- 	CLK(NULL,	"gpt2_fck",	&gpt2_fck,	CK_3XXX),
- 	CLK(NULL,	"gpt3_fck",	&gpt3_fck,	CK_3XXX),
- 	CLK(NULL,	"gpt4_fck",	&gpt4_fck,	CK_3XXX),
-@@ -3517,6 +3527,11 @@ int __init omap3xxx_clk_init(void)
- 	} else if (cpu_is_ti816x()) {
- 		cpu_mask = RATE_IN_TI816X;
- 		cpu_clkflg = CK_TI816X;
-+	} else if (cpu_is_am33xx()) {
-+		am33xx_clk_init();
-+		return 0;
-+	} else if (cpu_is_ti814x()) {
-+		cpu_mask = RATE_IN_TI814X;
- 	} else if (cpu_is_omap34xx()) {
- 		if (omap_rev() == OMAP3430_REV_ES1_0) {
- 			cpu_mask = RATE_IN_3430ES1;
-@@ -3600,7 +3615,7 @@ int __init omap3xxx_clk_init(void)
- 	 * Lock DPLL5 -- here only until other device init code can
- 	 * handle this
- 	 */
--	if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
-+	if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
- 		omap3_clk_lock_dpll5();
- 
- 	/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
-diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
-index 0798a80..08e86d7 100644
---- a/arch/arm/mach-omap2/clock44xx_data.c
-+++ b/arch/arm/mach-omap2/clock44xx_data.c
-@@ -1206,6 +1206,14 @@ static const struct clksel ocp_abe_iclk_div[] = {
- 	{ .parent = NULL },
- };
- 
-+static struct clk mpu_periphclk = {
-+	.name		= "mpu_periphclk",
-+	.parent		= &dpll_mpu_ck,
-+	.ops		= &clkops_null,
-+	.fixed_div	= 2,
-+	.recalc		= &omap_fixed_divisor_recalc,
-+};
-+
- static struct clk ocp_abe_iclk = {
- 	.name		= "ocp_abe_iclk",
- 	.parent		= &aess_fclk,
-@@ -3189,6 +3197,7 @@ static struct omap_clk omap44xx_clks[] = {
- 	CLK(NULL,	"l4_div_ck",			&l4_div_ck,	CK_443X),
- 	CLK(NULL,	"lp_clk_div_ck",		&lp_clk_div_ck,	CK_443X),
- 	CLK(NULL,	"l4_wkup_clk_mux_ck",		&l4_wkup_clk_mux_ck,	CK_443X),
-+	CLK("smp_twd",	NULL,				&mpu_periphclk,	CK_443X),
- 	CLK(NULL,	"ocp_abe_iclk",			&ocp_abe_iclk,	CK_443X),
- 	CLK(NULL,	"per_abe_24m_fclk",		&per_abe_24m_fclk,	CK_443X),
- 	CLK(NULL,	"per_abe_nc_fclk",		&per_abe_nc_fclk,	CK_443X),
-@@ -3295,7 +3304,7 @@ static struct omap_clk omap44xx_clks[] = {
- 	CLK(NULL,	"uart2_fck",			&uart2_fck,	CK_443X),
- 	CLK(NULL,	"uart3_fck",			&uart3_fck,	CK_443X),
- 	CLK(NULL,	"uart4_fck",			&uart4_fck,	CK_443X),
--	CLK("usbhs-omap.0",	"fs_fck",		&usb_host_fs_fck,	CK_443X),
-+	CLK("usbhs_omap",	"fs_fck",		&usb_host_fs_fck,	CK_443X),
- 	CLK(NULL,	"utmi_p1_gfclk",		&utmi_p1_gfclk,	CK_443X),
- 	CLK(NULL,	"usb_host_hs_utmi_p1_clk",	&usb_host_hs_utmi_p1_clk,	CK_443X),
- 	CLK(NULL,	"utmi_p2_gfclk",		&utmi_p2_gfclk,	CK_443X),
-@@ -3306,7 +3315,7 @@ static struct omap_clk omap44xx_clks[] = {
- 	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk,	CK_443X),
- 	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk,	CK_443X),
- 	CLK(NULL,	"usb_host_hs_func48mclk",	&usb_host_hs_func48mclk,	CK_443X),
--	CLK("usbhs-omap.0",	"hs_fck",		&usb_host_hs_fck,	CK_443X),
-+	CLK("usbhs_omap",	"hs_fck",		&usb_host_hs_fck,	CK_443X),
- 	CLK(NULL,	"otg_60m_gfclk",		&otg_60m_gfclk,	CK_443X),
- 	CLK(NULL,	"usb_otg_hs_xclk",		&usb_otg_hs_xclk,	CK_443X),
- 	CLK("musb-omap2430",	"ick",				&usb_otg_hs_ick,	CK_443X),
-@@ -3314,7 +3323,7 @@ static struct omap_clk omap44xx_clks[] = {
- 	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk,	CK_443X),
- 	CLK(NULL,	"usb_tll_hs_usb_ch0_clk",	&usb_tll_hs_usb_ch0_clk,	CK_443X),
- 	CLK(NULL,	"usb_tll_hs_usb_ch1_clk",	&usb_tll_hs_usb_ch1_clk,	CK_443X),
--	CLK("usbhs-omap.0",	"usbtll_ick",		&usb_tll_hs_ick,	CK_443X),
-+	CLK("usbhs_omap",	"usbtll_ick",		&usb_tll_hs_ick,	CK_443X),
- 	CLK(NULL,	"usim_ck",			&usim_ck,	CK_443X),
- 	CLK(NULL,	"usim_fclk",			&usim_fclk,	CK_443X),
- 	CLK(NULL,	"usim_fck",			&usim_fck,	CK_443X),
-@@ -3374,8 +3383,8 @@ static struct omap_clk omap44xx_clks[] = {
- 	CLK(NULL,	"uart2_ick",			&dummy_ck,	CK_443X),
- 	CLK(NULL,	"uart3_ick",			&dummy_ck,	CK_443X),
- 	CLK(NULL,	"uart4_ick",			&dummy_ck,	CK_443X),
--	CLK("usbhs-omap.0",	"usbhost_ick",		&dummy_ck,		CK_443X),
--	CLK("usbhs-omap.0",	"usbtll_fck",		&dummy_ck,	CK_443X),
-+	CLK("usbhs_omap",	"usbhost_ick",		&dummy_ck,		CK_443X),
-+	CLK("usbhs_omap",	"usbtll_fck",		&dummy_ck,	CK_443X),
- 	CLK("omap_wdt",	"ick",				&dummy_ck,	CK_443X),
- 	CLK("omap_timer.1",	"32k_ck",	&sys_32k_ck,	CK_443X),
- 	CLK("omap_timer.2",	"32k_ck",	&sys_32k_ck,	CK_443X),
-diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
-index f7b5860..72cb12b 100644
---- a/arch/arm/mach-omap2/clockdomain.h
-+++ b/arch/arm/mach-omap2/clockdomain.h
-@@ -195,6 +195,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
- extern void __init omap242x_clockdomains_init(void);
- extern void __init omap243x_clockdomains_init(void);
- extern void __init omap3xxx_clockdomains_init(void);
-+extern void __init am33xx_clockdomains_init(void);
- extern void __init omap44xx_clockdomains_init(void);
- extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
- extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
-@@ -202,6 +203,7 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
- extern struct clkdm_ops omap2_clkdm_operations;
- extern struct clkdm_ops omap3_clkdm_operations;
- extern struct clkdm_ops omap4_clkdm_operations;
-+extern struct clkdm_ops am33xx_clkdm_operations;
- 
- extern struct clkdm_dep gfx_24xx_wkdeps[];
- extern struct clkdm_dep dsp_24xx_wkdeps[];
-diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
-index a0d68db..edcab10 100644
---- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
-+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
-@@ -147,6 +147,9 @@ static void _enable_hwsup(struct clockdomain *clkdm)
- 	if (cpu_is_omap24xx())
- 		omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- 					       clkdm->clktrctrl_mask);
-+	else if (cpu_is_am33xx())
-+		am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs,
-+					       clkdm->clktrctrl_mask);
- 	else if (cpu_is_omap34xx())
- 		omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- 					       clkdm->clktrctrl_mask);
-@@ -157,6 +160,9 @@ static void _disable_hwsup(struct clockdomain *clkdm)
- 	if (cpu_is_omap24xx())
- 		omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- 						clkdm->clktrctrl_mask);
-+	else if (cpu_is_am33xx())
-+		am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs,
-+					       clkdm->clktrctrl_mask);
- 	else if (cpu_is_omap34xx())
- 		omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- 						clkdm->clktrctrl_mask);
-@@ -211,14 +217,22 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
- 
- static int omap3_clkdm_sleep(struct clockdomain *clkdm)
- {
--	omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
-+	if (cpu_is_am33xx())
-+		am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs,
-+				clkdm->clktrctrl_mask);
-+	else
-+		omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
- 				clkdm->clktrctrl_mask);
- 	return 0;
- }
- 
- static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
- {
--	omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
-+	if (cpu_is_am33xx())
-+		am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs,
-+				clkdm->clktrctrl_mask);
-+	else
-+		omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
- 				clkdm->clktrctrl_mask);
- 	return 0;
- }
-diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
-index 935c7f0..188afe2 100644
---- a/arch/arm/mach-omap2/clockdomain44xx.c
-+++ b/arch/arm/mach-omap2/clockdomain44xx.c
-@@ -128,3 +128,10 @@ struct clkdm_ops omap4_clkdm_operations = {
- 	.clkdm_clk_enable	= omap4_clkdm_clk_enable,
- 	.clkdm_clk_disable	= omap4_clkdm_clk_disable,
- };
-+
-+struct clkdm_ops am33xx_clkdm_operations = {
-+	.clkdm_sleep		= omap4_clkdm_sleep,
-+	.clkdm_wakeup		= omap4_clkdm_wakeup,
-+	.clkdm_clk_enable	= omap4_clkdm_clk_enable,
-+	.clkdm_clk_disable	= omap4_clkdm_clk_disable,
-+};
-diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
-new file mode 100644
-index 0000000..a4734e9
---- /dev/null
-+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
-@@ -0,0 +1,232 @@
-+/*
-+ * AM33XX Clock Domain data.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/io.h>
-+
-+#include "prcm44xx.h"
-+#include "clockdomain.h"
-+#include "cm.h"
-+#include "cm33xx.h"
-+#include "cm-regbits-33xx.h"
-+
-+static struct clockdomain l4ls_am33xx_clkdm = {
-+	.name		= "l4ls_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain l3s_am33xx_clkdm = {
-+	.name		= "l3s_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain l4fw_am33xx_clkdm = {
-+	.name		= "l4fw_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain l3_am33xx_clkdm = {
-+	.name		= "l3_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain l4hs_am33xx_clkdm = {
-+	.name		= "l4hs_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain ocpwp_l3_am33xx_clkdm = {
-+	.name		= "ocpwp_l3_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain pruss_ocp_am33xx_clkdm = {
-+	.name		= "pruss_ocp_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
-+	.name		= "cpsw_125mhz_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain lcdc_am33xx_clkdm = {
-+	.name		= "lcdc_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain clk_24mhz_am33xx_clkdm = {
-+	.name		= "clk_24mhz_clkdm",
-+	.pwrdm		= { .name = "per_pwrdm" },
-+	.cm_inst	= AM33XX_CM_PER_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain l4_wkup_am33xx_clkdm = {
-+	.name		= "l4_wkup_clkdm",
-+	.pwrdm		= { .name = "wkup_pwrdm" },
-+	.cm_inst	= AM33XX_CM_WKUP_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain l3_aon_am33xx_clkdm = {
-+	.name		= "l3_aon_clkdm",
-+	.pwrdm		= { .name = "wkup_pwrdm" },
-+	.cm_inst	= AM33XX_CM_WKUP_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
-+	.name		= "l4_wkup_aon_clkdm",
-+	.pwrdm		= { .name = "wkup_pwrdm" },
-+	.cm_inst	= AM33XX_CM_WKUP_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain mpu_am33xx_clkdm = {
-+	.name		= "mpu_clkdm",
-+	.pwrdm		= { .name = "mpu_pwrdm" },
-+	.cm_inst	= AM33XX_CM_MPU_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain l4_rtc_am33xx_clkdm = {
-+	.name		= "l4_rtc_clkdm",
-+	.pwrdm		= { .name = "rtc_pwrdm" },
-+	.cm_inst	= AM33XX_CM_RTC_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain gfx_l3_am33xx_clkdm = {
-+	.name		= "gfx_l3_clkdm",
-+	.pwrdm		= { .name = "gfx_pwrdm" },
-+	.cm_inst	= AM33XX_CM_GFX_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
-+	.name		= "gfx_l4ls_gfx_clkdm",
-+	.pwrdm		= { .name = "gfx_pwrdm" },
-+	.cm_inst	= AM33XX_CM_GFX_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain l4_cefuse_am33xx_clkdm = {
-+	.name		= "l4_cefuse_clkdm",
-+	.pwrdm		= { .name = "cefuse_pwrdm" },
-+	.cm_inst	= AM33XX_CM_CEFUSE_MOD,
-+	.prcm_partition	= AM33XX_PRM_PARTITION,
-+	.clkdm_offs	= AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
-+	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
-+	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
-+};
-+
-+static struct clockdomain *clockdomains_am33xx[] __initdata = {
-+	&l4ls_am33xx_clkdm,
-+	&l3s_am33xx_clkdm,
-+	&l4fw_am33xx_clkdm,
-+	&l3_am33xx_clkdm,
-+	&l4hs_am33xx_clkdm,
-+	&ocpwp_l3_am33xx_clkdm,
-+	&pruss_ocp_am33xx_clkdm,
-+	&cpsw_125mhz_am33xx_clkdm,
-+	&lcdc_am33xx_clkdm,
-+	&clk_24mhz_am33xx_clkdm,
-+	&l4_wkup_am33xx_clkdm,
-+	&l3_aon_am33xx_clkdm,
-+	&l4_wkup_aon_am33xx_clkdm,
-+	&mpu_am33xx_clkdm,
-+	&l4_rtc_am33xx_clkdm,
-+	&gfx_l3_am33xx_clkdm,
-+	&gfx_l4ls_gfx_am33xx_clkdm,
-+	&l4_cefuse_am33xx_clkdm,
-+	NULL,
-+};
-+
-+void __init am33xx_clockdomains_init(void)
-+{
-+	clkdm_register_platform_funcs(&am33xx_clkdm_operations);
-+	clkdm_register_clkdms(clockdomains_am33xx);
-+	clkdm_complete_init();
-+}
-diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
-new file mode 100644
-index 0000000..f3e2d4a
---- /dev/null
-+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
-@@ -0,0 +1,683 @@
-+/*
-+ * AM33XX Power Management register bits
-+ *
-+ * This file is automatically generated from the AM33XX hardware databases.
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
-+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
-+
-+/*
-+ * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
-+ * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
-+ */
-+#define AM33XX_AUTO_DPLL_MODE_SHIFT			0
-+#define AM33XX_AUTO_DPLL_MODE_MASK			(0x7 << 0)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT		14
-+#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK		(1 << 16)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT		11
-+#define AM33XX_CLKACTIVITY_CAN_CLK_MASK			(1 << 11)
-+
-+/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT		4
-+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK		(1 << 4)
-+
-+/* Used by CM_PER_CPSW_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT	4
-+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK	(1 << 4)
-+
-+/* Used by CM_PER_L4HS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT	4
-+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK	(1 << 4)
-+
-+/* Used by CM_PER_L4HS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT	5
-+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK		(1 << 5)
-+
-+/* Used by CM_PER_L4HS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT		6
-+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK		(1 << 6)
-+
-+/* Used by CM_PER_L3_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT		6
-+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK		(1 << 6)
-+
-+/* Used by CM_CEFUSE_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT	9
-+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK	(1 << 9)
-+
-+/* Used by CM_L3_AON_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT		2
-+#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK		(1 << 2)
-+
-+/* Used by CM_L3_AON_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT		4
-+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK		(1 << 4)
-+
-+/* Used by CM_PER_L3_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT		2
-+#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK		(1 << 2)
-+
-+/* Used by CM_GFX_L3_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT		9
-+#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK		(1 << 9)
-+
-+/* Used by CM_GFX_L3_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT		8
-+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK		(1 << 8)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT		8
-+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK		(1 << 8)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT		19
-+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK		(1 << 19)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT		20
-+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK		(1 << 20)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT		21
-+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK		(1 << 21)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT		22
-+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK		(1 << 22)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT		26
-+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK		(1 << 26)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT		18
-+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK		(1 << 18)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT		11
-+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK		(1 << 11)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT		24
-+#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK		(1 << 24)
-+
-+/* Used by CM_PER_PRUSS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT		5
-+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK		(1 << 5)
-+
-+/* Used by CM_PER_PRUSS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT		4
-+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK		(1 << 4)
-+
-+/* Used by CM_PER_PRUSS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT	6
-+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK		(1 << 6)
-+
-+/* Used by CM_PER_L3S_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT		3
-+#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK		(1 << 3)
-+
-+/* Used by CM_L3_AON_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT		3
-+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK		(1 << 3)
-+
-+/* Used by CM_PER_L3_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT		4
-+#define AM33XX_CLKACTIVITY_L3_GCLK_MASK			(1 << 4)
-+
-+/* Used by CM_PER_L4FW_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT		8
-+#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK		(1 << 8)
-+
-+/* Used by CM_PER_L4HS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT		3
-+#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK		(1 << 3)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT		8
-+#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK		(1 << 8)
-+
-+/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
-+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT		8
-+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK		(1 << 8)
-+
-+/* Used by CM_CEFUSE_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT	8
-+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK		(1 << 8)
-+
-+/* Used by CM_RTC_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT		8
-+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK		(1 << 8)
-+
-+/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT	2
-+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK	(1 << 2)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT		2
-+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK		(1 << 2)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT		17
-+#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK		(1 << 17)
-+
-+/* Used by CM_PER_LCDC_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT	4
-+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK	(1 << 4)
-+
-+/* Used by CM_PER_LCDC_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT	5
-+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK	(1 << 5)
-+
-+/* Used by CM_PER_L3_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT		7
-+#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK		(1 << 7)
-+
-+/* Used by CM_PER_L3_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT		3
-+#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK		(1 << 3)
-+
-+/* Used by CM_MPU_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT		2
-+#define AM33XX_CLKACTIVITY_MPU_CLK_MASK			(1 << 2)
-+
-+/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT		4
-+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK		(1 << 4)
-+
-+/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT		5
-+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK		(1 << 5)
-+
-+/* Used by CM_RTC_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT		9
-+#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK		(1 << 9)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT		25
-+#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK		(1 << 25)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT		3
-+#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK		(1 << 3)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT		10
-+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK		(1 << 10)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT		13
-+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK		(1 << 13)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT		14
-+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK		(1 << 14)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT		15
-+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK		(1 << 15)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT		16
-+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK		(1 << 16)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT		27
-+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK		(1 << 27)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT		28
-+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK		(1 << 28)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT		13
-+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK		(1 << 13)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT		12
-+#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK		(1 << 12)
-+
-+/* Used by CM_PER_L4LS_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT		10
-+#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK		(1 << 10)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT		9
-+#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK		(1 << 9)
-+
-+/* Used by CM_WKUP_CLKSTCTRL */
-+#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT		4
-+#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK		(1 << 4)
-+
-+/* Used by CLKSEL_GFX_FCLK */
-+#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT		0
-+#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK			(1 << 0)
-+
-+/* Used by CM_CLKOUT_CTRL */
-+#define AM33XX_CLKOUT2DIV_SHIFT				3
-+#define AM33XX_CLKOUT2DIV_MASK				(0x05 << 3)
-+
-+/* Used by CM_CLKOUT_CTRL */
-+#define AM33XX_CLKOUT2EN_SHIFT				7
-+#define AM33XX_CLKOUT2EN_MASK				(1 << 7)
-+
-+/* Used by CM_CLKOUT_CTRL */
-+#define AM33XX_CLKOUT2SOURCE_SHIFT			0
-+#define AM33XX_CLKOUT2SOURCE_MASK			(0x02 << 0)
-+
-+/*
-+ * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
-+ * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
-+ * CLKSEL_TIMER7_CLK
-+ */
-+#define AM33XX_CLKSEL_SHIFT				0
-+#define AM33XX_CLKSEL_MASK				(0x01 << 0)
-+
-+/*
-+ * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
-+ * CM_CPTS_RFT_CLKSEL
-+ */
-+#define AM33XX_CLKSEL_0_0_SHIFT				0
-+#define AM33XX_CLKSEL_0_0_MASK				(1 << 0)
-+
-+#define AM33XX_CLKSEL_0_1_SHIFT				0
-+#define AM33XX_CLKSEL_0_1_MASK				(3 << 0)
-+
-+/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
-+#define AM33XX_CLKSEL_0_2_SHIFT				0
-+#define AM33XX_CLKSEL_0_2_MASK				(7 << 0)
-+
-+/* Used by CLKSEL_GFX_FCLK */
-+#define AM33XX_CLKSEL_GFX_FCLK_SHIFT			1
-+#define AM33XX_CLKSEL_GFX_FCLK_MASK			(1 << 1)
-+
-+/*
-+ * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
-+ * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
-+ * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
-+ * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
-+ * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
-+ * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
-+ */
-+#define AM33XX_CLKTRCTRL_SHIFT				0
-+#define AM33XX_CLKTRCTRL_MASK				(0x3 << 0)
-+
-+/*
-+ * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
-+ * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
-+ * CM_SSC_DELTAMSTEP_DPLL_PER
-+ */
-+#define AM33XX_DELTAMSTEP_SHIFT				0
-+#define AM33XX_DELTAMSTEP_MASK				(0x19 << 0)
-+
-+/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
-+#define AM33XX_DPLL_BYP_CLKSEL_SHIFT			23
-+#define AM33XX_DPLL_BYP_CLKSEL_MASK			(1 << 23)
-+
-+/* Used by CM_CLKDCOLDO_DPLL_PER */
-+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT		8
-+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK		(1 << 8)
-+
-+/* Used by CM_CLKDCOLDO_DPLL_PER */
-+#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT		12
-+#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK			(1 << 12)
-+
-+/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
-+#define AM33XX_DPLL_CLKOUT_DIV_SHIFT			0
-+#define AM33XX_DPLL_CLKOUT_DIV_MASK			(0x1f << 0)
-+
-+/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
-+#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT		0
-+#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK			(0x06 << 0)
-+
-+/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
-+#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT		5
-+#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK		(1 << 5)
-+
-+/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
-+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT	7
-+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK		(1 << 7)
-+
-+/*
-+ * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
-+ * CM_DIV_M2_DPLL_PER
-+ */
-+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT		8
-+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK		(1 << 8)
-+
-+/*
-+ * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
-+ * CM_CLKSEL_DPLL_MPU
-+ */
-+#define AM33XX_DPLL_DIV_SHIFT				0
-+#define AM33XX_DPLL_DIV_MASK				(0x7f << 0)
-+
-+#define AM33XX_DPLL_PER_DIV_MASK			(0xff << 0)
-+
-+/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
-+#define AM33XX_DPLL_DIV_0_7_SHIFT			0
-+#define AM33XX_DPLL_DIV_0_7_MASK			(0x07 << 0)
-+
-+/*
-+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
-+ * CM_CLKMODE_DPLL_MPU
-+ */
-+#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT			8
-+#define AM33XX_DPLL_DRIFTGUARD_EN_MASK			(1 << 8)
-+
-+/*
-+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
-+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
-+ */
-+#define AM33XX_DPLL_EN_SHIFT				0
-+#define AM33XX_DPLL_EN_MASK				(0x7 << 0)
-+
-+/*
-+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
-+ * CM_CLKMODE_DPLL_MPU
-+ */
-+#define AM33XX_DPLL_LPMODE_EN_SHIFT			10
-+#define AM33XX_DPLL_LPMODE_EN_MASK			(1 << 10)
-+
-+/*
-+ * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
-+ * CM_CLKSEL_DPLL_MPU
-+ */
-+#define AM33XX_DPLL_MULT_SHIFT				8
-+#define AM33XX_DPLL_MULT_MASK				(0x7ff << 8)
-+
-+/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
-+#define AM33XX_DPLL_MULT_PERIPH_SHIFT			8
-+#define AM33XX_DPLL_MULT_PERIPH_MASK			(0xfff << 8)
-+
-+/*
-+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
-+ * CM_CLKMODE_DPLL_MPU
-+ */
-+#define AM33XX_DPLL_REGM4XEN_SHIFT			11
-+#define AM33XX_DPLL_REGM4XEN_MASK			(1 << 11)
-+
-+/* Used by CM_CLKSEL_DPLL_PERIPH */
-+#define AM33XX_DPLL_SD_DIV_SHIFT			24
-+#define AM33XX_DPLL_SD_DIV_MASK				(24, 31)
-+
-+/*
-+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
-+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
-+ */
-+#define AM33XX_DPLL_SSC_ACK_SHIFT			13
-+#define AM33XX_DPLL_SSC_ACK_MASK			(1 << 13)
-+
-+/*
-+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
-+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
-+ */
-+#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT		14
-+#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK			(1 << 14)
-+
-+/*
-+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
-+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
-+ */
-+#define AM33XX_DPLL_SSC_EN_SHIFT			12
-+#define AM33XX_DPLL_SSC_EN_MASK				(1 << 12)
-+
-+/* Used by CM_DIV_M4_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT		0
-+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK		(0x1f << 0)
-+
-+/* Used by CM_DIV_M4_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT		5
-+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK		(1 << 5)
-+
-+/* Used by CM_DIV_M4_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT	8
-+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK		(1 << 8)
-+
-+/* Used by CM_DIV_M4_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT		12
-+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK		(1 << 12)
-+
-+/* Used by CM_DIV_M5_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT		0
-+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK		(0x1f << 0)
-+
-+/* Used by CM_DIV_M5_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT		5
-+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK		(1 << 5)
-+
-+/* Used by CM_DIV_M5_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT	8
-+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK		(1 << 8)
-+
-+/* Used by CM_DIV_M5_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT		12
-+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK		(1 << 12)
-+
-+/* Used by CM_DIV_M6_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT		0
-+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK		(0x04 << 0)
-+
-+/* Used by CM_DIV_M6_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT		5
-+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK		(1 << 5)
-+
-+/* Used by CM_DIV_M6_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT	8
-+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK		(1 << 8)
-+
-+/* Used by CM_DIV_M6_DPLL_CORE */
-+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT		12
-+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK		(1 << 12)
-+
-+/*
-+ * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
-+ * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
-+ * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
-+ * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
-+ * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
-+ * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
-+ * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
-+ * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
-+ * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
-+ * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
-+ * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
-+ * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
-+ * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
-+ * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
-+ * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
-+ * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
-+ * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
-+ * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
-+ * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
-+ * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
-+ * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
-+ * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
-+ * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
-+ * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
-+ * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
-+ * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
-+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
-+ * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
-+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
-+ * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
-+ * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
-+ */
-+#define AM33XX_IDLEST_SHIFT				16
-+#define AM33XX_IDLEST_MASK				(0x3 << 16)
-+#define AM33XX_IDLEST_VAL				0x3
-+
-+/* Used by CM_MAC_CLKSEL */
-+#define AM33XX_MII_CLK_SEL_SHIFT			2
-+#define AM33XX_MII_CLK_SEL_MASK				(1 << 2)
-+
-+/*
-+ * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
-+ * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
-+ * CM_SSC_MODFREQDIV_DPLL_PER
-+ */
-+#define AM33XX_MODFREQDIV_EXPONENT_SHIFT		8
-+#define AM33XX_MODFREQDIV_EXPONENT_MASK			(0x10 << 8)
-+
-+/*
-+ * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
-+ * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
-+ * CM_SSC_MODFREQDIV_DPLL_PER
-+ */
-+#define AM33XX_MODFREQDIV_MANTISSA_SHIFT		0
-+#define AM33XX_MODFREQDIV_MANTISSA_MASK			(0x06 << 0)
-+
-+/*
-+ * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
-+ * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
-+ * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
-+ * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
-+ * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
-+ * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
-+ * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
-+ * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
-+ * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
-+ * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
-+ * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
-+ * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
-+ * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
-+ * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
-+ * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
-+ * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
-+ * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
-+ * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
-+ * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
-+ * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
-+ * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
-+ * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
-+ * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
-+ * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
-+ * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
-+ * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
-+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
-+ * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
-+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
-+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
-+ * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
-+ * CM_CEFUSE_CEFUSE_CLKCTRL
-+ */
-+#define AM33XX_MODULEMODE_SHIFT				0
-+#define AM33XX_MODULEMODE_MASK				(0x3 << 0)
-+
-+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
-+#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT			30
-+#define AM33XX_OPTCLK_DEBUG_CLKA_MASK			(1 << 30)
-+
-+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
-+#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT		19
-+#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK			(1 << 19)
-+
-+/* Used by CM_WKUP_GPIO0_CLKCTRL */
-+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT		18
-+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK		(1 << 18)
-+
-+/* Used by CM_PER_GPIO1_CLKCTRL */
-+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT		18
-+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK		(1 << 18)
-+
-+/* Used by CM_PER_GPIO2_CLKCTRL */
-+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT		18
-+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK		(1 << 18)
-+
-+/* Used by CM_PER_GPIO3_CLKCTRL */
-+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT		18
-+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK		(1 << 18)
-+
-+/* Used by CM_PER_GPIO4_CLKCTRL */
-+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT		18
-+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK		(1 << 18)
-+
-+/* Used by CM_PER_GPIO5_CLKCTRL */
-+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT		18
-+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK		(1 << 18)
-+
-+/* Used by CM_PER_GPIO6_CLKCTRL */
-+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT		18
-+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK		(1 << 18)
-+
-+/*
-+ * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
-+ * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
-+ * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
-+ * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
-+ * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
-+ * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
-+ */
-+#define AM33XX_STBYST_SHIFT				18
-+#define AM33XX_STBYST_MASK				(1 << 18)
-+
-+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
-+#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT			27
-+#define AM33XX_STM_PMD_CLKDIVSEL_MASK			(0x29 << 27)
-+
-+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
-+#define AM33XX_STM_PMD_CLKSEL_SHIFT			22
-+#define AM33XX_STM_PMD_CLKSEL_MASK			(0x23 << 22)
-+
-+/*
-+ * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
-+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
-+ */
-+#define AM33XX_ST_DPLL_CLK_SHIFT			0
-+#define AM33XX_ST_DPLL_CLK_MASK				(1 << 0)
-+
-+/* Used by CM_CLKDCOLDO_DPLL_PER */
-+#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT			8
-+#define AM33XX_ST_DPLL_CLKDCOLDO_MASK			(1 << 8)
-+
-+/*
-+ * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
-+ * CM_DIV_M2_DPLL_PER
-+ */
-+#define AM33XX_ST_DPLL_CLKOUT_SHIFT			9
-+#define AM33XX_ST_DPLL_CLKOUT_MASK			(1 << 9)
-+
-+/* Used by CM_DIV_M4_DPLL_CORE */
-+#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT		9
-+#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK		(1 << 9)
-+
-+/* Used by CM_DIV_M5_DPLL_CORE */
-+#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT		9
-+#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK		(1 << 9)
-+
-+/* Used by CM_DIV_M6_DPLL_CORE */
-+#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT		9
-+#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK		(1 << 9)
-+
-+/*
-+ * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
-+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
-+ */
-+#define AM33XX_ST_MN_BYPASS_SHIFT			8
-+#define AM33XX_ST_MN_BYPASS_MASK			(1 << 8)
-+
-+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
-+#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT			24
-+#define AM33XX_TRC_PMD_CLKDIVSEL_MASK			(0x26 << 24)
-+
-+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
-+#define AM33XX_TRC_PMD_CLKSEL_SHIFT			20
-+#define AM33XX_TRC_PMD_CLKSEL_MASK			(0x21 << 20)
-+#endif
-diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
-index 38830d8..b2418b4 100644
---- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
-+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
-@@ -18,7 +18,7 @@
- #include <linux/err.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "cm.h"
- #include "cm2xxx_3xxx.h"
-@@ -84,6 +84,16 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)
- 	omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
- }
- 
-+static void _am33xx_write_clktrctrl(u8 c, s16 module, u16 idx, u32 mask)
-+{
-+	u32 v;
-+
-+	v = omap2_cm_read_mod_reg(module, idx);
-+	v &= ~mask;
-+	v |= c << __ffs(mask);
-+	omap2_cm_write_mod_reg(v, module, idx);
-+}
-+
- bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
- {
- 	u32 v;
-@@ -195,6 +205,30 @@ void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
- 				    OMAP24XX_AUTO_96M_MASK);
- }
- 
-+void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 clkdm, u32 mask)
-+{
-+	_am33xx_write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst,
-+				clkdm, mask);
-+}
-+
-+void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 clkdm, u32 mask)
-+{
-+	_am33xx_write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst,
-+				clkdm, mask);
-+}
-+
-+void am33xx_cm_clkdm_force_sleep(s16 inst, u16 clkdm, u32 mask)
-+{
-+	_am33xx_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst,
-+				clkdm, mask);
-+}
-+
-+void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 clkdm, u32 mask)
-+{
-+	_am33xx_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst,
-+				clkdm, mask);
-+}
-+
- /*
-  *
-  */
-diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
-index 088bbad..1418fc1 100644
---- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
-+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
-@@ -122,6 +122,12 @@ extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
- extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
- extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
- 
-+extern int am33xx_cm_wait_module_ready(u16 inst, u16 clkctrl_reg);
-+extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 clkdm, u32 mask);
-+extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 clkdm, u32 mask);
-+extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 clkdm, u32 mask);
-+extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 clkdm, u32 mask);
-+
- extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
- extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
- 
-diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
-new file mode 100644
-index 0000000..4134901
---- /dev/null
-+++ b/arch/arm/mach-omap2/cm33xx.h
-@@ -0,0 +1,377 @@
-+/*
-+ * AM33XX CM instance offset macros
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
-+#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
-+
-+#include "common.h"
-+
-+#include "cm.h"
-+#include "cm-regbits-33xx.h"
-+#include "cm33xx.h"
-+
-+/* CM base address */
-+#define AM33XX_CM_BASE		0x44e00000
-+
-+#define AM33XX_CM_REGADDR(inst, reg)				\
-+	AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
-+
-+/* CM instances */
-+#define AM33XX_CM_PER_MOD		0x0000
-+#define AM33XX_CM_WKUP_MOD		0x0400
-+#define AM33XX_CM_DPLL_MOD		0x0500
-+#define AM33XX_CM_MPU_MOD		0x0600
-+#define AM33XX_CM_DEVICE_MOD		0x0700
-+#define AM33XX_CM_RTC_MOD		0x0800
-+#define AM33XX_CM_GFX_MOD		0x0900
-+#define AM33XX_CM_CEFUSE_MOD		0x0A00
-+
-+/* CM */
-+
-+/* CM.PER_CM register offsets */
-+#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET		0x0000
-+#define AM33XX_CM_PER_L4LS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
-+#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET		0x0004
-+#define AM33XX_CM_PER_L3S_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
-+#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET		0x0008
-+#define AM33XX_CM_PER_L4FW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
-+#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET		0x000c
-+#define AM33XX_CM_PER_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
-+#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET		0x0014
-+#define AM33XX_CM_PER_CPGMAC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
-+#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET		0x0018
-+#define AM33XX_CM_PER_LCDC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
-+#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET		0x001c
-+#define AM33XX_CM_PER_USB0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
-+#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET		0x0020
-+#define AM33XX_CM_PER_MLB_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
-+#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET		0x0024
-+#define AM33XX_CM_PER_TPTC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
-+#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0028
-+#define AM33XX_CM_PER_EMIF_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
-+#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET		0x002c
-+#define AM33XX_CM_PER_OCMCRAM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
-+#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET		0x0030
-+#define AM33XX_CM_PER_GPMC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
-+#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET		0x0034
-+#define AM33XX_CM_PER_MCASP0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
-+#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET		0x0038
-+#define AM33XX_CM_PER_UART5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
-+#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET		0x003c
-+#define AM33XX_CM_PER_MMC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
-+#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET		0x0040
-+#define AM33XX_CM_PER_ELM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
-+#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET		0x0044
-+#define AM33XX_CM_PER_I2C2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
-+#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET		0x0048
-+#define AM33XX_CM_PER_I2C1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
-+#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET		0x004c
-+#define AM33XX_CM_PER_SPI0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
-+#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET		0x0050
-+#define AM33XX_CM_PER_SPI1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
-+#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET		0x0054
-+#define AM33XX_CM_PER_SPI2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
-+#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET		0x0058
-+#define AM33XX_CM_PER_SPI3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
-+#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET		0x0060
-+#define AM33XX_CM_PER_L4LS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
-+#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET		0x0064
-+#define AM33XX_CM_PER_L4FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
-+#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET		0x0068
-+#define AM33XX_CM_PER_MCASP1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
-+#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET		0x006c
-+#define AM33XX_CM_PER_UART1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
-+#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET		0x0070
-+#define AM33XX_CM_PER_UART2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
-+#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET		0x0074
-+#define AM33XX_CM_PER_UART3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
-+#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET		0x0078
-+#define AM33XX_CM_PER_UART4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
-+#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET		0x007c
-+#define AM33XX_CM_PER_TIMER7_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
-+#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET		0x0080
-+#define AM33XX_CM_PER_TIMER2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
-+#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET		0x0084
-+#define AM33XX_CM_PER_TIMER3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
-+#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET		0x0088
-+#define AM33XX_CM_PER_TIMER4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
-+#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET		0x008c
-+#define AM33XX_CM_PER_MCASP2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
-+#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET		0x0090
-+#define AM33XX_CM_PER_RNG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
-+#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET		0x0094
-+#define AM33XX_CM_PER_AES0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
-+#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET		0x0098
-+#define AM33XX_CM_PER_AES1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
-+#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET		0x009c
-+#define AM33XX_CM_PER_DES_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
-+#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET		0x00a0
-+#define AM33XX_CM_PER_SHA0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
-+#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET		0x00a4
-+#define AM33XX_CM_PER_PKA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
-+#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET		0x00a8
-+#define AM33XX_CM_PER_GPIO6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
-+#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET		0x00ac
-+#define AM33XX_CM_PER_GPIO1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
-+#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET		0x00b0
-+#define AM33XX_CM_PER_GPIO2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
-+#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET		0x00b4
-+#define AM33XX_CM_PER_GPIO3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
-+#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET		0x00b8
-+#define AM33XX_CM_PER_GPIO4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
-+#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET		0x00bc
-+#define AM33XX_CM_PER_TPCC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
-+#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET		0x00c0
-+#define AM33XX_CM_PER_DCAN0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
-+#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET		0x00c4
-+#define AM33XX_CM_PER_DCAN1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
-+#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET		0x00cc
-+#define AM33XX_CM_PER_EPWMSS1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
-+#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET		0x00d0
-+#define AM33XX_CM_PER_EMIF_FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
-+#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET		0x00d4
-+#define AM33XX_CM_PER_EPWMSS0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
-+#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET		0x00d8
-+#define AM33XX_CM_PER_EPWMSS2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
-+#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET		0x00dc
-+#define AM33XX_CM_PER_L3_INSTR_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
-+#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET			0x00e0
-+#define AM33XX_CM_PER_L3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
-+#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET		0x00e4
-+#define AM33XX_CM_PER_IEEE5000_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
-+#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET		0x00e8
-+#define AM33XX_CM_PER_PRUSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
-+#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET		0x00ec
-+#define AM33XX_CM_PER_TIMER5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
-+#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET		0x00f0
-+#define AM33XX_CM_PER_TIMER6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
-+#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET		0x00f4
-+#define AM33XX_CM_PER_MMC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
-+#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET		0x00f8
-+#define AM33XX_CM_PER_MMC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
-+#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET		0x00fc
-+#define AM33XX_CM_PER_TPTC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
-+#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET		0x0100
-+#define AM33XX_CM_PER_TPTC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
-+#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET		0x0104
-+#define AM33XX_CM_PER_GPIO5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
-+#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET		0x010c
-+#define AM33XX_CM_PER_SPINLOCK_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
-+#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET		0x0110
-+#define AM33XX_CM_PER_MAILBOX0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
-+#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET		0x011c
-+#define AM33XX_CM_PER_L4HS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
-+#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET		0x0120
-+#define AM33XX_CM_PER_L4HS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
-+#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET		0x0124
-+#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
-+#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET		0x0128
-+#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
-+#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET		0x012c
-+#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
-+#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET		0x0130
-+#define AM33XX_CM_PER_OCPWP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
-+#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET		0x0134
-+#define AM33XX_CM_PER_MAILBOX1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
-+#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET		0x0140
-+#define AM33XX_CM_PER_PRUSS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
-+#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET		0x0144
-+#define AM33XX_CM_PER_CPSW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
-+#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET		0x0148
-+#define AM33XX_CM_PER_LCDC_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
-+#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET		0x014c
-+#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
-+#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET	0x0150
-+#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
-+
-+/* CM.WKUP_CM register offsets */
-+#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
-+#define AM33XX_CM_WKUP_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
-+#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET		0x0004
-+#define AM33XX_CM_WKUP_CONTROL_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
-+#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET		0x0008
-+#define AM33XX_CM_WKUP_GPIO0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
-+#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x000c
-+#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
-+#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET		0x0010
-+#define AM33XX_CM_WKUP_TIMER0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
-+#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET		0x0014
-+#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
-+#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET		0x0018
-+#define AM33XX_CM_L3_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
-+#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x001c
-+#define AM33XX_CM_AUTOIDLE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
-+#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET		0x0020
-+#define AM33XX_CM_IDLEST_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET	0x0024
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET	0x0028
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
-+#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET		0x002c
-+#define AM33XX_CM_CLKSEL_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
-+#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET		0x0030
-+#define AM33XX_CM_AUTOIDLE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
-+#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET		0x0034
-+#define AM33XX_CM_IDLEST_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET	0x0038
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET	0x003c
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
-+#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET		0x0040
-+#define AM33XX_CM_CLKSEL_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
-+#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET		0x0044
-+#define AM33XX_CM_AUTOIDLE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
-+#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET		0x0048
-+#define AM33XX_CM_IDLEST_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET	0x004c
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET	0x0050
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
-+#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET		0x0054
-+#define AM33XX_CM_CLKSEL_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
-+#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0058
-+#define AM33XX_CM_AUTOIDLE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
-+#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET		0x005c
-+#define AM33XX_CM_IDLEST_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0060
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x0064
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
-+#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET		0x0068
-+#define AM33XX_CM_CLKSEL_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
-+#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET		0x006c
-+#define AM33XX_CM_AUTOIDLE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
-+#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET		0x0070
-+#define AM33XX_CM_IDLEST_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET	0x0074
-+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET	0x0078
-+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
-+#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET		0x007c
-+#define AM33XX_CM_CLKDCOLDO_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
-+#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET		0x0080
-+#define AM33XX_CM_DIV_M4_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
-+#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET		0x0084
-+#define AM33XX_CM_DIV_M5_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
-+#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET		0x0088
-+#define AM33XX_CM_CLKMODE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
-+#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET		0x008c
-+#define AM33XX_CM_CLKMODE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
-+#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET		0x0090
-+#define AM33XX_CM_CLKMODE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
-+#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET		0x0094
-+#define AM33XX_CM_CLKMODE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
-+#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET		0x0098
-+#define AM33XX_CM_CLKMODE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
-+#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET		0x009c
-+#define AM33XX_CM_CLKSEL_DPLL_PERIPH			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
-+#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET		0x00a0
-+#define AM33XX_CM_DIV_M2_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
-+#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET		0x00a4
-+#define AM33XX_CM_DIV_M2_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
-+#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET		0x00a8
-+#define AM33XX_CM_DIV_M2_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
-+#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET		0x00ac
-+#define AM33XX_CM_DIV_M2_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
-+#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET		0x00b0
-+#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
-+#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET		0x00b4
-+#define AM33XX_CM_WKUP_UART0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
-+#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET		0x00b8
-+#define AM33XX_CM_WKUP_I2C0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
-+#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET		0x00bc
-+#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
-+#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET	0x00c0
-+#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
-+#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x00c4
-+#define AM33XX_CM_WKUP_TIMER1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
-+#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET	0x00c8
-+#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
-+#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET		0x00cc
-+#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
-+#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET		0x00d0
-+#define AM33XX_CM_WKUP_WDT0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
-+#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x00d4
-+#define AM33XX_CM_WKUP_WDT1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
-+#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET		0x00d8
-+#define AM33XX_CM_DIV_M6_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
-+
-+/* CM.DPLL_CM register offsets */
-+#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET			0x0004
-+#define AM33XX_CLKSEL_TIMER7_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
-+#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET			0x0008
-+#define AM33XX_CLKSEL_TIMER2_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
-+#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET			0x000c
-+#define AM33XX_CLKSEL_TIMER3_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
-+#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET			0x0010
-+#define AM33XX_CLKSEL_TIMER4_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
-+#define AM33XX_CM_MAC_CLKSEL_OFFSET			0x0014
-+#define AM33XX_CM_MAC_CLKSEL				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
-+#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET			0x0018
-+#define AM33XX_CLKSEL_TIMER5_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
-+#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET			0x001c
-+#define AM33XX_CLKSEL_TIMER6_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
-+#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET		0x0020
-+#define AM33XX_CM_CPTS_RFT_CLKSEL			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
-+#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET		0x0028
-+#define AM33XX_CLKSEL_TIMER1MS_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
-+#define AM33XX_CLKSEL_GFX_FCLK_OFFSET			0x002c
-+#define AM33XX_CLKSEL_GFX_FCLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
-+#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET		0x0030
-+#define AM33XX_CLKSEL_PRUSS_OCP_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
-+#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET		0x0034
-+#define AM33XX_CLKSEL_LCDC_PIXEL_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
-+#define AM33XX_CLKSEL_WDT1_CLK_OFFSET			0x0038
-+#define AM33XX_CLKSEL_WDT1_CLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
-+#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET		0x003c
-+#define AM33XX_CLKSEL_GPIO0_DBCLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
-+
-+/* CM.MPU_CM register offsets */
-+#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET			0x0000
-+#define AM33XX_CM_MPU_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
-+#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0004
-+#define AM33XX_CM_MPU_MPU_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
-+
-+/* CM.DEVICE_CM register offsets */
-+#define AM33XX_CM_CLKOUT_CTRL_OFFSET			0x0000
-+#define AM33XX_CM_CLKOUT_CTRL				AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
-+
-+/* CM.RTC_CM register offsets */
-+#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET		0x0000
-+#define AM33XX_CM_RTC_RTC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
-+#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET			0x0004
-+#define AM33XX_CM_RTC_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
-+
-+/* CM.GFX_CM register offsets */
-+#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET		0x0000
-+#define AM33XX_CM_GFX_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
-+#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET		0x0004
-+#define AM33XX_CM_GFX_GFX_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
-+#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET		0x0008
-+#define AM33XX_CM_GFX_BITBLT_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
-+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET	0x000c
-+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1		AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
-+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET		0x0010
-+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
-+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET		0x0014
-+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
-+
-+/* CM.CEFUSE_CM register offsets */
-+#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET		0x0000
-+#define AM33XX_CM_CEFUSE_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
-+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
-+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
-index e96f53e..6a83630 100644
---- a/arch/arm/mach-omap2/cm44xx.c
-+++ b/arch/arm/mach-omap2/cm44xx.c
-@@ -18,7 +18,7 @@
- #include <linux/err.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "cm.h"
- #include "cm1_44xx.h"
-diff --git a/arch/arm/mach-omap2/cminst33xx.h b/arch/arm/mach-omap2/cminst33xx.h
-new file mode 100644
-index 0000000..881c0af
---- /dev/null
-+++ b/arch/arm/mach-omap2/cminst33xx.h
-@@ -0,0 +1,63 @@
-+/*
-+ * am33xx Clock Management (CM) function prototypes
-+ *
-+ * Copyright (C) 2010 Nokia Corporation
-+ * Paul Walmsley
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
-+#define __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
-+
-+extern bool am33xx_cminst_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
-+extern void am33xx_cminst_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
-+extern void am33xx_cminst_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
-+extern void am33xx_cminst_clkdm_force_sleep(s16 inst, u16 cdoffs);
-+extern void am33xx_cminst_clkdm_force_wakeup(s16 inst, u16 cdoffs);
-+
-+extern int am33xx_cminst_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs);
-+
-+#ifdef CONFIG_SOC_OMAPAM33XX
-+extern int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
-+					 u16 clkctrl_offs);
-+
-+extern void am33xx_cminst_module_enable(u8 mode, u16 inst, s16 cdoffs,
-+				       u16 clkctrl_offs);
-+extern void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
-+					u16 clkctrl_offs);
-+
-+#else
-+
-+static inline int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
-+					u16 clkctrl_offs)
-+{
-+	return 0;
-+}
-+
-+static inline void am33xx_cminst_module_enable(u8 mode, u16 inst,
-+				s16 cdoffs, u16 clkctrl_offs)
-+{
-+}
-+
-+static inline void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
-+				 u16 clkctrl_offs)
-+{
-+}
-+
-+#endif
-+
-+/*
-+ * In an ideal world, we would not export these low-level functions,
-+ * but this will probably take some time to fix properly
-+ */
-+extern u32 am33xx_cminst_read_inst_reg(s16 inst, u16 idx);
-+extern void am33xx_cminst_write_inst_reg(u32 val, s16 inst, u16 idx);
-+extern u32 am33xx_cminst_rmw_inst_reg_bits(u32 mask, u32 bits,
-+					   s16 inst, s16 idx);
-+extern u32 am33xx_cminst_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
-+extern u32 am33xx_cminst_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
-+extern u32 am33xx_cminst_read_inst_reg_bits(u16 inst, s16 idx, u32 mask);
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
-index eb2a472..1ca9e12 100644
---- a/arch/arm/mach-omap2/cminst44xx.c
-+++ b/arch/arm/mach-omap2/cminst44xx.c
-@@ -20,7 +20,7 @@
- #include <linux/err.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "cm.h"
- #include "cm1_44xx.h"
-@@ -31,6 +31,7 @@
- #include "cm-regbits-44xx.h"
- #include "prcm44xx.h"
- #include "prm44xx.h"
-+#include "prm33xx.h"
- #include "prcm_mpu44xx.h"
- 
- /*
-@@ -49,13 +50,21 @@
- #define CLKCTRL_IDLEST_INTERFACE_IDLE		0x2
- #define CLKCTRL_IDLEST_DISABLED			0x3
- 
--static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
-+static u32 **_cm_bases;
-+static u32 max_cm_partitions;
-+
-+static u32 *omap44xx_cm_bases[] = {
- 	[OMAP4430_INVALID_PRCM_PARTITION]	= 0,
--	[OMAP4430_PRM_PARTITION]		= OMAP4430_PRM_BASE,
--	[OMAP4430_CM1_PARTITION]		= OMAP4430_CM1_BASE,
--	[OMAP4430_CM2_PARTITION]		= OMAP4430_CM2_BASE,
-+	[OMAP4430_PRM_PARTITION]		= OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
-+	[OMAP4430_CM1_PARTITION]		= OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE),
-+	[OMAP4430_CM2_PARTITION]		= OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
- 	[OMAP4430_SCRM_PARTITION]		= 0,
--	[OMAP4430_PRCM_MPU_PARTITION]		= OMAP4430_PRCM_MPU_BASE,
-+	[OMAP4430_PRCM_MPU_PARTITION]		= OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
-+};
-+
-+static u32 *am33xx_cm_bases[] = {
-+	[OMAP4430_INVALID_PRCM_PARTITION]	= 0,
-+	[AM33XX_PRM_PARTITION]			= AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE),
- };
- 
- /* Private functions */
-@@ -103,19 +112,19 @@ static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
- /* Read a register in a CM instance */
- u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
- {
--	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
-+	BUG_ON(part >= max_cm_partitions ||
- 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
- 	       !_cm_bases[part]);
--	return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
-+	return __raw_readl(_cm_bases[part] + ((inst + idx)/sizeof(u32)));
- }
- 
- /* Write into a register in a CM instance */
- void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
- {
--	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
-+	BUG_ON(part >= max_cm_partitions ||
- 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
- 	       !_cm_bases[part]);
--	__raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
-+	__raw_writel(val, _cm_bases[part] + ((inst + idx)/sizeof(u32)));
- }
- 
- /* Read-modify-write a register in CM1. Caller must lock */
-@@ -349,3 +358,14 @@ void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
- 	v &= ~OMAP4430_MODULEMODE_MASK;
- 	omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
- }
-+
-+void __init omap44xx_cminst_init(void)
-+{
-+	if (cpu_is_omap44xx()) {
-+		_cm_bases = omap44xx_cm_bases;
-+		max_cm_partitions = ARRAY_SIZE(omap44xx_cm_bases);
-+	} else if (cpu_is_am33xx()) {
-+		_cm_bases = am33xx_cm_bases;
-+		max_cm_partitions = ARRAY_SIZE(am33xx_cm_bases);
-+	}
-+}
-diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
-index a018a73..e37c779 100644
---- a/arch/arm/mach-omap2/cminst44xx.h
-+++ b/arch/arm/mach-omap2/cminst44xx.h
-@@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
- 
- extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
- 
--# ifdef CONFIG_ARCH_OMAP4
-+# if defined (CONFIG_ARCH_OMAP4) || defined (CONFIG_SOC_OMAPAM33XX)
- extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
- 					 u16 clkctrl_offs);
- 
-@@ -63,4 +63,5 @@ extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
- extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
- 					   u32 mask);
- 
-+extern void __init omap44xx_cminst_init(void);
- #endif
-diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
-index bcb0c58..5293192 100644
---- a/arch/arm/mach-omap2/common-board-devices.c
-+++ b/arch/arm/mach-omap2/common-board-devices.c
-@@ -33,7 +33,6 @@
- 	defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
- static struct omap2_mcspi_device_config ads7846_mcspi_config = {
- 	.turbo_mode	= 0,
--	.single_channel	= 1,	/* 0: slave, 1: master */
- };
- 
- static struct ads7846_platform_data ads7846_config = {
-@@ -92,49 +91,3 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
- {
- }
- #endif
--
--#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
--static struct omap_nand_platform_data nand_data;
--
--void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
--				 int nr_parts)
--{
--	u8 cs = 0;
--	u8 nandcs = GPMC_CS_NUM + 1;
--
--	/* find out the chip-select on which NAND exists */
--	while (cs < GPMC_CS_NUM) {
--		u32 ret = 0;
--		ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
--
--		if ((ret & 0xC00) == 0x800) {
--			printk(KERN_INFO "Found NAND on CS%d\n", cs);
--			if (nandcs > GPMC_CS_NUM)
--				nandcs = cs;
--		}
--		cs++;
--	}
--
--	if (nandcs > GPMC_CS_NUM) {
--		printk(KERN_INFO "NAND: Unable to find configuration "
--				 "in GPMC\n ");
--		return;
--	}
--
--	if (nandcs < GPMC_CS_NUM) {
--		nand_data.cs = nandcs;
--		nand_data.parts = parts;
--		nand_data.nr_parts = nr_parts;
--		nand_data.devsize = options;
--
--		printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
--		if (gpmc_nand_init(&nand_data) < 0)
--			printk(KERN_ERR "Unable to register NAND device\n");
--	}
--}
--#else
--void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
--				 int nr_parts)
--{
--}
--#endif
-diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
-index a0b4a428..72bb41b 100644
---- a/arch/arm/mach-omap2/common-board-devices.h
-+++ b/arch/arm/mach-omap2/common-board-devices.h
-@@ -10,6 +10,5 @@ struct ads7846_platform_data;
- 
- void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
- 		       struct ads7846_platform_data *board_pdata);
--void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
- 
- #endif /* __OMAP_COMMON_BOARD_DEVICES__ */
-diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
-index 110e5b9..aaf4211 100644
---- a/arch/arm/mach-omap2/common.c
-+++ b/arch/arm/mach-omap2/common.c
-@@ -17,7 +17,7 @@
- #include <linux/clk.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/board.h>
- #include <plat/mux.h>
- 
-@@ -110,23 +110,49 @@ void __init omap3_map_io(void)
- 
- /*
-  * Adjust TAP register base such that omap3_check_revision accesses the correct
-- * TI816X register for checking device ID (it adds 0x204 to tap base while
-- * TI816X DEVICE ID register is at offset 0x600 from control base).
-+ * TI81XX register for checking device ID (it adds 0x204 to tap base while
-+ * TI81XX DEVICE ID register is at offset 0x600 from control base).
-  */
--#define TI816X_TAP_BASE		(TI816X_CTRL_BASE + \
--				TI816X_CONTROL_DEVICE_ID - 0x204)
-+#define TI81XX_TAP_BASE		(TI81XX_CTRL_BASE + \
-+				TI81XX_CONTROL_DEVICE_ID - 0x204)
- 
--static struct omap_globals ti816x_globals = {
-+static struct omap_globals ti81xx_globals = {
- 	.class  = OMAP343X_CLASS,
--	.tap    = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
--	.ctrl   = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
--	.prm    = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
--	.cm     = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
-+	.tap    = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
-+	.ctrl   = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
-+	.prm    = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
-+	.cm     = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
- };
- 
--void __init omap2_set_globals_ti816x(void)
-+void __init omap2_set_globals_ti81xx(void)
- {
--	__omap2_set_globals(&ti816x_globals);
-+	__omap2_set_globals(&ti81xx_globals);
-+}
-+
-+void __init ti81xx_map_io(void)
-+{
-+	omapti81xx_map_common_io();
-+}
-+
-+#define AM33XX_TAP_BASE		(AM33XX_CTRL_BASE + \
-+				TI81XX_CONTROL_DEVICE_ID - 0x204)
-+
-+static struct omap_globals am33xx_globals = {
-+	.class  = AM335X_CLASS,
-+	.tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
-+	.ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
-+	.prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
-+	.cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
-+};
-+
-+void __init omap2_set_globals_am33xx(void)
-+{
-+	__omap2_set_globals(&am33xx_globals);
-+}
-+
-+void __init am33xx_map_io(void)
-+{
-+	omapam33xx_map_common_io();
- }
- #endif
- 
-diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
-new file mode 100644
-index 0000000..f62fa39
---- /dev/null
-+++ b/arch/arm/mach-omap2/common.h
-@@ -0,0 +1,240 @@
-+/*
-+ * Header for code common to all OMAP2+ machines.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the  GNU General Public License along
-+ * with this program; if not, write  to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
-+#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
-+#ifndef __ASSEMBLER__
-+
-+#include <linux/delay.h>
-+#include <plat/common.h>
-+#include <asm/proc-fns.h>
-+
-+#ifdef CONFIG_SOC_OMAP2420
-+extern void omap242x_map_common_io(void);
-+#else
-+static inline void omap242x_map_common_io(void)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_SOC_OMAP2430
-+extern void omap243x_map_common_io(void);
-+#else
-+static inline void omap243x_map_common_io(void)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_ARCH_OMAP3
-+extern void omap34xx_map_common_io(void);
-+#else
-+static inline void omap34xx_map_common_io(void)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_SOC_OMAPTI81XX
-+extern void omapti81xx_map_common_io(void);
-+#else
-+static inline void omapti81xx_map_common_io(void)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_SOC_OMAPAM33XX
-+extern void omapam33xx_map_common_io(void);
-+#else
-+static inline void omapam33xx_map_common_io(void)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_ARCH_OMAP4
-+extern void omap44xx_map_common_io(void);
-+#else
-+static inline void omap44xx_map_common_io(void)
-+{
-+}
-+#endif
-+
-+extern void omap2_init_common_infrastructure(void);
-+
-+extern struct sys_timer omap2_timer;
-+extern struct sys_timer omap3_timer;
-+extern struct sys_timer omap3_secure_timer;
-+extern struct sys_timer omap3_am33xx_timer;
-+extern struct sys_timer omap4_timer;
-+
-+void omap2420_init_early(void);
-+void omap2430_init_early(void);
-+void omap3430_init_early(void);
-+void omap35xx_init_early(void);
-+void omap3630_init_early(void);
-+void omap3_init_early(void);	/* Do not use this one */
-+void am35xx_init_early(void);
-+void ti81xx_init_early(void);
-+void am33xx_init_early(void);
-+void omap4430_init_early(void);
-+
-+/*
-+ * IO bases for various OMAP processors
-+ * Except the tap base, rest all the io bases
-+ * listed are physical addresses.
-+ */
-+struct omap_globals {
-+	u32		class;		/* OMAP class to detect */
-+	void __iomem	*tap;		/* Control module ID code */
-+	void __iomem	*sdrc;           /* SDRAM Controller */
-+	void __iomem	*sms;            /* SDRAM Memory Scheduler */
-+	void __iomem	*ctrl;           /* System Control Module */
-+	void __iomem	*ctrl_pad;	/* PAD Control Module */
-+	void __iomem	*prm;            /* Power and Reset Management */
-+	void __iomem	*cm;             /* Clock Management */
-+	void __iomem	*cm2;
-+};
-+
-+void omap2_set_globals_242x(void);
-+void omap2_set_globals_243x(void);
-+void omap2_set_globals_3xxx(void);
-+void omap2_set_globals_443x(void);
-+void omap2_set_globals_ti81xx(void);
-+void omap2_set_globals_am33xx(void);
-+
-+/* These get called from omap2_set_globals_xxxx(), do not call these */
-+void omap2_set_globals_tap(struct omap_globals *);
-+void omap2_set_globals_sdrc(struct omap_globals *);
-+void omap2_set_globals_control(struct omap_globals *);
-+void omap2_set_globals_prcm(struct omap_globals *);
-+
-+void omap242x_map_io(void);
-+void omap243x_map_io(void);
-+void omap3_map_io(void);
-+void am33xx_map_io(void);
-+void omap4_map_io(void);
-+void ti81xx_map_io(void);
-+
-+/**
-+ * omap_test_timeout - busy-loop, testing a condition
-+ * @cond: condition to test until it evaluates to true
-+ * @timeout: maximum number of microseconds in the timeout
-+ * @index: loop index (integer)
-+ *
-+ * Loop waiting for @cond to become true or until at least @timeout
-+ * microseconds have passed.  To use, define some integer @index in the
-+ * calling code.  After running, if @index == @timeout, then the loop has
-+ * timed out.
-+ */
-+#define omap_test_timeout(cond, timeout, index)			\
-+({								\
-+	for (index = 0; index < timeout; index++) {		\
-+		if (cond)					\
-+			break;					\
-+		udelay(1);					\
-+	}							\
-+})
-+
-+extern struct device *omap2_get_mpuss_device(void);
-+extern struct device *omap2_get_iva_device(void);
-+extern struct device *omap2_get_l3_device(void);
-+extern struct device *omap4_get_dsp_device(void);
-+
-+void omap2_init_irq(void);
-+void omap3_init_irq(void);
-+void ti81xx_init_irq(void);
-+extern int omap_irq_pending(void);
-+void omap_intc_save_context(void);
-+void omap_intc_restore_context(void);
-+void omap3_intc_suspend(void);
-+void omap3_intc_prepare_idle(void);
-+void omap3_intc_resume_idle(void);
-+void omap2_intc_handle_irq(struct pt_regs *regs);
-+void omap3_intc_handle_irq(struct pt_regs *regs);
-+
-+#ifdef CONFIG_CACHE_L2X0
-+extern void __iomem *omap4_get_l2cache_base(void);
-+#endif
-+
-+#ifdef CONFIG_SMP
-+extern void __iomem *omap4_get_scu_base(void);
-+#else
-+static inline void __iomem *omap4_get_scu_base(void)
-+{
-+	return NULL;
-+}
-+#endif
-+
-+extern void __init gic_init_irq(void);
-+extern void omap_smc1(u32 fn, u32 arg);
-+extern void __iomem *omap4_get_sar_ram_base(void);
-+extern void omap_do_wfi(void);
-+
-+#ifdef CONFIG_SMP
-+/* Needed for secondary core boot */
-+extern void omap_secondary_startup(void);
-+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
-+extern void omap_auxcoreboot_addr(u32 cpu_addr);
-+extern u32 omap_read_auxcoreboot0(void);
-+#endif
-+
-+#if defined(CONFIG_SMP) && defined(CONFIG_PM)
-+extern int omap4_mpuss_init(void);
-+extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
-+extern int omap4_finish_suspend(unsigned long cpu_state);
-+extern void omap4_cpu_resume(void);
-+extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
-+extern u32 omap4_mpuss_read_prev_context_state(void);
-+#else
-+static inline int omap4_enter_lowpower(unsigned int cpu,
-+					unsigned int power_state)
-+{
-+	cpu_do_idle();
-+	return 0;
-+}
-+
-+static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
-+{
-+	cpu_do_idle();
-+	return 0;
-+}
-+
-+static inline int omap4_mpuss_init(void)
-+{
-+	return 0;
-+}
-+
-+static inline int omap4_finish_suspend(unsigned long cpu_state)
-+{
-+	return 0;
-+}
-+
-+static inline void omap4_cpu_resume(void)
-+{}
-+
-+static inline u32 omap4_mpuss_read_prev_context_state(void)
-+{
-+	return 0;
-+}
-+#endif
-+#endif /* __ASSEMBLER__ */
-+#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
-diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
-index e34d27f..f7fc60e 100644
---- a/arch/arm/mach-omap2/control.c
-+++ b/arch/arm/mach-omap2/control.c
-@@ -13,9 +13,10 @@
- #undef DEBUG
- 
- #include <linux/kernel.h>
-+#include <linux/module.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/sdrc.h>
- 
- #include "cm-regbits-34xx.h"
-@@ -190,6 +191,7 @@ void omap_ctrl_writel(u32 val, u16 offset)
- {
- 	__raw_writel(val, OMAP_CTRL_REGADDR(offset));
- }
-+EXPORT_SYMBOL_GPL(omap_ctrl_writel);
- 
- /*
-  * On OMAP4 control pad are not addressable from control
-diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
-index d4ef75d..4aeefbd 100644
---- a/arch/arm/mach-omap2/control.h
-+++ b/arch/arm/mach-omap2/control.h
-@@ -29,6 +29,8 @@
- 		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
- #define OMAP343X_CTRL_REGADDR(reg)					\
- 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
-+#define AM33XX_CTRL_REGADDR(reg)					\
-+		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
- #else
- #define OMAP242X_CTRL_REGADDR(reg)					\
- 		OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-@@ -36,6 +38,8 @@
- 		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
- #define OMAP343X_CTRL_REGADDR(reg)					\
- 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
-+#define AM33XX_CTRL_REGADDR(reg)					\
-+		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
- #endif /* __ASSEMBLY__ */
- 
- /*
-@@ -52,8 +56,14 @@
- #define OMAP343X_CONTROL_PADCONFS_WKUP	0xa00
- #define OMAP343X_CONTROL_GENERAL_WKUP	0xa60
- 
--/* TI816X spefic control submodules */
--#define TI816X_CONTROL_DEVCONF		0x600
-+/* TI81XX spefic control submodules */
-+#define TI81XX_CONTROL_DEVCONF		0x600
-+
-+/* TI81XX CONTROL_DEVCONF register offsets */
-+#define TI81XX_CONTROL_MAC_ID0_LO       (TI81XX_CONTROL_DEVCONF + 0x030)
-+#define TI81XX_CONTROL_MAC_ID0_HI       (TI81XX_CONTROL_DEVCONF + 0x034)
-+#define TI81XX_CONTROL_MAC_ID1_LO       (TI81XX_CONTROL_DEVCONF + 0x038)
-+#define TI81XX_CONTROL_MAC_ID1_HI       (TI81XX_CONTROL_DEVCONF + 0x03c)
- 
- /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
- 
-@@ -244,8 +254,8 @@
- #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
- #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
- 
--/* TI816X CONTROL_DEVCONF register offsets */
--#define TI816X_CONTROL_DEVICE_ID	(TI816X_CONTROL_DEVCONF + 0x000)
-+/* TI81XX CONTROL_DEVCONF register offsets */
-+#define TI81XX_CONTROL_DEVICE_ID	(TI81XX_CONTROL_DEVCONF + 0x000)
- 
- /*
-  * REVISIT: This list of registers is not comprehensive - there are more
-@@ -338,6 +348,35 @@
- #define AM35XX_HECC_SW_RST		BIT(3)
- #define AM35XX_VPFE_PCLK_SW_RST		BIT(4)
- 
-+/* AM33XX CONTROL_STATUS bits */
-+#define AM33XX_SYSBOOT0			(0xff << 0)
-+#define AM33XX_DEVTYPE			(1 << 8)
-+#define AM33XX_GPMC_CS0_BW		(1 << 16)
-+#define AM33XX_GPMC_CS0_WAITEN		(1 << 17)
-+#define AM33XX_GPMC_CS0_ADMUX		(0x3 << 18)
-+#define AM33XX_SYSBOOT1			(0x3 << 22)
-+
-+/*
-+ * CONTROL AM33XX STATUS register to identify boot-time configurations
-+ */
-+#define AM33XX_CONTROL_STATUS_OFF	0x040
-+#define AM33XX_CONTROL_STATUS		AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE + \
-+						AM33XX_CONTROL_STATUS_OFF)
-+#define AM33XX_DEV_FEATURE		0x604
-+#define AM33XX_SGX_SHIFT		29
-+#define AM33XX_SGX_MASK			(1 << AM33XX_SGX_SHIFT)
-+
-+/*
-+ * CONTROL AM33XX PWMSS_CTRL register to enable time base clock Enable
-+ */
-+
-+#define AM33XX_CONTROL_PWMSS_CTRL_OFS	0x664
-+#define AM33XX_PWMSS0_TBCLKEN		0x0
-+#define AM33XX_PWMSS1_TBCLKEN		0x1
-+#define AM33XX_PWMSS2_TBCLKEN		0x2
-+#define AM33XX_CONTROL_PWMSS_CTRL	AM33XX_L4_WK_IO_ADDRESS( \
-+		AM33XX_CTRL_BASE + AM33XX_CONTROL_PWMSS_CTRL_OFS)
-+
- /*
-  * CONTROL OMAP STATUS register to identify OMAP3 features
-  */
-diff --git a/arch/arm/mach-omap2/cpuidle33xx.c b/arch/arm/mach-omap2/cpuidle33xx.c
-new file mode 100644
-index 0000000..7e14de4
---- /dev/null
-+++ b/arch/arm/mach-omap2/cpuidle33xx.c
-@@ -0,0 +1,179 @@
-+/*
-+ * CPU idle for AM33XX SoCs
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated. http://www.ti.com/
-+ *
-+ * Derived from Davinci CPU idle code
-+ * (arch/arm/mach-davinci/cpuidle.c)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/cpuidle.h>
-+#include <linux/sched.h>
-+#include <asm/proc-fns.h>
-+
-+#include <plat/emif.h>
-+
-+#include "cpuidle33xx.h"
-+
-+#define AM33XX_CPUIDLE_MAX_STATES	2
-+
-+struct am33xx_ops {
-+	void (*enter) (u32 flags);
-+	void (*exit) (u32 flags);
-+	u32 flags;
-+};
-+
-+/* fields in am33xx_ops.flags */
-+#define AM33XX_CPUIDLE_FLAGS_DDR2_PWDN	BIT(0)
-+
-+static struct cpuidle_driver am33xx_idle_driver = {
-+	.name	= "cpuidle-am33xx",
-+	.owner	= THIS_MODULE,
-+};
-+
-+static DEFINE_PER_CPU(struct cpuidle_device, am33xx_cpuidle_device);
-+static void __iomem *emif_base;
-+
-+static void am33xx_save_ddr_power(int enter, bool pdown)
-+{
-+	u32 val;
-+
-+	val = __raw_readl(emif_base + EMIF4_0_SDRAM_MGMT_CTRL);
-+
-+	/* TODO: Choose the mode based on memory type */
-+	if (enter)
-+		val = SELF_REFRESH_ENABLE(64);
-+	else
-+		val = SELF_REFRESH_DISABLE;
-+
-+	__raw_writel(val, emif_base + EMIF4_0_SDRAM_MGMT_CTRL);
-+}
-+
-+static void am33xx_c2state_enter(u32 flags)
-+{
-+	am33xx_save_ddr_power(1, !!(flags & AM33XX_CPUIDLE_FLAGS_DDR2_PWDN));
-+}
-+
-+static void am33xx_c2state_exit(u32 flags)
-+{
-+	am33xx_save_ddr_power(0, !!(flags & AM33XX_CPUIDLE_FLAGS_DDR2_PWDN));
-+}
-+
-+static struct am33xx_ops am33xx_states[AM33XX_CPUIDLE_MAX_STATES] = {
-+	[1] = {
-+		.enter	= am33xx_c2state_enter,
-+		.exit	= am33xx_c2state_exit,
-+	},
-+};
-+
-+/* Actual code that puts the SoC in different idle states */
-+static int am33xx_enter_idle(struct cpuidle_device *dev,
-+				struct cpuidle_driver *drv, int index)
-+{
-+	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
-+	struct am33xx_ops *ops = cpuidle_get_statedata(state_usage);
-+	struct timeval before, after;
-+	int idle_time;
-+
-+	local_irq_disable();
-+	do_gettimeofday(&before);
-+
-+	if (ops && ops->enter)
-+		ops->enter(ops->flags);
-+
-+	/* Wait for interrupt state */
-+	cpu_do_idle();
-+	if (ops && ops->exit)
-+		ops->exit(ops->flags);
-+
-+	do_gettimeofday(&after);
-+	local_irq_enable();
-+	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
-+			(after.tv_usec - before.tv_usec);
-+
-+	dev->last_residency = idle_time;
-+
-+	return index;
-+}
-+
-+static int __init am33xx_cpuidle_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+	struct cpuidle_device *device;
-+	struct cpuidle_driver *driver = &am33xx_idle_driver;
-+	struct am33xx_cpuidle_config *pdata = pdev->dev.platform_data;
-+
-+	device = &per_cpu(am33xx_cpuidle_device, smp_processor_id());
-+
-+	if (!pdata) {
-+		dev_err(&pdev->dev, "cannot get platform data\n");
-+		return -ENOENT;
-+	}
-+
-+	emif_base = pdata->emif_base;
-+
-+	/* Wait for interrupt state */
-+	driver->states[0].enter = am33xx_enter_idle;
-+	driver->states[0].exit_latency = 1;
-+	driver->states[0].target_residency = 10000;
-+	driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
-+	strcpy(driver->states[0].name, "WFI");
-+	strcpy(driver->states[0].desc, "Wait for interrupt");
-+
-+	/* Wait for interrupt and DDR self refresh state */
-+	driver->states[1].enter = am33xx_enter_idle;
-+	driver->states[1].exit_latency = 100;
-+	driver->states[1].target_residency = 10000;
-+	driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
-+	strcpy(driver->states[1].name, "DDR SR");
-+	strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
-+	if (pdata->ddr2_pdown)
-+		am33xx_states[1].flags |= AM33XX_CPUIDLE_FLAGS_DDR2_PWDN;
-+	cpuidle_set_statedata(&device->states_usage[1], &am33xx_states[1]);
-+
-+	device->state_count = AM33XX_CPUIDLE_MAX_STATES;
-+	driver->state_count = AM33XX_CPUIDLE_MAX_STATES;
-+
-+	ret = cpuidle_register_driver(&am33xx_idle_driver);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to register driver\n");
-+		return ret;
-+	}
-+
-+	ret = cpuidle_register_device(device);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to register device\n");
-+		cpuidle_unregister_driver(&am33xx_idle_driver);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static struct platform_driver am33xx_cpuidle_driver = {
-+	.driver = {
-+		.name	= "cpuidle-am33xx",
-+		.owner	= THIS_MODULE,
-+	},
-+};
-+
-+static int __init am33xx_cpuidle_init(void)
-+{
-+	return platform_driver_probe(&am33xx_cpuidle_driver,
-+						am33xx_cpuidle_probe);
-+}
-+device_initcall(am33xx_cpuidle_init);
-diff --git a/arch/arm/mach-omap2/cpuidle33xx.h b/arch/arm/mach-omap2/cpuidle33xx.h
-new file mode 100644
-index 0000000..c092fba
---- /dev/null
-+++ b/arch/arm/mach-omap2/cpuidle33xx.h
-@@ -0,0 +1,24 @@
-+/*
-+ * TI AM33XX cpuidle platform support
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef _AM33XX_CPUIDLE_H
-+#define _AM33XX_CPUIDLE_H
-+
-+struct am33xx_cpuidle_config {
-+	u32 ddr2_pdown;
-+	void __iomem *emif_base;
-+};
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
-index 942bb4f..464cffd 100644
---- a/arch/arm/mach-omap2/cpuidle34xx.c
-+++ b/arch/arm/mach-omap2/cpuidle34xx.c
-@@ -25,15 +25,16 @@
- #include <linux/sched.h>
- #include <linux/cpuidle.h>
- #include <linux/export.h>
-+#include <linux/cpu_pm.h>
- 
- #include <plat/prcm.h>
- #include <plat/irqs.h>
- #include "powerdomain.h"
- #include "clockdomain.h"
--#include <plat/serial.h>
- 
- #include "pm.h"
- #include "control.h"
-+#include "common.h"
- 
- #ifdef CONFIG_CPU_IDLE
- 
-@@ -123,9 +124,23 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
- 		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
- 	}
- 
-+	/*
-+	 * Call idle CPU PM enter notifier chain so that
-+	 * VFP context is saved.
-+	 */
-+	if (mpu_state == PWRDM_POWER_OFF)
-+		cpu_pm_enter();
-+
- 	/* Execute ARM wfi */
- 	omap_sram_idle();
- 
-+	/*
-+	 * Call idle CPU PM enter notifier chain to restore
-+	 * VFP context.
-+	 */
-+	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
-+		cpu_pm_exit();
-+
- 	/* Re-allow idle for C1 */
- 	if (index == 0) {
- 		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
-@@ -244,11 +259,6 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
- 	struct omap3_idle_statedata *cx;
- 	int ret;
- 
--	if (!omap3_can_sleep()) {
--		new_state_idx = drv->safe_state_index;
--		goto select_state;
--	}
--
- 	/*
- 	 * Prevent idle completely if CAM is active.
- 	 * CAM does not have wakeup capability in OMAP3.
-diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
-new file mode 100644
-index 0000000..cfdbb86
---- /dev/null
-+++ b/arch/arm/mach-omap2/cpuidle44xx.c
-@@ -0,0 +1,245 @@
-+/*
-+ * OMAP4 CPU idle Routines
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ * Rajendra Nayak <rnayak@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/sched.h>
-+#include <linux/cpuidle.h>
-+#include <linux/cpu_pm.h>
-+#include <linux/export.h>
-+#include <linux/clockchips.h>
-+
-+#include <asm/proc-fns.h>
-+
-+#include "common.h"
-+#include "pm.h"
-+#include "prm.h"
-+
-+#ifdef CONFIG_CPU_IDLE
-+
-+/* Machine specific information to be recorded in the C-state driver_data */
-+struct omap4_idle_statedata {
-+	u32 cpu_state;
-+	u32 mpu_logic_state;
-+	u32 mpu_state;
-+	u8 valid;
-+};
-+
-+static struct cpuidle_params cpuidle_params_table[] = {
-+	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
-+	{.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
-+	/* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
-+	{.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
-+	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
-+	{.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
-+};
-+
-+#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
-+
-+struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
-+static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
-+
-+/**
-+ * omap4_enter_idle - Programs OMAP4 to enter the specified state
-+ * @dev: cpuidle device
-+ * @drv: cpuidle driver
-+ * @index: the index of state to be entered
-+ *
-+ * Called from the CPUidle framework to program the device to the
-+ * specified low power state selected by the governor.
-+ * Returns the amount of time spent in the low power state.
-+ */
-+static int omap4_enter_idle(struct cpuidle_device *dev,
-+			struct cpuidle_driver *drv,
-+			int index)
-+{
-+	struct omap4_idle_statedata *cx =
-+			cpuidle_get_statedata(&dev->states_usage[index]);
-+	struct timespec ts_preidle, ts_postidle, ts_idle;
-+	u32 cpu1_state;
-+	int idle_time;
-+	int new_state_idx;
-+	int cpu_id = smp_processor_id();
-+
-+	/* Used to keep track of the total time in idle */
-+	getnstimeofday(&ts_preidle);
-+
-+	local_irq_disable();
-+	local_fiq_disable();
-+
-+	/*
-+	 * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
-+	 * This is necessary to honour hardware recommondation
-+	 * of triggeing all the possible low power modes once CPU1 is
-+	 * out of coherency and in OFF mode.
-+	 * Update dev->last_state so that governor stats reflects right
-+	 * data.
-+	 */
-+	cpu1_state = pwrdm_read_pwrst(cpu1_pd);
-+	if (cpu1_state != PWRDM_POWER_OFF) {
-+		new_state_idx = drv->safe_state_index;
-+		cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
-+	}
-+
-+	if (index > 0)
-+		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
-+
-+	/*
-+	 * Call idle CPU PM enter notifier chain so that
-+	 * VFP and per CPU interrupt context is saved.
-+	 */
-+	if (cx->cpu_state == PWRDM_POWER_OFF)
-+		cpu_pm_enter();
-+
-+	pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
-+	omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
-+
-+	/*
-+	 * Call idle CPU cluster PM enter notifier chain
-+	 * to save GIC and wakeupgen context.
-+	 */
-+	if ((cx->mpu_state == PWRDM_POWER_RET) &&
-+		(cx->mpu_logic_state == PWRDM_POWER_OFF))
-+			cpu_cluster_pm_enter();
-+
-+	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
-+
-+	/*
-+	 * Call idle CPU PM exit notifier chain to restore
-+	 * VFP and per CPU IRQ context. Only CPU0 state is
-+	 * considered since CPU1 is managed by CPU hotplug.
-+	 */
-+	if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
-+		cpu_pm_exit();
-+
-+	/*
-+	 * Call idle CPU cluster PM exit notifier chain
-+	 * to restore GIC and wakeupgen context.
-+	 */
-+	if (omap4_mpuss_read_prev_context_state())
-+		cpu_cluster_pm_exit();
-+
-+	if (index > 0)
-+		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
-+
-+	getnstimeofday(&ts_postidle);
-+	ts_idle = timespec_sub(ts_postidle, ts_preidle);
-+
-+	local_irq_enable();
-+	local_fiq_enable();
-+
-+	idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
-+								USEC_PER_SEC;
-+
-+	/* Update cpuidle counters */
-+	dev->last_residency = idle_time;
-+
-+	return index;
-+}
-+
-+DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
-+
-+struct cpuidle_driver omap4_idle_driver = {
-+	.name =		"omap4_idle",
-+	.owner =	THIS_MODULE,
-+};
-+
-+static inline void _fill_cstate(struct cpuidle_driver *drv,
-+					int idx, const char *descr)
-+{
-+	struct cpuidle_state *state = &drv->states[idx];
-+
-+	state->exit_latency	= cpuidle_params_table[idx].exit_latency;
-+	state->target_residency	= cpuidle_params_table[idx].target_residency;
-+	state->flags		= CPUIDLE_FLAG_TIME_VALID;
-+	state->enter		= omap4_enter_idle;
-+	sprintf(state->name, "C%d", idx + 1);
-+	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
-+}
-+
-+static inline struct omap4_idle_statedata *_fill_cstate_usage(
-+					struct cpuidle_device *dev,
-+					int idx)
-+{
-+	struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
-+	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
-+
-+	cx->valid		= cpuidle_params_table[idx].valid;
-+	cpuidle_set_statedata(state_usage, cx);
-+
-+	return cx;
-+}
-+
-+
-+
-+/**
-+ * omap4_idle_init - Init routine for OMAP4 idle
-+ *
-+ * Registers the OMAP4 specific cpuidle driver to the cpuidle
-+ * framework with the valid set of states.
-+ */
-+int __init omap4_idle_init(void)
-+{
-+	struct omap4_idle_statedata *cx;
-+	struct cpuidle_device *dev;
-+	struct cpuidle_driver *drv = &omap4_idle_driver;
-+	unsigned int cpu_id = 0;
-+
-+	mpu_pd = pwrdm_lookup("mpu_pwrdm");
-+	cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
-+	cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
-+	if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
-+		return -ENODEV;
-+
-+
-+	drv->safe_state_index = -1;
-+	dev = &per_cpu(omap4_idle_dev, cpu_id);
-+	dev->cpu = cpu_id;
-+
-+	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
-+	_fill_cstate(drv, 0, "MPUSS ON");
-+	drv->safe_state_index = 0;
-+	cx = _fill_cstate_usage(dev, 0);
-+	cx->valid = 1;	/* C1 is always valid */
-+	cx->cpu_state = PWRDM_POWER_ON;
-+	cx->mpu_state = PWRDM_POWER_ON;
-+	cx->mpu_logic_state = PWRDM_POWER_RET;
-+
-+	/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
-+	_fill_cstate(drv, 1, "MPUSS CSWR");
-+	cx = _fill_cstate_usage(dev, 1);
-+	cx->cpu_state = PWRDM_POWER_OFF;
-+	cx->mpu_state = PWRDM_POWER_RET;
-+	cx->mpu_logic_state = PWRDM_POWER_RET;
-+
-+	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
-+	_fill_cstate(drv, 2, "MPUSS OSWR");
-+	cx = _fill_cstate_usage(dev, 2);
-+	cx->cpu_state = PWRDM_POWER_OFF;
-+	cx->mpu_state = PWRDM_POWER_RET;
-+	cx->mpu_logic_state = PWRDM_POWER_OFF;
-+
-+	drv->state_count = OMAP4_NUM_STATES;
-+	cpuidle_register_driver(&omap4_idle_driver);
-+
-+	dev->state_count = OMAP4_NUM_STATES;
-+	if (cpuidle_register_device(dev)) {
-+		pr_err("%s: CPUidle register device failed\n", __func__);
-+			return -EIO;
-+		}
-+
-+	return 0;
-+}
-+#else
-+int __init omap4_idle_init(void)
-+{
-+	return 0;
-+}
-+#endif /* CONFIG_CPU_IDLE */
-diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
-index c15cfad..9e029da 100644
---- a/arch/arm/mach-omap2/devices.c
-+++ b/arch/arm/mach-omap2/devices.c
-@@ -17,13 +17,28 @@
- #include <linux/err.h>
- #include <linux/slab.h>
- #include <linux/of.h>
-+#include <linux/davinci_emac.h>
-+#include <linux/cpsw.h>
-+#include <linux/etherdevice.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/can/platform/d_can.h>
-+#include <linux/platform_data/uio_pruss.h>
-+#include <linux/pwm/pwm.h>
-+#include <linux/input/ti_tscadc.h>
- 
- #include <mach/hardware.h>
- #include <mach/irqs.h>
-+#include <mach/board-am335xevm.h>
- #include <asm/mach-types.h>
- #include <asm/mach/map.h>
- #include <asm/pmu.h>
- 
-+#ifdef	CONFIG_OMAP3_EDMA
-+#include <mach/edma.h>
-+#endif
-+
-+#include <asm/hardware/asp.h>
-+
- #include <plat/tc.h>
- #include <plat/board.h>
- #include <plat/mcbsp.h>
-@@ -32,6 +47,12 @@
- #include <plat/omap_hwmod.h>
- #include <plat/omap_device.h>
- #include <plat/omap4-keypad.h>
-+#include <plat/config_pwm.h>
-+#include <plat/cpu.h>
-+#include <plat/gpmc.h>
-+
-+/* LCD controller similar DA8xx */
-+#include <video/da8xx-fb.h>
- 
- #include "mux.h"
- #include "control.h"
-@@ -51,7 +72,7 @@ static int __init omap3_l3_init(void)
- 	 * To avoid code running on other OMAPs in
- 	 * multi-omap builds
- 	 */
--	if (!(cpu_is_omap34xx()))
-+	if (!(cpu_is_omap34xx()) || (cpu_is_am33xx()))
- 		return -ENODEV;
- 
- 	l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
-@@ -127,6 +148,99 @@ static struct platform_device omap2cam_device = {
- };
- #endif
- 
-+int __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
-+{
-+	int id = 0;
-+	struct platform_device *pdev;
-+	struct omap_hwmod *oh;
-+	char *oh_name = "lcdc";
-+	char *dev_name = "da8xx_lcdc";
-+
-+	oh = omap_hwmod_lookup(oh_name);
-+	if (!oh) {
-+		pr_err("Could not look up LCD%d hwmod\n", id);
-+		return -ENODEV;
-+	}
-+
-+	pdev = omap_device_build(dev_name, id, oh, pdata,
-+			sizeof(struct da8xx_lcdc_platform_data), NULL, 0, 0);
-+	if (IS_ERR(pdev)) {
-+		WARN(1, "Can't build omap_device for %s:%s.\n",
-+			dev_name, oh->name);
-+		return PTR_ERR(pdev);
-+	}
-+	return 0;
-+}
-+
-+int __init am33xx_register_tsc(struct tsc_data *pdata)
-+{
-+	int id = -1;
-+	struct platform_device *pdev;
-+	struct omap_hwmod *oh;
-+	char *oh_name = "adc_tsc";
-+	char *dev_name = "tsc";
-+
-+	oh = omap_hwmod_lookup(oh_name);
-+	if (!oh) {
-+		pr_err("Could not look up TSC%d hwmod\n", id);
-+		return -ENODEV;
-+	}
-+
-+	pdev = omap_device_build(dev_name, id, oh, pdata,
-+			sizeof(struct tsc_data), NULL, 0, 0);
-+
-+	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
-+			dev_name, oh->name);
-+	return 0;
-+}
-+
-+#if defined(CONFIG_SND_AM335X_SOC_EVM) || \
-+				defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
-+int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr)
-+{
-+	int l;
-+	struct omap_hwmod *oh;
-+	struct platform_device *pdev;
-+	char oh_name[12];
-+	char *dev_name = "davinci-mcasp";
-+
-+	l = snprintf(oh_name, 12, "mcasp%d", ctrl_nr);
-+
-+	oh = omap_hwmod_lookup(oh_name);
-+	if (!oh) {
-+		pr_err("could not look up %s\n", oh_name);
-+		return -ENODEV;
-+	}
-+
-+	pdev = omap_device_build(dev_name, ctrl_nr, oh, pdata,
-+			sizeof(struct snd_platform_data), NULL, 0, 0);
-+	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
-+			dev_name, oh->name);
-+	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
-+}
-+
-+#else
-+int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr)
-+{
-+	return 0;
-+}
-+#endif
-+
-+#if (defined(CONFIG_SND_AM33XX_SOC) || (defined(CONFIG_SND_AM33XX_SOC_MODULE)))
-+struct platform_device am33xx_pcm_device = {
-+	.name		= "davinci-pcm-audio",
-+	.id		= -1,
-+};
-+
-+static void am33xx_init_pcm(void)
-+{
-+	platform_device_register(&am33xx_pcm_device);
-+}
-+
-+#else
-+static inline void am33xx_init_pcm(void) {}
-+#endif
-+
- static struct resource omap3isp_resources[] = {
- 	{
- 		.start		= OMAP3430_ISP_BASE,
-@@ -299,6 +413,9 @@ OMAP_MCBSP_PLATFORM_DEVICE(5);
- 
- static void omap_init_audio(void)
- {
-+	if (cpu_is_am33xx())
-+		return;
-+
- 	platform_device_register(&omap_mcbsp1);
- 	platform_device_register(&omap_mcbsp2);
- 	if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
-@@ -336,6 +453,27 @@ static void omap_init_mcpdm(void)
- static inline void omap_init_mcpdm(void) {}
- #endif
- 
-+#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
-+		defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
-+
-+static void omap_init_dmic(void)
-+{
-+	struct omap_hwmod *oh;
-+	struct platform_device *pdev;
-+
-+	oh = omap_hwmod_lookup("dmic");
-+	if (!oh) {
-+		printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
-+		return;
-+	}
-+
-+	pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
-+	WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
-+}
-+#else
-+static inline void omap_init_dmic(void) {}
-+#endif
-+
- #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
- 
- #include <plat/mcspi.h>
-@@ -386,6 +524,92 @@ static void omap_init_mcspi(void)
- static inline void omap_init_mcspi(void) {}
- #endif
- 
-+int __init omap_init_elm(void)
-+{
-+	int id = -1;
-+	struct platform_device *pdev;
-+	struct omap_hwmod *oh;
-+	char *oh_name = "elm";
-+	char *name = "omap2_elm";
-+
-+	oh = omap_hwmod_lookup(oh_name);
-+	if (!oh) {
-+		pr_err("Could not look up %s\n", oh_name);
-+		return -ENODEV;
-+	}
-+
-+	pdev = omap_device_build(name, id, oh, NULL, 0, NULL, 0, 0);
-+
-+	if (IS_ERR(pdev)) {
-+		WARN(1, "Can't build omap_device for %s:%s.\n",
-+						name, oh->name);
-+		return PTR_ERR(pdev);
-+	}
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_SOC_OMAPAM33XX
-+#define PWM_STR_LEN 10
-+int __init am33xx_register_ecap(int id, struct pwmss_platform_data *pdata)
-+{
-+	struct platform_device *pdev;
-+	struct omap_hwmod *oh;
-+	char *oh_name = "ecap";
-+	char dev_name[PWM_STR_LEN];
-+
-+	sprintf(dev_name, "ecap.%d", id);
-+
-+	oh = omap_hwmod_lookup(dev_name);
-+	if (!oh) {
-+		pr_err("Could not look up %s hwmod\n", dev_name);
-+		return -ENODEV;
-+	}
-+
-+	pdev = omap_device_build(oh_name, id, oh, pdata,
-+			sizeof(*pdata), NULL, 0, 0);
-+
-+	if (IS_ERR(pdev)) {
-+		WARN(1, "Can't build omap_device for %s:%s.\n",
-+			dev_name, oh->name);
-+		return PTR_ERR(pdev);
-+	}
-+	return 0;
-+}
-+
-+int __init am33xx_register_ehrpwm(int id, struct pwmss_platform_data *pdata)
-+{
-+	struct platform_device *pdev;
-+	struct omap_hwmod *oh;
-+	char *oh_name = "ehrpwm";
-+	char dev_name[PWM_STR_LEN];
-+
-+	sprintf(dev_name, "ehrpwm.%d", id);
-+
-+	oh = omap_hwmod_lookup(dev_name);
-+	if (!oh) {
-+		pr_err("Could not look up %s hwmod\n", dev_name);
-+		return -ENODEV;
-+	}
-+
-+	pdev = omap_device_build(oh_name, id, oh, pdata,
-+			sizeof(*pdata), NULL, 0, 0);
-+
-+	if (IS_ERR(pdev)) {
-+		WARN(1, "Can't build omap_device for %s:%s.\n",
-+			dev_name, oh->name);
-+		return PTR_ERR(pdev);
-+	}
-+	return 0;
-+}
-+
-+#else
-+static int __init am335x_register_ehrpwm(int id,
-+		struct pwmss_platform_data *pdata) { }
-+static int __init am335x_register_ecap(int id,
-+		struct pwmss_platform_data *pdata) { }
-+#endif
-+
- static struct resource omap2_pmu_resource = {
- 	.start	= 3,
- 	.end	= 3,
-@@ -408,7 +632,7 @@ static void omap_init_pmu(void)
- {
- 	if (cpu_is_omap24xx())
- 		omap_pmu_device.resource = &omap2_pmu_resource;
--	else if (cpu_is_omap34xx())
-+	else if (cpu_is_omap34xx() && !cpu_is_am33xx())
- 		omap_pmu_device.resource = &omap3_pmu_resource;
- 	else
- 		return;
-@@ -469,7 +693,7 @@ static void omap_init_sham(void)
- 	if (cpu_is_omap24xx()) {
- 		sham_device.resource = omap2_sham_resources;
- 		sham_device.num_resources = omap2_sham_resources_sz;
--	} else if (cpu_is_omap34xx()) {
-+	} else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
- 		sham_device.resource = omap3_sham_resources;
- 		sham_device.num_resources = omap3_sham_resources_sz;
- 	} else {
-@@ -538,7 +762,7 @@ static void omap_init_aes(void)
- 	if (cpu_is_omap24xx()) {
- 		aes_device.resource = omap2_aes_resources;
- 		aes_device.num_resources = omap2_aes_resources_sz;
--	} else if (cpu_is_omap34xx()) {
-+	} else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
- 		aes_device.resource = omap3_aes_resources;
- 		aes_device.num_resources = omap3_aes_resources_sz;
- 	} else {
-@@ -671,6 +895,268 @@ static void omap_init_vout(void)
- static inline void omap_init_vout(void) {}
- #endif
- 
-+#if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
-+
-+#define AM33XX_SCM_BASE_EDMA		0x00000f90
-+
-+static const s16 am33xx_dma_rsv_chans[][2] = {
-+	/* (offset, number) */
-+	{0, 2},
-+	{14, 2},
-+	{26, 6},
-+	{48, 4},
-+	{56, 8},
-+	{-1, -1}
-+};
-+
-+static const s16 am33xx_dma_rsv_slots[][2] = {
-+	/* (offset, number) */
-+	{0, 2},
-+	{14, 2},
-+	{26, 6},
-+	{48, 4},
-+	{56, 8},
-+	{64, 127},
-+	{-1, -1}
-+};
-+
-+/* Three Transfer Controllers on AM33XX */
-+static const s8 am33xx_queue_tc_mapping[][2] = {
-+	/* {event queue no, TC no} */
-+	{0, 0},
-+	{1, 1},
-+	{2, 2},
-+	{-1, -1}
-+};
-+
-+static const s8 am33xx_queue_priority_mapping[][2] = {
-+	/* {event queue no, Priority} */
-+	{0, 0},
-+	{1, 1},
-+	{2, 2},
-+	{-1, -1}
-+};
-+
-+static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
-+	/* {xbar event no, Channel} */
-+	{1, 12},	/* SDTXEVT1 -> MMCHS2 */
-+	{2, 13},	/* SDRXEVT1 -> MMCHS2 */
-+	{3, -1},
-+	{4, -1},
-+	{5, -1},
-+	{6, -1},
-+	{7, -1},
-+	{8, -1},
-+	{9, -1},
-+	{10, -1},
-+	{11, -1},
-+	{12, -1},
-+	{13, -1},
-+	{14, -1},
-+	{15, -1},
-+	{16, -1},
-+	{17, -1},
-+	{18, -1},
-+	{19, -1},
-+	{20, -1},
-+	{21, -1},
-+	{22, -1},
-+	{23, -1},
-+	{24, -1},
-+	{25, -1},
-+	{26, -1},
-+	{27, -1},
-+	{28, -1},
-+	{29, -1},
-+	{30, -1},
-+	{31, -1},
-+	{-1, -1}
-+};
-+
-+/**
-+ * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
-+ * according to the configuration provided
-+ * @event: the event number for which mapping is required
-+ * @channel: channel being activated
-+ * @xbar_event_mapping: array that has the event to channel map
-+ *
-+ * Events that are routed by default are not mapped. Only events that
-+ * are crossbar mapped are routed to available channels according to
-+ * the configuration provided
-+ *
-+ * Returns zero on success, else negative errno.
-+ */
-+int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
-+			struct event_to_channel_map *xbar_event_mapping)
-+{
-+	unsigned int ctrl = 0;
-+	unsigned int xbar_evt_no = 0;
-+	unsigned int val = 0;
-+	unsigned int offset = 0;
-+	unsigned int mask = 0;
-+
-+	ctrl = EDMA_CTLR(event);
-+	xbar_evt_no = event - (edma_cc[ctrl]->num_channels);
-+
-+	if (event < edma_cc[ctrl]->num_channels) {
-+		*channel = event;
-+	} else if (event < edma_cc[ctrl]->num_events) {
-+		*channel = xbar_event_mapping[xbar_evt_no].channel_no;
-+		/* confirm the range */
-+		if (*channel < EDMA_MAX_DMACH)
-+			clear_bit(*channel, edma_cc[ctrl]->edma_unused);
-+		mask = (*channel)%4;
-+		offset = (*channel)/4;
-+		offset *= 4;
-+		offset += mask;
-+		val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
-+					AM33XX_SCM_BASE_EDMA + offset));
-+		val = val & (~(0xFF));
-+		val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
-+		__raw_writel(val,
-+			AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
-+		return 0;
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static struct edma_soc_info am33xx_edma_info[] = {
-+	{
-+		.n_channel		= 64,
-+		.n_region		= 4,
-+		.n_slot			= 256,
-+		.n_tc			= 3,
-+		.n_cc			= 1,
-+		.rsv_chans		= am33xx_dma_rsv_chans,
-+		.rsv_slots		= am33xx_dma_rsv_slots,
-+		.queue_tc_mapping	= am33xx_queue_tc_mapping,
-+		.queue_priority_mapping	= am33xx_queue_priority_mapping,
-+		.is_xbar		= 1,
-+		.n_events		= 95,
-+		.xbar_event_mapping	= am33xx_xbar_event_mapping,
-+		.map_xbar_channel	= map_xbar_event_to_channel,
-+	},
-+};
-+
-+static int __init am33xx_register_edma(void)
-+{
-+	int i, l;
-+	struct omap_hwmod *oh[4];
-+	struct platform_device *pdev;
-+	struct edma_soc_info *pdata = am33xx_edma_info;
-+	char oh_name[8];
-+
-+	if (!cpu_is_am33xx())
-+		return -ENODEV;
-+
-+	oh[0] = omap_hwmod_lookup("tpcc");
-+	if (!oh[0]) {
-+		pr_err("could not look up %s\n", "tpcc");
-+		return -ENODEV;
-+	}
-+
-+	for (i = 0; i < 3; i++) {
-+		l = snprintf(oh_name, 8, "tptc%d", i);
-+
-+		oh[i+1] = omap_hwmod_lookup(oh_name);
-+		if (!oh[i+1]) {
-+			pr_err("could not look up %s\n", oh_name);
-+			return -ENODEV;
-+		}
-+	}
-+
-+	pdev = omap_device_build_ss("edma", 0, oh, 4, pdata, sizeof(*pdata),
-+								NULL, 0, 0);
-+
-+	WARN(IS_ERR(pdev), "could not build omap_device for edma\n");
-+
-+	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
-+
-+}
-+
-+#else
-+static inline void am33xx_register_edma(void) {}
-+#endif
-+
-+#if defined (CONFIG_SOC_OMAPAM33XX)
-+struct uio_pruss_pdata am335x_pruss_uio_pdata = {
-+	.pintc_base	= 0x20000,
-+};
-+
-+static struct resource am335x_pruss_resources[] = {
-+	{
-+		.start	= AM33XX_ICSS_BASE,
-+		.end	= AM33XX_ICSS_BASE + AM33XX_ICSS_LEN,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_ICSS0_0,
-+		.end	= AM33XX_IRQ_ICSS0_0,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_ICSS0_1,
-+		.end	= AM33XX_IRQ_ICSS0_1,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_ICSS0_2,
-+		.end	= AM33XX_IRQ_ICSS0_2,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_ICSS0_3,
-+		.end	= AM33XX_IRQ_ICSS0_3,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_ICSS0_4,
-+		.end	= AM33XX_IRQ_ICSS0_4,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_ICSS0_5,
-+		.end	= AM33XX_IRQ_ICSS0_5,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_ICSS0_6,
-+		.end	= AM33XX_IRQ_ICSS0_6,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_ICSS0_7,
-+		.end	= AM33XX_IRQ_ICSS0_7,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+};
-+
-+static struct platform_device am335x_pruss_uio_dev = {
-+	.name		= "pruss_uio",
-+	.id		= -1,
-+	.num_resources	= ARRAY_SIZE(am335x_pruss_resources),
-+	.resource	= am335x_pruss_resources,
-+	.dev	 =	{
-+		.coherent_dma_mask = 0xffffffff,
-+	}
-+};
-+
-+int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config)
-+{
-+	am335x_pruss_uio_dev.dev.platform_data = config;
-+	return platform_device_register(&am335x_pruss_uio_dev);
-+}
-+
-+static struct platform_device am335x_sgx = {
-+	.name	= "sgx",
-+	.id	= -1,
-+};
-+
-+#endif
-+
- /*-------------------------------------------------------------------------*/
- 
- static int __init omap2_init_devices(void)
-@@ -681,6 +1167,7 @@ static int __init omap2_init_devices(void)
- 	 */
- 	omap_init_audio();
- 	omap_init_mcpdm();
-+	omap_init_dmic();
- 	omap_init_camera();
- 	omap_init_mbox();
- 	omap_init_mcspi();
-@@ -690,11 +1177,276 @@ static int __init omap2_init_devices(void)
- 	omap_init_sham();
- 	omap_init_aes();
- 	omap_init_vout();
--
-+	am33xx_register_edma();
-+	am33xx_init_pcm();
-+#if defined (CONFIG_SOC_OMAPAM33XX)
-+	am335x_register_pruss_uio(&am335x_pruss_uio_pdata);
-+	if (omap3_has_sgx())
-+		platform_device_register(&am335x_sgx);
-+#endif
- 	return 0;
- }
- arch_initcall(omap2_init_devices);
- 
-+#define AM33XX_EMAC_MDIO_FREQ		(1000000)
-+
-+static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
-+/* TODO : Verify the offsets */
-+static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
-+	{
-+		.slave_reg_ofs  = 0x208,
-+		.sliver_reg_ofs = 0xd80,
-+		.phy_id		= "0:00",
-+	},
-+	{
-+		.slave_reg_ofs  = 0x308,
-+		.sliver_reg_ofs = 0xdc0,
-+		.phy_id		= "0:01",
-+	},
-+};
-+
-+static struct cpsw_platform_data am33xx_cpsw_pdata = {
-+	.ss_reg_ofs		= 0x1200,
-+	.channels		= 8,
-+	.cpdma_reg_ofs		= 0x800,
-+	.slaves			= 2,
-+	.slave_data		= am33xx_cpsw_slaves,
-+	.ale_reg_ofs		= 0xd00,
-+	.ale_entries		= 1024,
-+	.host_port_reg_ofs      = 0x108,
-+	.hw_stats_reg_ofs       = 0x900,
-+	.bd_ram_ofs		= 0x2000,
-+	.bd_ram_size		= SZ_8K,
-+	.rx_descs               = 64,
-+	.mac_control            = BIT(5), /* MIIEN */
-+	.gigabit_en		= 1,
-+	.host_port_num		= 0,
-+	.no_bd_ram		= false,
-+	.version		= CPSW_VERSION_2,
-+};
-+
-+static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
-+	.bus_freq       = AM33XX_EMAC_MDIO_FREQ,
-+};
-+
-+static struct resource am33xx_cpsw_mdioresources[] = {
-+	{
-+		.start  = AM33XX_CPSW_MDIO_BASE,
-+		.end    = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
-+		.flags  = IORESOURCE_MEM,
-+	},
-+};
-+
-+static struct platform_device am33xx_cpsw_mdiodevice = {
-+	.name           = "davinci_mdio",
-+	.id             = 0,
-+	.num_resources  = ARRAY_SIZE(am33xx_cpsw_mdioresources),
-+	.resource       = am33xx_cpsw_mdioresources,
-+	.dev.platform_data = &am33xx_cpsw_mdiopdata,
-+};
-+
-+static struct resource am33xx_cpsw_resources[] = {
-+	{
-+		.start  = AM33XX_CPSW_BASE,
-+		.end    = AM33XX_CPSW_BASE + SZ_2K - 1,
-+		.flags  = IORESOURCE_MEM,
-+	},
-+	{
-+		.start  = AM33XX_CPSW_SS_BASE,
-+		.end    = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
-+		.flags  = IORESOURCE_MEM,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_CPSW_C0_RX,
-+		.end	= AM33XX_IRQ_CPSW_C0_RX,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_DMTIMER5,
-+		.end	= AM33XX_IRQ_DMTIMER5,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_DMTIMER6,
-+		.end	= AM33XX_IRQ_DMTIMER6,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= AM33XX_IRQ_CPSW_C0,
-+		.end	= AM33XX_IRQ_CPSW_C0,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+};
-+
-+static struct platform_device am33xx_cpsw_device = {
-+	.name		=	"cpsw",
-+	.id		=	0,
-+	.num_resources	=	ARRAY_SIZE(am33xx_cpsw_resources),
-+	.resource	=	am33xx_cpsw_resources,
-+	.dev		=	{
-+					.platform_data	= &am33xx_cpsw_pdata,
-+					.dma_mask	= &am33xx_cpsw_dmamask,
-+					.coherent_dma_mask = DMA_BIT_MASK(32),
-+				},
-+};
-+
-+static unsigned char  am33xx_macid0[ETH_ALEN];
-+static unsigned char  am33xx_macid1[ETH_ALEN];
-+static unsigned int   am33xx_evmid;
-+
-+/*
-+* am33xx_evmid_fillup - set up board evmid
-+* @evmid - evm id which needs to be configured
-+*
-+* This function is called to configure board evm id.
-+* IA Motor Control EVM needs special setting of MAC PHY Id.
-+* This function is called when IA Motor Control EVM is detected
-+* during boot-up.
-+*/
-+void am33xx_evmid_fillup(unsigned int evmid)
-+{
-+	am33xx_evmid = evmid;
-+	return;
-+}
-+
-+/*
-+* am33xx_cpsw_macidfillup - setup mac adrresses
-+* @eeprommacid0 - mac id 0 which needs to be configured
-+* @eeprommacid1 - mac id 1 which needs to be configured
-+*
-+* This function is called to configure mac addresses.
-+* Mac addresses are read from eeprom and this function is called
-+* to store those mac adresses in am33xx_macid0 and am33xx_macid1.
-+* In case, mac address read from eFuse are invalid, mac addresses
-+* stored in these variable are used.
-+*/
-+void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
-+{
-+	u32 i;
-+
-+	/* Fillup these mac addresses with the mac adresses from eeprom */
-+	for (i = 0; i < ETH_ALEN; i++) {
-+		am33xx_macid0[i] = eeprommacid0[i];
-+		am33xx_macid1[i] = eeprommacid1[i];
-+	}
-+
-+	return;
-+}
-+
-+#define MII_MODE_ENABLE		0x0
-+#define RMII_MODE_ENABLE	0x5
-+#define RGMII_MODE_ENABLE	0xA
-+#define MAC_MII_SEL		0x650
-+
-+void am33xx_cpsw_init(unsigned int gigen)
-+{
-+	u32 mac_lo, mac_hi;
-+	u32 i;
-+
-+	mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
-+	mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
-+	am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
-+	am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-+	am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-+	am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-+	am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
-+	am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-+
-+	/* Read MACID0 from eeprom if eFuse MACID is invalid */
-+	if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
-+		for (i = 0; i < ETH_ALEN; i++)
-+			am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
-+	}
-+
-+	mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
-+	mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
-+	am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
-+	am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-+	am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-+	am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-+	am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
-+	am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-+
-+	/* Read MACID1 from eeprom if eFuse MACID is invalid */
-+	if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
-+		for (i = 0; i < ETH_ALEN; i++)
-+			am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
-+	}
-+
-+	if (am33xx_evmid == BEAGLE_BONE_OLD) {
-+		__raw_writel(RMII_MODE_ENABLE,
-+				AM33XX_CTRL_REGADDR(MAC_MII_SEL));
-+	} else if (am33xx_evmid == BEAGLE_BONE_A3) {
-+		__raw_writel(MII_MODE_ENABLE,
-+				AM33XX_CTRL_REGADDR(MAC_MII_SEL));
-+	} else if (am33xx_evmid == IND_AUT_MTR_EVM) {
-+		am33xx_cpsw_slaves[0].phy_id = "0:1e";
-+		am33xx_cpsw_slaves[1].phy_id = "0:00";
-+	} else {
-+		__raw_writel(RGMII_MODE_ENABLE,
-+				AM33XX_CTRL_REGADDR(MAC_MII_SEL));
-+	}
-+
-+	am33xx_cpsw_pdata.gigabit_en = gigen;
-+
-+	memcpy(am33xx_cpsw_pdata.mac_addr,
-+			am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
-+	platform_device_register(&am33xx_cpsw_mdiodevice);
-+	platform_device_register(&am33xx_cpsw_device);
-+	clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
-+			NULL, &am33xx_cpsw_device.dev);
-+}
-+
-+#define AM33XX_DCAN_NUM_MSG_OBJS		64
-+#define AM33XX_DCAN_RAMINIT_OFFSET		0x644
-+#define AM33XX_DCAN_RAMINIT_START(n)		(0x1 << n)
-+
-+static void d_can_hw_raminit(unsigned int instance, unsigned int enable)
-+{
-+	u32 val;
-+
-+	/* Read the value */
-+	val = readl(AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
-+	if (enable) {
-+		/* Set to "1" */
-+		val &= ~AM33XX_DCAN_RAMINIT_START(instance);
-+		val |= AM33XX_DCAN_RAMINIT_START(instance);
-+		writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
-+	} else {
-+		/* Set to "0" */
-+		val &= ~AM33XX_DCAN_RAMINIT_START(instance);
-+		writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
-+	}
-+}
-+
-+/* dcan dev_attr */
-+static struct d_can_platform_data am33xx_dcan_info = {
-+	.num_of_msg_objs	= AM33XX_DCAN_NUM_MSG_OBJS,
-+	.ram_init		= d_can_hw_raminit,
-+	.dma_support		= false,
-+};
-+
-+void am33xx_d_can_init(unsigned int instance)
-+{
-+	struct omap_hwmod *oh;
-+	struct platform_device *pdev;
-+	char oh_name[L3_MODULES_MAX_LEN];
-+
-+	/* Copy string name to oh_name buffer */
-+	snprintf(oh_name, L3_MODULES_MAX_LEN, "d_can%d", instance);
-+
-+	oh = omap_hwmod_lookup(oh_name);
-+	if (!oh) {
-+		pr_err("could not find %s hwmod data\n", oh_name);
-+		return;
-+	}
-+
-+	pdev = omap_device_build("d_can", instance, oh, &am33xx_dcan_info,
-+			sizeof(am33xx_dcan_info), NULL, 0, 0);
-+	if (IS_ERR(pdev))
-+		pr_err("could not build omap_device for %s\n", oh_name);
-+}
-+
- #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
- static int __init omap_init_wdt(void)
- {
-@@ -720,3 +1472,27 @@ static int __init omap_init_wdt(void)
- }
- subsys_initcall(omap_init_wdt);
- #endif
-+
-+int __init omap_init_gpmc(struct gpmc_devices_info *pdata, int pdata_len)
-+{
-+	struct omap_hwmod *oh;
-+	struct platform_device *pdev;
-+	char *name = "omap-gpmc";
-+	char *oh_name = "gpmc";
-+
-+	oh = omap_hwmod_lookup(oh_name);
-+	if (!oh) {
-+		pr_err("Could not look up %s\n", oh_name);
-+		return -ENODEV;
-+	}
-+
-+	pdev = omap_device_build(name, -1, oh, pdata,
-+					pdata_len, NULL, 0, 0);
-+	if (IS_ERR(pdev)) {
-+		WARN(1, "Can't build omap_device for %s:%s.\n",
-+						name, oh->name);
-+		return PTR_ERR(pdev);
-+	}
-+
-+	return 0;
-+}
-diff --git a/arch/arm/mach-omap2/devices.h b/arch/arm/mach-omap2/devices.h
-index f61eb6e..4725325 100644
---- a/arch/arm/mach-omap2/devices.h
-+++ b/arch/arm/mach-omap2/devices.h
-@@ -16,4 +16,12 @@ struct isp_platform_data;
- 
- int omap3_init_camera(struct isp_platform_data *pdata);
- 
-+int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr);
-+extern int __init am33xx_register_tsc(struct tsc_data *pdata);
-+extern int __init am33xx_register_ecap(int id,
-+		struct pwmss_platform_data *pdata);
-+extern int __init am33xx_register_ehrpwm(int id,
-+		struct pwmss_platform_data *pdata);
-+extern int __init omap_init_elm(void);
-+
- #endif
-diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
-index dce9905..bc6cf86 100644
---- a/arch/arm/mach-omap2/display.c
-+++ b/arch/arm/mach-omap2/display.c
-@@ -22,12 +22,13 @@
- #include <linux/io.h>
- #include <linux/clk.h>
- #include <linux/err.h>
-+#include <linux/delay.h>
- 
- #include <video/omapdss.h>
- #include <plat/omap_hwmod.h>
- #include <plat/omap_device.h>
- #include <plat/omap-pm.h>
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "control.h"
- #include "display.h"
-diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
-index fc56745..bf0db5d 100644
---- a/arch/arm/mach-omap2/dpll3xxx.c
-+++ b/arch/arm/mach-omap2/dpll3xxx.c
-@@ -142,7 +142,8 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
- 
- 	ai = omap3_dpll_autoidle_read(clk);
- 
--	omap3_dpll_deny_idle(clk);
-+	if (ai)
-+		omap3_dpll_deny_idle(clk);
- 
- 	_omap3_dpll_write_clken(clk, DPLL_LOCKED);
- 
-@@ -186,8 +187,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
- 
- 	if (ai)
- 		omap3_dpll_allow_idle(clk);
--	else
--		omap3_dpll_deny_idle(clk);
- 
- 	return r;
- }
-@@ -216,8 +215,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
- 
- 	if (ai)
- 		omap3_dpll_allow_idle(clk);
--	else
--		omap3_dpll_deny_idle(clk);
- 
- 	return 0;
- }
-@@ -301,10 +298,10 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
- 	_omap3_noncore_dpll_bypass(clk);
- 
- 	/*
--	 * Set jitter correction. No jitter correction for OMAP4 and 3630
--	 * since freqsel field is no longer present
-+	 * Set jitter correction. No jitter correction for OMAP4, 3630
-+	 * and AM33XX since freqsel field is no longer present
- 	 */
--	if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
-+	if (!cpu_is_omap44xx() && !cpu_is_omap3630() && !cpu_is_am33xx()) {
- 		v = __raw_readl(dd->control_reg);
- 		v &= ~dd->freqsel_mask;
- 		v |= freqsel << __ffs(dd->freqsel_mask);
-@@ -463,8 +460,9 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
- 		if (dd->last_rounded_rate == 0)
- 			return -EINVAL;
- 
--		/* No freqsel on OMAP4 and OMAP3630 */
--		if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
-+		/* No freqsel on OMAP4, OMAP3630 and AM33XX */
-+		if (!cpu_is_omap44xx() && !cpu_is_omap3630() &&
-+			!cpu_is_am33xx()) {
- 			freqsel = _omap3_dpll_compute_freqsel(clk,
- 						dd->last_rounded_n);
- 			if (!freqsel)
-@@ -519,6 +517,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
- 
- 	dd = clk->dpll_data;
- 
-+	if (!dd->autoidle_reg)
-+		return -EINVAL;
-+
- 	v = __raw_readl(dd->autoidle_reg);
- 	v &= dd->autoidle_mask;
- 	v >>= __ffs(dd->autoidle_mask);
-@@ -545,6 +546,12 @@ void omap3_dpll_allow_idle(struct clk *clk)
- 
- 	dd = clk->dpll_data;
- 
-+	if (!dd->autoidle_reg) {
-+		pr_debug("clock: DPLL %s: autoidle not supported\n",
-+			clk->name);
-+		return;
-+	}
-+
- 	/*
- 	 * REVISIT: CORE DPLL can optionally enter low-power bypass
- 	 * by writing 0x5 instead of 0x1.  Add some mechanism to
-@@ -554,6 +561,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
- 	v &= ~dd->autoidle_mask;
- 	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
- 	__raw_writel(v, dd->autoidle_reg);
-+
- }
- 
- /**
-@@ -572,6 +580,12 @@ void omap3_dpll_deny_idle(struct clk *clk)
- 
- 	dd = clk->dpll_data;
- 
-+	if (!dd->autoidle_reg) {
-+		pr_debug("clock: DPLL %s: autoidle not supported\n",
-+			clk->name);
-+		return;
-+	}
-+
- 	v = __raw_readl(dd->autoidle_reg);
- 	v &= ~dd->autoidle_mask;
- 	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
-diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
-index 8ad210b..0207a66 100644
---- a/arch/arm/mach-omap2/gpmc-nand.c
-+++ b/arch/arm/mach-omap2/gpmc-nand.c
-@@ -81,12 +81,37 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data
- 	return 0;
- }
- 
--int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
-+int __devinit gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
- {
- 	int err	= 0;
-+	u8 cs = 0;
- 	struct device *dev = &gpmc_nand_device.dev;
- 
-+	/* if cs not provided, find out the chip-select on which NAND exist */
-+	if (gpmc_nand_data->cs > GPMC_CS_NUM)
-+		while (cs < GPMC_CS_NUM) {
-+			u32 ret = 0;
-+			ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-+
-+			if ((ret & 0xC00) == 0x800) {
-+				printk(KERN_INFO "Found NAND on CS%d\n", cs);
-+				gpmc_nand_data->cs = cs;
-+				break;
-+			}
-+			cs++;
-+		}
-+
-+	if (gpmc_nand_data->cs > GPMC_CS_NUM) {
-+		printk(KERN_INFO "NAND: Unable to find configuration "
-+				 "in GPMC\n ");
-+		return -ENODEV;
-+	}
-+
- 	gpmc_nand_device.dev.platform_data = gpmc_nand_data;
-+	gpmc_nand_data->ctrlr_suspend	= gpmc_suspend;
-+	gpmc_nand_data->ctrlr_resume	= gpmc_resume;
-+
-+	printk(KERN_INFO "Registering NAND on CS%d\n", gpmc_nand_data->cs);
- 
- 	err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
- 				&gpmc_nand_data->phys_base);
-diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
-index dfffbbf..9a276f8 100644
---- a/arch/arm/mach-omap2/gpmc.c
-+++ b/arch/arm/mach-omap2/gpmc.c
-@@ -14,6 +14,8 @@
-  */
- #undef DEBUG
- 
-+#include <linux/platform_device.h>
-+
- #include <linux/irq.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
-@@ -24,9 +26,11 @@
- #include <linux/io.h>
- #include <linux/module.h>
- #include <linux/interrupt.h>
-+#include <linux/pm_runtime.h>
- 
- #include <asm/mach-types.h>
- #include <plat/gpmc.h>
-+#include <plat/nand.h>
- 
- #include <plat/sdrc.h>
- 
-@@ -49,6 +53,7 @@
- #define GPMC_ECC_CONTROL	0x1f8
- #define GPMC_ECC_SIZE_CONFIG	0x1fc
- #define GPMC_ECC1_RESULT        0x200
-+#define GPMC_ECC_BCH_RESULT_0	0x240
- 
- #define GPMC_CS0_OFFSET		0x60
- #define GPMC_CS_SIZE		0x30
-@@ -91,58 +96,99 @@ struct omap3_gpmc_regs {
- 	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
- };
- 
--static struct resource	gpmc_mem_root;
--static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
--static DEFINE_SPINLOCK(gpmc_mem_lock);
--static unsigned int gpmc_cs_map;	/* flag for cs which are initialized */
--static int gpmc_ecc_used = -EINVAL;	/* cs using ecc engine */
- 
--static void __iomem *gpmc_base;
-+#define	DRIVER_NAME	"omap-gpmc"
- 
--static struct clk *gpmc_l3_clk;
-+struct gpmc {
-+	struct device	*dev;
-+	void __iomem	*io_base;
-+	unsigned long	phys_base;
-+	u32		memsize;
-+	unsigned int	cs_map;
-+	int		ecc_used;
-+	spinlock_t	mem_lock;
-+	struct resource	mem_root;
-+	struct resource	cs_mem[GPMC_CS_NUM];
-+};
- 
--static irqreturn_t gpmc_handle_irq(int irq, void *dev);
-+static struct gpmc *gpmc;
- 
- static void gpmc_write_reg(int idx, u32 val)
- {
--	__raw_writel(val, gpmc_base + idx);
-+	writel(val, gpmc->io_base + idx);
- }
- 
- static u32 gpmc_read_reg(int idx)
- {
--	return __raw_readl(gpmc_base + idx);
-+	return readl(gpmc->io_base + idx);
- }
- 
- static void gpmc_cs_write_byte(int cs, int idx, u8 val)
- {
- 	void __iomem *reg_addr;
- 
--	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
--	__raw_writeb(val, reg_addr);
-+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-+	writeb(val, reg_addr);
- }
- 
- static u8 gpmc_cs_read_byte(int cs, int idx)
- {
- 	void __iomem *reg_addr;
- 
--	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
--	return __raw_readb(reg_addr);
-+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-+	return readb(reg_addr);
- }
- 
- void gpmc_cs_write_reg(int cs, int idx, u32 val)
- {
- 	void __iomem *reg_addr;
- 
--	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
--	__raw_writel(val, reg_addr);
-+	if (!gpmc) {
-+		pr_err("%s invoked without initializing GPMC\n", __func__);
-+		return;
-+	}
-+
-+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-+	writel(val, reg_addr);
- }
- 
- u32 gpmc_cs_read_reg(int cs, int idx)
- {
- 	void __iomem *reg_addr;
- 
--	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
--	return __raw_readl(reg_addr);
-+	if (!gpmc) {
-+		pr_err("%s invoked without initializing GPMC\n", __func__);
-+		return 0;
-+	}
-+
-+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-+	return readl(reg_addr);
-+}
-+
-+static struct clk *gpmc_l3_clk;
-+
-+static void __devinit gpmc_clk_init(struct device *dev)
-+{
-+	char *ck = NULL;
-+
-+	if (cpu_is_omap24xx())
-+		ck = "core_l3_ck";
-+	else if (cpu_is_omap34xx())
-+		ck = "gpmc_fck";
-+	else if (cpu_is_omap44xx())
-+		ck = "gpmc_ck";
-+
-+	if (WARN_ON(!ck))
-+		return;
-+
-+	gpmc_l3_clk = clk_get(NULL, ck);
-+	if (IS_ERR(gpmc_l3_clk)) {
-+		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
-+		BUG();
-+	}
-+
-+	pm_runtime_enable(dev);
-+	pm_runtime_get_sync(dev);
- }
- 
- /* TODO: Add support for gpmc_fck to clock framework and use it */
-@@ -341,6 +387,11 @@ static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
- 	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
- 	mask = (l >> 8) & 0x0f;
- 	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
-+
-+	if (cpu_is_am33xx()) {
-+		*base = 0x8000000;
-+		*size = 0x10000000;
-+	}
- }
- 
- static int gpmc_cs_mem_enabled(int cs)
-@@ -356,8 +407,8 @@ int gpmc_cs_set_reserved(int cs, int reserved)
- 	if (cs > GPMC_CS_NUM)
- 		return -ENODEV;
- 
--	gpmc_cs_map &= ~(1 << cs);
--	gpmc_cs_map |= (reserved ? 1 : 0) << cs;
-+	gpmc->cs_map &= ~(1 << cs);
-+	gpmc->cs_map |= (reserved ? 1 : 0) << cs;
- 
- 	return 0;
- }
-@@ -367,7 +418,7 @@ int gpmc_cs_reserved(int cs)
- 	if (cs > GPMC_CS_NUM)
- 		return -ENODEV;
- 
--	return gpmc_cs_map & (1 << cs);
-+	return gpmc->cs_map & (1 << cs);
- }
- 
- static unsigned long gpmc_mem_align(unsigned long size)
-@@ -386,22 +437,22 @@ static unsigned long gpmc_mem_align(unsigned long size)
- 
- static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
- {
--	struct resource	*res = &gpmc_cs_mem[cs];
-+	struct resource	*res = &gpmc->cs_mem[cs];
- 	int r;
- 
- 	size = gpmc_mem_align(size);
--	spin_lock(&gpmc_mem_lock);
-+	spin_lock(&gpmc->mem_lock);
- 	res->start = base;
- 	res->end = base + size - 1;
--	r = request_resource(&gpmc_mem_root, res);
--	spin_unlock(&gpmc_mem_lock);
-+	r = request_resource(&gpmc->mem_root, res);
-+	spin_unlock(&gpmc->mem_lock);
- 
- 	return r;
- }
- 
- int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
- {
--	struct resource *res = &gpmc_cs_mem[cs];
-+	struct resource *res = &gpmc->cs_mem[cs];
- 	int r = -1;
- 
- 	if (cs > GPMC_CS_NUM)
-@@ -411,7 +462,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
- 	if (size > (1 << GPMC_SECTION_SHIFT))
- 		return -ENOMEM;
- 
--	spin_lock(&gpmc_mem_lock);
-+	spin_lock(&gpmc->mem_lock);
- 	if (gpmc_cs_reserved(cs)) {
- 		r = -EBUSY;
- 		goto out;
-@@ -419,7 +470,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
- 	if (gpmc_cs_mem_enabled(cs))
- 		r = adjust_resource(res, res->start & ~(size - 1), size);
- 	if (r < 0)
--		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
-+		r = allocate_resource(&gpmc->mem_root, res, size, 0, ~0,
- 				      size, NULL, NULL);
- 	if (r < 0)
- 		goto out;
-@@ -428,24 +479,24 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
- 	*base = res->start;
- 	gpmc_cs_set_reserved(cs, 1);
- out:
--	spin_unlock(&gpmc_mem_lock);
-+	spin_unlock(&gpmc->mem_lock);
- 	return r;
- }
- EXPORT_SYMBOL(gpmc_cs_request);
- 
- void gpmc_cs_free(int cs)
- {
--	spin_lock(&gpmc_mem_lock);
-+	spin_lock(&gpmc->mem_lock);
- 	if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
- 		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
- 		BUG();
--		spin_unlock(&gpmc_mem_lock);
-+		spin_unlock(&gpmc->mem_lock);
- 		return;
- 	}
- 	gpmc_cs_disable_mem(cs);
--	release_resource(&gpmc_cs_mem[cs]);
-+	release_resource(&gpmc->cs_mem[cs]);
- 	gpmc_cs_set_reserved(cs, 0);
--	spin_unlock(&gpmc_mem_lock);
-+	spin_unlock(&gpmc->mem_lock);
- }
- EXPORT_SYMBOL(gpmc_cs_free);
- 
-@@ -668,7 +719,7 @@ int gpmc_prefetch_reset(int cs)
- }
- EXPORT_SYMBOL(gpmc_prefetch_reset);
- 
--static void __init gpmc_mem_init(void)
-+static void __devinit gpmc_mem_init(void)
- {
- 	int cs;
- 	unsigned long boot_rom_space = 0;
-@@ -680,8 +731,8 @@ static void __init gpmc_mem_init(void)
- 	/* In apollon the CS0 is mapped as 0x0000 0000 */
- 	if (machine_is_omap_apollon())
- 		boot_rom_space = 0;
--	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
--	gpmc_mem_root.end = GPMC_MEM_END;
-+	gpmc->mem_root.start = GPMC_MEM_START + boot_rom_space;
-+	gpmc->mem_root.end = GPMC_MEM_END;
- 
- 	/* Reserve all regions that has been set up by bootloader */
- 	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-@@ -695,85 +746,107 @@ static void __init gpmc_mem_init(void)
- 	}
- }
- 
--static int __init gpmc_init(void)
-+struct device *gpmc_dev;
-+
-+static int __devinit gpmc_probe(struct platform_device *pdev)
- {
--	u32 l, irq;
--	int cs, ret = -EINVAL;
--	int gpmc_irq;
--	char *ck = NULL;
-+	u32 l;
-+	int ret = -EINVAL;
-+	struct resource *res = NULL;
-+	struct gpmc_devices_info *gpmc_device = pdev->dev.platform_data;
-+	void *p;
- 
--	if (cpu_is_omap24xx()) {
--		ck = "core_l3_ck";
--		if (cpu_is_omap2420())
--			l = OMAP2420_GPMC_BASE;
--		else
--			l = OMAP34XX_GPMC_BASE;
--		gpmc_irq = INT_34XX_GPMC_IRQ;
--	} else if (cpu_is_omap34xx()) {
--		ck = "gpmc_fck";
--		l = OMAP34XX_GPMC_BASE;
--		gpmc_irq = INT_34XX_GPMC_IRQ;
--	} else if (cpu_is_omap44xx()) {
--		ck = "gpmc_ck";
--		l = OMAP44XX_GPMC_BASE;
--		gpmc_irq = OMAP44XX_IRQ_GPMC;
--	}
-+	/* XXX: This should go away with HWMOD & runtime PM adaptation */
-+	gpmc_clk_init(&pdev->dev);
- 
--	if (WARN_ON(!ck))
--		return ret;
-+	gpmc_dev = &pdev->dev;
- 
--	gpmc_l3_clk = clk_get(NULL, ck);
--	if (IS_ERR(gpmc_l3_clk)) {
--		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
--		BUG();
-+	gpmc = devm_kzalloc(&pdev->dev, sizeof(struct gpmc), GFP_KERNEL);
-+	if (!gpmc)
-+		return -ENOMEM;
-+
-+	gpmc->dev = &pdev->dev;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res) {
-+		ret = -ENOENT;
-+		dev_err(gpmc->dev, "Failed to get resource: memory\n");
-+		goto err_res;
-+	}
-+	gpmc->phys_base = res->start;
-+	gpmc->memsize = resource_size(res);
-+
-+	if (request_mem_region(gpmc->phys_base,
-+		gpmc->memsize, DRIVER_NAME) == NULL) {
-+		ret = -ENOMEM;
-+		dev_err(gpmc->dev, "Failed to request memory region\n");
-+		goto err_mem;
- 	}
- 
--	gpmc_base = ioremap(l, SZ_4K);
--	if (!gpmc_base) {
--		clk_put(gpmc_l3_clk);
--		printk(KERN_ERR "Could not get GPMC register memory\n");
--		BUG();
-+	gpmc->io_base = ioremap(gpmc->phys_base, gpmc->memsize);
-+	if (!gpmc->io_base) {
-+		ret = -ENOMEM;
-+		dev_err(gpmc->dev, "Failed to ioremap memory\n");
-+		goto err_remap;
- 	}
- 
--	clk_enable(gpmc_l3_clk);
-+	gpmc->ecc_used = -EINVAL;
-+	spin_lock_init(&gpmc->mem_lock);
-+	platform_set_drvdata(pdev, gpmc);
- 
- 	l = gpmc_read_reg(GPMC_REVISION);
--	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
--	/* Set smart idle mode and automatic L3 clock gating */
--	l = gpmc_read_reg(GPMC_SYSCONFIG);
--	l &= 0x03 << 3;
--	l |= (0x02 << 3) | (1 << 0);
--	gpmc_write_reg(GPMC_SYSCONFIG, l);
-+	dev_info(gpmc->dev, "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
-+
- 	gpmc_mem_init();
- 
--	/* initalize the irq_chained */
--	irq = OMAP_GPMC_IRQ_BASE;
--	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
--		irq_set_chip_and_handler(irq, &dummy_irq_chip,
--						handle_simple_irq);
--		set_irq_flags(irq, IRQF_VALID);
--		irq++;
--	}
-+	for (p = gpmc_device->pdata; p; gpmc_device++, p = gpmc_device->pdata)
-+		if (gpmc_device->flag & GPMC_DEVICE_NAND)
-+			gpmc_nand_init((struct omap_nand_platform_data *) p);
-+	return 0;
- 
--	ret = request_irq(gpmc_irq,
--			gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
--	if (ret)
--		pr_err("gpmc: irq-%d could not claim: err %d\n",
--						gpmc_irq, ret);
-+err_remap:
-+	release_mem_region(gpmc->phys_base, gpmc->memsize);
-+err_mem:
-+err_res:
-+	devm_kfree(&pdev->dev, gpmc);
- 	return ret;
- }
--postcore_initcall(gpmc_init);
- 
--static irqreturn_t gpmc_handle_irq(int irq, void *dev)
-+static int __devexit gpmc_remove(struct platform_device *pdev)
- {
--	u8 cs;
-+	struct gpmc *gpmc = platform_get_drvdata(pdev);
-+
-+	platform_set_drvdata(pdev, NULL);
-+	iounmap(gpmc->io_base);
-+	release_mem_region(gpmc->phys_base, gpmc->memsize);
-+	devm_kfree(&pdev->dev, gpmc);
-+
-+	return 0;
-+}
- 
--	/* check cs to invoke the irq */
--	cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
--	if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
--		generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
-+static struct platform_driver gpmc_driver = {
-+	.probe		= gpmc_probe,
-+	.remove		= __devexit_p(gpmc_remove),
-+	.driver		= {
-+		.name	= DRIVER_NAME,
-+		.owner	= THIS_MODULE,
-+	},
-+};
-+
-+module_platform_driver(gpmc_driver);
- 
--	return IRQ_HANDLED;
-+int gpmc_suspend(void)
-+{
-+	omap3_gpmc_save_context();
-+	pm_runtime_put_sync(gpmc_dev);
-+	return 0;
-+}
-+
-+int gpmc_resume(void)
-+{
-+	pm_runtime_get_sync(gpmc_dev);
-+	omap3_gpmc_restore_context();
-+	return 0;
- }
- 
- #ifdef CONFIG_ARCH_OMAP3
-@@ -845,52 +918,74 @@ void omap3_gpmc_restore_context(void)
- 
- /**
-  * gpmc_enable_hwecc - enable hardware ecc functionality
-+ * @ecc_type: ecc type e.g. Hamming, BCH
-  * @cs: chip select number
-  * @mode: read/write mode
-  * @dev_width: device bus width(1 for x16, 0 for x8)
-  * @ecc_size: bytes for which ECC will be generated
-  */
--int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
-+int gpmc_enable_hwecc(int ecc_type, int cs, int mode,
-+			int dev_width, int ecc_size)
- {
--	unsigned int val;
--
--	/* check if ecc module is in used */
--	if (gpmc_ecc_used != -EINVAL)
--		return -EINVAL;
--
--	gpmc_ecc_used = cs;
--
--	/* clear ecc and enable bits */
--	val = ((0x00000001<<8) | 0x00000001);
--	gpmc_write_reg(GPMC_ECC_CONTROL, val);
--
--	/* program ecc and result sizes */
--	val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
--	gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
-+	unsigned int bch_mod = 0, bch_wrapmode = 0, eccsize1 = 0, eccsize0 = 0;
-+	unsigned int ecc_conf_val = 0, ecc_size_conf_val = 0;
- 
- 	switch (mode) {
- 	case GPMC_ECC_READ:
--		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
-+		if (ecc_type == OMAP_ECC_BCH4_CODE_HW) {
-+			eccsize1 = 0xD; eccsize0 = 0x48;
-+			bch_mod = 0;
-+			bch_wrapmode = 0x09;
-+		} else if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
-+			eccsize1 = 0x2; eccsize0 = 0x1A;
-+			bch_mod = 1;
-+			bch_wrapmode = 0x01;
-+		} else
-+			eccsize1 = ((ecc_size >> 1) - 1);
- 		break;
- 	case GPMC_ECC_READSYN:
--		 gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
- 		break;
- 	case GPMC_ECC_WRITE:
--		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
-+		if (ecc_type == OMAP_ECC_BCH4_CODE_HW) {
-+			eccsize1 = 0x20; eccsize0 = 0x00;
-+			bch_mod = 0;
-+			bch_wrapmode = 0x06;
-+		} else if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
-+			eccsize1 = 0x1c; eccsize0 = 0x00;
-+			bch_mod = 1;
-+			bch_wrapmode = 0x01;
-+		} else
-+			eccsize1 = ((ecc_size >> 1) - 1);
- 		break;
- 	default:
- 		printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
- 		break;
- 	}
- 
--	/* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
--	val = (dev_width << 7) | (cs << 1) | (0x1);
--	gpmc_write_reg(GPMC_ECC_CONFIG, val);
-+	/* clear ecc and enable bits */
-+	if ((ecc_type == OMAP_ECC_BCH4_CODE_HW) ||
-+		(ecc_type == OMAP_ECC_BCH8_CODE_HW)) {
-+		gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000001);
-+		ecc_size_conf_val = (eccsize1 << 22) | (eccsize0 << 12);
-+		ecc_conf_val = ((0x01 << 16) | (bch_mod << 12)
-+			| (bch_wrapmode << 8) | (dev_width << 7)
-+			| (0x00 << 4) | (cs << 1) | (0x1));
-+	} else {
-+		gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000101);
-+		ecc_size_conf_val = (eccsize1 << 22) | 0x0000000F;
-+		ecc_conf_val = (dev_width << 7) | (cs << 1) | (0x1);
-+	}
-+
-+	gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, ecc_size_conf_val);
-+	gpmc_write_reg(GPMC_ECC_CONFIG, ecc_conf_val);
-+	gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000101);
- 	return 0;
- }
-+EXPORT_SYMBOL(gpmc_enable_hwecc);
- 
- /**
-  * gpmc_calculate_ecc - generate non-inverted ecc bytes
-+ * @ecc_type: ecc type e.g. Hamming, BCH
-  * @cs: chip select number
-  * @dat: data pointer over which ecc is computed
-  * @ecc_code: ecc code buffer
-@@ -901,20 +996,51 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
-  * an erased page will produce an ECC mismatch between generated and read
-  * ECC bytes that has to be dealt with separately.
-  */
--int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
-+int gpmc_calculate_ecc(int ecc_type, int cs,
-+		const u_char *dat, u_char *ecc_code)
- {
--	unsigned int val = 0x0;
--
--	if (gpmc_ecc_used != cs)
--		return -EINVAL;
--
--	/* read ecc result */
--	val = gpmc_read_reg(GPMC_ECC1_RESULT);
--	*ecc_code++ = val;          /* P128e, ..., P1e */
--	*ecc_code++ = val >> 16;    /* P128o, ..., P1o */
--	/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
--	*ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
-+	unsigned int reg;
-+	unsigned int val1 = 0x0, val2 = 0x0;
-+	unsigned int val3 = 0x0, val4 = 0x0;
-+	int i;
- 
--	gpmc_ecc_used = -EINVAL;
-+	if ((ecc_type == OMAP_ECC_BCH4_CODE_HW) ||
-+		(ecc_type == OMAP_ECC_BCH8_CODE_HW)) {
-+		for (i = 0; i < 1; i++) {
-+			/*
-+			 * Reading HW ECC_BCH_Results
-+			 * 0x240-0x24C, 0x250-0x25C, 0x260-0x26C, 0x270-0x27C
-+			 */
-+			reg =  GPMC_ECC_BCH_RESULT_0 + (0x10 * i);
-+			val1 = gpmc_read_reg(reg);
-+			val2 = gpmc_read_reg(reg + 4);
-+			if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
-+				val3 = gpmc_read_reg(reg + 8);
-+				val4 = gpmc_read_reg(reg + 12);
-+
-+				*ecc_code++ = (val4 & 0xFF);
-+				*ecc_code++ = ((val3 >> 24) & 0xFF);
-+				*ecc_code++ = ((val3 >> 16) & 0xFF);
-+				*ecc_code++ = ((val3 >> 8) & 0xFF);
-+				*ecc_code++ = (val3 & 0xFF);
-+				*ecc_code++ = ((val2 >> 24) & 0xFF);
-+			}
-+			*ecc_code++ = ((val2 >> 16) & 0xFF);
-+			*ecc_code++ = ((val2 >> 8) & 0xFF);
-+			*ecc_code++ = (val2 & 0xFF);
-+			*ecc_code++ = ((val1 >> 24) & 0xFF);
-+			*ecc_code++ = ((val1 >> 16) & 0xFF);
-+			*ecc_code++ = ((val1 >> 8) & 0xFF);
-+			*ecc_code++ = (val1 & 0xFF);
-+		}
-+	} else {
-+		/* read ecc result */
-+		val1 = gpmc_read_reg(GPMC_ECC1_RESULT);
-+		*ecc_code++ = val1;          /* P128e, ..., P1e */
-+		*ecc_code++ = val1 >> 16;    /* P128o, ..., P1o */
-+		/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
-+		*ecc_code++ = ((val1 >> 8) & 0x0f) | ((val1 >> 20) & 0xf0);
-+	}
- 	return 0;
- }
-+EXPORT_SYMBOL(gpmc_calculate_ecc);
-diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
-index f4a1020..93fbf39 100644
---- a/arch/arm/mach-omap2/hsmmc.c
-+++ b/arch/arm/mach-omap2/hsmmc.c
-@@ -171,6 +171,17 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
- 	}
- }
- 
-+static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
-+{
-+	u32 reg;
-+
-+	if (mmc->slots[0].internal_clock) {
-+		reg = omap_ctrl_readl(control_devconf1_offset);
-+		reg |= OMAP2_MMCSDIO2ADPCLKISEL;
-+		omap_ctrl_writel(reg, control_devconf1_offset);
-+	}
-+}
-+
- static void hsmmc23_before_set_reg(struct device *dev, int slot,
- 				   int power_on, int vdd)
- {
-@@ -179,16 +190,19 @@ static void hsmmc23_before_set_reg(struct device *dev, int slot,
- 	if (mmc->slots[0].remux)
- 		mmc->slots[0].remux(dev, slot, power_on);
- 
--	if (power_on) {
--		/* Only MMC2 supports a CLKIN */
--		if (mmc->slots[0].internal_clock) {
--			u32 reg;
-+	if (power_on)
-+		hsmmc2_select_input_clk_src(mmc);
-+}
- 
--			reg = omap_ctrl_readl(control_devconf1_offset);
--			reg |= OMAP2_MMCSDIO2ADPCLKISEL;
--			omap_ctrl_writel(reg, control_devconf1_offset);
--		}
--	}
-+static int am35x_hsmmc2_set_power(struct device *dev, int slot,
-+				  int power_on, int vdd)
-+{
-+	struct omap_mmc_platform_data *mmc = dev->platform_data;
-+
-+	if (power_on)
-+		hsmmc2_select_input_clk_src(mmc);
-+
-+	return 0;
- }
- 
- static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
-@@ -200,10 +214,12 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
- static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
- 			int controller_nr)
- {
--	if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
-+	if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
-+		(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
- 		omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
- 					OMAP_PIN_INPUT_PULLUP);
--	if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
-+	if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
-+		(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
- 		omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
- 					OMAP_PIN_INPUT_PULLUP);
- 	if (cpu_is_omap34xx()) {
-@@ -288,6 +304,9 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
- 		return -ENOMEM;
- 	}
- 
-+	if (cpu_is_am33xx())
-+		mmc->version = MMC_CTRL_VERSION_2;
-+
- 	if (c->name)
- 		strncpy(hc_name, c->name, HSMMC_NAME_LEN);
- 	else
-@@ -296,6 +315,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
- 	mmc->slots[0].name = hc_name;
- 	mmc->nr_slots = 1;
- 	mmc->slots[0].caps = c->caps;
-+	mmc->slots[0].pm_caps = c->pm_caps;
- 	mmc->slots[0].internal_clock = !c->ext_clock;
- 	mmc->dma_mask = 0xffffffff;
- 	if (cpu_is_omap44xx())
-@@ -336,14 +356,21 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
- 	 *
- 	 * temporary HACK: ocr_mask instead of fixed supply
- 	 */
--	mmc->slots[0].ocr_mask = c->ocr_mask;
--
--	if (cpu_is_omap3517() || cpu_is_omap3505())
--		mmc->slots[0].set_power = nop_mmc_set_power;
-+	if (cpu_is_omap3505() || cpu_is_omap3517())
-+		mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
-+					 MMC_VDD_26_27 |
-+					 MMC_VDD_27_28 |
-+					 MMC_VDD_29_30 |
-+					 MMC_VDD_30_31 |
-+					 MMC_VDD_31_32;
- 	else
-+		mmc->slots[0].ocr_mask = c->ocr_mask;
-+
-+	if (!cpu_is_omap3517() && !cpu_is_omap3505() && !cpu_is_am33xx())
- 		mmc->slots[0].features |= HSMMC_HAS_PBIAS;
- 
--	if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
-+	if ((cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) ||
-+								cpu_is_am33xx())
- 		mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
- 
- 	switch (c->mmc) {
-@@ -363,6 +390,9 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
- 			}
- 		}
- 
-+		if (cpu_is_omap3517() || cpu_is_omap3505() || cpu_is_am33xx())
-+			mmc->slots[0].set_power = nop_mmc_set_power;
-+
- 		/* OMAP3630 HSMMC1 supports only 4-bit */
- 		if (cpu_is_omap3630() &&
- 				(c->caps & MMC_CAP_8_BIT_DATA)) {
-@@ -372,6 +402,12 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
- 		}
- 		break;
- 	case 2:
-+		if (cpu_is_omap3517() || cpu_is_omap3505())
-+			mmc->slots[0].set_power = am35x_hsmmc2_set_power;
-+
-+		if (cpu_is_am33xx())
-+			mmc->slots[0].set_power = nop_mmc_set_power;
-+
- 		if (c->ext_clock)
- 			c->transceiver = 1;
- 		if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
-@@ -421,7 +457,9 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
- 		pr_err("%s fails!\n", __func__);
- 		goto done;
- 	}
--	omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
-+
-+	if (!cpu_is_am33xx())
-+		omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
- 
- 	name = "omap_hsmmc";
- 
-diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
-index f757e78..c440973 100644
---- a/arch/arm/mach-omap2/hsmmc.h
-+++ b/arch/arm/mach-omap2/hsmmc.h
-@@ -12,6 +12,7 @@ struct omap2_hsmmc_info {
- 	u8	mmc;		/* controller 1/2/3 */
- 	u32	caps;		/* 4/8 wires and any additional host
- 				 * capabilities OR'd (ref. linux/mmc/host.h) */
-+	u32	pm_caps;	/* PM capabilities */
- 	bool	transceiver;	/* MMC-2 option */
- 	bool	ext_clock;	/* use external pin for input clock */
- 	bool	cover_only;	/* No card detect - just cover switch */
-diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
-index ace9994..a12e224 100644
---- a/arch/arm/mach-omap2/i2c.c
-+++ b/arch/arm/mach-omap2/i2c.c
-@@ -21,7 +21,7 @@
- 
- #include <plat/cpu.h>
- #include <plat/i2c.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/omap_hwmod.h>
- 
- #include "mux.h"
-diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
-index 7f47092..7b913d3 100644
---- a/arch/arm/mach-omap2/id.c
-+++ b/arch/arm/mach-omap2/id.c
-@@ -21,7 +21,7 @@
- 
- #include <asm/cputype.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/cpu.h>
- 
- #include <mach/id.h>
-@@ -29,7 +29,7 @@
- #include "control.h"
- 
- static unsigned int omap_revision;
--
-+static const char *cpu_rev;
- u32 omap_features;
- 
- unsigned int omap_rev(void)
-@@ -44,6 +44,8 @@ int omap_type(void)
- 
- 	if (cpu_is_omap24xx()) {
- 		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
-+	} else if (cpu_is_am33xx()) {
-+		val = omap_ctrl_readl(AM33XX_CONTROL_STATUS_OFF);
- 	} else if (cpu_is_omap34xx()) {
- 		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
- 	} else if (cpu_is_omap44xx()) {
-@@ -112,7 +114,7 @@ void omap_get_die_id(struct omap_die_id *odi)
- 	odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
- }
- 
--static void __init omap24xx_check_revision(void)
-+void __init omap2xxx_check_revision(void)
- {
- 	int i, j;
- 	u32 idcode, prod_id;
-@@ -166,13 +168,63 @@ static void __init omap24xx_check_revision(void)
- 	pr_info("\n");
- }
- 
-+#define OMAP3_SHOW_FEATURE(feat)		\
-+	if (omap3_has_ ##feat())		\
-+		printk(#feat" ");
-+
-+static void __init omap3_cpuinfo(void)
-+{
-+	const char *cpu_name;
-+
-+	/*
-+	 * OMAP3430 and OMAP3530 are assumed to be same.
-+	 *
-+	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
-+	 * on available features. Upon detection, update the CPU id
-+	 * and CPU class bits.
-+	 */
-+	if (cpu_is_omap3630()) {
-+		cpu_name = "OMAP3630";
-+	} else if (cpu_is_omap3517()) {
-+		/* AM35xx devices */
-+		cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
-+	} else if (cpu_is_ti816x()) {
-+		cpu_name = "TI816X";
-+	} else if (cpu_is_am335x()) {
-+		cpu_name =  "AM335X";
-+	} else if (cpu_is_ti814x()) {
-+		cpu_name = "TI814X";
-+	} else if (omap3_has_iva() && omap3_has_sgx()) {
-+		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
-+		cpu_name = "OMAP3430/3530";
-+	} else if (omap3_has_iva()) {
-+		cpu_name = "OMAP3525";
-+	} else if (omap3_has_sgx()) {
-+		cpu_name = "OMAP3515";
-+	} else {
-+		cpu_name = "OMAP3503";
-+	}
-+
-+	/* Print verbose information */
-+	pr_info("%s ES%s (", cpu_name, cpu_rev);
-+
-+	OMAP3_SHOW_FEATURE(l2cache);
-+	OMAP3_SHOW_FEATURE(iva);
-+	OMAP3_SHOW_FEATURE(sgx);
-+	OMAP3_SHOW_FEATURE(neon);
-+	OMAP3_SHOW_FEATURE(isp);
-+	OMAP3_SHOW_FEATURE(192mhz_clk);
-+
-+	printk(")\n");
-+}
-+
- #define OMAP3_CHECK_FEATURE(status,feat)				\
- 	if (((status & OMAP3_ ##feat## _MASK) 				\
- 		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
- 		omap_features |= OMAP3_HAS_ ##feat;			\
- 	}
- 
--static void __init omap3_check_features(void)
-+void __init omap3xxx_check_features(void)
- {
- 	u32 status;
- 
-@@ -199,9 +251,11 @@ static void __init omap3_check_features(void)
- 	 * TODO: Get additional info (where applicable)
- 	 *       e.g. Size of L2 cache.
- 	 */
-+
-+	omap3_cpuinfo();
- }
- 
--static void __init omap4_check_features(void)
-+void __init omap4xxx_check_features(void)
- {
- 	u32 si_type;
- 
-@@ -226,12 +280,26 @@ static void __init omap4_check_features(void)
- 	}
- }
- 
--static void __init ti816x_check_features(void)
-+void __init ti81xx_check_features(void)
- {
- 	omap_features = OMAP3_HAS_NEON;
-+	omap3_cpuinfo();
- }
- 
--static void __init omap3_check_revision(const char **cpu_rev)
-+void __init am33xx_check_features(void)
-+{
-+	u32 status;
-+
-+	omap_features = OMAP3_HAS_NEON;
-+
-+	status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
-+	if (status & AM33XX_SGX_MASK)
-+		omap_features |= OMAP3_HAS_SGX;
-+
-+	omap3_cpuinfo();
-+}
-+
-+void __init omap3xxx_check_revision(void)
- {
- 	u32 cpuid, idcode;
- 	u16 hawkeye;
-@@ -245,7 +313,7 @@ static void __init omap3_check_revision(const char **cpu_rev)
- 	cpuid = read_cpuid(CPUID_ID);
- 	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
- 		omap_revision = OMAP3430_REV_ES1_0;
--		*cpu_rev = "1.0";
-+		cpu_rev = "1.0";
- 		return;
- 	}
- 
-@@ -266,26 +334,26 @@ static void __init omap3_check_revision(const char **cpu_rev)
- 		case 0: /* Take care of early samples */
- 		case 1:
- 			omap_revision = OMAP3430_REV_ES2_0;
--			*cpu_rev = "2.0";
-+			cpu_rev = "2.0";
- 			break;
- 		case 2:
- 			omap_revision = OMAP3430_REV_ES2_1;
--			*cpu_rev = "2.1";
-+			cpu_rev = "2.1";
- 			break;
- 		case 3:
- 			omap_revision = OMAP3430_REV_ES3_0;
--			*cpu_rev = "3.0";
-+			cpu_rev = "3.0";
- 			break;
- 		case 4:
- 			omap_revision = OMAP3430_REV_ES3_1;
--			*cpu_rev = "3.1";
-+			cpu_rev = "3.1";
- 			break;
- 		case 7:
- 		/* FALLTHROUGH */
- 		default:
- 			/* Use the latest known revision as default */
- 			omap_revision = OMAP3430_REV_ES3_1_2;
--			*cpu_rev = "3.1.2";
-+			cpu_rev = "3.1.2";
- 		}
- 		break;
- 	case 0xb868:
-@@ -298,13 +366,13 @@ static void __init omap3_check_revision(const char **cpu_rev)
- 		switch (rev) {
- 		case 0:
- 			omap_revision = OMAP3517_REV_ES1_0;
--			*cpu_rev = "1.0";
-+			cpu_rev = "1.0";
- 			break;
- 		case 1:
- 		/* FALLTHROUGH */
- 		default:
- 			omap_revision = OMAP3517_REV_ES1_1;
--			*cpu_rev = "1.1";
-+			cpu_rev = "1.1";
- 		}
- 		break;
- 	case 0xb891:
-@@ -313,42 +381,66 @@ static void __init omap3_check_revision(const char **cpu_rev)
- 		switch(rev) {
- 		case 0: /* Take care of early samples */
- 			omap_revision = OMAP3630_REV_ES1_0;
--			*cpu_rev = "1.0";
-+			cpu_rev = "1.0";
- 			break;
- 		case 1:
- 			omap_revision = OMAP3630_REV_ES1_1;
--			*cpu_rev = "1.1";
-+			cpu_rev = "1.1";
- 			break;
- 		case 2:
- 		/* FALLTHROUGH */
- 		default:
- 			omap_revision = OMAP3630_REV_ES1_2;
--			*cpu_rev = "1.2";
-+			cpu_rev = "1.2";
- 		}
- 		break;
- 	case 0xb81e:
- 		switch (rev) {
- 		case 0:
- 			omap_revision = TI8168_REV_ES1_0;
--			*cpu_rev = "1.0";
-+			cpu_rev = "1.0";
- 			break;
- 		case 1:
- 		/* FALLTHROUGH */
- 		default:
- 			omap_revision = TI8168_REV_ES1_1;
--			*cpu_rev = "1.1";
-+			cpu_rev = "1.1";
-+			break;
-+		}
-+		break;
-+	case 0xb944:
-+		omap_revision = AM335X_REV_ES1_0;
-+		cpu_rev = "1.0";
-+		break;
-+	case 0xb8f2:
-+		switch (rev) {
-+		case 0:
-+		/* FALLTHROUGH */
-+		case 1:
-+			omap_revision = TI8148_REV_ES1_0;
-+			cpu_rev = "1.0";
-+			break;
-+		case 2:
-+			omap_revision = TI8148_REV_ES2_0;
-+			cpu_rev = "2.0";
-+			break;
-+		case 3:
-+		/* FALLTHROUGH */
-+		default:
-+			omap_revision = TI8148_REV_ES2_1;
-+			cpu_rev = "2.1";
- 			break;
- 		}
- 		break;
- 	default:
- 		/* Unknown default to latest silicon rev as default */
- 		omap_revision = OMAP3630_REV_ES1_2;
--		*cpu_rev = "1.2";
-+		cpu_rev = "1.2";
- 		pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
- 	}
- }
- 
--static void __init omap4_check_revision(void)
-+void __init omap4xxx_check_revision(void)
- {
- 	u32 idcode;
- 	u16 hawkeye;
-@@ -367,7 +459,7 @@ static void __init omap4_check_revision(void)
- 	 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
- 	 * Use ARM register to detect the correct ES version
- 	 */
--	if (!rev && (hawkeye != 0xb94e)) {
-+	if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
- 		idcode = read_cpuid(CPUID_ID);
- 		rev = (idcode & 0xf) - 1;
- 	}
-@@ -389,8 +481,11 @@ static void __init omap4_check_revision(void)
- 			omap_revision = OMAP4430_REV_ES2_1;
- 			break;
- 		case 4:
--		default:
- 			omap_revision = OMAP4430_REV_ES2_2;
-+			break;
-+		case 6:
-+		default:
-+			omap_revision = OMAP4430_REV_ES2_3;
- 		}
- 		break;
- 	case 0xb94e:
-@@ -401,94 +496,23 @@ static void __init omap4_check_revision(void)
- 			break;
- 		}
- 		break;
-+	case 0xb975:
-+		switch (rev) {
-+		case 0:
-+		default:
-+			omap_revision = OMAP4470_REV_ES1_0;
-+			break;
-+		}
-+		break;
- 	default:
- 		/* Unknown default to latest silicon rev as default */
--		omap_revision = OMAP4430_REV_ES2_2;
-+		omap_revision = OMAP4430_REV_ES2_3;
- 	}
- 
- 	pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
- 		((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
- }
- 
--#define OMAP3_SHOW_FEATURE(feat)		\
--	if (omap3_has_ ##feat())		\
--		printk(#feat" ");
--
--static void __init omap3_cpuinfo(const char *cpu_rev)
--{
--	const char *cpu_name;
--
--	/*
--	 * OMAP3430 and OMAP3530 are assumed to be same.
--	 *
--	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
--	 * on available features. Upon detection, update the CPU id
--	 * and CPU class bits.
--	 */
--	if (cpu_is_omap3630()) {
--		cpu_name = "OMAP3630";
--	} else if (cpu_is_omap3517()) {
--		/* AM35xx devices */
--		cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
--	} else if (cpu_is_ti816x()) {
--		cpu_name = "TI816X";
--	} else if (omap3_has_iva() && omap3_has_sgx()) {
--		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
--		cpu_name = "OMAP3430/3530";
--	} else if (omap3_has_iva()) {
--		cpu_name = "OMAP3525";
--	} else if (omap3_has_sgx()) {
--		cpu_name = "OMAP3515";
--	} else {
--		cpu_name = "OMAP3503";
--	}
--
--	/* Print verbose information */
--	pr_info("%s ES%s (", cpu_name, cpu_rev);
--
--	OMAP3_SHOW_FEATURE(l2cache);
--	OMAP3_SHOW_FEATURE(iva);
--	OMAP3_SHOW_FEATURE(sgx);
--	OMAP3_SHOW_FEATURE(neon);
--	OMAP3_SHOW_FEATURE(isp);
--	OMAP3_SHOW_FEATURE(192mhz_clk);
--
--	printk(")\n");
--}
--
--/*
-- * Try to detect the exact revision of the omap we're running on
-- */
--void __init omap2_check_revision(void)
--{
--	const char *cpu_rev;
--
--	/*
--	 * At this point we have an idea about the processor revision set
--	 * earlier with omap2_set_globals_tap().
--	 */
--	if (cpu_is_omap24xx()) {
--		omap24xx_check_revision();
--	} else if (cpu_is_omap34xx()) {
--		omap3_check_revision(&cpu_rev);
--
--		/* TI816X doesn't have feature register */
--		if (!cpu_is_ti816x())
--			omap3_check_features();
--		else
--			ti816x_check_features();
--
--		omap3_cpuinfo(cpu_rev);
--		return;
--	} else if (cpu_is_omap44xx()) {
--		omap4_check_revision();
--		omap4_check_features();
--		return;
--	} else {
--		pr_err("OMAP revision unknown, please fix!\n");
--	}
--}
--
- /*
-  * Set up things for map_io and processor detection later on. Gets called
-  * pretty much first thing from board init. For multi-omap, this gets
-diff --git a/arch/arm/mach-omap2/include/mach/barriers.h b/arch/arm/mach-omap2/include/mach/barriers.h
-new file mode 100644
-index 0000000..4fa72c7
---- /dev/null
-+++ b/arch/arm/mach-omap2/include/mach/barriers.h
-@@ -0,0 +1,31 @@
-+/*
-+ * OMAP memory barrier header.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ *  Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *  Richard Woodruff <r-woodruff2@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __MACH_BARRIERS_H
-+#define __MACH_BARRIERS_H
-+
-+extern void omap_bus_sync(void);
-+
-+#define rmb()		dsb()
-+#define wmb()		do { dsb(); outer_sync(); omap_bus_sync(); } while (0)
-+#define mb()		wmb()
-+
-+#endif	/* __MACH_BARRIERS_H */
-diff --git a/arch/arm/mach-omap2/include/mach/board-am335xevm.h b/arch/arm/mach-omap2/include/mach/board-am335xevm.h
-new file mode 100644
-index 0000000..a8fe93a
---- /dev/null
-+++ b/arch/arm/mach-omap2/include/mach/board-am335xevm.h
-@@ -0,0 +1,47 @@
-+/*
-+ * Code for supporting AM335X EVM.
-+ *
-+ * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef _BOARD_AM335X_H
-+#define _BOARD_AM335X_H
-+
-+#define BASEBOARD_I2C_ADDR	0x50
-+#define DAUG_BOARD_I2C_ADDR	0x51
-+#define LCD_BOARD_I2C_ADDR	0x52
-+
-+#define LOW_COST_EVM		0
-+#define GEN_PURP_EVM		1
-+#define IND_AUT_MTR_EVM		2
-+#define IP_PHN_EVM		3
-+#define BEAGLE_BONE_OLD		4
-+#define BEAGLE_BONE_A3		5
-+
-+/* REVIST : check posibility of PROFILE_(x) syntax usage */
-+#define PROFILE_NONE	-1	/* Few EVM doesn't have profiles */
-+#define PROFILE_0		(0x1 << 0)
-+#define PROFILE_1		(0x1 << 1)
-+#define PROFILE_2		(0x1 << 2)
-+#define PROFILE_3		(0x1 << 3)
-+#define PROFILE_4		(0x1 << 4)
-+#define PROFILE_5		(0x1 << 5)
-+#define PROFILE_6		(0x1 << 6)
-+#define PROFILE_7		(0x1 << 7)
-+#define PROFILE_ALL		0xFF
-+
-+void am33xx_evmid_fillup(unsigned int evmid);
-+void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1);
-+void am33xx_cpsw_init(unsigned int gigen);
-+void am33xx_d_can_init(unsigned int instance);
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
-index 13f98e5..b9b10e5 100644
---- a/arch/arm/mach-omap2/include/mach/debug-macro.S
-+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
-@@ -66,12 +66,16 @@ omap_uart_lsr:	.word	0
- 		beq	34f			@ configure OMAP3UART4
- 		cmp	\rp, #OMAP4UART4	@ only on 44xx
- 		beq	44f			@ configure OMAP4UART4
--		cmp	\rp, #TI816XUART1	@ ti816x UART offsets different
-+		cmp	\rp, #TI81XXUART1	@ ti81Xx UART offsets different
- 		beq	81f			@ configure UART1
--		cmp	\rp, #TI816XUART2	@ ti816x UART offsets different
-+		cmp	\rp, #TI81XXUART2	@ ti81Xx UART offsets different
- 		beq	82f			@ configure UART2
--		cmp	\rp, #TI816XUART3	@ ti816x UART offsets different
-+		cmp	\rp, #TI81XXUART3	@ ti81Xx UART offsets different
- 		beq	83f			@ configure UART3
-+		cmp	\rp, #AM33XXUART1	@ AM33XX UART offsets different
-+		beq	84f			@ configure UART1
-+		cmp	\rp, #AM33XXUART4	@ AM33XX UART offsets different
-+		beq	85f			@ configure UART1
- 		cmp	\rp, #ZOOM_UART		@ only on zoom2/3
- 		beq	95f			@ configure ZOOM_UART
- 
-@@ -94,13 +98,17 @@ omap_uart_lsr:	.word	0
- 		b	98f
- 44:		mov	\rp, #UART_OFFSET(OMAP4_UART4_BASE)
- 		b	98f
--81:		mov	\rp, #UART_OFFSET(TI816X_UART1_BASE)
-+81:		mov	\rp, #UART_OFFSET(TI81XX_UART1_BASE)
- 		b	98f
--82:		mov	\rp, #UART_OFFSET(TI816X_UART2_BASE)
-+82:		mov	\rp, #UART_OFFSET(TI81XX_UART2_BASE)
- 		b	98f
--83:		mov	\rp, #UART_OFFSET(TI816X_UART3_BASE)
-+83:		mov	\rp, #UART_OFFSET(TI81XX_UART3_BASE)
-+		b	98f
-+84:		ldr	\rp, =AM33XX_UART1_BASE
-+		and	\rp, \rp, #0x00ffffff
-+		b	97f
-+85:		ldr	\rp, =UART_OFFSET(AM33XX_UART4_BASE)
- 		b	98f
--
- 95:		ldr	\rp, =ZOOM_UART_BASE
- 		str	\rp, [\tmp, #0]		@ omap_uart_phys
- 		ldr	\rp, =ZOOM_UART_VIRT
-@@ -109,6 +117,17 @@ omap_uart_lsr:	.word	0
- 		str	\rp, [\tmp, #8]		@ omap_uart_lsr
- 		b	10b
- 
-+		/* AM33XX: Store both phys and virt address for the uart */
-+97:		add	\rp, \rp, #0x44000000	@ phys base
-+		str	\rp, [\tmp, #0]		@ omap_uart_phys
-+		sub	\rp, \rp, #0x44000000	@ phys base
-+		add	\rp, \rp, #0xf9000000	@ virt base
-+		str	\rp, [\tmp, #4]		@ omap_uart_virt
-+		mov	\rp, #(UART_LSR << OMAP_PORT_SHIFT)
-+		str	\rp, [\tmp, #8]		@ omap_uart_lsr
-+
-+		b	10b
-+
- 		/* Store both phys and virt address for the uart */
- 98:		add	\rp, \rp, #0x48000000	@ phys base
- 		str	\rp, [\tmp, #0]		@ omap_uart_phys
-diff --git a/arch/arm/mach-omap2/include/mach/edma.h b/arch/arm/mach-omap2/include/mach/edma.h
-new file mode 100644
-index 0000000..9f2a7e4
---- /dev/null
-+++ b/arch/arm/mach-omap2/include/mach/edma.h
-@@ -0,0 +1,250 @@
-+/*
-+ * TI EDMA3 definitions
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+/*
-+ * This EDMA3 programming framework exposes two basic kinds of resource:
-+ *
-+ *  Channel	Triggers transfers, usually from a hardware event but
-+ *		also manually or by "chaining" from DMA completions.
-+ *		Each channel is coupled to a Parameter RAM (PaRAM) slot.
-+ *
-+ *  Slot	Each PaRAM slot holds a DMA transfer descriptor (PaRAM
-+ *		"set"), source and destination addresses, a link to a
-+ *		next PaRAM slot (if any), options for the transfer, and
-+ *		instructions for updating those addresses.  There are
-+ *		more than twice as many slots as event channels.
-+ *
-+ * Each PaRAM set describes a sequence of transfers, either for one large
-+ * buffer or for several discontiguous smaller buffers.  An EDMA transfer
-+ * is driven only from a channel, which performs the transfers specified
-+ * in its PaRAM slot until there are no more transfers.  When that last
-+ * transfer completes, the "link" field may be used to reload the channel's
-+ * PaRAM slot with a new transfer descriptor.
-+ *
-+ * The EDMA Channel Controller (CC) maps requests from channels into physical
-+ * Transfer Controller (TC) requests when the channel triggers (by hardware
-+ * or software events, or by chaining).  The two physical DMA channels provided
-+ * by the TCs are thus shared by many logical channels.
-+ *
-+ * EDMA hardware also has a "QDMA" mechanism which is not currently
-+ * supported through this interface.  (DSP firmware uses it though.)
-+ */
-+
-+#ifndef EDMA_H_
-+#define EDMA_H_
-+
-+/* PaRAM slots are laid out like this */
-+struct edmacc_param {
-+	unsigned int opt;
-+	unsigned int src;
-+	unsigned int a_b_cnt;
-+	unsigned int dst;
-+	unsigned int src_dst_bidx;
-+	unsigned int link_bcntrld;
-+	unsigned int src_dst_cidx;
-+	unsigned int ccnt;
-+};
-+
-+/* fields in edmacc_param.opt */
-+#define SAM		BIT(0)
-+#define DAM		BIT(1)
-+#define SYNCDIM		BIT(2)
-+#define STATIC		BIT(3)
-+#define EDMA_FWID	(0x07 << 8)
-+#define TCCMODE		BIT(11)
-+#define EDMA_TCC(t)	((t) << 12)
-+#define TCINTEN		BIT(20)
-+#define ITCINTEN	BIT(21)
-+#define TCCHEN		BIT(22)
-+#define ITCCHEN		BIT(23)
-+
-+#define TRWORD (0x7<<2)
-+#define PAENTRY (0x1ff<<5)
-+
-+/*ch_status paramater of callback function possible values*/
-+#define DMA_COMPLETE 1
-+#define DMA_CC_ERROR 2
-+#define DMA_TC0_ERROR 3
-+#define DMA_TC1_ERROR 4
-+#define DMA_TC2_ERROR 5
-+#define DMA_TC3_ERROR 6
-+
-+enum address_mode {
-+	INCR = 0,
-+	FIFO = 1
-+};
-+
-+enum fifo_width {
-+	W8BIT = 0,
-+	W16BIT = 1,
-+	W32BIT = 2,
-+	W64BIT = 3,
-+	W128BIT = 4,
-+	W256BIT = 5
-+};
-+
-+enum dma_event_q {
-+	EVENTQ_0 = 0,
-+	EVENTQ_1 = 1,
-+	EVENTQ_2 = 2,
-+	EVENTQ_3 = 3,
-+	EVENTQ_DEFAULT = -1
-+};
-+
-+enum sync_dimension {
-+	ASYNC = 0,
-+	ABSYNC = 1
-+};
-+
-+#define EDMA_CTLR_CHAN(ctlr, chan)	(((ctlr) << 16) | (chan))
-+#define EDMA_CTLR(i)			((i) >> 16)
-+#define EDMA_CHAN_SLOT(i)		((i) & 0xffff)
-+
-+#define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
-+#define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
-+#define EDMA_CONT_PARAMS_ANY		 1001
-+#define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
-+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-+
-+#define EDMA_MAX_DMACH           64
-+#define EDMA_MAX_PARAMENTRY     512
-+#define EDMA_MAX_CC               2
-+#define EDMA_MAX_REGION           4
-+
-+
-+/* Mapping of crossbar event numbers to actual DMA channels*/
-+struct event_to_channel_map {
-+	unsigned        xbar_event_no;
-+	int		channel_no;
-+};
-+
-+/* actual number of DMA channels and slots on this silicon */
-+struct edma {
-+	/* how many dma resources of each type */
-+	unsigned	num_channels;
-+	unsigned	num_region;
-+	unsigned	num_slots;
-+	unsigned	num_tc;
-+	unsigned	num_cc;
-+	enum dma_event_q	default_queue;
-+
-+	/* list of channels with no even trigger; terminated by "-1" */
-+	const s8	*noevent;
-+
-+	/* The edma_inuse bit for each PaRAM slot is clear unless the
-+	 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
-+	 */
-+	DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
-+
-+	/* The edma_unused bit for each channel is clear unless
-+	 * it is not being used on this platform. It uses a bit
-+	 * of SOC-specific initialization code.
-+	 */
-+	DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
-+
-+	unsigned	irq_res_start;
-+	unsigned	irq_res_end;
-+
-+	struct dma_interrupt_data {
-+		void (*callback)(unsigned channel, unsigned short ch_status,
-+				void *data);
-+		void *data;
-+	} intr_data[EDMA_MAX_DMACH];
-+
-+	unsigned	is_xbar;
-+	unsigned	num_events;
-+	struct event_to_channel_map	*xbar_event_mapping;
-+
-+	/* suspend/resume backup parameters */
-+	struct edmacc_param *bkp_prm_set;
-+	unsigned int *bkp_ch_map;		/* 64 registers */
-+	unsigned int *bkp_que_num;		/* 8 registers */
-+	unsigned int *bkp_drae;
-+	unsigned int *bkp_draeh;
-+	unsigned int *bkp_qrae;
-+	unsigned int bkp_sh_esr;
-+	unsigned int bkp_sh_esrh;
-+	unsigned int bkp_sh_eesr;
-+	unsigned int bkp_sh_eesrh;
-+	unsigned int bkp_sh_iesr;
-+	unsigned int bkp_sh_iesrh;
-+	unsigned int bkp_que_tc_map;
-+	unsigned int bkp_que_pri;
-+};
-+
-+extern struct edma *edma_cc[EDMA_MAX_CC];
-+
-+/* alloc/free DMA channels and their dedicated parameter RAM slots */
-+int edma_alloc_channel(int channel,
-+	void (*callback)(unsigned channel, u16 ch_status, void *data),
-+	void *data, enum dma_event_q);
-+void edma_free_channel(unsigned channel);
-+
-+/* alloc/free parameter RAM slots */
-+int edma_alloc_slot(unsigned ctlr, int slot);
-+void edma_free_slot(unsigned slot);
-+
-+/* alloc/free a set of contiguous parameter RAM slots */
-+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-+int edma_free_cont_slots(unsigned slot, int count);
-+
-+/* calls that operate on part of a parameter RAM slot */
-+void edma_set_src(unsigned slot, dma_addr_t src_port,
-+				enum address_mode mode, enum fifo_width);
-+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
-+				 enum address_mode mode, enum fifo_width);
-+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
-+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-+void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
-+		u16 bcnt_rld, enum sync_dimension sync_mode);
-+void edma_link(unsigned from, unsigned to);
-+void edma_unlink(unsigned from);
-+
-+/* calls that operate on an entire parameter RAM slot */
-+void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-+void edma_read_slot(unsigned slot, struct edmacc_param *params);
-+
-+/* channel control operations */
-+int edma_start(unsigned channel);
-+void edma_stop(unsigned channel);
-+void edma_clean_channel(unsigned channel);
-+void edma_clear_event(unsigned channel);
-+void edma_pause(unsigned channel);
-+void edma_resume(unsigned channel);
-+
-+/* platform_data for EDMA driver */
-+struct edma_soc_info {
-+
-+	/* how many dma resources of each type */
-+	unsigned	n_channel;
-+	unsigned	n_region;
-+	unsigned	n_slot;
-+	unsigned	n_tc;
-+	unsigned	n_cc;
-+	enum dma_event_q	default_queue;
-+
-+	const s16	(*rsv_chans)[2];
-+	const s16	(*rsv_slots)[2];
-+	const s8	(*queue_tc_mapping)[2];
-+	const s8	(*queue_priority_mapping)[2];
-+	unsigned	is_xbar;
-+	unsigned	n_events;
-+	struct event_to_channel_map    *xbar_event_mapping;
-+	int		(*map_xbar_channel)(unsigned event, unsigned *channel,
-+				struct event_to_channel_map *xbar_event_map);
-+};
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
-index feb90a1..56964a0 100644
---- a/arch/arm/mach-omap2/include/mach/entry-macro.S
-+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
-@@ -10,146 +10,9 @@
-  * License version 2. This program is licensed "as is" without any
-  * warranty of any kind, whether express or implied.
-  */
--#include <mach/hardware.h>
--#include <mach/io.h>
--#include <mach/irqs.h>
--#include <asm/hardware/gic.h>
--
--#include <plat/omap24xx.h>
--#include <plat/omap34xx.h>
--#include <plat/omap44xx.h>
--
--#include <plat/multi.h>
--
--#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
--#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
--#define OMAP4_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
--#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
--#define	ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
- 
- 		.macro	disable_fiq
- 		.endm
- 
- 		.macro  arch_ret_to_user, tmp1, tmp2
- 		.endm
--
--/*
-- * Unoptimized irq functions for multi-omap2, 3 and 4
-- */
--
--#ifdef MULTI_OMAP2
--		/*
--		 * Configure the interrupt base on the first interrupt.
--		 * See also omap_irq_base_init for setting omap_irq_base.
--		 */
--		.macro  get_irqnr_preamble, base, tmp
--		ldr	\base, =omap_irq_base	@ irq base address
--		ldr	\base, [\base, #0]	@ irq base value
--		.endm
--
--		/* Check the pending interrupts. Note that base already set */
--		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--		tst	\base, #0x100		@ gic address?
--		bne	4401f			@ found gic
--
--		/* Handle omap2 and omap3 */
--		ldr	\irqnr, [\base, #0x98] /* IRQ pending reg 1 */
--		cmp	\irqnr, #0x0
--		bne	9998f
--		ldr	\irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
--		cmp	\irqnr, #0x0
--		bne	9998f
--		ldr	\irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
--		cmp	\irqnr, #0x0
--		bne	9998f
--
--		/*
--		 * ti816x has additional IRQ pending register. Checking this
--		 * register on omap2 & omap3 has no effect (read as 0).
--		 */
--		ldr	\irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
--		cmp	\irqnr, #0x0
--9998:
--		ldrne	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
--		and	\irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
--		b	9999f
--
--		/* Handle omap4 */
--4401:		ldr     \irqstat, [\base, #GIC_CPU_INTACK]
--		ldr     \tmp, =1021
--		bic     \irqnr, \irqstat, #0x1c00
--		cmp     \irqnr, #15
--		cmpcc   \irqnr, \irqnr
--		cmpne   \irqnr, \tmp
--		cmpcs   \irqnr, \irqnr
--9999:
--		.endm
--
--#ifdef CONFIG_SMP
--		/* We assume that irqstat (the raw value of the IRQ acknowledge
--		 * register) is preserved from the macro above.
--		 * If there is an IPI, we immediately signal end of interrupt
--		 * on the controller, since this requires the original irqstat
--		 * value which we won't easily be able to recreate later.
--		 */
--
--		.macro test_for_ipi, irqnr, irqstat, base, tmp
--		bic	\irqnr, \irqstat, #0x1c00
--		cmp	\irqnr, #16
--		it	cc
--		strcc	\irqstat, [\base, #GIC_CPU_EOI]
--		it	cs
--		cmpcs	\irqnr, \irqnr
--		.endm
--#endif	/* CONFIG_SMP */
--
--#else	/* MULTI_OMAP2 */
--
--
--/*
-- * Optimized irq functions for omap2, 3 and 4
-- */
--
--#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
--		.macro  get_irqnr_preamble, base, tmp
--#ifdef CONFIG_ARCH_OMAP2
--		ldr	\base, =OMAP2_IRQ_BASE
--#else
--		ldr	\base, =OMAP3_IRQ_BASE
--#endif
--		.endm
--
--		/* Check the pending interrupts. Note that base already set */
--		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--		ldr	\irqnr, [\base, #0x98] /* IRQ pending reg 1 */
--		cmp	\irqnr, #0x0
--		bne	9999f
--		ldr	\irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
--		cmp	\irqnr, #0x0
--		bne	9999f
--		ldr	\irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
--		cmp	\irqnr, #0x0
--#ifdef CONFIG_SOC_OMAPTI816X
--		bne	9999f
--		ldr	\irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
--		cmp	\irqnr, #0x0
--#endif
--9999:
--		ldrne	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
--		and	\irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
--
--		.endm
--#endif
--
--
--#ifdef CONFIG_ARCH_OMAP4
--#define HAVE_GET_IRQNR_PREAMBLE
--#include <asm/hardware/entry-macro-gic.S>
--
--		.macro  get_irqnr_preamble, base, tmp
--		ldr     \base, =OMAP4_IRQ_BASE
--		.endm
--
--#endif
--
--#endif	/* MULTI_OMAP2 */
-diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/include/mach/omap-secure.h
-new file mode 100644
-index 0000000..c90a435
---- /dev/null
-+++ b/arch/arm/mach-omap2/include/mach/omap-secure.h
-@@ -0,0 +1,57 @@
-+/*
-+ * omap-secure.h: OMAP Secure infrastructure header.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef OMAP_ARCH_OMAP_SECURE_H
-+#define OMAP_ARCH_OMAP_SECURE_H
-+
-+/* Monitor error code */
-+#define  API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR	0xFFFFFFFE
-+#define  API_HAL_RET_VALUE_SERVICE_UNKNWON		0xFFFFFFFF
-+
-+/* HAL API error codes */
-+#define  API_HAL_RET_VALUE_OK		0x00
-+#define  API_HAL_RET_VALUE_FAIL		0x01
-+
-+/* Secure HAL API flags */
-+#define FLAG_START_CRITICAL		0x4
-+#define FLAG_IRQFIQ_MASK		0x3
-+#define FLAG_IRQ_ENABLE			0x2
-+#define FLAG_FIQ_ENABLE			0x1
-+#define NO_FLAG				0x0
-+
-+/* Maximum Secure memory storage size */
-+#define OMAP_SECURE_RAM_STORAGE	(88 * SZ_1K)
-+
-+/* Secure low power HAL API index */
-+#define OMAP4_HAL_SAVESECURERAM_INDEX	0x1a
-+#define OMAP4_HAL_SAVEHW_INDEX		0x1b
-+#define OMAP4_HAL_SAVEALL_INDEX		0x1c
-+#define OMAP4_HAL_SAVEGIC_INDEX		0x1d
-+
-+/* Secure Monitor mode APIs */
-+#define OMAP4_MON_SCU_PWR_INDEX		0x108
-+#define OMAP4_MON_L2X0_DBG_CTRL_INDEX	0x100
-+#define OMAP4_MON_L2X0_CTRL_INDEX	0x102
-+#define OMAP4_MON_L2X0_AUXCTRL_INDEX	0x109
-+#define OMAP4_MON_L2X0_PREFETCH_INDEX	0x113
-+
-+/* Secure PPA(Primary Protected Application) APIs */
-+#define OMAP4_PPA_L2_POR_INDEX		0x23
-+#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25
-+
-+#ifndef __ASSEMBLER__
-+
-+extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
-+				u32 arg1, u32 arg2, u32 arg3, u32 arg4);
-+extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
-+extern phys_addr_t omap_secure_ram_mempool_base(void);
-+
-+#endif /* __ASSEMBLER__ */
-+#endif /* OMAP_ARCH_OMAP_SECURE_H */
-diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
-new file mode 100644
-index 0000000..d79321b
---- /dev/null
-+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
-@@ -0,0 +1,39 @@
-+/*
-+ * OMAP WakeupGen header file
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef OMAP_ARCH_WAKEUPGEN_H
-+#define OMAP_ARCH_WAKEUPGEN_H
-+
-+#define OMAP_WKG_CONTROL_0			0x00
-+#define OMAP_WKG_ENB_A_0			0x10
-+#define OMAP_WKG_ENB_B_0			0x14
-+#define OMAP_WKG_ENB_C_0			0x18
-+#define OMAP_WKG_ENB_D_0			0x1c
-+#define OMAP_WKG_ENB_SECURE_A_0			0x20
-+#define OMAP_WKG_ENB_SECURE_B_0			0x24
-+#define OMAP_WKG_ENB_SECURE_C_0			0x28
-+#define OMAP_WKG_ENB_SECURE_D_0			0x2c
-+#define OMAP_WKG_ENB_A_1			0x410
-+#define OMAP_WKG_ENB_B_1			0x414
-+#define OMAP_WKG_ENB_C_1			0x418
-+#define OMAP_WKG_ENB_D_1			0x41c
-+#define OMAP_WKG_ENB_SECURE_A_1			0x420
-+#define OMAP_WKG_ENB_SECURE_B_1			0x424
-+#define OMAP_WKG_ENB_SECURE_C_1			0x428
-+#define OMAP_WKG_ENB_SECURE_D_1			0x42c
-+#define OMAP_AUX_CORE_BOOT_0			0x800
-+#define OMAP_AUX_CORE_BOOT_1			0x804
-+#define OMAP_PTMSYNCREQ_MASK			0xc00
-+#define OMAP_PTMSYNCREQ_EN			0xc04
-+#define OMAP_TIMESTAMPCYCLELO			0xc08
-+#define OMAP_TIMESTAMPCYCLEHI			0xc0c
-+
-+extern int __init omap_wakeupgen_init(void);
-+#endif
-diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
-deleted file mode 100644
-index e4bd87619..0000000
---- a/arch/arm/mach-omap2/include/mach/omap4-common.h
-+++ /dev/null
-@@ -1,43 +0,0 @@
--/*
-- * omap4-common.h: OMAP4 specific common header file
-- *
-- * Copyright (C) 2010 Texas Instruments, Inc.
-- *
-- * Author:
-- *	Santosh Shilimkar <santosh.shilimkar@ti.com>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--#ifndef OMAP_ARCH_OMAP4_COMMON_H
--#define OMAP_ARCH_OMAP4_COMMON_H
--
--/*
-- * wfi used in low power code. Directly opcode is used instead
-- * of instruction to avoid mulit-omap build break
-- */
--#ifdef CONFIG_THUMB2_KERNEL
--#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
--#else
--#define do_wfi()			\
--		__asm__ __volatile__ (".word	0xe320f003" : : : "memory")
--#endif
--
--#ifdef CONFIG_CACHE_L2X0
--extern void __iomem *l2cache_base;
--#endif
--
--extern void __iomem *gic_dist_base_addr;
--
--extern void __init gic_init_irq(void);
--extern void omap_smc1(u32 fn, u32 arg);
--
--#ifdef CONFIG_SMP
--/* Needed for secondary core boot */
--extern void omap_secondary_startup(void);
--extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
--extern void omap_auxcoreboot_addr(u32 cpu_addr);
--extern u32 omap_read_auxcoreboot0(void);
--#endif
--#endif
-diff --git a/arch/arm/mach-omap2/include/mach/sram.h b/arch/arm/mach-omap2/include/mach/sram.h
-new file mode 100644
-index 0000000..7869e2f
---- /dev/null
-+++ b/arch/arm/mach-omap2/include/mach/sram.h
-@@ -0,0 +1,14 @@
-+/*
-+ * arch/arm/mach-omap2/include/mach/sram.h
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#ifndef __ARCH_ARM_SRAM_H
-+#define __ARCH_ARM_SRAM_H
-+
-+#include <plat/sram.h>
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
-deleted file mode 100644
-index 8663199..0000000
---- a/arch/arm/mach-omap2/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/*
-- *  arch/arm/plat-omap/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2000 Russell King.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- */
--#define VMALLOC_END	  0xf8000000UL
-diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
-index 25d20ce..729be3c 100644
---- a/arch/arm/mach-omap2/io.c
-+++ b/arch/arm/mach-omap2/io.c
-@@ -35,15 +35,17 @@
- #include "clock3xxx.h"
- #include "clock44xx.h"
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/omap-pm.h>
- #include "voltage.h"
- #include "powerdomain.h"
-+#include "prminst44xx.h"
-+#include "cminst44xx.h"
- 
- #include "clockdomain.h"
- #include <plat/omap_hwmod.h>
- #include <plat/multi.h>
--#include <plat/common.h>
-+#include "common.h"
- 
- /*
-  * The machine specific code may provide the extra mapping besides the
-@@ -176,14 +178,31 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
- };
- #endif
- 
--#ifdef CONFIG_SOC_OMAPTI816X
--static struct map_desc omapti816x_io_desc[] __initdata = {
-+#ifdef CONFIG_SOC_OMAPTI81XX
-+static struct map_desc omapti81xx_io_desc[] __initdata = {
-+	{
-+		.virtual	= L4_34XX_VIRT,
-+		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
-+		.length		= L4_34XX_SIZE,
-+		.type		= MT_DEVICE
-+	}
-+};
-+#endif
-+
-+#ifdef CONFIG_SOC_OMAPAM33XX
-+static struct map_desc omapam33xx_io_desc[] __initdata = {
- 	{
- 		.virtual	= L4_34XX_VIRT,
- 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
- 		.length		= L4_34XX_SIZE,
- 		.type		= MT_DEVICE
- 	},
-+	{
-+		.virtual	= L4_WK_AM33XX_VIRT,
-+		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
-+		.length		= L4_WK_AM33XX_SIZE,
-+		.type		= MT_DEVICE
-+	}
- };
- #endif
- 
-@@ -237,6 +256,15 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
- 		.length		= L4_EMU_44XX_SIZE,
- 		.type		= MT_DEVICE,
- 	},
-+#ifdef CONFIG_OMAP4_ERRATA_I688
-+	{
-+		.virtual	= OMAP4_SRAM_VA,
-+		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
-+		.length		= PAGE_SIZE,
-+		.type		= MT_MEMORY_SO,
-+	},
-+#endif
-+
- };
- #endif
- 
-@@ -263,10 +291,17 @@ void __init omap34xx_map_common_io(void)
- }
- #endif
- 
--#ifdef CONFIG_SOC_OMAPTI816X
--void __init omapti816x_map_common_io(void)
-+#ifdef CONFIG_SOC_OMAPTI81XX
-+void __init omapti81xx_map_common_io(void)
- {
--	iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
-+	iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
-+}
-+#endif
-+
-+#ifdef CONFIG_SOC_OMAPAM33XX
-+void __init omapam33xx_map_common_io(void)
-+{
-+	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
- }
- #endif
- 
-@@ -316,13 +351,8 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
- 	return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
- }
- 
--/* See irq.c, omap4-common.c and entry-macro.S */
--void __iomem *omap_irq_base;
--
- static void __init omap_common_init_early(void)
- {
--	omap2_check_revision();
--	omap_ioremap_init();
- 	omap_init_consistent_dma_size();
- }
- 
-@@ -363,6 +393,7 @@ static void __init omap_hwmod_init_postsetup(void)
- void __init omap2420_init_early(void)
- {
- 	omap2_set_globals_242x();
-+	omap2xxx_check_revision();
- 	omap_common_init_early();
- 	omap2xxx_voltagedomains_init();
- 	omap242x_powerdomains_init();
-@@ -375,6 +406,7 @@ void __init omap2420_init_early(void)
- void __init omap2430_init_early(void)
- {
- 	omap2_set_globals_243x();
-+	omap2xxx_check_revision();
- 	omap_common_init_early();
- 	omap2xxx_voltagedomains_init();
- 	omap243x_powerdomains_init();
-@@ -393,6 +425,8 @@ void __init omap2430_init_early(void)
- void __init omap3_init_early(void)
- {
- 	omap2_set_globals_3xxx();
-+	omap3xxx_check_revision();
-+	omap3xxx_check_features();
- 	omap_common_init_early();
- 	omap3xxx_voltagedomains_init();
- 	omap3xxx_powerdomains_init();
-@@ -422,9 +456,11 @@ void __init am35xx_init_early(void)
- 	omap3_init_early();
- }
- 
--void __init ti816x_init_early(void)
-+void __init ti81xx_init_early(void)
- {
--	omap2_set_globals_ti816x();
-+	omap2_set_globals_ti81xx();
-+	omap3xxx_check_revision();
-+	ti81xx_check_features();
- 	omap_common_init_early();
- 	omap3xxx_voltagedomains_init();
- 	omap3xxx_powerdomains_init();
-@@ -433,15 +469,35 @@ void __init ti816x_init_early(void)
- 	omap_hwmod_init_postsetup();
- 	omap3xxx_clk_init();
- }
-+
-+void __init am33xx_init_early(void)
-+{
-+	omap2_set_globals_am33xx();
-+	omap3xxx_check_revision();
-+	am33xx_check_features();
-+	omap_common_init_early();
-+	am33xx_voltagedomains_init();
-+	omap44xx_prminst_init();
-+	am33xx_powerdomains_init();
-+	omap44xx_cminst_init();
-+	am33xx_clockdomains_init();
-+	am33xx_hwmod_init();
-+	omap_hwmod_init_postsetup();
-+	omap3xxx_clk_init();
-+}
- #endif
- 
- #ifdef CONFIG_ARCH_OMAP4
- void __init omap4430_init_early(void)
- {
- 	omap2_set_globals_443x();
-+	omap4xxx_check_revision();
-+	omap4xxx_check_features();
- 	omap_common_init_early();
- 	omap44xx_voltagedomains_init();
-+	omap44xx_prminst_init();
- 	omap44xx_powerdomains_init();
-+	omap44xx_cminst_init();
- 	omap44xx_clockdomains_init();
- 	omap44xx_hwmod_init();
- 	omap_hwmod_init_postsetup();
-diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
-index 65f1be6..419b1a10 100644
---- a/arch/arm/mach-omap2/irq.c
-+++ b/arch/arm/mach-omap2/irq.c
-@@ -15,6 +15,7 @@
- #include <linux/interrupt.h>
- #include <linux/io.h>
- #include <mach/hardware.h>
-+#include <asm/exception.h>
- #include <asm/mach/irq.h>
- 
- 
-@@ -35,6 +36,11 @@
- /* Number of IRQ state bits in each MIR register */
- #define IRQ_BITS_PER_REG	32
- 
-+#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
-+#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
-+#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
-+#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
-+
- /*
-  * OMAP2 has a number of different interrupt controllers, each interrupt
-  * controller is identified as its own "bank". Register definitions are
-@@ -143,6 +149,7 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
- 
- static void __init omap_init_irq(u32 base, int nr_irqs)
- {
-+	void __iomem *omap_irq_base;
- 	unsigned long nr_of_irqs = 0;
- 	unsigned int nr_banks = 0;
- 	int i, j;
-@@ -186,11 +193,49 @@ void __init omap3_init_irq(void)
- 	omap_init_irq(OMAP34XX_IC_BASE, 96);
- }
- 
--void __init ti816x_init_irq(void)
-+void __init ti81xx_init_irq(void)
- {
- 	omap_init_irq(OMAP34XX_IC_BASE, 128);
- }
- 
-+static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
-+{
-+	u32 irqnr;
-+
-+	do {
-+		irqnr = readl_relaxed(base_addr + 0x98);
-+		if (irqnr)
-+			goto out;
-+
-+		irqnr = readl_relaxed(base_addr + 0xb8);
-+		if (irqnr)
-+			goto out;
-+
-+		irqnr = readl_relaxed(base_addr + 0xd8);
-+#if defined(CONFIG_SOC_OMAPTI816X) || defined(CONFIG_SOC_OMAPAM33XX)
-+		if (irqnr)
-+			goto out;
-+		irqnr = readl_relaxed(base_addr + 0xf8);
-+#endif
-+
-+out:
-+		if (!irqnr)
-+			break;
-+
-+		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
-+		irqnr &= ACTIVEIRQ_MASK;
-+
-+		if (irqnr)
-+			handle_IRQ(irqnr, regs);
-+	} while (irqnr);
-+}
-+
-+asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
-+{
-+	void __iomem *base_addr = OMAP2_IRQ_BASE;
-+	omap_intc_handle_irq(base_addr, regs);
-+}
-+
- #ifdef CONFIG_ARCH_OMAP3
- static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
- 
-@@ -263,4 +308,10 @@ void omap3_intc_resume_idle(void)
- 	/* Re-enable autoidle */
- 	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
- }
-+
-+asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
-+{
-+	void __iomem *base_addr = OMAP3_IRQ_BASE;
-+	omap_intc_handle_irq(base_addr, regs);
-+}
- #endif /* CONFIG_ARCH_OMAP3 */
-diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
-index 609ea2d..c822126 100644
---- a/arch/arm/mach-omap2/mailbox.c
-+++ b/arch/arm/mach-omap2/mailbox.c
-@@ -20,25 +20,29 @@
- #include <mach/irqs.h>
- 
- #define MAILBOX_REVISION		0x000
--#define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
--#define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
--#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 4 * (m))
--#define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
--#define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
-+#define MAILBOX_MESSAGE(m)		(0x040 + 0x4 * (m))
-+#define MAILBOX_FIFOSTATUS(m)		(0x080 + 0x4 * (m))
-+#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 0x4 * (m))
-+#define MAILBOX_IRQSTATUS(u)		(0x100 + 0x8 * (u))
-+#define MAILBOX_IRQENABLE(u)		(0x104 + 0x8 * (u))
- 
--#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
--#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
--#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))
-+#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
-+#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
-+#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
- 
- #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
- #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))
- 
-+/* TODO: This can and should be based on #users and #sub-modules */
- #define MBOX_REG_SIZE			0x120
- 
- #define OMAP4_MBOX_REG_SIZE		0x130
- 
-+#define AM33XX_MBOX_REG_SIZE		0x140
-+
- #define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))
- #define OMAP4_MBOX_NR_REGS		(OMAP4_MBOX_REG_SIZE / sizeof(u32))
-+#define AM33XX_MBOX_NR_REGS		(AM33XX_MBOX_REG_SIZE / sizeof(u32))
- 
- static void __iomem *mbox_base;
- 
-@@ -123,6 +127,20 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
- 	return mbox_read_reg(fifo->fifo_stat);
- }
- 
-+static int omap2_mbox_fifo_needs_flush(struct omap_mbox *mbox)
-+{
-+	struct omap_mbox2_fifo *fifo =
-+		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
-+	return (mbox_read_reg(fifo->msg_stat) == 0);
-+}
-+
-+static mbox_msg_t omap2_mbox_fifo_readback(struct omap_mbox *mbox)
-+{
-+	struct omap_mbox2_fifo *fifo =
-+		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
-+	return (mbox_msg_t) mbox_read_reg(fifo->msg);
-+}
-+
- /* Mailbox IRQ handle functions */
- static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
- 		omap_mbox_type_t irq)
-@@ -141,7 +159,7 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
- 	struct omap_mbox2_priv *p = mbox->priv;
- 	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
- 
--	if (!cpu_is_omap44xx())
-+	if (!cpu_is_omap44xx() && !cpu_is_am33xx())
- 		bit = mbox_read_reg(p->irqdisable) & ~bit;
- 
- 	mbox_write_reg(bit, p->irqdisable);
-@@ -205,19 +223,21 @@ static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
- }
- 
- static struct omap_mbox_ops omap2_mbox_ops = {
--	.type		= OMAP_MBOX_TYPE2,
--	.startup	= omap2_mbox_startup,
--	.shutdown	= omap2_mbox_shutdown,
--	.fifo_read	= omap2_mbox_fifo_read,
--	.fifo_write	= omap2_mbox_fifo_write,
--	.fifo_empty	= omap2_mbox_fifo_empty,
--	.fifo_full	= omap2_mbox_fifo_full,
--	.enable_irq	= omap2_mbox_enable_irq,
--	.disable_irq	= omap2_mbox_disable_irq,
--	.ack_irq	= omap2_mbox_ack_irq,
--	.is_irq		= omap2_mbox_is_irq,
--	.save_ctx	= omap2_mbox_save_ctx,
--	.restore_ctx	= omap2_mbox_restore_ctx,
-+	.type			= OMAP_MBOX_TYPE2,
-+	.startup		= omap2_mbox_startup,
-+	.shutdown		= omap2_mbox_shutdown,
-+	.fifo_read		= omap2_mbox_fifo_read,
-+	.fifo_write		= omap2_mbox_fifo_write,
-+	.fifo_empty		= omap2_mbox_fifo_empty,
-+	.fifo_full		= omap2_mbox_fifo_full,
-+	.fifo_needs_flush	= omap2_mbox_fifo_needs_flush,
-+	.fifo_readback		= omap2_mbox_fifo_readback,
-+	.enable_irq		= omap2_mbox_enable_irq,
-+	.disable_irq		= omap2_mbox_disable_irq,
-+	.ack_irq		= omap2_mbox_ack_irq,
-+	.is_irq			= omap2_mbox_is_irq,
-+	.save_ctx		= omap2_mbox_save_ctx,
-+	.restore_ctx		= omap2_mbox_restore_ctx,
- };
- 
- /*
-@@ -229,7 +249,6 @@ static struct omap_mbox_ops omap2_mbox_ops = {
- 
- /* FIXME: the following structs should be filled automatically by the user id */
- 
--#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
- /* DSP */
- static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
- 	.tx_fifo = {
-@@ -252,13 +271,9 @@ struct omap_mbox mbox_dsp_info = {
- 	.ops	= &omap2_mbox_ops,
- 	.priv	= &omap2_mbox_dsp_priv,
- };
--#endif
- 
--#if defined(CONFIG_ARCH_OMAP3)
- struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
--#endif
- 
--#if defined(CONFIG_SOC_OMAP2420)
- /* IVA */
- static struct omap_mbox2_priv omap2_mbox_iva_priv = {
- 	.tx_fifo = {
-@@ -283,9 +298,34 @@ static struct omap_mbox mbox_iva_info = {
- };
- 
- struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
--#endif
- 
--#if defined(CONFIG_ARCH_OMAP4)
-+/* A8 -> Wakeup-M3 */
-+static struct omap_mbox2_priv omap2_mbox_m3_priv = {
-+	.tx_fifo = {
-+		.msg		= MAILBOX_MESSAGE(0),
-+		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
-+		.msg_stat	= MAILBOX_MSGSTATUS(0),
-+	},
-+	/* TODO: No M3->A8 so this needs to be removed */
-+	.rx_fifo = {
-+		.msg		= MAILBOX_MESSAGE(1),
-+		.msg_stat	= MAILBOX_MSGSTATUS(1),
-+	},
-+	.irqenable	= OMAP4_MAILBOX_IRQENABLE(3),
-+	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(3),
-+	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
-+	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(0),
-+	.irqdisable	= OMAP4_MAILBOX_IRQENABLE_CLR(3),
-+};
-+
-+struct omap_mbox wkup_m3_info = {
-+	.name	= "wkup_m3",
-+	.ops	= &omap2_mbox_ops,
-+	.priv	= &omap2_mbox_m3_priv,
-+};
-+
-+struct omap_mbox *am33xx_mboxes[] = { &wkup_m3_info, NULL };
-+
- /* OMAP4 */
- static struct omap_mbox2_priv omap2_mbox_1_priv = {
- 	.tx_fifo = {
-@@ -332,7 +372,6 @@ struct omap_mbox mbox_2_info = {
- };
- 
- struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
--#endif
- 
- static int __devinit omap2_mbox_probe(struct platform_device *pdev)
- {
-@@ -342,14 +381,15 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
- 
- 	if (false)
- 		;
--#if defined(CONFIG_ARCH_OMAP3)
--	else if (cpu_is_omap34xx()) {
-+	else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
- 		list = omap3_mboxes;
- 
- 		list[0]->irq = platform_get_irq(pdev, 0);
-+	} else if (cpu_is_am33xx()) {
-+		list = am33xx_mboxes;
-+
-+		list[0]->irq = platform_get_irq(pdev, 0);
- 	}
--#endif
--#if defined(CONFIG_ARCH_OMAP2)
- 	else if (cpu_is_omap2430()) {
- 		list = omap2_mboxes;
- 
-@@ -360,14 +400,11 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
- 		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
- 		list[1]->irq = platform_get_irq_byname(pdev, "iva");
- 	}
--#endif
--#if defined(CONFIG_ARCH_OMAP4)
- 	else if (cpu_is_omap44xx()) {
- 		list = omap4_mboxes;
- 
- 		list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
- 	}
--#endif
- 	else {
- 		pr_err("%s: platform not supported\n", __func__);
- 		return -ENODEV;
-@@ -412,7 +449,7 @@ static void __exit omap2_mbox_exit(void)
- 	platform_driver_unregister(&omap2_mbox_driver);
- }
- 
--module_init(omap2_mbox_init);
-+device_initcall(omap2_mbox_init);
- module_exit(omap2_mbox_exit);
- 
- MODULE_LICENSE("GPL v2");
-diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
-index 655e948..e1cc75d 100644
---- a/arch/arm/mach-omap2/mux.c
-+++ b/arch/arm/mach-omap2/mux.c
-@@ -32,6 +32,8 @@
- #include <linux/debugfs.h>
- #include <linux/seq_file.h>
- #include <linux/uaccess.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
- 
- #include <asm/system.h>
- 
-@@ -39,6 +41,7 @@
- 
- #include "control.h"
- #include "mux.h"
-+#include "prm.h"
- 
- #define OMAP_MUX_BASE_OFFSET		0x30	/* Offset from CTRL_BASE */
- #define OMAP_MUX_BASE_SZ		0x5ca
-@@ -306,7 +309,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
- 		pad->idle = bpad->idle;
- 		pad->off = bpad->off;
- 
--		if (pad->flags & OMAP_DEVICE_PAD_REMUX)
-+		if (pad->flags &
-+		    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
- 			nr_pads_dynamic++;
- 
- 		pr_debug("%s: Initialized %s\n", __func__, pad->name);
-@@ -331,7 +335,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
- 	for (i = 0; i < hmux->nr_pads; i++) {
- 		struct omap_device_pad *pad = &hmux->pads[i];
- 
--		if (pad->flags & OMAP_DEVICE_PAD_REMUX) {
-+		if (pad->flags &
-+		    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
- 			pr_debug("%s: pad %s tagged dynamic\n",
- 					__func__, pad->name);
- 			hmux->pads_dynamic[nr_pads_dynamic] = pad;
-@@ -351,6 +356,78 @@ err1:
- 	return NULL;
- }
- 
-+/**
-+ * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
-+ * @hmux: Pads for a hwmod
-+ * @mpu_irqs: MPU irq array for a hwmod
-+ *
-+ * Scans the wakeup status of pads for a single hwmod.  If an irq
-+ * array is defined for this mux, the parser will call the registered
-+ * ISRs for corresponding pads, otherwise the parser will stop at the
-+ * first wakeup active pad and return.  Returns true if there is a
-+ * pending and non-served wakeup event for the mux, otherwise false.
-+ */
-+static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
-+		struct omap_hwmod_irq_info *mpu_irqs)
-+{
-+	int i, irq;
-+	unsigned int val;
-+	u32 handled_irqs = 0;
-+
-+	for (i = 0; i < hmux->nr_pads_dynamic; i++) {
-+		struct omap_device_pad *pad = hmux->pads_dynamic[i];
-+
-+		if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
-+		    !(pad->idle & OMAP_WAKEUP_EN))
-+			continue;
-+
-+		val = omap_mux_read(pad->partition, pad->mux->reg_offset);
-+		if (!(val & OMAP_WAKEUP_EVENT))
-+			continue;
-+
-+		if (!hmux->irqs)
-+			return true;
-+
-+		irq = hmux->irqs[i];
-+		/* make sure we only handle each irq once */
-+		if (handled_irqs & 1 << irq)
-+			continue;
-+
-+		handled_irqs |= 1 << irq;
-+
-+		generic_handle_irq(mpu_irqs[irq].irq);
-+	}
-+
-+	return false;
-+}
-+
-+/**
-+ * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
-+ *
-+ * Checks a single hwmod for every wakeup capable pad to see if there is an
-+ * active wakeup event. If this is the case, call the corresponding ISR.
-+ */
-+static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
-+{
-+	if (!oh->mux || !oh->mux->enabled)
-+		return 0;
-+	if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
-+		generic_handle_irq(oh->mpu_irqs[0].irq);
-+	return 0;
-+}
-+
-+/**
-+ * omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
-+ *
-+ * Calls a function for each registered omap_hwmod to check
-+ * pad wakeup statuses.
-+ */
-+static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
-+{
-+	omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
-+	return IRQ_HANDLED;
-+}
-+
- /* Assumes the calling function takes care of locking */
- void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
- {
-@@ -715,6 +792,7 @@ static void __init omap_mux_free_names(struct omap_mux *m)
- static int __init omap_mux_late_init(void)
- {
- 	struct omap_mux_partition *partition;
-+	int ret;
- 
- 	list_for_each_entry(partition, &mux_partitions, node) {
- 		struct omap_mux_entry *e, *tmp;
-@@ -735,6 +813,13 @@ static int __init omap_mux_late_init(void)
- 		}
- 	}
- 
-+	ret = request_irq(omap_prcm_event_to_irq("io"),
-+		omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
-+			"hwmod_io", omap_mux_late_init);
-+
-+	if (ret)
-+		pr_warning("mux: Failed to setup hwmod io irq %d\n", ret);
-+
- 	omap_mux_dbg_init();
- 
- 	return 0;
-diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
-index 2132308..11671be 100644
---- a/arch/arm/mach-omap2/mux.h
-+++ b/arch/arm/mach-omap2/mux.h
-@@ -11,6 +11,7 @@
- #include "mux2430.h"
- #include "mux34xx.h"
- #include "mux44xx.h"
-+#include "mux33xx.h"
- 
- #define OMAP_MUX_TERMINATOR	0xffff
- 
-@@ -41,6 +42,28 @@
- /* 44xx specific mux bit defines */
- #define OMAP_WAKEUP_EVENT		(1 << 15)
- 
-+/* am33xx specific mux bit defines */
-+#define AM33XX_SLEWCTRL_FAST		(0 << 6)
-+#define AM33XX_SLEWCTRL_SLOW		(1 << 6)
-+#define AM33XX_INPUT_EN			(1 << 5)
-+#define AM33XX_PULL_UP			(1 << 4)
-+/* bit 3: 0 - enable, 1 - disable for pull enable */
-+#define AM33XX_PULL_DISA		(1 << 3)
-+#define AM33XX_PULL_ENBL		(0 << 3)
-+
-+/* Definition of output pin could have pull disabled, but
-+ * this has not been done due to two reasons
-+ * 1. AM33XX_MUX will take care of it
-+ * 2. If pull was disabled for out macro, combining out & in pull on macros
-+ *    would disable pull resistor and AM33XX_MUX cannot take care of the
-+ *    correct pull setting and unintentionally pull would get disabled
-+ */
-+#define	AM33XX_PIN_OUTPUT		(0)
-+#define	AM33XX_PIN_OUTPUT_PULLUP	(AM33XX_PULL_UP)
-+#define	AM33XX_PIN_INPUT		(AM33XX_INPUT_EN | AM33XX_PULL_DISA)
-+#define	AM33XX_PIN_INPUT_PULLUP		(AM33XX_INPUT_EN | AM33XX_PULL_UP)
-+#define	AM33XX_PIN_INPUT_PULLDOWN	(AM33XX_INPUT_EN)
-+
- /* Active pin states */
- #define OMAP_PIN_OUTPUT			0
- #define OMAP_PIN_INPUT			OMAP_INPUT_EN
-@@ -331,6 +354,12 @@ int omap4_mux_init(struct omap_board_mux *board_subset,
- 	struct omap_board_mux *board_wkup_subset, int flags);
- 
- /**
-+ * am33xx_mux_init() - initialize mux system along with board specific set
-+ * @board_mux:		Board specific mux table
-+ */
-+int am33xx_mux_init(struct omap_board_mux *board_mux);
-+
-+/**
-  * omap_mux_init - private mux init function, do not call
-  */
- int omap_mux_init(const char *name, u32 flags,
-diff --git a/arch/arm/mach-omap2/mux33xx.c b/arch/arm/mach-omap2/mux33xx.c
-new file mode 100644
-index 0000000..25dcedb
---- /dev/null
-+++ b/arch/arm/mach-omap2/mux33xx.c
-@@ -0,0 +1,619 @@
-+/*
-+ * AM33XX mux data
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
-+ *
-+ * Copyright (C) 2009 Nokia
-+ * Copyright (C) 2009 Texas Instruments
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+
-+#include "mux.h"
-+
-+#ifdef CONFIG_OMAP_MUX
-+
-+#define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)		\
-+{									\
-+	.reg_offset	= (AM33XX_CONTROL_PADCONF_##M0##_OFFSET),	\
-+	.gpio		= (g),						\
-+	.muxnames	= { m0, m1, m2, m3, m4, m5, m6, m7 },		\
-+}
-+
-+/* AM33XX pin mux super set */
-+static struct omap_mux __initdata am33xx_muxmodes[] = {
-+	_AM33XX_MUXENTRY(GPMC_AD0, 0,
-+		"gpmc_ad0", "mmc1_dat0", NULL, NULL,
-+		NULL, NULL, NULL, "gpio1_0"),
-+	_AM33XX_MUXENTRY(GPMC_AD1, 0,
-+		"gpmc_ad1", "mmc1_dat1", NULL, NULL,
-+		NULL, NULL, NULL, "gpio1_1"),
-+	_AM33XX_MUXENTRY(GPMC_AD2, 0,
-+		"gpmc_ad2", "mmc1_dat2", NULL, NULL,
-+		NULL, NULL, NULL, "gpio1_2"),
-+	_AM33XX_MUXENTRY(GPMC_AD3, 0,
-+		"gpmc_ad3", "mmc1_dat3", NULL, NULL,
-+		NULL, NULL, NULL, "gpio1_3"),
-+	_AM33XX_MUXENTRY(GPMC_AD4, 0,
-+		"gpmc_ad4", "mmc1_dat4", NULL, NULL,
-+		NULL, NULL, NULL, "gpio1_4"),
-+	_AM33XX_MUXENTRY(GPMC_AD5, 0,
-+		"gpmc_ad5", "mmc1_dat5", NULL, NULL,
-+		NULL, NULL, NULL, "gpio1_5"),
-+	_AM33XX_MUXENTRY(GPMC_AD6, 0,
-+		"gpmc_ad6", "mmc1_dat6", NULL, NULL,
-+		NULL, NULL, NULL, "gpio1_6"),
-+	_AM33XX_MUXENTRY(GPMC_AD7, 0,
-+		"gpmc_ad7", "mmc1_dat7", NULL, NULL,
-+		NULL, NULL, NULL, "gpio1_7"),
-+	_AM33XX_MUXENTRY(GPMC_AD8, 0,
-+		"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
-+		NULL, NULL, NULL, "gpio0_22"),
-+	_AM33XX_MUXENTRY(GPMC_AD9, 0,
-+		"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
-+		"ehrpwm2B", NULL, NULL, "gpio0_23"),
-+	_AM33XX_MUXENTRY(GPMC_AD10, 0,
-+		"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
-+		NULL, NULL, NULL, "gpio0_26"),
-+	_AM33XX_MUXENTRY(GPMC_AD11, 0,
-+		"gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
-+		NULL, NULL, NULL, "gpio0_27"),
-+	_AM33XX_MUXENTRY(GPMC_AD12, 0,
-+		"gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
-+		NULL, NULL, NULL, "gpio1_12"),
-+	_AM33XX_MUXENTRY(GPMC_AD13, 0,
-+		"gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
-+		NULL, NULL, NULL, "gpio1_13"),
-+	_AM33XX_MUXENTRY(GPMC_AD14, 0,
-+		"gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
-+		NULL, NULL, NULL, "gpio1_14"),
-+	_AM33XX_MUXENTRY(GPMC_AD15, 0,
-+		"gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
-+		NULL, NULL, NULL, "gpio1_15"),
-+	_AM33XX_MUXENTRY(GPMC_A0, 0,
-+		"gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
-+		NULL, NULL, NULL, "gpio1_16"),
-+	_AM33XX_MUXENTRY(GPMC_A1, 0,
-+		"gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
-+		NULL, NULL, NULL, "gpio1_17"),
-+	_AM33XX_MUXENTRY(GPMC_A2, 0,
-+		"gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
-+		NULL, NULL, "ehrpwm1A", "gpio1_18"),
-+	_AM33XX_MUXENTRY(GPMC_A3, 0,
-+		"gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
-+		NULL, NULL, NULL, "gpio1_19"),
-+	_AM33XX_MUXENTRY(GPMC_A4, 0,
-+		"gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
-+		"gpmc_a20", NULL, NULL, "gpio1_20"),
-+	_AM33XX_MUXENTRY(GPMC_A5, 0,
-+		"gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
-+		"gpmc_a21", NULL, NULL, "gpio1_21"),
-+	_AM33XX_MUXENTRY(GPMC_A6, 0,
-+		"gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
-+		"gpmc_a22", NULL, NULL, "gpio1_22"),
-+	_AM33XX_MUXENTRY(GPMC_A7, 0,
-+		"gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
-+		NULL, NULL, NULL, "gpio1_23"),
-+	_AM33XX_MUXENTRY(GPMC_A8, 0,
-+		"gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
-+		NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
-+	_AM33XX_MUXENTRY(GPMC_A9, 0,
-+		"gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
-+		NULL, NULL, "mcasp0_fsx", "gpio1_25"),
-+	_AM33XX_MUXENTRY(GPMC_A10, 0,
-+		"gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
-+		NULL, NULL, "mcasp0_axr0", "gpio1_26"),
-+	_AM33XX_MUXENTRY(GPMC_A11, 0,
-+		"gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
-+		NULL, NULL, "mcasp0_axr1", "gpio1_27"),
-+	_AM33XX_MUXENTRY(GPMC_WAIT0, 0,
-+		"gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
-+		"mmc1_sdcd", NULL, NULL, "gpio0_30"),
-+	_AM33XX_MUXENTRY(GPMC_WPN, 0,
-+		"gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
-+		"mmc2_sdcd", NULL, NULL, "gpio0_31"),
-+	_AM33XX_MUXENTRY(GPMC_BEN1, 0,
-+		"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
-+		NULL, NULL, "mcasp0_aclkr", "gpio1_28"),
-+	_AM33XX_MUXENTRY(GPMC_CSN0, 0,
-+		"gpmc_csn0", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio1_29"),
-+	_AM33XX_MUXENTRY(GPMC_CSN1, 0,
-+		"gpmc_csn1", NULL, "mmc1_clk", NULL,
-+		NULL, NULL, NULL, "gpio1_30"),
-+	_AM33XX_MUXENTRY(GPMC_CSN2, 0,
-+		"gpmc_csn2", NULL, "mmc1_cmd", NULL,
-+		NULL, NULL, NULL, "gpio1_31"),
-+	_AM33XX_MUXENTRY(GPMC_CSN3, 0,
-+		"gpmc_csn3", NULL, NULL, "mmc2_cmd",
-+		NULL, NULL, NULL, "gpio2_0"),
-+	_AM33XX_MUXENTRY(GPMC_CLK, 0,
-+		"gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
-+		NULL, NULL, "mcasp0_fsr", "gpio2_1"),
-+	_AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
-+		"gpmc_advn_ale", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "mmc1_sdcd"),
-+	_AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
-+		"gpmc_oen_ren", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_3"),
-+	_AM33XX_MUXENTRY(GPMC_WEN, 0,
-+		"gpmc_wen", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_4"),
-+	_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
-+		"gpmc_ben0_cle", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_5"),
-+	_AM33XX_MUXENTRY(LCD_DATA0, 0,
-+		"lcd_data0", "gpmc_a0", NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_6"),
-+	_AM33XX_MUXENTRY(LCD_DATA1, 0,
-+		"lcd_data1", "gpmc_a1", NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_7"),
-+	_AM33XX_MUXENTRY(LCD_DATA2, 0,
-+		"lcd_data2", "gpmc_a2", NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_8"),
-+	_AM33XX_MUXENTRY(LCD_DATA3, 0,
-+		"lcd_data3", "gpmc_a3", NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_9"),
-+	_AM33XX_MUXENTRY(LCD_DATA4, 0,
-+		"lcd_data4", "gpmc_a4", NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_10"),
-+	_AM33XX_MUXENTRY(LCD_DATA5, 0,
-+		"lcd_data5", "gpmc_a5", NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_11"),
-+	_AM33XX_MUXENTRY(LCD_DATA6, 0,
-+		"lcd_data6", "gpmc_a6", NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_12"),
-+	_AM33XX_MUXENTRY(LCD_DATA7, 0,
-+		"lcd_data7", "gpmc_a7", NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_13"),
-+	_AM33XX_MUXENTRY(LCD_DATA8, 0,
-+		"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
-+		NULL, NULL, "uart2_ctsn", "gpio2_14"),
-+	_AM33XX_MUXENTRY(LCD_DATA9, 0,
-+		"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
-+		NULL, NULL, "uart2_rtsn", "gpio2_15"),
-+	_AM33XX_MUXENTRY(LCD_DATA10, 0,
-+		"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
-+		NULL, NULL, NULL, "gpio2_16"),
-+	_AM33XX_MUXENTRY(LCD_DATA11, 0,
-+		"lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
-+		"mcasp0_axr2", NULL, NULL, "gpio2_17"),
-+	_AM33XX_MUXENTRY(LCD_DATA12, 0,
-+		"lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr",
-+		"mcasp0_axr2", NULL, NULL, "gpio0_8"),
-+	_AM33XX_MUXENTRY(LCD_DATA13, 0,
-+		"lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr",
-+		"mcasp0_axr3", NULL, NULL, "gpio0_9"),
-+	_AM33XX_MUXENTRY(LCD_DATA14, 0,
-+		"lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
-+		NULL, NULL, NULL, "gpio0_10"),
-+	_AM33XX_MUXENTRY(LCD_DATA15, 0,
-+		"lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
-+		"mcasp0_axr3", NULL, NULL, "gpio0_11"),
-+	_AM33XX_MUXENTRY(LCD_VSYNC, 0,
-+		"lcd_vsync", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_22"),
-+	_AM33XX_MUXENTRY(LCD_HSYNC, 0,
-+		"lcd_hsync", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_23"),
-+	_AM33XX_MUXENTRY(LCD_PCLK, 0,
-+		"lcd_pclk", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_24"),
-+	_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
-+		"lcd_ac_bias_en", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_25"),
-+	_AM33XX_MUXENTRY(MMC0_DAT3, 0,
-+		"mmc0_dat3", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_26"),
-+	_AM33XX_MUXENTRY(MMC0_DAT2, 0,
-+		"mmc0_dat2", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_27"),
-+	_AM33XX_MUXENTRY(MMC0_DAT1, 0,
-+		"mmc0_dat1", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_28"),
-+	_AM33XX_MUXENTRY(MMC0_DAT0, 0,
-+		"mmc0_dat0", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_29"),
-+	_AM33XX_MUXENTRY(MMC0_CLK, 0,
-+		"mmc0_clk", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_30"),
-+	_AM33XX_MUXENTRY(MMC0_CMD, 0,
-+		"mmc0_cmd", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio2_31"),
-+	_AM33XX_MUXENTRY(MII1_COL, 0,
-+		"mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
-+		"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
-+	_AM33XX_MUXENTRY(MII1_CRS, 0,
-+		"mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
-+		"mcasp1_aclkx", NULL, NULL, "gpio3_1"),
-+	_AM33XX_MUXENTRY(MII1_RXERR, 0,
-+		"mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
-+		"mcasp1_fsx", NULL, NULL, "gpio3_2"),
-+	_AM33XX_MUXENTRY(MII1_TXEN, 0,
-+		"mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
-+		"mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"),
-+	_AM33XX_MUXENTRY(MII1_RXDV, 0,
-+		"mii1_rxdv", NULL, "rgmii1_rctl", NULL,
-+		"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),
-+	_AM33XX_MUXENTRY(MII1_TXD3, 0,
-+		"mii1_txd3", NULL, "rgmii1_td3", NULL,
-+		"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
-+	_AM33XX_MUXENTRY(MII1_TXD2, 0,
-+		"mii1_txd2", NULL, "rgmii1_td2", NULL,
-+		"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
-+	_AM33XX_MUXENTRY(MII1_TXD1, 0,
-+		"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
-+		"mcasp1_axr1", NULL, "mmc1_cmd", "gpio0_21"),
-+	_AM33XX_MUXENTRY(MII1_TXD0, 0,
-+		"mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
-+		"mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"),
-+	_AM33XX_MUXENTRY(MII1_TXCLK, 0,
-+		"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
-+		"mmc1_dat0", NULL, "mcasp0_aclkx", "gpio3_9"),
-+	_AM33XX_MUXENTRY(MII1_RXCLK, 0,
-+		"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
-+		"mmc1_dat1", NULL, "mcasp0_fsx", "gpio3_10"),
-+	_AM33XX_MUXENTRY(MII1_RXD3, 0,
-+		"mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",
-+		"mmc1_dat2", NULL, "mcasp0_axr0", "gpio2_18"),
-+	_AM33XX_MUXENTRY(MII1_RXD2, 0,
-+		"mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",
-+		"mmc1_dat3", NULL, "mcasp0_axr1", "gpio2_19"),
-+	_AM33XX_MUXENTRY(MII1_RXD1, 0,
-+		"mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
-+		"mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"),
-+	_AM33XX_MUXENTRY(MII1_RXD0, 0,
-+		"mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
-+		"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"),
-+	_AM33XX_MUXENTRY(MII1_REFCLK, 0,
-+		"rmii1_refclk", NULL, "spi1_cs0", NULL,
-+		"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"),
-+	_AM33XX_MUXENTRY(MDIO_DATA, 0,
-+		"mdio_data", NULL, NULL, NULL,
-+		"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
-+	_AM33XX_MUXENTRY(MDIO_CLK, 0,
-+		"mdio_clk", NULL, NULL, NULL,
-+		"mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
-+	_AM33XX_MUXENTRY(SPI0_SCLK, 0,
-+		"spi0_sclk", "uart2_rxd", "i2c2_sda", NULL,
-+		NULL, NULL, NULL, "gpio0_2"),
-+	_AM33XX_MUXENTRY(SPI0_D0, 0,
-+		"spi0_d0", "uart2_txd", "i2c2_scl", NULL,
-+		NULL, NULL, NULL, "gpio0_3"),
-+	_AM33XX_MUXENTRY(SPI0_D1, 0,
-+		"spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
-+		NULL, NULL, NULL, "gpio0_4"),
-+	_AM33XX_MUXENTRY(SPI0_CS0, 0,
-+		"spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
-+		NULL, NULL, NULL, "gpio0_5"),
-+	_AM33XX_MUXENTRY(SPI0_CS1, 0,
-+		"spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
-+		NULL, "mmc0_sdcd", NULL, "gpio0_6"),
-+	_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
-+		"ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
-+		"spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
-+	_AM33XX_MUXENTRY(UART0_CTSN, 0,
-+		"uart0_ctsn", NULL, "d_can1_tx", "i2c1_sda",
-+		"spi1_d0", NULL, NULL, "gpio1_8"),
-+	_AM33XX_MUXENTRY(UART0_RTSN, 0,
-+		"uart0_rtsn", NULL, "d_can1_rx", "i2c1_scl",
-+		"spi1_d1", "spi1_cs0", NULL, "gpio1_9"),
-+	_AM33XX_MUXENTRY(UART0_RXD, 0,
-+		"uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda",
-+		NULL, NULL, NULL, "gpio1_10"),
-+	_AM33XX_MUXENTRY(UART0_TXD, 0,
-+		"uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl",
-+		NULL, NULL, NULL, "gpio1_11"),
-+	_AM33XX_MUXENTRY(UART1_CTSN, 0,
-+		"uart1_ctsn", NULL, "d_can0_tx", "i2c2_sda",
-+		"spi1_cs0", NULL, NULL, "gpio0_12"),
-+	_AM33XX_MUXENTRY(UART1_RTSN, 0,
-+		"uart1_rtsn", NULL, "d_can0_rx", "i2c2_scl",
-+		"spi1_cs1", NULL, NULL, "gpio0_13"),
-+	_AM33XX_MUXENTRY(UART1_RXD, 0,
-+		"uart1_rxd", "mmc1_sdwp", "d_can1_tx", "i2c1_sda",
-+		NULL, "pr1_uart0_rxd_mux1", NULL, "gpio0_14"),
-+	_AM33XX_MUXENTRY(UART1_TXD, 0,
-+		"uart1_txd", "mmc2_sdwp", "d_can1_rx", "i2c1_scl",
-+		NULL, "pr1_uart0_txd_mux1", NULL, "gpio0_15"),
-+	_AM33XX_MUXENTRY(I2C0_SDA, 0,
-+		"i2c0_sda", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio3_5"),
-+	_AM33XX_MUXENTRY(I2C0_SCL, 0,
-+		"i2c0_scl", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio3_6"),
-+	_AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
-+		"mcasp0_aclkx", NULL, NULL, "spi1_sclk",
-+		"mmc0_sdcd", NULL, NULL, "gpio3_14"),
-+	_AM33XX_MUXENTRY(MCASP0_FSX, 0,
-+		"mcasp0_fsx", NULL, NULL, "spi1_d0",
-+		"mmc1_sdcd", NULL, NULL, "gpio3_15"),
-+	_AM33XX_MUXENTRY(MCASP0_AXR0, 0,
-+		"mcasp0_axr0", NULL, NULL, "spi1_d1",
-+		"mmc2_sdcd", NULL, NULL, "gpio3_16"),
-+	_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
-+		"mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
-+		NULL, NULL, NULL, "gpio3_17"),
-+	_AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
-+		"mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
-+		"mmc0_sdwp", NULL, NULL, "gpio3_18"),
-+	_AM33XX_MUXENTRY(MCASP0_FSR, 0,
-+		"mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx",
-+		NULL, "pr1_pru0_pru_r30_5", NULL, "gpio3_19"),
-+	_AM33XX_MUXENTRY(MCASP0_AXR1, 0,
-+		"mcasp0_axr1", NULL, NULL, "mcasp1_axr0",
-+		NULL, NULL, NULL, "gpio3_20"),
-+	_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
-+		"mcasp0_ahclkx", NULL, "mcasp0_axr3", "mcasp1_axr1",
-+		NULL, NULL, NULL, "gpio3_21"),
-+	_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
-+		"xdma_event_intr0", NULL, NULL, NULL,
-+		"spi1_cs1", NULL, NULL, "gpio0_19"),
-+	_AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
-+		"xdma_event_intr1", NULL, NULL, "clkout2",
-+		NULL, NULL, NULL, "gpio0_20"),
-+	_AM33XX_MUXENTRY(WARMRSTN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(PWRONRSTN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(NMIN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(XTALIN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(XTALOUT, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(TMS, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(TDI, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(TDO, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(TCK, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(TRSTN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(EMU0, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio3_7"),
-+	_AM33XX_MUXENTRY(EMU1, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio3_8"),
-+	_AM33XX_MUXENTRY(RTC_XTALIN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(RTC_XTALOUT, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(EXT_WAKEUP, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
-+		"usb0_drvvbus", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio0_18"),
-+	_AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
-+		"usb1_drvvbus", NULL, NULL, NULL,
-+		NULL, NULL, NULL, "gpio3_13"),
-+	_AM33XX_MUXENTRY(DDR_RESETN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_CSN0, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_CKE, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_CK, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_CKN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_CASN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_RASN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_WEN, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_BA0, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_BA1, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_BA2, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A0, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A1, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A2, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A3, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A4, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A5, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A6, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A7, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A8, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A9, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A10, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A11, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A12, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A13, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A14, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_A15, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_ODT, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D0, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D1, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D2, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D3, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D4, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D5, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D6, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D7, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D8, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D9, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D10, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D11, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D12, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D13, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D14, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_D15, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_DQM0, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_DQM1, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_DQS0, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_DQSN0, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_DQS1, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_DQSN1, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_VREF, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(DDR_VTP, 0,
-+		NULL, NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(AIN0, 0,
-+		"ain0", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(AIN1, 0,
-+		"ain1", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(AIN2, 0,
-+		"ain2", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(AIN3, 0,
-+		"ain3", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(AIN4, 0,
-+		"ain4", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(AIN5, 0,
-+		"ain5", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(AIN6, 0,
-+		"ain6", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(AIN7, 0,
-+		"ain7", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(VREFP, 0,
-+		"vrefp", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	_AM33XX_MUXENTRY(VREFN, 0,
-+		"vrefn", NULL, NULL, NULL,
-+		NULL, NULL, NULL, NULL),
-+	{ .reg_offset = OMAP_MUX_TERMINATOR },
-+};
-+
-+int __init am33xx_mux_init(struct omap_board_mux *board_subset)
-+{
-+	return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
-+			AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
-+			NULL, board_subset, NULL);
-+}
-+#else
-+int __init am33xx_mux_init(struct omap_board_mux *board_subset)
-+{
-+	return 0;
-+}
-+#endif
-diff --git a/arch/arm/mach-omap2/mux33xx.h b/arch/arm/mach-omap2/mux33xx.h
-new file mode 100644
-index 0000000..348c8e5
---- /dev/null
-+++ b/arch/arm/mach-omap2/mux33xx.h
-@@ -0,0 +1,245 @@
-+/*
-+ * AM33XX pad control register macros.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_MUX335X_H
-+#define __ARCH_ARM_MACH_OMAP2_MUX335X_H
-+
-+#define AM33XX_CONTROL_PADCONF_MUX_PBASE			0x44E10000LU
-+
-+/* If pin is not defined as input, pull would get disabled.
-+ * If defined as input, flags supplied will determine pull on/off.
-+ */
-+#define AM33XX_MUX(mode0, mux_value)					\
-+{									\
-+	.reg_offset	= (AM33XX_CONTROL_PADCONF_##mode0##_OFFSET),	\
-+	.value		= (((mux_value) & AM33XX_INPUT_EN) ? (mux_value)\
-+				: ((mux_value) | AM33XX_PULL_DISA)),	\
-+}
-+
-+/*
-+ * AM33XX CONTROL_PADCONF* register offsets for pin-muxing
-+ *
-+ * Add AM33XX_CONTROL_PADCONF_MUX_PBASE to these values to get the
-+ * absolute addresses. The macro names below are mode-0 names of
-+ * corresponding pins.
-+ */
-+
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET			0x0800
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD1_OFFSET			0x0804
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD2_OFFSET			0x0808
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD3_OFFSET			0x080C
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD4_OFFSET			0x0810
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD5_OFFSET			0x0814
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD6_OFFSET			0x0818
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD7_OFFSET			0x081C
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD8_OFFSET			0x0820
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD9_OFFSET			0x0824
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD10_OFFSET			0x0828
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD11_OFFSET			0x082C
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD12_OFFSET			0x0830
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD13_OFFSET			0x0834
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD14_OFFSET			0x0838
-+#define AM33XX_CONTROL_PADCONF_GPMC_AD15_OFFSET			0x083C
-+#define AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET			0x0840
-+#define AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET			0x0844
-+#define AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET			0x0848
-+#define AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET			0x084C
-+#define AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET			0x0850
-+#define AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET			0x0854
-+#define AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET			0x0858
-+#define AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET			0x085C
-+#define AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET			0x0860
-+#define AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET			0x0864
-+#define AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET			0x0868
-+#define AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET			0x086C
-+#define AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET		0x0870
-+#define AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET			0x0874
-+#define AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET			0x0878
-+#define AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET			0x087C
-+#define AM33XX_CONTROL_PADCONF_GPMC_CSN1_OFFSET			0x0880
-+#define AM33XX_CONTROL_PADCONF_GPMC_CSN2_OFFSET			0x0884
-+#define AM33XX_CONTROL_PADCONF_GPMC_CSN3_OFFSET			0x0888
-+#define AM33XX_CONTROL_PADCONF_GPMC_CLK_OFFSET			0x088C
-+#define AM33XX_CONTROL_PADCONF_GPMC_ADVN_ALE_OFFSET		0x0890
-+#define AM33XX_CONTROL_PADCONF_GPMC_OEN_REN_OFFSET		0x0894
-+#define AM33XX_CONTROL_PADCONF_GPMC_WEN_OFFSET			0x0898
-+#define AM33XX_CONTROL_PADCONF_GPMC_BEN0_CLE_OFFSET		0x089C
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA0_OFFSET			0x08A0
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA1_OFFSET			0x08A4
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA2_OFFSET			0x08A8
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA3_OFFSET			0x08AC
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA4_OFFSET			0x08B0
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA5_OFFSET			0x08B4
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA6_OFFSET			0x08B8
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA7_OFFSET			0x08BC
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA8_OFFSET			0x08C0
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA9_OFFSET			0x08C4
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA10_OFFSET		0x08C8
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA11_OFFSET		0x08CC
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA12_OFFSET		0x08D0
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA13_OFFSET		0x08D4
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA14_OFFSET		0x08D8
-+#define AM33XX_CONTROL_PADCONF_LCD_DATA15_OFFSET		0x08DC
-+#define AM33XX_CONTROL_PADCONF_LCD_VSYNC_OFFSET			0x08E0
-+#define AM33XX_CONTROL_PADCONF_LCD_HSYNC_OFFSET			0x08E4
-+#define AM33XX_CONTROL_PADCONF_LCD_PCLK_OFFSET			0x08E8
-+#define AM33XX_CONTROL_PADCONF_LCD_AC_BIAS_EN_OFFSET		0x08EC
-+#define AM33XX_CONTROL_PADCONF_MMC0_DAT3_OFFSET			0x08F0
-+#define AM33XX_CONTROL_PADCONF_MMC0_DAT2_OFFSET			0x08F4
-+#define AM33XX_CONTROL_PADCONF_MMC0_DAT1_OFFSET			0x08F8
-+#define AM33XX_CONTROL_PADCONF_MMC0_DAT0_OFFSET			0x08FC
-+#define AM33XX_CONTROL_PADCONF_MMC0_CLK_OFFSET			0x0900
-+#define AM33XX_CONTROL_PADCONF_MMC0_CMD_OFFSET			0x0904
-+#define AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET			0x0908
-+#define AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET			0x090C
-+#define AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET		0x0910
-+#define AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET			0x0914
-+#define AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET			0x0918
-+#define AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET			0x091C
-+#define AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET			0x0920
-+#define AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET			0x0924
-+#define AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET			0x0928
-+#define AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET		0x092C
-+#define AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET		0x0930
-+#define AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET			0x0934
-+#define AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET			0x0938
-+#define AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET			0x093C
-+#define AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET			0x0940
-+#define AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET		0x0944
-+#define AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET			0x0948
-+#define AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET			0x094C
-+#define AM33XX_CONTROL_PADCONF_SPI0_SCLK_OFFSET			0x0950
-+#define AM33XX_CONTROL_PADCONF_SPI0_D0_OFFSET			0x0954
-+#define AM33XX_CONTROL_PADCONF_SPI0_D1_OFFSET			0x0958
-+#define AM33XX_CONTROL_PADCONF_SPI0_CS0_OFFSET			0x095C
-+#define AM33XX_CONTROL_PADCONF_SPI0_CS1_OFFSET			0x0960
-+#define AM33XX_CONTROL_PADCONF_ECAP0_IN_PWM0_OUT_OFFSET		0x0964
-+#define AM33XX_CONTROL_PADCONF_UART0_CTSN_OFFSET		0x0968
-+#define AM33XX_CONTROL_PADCONF_UART0_RTSN_OFFSET		0x096C
-+#define AM33XX_CONTROL_PADCONF_UART0_RXD_OFFSET			0x0970
-+#define AM33XX_CONTROL_PADCONF_UART0_TXD_OFFSET			0x0974
-+#define AM33XX_CONTROL_PADCONF_UART1_CTSN_OFFSET		0x0978
-+#define AM33XX_CONTROL_PADCONF_UART1_RTSN_OFFSET		0x097C
-+#define AM33XX_CONTROL_PADCONF_UART1_RXD_OFFSET			0x0980
-+#define AM33XX_CONTROL_PADCONF_UART1_TXD_OFFSET			0x0984
-+#define AM33XX_CONTROL_PADCONF_I2C0_SDA_OFFSET			0x0988
-+#define AM33XX_CONTROL_PADCONF_I2C0_SCL_OFFSET			0x098C
-+#define AM33XX_CONTROL_PADCONF_MCASP0_ACLKX_OFFSET		0x0990
-+#define AM33XX_CONTROL_PADCONF_MCASP0_FSX_OFFSET		0x0994
-+#define AM33XX_CONTROL_PADCONF_MCASP0_AXR0_OFFSET		0x0998
-+#define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKR_OFFSET		0x099C
-+#define AM33XX_CONTROL_PADCONF_MCASP0_ACLKR_OFFSET		0x09A0
-+#define AM33XX_CONTROL_PADCONF_MCASP0_FSR_OFFSET		0x09A4
-+#define AM33XX_CONTROL_PADCONF_MCASP0_AXR1_OFFSET		0x09A8
-+#define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKX_OFFSET		0x09AC
-+#define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR0_OFFSET		0x09B0
-+#define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR1_OFFSET		0x09B4
-+#define AM33XX_CONTROL_PADCONF_WARMRSTN_OFFSET			0x09B8
-+#define AM33XX_CONTROL_PADCONF_PWRONRSTN_OFFSET			0x09BC
-+#define AM33XX_CONTROL_PADCONF_NMIN_OFFSET			0x09C0
-+#define AM33XX_CONTROL_PADCONF_XTALIN_OFFSET			0x09C4
-+#define AM33XX_CONTROL_PADCONF_XTALOUT_OFFSET			0x09C8
-+#define AM33XX_CONTROL_PADCONF_TMS_OFFSET			0x09D0
-+#define AM33XX_CONTROL_PADCONF_TDI_OFFSET			0x09D4
-+#define AM33XX_CONTROL_PADCONF_TDO_OFFSET			0x09D8
-+#define AM33XX_CONTROL_PADCONF_TCK_OFFSET			0x09DC
-+#define AM33XX_CONTROL_PADCONF_TRSTN_OFFSET			0x09E0
-+#define AM33XX_CONTROL_PADCONF_EMU0_OFFSET			0x09E4
-+#define AM33XX_CONTROL_PADCONF_EMU1_OFFSET			0x09E8
-+#define AM33XX_CONTROL_PADCONF_RTC_XTALIN_OFFSET		0x09EC
-+#define AM33XX_CONTROL_PADCONF_RTC_XTALOUT_OFFSET		0x09F0
-+#define AM33XX_CONTROL_PADCONF_RTC_PWRONRSTN_OFFSET		0x09F8
-+#define AM33XX_CONTROL_PADCONF_EXT_WAKEUP_OFFSET		0x0A00
-+#define AM33XX_CONTROL_PADCONF_PMIC_POWER_EN_OFFSET		0x09F4
-+#define AM33XX_CONTROL_PADCONF_RTC_KALDO_ENN_OFFSET		0x0A04
-+#define AM33XX_CONTROL_PADCONF_USB0_DM_OFFSET			0x0A08
-+#define AM33XX_CONTROL_PADCONF_USB0_DP_OFFSET		        0x0A0C
-+#define AM33XX_CONTROL_PADCONF_USB0_CE_OFFSET		        0x0A10
-+#define AM33XX_CONTROL_PADCONF_USB0_ID_OFFSET		        0x0A14
-+#define AM33XX_CONTROL_PADCONF_USB0_VBUS_OFFSET			0x0A18
-+#define AM33XX_CONTROL_PADCONF_USB0_DRVVBUS_OFFSET		0x0A1C
-+#define AM33XX_CONTROL_PADCONF_USB1_DM_OFFSET			0x0A20
-+#define AM33XX_CONTROL_PADCONF_USB1_DP_OFFSET		        0x0A24
-+#define AM33XX_CONTROL_PADCONF_USB1_CE_OFFSET		        0x0A28
-+#define AM33XX_CONTROL_PADCONF_USB1_ID_OFFSET		        0x0A2C
-+#define AM33XX_CONTROL_PADCONF_USB1_VBUS_OFFSET			0x0A30
-+#define AM33XX_CONTROL_PADCONF_USB1_DRVVBUS_OFFSET		0x0A34
-+#define AM33XX_CONTROL_PADCONF_DDR_RESETN_OFFSET		0x0A38
-+#define AM33XX_CONTROL_PADCONF_DDR_CSN0_OFFSET			0x0A3C
-+#define AM33XX_CONTROL_PADCONF_DDR_CKE_OFFSET			0x0A40
-+#define AM33XX_CONTROL_PADCONF_DDR_CK_OFFSET			0x0A44
-+#define AM33XX_CONTROL_PADCONF_DDR_CKN_OFFSET			0x0A48
-+#define AM33XX_CONTROL_PADCONF_DDR_CASN_OFFSET			0x0A4C
-+#define AM33XX_CONTROL_PADCONF_DDR_RASN_OFFSET			0x0A50
-+#define AM33XX_CONTROL_PADCONF_DDR_WEN_OFFSET			0x0A54
-+#define AM33XX_CONTROL_PADCONF_DDR_BA0_OFFSET			0x0A58
-+#define AM33XX_CONTROL_PADCONF_DDR_BA1_OFFSET			0x0A5C
-+#define AM33XX_CONTROL_PADCONF_DDR_BA2_OFFSET			0x0A60
-+#define AM33XX_CONTROL_PADCONF_DDR_A0_OFFSET			0x0A64
-+#define AM33XX_CONTROL_PADCONF_DDR_A1_OFFSET			0x0A68
-+#define AM33XX_CONTROL_PADCONF_DDR_A2_OFFSET			0x0A6C
-+#define AM33XX_CONTROL_PADCONF_DDR_A3_OFFSET			0x0A70
-+#define AM33XX_CONTROL_PADCONF_DDR_A4_OFFSET			0x0A74
-+#define AM33XX_CONTROL_PADCONF_DDR_A5_OFFSET			0x0A78
-+#define AM33XX_CONTROL_PADCONF_DDR_A6_OFFSET			0x0A7C
-+#define AM33XX_CONTROL_PADCONF_DDR_A7_OFFSET			0x0A80
-+#define AM33XX_CONTROL_PADCONF_DDR_A8_OFFSET			0x0A84
-+#define AM33XX_CONTROL_PADCONF_DDR_A9_OFFSET			0x0A88
-+#define AM33XX_CONTROL_PADCONF_DDR_A10_OFFSET			0x0A8C
-+#define AM33XX_CONTROL_PADCONF_DDR_A11_OFFSET			0x0A90
-+#define AM33XX_CONTROL_PADCONF_DDR_A12_OFFSET			0x0A94
-+#define AM33XX_CONTROL_PADCONF_DDR_A13_OFFSET			0x0A98
-+#define AM33XX_CONTROL_PADCONF_DDR_A14_OFFSET			0x0A9C
-+#define AM33XX_CONTROL_PADCONF_DDR_A15_OFFSET			0x0AA0
-+#define AM33XX_CONTROL_PADCONF_DDR_ODT_OFFSET			0x0AA4
-+#define AM33XX_CONTROL_PADCONF_DDR_D0_OFFSET			0x0AA8
-+#define AM33XX_CONTROL_PADCONF_DDR_D1_OFFSET			0x0AAC
-+#define AM33XX_CONTROL_PADCONF_DDR_D2_OFFSET			0x0AB0
-+#define AM33XX_CONTROL_PADCONF_DDR_D3_OFFSET			0x0AB4
-+#define AM33XX_CONTROL_PADCONF_DDR_D4_OFFSET			0x0AB8
-+#define AM33XX_CONTROL_PADCONF_DDR_D5_OFFSET			0x0ABC
-+#define AM33XX_CONTROL_PADCONF_DDR_D6_OFFSET			0x0AC0
-+#define AM33XX_CONTROL_PADCONF_DDR_D7_OFFSET			0x0AC4
-+#define AM33XX_CONTROL_PADCONF_DDR_D8_OFFSET			0x0AC8
-+#define AM33XX_CONTROL_PADCONF_DDR_D9_OFFSET			0x0ACC
-+#define AM33XX_CONTROL_PADCONF_DDR_D10_OFFSET			0x0AD0
-+#define AM33XX_CONTROL_PADCONF_DDR_D11_OFFSET			0x0AD4
-+#define AM33XX_CONTROL_PADCONF_DDR_D12_OFFSET			0x0AD8
-+#define AM33XX_CONTROL_PADCONF_DDR_D13_OFFSET			0x0ADC
-+#define AM33XX_CONTROL_PADCONF_DDR_D14_OFFSET			0x0AE0
-+#define AM33XX_CONTROL_PADCONF_DDR_D15_OFFSET			0x0AE4
-+#define AM33XX_CONTROL_PADCONF_DDR_DQM0_OFFSET			0x0AE8
-+#define AM33XX_CONTROL_PADCONF_DDR_DQM1_OFFSET			0x0AEC
-+#define AM33XX_CONTROL_PADCONF_DDR_DQS0_OFFSET			0x0AF0
-+#define AM33XX_CONTROL_PADCONF_DDR_DQSN0_OFFSET			0x0AF4
-+#define AM33XX_CONTROL_PADCONF_DDR_DQS1_OFFSET			0x0AF8
-+#define AM33XX_CONTROL_PADCONF_DDR_DQSN1_OFFSET			0x0AFC
-+#define AM33XX_CONTROL_PADCONF_DDR_VREF_OFFSET			0x0B00
-+#define AM33XX_CONTROL_PADCONF_DDR_VTP_OFFSET			0x0B04
-+#define AM33XX_CONTROL_PADCONF_AIN7_OFFSET			0x0B10
-+#define AM33XX_CONTROL_PADCONF_AIN6_OFFSET			0x0B14
-+#define AM33XX_CONTROL_PADCONF_AIN5_OFFSET			0x0B18
-+#define AM33XX_CONTROL_PADCONF_AIN4_OFFSET			0x0B1C
-+#define AM33XX_CONTROL_PADCONF_AIN3_OFFSET			0x0B20
-+#define AM33XX_CONTROL_PADCONF_AIN2_OFFSET			0x0B24
-+#define AM33XX_CONTROL_PADCONF_AIN1_OFFSET			0x0B28
-+#define AM33XX_CONTROL_PADCONF_AIN0_OFFSET			0x0B2C
-+#define AM33XX_CONTROL_PADCONF_VREFP_OFFSET			0x0B30
-+#define AM33XX_CONTROL_PADCONF_VREFN_OFFSET			0x0B34
-+
-+#define AM33XX_CONTROL_PADCONF_MUX_SIZE				\
-+		(AM33XX_CONTROL_PADCONF_VREFN_OFFSET + 0x4)
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
-index 4ee6aec..b13ef7e 100644
---- a/arch/arm/mach-omap2/omap-headsmp.S
-+++ b/arch/arm/mach-omap2/omap-headsmp.S
-@@ -18,11 +18,6 @@
- #include <linux/linkage.h>
- #include <linux/init.h>
- 
--/* Physical address needed since MMU not enabled yet on secondary core */
--#define OMAP4_AUX_CORE_BOOT1_PA			0x48281804
--
--	__INIT
--
- /*
-  * OMAP4 specific entry point for secondary CPU to jump from ROM
-  * code.  This routine also provides a holding flag into which
-diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
-index 4976b93..adbe4d8 100644
---- a/arch/arm/mach-omap2/omap-hotplug.c
-+++ b/arch/arm/mach-omap2/omap-hotplug.c
-@@ -19,7 +19,10 @@
- #include <linux/smp.h>
- 
- #include <asm/cacheflush.h>
--#include <mach/omap4-common.h>
-+
-+#include "common.h"
-+
-+#include "powerdomain.h"
- 
- int platform_cpu_kill(unsigned int cpu)
- {
-@@ -32,6 +35,8 @@ int platform_cpu_kill(unsigned int cpu)
-  */
- void platform_cpu_die(unsigned int cpu)
- {
-+	unsigned int this_cpu;
-+
- 	flush_cache_all();
- 	dsb();
- 
-@@ -39,15 +44,15 @@ void platform_cpu_die(unsigned int cpu)
- 	 * we're ready for shutdown now, so do it
- 	 */
- 	if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
--		printk(KERN_CRIT "Secure clear status failed\n");
-+		pr_err("Secure clear status failed\n");
- 
- 	for (;;) {
- 		/*
--		 * Execute WFI
-+		 * Enter into low power state
- 		 */
--		do_wfi();
--
--		if (omap_read_auxcoreboot0() == cpu) {
-+		omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
-+		this_cpu = smp_processor_id();
-+		if (omap_read_auxcoreboot0() == this_cpu) {
- 			/*
- 			 * OK, proper wakeup, we're done
- 			 */
-diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
-index ac49384..b882204 100644
---- a/arch/arm/mach-omap2/omap-iommu.c
-+++ b/arch/arm/mach-omap2/omap-iommu.c
-@@ -150,8 +150,7 @@ err_out:
- 		platform_device_put(omap_iommu_pdev[i]);
- 	return err;
- }
--/* must be ready before omap3isp is probed */
--subsys_initcall(omap_iommu_init);
-+module_init(omap_iommu_init);
- 
- static void __exit omap_iommu_exit(void)
- {
-diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
-new file mode 100644
-index 0000000..1d5d010
---- /dev/null
-+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
-@@ -0,0 +1,398 @@
-+/*
-+ * OMAP MPUSS low power code
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *
-+ * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
-+ * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
-+ * CPU0 and CPU1 LPRM modules.
-+ * CPU0, CPU1 and MPUSS each have there own power domain and
-+ * hence multiple low power combinations of MPUSS are possible.
-+ *
-+ * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
-+ * because the mode is not supported by hw constraints of dormant
-+ * mode. While waking up from the dormant mode, a reset  signal
-+ * to the Cortex-A9 processor must be asserted by the external
-+ * power controller.
-+ *
-+ * With architectural inputs and hardware recommendations, only
-+ * below modes are supported from power gain vs latency point of view.
-+ *
-+ *	CPU0		CPU1		MPUSS
-+ *	----------------------------------------------
-+ *	ON		ON		ON
-+ *	ON(Inactive)	OFF		ON(Inactive)
-+ *	OFF		OFF		CSWR
-+ *	OFF		OFF		OSWR
-+ *	OFF		OFF		OFF(Device OFF *TBD)
-+ *	----------------------------------------------
-+ *
-+ * Note: CPU0 is the master core and it is the last CPU to go down
-+ * and first to wake-up when MPUSS low power states are excercised
-+ *
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/io.h>
-+#include <linux/errno.h>
-+#include <linux/linkage.h>
-+#include <linux/smp.h>
-+
-+#include <asm/cacheflush.h>
-+#include <asm/tlbflush.h>
-+#include <asm/smp_scu.h>
-+#include <asm/system.h>
-+#include <asm/pgalloc.h>
-+#include <asm/suspend.h>
-+#include <asm/hardware/cache-l2x0.h>
-+
-+#include <plat/omap44xx.h>
-+
-+#include "common.h"
-+#include "omap4-sar-layout.h"
-+#include "pm.h"
-+#include "prcm_mpu44xx.h"
-+#include "prminst44xx.h"
-+#include "prcm44xx.h"
-+#include "prm44xx.h"
-+#include "prm-regbits-44xx.h"
-+
-+#ifdef CONFIG_SMP
-+
-+struct omap4_cpu_pm_info {
-+	struct powerdomain *pwrdm;
-+	void __iomem *scu_sar_addr;
-+	void __iomem *wkup_sar_addr;
-+	void __iomem *l2x0_sar_addr;
-+};
-+
-+static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
-+static struct powerdomain *mpuss_pd;
-+static void __iomem *sar_base;
-+
-+/*
-+ * Program the wakeup routine address for the CPU0 and CPU1
-+ * used for OFF or DORMANT wakeup.
-+ */
-+static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
-+{
-+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-+
-+	__raw_writel(addr, pm_info->wkup_sar_addr);
-+}
-+
-+/*
-+ * Set the CPUx powerdomain's previous power state
-+ */
-+static inline void set_cpu_next_pwrst(unsigned int cpu_id,
-+				unsigned int power_state)
-+{
-+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-+
-+	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
-+}
-+
-+/*
-+ * Read CPU's previous power state
-+ */
-+static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
-+{
-+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-+
-+	return pwrdm_read_prev_pwrst(pm_info->pwrdm);
-+}
-+
-+/*
-+ * Clear the CPUx powerdomain's previous power state
-+ */
-+static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
-+{
-+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-+
-+	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
-+}
-+
-+/*
-+ * Store the SCU power status value to scratchpad memory
-+ */
-+static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
-+{
-+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-+	u32 scu_pwr_st;
-+
-+	switch (cpu_state) {
-+	case PWRDM_POWER_RET:
-+		scu_pwr_st = SCU_PM_DORMANT;
-+		break;
-+	case PWRDM_POWER_OFF:
-+		scu_pwr_st = SCU_PM_POWEROFF;
-+		break;
-+	case PWRDM_POWER_ON:
-+	case PWRDM_POWER_INACTIVE:
-+	default:
-+		scu_pwr_st = SCU_PM_NORMAL;
-+		break;
-+	}
-+
-+	__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
-+}
-+
-+/* Helper functions for MPUSS OSWR */
-+static inline void mpuss_clear_prev_logic_pwrst(void)
-+{
-+	u32 reg;
-+
-+	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-+		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
-+	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
-+		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
-+}
-+
-+static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
-+{
-+	u32 reg;
-+
-+	if (cpu_id) {
-+		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
-+					OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
-+		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
-+					OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
-+	} else {
-+		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
-+					OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
-+		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
-+					OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
-+	}
-+}
-+
-+/**
-+ * omap4_mpuss_read_prev_context_state:
-+ * Function returns the MPUSS previous context state
-+ */
-+u32 omap4_mpuss_read_prev_context_state(void)
-+{
-+	u32 reg;
-+
-+	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-+		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
-+	reg &= OMAP4430_LOSTCONTEXT_DFF_MASK;
-+	return reg;
-+}
-+
-+/*
-+ * Store the CPU cluster state for L2X0 low power operations.
-+ */
-+static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
-+{
-+	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-+
-+	__raw_writel(save_state, pm_info->l2x0_sar_addr);
-+}
-+
-+/*
-+ * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
-+ * in every restore MPUSS OFF path.
-+ */
-+#ifdef CONFIG_CACHE_L2X0
-+static void save_l2x0_context(void)
-+{
-+	u32 val;
-+	void __iomem *l2x0_base = omap4_get_l2cache_base();
-+
-+	val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
-+	__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
-+	val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
-+	__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
-+}
-+#else
-+static void save_l2x0_context(void)
-+{}
-+#endif
-+
-+/**
-+ * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
-+ * The purpose of this function is to manage low power programming
-+ * of OMAP4 MPUSS subsystem
-+ * @cpu : CPU ID
-+ * @power_state: Low power state.
-+ *
-+ * MPUSS states for the context save:
-+ * save_state =
-+ *	0 - Nothing lost and no need to save: MPUSS INACTIVE
-+ *	1 - CPUx L1 and logic lost: MPUSS CSWR
-+ *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
-+ *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
-+ */
-+int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
-+{
-+	unsigned int save_state = 0;
-+	unsigned int wakeup_cpu;
-+
-+	if (omap_rev() == OMAP4430_REV_ES1_0)
-+		return -ENXIO;
-+
-+	switch (power_state) {
-+	case PWRDM_POWER_ON:
-+	case PWRDM_POWER_INACTIVE:
-+		save_state = 0;
-+		break;
-+	case PWRDM_POWER_OFF:
-+		save_state = 1;
-+		break;
-+	case PWRDM_POWER_RET:
-+	default:
-+		/*
-+		 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
-+		 * doesn't make much scense, since logic is lost and $L1
-+		 * needs to be cleaned because of coherency. This makes
-+		 * CPUx OSWR equivalent to CPUX OFF and hence not supported
-+		 */
-+		WARN_ON(1);
-+		return -ENXIO;
-+	}
-+
-+	pwrdm_pre_transition();
-+
-+	/*
-+	 * Check MPUSS next state and save interrupt controller if needed.
-+	 * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
-+	 */
-+	mpuss_clear_prev_logic_pwrst();
-+	pwrdm_clear_all_prev_pwrst(mpuss_pd);
-+	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
-+		(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
-+		save_state = 2;
-+
-+	clear_cpu_prev_pwrst(cpu);
-+	cpu_clear_prev_logic_pwrst(cpu);
-+	set_cpu_next_pwrst(cpu, power_state);
-+	set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
-+	scu_pwrst_prepare(cpu, power_state);
-+	l2x0_pwrst_prepare(cpu, save_state);
-+
-+	/*
-+	 * Call low level function  with targeted low power state.
-+	 */
-+	cpu_suspend(save_state, omap4_finish_suspend);
-+
-+	/*
-+	 * Restore the CPUx power state to ON otherwise CPUx
-+	 * power domain can transitions to programmed low power
-+	 * state while doing WFI outside the low powe code. On
-+	 * secure devices, CPUx does WFI which can result in
-+	 * domain transition
-+	 */
-+	wakeup_cpu = smp_processor_id();
-+	set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
-+
-+	pwrdm_post_transition();
-+
-+	return 0;
-+}
-+
-+/**
-+ * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
-+ * @cpu : CPU ID
-+ * @power_state: CPU low power state.
-+ */
-+int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
-+{
-+	unsigned int cpu_state = 0;
-+
-+	if (omap_rev() == OMAP4430_REV_ES1_0)
-+		return -ENXIO;
-+
-+	if (power_state == PWRDM_POWER_OFF)
-+		cpu_state = 1;
-+
-+	clear_cpu_prev_pwrst(cpu);
-+	set_cpu_next_pwrst(cpu, power_state);
-+	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
-+	scu_pwrst_prepare(cpu, power_state);
-+
-+	/*
-+	 * CPU never retuns back if targetted power state is OFF mode.
-+	 * CPU ONLINE follows normal CPU ONLINE ptah via
-+	 * omap_secondary_startup().
-+	 */
-+	omap4_finish_suspend(cpu_state);
-+
-+	set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
-+	return 0;
-+}
-+
-+
-+/*
-+ * Initialise OMAP4 MPUSS
-+ */
-+int __init omap4_mpuss_init(void)
-+{
-+	struct omap4_cpu_pm_info *pm_info;
-+
-+	if (omap_rev() == OMAP4430_REV_ES1_0) {
-+		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
-+		return -ENODEV;
-+	}
-+
-+	sar_base = omap4_get_sar_ram_base();
-+
-+	/* Initilaise per CPU PM information */
-+	pm_info = &per_cpu(omap4_pm_info, 0x0);
-+	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
-+	pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
-+	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
-+	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
-+	if (!pm_info->pwrdm) {
-+		pr_err("Lookup failed for CPU0 pwrdm\n");
-+		return -ENODEV;
-+	}
-+
-+	/* Clear CPU previous power domain state */
-+	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
-+	cpu_clear_prev_logic_pwrst(0);
-+
-+	/* Initialise CPU0 power domain state to ON */
-+	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
-+
-+	pm_info = &per_cpu(omap4_pm_info, 0x1);
-+	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
-+	pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
-+	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
-+	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
-+	if (!pm_info->pwrdm) {
-+		pr_err("Lookup failed for CPU1 pwrdm\n");
-+		return -ENODEV;
-+	}
-+
-+	/* Clear CPU previous power domain state */
-+	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
-+	cpu_clear_prev_logic_pwrst(1);
-+
-+	/* Initialise CPU1 power domain state to ON */
-+	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
-+
-+	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
-+	if (!mpuss_pd) {
-+		pr_err("Failed to lookup MPUSS power domain\n");
-+		return -ENODEV;
-+	}
-+	pwrdm_clear_all_prev_pwrst(mpuss_pd);
-+	mpuss_clear_prev_logic_pwrst();
-+
-+	/* Save device type on scratchpad for low level code to use */
-+	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
-+		__raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
-+	else
-+		__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
-+
-+	save_l2x0_context();
-+
-+	return 0;
-+}
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
-new file mode 100644
-index 0000000..69f3c72
---- /dev/null
-+++ b/arch/arm/mach-omap2/omap-secure.c
-@@ -0,0 +1,81 @@
-+/*
-+ * OMAP Secure API infrastructure.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *
-+ *
-+ * This program is free software,you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/memblock.h>
-+
-+#include <asm/cacheflush.h>
-+
-+#include <mach/omap-secure.h>
-+
-+static phys_addr_t omap_secure_memblock_base;
-+
-+/**
-+ * omap_sec_dispatcher: Routine to dispatch low power secure
-+ * service routines
-+ * @idx: The HAL API index
-+ * @flag: The flag indicating criticality of operation
-+ * @nargs: Number of valid arguments out of four.
-+ * @arg1, arg2, arg3 args4: Parameters passed to secure API
-+ *
-+ * Return the non-zero error value on failure.
-+ */
-+u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
-+							 u32 arg3, u32 arg4)
-+{
-+	u32 ret;
-+	u32 param[5];
-+
-+	param[0] = nargs;
-+	param[1] = arg1;
-+	param[2] = arg2;
-+	param[3] = arg3;
-+	param[4] = arg4;
-+
-+	/*
-+	 * Secure API needs physical address
-+	 * pointer for the parameters
-+	 */
-+	flush_cache_all();
-+	outer_clean_range(__pa(param), __pa(param + 5));
-+	ret = omap_smc2(idx, flag, __pa(param));
-+
-+	return ret;
-+}
-+
-+/* Allocate the memory to save secure ram */
-+int __init omap_secure_ram_reserve_memblock(void)
-+{
-+	phys_addr_t paddr;
-+	u32 size = OMAP_SECURE_RAM_STORAGE;
-+
-+	size = ALIGN(size, SZ_1M);
-+	paddr = memblock_alloc(size, SZ_1M);
-+	if (!paddr) {
-+		pr_err("%s: failed to reserve %x bytes\n",
-+				__func__, size);
-+		return -ENOMEM;
-+	}
-+	memblock_free(paddr, size);
-+	memblock_remove(paddr, size);
-+
-+	omap_secure_memblock_base = paddr;
-+
-+	return 0;
-+}
-+
-+phys_addr_t omap_secure_ram_mempool_base(void)
-+{
-+	return omap_secure_memblock_base;
-+}
-diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S
-new file mode 100644
-index 0000000..f6441c1
---- /dev/null
-+++ b/arch/arm/mach-omap2/omap-smc.S
-@@ -0,0 +1,80 @@
-+/*
-+ * OMAP44xx secure APIs file.
-+ *
-+ * Copyright (C) 2010 Texas Instruments, Inc.
-+ * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *
-+ *
-+ * This program is free software,you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/linkage.h>
-+
-+/*
-+ * This is common routine to manage secure monitor API
-+ * used to modify the PL310 secure registers.
-+ * 'r0' contains the value to be modified and 'r12' contains
-+ * the monitor API number. It uses few CPU registers
-+ * internally and hence they need be backed up including
-+ * link register "lr".
-+ * Function signature : void omap_smc1(u32 fn, u32 arg)
-+ */
-+
-+ENTRY(omap_smc1)
-+	stmfd   sp!, {r2-r12, lr}
-+	mov	r12, r0
-+	mov 	r0, r1
-+	dsb
-+	smc	#0
-+	ldmfd   sp!, {r2-r12, pc}
-+ENDPROC(omap_smc1)
-+
-+/**
-+ * u32 omap_smc2(u32 id, u32 falg, u32 pargs)
-+ * Low level common routine for secure HAL and PPA APIs.
-+ * @id: Application ID of HAL APIs
-+ * @flag: Flag to indicate the criticality of operation
-+ * @pargs: Physical address of parameter list starting
-+ *	    with number of parametrs
-+ */
-+ENTRY(omap_smc2)
-+	stmfd   sp!, {r4-r12, lr}
-+	mov	r3, r2
-+	mov	r2, r1
-+	mov	r1, #0x0	@ Process ID
-+	mov	r6, #0xff
-+	mov	r12, #0x00	@ Secure Service ID
-+	mov	r7, #0
-+	mcr	p15, 0, r7, c7, c5, 6
-+	dsb
-+	dmb
-+	smc	#0
-+	ldmfd   sp!, {r4-r12, pc}
-+ENDPROC(omap_smc2)
-+
-+ENTRY(omap_modify_auxcoreboot0)
-+	stmfd   sp!, {r1-r12, lr}
-+	ldr	r12, =0x104
-+	dsb
-+	smc	#0
-+	ldmfd   sp!, {r1-r12, pc}
-+ENDPROC(omap_modify_auxcoreboot0)
-+
-+ENTRY(omap_auxcoreboot_addr)
-+	stmfd   sp!, {r2-r12, lr}
-+	ldr	r12, =0x105
-+	dsb
-+	smc	#0
-+	ldmfd   sp!, {r2-r12, pc}
-+ENDPROC(omap_auxcoreboot_addr)
-+
-+ENTRY(omap_read_auxcoreboot0)
-+	stmfd   sp!, {r2-r12, lr}
-+	ldr	r12, =0x103
-+	dsb
-+	smc	#0
-+	mov	r0, r0, lsr #9
-+	ldmfd   sp!, {r2-r12, pc}
-+ENDPROC(omap_read_auxcoreboot0)
-diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
-index 4412ddb..c1bf3ef 100644
---- a/arch/arm/mach-omap2/omap-smp.c
-+++ b/arch/arm/mach-omap2/omap-smp.c
-@@ -24,16 +24,37 @@
- #include <asm/hardware/gic.h>
- #include <asm/smp_scu.h>
- #include <mach/hardware.h>
--#include <mach/omap4-common.h>
-+#include <mach/omap-secure.h>
-+
-+#include "common.h"
-+
-+#include "clockdomain.h"
- 
- /* SCU base address */
- static void __iomem *scu_base;
- 
- static DEFINE_SPINLOCK(boot_lock);
- 
-+void __iomem *omap4_get_scu_base(void)
-+{
-+	return scu_base;
-+}
-+
- void __cpuinit platform_secondary_init(unsigned int cpu)
- {
- 	/*
-+	 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
-+	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
-+	 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
-+	 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
-+	 * OMAP443X GP devices- SMP bit isn't accessible.
-+	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
-+	 */
-+	if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
-+		omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
-+							4, 0, 0, 0, 0, 0);
-+
-+	/*
- 	 * If any interrupts are already enabled for the primary
- 	 * core (e.g. timer irq), then they will not have been enabled
- 	 * for us: do so
-@@ -49,6 +70,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
- 
- int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
- {
-+	static struct clockdomain *cpu1_clkdm;
-+	static bool booted;
- 	/*
- 	 * Set synchronisation state between this boot processor
- 	 * and the secondary one
-@@ -64,6 +87,29 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
- 	omap_modify_auxcoreboot0(0x200, 0xfffffdff);
- 	flush_cache_all();
- 	smp_wmb();
-+
-+	if (!cpu1_clkdm)
-+		cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
-+
-+	/*
-+	 * The SGI(Software Generated Interrupts) are not wakeup capable
-+	 * from low power states. This is known limitation on OMAP4 and
-+	 * needs to be worked around by using software forced clockdomain
-+	 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
-+	 * software force wakeup. The clockdomain is then put back to
-+	 * hardware supervised mode.
-+	 * More details can be found in OMAP4430 TRM - Version J
-+	 * Section :
-+	 *	4.3.4.2 Power States of CPU0 and CPU1
-+	 */
-+	if (booted) {
-+		clkdm_wakeup(cpu1_clkdm);
-+		clkdm_allow_idle(cpu1_clkdm);
-+	} else {
-+		dsb_sev();
-+		booted = true;
-+	}
-+
- 	gic_raise_softirq(cpumask_of(cpu), 1);
- 
- 	/*
-diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
-new file mode 100644
-index 0000000..d3d8971
---- /dev/null
-+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
-@@ -0,0 +1,389 @@
-+/*
-+ * OMAP WakeupGen Source file
-+ *
-+ * OMAP WakeupGen is the interrupt controller extension used along
-+ * with ARM GIC to wake the CPU out from low power states on
-+ * external interrupts. It is responsible for generating wakeup
-+ * event from the incoming interrupts and enable bits. It is
-+ * implemented in MPU always ON power domain. During normal operation,
-+ * WakeupGen delivers external interrupts directly to the GIC.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/platform_device.h>
-+#include <linux/cpu.h>
-+#include <linux/notifier.h>
-+#include <linux/cpu_pm.h>
-+
-+#include <asm/hardware/gic.h>
-+
-+#include <mach/omap-wakeupgen.h>
-+#include <mach/omap-secure.h>
-+
-+#include "omap4-sar-layout.h"
-+#include "common.h"
-+
-+#define NR_REG_BANKS		4
-+#define MAX_IRQS		128
-+#define WKG_MASK_ALL		0x00000000
-+#define WKG_UNMASK_ALL		0xffffffff
-+#define CPU_ENA_OFFSET		0x400
-+#define CPU0_ID			0x0
-+#define CPU1_ID			0x1
-+
-+static void __iomem *wakeupgen_base;
-+static void __iomem *sar_base;
-+static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
-+static DEFINE_SPINLOCK(wakeupgen_lock);
-+static unsigned int irq_target_cpu[NR_IRQS];
-+
-+/*
-+ * Static helper functions.
-+ */
-+static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
-+{
-+	return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
-+				(cpu * CPU_ENA_OFFSET) + (idx * 4));
-+}
-+
-+static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
-+{
-+	__raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
-+				(cpu * CPU_ENA_OFFSET) + (idx * 4));
-+}
-+
-+static inline void sar_writel(u32 val, u32 offset, u8 idx)
-+{
-+	__raw_writel(val, sar_base + offset + (idx * 4));
-+}
-+
-+static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
-+{
-+	u8 i;
-+
-+	for (i = 0; i < NR_REG_BANKS; i++)
-+		wakeupgen_writel(reg, i, cpu);
-+}
-+
-+static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
-+{
-+	unsigned int spi_irq;
-+
-+	/*
-+	 * PPIs and SGIs are not supported.
-+	 */
-+	if (irq < OMAP44XX_IRQ_GIC_START)
-+		return -EINVAL;
-+
-+	/*
-+	 * Subtract the GIC offset.
-+	 */
-+	spi_irq = irq - OMAP44XX_IRQ_GIC_START;
-+	if (spi_irq > MAX_IRQS) {
-+		pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
-+		return -EINVAL;
-+	}
-+
-+	/*
-+	 * Each WakeupGen register controls 32 interrupt.
-+	 * i.e. 1 bit per SPI IRQ
-+	 */
-+	*reg_index = spi_irq >> 5;
-+	*bit_posn = spi_irq %= 32;
-+
-+	return 0;
-+}
-+
-+static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
-+{
-+	u32 val, bit_number;
-+	u8 i;
-+
-+	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
-+		return;
-+
-+	val = wakeupgen_readl(i, cpu);
-+	val &= ~BIT(bit_number);
-+	wakeupgen_writel(val, i, cpu);
-+}
-+
-+static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
-+{
-+	u32 val, bit_number;
-+	u8 i;
-+
-+	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
-+		return;
-+
-+	val = wakeupgen_readl(i, cpu);
-+	val |= BIT(bit_number);
-+	wakeupgen_writel(val, i, cpu);
-+}
-+
-+static void _wakeupgen_save_masks(unsigned int cpu)
-+{
-+	u8 i;
-+
-+	for (i = 0; i < NR_REG_BANKS; i++)
-+		per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
-+}
-+
-+static void _wakeupgen_restore_masks(unsigned int cpu)
-+{
-+	u8 i;
-+
-+	for (i = 0; i < NR_REG_BANKS; i++)
-+		wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
-+}
-+
-+/*
-+ * Architecture specific Mask extension
-+ */
-+static void wakeupgen_mask(struct irq_data *d)
-+{
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&wakeupgen_lock, flags);
-+	_wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
-+	spin_unlock_irqrestore(&wakeupgen_lock, flags);
-+}
-+
-+/*
-+ * Architecture specific Unmask extension
-+ */
-+static void wakeupgen_unmask(struct irq_data *d)
-+{
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&wakeupgen_lock, flags);
-+	_wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
-+	spin_unlock_irqrestore(&wakeupgen_lock, flags);
-+}
-+
-+/*
-+ * Mask or unmask all interrupts on given CPU.
-+ *	0 = Mask all interrupts on the 'cpu'
-+ *	1 = Unmask all interrupts on the 'cpu'
-+ * Ensure that the initial mask is maintained. This is faster than
-+ * iterating through GIC registers to arrive at the correct masks.
-+ */
-+static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
-+{
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&wakeupgen_lock, flags);
-+	if (set) {
-+		_wakeupgen_save_masks(cpu);
-+		_wakeupgen_set_all(cpu, WKG_MASK_ALL);
-+	} else {
-+		_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
-+		_wakeupgen_restore_masks(cpu);
-+	}
-+	spin_unlock_irqrestore(&wakeupgen_lock, flags);
-+}
-+
-+#ifdef CONFIG_CPU_PM
-+/*
-+ * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
-+ * ROM code. WakeupGen IP is integrated along with GIC to manage the
-+ * interrupt wakeups from CPU low power states. It manages
-+ * masking/unmasking of Shared peripheral interrupts(SPI). So the
-+ * interrupt enable/disable control should be in sync and consistent
-+ * at WakeupGen and GIC so that interrupts are not lost.
-+ */
-+static void irq_save_context(void)
-+{
-+	u32 i, val;
-+
-+	if (omap_rev() == OMAP4430_REV_ES1_0)
-+		return;
-+
-+	if (!sar_base)
-+		sar_base = omap4_get_sar_ram_base();
-+
-+	for (i = 0; i < NR_REG_BANKS; i++) {
-+		/* Save the CPUx interrupt mask for IRQ 0 to 127 */
-+		val = wakeupgen_readl(i, 0);
-+		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
-+		val = wakeupgen_readl(i, 1);
-+		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
-+
-+		/*
-+		 * Disable the secure interrupts for CPUx. The restore
-+		 * code blindly restores secure and non-secure interrupt
-+		 * masks from SAR RAM. Secure interrupts are not suppose
-+		 * to be enabled from HLOS. So overwrite the SAR location
-+		 * so that the secure interrupt remains disabled.
-+		 */
-+		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
-+		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
-+	}
-+
-+	/* Save AuxBoot* registers */
-+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-+	__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
-+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-+	__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
-+
-+	/* Save SyncReq generation logic */
-+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-+	__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
-+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-+	__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
-+
-+	/* Save SyncReq generation logic */
-+	val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
-+	__raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
-+	val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
-+	__raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
-+
-+	/* Set the Backup Bit Mask status */
-+	val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
-+	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
-+	__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
-+}
-+
-+/*
-+ * Clear WakeupGen SAR backup status.
-+ */
-+void irq_sar_clear(void)
-+{
-+	u32 val;
-+	val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
-+	val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
-+	__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
-+}
-+
-+/*
-+ * Save GIC and Wakeupgen interrupt context using secure API
-+ * for HS/EMU devices.
-+ */
-+static void irq_save_secure_context(void)
-+{
-+	u32 ret;
-+	ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
-+				FLAG_START_CRITICAL,
-+				0, 0, 0, 0, 0);
-+	if (ret != API_HAL_RET_VALUE_OK)
-+		pr_err("GIC and Wakeupgen context save failed\n");
-+}
-+#endif
-+
-+#ifdef CONFIG_HOTPLUG_CPU
-+static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
-+					 unsigned long action, void *hcpu)
-+{
-+	unsigned int cpu = (unsigned int)hcpu;
-+
-+	switch (action) {
-+	case CPU_ONLINE:
-+		wakeupgen_irqmask_all(cpu, 0);
-+		break;
-+	case CPU_DEAD:
-+		wakeupgen_irqmask_all(cpu, 1);
-+		break;
-+	}
-+	return NOTIFY_OK;
-+}
-+
-+static struct notifier_block __refdata irq_hotplug_notifier = {
-+	.notifier_call = irq_cpu_hotplug_notify,
-+};
-+
-+static void __init irq_hotplug_init(void)
-+{
-+	register_hotcpu_notifier(&irq_hotplug_notifier);
-+}
-+#else
-+static void __init irq_hotplug_init(void)
-+{}
-+#endif
-+
-+#ifdef CONFIG_CPU_PM
-+static int irq_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
-+{
-+	switch (cmd) {
-+	case CPU_CLUSTER_PM_ENTER:
-+		if (omap_type() == OMAP2_DEVICE_TYPE_GP)
-+			irq_save_context();
-+		else
-+			irq_save_secure_context();
-+		break;
-+	case CPU_CLUSTER_PM_EXIT:
-+		if (omap_type() == OMAP2_DEVICE_TYPE_GP)
-+			irq_sar_clear();
-+		break;
-+	}
-+	return NOTIFY_OK;
-+}
-+
-+static struct notifier_block irq_notifier_block = {
-+	.notifier_call = irq_notifier,
-+};
-+
-+static void __init irq_pm_init(void)
-+{
-+	cpu_pm_register_notifier(&irq_notifier_block);
-+}
-+#else
-+static void __init irq_pm_init(void)
-+{}
-+#endif
-+
-+/*
-+ * Initialise the wakeupgen module.
-+ */
-+int __init omap_wakeupgen_init(void)
-+{
-+	int i;
-+	unsigned int boot_cpu = smp_processor_id();
-+
-+	/* Not supported on OMAP4 ES1.0 silicon */
-+	if (omap_rev() == OMAP4430_REV_ES1_0) {
-+		WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
-+		return -EPERM;
-+	}
-+
-+	/* Static mapping, never released */
-+	wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
-+	if (WARN_ON(!wakeupgen_base))
-+		return -ENOMEM;
-+
-+	/* Clear all IRQ bitmasks at wakeupGen level */
-+	for (i = 0; i < NR_REG_BANKS; i++) {
-+		wakeupgen_writel(0, i, CPU0_ID);
-+		wakeupgen_writel(0, i, CPU1_ID);
-+	}
-+
-+	/*
-+	 * Override GIC architecture specific functions to add
-+	 * OMAP WakeupGen interrupt controller along with GIC
-+	 */
-+	gic_arch_extn.irq_mask = wakeupgen_mask;
-+	gic_arch_extn.irq_unmask = wakeupgen_unmask;
-+	gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
-+
-+	/*
-+	 * FIXME: Add support to set_smp_affinity() once the core
-+	 * GIC code has necessary hooks in place.
-+	 */
-+
-+	/* Associate all the IRQs to boot CPU like GIC init does. */
-+	for (i = 0; i < NR_IRQS; i++)
-+		irq_target_cpu[i] = boot_cpu;
-+
-+	irq_hotplug_init();
-+	irq_pm_init();
-+
-+	return 0;
-+}
-diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
-index 35ac3e5..bc16c81 100644
---- a/arch/arm/mach-omap2/omap4-common.c
-+++ b/arch/arm/mach-omap2/omap4-common.c
-@@ -15,24 +15,80 @@
- #include <linux/init.h>
- #include <linux/io.h>
- #include <linux/platform_device.h>
-+#include <linux/memblock.h>
- 
- #include <asm/hardware/gic.h>
- #include <asm/hardware/cache-l2x0.h>
-+#include <asm/mach/map.h>
- 
- #include <plat/irqs.h>
-+#include <plat/sram.h>
- 
- #include <mach/hardware.h>
--#include <mach/omap4-common.h>
-+#include <mach/omap-wakeupgen.h>
-+
-+#include "common.h"
-+#include "omap4-sar-layout.h"
- 
- #ifdef CONFIG_CACHE_L2X0
--void __iomem *l2cache_base;
-+static void __iomem *l2cache_base;
- #endif
- 
--void __iomem *gic_dist_base_addr;
-+static void __iomem *sar_ram_base;
-+
-+#ifdef CONFIG_OMAP4_ERRATA_I688
-+/* Used to implement memory barrier on DRAM path */
-+#define OMAP4_DRAM_BARRIER_VA			0xfe600000
-+
-+void __iomem *dram_sync, *sram_sync;
-+
-+void omap_bus_sync(void)
-+{
-+	if (dram_sync && sram_sync) {
-+		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
-+		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
-+		isb();
-+	}
-+}
-+
-+static int __init omap_barriers_init(void)
-+{
-+	struct map_desc dram_io_desc[1];
-+	phys_addr_t paddr;
-+	u32 size;
-+
-+	if (!cpu_is_omap44xx())
-+		return -ENODEV;
- 
-+	size = ALIGN(PAGE_SIZE, SZ_1M);
-+	paddr = memblock_alloc(size, SZ_1M);
-+	if (!paddr) {
-+		pr_err("%s: failed to reserve 4 Kbytes\n", __func__);
-+		return -ENOMEM;
-+	}
-+	memblock_free(paddr, size);
-+	memblock_remove(paddr, size);
-+	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
-+	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
-+	dram_io_desc[0].length = size;
-+	dram_io_desc[0].type = MT_MEMORY_SO;
-+	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
-+	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
-+	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
-+
-+	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
-+		(long long) paddr, dram_io_desc[0].virtual);
-+
-+	return 0;
-+}
-+core_initcall(omap_barriers_init);
-+#endif
- 
- void __init gic_init_irq(void)
- {
-+	void __iomem *omap_irq_base;
-+	void __iomem *gic_dist_base_addr;
-+
- 	/* Static mapping, never released */
- 	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
- 	BUG_ON(!gic_dist_base_addr);
-@@ -41,11 +97,18 @@ void __init gic_init_irq(void)
- 	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
- 	BUG_ON(!omap_irq_base);
- 
-+	omap_wakeupgen_init();
-+
- 	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
- }
- 
- #ifdef CONFIG_CACHE_L2X0
- 
-+void __iomem *omap4_get_l2cache_base(void)
-+{
-+	return l2cache_base;
-+}
-+
- static void omap4_l2x0_disable(void)
- {
- 	/* Disable PL310 L2 Cache controller */
-@@ -71,7 +134,8 @@ static int __init omap_l2_cache_init(void)
- 
- 	/* Static mapping, never released */
- 	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
--	BUG_ON(!l2cache_base);
-+	if (WARN_ON(!l2cache_base))
-+		return -ENOMEM;
- 
- 	/*
- 	 * 16-way associativity, parity disabled
-@@ -111,3 +175,30 @@ static int __init omap_l2_cache_init(void)
- }
- early_initcall(omap_l2_cache_init);
- #endif
-+
-+void __iomem *omap4_get_sar_ram_base(void)
-+{
-+	return sar_ram_base;
-+}
-+
-+/*
-+ * SAR RAM used to save and restore the HW
-+ * context in low power modes
-+ */
-+static int __init omap4_sar_ram_init(void)
-+{
-+	/*
-+	 * To avoid code running on other OMAPs in
-+	 * multi-omap builds
-+	 */
-+	if (!cpu_is_omap44xx())
-+		return -ENOMEM;
-+
-+	/* Static mapping, never released */
-+	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
-+	if (WARN_ON(!sar_ram_base))
-+		return -ENOMEM;
-+
-+	return 0;
-+}
-+early_initcall(omap4_sar_ram_init);
-diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
-new file mode 100644
-index 0000000..fe5b545
---- /dev/null
-+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
-@@ -0,0 +1,50 @@
-+/*
-+ * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
-+#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
-+
-+/*
-+ * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
-+ */
-+#define SAR_BANK1_OFFSET		0x0000
-+#define SAR_BANK2_OFFSET		0x1000
-+#define SAR_BANK3_OFFSET		0x2000
-+#define SAR_BANK4_OFFSET		0x3000
-+
-+/* Scratch pad memory offsets from SAR_BANK1 */
-+#define SCU_OFFSET0				0xd00
-+#define SCU_OFFSET1				0xd04
-+#define OMAP_TYPE_OFFSET			0xd10
-+#define L2X0_SAVE_OFFSET0			0xd14
-+#define L2X0_SAVE_OFFSET1			0xd18
-+#define L2X0_AUXCTRL_OFFSET			0xd1c
-+#define L2X0_PREFETCH_CTRL_OFFSET		0xd20
-+
-+/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
-+#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET		0xa04
-+#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET		0xa08
-+
-+#define SAR_BACKUP_STATUS_OFFSET		(SAR_BANK3_OFFSET + 0x500)
-+#define SAR_SECURE_RAM_SIZE_OFFSET		(SAR_BANK3_OFFSET + 0x504)
-+#define SAR_SECRAM_SAVED_AT_OFFSET		(SAR_BANK3_OFFSET + 0x508)
-+
-+/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
-+#define WAKEUPGENENB_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x684)
-+#define WAKEUPGENENB_SECURE_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x694)
-+#define WAKEUPGENENB_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0x6a4)
-+#define WAKEUPGENENB_SECURE_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0x6b4)
-+#define AUXCOREBOOT0_OFFSET			(SAR_BANK3_OFFSET + 0x6c4)
-+#define AUXCOREBOOT1_OFFSET			(SAR_BANK3_OFFSET + 0x6c8)
-+#define PTMSYNCREQ_MASK_OFFSET			(SAR_BANK3_OFFSET + 0x6cc)
-+#define PTMSYNCREQ_EN_OFFSET			(SAR_BANK3_OFFSET + 0x6d0)
-+#define SAR_BACKUP_STATUS_WAKEUPGEN		0x10
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
-deleted file mode 100644
-index e69d37d..0000000
---- a/arch/arm/mach-omap2/omap44xx-smc.S
-+++ /dev/null
-@@ -1,57 +0,0 @@
--/*
-- * OMAP44xx secure APIs file.
-- *
-- * Copyright (C) 2010 Texas Instruments, Inc.
-- * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
-- *
-- *
-- * This program is free software,you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--
--#include <linux/linkage.h>
--
--/*
-- * This is common routine to manage secure monitor API
-- * used to modify the PL310 secure registers.
-- * 'r0' contains the value to be modified and 'r12' contains
-- * the monitor API number. It uses few CPU registers
-- * internally and hence they need be backed up including
-- * link register "lr".
-- * Function signature : void omap_smc1(u32 fn, u32 arg)
-- */
--
--ENTRY(omap_smc1)
--	stmfd   sp!, {r2-r12, lr}
--	mov	r12, r0
--	mov 	r0, r1
--	dsb
--	smc	#0
--	ldmfd   sp!, {r2-r12, pc}
--ENDPROC(omap_smc1)
--
--ENTRY(omap_modify_auxcoreboot0)
--	stmfd   sp!, {r1-r12, lr}
--	ldr	r12, =0x104
--	dsb
--	smc	#0
--	ldmfd   sp!, {r1-r12, pc}
--ENDPROC(omap_modify_auxcoreboot0)
--
--ENTRY(omap_auxcoreboot_addr)
--	stmfd   sp!, {r2-r12, lr}
--	ldr	r12, =0x105
--	dsb
--	smc	#0
--	ldmfd   sp!, {r2-r12, pc}
--ENDPROC(omap_auxcoreboot_addr)
--
--ENTRY(omap_read_auxcoreboot0)
--	stmfd   sp!, {r2-r12, lr}
--	ldr	r12, =0x103
--	dsb
--	smc	#0
--	mov	r0, r0, lsr #9
--	ldmfd   sp!, {r2-r12, pc}
--ENDPROC(omap_read_auxcoreboot0)
-diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
-index 207a2ff..bc14f9f 100644
---- a/arch/arm/mach-omap2/omap_hwmod.c
-+++ b/arch/arm/mach-omap2/omap_hwmod.c
-@@ -136,8 +136,9 @@
- #include <linux/list.h>
- #include <linux/mutex.h>
- #include <linux/spinlock.h>
-+#include <linux/slab.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/cpu.h>
- #include "clockdomain.h"
- #include "powerdomain.h"
-@@ -149,6 +150,7 @@
- #include "cminst44xx.h"
- #include "prm2xxx_3xxx.h"
- #include "prm44xx.h"
-+#include "prm33xx.h"
- #include "prminst44xx.h"
- #include "mux.h"
- 
-@@ -381,6 +383,51 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
- }
- 
- /**
-+ * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
-+ * @oh: struct omap_hwmod *
-+ * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
-+ *
-+ * Set or clear the I/O pad wakeup flag in the mux entries for the
-+ * hwmod @oh.  This function changes the @oh->mux->pads_dynamic array
-+ * in memory.  If the hwmod is currently idled, and the new idle
-+ * values don't match the previous ones, this function will also
-+ * update the SCM PADCTRL registers.  Otherwise, if the hwmod is not
-+ * currently idled, this function won't touch the hardware: the new
-+ * mux settings are written to the SCM PADCTRL registers when the
-+ * hwmod is idled.  No return value.
-+ */
-+static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
-+{
-+	struct omap_device_pad *pad;
-+	bool change = false;
-+	u16 prev_idle;
-+	int j;
-+
-+	if (!oh->mux || !oh->mux->enabled)
-+		return;
-+
-+	for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
-+		pad = oh->mux->pads_dynamic[j];
-+
-+		if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
-+			continue;
-+
-+		prev_idle = pad->idle;
-+
-+		if (set_wake)
-+			pad->idle |= OMAP_WAKEUP_EN;
-+		else
-+			pad->idle &= ~OMAP_WAKEUP_EN;
-+
-+		if (prev_idle != pad->idle)
-+			change = true;
-+	}
-+
-+	if (change && oh->_state == _HWMOD_STATE_IDLE)
-+		omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
-+}
-+
-+/**
-  * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
-  * @oh: struct omap_hwmod *
-  *
-@@ -688,45 +735,83 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
-  */
- static void _enable_module(struct omap_hwmod *oh)
- {
--	/* The module mode does not exist prior OMAP4 */
--	if (cpu_is_omap24xx() || cpu_is_omap34xx())
-+	/* The module mode does not exist prior OMAP4 & AM33xx */
-+	if (!cpu_is_omap44xx() && !cpu_is_am33xx())
- 		return;
- 
- 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
- 		return;
- 
- 	pr_debug("omap_hwmod: %s: _enable_module: %d\n",
--		 oh->name, oh->prcm.omap4.modulemode);
-+			oh->name, oh->prcm.omap4.modulemode);
- 
- 	omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
--				   oh->clkdm->prcm_partition,
--				   oh->clkdm->cm_inst,
--				   oh->clkdm->clkdm_offs,
--				   oh->prcm.omap4.clkctrl_offs);
-+			oh->clkdm->prcm_partition,
-+			oh->clkdm->cm_inst,
-+			oh->clkdm->clkdm_offs,
-+			oh->prcm.omap4.clkctrl_offs);
-+}
-+
-+/**
-+ * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
-+ * @oh: struct omap_hwmod *
-+ *
-+ * Wait for a module @oh to enter slave idle.  Returns 0 if the module
-+ * does not have an IDLEST bit or if the module successfully enters
-+ * slave idle; otherwise, pass along the return value of the
-+ * appropriate *_cm*_wait_module_idle() function.
-+ */
-+static int _omap4_wait_target_disable(struct omap_hwmod *oh)
-+{
-+	if (!cpu_is_omap44xx() && !cpu_is_am33xx())
-+		return 0;
-+
-+	if (!oh)
-+		return -EINVAL;
-+
-+	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
-+		return 0;
-+
-+	if (oh->flags & HWMOD_NO_IDLEST)
-+		return 0;
-+
-+	return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
-+					     oh->clkdm->cm_inst,
-+					     oh->clkdm->clkdm_offs,
-+					     oh->prcm.omap4.clkctrl_offs);
- }
- 
- /**
-- * _disable_module - enable CLKCTRL modulemode on OMAP4
-+ * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
-  * @oh: struct omap_hwmod *
-  *
-  * Disable the PRCM module mode related to the hwmod @oh.
-- * No return value.
-+ * Return EINVAL if the modulemode is not supported and 0 in case of success.
-  */
--static void _disable_module(struct omap_hwmod *oh)
-+static int _omap4_disable_module(struct omap_hwmod *oh)
- {
--	/* The module mode does not exist prior OMAP4 */
--	if (cpu_is_omap24xx() || cpu_is_omap34xx())
--		return;
-+	int v;
-+
-+	/* The module mode does not exist prior OMAP4 & AM33xx */
-+	if (!cpu_is_omap44xx() && !cpu_is_am33xx())
-+		return -EINVAL;
- 
- 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
--		return;
-+		return -EINVAL;
- 
--	pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);
-+	pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
- 
- 	omap4_cminst_module_disable(oh->clkdm->prcm_partition,
--				    oh->clkdm->cm_inst,
--				    oh->clkdm->clkdm_offs,
--				    oh->prcm.omap4.clkctrl_offs);
-+			oh->clkdm->cm_inst,
-+			oh->clkdm->clkdm_offs,
-+			oh->prcm.omap4.clkctrl_offs);
-+
-+	v = _omap4_wait_target_disable(oh);
-+	if (v)
-+		pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
-+				oh->name);
-+
-+	return 0;
- }
- 
- /**
-@@ -1051,7 +1136,7 @@ static struct omap_hwmod *_lookup(const char *name)
-  */
- static int _init_clkdm(struct omap_hwmod *oh)
- {
--	if (cpu_is_omap24xx() || cpu_is_omap34xx())
-+	if (cpu_is_omap24xx() || (cpu_is_omap34xx() && !cpu_is_am33xx()))
- 		return 0;
- 
- 	if (!oh->clkdm_name) {
-@@ -1133,11 +1218,13 @@ static int _wait_target_ready(struct omap_hwmod *oh)
- 
- 	/* XXX check clock enable states */
- 
--	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
--		ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
--						 oh->prcm.omap2.idlest_reg_id,
--						 oh->prcm.omap2.idlest_idle_bit);
--	} else if (cpu_is_omap44xx()) {
-+	/*
-+	 * In order to use omap4 cminst code for am33xx family of devices,
-+	 * first check cpu_is_am33xx here.
-+	 *
-+	 * Note: cpu_is_omap34xx is true for am33xx device as well.
-+	 */
-+	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 		if (!oh->clkdm)
- 			return -EINVAL;
- 
-@@ -1145,6 +1232,11 @@ static int _wait_target_ready(struct omap_hwmod *oh)
- 						     oh->clkdm->cm_inst,
- 						     oh->clkdm->clkdm_offs,
- 						     oh->prcm.omap4.clkctrl_offs);
-+	} else if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-+			ret = omap2_cm_wait_module_ready(
-+						oh->prcm.omap2.module_offs,
-+						oh->prcm.omap2.idlest_reg_id,
-+						oh->prcm.omap2.idlest_idle_bit);
- 	} else {
- 		BUG();
- 	};
-@@ -1153,36 +1245,6 @@ static int _wait_target_ready(struct omap_hwmod *oh)
- }
- 
- /**
-- * _wait_target_disable - wait for a module to be disabled
-- * @oh: struct omap_hwmod *
-- *
-- * Wait for a module @oh to enter slave idle.  Returns 0 if the module
-- * does not have an IDLEST bit or if the module successfully enters
-- * slave idle; otherwise, pass along the return value of the
-- * appropriate *_cm*_wait_module_idle() function.
-- */
--static int _wait_target_disable(struct omap_hwmod *oh)
--{
--	/* TODO: For now just handle OMAP4+ */
--	if (cpu_is_omap24xx() || cpu_is_omap34xx())
--		return 0;
--
--	if (!oh)
--		return -EINVAL;
--
--	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
--		return 0;
--
--	if (oh->flags & HWMOD_NO_IDLEST)
--		return 0;
--
--	return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
--					     oh->clkdm->cm_inst,
--					     oh->clkdm->clkdm_offs,
--					     oh->prcm.omap4.clkctrl_offs);
--}
--
--/**
-  * _lookup_hardreset - fill register bit info for this hwmod/reset line
-  * @oh: struct omap_hwmod *
-  * @name: name of the reset line in the context of this hwmod
-@@ -1234,14 +1296,20 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
- 	if (IS_ERR_VALUE(ret))
- 		return ret;
- 
--	if (cpu_is_omap24xx() || cpu_is_omap34xx())
--		return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
--						  ohri.rst_shift);
--	else if (cpu_is_omap44xx())
-+	/*
-+	 * In order to use omap4 prm code for am33xx family of devices,
-+	 * first check cpu_is_am33xx here.
-+	 *
-+	 * Note: cpu_is_omap34xx is true for am33xx device as well.
-+	 */
-+	if (cpu_is_omap44xx() || cpu_is_am33xx())
- 		return omap4_prminst_assert_hardreset(ohri.rst_shift,
- 				  oh->clkdm->pwrdm.ptr->prcm_partition,
- 				  oh->clkdm->pwrdm.ptr->prcm_offs,
- 				  oh->prcm.omap4.rstctrl_offs);
-+	else if (cpu_is_omap24xx() || cpu_is_omap34xx())
-+		return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
-+						  ohri.rst_shift);
- 	else
- 		return -EINVAL;
- }
-@@ -1268,11 +1336,13 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
- 	if (IS_ERR_VALUE(ret))
- 		return ret;
- 
--	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
--		ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
--						   ohri.rst_shift,
--						   ohri.st_shift);
--	} else if (cpu_is_omap44xx()) {
-+	/*
-+	 * In order to use omap4 prm code for am33xx family of devices,
-+	 * first check cpu_is_am33xx here.
-+	 *
-+	 * Note: cpu_is_omap34xx is true for am33xx device as well.
-+	 */
-+	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 		if (ohri.st_shift)
- 			pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
- 			       oh->name, name);
-@@ -1280,6 +1350,10 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
- 				  oh->clkdm->pwrdm.ptr->prcm_partition,
- 				  oh->clkdm->pwrdm.ptr->prcm_offs,
- 				  oh->prcm.omap4.rstctrl_offs);
-+	} else if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-+		ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
-+						   ohri.rst_shift,
-+						   ohri.st_shift);
- 	} else {
- 		return -EINVAL;
- 	}
-@@ -1310,14 +1384,20 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
- 	if (IS_ERR_VALUE(ret))
- 		return ret;
- 
--	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
--		return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
--						       ohri.st_shift);
--	} else if (cpu_is_omap44xx()) {
-+	/*
-+	 * In order to use omap4 prm code for am33xx family of devices,
-+	 * first check cpu_is_am33xx here.
-+	 *
-+	 * Note: cpu_is_omap34xx is true for am33xx device as well.
-+	 */
-+	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 		return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
- 				  oh->clkdm->pwrdm.ptr->prcm_partition,
- 				  oh->clkdm->pwrdm.ptr->prcm_offs,
- 				  oh->prcm.omap4.rstctrl_offs);
-+	} else if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-+		return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
-+						       ohri.st_shift);
- 	} else {
- 		return -EINVAL;
- 	}
-@@ -1441,6 +1521,25 @@ static int _enable(struct omap_hwmod *oh)
- 
- 	pr_debug("omap_hwmod: %s: enabling\n", oh->name);
- 
-+	/*
-+	 * hwmods with HWMOD_INIT_NO_IDLE flag set are left
-+	 * in enabled state at init.
-+	 * Now that someone is really trying to enable them,
-+	 * just ensure that the hwmod mux is set.
-+	 */
-+	if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
-+		/*
-+		 * If the caller has mux data populated, do the mux'ing
-+		 * which wouldn't have been done as part of the _enable()
-+		 * done during setup.
-+		 */
-+		if (oh->mux)
-+			omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
-+
-+		oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
-+		return 0;
-+	}
-+
- 	if (oh->_state != _HWMOD_STATE_INITIALIZED &&
- 	    oh->_state != _HWMOD_STATE_IDLE &&
- 	    oh->_state != _HWMOD_STATE_DISABLED) {
-@@ -1524,8 +1623,6 @@ static int _enable(struct omap_hwmod *oh)
-  */
- static int _idle(struct omap_hwmod *oh)
- {
--	int ret;
--
- 	pr_debug("omap_hwmod: %s: idling\n", oh->name);
- 
- 	if (oh->_state != _HWMOD_STATE_ENABLED) {
-@@ -1537,11 +1634,9 @@ static int _idle(struct omap_hwmod *oh)
- 	if (oh->class->sysc)
- 		_idle_sysc(oh);
- 	_del_initiator_dep(oh, mpu_oh);
--	_disable_module(oh);
--	ret = _wait_target_disable(oh);
--	if (ret)
--		pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
--			oh->name);
-+
-+	_omap4_disable_module(oh);
-+
- 	/*
- 	 * The module must be in idle mode before disabling any parents
- 	 * clocks. Otherwise, the parent clock might be disabled before
-@@ -1642,11 +1737,7 @@ static int _shutdown(struct omap_hwmod *oh)
- 	if (oh->_state == _HWMOD_STATE_ENABLED) {
- 		_del_initiator_dep(oh, mpu_oh);
- 		/* XXX what about the other system initiators here? dma, dsp */
--		_disable_module(oh);
--		ret = _wait_target_disable(oh);
--		if (ret)
--			pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
--				oh->name);
-+		_omap4_disable_module(oh);
- 		_disable_clocks(oh);
- 		if (oh->clkdm)
- 			clkdm_hwmod_disable(oh->clkdm, oh);
-@@ -1744,8 +1835,10 @@ static int _setup(struct omap_hwmod *oh, void *data)
- 	 * it should be set by the core code as a runtime flag during startup
- 	 */
- 	if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
--	    (postsetup_state == _HWMOD_STATE_IDLE))
-+	    (postsetup_state == _HWMOD_STATE_IDLE)) {
-+		oh->_int_flags |= _HWMOD_SKIP_ENABLE;
- 		postsetup_state = _HWMOD_STATE_ENABLED;
-+	}
- 
- 	if (postsetup_state == _HWMOD_STATE_IDLE)
- 		_idle(oh);
-@@ -1857,6 +1950,35 @@ error:
- }
- 
- /**
-+ * omap_hwmod_set_master_standbymode - set the hwmod's OCP master standbymode
-+ * @oh: struct omap_hwmod *
-+ * @standbymode: MSTANDBY field bits (shifted to bit 0)
-+ *
-+ * Sets the IP block's OCP master staandby mode in hardware, and updates our
-+ * local copy.  Intended to be used by drivers that have some erratum
-+ * that requires direct manipulation of the MSTANDBY bits.  Returns
-+ * -EINVAL if @oh is null, or passes along the return value from
-+ * _set_master_standbymode().
-+ *
-+ */
-+int omap_hwmod_set_master_standbymode(struct omap_hwmod *oh, u8 standbymode)
-+{
-+	u32 v;
-+	int retval = 0;
-+
-+	if (!oh)
-+		return -EINVAL;
-+
-+	v = oh->_sysc_cache;
-+
-+	retval = _set_master_standbymode(oh, standbymode, &v);
-+	if (!retval)
-+		_write_sysconfig(v, oh);
-+
-+	return retval;
-+}
-+
-+/**
-  * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
-  * @oh: struct omap_hwmod *
-  * @idlemode: SIDLEMODE field bits (shifted to bit 0)
-@@ -2416,6 +2538,7 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
- 	v = oh->_sysc_cache;
- 	_enable_wakeup(oh, &v);
- 	_write_sysconfig(v, oh);
-+	_set_idle_ioring_wakeup(oh, true);
- 	spin_unlock_irqrestore(&oh->_lock, flags);
- 
- 	return 0;
-@@ -2446,6 +2569,7 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
- 	v = oh->_sysc_cache;
- 	_disable_wakeup(oh, &v);
- 	_write_sysconfig(v, oh);
-+	_set_idle_ioring_wakeup(oh, false);
- 	spin_unlock_irqrestore(&oh->_lock, flags);
- 
- 	return 0;
-@@ -2662,3 +2786,57 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
- 
- 	return 0;
- }
-+
-+/**
-+ * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ
-+ * @oh: struct omap_hwmod * containing hwmod mux entries
-+ * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup
-+ * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup
-+ *
-+ * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux
-+ * entry number @pad_idx for the hwmod @oh, trigger the interrupt
-+ * service routine for the hwmod's mpu_irqs array index @irq_idx.  If
-+ * this function is not called for a given pad_idx, then the ISR
-+ * associated with @oh's first MPU IRQ will be triggered when an I/O
-+ * pad wakeup occurs on that pad.  Note that @pad_idx is the index of
-+ * the _dynamic or wakeup_ entry: if there are other entries not
-+ * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these
-+ * entries are NOT COUNTED in the dynamic pad index.  This function
-+ * must be called separately for each pad that requires its interrupt
-+ * to be re-routed this way.  Returns -EINVAL if there is an argument
-+ * problem or if @oh does not have hwmod mux entries or MPU IRQs;
-+ * returns -ENOMEM if memory cannot be allocated; or 0 upon success.
-+ *
-+ * XXX This function interface is fragile.  Rather than using array
-+ * indexes, which are subject to unpredictable change, it should be
-+ * using hwmod IRQ names, and some other stable key for the hwmod mux
-+ * pad records.
-+ */
-+int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
-+{
-+	int nr_irqs;
-+
-+	might_sleep();
-+
-+	if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 ||
-+	    pad_idx >= oh->mux->nr_pads_dynamic)
-+		return -EINVAL;
-+
-+	/* Check the number of available mpu_irqs */
-+	for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++)
-+		;
-+
-+	if (irq_idx >= nr_irqs)
-+		return -EINVAL;
-+
-+	if (!oh->mux->irqs) {
-+		/* XXX What frees this? */
-+		oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic,
-+			GFP_KERNEL);
-+		if (!oh->mux->irqs)
-+			return -ENOMEM;
-+	}
-+	oh->mux->irqs[pad_idx] = irq_idx;
-+
-+	return 0;
-+}
-diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
-new file mode 100644
-index 0000000..9d3c9a5
---- /dev/null
-+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
-@@ -0,0 +1,3412 @@
-+/*
-+ * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
-+ *
-+ * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This file is automatically generated from the AM33XX hardware databases.
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <plat/omap_hwmod.h>
-+#include <plat/cpu.h>
-+#include <plat/gpio.h>
-+#include <plat/dma.h>
-+#include <plat/mmc.h>
-+#include <plat/mcspi.h>
-+#include <plat/i2c.h>
-+
-+#include "omap_hwmod_common_data.h"
-+#include "control.h"
-+#include "cm33xx.h"
-+#include "prm33xx.h"
-+
-+/* Backward references (IPs with Bus Master capability) */
-+static struct omap_hwmod am33xx_mpu_hwmod;
-+static struct omap_hwmod am33xx_l3_main_hwmod;
-+static struct omap_hwmod am33xx_l3slow_hwmod;
-+static struct omap_hwmod am33xx_l4wkup_hwmod;
-+static struct omap_hwmod am33xx_l4per_hwmod;
-+static struct omap_hwmod am33xx_uart1_hwmod;
-+static struct omap_hwmod am33xx_uart2_hwmod;
-+static struct omap_hwmod am33xx_uart3_hwmod;
-+static struct omap_hwmod am33xx_uart4_hwmod;
-+static struct omap_hwmod am33xx_uart5_hwmod;
-+static struct omap_hwmod am33xx_uart6_hwmod;
-+static struct omap_hwmod am33xx_timer0_hwmod;
-+static struct omap_hwmod am33xx_timer1_hwmod;
-+static struct omap_hwmod am33xx_timer2_hwmod;
-+static struct omap_hwmod am33xx_timer3_hwmod;
-+static struct omap_hwmod am33xx_timer4_hwmod;
-+static struct omap_hwmod am33xx_timer5_hwmod;
-+static struct omap_hwmod am33xx_timer6_hwmod;
-+static struct omap_hwmod am33xx_timer7_hwmod;
-+static struct omap_hwmod am33xx_wd_timer1_hwmod;
-+static struct omap_hwmod am33xx_tpcc_hwmod;
-+static struct omap_hwmod am33xx_tptc0_hwmod;
-+static struct omap_hwmod am33xx_tptc1_hwmod;
-+static struct omap_hwmod am33xx_tptc2_hwmod;
-+static struct omap_hwmod am33xx_dcan0_hwmod;
-+static struct omap_hwmod am33xx_dcan1_hwmod;
-+static struct omap_hwmod am33xx_gpio0_hwmod;
-+static struct omap_hwmod am33xx_gpio1_hwmod;
-+static struct omap_hwmod am33xx_gpio2_hwmod;
-+static struct omap_hwmod am33xx_gpio3_hwmod;
-+static struct omap_hwmod am33xx_i2c1_hwmod;
-+static struct omap_hwmod am33xx_i2c2_hwmod;
-+static struct omap_hwmod am33xx_i2c3_hwmod;
-+static struct omap_hwmod am33xx_usbss_hwmod;
-+static struct omap_hwmod am33xx_mmc0_hwmod;
-+static struct omap_hwmod am33xx_mmc1_hwmod;
-+static struct omap_hwmod am33xx_mmc2_hwmod;
-+static struct omap_hwmod am33xx_spi0_hwmod;
-+static struct omap_hwmod am33xx_spi1_hwmod;
-+static struct omap_hwmod am33xx_elm_hwmod;
-+static struct omap_hwmod am33xx_adc_tsc_hwmod;
-+static struct omap_hwmod am33xx_mcasp0_hwmod;
-+static struct omap_hwmod am33xx_mcasp1_hwmod;
-+static struct omap_hwmod am33xx_ehrpwm0_hwmod;
-+static struct omap_hwmod am33xx_ehrpwm1_hwmod;
-+static struct omap_hwmod am33xx_ehrpwm2_hwmod;
-+static struct omap_hwmod am33xx_ecap0_hwmod;
-+static struct omap_hwmod am33xx_ecap1_hwmod;
-+static struct omap_hwmod am33xx_ecap2_hwmod;
-+static struct omap_hwmod am33xx_gpmc_hwmod;
-+static struct omap_hwmod am33xx_lcdc_hwmod;
-+static struct omap_hwmod am33xx_mailbox_hwmod;
-+static struct omap_hwmod am33xx_cpgmac0_hwmod;
-+
-+/*
-+ * Interconnects hwmod structures
-+ * hwmods that compose the global AM33XX OCP interconnect
-+ */
-+
-+/* MPU -> L3_SLOW Peripheral interface */
-+static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
-+	.master 	= &am33xx_mpu_hwmod,
-+	.slave		= &am33xx_l3slow_hwmod,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+/* L3 SLOW -> L4_PER Peripheral interface */
-+static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
-+	.master 	= &am33xx_l3slow_hwmod,
-+	.slave		= &am33xx_l4per_hwmod,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+/* L3 SLOW -> L4_WKUP Peripheral interface */
-+static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
-+	.master 	= &am33xx_l3slow_hwmod,
-+	.slave		= &am33xx_l4wkup_hwmod,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+/* Master interfaces on the L4_WKUP interconnect */
-+static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
-+	&am33xx_l3_slow__l4_per,
-+	&am33xx_l3_slow__l4_wkup,
-+};
-+
-+/* Slave interfaces on the L3_SLOW interconnect */
-+static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
-+	&am33xx_mpu__l3_slow,
-+};
-+
-+static struct omap_hwmod am33xx_l3slow_hwmod = {
-+	.name		= "l3_slow",
-+	.class		= &l3_hwmod_class,
-+	.clkdm_name	= "l3s_clkdm",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.masters	= am33xx_l3_slow_masters,
-+	.masters_cnt	= ARRAY_SIZE(am33xx_l3_slow_masters),
-+	.slaves		= am33xx_l3_slow_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_l3_slow_slaves),
-+};
-+
-+/* L4 PER -> DCAN0 */
-+static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
-+	{
-+		.pa_start	= 0x481CC000,
-+		.pa_end		= 0x481CC000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_dcan0_hwmod,
-+	.clk		= "dcan0_ick",
-+	.addr		= am33xx_dcan0_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+/* L4 PER -> DCAN1 */
-+static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
-+	{
-+		.pa_start	= 0x481D0000,
-+		.pa_end		= 0x481D0000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_dcan1_hwmod,
-+	.clk		= "dcan1_ick",
-+	.addr		= am33xx_dcan1_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+/* L4 PER -> GPIO2 */
-+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
-+	{
-+		.pa_start	= 0x4804C000,
-+		.pa_end		= 0x4804C000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_gpio1_hwmod,
-+	.clk		= "l4ls_gclk",
-+	.addr		= am33xx_gpio1_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+/* L4 PER -> GPIO3 */
-+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
-+	{
-+		.pa_start	= 0x481AC000,
-+		.pa_end		= 0x481AC000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_gpio2_hwmod,
-+	.clk		= "l4ls_gclk",
-+	.addr		= am33xx_gpio2_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+/* L4 PER -> GPIO4 */
-+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
-+	{
-+		.pa_start	= 0x481AE000,
-+		.pa_end		= 0x481AE000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_gpio3_hwmod,
-+	.clk		= "l4ls_gclk",
-+	.addr		= am33xx_gpio3_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+/* Master interfaces on the L4_PER interconnect */
-+static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
-+	&am33xx_l4_per__dcan0,
-+	&am33xx_l4_per__dcan1,
-+	&am33xx_l4_per__gpio1,
-+	&am33xx_l4_per__gpio2,
-+	&am33xx_l4_per__gpio3,
-+};
-+
-+/* Slave interfaces on the L4_PER interconnect */
-+static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
-+	&am33xx_l3_slow__l4_per,
-+};
-+
-+static struct omap_hwmod am33xx_l4per_hwmod = {
-+	.name		= "l4_per",
-+	.class		= &l4_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.masters	= am33xx_l4_per_masters,
-+	.masters_cnt	= ARRAY_SIZE(am33xx_l4_per_masters),
-+	.slaves		= am33xx_l4_per_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_per_slaves),
-+};
-+
-+/* L4 WKUP -> I2C1 */
-+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
-+	{
-+		.pa_start	= 0x44E0B000,
-+		.pa_end		= 0x44E0B000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
-+	.master		= &am33xx_l4wkup_hwmod,
-+	.slave		= &am33xx_i2c1_hwmod,
-+	.addr		= am33xx_i2c1_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+/* L4 WKUP -> GPIO1 */
-+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
-+	{
-+		.pa_start	= 0x44E07000,
-+		.pa_end		= 0x44E07000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
-+	.master		= &am33xx_l4wkup_hwmod,
-+	.slave		= &am33xx_gpio0_hwmod,
-+	.clk		= "l4ls_gclk",
-+	.addr		= am33xx_gpio0_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+/* Master interfaces on the L4_WKUP interconnect */
-+static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
-+	&am33xx_l4_wkup__gpio0,
-+};
-+/* Slave interfaces on the L4_WKUP interconnect */
-+static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
-+	&am33xx_l3_slow__l4_wkup,
-+};
-+
-+static struct omap_hwmod am33xx_l4wkup_hwmod = {
-+	.name		= "l4_wkup",
-+	.class		= &l4_hwmod_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.masters	= am33xx_l4_wkup_masters,
-+	.masters_cnt	= ARRAY_SIZE(am33xx_l4_wkup_masters),
-+	.slaves		= am33xx_l4_wkup_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_wkup_slaves),
-+};
-+
-+/* adc_tsc */
-+static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
-+	.rev_offs	= 0x00,
-+	.sysc_offs	= 0x10,
-+	.sysc_flags	= SYSC_HAS_SIDLEMODE,
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			SIDLE_SMART_WKUP),
-+	.sysc_fields	= &omap_hwmod_sysc_type2,
-+};
-+
-+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
-+	.name		= "adc_tsc",
-+	.sysc		= &am33xx_adc_tsc_sysc,
-+};
-+
-+/* L4 WKUP -> ADC_TSC */
-+static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
-+	{
-+		.pa_start	= 0x44E0D000,
-+		.pa_end		= 0x44E0D000 + SZ_8K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
-+	.master		= &am33xx_l4wkup_hwmod,
-+	.slave		= &am33xx_adc_tsc_hwmod,
-+	.clk		= "adc_tsc_ick",
-+	.addr		= am33xx_adc_tsc_addrs,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
-+	&am33xx_l4_wkup_adc_tsc,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
-+	{ .irq = 16 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
-+	.name		= "adc_tsc",
-+	.class		= &am33xx_adc_tsc_hwmod_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.mpu_irqs	= am33xx_adc_tsc_irqs,
-+	.main_clk	= "adc_tsc_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_adc_tsc_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_adc_tsc_slaves),
-+};
-+
-+/* 'aes' class */
-+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
-+	.name		= "aes",
-+};
-+
-+/* aes0 */
-+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
-+	{ .irq = 102 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_aes0_hwmod = {
-+	.name		= "aes0",
-+	.class		= &am33xx_aes_hwmod_class,
-+	.clkdm_name	= "l3_clkdm",
-+	.mpu_irqs	= am33xx_aes0_irqs,
-+	.main_clk	= "aes0_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* cefuse */
-+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
-+	.name		= "cefuse",
-+};
-+
-+static struct omap_hwmod am33xx_cefuse_hwmod = {
-+	.name		= "cefuse",
-+	.class		= &am33xx_cefuse_hwmod_class,
-+	.clkdm_name	= "l4_cefuse_clkdm",
-+	.main_clk	= "cefuse_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* clkdiv32k */
-+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
-+	.name		= "clkdiv32k",
-+};
-+
-+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
-+	.name		= "clkdiv32k",
-+	.class		= &am33xx_clkdiv32k_hwmod_class,
-+	.clkdm_name	= "clk_24mhz_clkdm",
-+	.main_clk	= "clkdiv32k_ick",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+};
-+
-+/* control */
-+static struct omap_hwmod_class am33xx_control_hwmod_class = {
-+	.name		= "control",
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
-+	{ .irq = 8 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_control_hwmod = {
-+	.name		= "control",
-+	.class		= &am33xx_control_hwmod_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.mpu_irqs	= am33xx_control_irqs,
-+	.main_clk	= "control_fck",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* cpgmac0 */
-+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
-+	.rev_offs	= 0x0,
-+	.sysc_offs	= 0x8,
-+	.syss_offs	= 0x4,
-+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
-+			SYSS_HAS_RESET_STATUS),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
-+			MSTANDBY_NO),
-+	.sysc_fields	= &omap_hwmod_sysc_type3,
-+};
-+
-+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
-+	.name		= "cpgmac0",
-+	.sysc		= &am33xx_cpgmac_sysc,
-+};
-+
-+struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
-+	{
-+		.pa_start	= 0x4A101200,
-+		.pa_end		= 0x4A101200 + SZ_8K - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
-+	.master		= &am33xx_l3_main_hwmod,
-+	.slave		= &am33xx_cpgmac0_hwmod,
-+	.addr		= am33xx_cpgmac0_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
-+	&am33xx_l3_main__cpgmac0,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
-+	{ .name = "c0_rx_thresh_pend", .irq = 40 },
-+	{ .name = "c0_rx_pend", .irq = 41 },
-+	{ .name = "c0_tx_pend", .irq = 42 },
-+	{ .name = "c0_misc_pend", .irq = 43 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
-+	.name		= "cpgmac0",
-+	.class		= &am33xx_cpgmac0_hwmod_class,
-+	.clkdm_name	= "cpsw_125mhz_clkdm",
-+	.mpu_irqs	= am33xx_cpgmac0_irqs,
-+	.main_clk	= "cpgmac0_ick",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_cpgmac0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_cpgmac0_slaves),
-+	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
-+				HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+};
-+
-+/* 'dcan' class */
-+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
-+	.name		= "d_can",
-+};
-+
-+/* dcan0 slave ports */
-+static struct omap_hwmod_ocp_if *am33xx_dcan0_slaves[] = {
-+	&am33xx_l4_per__dcan0,
-+};
-+
-+/* dcan0 */
-+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
-+	{ .name = "d_can_ms", .irq = 52 },
-+	{ .name = "d_can_mo", .irq = 53 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_dcan0_hwmod = {
-+	.name		= "d_can0",
-+	.class		= &am33xx_dcan_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_dcan0_irqs,
-+	.main_clk	= "dcan0_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_dcan0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_dcan0_slaves),
-+};
-+
-+/* dcan1 slave ports */
-+static struct omap_hwmod_ocp_if *am33xx_dcan1_slaves[] = {
-+	&am33xx_l4_per__dcan1,
-+};
-+
-+/* dcan1 */
-+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
-+	{ .name = "d_can_ms", .irq = 55 },
-+	{ .name = "d_can_mo", .irq = 56 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_dcan1_hwmod = {
-+	.name		= "d_can1",
-+	.class		= &am33xx_dcan_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_dcan1_irqs,
-+	.main_clk	= "dcan1_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_dcan1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_dcan1_slaves),
-+};
-+
-+/* debugss */
-+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
-+	.name		= "debugss",
-+};
-+
-+static struct omap_hwmod am33xx_debugss_hwmod = {
-+	.name		= "debugss",
-+	.class		= &am33xx_debugss_hwmod_class,
-+	.clkdm_name	= "l3_aon_clkdm",
-+	.main_clk	= "debugss_ick",
-+#ifdef CONFIG_DEBUG_JTAG_ENABLE
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+#endif
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* elm */
-+static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.syss_offs	= 0x0014,
-+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-+			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
-+			SYSS_HAS_RESET_STATUS),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
-+	.name		= "elm",
-+	.sysc		= &am33xx_elm_sysc,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
-+	{ .irq = 4 },
-+	{ .irq = -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
-+	{
-+		.pa_start	= 0x48080000,
-+		.pa_end		= 0x48080000 + SZ_8K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_elm_hwmod,
-+	.addr		= am33xx_elm_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
-+	&am33xx_l4_core__elm,
-+};
-+
-+static struct omap_hwmod am33xx_elm_hwmod = {
-+	.name		= "elm",
-+	.class		= &am33xx_elm_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_elm_irqs,
-+	.main_clk	= "elm_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_elm_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_elm_slaves),
-+};
-+
-+/* emif_fw */
-+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
-+	.name		= "emif_fw",
-+};
-+
-+static struct omap_hwmod am33xx_emif_fw_hwmod = {
-+	.name		= "emif_fw",
-+	.class		= &am33xx_emif_fw_hwmod_class,
-+	.clkdm_name	= "l4fw_clkdm",
-+	.main_clk	= "emif_fw_fck",
-+	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* 'epwmss' class */
-+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
-+	.rev_offs	= 0x0,
-+	.sysc_offs	= 0x4,
-+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-+			MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
-+	.sysc_fields	= &omap_hwmod_sysc_type2,
-+};
-+
-+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
-+	.name		= "epwmss",
-+	.sysc		= &am33xx_epwmss_sysc,
-+};
-+
-+/* ehrpwm0 */
-+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
-+	{ .irq		= 86 },
-+	{ .irq		= 58 },
-+	{ .irq		= -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
-+/*
-+ * Splitting the resources to handle access of PWMSS config space and module
-+ * specific part independently
-+ */
-+	{
-+		.pa_start	= 0x48300000,
-+		.pa_end		= 0x48300000 + SZ_16 - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
-+	},
-+	{
-+		.pa_start	= 0x48300000 + SZ_512,
-+		.pa_end		= 0x48300000 + SZ_512 + SZ_256 - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm0 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_ehrpwm0_hwmod,
-+	.addr		= am33xx_ehrpwm0_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_ehrpwm0_slaves[] = {
-+	&am33xx_l4_core__ehrpwm0,
-+};
-+
-+static struct omap_hwmod_opt_clk ehrpwm0_opt_clks[] = {
-+	{ .role = "tbclk", .clk = "ehrpwm0_tbclk" },
-+};
-+
-+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
-+	.name		= "ehrpwm.0",
-+	.mpu_irqs	= am33xx_ehrpwm0_irqs,
-+	.class		= &am33xx_epwmss_hwmod_class,
-+	.main_clk	= "epwmss0_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_ehrpwm0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_ehrpwm0_slaves),
-+	.opt_clks	= ehrpwm0_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(ehrpwm0_opt_clks),
-+};
-+
-+/* ehrpwm1 */
-+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
-+	{ .irq		= 87 },
-+	{ .irq		= 59 },
-+	{ .irq		= -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
-+/*
-+ * Splitting the resources to handle access of PWMSS config space and module
-+ * specific part independently
-+ */
-+	{
-+		.pa_start	= 0x48302000,
-+		.pa_end		= 0x48302000 + SZ_16 - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
-+	},
-+	{
-+		.pa_start	= 0x48302000 + SZ_512,
-+		.pa_end		= 0x48302000 + SZ_512 + SZ_256 - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm1 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_ehrpwm1_hwmod,
-+	.addr		= am33xx_ehrpwm1_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_ehrpwm1_slaves[] = {
-+	&am33xx_l4_core__ehrpwm1,
-+};
-+
-+static struct omap_hwmod_opt_clk ehrpwm1_opt_clks[] = {
-+	{ .role = "tbclk", .clk = "ehrpwm1_tbclk" },
-+};
-+
-+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
-+	.name		= "ehrpwm.1",
-+	.mpu_irqs	= am33xx_ehrpwm1_irqs,
-+	.class		= &am33xx_epwmss_hwmod_class,
-+	.main_clk	= "epwmss1_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_ehrpwm1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_ehrpwm1_slaves),
-+	.opt_clks	= ehrpwm1_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(ehrpwm1_opt_clks),
-+};
-+
-+/* ehrpwm2 */
-+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
-+	{ .irq		= 39 },
-+	{ .irq		= 60 },
-+	{ .irq		= -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
-+/*
-+ * Splitting the resources to handle access of PWMSS config space and module
-+ * specific part independently
-+ */
-+	{
-+		.pa_start	= 0x48304000,
-+		.pa_end		= 0x48304000 + SZ_16 - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
-+	},
-+	{
-+		.pa_start	= 0x48304000 + SZ_512,
-+		.pa_end		= 0x48304000 + SZ_512 + SZ_256 - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm2 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_ehrpwm2_hwmod,
-+	.addr		= am33xx_ehrpwm2_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_ehrpwm2_slaves[] = {
-+	&am33xx_l4_core__ehrpwm2,
-+};
-+
-+static struct omap_hwmod_opt_clk ehrpwm2_opt_clks[] = {
-+	{ .role = "tbclk", .clk = "ehrpwm2_tbclk" },
-+};
-+
-+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
-+	.name		= "ehrpwm.2",
-+	.mpu_irqs	= am33xx_ehrpwm2_irqs,
-+	.class		= &am33xx_epwmss_hwmod_class,
-+	.main_clk	= "epwmss2_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_ehrpwm2_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_ehrpwm2_slaves),
-+	.opt_clks	= ehrpwm2_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(ehrpwm2_opt_clks),
-+};
-+
-+/* ecap0 */
-+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
-+	{ .irq		= 31 },
-+	{ .irq		= -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
-+/*
-+ * Splitting the resources to handle access of PWMSS config space and module
-+ * specific part independently
-+ */
-+	{
-+		.pa_start	= 0x48300000,
-+		.pa_end		= 0x48300000 + SZ_16 - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
-+	},
-+	{
-+		.pa_start	= 0x48300000 + SZ_256,
-+		.pa_end		= 0x48300000 + SZ_256 + SZ_256 - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l4_core__ecap0 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_ecap0_hwmod,
-+	.addr		= am33xx_ecap0_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_ecap0_slaves[] = {
-+	&am33xx_l4_core__ecap0,
-+};
-+
-+static struct omap_hwmod am33xx_ecap0_hwmod = {
-+	.name		= "ecap.0",
-+	.mpu_irqs	= am33xx_ecap0_irqs,
-+	.class		= &am33xx_epwmss_hwmod_class,
-+	.main_clk	= "epwmss0_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_ecap0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_ecap0_slaves),
-+};
-+
-+/* ecap1 */
-+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
-+	{ .irq		= 47 },
-+	{ .irq		= -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
-+/*
-+ * Splitting the resources to handle access of PWMSS config space and module
-+ * specific part independently
-+ */
-+	{
-+		.pa_start	= 0x48302000,
-+		.pa_end		= 0x48302000 + SZ_16 - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
-+	},
-+	{
-+		.pa_start	= 0x48302000 + SZ_256,
-+		.pa_end		= 0x48302000 + SZ_256 + SZ_256 - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l4_core__ecap1 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_ecap1_hwmod,
-+	.addr		= am33xx_ecap1_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_ecap1_slaves[] = {
-+	&am33xx_l4_core__ecap1,
-+};
-+
-+static struct omap_hwmod am33xx_ecap1_hwmod = {
-+	.name		= "ecap.1",
-+	.mpu_irqs	= am33xx_ecap1_irqs,
-+	.class		= &am33xx_epwmss_hwmod_class,
-+	.main_clk	= "epwmss1_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_ecap1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_ecap1_slaves),
-+};
-+
-+/* ecap2 */
-+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
-+	{ .irq		= 61 },
-+	{ .irq		= -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
-+/*
-+ * Splitting the resources to handle access of PWMSS config space and module
-+ * specific part independently
-+ */
-+	{
-+		.pa_start	= 0x48304000,
-+		.pa_end		= 0x48304000 + SZ_16 - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
-+	},
-+	{
-+		.pa_start	= 0x48304000 + SZ_256,
-+		.pa_end		= 0x48304000 + SZ_256 + SZ_256 - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l4_core__ecap2 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_ecap2_hwmod,
-+	.addr		= am33xx_ecap2_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_ecap2_slaves[] = {
-+	&am33xx_l4_core__ecap2,
-+};
-+
-+static struct omap_hwmod am33xx_ecap2_hwmod = {
-+	.name		= "ecap.2",
-+	.mpu_irqs	= am33xx_ecap2_irqs,
-+	.class		= &am33xx_epwmss_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.main_clk	= "epwmss2_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_ecap2_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_ecap2_slaves),
-+};
-+
-+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.syss_offs	= 0x0114,
-+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
-+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-+			   SYSS_HAS_RESET_STATUS),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			SIDLE_SMART_WKUP),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+/* 'gpio' class */
-+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
-+	.name		= "gpio",
-+	.sysc		= &am33xx_gpio_sysc,
-+	.rev		= 2,
-+};
-+
-+static struct omap_gpio_dev_attr gpio_dev_attr = {
-+	.bank_width	= 32,
-+	.dbck_flag	= true,
-+};
-+
-+/* gpio0 */
-+static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
-+	&am33xx_l4_wkup__gpio0,
-+};
-+
-+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
-+	{ .role = "dbclk", .clk = "gpio0_dbclk" },
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
-+	{ .irq = 96 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_gpio0_hwmod = {
-+	.name		= "gpio1",
-+	.class		= &am33xx_gpio_hwmod_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.mpu_irqs	= am33xx_gpio0_irqs,
-+	.main_clk	= "gpio0_ick",
-+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.opt_clks	= gpio0_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(gpio0_opt_clks),
-+	.dev_attr	= &gpio_dev_attr,
-+	.slaves		= am33xx_gpio0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio0_slaves),
-+};
-+
-+/* gpio1 */
-+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
-+	{ .irq = 98 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
-+	&am33xx_l4_per__gpio1,
-+};
-+
-+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
-+	{ .role = "dbclk", .clk = "gpio1_dbclk" },
-+};
-+
-+static struct omap_hwmod am33xx_gpio1_hwmod = {
-+	.name		= "gpio2",
-+	.class		= &am33xx_gpio_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_gpio1_irqs,
-+	.main_clk	= "gpio1_ick",
-+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.opt_clks	= gpio1_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
-+	.dev_attr	= &gpio_dev_attr,
-+	.slaves		= am33xx_gpio1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio1_slaves),
-+};
-+
-+/* gpio2 */
-+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
-+	{ .irq = 32 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
-+	&am33xx_l4_per__gpio2,
-+};
-+
-+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
-+	{ .role = "dbclk", .clk = "gpio2_dbclk" },
-+};
-+
-+static struct omap_hwmod am33xx_gpio2_hwmod = {
-+	.name		= "gpio3",
-+	.class		= &am33xx_gpio_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_gpio2_irqs,
-+	.main_clk	= "gpio2_ick",
-+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.opt_clks	= gpio2_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
-+	.dev_attr	= &gpio_dev_attr,
-+	.slaves		= am33xx_gpio2_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio2_slaves),
-+};
-+
-+/* gpio3 */
-+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
-+	{ .irq = 62 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
-+	&am33xx_l4_per__gpio3,
-+};
-+
-+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
-+	{ .role = "dbclk", .clk = "gpio3_dbclk" },
-+};
-+
-+static struct omap_hwmod am33xx_gpio3_hwmod = {
-+	.name		= "gpio4",
-+	.class		= &am33xx_gpio_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_gpio3_irqs,
-+	.main_clk	= "gpio3_ick",
-+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.opt_clks	= gpio3_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
-+	.dev_attr	= &gpio_dev_attr,
-+	.slaves		= am33xx_gpio3_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio3_slaves),
-+};
-+
-+/* gpmc */
-+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
-+	.rev_offs	= 0x0,
-+	.sysc_offs	= 0x10,
-+	.syss_offs	= 0x14,
-+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
-+			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
-+	.name		= "gpmc",
-+	.sysc		= &gpmc_sysc,
-+};
-+
-+struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
-+	{
-+		.pa_start	= 0x50000000,
-+		.pa_end		= 0x50000000 + SZ_8K - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
-+	.master		= &am33xx_l3_main_hwmod,
-+	.slave		= &am33xx_gpmc_hwmod,
-+	.addr		= am33xx_gpmc_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
-+	&am33xx_l3_main__gpmc,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
-+	{ .irq = 100 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_gpmc_hwmod = {
-+	.name		= "gpmc",
-+	.class		= &am33xx_gpmc_hwmod_class,
-+	.clkdm_name	= "l3s_clkdm",
-+	.mpu_irqs	= am33xx_gpmc_irqs,
-+	.main_clk	= "gpmc_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_gpmc_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_gpmc_slaves),
-+	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
-+				HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+};
-+
-+/* 'i2c' class */
-+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
-+	.sysc_offs	= 0x0010,
-+	.syss_offs	= 0x0090,
-+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
-+			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-+			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			SIDLE_SMART_WKUP),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_i2c_dev_attr i2c_dev_attr = {
-+	.flags		= OMAP_I2C_FLAG_BUS_SHIFT_NONE |
-+					OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
-+};
-+
-+static struct omap_hwmod_class i2c_class = {
-+	.name		= "i2c",
-+	.sysc		= &am33xx_i2c_sysc,
-+	.rev		= OMAP_I2C_IP_VERSION_2,
-+	.reset		= &omap_i2c_reset,
-+};
-+
-+/* I2C1 */
-+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
-+	{ .irq = 70 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
-+	{ .name = "tx", .dma_req = 0, },
-+	{ .name = "rx", .dma_req = 0, },
-+	{ .dma_req = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
-+	&am33xx_l4_wkup_i2c1,
-+};
-+
-+static struct omap_hwmod am33xx_i2c1_hwmod = {
-+	.name		= "i2c1",
-+	.class		= &i2c_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.mpu_irqs	= i2c1_mpu_irqs,
-+	.main_clk	= "i2c1_fck",
-+	.sdma_reqs	= i2c1_edma_reqs,
-+	.flags		= HWMOD_16BIT_REG,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.dev_attr	= &i2c_dev_attr,
-+	.slaves		= am33xx_i2c1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c1_slaves),
-+};
-+
-+/* i2c2 */
-+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
-+	{
-+		.pa_start	= 0x4802A000,
-+		.pa_end		= 0x4802A000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_i2c2_hwmod,
-+	.addr		= am33xx_i2c2_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
-+	{ .irq = 71 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
-+	{ .name = "tx", .dma_req = 0, },
-+	{ .name = "rx", .dma_req = 0, },
-+	{ .dma_req = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
-+	&am335_l4_per_i2c2,
-+};
-+
-+static struct omap_hwmod am33xx_i2c2_hwmod = {
-+	.name		= "i2c2",
-+	.class		= &i2c_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= i2c2_mpu_irqs,
-+	.main_clk	= "i2c2_fck",
-+	.sdma_reqs	= i2c2_edma_reqs,
-+	.flags		= HWMOD_16BIT_REG,
-+	.prcm		= {
-+		.omap4 = {
-+			.clkctrl_offs	= AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.dev_attr	= &i2c_dev_attr,
-+	.slaves		= am33xx_i2c2_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c2_slaves),
-+};
-+
-+/* I2C3 */
-+static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
-+	{
-+		.pa_start	= 0x4819C000,
-+		.pa_end		= 0x4819C000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_i2c3_hwmod,
-+	.addr		= am33xx_i2c3_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
-+	&am335_l4_per_i2c3,
-+};
-+
-+static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
-+	{ .name = "tx", .dma_req = 0, },
-+	{ .name = "rx", .dma_req = 0, },
-+	{ .dma_req = -1 }
-+};
-+
-+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
-+	{ .irq = 30 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_i2c3_hwmod = {
-+	.name		= "i2c3",
-+	.class		= &i2c_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= i2c3_mpu_irqs,
-+	.main_clk	= "i2c3_fck",
-+	.sdma_reqs	= i2c3_edma_reqs,
-+	.flags		= HWMOD_16BIT_REG,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.dev_attr	= &i2c_dev_attr,
-+	.slaves		= am33xx_i2c3_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c3_slaves),
-+};
-+
-+
-+/* ieee5000 */
-+static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
-+	.name		= "ieee5000",
-+};
-+
-+static struct omap_hwmod am33xx_ieee5000_hwmod = {
-+	.name		= "ieee5000",
-+	.class		= &am33xx_ieee5000_hwmod_class,
-+	.clkdm_name	= "l3s_clkdm",
-+	.main_clk	= "ieee5000_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+
-+/* 'l3' class */
-+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
-+	.name		= "l3",
-+};
-+
-+/* l4_hs */
-+static struct omap_hwmod am33xx_l4_hs_hwmod = {
-+	.name		= "l4_hs",
-+	.class		= &am33xx_l3_hwmod_class,
-+	.clkdm_name	= "l4hs_clkdm",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* l3_instr */
-+static struct omap_hwmod am33xx_l3_instr_hwmod = {
-+	.name		= "l3_instr",
-+	.class		= &am33xx_l3_hwmod_class,
-+	.clkdm_name	= "l3_clkdm",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* l3_main */
-+static struct omap_hwmod am33xx_l3_main_hwmod = {
-+	.name		= "l3_main",
-+	.class		= &am33xx_l3_hwmod_class,
-+	.clkdm_name	= "l3_clkdm",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* 'l4fw' class */
-+static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
-+	.name		= "l4fw",
-+};
-+
-+/* l4fw */
-+static struct omap_hwmod am33xx_l4fw_hwmod = {
-+	.name		= "l4fw",
-+	.class		= &am33xx_l4fw_hwmod_class,
-+	.clkdm_name	= "l4fw_clkdm",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* 'l4ls' class */
-+static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
-+	.name		= "l4ls",
-+};
-+
-+/* l4ls */
-+static struct omap_hwmod am33xx_l4ls_hwmod = {
-+	.name		= "l4ls",
-+	.class		= &am33xx_l4ls_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.main_clk	= "l4ls_gclk",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* lcdc */
-+static struct omap_hwmod_class_sysconfig lcdc_sysc = {
-+	.rev_offs	= 0x0,
-+	.sysc_offs	= 0x54,
-+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type2,
-+};
-+
-+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
-+	.name		= "lcdc",
-+	.sysc		= &lcdc_sysc,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
-+	{ .irq = 36 },
-+	{ .irq = -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
-+	{
-+		.pa_start	= 0x4830E000,
-+		.pa_end		= 0x4830E000 + SZ_8K - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
-+	.master		= &am33xx_l3_main_hwmod,
-+	.slave		= &am33xx_lcdc_hwmod,
-+	.addr		= am33xx_lcdc_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
-+	&am33xx_l3_main__lcdc,
-+};
-+
-+static struct omap_hwmod am33xx_lcdc_hwmod = {
-+	.name		= "lcdc",
-+	.class		= &am33xx_lcdc_hwmod_class,
-+	.clkdm_name	= "lcdc_clkdm",
-+	.mpu_irqs	= am33xx_lcdc_irqs,
-+	.main_clk	= "lcdc_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_lcdc_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_lcdc_slaves),
-+	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-+};
-+
-+/*
-+ * 'mailbox' class
-+ * mailbox module allowing communication between the on-chip processors using a
-+ * queued mailbox-interrupt mechanism.
-+ */
-+
-+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
-+			SYSC_HAS_SOFTRESET),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type2,
-+};
-+
-+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
-+	.name	= "mailbox",
-+	.sysc	= &am33xx_mailbox_sysc,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
-+	{ .irq = 77 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
-+	{
-+		.pa_start	= 0x480C8000,
-+		.pa_end		= 0x480C8000 + (SZ_4K - 1),
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+/* l4_cfg -> mailbox */
-+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_mailbox_hwmod,
-+	.addr		= am33xx_mailbox_addrs,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
-+	&am33xx_l4_per__mailbox,
-+};
-+
-+static struct omap_hwmod am33xx_mailbox_hwmod = {
-+	.name		= "mailbox",
-+	.class		= &am33xx_mailbox_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_mailbox_irqs,
-+	.main_clk	= "mailbox0_fck",
-+	.prcm = {
-+		.omap4 = {
-+			.clkctrl_offs	= AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_mailbox_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_mailbox_slaves),
-+};
-+
-+/* 'mcasp' class */
-+
-+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
-+	.rev_offs	= 0x0,
-+	.sysc_offs	= 0x4,
-+	.sysc_flags	= SYSC_HAS_SIDLEMODE,
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type3,
-+};
-+
-+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
-+	.name	= "mcasp",
-+	.sysc	= &am33xx_mcasp_sysc,
-+};
-+
-+/* mcasp0 */
-+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
-+	{ .name = "ax", .irq = 80, },
-+	{ .name = "ar", .irq = 81, },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
-+	{ .name = "tx", .dma_req = AM33XX_DMA_MCASP0_X, },
-+	{ .name = "rx", .dma_req = AM33XX_DMA_MCASP0_R, },
-+	{ .dma_req = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
-+	{
-+		.pa_start	= 0x48038000,
-+		.pa_end		= 0x48038000 + (SZ_1K * 12) - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
-+	.master		= &am33xx_l3slow_hwmod,
-+	.slave		= &am33xx_mcasp0_hwmod,
-+	.clk		= "mcasp0_ick",
-+	.addr		= am33xx_mcasp0_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
-+	&am33xx_l3_slow__mcasp0,
-+};
-+
-+static struct omap_hwmod am33xx_mcasp0_hwmod = {
-+	.name		= "mcasp0",
-+	.class		= &am33xx_mcasp_hwmod_class,
-+	.clkdm_name	= "l3s_clkdm",
-+	.mpu_irqs	= am33xx_mcasp0_irqs,
-+	.sdma_reqs	= am33xx_mcasp0_edma_reqs,
-+	.main_clk	= "mcasp0_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_mcasp0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_mcasp0_slaves),
-+};
-+
-+/* mcasp1 */
-+static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
-+	{ .name = "ax", .irq = 82, },
-+	{ .name = "ar", .irq = 83, },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
-+	{ .name = "tx", .dma_req = AM33XX_DMA_MCASP1_X, },
-+	{ .name = "rx", .dma_req = AM33XX_DMA_MCASP1_R, },
-+	{ .dma_req = -1 }
-+};
-+
-+
-+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
-+	{
-+		.pa_start	= 0x4803C000,
-+		.pa_end		= 0x4803C000 + (SZ_1K * 12) - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
-+	.master		= &am33xx_l3slow_hwmod,
-+	.slave		= &am33xx_mcasp1_hwmod,
-+	.clk		= "mcasp1_ick",
-+	.addr		= am33xx_mcasp1_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
-+	&am33xx_l3_slow__mcasp1,
-+};
-+
-+static struct omap_hwmod am33xx_mcasp1_hwmod = {
-+	.name		= "mcasp1",
-+	.class		= &am33xx_mcasp_hwmod_class,
-+	.clkdm_name	= "l3s_clkdm",
-+	.mpu_irqs	= am33xx_mcasp1_irqs,
-+	.sdma_reqs	= am33xx_mcasp1_edma_reqs,
-+	.main_clk	= "mcasp1_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_mcasp1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_mcasp1_slaves),
-+};
-+
-+/* 'mmc' class */
-+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
-+	.rev_offs	= 0x1fc,
-+	.sysc_offs	= 0x10,
-+	.syss_offs	= 0x14,
-+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-+			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-+			SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
-+	.name		= "mmc",
-+	.sysc		= &am33xx_mmc_sysc,
-+};
-+
-+/* mmc0 */
-+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
-+	{ .irq = 64 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
-+	{ .name = "tx", .dma_req = 24, },
-+	{ .name = "rx", .dma_req = 25, },
-+	{ .dma_req = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
-+	{
-+		.pa_start	= 0x48060100,
-+		.pa_end		= 0x48060100 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
-+	.master		= &am33xx_l4ls_hwmod,
-+	.slave		= &am33xx_mmc0_hwmod,
-+	.clk		= "mmc0_ick",
-+	.addr		= am33xx_mmc0_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
-+	&am33xx_l4ls__mmc0,
-+};
-+
-+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
-+	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-+};
-+
-+static struct omap_hwmod am33xx_mmc0_hwmod = {
-+	.name		= "mmc1",
-+	.class		= &am33xx_mmc_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_mmc0_irqs,
-+	.main_clk	= "mmc0_fck",
-+	.sdma_reqs	= am33xx_mmc0_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.dev_attr	= &am33xx_mmc0_dev_attr,
-+	.slaves		= am33xx_mmc0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc0_slaves),
-+};
-+
-+/* mmc1 */
-+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
-+	{ .irq = 28 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
-+	{ .name = "tx", .dma_req = 2, },
-+	{ .name = "rx", .dma_req = 3, },
-+	{ .dma_req = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
-+	{
-+		.pa_start	= 0x481D8100,
-+		.pa_end		= 0x481D8100 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
-+	.master		= &am33xx_l4ls_hwmod,
-+	.slave		= &am33xx_mmc1_hwmod,
-+	.clk		= "mmc1_ick",
-+	.addr		= am33xx_mmc1_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
-+	&am33xx_l4ls__mmc1,
-+};
-+
-+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
-+	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-+};
-+
-+static struct omap_hwmod am33xx_mmc1_hwmod = {
-+	.name		= "mmc2",
-+	.class		= &am33xx_mmc_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_mmc1_irqs,
-+	.main_clk	= "mmc1_fck",
-+	.sdma_reqs	= am33xx_mmc1_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.dev_attr	= &am33xx_mmc1_dev_attr,
-+	.slaves		= am33xx_mmc1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc1_slaves),
-+};
-+
-+/* mmc2 */
-+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
-+	{ .irq = 29 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
-+	{ .name = "tx", .dma_req = 64, },
-+	{ .name = "rx", .dma_req = 65, },
-+	{ .dma_req = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
-+	{
-+		.pa_start	= 0x47810100,
-+		.pa_end		= 0x47810100 + SZ_64K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
-+	.master		= &am33xx_l3_main_hwmod,
-+	.slave		= &am33xx_mmc2_hwmod,
-+	.clk		= "mmc2_ick",
-+	.addr		= am33xx_mmc2_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
-+	&am33xx_l3_main__mmc2,
-+};
-+
-+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
-+	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-+};
-+static struct omap_hwmod am33xx_mmc2_hwmod = {
-+	.name		= "mmc3",
-+	.class		= &am33xx_mmc_hwmod_class,
-+	.clkdm_name	= "l3s_clkdm",
-+	.mpu_irqs	= am33xx_mmc2_irqs,
-+	.main_clk	= "mmc2_fck",
-+	.sdma_reqs	= am33xx_mmc2_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.dev_attr	= &am33xx_mmc2_dev_attr,
-+	.slaves		= am33xx_mmc2_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc2_slaves),
-+};
-+
-+/* Master interfaces on the MPU interconnect */
-+static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
-+	&am33xx_mpu__l3_slow,
-+};
-+
-+/* mpu */
-+static struct omap_hwmod am33xx_mpu_hwmod = {
-+	.name		= "mpu",
-+	.class		= &mpu_hwmod_class,
-+	.clkdm_name	= "mpu_clkdm",
-+	.main_clk	= "mpu_fck",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.masters	= am33xx_l3_mpu_masters,
-+	.masters_cnt	= ARRAY_SIZE(am33xx_l3_mpu_masters),
-+};
-+
-+/* ocmcram */
-+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
-+	.name = "ocmcram",
-+};
-+
-+static struct omap_hwmod am33xx_ocmcram_hwmod = {
-+	.name		= "ocmcram",
-+	.class		= &am33xx_ocmcram_hwmod_class,
-+	.clkdm_name	= "l3_clkdm",
-+	.main_clk	= "ocmcram_ick",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* ocpwp */
-+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
-+	.name		= "ocpwp",
-+};
-+
-+static struct omap_hwmod am33xx_ocpwp_hwmod = {
-+	.name		= "ocpwp",
-+	.class		= &am33xx_ocpwp_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.main_clk	= "ocpwp_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* rtc */
-+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
-+	.name		= "rtc",
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
-+	{ .irq = 75 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_rtc_hwmod = {
-+	.name		= "rtc",
-+	.class		= &am33xx_rtc_hwmod_class,
-+	.clkdm_name	= "l4_rtc_clkdm",
-+	.mpu_irqs	= am33xx_rtc_irqs,
-+	.main_clk	= "rtc_fck",
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* sha0 */
-+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
-+	.name		= "sha0",
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
-+	{ .irq = 108 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_sha0_hwmod = {
-+	.name		= "sha0",
-+	.class		= &am33xx_sha0_hwmod_class,
-+	.clkdm_name	= "l3_clkdm",
-+	.mpu_irqs	= am33xx_sha0_irqs,
-+	.main_clk	= "sha0_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* 'smartreflex' class */
-+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
-+	.name		= "smartreflex",
-+};
-+
-+/* smartreflex0 */
-+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
-+	{ .irq = 120 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
-+	.name		= "smartreflex0",
-+	.class		= &am33xx_smartreflex_hwmod_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.mpu_irqs	= am33xx_smartreflex0_irqs,
-+	.main_clk	= "smartreflex0_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* smartreflex1 */
-+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
-+	{ .irq = 121 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
-+	.name		= "smartreflex1",
-+	.class		= &am33xx_smartreflex_hwmod_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.mpu_irqs	= am33xx_smartreflex1_irqs,
-+	.main_clk	= "smartreflex1_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* 'spi' class */
-+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0110,
-+	.syss_offs	= 0x0114,
-+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-+			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
-+			SYSS_HAS_RESET_STATUS),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
-+	.name		= "mcspi",
-+	.sysc		= &am33xx_mcspi_sysc,
-+	.rev		= OMAP4_MCSPI_REV,
-+};
-+
-+/* spi0 */
-+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
-+	{ .irq = 65 },
-+	{ .irq = -1 }
-+};
-+
-+struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
-+	{ .name = "rx0", .dma_req = 17 },
-+	{ .name = "tx0", .dma_req = 16 },
-+	{ .name = "rx1", .dma_req = 19 },
-+	{ .name = "tx1", .dma_req = 18 },
-+	{ .dma_req = -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
-+	{
-+		.pa_start	= 0x48030000,
-+		.pa_end		= 0x48030000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_spi0_hwmod,
-+	.clk		= "spi0_ick",
-+	.addr		= am33xx_mcspi0_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
-+	&am33xx_l4_core__mcspi0,
-+};
-+
-+struct omap2_mcspi_dev_attr mcspi_attrib = {
-+	.num_chipselect	= 2,
-+};
-+static struct omap_hwmod am33xx_spi0_hwmod = {
-+	.name		= "spi0",
-+	.class		= &am33xx_spi_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_spi0_irqs,
-+	.main_clk	= "spi0_fck",
-+	.sdma_reqs	= am33xx_mcspi0_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.dev_attr	= &mcspi_attrib,
-+	.slaves		= am33xx_mcspi0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi0_slaves),
-+};
-+
-+/* spi1 */
-+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
-+	{ .irq = 125 },
-+	{ .irq = -1 }
-+};
-+
-+struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
-+	{ .name = "rx0", .dma_req = 43 },
-+	{ .name = "tx0", .dma_req = 42 },
-+	{ .name = "rx1", .dma_req = 45 },
-+	{ .name = "tx1", .dma_req = 44 },
-+	{ .dma_req = -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
-+	{
-+		.pa_start	= 0x481A0000,
-+		.pa_end		= 0x481A0000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_spi1_hwmod,
-+	.clk		= "spi1_ick",
-+	.addr		= am33xx_mcspi1_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
-+	&am33xx_l4_core__mcspi1,
-+};
-+static struct omap_hwmod am33xx_spi1_hwmod = {
-+	.name		= "spi1",
-+	.class		= &am33xx_spi_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_spi1_irqs,
-+	.main_clk	= "spi1_fck",
-+	.sdma_reqs	= am33xx_mcspi1_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.dev_attr	= &mcspi_attrib,
-+	.slaves		= am33xx_mcspi1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi1_slaves),
-+};
-+
-+/* spinlock */
-+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
-+	.name		= "spinlock",
-+};
-+
-+static struct omap_hwmod am33xx_spinlock_hwmod = {
-+	.name		= "spinlock",
-+	.class		= &am33xx_spinlock_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.main_clk	= "spinlock_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+};
-+
-+/* 'timer 0 & 2-7' class */
-+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.syss_offs	= 0x0014,
-+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			SIDLE_SMART_WKUP),
-+	.sysc_fields	= &omap_hwmod_sysc_type2,
-+};
-+
-+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
-+	.name		= "timer",
-+	.sysc		= &am33xx_timer_sysc,
-+};
-+
-+/* timer0 */
-+/* l4 wkup -> timer0 interface */
-+static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
-+	{
-+		.pa_start	= 0x44E05000,
-+		.pa_end		= 0x44E05000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
-+	.master		= &am33xx_l4wkup_hwmod,
-+	.slave		= &am33xx_timer0_hwmod,
-+	.clk		= "timer0_ick",
-+	.addr		= am33xx_timer0_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
-+	&am33xx_l4wkup__timer0,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
-+	{ .irq = 66 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_timer0_hwmod = {
-+	.name		= "timer0",
-+	.class		= &am33xx_timer_hwmod_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.mpu_irqs	= am33xx_timer0_irqs,
-+	.main_clk	= "timer0_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_timer0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer0_slaves),
-+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+};
-+
-+/* timer1 1ms */
-+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.syss_offs	= 0x0014,
-+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-+			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
-+			SYSS_HAS_RESET_STATUS),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
-+	.name		= "timer",
-+	.sysc		= &am33xx_timer1ms_sysc,
-+};
-+
-+/* l4 wkup -> timer1 interface */
-+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
-+	{
-+		.pa_start	= 0x44E31000,
-+		.pa_end		= 0x44E31000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
-+	.master		= &am33xx_l4wkup_hwmod,
-+	.slave		= &am33xx_timer1_hwmod,
-+	.clk		= "timer1_ick",
-+	.addr		= am33xx_timer1_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
-+	&am33xx_l4wkup__timer1,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
-+	{ .irq = 67 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_timer1_hwmod = {
-+	.name		= "timer1",
-+	.class		= &am33xx_timer1ms_hwmod_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.mpu_irqs	= am33xx_timer1_irqs,
-+	.main_clk	= "timer1_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_timer1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer1_slaves),
-+};
-+
-+/* timer2 */
-+/* l4 per -> timer2 interface */
-+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
-+	{
-+		.pa_start	= 0x48040000,
-+		.pa_end		= 0x48040000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_timer2_hwmod,
-+	.clk		= "timer2_ick",
-+	.addr		= am33xx_timer2_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
-+	&am33xx_l4per__timer2,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
-+	{ .irq = 68 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_timer2_hwmod = {
-+	.name		= "timer2",
-+	.class		= &am33xx_timer_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_timer2_irqs,
-+	.main_clk	= "timer2_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_timer2_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer2_slaves),
-+};
-+
-+/* timer3 */
-+/* l4 per -> timer3 interface */
-+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
-+	{
-+		.pa_start	= 0x48042000,
-+		.pa_end		= 0x48042000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_timer3_hwmod,
-+	.clk		= "timer3_ick",
-+	.addr		= am33xx_timer3_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
-+	&am33xx_l4per__timer3,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
-+	{ .irq = 69 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_timer3_hwmod = {
-+	.name		= "timer3",
-+	.class		= &am33xx_timer_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_timer3_irqs,
-+	.main_clk	= "timer3_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_timer3_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer3_slaves),
-+};
-+
-+/* timer4 */
-+/* l4 per -> timer4 interface */
-+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
-+	{
-+		.pa_start	= 0x48044000,
-+		.pa_end		= 0x48044000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_timer4_hwmod,
-+	.clk		= "timer4_ick",
-+	.addr		= am33xx_timer4_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
-+	&am33xx_l4per__timer4,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
-+	{ .irq = 92 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_timer4_hwmod = {
-+	.name		= "timer4",
-+	.class		= &am33xx_timer_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_timer4_irqs,
-+	.main_clk	= "timer4_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_timer4_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer4_slaves),
-+};
-+
-+/* timer5 */
-+/* l4 per -> timer5 interface */
-+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
-+	{
-+		.pa_start	= 0x48046000,
-+		.pa_end		= 0x48046000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_timer5_hwmod,
-+	.clk		= "timer5_ick",
-+	.addr		= am33xx_timer5_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
-+	&am33xx_l4per__timer5,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
-+	{ .irq = 93 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_timer5_hwmod = {
-+	.name		= "timer5",
-+	.class		= &am33xx_timer_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_timer5_irqs,
-+	.main_clk	= "timer5_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_timer5_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer5_slaves),
-+};
-+
-+/* timer6 */
-+/* l4 per -> timer6 interface */
-+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
-+	{
-+		.pa_start	= 0x48048000,
-+		.pa_end		= 0x48048000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_timer6_hwmod,
-+	.clk		= "timer6_ick",
-+	.addr		= am33xx_timer6_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
-+	&am33xx_l4per__timer6,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
-+	{ .irq = 94 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_timer6_hwmod = {
-+	.name		= "timer6",
-+	.class		= &am33xx_timer_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_timer6_irqs,
-+	.main_clk	= "timer6_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_timer6_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer6_slaves),
-+};
-+
-+/* timer7 */
-+/* l4 per -> timer7 interface */
-+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
-+	{
-+		.pa_start	= 0x4804A000,
-+		.pa_end		= 0x4804A000 + SZ_1K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
-+	.master		= &am33xx_l4per_hwmod,
-+	.slave		= &am33xx_timer7_hwmod,
-+	.clk		= "timer7_ick",
-+	.addr		= am33xx_timer7_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
-+	&am33xx_l4per__timer7,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
-+	{ .irq = 95 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod am33xx_timer7_hwmod = {
-+	.name		= "timer7",
-+	.class		= &am33xx_timer_hwmod_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_timer7_irqs,
-+	.main_clk	= "timer7_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_timer7_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer7_slaves),
-+};
-+
-+/* tpcc */
-+#define AM33XX_TPCC_BASE		0x49000000
-+#define AM33XX_TPTC0_BASE		0x49800000
-+#define AM33XX_TPTC1_BASE		0x49900000
-+#define AM33XX_TPTC2_BASE		0x49a00000
-+
-+/* 'tpcc' class */
-+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
-+	.name		= "tpcc",
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
-+	{ .name	= "edma0", .irq = 12 },
-+	{ .name = "edma0_mperr", .irq = 13, },
-+	{ .name	= "edma0_err", .irq = 14 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
-+	{
-+		.name		= "edma_cc0",
-+		.pa_start	= AM33XX_TPCC_BASE,
-+		.pa_end		= AM33XX_TPCC_BASE + SZ_32K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
-+	.master		= &am33xx_l3_main_hwmod,
-+	.slave		= &am33xx_tpcc_hwmod,
-+	.addr		= am33xx_tpcc_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
-+	&am33xx_l3_main__tpcc,
-+};
-+
-+static struct omap_hwmod am33xx_tpcc_hwmod = {
-+	.name		= "tpcc",
-+	.class		= &am33xx_tpcc_hwmod_class,
-+	.clkdm_name	= "l3_clkdm",
-+	.mpu_irqs	= am33xx_tpcc_irqs,
-+	.main_clk	= "tpcc_ick",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_tpcc_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_tpcc_slaves),
-+};
-+
-+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
-+	.rev_offs	= 0x0,
-+	.sysc_offs	= 0x10,
-+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-+			SYSC_HAS_MIDLEMODE),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
-+	.sysc_fields	= &omap_hwmod_sysc_type2,
-+};
-+
-+/* 'tptc' class */
-+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
-+	.name		= "tptc",
-+	.sysc		= &am33xx_tptc_sysc,
-+};
-+
-+/* tptc0 */
-+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
-+	{ .irq = 112 },
-+	{ .irq = -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
-+	{
-+		.name		= "edma_tc0",
-+		.pa_start	= AM33XX_TPTC0_BASE,
-+		.pa_end		= AM33XX_TPTC0_BASE + SZ_8K - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
-+	.master		= &am33xx_l3_main_hwmod,
-+	.slave		= &am33xx_tptc0_hwmod,
-+	.addr		= am33xx_tptc0_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
-+	&am33xx_l3_main__tptc0,
-+};
-+
-+static struct omap_hwmod am33xx_tptc0_hwmod = {
-+	.name		= "tptc0",
-+	.class		= &am33xx_tptc_hwmod_class,
-+	.clkdm_name	= "l3_clkdm",
-+	.mpu_irqs	= am33xx_tptc0_irqs,
-+	.main_clk	= "tptc0_ick",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_tptc0_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_tptc0_slaves),
-+	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-+};
-+
-+/* tptc1 */
-+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
-+	{ .irq = 113 },
-+	{ .irq = -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
-+	{
-+		.name		= "edma_tc1",
-+		.pa_start	= AM33XX_TPTC1_BASE,
-+		.pa_end		= AM33XX_TPTC1_BASE + SZ_8K - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
-+	.master		= &am33xx_l3_main_hwmod,
-+	.slave		= &am33xx_tptc1_hwmod,
-+	.addr		= am33xx_tptc1_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
-+	&am33xx_l3_main__tptc1,
-+};
-+
-+static struct omap_hwmod am33xx_tptc1_hwmod = {
-+	.name		= "tptc1",
-+	.class		= &am33xx_tptc_hwmod_class,
-+	.clkdm_name	= "l3_clkdm",
-+	.mpu_irqs	= am33xx_tptc1_irqs,
-+	.main_clk	= "tptc1_ick",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_tptc1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_tptc1_slaves),
-+	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-+};
-+
-+/* tptc2 */
-+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
-+	{ .irq = 114 },
-+	{ .irq = -1 }
-+};
-+
-+struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
-+	{
-+		.name		= "edma_tc2",
-+		.pa_start	= AM33XX_TPTC2_BASE,
-+		.pa_end		= AM33XX_TPTC2_BASE + SZ_8K - 1,
-+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
-+	.master		= &am33xx_l3_main_hwmod,
-+	.slave		= &am33xx_tptc2_hwmod,
-+	.addr		= am33xx_tptc2_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
-+	&am33xx_l3_main__tptc2,
-+};
-+
-+static struct omap_hwmod am33xx_tptc2_hwmod = {
-+	.name		= "tptc2",
-+	.class		= &am33xx_tptc_hwmod_class,
-+	.clkdm_name	= "l3_clkdm",
-+	.mpu_irqs	= am33xx_tptc2_irqs,
-+	.main_clk	= "tptc2_ick",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_tptc2_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_tptc2_slaves),
-+	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-+};
-+
-+/* 'uart' class */
-+static struct omap_hwmod_class_sysconfig uart_sysc = {
-+	.rev_offs	= 0x50,
-+	.sysc_offs	= 0x54,
-+	.syss_offs	= 0x58,
-+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
-+			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			SIDLE_SMART_WKUP),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class uart_class = {
-+	.name		= "uart",
-+	.sysc		= &uart_sysc,
-+};
-+
-+/* uart1 */
-+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
-+	{ .name = "tx",	.dma_req = 26, },
-+	{ .name = "rx",	.dma_req = 27, },
-+	{ .dma_req = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
-+	{
-+		.pa_start	= 0x44E09000,
-+		.pa_end		= 0x44E09000 + SZ_8K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
-+	.master		= &am33xx_l4wkup_hwmod,
-+	.slave		= &am33xx_uart1_hwmod,
-+	.clk		= "uart1_ick",
-+	.addr		= am33xx_uart1_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
-+	{ .irq = 72 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
-+	&am33xx_l4_wkup__uart1,
-+};
-+
-+static struct omap_hwmod am33xx_uart1_hwmod = {
-+	.name		= "uart1",
-+	.class		= &uart_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.mpu_irqs	= am33xx_uart1_irqs,
-+	.main_clk	= "uart1_fck",
-+	.sdma_reqs	= uart1_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_uart1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart1_slaves),
-+};
-+
-+/* uart2 */
-+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
-+	{
-+		.pa_start	= 0x48022000,
-+		.pa_end		= 0x48022000 + SZ_8K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
-+	.slave		= &am33xx_uart2_hwmod,
-+	.clk		= "uart2_ick",
-+	.addr		= am33xx_uart2_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
-+	{ .irq = 73 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
-+	&am33xx_l4_ls__uart2,
-+};
-+
-+static struct omap_hwmod am33xx_uart2_hwmod = {
-+	.name		= "uart2",
-+	.class		= &uart_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_uart2_irqs,
-+	.main_clk	= "uart2_fck",
-+	.sdma_reqs	= uart1_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_uart2_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart2_slaves),
-+};
-+
-+/* uart3 */
-+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
-+	{ .name = "tx",	.dma_req = 30, },
-+	{ .name = "rx",	.dma_req = 31, },
-+	{ .dma_req = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
-+	{
-+		.pa_start	= 0x48024000,
-+		.pa_end		= 0x48024000 + SZ_8K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
-+	.slave		= &am33xx_uart3_hwmod,
-+	.clk		= "uart3_ick",
-+	.addr		= am33xx_uart3_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
-+	{ .irq = 74 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
-+	&am33xx_l4_ls__uart3,
-+};
-+
-+static struct omap_hwmod am33xx_uart3_hwmod = {
-+	.name		= "uart3",
-+	.class		= &uart_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_uart3_irqs,
-+	.main_clk	= "uart3_fck",
-+	.sdma_reqs	= uart3_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_uart3_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart3_slaves),
-+};
-+
-+/* uart4 */
-+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
-+	{
-+		.pa_start	= 0x481A6000,
-+		.pa_end		= 0x481A6000 + SZ_8K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
-+	.slave		= &am33xx_uart4_hwmod,
-+	.clk		= "uart4_ick",
-+	.addr		= am33xx_uart4_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
-+	{ .irq = 44 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
-+	&am33xx_l4_ls__uart4,
-+};
-+
-+static struct omap_hwmod am33xx_uart4_hwmod = {
-+	.name		= "uart4",
-+	.class		= &uart_class,
-+	.mpu_irqs	= am33xx_uart4_irqs,
-+	.main_clk	= "uart4_fck",
-+	.clkdm_name	= "l4ls_clkdm",
-+	.sdma_reqs	= uart1_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_uart4_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart4_slaves),
-+};
-+
-+/* uart5 */
-+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
-+	{
-+		.pa_start	= 0x481A8000,
-+		.pa_end		= 0x481A8000 + SZ_8K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
-+	.slave		= &am33xx_uart5_hwmod,
-+	.clk		= "uart5_ick",
-+	.addr		= am33xx_uart5_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
-+	{ .irq = 45 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
-+	&am33xx_l4_ls__uart5,
-+};
-+
-+static struct omap_hwmod am33xx_uart5_hwmod = {
-+	.name		= "uart5",
-+	.class		= &uart_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_uart5_irqs,
-+	.main_clk	= "uart5_fck",
-+	.sdma_reqs	= uart1_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_uart5_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart5_slaves),
-+};
-+
-+/* uart6 */
-+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
-+	{
-+		.pa_start	= 0x481AA000,
-+		.pa_end		= 0x481AA000 + SZ_8K - 1,
-+		.flags		= ADDR_TYPE_RT,
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
-+	.slave		= &am33xx_uart6_hwmod,
-+	.clk		= "uart6_ick",
-+	.addr		= am33xx_uart6_addr_space,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
-+	{ .irq = 46 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
-+	&am33xx_l4_ls__uart6,
-+};
-+
-+static struct omap_hwmod am33xx_uart6_hwmod = {
-+	.name		= "uart6",
-+	.class		= &uart_class,
-+	.clkdm_name	= "l4ls_clkdm",
-+	.mpu_irqs	= am33xx_uart6_irqs,
-+	.main_clk	= "uart6_fck",
-+	.sdma_reqs	= uart1_edma_reqs,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_uart6_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart6_slaves),
-+};
-+
-+/* 'wd_timer' class */
-+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
-+	.name		= "wd_timer",
-+};
-+
-+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
-+	{
-+		.pa_start	= 0x44E35000,
-+		.pa_end		= 0x44E35000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+/* l4_wkup -> wd_timer1 */
-+static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
-+	.master		= &am33xx_l4wkup_hwmod,
-+	.slave		= &am33xx_wd_timer1_hwmod,
-+	.addr		= am33xx_wd_timer1_addrs,
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
-+	&am33xx_l4wkup__wd_timer1,
-+};
-+
-+/*
-+ * TODO: device.c file uses hardcoded name for watchdog timer
-+ * driver "wd_timer2, so we are also using same name as of now...
-+ */
-+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
-+	.name		= "wd_timer2",
-+	.class		= &am33xx_wd_timer_hwmod_class,
-+	.clkdm_name	= "l4_wkup_clkdm",
-+	.main_clk	= "wdt1_fck",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_wd_timer1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_wd_timer1_slaves),
-+};
-+
-+/* wkup_m3 */
-+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
-+	.name		= "wkup_m3",
-+};
-+
-+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
-+	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
-+};
-+
-+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
-+	.name		= "wkup_m3",
-+	.class		= &am33xx_wkup_m3_hwmod_class,
-+	.clkdm_name	= "l4_wkup_aon_clkdm",
-+	.main_clk	= "wkup_m3_fck",
-+	.flags		= HWMOD_INIT_NO_RESET,	/* Keep hardreset asserted */
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
-+			.rstctrl_offs	= AM33XX_RM_WKUP_RSTCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.rst_lines	= am33xx_wkup_m3_resets,
-+	.rst_lines_cnt	= ARRAY_SIZE(am33xx_wkup_m3_resets),
-+};
-+
-+/* usbss */
-+/* L3 SLOW -> USBSS interface */
-+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
-+	{
-+		.name		= "usbss",
-+		.pa_start	= 0x47400000,
-+		.pa_end		= 0x47400000 + SZ_4K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{
-+		.name		= "musb0",
-+		.pa_start	= 0x47401000,
-+		.pa_end		= 0x47401000 + SZ_2K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{
-+		.name		= "musb1",
-+		.pa_start	= 0x47401800,
-+		.pa_end		= 0x47401800 + SZ_2K - 1,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
-+	.rev_offs	= 0x0,
-+	.sysc_offs	= 0x10,
-+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type2,
-+};
-+
-+static struct omap_hwmod_class am33xx_usbotg_class = {
-+	.name		= "usbotg",
-+	.sysc		= &am33xx_usbhsotg_sysc,
-+};
-+
-+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
-+	{ .name = "usbss-irq", .irq = 17, },
-+	{ .name = "musb0-irq", .irq = 18, },
-+	{ .name = "musb1-irq", .irq = 19, },
-+	{ .irq = -1, },
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
-+	.master		= &am33xx_l3slow_hwmod,
-+	.slave		= &am33xx_usbss_hwmod,
-+	.clk		= "usbotg_ick",
-+	.addr		= am33xx_usbss_addr_space,
-+	.user		= OCP_USER_MPU,
-+	.flags		= OCPIF_SWSUP_IDLE,
-+};
-+
-+static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
-+	&am33xx_l3_slow__usbss,
-+};
-+
-+static struct omap_hwmod am33xx_usbss_hwmod = {
-+	.name		= "usb_otg_hs",
-+	.class		= &am33xx_usbotg_class,
-+	.clkdm_name	= "l3s_clkdm",
-+	.mpu_irqs	= am33xx_usbss_mpu_irqs,
-+	.main_clk	= "usbotg_fck",
-+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= am33xx_usbss_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(am33xx_usbss_slaves),
-+	.class		= &am33xx_usbotg_class,
-+	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-+};
-+
-+/* gfx */
-+/* Pseudo hwmod for reset control purpose only */
-+static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
-+	.name	= "gfx",
-+};
-+
-+static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
-+	{ .name = "gfx", .rst_shift = 0 },
-+};
-+
-+static struct omap_hwmod am33xx_gfx_hwmod = {
-+	.name		= "gfx",
-+	.class		= &am33xx_gfx_hwmod_class,
-+	.clkdm_name	= "gfx_l3_clkdm",
-+	.main_clk	= "gfx_fclk",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
-+			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.rst_lines	= am33xx_gfx_resets,
-+	.rst_lines_cnt	= ARRAY_SIZE(am33xx_gfx_resets),
-+};
-+
-+/* PRUSS */
-+/* Pseudo hwmod for reset control purpose only */
-+static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
-+	.name	= "pruss",
-+};
-+
-+static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
-+	{ .name = "pruss", .rst_shift = 1 },
-+};
-+
-+static struct omap_hwmod am33xx_pruss_hwmod = {
-+	.name		= "pruss",
-+	.class		= &am33xx_pruss_hwmod_class,
-+	.clkdm_name	= "pruss_ocp_clkdm",
-+	.main_clk	= "pruss_uart_gclk",
-+	.prcm		= {
-+		.omap4	= {
-+			.clkctrl_offs	= AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
-+			.rstctrl_offs	= AM33XX_RM_PER_RSTCTRL_OFFSET,
-+			.modulemode	= MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.rst_lines	= am33xx_pruss_resets,
-+	.rst_lines_cnt	= ARRAY_SIZE(am33xx_pruss_resets),
-+};
-+
-+static __initdata struct omap_hwmod *am33xx_hwmods[] = {
-+	/* l3 class */
-+	&am33xx_l3_instr_hwmod,
-+	&am33xx_l3_main_hwmod,
-+	/* l3s class */
-+	&am33xx_l3slow_hwmod,
-+	/* l4hs class */
-+	&am33xx_l4_hs_hwmod,
-+	/* l4fw class */
-+	&am33xx_l4fw_hwmod,
-+	/* l4ls class */
-+	&am33xx_l4ls_hwmod,
-+	/* l4per class */
-+	&am33xx_l4per_hwmod,
-+	/* l4wkup class */
-+	&am33xx_l4wkup_hwmod,
-+	/* clkdiv32k class */
-+	&am33xx_clkdiv32k_hwmod,
-+	/* mpu class */
-+	&am33xx_mpu_hwmod,
-+	/* adc_tsc class */
-+	&am33xx_adc_tsc_hwmod,
-+	/* aes class */
-+	&am33xx_aes0_hwmod,
-+	/* cefuse class */
-+	&am33xx_cefuse_hwmod,
-+	/* control class */
-+	&am33xx_control_hwmod,
-+	/* dcan class */
-+	&am33xx_dcan0_hwmod,
-+	&am33xx_dcan1_hwmod,
-+	/* debugss class */
-+	&am33xx_debugss_hwmod,
-+	/* elm class */
-+	&am33xx_elm_hwmod,
-+	/* emif_fw class */
-+	&am33xx_emif_fw_hwmod,
-+	/* epwmss class */
-+	&am33xx_ehrpwm0_hwmod,
-+	&am33xx_ehrpwm1_hwmod,
-+	&am33xx_ehrpwm2_hwmod,
-+	&am33xx_ecap0_hwmod,
-+	&am33xx_ecap1_hwmod,
-+	&am33xx_ecap2_hwmod,
-+	/* gpio class */
-+	&am33xx_gpio0_hwmod,
-+	&am33xx_gpio1_hwmod,
-+	&am33xx_gpio2_hwmod,
-+	&am33xx_gpio3_hwmod,
-+	/* gpmc class */
-+	&am33xx_gpmc_hwmod,
-+	/* i2c class */
-+	&am33xx_i2c1_hwmod,
-+	&am33xx_i2c2_hwmod,
-+	&am33xx_i2c3_hwmod,
-+	/* ieee5000 class */
-+	&am33xx_ieee5000_hwmod,
-+	/* mailbox class */
-+	&am33xx_mailbox_hwmod,
-+	/* mcasp class */
-+	&am33xx_mcasp0_hwmod,
-+	&am33xx_mcasp1_hwmod,
-+	/* mmc class */
-+	&am33xx_mmc0_hwmod,
-+	&am33xx_mmc1_hwmod,
-+	&am33xx_mmc2_hwmod,
-+	/* ocmcram class */
-+	&am33xx_ocmcram_hwmod,
-+	/* ocpwp class */
-+	&am33xx_ocpwp_hwmod,
-+	/* rtc class */
-+	&am33xx_rtc_hwmod,
-+	/* sha0 class */
-+	&am33xx_sha0_hwmod,
-+	/* smartreflex class */
-+	&am33xx_smartreflex0_hwmod,
-+	&am33xx_smartreflex1_hwmod,
-+	/* spi class */
-+	&am33xx_spi0_hwmod,
-+	&am33xx_spi1_hwmod,
-+	/* spinlock class */
-+	&am33xx_spinlock_hwmod,
-+	/* uart class */
-+	&am33xx_uart1_hwmod,
-+	&am33xx_uart2_hwmod,
-+	&am33xx_uart3_hwmod,
-+	&am33xx_uart4_hwmod,
-+	&am33xx_uart5_hwmod,
-+	&am33xx_uart6_hwmod,
-+	/* timer class */
-+	&am33xx_timer0_hwmod,
-+	&am33xx_timer1_hwmod,
-+	&am33xx_timer2_hwmod,
-+	&am33xx_timer3_hwmod,
-+	&am33xx_timer4_hwmod,
-+	&am33xx_timer5_hwmod,
-+	&am33xx_timer6_hwmod,
-+	&am33xx_timer7_hwmod,
-+	/* wkup_m3 class */
-+	&am33xx_wkup_m3_hwmod,
-+	/* wd_timer class */
-+	&am33xx_wd_timer1_hwmod,
-+	/* usbss hwmod */
-+	&am33xx_usbss_hwmod,
-+	/* cpgmac0 class */
-+	&am33xx_cpgmac0_hwmod,
-+	/* tptc class */
-+	&am33xx_tptc0_hwmod,
-+	&am33xx_tptc1_hwmod,
-+	&am33xx_tptc2_hwmod,
-+	/* tpcc class */
-+	&am33xx_tpcc_hwmod,
-+	/* LCDC class */
-+	&am33xx_lcdc_hwmod,
-+	/* gfx/sgx */
-+	&am33xx_gfx_hwmod,
-+	/* pruss */
-+	&am33xx_pruss_hwmod,
-+	NULL,
-+};
-+
-+int __init am33xx_hwmod_init(void)
-+{
-+	return omap_hwmod_register(am33xx_hwmods);
-+}
-diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
-index eef43e2..5324e8d 100644
---- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
-@@ -84,6 +84,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
- static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
- static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
- static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
-+static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
-+static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
- 
- /* L3 -> L4_CORE interface */
- static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
-@@ -164,6 +166,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod;
- static struct omap_hwmod omap3xxx_uart2_hwmod;
- static struct omap_hwmod omap3xxx_uart3_hwmod;
- static struct omap_hwmod omap3xxx_uart4_hwmod;
-+static struct omap_hwmod am35xx_uart4_hwmod;
- static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
- 
- /* l3_core -> usbhsotg interface */
-@@ -299,6 +302,23 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
- 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
- };
- 
-+/* AM35xx: L4 CORE -> UART4 interface */
-+static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
-+	{
-+		.pa_start       = OMAP3_UART4_AM35XX_BASE,
-+		.pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
-+		.flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-+	},
-+};
-+
-+static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
-+	.master         = &omap3xxx_l4_core_hwmod,
-+	.slave          = &am35xx_uart4_hwmod,
-+	.clk            = "uart4_ick",
-+	.addr           = am35xx_uart4_addr_space,
-+	.user           = OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
- /* L4 CORE -> I2C1 interface */
- static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
- 	.master		= &omap3xxx_l4_core_hwmod,
-@@ -1162,6 +1182,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
- 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.clockact	= CLOCKACT_TEST_ICLK,
- 	.sysc_fields    = &omap_hwmod_sysc_type1,
- };
- 
-@@ -1309,6 +1330,39 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
- 	.class		= &omap2_uart_class,
- };
- 
-+static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
-+	{ .irq = INT_35XX_UART4_IRQ, },
-+};
-+
-+static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
-+	{ .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
-+	{ .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
-+};
-+
-+static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
-+	&am35xx_l4_core__uart4,
-+};
-+
-+static struct omap_hwmod am35xx_uart4_hwmod = {
-+	.name           = "uart4",
-+	.mpu_irqs       = am35xx_uart4_mpu_irqs,
-+	.sdma_reqs      = am35xx_uart4_sdma_reqs,
-+	.main_clk       = "uart4_fck",
-+	.prcm           = {
-+		.omap2 = {
-+			.module_offs = CORE_MOD,
-+			.prcm_reg_id = 1,
-+			.module_bit = OMAP3430_EN_UART4_SHIFT,
-+			.idlest_reg_id = 1,
-+			.idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
-+		},
-+	},
-+	.slaves         = am35xx_uart4_slaves,
-+	.slaves_cnt     = ARRAY_SIZE(am35xx_uart4_slaves),
-+	.class          = &omap2_uart_class,
-+};
-+
-+
- static struct omap_hwmod_class i2c_class = {
- 	.name	= "i2c",
- 	.sysc	= &i2c_sysc,
-@@ -1636,7 +1690,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
- 
- static struct omap_hwmod omap3xxx_i2c1_hwmod = {
- 	.name		= "i2c1",
--	.flags		= HWMOD_16BIT_REG,
-+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- 	.mpu_irqs	= omap2_i2c1_mpu_irqs,
- 	.sdma_reqs	= omap2_i2c1_sdma_reqs,
- 	.main_clk	= "i2c1_fck",
-@@ -1670,7 +1724,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
- 
- static struct omap_hwmod omap3xxx_i2c2_hwmod = {
- 	.name		= "i2c2",
--	.flags		= HWMOD_16BIT_REG,
-+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- 	.mpu_irqs	= omap2_i2c2_mpu_irqs,
- 	.sdma_reqs	= omap2_i2c2_sdma_reqs,
- 	.main_clk	= "i2c2_fck",
-@@ -1715,7 +1769,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
- 
- static struct omap_hwmod omap3xxx_i2c3_hwmod = {
- 	.name		= "i2c3",
--	.flags		= HWMOD_16BIT_REG,
-+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- 	.mpu_irqs	= i2c3_mpu_irqs,
- 	.sdma_reqs	= i2c3_sdma_reqs,
- 	.main_clk	= "i2c3_fck",
-@@ -3072,7 +3126,35 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
- 	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
- };
- 
--static struct omap_hwmod omap3xxx_mmc1_hwmod = {
-+/* See 35xx errata 2.1.1.128 in SPRZ278F */
-+static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
-+	.flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
-+		  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
-+};
-+
-+static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
-+	.name		= "mmc1",
-+	.mpu_irqs	= omap34xx_mmc1_mpu_irqs,
-+	.sdma_reqs	= omap34xx_mmc1_sdma_reqs,
-+	.opt_clks	= omap34xx_mmc1_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
-+	.main_clk	= "mmchs1_fck",
-+	.prcm		= {
-+		.omap2 = {
-+			.module_offs = CORE_MOD,
-+			.prcm_reg_id = 1,
-+			.module_bit = OMAP3430_EN_MMC1_SHIFT,
-+			.idlest_reg_id = 1,
-+			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
-+		},
-+	},
-+	.dev_attr	= &mmc1_pre_es3_dev_attr,
-+	.slaves		= omap3xxx_mmc1_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_mmc1_slaves),
-+	.class		= &omap34xx_mmc_class,
-+};
-+
-+static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
- 	.name		= "mmc1",
- 	.mpu_irqs	= omap34xx_mmc1_mpu_irqs,
- 	.sdma_reqs	= omap34xx_mmc1_sdma_reqs,
-@@ -3115,7 +3197,34 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
- 	&omap3xxx_l4_core__mmc2,
- };
- 
--static struct omap_hwmod omap3xxx_mmc2_hwmod = {
-+/* See 35xx errata 2.1.1.128 in SPRZ278F */
-+static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
-+	.flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
-+};
-+
-+static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
-+	.name		= "mmc2",
-+	.mpu_irqs	= omap34xx_mmc2_mpu_irqs,
-+	.sdma_reqs	= omap34xx_mmc2_sdma_reqs,
-+	.opt_clks	= omap34xx_mmc2_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
-+	.main_clk	= "mmchs2_fck",
-+	.prcm		= {
-+		.omap2 = {
-+			.module_offs = CORE_MOD,
-+			.prcm_reg_id = 1,
-+			.module_bit = OMAP3430_EN_MMC2_SHIFT,
-+			.idlest_reg_id = 1,
-+			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
-+		},
-+	},
-+	.dev_attr	= &mmc2_pre_es3_dev_attr,
-+	.slaves		= omap3xxx_mmc2_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_mmc2_slaves),
-+	.class		= &omap34xx_mmc_class,
-+};
-+
-+static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
- 	.name		= "mmc2",
- 	.mpu_irqs	= omap34xx_mmc2_mpu_irqs,
- 	.sdma_reqs	= omap34xx_mmc2_sdma_reqs,
-@@ -3177,13 +3286,223 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
- 	.class		= &omap34xx_mmc_class,
- };
- 
-+/*
-+ * 'usb_host_hs' class
-+ * high-speed multi-port usb host controller
-+ */
-+static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
-+	.master		= &omap3xxx_usb_host_hs_hwmod,
-+	.slave		= &omap3xxx_l3_main_hwmod,
-+	.clk		= "core_l3_ick",
-+	.user		= OCP_USER_MPU,
-+};
-+
-+static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.syss_offs	= 0x0014,
-+	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
-+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
-+			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
-+	.name = "usb_host_hs",
-+	.sysc = &omap3xxx_usb_host_hs_sysc,
-+};
-+
-+static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
-+	&omap3xxx_usb_host_hs__l3_main_2,
-+};
-+
-+static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
-+	{
-+		.name		= "uhh",
-+		.pa_start	= 0x48064000,
-+		.pa_end		= 0x480643ff,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{
-+		.name		= "ohci",
-+		.pa_start	= 0x48064400,
-+		.pa_end		= 0x480647ff,
-+	},
-+	{
-+		.name		= "ehci",
-+		.pa_start	= 0x48064800,
-+		.pa_end		= 0x48064cff,
-+	},
-+	{}
-+};
-+
-+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
-+	.master		= &omap3xxx_l4_core_hwmod,
-+	.slave		= &omap3xxx_usb_host_hs_hwmod,
-+	.clk		= "usbhost_ick",
-+	.addr		= omap3xxx_usb_host_hs_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
-+	&omap3xxx_l4_core__usb_host_hs,
-+};
-+
-+static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
-+	  { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
-+};
-+
-+static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
-+	{ .name = "ohci-irq", .irq = 76 },
-+	{ .name = "ehci-irq", .irq = 77 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
-+	.name		= "usb_host_hs",
-+	.class		= &omap3xxx_usb_host_hs_hwmod_class,
-+	.clkdm_name	= "l3_init_clkdm",
-+	.mpu_irqs	= omap3xxx_usb_host_hs_irqs,
-+	.main_clk	= "usbhost_48m_fck",
-+	.prcm = {
-+		.omap2 = {
-+			.module_offs = OMAP3430ES2_USBHOST_MOD,
-+			.prcm_reg_id = 1,
-+			.module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
-+			.idlest_reg_id = 1,
-+			.idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
-+			.idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
-+		},
-+	},
-+	.opt_clks	= omap3xxx_usb_host_hs_opt_clks,
-+	.opt_clks_cnt	= ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
-+	.slaves		= omap3xxx_usb_host_hs_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
-+	.masters	= omap3xxx_usb_host_hs_masters,
-+	.masters_cnt	= ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
-+
-+	/*
-+	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
-+	 * id: i660
-+	 *
-+	 * Description:
-+	 * In the following configuration :
-+	 * - USBHOST module is set to smart-idle mode
-+	 * - PRCM asserts idle_req to the USBHOST module ( This typically
-+	 *   happens when the system is going to a low power mode : all ports
-+	 *   have been suspended, the master part of the USBHOST module has
-+	 *   entered the standby state, and SW has cut the functional clocks)
-+	 * - an USBHOST interrupt occurs before the module is able to answer
-+	 *   idle_ack, typically a remote wakeup IRQ.
-+	 * Then the USB HOST module will enter a deadlock situation where it
-+	 * is no more accessible nor functional.
-+	 *
-+	 * Workaround:
-+	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
-+	 */
-+
-+	/*
-+	 * Errata: USB host EHCI may stall when entering smart-standby mode
-+	 * Id: i571
-+	 *
-+	 * Description:
-+	 * When the USBHOST module is set to smart-standby mode, and when it is
-+	 * ready to enter the standby state (i.e. all ports are suspended and
-+	 * all attached devices are in suspend mode), then it can wrongly assert
-+	 * the Mstandby signal too early while there are still some residual OCP
-+	 * transactions ongoing. If this condition occurs, the internal state
-+	 * machine may go to an undefined state and the USB link may be stuck
-+	 * upon the next resume.
-+	 *
-+	 * Workaround:
-+	 * Don't use smart standby; use only force standby,
-+	 * hence HWMOD_SWSUP_MSTANDBY
-+	 */
-+
-+	/*
-+	 * During system boot; If the hwmod framework resets the module
-+	 * the module will have smart idle settings; which can lead to deadlock
-+	 * (above Errata Id:i660); so, dont reset the module during boot;
-+	 * Use HWMOD_INIT_NO_RESET.
-+	 */
-+
-+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
-+			  HWMOD_INIT_NO_RESET,
-+};
-+
-+/*
-+ * 'usb_tll_hs' class
-+ * usb_tll_hs module is the adapter on the usb_host_hs ports
-+ */
-+static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.syss_offs	= 0x0014,
-+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-+			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-+			   SYSC_HAS_AUTOIDLE),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
-+	.name = "usb_tll_hs",
-+	.sysc = &omap3xxx_usb_tll_hs_sysc,
-+};
-+
-+static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
-+	{ .name = "tll-irq", .irq = 78 },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
-+	{
-+		.name		= "tll",
-+		.pa_start	= 0x48062000,
-+		.pa_end		= 0x48062fff,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{}
-+};
-+
-+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
-+	.master		= &omap3xxx_l4_core_hwmod,
-+	.slave		= &omap3xxx_usb_tll_hs_hwmod,
-+	.clk		= "usbtll_ick",
-+	.addr		= omap3xxx_usb_tll_hs_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
-+	&omap3xxx_l4_core__usb_tll_hs,
-+};
-+
-+static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
-+	.name		= "usb_tll_hs",
-+	.class		= &omap3xxx_usb_tll_hs_hwmod_class,
-+	.clkdm_name	= "l3_init_clkdm",
-+	.mpu_irqs	= omap3xxx_usb_tll_hs_irqs,
-+	.main_clk	= "usbtll_fck",
-+	.prcm = {
-+		.omap2 = {
-+			.module_offs = CORE_MOD,
-+			.prcm_reg_id = 3,
-+			.module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
-+			.idlest_reg_id = 3,
-+			.idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
-+		},
-+	},
-+	.slaves		= omap3xxx_usb_tll_hs_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
-+};
-+
- static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
- 	&omap3xxx_l3_main_hwmod,
- 	&omap3xxx_l4_core_hwmod,
- 	&omap3xxx_l4_per_hwmod,
- 	&omap3xxx_l4_wkup_hwmod,
--	&omap3xxx_mmc1_hwmod,
--	&omap3xxx_mmc2_hwmod,
- 	&omap3xxx_mmc3_hwmod,
- 	&omap3xxx_mpu_hwmod,
- 
-@@ -3198,12 +3517,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
- 	&omap3xxx_timer9_hwmod,
- 	&omap3xxx_timer10_hwmod,
- 	&omap3xxx_timer11_hwmod,
--	&omap3xxx_timer12_hwmod,
- 
- 	&omap3xxx_wd_timer2_hwmod,
- 	&omap3xxx_uart1_hwmod,
- 	&omap3xxx_uart2_hwmod,
- 	&omap3xxx_uart3_hwmod,
-+
- 	/* dss class */
- 	&omap3xxx_dss_dispc_hwmod,
- 	&omap3xxx_dss_dsi1_hwmod,
-@@ -3245,6 +3564,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
- 	NULL,
- };
- 
-+/* GP-only hwmods */
-+static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
-+	&omap3xxx_timer12_hwmod,
-+	NULL
-+};
-+
- /* 3430ES1-only hwmods */
- static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
- 	&omap3430es1_dss_core_hwmod,
-@@ -3255,6 +3580,22 @@ static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
- static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
- 	&omap3xxx_dss_core_hwmod,
- 	&omap3xxx_usbhsotg_hwmod,
-+	&omap3xxx_usb_host_hs_hwmod,
-+	&omap3xxx_usb_tll_hs_hwmod,
-+	NULL
-+};
-+
-+/* <= 3430ES3-only hwmods */
-+static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
-+	&omap3xxx_pre_es3_mmc1_hwmod,
-+	&omap3xxx_pre_es3_mmc2_hwmod,
-+	NULL
-+};
-+
-+/* 3430ES3+-only hwmods */
-+static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
-+	&omap3xxx_es3plus_mmc1_hwmod,
-+	&omap3xxx_es3plus_mmc2_hwmod,
- 	NULL
- };
- 
-@@ -3276,12 +3617,21 @@ static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
- 	&omap36xx_sr2_hwmod,
- 	&omap3xxx_usbhsotg_hwmod,
- 	&omap3xxx_mailbox_hwmod,
-+	&omap3xxx_usb_host_hs_hwmod,
-+	&omap3xxx_usb_tll_hs_hwmod,
-+	&omap3xxx_es3plus_mmc1_hwmod,
-+	&omap3xxx_es3plus_mmc2_hwmod,
- 	NULL
- };
- 
- static __initdata struct omap_hwmod *am35xx_hwmods[] = {
- 	&omap3xxx_dss_core_hwmod, /* XXX ??? */
- 	&am35xx_usbhsotg_hwmod,
-+	&am35xx_uart4_hwmod,
-+	&omap3xxx_usb_host_hs_hwmod,
-+	&omap3xxx_usb_tll_hs_hwmod,
-+	&omap3xxx_es3plus_mmc1_hwmod,
-+	&omap3xxx_es3plus_mmc2_hwmod,
- 	NULL
- };
- 
-@@ -3296,6 +3646,13 @@ int __init omap3xxx_hwmod_init(void)
- 	if (r < 0)
- 		return r;
- 
-+	/* Register GP-only hwmods. */
-+	if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
-+		r = omap_hwmod_register(omap3xxx_gp_hwmods);
-+		if (r < 0)
-+			return r;
-+	}
-+
- 	rev = omap_rev();
- 
- 	/*
-@@ -3334,6 +3691,21 @@ int __init omap3xxx_hwmod_init(void)
- 		h = omap3430es2plus_hwmods;
- 	};
- 
-+	if (h) {
-+		r = omap_hwmod_register(h);
-+		if (r < 0)
-+			return r;
-+	}
-+
-+	h = NULL;
-+	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
-+	    rev == OMAP3430_REV_ES2_1) {
-+		h = omap3430_pre_es3_hwmods;
-+	} else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
-+		   rev == OMAP3430_REV_ES3_1_2) {
-+		h = omap3430_es3plus_hwmods;
-+	};
-+
- 	if (h)
- 		r = omap_hwmod_register(h);
- 
-diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
-index daaf165..31a3084 100644
---- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
-@@ -53,6 +53,7 @@ static struct omap_hwmod omap44xx_dmm_hwmod;
- static struct omap_hwmod omap44xx_dsp_hwmod;
- static struct omap_hwmod omap44xx_dss_hwmod;
- static struct omap_hwmod omap44xx_emif_fw_hwmod;
-+static struct omap_hwmod omap44xx_fdif_hwmod;
- static struct omap_hwmod omap44xx_hsi_hwmod;
- static struct omap_hwmod omap44xx_ipu_hwmod;
- static struct omap_hwmod omap44xx_iss_hwmod;
-@@ -70,6 +71,8 @@ static struct omap_hwmod omap44xx_mmc2_hwmod;
- static struct omap_hwmod omap44xx_mpu_hwmod;
- static struct omap_hwmod omap44xx_mpu_private_hwmod;
- static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
-+static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
-+static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
- 
- /*
-  * Interconnects omap_hwmod structures
-@@ -346,6 +349,14 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
- 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
- };
- 
-+/* fdif -> l3_main_2 */
-+static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
-+	.master		= &omap44xx_fdif_hwmod,
-+	.slave		= &omap44xx_l3_main_2_hwmod,
-+	.clk		= "l3_div_ck",
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
- /* hsi -> l3_main_2 */
- static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
- 	.master		= &omap44xx_hsi_hwmod,
-@@ -415,6 +426,7 @@ static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
- /* l3_main_2 slave ports */
- static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
- 	&omap44xx_dma_system__l3_main_2,
-+	&omap44xx_fdif__l3_main_2,
- 	&omap44xx_hsi__l3_main_2,
- 	&omap44xx_ipu__l3_main_2,
- 	&omap44xx_iss__l3_main_2,
-@@ -1029,6 +1041,7 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
- 
- static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
- 	{
-+		.name		= "mpu",
- 		.pa_start	= 0x4012e000,
- 		.pa_end		= 0x4012e07f,
- 		.flags		= ADDR_TYPE_RT
-@@ -1047,6 +1060,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
- 
- static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
- 	{
-+		.name		= "dma",
- 		.pa_start	= 0x4902e000,
- 		.pa_end		= 0x4902e07f,
- 		.flags		= ADDR_TYPE_RT
-@@ -1797,6 +1811,79 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
- };
- 
- /*
-+ * 'fdif' class
-+ * face detection hw accelerator module
-+ */
-+
-+static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
-+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type2,
-+};
-+
-+static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
-+	.name	= "fdif",
-+	.sysc	= &omap44xx_fdif_sysc,
-+};
-+
-+/* fdif */
-+static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
-+	{ .irq = 69 + OMAP44XX_IRQ_GIC_START },
-+	{ .irq = -1 }
-+};
-+
-+/* fdif master ports */
-+static struct omap_hwmod_ocp_if *omap44xx_fdif_masters[] = {
-+	&omap44xx_fdif__l3_main_2,
-+};
-+
-+static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
-+	{
-+		.pa_start	= 0x4a10a000,
-+		.pa_end		= 0x4a10a1ff,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{ }
-+};
-+
-+/* l4_cfg -> fdif */
-+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
-+	.master		= &omap44xx_l4_cfg_hwmod,
-+	.slave		= &omap44xx_fdif_hwmod,
-+	.clk		= "l4_div_ck",
-+	.addr		= omap44xx_fdif_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+/* fdif slave ports */
-+static struct omap_hwmod_ocp_if *omap44xx_fdif_slaves[] = {
-+	&omap44xx_l4_cfg__fdif,
-+};
-+
-+static struct omap_hwmod omap44xx_fdif_hwmod = {
-+	.name		= "fdif",
-+	.class		= &omap44xx_fdif_hwmod_class,
-+	.clkdm_name	= "iss_clkdm",
-+	.mpu_irqs	= omap44xx_fdif_irqs,
-+	.main_clk	= "fdif_fck",
-+	.prcm = {
-+		.omap4 = {
-+			.clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
-+			.context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
-+			.modulemode   = MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.slaves		= omap44xx_fdif_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(omap44xx_fdif_slaves),
-+	.masters	= omap44xx_fdif_masters,
-+	.masters_cnt	= ARRAY_SIZE(omap44xx_fdif_masters),
-+};
-+
-+/*
-  * 'gpio' class
-  * general purpose io module
-  */
-@@ -2246,6 +2333,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
- 			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- 			   SIDLE_SMART_WKUP),
-+	.clockact	= CLOCKACT_TEST_ICLK,
- 	.sysc_fields	= &omap_hwmod_sysc_type1,
- };
- 
-@@ -2300,7 +2388,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
- 	.name		= "i2c1",
- 	.class		= &omap44xx_i2c_hwmod_class,
- 	.clkdm_name	= "l4_per_clkdm",
--	.flags		= HWMOD_16BIT_REG,
-+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- 	.mpu_irqs	= omap44xx_i2c1_irqs,
- 	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
- 	.main_clk	= "i2c1_fck",
-@@ -2356,7 +2444,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
- 	.name		= "i2c2",
- 	.class		= &omap44xx_i2c_hwmod_class,
- 	.clkdm_name	= "l4_per_clkdm",
--	.flags		= HWMOD_16BIT_REG,
-+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- 	.mpu_irqs	= omap44xx_i2c2_irqs,
- 	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
- 	.main_clk	= "i2c2_fck",
-@@ -2412,7 +2500,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
- 	.name		= "i2c3",
- 	.class		= &omap44xx_i2c_hwmod_class,
- 	.clkdm_name	= "l4_per_clkdm",
--	.flags		= HWMOD_16BIT_REG,
-+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- 	.mpu_irqs	= omap44xx_i2c3_irqs,
- 	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,
- 	.main_clk	= "i2c3_fck",
-@@ -2468,7 +2556,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
- 	.name		= "i2c4",
- 	.class		= &omap44xx_i2c_hwmod_class,
- 	.clkdm_name	= "l4_per_clkdm",
--	.flags		= HWMOD_16BIT_REG,
-+	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- 	.mpu_irqs	= omap44xx_i2c4_irqs,
- 	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,
- 	.main_clk	= "i2c4_fck",
-@@ -5276,6 +5364,207 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
- 	.slaves_cnt	= ARRAY_SIZE(omap44xx_wd_timer3_slaves),
- };
- 
-+/*
-+ * 'usb_host_hs' class
-+ * high-speed multi-port usb host controller
-+ */
-+static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
-+	.master		= &omap44xx_usb_host_hs_hwmod,
-+	.slave		= &omap44xx_l3_main_2_hwmod,
-+	.clk		= "l3_div_ck",
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.syss_offs	= 0x0014,
-+	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
-+			   SYSC_HAS_SOFTRESET),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
-+	.sysc_fields	= &omap_hwmod_sysc_type2,
-+};
-+
-+static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
-+	.name = "usb_host_hs",
-+	.sysc = &omap44xx_usb_host_hs_sysc,
-+};
-+
-+static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
-+	&omap44xx_usb_host_hs__l3_main_2,
-+};
-+
-+static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
-+	{
-+		.name		= "uhh",
-+		.pa_start	= 0x4a064000,
-+		.pa_end		= 0x4a0647ff,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{
-+		.name		= "ohci",
-+		.pa_start	= 0x4a064800,
-+		.pa_end		= 0x4a064bff,
-+	},
-+	{
-+		.name		= "ehci",
-+		.pa_start	= 0x4a064c00,
-+		.pa_end		= 0x4a064fff,
-+	},
-+	{}
-+};
-+
-+static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
-+	{ .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
-+	{ .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
-+	.master		= &omap44xx_l4_cfg_hwmod,
-+	.slave		= &omap44xx_usb_host_hs_hwmod,
-+	.clk		= "l4_div_ck",
-+	.addr		= omap44xx_usb_host_hs_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
-+	&omap44xx_l4_cfg__usb_host_hs,
-+};
-+
-+static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
-+	.name		= "usb_host_hs",
-+	.class		= &omap44xx_usb_host_hs_hwmod_class,
-+	.clkdm_name	= "l3_init_clkdm",
-+	.main_clk	= "usb_host_hs_fck",
-+	.prcm = {
-+		.omap4 = {
-+			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
-+			.context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
-+			.modulemode   = MODULEMODE_SWCTRL,
-+		},
-+	},
-+	.mpu_irqs	= omap44xx_usb_host_hs_irqs,
-+	.slaves		= omap44xx_usb_host_hs_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
-+	.masters	= omap44xx_usb_host_hs_masters,
-+	.masters_cnt	= ARRAY_SIZE(omap44xx_usb_host_hs_masters),
-+
-+	/*
-+	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
-+	 * id: i660
-+	 *
-+	 * Description:
-+	 * In the following configuration :
-+	 * - USBHOST module is set to smart-idle mode
-+	 * - PRCM asserts idle_req to the USBHOST module ( This typically
-+	 *   happens when the system is going to a low power mode : all ports
-+	 *   have been suspended, the master part of the USBHOST module has
-+	 *   entered the standby state, and SW has cut the functional clocks)
-+	 * - an USBHOST interrupt occurs before the module is able to answer
-+	 *   idle_ack, typically a remote wakeup IRQ.
-+	 * Then the USB HOST module will enter a deadlock situation where it
-+	 * is no more accessible nor functional.
-+	 *
-+	 * Workaround:
-+	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
-+	 */
-+
-+	/*
-+	 * Errata: USB host EHCI may stall when entering smart-standby mode
-+	 * Id: i571
-+	 *
-+	 * Description:
-+	 * When the USBHOST module is set to smart-standby mode, and when it is
-+	 * ready to enter the standby state (i.e. all ports are suspended and
-+	 * all attached devices are in suspend mode), then it can wrongly assert
-+	 * the Mstandby signal too early while there are still some residual OCP
-+	 * transactions ongoing. If this condition occurs, the internal state
-+	 * machine may go to an undefined state and the USB link may be stuck
-+	 * upon the next resume.
-+	 *
-+	 * Workaround:
-+	 * Don't use smart standby; use only force standby,
-+	 * hence HWMOD_SWSUP_MSTANDBY
-+	 */
-+
-+	/*
-+	 * During system boot; If the hwmod framework resets the module
-+	 * the module will have smart idle settings; which can lead to deadlock
-+	 * (above Errata Id:i660); so, dont reset the module during boot;
-+	 * Use HWMOD_INIT_NO_RESET.
-+	 */
-+
-+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
-+			  HWMOD_INIT_NO_RESET,
-+};
-+
-+/*
-+ * 'usb_tll_hs' class
-+ * usb_tll_hs module is the adapter on the usb_host_hs ports
-+ */
-+static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
-+	.rev_offs	= 0x0000,
-+	.sysc_offs	= 0x0010,
-+	.syss_offs	= 0x0014,
-+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-+			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-+			   SYSC_HAS_AUTOIDLE),
-+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+	.sysc_fields	= &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
-+	.name = "usb_tll_hs",
-+	.sysc = &omap44xx_usb_tll_hs_sysc,
-+};
-+
-+static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
-+	{ .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
-+	{ .irq = -1 }
-+};
-+
-+static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
-+	{
-+		.name		= "tll",
-+		.pa_start	= 0x4a062000,
-+		.pa_end		= 0x4a063fff,
-+		.flags		= ADDR_TYPE_RT
-+	},
-+	{}
-+};
-+
-+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
-+	.master		= &omap44xx_l4_cfg_hwmod,
-+	.slave		= &omap44xx_usb_tll_hs_hwmod,
-+	.clk		= "l4_div_ck",
-+	.addr		= omap44xx_usb_tll_hs_addrs,
-+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-+};
-+
-+static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
-+	&omap44xx_l4_cfg__usb_tll_hs,
-+};
-+
-+static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
-+	.name		= "usb_tll_hs",
-+	.class		= &omap44xx_usb_tll_hs_hwmod_class,
-+	.clkdm_name	= "l3_init_clkdm",
-+	.main_clk	= "usb_tll_hs_ick",
-+	.prcm = {
-+		.omap4 = {
-+			.clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
-+			.context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
-+			.modulemode   = MODULEMODE_HWCTRL,
-+		},
-+	},
-+	.mpu_irqs	= omap44xx_usb_tll_hs_irqs,
-+	.slaves		= omap44xx_usb_tll_hs_slaves,
-+	.slaves_cnt	= ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
-+};
-+
- static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
- 
- 	/* dmm class */
-@@ -5327,6 +5616,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
- 	&omap44xx_dss_rfbi_hwmod,
- 	&omap44xx_dss_venc_hwmod,
- 
-+	/* fdif class */
-+	&omap44xx_fdif_hwmod,
-+
- 	/* gpio class */
- 	&omap44xx_gpio1_hwmod,
- 	&omap44xx_gpio2_hwmod,
-@@ -5415,13 +5707,16 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
- 	&omap44xx_uart3_hwmod,
- 	&omap44xx_uart4_hwmod,
- 
-+	/* usb host class */
-+	&omap44xx_usb_host_hs_hwmod,
-+	&omap44xx_usb_tll_hs_hwmod,
-+
- 	/* usb_otg_hs class */
- 	&omap44xx_usb_otg_hs_hwmod,
- 
- 	/* wd_timer class */
- 	&omap44xx_wd_timer2_hwmod,
- 	&omap44xx_wd_timer3_hwmod,
--
- 	NULL,
- };
- 
-diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
-index 51e5418..063925c 100644
---- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
-@@ -49,6 +49,28 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
- 	.srst_shift	= SYSC_TYPE2_SOFTRESET_SHIFT,
- };
- 
-+/**
-+ * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
-+ * Used by some IPs on AM33xx
-+ */
-+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
-+	.midle_shift	= SYSC_TYPE3_MIDLEMODE_SHIFT,
-+	.sidle_shift	= SYSC_TYPE3_SIDLEMODE_SHIFT,
-+};
-+
-+/**
-+ * struct omap_hwmod_sysc_type4 - TYPE4 sysconfig scheme.
-+ * Used by some IPs on AM33xx
-+ */
-+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4 = {
-+	.midle_shift	= SYSC_TYPE4_MIDLEMODE_SHIFT,
-+	.clkact_shift	= SYSC_TYPE4_CLOCKACTIVITY_SHIFT,
-+	.sidle_shift	= SYSC_TYPE4_SIDLEMODE_SHIFT,
-+	.enwkup_shift	= SYSC_TYPE4_ENAWAKEUP_SHIFT,
-+	.srst_shift	= SYSC_TYPE4_SOFTRESET_SHIFT,
-+	.autoidle_shift	= SYSC_TYPE4_AUTOIDLE_SHIFT,
-+};
-+
- struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
- 	.manager_count		= 2,
- 	.has_framedonetv_irq	= 0
-diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
-index 58775e3..b97a54a 100644
---- a/arch/arm/mach-omap2/omap_phy_internal.c
-+++ b/arch/arm/mach-omap2/omap_phy_internal.c
-@@ -29,6 +29,8 @@
- #include <linux/usb.h>
- 
- #include <plat/usb.h>
-+#include <plat/am33xx.h>
-+#include <plat/ti81xx.h>
- #include "control.h"
- 
- /* OMAP control module register for UTMI PHY */
-@@ -185,7 +187,7 @@ void am35x_musb_reset(void)
- 	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
- }
- 
--void am35x_musb_phy_power(u8 on)
-+void am35x_musb_phy_power(u8 id, u8 on)
- {
- 	unsigned long timeout = jiffies + msecs_to_jiffies(100);
- 	u32 devconf2;
-@@ -260,3 +262,43 @@ void am35x_set_mode(u8 musb_mode)
- 
- 	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
- }
-+
-+void ti81xx_musb_phy_power(u8 id, u8 on)
-+{
-+	void __iomem *scm_base = NULL;
-+	u32 usbphycfg;
-+
-+	if (cpu_is_ti816x())
-+		scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
-+	else if (cpu_is_am33xx())
-+		scm_base = ioremap(AM33XX_SCM_BASE, SZ_2K);
-+
-+	if (!scm_base) {
-+		pr_err("system control module ioremap failed\n");
-+		return;
-+	}
-+
-+	usbphycfg = __raw_readl(scm_base + (id ? USBCTRL1 : USBCTRL0));
-+
-+	if (on) {
-+		if (cpu_is_ti816x()) {
-+			usbphycfg |= id ? TI816X_USBPHY1_NORMAL_MODE :
-+						TI816X_USBPHY0_NORMAL_MODE;
-+			usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
-+		} else if (cpu_is_am33xx()) {
-+			usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN);
-+			usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN);
-+		}
-+	} else {
-+		if (cpu_is_ti816x())
-+			usbphycfg &= ~((id ? TI816X_USBPHY1_NORMAL_MODE :
-+					TI816X_USBPHY0_NORMAL_MODE)
-+					| TI816X_USBPHY_REFCLK_OSC);
-+		else if (cpu_is_am33xx())
-+			usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
-+
-+	}
-+	__raw_writel(usbphycfg, scm_base + (id ? USBCTRL1 : USBCTRL0));
-+
-+	iounmap(scm_base);
-+}
-diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
-index f515a1a..91f3c2e 100644
---- a/arch/arm/mach-omap2/omap_twl.c
-+++ b/arch/arm/mach-omap2/omap_twl.c
-@@ -285,7 +285,7 @@ int __init omap3_twl_init(void)
- {
- 	struct voltagedomain *voltdm;
- 
--	if (!cpu_is_omap34xx())
-+	if (!cpu_is_omap34xx() || cpu_is_am33xx())
- 		return -ENODEV;
- 
- 	if (cpu_is_omap3630()) {
-diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
-index 8affc66..8fae534 100644
---- a/arch/arm/mach-omap2/opp2xxx.h
-+++ b/arch/arm/mach-omap2/opp2xxx.h
-@@ -51,7 +51,7 @@ struct prcm_config {
- 	unsigned long cm_clksel2_pll;	/* dpllx1 or x2 out */
- 	unsigned long cm_clksel_mdm;	/* modem dividers 2430 only */
- 	unsigned long base_sdrc_rfr;	/* base refresh timing for a set */
--	unsigned char flags;
-+	unsigned short flags;
- };
- 
- 
-diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
-index d95f3f9..0e540c8 100644
---- a/arch/arm/mach-omap2/opp3xxx_data.c
-+++ b/arch/arm/mach-omap2/opp3xxx_data.c
-@@ -150,6 +150,26 @@ static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
- 	OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
- };
- 
-+/* 33xx */
-+
-+/* VDD1 */
-+
-+#define AM33XX_VDD_MPU_OPP50_UV		950000
-+#define AM33XX_VDD_MPU_OPP100_UV	1100000
-+#define AM33XX_VDD_MPU_OPP120_UV	1200000
-+#define AM33XX_VDD_MPU_OPPTURBO_UV	1260000
-+
-+static struct omap_opp_def __initdata am33xx_opp_def_list[] = {
-+	/* MPU OPP1 - OPP50 */
-+	OPP_INITIALIZER("mpu", true,  275000000, AM33XX_VDD_MPU_OPP50_UV),
-+	/* MPU OPP2 - OPP100 */
-+	OPP_INITIALIZER("mpu", true,  500000000, AM33XX_VDD_MPU_OPP100_UV),
-+	/* MPU OPP3 - OPP120 */
-+	OPP_INITIALIZER("mpu", true,  600000000, AM33XX_VDD_MPU_OPP120_UV),
-+	/* MPU OPP4 - OPPTurbo */
-+	OPP_INITIALIZER("mpu", true,  720000000, AM33XX_VDD_MPU_OPPTURBO_UV),
-+};
-+
- /**
-  * omap3_opp_init() - initialize omap3 opp table
-  */
-@@ -163,6 +183,9 @@ int __init omap3_opp_init(void)
- 	if (cpu_is_omap3630())
- 		r = omap_init_opp_table(omap36xx_opp_def_list,
- 			ARRAY_SIZE(omap36xx_opp_def_list));
-+	else if (cpu_is_am33xx())
-+		r = omap_init_opp_table(am33xx_opp_def_list,
-+			ARRAY_SIZE(am33xx_opp_def_list));
- 	else
- 		r = omap_init_opp_table(omap34xx_opp_def_list,
- 			ARRAY_SIZE(omap34xx_opp_def_list));
-diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
-index 00bff46..5f98ef8 100644
---- a/arch/arm/mach-omap2/pm.c
-+++ b/arch/arm/mach-omap2/pm.c
-@@ -18,7 +18,7 @@
- 
- #include <plat/omap-pm.h>
- #include <plat/omap_device.h>
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "voltage.h"
- #include "powerdomain.h"
-@@ -198,7 +198,7 @@ exit:
- 
- static void __init omap3_init_voltages(void)
- {
--	if (!cpu_is_omap34xx())
-+	if (!cpu_is_omap34xx() || cpu_is_am33xx())
- 		return;
- 
- 	omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
-diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
-index 4e166ad..68aeafc 100644
---- a/arch/arm/mach-omap2/pm.h
-+++ b/arch/arm/mach-omap2/pm.h
-@@ -21,6 +21,7 @@ extern void omap_sram_idle(void);
- extern int omap3_can_sleep(void);
- extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
- extern int omap3_idle_init(void);
-+extern int omap4_idle_init(void);
- 
- #if defined(CONFIG_PM_OPP)
- extern int omap3_opp_init(void);
-@@ -95,6 +96,15 @@ extern unsigned int save_secure_ram_context_sz;
- 
- extern void omap3_save_scratchpad_contents(void);
- 
-+/* 33xx */
-+/* am33xx_do_wfi function pointer and size, for copy to SRAM */
-+extern void am33xx_do_wfi(void);
-+extern unsigned int am33xx_do_wfi_sz;
-+/* ... and its pointer from SRAM after copy */
-+extern void (*am33xx_do_wfi_sram)(void);
-+/* The resume location */
-+extern void am33xx_resume_vector(void);
-+
- #define PM_RTA_ERRATUM_i608		(1 << 0)
- #define PM_SDRC_WAKEUP_ERRATUM_i583	(1 << 1)
- 
-diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
-index cf0c216..b8822f8 100644
---- a/arch/arm/mach-omap2/pm24xx.c
-+++ b/arch/arm/mach-omap2/pm24xx.c
-@@ -30,7 +30,6 @@
- #include <linux/irq.h>
- #include <linux/time.h>
- #include <linux/gpio.h>
--#include <linux/console.h>
- 
- #include <asm/mach/time.h>
- #include <asm/mach/irq.h>
-@@ -42,6 +41,7 @@
- #include <plat/dma.h>
- #include <plat/board.h>
- 
-+#include "common.h"
- #include "prm2xxx_3xxx.h"
- #include "prm-regbits-24xx.h"
- #include "cm2xxx_3xxx.h"
-@@ -126,27 +126,11 @@ static void omap2_enter_full_retention(void)
- 	if (omap_irq_pending())
- 		goto no_sleep;
- 
--	/* Block console output in case it is on one of the OMAP UARTs */
--	if (!is_suspending())
--		if (!console_trylock())
--			goto no_sleep;
--
--	omap_uart_prepare_idle(0);
--	omap_uart_prepare_idle(1);
--	omap_uart_prepare_idle(2);
--
- 	/* Jump to SRAM suspend code */
- 	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
- 			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
- 			   OMAP_SDRC_REGADDR(SDRC_POWER));
- 
--	omap_uart_resume_idle(2);
--	omap_uart_resume_idle(1);
--	omap_uart_resume_idle(0);
--
--	if (!is_suspending())
--		console_unlock();
--
- no_sleep:
- 	omap2_gpio_resume_after_idle();
- 
-@@ -238,8 +222,6 @@ static int omap2_can_sleep(void)
- {
- 	if (omap2_fclks_active())
- 		return 0;
--	if (!omap_uart_can_sleep())
--		return 0;
- 	if (osc_ck->usecount > 1)
- 		return 0;
- 	if (omap_dma_running())
-@@ -290,7 +272,6 @@ static int omap2_pm_suspend(void)
- 	mir1 = omap_readl(0x480fe0a4);
- 	omap_writel(1 << 5, 0x480fe0ac);
- 
--	omap_uart_prepare_suspend();
- 	omap2_enter_full_retention();
- 
- 	omap_writel(mir1, 0x480fe0a4);
-diff --git a/arch/arm/mach-omap2/pm33xx.c b/arch/arm/mach-omap2/pm33xx.c
-new file mode 100644
-index 0000000..70bcb42
---- /dev/null
-+++ b/arch/arm/mach-omap2/pm33xx.c
-@@ -0,0 +1,569 @@
-+/*
-+ * AM33XX Power Management Routines
-+ *
-+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/clk.h>
-+#include <linux/console.h>
-+#include <linux/err.h>
-+#include <linux/firmware.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/sched.h>
-+#include <linux/suspend.h>
-+#include <linux/completion.h>
-+#include <linux/pm_runtime.h>
-+
-+#include <plat/prcm.h>
-+#include <plat/mailbox.h>
-+#include <plat/sram.h>
-+#include <plat/omap_hwmod.h>
-+#include <plat/omap_device.h>
-+
-+#include <asm/suspend.h>
-+#include <asm/proc-fns.h>
-+#include <asm/sizes.h>
-+
-+#include "pm.h"
-+#include "cm33xx.h"
-+#include "pm33xx.h"
-+#include "control.h"
-+#include "clockdomain.h"
-+#include "powerdomain.h"
-+
-+void (*am33xx_do_wfi_sram)(void);
-+
-+#define DS_MODE		DS0_ID	/* DS0/1_ID */
-+#define MODULE_DISABLE	0x0
-+#define MODULE_ENABLE	0x2
-+
-+#ifdef CONFIG_SUSPEND
-+
-+void __iomem *ipc_regs;
-+void __iomem *m3_eoi;
-+void __iomem *m3_code;
-+
-+bool enable_deep_sleep = true;
-+static suspend_state_t suspend_state = PM_SUSPEND_ON;
-+
-+static struct device *mpu_dev;
-+static struct omap_mbox *m3_mbox;
-+static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm;
-+static struct clockdomain *gfx_l3_clkdm, *gfx_l4ls_clkdm;
-+
-+static struct am33xx_padconf lp_padconf;
-+static int gmii_sel;
-+
-+static int core_suspend_stat = -1;
-+static int m3_state = M3_STATE_UNKNOWN;
-+
-+static int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *);
-+static int am33xx_verify_lp_state(void);
-+static void am33xx_m3_state_machine_reset(void);
-+
-+static DECLARE_COMPLETION(a8_m3_sync);
-+
-+static void save_padconf(void)
-+{
-+	lp_padconf.mii1_col	= readl(AM33XX_CTRL_REGADDR(0x0908));
-+	lp_padconf.mii1_crs	= readl(AM33XX_CTRL_REGADDR(0x090c));
-+	lp_padconf.mii1_rxerr	= readl(AM33XX_CTRL_REGADDR(0x0910));
-+	lp_padconf.mii1_txen	= readl(AM33XX_CTRL_REGADDR(0x0914));
-+	lp_padconf.mii1_rxdv	= readl(AM33XX_CTRL_REGADDR(0x0918));
-+	lp_padconf.mii1_txd3	= readl(AM33XX_CTRL_REGADDR(0x091c));
-+	lp_padconf.mii1_txd2	= readl(AM33XX_CTRL_REGADDR(0x0920));
-+	lp_padconf.mii1_txd1	= readl(AM33XX_CTRL_REGADDR(0x0924));
-+	lp_padconf.mii1_txd0	= readl(AM33XX_CTRL_REGADDR(0x0928));
-+	lp_padconf.mii1_txclk	= readl(AM33XX_CTRL_REGADDR(0x092c));
-+	lp_padconf.mii1_rxclk	= readl(AM33XX_CTRL_REGADDR(0x0930));
-+	lp_padconf.mii1_rxd3	= readl(AM33XX_CTRL_REGADDR(0x0934));
-+	lp_padconf.mii1_rxd2	= readl(AM33XX_CTRL_REGADDR(0x0938));
-+	lp_padconf.mii1_rxd1	= readl(AM33XX_CTRL_REGADDR(0x093c));
-+	lp_padconf.mii1_rxd0	= readl(AM33XX_CTRL_REGADDR(0x0940));
-+	lp_padconf.rmii1_refclk	= readl(AM33XX_CTRL_REGADDR(0x0944));
-+	lp_padconf.mdio_data	= readl(AM33XX_CTRL_REGADDR(0x0948));
-+	lp_padconf.mdio_clk	= readl(AM33XX_CTRL_REGADDR(0x094c));
-+	gmii_sel		= readl(AM33XX_CTRL_REGADDR(0x0650));
-+}
-+
-+static void restore_padconf(void)
-+{
-+	writel(lp_padconf.mii1_col, AM33XX_CTRL_REGADDR(0x0908));
-+	writel(lp_padconf.mii1_crs, AM33XX_CTRL_REGADDR(0x090c));
-+	writel(lp_padconf.mii1_rxerr, AM33XX_CTRL_REGADDR(0x0910));
-+	writel(lp_padconf.mii1_txen, AM33XX_CTRL_REGADDR(0x0914));
-+	writel(lp_padconf.mii1_rxdv, AM33XX_CTRL_REGADDR(0x0918));
-+	writel(lp_padconf.mii1_txd3, AM33XX_CTRL_REGADDR(0x091c));
-+	writel(lp_padconf.mii1_txd2, AM33XX_CTRL_REGADDR(0x0920));
-+	writel(lp_padconf.mii1_txd1, AM33XX_CTRL_REGADDR(0x0924));
-+	writel(lp_padconf.mii1_txd0, AM33XX_CTRL_REGADDR(0x0928));
-+	writel(lp_padconf.mii1_txclk, AM33XX_CTRL_REGADDR(0x092c));
-+	writel(lp_padconf.mii1_rxclk, AM33XX_CTRL_REGADDR(0x0930));
-+	writel(lp_padconf.mii1_rxd3, AM33XX_CTRL_REGADDR(0x0934));
-+	writel(lp_padconf.mii1_rxd2, AM33XX_CTRL_REGADDR(0x0938));
-+	writel(lp_padconf.mii1_rxd1, AM33XX_CTRL_REGADDR(0x093c));
-+	writel(lp_padconf.mii1_rxd0, AM33XX_CTRL_REGADDR(0x0940));
-+	writel(lp_padconf.rmii1_refclk, AM33XX_CTRL_REGADDR(0x0944));
-+	writel(lp_padconf.mdio_data, AM33XX_CTRL_REGADDR(0x0948));
-+	writel(lp_padconf.mdio_clk, AM33XX_CTRL_REGADDR(0x094c));
-+	writel(gmii_sel, AM33XX_CTRL_REGADDR(0x0650));
-+}
-+
-+static int am33xx_pm_prepare_late(void)
-+{
-+	int ret = 0;
-+
-+	save_padconf();
-+
-+	return ret;
-+}
-+
-+static void am33xx_pm_finish(void)
-+{
-+	restore_padconf();
-+}
-+
-+static int am33xx_do_sram_idle(long unsigned int state)
-+{
-+	am33xx_do_wfi_sram();
-+	return 0;
-+}
-+
-+static int am33xx_pm_suspend(void)
-+{
-+	int state, ret = 0;
-+
-+	struct omap_hwmod *cpgmac_oh, *gpmc_oh, *usb_oh;
-+
-+	cpgmac_oh	= omap_hwmod_lookup("cpgmac0");
-+	usb_oh		= omap_hwmod_lookup("usb_otg_hs");
-+	gpmc_oh		= omap_hwmod_lookup("gpmc");
-+
-+	omap_hwmod_enable(cpgmac_oh);
-+	omap_hwmod_enable(usb_oh);
-+	omap_hwmod_enable(gpmc_oh);
-+
-+	omap_hwmod_idle(cpgmac_oh);
-+	omap_hwmod_idle(usb_oh);
-+	omap_hwmod_idle(gpmc_oh);
-+
-+	if (gfx_l3_clkdm && gfx_l4ls_clkdm) {
-+		clkdm_sleep(gfx_l3_clkdm);
-+		clkdm_sleep(gfx_l4ls_clkdm);
-+	}
-+
-+	/* Try to put GFX to sleep */
-+	if (gfx_pwrdm)
-+		pwrdm_set_next_pwrst(gfx_pwrdm, PWRDM_POWER_OFF);
-+	else
-+		pr_err("Could not program GFX to low power state\n");
-+
-+	writel(0x0, AM33XX_CM_MPU_MPU_CLKCTRL);
-+
-+	ret = cpu_suspend(0, am33xx_do_sram_idle);
-+
-+	writel(0x2, AM33XX_CM_MPU_MPU_CLKCTRL);
-+
-+	if (gfx_pwrdm) {
-+		state = pwrdm_read_pwrst(gfx_pwrdm);
-+		if (state != PWRDM_POWER_OFF)
-+			pr_err("GFX domain did not transition to low power state\n");
-+		else
-+			pr_info("GFX domain entered low power state\n");
-+	}
-+
-+	/* XXX: Why do we need to wakeup the clockdomains? */
-+	if(gfx_l3_clkdm && gfx_l4ls_clkdm) {
-+		clkdm_wakeup(gfx_l3_clkdm);
-+		clkdm_wakeup(gfx_l4ls_clkdm);
-+	}
-+
-+	core_suspend_stat = ret;
-+
-+	return ret;
-+}
-+
-+static int am33xx_pm_enter(suspend_state_t unused)
-+{
-+	int ret = 0;
-+
-+	switch (suspend_state) {
-+	case PM_SUSPEND_STANDBY:
-+	case PM_SUSPEND_MEM:
-+		ret = am33xx_pm_suspend();
-+		break;
-+	default:
-+		ret = -EINVAL;
-+	}
-+
-+	return ret;
-+}
-+
-+static int am33xx_pm_begin(suspend_state_t state)
-+{
-+	int ret = 0;
-+
-+	disable_hlt();
-+
-+	am33xx_lp_ipc.resume_addr = DS_RESUME_ADDR;
-+	am33xx_lp_ipc.sleep_mode  = DS_MODE;
-+	am33xx_lp_ipc.ipc_data1	  = DS_IPC_DEFAULT;
-+	am33xx_lp_ipc.ipc_data2   = DS_IPC_DEFAULT;
-+
-+	am33xx_ipc_cmd(&am33xx_lp_ipc);
-+
-+	m3_state = M3_STATE_MSG_FOR_LP;
-+
-+	omap_mbox_enable_irq(m3_mbox, IRQ_RX);
-+
-+	ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
-+	if (ret) {
-+		pr_err("A8<->CM3 MSG for LP failed\n");
-+		am33xx_m3_state_machine_reset();
-+		ret = -1;
-+	}
-+
-+	if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000))) {
-+		pr_err("A8<->CM3 sync failure\n");
-+		am33xx_m3_state_machine_reset();
-+		ret = -1;
-+	} else {
-+		pr_debug("Message sent for entering %s\n",
-+			(DS_MODE == DS0_ID ? "DS0" : "DS1"));
-+		omap_mbox_disable_irq(m3_mbox, IRQ_RX);
-+	}
-+
-+	suspend_state = state;
-+	return ret;
-+}
-+
-+static void am33xx_m3_state_machine_reset(void)
-+{
-+	int ret = 0;
-+
-+	am33xx_lp_ipc.resume_addr = 0x0;
-+	am33xx_lp_ipc.sleep_mode  = 0xe;
-+	am33xx_lp_ipc.ipc_data1	  = DS_IPC_DEFAULT;
-+	am33xx_lp_ipc.ipc_data2   = DS_IPC_DEFAULT;
-+
-+	am33xx_ipc_cmd(&am33xx_lp_ipc);
-+
-+	m3_state = M3_STATE_MSG_FOR_RESET;
-+
-+	ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
-+	if (!ret) {
-+		pr_debug("Message sent for resetting M3 state machine\n");
-+		if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000)))
-+			pr_err("A8<->CM3 sync failure\n");
-+	} else {
-+		pr_err("Could not reset M3 state machine!!!\n");
-+		m3_state = M3_STATE_UNKNOWN;
-+	}
-+}
-+
-+static void am33xx_pm_end(void)
-+{
-+	int ret;
-+
-+	suspend_state = PM_SUSPEND_ON;
-+
-+	ret = am33xx_verify_lp_state();
-+
-+	omap_mbox_enable_irq(m3_mbox, IRQ_RX);
-+
-+	am33xx_m3_state_machine_reset();
-+
-+	enable_hlt();
-+
-+	return;
-+}
-+
-+static const struct platform_suspend_ops am33xx_pm_ops = {
-+	.begin		= am33xx_pm_begin,
-+	.end		= am33xx_pm_end,
-+	.enter		= am33xx_pm_enter,
-+	.valid		= suspend_valid_only_mem,
-+	.prepare	= am33xx_pm_prepare_late,
-+	.finish		= am33xx_pm_finish,
-+};
-+
-+int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *data)
-+{
-+	writel(data->resume_addr, ipc_regs);
-+	writel(data->sleep_mode, ipc_regs + 0x4);
-+	writel(data->ipc_data1, ipc_regs + 0x8);
-+	writel(data->ipc_data2, ipc_regs + 0xc);
-+
-+	return 0;
-+}
-+
-+/* return 0 if no reset M3 needed, 1 otherwise */
-+static int am33xx_verify_lp_state(void)
-+{
-+	int status, ret = 0;
-+
-+	if (core_suspend_stat) {
-+		pr_err("Kernel core reported suspend failure\n");
-+		ret = -1;
-+		goto clear_old_status;
-+	}
-+
-+	status = readl(ipc_regs + 0x4);
-+	status &= 0xffff0000;
-+
-+	if (status == 0x0) {
-+		pr_info("Successfully transitioned all domains to low power state\n");
-+		goto clear_old_status;
-+	} else if (status == 0x10000) {
-+		pr_err("Could not enter low power state\n"
-+			"Please check for active clocks in PER domain\n");
-+		ret = -1;
-+		goto clear_old_status;
-+	} else {
-+		pr_err("Something is terribly wrong :(\nStatus = %0x\n",
-+				status);
-+		ret = -1;
-+	}
-+
-+clear_old_status:
-+	/* After decoding write back the bad status */
-+	status = readl(ipc_regs + 0x4);
-+	status &= 0xffff0000;
-+	status |= 0x10000;
-+	writel(status, ipc_regs + 0x4);
-+
-+	return ret;
-+}
-+
-+/*
-+ * Dummy notifier for the mailbox
-+ * TODO: Can this be completely removed?
-+ */
-+int wkup_m3_mbox_msg(struct notifier_block *self, unsigned long len, void *msg)
-+{
-+	return 0;
-+}
-+
-+static struct notifier_block wkup_m3_mbox_notifier = {
-+	.notifier_call = wkup_m3_mbox_msg,
-+};
-+
-+static irqreturn_t wkup_m3_txev_handler(int irq, void *unused)
-+{
-+	writel(0x1, m3_eoi);
-+
-+	if (m3_state == M3_STATE_RESET) {
-+		m3_state = M3_STATE_INITED;
-+	} else if (m3_state == M3_STATE_MSG_FOR_RESET) {
-+		m3_state = M3_STATE_INITED;
-+		omap_mbox_msg_rx_flush(m3_mbox);
-+		if (m3_mbox->ops->ack_irq)
-+			m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
-+		complete(&a8_m3_sync);
-+	} else if (m3_state == M3_STATE_MSG_FOR_LP) {
-+		omap_mbox_msg_rx_flush(m3_mbox);
-+		if (m3_mbox->ops->ack_irq)
-+			m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
-+		complete(&a8_m3_sync);
-+	} else if (m3_state == M3_STATE_UNKNOWN) {
-+		pr_err("IRQ %d with CM3 in unknown state\n", irq);
-+		omap_mbox_msg_rx_flush(m3_mbox);
-+		if (m3_mbox->ops->ack_irq)
-+			m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
-+		return IRQ_NONE;
-+	}
-+
-+	writel(0x0, m3_eoi);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+/* Initiliaze WKUP_M3, load the binary blob and let it run */
-+static int wkup_m3_init(void)
-+{
-+	struct clk *m3_clk;
-+	struct omap_hwmod *wkup_m3_oh;
-+	const struct firmware *firmware;
-+	int ret = 0;
-+
-+	wkup_m3_oh = omap_hwmod_lookup("wkup_m3");
-+
-+	if (!wkup_m3_oh) {
-+		pr_err("%s: could not find omap_hwmod\n", __func__);
-+		ret = -ENODEV;
-+		goto exit;
-+	}
-+
-+	ipc_regs = ioremap(A8_M3_IPC_REGS, 0x4*8);
-+	if (!ipc_regs) {
-+		pr_err("Could not ioremap the IPC area\b");
-+		ret = -ENOMEM;
-+		goto exit;
-+	}
-+
-+	m3_eoi = ioremap(M3_TXEV_EOI, 0x4);
-+	if (!m3_eoi) {
-+		pr_err("Could not ioremap the EOI register\n");
-+		ret = -ENOMEM;
-+		goto err1;
-+	}
-+
-+	/* Reserve the MBOX for sending messages to M3 */
-+	m3_mbox = omap_mbox_get("wkup_m3", &wkup_m3_mbox_notifier);
-+	if (IS_ERR(m3_mbox)) {
-+		pr_err("Could not reserve mailbox for A8->M3 IPC\n");
-+		ret = -ENODEV;
-+		goto err2;
-+	}
-+
-+	/* Enable access to the M3 code and data area from A8 */
-+	m3_clk = clk_get(NULL, "wkup_m3_fck");
-+	if (IS_ERR(m3_clk)) {
-+		pr_err("%s failed to enable WKUP_M3 clock\n", __func__);
-+		goto err3;
-+	}
-+
-+	if (clk_enable(m3_clk)) {
-+		pr_err("%s WKUP_M3: clock enable Failed\n", __func__);
-+		goto err4;
-+	}
-+
-+	m3_code = ioremap(M3_UMEM, SZ_16K);
-+	if (!m3_code) {
-+		pr_err("%s Could not ioremap M3 code space\n", __func__);
-+		ret = -ENOMEM;
-+		goto err5;
-+	}
-+
-+	pr_info("Trying to load am335x-pm-firmware.bin (60 secs timeout)\n");
-+
-+	ret = request_firmware(&firmware, "am335x-pm-firmware.bin", mpu_dev);
-+	if (ret < 0) {
-+		dev_err(mpu_dev, "request_firmware failed\n");
-+		goto err6;
-+	} else {
-+		memcpy(m3_code, firmware->data, firmware->size);
-+		pr_info("Copied the M3 firmware to UMEM\n");
-+	}
-+
-+	ret = request_irq(AM33XX_IRQ_M3_M3SP_TXEV, wkup_m3_txev_handler,
-+			  IRQF_DISABLED, "wkup_m3_txev", NULL);
-+	if (ret) {
-+		pr_err("%s request_irq failed for 0x%x\n", __func__,
-+			AM33XX_IRQ_M3_M3SP_TXEV);
-+		goto err6;
-+	}
-+
-+	m3_state = M3_STATE_RESET;
-+
-+	ret = omap_hwmod_deassert_hardreset(wkup_m3_oh, "wkup_m3");
-+	if (ret) {
-+		pr_err("Could not deassert the reset for WKUP_M3\n");
-+		goto err6;
-+	} else {
-+		return 0;
-+	}
-+
-+err6:
-+	release_firmware(firmware);
-+	iounmap(m3_code);
-+err5:
-+	clk_disable(m3_clk);
-+err4:
-+	clk_put(m3_clk);
-+err3:
-+	omap_mbox_put(m3_mbox, &wkup_m3_mbox_notifier);
-+err2:
-+	iounmap(m3_eoi);
-+err1:
-+	iounmap(ipc_regs);
-+exit:
-+	return ret;
-+}
-+
-+/*
-+ * Initiate sleep transition for other clockdomains, if
-+ * they are not used
-+ */
-+static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
-+{
-+	if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-+			atomic_read(&clkdm->usecount) == 0)
-+		clkdm_sleep(clkdm);
-+	return 0;
-+}
-+#endif /* CONFIG_SUSPEND */
-+
-+/*
-+ * Push the minimal suspend-resume code to SRAM
-+ */
-+void am33xx_push_sram_idle(void)
-+{
-+	am33xx_do_wfi_sram = omap_sram_push(am33xx_do_wfi, am33xx_do_wfi_sz);
-+}
-+
-+static int __init am33xx_pm_init(void)
-+{
-+	int ret;
-+
-+	if (!cpu_is_am33xx())
-+		return -ENODEV;
-+
-+	pr_info("Power Management for AM33XX family\n");
-+
-+#ifdef CONFIG_SUSPEND
-+	(void) clkdm_for_each(clkdms_setup, NULL);
-+
-+	/* CEFUSE domain should be turned off post bootup */
-+	cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
-+	if (cefuse_pwrdm == NULL)
-+		printk(KERN_ERR "Failed to get cefuse_pwrdm\n");
-+	else
-+		pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF);
-+
-+	gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
-+	if (gfx_pwrdm == NULL)
-+		printk(KERN_ERR "Failed to get gfx_pwrdm\n");
-+
-+	gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm");
-+	if (gfx_l3_clkdm == NULL)
-+		printk(KERN_ERR "Failed to get gfx_l3_clkdm\n");
-+
-+	gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
-+	if (gfx_l4ls_clkdm == NULL)
-+		printk(KERN_ERR "Failed to get gfx_l4ls_gfx_clkdm\n");
-+
-+	mpu_dev = omap_device_get_by_hwmod_name("mpu");
-+
-+	if (!mpu_dev) {
-+		pr_warning("%s: unable to get the mpu device\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	ret = wkup_m3_init();
-+
-+	if (ret) {
-+		pr_err("Could not initialise WKUP_M3. "
-+			"Power management will be compromised\n");
-+		enable_deep_sleep = false;
-+	}
-+
-+	if (enable_deep_sleep)
-+		suspend_set_ops(&am33xx_pm_ops);
-+#endif /* CONFIG_SUSPEND */
-+
-+	return ret;
-+}
-+late_initcall(am33xx_pm_init);
-diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
-new file mode 100644
-index 0000000..f72c28e
---- /dev/null
-+++ b/arch/arm/mach-omap2/pm33xx.h
-@@ -0,0 +1,151 @@
-+/*
-+ * AM33XX Power Management Routines
-+ *
-+ * Copyright (C) 2012 Texas Instruments Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
-+#define __ARCH_ARM_MACH_OMAP2_PM33XX_H
-+
-+#include <mach/hardware.h>	/* XXX Is this the right one to include? */
-+
-+#ifndef __ASSEMBLER__
-+extern void __iomem *am33xx_get_ram_base(void);
-+
-+struct a8_wkup_m3_ipc_data {
-+	int resume_addr;
-+	int sleep_mode;
-+	int ipc_data1;
-+	int ipc_data2;
-+} am33xx_lp_ipc;
-+
-+struct am33xx_padconf {
-+	int	mii1_col;
-+	int	mii1_crs;
-+	int	mii1_rxerr;
-+	int	mii1_txen;
-+	int	mii1_rxdv;
-+	int	mii1_txd3;
-+	int	mii1_txd2;
-+	int	mii1_txd1;
-+	int	mii1_txd0;
-+	int	mii1_txclk;
-+	int	mii1_rxclk;
-+	int	mii1_rxd3;
-+	int	mii1_rxd2;
-+	int	mii1_rxd1;
-+	int	mii1_rxd0;
-+	int	rmii1_refclk;
-+	int	mdio_data;
-+	int	mdio_clk;
-+};
-+#endif /* ASSEMBLER */
-+
-+#define M3_TXEV_EOI			(AM33XX_CTRL_BASE + 0x1324)
-+#define A8_M3_IPC_REGS			(AM33XX_CTRL_BASE + 0x1328)
-+#define DS_RESUME_ADDR			0x40300340
-+#define DS_IPC_DEFAULT			0xffffffff
-+#define M3_UMEM				0x44D00000
-+
-+#define	DS0_ID				0x3
-+#define DS1_ID				0x5
-+
-+#define M3_STATE_UNKNOWN		-1
-+#define M3_STATE_RESET			0
-+#define M3_STATE_INITED			1
-+#define M3_STATE_MSG_FOR_LP		2
-+#define M3_STATE_MSG_FOR_RESET		3
-+
-+/* DDR offsets */
-+#define DDR_CMD0_IOCTRL			(AM33XX_CTRL_BASE + 0x1404)
-+#define DDR_CMD1_IOCTRL			(AM33XX_CTRL_BASE + 0x1408)
-+#define DDR_CMD2_IOCTRL			(AM33XX_CTRL_BASE + 0x140C)
-+#define DDR_DATA0_IOCTRL		(AM33XX_CTRL_BASE + 0x1440)
-+#define DDR_DATA1_IOCTRL		(AM33XX_CTRL_BASE + 0x1444)
-+
-+#define DDR_IO_CTRL			(AM33XX_CTRL_BASE + 0x0E04)
-+#define VTP0_CTRL_REG			(AM33XX_CTRL_BASE + 0x0E0C)
-+#define DDR_CKE_CTRL			(AM33XX_CTRL_BASE + 0x131C)
-+#define DDR_PHY_BASE_ADDR		(AM33XX_CTRL_BASE + 0x2000)
-+
-+#define CMD0_CTRL_SLAVE_RATIO_0		(DDR_PHY_BASE_ADDR + 0x01C)
-+#define CMD0_CTRL_SLAVE_FORCE_0		(DDR_PHY_BASE_ADDR + 0x020)
-+#define CMD0_CTRL_SLAVE_DELAY_0		(DDR_PHY_BASE_ADDR + 0x024)
-+#define CMD0_DLL_LOCK_DIFF_0		(DDR_PHY_BASE_ADDR + 0x028)
-+#define CMD0_INVERT_CLKOUT_0		(DDR_PHY_BASE_ADDR + 0x02C)
-+
-+#define CMD1_CTRL_SLAVE_RATIO_0		(DDR_PHY_BASE_ADDR + 0x050)
-+#define CMD1_CTRL_SLAVE_FORCE_0		(DDR_PHY_BASE_ADDR + 0x054)
-+#define CMD1_CTRL_SLAVE_DELAY_0		(DDR_PHY_BASE_ADDR + 0x058)
-+#define CMD1_DLL_LOCK_DIFF_0		(DDR_PHY_BASE_ADDR + 0x05C)
-+#define CMD1_INVERT_CLKOUT_0		(DDR_PHY_BASE_ADDR + 0x060)
-+
-+#define CMD2_CTRL_SLAVE_RATIO_0		(DDR_PHY_BASE_ADDR + 0x084)
-+#define CMD2_CTRL_SLAVE_FORCE_0		(DDR_PHY_BASE_ADDR + 0x088)
-+#define CMD2_CTRL_SLAVE_DELAY_0		(DDR_PHY_BASE_ADDR + 0x08C)
-+#define CMD2_DLL_LOCK_DIFF_0		(DDR_PHY_BASE_ADDR + 0x090)
-+#define CMD2_INVERT_CLKOUT_0		(DDR_PHY_BASE_ADDR + 0x094)
-+
-+#define DATA0_RD_DQS_SLAVE_RATIO_0	(DDR_PHY_BASE_ADDR + 0x0C8)
-+#define DATA0_RD_DQS_SLAVE_RATIO_1	(DDR_PHY_BASE_ADDR + 0x0CC)
-+
-+#define DATA0_WR_DQS_SLAVE_RATIO_0	(DDR_PHY_BASE_ADDR + 0x0DC)
-+#define DATA0_WR_DQS_SLAVE_RATIO_1	(DDR_PHY_BASE_ADDR + 0x0E0)
-+
-+#define DATA0_WRLVL_INIT_RATIO_0	(DDR_PHY_BASE_ADDR + 0x0F0)
-+#define DATA0_WRLVL_INIT_RATIO_1	(DDR_PHY_BASE_ADDR + 0x0F4)
-+
-+#define DATA0_GATELVL_INIT_RATIO_0	(DDR_PHY_BASE_ADDR + 0x0FC)
-+#define DATA0_GATELVL_INIT_RATIO_1	(DDR_PHY_BASE_ADDR + 0x100)
-+
-+#define DATA0_FIFO_WE_SLAVE_RATIO_0	(DDR_PHY_BASE_ADDR + 0x108)
-+#define DATA0_FIFO_WE_SLAVE_RATIO_1	(DDR_PHY_BASE_ADDR + 0x10C)
-+
-+#define DATA0_WR_DATA_SLAVE_RATIO_0	(DDR_PHY_BASE_ADDR + 0x120)
-+#define DATA0_WR_DATA_SLAVE_RATIO_1	(DDR_PHY_BASE_ADDR + 0x124)
-+
-+#define DATA0_DLL_LOCK_DIFF_0		(DDR_PHY_BASE_ADDR + 0x138)
-+
-+#define DATA0_RANK0_DELAYS_0		(DDR_PHY_BASE_ADDR + 0x134)
-+#define DATA1_RANK0_DELAYS_0		(DDR_PHY_BASE_ADDR + 0x1D8)
-+
-+/* Temp placeholder for the values we want in the registers */
-+#define EMIF_READ_LATENCY	0x100005	/* Enable Dynamic Power Down */
-+#define EMIF_TIM1		0x0666B3C9
-+#define EMIF_TIM2		0x243631CA
-+#define EMIF_TIM3		0x0000033F
-+#define EMIF_SDCFG		0x41805332
-+#define EMIF_SDREF		0x0000081a
-+#define EMIF_SDMGT		0x80000000
-+#define EMIF_SDRAM		0x00004650
-+#define EMIF_PHYCFG		0x2
-+
-+#define DDR2_DLL_LOCK_DIFF	0x0
-+#define DDR2_RD_DQS		0x12
-+#define DDR2_PHY_FIFO_WE	0x80
-+
-+#define DDR_PHY_RESET		(0x1 << 10)
-+#define DDR_PHY_READY		(0x1 << 2)
-+#define DDR2_RATIO		0x80
-+#define CMD_FORCE		0x00
-+#define CMD_DELAY		0x00
-+
-+#define DDR2_INVERT_CLKOUT	0x00
-+#define DDR2_WR_DQS		0x00
-+#define DDR2_PHY_WRLVL		0x00
-+#define DDR2_PHY_GATELVL	0x00
-+#define DDR2_PHY_WR_DATA	0x40
-+#define PHY_RANK0_DELAY		0x01
-+#define PHY_DLL_LOCK_DIFF	0x0
-+#define DDR_IOCTRL_VALUE	0x18B
-+
-+#define VTP_CTRL_READY		(0x1 << 5)
-+#define VTP_CTRL_ENABLE		(0x1 << 6)
-+#define VTP_CTRL_LOCK_EN	(0x1 << 4)
-+#define VTP_CTRL_START_EN	(0x1)
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
-index efa6649..1c2e2eb 100644
---- a/arch/arm/mach-omap2/pm34xx.c
-+++ b/arch/arm/mach-omap2/pm34xx.c
-@@ -28,7 +28,6 @@
- #include <linux/clk.h>
- #include <linux/delay.h>
- #include <linux/slab.h>
--#include <linux/console.h>
- #include <trace/events/power.h>
- 
- #include <asm/suspend.h>
-@@ -36,12 +35,12 @@
- #include <plat/sram.h>
- #include "clockdomain.h"
- #include "powerdomain.h"
--#include <plat/serial.h>
- #include <plat/sdrc.h>
- #include <plat/prcm.h>
- #include <plat/gpmc.h>
- #include <plat/dma.h>
- 
-+#include "common.h"
- #include "cm2xxx_3xxx.h"
- #include "cm-regbits-34xx.h"
- #include "prm-regbits-34xx.h"
-@@ -53,15 +52,6 @@
- 
- #ifdef CONFIG_SUSPEND
- static suspend_state_t suspend_state = PM_SUSPEND_ON;
--static inline bool is_suspending(void)
--{
--	return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
--}
--#else
--static inline bool is_suspending(void)
--{
--	return false;
--}
- #endif
- 
- /* pm34xx errata defined in pm.h */
-@@ -194,7 +184,7 @@ static void omap3_save_secure_ram_context(void)
-  * that any peripheral wake-up events occurring while attempting to
-  * clear the PM_WKST_x are detected and cleared.
-  */
--static int prcm_clear_mod_irqs(s16 module, u8 regs)
-+static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
- {
- 	u32 wkst, fclk, iclk, clken;
- 	u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
-@@ -206,6 +196,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
- 
- 	wkst = omap2_prm_read_mod_reg(module, wkst_off);
- 	wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
-+	wkst &= ~ignore_bits;
- 	if (wkst) {
- 		iclk = omap2_cm_read_mod_reg(module, iclk_off);
- 		fclk = omap2_cm_read_mod_reg(module, fclk_off);
-@@ -221,6 +212,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
- 			omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
- 			omap2_prm_write_mod_reg(wkst, module, wkst_off);
- 			wkst = omap2_prm_read_mod_reg(module, wkst_off);
-+			wkst &= ~ignore_bits;
- 			c++;
- 		}
- 		omap2_cm_write_mod_reg(iclk, module, iclk_off);
-@@ -230,76 +222,35 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
- 	return c;
- }
- 
--static int _prcm_int_handle_wakeup(void)
-+static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
- {
- 	int c;
- 
--	c = prcm_clear_mod_irqs(WKUP_MOD, 1);
--	c += prcm_clear_mod_irqs(CORE_MOD, 1);
--	c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
--	if (omap_rev() > OMAP3430_REV_ES1_0) {
--		c += prcm_clear_mod_irqs(CORE_MOD, 3);
--		c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
--	}
-+	c = prcm_clear_mod_irqs(WKUP_MOD, 1,
-+		~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
- 
--	return c;
-+	return c ? IRQ_HANDLED : IRQ_NONE;
- }
- 
--/*
-- * PRCM Interrupt Handler
-- *
-- * The PRM_IRQSTATUS_MPU register indicates if there are any pending
-- * interrupts from the PRCM for the MPU. These bits must be cleared in
-- * order to clear the PRCM interrupt. The PRCM interrupt handler is
-- * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
-- * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
-- * register indicates that a wake-up event is pending for the MPU and
-- * this bit can only be cleared if the all the wake-up events latched
-- * in the various PM_WKST_x registers have been cleared. The interrupt
-- * handler is implemented using a do-while loop so that if a wake-up
-- * event occurred during the processing of the prcm interrupt handler
-- * (setting a bit in the corresponding PM_WKST_x register and thus
-- * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
-- * this would be handled.
-- */
--static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
-+static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
- {
--	u32 irqenable_mpu, irqstatus_mpu;
--	int c = 0;
--
--	irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
--					 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
--	irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
--					 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
--	irqstatus_mpu &= irqenable_mpu;
--
--	do {
--		if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
--				     OMAP3430_IO_ST_MASK)) {
--			c = _prcm_int_handle_wakeup();
--
--			/*
--			 * Is the MPU PRCM interrupt handler racing with the
--			 * IVA2 PRCM interrupt handler ?
--			 */
--			WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
--			     "but no wakeup sources are marked\n");
--		} else {
--			/* XXX we need to expand our PRCM interrupt handler */
--			WARN(1, "prcm: WARNING: PRCM interrupt received, but "
--			     "no code to handle it (%08x)\n", irqstatus_mpu);
--		}
--
--		omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
--					OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
--
--		irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
--					OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
--		irqstatus_mpu &= irqenable_mpu;
-+	int c;
- 
--	} while (irqstatus_mpu);
-+	/*
-+	 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
-+	 * these are handled in a separate handler to avoid acking
-+	 * IO events before parsing in mux code
-+	 */
-+	c = prcm_clear_mod_irqs(WKUP_MOD, 1,
-+		OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
-+	c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
-+	c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
-+	if (omap_rev() > OMAP3430_REV_ES1_0) {
-+		c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
-+		c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
-+	}
- 
--	return IRQ_HANDLED;
-+	return c ? IRQ_HANDLED : IRQ_NONE;
- }
- 
- static void omap34xx_save_context(u32 *save)
-@@ -375,20 +326,11 @@ void omap_sram_idle(void)
- 			omap3_enable_io_chain();
- 	}
- 
--	/* Block console output in case it is on one of the OMAP UARTs */
--	if (!is_suspending())
--		if (per_next_state < PWRDM_POWER_ON ||
--		    core_next_state < PWRDM_POWER_ON)
--			if (!console_trylock())
--				goto console_still_active;
--
- 	pwrdm_pre_transition();
- 
- 	/* PER */
- 	if (per_next_state < PWRDM_POWER_ON) {
- 		per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
--		omap_uart_prepare_idle(2);
--		omap_uart_prepare_idle(3);
- 		omap2_gpio_prepare_for_idle(per_going_off);
- 		if (per_next_state == PWRDM_POWER_OFF)
- 				omap3_per_save_context();
-@@ -396,8 +338,6 @@ void omap_sram_idle(void)
- 
- 	/* CORE */
- 	if (core_next_state < PWRDM_POWER_ON) {
--		omap_uart_prepare_idle(0);
--		omap_uart_prepare_idle(1);
- 		if (core_next_state == PWRDM_POWER_OFF) {
- 			omap3_core_save_context();
- 			omap3_cm_save_context();
-@@ -446,8 +386,6 @@ void omap_sram_idle(void)
- 			omap3_sram_restore_context();
- 			omap2_sms_restore_context();
- 		}
--		omap_uart_resume_idle(0);
--		omap_uart_resume_idle(1);
- 		if (core_next_state == PWRDM_POWER_OFF)
- 			omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
- 					       OMAP3430_GR_MOD,
-@@ -463,14 +401,8 @@ void omap_sram_idle(void)
- 		omap2_gpio_resume_after_idle();
- 		if (per_prev_state == PWRDM_POWER_OFF)
- 			omap3_per_restore_context();
--		omap_uart_resume_idle(2);
--		omap_uart_resume_idle(3);
- 	}
- 
--	if (!is_suspending())
--		console_unlock();
--
--console_still_active:
- 	/* Disable IO-PAD and IO-CHAIN wakeup */
- 	if (omap3_has_io_wakeup() &&
- 	    (per_next_state < PWRDM_POWER_ON ||
-@@ -484,21 +416,11 @@ console_still_active:
- 	clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
- }
- 
--int omap3_can_sleep(void)
--{
--	if (!omap_uart_can_sleep())
--		return 0;
--	return 1;
--}
--
- static void omap3_pm_idle(void)
- {
- 	local_irq_disable();
- 	local_fiq_disable();
- 
--	if (!omap3_can_sleep())
--		goto out;
--
- 	if (omap_irq_pending() || need_resched())
- 		goto out;
- 
-@@ -532,7 +454,6 @@ static int omap3_pm_suspend(void)
- 			goto restore;
- 	}
- 
--	omap_uart_prepare_suspend();
- 	omap3_intc_suspend();
- 
- 	omap_sram_idle();
-@@ -579,22 +500,27 @@ static int omap3_pm_begin(suspend_state_t state)
- {
- 	disable_hlt();
- 	suspend_state = state;
--	omap_uart_enable_irqs(0);
-+	omap_prcm_irq_prepare();
- 	return 0;
- }
- 
- static void omap3_pm_end(void)
- {
- 	suspend_state = PM_SUSPEND_ON;
--	omap_uart_enable_irqs(1);
- 	enable_hlt();
- 	return;
- }
- 
-+static void omap3_pm_finish(void)
-+{
-+	omap_prcm_irq_complete();
-+}
-+
- static const struct platform_suspend_ops omap_pm_ops = {
- 	.begin		= omap3_pm_begin,
- 	.end		= omap3_pm_end,
- 	.enter		= omap3_pm_enter,
-+	.finish		= omap3_pm_finish,
- 	.valid		= suspend_valid_only_mem,
- };
- #endif /* CONFIG_SUSPEND */
-@@ -679,7 +605,9 @@ static void __init prcm_setup_regs(void)
- 					OMAP3630_GRPSEL_UART4_MASK : 0;
- 
- 	/* XXX This should be handled by hwmod code or SCM init code */
--	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
-+	/* This causes MUSB failure on AM3517 so disable it. */
-+	if (!cpu_is_omap3517() && !cpu_is_omap3505())
-+		omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
- 
- 	/*
- 	 * Enable control of expternal oscillator through
-@@ -700,10 +628,6 @@ static void __init prcm_setup_regs(void)
- 			  OMAP3430_GRPSEL_GPT1_MASK |
- 			  OMAP3430_GRPSEL_GPT12_MASK,
- 			  WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
--	/* For some reason IO doesn't generate wakeup event even if
--	 * it is selected to mpu wakeup goup */
--	omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
--			  OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
- 
- 	/* Enable PM_WKEN to support DSS LPR */
- 	omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
-@@ -868,7 +792,7 @@ static int __init omap3_pm_init(void)
- 	struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
- 	int ret;
- 
--	if (!cpu_is_omap34xx())
-+	if (!cpu_is_omap34xx() || cpu_is_am33xx())
- 		return -ENODEV;
- 
- 	if (!omap3_has_io_chain_ctrl())
-@@ -880,12 +804,21 @@ static int __init omap3_pm_init(void)
- 	 * supervised mode for powerdomains */
- 	prcm_setup_regs();
- 
--	ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
--			  (irq_handler_t)prcm_interrupt_handler,
--			  IRQF_DISABLED, "prcm", NULL);
-+	ret = request_irq(omap_prcm_event_to_irq("wkup"),
-+		_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
-+
-+	if (ret) {
-+		pr_err("pm: Failed to request pm_wkup irq\n");
-+		goto err1;
-+	}
-+
-+	/* IO interrupt is shared with mux code */
-+	ret = request_irq(omap_prcm_event_to_irq("io"),
-+		_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
-+		omap3_pm_init);
-+
- 	if (ret) {
--		printk(KERN_ERR "request_irq failed to register for 0x%x\n",
--		       INT_34XX_PRCM_MPU_IRQ);
-+		pr_err("pm: Failed to request pm_io irq\n");
- 		goto err1;
- 	}
- 
-diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
-index 59a870b..c264ef7 100644
---- a/arch/arm/mach-omap2/pm44xx.c
-+++ b/arch/arm/mach-omap2/pm44xx.c
-@@ -1,8 +1,9 @@
- /*
-  * OMAP4 Power Management Routines
-  *
-- * Copyright (C) 2010 Texas Instruments, Inc.
-+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
-  * Rajendra Nayak <rnayak@ti.com>
-+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License version 2 as
-@@ -16,14 +17,17 @@
- #include <linux/err.h>
- #include <linux/slab.h>
- 
-+#include "common.h"
-+#include "clockdomain.h"
- #include "powerdomain.h"
--#include <mach/omap4-common.h>
-+#include "pm.h"
- 
- struct power_state {
- 	struct powerdomain *pwrdm;
- 	u32 next_state;
- #ifdef CONFIG_SUSPEND
- 	u32 saved_state;
-+	u32 saved_logic_state;
- #endif
- 	struct list_head node;
- };
-@@ -33,7 +37,50 @@ static LIST_HEAD(pwrst_list);
- #ifdef CONFIG_SUSPEND
- static int omap4_pm_suspend(void)
- {
--	do_wfi();
-+	struct power_state *pwrst;
-+	int state, ret = 0;
-+	u32 cpu_id = smp_processor_id();
-+
-+	/* Save current powerdomain state */
-+	list_for_each_entry(pwrst, &pwrst_list, node) {
-+		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
-+		pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
-+	}
-+
-+	/* Set targeted power domain states by suspend */
-+	list_for_each_entry(pwrst, &pwrst_list, node) {
-+		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
-+		pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
-+	}
-+
-+	/*
-+	 * For MPUSS to hit power domain retention(CSWR or OSWR),
-+	 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
-+	 * since CPU power domain CSWR is not supported by hardware
-+	 * Only master CPU follows suspend path. All other CPUs follow
-+	 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
-+	 * domain CSWR is not supported by hardware.
-+	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
-+	 */
-+	omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
-+
-+	/* Restore next powerdomain state */
-+	list_for_each_entry(pwrst, &pwrst_list, node) {
-+		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
-+		if (state > pwrst->next_state) {
-+			pr_info("Powerdomain (%s) didn't enter "
-+			       "target state %d\n",
-+			       pwrst->pwrdm->name, pwrst->next_state);
-+			ret = -1;
-+		}
-+		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
-+		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
-+	}
-+	if (ret)
-+		pr_crit("Could not enter target state in pm_suspend\n");
-+	else
-+		pr_info("Successfully put all powerdomains to target state\n");
-+
- 	return 0;
- }
- 
-@@ -73,6 +120,22 @@ static const struct platform_suspend_ops omap_pm_ops = {
- };
- #endif /* CONFIG_SUSPEND */
- 
-+/*
-+ * Enable hardware supervised mode for all clockdomains if it's
-+ * supported. Initiate sleep transition for other clockdomains, if
-+ * they are not used
-+ */
-+static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
-+{
-+	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-+		clkdm_allow_idle(clkdm);
-+	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-+			atomic_read(&clkdm->usecount) == 0)
-+		clkdm_sleep(clkdm);
-+	return 0;
-+}
-+
-+
- static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
- {
- 	struct power_state *pwrst;
-@@ -80,14 +143,48 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
- 	if (!pwrdm->pwrsts)
- 		return 0;
- 
-+	/*
-+	 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
-+	 * through hotplug path and CPU0 explicitly programmed
-+	 * further down in the code path
-+	 */
-+	if (!strncmp(pwrdm->name, "cpu", 3))
-+		return 0;
-+
-+	/*
-+	 * FIXME: Remove this check when core retention is supported
-+	 * Only MPUSS power domain is added in the list.
-+	 */
-+	if (strcmp(pwrdm->name, "mpu_pwrdm"))
-+		return 0;
-+
- 	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
- 	if (!pwrst)
- 		return -ENOMEM;
-+
- 	pwrst->pwrdm = pwrdm;
--	pwrst->next_state = PWRDM_POWER_ON;
-+	pwrst->next_state = PWRDM_POWER_RET;
- 	list_add(&pwrst->node, &pwrst_list);
- 
--	return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state);
-+	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
-+}
-+
-+/**
-+ * omap_default_idle - OMAP4 default ilde routine.'
-+ *
-+ * Implements OMAP4 memory, IO ordering requirements which can't be addressed
-+ * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
-+ * by secondary CPU with CONFIG_CPUIDLE.
-+ */
-+static void omap_default_idle(void)
-+{
-+	local_irq_disable();
-+	local_fiq_disable();
-+
-+	omap_do_wfi();
-+
-+	local_fiq_enable();
-+	local_irq_enable();
- }
- 
- /**
-@@ -99,10 +196,17 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
- static int __init omap4_pm_init(void)
- {
- 	int ret;
-+	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
-+	struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
- 
- 	if (!cpu_is_omap44xx())
- 		return -ENODEV;
- 
-+	if (omap_rev() == OMAP4430_REV_ES1_0) {
-+		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
-+		return -ENODEV;
-+	}
-+
- 	pr_err("Power Management for TI OMAP4.\n");
- 
- 	ret = pwrdm_for_each(pwrdms_setup, NULL);
-@@ -111,10 +215,51 @@ static int __init omap4_pm_init(void)
- 		goto err2;
- 	}
- 
-+	/*
-+	 * The dynamic dependency between MPUSS -> MEMIF and
-+	 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
-+	 * expected. The hardware recommendation is to enable static
-+	 * dependencies for these to avoid system lock ups or random crashes.
-+	 */
-+	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
-+	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
-+	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
-+	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
-+	l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
-+	ducati_clkdm = clkdm_lookup("ducati_clkdm");
-+	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
-+		(!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
-+		goto err2;
-+
-+	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
-+	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
-+	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
-+	ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
-+	ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
-+	ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
-+	if (ret) {
-+		pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
-+				"wakeup dependency\n");
-+		goto err2;
-+	}
-+
-+	ret = omap4_mpuss_init();
-+	if (ret) {
-+		pr_err("Failed to initialise OMAP4 MPUSS\n");
-+		goto err2;
-+	}
-+
-+	(void) clkdm_for_each(clkdms_setup, NULL);
-+
- #ifdef CONFIG_SUSPEND
- 	suspend_set_ops(&omap_pm_ops);
- #endif /* CONFIG_SUSPEND */
- 
-+	/* Overwrite the default arch_idle() */
-+	pm_idle = omap_default_idle;
-+
-+	omap4_idle_init();
-+
- err2:
- 	return ret;
- }
-diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
-index 0d72a8a..437e51d 100644
---- a/arch/arm/mach-omap2/powerdomain.h
-+++ b/arch/arm/mach-omap2/powerdomain.h
-@@ -67,9 +67,9 @@
- 
- /*
-  * Maximum number of clockdomains that can be associated with a powerdomain.
-- * CORE powerdomain on OMAP4 is the worst case
-+ * CORE powerdomain on AM33XX is the worst case
-  */
--#define PWRDM_MAX_CLKDMS	9
-+#define PWRDM_MAX_CLKDMS	11
- 
- /* XXX A completely arbitrary number. What is reasonable here? */
- #define PWRDM_TRANSITION_BAILOUT 100000
-@@ -92,6 +92,8 @@ struct powerdomain;
-  * @pwrdm_clkdms: Clockdomains in this powerdomain
-  * @node: list_head linking all powerdomains
-  * @voltdm_node: list_head linking all powerdomains in a voltagedomain
-+ * @pwrstctrl_offs: XXX_PWRSTCTRL reg offset from prcm_offs
-+ * @pwrstst_offs: XXX_PWRSTST reg offset from prcm_offs
-  * @state:
-  * @state_counter:
-  * @timer:
-@@ -121,6 +123,8 @@ struct powerdomain {
- 	unsigned ret_logic_off_counter;
- 	unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
- 
-+	u8 pwrstctrl_offs;
-+	u8 pwrstst_offs;
- #ifdef CONFIG_PM_DEBUG
- 	s64 timer;
- 	s64 state_timer[PWRDM_MAX_PWRSTS];
-@@ -223,10 +227,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
- extern void omap242x_powerdomains_init(void);
- extern void omap243x_powerdomains_init(void);
- extern void omap3xxx_powerdomains_init(void);
-+extern void am33xx_powerdomains_init(void);
- extern void omap44xx_powerdomains_init(void);
- 
- extern struct pwrdm_ops omap2_pwrdm_operations;
- extern struct pwrdm_ops omap3_pwrdm_operations;
-+extern struct pwrdm_ops am33xx_pwrdm_operations;
- extern struct pwrdm_ops omap4_pwrdm_operations;
- 
- /* Common Internal functions used across OMAP rev's */
-diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
-index a7880af..b088540 100644
---- a/arch/arm/mach-omap2/powerdomain44xx.c
-+++ b/arch/arm/mach-omap2/powerdomain44xx.c
-@@ -28,7 +28,7 @@ static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
- 	omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
- 					(pwrst << OMAP_POWERSTATE_SHIFT),
- 					pwrdm->prcm_partition,
--					pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
-+					pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
- 	return 0;
- }
- 
-@@ -37,7 +37,7 @@ static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
- 	u32 v;
- 
- 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
--					OMAP4_PM_PWSTCTRL);
-+					pwrdm->pwrstctrl_offs);
- 	v &= OMAP_POWERSTATE_MASK;
- 	v >>= OMAP_POWERSTATE_SHIFT;
- 
-@@ -49,7 +49,7 @@ static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
- 	u32 v;
- 
- 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
--					OMAP4_PM_PWSTST);
-+					pwrdm->pwrstst_offs);
- 	v &= OMAP_POWERSTATEST_MASK;
- 	v >>= OMAP_POWERSTATEST_SHIFT;
- 
-@@ -61,7 +61,7 @@ static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
- 	u32 v;
- 
- 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
--					OMAP4_PM_PWSTST);
-+					pwrdm->pwrstst_offs);
- 	v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
- 	v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
- 
-@@ -73,7 +73,7 @@ static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
- 	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
- 					(1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
- 					pwrdm->prcm_partition,
--					pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
-+					pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
- 	return 0;
- }
- 
-@@ -82,7 +82,7 @@ static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
- 	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
- 					OMAP4430_LASTPOWERSTATEENTERED_MASK,
- 					pwrdm->prcm_partition,
--					pwrdm->prcm_offs, OMAP4_PM_PWSTST);
-+					pwrdm->prcm_offs, pwrdm->pwrstst_offs);
- 	return 0;
- }
- 
-@@ -93,7 +93,7 @@ static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
- 	v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
- 	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
- 					pwrdm->prcm_partition, pwrdm->prcm_offs,
--					OMAP4_PM_PWSTCTRL);
-+					pwrdm->pwrstctrl_offs);
- 
- 	return 0;
- }
-@@ -107,7 +107,7 @@ static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
- 
- 	omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
- 					pwrdm->prcm_partition, pwrdm->prcm_offs,
--					OMAP4_PM_PWSTCTRL);
-+					pwrdm->pwrstctrl_offs);
- 
- 	return 0;
- }
-@@ -131,7 +131,7 @@ static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
- 	u32 v;
- 
- 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
--					OMAP4_PM_PWSTST);
-+					pwrdm->pwrstst_offs);
- 	v &= OMAP4430_LOGICSTATEST_MASK;
- 	v >>= OMAP4430_LOGICSTATEST_SHIFT;
- 
-@@ -157,7 +157,7 @@ static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
- 	m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
- 
- 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
--					OMAP4_PM_PWSTST);
-+					pwrdm->pwrstst_offs);
- 	v &= m;
- 	v >>= __ffs(m);
- 
-@@ -171,7 +171,7 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
- 	m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
- 
- 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
--					OMAP4_PM_PWSTCTRL);
-+					pwrdm->pwrstctrl_offs);
- 	v &= m;
- 	v >>= __ffs(m);
- 
-@@ -191,7 +191,7 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
- 	/* XXX Is this udelay() value meaningful? */
- 	while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
- 					    pwrdm->prcm_offs,
--					    OMAP4_PM_PWSTST) &
-+					    pwrdm->pwrstst_offs) &
- 		OMAP_INTRANSITION_MASK) &&
- 	       (c++ < PWRDM_TRANSITION_BAILOUT))
- 		udelay(1);
-diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
-new file mode 100644
-index 0000000..32a75e5
---- /dev/null
-+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
-@@ -0,0 +1,134 @@
-+/*
-+ * AM33XX Power domains framework
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+
-+#include "powerdomain.h"
-+#include "prcm-common.h"
-+#include "prm33xx.h"
-+#include "prcm44xx.h"
-+
-+static struct powerdomain gfx_33xx_pwrdm = {
-+	.name			= "gfx_pwrdm",
-+	.voltdm			= { .name = "core" },
-+	.prcm_partition		= AM33XX_PRM_PARTITION,
-+	.prcm_offs		= AM33XX_PRM_GFX_MOD,
-+	.pwrsts			= PWRSTS_OFF_ON,
-+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
-+	.pwrstctrl_offs		= AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
-+	.pwrstst_offs		= AM33XX_PM_GFX_PWRSTST_OFFSET,
-+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
-+	.banks			= 1,
-+	.pwrsts_mem_ret		= {
-+		[0]	= PWRSTS_OFF_RET,	/* gfx_mem */
-+	},
-+	.pwrsts_mem_on		= {
-+		[0]	= PWRSTS_ON,		/* gfx_mem */
-+	},
-+};
-+
-+static struct powerdomain rtc_33xx_pwrdm = {
-+	.name			= "rtc_pwrdm",
-+	.voltdm			= { .name = "rtc" },
-+	.prcm_partition		= AM33XX_PRM_PARTITION,
-+	.prcm_offs		= AM33XX_PRM_RTC_MOD,
-+	.pwrsts			= PWRSTS_ON,
-+	.pwrstctrl_offs		= AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
-+	.pwrstst_offs		= AM33XX_PM_RTC_PWRSTST_OFFSET,
-+};
-+
-+static struct powerdomain wkup_33xx_pwrdm = {
-+	.name			= "wkup_pwrdm",
-+	.voltdm			= { .name = "core" },
-+	.prcm_partition		= AM33XX_PRM_PARTITION,
-+	.prcm_offs		= AM33XX_PRM_WKUP_MOD,
-+	.pwrsts			= PWRSTS_ON,
-+	.pwrstctrl_offs		= AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
-+	.pwrstst_offs		= AM33XX_PM_WKUP_PWRSTST_OFFSET,
-+};
-+
-+static struct powerdomain per_33xx_pwrdm = {
-+	.name			= "per_pwrdm",
-+	.voltdm			= { .name = "core" },
-+	.prcm_partition		= AM33XX_PRM_PARTITION,
-+	.prcm_offs		= AM33XX_PRM_PER_MOD,
-+	.pwrsts			= PWRSTS_OFF_RET_ON,
-+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
-+	.pwrstctrl_offs		= AM33XX_PM_PER_PWRSTCTRL_OFFSET,
-+	.pwrstst_offs		= AM33XX_PM_PER_PWRSTST_OFFSET,
-+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
-+	.banks			= 3,
-+	.pwrsts_mem_ret		= {
-+		[0]	= PWRSTS_OFF_RET,	/* pruss_mem */
-+		[1]	= PWRSTS_OFF_RET,	/* per_mem */
-+		[2]	= PWRSTS_OFF_RET,	/* ram_mem */
-+	},
-+	.pwrsts_mem_on		= {
-+		[0]	= PWRSTS_ON,		/* pruss_mem */
-+		[1]	= PWRSTS_ON,		/* per_mem */
-+		[2]	= PWRSTS_ON,		/* ram_mem */
-+	},
-+};
-+
-+static struct powerdomain mpu_33xx_pwrdm = {
-+	.name			= "mpu_pwrdm",
-+	.voltdm			= { .name = "mpu" },
-+	.prcm_partition		= AM33XX_PRM_PARTITION,
-+	.prcm_offs		= AM33XX_PRM_MPU_MOD,
-+	.pwrsts			= PWRSTS_OFF_RET_ON,
-+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
-+	.pwrstctrl_offs		= AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
-+	.pwrstst_offs		= AM33XX_PM_MPU_PWRSTST_OFFSET,
-+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
-+	.banks			= 3,
-+	.pwrsts_mem_ret		= {
-+		[0]	= PWRSTS_OFF_RET,	/* mpu_l1 */
-+		[1]	= PWRSTS_OFF_RET,	/* mpu_l2 */
-+		[2]	= PWRSTS_OFF_RET,	/* mpu_ram */
-+	},
-+	.pwrsts_mem_on		= {
-+		[0]	= PWRSTS_ON,		/* mpu_l1 */
-+		[1]	= PWRSTS_ON,		/* mpu_l2 */
-+		[2]	= PWRSTS_ON,		/* mpu_ram */
-+	},
-+};
-+
-+static struct powerdomain cefuse_33xx_pwrdm = {
-+	.name			= "cefuse_pwrdm",
-+	.voltdm			= { .name = "core" },
-+	.prcm_partition		= AM33XX_PRM_PARTITION,
-+	.prcm_offs		= AM33XX_PRM_CEFUSE_MOD,
-+	.pwrsts			= PWRSTS_OFF_ON,
-+	.pwrstctrl_offs		= AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
-+	.pwrstst_offs		= AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
-+};
-+
-+static struct powerdomain *powerdomains_am33xx[] __initdata = {
-+	&gfx_33xx_pwrdm,
-+	&rtc_33xx_pwrdm,
-+	&wkup_33xx_pwrdm,
-+	&per_33xx_pwrdm,
-+	&mpu_33xx_pwrdm,
-+	&cefuse_33xx_pwrdm,
-+	NULL,
-+};
-+
-+void __init am33xx_powerdomains_init(void)
-+{
-+	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
-+	pwrdm_register_pwrdms(powerdomains_am33xx);
-+	pwrdm_complete_init();
-+}
-diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
-index 704664c..7cf8dcd0 100644
---- a/arch/arm/mach-omap2/powerdomains44xx_data.c
-+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
-@@ -352,7 +352,16 @@ static struct powerdomain *powerdomains_omap44xx[] __initdata = {
- 
- void __init omap44xx_powerdomains_init(void)
- {
-+	int i;
-+
- 	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
-+	/* Initialise PRM reg offs to default value */
-+	for (i = 0; powerdomains_omap44xx[i] != NULL; i++) {
-+		struct powerdomain *pwrdm = powerdomains_omap44xx[i];
-+
-+		pwrdm->pwrstctrl_offs = OMAP4_PM_PWSTCTRL;
-+		pwrdm->pwrstst_offs = OMAP4_PM_PWSTST;
-+	}
- 	pwrdm_register_pwrdms(powerdomains_omap44xx);
- 	pwrdm_complete_init();
- }
-diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
-index 0363dcb..5aa5435 100644
---- a/arch/arm/mach-omap2/prcm-common.h
-+++ b/arch/arm/mach-omap2/prcm-common.h
-@@ -4,7 +4,7 @@
- /*
-  * OMAP2/3 PRCM base and module definitions
-  *
-- * Copyright (C) 2007-2009 Texas Instruments, Inc.
-+ * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
-  * Copyright (C) 2007-2009 Nokia Corporation
-  *
-  * Written by Paul Walmsley
-@@ -201,6 +201,8 @@
- #define OMAP3430_EN_MMC2_SHIFT				25
- #define OMAP3430_EN_MMC1_MASK				(1 << 24)
- #define OMAP3430_EN_MMC1_SHIFT				24
-+#define OMAP3430_EN_UART4_MASK				(1 << 23)
-+#define OMAP3430_EN_UART4_SHIFT				23
- #define OMAP3430_EN_MCSPI4_MASK				(1 << 21)
- #define OMAP3430_EN_MCSPI4_SHIFT			21
- #define OMAP3430_EN_MCSPI3_MASK				(1 << 20)
-@@ -408,6 +410,79 @@
- extern void __iomem *prm_base;
- extern void __iomem *cm_base;
- extern void __iomem *cm2_base;
-+
-+/**
-+ * struct omap_prcm_irq - describes a PRCM interrupt bit
-+ * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
-+ * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
-+ * @priority: should this interrupt be handled before @priority=false IRQs?
-+ *
-+ * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
-+ * On systems with multiple PRM MPU IRQ registers, the bitfields read from
-+ * the registers are concatenated, so @offset could be > 31 on these systems -
-+ * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
-+ * have @priority set to true.
-+ */
-+struct omap_prcm_irq {
-+	const char *name;
-+	unsigned int offset;
-+	bool priority;
-+};
-+
-+/**
-+ * struct omap_prcm_irq_setup - PRCM interrupt controller details
-+ * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
-+ * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
-+ * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
-+ * @nr_irqs: number of entries in the @irqs array
-+ * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
-+ * @irq: MPU IRQ asserted when a PRCM interrupt arrives
-+ * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
-+ * @ocp_barrier: fn ptr to force buffered PRM writes to complete
-+ * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
-+ * @restore_irqen: fn ptr to save and clear IRQENABLE regs
-+ * @saved_mask: IRQENABLE regs are saved here during suspend
-+ * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
-+ * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
-+ * @suspended: set to true after Linux suspend code has called our ->prepare()
-+ * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
-+ *
-+ * @saved_mask, @priority_mask, @base_irq, @suspended, and
-+ * @suspend_save_flag are populated dynamically, and are not to be
-+ * specified in static initializers.
-+ */
-+struct omap_prcm_irq_setup {
-+	u16 ack;
-+	u16 mask;
-+	u8 nr_regs;
-+	u8 nr_irqs;
-+	const struct omap_prcm_irq *irqs;
-+	int irq;
-+	void (*read_pending_irqs)(unsigned long *events);
-+	void (*ocp_barrier)(void);
-+	void (*save_and_clear_irqen)(u32 *saved_mask);
-+	void (*restore_irqen)(u32 *saved_mask);
-+	u32 *saved_mask;
-+	u32 *priority_mask;
-+	int base_irq;
-+	bool suspended;
-+	bool suspend_save_flag;
-+};
-+
-+/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
-+#define OMAP_PRCM_IRQ(_name, _offset, _priority) {	\
-+	.name = _name,					\
-+	.offset = _offset,				\
-+	.priority = _priority				\
-+	}
-+
-+extern void omap_prcm_irq_cleanup(void);
-+extern int omap_prcm_register_chain_handler(
-+	struct omap_prcm_irq_setup *irq_setup);
-+extern int omap_prcm_event_to_irq(const char *event);
-+extern void omap_prcm_irq_prepare(void);
-+extern void omap_prcm_irq_complete(void);
-+
- # endif
- 
- #endif
-diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
-index 597e2da..267d07c 100644
---- a/arch/arm/mach-omap2/prcm.c
-+++ b/arch/arm/mach-omap2/prcm.c
-@@ -26,7 +26,7 @@
- #include <linux/export.h>
- 
- #include <mach/system.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/prcm.h>
- #include <plat/irqs.h>
- 
-@@ -35,6 +35,7 @@
- #include "cm2xxx_3xxx.h"
- #include "prm2xxx_3xxx.h"
- #include "prm44xx.h"
-+#include "prm33xx.h"
- #include "prminst44xx.h"
- #include "prm-regbits-24xx.h"
- #include "prm-regbits-44xx.h"
-@@ -67,6 +68,10 @@ static void omap_prcm_arch_reset(char mode, const char *cmd)
- 		omap2xxx_clk_prepare_for_reboot();
- 
- 		prcm_offs = WKUP_MOD;
-+	} else if (cpu_is_am33xx()) {
-+		prcm_offs = AM33XX_PRM_DEVICE_MOD;
-+		omap2_prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_COLD_SW_MASK,
-+					prcm_offs, AM33XX_PRM_RSTCTRL_OFFSET);
- 	} else if (cpu_is_omap34xx()) {
- 		prcm_offs = OMAP3430_GR_MOD;
- 		omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
-diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
-index 7334ffb..02e5a8b 100644
---- a/arch/arm/mach-omap2/prcm44xx.h
-+++ b/arch/arm/mach-omap2/prcm44xx.h
-@@ -31,6 +31,8 @@
- #define OMAP4430_CM2_PARTITION			3
- #define OMAP4430_SCRM_PARTITION			4
- #define OMAP4430_PRCM_MPU_PARTITION		5
-+/* AM33XX PRCM is closer to OMAP4, so try to reuse all API's */
-+#define AM33XX_PRM_PARTITION			1
- 
- /*
-  * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
-diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
-index 171fe17..ca669b5 100644
---- a/arch/arm/mach-omap2/prcm_mpu44xx.c
-+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
-@@ -15,7 +15,7 @@
- #include <linux/err.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "prcm_mpu44xx.h"
- #include "cm-regbits-44xx.h"
-diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
-new file mode 100644
-index 0000000..f716ae1
---- /dev/null
-+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
-@@ -0,0 +1,357 @@
-+/*
-+ * AM33XX Power Management register bits
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
-+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
-+
-+#include "prm.h"
-+
-+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-+#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT			1
-+#define AM33XX_ABBOFF_ACT_EXPORT_MASK			(1 << 1)
-+
-+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-+#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT		2
-+#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK			(1 << 2)
-+
-+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-+#define AM33XX_AIPOFF_SHIFT				8
-+#define AM33XX_AIPOFF_MASK				(1 << 8)
-+
-+/* Used by PM_WKUP_PWRSTST */
-+#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT		17
-+#define AM33XX_DEBUGSS_MEM_STATEST_MASK			(0x3 << 17)
-+
-+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-+#define AM33XX_DISABLE_RTA_EXPORT_SHIFT			0
-+#define AM33XX_DISABLE_RTA_EXPORT_MASK			(1 << 0)
-+
-+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-+#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT			12
-+#define AM33XX_DPLL_CORE_RECAL_EN_MASK			(1 << 12)
-+
-+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-+#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT			12
-+#define AM33XX_DPLL_CORE_RECAL_ST_MASK			(1 << 12)
-+
-+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-+#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT			14
-+#define AM33XX_DPLL_DDR_RECAL_EN_MASK			(1 << 14)
-+
-+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-+#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT			14
-+#define AM33XX_DPLL_DDR_RECAL_ST_MASK			(1 << 14)
-+
-+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-+#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT			15
-+#define AM33XX_DPLL_DISP_RECAL_EN_MASK			(1 << 15)
-+
-+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-+#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT			13
-+#define AM33XX_DPLL_DISP_RECAL_ST_MASK			(1 << 13)
-+
-+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-+#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT			11
-+#define AM33XX_DPLL_MPU_RECAL_EN_MASK			(1 << 11)
-+
-+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-+#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT			11
-+#define AM33XX_DPLL_MPU_RECAL_ST_MASK			(1 << 11)
-+
-+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-+#define AM33XX_DPLL_PER_RECAL_EN_SHIFT			13
-+#define AM33XX_DPLL_PER_RECAL_EN_MASK			(1 << 13)
-+
-+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-+#define AM33XX_DPLL_PER_RECAL_ST_SHIFT			15
-+#define AM33XX_DPLL_PER_RECAL_ST_MASK			(1 << 15)
-+
-+/* Used by RM_WKUP_RSTST */
-+#define AM33XX_EMULATION_M3_RST_SHIFT			6
-+#define AM33XX_EMULATION_M3_RST_MASK			(1 << 6)
-+
-+/* Used by RM_MPU_RSTST */
-+#define AM33XX_EMULATION_MPU_RST_SHIFT			5
-+#define AM33XX_EMULATION_MPU_RST_MASK			(1 << 5)
-+
-+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-+#define AM33XX_ENFUNC1_EXPORT_SHIFT			3
-+#define AM33XX_ENFUNC1_EXPORT_MASK			(1 << 3)
-+
-+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-+#define AM33XX_ENFUNC3_EXPORT_SHIFT			5
-+#define AM33XX_ENFUNC3_EXPORT_MASK			(1 << 5)
-+
-+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-+#define AM33XX_ENFUNC4_SHIFT				6
-+#define AM33XX_ENFUNC4_MASK				(1 << 6)
-+
-+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
-+#define AM33XX_ENFUNC5_SHIFT				7
-+#define AM33XX_ENFUNC5_MASK				(1 << 7)
-+
-+/* Used by PRM_RSTST */
-+#define AM33XX_EXTERNAL_WARM_RST_SHIFT			5
-+#define AM33XX_EXTERNAL_WARM_RST_MASK			(1 << 5)
-+
-+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-+#define AM33XX_FORCEWKUP_EN_SHIFT			10
-+#define AM33XX_FORCEWKUP_EN_MASK			(1 << 10)
-+
-+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-+#define AM33XX_FORCEWKUP_ST_SHIFT			10
-+#define AM33XX_FORCEWKUP_ST_MASK			(1 << 10)
-+
-+/* Used by PM_GFX_PWRSTCTRL */
-+#define AM33XX_GFX_MEM_ONSTATE_SHIFT			17
-+#define AM33XX_GFX_MEM_ONSTATE_MASK			(0x3 << 17)
-+
-+/* Used by PM_GFX_PWRSTCTRL */
-+#define AM33XX_GFX_MEM_RETSTATE_SHIFT			6
-+#define AM33XX_GFX_MEM_RETSTATE_MASK			(1 << 6)
-+
-+/* Used by PM_GFX_PWRSTST */
-+#define AM33XX_GFX_MEM_STATEST_SHIFT			4
-+#define AM33XX_GFX_MEM_STATEST_MASK			(0x3 << 4)
-+
-+/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
-+#define AM33XX_GFX_RST_SHIFT				0
-+#define AM33XX_GFX_RST_MASK				(1 << 0)
-+
-+/* Used by PRM_RSTST */
-+#define AM33XX_GLOBAL_COLD_RST_SHIFT			0
-+#define AM33XX_GLOBAL_COLD_RST_MASK			(1 << 0)
-+
-+/* Used by PRM_RSTST */
-+#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT			1
-+#define AM33XX_GLOBAL_WARM_SW_RST_MASK			(1 << 1)
-+
-+/* Used by RM_WKUP_RSTST */
-+#define AM33XX_ICECRUSHER_M3_RST_SHIFT			7
-+#define AM33XX_ICECRUSHER_M3_RST_MASK			(1 << 7)
-+
-+/* Used by RM_MPU_RSTST */
-+#define AM33XX_ICECRUSHER_MPU_RST_SHIFT			6
-+#define AM33XX_ICECRUSHER_MPU_RST_MASK			(1 << 6)
-+
-+/* Used by PRM_RSTST */
-+#define AM33XX_ICEPICK_RST_SHIFT			9
-+#define AM33XX_ICEPICK_RST_MASK				(1 << 9)
-+
-+/* Used by RM_PER_RSTCTRL */
-+#define AM33XX_ICSS_LRST_SHIFT				1
-+#define AM33XX_ICSS_LRST_MASK				(1 << 1)
-+
-+/* Used by PM_PER_PWRSTCTRL */
-+#define AM33XX_ICSS_MEM_ONSTATE_SHIFT			5
-+#define AM33XX_ICSS_MEM_ONSTATE_MASK			(0x3 << 5)
-+
-+/* Used by PM_PER_PWRSTCTRL */
-+#define AM33XX_ICSS_MEM_RETSTATE_SHIFT			7
-+#define AM33XX_ICSS_MEM_RETSTATE_MASK			(1 << 7)
-+
-+/* Used by PM_PER_PWRSTST */
-+#define AM33XX_ICSS_MEM_STATEST_SHIFT			23
-+#define AM33XX_ICSS_MEM_STATEST_MASK			(0x3 << 23)
-+
-+/*
-+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
-+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
-+ */
-+#define AM33XX_INTRANSITION_SHIFT			20
-+#define AM33XX_INTRANSITION_MASK			(1 << 20)
-+
-+/* Used by PM_CEFUSE_PWRSTST */
-+#define AM33XX_LASTPOWERSTATEENTERED_SHIFT		24
-+#define AM33XX_LASTPOWERSTATEENTERED_MASK		(0x3 << 24)
-+
-+/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
-+#define AM33XX_LOGICRETSTATE_SHIFT			2
-+#define AM33XX_LOGICRETSTATE_MASK			(1 << 2)
-+
-+/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
-+#define AM33XX_LOGICRETSTATE_3_3_SHIFT			3
-+#define AM33XX_LOGICRETSTATE_3_3_MASK			(1 << 3)
-+
-+/*
-+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
-+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
-+ */
-+#define AM33XX_LOGICSTATEST_SHIFT			2
-+#define AM33XX_LOGICSTATEST_MASK			(1 << 2)
-+
-+/*
-+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
-+ * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
-+ */
-+#define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4
-+#define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4)
-+
-+/* Used by PM_MPU_PWRSTCTRL */
-+#define AM33XX_MPU_L1_ONSTATE_SHIFT			18
-+#define AM33XX_MPU_L1_ONSTATE_MASK			(0x3 << 18)
-+
-+/* Used by PM_MPU_PWRSTCTRL */
-+#define AM33XX_MPU_L1_RETSTATE_SHIFT			22
-+#define AM33XX_MPU_L1_RETSTATE_MASK			(1 << 22)
-+
-+/* Used by PM_MPU_PWRSTST */
-+#define AM33XX_MPU_L1_STATEST_SHIFT			6
-+#define AM33XX_MPU_L1_STATEST_MASK			(0x3 << 6)
-+
-+/* Used by PM_MPU_PWRSTCTRL */
-+#define AM33XX_MPU_L2_ONSTATE_SHIFT			20
-+#define AM33XX_MPU_L2_ONSTATE_MASK			(0x3 << 20)
-+
-+/* Used by PM_MPU_PWRSTCTRL */
-+#define AM33XX_MPU_L2_RETSTATE_SHIFT			23
-+#define AM33XX_MPU_L2_RETSTATE_MASK			(1 << 23)
-+
-+/* Used by PM_MPU_PWRSTST */
-+#define AM33XX_MPU_L2_STATEST_SHIFT			8
-+#define AM33XX_MPU_L2_STATEST_MASK			(0x3 << 8)
-+
-+/* Used by PM_MPU_PWRSTCTRL */
-+#define AM33XX_MPU_RAM_ONSTATE_SHIFT			16
-+#define AM33XX_MPU_RAM_ONSTATE_MASK			(0x3 << 16)
-+
-+/* Used by PM_MPU_PWRSTCTRL */
-+#define AM33XX_MPU_RAM_RETSTATE_SHIFT			24
-+#define AM33XX_MPU_RAM_RETSTATE_MASK			(1 << 24)
-+
-+/* Used by PM_MPU_PWRSTST */
-+#define AM33XX_MPU_RAM_STATEST_SHIFT			4
-+#define AM33XX_MPU_RAM_STATEST_MASK			(0x3 << 4)
-+
-+/* Used by PRM_RSTST */
-+#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT		2
-+#define AM33XX_MPU_SECURITY_VIOL_RST_MASK		(1 << 2)
-+
-+/* Used by PRM_SRAM_COUNT */
-+#define AM33XX_PCHARGECNT_VALUE_SHIFT			0
-+#define AM33XX_PCHARGECNT_VALUE_MASK			(0x3f << 0)
-+
-+/* Used by RM_PER_RSTCTRL */
-+#define AM33XX_PCI_LRST_SHIFT				0
-+#define AM33XX_PCI_LRST_MASK				(1 << 0)
-+
-+/* Renamed from PCI_LRST Used by RM_PER_RSTST */
-+#define AM33XX_PCI_LRST_5_5_SHIFT			5
-+#define AM33XX_PCI_LRST_5_5_MASK			(1 << 5)
-+
-+/* Used by PM_PER_PWRSTCTRL */
-+#define AM33XX_PER_MEM_ONSTATE_SHIFT			25
-+#define AM33XX_PER_MEM_ONSTATE_MASK			(0x3 << 25)
-+
-+/* Used by PM_PER_PWRSTCTRL */
-+#define AM33XX_PER_MEM_RETSTATE_SHIFT			29
-+#define AM33XX_PER_MEM_RETSTATE_MASK			(1 << 29)
-+
-+/* Used by PM_PER_PWRSTST */
-+#define AM33XX_PER_MEM_STATEST_SHIFT			17
-+#define AM33XX_PER_MEM_STATEST_MASK			(0x3 << 17)
-+
-+/*
-+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
-+ * PM_MPU_PWRSTCTRL
-+ */
-+#define AM33XX_POWERSTATE_SHIFT				0
-+#define AM33XX_POWERSTATE_MASK				(0x3 << 0)
-+
-+/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
-+#define AM33XX_POWERSTATEST_SHIFT			0
-+#define AM33XX_POWERSTATEST_MASK			(0x3 << 0)
-+
-+/* Used by PM_PER_PWRSTCTRL */
-+#define AM33XX_RAM_MEM_ONSTATE_SHIFT			30
-+#define AM33XX_RAM_MEM_ONSTATE_MASK			(0x3 << 30)
-+
-+/* Used by PM_PER_PWRSTCTRL */
-+#define AM33XX_RAM_MEM_RETSTATE_SHIFT			27
-+#define AM33XX_RAM_MEM_RETSTATE_MASK			(1 << 27)
-+
-+/* Used by PM_PER_PWRSTST */
-+#define AM33XX_RAM_MEM_STATEST_SHIFT			21
-+#define AM33XX_RAM_MEM_STATEST_MASK			(0x3 << 21)
-+
-+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
-+#define AM33XX_RETMODE_ENABLE_SHIFT			0
-+#define AM33XX_RETMODE_ENABLE_MASK			(1 << 0)
-+
-+/* Used by REVISION_PRM */
-+#define AM33XX_REV_SHIFT				0
-+#define AM33XX_REV_MASK					(0xff << 0)
-+
-+/* Used by PRM_RSTTIME */
-+#define AM33XX_RSTTIME1_SHIFT				0
-+#define AM33XX_RSTTIME1_MASK				(0xff << 0)
-+
-+/* Used by PRM_RSTTIME */
-+#define AM33XX_RSTTIME2_SHIFT				8
-+#define AM33XX_RSTTIME2_MASK				(0x1f << 8)
-+
-+/* Used by PRM_RSTCTRL */
-+#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT			1
-+#define AM33XX_RST_GLOBAL_COLD_SW_MASK			(1 << 1)
-+
-+/* Used by PRM_RSTCTRL */
-+#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT			0
-+#define AM33XX_RST_GLOBAL_WARM_SW_MASK			(1 << 0)
-+
-+/* Used by PRM_SRAM_COUNT */
-+#define AM33XX_SLPCNT_VALUE_SHIFT			16
-+#define AM33XX_SLPCNT_VALUE_MASK			(0xff << 16)
-+
-+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
-+#define AM33XX_SRAMLDO_STATUS_SHIFT			8
-+#define AM33XX_SRAMLDO_STATUS_MASK			(1 << 8)
-+
-+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
-+#define AM33XX_SRAM_IN_TRANSITION_SHIFT			9
-+#define AM33XX_SRAM_IN_TRANSITION_MASK			(1 << 9)
-+
-+/* Used by PRM_SRAM_COUNT */
-+#define AM33XX_STARTUP_COUNT_SHIFT			24
-+#define AM33XX_STARTUP_COUNT_MASK			(0xff << 24)
-+
-+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
-+#define AM33XX_TRANSITION_EN_SHIFT			8
-+#define AM33XX_TRANSITION_EN_MASK			(1 << 8)
-+
-+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
-+#define AM33XX_TRANSITION_ST_SHIFT			8
-+#define AM33XX_TRANSITION_ST_MASK			(1 << 8)
-+
-+/* Used by PRM_SRAM_COUNT */
-+#define AM33XX_VSETUPCNT_VALUE_SHIFT			8
-+#define AM33XX_VSETUPCNT_VALUE_MASK			(0xff << 8)
-+
-+/* Used by PRM_RSTST */
-+#define AM33XX_WDT0_RST_SHIFT				3
-+#define AM33XX_WDT0_RST_MASK				(1 << 3)
-+
-+/* Used by PRM_RSTST */
-+#define AM33XX_WDT1_RST_SHIFT				4
-+#define AM33XX_WDT1_RST_MASK				(1 << 4)
-+
-+/* Used by RM_WKUP_RSTCTRL */
-+#define AM33XX_WKUP_M3_LRST_SHIFT			3
-+#define AM33XX_WKUP_M3_LRST_MASK			(1 << 3)
-+
-+/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
-+#define AM33XX_WKUP_M3_LRST_5_5_SHIFT			5
-+#define AM33XX_WKUP_M3_LRST_5_5_MASK			(1 << 5)
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
-index f02d87f..fa803c6 100644
---- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
-+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
-@@ -1,7 +1,7 @@
- /*
-  * OMAP2/3 PRM module functions
-  *
-- * Copyright (C) 2010 Texas Instruments, Inc.
-+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
-  * Copyright (C) 2010 Nokia Corporation
-  * Benoît Cousson
-  * Paul Walmsley
-@@ -16,7 +16,7 @@
- #include <linux/err.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/cpu.h>
- #include <plat/prcm.h>
- 
-@@ -27,6 +27,24 @@
- #include "prm-regbits-24xx.h"
- #include "prm-regbits-34xx.h"
- 
-+static const struct omap_prcm_irq omap3_prcm_irqs[] = {
-+	OMAP_PRCM_IRQ("wkup",	0,	0),
-+	OMAP_PRCM_IRQ("io",	9,	1),
-+};
-+
-+static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
-+	.ack			= OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
-+	.mask			= OMAP3_PRM_IRQENABLE_MPU_OFFSET,
-+	.nr_regs		= 1,
-+	.irqs			= omap3_prcm_irqs,
-+	.nr_irqs		= ARRAY_SIZE(omap3_prcm_irqs),
-+	.irq			= INT_34XX_PRCM_MPU_IRQ,
-+	.read_pending_irqs	= &omap3xxx_prm_read_pending_irqs,
-+	.ocp_barrier		= &omap3xxx_prm_ocp_barrier,
-+	.save_and_clear_irqen	= &omap3xxx_prm_save_and_clear_irqen,
-+	.restore_irqen		= &omap3xxx_prm_restore_irqen,
-+};
-+
- u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
- {
- 	return __raw_readl(prm_base + module + idx);
-@@ -212,3 +230,80 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
- {
- 	return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
- }
-+
-+/**
-+ * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
-+ * @events: ptr to a u32, preallocated by caller
-+ *
-+ * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
-+ * MPU IRQs, and store the result into the u32 pointed to by @events.
-+ * No return value.
-+ */
-+void omap3xxx_prm_read_pending_irqs(unsigned long *events)
-+{
-+	u32 mask, st;
-+
-+	/* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
-+	mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-+	st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-+
-+	events[0] = mask & st;
-+}
-+
-+/**
-+ * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
-+ *
-+ * Force any buffered writes to the PRM IP block to complete.  Needed
-+ * by the PRM IRQ handler, which reads and writes directly to the IP
-+ * block, to avoid race conditions after acknowledging or clearing IRQ
-+ * bits.  No return value.
-+ */
-+void omap3xxx_prm_ocp_barrier(void)
-+{
-+	omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
-+}
-+
-+/**
-+ * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
-+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
-+ *
-+ * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
-+ * must be allocated by the caller.  Intended to be used in the PRM
-+ * interrupt handler suspend callback.  The OCP barrier is needed to
-+ * ensure the write to disable PRM interrupts reaches the PRM before
-+ * returning; otherwise, spurious interrupts might occur.  No return
-+ * value.
-+ */
-+void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
-+{
-+	saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
-+					       OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-+	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-+
-+	/* OCP barrier */
-+	omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
-+}
-+
-+/**
-+ * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
-+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
-+ *
-+ * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
-+ * to be used in the PRM interrupt handler resume callback to restore
-+ * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
-+ * barrier should be needed here; any pending PRM interrupts will fire
-+ * once the writes reach the PRM.  No return value.
-+ */
-+void omap3xxx_prm_restore_irqen(u32 *saved_mask)
-+{
-+	omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
-+				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-+}
-+
-+static int __init omap3xxx_prcm_init(void)
-+{
-+	if (cpu_is_omap34xx() && !cpu_is_am33xx())
-+		return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
-+	return 0;
-+}
-+subsys_initcall(omap3xxx_prcm_init);
-diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
-index cef533d..70ac2a1 100644
---- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
-+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
-@@ -1,7 +1,7 @@
- /*
-  * OMAP2/3 Power/Reset Management (PRM) register definitions
-  *
-- * Copyright (C) 2007-2009 Texas Instruments, Inc.
-+ * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
-  * Copyright (C) 2008-2010 Nokia Corporation
-  * Paul Walmsley
-  *
-@@ -314,6 +314,13 @@ void omap3_prm_vp_clear_txdone(u8 vp_id);
- extern u32 omap3_prm_vcvp_read(u8 offset);
- extern void omap3_prm_vcvp_write(u32 val, u8 offset);
- extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-+
-+/* PRM interrupt-related functions */
-+extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
-+extern void omap3xxx_prm_ocp_barrier(void);
-+extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
-+extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
-+
- #endif	/* CONFIG_ARCH_OMAP4 */
- 
- #endif
-diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
-new file mode 100644
-index 0000000..aa1e8c7
---- /dev/null
-+++ b/arch/arm/mach-omap2/prm33xx.h
-@@ -0,0 +1,118 @@
-+/*
-+ * AM33XX PRM instance offset macros
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
-+#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
-+
-+#include "prcm-common.h"
-+#include "prm.h"
-+
-+#define AM33XX_PRM_BASE               0x44E00000
-+
-+#define AM33XX_PRM_REGADDR(inst, reg)                         \
-+	AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
-+
-+/* PRM instances */
-+#define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
-+#define AM33XX_PRM_PER_MOD		0x0C00
-+#define AM33XX_PRM_WKUP_MOD		0x0D00
-+#define AM33XX_PRM_MPU_MOD		0x0E00
-+#define AM33XX_PRM_DEVICE_MOD		0x0F00
-+#define AM33XX_PRM_RTC_MOD		0x1000
-+#define AM33XX_PRM_GFX_MOD		0x1100
-+#define AM33XX_PRM_CEFUSE_MOD		0x1200
-+
-+/* PRM */
-+
-+/* PRM.OCP_SOCKET_PRM register offsets */
-+#define AM33XX_REVISION_PRM_OFFSET		0x0000
-+#define AM33XX_REVISION_PRM			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
-+#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET		0x0004
-+#define AM33XX_PRM_IRQSTATUS_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
-+#define AM33XX_PRM_IRQENABLE_MPU_OFFSET		0x0008
-+#define AM33XX_PRM_IRQENABLE_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
-+#define AM33XX_PRM_IRQSTATUS_M3_OFFSET		0x000c
-+#define AM33XX_PRM_IRQSTATUS_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
-+#define AM33XX_PRM_IRQENABLE_M3_OFFSET		0x0010
-+#define AM33XX_PRM_IRQENABLE_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
-+
-+/* PRM.PER_PRM register offsets */
-+#define AM33XX_RM_PER_RSTCTRL_OFFSET		0x0000
-+#define AM33XX_RM_PER_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
-+#define AM33XX_RM_PER_RSTST_OFFSET		0x0004
-+#define AM33XX_RM_PER_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
-+#define AM33XX_PM_PER_PWRSTST_OFFSET		0x0008
-+#define AM33XX_PM_PER_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
-+#define AM33XX_PM_PER_PWRSTCTRL_OFFSET		0x000c
-+#define AM33XX_PM_PER_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
-+
-+/* PRM.WKUP_PRM register offsets */
-+#define AM33XX_RM_WKUP_RSTCTRL_OFFSET		0x0000
-+#define AM33XX_RM_WKUP_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
-+#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET		0x0004
-+#define AM33XX_PM_WKUP_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
-+#define AM33XX_PM_WKUP_PWRSTST_OFFSET		0x0008
-+#define AM33XX_PM_WKUP_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
-+#define AM33XX_RM_WKUP_RSTST_OFFSET		0x000c
-+#define AM33XX_RM_WKUP_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
-+
-+/* PRM.MPU_PRM register offsets */
-+#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET		0x0000
-+#define AM33XX_PM_MPU_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
-+#define AM33XX_PM_MPU_PWRSTST_OFFSET		0x0004
-+#define AM33XX_PM_MPU_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
-+#define AM33XX_RM_MPU_RSTST_OFFSET		0x0008
-+#define AM33XX_RM_MPU_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
-+
-+/* PRM.DEVICE_PRM register offsets */
-+#define AM33XX_PRM_RSTCTRL_OFFSET		0x0000
-+#define AM33XX_PRM_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
-+#define AM33XX_PRM_RSTTIME_OFFSET		0x0004
-+#define AM33XX_PRM_RSTTIME			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
-+#define AM33XX_PRM_RSTST_OFFSET			0x0008
-+#define AM33XX_PRM_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
-+#define AM33XX_PRM_SRAM_COUNT_OFFSET		0x000c
-+#define AM33XX_PRM_SRAM_COUNT			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
-+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET	0x0010
-+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
-+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET	0x0014
-+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
-+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET	0x0018
-+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
-+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET	0x001c
-+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
-+
-+/* PRM.RTC_PRM register offsets */
-+#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET		0x0000
-+#define AM33XX_PM_RTC_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
-+#define AM33XX_PM_RTC_PWRSTST_OFFSET		0x0004
-+#define AM33XX_PM_RTC_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
-+
-+/* PRM.GFX_PRM register offsets */
-+#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET		0x0000
-+#define AM33XX_PM_GFX_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
-+#define AM33XX_RM_GFX_RSTCTRL_OFFSET		0x0004
-+#define AM33XX_RM_GFX_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
-+#define AM33XX_PM_GFX_PWRSTST_OFFSET		0x0010
-+#define AM33XX_PM_GFX_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
-+#define AM33XX_RM_GFX_RSTST_OFFSET		0x0014
-+#define AM33XX_RM_GFX_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
-+
-+/* PRM.CEFUSE_PRM register offsets */
-+#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET	0x0000
-+#define AM33XX_PM_CEFUSE_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
-+#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET		0x0004
-+#define AM33XX_PM_CEFUSE_PWRSTST		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
-+#endif
-diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
-index 495a31a..33dd655 100644
---- a/arch/arm/mach-omap2/prm44xx.c
-+++ b/arch/arm/mach-omap2/prm44xx.c
-@@ -17,7 +17,7 @@
- #include <linux/err.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/cpu.h>
- #include <plat/prcm.h>
- 
-@@ -27,6 +27,24 @@
- #include "prcm44xx.h"
- #include "prminst44xx.h"
- 
-+static const struct omap_prcm_irq omap4_prcm_irqs[] = {
-+	OMAP_PRCM_IRQ("wkup",   0,      0),
-+	OMAP_PRCM_IRQ("io",     9,      1),
-+};
-+
-+static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
-+	.ack			= OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
-+	.mask			= OMAP4_PRM_IRQENABLE_MPU_OFFSET,
-+	.nr_regs		= 2,
-+	.irqs			= omap4_prcm_irqs,
-+	.nr_irqs		= ARRAY_SIZE(omap4_prcm_irqs),
-+	.irq			= OMAP44XX_IRQ_PRCM,
-+	.read_pending_irqs	= &omap44xx_prm_read_pending_irqs,
-+	.ocp_barrier		= &omap44xx_prm_ocp_barrier,
-+	.save_and_clear_irqen	= &omap44xx_prm_save_and_clear_irqen,
-+	.restore_irqen		= &omap44xx_prm_restore_irqen,
-+};
-+
- /* PRM low-level functions */
- 
- /* Read a register in a CM/PRM instance in the PRM module */
-@@ -121,3 +139,101 @@ u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
- 					       OMAP4430_PRM_DEVICE_INST,
- 					       offset);
- }
-+
-+static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
-+{
-+	u32 mask, st;
-+
-+	/* XXX read mask from RAM? */
-+	mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs);
-+	st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs);
-+
-+	return mask & st;
-+}
-+
-+/**
-+ * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
-+ * @events: ptr to two consecutive u32s, preallocated by caller
-+ *
-+ * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
-+ * MPU IRQs, and store the result into the two u32s pointed to by @events.
-+ * No return value.
-+ */
-+void omap44xx_prm_read_pending_irqs(unsigned long *events)
-+{
-+	events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
-+					  OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
-+
-+	events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
-+					  OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
-+}
-+
-+/**
-+ * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
-+ *
-+ * Force any buffered writes to the PRM IP block to complete.  Needed
-+ * by the PRM IRQ handler, which reads and writes directly to the IP
-+ * block, to avoid race conditions after acknowledging or clearing IRQ
-+ * bits.  No return value.
-+ */
-+void omap44xx_prm_ocp_barrier(void)
-+{
-+	omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
-+				OMAP4_REVISION_PRM_OFFSET);
-+}
-+
-+/**
-+ * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
-+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
-+ *
-+ * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
-+ * @saved_mask.  @saved_mask must be allocated by the caller.
-+ * Intended to be used in the PRM interrupt handler suspend callback.
-+ * The OCP barrier is needed to ensure the write to disable PRM
-+ * interrupts reaches the PRM before returning; otherwise, spurious
-+ * interrupts might occur.  No return value.
-+ */
-+void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
-+{
-+	saved_mask[0] =
-+		omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
-+					OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
-+	saved_mask[1] =
-+		omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
-+					OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
-+
-+	omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
-+				 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
-+	omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
-+				 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
-+
-+	/* OCP barrier */
-+	omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
-+				OMAP4_REVISION_PRM_OFFSET);
-+}
-+
-+/**
-+ * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
-+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
-+ *
-+ * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
-+ * @saved_mask.  Intended to be used in the PRM interrupt handler resume
-+ * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
-+ * No OCP barrier should be needed here; any pending PRM interrupts will fire
-+ * once the writes reach the PRM.  No return value.
-+ */
-+void omap44xx_prm_restore_irqen(u32 *saved_mask)
-+{
-+	omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST,
-+				 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
-+	omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST,
-+				 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
-+}
-+
-+static int __init omap4xxx_prcm_init(void)
-+{
-+	if (cpu_is_omap44xx())
-+		return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
-+	return 0;
-+}
-+subsys_initcall(omap4xxx_prcm_init);
-diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
-index 3d66ccd..7978092 100644
---- a/arch/arm/mach-omap2/prm44xx.h
-+++ b/arch/arm/mach-omap2/prm44xx.h
-@@ -1,7 +1,7 @@
- /*
-  * OMAP44xx PRM instance offset macros
-  *
-- * Copyright (C) 2009-2010 Texas Instruments, Inc.
-+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
-  * Copyright (C) 2009-2010 Nokia Corporation
-  *
-  * Paul Walmsley (paul@pwsan.com)
-@@ -763,6 +763,12 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
- extern void omap4_prm_vcvp_write(u32 val, u8 offset);
- extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
- 
-+/* PRM interrupt-related functions */
-+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-+extern void omap44xx_prm_ocp_barrier(void);
-+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
-+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
-+
- # endif
- 
- #endif
-diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
-new file mode 100644
-index 0000000..860118a
---- /dev/null
-+++ b/arch/arm/mach-omap2/prm_common.c
-@@ -0,0 +1,320 @@
-+/*
-+ * OMAP2+ common Power & Reset Management (PRM) IP block functions
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ * Tero Kristo <t-kristo@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ *
-+ * For historical purposes, the API used to configure the PRM
-+ * interrupt handler refers to it as the "PRCM interrupt."  The
-+ * underlying registers are located in the PRM on OMAP3/4.
-+ *
-+ * XXX This code should eventually be moved to a PRM driver.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+
-+#include <mach/system.h>
-+#include <plat/common.h>
-+#include <plat/prcm.h>
-+#include <plat/irqs.h>
-+
-+#include "prm2xxx_3xxx.h"
-+#include "prm44xx.h"
-+
-+/*
-+ * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
-+ * XXX this is technically not needed, since
-+ * omap_prcm_register_chain_handler() could allocate this based on the
-+ * actual amount of memory needed for the SoC
-+ */
-+#define OMAP_PRCM_MAX_NR_PENDING_REG		2
-+
-+/*
-+ * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
-+ * by the PRCM interrupt handler code.  There will be one 'chip' per
-+ * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
-+ * one "chip" and OMAP4 will have two.)
-+ */
-+static struct irq_chip_generic **prcm_irq_chips;
-+
-+/*
-+ * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
-+ * is currently running on.  Defined and passed by initialization code
-+ * that calls omap_prcm_register_chain_handler().
-+ */
-+static struct omap_prcm_irq_setup *prcm_irq_setup;
-+
-+/* Private functions */
-+
-+/*
-+ * Move priority events from events to priority_events array
-+ */
-+static void omap_prcm_events_filter_priority(unsigned long *events,
-+	unsigned long *priority_events)
-+{
-+	int i;
-+
-+	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
-+		priority_events[i] =
-+			events[i] & prcm_irq_setup->priority_mask[i];
-+		events[i] ^= priority_events[i];
-+	}
-+}
-+
-+/*
-+ * PRCM Interrupt Handler
-+ *
-+ * This is a common handler for the OMAP PRCM interrupts. Pending
-+ * interrupts are detected by a call to prcm_pending_events and
-+ * dispatched accordingly. Clearing of the wakeup events should be
-+ * done by the SoC specific individual handlers.
-+ */
-+static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
-+{
-+	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
-+	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
-+	struct irq_chip *chip = irq_desc_get_chip(desc);
-+	unsigned int virtirq;
-+	int nr_irqs = prcm_irq_setup->nr_regs * 32;
-+
-+	/*
-+	 * If we are suspended, mask all interrupts from PRCM level,
-+	 * this does not ack them, and they will be pending until we
-+	 * re-enable the interrupts, at which point the
-+	 * omap_prcm_irq_handler will be executed again.  The
-+	 * _save_and_clear_irqen() function must ensure that the PRM
-+	 * write to disable all IRQs has reached the PRM before
-+	 * returning, or spurious PRCM interrupts may occur during
-+	 * suspend.
-+	 */
-+	if (prcm_irq_setup->suspended) {
-+		prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
-+		prcm_irq_setup->suspend_save_flag = true;
-+	}
-+
-+	/*
-+	 * Loop until all pending irqs are handled, since
-+	 * generic_handle_irq() can cause new irqs to come
-+	 */
-+	while (!prcm_irq_setup->suspended) {
-+		prcm_irq_setup->read_pending_irqs(pending);
-+
-+		/* No bit set, then all IRQs are handled */
-+		if (find_first_bit(pending, nr_irqs) >= nr_irqs)
-+			break;
-+
-+		omap_prcm_events_filter_priority(pending, priority_pending);
-+
-+		/*
-+		 * Loop on all currently pending irqs so that new irqs
-+		 * cannot starve previously pending irqs
-+		 */
-+
-+		/* Serve priority events first */
-+		for_each_set_bit(virtirq, priority_pending, nr_irqs)
-+			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
-+
-+		/* Serve normal events next */
-+		for_each_set_bit(virtirq, pending, nr_irqs)
-+			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
-+	}
-+	if (chip->irq_ack)
-+		chip->irq_ack(&desc->irq_data);
-+	if (chip->irq_eoi)
-+		chip->irq_eoi(&desc->irq_data);
-+	chip->irq_unmask(&desc->irq_data);
-+
-+	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
-+}
-+
-+/* Public functions */
-+
-+/**
-+ * omap_prcm_event_to_irq - given a PRCM event name, returns the
-+ * corresponding IRQ on which the handler should be registered
-+ * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
-+ *
-+ * Returns the Linux internal IRQ ID corresponding to @name upon success,
-+ * or -ENOENT upon failure.
-+ */
-+int omap_prcm_event_to_irq(const char *name)
-+{
-+	int i;
-+
-+	if (!prcm_irq_setup || !name)
-+		return -ENOENT;
-+
-+	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
-+		if (!strcmp(prcm_irq_setup->irqs[i].name, name))
-+			return prcm_irq_setup->base_irq +
-+				prcm_irq_setup->irqs[i].offset;
-+
-+	return -ENOENT;
-+}
-+
-+/**
-+ * omap_prcm_irq_cleanup - reverses memory allocated and other steps
-+ * done by omap_prcm_register_chain_handler()
-+ *
-+ * No return value.
-+ */
-+void omap_prcm_irq_cleanup(void)
-+{
-+	int i;
-+
-+	if (!prcm_irq_setup) {
-+		pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
-+		return;
-+	}
-+
-+	if (prcm_irq_chips) {
-+		for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
-+			if (prcm_irq_chips[i])
-+				irq_remove_generic_chip(prcm_irq_chips[i],
-+					0xffffffff, 0, 0);
-+			prcm_irq_chips[i] = NULL;
-+		}
-+		kfree(prcm_irq_chips);
-+		prcm_irq_chips = NULL;
-+	}
-+
-+	kfree(prcm_irq_setup->saved_mask);
-+	prcm_irq_setup->saved_mask = NULL;
-+
-+	kfree(prcm_irq_setup->priority_mask);
-+	prcm_irq_setup->priority_mask = NULL;
-+
-+	irq_set_chained_handler(prcm_irq_setup->irq, NULL);
-+
-+	if (prcm_irq_setup->base_irq > 0)
-+		irq_free_descs(prcm_irq_setup->base_irq,
-+			prcm_irq_setup->nr_regs * 32);
-+	prcm_irq_setup->base_irq = 0;
-+}
-+
-+void omap_prcm_irq_prepare(void)
-+{
-+	prcm_irq_setup->suspended = true;
-+}
-+
-+void omap_prcm_irq_complete(void)
-+{
-+	prcm_irq_setup->suspended = false;
-+
-+	/* If we have not saved the masks, do not attempt to restore */
-+	if (!prcm_irq_setup->suspend_save_flag)
-+		return;
-+
-+	prcm_irq_setup->suspend_save_flag = false;
-+
-+	/*
-+	 * Re-enable all masked PRCM irq sources, this causes the PRCM
-+	 * interrupt to fire immediately if the events were masked
-+	 * previously in the chain handler
-+	 */
-+	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
-+}
-+
-+/**
-+ * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
-+ * handler based on provided parameters
-+ * @irq_setup: hardware data about the underlying PRM/PRCM
-+ *
-+ * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
-+ * one generic IRQ chip per PRM interrupt status/enable register pair.
-+ * Returns 0 upon success, -EINVAL if called twice or if invalid
-+ * arguments are passed, or -ENOMEM on any other error.
-+ */
-+int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
-+{
-+	int nr_regs = irq_setup->nr_regs;
-+	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
-+	int offset, i;
-+	struct irq_chip_generic *gc;
-+	struct irq_chip_type *ct;
-+
-+	if (!irq_setup)
-+		return -EINVAL;
-+
-+	if (prcm_irq_setup) {
-+		pr_err("PRCM: already initialized; won't reinitialize\n");
-+		return -EINVAL;
-+	}
-+
-+	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
-+		pr_err("PRCM: nr_regs too large\n");
-+		return -EINVAL;
-+	}
-+
-+	prcm_irq_setup = irq_setup;
-+
-+	prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
-+	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
-+	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
-+		GFP_KERNEL);
-+
-+	if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
-+	    !prcm_irq_setup->priority_mask) {
-+		pr_err("PRCM: kzalloc failed\n");
-+		goto err;
-+	}
-+
-+	memset(mask, 0, sizeof(mask));
-+
-+	for (i = 0; i < irq_setup->nr_irqs; i++) {
-+		offset = irq_setup->irqs[i].offset;
-+		mask[offset >> 5] |= 1 << (offset & 0x1f);
-+		if (irq_setup->irqs[i].priority)
-+			irq_setup->priority_mask[offset >> 5] |=
-+				1 << (offset & 0x1f);
-+	}
-+
-+	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
-+
-+	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
-+		0);
-+
-+	if (irq_setup->base_irq < 0) {
-+		pr_err("PRCM: failed to allocate irq descs: %d\n",
-+			irq_setup->base_irq);
-+		goto err;
-+	}
-+
-+	for (i = 0; i <= irq_setup->nr_regs; i++) {
-+		gc = irq_alloc_generic_chip("PRCM", 1,
-+			irq_setup->base_irq + i * 32, prm_base,
-+			handle_level_irq);
-+
-+		if (!gc) {
-+			pr_err("PRCM: failed to allocate generic chip\n");
-+			goto err;
-+		}
-+		ct = gc->chip_types;
-+		ct->chip.irq_ack = irq_gc_ack_set_bit;
-+		ct->chip.irq_mask = irq_gc_mask_clr_bit;
-+		ct->chip.irq_unmask = irq_gc_mask_set_bit;
-+
-+		ct->regs.ack = irq_setup->ack + i * 4;
-+		ct->regs.mask = irq_setup->mask + i * 4;
-+
-+		irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
-+		prcm_irq_chips[i] = gc;
-+	}
-+
-+	return 0;
-+
-+err:
-+	omap_prcm_irq_cleanup();
-+	return -ENOMEM;
-+}
-diff --git a/arch/arm/mach-omap2/prminst33xx.h b/arch/arm/mach-omap2/prminst33xx.h
-new file mode 100644
-index 0000000..c9a2ba5
---- /dev/null
-+++ b/arch/arm/mach-omap2/prminst33xx.h
-@@ -0,0 +1,29 @@
-+/*
-+ * AM33XX Power/Reset Management (PRM) function prototypes
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ARCH_ASM_MACH_OMAP2_PRMINST33XX_H
-+#define __ARCH_ASM_MACH_OMAP2_PRMINST33XX_H
-+
-+extern u32 am33xx_prminst_read_inst_reg(s16 inst, u16 idx);
-+extern void am33xx_prminst_write_inst_reg(u32 val, s16 inst, u16 idx);
-+extern u32 am33xx_prminst_rmw_inst_reg_bits(u32 mask, u32 bits,
-+					   s16 inst, s16 idx);
-+extern u32 am33xx_prminst_is_hardreset_asserted(s16 domain, s16 idx, u32 mask);
-+extern int am33xx_prminst_assert_hardreset(s16 prm_mod, u8 shift);
-+extern int am33xx_prminst_deassert_hardreset(s16 prm_mod, u8 rst_shift,
-+					u8 st_shift);
-+extern void am33xx_prm_global_warm_sw_reset(void);
-+
-+#endif
-diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
-index 3a7bab1..5fd13b4 100644
---- a/arch/arm/mach-omap2/prminst44xx.c
-+++ b/arch/arm/mach-omap2/prminst44xx.c
-@@ -16,40 +16,48 @@
- #include <linux/err.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "prm44xx.h"
-+#include "prm33xx.h"
- #include "prminst44xx.h"
- #include "prm-regbits-44xx.h"
- #include "prcm44xx.h"
- #include "prcm_mpu44xx.h"
- 
--static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
-+static u32 **_prm_bases;
-+static u32 max_prm_partitions;
-+
-+static u32 *omap44xx_prm_bases[] = {
- 	[OMAP4430_INVALID_PRCM_PARTITION]	= 0,
--	[OMAP4430_PRM_PARTITION]		= OMAP4430_PRM_BASE,
-+	[OMAP4430_PRM_PARTITION]		= OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
- 	[OMAP4430_CM1_PARTITION]		= 0,
- 	[OMAP4430_CM2_PARTITION]		= 0,
- 	[OMAP4430_SCRM_PARTITION]		= 0,
--	[OMAP4430_PRCM_MPU_PARTITION]		= OMAP4430_PRCM_MPU_BASE,
-+	[OMAP4430_PRCM_MPU_PARTITION]		= OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
-+};
-+
-+static u32 *am33xx_prm_bases[] = {
-+	[OMAP4430_INVALID_PRCM_PARTITION]	= 0,
-+	[AM33XX_PRM_PARTITION]			= AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE),
- };
- 
- /* Read a register in a PRM instance */
- u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
- {
--	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
-+	BUG_ON(part >= max_prm_partitions ||
- 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
- 	       !_prm_bases[part]);
--	return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst +
--					       idx));
-+	return __raw_readl(_prm_bases[part] + ((inst + idx)/sizeof(u32)));
- }
- 
- /* Write into a register in a PRM instance */
- void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
- {
--	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
-+	BUG_ON(part >= max_prm_partitions ||
- 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
- 	       !_prm_bases[part]);
--	__raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx));
-+	__raw_writel(val, _prm_bases[part] + ((inst + idx)/sizeof(u32)));
- }
- 
- /* Read-modify-write a register in PRM. Caller must lock */
-@@ -174,3 +182,14 @@ void omap4_prminst_global_warm_sw_reset(void)
- 				    OMAP4430_PRM_DEVICE_INST,
- 				    OMAP4_PRM_RSTCTRL_OFFSET);
- }
-+
-+void __init omap44xx_prminst_init(void)
-+{
-+	if (cpu_is_omap44xx()) {
-+		_prm_bases = omap44xx_prm_bases;
-+		max_prm_partitions = ARRAY_SIZE(omap44xx_prm_bases);
-+	} else if (cpu_is_am33xx()) {
-+		_prm_bases = am33xx_prm_bases;
-+		max_prm_partitions = ARRAY_SIZE(am33xx_prm_bases);
-+	}
-+}
-diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
-index 46f2efb..9a44c68 100644
---- a/arch/arm/mach-omap2/prminst44xx.h
-+++ b/arch/arm/mach-omap2/prminst44xx.h
-@@ -29,5 +29,5 @@ extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
- 					  u16 rstctrl_offs);
- extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
- 					    u16 rstctrl_offs);
--
-+extern void __init omap44xx_prminst_init(void);
- #endif
-diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
-index 14caa22..7479d7e 100644
---- a/arch/arm/mach-omap2/sdram-nokia.c
-+++ b/arch/arm/mach-omap2/sdram-nokia.c
-@@ -1,7 +1,7 @@
- /*
-  * SDRC register values for Nokia boards
-  *
-- * Copyright (C) 2008, 2010 Nokia Corporation
-+ * Copyright (C) 2008, 2010-2011 Nokia Corporation
-  *
-  * Lauri Leukkunen <lauri.leukkunen@nokia.com>
-  *
-@@ -18,7 +18,7 @@
- #include <linux/io.h>
- 
- #include <plat/io.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/clock.h>
- #include <plat/sdrc.h>
- 
-@@ -107,14 +107,37 @@ static const struct sdram_timings nokia_195dot2mhz_timings[] = {
- 	},
- };
- 
-+static const struct sdram_timings nokia_200mhz_timings[] = {
-+	{
-+		.casl = 3,
-+		.tDAL = 30000,
-+		.tDPL = 15000,
-+		.tRRD = 10000,
-+		.tRCD = 20000,
-+		.tRP = 15000,
-+		.tRAS = 40000,
-+		.tRC = 55000,
-+		.tRFC = 140000,
-+		.tXSR = 200000,
-+
-+		.tREF = 7800,
-+
-+		.tXP = 2,
-+		.tCKE = 4,
-+		.tWTR = 2
-+	},
-+};
-+
- static const struct {
- 	long rate;
- 	struct sdram_timings const *data;
- } nokia_timings[] = {
- 	{ 83000000, nokia_166mhz_timings },
- 	{ 97600000, nokia_97dot6mhz_timings },
-+	{ 100000000, nokia_200mhz_timings },
- 	{ 166000000, nokia_166mhz_timings },
- 	{ 195200000, nokia_195dot2mhz_timings },
-+	{ 200000000, nokia_200mhz_timings },
- };
- static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
- 
-diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
-index 8f27828..e3d345f 100644
---- a/arch/arm/mach-omap2/sdrc.c
-+++ b/arch/arm/mach-omap2/sdrc.c
-@@ -23,7 +23,7 @@
- #include <linux/clk.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/clock.h>
- #include <plat/sram.h>
- 
-diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
-index ccdb010..791a63c 100644
---- a/arch/arm/mach-omap2/sdrc2xxx.c
-+++ b/arch/arm/mach-omap2/sdrc2xxx.c
-@@ -24,7 +24,7 @@
- #include <linux/clk.h>
- #include <linux/io.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/clock.h>
- #include <plat/sram.h>
- 
-diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
-index 9992dbf..bfa8ae3 100644
---- a/arch/arm/mach-omap2/serial.c
-+++ b/arch/arm/mach-omap2/serial.c
-@@ -19,26 +19,21 @@
-  */
- #include <linux/kernel.h>
- #include <linux/init.h>
--#include <linux/serial_reg.h>
- #include <linux/clk.h>
- #include <linux/io.h>
- #include <linux/delay.h>
- #include <linux/platform_device.h>
- #include <linux/slab.h>
--#include <linux/serial_8250.h>
- #include <linux/pm_runtime.h>
- #include <linux/console.h>
- 
--#ifdef CONFIG_SERIAL_OMAP
- #include <plat/omap-serial.h>
--#endif
--
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/board.h>
--#include <plat/clock.h>
- #include <plat/dma.h>
- #include <plat/omap_hwmod.h>
- #include <plat/omap_device.h>
-+#include <plat/omap-pm.h>
- 
- #include "prm2xxx_3xxx.h"
- #include "pm.h"
-@@ -47,603 +42,226 @@
- #include "control.h"
- #include "mux.h"
- 
--#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV	0x52
--#define UART_OMAP_WER		0x17	/* Wake-up enable register */
--
--#define UART_ERRATA_FIFO_FULL_ABORT	(0x1 << 0)
--#define UART_ERRATA_i202_MDR1_ACCESS	(0x1 << 1)
--
- /*
-- * NOTE: By default the serial timeout is disabled as it causes lost characters
-- * over the serial ports. This means that the UART clocks will stay on until
-- * disabled via sysfs. This also causes that any deeper omap sleep states are
-- * blocked. 
-+ * NOTE: By default the serial auto_suspend timeout is disabled as it causes
-+ * lost characters over the serial ports. This means that the UART clocks will
-+ * stay on until power/autosuspend_delay is set for the uart from sysfs.
-+ * This also causes that any deeper omap sleep states are blocked.
-  */
--#define DEFAULT_TIMEOUT 0
-+#define DEFAULT_AUTOSUSPEND_DELAY	-1
- 
- #define MAX_UART_HWMOD_NAME_LEN		16
- 
- struct omap_uart_state {
- 	int num;
- 	int can_sleep;
--	struct timer_list timer;
--	u32 timeout;
--
--	void __iomem *wk_st;
--	void __iomem *wk_en;
--	u32 wk_mask;
--	u32 padconf;
--	u32 dma_enabled;
--
--	struct clk *ick;
--	struct clk *fck;
--	int clocked;
--
--	int irq;
--	int regshift;
--	int irqflags;
--	void __iomem *membase;
--	resource_size_t mapbase;
- 
- 	struct list_head node;
- 	struct omap_hwmod *oh;
- 	struct platform_device *pdev;
--
--	u32 errata;
--#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
--	int context_valid;
--
--	/* Registers to be saved/restored for OFF-mode */
--	u16 dll;
--	u16 dlh;
--	u16 ier;
--	u16 sysc;
--	u16 scr;
--	u16 wer;
--	u16 mcr;
--#endif
- };
- 
- static LIST_HEAD(uart_list);
- static u8 num_uarts;
-+static u8 console_uart_id = -1;
-+static u8 no_console_suspend;
-+static u8 uart_debug;
-+
-+#define DEFAULT_RXDMA_POLLRATE		1	/* RX DMA polling rate (us) */
-+#define DEFAULT_RXDMA_BUFSIZE		4096	/* RX DMA buffer size */
-+#define DEFAULT_RXDMA_TIMEOUT		(3 * HZ)/* RX DMA timeout (jiffies) */
-+
-+static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
-+	{
-+		.dma_enabled	= false,
-+		.dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
-+		.dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
-+		.dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
-+		.autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
-+	},
-+};
- 
--static inline unsigned int __serial_read_reg(struct uart_port *up,
--					     int offset)
--{
--	offset <<= up->regshift;
--	return (unsigned int)__raw_readb(up->membase + offset);
--}
--
--static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
--					   int offset)
-+#ifdef CONFIG_PM
-+static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
- {
--	offset <<= uart->regshift;
--	return (unsigned int)__raw_readb(uart->membase + offset);
--}
-+	struct omap_device *od = to_omap_device(pdev);
- 
--static inline void __serial_write_reg(struct uart_port *up, int offset,
--		int value)
--{
--	offset <<= up->regshift;
--	__raw_writeb(value, up->membase + offset);
--}
-+	if (!od)
-+		return;
- 
--static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
--				    int value)
--{
--	offset <<= uart->regshift;
--	__raw_writeb(value, uart->membase + offset);
-+	if (enable)
-+		omap_hwmod_enable_wakeup(od->hwmods[0]);
-+	else
-+		omap_hwmod_disable_wakeup(od->hwmods[0]);
- }
- 
- /*
-- * Internal UARTs need to be initialized for the 8250 autoconfig to work
-- * properly. Note that the TX watermark initialization may not be needed
-- * once the 8250.c watermark handling code is merged.
-+ * Errata i291: [UART]:Cannot Acknowledge Idle Requests
-+ * in Smartidle Mode When Configured for DMA Operations.
-+ * WA: configure uart in force idle mode.
-  */
--
--static inline void __init omap_uart_reset(struct omap_uart_state *uart)
-+static void omap_uart_set_noidle(struct platform_device *pdev)
- {
--	serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
--	serial_write_reg(uart, UART_OMAP_SCR, 0x08);
--	serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
--}
--
--#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
-+	struct omap_device *od = to_omap_device(pdev);
- 
--/*
-- * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
-- * The access to uart register after MDR1 Access
-- * causes UART to corrupt data.
-- *
-- * Need a delay =
-- * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
-- * give 10 times as much
-- */
--static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
--		u8 fcr_val)
--{
--	u8 timeout = 255;
--
--	serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
--	udelay(2);
--	serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
--			UART_FCR_CLEAR_RCVR);
--	/*
--	 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
--	 * TX_FIFO_E bit is 1.
--	 */
--	while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
--				(UART_LSR_THRE | UART_LSR_DR))) {
--		timeout--;
--		if (!timeout) {
--			/* Should *never* happen. we warn and carry on */
--			dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
--			serial_read_reg(uart, UART_LSR));
--			break;
--		}
--		udelay(1);
--	}
-+	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
- }
- 
--static void omap_uart_save_context(struct omap_uart_state *uart)
-+static void omap_uart_set_forceidle(struct platform_device *pdev)
- {
--	u16 lcr = 0;
-+	struct omap_device *od = to_omap_device(pdev);
- 
--	if (!enable_off_mode)
--		return;
--
--	lcr = serial_read_reg(uart, UART_LCR);
--	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
--	uart->dll = serial_read_reg(uart, UART_DLL);
--	uart->dlh = serial_read_reg(uart, UART_DLM);
--	serial_write_reg(uart, UART_LCR, lcr);
--	uart->ier = serial_read_reg(uart, UART_IER);
--	uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
--	uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
--	uart->wer = serial_read_reg(uart, UART_OMAP_WER);
--	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
--	uart->mcr = serial_read_reg(uart, UART_MCR);
--	serial_write_reg(uart, UART_LCR, lcr);
--
--	uart->context_valid = 1;
-+	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
- }
- 
--static void omap_uart_restore_context(struct omap_uart_state *uart)
--{
--	u16 efr = 0;
--
--	if (!enable_off_mode)
--		return;
--
--	if (!uart->context_valid)
--		return;
--
--	uart->context_valid = 0;
--
--	if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
--		omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
--	else
--		serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
--
--	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
--	efr = serial_read_reg(uart, UART_EFR);
--	serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
--	serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
--	serial_write_reg(uart, UART_IER, 0x0);
--	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
--	serial_write_reg(uart, UART_DLL, uart->dll);
--	serial_write_reg(uart, UART_DLM, uart->dlh);
--	serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
--	serial_write_reg(uart, UART_IER, uart->ier);
--	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
--	serial_write_reg(uart, UART_MCR, uart->mcr);
--	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
--	serial_write_reg(uart, UART_EFR, efr);
--	serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
--	serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
--	serial_write_reg(uart, UART_OMAP_WER, uart->wer);
--	serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
--
--	if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
--		omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
--	else
--		/* UART 16x mode */
--		serial_write_reg(uart, UART_OMAP_MDR1,
--				UART_OMAP_MDR1_16X_MODE);
--}
- #else
--static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
--static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
--#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
--
--static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
--{
--	if (uart->clocked)
--		return;
--
--	omap_device_enable(uart->pdev);
--	uart->clocked = 1;
--	omap_uart_restore_context(uart);
--}
--
--#ifdef CONFIG_PM
--
--static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
--{
--	if (!uart->clocked)
--		return;
--
--	omap_uart_save_context(uart);
--	uart->clocked = 0;
--	omap_device_idle(uart->pdev);
--}
--
--static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
--{
--	/* Set wake-enable bit */
--	if (uart->wk_en && uart->wk_mask) {
--		u32 v = __raw_readl(uart->wk_en);
--		v |= uart->wk_mask;
--		__raw_writel(v, uart->wk_en);
--	}
--
--	/* Ensure IOPAD wake-enables are set */
--	if (cpu_is_omap34xx() && uart->padconf) {
--		u16 v = omap_ctrl_readw(uart->padconf);
--		v |= OMAP3_PADCONF_WAKEUPENABLE0;
--		omap_ctrl_writew(v, uart->padconf);
--	}
--}
--
--static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
--{
--	/* Clear wake-enable bit */
--	if (uart->wk_en && uart->wk_mask) {
--		u32 v = __raw_readl(uart->wk_en);
--		v &= ~uart->wk_mask;
--		__raw_writel(v, uart->wk_en);
--	}
--
--	/* Ensure IOPAD wake-enables are cleared */
--	if (cpu_is_omap34xx() && uart->padconf) {
--		u16 v = omap_ctrl_readw(uart->padconf);
--		v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
--		omap_ctrl_writew(v, uart->padconf);
--	}
--}
--
--static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
--					       int enable)
--{
--	u8 idlemode;
--
--	if (enable) {
--		/**
--		 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
--		 * in Smartidle Mode When Configured for DMA Operations.
--		 */
--		if (uart->dma_enabled)
--			idlemode = HWMOD_IDLEMODE_FORCE;
--		else
--			idlemode = HWMOD_IDLEMODE_SMART;
--	} else {
--		idlemode = HWMOD_IDLEMODE_NO;
--	}
--
--	omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
--}
--
--static void omap_uart_block_sleep(struct omap_uart_state *uart)
--{
--	omap_uart_enable_clocks(uart);
--
--	omap_uart_smart_idle_enable(uart, 0);
--	uart->can_sleep = 0;
--	if (uart->timeout)
--		mod_timer(&uart->timer, jiffies + uart->timeout);
--	else
--		del_timer(&uart->timer);
--}
--
--static void omap_uart_allow_sleep(struct omap_uart_state *uart)
--{
--	if (device_may_wakeup(&uart->pdev->dev))
--		omap_uart_enable_wakeup(uart);
--	else
--		omap_uart_disable_wakeup(uart);
--
--	if (!uart->clocked)
--		return;
--
--	omap_uart_smart_idle_enable(uart, 1);
--	uart->can_sleep = 1;
--	del_timer(&uart->timer);
--}
--
--static void omap_uart_idle_timer(unsigned long data)
--{
--	struct omap_uart_state *uart = (struct omap_uart_state *)data;
--
--	omap_uart_allow_sleep(uart);
--}
--
--void omap_uart_prepare_idle(int num)
--{
--	struct omap_uart_state *uart;
--
--	list_for_each_entry(uart, &uart_list, node) {
--		if (num == uart->num && uart->can_sleep) {
--			omap_uart_disable_clocks(uart);
--			return;
--		}
--	}
--}
--
--void omap_uart_resume_idle(int num)
--{
--	struct omap_uart_state *uart;
--
--	list_for_each_entry(uart, &uart_list, node) {
--		if (num == uart->num && uart->can_sleep) {
--			omap_uart_enable_clocks(uart);
--
--			/* Check for IO pad wakeup */
--			if (cpu_is_omap34xx() && uart->padconf) {
--				u16 p = omap_ctrl_readw(uart->padconf);
--
--				if (p & OMAP3_PADCONF_WAKEUPEVENT0)
--					omap_uart_block_sleep(uart);
--			}
--
--			/* Check for normal UART wakeup */
--			if (__raw_readl(uart->wk_st) & uart->wk_mask)
--				omap_uart_block_sleep(uart);
--			return;
--		}
--	}
--}
--
--void omap_uart_prepare_suspend(void)
--{
--	struct omap_uart_state *uart;
--
--	list_for_each_entry(uart, &uart_list, node) {
--		omap_uart_allow_sleep(uart);
--	}
--}
--
--int omap_uart_can_sleep(void)
--{
--	struct omap_uart_state *uart;
--	int can_sleep = 1;
--
--	list_for_each_entry(uart, &uart_list, node) {
--		if (!uart->clocked)
--			continue;
--
--		if (!uart->can_sleep) {
--			can_sleep = 0;
--			continue;
--		}
--
--		/* This UART can now safely sleep. */
--		omap_uart_allow_sleep(uart);
--	}
--
--	return can_sleep;
--}
-+static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
-+{}
-+static void omap_uart_set_noidle(struct platform_device *pdev) {}
-+static void omap_uart_set_forceidle(struct platform_device *pdev) {}
-+#endif /* CONFIG_PM */
- 
--/**
-- * omap_uart_interrupt()
-- *
-- * This handler is used only to detect that *any* UART interrupt has
-- * occurred.  It does _nothing_ to handle the interrupt.  Rather,
-- * any UART interrupt will trigger the inactivity timer so the
-- * UART will not idle or sleep for its timeout period.
-- *
-- **/
--/* static int first_interrupt; */
--static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
--{
--	struct omap_uart_state *uart = dev_id;
-+#ifdef CONFIG_OMAP_MUX
-+static struct omap_device_pad default_uart1_pads[] __initdata = {
-+	{
-+		.name	= "uart1_cts.uart1_cts",
-+		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart1_rts.uart1_rts",
-+		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart1_tx.uart1_tx",
-+		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart1_rx.uart1_rx",
-+		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-+		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-+		.idle	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-+	},
-+};
- 
--	omap_uart_block_sleep(uart);
-+static struct omap_device_pad default_uart2_pads[] __initdata = {
-+	{
-+		.name	= "uart2_cts.uart2_cts",
-+		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart2_rts.uart2_rts",
-+		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart2_tx.uart2_tx",
-+		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart2_rx.uart2_rx",
-+		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-+		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-+		.idle	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-+	},
-+};
- 
--	return IRQ_NONE;
--}
-+static struct omap_device_pad default_uart3_pads[] __initdata = {
-+	{
-+		.name	= "uart3_cts_rctx.uart3_cts_rctx",
-+		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart3_rts_sd.uart3_rts_sd",
-+		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart3_tx_irtx.uart3_tx_irtx",
-+		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart3_rx_irrx.uart3_rx_irrx",
-+		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-+		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-+		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-+	},
-+};
- 
--static void omap_uart_idle_init(struct omap_uart_state *uart)
--{
--	int ret;
--
--	uart->can_sleep = 0;
--	uart->timeout = DEFAULT_TIMEOUT;
--	setup_timer(&uart->timer, omap_uart_idle_timer,
--		    (unsigned long) uart);
--	if (uart->timeout)
--		mod_timer(&uart->timer, jiffies + uart->timeout);
--	omap_uart_smart_idle_enable(uart, 0);
--
--	if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
--		u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
--		u32 wk_mask = 0;
--		u32 padconf = 0;
--
--		/* XXX These PRM accesses do not belong here */
--		uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
--		uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
--		switch (uart->num) {
--		case 0:
--			wk_mask = OMAP3430_ST_UART1_MASK;
--			padconf = 0x182;
--			break;
--		case 1:
--			wk_mask = OMAP3430_ST_UART2_MASK;
--			padconf = 0x17a;
--			break;
--		case 2:
--			wk_mask = OMAP3430_ST_UART3_MASK;
--			padconf = 0x19e;
--			break;
--		case 3:
--			wk_mask = OMAP3630_ST_UART4_MASK;
--			padconf = 0x0d2;
--			break;
--		}
--		uart->wk_mask = wk_mask;
--		uart->padconf = padconf;
--	} else if (cpu_is_omap24xx()) {
--		u32 wk_mask = 0;
--		u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
--
--		switch (uart->num) {
--		case 0:
--			wk_mask = OMAP24XX_ST_UART1_MASK;
--			break;
--		case 1:
--			wk_mask = OMAP24XX_ST_UART2_MASK;
--			break;
--		case 2:
--			wk_en = OMAP24XX_PM_WKEN2;
--			wk_st = OMAP24XX_PM_WKST2;
--			wk_mask = OMAP24XX_ST_UART3_MASK;
--			break;
--		}
--		uart->wk_mask = wk_mask;
--		if (cpu_is_omap2430()) {
--			uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
--			uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
--		} else if (cpu_is_omap2420()) {
--			uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
--			uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
--		}
--	} else {
--		uart->wk_en = NULL;
--		uart->wk_st = NULL;
--		uart->wk_mask = 0;
--		uart->padconf = 0;
--	}
-+static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
-+	{
-+		.name   = "gpmc_wait2.uart4_tx",
-+		.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "gpmc_wait3.uart4_rx",
-+		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-+		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-+		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-+	},
-+};
- 
--	uart->irqflags |= IRQF_SHARED;
--	ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
--				   IRQF_SHARED, "serial idle", (void *)uart);
--	WARN_ON(ret);
--}
-+static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
-+	{
-+		.name	= "uart4_tx.uart4_tx",
-+		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-+	},
-+	{
-+		.name	= "uart4_rx.uart4_rx",
-+		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-+		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-+		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-+	},
-+};
- 
--void omap_uart_enable_irqs(int enable)
-+static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
- {
--	int ret;
--	struct omap_uart_state *uart;
--
--	list_for_each_entry(uart, &uart_list, node) {
--		if (enable) {
--			pm_runtime_put_sync(&uart->pdev->dev);
--			ret = request_threaded_irq(uart->irq, NULL,
--						   omap_uart_interrupt,
--						   IRQF_SHARED,
--						   "serial idle",
--						   (void *)uart);
--		} else {
--			pm_runtime_get_noresume(&uart->pdev->dev);
--			free_irq(uart->irq, (void *)uart);
-+	switch (bdata->id) {
-+	case 0:
-+		bdata->pads = default_uart1_pads;
-+		bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
-+		break;
-+	case 1:
-+		bdata->pads = default_uart2_pads;
-+		bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
-+		break;
-+	case 2:
-+		bdata->pads = default_uart3_pads;
-+		bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
-+		break;
-+	case 3:
-+		if (cpu_is_omap44xx()) {
-+			bdata->pads = default_omap4_uart4_pads;
-+			bdata->pads_cnt =
-+				ARRAY_SIZE(default_omap4_uart4_pads);
-+		} else if (cpu_is_omap3630()) {
-+			bdata->pads = default_omap36xx_uart4_pads;
-+			bdata->pads_cnt =
-+				ARRAY_SIZE(default_omap36xx_uart4_pads);
- 		}
-+		break;
-+	default:
-+		break;
- 	}
- }
--
--static ssize_t sleep_timeout_show(struct device *dev,
--				  struct device_attribute *attr,
--				  char *buf)
--{
--	struct platform_device *pdev = to_platform_device(dev);
--	struct omap_device *odev = to_omap_device(pdev);
--	struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
--
--	return sprintf(buf, "%u\n", uart->timeout / HZ);
--}
--
--static ssize_t sleep_timeout_store(struct device *dev,
--				   struct device_attribute *attr,
--				   const char *buf, size_t n)
--{
--	struct platform_device *pdev = to_platform_device(dev);
--	struct omap_device *odev = to_omap_device(pdev);
--	struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
--	unsigned int value;
--
--	if (sscanf(buf, "%u", &value) != 1) {
--		dev_err(dev, "sleep_timeout_store: Invalid value\n");
--		return -EINVAL;
--	}
--
--	uart->timeout = value * HZ;
--	if (uart->timeout)
--		mod_timer(&uart->timer, jiffies + uart->timeout);
--	else
--		/* A zero value means disable timeout feature */
--		omap_uart_block_sleep(uart);
--
--	return n;
--}
--
--static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
--		sleep_timeout_store);
--#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
- #else
--static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
--static void omap_uart_block_sleep(struct omap_uart_state *uart)
--{
--	/* Needed to enable UART clocks when built without CONFIG_PM */
--	omap_uart_enable_clocks(uart);
--}
--#define DEV_CREATE_FILE(dev, attr)
--#endif /* CONFIG_PM */
--
--#ifndef CONFIG_SERIAL_OMAP
--/*
-- * Override the default 8250 read handler: mem_serial_in()
-- * Empty RX fifo read causes an abort on omap3630 and omap4
-- * This function makes sure that an empty rx fifo is not read on these silicons
-- * (OMAP1/2/3430 are not affected)
-- */
--static unsigned int serial_in_override(struct uart_port *up, int offset)
--{
--	if (UART_RX == offset) {
--		unsigned int lsr;
--		lsr = __serial_read_reg(up, UART_LSR);
--		if (!(lsr & UART_LSR_DR))
--			return -EPERM;
--	}
--
--	return __serial_read_reg(up, offset);
--}
-+static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
-+#endif
- 
--static void serial_out_override(struct uart_port *up, int offset, int value)
-+char *cmdline_find_option(char *str)
- {
--	unsigned int status, tmout = 10000;
-+	extern char *saved_command_line;
- 
--	status = __serial_read_reg(up, UART_LSR);
--	while (!(status & UART_LSR_THRE)) {
--		/* Wait up to 10ms for the character(s) to be sent. */
--		if (--tmout == 0)
--			break;
--		udelay(1);
--		status = __serial_read_reg(up, UART_LSR);
--	}
--	__serial_write_reg(up, offset, value);
-+	return strstr(saved_command_line, str);
- }
--#endif
- 
- static int __init omap_serial_early_init(void)
- {
--	int i = 0;
--
- 	do {
- 		char oh_name[MAX_UART_HWMOD_NAME_LEN];
- 		struct omap_hwmod *oh;
- 		struct omap_uart_state *uart;
-+		char uart_name[MAX_UART_HWMOD_NAME_LEN];
- 
- 		snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
--			 "uart%d", i + 1);
-+			 "uart%d", num_uarts + 1);
- 		oh = omap_hwmod_lookup(oh_name);
- 		if (!oh)
- 			break;
-@@ -653,21 +271,35 @@ static int __init omap_serial_early_init(void)
- 			return -ENODEV;
- 
- 		uart->oh = oh;
--		uart->num = i++;
-+		uart->num = num_uarts++;
- 		list_add_tail(&uart->node, &uart_list);
--		num_uarts++;
--
--		/*
--		 * NOTE: omap_hwmod_setup*() has not yet been called,
--		 *       so no hwmod functions will work yet.
--		 */
--
--		/*
--		 * During UART early init, device need to be probed
--		 * to determine SoC specific init before omap_device
--		 * is ready.  Therefore, don't allow idle here
--		 */
--		uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
-+		snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
-+				"%s%d", OMAP_SERIAL_NAME, uart->num);
-+
-+		if (cmdline_find_option(uart_name)) {
-+			console_uart_id = uart->num;
-+
-+			if (console_loglevel >= 10) {
-+				uart_debug = true;
-+				pr_info("%s used as console in debug mode"
-+						" uart%d clocks will not be"
-+						" gated", uart_name, uart->num);
-+			}
-+
-+			if (cmdline_find_option("no_console_suspend"))
-+				no_console_suspend = true;
-+
-+			/*
-+			 * omap-uart can be used for earlyprintk logs
-+			 * So if omap-uart is used as console then prevent
-+			 * uart reset and idle to get logs from omap-uart
-+			 * until uart console driver is available to take
-+			 * care for console messages.
-+			 * Idling or resetting omap-uart while printing logs
-+			 * early boot logs can stall the boot-up.
-+			 */
-+			oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
-+		}
- 	} while (1);
- 
- 	return 0;
-@@ -677,6 +309,7 @@ core_initcall(omap_serial_early_init);
- /**
-  * omap_serial_init_port() - initialize single serial port
-  * @bdata: port specific board data pointer
-+ * @info: platform specific data pointer
-  *
-  * This function initialies serial driver for given port only.
-  * Platforms can call this function instead of omap_serial_init()
-@@ -685,7 +318,8 @@ core_initcall(omap_serial_early_init);
-  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
-  * use only one of the two.
-  */
--void __init omap_serial_init_port(struct omap_board_data *bdata)
-+void __init omap_serial_init_port(struct omap_board_data *bdata,
-+			struct omap_uart_port_info *info)
- {
- 	struct omap_uart_state *uart;
- 	struct omap_hwmod *oh;
-@@ -693,15 +327,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
- 	void *pdata = NULL;
- 	u32 pdata_size = 0;
- 	char *name;
--#ifndef CONFIG_SERIAL_OMAP
--	struct plat_serial8250_port ports[2] = {
--		{},
--		{.flags = 0},
--	};
--	struct plat_serial8250_port *p = &ports[0];
--#else
- 	struct omap_uart_port_info omap_up;
--#endif
- 
- 	if (WARN_ON(!bdata))
- 		return;
-@@ -713,66 +339,34 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
- 	list_for_each_entry(uart, &uart_list, node)
- 		if (bdata->id == uart->num)
- 			break;
-+	if (!info)
-+		info = omap_serial_default_info;
- 
- 	oh = uart->oh;
--	uart->dma_enabled = 0;
--#ifndef CONFIG_SERIAL_OMAP
--	name = "serial8250";
--
--	/*
--	 * !! 8250 driver does not use standard IORESOURCE* It
--	 * has it's own custom pdata that can be taken from
--	 * the hwmod resource data.  But, this needs to be
--	 * done after the build.
--	 *
--	 * ?? does it have to be done before the register ??
--	 * YES, because platform_device_data_add() copies
--	 * pdata, it does not use a pointer.
--	 */
--	p->flags = UPF_BOOT_AUTOCONF;
--	p->iotype = UPIO_MEM;
--	p->regshift = 2;
--	p->uartclk = OMAP24XX_BASE_BAUD * 16;
--	p->irq = oh->mpu_irqs[0].irq;
--	p->mapbase = oh->slaves[0]->addr->pa_start;
--	p->membase = omap_hwmod_get_mpu_rt_va(oh);
--	p->irqflags = IRQF_SHARED;
--	p->private_data = uart;
--
--	/*
--	 * omap44xx, ti816x: Never read empty UART fifo
--	 * omap3xxx: Never read empty UART fifo on UARTs
--	 * with IP rev >=0x52
--	 */
--	uart->regshift = p->regshift;
--	uart->membase = p->membase;
--	if (cpu_is_omap44xx() || cpu_is_ti816x())
--		uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
--	else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
--			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
--		uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
--
--	if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
--		p->serial_in = serial_in_override;
--		p->serial_out = serial_out_override;
--	}
--
--	pdata = &ports[0];
--	pdata_size = 2 * sizeof(struct plat_serial8250_port);
--#else
--
- 	name = DRIVER_NAME;
- 
--	omap_up.dma_enabled = uart->dma_enabled;
-+	omap_up.dma_enabled = info->dma_enabled;
- 	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
--	omap_up.mapbase = oh->slaves[0]->addr->pa_start;
--	omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
--	omap_up.irqflags = IRQF_SHARED;
--	omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
-+	omap_up.flags = UPF_BOOT_AUTOCONF;
-+	omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
-+	omap_up.set_forceidle = omap_uart_set_forceidle;
-+	omap_up.set_noidle = omap_uart_set_noidle;
-+	omap_up.enable_wakeup = omap_uart_enable_wakeup;
-+	omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
-+	omap_up.dma_rx_timeout = info->dma_rx_timeout;
-+	omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
-+	omap_up.autosuspend_timeout = info->autosuspend_timeout;
-+
-+	/* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
-+	if (!cpu_is_omap2420() && !cpu_is_ti816x())
-+		omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
-+
-+	/* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
-+	if ((cpu_is_omap34xx() || cpu_is_omap3630()) && !cpu_is_am33xx())
-+		omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
- 
- 	pdata = &omap_up;
- 	pdata_size = sizeof(struct omap_uart_port_info);
--#endif
- 
- 	if (WARN_ON(!oh))
- 		return;
-@@ -782,64 +376,29 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
- 	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
- 	     name, oh->name);
- 
--	omap_device_disable_idle_on_suspend(pdev);
-+	if ((console_uart_id == bdata->id) && no_console_suspend)
-+		omap_device_disable_idle_on_suspend(pdev);
-+
- 	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
- 
--	uart->irq = oh->mpu_irqs[0].irq;
--	uart->regshift = 2;
--	uart->mapbase = oh->slaves[0]->addr->pa_start;
--	uart->membase = omap_hwmod_get_mpu_rt_va(oh);
- 	uart->pdev = pdev;
- 
- 	oh->dev_attr = uart;
- 
--	console_lock(); /* in case the earlycon is on the UART */
--
--	/*
--	 * Because of early UART probing, UART did not get idled
--	 * on init.  Now that omap_device is ready, ensure full idle
--	 * before doing omap_device_enable().
--	 */
--	omap_hwmod_idle(uart->oh);
--
--	omap_device_enable(uart->pdev);
--	omap_uart_idle_init(uart);
--	omap_uart_reset(uart);
--	omap_hwmod_enable_wakeup(uart->oh);
--	omap_device_idle(uart->pdev);
--
--	/*
--	 * Need to block sleep long enough for interrupt driven
--	 * driver to start.  Console driver is in polling mode
--	 * so device needs to be kept enabled while polling driver
--	 * is in use.
--	 */
--	if (uart->timeout)
--		uart->timeout = (30 * HZ);
--	omap_uart_block_sleep(uart);
--	uart->timeout = DEFAULT_TIMEOUT;
--
--	console_unlock();
--
--	if ((cpu_is_omap34xx() && uart->padconf) ||
--	    (uart->wk_en && uart->wk_mask)) {
-+	if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
-+			&& !uart_debug)
- 		device_init_wakeup(&pdev->dev, true);
--		DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
--	}
--
--	/* Enable the MDR1 errata for OMAP3 */
--	if (cpu_is_omap34xx() && !cpu_is_ti816x())
--		uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
- }
- 
- /**
-- * omap_serial_init() - initialize all supported serial ports
-+ * omap_serial_board_init() - initialize all supported serial ports
-+ * @info: platform specific data pointer
-  *
-  * Initializes all available UARTs as serial ports. Platforms
-  * can call this function when they want to have default behaviour
-  * for serial ports (e.g initialize them all as serial ports).
-  */
--void __init omap_serial_init(void)
-+void __init omap_serial_board_init(struct omap_uart_port_info *info)
- {
- 	struct omap_uart_state *uart;
- 	struct omap_board_data bdata;
-@@ -849,7 +408,26 @@ void __init omap_serial_init(void)
- 		bdata.flags = 0;
- 		bdata.pads = NULL;
- 		bdata.pads_cnt = 0;
--		omap_serial_init_port(&bdata);
- 
-+		if (cpu_is_omap44xx() || (cpu_is_omap34xx() &&
-+							!cpu_is_am33xx()))
-+			omap_serial_fill_default_pads(&bdata);
-+
-+		if (!info)
-+			omap_serial_init_port(&bdata, NULL);
-+		else
-+			omap_serial_init_port(&bdata, &info[uart->num]);
- 	}
- }
-+
-+/**
-+ * omap_serial_init() - initialize all supported serial ports
-+ *
-+ * Initializes all available UARTs.
-+ * Platforms can call this function when they want to have default behaviour
-+ * for serial ports (e.g initialize them all as serial ports).
-+ */
-+void __init omap_serial_init(void)
-+{
-+	omap_serial_board_init(NULL);
-+}
-diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
-new file mode 100644
-index 0000000..69b49ea
---- /dev/null
-+++ b/arch/arm/mach-omap2/sleep33xx.S
-@@ -0,0 +1,751 @@
-+/*
-+ * Low level suspend code for AM33XX SoCs
-+ *
-+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/linkage.h>
-+#include <linux/init.h>
-+#include <asm/memory.h>
-+#include <asm/assembler.h>
-+#include <mach/io.h>
-+#include <plat/emif.h>
-+#include "cm33xx.h"
-+
-+#include <plat/emif.h>
-+#include <plat/sram.h>
-+
-+#include "cm33xx.h"
-+#include "pm33xx.h"
-+#include "prm33xx.h"
-+#include "control.h"
-+
-+/* We should probably pass in the virtual address of PRCM, Control and EMIF
-+ * along with the physical addresses
-+ * load it into the registers and then continue
-+ */
-+	.align 3
-+ENTRY(am33xx_do_wfi)
-+	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
-+
-+	.macro	pll_bypass, name, clk_mode_addr, idlest_addr
-+pll_bypass_\name:
-+	ldr	r0, \clk_mode_addr
-+	ldr	r1, [r0]
-+	bic	r1, r1, #(7 << 0)
-+	orr	r1, r1, #0x5
-+	str	r1, [r0]
-+	ldr	r0, \idlest_addr
-+wait_pll_bypass_\name:
-+	ldr	r1, [r0]
-+	tst	r1, #0x0
-+	bne	wait_pll_bypass_\name
-+	.endm
-+
-+	.macro	pll_lock, name, clk_mode_addr, idlest_addr
-+pll_lock_\name:
-+	ldr	r0, \clk_mode_addr
-+	ldr	r1, [r0]
-+	bic	r1, r1, #(7 << 0)
-+	orr	r1, r1, #0x7
-+	str	r1, [r0]
-+	ldr	r0, \idlest_addr
-+wait_pll_lock_\name:
-+	ldr	r1, [r0]
-+	tst	r1, #0x1
-+	bne	wait_pll_lock_\name
-+	.endm
-+
-+	/* EMIF config for low power mode */
-+	ldr	r0, emif_addr_func
-+	blx	r0
-+
-+	str	r0, emif_addr_virt
-+
-+	/* Ensure that all the writes to DDR leave the A8 */
-+	dsb
-+	dmb
-+	isb
-+
-+	add	r1, r0, #EMIF4_0_SDRAM_MGMT_CTRL
-+	ldr	r2, [r1]
-+	orr	r2, r2, #0xa0		@ a reasonable delay for entering SR
-+	str	r2, [r1, #0]
-+
-+	ldr	r2, ddr_start		@ do a dummy access to DDR
-+	ldr	r3, [r2, #0]
-+	ldr	r3, [r1, #0]
-+	orr	r3, r3, #0x200		@ now set the LP MODE to Self-Refresh
-+	str	r3, [r1, #0]
-+	str	r2, [r1, #4]		@ write to shadow register also
-+
-+	mov	r1, #0x1000		@ Give some time for the system to enter SR
-+wait_sr:
-+	subs	r1, r1, #1
-+	bne	wait_sr
-+
-+	/* Disable EMIF at this point */
-+	ldr	r1, virt_emif_clkctrl
-+	ldr	r2, [r1]
-+	bic	r2, r2, #(3 << 0)
-+	str	r2, [r1]
-+
-+	ldr	r1, virt_emif_clkctrl
-+wait_emif_disable:
-+	ldr	r2, [r1]
-+	ldr	r3, module_disabled_val
-+	cmp	r2, r3
-+	bne	wait_emif_disable
-+
-+	/* Weak pull down for DQ, DM */
-+	ldr	r1, virt_ddr_io_pull1
-+	ldr	r2, susp_io_pull
-+	str	r2, [r1]
-+
-+	ldr	r1, virt_ddr_io_pull2
-+	ldr	r2, susp_io_pull
-+	str	r2, [r1]
-+
-+	/* Disable VTP with N & P = 0x1 */
-+	ldr	r1, virt_ddr_vtp_ctrl
-+	ldr	r2, susp_vtp_ctrl_val
-+	str	r2, [r1]
-+
-+	/* IO to work in mDDR mode */
-+	ldr	r0, virt_ddr_io_ctrl
-+	ldr	r1, [r0]
-+	mov	r2, #1
-+	mov	r3, r2, lsl #28
-+	str	r3, [r0]
-+
-+	/* Enable SRAM LDO ret mode */
-+	ldr	r0, virt_sram_ldo_addr
-+	ldr	r1, [r0]
-+	orr	r1, #1
-+	str	r1, [r0]
-+
-+	/* Put the PLLs in bypass mode */
-+	pll_bypass	core, virt_core_clk_mode, virt_core_idlest
-+	pll_bypass	ddr, virt_ddr_clk_mode, virt_ddr_idlest
-+	pll_bypass	disp, virt_disp_clk_mode, virt_disp_idlest
-+	pll_bypass	per, virt_per_clk_mode, virt_per_idlest
-+	pll_bypass	mpu, virt_mpu_clk_mode, virt_mpu_idlest
-+
-+	dsb
-+	dmb
-+	isb
-+
-+	wfi
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+
-+	/* We come here in case of an abort */
-+
-+	/* Relock the PLLs */
-+	pll_lock	mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest
-+	pll_lock	per_abt, virt_per_clk_mode, virt_per_idlest
-+	pll_lock	disp_abt, virt_disp_clk_mode, virt_disp_idlest
-+	pll_lock	ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest
-+	pll_lock	core_abt, virt_core_clk_mode, virt_core_idlest
-+
-+	/* Disable SRAM LDO ret mode */
-+	ldr	r0, virt_sram_ldo_addr
-+	ldr	r1, [r0]
-+	bic	r1, #1
-+	str	r1, [r0]
-+
-+	/* IO to work in DDR mode */
-+	ldr	r0, virt_ddr_io_ctrl
-+	ldr	r1, [r0]
-+	mov	r2, #0x0
-+	mov	r3, r2, lsl #28
-+	str	r3, [r0]
-+
-+	/* Restore the pull for DQ, DM */
-+	ldr	r1, virt_ddr_io_pull1
-+	ldr	r2, resume_io_pull1
-+	str	r2, [r1]
-+
-+	ldr	r1, virt_ddr_io_pull2
-+	ldr	r2, resume_io_pull2
-+	str	r2, [r1]
-+
-+	/* Enable VTP */
-+config_vtp_abt:
-+	ldr	r0, virt_ddr_vtp_ctrl
-+	ldr	r1, [r0]
-+	mov	r2, #0x0	@ clear the register
-+	str	r2, [r0]
-+	mov	r2, #0x6	@ write the filter value
-+	str	r2, [r0]
-+
-+	ldr	r1, [r0]
-+	ldr	r2, vtp_enable	@ set the enable bit
-+	orr	r2, r2, r1
-+	str	r2, [r0]
-+
-+	ldr	r1, [r0]	@ toggle the CLRZ bit
-+	bic	r1, #1
-+	str	r1, [r0]
-+
-+	ldr	r1, [r0]
-+	orr	r1, #1
-+	str	r1, [r0]
-+
-+poll_vtp_ready_abt:
-+	ldr	r1, [r0]	@ poll for VTP ready
-+	tst	r1, #(1 << 5)
-+	beq	poll_vtp_ready_abt
-+
-+	/* Enable EMIF */
-+	ldr	r1, virt_emif_clkctrl
-+	mov	r2, #0x2
-+	str	r2, [r1]
-+wait_emif_enable:
-+	ldr	r3, [r1]
-+	cmp	r2, r3
-+	bne	wait_emif_enable
-+
-+	/* Disable EMIF self-refresh */
-+	ldr	r0, emif_addr_virt
-+	add	r0, r0, #EMIF4_0_SDRAM_MGMT_CTRL
-+	ldr	r1, [r0]
-+	bic	r1, r1, #(0x7 << 7)
-+	str	r1, [r0]
-+
-+	mov	r0, #7
-+	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
-+
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+
-+	/* Take the PLLs out of LP_BYPASS */
-+	pll_lock	mpu, phys_mpu_clk_mode, phys_mpu_idlest
-+	pll_lock	per, phys_per_clk_mode, phys_per_idlest
-+	pll_lock	disp, phys_disp_clk_mode, phys_disp_idlest
-+	pll_lock	ddr, phys_ddr_clk_mode, phys_ddr_idlest
-+	pll_lock	core, phys_core_clk_mode, phys_core_idlest
-+
-+	/* Disable SRAM LDO ret mode */
-+	ldr	r0, phys_sram_ldo_addr
-+	ldr	r1, [r0]
-+	bic	r1, #1
-+	str	r1, [r0]
-+
-+	/* Restore the pull for DQ, DM */
-+	ldr	r1, phys_ddr_io_pull1
-+	ldr	r2, resume_io_pull1
-+	str	r2, [r1]
-+
-+	ldr	r1, phys_ddr_io_pull2
-+	ldr	r2, resume_io_pull2
-+	str	r2, [r1]
-+
-+	/* Disable EMIF self-refresh */
-+	ldr	r0, emif_phys_addr
-+	add	r0, r0, #EMIF4_0_SDRAM_MGMT_CTRL
-+	ldr	r1, [r0]
-+	bic	r1, r1, #(0x7 << 7)
-+	str	r1, [r0]
-+
-+	/* Take out IO of mDDR mode */
-+	ldr	r0, phys_ddr_io_ctrl
-+	ldr	r1, [r0]
-+	bic	r1, r1, #28
-+	str	r1, [r0]
-+
-+/*
-+ * Instead of harcoding the EMIF and DDR PHY related settings
-+ * in this file, the sane thing to do would have been to backup
-+ * the register contents during suspend and restore it back in
-+ * the resume path. However, due to the Si errata related to
-+ * DDR PHY registers, these registers are read-only. So, we'll
-+ * need to hardcode atleast the DDR PHY configuration over here.
-+ * We _could_ back up the EMIF registers but in order to be
-+ * consistent with the DDR setup procedure we skip this for now.
-+ * The person updating the DDR PHY config values is expected
-+ * to update the EMIF config values also.
-+ */
-+
-+config_vtp:
-+	ldr	r0, vtp0_addr
-+	ldr	r1, [r0]
-+	mov	r2, #0x0	@ clear the register
-+	str	r2, [r0]
-+	mov	r2, #0x6	@ write the filter value
-+	str	r2, [r0]
-+
-+	ldr	r1, [r0]
-+	ldr	r2, vtp_enable	@ set the enable bit
-+	orr	r2, r2, r1
-+	str	r2, [r0]
-+
-+	ldr	r1, [r0]	@ toggle the CLRZ bit
-+	bic	r1, #1
-+	str	r1, [r0]
-+
-+	ldr	r1, [r0]
-+	orr	r1, #1
-+	str	r1, [r0]
-+
-+poll_vtp_ready:
-+	ldr	r1, [r0]	@ poll for VTP ready
-+	tst	r1, #(1 << 5)
-+	beq	poll_vtp_ready
-+
-+cmd_macro_config:
-+	ldr	r0, ddr_phy_base
-+	ldr	r1, [r0]
-+	ldr	r2, ddr2_ratio_val
-+	mov	r3, r2
-+	@ TODO: Need to use proper variable here
-+	mov	r4, #0
-+	str	r3, [r0, #28]	@cmd0
-+	str	r4, [r0, #32]
-+	str	r4, [r0, #36]
-+	str	r4, [r0, #40]
-+	str	r4, [r0, #44]
-+	str	r3, [r0, #80]	@cmd1
-+	str	r4, [r0, #84]
-+	str	r4, [r0, #88]
-+	str	r4, [r0, #92]
-+	str	r4, [r0, #96]
-+	str	r3, [r0, #132]	@cmd2
-+	str	r4, [r0, #136]
-+	str	r4, [r0, #140]
-+	str	r4, [r0, #144]
-+	str	r4, [r0, #148]
-+
-+	mov	r3, #0x0
-+	bl	data_macro_config
-+	mov	r3, #0xa4
-+	bl	data_macro_config
-+	b	setup_rank_delays
-+
-+data_macro_config:
-+	ldr	r0, ddr_phy_base
-+	add	r0, r0, r3
-+rd_dqs:
-+	ldr	r1, data0_rd_dqs_slave_ratio0_val
-+	mov	r2, r1
-+	/* shift by 30, 20, 10 and orr */
-+	mov	r5, r2, lsl #10
-+	mov	r6, r2, lsl #20
-+	mov	r7, r2, lsl #30
-+	orr	r2, r2, r5
-+	orr	r2, r2, r6
-+	orr	r2, r2, r7
-+	/* Done with crazy bit ops. store it now */
-+	str	r2, [r0, #200]
-+	ldr	r1, data0_rd_dqs_slave_ratio1_val
-+	mov	r2, r1
-+	mov	r5, r2, lsr #2
-+	mov	r2, r5
-+	str	r2, [r0, #204]
-+wr_dqs:
-+	ldr	r1, data0_wr_dqs_slave_ratio0_val
-+	mov	r2, r1
-+	/* shift by 30, 20, 10 and orr */
-+	mov	r5, r2, lsl #10
-+	mov	r6, r2, lsl #20
-+	mov	r7, r2, lsl #30
-+	orr	r2, r2, r5
-+	orr	r2, r2, r6
-+	orr	r2, r2, r7
-+	/* Done with crazy bit ops. store it now */
-+	str	r2, [r0, #220]
-+	ldr	r1, data0_wr_dqs_slave_ratio1_val
-+	mov	r2, r1
-+	mov	r5, r2, lsr #2
-+	mov	r2, r5
-+	str	r2, [r0, #224]
-+wr_lvl:
-+	ldr	r1, data0_wr_lvl_init_ratio0_val
-+	mov	r2, r1
-+	/* shift by 30, 20, 10 and orr */
-+	mov	r5, r2, lsl #10
-+	mov	r6, r2, lsl #20
-+	mov	r7, r2, lsl #30
-+	orr	r2, r2, r5
-+	orr	r2, r2, r6
-+	orr	r2, r2, r7
-+	/* Done with crazy bit ops. store it now */
-+	str	r2, [r0, #240]
-+	ldr	r1, data0_wr_lvl_init_ratio1_val
-+	mov	r2, r1
-+	mov	r5, r2, lsr #2
-+	mov	r2, r5
-+	str	r2, [r0, #244]
-+gate_lvl:
-+	ldr	r1, data0_gate_lvl_init_ratio0_val
-+	mov	r2, r1
-+	/* shift by 30, 20, 10 and orr */
-+	mov	r5, r2, lsl #10
-+	mov	r6, r2, lsl #20
-+	mov	r7, r2, lsl #30
-+	orr	r2, r2, r5
-+	orr	r2, r2, r6
-+	orr	r2, r2, r7
-+	/* Done with crazy bit ops. store it now */
-+	str	r2, [r0, #248]
-+	ldr	r1, data0_gate_lvl_init_ratio1_val
-+	mov	r2, r1
-+	mov	r5, r2, lsr #2
-+	mov	r2, r5
-+	str	r2, [r0, #256]
-+we_slv:
-+	ldr	r1, data0_wr_lvl_slave_ratio0_val
-+	mov	r2, r1
-+	/* shift by 30, 20, 10 and orr */
-+	mov	r5, r2, lsl #10
-+	mov	r6, r2, lsl #20
-+	mov	r7, r2, lsl #30
-+	orr	r2, r2, r5
-+	orr	r2, r2, r6
-+	orr	r2, r2, r7
-+	/* Done with crazy bit ops. store it now */
-+	str	r2, [r0, #264]
-+	ldr	r1, data0_wr_lvl_slave_ratio1_val
-+	mov	r2, r1
-+	mov	r5, r2, lsr #2
-+	mov	r2, r5
-+	str	r2, [r0, #268]
-+wr_data:
-+	ldr	r1, data0_wr_data_slave_ratio0_val
-+	mov	r2, r1
-+	/* shift by 30, 20, 10 and orr */
-+	mov	r5, r2, lsl #10
-+	mov	r6, r2, lsl #20
-+	mov	r7, r2, lsl #30
-+	orr	r2, r2, r5
-+	orr	r2, r2, r6
-+	orr	r2, r2, r7
-+	/* Done with crazy bit ops. store it now */
-+	str	r2, [r0, #288]
-+	ldr	r1, data0_wr_data_slave_ratio1_val
-+	mov	r2, r1
-+	mov	r5, r2, lsr #2
-+	mov	r2, r5
-+	str	r2, [r0, #292]
-+dll_lock:
-+	ldr	r1, data0_dll_lock_diff_val
-+	mov	r2, r1
-+	str	r2, [r0, #312]
-+
-+setup_rank_delays:
-+	ldr	r1, data0_rank0_delay0_val
-+	mov	r2, r1
-+	str	r2, [r0, #308]
-+	ldr	r1, data1_rank0_delay1_val
-+	mov	r2, r1
-+	str	r2, [r0, #472]
-+
-+setup_io_ctrl:
-+	ldr	r0, control_base
-+	ldr	r1, ddr_ioctrl_val
-+	mov	r2, r1
-+	ldr	r4, ddr_cmd_offset
-+	mov	r3, r4
-+	str	r2, [r0, r3]	@cmd0 0x1404
-+	add	r3, r3, #4
-+	str	r2, [r0, r3]	@cmd1 0x1408
-+	add	r3, r3, #4
-+	str	r2, [r0, r3]	@cmd2 0x140c
-+	ldr	r4, ddr_data_offset
-+	mov	r3, r4
-+	str	r2, [r0, r3]	@data0 0x1440
-+	add	r3, r3, #4
-+	str	r2, [r0, r3]	@data1 0x1444
-+
-+misc_config:
-+	ldr	r1, ddr_io_ctrl_addr
-+	ldr	r2, [r1]
-+	and	r2, #0xefffffff
-+	str	r2, [r1]
-+	ldr	r1, ddr_cke_addr
-+	ldr	r2, [r1]
-+	orr	r2, #0x00000001
-+	str	r2, [r1]
-+
-+config_emif_timings:
-+	mov	r3, #1275068416	@ 0x4c000000
-+disable_sr:
-+	mov	r4, #0
-+	str	r4, [r3, #56]	@ 0x38
-+	ldr	r4, emif_rd_lat_val
-+	mov	r2, r4
-+rd_lat:
-+	str	r2, [r3, #228]	@ 0xe4
-+	str	r2, [r3, #232]	@ 0xe8
-+	str	r2, [r3, #236]	@ 0xec
-+timing1:
-+	ldr	r4, emif_timing1_val
-+	mov	r2, r4
-+	str	r2, [r3, #24]
-+	str	r2, [r3, #28]
-+timing2:
-+	ldr	r4, emif_timing2_val
-+	mov	r2, r4
-+	str	r2, [r3, #32]
-+	str	r2, [r3, #36]	@ 0x24
-+timing3:
-+	ldr	r4, emif_timing3_val
-+	mov	r2, r4
-+	str	r2, [r3, #40]	@ 0x28
-+	str	r2, [r3, #44]	@ 0x2c
-+sdcfg1:
-+	ldr	r4, emif_sdcfg_val
-+	mov	r2, r4
-+	str	r2, [r3, #8]
-+	str	r2, [r3, #12]
-+ref_ctrl_const:
-+	ldr	r4, emif_ref_ctrl_const_val
-+	mov	r2, r4
-+	str	r2, [r3, #16]
-+	str	r2, [r3, #20]
-+
-+	/* GEL had a loop with init value of 5000 */
-+	mov	r0, #0x1000
-+wait_loop1:
-+	subs	r0, r0, #1
-+	bne	wait_loop1
-+
-+ref_ctrl_actual:
-+	ldr	r4, emif_ref_ctrl_val
-+	mov	r2, r4
-+	str	r2, [r3, #16]
-+	str	r2, [r3, #20]
-+sdcfg2:
-+	ldr	r4, emif_sdcfg_val
-+	mov	r2, r4
-+	str	r2, [r3, #8]
-+	str	r2, [r3, #12]
-+
-+	/* Back from la-la-land. Kill some time for sanity to settle in */
-+	mov	r0, #0x1000
-+wait_loop2:
-+	subs	r0, r0, #1
-+	bne	wait_loop2
-+
-+	/* We are back. Branch to the common CPU resume routine */
-+ENTRY(am33xx_resume_vector)
-+	ldr	pc, resume_addr
-+
-+/*
-+ * Local variables
-+ */
-+
-+resume_addr:
-+	.word	cpu_resume - PAGE_OFFSET + 0x80000000
-+
-+emif_addr_func:
-+	.word	am33xx_get_ram_base
-+emif_phys_addr:
-+	.word	AM33XX_EMIF0_BASE
-+
-+emif_pm_ctrl:
-+	.word EMIF4_0_SDRAM_MGMT_CTRL
-+ddr_start:
-+	.word PAGE_OFFSET
-+
-+virt_mpu_idlest:
-+	.word	AM33XX_CM_IDLEST_DPLL_MPU
-+virt_mpu_clk_mode:
-+	.word	AM33XX_CM_CLKMODE_DPLL_MPU
-+
-+phys_pll_mod:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD
-+phys_mpu_clk_mode:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET
-+phys_mpu_idlest:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_MPU_OFFSET
-+
-+virt_core_idlest:
-+	.word	AM33XX_CM_IDLEST_DPLL_CORE
-+virt_core_clk_mode:
-+	.word	AM33XX_CM_CLKMODE_DPLL_CORE
-+phys_core_clk_mode:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET
-+phys_core_idlest:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_CORE_OFFSET
-+
-+virt_per_idlest:
-+	.word	AM33XX_CM_IDLEST_DPLL_PER
-+virt_per_clk_mode:
-+	.word	AM33XX_CM_CLKMODE_DPLL_PER
-+phys_per_clk_mode:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_PER_OFFSET
-+phys_per_idlest:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_PER_OFFSET
-+
-+virt_disp_idlest:
-+	.word	AM33XX_CM_IDLEST_DPLL_DISP
-+virt_disp_clk_mode:
-+	.word	AM33XX_CM_CLKMODE_DPLL_DISP
-+phys_disp_clk_mode:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET
-+phys_disp_idlest:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_DISP_OFFSET
-+
-+virt_ddr_idlest:
-+	.word	AM33XX_CM_IDLEST_DPLL_DDR
-+virt_ddr_clk_mode:
-+	.word	AM33XX_CM_CLKMODE_DPLL_DDR
-+phys_ddr_clk_mode:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET
-+phys_ddr_idlest:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_DDR_OFFSET
-+
-+virt_sram_ldo_addr:
-+	.word	AM33XX_PRM_LDO_SRAM_MPU_CTRL
-+phys_sram_ldo_addr:
-+	.word	AM33XX_PRM_BASE + AM33XX_PRM_DEVICE_MOD + AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET
-+
-+virt_emif_clkctrl:
-+	.word	AM33XX_CM_PER_EMIF_CLKCTRL
-+phys_emif_clkctrl:
-+	.word	AM33XX_CM_BASE + AM33XX_CM_PER_MOD + AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET
-+module_disabled_val:
-+	.word	0x30000
-+
-+/* DDR related stuff */
-+vtp0_addr:
-+	.word	VTP0_CTRL_REG
-+vtp_enable:
-+	.word	VTP_CTRL_ENABLE
-+vtp_start_en:
-+	.word	VTP_CTRL_START_EN
-+vtp_ready:
-+	.word	VTP_CTRL_READY
-+
-+ddr_phy_base:
-+	.word	DDR_PHY_BASE_ADDR
-+ddr2_ratio_val:
-+	.word	DDR2_RATIO
-+data0_rd_dqs_slave_ratio0_val:
-+	.word	DDR2_RD_DQS
-+data0_rd_dqs_slave_ratio1_val:
-+	.word	DDR2_RD_DQS
-+data0_wr_dqs_slave_ratio0_val:
-+	.word	DDR2_WR_DQS
-+data0_wr_dqs_slave_ratio1_val:
-+	.word	DDR2_WR_DQS
-+data0_wr_lvl_init_ratio0_val:
-+	.word	DDR2_PHY_WRLVL
-+data0_wr_lvl_init_ratio1_val:
-+	.word	DDR2_PHY_WRLVL
-+data0_gate_lvl_init_ratio0_val:
-+	.word	DDR2_PHY_GATELVL
-+data0_gate_lvl_init_ratio1_val:
-+	.word	DDR2_PHY_GATELVL
-+data0_wr_lvl_slave_ratio0_val:
-+	.word	DDR2_PHY_FIFO_WE
-+data0_wr_lvl_slave_ratio1_val:
-+	.word	DDR2_PHY_FIFO_WE
-+data0_wr_data_slave_ratio0_val:
-+	.word	DDR2_PHY_WR_DATA
-+data0_wr_data_slave_ratio1_val:
-+	.word	DDR2_PHY_WR_DATA
-+data0_dll_lock_diff_val:
-+	.word	PHY_DLL_LOCK_DIFF
-+
-+data0_rank0_delay0_val:
-+	.word	PHY_RANK0_DELAY
-+data1_rank0_delay1_val:
-+	.word	PHY_RANK0_DELAY
-+
-+control_base:
-+	.word	AM33XX_CTRL_BASE
-+ddr_io_ctrl_addr:
-+	.word	DDR_IO_CTRL
-+ddr_ioctrl_val:
-+	.word	0x18B
-+ddr_cmd_offset:
-+	.word	0x1404
-+ddr_data_offset:
-+	.word	0x1440
-+virt_ddr_io_ctrl:
-+	.word	AM33XX_CTRL_REGADDR(0x0E04)
-+phys_ddr_io_ctrl:
-+	.word	DDR_IO_CTRL
-+virt_ddr_vtp_ctrl:
-+	.word	AM33XX_CTRL_REGADDR(0x0E0C)
-+phys_ddr_vtp_ctrl:
-+	.word	VTP0_CTRL_REG
-+virt_ddr_io_pull1:
-+	.word	AM33XX_CTRL_REGADDR(0x1440)
-+phys_ddr_io_pull1:
-+	.word	AM33XX_CTRL_BASE + (0x1440)
-+virt_ddr_io_pull2:
-+	.word	AM33XX_CTRL_REGADDR(0x1444)
-+phys_ddr_io_pull2:
-+	.word	AM33XX_CTRL_BASE + (0x1444)
-+virt_ddr_io_pull3:
-+	.word	AM33XX_CTRL_REGADDR(0x1448)
-+phys_ddr_io_pull3:
-+	.word	AM33XX_CTRL_BASE + (0x1448)
-+
-+ddr_cke_addr:
-+	.word	DDR_CKE_CTRL
-+emif_rd_lat_val:
-+	.word	EMIF_READ_LATENCY
-+emif_timing1_val:
-+	.word	EMIF_TIM1
-+emif_timing2_val:
-+	.word	EMIF_TIM2
-+emif_timing3_val:
-+	.word	EMIF_TIM3
-+emif_sdcfg_val:
-+	.word	EMIF_SDCFG
-+emif_ref_ctrl_const_val:
-+	.word	0x4650
-+emif_ref_ctrl_val:
-+	.word	EMIF_SDREF
-+
-+susp_io_pull:
-+	.word	0x3FF00003
-+resume_io_pull1:
-+	.word	0x18B
-+resume_io_pull2:
-+	.word	0x18B
-+dyn_pd_val:
-+	.word	0x100000
-+susp_sdram_config:
-+	.word	0x40805332
-+susp_vtp_ctrl_val:
-+	.word	0x10117
-+emif_addr_virt:
-+	.word	0xDEADBEEF
-+
-+
-+ENTRY(am33xx_do_wfi_sz)
-+	.word	. - am33xx_do_wfi
-diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
-new file mode 100644
-index 0000000..abd2834
---- /dev/null
-+++ b/arch/arm/mach-omap2/sleep44xx.S
-@@ -0,0 +1,379 @@
-+/*
-+ * OMAP44xx sleep code.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc.
-+ * 	Santosh Shilimkar <santosh.shilimkar@ti.com>
-+ *
-+ * This program is free software,you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/linkage.h>
-+#include <asm/system.h>
-+#include <asm/smp_scu.h>
-+#include <asm/memory.h>
-+#include <asm/hardware/cache-l2x0.h>
-+
-+#include <plat/omap44xx.h>
-+#include <mach/omap-secure.h>
-+
-+#include "common.h"
-+#include "omap4-sar-layout.h"
-+
-+#if defined(CONFIG_SMP) && defined(CONFIG_PM)
-+
-+.macro	DO_SMC
-+	dsb
-+	smc	#0
-+	dsb
-+.endm
-+
-+ppa_zero_params:
-+	.word		0x0
-+
-+ppa_por_params:
-+	.word		1, 0
-+
-+/*
-+ * =============================
-+ * == CPU suspend finisher ==
-+ * =============================
-+ *
-+ * void omap4_finish_suspend(unsigned long cpu_state)
-+ *
-+ * This function code saves the CPU context and performs the CPU
-+ * power down sequence. Calling WFI effectively changes the CPU
-+ * power domains states to the desired target power state.
-+ *
-+ * @cpu_state : contains context save state (r0)
-+ *	0 - No context lost
-+ * 	1 - CPUx L1 and logic lost: MPUSS CSWR
-+ * 	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
-+ *	3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
-+ * @return: This function never returns for CPU OFF and DORMANT power states.
-+ * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
-+ * from this follows a full CPU reset path via ROM code to CPU restore code.
-+ * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
-+ * It returns to the caller for CPU INACTIVE and ON power states or in case
-+ * CPU failed to transition to targeted OFF/DORMANT state.
-+ */
-+ENTRY(omap4_finish_suspend)
-+	stmfd	sp!, {lr}
-+	cmp	r0, #0x0
-+	beq	do_WFI				@ No lowpower state, jump to WFI
-+
-+	/*
-+	 * Flush all data from the L1 data cache before disabling
-+	 * SCTLR.C bit.
-+	 */
-+	bl	omap4_get_sar_ram_base
-+	ldr	r9, [r0, #OMAP_TYPE_OFFSET]
-+	cmp	r9, #0x1			@ Check for HS device
-+	bne	skip_secure_l1_clean
-+	mov	r0, #SCU_PM_NORMAL
-+	mov	r1, #0xFF			@ clean seucre L1
-+	stmfd   r13!, {r4-r12, r14}
-+	ldr	r12, =OMAP4_MON_SCU_PWR_INDEX
-+	DO_SMC
-+	ldmfd   r13!, {r4-r12, r14}
-+skip_secure_l1_clean:
-+	bl	v7_flush_dcache_all
-+
-+	/*
-+	 * Clear the SCTLR.C bit to prevent further data cache
-+	 * allocation. Clearing SCTLR.C would make all the data accesses
-+	 * strongly ordered and would not hit the cache.
-+	 */
-+	mrc	p15, 0, r0, c1, c0, 0
-+	bic	r0, r0, #(1 << 2)		@ Disable the C bit
-+	mcr	p15, 0, r0, c1, c0, 0
-+	isb
-+
-+	/*
-+	 * Invalidate L1 data cache. Even though only invalidate is
-+	 * necessary exported flush API is used here. Doing clean
-+	 * on already clean cache would be almost NOP.
-+	 */
-+	bl	v7_flush_dcache_all
-+
-+	/*
-+	 * Switch the CPU from Symmetric Multiprocessing (SMP) mode
-+	 * to AsymmetricMultiprocessing (AMP) mode by programming
-+	 * the SCU power status to DORMANT or OFF mode.
-+	 * This enables the CPU to be taken out of coherency by
-+	 * preventing the CPU from receiving cache, TLB, or BTB
-+	 * maintenance operations broadcast by other CPUs in the cluster.
-+	 */
-+	bl	omap4_get_sar_ram_base
-+	mov	r8, r0
-+	ldr	r9, [r8, #OMAP_TYPE_OFFSET]
-+	cmp	r9, #0x1			@ Check for HS device
-+	bne	scu_gp_set
-+	mrc	p15, 0, r0, c0, c0, 5		@ Read MPIDR
-+	ands	r0, r0, #0x0f
-+	ldreq	r0, [r8, #SCU_OFFSET0]
-+	ldrne	r0, [r8, #SCU_OFFSET1]
-+	mov	r1, #0x00
-+	stmfd   r13!, {r4-r12, r14}
-+	ldr	r12, =OMAP4_MON_SCU_PWR_INDEX
-+	DO_SMC
-+	ldmfd   r13!, {r4-r12, r14}
-+	b	skip_scu_gp_set
-+scu_gp_set:
-+	mrc	p15, 0, r0, c0, c0, 5		@ Read MPIDR
-+	ands	r0, r0, #0x0f
-+	ldreq	r1, [r8, #SCU_OFFSET0]
-+	ldrne	r1, [r8, #SCU_OFFSET1]
-+	bl	omap4_get_scu_base
-+	bl	scu_power_mode
-+skip_scu_gp_set:
-+	mrc	p15, 0, r0, c1, c1, 2		@ Read NSACR data
-+	tst	r0, #(1 << 18)
-+	mrcne	p15, 0, r0, c1, c0, 1
-+	bicne	r0, r0, #(1 << 6)		@ Disable SMP bit
-+	mcrne	p15, 0, r0, c1, c0, 1
-+	isb
-+	dsb
-+#ifdef CONFIG_CACHE_L2X0
-+	/*
-+	 * Clean and invalidate the L2 cache.
-+	 * Common cache-l2x0.c functions can't be used here since it
-+	 * uses spinlocks. We are out of coherency here with data cache
-+	 * disabled. The spinlock implementation uses exclusive load/store
-+	 * instruction which can fail without data cache being enabled.
-+	 * OMAP4 hardware doesn't support exclusive monitor which can
-+	 * overcome exclusive access issue. Because of this, CPU can
-+	 * lead to deadlock.
-+	 */
-+	bl	omap4_get_sar_ram_base
-+	mov	r8, r0
-+	mrc	p15, 0, r5, c0, c0, 5		@ Read MPIDR
-+	ands	r5, r5, #0x0f
-+	ldreq	r0, [r8, #L2X0_SAVE_OFFSET0]	@ Retrieve L2 state from SAR
-+	ldrne	r0, [r8, #L2X0_SAVE_OFFSET1]	@ memory.
-+	cmp	r0, #3
-+	bne	do_WFI
-+#ifdef CONFIG_PL310_ERRATA_727915
-+	mov	r0, #0x03
-+	mov	r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
-+	DO_SMC
-+#endif
-+	bl	omap4_get_l2cache_base
-+	mov	r2, r0
-+	ldr	r0, =0xffff
-+	str	r0, [r2, #L2X0_CLEAN_INV_WAY]
-+wait:
-+	ldr	r0, [r2, #L2X0_CLEAN_INV_WAY]
-+	ldr	r1, =0xffff
-+	ands	r0, r0, r1
-+	bne	wait
-+#ifdef CONFIG_PL310_ERRATA_727915
-+	mov	r0, #0x00
-+	mov	r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
-+	DO_SMC
-+#endif
-+l2x_sync:
-+	bl	omap4_get_l2cache_base
-+	mov	r2, r0
-+	mov	r0, #0x0
-+	str	r0, [r2, #L2X0_CACHE_SYNC]
-+sync:
-+	ldr	r0, [r2, #L2X0_CACHE_SYNC]
-+	ands	r0, r0, #0x1
-+	bne	sync
-+#endif
-+
-+do_WFI:
-+	bl	omap_do_wfi
-+
-+	/*
-+	 * CPU is here when it failed to enter OFF/DORMANT or
-+	 * no low power state was attempted.
-+	 */
-+	mrc	p15, 0, r0, c1, c0, 0
-+	tst	r0, #(1 << 2)			@ Check C bit enabled?
-+	orreq	r0, r0, #(1 << 2)		@ Enable the C bit
-+	mcreq	p15, 0, r0, c1, c0, 0
-+	isb
-+
-+	/*
-+	 * Ensure the CPU power state is set to NORMAL in
-+	 * SCU power state so that CPU is back in coherency.
-+	 * In non-coherent mode CPU can lock-up and lead to
-+	 * system deadlock.
-+	 */
-+	mrc	p15, 0, r0, c1, c0, 1
-+	tst	r0, #(1 << 6)			@ Check SMP bit enabled?
-+	orreq	r0, r0, #(1 << 6)
-+	mcreq	p15, 0, r0, c1, c0, 1
-+	isb
-+	bl	omap4_get_sar_ram_base
-+	mov	r8, r0
-+	ldr	r9, [r8, #OMAP_TYPE_OFFSET]
-+	cmp	r9, #0x1			@ Check for HS device
-+	bne	scu_gp_clear
-+	mov	r0, #SCU_PM_NORMAL
-+	mov	r1, #0x00
-+	stmfd   r13!, {r4-r12, r14}
-+	ldr	r12, =OMAP4_MON_SCU_PWR_INDEX
-+	DO_SMC
-+	ldmfd   r13!, {r4-r12, r14}
-+	b	skip_scu_gp_clear
-+scu_gp_clear:
-+	bl	omap4_get_scu_base
-+	mov	r1, #SCU_PM_NORMAL
-+	bl	scu_power_mode
-+skip_scu_gp_clear:
-+	isb
-+	dsb
-+	ldmfd	sp!, {pc}
-+ENDPROC(omap4_finish_suspend)
-+
-+/*
-+ * ============================
-+ * == CPU resume entry point ==
-+ * ============================
-+ *
-+ * void omap4_cpu_resume(void)
-+ *
-+ * ROM code jumps to this function while waking up from CPU
-+ * OFF or DORMANT state. Physical address of the function is
-+ * stored in the SAR RAM while entering to OFF or DORMANT mode.
-+ * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
-+ */
-+ENTRY(omap4_cpu_resume)
-+	/*
-+	 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
-+	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
-+	 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
-+	 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
-+	 * OMAP443X GP devices- SMP bit isn't accessible.
-+	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
-+	 */
-+	ldr	r8, =OMAP44XX_SAR_RAM_BASE
-+	ldr	r9, [r8, #OMAP_TYPE_OFFSET]
-+	cmp	r9, #0x1			@ Skip if GP device
-+	bne	skip_ns_smp_enable
-+	mrc     p15, 0, r0, c0, c0, 5
-+	ands    r0, r0, #0x0f
-+	beq	skip_ns_smp_enable
-+ppa_actrl_retry:
-+	mov     r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
-+	adr	r3, ppa_zero_params		@ Pointer to parameters
-+	mov	r1, #0x0			@ Process ID
-+	mov	r2, #0x4			@ Flag
-+	mov	r6, #0xff
-+	mov	r12, #0x00			@ Secure Service ID
-+	DO_SMC
-+	cmp	r0, #0x0			@ API returns 0 on success.
-+	beq	enable_smp_bit
-+	b	ppa_actrl_retry
-+enable_smp_bit:
-+	mrc	p15, 0, r0, c1, c0, 1
-+	tst	r0, #(1 << 6)			@ Check SMP bit enabled?
-+	orreq	r0, r0, #(1 << 6)
-+	mcreq	p15, 0, r0, c1, c0, 1
-+	isb
-+skip_ns_smp_enable:
-+#ifdef CONFIG_CACHE_L2X0
-+	/*
-+	 * Restore the L2 AUXCTRL and enable the L2 cache.
-+	 * OMAP4_MON_L2X0_AUXCTRL_INDEX =  Program the L2X0 AUXCTRL
-+	 * OMAP4_MON_L2X0_CTRL_INDEX =  Enable the L2 using L2X0 CTRL
-+	 * register r0 contains value to be programmed.
-+	 * L2 cache is already invalidate by ROM code as part
-+	 * of MPUSS OFF wakeup path.
-+	 */
-+	ldr	r2, =OMAP44XX_L2CACHE_BASE
-+	ldr	r0, [r2, #L2X0_CTRL]
-+	and	r0, #0x0f
-+	cmp	r0, #1
-+	beq	skip_l2en			@ Skip if already enabled
-+	ldr	r3, =OMAP44XX_SAR_RAM_BASE
-+	ldr	r1, [r3, #OMAP_TYPE_OFFSET]
-+	cmp	r1, #0x1			@ Check for HS device
-+	bne     set_gp_por
-+	ldr     r0, =OMAP4_PPA_L2_POR_INDEX
-+	ldr     r1, =OMAP44XX_SAR_RAM_BASE
-+	ldr     r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
-+	adr     r3, ppa_por_params
-+	str     r4, [r3, #0x04]
-+	mov	r1, #0x0			@ Process ID
-+	mov	r2, #0x4			@ Flag
-+	mov	r6, #0xff
-+	mov	r12, #0x00			@ Secure Service ID
-+	DO_SMC
-+	b	set_aux_ctrl
-+set_gp_por:
-+	ldr     r1, =OMAP44XX_SAR_RAM_BASE
-+	ldr     r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
-+	ldr	r12, =OMAP4_MON_L2X0_PREFETCH_INDEX	@ Setup L2 PREFETCH
-+	DO_SMC
-+set_aux_ctrl:
-+	ldr     r1, =OMAP44XX_SAR_RAM_BASE
-+	ldr	r0, [r1, #L2X0_AUXCTRL_OFFSET]
-+	ldr	r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX	@ Setup L2 AUXCTRL
-+	DO_SMC
-+	mov	r0, #0x1
-+	ldr	r12, =OMAP4_MON_L2X0_CTRL_INDEX		@ Enable L2 cache
-+	DO_SMC
-+skip_l2en:
-+#endif
-+
-+	b	cpu_resume			@ Jump to generic resume
-+ENDPROC(omap4_cpu_resume)
-+#endif
-+
-+#ifndef CONFIG_OMAP4_ERRATA_I688
-+ENTRY(omap_bus_sync)
-+	mov	pc, lr
-+ENDPROC(omap_bus_sync)
-+#endif
-+
-+ENTRY(omap_do_wfi)
-+	stmfd	sp!, {lr}
-+	/* Drain interconnect write buffers. */
-+	bl omap_bus_sync
-+
-+	/*
-+	 * Execute an ISB instruction to ensure that all of the
-+	 * CP15 register changes have been committed.
-+	 */
-+	isb
-+
-+	/*
-+	 * Execute a barrier instruction to ensure that all cache,
-+	 * TLB and branch predictor maintenance operations issued
-+	 * by any CPU in the cluster have completed.
-+	 */
-+	dsb
-+	dmb
-+
-+	/*
-+	 * Execute a WFI instruction and wait until the
-+	 * STANDBYWFI output is asserted to indicate that the
-+	 * CPU is in idle and low power state. CPU can specualatively
-+	 * prefetch the instructions so add NOPs after WFI. Sixteen
-+	 * NOPs as per Cortex-A9 pipeline.
-+	 */
-+	wfi					@ Wait For Interrupt
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+	nop
-+
-+	ldmfd	sp!, {pc}
-+ENDPROC(omap_do_wfi)
-diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index cf246b3..9dd9345 100644
---- a/arch/arm/mach-omap2/smartreflex.c
-+++ b/arch/arm/mach-omap2/smartreflex.c
-@@ -26,7 +26,7 @@
- #include <linux/slab.h>
- #include <linux/pm_runtime.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "pm.h"
- #include "smartreflex.h"
-diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
-index 037b0d7..1af3871 100644
---- a/arch/arm/mach-omap2/timer.c
-+++ b/arch/arm/mach-omap2/timer.c
-@@ -41,12 +41,16 @@
- #include <plat/dmtimer.h>
- #include <asm/localtimer.h>
- #include <asm/sched_clock.h>
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/omap_hwmod.h>
- #include <plat/omap_device.h>
- #include <plat/omap-pm.h>
-+#include <plat/clock.h>
- 
-+#include "clockdomain.h"
- #include "powerdomain.h"
-+#include "cm2xxx_3xxx.h"
-+#include "cminst44xx.h"
- 
- /* Parent clocks, eventually these will come from the clock framework */
- 
-@@ -56,6 +60,7 @@
- #define OMAP2_32K_SOURCE	"func_32k_ck"
- #define OMAP3_32K_SOURCE	"omap_32k_fck"
- #define OMAP4_32K_SOURCE	"sys_32k_ck"
-+#define AM33XX_RTC32K_SOURCE	"clk_32768_ck"
- 
- #ifdef CONFIG_OMAP_32K_TIMER
- #define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
-@@ -139,6 +144,67 @@ static struct clock_event_device clockevent_gpt = {
- 	.set_mode	= omap2_gp_timer_set_mode,
- };
- 
-+static int _is_timer_idle(struct omap_hwmod *oh)
-+{
-+	int ret;
-+
-+	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-+		if (!oh->clkdm)
-+			return -EINVAL;
-+		ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
-+				oh->clkdm->cm_inst,
-+				oh->clkdm->clkdm_offs,
-+				oh->prcm.omap4.clkctrl_offs);
-+	} else if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-+		ret = omap2_cm_wait_module_ready(
-+				oh->prcm.omap2.module_offs,
-+				oh->prcm.omap2.idlest_reg_id,
-+				oh->prcm.omap2.idlest_idle_bit);
-+	} else {
-+		BUG();
-+	}
-+
-+	return ret;
-+}
-+
-+static int omap_dm_timer_switch_src(struct omap_hwmod *oh,
-+		struct omap_dm_timer *timer, const char *fck_source)
-+{
-+	struct clk *src, *cur_parent;
-+	int res;
-+
-+	src = clk_get(NULL, fck_source);
-+	if (IS_ERR(src))
-+		return -EINVAL;
-+
-+	/* Reserve HW/clock-tree default source for fallback */
-+	cur_parent = clk_get_parent(timer->fclk);
-+
-+	/* Switch to configured source */
-+	res = __omap_dm_timer_set_source(timer->fclk, src);
-+	if (IS_ERR_VALUE(res))
-+		pr_warning("%s: timer%i cannot set source\n",
-+				__func__, timer->id);
-+
-+	/* Check whether timer module is went into idle state */
-+	res = _is_timer_idle(oh);
-+	if (res && cur_parent) {
-+		/* Fallback to default timer source */
-+		pr_warning("%s: Switching to HW default clocksource(%s) for "
-+				"timer%i, this may impact timekeeping in low "
-+				"power state\n",
-+				__func__, cur_parent->name, timer->id);
-+
-+		res = __omap_dm_timer_set_source(timer->fclk, cur_parent);
-+		if (IS_ERR_VALUE(res))
-+			pr_warning("%s: timer%i cannot set source\n",
-+					__func__, timer->id);
-+	}
-+	clk_put(src);
-+
-+	return res;
-+}
-+
- static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
- 						int gptimer_id,
- 						const char *fck_source)
-@@ -155,6 +221,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
- 		return -ENODEV;
- 
- 	timer->irq = oh->mpu_irqs[0].irq;
-+	timer->id = gptimer_id;
- 	timer->phys_base = oh->slaves[0]->addr->pa_start;
- 	size = oh->slaves[0]->addr->pa_end - timer->phys_base;
- 
-@@ -178,21 +245,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
- 
- 	omap_hwmod_enable(oh);
- 
--	sys_timer_reserved |= (1 << (gptimer_id - 1));
-+	sys_timer_reserved |= (1 << (gptimer_id));
- 
- 	if (gptimer_id != 12) {
--		struct clk *src;
--
--		src = clk_get(NULL, fck_source);
--		if (IS_ERR(src)) {
--			res = -EINVAL;
--		} else {
--			res = __omap_dm_timer_set_source(timer->fclk, src);
--			if (IS_ERR_VALUE(res))
--				pr_warning("%s: timer%i cannot set source\n",
--						__func__, gptimer_id);
--			clk_put(src);
--		}
-+		res = omap_dm_timer_switch_src(oh, timer, fck_source);
- 	}
- 	__omap_dm_timer_init_regs(timer);
- 	__omap_dm_timer_reset(timer, 1, 1);
-@@ -309,6 +365,35 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
- }
- #endif
- 
-+static void omap_dmtimer_resume(void)
-+{
-+	char name[10];
-+	struct omap_hwmod *oh;
-+
-+	sprintf(name, "timer%d", clkev.id);
-+	oh = omap_hwmod_lookup(name);
-+	if (!oh)
-+		return;
-+
-+	omap_hwmod_enable(oh);
-+	__omap_dm_timer_load_start(&clkev,
-+			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
-+	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
-+}
-+
-+static void omap_dmtimer_suspend(void)
-+{
-+	char name[10];
-+	struct omap_hwmod *oh;
-+
-+	sprintf(name, "timer%d", clkev.id);
-+	oh = omap_hwmod_lookup(name);
-+	if (!oh)
-+		return;
-+
-+	omap_hwmod_idle(oh);
-+}
-+
- #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
- 				clksrc_nr, clksrc_src)			\
- static void __init omap##name##_timer_init(void)			\
-@@ -319,7 +404,9 @@ static void __init omap##name##_timer_init(void)			\
- 
- #define OMAP_SYS_TIMER(name)						\
- struct sys_timer omap##name##_timer = {					\
--	.init	= omap##name##_timer_init,				\
-+	.init		= omap##name##_timer_init,			\
-+	.suspend	= omap_dmtimer_suspend,				\
-+	.resume		= omap_dmtimer_resume,				\
- };
- 
- #ifdef CONFIG_ARCH_OMAP2
-@@ -333,6 +420,8 @@ OMAP_SYS_TIMER(3)
- OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
- 			2, OMAP3_MPU_SOURCE)
- OMAP_SYS_TIMER(3_secure)
-+OMAP_SYS_TIMER_INIT(3_am33xx, 2, OMAP4_MPU_SOURCE, 1, AM33XX_RTC32K_SOURCE)
-+OMAP_SYS_TIMER(3_am33xx)
- #endif
- 
- #ifdef CONFIG_ARCH_OMAP4
-@@ -460,7 +549,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
- 	pdata->timer_ip_version = oh->class->rev;
- 
- 	/* Mark clocksource and clockevent timers as reserved */
--	if ((sys_timer_reserved >> (id - 1)) & 0x1)
-+	if ((sys_timer_reserved & (0x1 << id)))
- 		pdata->reserved = 1;
- 
- 	pwrdm = omap_hwmod_get_pwrdm(oh);
-diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
-index 89ae298..771dc78 100644
---- a/arch/arm/mach-omap2/usb-host.c
-+++ b/arch/arm/mach-omap2/usb-host.c
-@@ -28,51 +28,28 @@
- #include <mach/hardware.h>
- #include <mach/irqs.h>
- #include <plat/usb.h>
-+#include <plat/omap_device.h>
- 
- #include "mux.h"
- 
- #ifdef CONFIG_MFD_OMAP_USB_HOST
- 
--#define OMAP_USBHS_DEVICE	"usbhs-omap"
--
--static struct resource usbhs_resources[] = {
--	{
--		.name	= "uhh",
--		.flags	= IORESOURCE_MEM,
--	},
--	{
--		.name	= "tll",
--		.flags	= IORESOURCE_MEM,
--	},
--	{
--		.name	= "ehci",
--		.flags	= IORESOURCE_MEM,
--	},
--	{
--		.name	= "ehci-irq",
--		.flags	= IORESOURCE_IRQ,
--	},
--	{
--		.name	= "ohci",
--		.flags	= IORESOURCE_MEM,
--	},
--	{
--		.name	= "ohci-irq",
--		.flags	= IORESOURCE_IRQ,
--	}
--};
--
--static struct platform_device usbhs_device = {
--	.name		= OMAP_USBHS_DEVICE,
--	.id		= 0,
--	.num_resources	= ARRAY_SIZE(usbhs_resources),
--	.resource	= usbhs_resources,
--};
-+#define OMAP_USBHS_DEVICE	"usbhs_omap"
-+#define	USBHS_UHH_HWMODNAME	"usb_host_hs"
-+#define USBHS_TLL_HWMODNAME	"usb_tll_hs"
- 
- static struct usbhs_omap_platform_data		usbhs_data;
- static struct ehci_hcd_omap_platform_data	ehci_data;
- static struct ohci_hcd_omap_platform_data	ohci_data;
- 
-+static struct omap_device_pm_latency omap_uhhtll_latency[] = {
-+	  {
-+		.deactivate_func = omap_device_idle_hwmods,
-+		.activate_func	 = omap_device_enable_hwmods,
-+		.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-+	  },
-+};
-+
- /* MUX settings for EHCI pins */
- /*
-  * setup_ehci_io_mux - initialize IO pad mux for USBHOST
-@@ -508,7 +485,10 @@ static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
- 
- void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
- {
--	int	i;
-+	struct omap_hwmod	*oh[2];
-+	struct omap_device	*od;
-+	int			bus_id = -1;
-+	int			i;
- 
- 	for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
- 		usbhs_data.port_mode[i] = pdata->port_mode[i];
-@@ -523,44 +503,34 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
- 	usbhs_data.ohci_data = &ohci_data;
- 
- 	if (cpu_is_omap34xx()) {
--		usbhs_resources[0].start = OMAP34XX_UHH_CONFIG_BASE;
--		usbhs_resources[0].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1;
--		usbhs_resources[1].start = OMAP34XX_USBTLL_BASE;
--		usbhs_resources[1].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1;
--		usbhs_resources[2].start	= OMAP34XX_EHCI_BASE;
--		usbhs_resources[2].end	= OMAP34XX_EHCI_BASE + SZ_1K - 1;
--		usbhs_resources[3].start = INT_34XX_EHCI_IRQ;
--		usbhs_resources[4].start	= OMAP34XX_OHCI_BASE;
--		usbhs_resources[4].end	= OMAP34XX_OHCI_BASE + SZ_1K - 1;
--		usbhs_resources[5].start = INT_34XX_OHCI_IRQ;
- 		setup_ehci_io_mux(pdata->port_mode);
- 		setup_ohci_io_mux(pdata->port_mode);
- 	} else if (cpu_is_omap44xx()) {
--		usbhs_resources[0].start = OMAP44XX_UHH_CONFIG_BASE;
--		usbhs_resources[0].end = OMAP44XX_UHH_CONFIG_BASE + SZ_1K - 1;
--		usbhs_resources[1].start = OMAP44XX_USBTLL_BASE;
--		usbhs_resources[1].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1;
--		usbhs_resources[2].start = OMAP44XX_HSUSB_EHCI_BASE;
--		usbhs_resources[2].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1;
--		usbhs_resources[3].start = OMAP44XX_IRQ_EHCI;
--		usbhs_resources[4].start = OMAP44XX_HSUSB_OHCI_BASE;
--		usbhs_resources[4].end = OMAP44XX_HSUSB_OHCI_BASE + SZ_1K - 1;
--		usbhs_resources[5].start = OMAP44XX_IRQ_OHCI;
- 		setup_4430ehci_io_mux(pdata->port_mode);
- 		setup_4430ohci_io_mux(pdata->port_mode);
- 	}
- 
--	if (platform_device_add_data(&usbhs_device,
--				&usbhs_data, sizeof(usbhs_data)) < 0) {
--		printk(KERN_ERR "USBHS platform_device_add_data failed\n");
--		goto init_end;
-+	oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
-+	if (!oh[0]) {
-+		pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
-+		return;
- 	}
- 
--	if (platform_device_register(&usbhs_device) < 0)
--		printk(KERN_ERR "USBHS platform_device_register failed\n");
-+	oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
-+	if (!oh[1]) {
-+		pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
-+		return;
-+	}
- 
--init_end:
--	return;
-+	od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
-+				(void *)&usbhs_data, sizeof(usbhs_data),
-+				omap_uhhtll_latency,
-+				ARRAY_SIZE(omap_uhhtll_latency), false);
-+	if (IS_ERR(od)) {
-+		pr_err("Could not build hwmod devices %s,%s\n",
-+			USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
-+		return;
-+	}
- }
- 
- #else
-@@ -570,5 +540,3 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
- }
- 
- #endif
--
--
-diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
-index 2679750..7bc40a0 100644
---- a/arch/arm/mach-omap2/usb-musb.c
-+++ b/arch/arm/mach-omap2/usb-musb.c
-@@ -34,28 +34,22 @@
- #include "mux.h"
- 
- static struct musb_hdrc_config musb_config = {
-+	.fifo_mode	= 4,
- 	.multipoint	= 1,
- 	.dyn_fifo	= 1,
- 	.num_eps	= 16,
- 	.ram_bits	= 12,
- };
- 
--static struct musb_hdrc_platform_data musb_plat = {
--#ifdef CONFIG_USB_MUSB_OTG
--	.mode		= MUSB_OTG,
--#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
--	.mode		= MUSB_HOST,
--#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
--	.mode		= MUSB_PERIPHERAL,
--#endif
--	/* .clock is set dynamically */
--	.config		= &musb_config,
--
--	/* REVISIT charge pump on TWL4030 can supply up to
--	 * 100 mA ... but this value is board-specific, like
--	 * "mode", and should be passed to usb_musb_init().
--	 */
--	.power		= 50,			/* up to 100 mA */
-+static struct musb_hdrc_platform_data musb_plat[] = {
-+	{
-+		.config         = &musb_config,
-+		.clock          = "ick",
-+	},
-+	{
-+		.config         = &musb_config,
-+		.clock          = "ick",
-+	},
- };
- 
- static u64 musb_dmamask = DMA_BIT_MASK(32);
-@@ -84,15 +78,27 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
- 	 * REVISIT: This line can be removed once all the platforms using
- 	 * musb_core.c have been converted to use use clkdev.
- 	 */
--	musb_plat.clock = "ick";
--	musb_plat.board_data = board_data;
--	musb_plat.power = board_data->power >> 1;
--	musb_plat.mode = board_data->mode;
--	musb_plat.extvbus = board_data->extvbus;
-+	musb_plat[0].clock = "ick";
-+	musb_plat[0].board_data = board_data;
-+	musb_plat[0].power = board_data->power >> 1;
-+	musb_plat[0].mode = board_data->mode;
-+	musb_plat[0].extvbus = board_data->extvbus;
-+
-+	/*
-+	 * OMAP3630/AM35x platform has MUSB RTL-1.8 which has the fix for the
-+	 * issue restricting active endpoints to use first 8K of FIFO space.
-+	 * This issue restricts OMAP35x platform to use fifo_mode '5'.
-+	 */
-+	if (cpu_is_omap3430())
-+		musb_config.fifo_mode = 5;
- 
- 	if (cpu_is_omap3517() || cpu_is_omap3505()) {
- 		oh_name = "am35x_otg_hs";
- 		name = "musb-am35x";
-+	} else if (cpu_is_ti81xx() || cpu_is_am33xx()) {
-+		board_data->set_phy_power = ti81xx_musb_phy_power;
-+		oh_name = "usb_otg_hs";
-+		name = "musb-ti81xx";
- 	} else {
- 		oh_name = "usb_otg_hs";
- 		name = "musb-omap2430";
-diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
-index 031d116..e78f5a8 100644
---- a/arch/arm/mach-omap2/vc.c
-+++ b/arch/arm/mach-omap2/vc.c
-@@ -292,9 +292,8 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
- 	u32 val;
- 
- 	if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
--		pr_err("%s: PMIC info requried to configure vc for"
--			"vdd_%s not populated.Hence cannot initialize vc\n",
--			__func__, voltdm->name);
-+		pr_err("%s: missing PMIC for vdd_%s.\n",
-+		       __func__, voltdm->name);
- 		return;
- 	}
- 
-diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
-index cfe348e..a5ec7f8f 100644
---- a/arch/arm/mach-omap2/vc3xxx_data.c
-+++ b/arch/arm/mach-omap2/vc3xxx_data.c
-@@ -18,7 +18,7 @@
- #include <linux/err.h>
- #include <linux/init.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "prm-regbits-34xx.h"
- #include "voltage.h"
-diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
-index 2740a96..d70b930 100644
---- a/arch/arm/mach-omap2/vc44xx_data.c
-+++ b/arch/arm/mach-omap2/vc44xx_data.c
-@@ -18,7 +18,7 @@
- #include <linux/err.h>
- #include <linux/init.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "prm44xx.h"
- #include "prm-regbits-44xx.h"
-diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
-index 1f8fdf7..8a36342 100644
---- a/arch/arm/mach-omap2/voltage.c
-+++ b/arch/arm/mach-omap2/voltage.c
-@@ -27,7 +27,7 @@
- #include <linux/slab.h>
- #include <linux/clk.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "prm-regbits-34xx.h"
- #include "prm-regbits-44xx.h"
-diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
-index 16a1b09..a7c43c1 100644
---- a/arch/arm/mach-omap2/voltage.h
-+++ b/arch/arm/mach-omap2/voltage.h
-@@ -156,6 +156,7 @@ int omap_voltage_late_init(void);
- 
- extern void omap2xxx_voltagedomains_init(void);
- extern void omap3xxx_voltagedomains_init(void);
-+extern void am33xx_voltagedomains_init(void);
- extern void omap44xx_voltagedomains_init(void);
- 
- struct voltagedomain *voltdm_lookup(const char *name);
-diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
-new file mode 100644
-index 0000000..965458d
---- /dev/null
-+++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
-@@ -0,0 +1,43 @@
-+/*
-+ * AM33XX voltage domain data
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+
-+#include "voltage.h"
-+
-+static struct voltagedomain am33xx_voltdm_mpu = {
-+	.name		= "mpu",
-+};
-+
-+static struct voltagedomain am33xx_voltdm_core = {
-+	.name		= "core",
-+};
-+
-+static struct voltagedomain am33xx_voltdm_rtc = {
-+	.name		= "rtc",
-+};
-+
-+static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
-+	&am33xx_voltdm_mpu,
-+	&am33xx_voltdm_core,
-+	&am33xx_voltdm_rtc,
-+	NULL,
-+};
-+
-+void __init am33xx_voltagedomains_init(void)
-+{
-+	voltdm_init(voltagedomains_am33xx);
-+}
-diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
-index 071101d..c005e2f 100644
---- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
-+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
-@@ -18,7 +18,7 @@
- #include <linux/err.h>
- #include <linux/init.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- #include <plat/cpu.h>
- 
- #include "prm-regbits-34xx.h"
-@@ -31,6 +31,14 @@
-  * VDD data
-  */
- 
-+/* OMAP3-common voltagedomain data */
-+
-+static struct voltagedomain omap3_voltdm_wkup = {
-+	.name = "wakeup",
-+};
-+
-+/* 34xx/36xx voltagedomain data */
-+
- static const struct omap_vfsm_instance omap3_vdd1_vfsm = {
- 	.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
- 	.voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
-@@ -63,10 +71,6 @@ static struct voltagedomain omap3_voltdm_core = {
- 	.vp = &omap3_vp_core,
- };
- 
--static struct voltagedomain omap3_voltdm_wkup = {
--	.name = "wakeup",
--};
--
- static struct voltagedomain *voltagedomains_omap3[] __initdata = {
- 	&omap3_voltdm_mpu,
- 	&omap3_voltdm_core,
-@@ -74,11 +78,30 @@ static struct voltagedomain *voltagedomains_omap3[] __initdata = {
- 	NULL,
- };
- 
-+/* AM35xx voltagedomain data */
-+
-+static struct voltagedomain am35xx_voltdm_mpu = {
-+	.name = "mpu_iva",
-+};
-+
-+static struct voltagedomain am35xx_voltdm_core = {
-+	.name = "core",
-+};
-+
-+static struct voltagedomain *voltagedomains_am35xx[] __initdata = {
-+	&am35xx_voltdm_mpu,
-+	&am35xx_voltdm_core,
-+	&omap3_voltdm_wkup,
-+	NULL,
-+};
-+
-+
- static const char *sys_clk_name __initdata = "sys_ck";
- 
- void __init omap3xxx_voltagedomains_init(void)
- {
- 	struct voltagedomain *voltdm;
-+	struct voltagedomain **voltdms;
- 	int i;
- 
- 	/*
-@@ -93,8 +116,13 @@ void __init omap3xxx_voltagedomains_init(void)
- 		omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
- 	}
- 
--	for (i = 0; voltdm = voltagedomains_omap3[i], voltdm; i++)
-+	if (cpu_is_omap3517() || cpu_is_omap3505())
-+		voltdms = voltagedomains_am35xx;
-+	else
-+		voltdms = voltagedomains_omap3;
-+
-+	for (i = 0; voltdm = voltdms[i], voltdm; i++)
- 		voltdm->sys_clk.name = sys_clk_name;
- 
--	voltdm_init(voltagedomains_omap3);
-+	voltdm_init(voltdms);
- };
-diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
-index c4584e9..4e11d02 100644
---- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
-+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
-@@ -21,7 +21,7 @@
- #include <linux/err.h>
- #include <linux/init.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "prm-regbits-44xx.h"
- #include "prm44xx.h"
-diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
-index 3b52027..fde109c 100644
---- a/arch/arm/mach-omap2/vp.c
-+++ b/arch/arm/mach-omap2/vp.c
-@@ -1,7 +1,7 @@
- #include <linux/kernel.h>
- #include <linux/init.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "voltage.h"
- #include "vp.h"
-@@ -42,7 +42,8 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
- 	u32 vddmin, vddmax, vstepmin, vstepmax;
- 
- 	if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
--		pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
-+		pr_err("%s: missing PMIC for vdd_%s.\n",
-+		       __func__, voltdm->name);
- 		return;
- 	}
- 
-diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
-index 260c554..bd89f80 100644
---- a/arch/arm/mach-omap2/vp3xxx_data.c
-+++ b/arch/arm/mach-omap2/vp3xxx_data.c
-@@ -19,7 +19,7 @@
- #include <linux/err.h>
- #include <linux/init.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "prm-regbits-34xx.h"
- #include "voltage.h"
-diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
-index b4e7704..8c031d1 100644
---- a/arch/arm/mach-omap2/vp44xx_data.c
-+++ b/arch/arm/mach-omap2/vp44xx_data.c
-@@ -19,7 +19,7 @@
- #include <linux/err.h>
- #include <linux/init.h>
- 
--#include <plat/common.h>
-+#include "common.h"
- 
- #include "prm44xx.h"
- #include "prm-regbits-44xx.h"
-diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
-index c519610..e9d9afd 100644
---- a/arch/arm/mach-orion5x/include/mach/io.h
-+++ b/arch/arm/mach-orion5x/include/mach/io.h
-@@ -15,31 +15,6 @@
- 
- #define IO_SPACE_LIMIT		0xffffffff
- 
--static inline void __iomem *
--__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
--{
--	void __iomem *retval;
--	unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE;
--	if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE &&
--	    size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) {
--		retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs;
--	} else {
--		retval = __arm_ioremap(paddr, size, mtype);
--	}
--
--	return retval;
--}
--
--static inline void
--__arch_iounmap(void __iomem *addr)
--{
--	if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
--	    addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
--		__iounmap(addr);
--}
--
--#define __arch_ioremap		__arch_ioremap
--#define __arch_iounmap		__arch_iounmap
- #define __io(a)			__typesafe_io(a)
- #define __mem_pci(a)		(a)
- 
-diff --git a/arch/arm/mach-orion5x/include/mach/vmalloc.h b/arch/arm/mach-orion5x/include/mach/vmalloc.h
-deleted file mode 100644
-index 06b50ae..0000000
---- a/arch/arm/mach-orion5x/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,5 +0,0 @@
--/*
-- * arch/arm/mach-orion5x/include/mach/vmalloc.h
-- */
--
--#define VMALLOC_END       0xfd800000UL
-diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
-index 34d0834..ad871bd 100644
---- a/arch/arm/mach-picoxcell/common.c
-+++ b/arch/arm/mach-picoxcell/common.c
-@@ -11,6 +11,7 @@
- #include <linux/irqdomain.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
-+#include <linux/of_irq.h>
- #include <linux/of_platform.h>
- 
- #include <asm/mach/arch.h>
-@@ -33,22 +34,20 @@ static const char *picoxcell_dt_match[] = {
- };
- 
- static const struct of_device_id vic_of_match[] __initconst = {
--	{ .compatible = "arm,pl192-vic" },
-+	{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
- 	{ /* Sentinel */ }
- };
- 
- static void __init picoxcell_init_irq(void)
- {
--	vic_init(IO_ADDRESS(PICOXCELL_VIC0_BASE), 0, ~0, 0);
--	vic_init(IO_ADDRESS(PICOXCELL_VIC1_BASE), 32, ~0, 0);
--	irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC0_BASE, 0);
--	irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC1_BASE, 32);
-+	of_irq_init(vic_of_match);
- }
- 
- DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
- 	.map_io		= picoxcell_map_io,
- 	.nr_irqs	= ARCH_NR_IRQS,
- 	.init_irq	= picoxcell_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &picoxcell_timer,
- 	.init_machine	= picoxcell_init_machine,
- 	.dt_compat	= picoxcell_dt_match,
-diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
-index a6b09f7..9b505ac 100644
---- a/arch/arm/mach-picoxcell/include/mach/entry-macro.S
-+++ b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
-@@ -9,11 +9,8 @@
-  * License version 2. This program is licensed "as is" without any
-  * warranty of any kind, whether express or implied.
-  */
--#include <mach/hardware.h>
--#include <mach/irqs.h>
--#include <mach/map.h>
-+	.macro  disable_fiq
-+	.endm
- 
--#define VA_VIC0		IO_ADDRESS(PICOXCELL_VIC0_BASE)
--#define VA_VIC1		IO_ADDRESS(PICOXCELL_VIC1_BASE)
--
--#include <asm/entry-macro-vic2.S>
-+	.macro  arch_ret_to_user, tmp1, tmp2
-+	.endm
-diff --git a/arch/arm/mach-picoxcell/include/mach/vmalloc.h b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
-deleted file mode 100644
-index 0216cc4..0000000
---- a/arch/arm/mach-picoxcell/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,14 +0,0 @@
--/*
-- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- */
--#define VMALLOC_END	0xfe000000UL
-diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h
-index 5dda2bb..5d6384a 100644
---- a/arch/arm/mach-pnx4008/include/mach/system.h
-+++ b/arch/arm/mach-pnx4008/include/mach/system.h
-@@ -32,7 +32,7 @@ static void arch_idle(void)
- 
- static inline void arch_reset(char mode, const char *cmd)
- {
--	cpu_reset(0);
-+	soft_restart(0);
- }
- 
- #endif
-diff --git a/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
-deleted file mode 100644
-index 184913c..0000000
---- a/arch/arm/mach-pnx4008/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/*
-- * arch/arm/mach-pnx4008/include/mach/vmalloc.h
-- *
-- * Author: Vitaly Wool <source@mvista.com>
-- *
-- * 2006 (c) MontaVista Software, Inc. This file is licensed under
-- * the terms of the GNU General Public License version 2. This program
-- * is licensed "as is" without any warranty of any kind, whether express
-- * or implied.
-- */
--
--/*
-- * Just any arbitrary offset to the start of the vmalloc VM area: the
-- * current 8MB value just means that there will be a 8MB "hole" after the
-- * physical memory until the kernel virtual memory starts.  That means that
-- * any out-of-bounds memory accesses will hopefully be caught.
-- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
-- * area for the same reason. ;)
-- */
--#define VMALLOC_END       0xd0000000UL
-diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
-index 66b1ae2..6f24353 100644
---- a/arch/arm/mach-prima2/include/mach/map.h
-+++ b/arch/arm/mach-prima2/include/mach/map.h
-@@ -9,8 +9,10 @@
- #ifndef __MACH_PRIMA2_MAP_H__
- #define __MACH_PRIMA2_MAP_H__
- 
--#include <mach/vmalloc.h>
-+#include <linux/const.h>
- 
--#define SIRFSOC_VA(x)			(VMALLOC_END + ((x) & 0x00FFF000))
-+#define SIRFSOC_VA_BASE		_AC(0xFEC00000, UL)
-+
-+#define SIRFSOC_VA(x)		(SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
- 
- #endif
-diff --git a/arch/arm/mach-prima2/include/mach/vmalloc.h b/arch/arm/mach-prima2/include/mach/vmalloc.h
-deleted file mode 100644
-index c9f90fe..0000000
---- a/arch/arm/mach-prima2/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,16 +0,0 @@
--/*
-- * arch/arm/ach-prima2/include/mach/vmalloc.h
-- *
-- * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
-- *
-- * Licensed under GPLv2 or later.
-- */
--
--#ifndef __MACH_VMALLOC_H
--#define __MACH_VMALLOC_H
--
--#include <linux/const.h>
--
--#define VMALLOC_END    _AC(0xFEC00000, UL)
--
--#endif
-diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
-index a73bc86..260c0c1 100644
---- a/arch/arm/mach-pxa/include/mach/entry-macro.S
-+++ b/arch/arm/mach-pxa/include/mach/entry-macro.S
-@@ -7,45 +7,9 @@
-  * License version 2. This program is licensed "as is" without any
-  * warranty of any kind, whether express or implied.
-  */
--#include <mach/hardware.h>
--#include <mach/irqs.h>
- 
- 		.macro	disable_fiq
- 		.endm
- 
--		.macro  get_irqnr_preamble, base, tmp
--		.endm
--
- 		.macro  arch_ret_to_user, tmp1, tmp2
- 		.endm
--
--		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--		mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
--		mov	\tmp, \tmp, lsr #13
--		and	\tmp, \tmp, #0x7		@ Core G
--		cmp	\tmp, #1
--		bhi	1002f
--
--		@ Core Generation 1 (PXA25x)
--		mov	\base, #io_p2v(0x40000000)	@ IIR Ctl = 0x40d00000
--		add	\base, \base, #0x00d00000
--		ldr	\irqstat, [\base, #0]		@ ICIP
--		ldr	\irqnr, [\base, #4]		@ ICMR
--
--		ands	\irqnr, \irqstat, \irqnr
--		beq	1001f
--		rsb	\irqstat, \irqnr, #0
--		and	\irqstat, \irqstat, \irqnr
--		clz	\irqnr, \irqstat
--		rsb	\irqnr, \irqnr, #(31 + PXA_IRQ(0))
--		b	1001f
--1002:
--		@ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
--		mrc	p6, 0, \irqstat, c5, c0, 0	@ ICHP
--		tst	\irqstat, #0x80000000
--		beq	1001f
--		bic	\irqstat, \irqstat, #0x80000000
--		mov	\irqnr, \irqstat, lsr #16
--		add	\irqnr, \irqnr, #(PXA_IRQ(0))
--1001:
--		.endm
-diff --git a/arch/arm/mach-pxa/include/mach/vmalloc.h b/arch/arm/mach-pxa/include/mach/vmalloc.h
-deleted file mode 100644
-index bfecfbf..0000000
---- a/arch/arm/mach-pxa/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,11 +0,0 @@
--/*
-- * arch/arm/mach-pxa/include/mach/vmalloc.h
-- *
-- * Author:	Nicolas Pitre
-- * Copyright:	(C) 2001 MontaVista Software Inc.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--#define VMALLOC_END       (0xe8000000UL)
-diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
-index b938fc2..4f47a76 100644
---- a/arch/arm/mach-pxa/mioa701.c
-+++ b/arch/arm/mach-pxa/mioa701.c
-@@ -752,6 +752,7 @@ static void mioa701_machine_exit(void)
- 
- MACHINE_START(MIOA701, "MIO A701")
- 	.atag_offset	= 0x100,
-+	.restart_mode	= 's',
- 	.map_io		= &pxa27x_map_io,
- 	.init_irq	= &pxa27x_init_irq,
- 	.handle_irq	= &pxa27x_handle_irq,
-diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
-index 50c8331..afcb48a 100644
---- a/arch/arm/mach-pxa/poodle.c
-+++ b/arch/arm/mach-pxa/poodle.c
-@@ -420,17 +420,11 @@ static void poodle_poweroff(void)
- 	arm_machine_restart('h', NULL);
- }
- 
--static void poodle_restart(char mode, const char *cmd)
--{
--	arm_machine_restart('h', cmd);
--}
--
- static void __init poodle_init(void)
- {
- 	int ret = 0;
- 
- 	pm_power_off = poodle_poweroff;
--	arm_pm_restart = poodle_restart;
- 
- 	PCFR |= PCFR_OPDE;
- 
-diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
-index 01e9d64..b8bcda1 100644
---- a/arch/arm/mach-pxa/reset.c
-+++ b/arch/arm/mach-pxa/reset.c
-@@ -88,7 +88,7 @@ void arch_reset(char mode, const char *cmd)
- 	switch (mode) {
- 	case 's':
- 		/* Jump into ROM at address 0 */
--		cpu_reset(0);
-+		soft_restart(0);
- 		break;
- 	case 'g':
- 		do_gpio_reset();
-diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
-index 953a919..2f57d94 100644
---- a/arch/arm/mach-pxa/spitz.c
-+++ b/arch/arm/mach-pxa/spitz.c
-@@ -982,6 +982,7 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
- 
- #ifdef CONFIG_MACH_SPITZ
- MACHINE_START(SPITZ, "SHARP Spitz")
-+	.restart_mode	= 'g',
- 	.fixup		= spitz_fixup,
- 	.map_io		= pxa27x_map_io,
- 	.init_irq	= pxa27x_init_irq,
-@@ -993,6 +994,7 @@ MACHINE_END
- 
- #ifdef CONFIG_MACH_BORZOI
- MACHINE_START(BORZOI, "SHARP Borzoi")
-+	.restart_mode	= 'g',
- 	.fixup		= spitz_fixup,
- 	.map_io		= pxa27x_map_io,
- 	.init_irq	= pxa27x_init_irq,
-@@ -1004,6 +1006,7 @@ MACHINE_END
- 
- #ifdef CONFIG_MACH_AKITA
- MACHINE_START(AKITA, "SHARP Akita")
-+	.restart_mode	= 'g',
- 	.fixup		= spitz_fixup,
- 	.map_io		= pxa27x_map_io,
- 	.init_irq	= pxa27x_init_irq,
-diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
-index 402b0c9..ef64530 100644
---- a/arch/arm/mach-pxa/tosa.c
-+++ b/arch/arm/mach-pxa/tosa.c
-@@ -970,6 +970,7 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
- }
- 
- MACHINE_START(TOSA, "SHARP Tosa")
-+	.restart_mode	= 'g',
- 	.fixup          = fixup_tosa,
- 	.map_io         = pxa25x_map_io,
- 	.nr_irqs	= TOSA_NR_IRQS,
-diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
-index 4071164..e8a5179 100644
---- a/arch/arm/mach-realview/include/mach/entry-macro.S
-+++ b/arch/arm/mach-realview/include/mach/entry-macro.S
-@@ -7,8 +7,6 @@
-  * License version 2. This program is licensed "as is" without any
-  * warranty of any kind, whether express or implied.
-  */
--#include <mach/hardware.h>
--#include <asm/hardware/entry-macro-gic.S>
- 
- 		.macro	disable_fiq
- 		.endm
-diff --git a/arch/arm/mach-realview/include/mach/vmalloc.h b/arch/arm/mach-realview/include/mach/vmalloc.h
-deleted file mode 100644
-index a2a4c68..0000000
---- a/arch/arm/mach-realview/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,21 +0,0 @@
--/*
-- *  arch/arm/mach-realview/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2003 ARM Limited
-- *  Copyright (C) 2000 Russell King.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#define VMALLOC_END		0xf8000000UL
-diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
-index 026c66a..1ca944a 100644
---- a/arch/arm/mach-realview/realview_eb.c
-+++ b/arch/arm/mach-realview/realview_eb.c
-@@ -91,8 +91,8 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
- 
- static struct map_desc realview_eb11mp_io_desc[] __initdata = {
- 	{
--		.virtual	= IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
--		.pfn		= __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
-+		.virtual	= IO_ADDRESS(REALVIEW_EB11MP_SCU_BASE),
-+		.pfn		= __phys_to_pfn(REALVIEW_EB11MP_SCU_BASE),
- 		.length		= SZ_4K,
- 		.type		= MT_DEVICE,
- 	}, {
-@@ -469,6 +469,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
- 	.init_early	= realview_init_early,
- 	.init_irq	= gic_init_irq,
- 	.timer		= &realview_eb_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= realview_eb_init,
- #ifdef CONFIG_ZONE_DMA
- 	.dma_zone_size	= SZ_256M,
-diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
-index c057540..bd8fec8 100644
---- a/arch/arm/mach-realview/realview_pb1176.c
-+++ b/arch/arm/mach-realview/realview_pb1176.c
-@@ -392,6 +392,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
- 	.init_early	= realview_init_early,
- 	.init_irq	= gic_init_irq,
- 	.timer		= &realview_pb1176_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= realview_pb1176_init,
- #ifdef CONFIG_ZONE_DMA
- 	.dma_zone_size	= SZ_256M,
-diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
-index 671ad6d..fa73ba8 100644
---- a/arch/arm/mach-realview/realview_pb11mp.c
-+++ b/arch/arm/mach-realview/realview_pb11mp.c
-@@ -366,6 +366,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
- 	.init_early	= realview_init_early,
- 	.init_irq	= gic_init_irq,
- 	.timer		= &realview_pb11mp_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= realview_pb11mp_init,
- #ifdef CONFIG_ZONE_DMA
- 	.dma_zone_size	= SZ_256M,
-diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
-index cbf22df..6e5f2b9 100644
---- a/arch/arm/mach-realview/realview_pba8.c
-+++ b/arch/arm/mach-realview/realview_pba8.c
-@@ -316,6 +316,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
- 	.init_early	= realview_init_early,
- 	.init_irq	= gic_init_irq,
- 	.timer		= &realview_pba8_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= realview_pba8_init,
- #ifdef CONFIG_ZONE_DMA
- 	.dma_zone_size	= SZ_256M,
-diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
-index 63c4114..7aabc21 100644
---- a/arch/arm/mach-realview/realview_pbx.c
-+++ b/arch/arm/mach-realview/realview_pbx.c
-@@ -98,8 +98,8 @@ static struct map_desc realview_pbx_io_desc[] __initdata = {
- 
- static struct map_desc realview_local_io_desc[] __initdata = {
- 	{
--		.virtual        = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_CPU_BASE),
--		.pfn            = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_CPU_BASE),
-+		.virtual        = IO_ADDRESS(REALVIEW_PBX_TILE_SCU_BASE),
-+		.pfn            = __phys_to_pfn(REALVIEW_PBX_TILE_SCU_BASE),
- 		.length         = SZ_4K,
- 		.type           = MT_DEVICE,
- 	}, {
-@@ -399,6 +399,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
- 	.init_early	= realview_init_early,
- 	.init_irq	= gic_init_irq,
- 	.timer		= &realview_pbx_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= realview_pbx_init,
- #ifdef CONFIG_ZONE_DMA
- 	.dma_zone_size	= SZ_256M,
-diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h
-index 45c7b93..a354f4d 100644
---- a/arch/arm/mach-rpc/include/mach/system.h
-+++ b/arch/arm/mach-rpc/include/mach/system.h
-@@ -23,5 +23,5 @@ static inline void arch_reset(char mode, const char *cmd)
- 	/*
- 	 * Jump into the ROM
- 	 */
--	cpu_reset(0);
-+	soft_restart(0);
- }
-diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h
-deleted file mode 100644
-index fb70022..0000000
---- a/arch/arm/mach-rpc/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,10 +0,0 @@
--/*
-- *  arch/arm/mach-rpc/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 1997 Russell King
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--#define VMALLOC_END       0xdc000000UL
-diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
-index 6faadce..913893d 100644
---- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
-+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
-@@ -19,7 +19,7 @@ static void
- arch_reset(char mode, const char *cmd)
- {
- 	if (mode == 's') {
--		cpu_reset(0);
-+		soft_restart(0);
- 	}
- 
- 	if (s3c24xx_reset_hook)
-@@ -28,5 +28,5 @@ arch_reset(char mode, const char *cmd)
- 	arch_wdt_reset();
- 
- 	/* we'll take a jump through zero as a poor second */
--	cpu_reset(0);
-+	soft_restart(0);
- }
-diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
-deleted file mode 100644
-index 7a311e8..0000000
---- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
-- *
-- * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
-- *
-- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
-- *		      http://www.simtec.co.uk/products/SWLINUX/
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- *
-- * S3C2410 vmalloc definition
--*/
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H
--
--#define VMALLOC_END	0xF6000000UL
--
--#endif /* __ASM_ARCH_VMALLOC_H */
-diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
-index dd36260..dc2bc15 100644
---- a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
-+++ b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
-@@ -12,7 +12,8 @@
-  * warranty of any kind, whether express or implied.
- */
- 
--#include <mach/map.h>
--#include <mach/irqs.h>
-+		.macro  disable_fiq
-+		.endm
- 
--#include <asm/entry-macro-vic2.S>
-+		.macro  arch_ret_to_user, tmp1, tmp2
-+		.endm
-diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
-index 2e58cb7..d8ca578 100644
---- a/arch/arm/mach-s3c64xx/include/mach/system.h
-+++ b/arch/arm/mach-s3c64xx/include/mach/system.h
-@@ -24,7 +24,7 @@ static void arch_reset(char mode, const char *cmd)
- 		arch_wdt_reset();
- 
- 	/* if all else fails, or mode was for soft, jump to 0 */
--	cpu_reset(0);
-+	soft_restart(0);
- }
- 
- #endif /* __ASM_ARCH_IRQ_H */
-diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
-deleted file mode 100644
-index 23f75e5..0000000
---- a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/* arch/arm/mach-s3c64xx/include/mach/vmalloc.h
-- *
-- * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
-- *
-- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
-- *		      http://www.simtec.co.uk/products/SWLINUX/
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- *
-- * S3C6400 vmalloc definition
--*/
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H
--
--#define VMALLOC_END	0xF6000000UL
--
--#endif /* __ASM_ARCH_VMALLOC_H */
-diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
-index 8eba88e..2bbc14d 100644
---- a/arch/arm/mach-s3c64xx/mach-anw6410.c
-+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
-@@ -30,6 +30,7 @@
- 
- #include <video/platform_lcd.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/mach/irq.h>
-@@ -236,6 +237,7 @@ MACHINE_START(ANW6410, "A&W6410")
- 	.atag_offset	= 0x100,
- 
- 	.init_irq	= s3c6410_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= anw6410_map_io,
- 	.init_machine	= anw6410_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
-index d04b654..988ac2e 100644
---- a/arch/arm/mach-s3c64xx/mach-crag6410.c
-+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
-@@ -37,6 +37,7 @@
- #include <linux/mfd/wm831x/irq.h>
- #include <linux/mfd/wm831x/gpio.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach-types.h>
- 
-@@ -711,6 +712,7 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
- 	/* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s3c6410_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= crag6410_map_io,
- 	.init_machine	= crag6410_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
-index 952f75f..c5955f3 100644
---- a/arch/arm/mach-s3c64xx/mach-hmt.c
-+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
-@@ -29,6 +29,7 @@
- #include <mach/hardware.h>
- #include <mach/map.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/irq.h>
- #include <asm/mach-types.h>
- 
-@@ -267,6 +268,7 @@ MACHINE_START(HMT, "Airgoo-HMT")
- 	/* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s3c6410_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= hmt_map_io,
- 	.init_machine	= hmt_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
-index 1bc85c3..4415c85 100644
---- a/arch/arm/mach-s3c64xx/mach-mini6410.c
-+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
-@@ -24,6 +24,7 @@
- #include <linux/serial_core.h>
- #include <linux/types.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
-@@ -345,6 +346,7 @@ MACHINE_START(MINI6410, "MINI6410")
- 	/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s3c6410_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= mini6410_map_io,
- 	.init_machine	= mini6410_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
-index cb13cba..9b2c610 100644
---- a/arch/arm/mach-s3c64xx/mach-ncp.c
-+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
-@@ -25,6 +25,7 @@
- 
- #include <video/platform_lcd.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/mach/irq.h>
-@@ -99,6 +100,7 @@ MACHINE_START(NCP, "NCP")
- 	/* Maintainer: Samsung Electronics */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s3c6410_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= ncp_map_io,
- 	.init_machine	= ncp_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
-index 87281e4..dbab49f 100644
---- a/arch/arm/mach-s3c64xx/mach-real6410.c
-+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
-@@ -25,6 +25,7 @@
- #include <linux/serial_core.h>
- #include <linux/types.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
-@@ -326,6 +327,7 @@ MACHINE_START(REAL6410, "REAL6410")
- 	.atag_offset	= 0x100,
- 
- 	.init_irq	= s3c6410_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= real6410_map_io,
- 	.init_machine	= real6410_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
-index 94c831d..0539452 100644
---- a/arch/arm/mach-s3c64xx/mach-smartq5.c
-+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
-@@ -17,6 +17,7 @@
- #include <linux/leds.h>
- #include <linux/platform_device.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
-@@ -148,6 +149,7 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
- 	/* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s3c6410_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= smartq_map_io,
- 	.init_machine	= smartq5_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
-index f112547..a58d1ba 100644
---- a/arch/arm/mach-s3c64xx/mach-smartq7.c
-+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
-@@ -17,6 +17,7 @@
- #include <linux/leds.h>
- #include <linux/platform_device.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
-@@ -164,6 +165,7 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
- 	/* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s3c6410_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= smartq_map_io,
- 	.init_machine	= smartq7_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
-index 73450c2..be28a59 100644
---- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
-+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
-@@ -22,6 +22,7 @@
- 
- #include <asm/mach-types.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/mach/irq.h>
-@@ -88,6 +89,7 @@ MACHINE_START(SMDK6400, "SMDK6400")
- 	.atag_offset	= 0x100,
- 
- 	.init_irq	= s3c6400_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= smdk6400_map_io,
- 	.init_machine	= smdk6400_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
-index 8bc8edd..0830915 100644
---- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
-+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
-@@ -43,6 +43,7 @@
- 
- #include <video/platform_lcd.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/mach/irq.h>
-@@ -700,6 +701,7 @@ MACHINE_START(SMDK6410, "SMDK6410")
- 	.atag_offset	= 0x100,
- 
- 	.init_irq	= s3c6410_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= smdk6410_map_io,
- 	.init_machine	= smdk6410_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
-index 10b62b4..fbb246d 100644
---- a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
-+++ b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
-@@ -10,7 +10,8 @@
-  * published by the Free Software Foundation.
- */
- 
--#include <mach/map.h>
--#include <plat/irqs.h>
-+		.macro  disable_fiq
-+		.endm
- 
--#include <asm/entry-macro-vic2.S>
-+		.macro  arch_ret_to_user, tmp1, tmp2
-+		.endm
-diff --git a/arch/arm/mach-s5p64x0/include/mach/vmalloc.h b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
-deleted file mode 100644
-index 38dcc71..0000000
---- a/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/* linux/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
-- *
-- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
-- *		http://www.samsung.com
-- *
-- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- *
-- * S3C6400 vmalloc definition
--*/
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H
--
--#define VMALLOC_END	0xF6000000UL
--
--#endif /* __ASM_ARCH_VMALLOC_H */
-diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
-index 4a1250c..c272c3f 100644
---- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
-+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
-@@ -27,6 +27,7 @@
- 
- #include <video/platform_lcd.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/irq.h>
-@@ -242,6 +243,7 @@ MACHINE_START(SMDK6440, "SMDK6440")
- 	.atag_offset	= 0x100,
- 
- 	.init_irq	= s5p6440_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= smdk6440_map_io,
- 	.init_machine	= smdk6440_machine_init,
- 	.timer		= &s5p_timer,
-diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
-index 0ab129e..7a47009 100644
---- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
-+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
-@@ -27,6 +27,7 @@
- 
- #include <video/platform_lcd.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/irq.h>
-@@ -262,6 +263,7 @@ MACHINE_START(SMDK6450, "SMDK6450")
- 	.atag_offset	= 0x100,
- 
- 	.init_irq	= s5p6450_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= smdk6450_map_io,
- 	.init_machine	= smdk6450_machine_init,
- 	.timer		= &s5p_timer,
-diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
-index ba76af0..b8c242e 100644
---- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
-+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
-@@ -12,39 +12,14 @@
-  * warranty of any kind, whether express or implied.
- */
- 
--#include <asm/hardware/vic.h>
--#include <mach/map.h>
--#include <plat/irqs.h>
--
- 	.macro	disable_fiq
- 	.endm
- 
- 	.macro	get_irqnr_preamble, base, tmp
--	ldr	\base, =VA_VIC0
- 	.endm
- 
- 	.macro	arch_ret_to_user, tmp1, tmp2
- 	.endm
- 
- 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--
--	@ check the vic0
--	mov	\irqnr, # S5P_IRQ_OFFSET + 31
--	ldr	\irqstat, [ \base, # VIC_IRQ_STATUS ]
--	teq	\irqstat, #0
--
--	@ otherwise try vic1
--	addeq	\tmp, \base, #(VA_VIC1 - VA_VIC0)
--	addeq	\irqnr, \irqnr, #32
--	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
--	teqeq	\irqstat, #0
--
--	@ otherwise try vic2
--	addeq	\tmp, \base, #(VA_VIC2 - VA_VIC0)
--	addeq	\irqnr, \irqnr, #32
--	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
--	teqeq	\irqstat, #0
--
--	clzne	\irqstat, \irqstat
--	subne	\irqnr, \irqnr, \irqstat
- 	.endm
-diff --git a/arch/arm/mach-s5pc100/include/mach/vmalloc.h b/arch/arm/mach-s5pc100/include/mach/vmalloc.h
-deleted file mode 100644
-index 44c8e57..0000000
---- a/arch/arm/mach-s5pc100/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/* arch/arm/mach-s5pc100/include/mach/vmalloc.h
-- *
-- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- *
-- * S3C6400 vmalloc definition
--*/
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H
--
--#define VMALLOC_END	0xF6000000UL
--
--#endif /* __ASM_ARCH_VMALLOC_H */
-diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
-index 26f5c91..93ebe3a 100644
---- a/arch/arm/mach-s5pc100/mach-smdkc100.c
-+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
-@@ -25,6 +25,7 @@
- #include <linux/input.h>
- #include <linux/pwm_backlight.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- 
-@@ -250,6 +251,7 @@ MACHINE_START(SMDKC100, "SMDKC100")
- 	/* Maintainer: Byungho Min <bhmin@samsung.com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s5pc100_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= smdkc100_map_io,
- 	.init_machine	= smdkc100_machine_init,
- 	.timer		= &s3c24xx_timer,
-diff --git a/arch/arm/mach-s5pv210/include/mach/entry-macro.S b/arch/arm/mach-s5pv210/include/mach/entry-macro.S
-index 3aa41ac..bebca1b 100644
---- a/arch/arm/mach-s5pv210/include/mach/entry-macro.S
-+++ b/arch/arm/mach-s5pv210/include/mach/entry-macro.S
-@@ -10,45 +10,8 @@
-  * published by the Free Software Foundation.
- */
- 
--#include <asm/hardware/vic.h>
--#include <mach/map.h>
--#include <plat/irqs.h>
--
- 	.macro	disable_fiq
- 	.endm
- 
--	.macro	get_irqnr_preamble, base, tmp
--	ldr	\base, =VA_VIC0
--	.endm
--
- 	.macro	arch_ret_to_user, tmp1, tmp2
- 	.endm
--
--	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--
--	@ check the vic0
--	mov	\irqnr, # S5P_IRQ_OFFSET + 31
--	ldr	\irqstat, [ \base, # VIC_IRQ_STATUS ]
--	teq	\irqstat, #0
--
--	@ otherwise try vic1
--	addeq	\tmp, \base, #(VA_VIC1 - VA_VIC0)
--	addeq	\irqnr, \irqnr, #32
--	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
--	teqeq	\irqstat, #0
--
--	@ otherwise try vic2
--	addeq	\tmp, \base, #(VA_VIC2 - VA_VIC0)
--	addeq	\irqnr, \irqnr, #32
--	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
--	teqeq	\irqstat, #0
--
--	@ otherwise try vic3
--	addeq	\tmp, \base, #(VA_VIC3 - VA_VIC0)
--	addeq	\irqnr, \irqnr, #32
--	ldreq	\irqstat, [ \tmp, # VIC_IRQ_STATUS ]
--	teqeq	\irqstat, #0
--
--	clzne	\irqstat, \irqstat
--	subne	\irqnr, \irqnr, \irqstat
--	.endm
-diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h
-deleted file mode 100644
-index a6c659d..0000000
---- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,22 +0,0 @@
--/* linux/arch/arm/mach-s5p6442/include/mach/vmalloc.h
-- *
-- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
-- *
-- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
-- *		http://www.samsung.com/
-- *
-- * Based on arch/arm/mach-s5p6442/include/mach/vmalloc.h
-- *
-- * S5PV210 vmalloc definition
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
--*/
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H __FILE__
--
--#define VMALLOC_END	0xF6000000UL
--
--#endif /* __ASM_ARCH_VMALLOC_H */
-diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
-index 5811a96..71ca956 100644
---- a/arch/arm/mach-s5pv210/mach-aquila.c
-+++ b/arch/arm/mach-s5pv210/mach-aquila.c
-@@ -22,6 +22,7 @@
- #include <linux/input.h>
- #include <linux/gpio.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/setup.h>
-@@ -680,6 +681,7 @@ MACHINE_START(AQUILA, "Aquila")
- 	   Kyungmin Park <kyungmin.park@samsung.com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s5pv210_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= aquila_map_io,
- 	.init_machine	= aquila_machine_init,
- 	.timer		= &s5p_timer,
-diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
-index 15edcae..448fd9e 100644
---- a/arch/arm/mach-s5pv210/mach-goni.c
-+++ b/arch/arm/mach-s5pv210/mach-goni.c
-@@ -27,6 +27,7 @@
- #include <linux/gpio.h>
- #include <linux/interrupt.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/setup.h>
-@@ -956,6 +957,7 @@ MACHINE_START(GONI, "GONI")
- 	/* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s5pv210_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= goni_map_io,
- 	.init_machine	= goni_machine_init,
- 	.timer		= &s5p_timer,
-diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
-index f7266bb..c2531ff 100644
---- a/arch/arm/mach-s5pv210/mach-smdkc110.c
-+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
-@@ -15,6 +15,7 @@
- #include <linux/i2c.h>
- #include <linux/sysdev.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/setup.h>
-@@ -138,6 +139,7 @@ MACHINE_START(SMDKC110, "SMDKC110")
- 	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s5pv210_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= smdkc110_map_io,
- 	.init_machine	= smdkc110_machine_init,
- 	.timer		= &s5p_timer,
-diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
-index 8662ef6..3ac9e57 100644
---- a/arch/arm/mach-s5pv210/mach-smdkv210.c
-+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
-@@ -20,6 +20,7 @@
- #include <linux/delay.h>
- #include <linux/pwm_backlight.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/setup.h>
-@@ -316,6 +317,7 @@ MACHINE_START(SMDKV210, "SMDKV210")
- 	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s5pv210_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= smdkv210_map_io,
- 	.init_machine	= smdkv210_machine_init,
- 	.timer		= &s5p_timer,
-diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
-index 97cc066..df70fcb 100644
---- a/arch/arm/mach-s5pv210/mach-torbreck.c
-+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
-@@ -14,6 +14,7 @@
- #include <linux/init.h>
- #include <linux/serial_core.h>
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/setup.h>
-@@ -127,6 +128,7 @@ MACHINE_START(TORBRECK, "TORBRECK")
- 	/* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
- 	.atag_offset	= 0x100,
- 	.init_irq	= s5pv210_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.map_io		= torbreck_map_io,
- 	.init_machine	= torbreck_machine_init,
- 	.timer		= &s5p_timer,
-diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
-index ba9da9f..345d35b 100644
---- a/arch/arm/mach-sa1100/include/mach/system.h
-+++ b/arch/arm/mach-sa1100/include/mach/system.h
-@@ -14,7 +14,7 @@ static inline void arch_reset(char mode, const char *cmd)
- {
- 	if (mode == 's') {
- 		/* Jump into ROM at address 0 */
--		cpu_reset(0);
-+		soft_restart(0);
- 	} else {
- 		/* Use on-chip reset capability */
- 		RSRR = RSRR_SWR;
-diff --git a/arch/arm/mach-sa1100/include/mach/vmalloc.h b/arch/arm/mach-sa1100/include/mach/vmalloc.h
-deleted file mode 100644
-index b3d0023..0000000
---- a/arch/arm/mach-sa1100/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,4 +0,0 @@
--/*
-- * arch/arm/mach-sa1100/include/mach/vmalloc.h
-- */
--#define VMALLOC_END       (0xe8000000UL)
-diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
-index feda3ca..f4b25d8 100644
---- a/arch/arm/mach-shark/core.c
-+++ b/arch/arm/mach-shark/core.c
-@@ -29,7 +29,6 @@
- void arch_reset(char mode, const char *cmd)
- {
-         short temp;
--        local_irq_disable();
-         /* Reset the Machine via pc[3] of the sequoia chipset */
-         outw(0x09,0x24);
-         temp=inw(0x26);
-diff --git a/arch/arm/mach-shark/include/mach/vmalloc.h b/arch/arm/mach-shark/include/mach/vmalloc.h
-deleted file mode 100644
-index b10df98..0000000
---- a/arch/arm/mach-shark/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,4 +0,0 @@
--/*
-- * arch/arm/mach-shark/include/mach/vmalloc.h
-- */
--#define VMALLOC_END       0xd0000000UL
-diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
-index 737bdc6..5ca1f9d 100644
---- a/arch/arm/mach-shmobile/Makefile
-+++ b/arch/arm/mach-shmobile/Makefile
-@@ -28,7 +28,6 @@ pfc-$(CONFIG_ARCH_SH73A0)	+= pfc-sh73a0.o
- obj-$(CONFIG_ARCH_SH7367)	+= entry-intc.o
- obj-$(CONFIG_ARCH_SH7377)	+= entry-intc.o
- obj-$(CONFIG_ARCH_SH7372)	+= entry-intc.o
--obj-$(CONFIG_ARCH_SH73A0)	+= entry-gic.o
- 
- # PM objects
- obj-$(CONFIG_SUSPEND)		+= suspend.o
-diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
-index 7119b87..f71fa3c 100644
---- a/arch/arm/mach-shmobile/board-ag5evm.c
-+++ b/arch/arm/mach-shmobile/board-ag5evm.c
-@@ -609,7 +609,7 @@ MACHINE_START(AG5EVM, "ag5evm")
- 	.map_io		= ag5evm_map_io,
- 	.nr_irqs	= NR_IRQS_LEGACY,
- 	.init_irq	= sh73a0_init_irq,
--	.handle_irq	= shmobile_handle_irq_gic,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= ag5evm_init,
- 	.timer		= &ag5evm_timer,
- MACHINE_END
-diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S
-deleted file mode 100644
-index e20239b..0000000
---- a/arch/arm/mach-shmobile/entry-gic.S
-+++ /dev/null
-@@ -1,18 +0,0 @@
--/*
-- * ARM Interrupt demux handler using GIC
-- *
-- * Copyright (C) 2010 Magnus Damm
-- * Copyright (C) 2011 Paul Mundt
-- * Copyright (C) 2010 - 2011 Renesas Solutions Corp.
-- *
-- * This file is licensed under  the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-- */
--
--#include <asm/assembler.h>
--#include <asm/entry-macro-multi.S>
--#include <asm/hardware/gic.h>
--#include <asm/hardware/entry-macro-gic.S>
--
--	arch_irq_handler shmobile_handle_irq_gic
-diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
-index 834bd6c..4bf82c1 100644
---- a/arch/arm/mach-shmobile/include/mach/common.h
-+++ b/arch/arm/mach-shmobile/include/mach/common.h
-@@ -7,7 +7,6 @@ extern void shmobile_secondary_vector(void);
- struct clk;
- extern int clk_init(void);
- extern void shmobile_handle_irq_intc(struct pt_regs *);
--extern void shmobile_handle_irq_gic(struct pt_regs *);
- extern struct platform_suspend_ops shmobile_suspend_ops;
- struct cpuidle_driver;
- extern void (*shmobile_cpuidle_modes[])(void);
-diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
-index 8d4a416..2a57b29 100644
---- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
-+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
-@@ -18,14 +18,5 @@
- 	.macro  disable_fiq
- 	.endm
- 
--	.macro  get_irqnr_preamble, base, tmp
--	.endm
--
--	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
--	.endm
--
--	.macro  test_for_ipi, irqnr, irqstat, base, tmp
--	.endm
--
- 	.macro  arch_ret_to_user, tmp1, tmp2
- 	.endm
-diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
-index 76a687e..956ac18 100644
---- a/arch/arm/mach-shmobile/include/mach/system.h
-+++ b/arch/arm/mach-shmobile/include/mach/system.h
-@@ -8,7 +8,7 @@ static inline void arch_idle(void)
- 
- static inline void arch_reset(char mode, const char *cmd)
- {
--	cpu_reset(0);
-+	soft_restart(0);
- }
- 
- #endif
-diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
-deleted file mode 100644
-index 2b8fd8b..0000000
---- a/arch/arm/mach-shmobile/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,7 +0,0 @@
--#ifndef __ASM_MACH_VMALLOC_H
--#define __ASM_MACH_VMALLOC_H
--
--/* Vmalloc at ... - 0xe5ffffff */
--#define VMALLOC_END 0xe6000000UL
--
--#endif /* __ASM_MACH_VMALLOC_H */
-diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
-index 53da422..de3bb41 100644
---- a/arch/arm/mach-spear3xx/include/mach/entry-macro.S
-+++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
-@@ -11,35 +11,8 @@
-  * warranty of any kind, whether express or implied.
-  */
- 
--#include <asm/hardware/vic.h>
--#include <mach/hardware.h>
--
- 		.macro	disable_fiq
- 		.endm
- 
--		.macro	get_irqnr_preamble, base, tmp
--		.endm
--
- 		.macro	arch_ret_to_user, tmp1, tmp2
- 		.endm
--
--		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--		ldr	\base, =VA_SPEAR3XX_ML1_VIC_BASE
--		ldr	\irqstat, [\base, #VIC_IRQ_STATUS]	@ get status
--		teq	\irqstat, #0
--		beq	1001f				@ this will set/reset
--							@ zero register
--		/*
--		 * Following code will find bit position of least significang
--		 * bit set in irqstat, using following equation
--		 * least significant bit set in n = (n & ~(n-1))
--		 */
--		sub	\tmp, \irqstat, #1		@ tmp = irqstat - 1
--		mvn	\tmp, \tmp			@ tmp = ~tmp
--		and	\irqstat, \irqstat, \tmp	@ irqstat &= tmp
--		/* Now, irqstat is = bit no. of 1st bit set in vic irq status */
--		clz	\tmp, \irqstat			@ tmp = leading zeros
--		rsb	\irqnr, \tmp, #0x1F		@ irqnr = 32 - tmp - 1
--
--1001:		/* EQ will be set if no irqs pending */
--		.endm
-diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
-deleted file mode 100644
-index df977b3..0000000
---- a/arch/arm/mach-spear3xx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,19 +0,0 @@
--/*
-- * arch/arm/mach-spear3xx/include/mach/vmalloc.h
-- *
-- * Defining Vmalloc area for SPEAr3xx machine family
-- *
-- * Copyright (C) 2009 ST Microelectronics
-- * Viresh Kumar<viresh.kumar@st.com>
-- *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-- */
--
--#ifndef __MACH_VMALLOC_H
--#define __MACH_VMALLOC_H
--
--#include <plat/vmalloc.h>
--
--#endif /* __MACH_VMALLOC_H */
-diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
-index a5ff98e..61068ba 100644
---- a/arch/arm/mach-spear3xx/spear300_evb.c
-+++ b/arch/arm/mach-spear3xx/spear300_evb.c
-@@ -11,6 +11,7 @@
-  * warranty of any kind, whether express or implied.
-  */
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach-types.h>
- #include <mach/generic.h>
-@@ -67,6 +68,7 @@ MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
- 	.atag_offset	=	0x100,
- 	.map_io		=	spear3xx_map_io,
- 	.init_irq	=	spear3xx_init_irq,
-+	.handle_irq	=	vic_handle_irq,
- 	.timer		=	&spear3xx_timer,
- 	.init_machine	=	spear300_evb_init,
- MACHINE_END
-diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
-index 45d180d..7903abe 100644
---- a/arch/arm/mach-spear3xx/spear310_evb.c
-+++ b/arch/arm/mach-spear3xx/spear310_evb.c
-@@ -11,6 +11,7 @@
-  * warranty of any kind, whether express or implied.
-  */
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach-types.h>
- #include <mach/generic.h>
-@@ -73,6 +74,7 @@ MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
- 	.atag_offset	=	0x100,
- 	.map_io		=	spear3xx_map_io,
- 	.init_irq	=	spear3xx_init_irq,
-+	.handle_irq	=	vic_handle_irq,
- 	.timer		=	&spear3xx_timer,
- 	.init_machine	=	spear310_evb_init,
- MACHINE_END
-diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
-index 2287984..e9751f9 100644
---- a/arch/arm/mach-spear3xx/spear320_evb.c
-+++ b/arch/arm/mach-spear3xx/spear320_evb.c
-@@ -11,6 +11,7 @@
-  * warranty of any kind, whether express or implied.
-  */
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach-types.h>
- #include <mach/generic.h>
-@@ -71,6 +72,7 @@ MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
- 	.atag_offset	=	0x100,
- 	.map_io		=	spear3xx_map_io,
- 	.init_irq	=	spear3xx_init_irq,
-+	.handle_irq	=	vic_handle_irq,
- 	.timer		=	&spear3xx_timer,
- 	.init_machine	=	spear320_evb_init,
- MACHINE_END
-diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
-index 8a0b0ed..d490a91 100644
---- a/arch/arm/mach-spear6xx/include/mach/entry-macro.S
-+++ b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
-@@ -11,44 +11,8 @@
-  * warranty of any kind, whether express or implied.
-  */
- 
--#include <asm/hardware/vic.h>
--#include <mach/hardware.h>
--
- 		.macro	disable_fiq
- 		.endm
- 
--		.macro	get_irqnr_preamble, base, tmp
--		.endm
--
- 		.macro	arch_ret_to_user, tmp1, tmp2
- 		.endm
--
--		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--		ldr	\base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE
--		ldr	\irqstat, [\base, #VIC_IRQ_STATUS]	@ get status
--		mov	\irqnr, #0
--		teq	\irqstat, #0
--		bne	1001f
--		ldr	\base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE
--		ldr	\irqstat, [\base, #VIC_IRQ_STATUS]	@ get status
--		teq	\irqstat, #0
--		beq	1002f				@ this will set/reset
--							@ zero register
--		mov	\irqnr, #32
--1001:
--		/*
--		 * Following code will find bit position of least significang
--		 * bit set in irqstat, using following equation
--		 * least significant bit set in n = (n & ~(n-1))
--		 */
--		sub	\tmp, \irqstat, #1		@ tmp = irqstat - 1
--		mvn	\tmp, \tmp			@ tmp = ~tmp
--		and	\irqstat, \irqstat, \tmp	@ irqstat &= tmp
--		/* Now, irqstat is = bit no. of 1st bit set in vic irq status */
--		clz	\tmp, \irqstat			@ tmp = leading zeros
--
--		rsb	\tmp, \tmp, #0x1F		@ tmp = 32 - tmp - 1
--		add	\irqnr, \irqnr, \tmp
--
--1002:		/* EQ will be set if no irqs pending */
--		.endm
-diff --git a/arch/arm/mach-spear6xx/include/mach/vmalloc.h b/arch/arm/mach-spear6xx/include/mach/vmalloc.h
-deleted file mode 100644
-index 4a0b56c..0000000
---- a/arch/arm/mach-spear6xx/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,19 +0,0 @@
--/*
-- * arch/arm/mach-spear6xx/include/mach/vmalloc.h
-- *
-- * Defining Vmalloc area for SPEAr6xx machine family
-- *
-- * Copyright (C) 2009 ST Microelectronics
-- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
-- *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-- */
--
--#ifndef __MACH_VMALLOC_H
--#define __MACH_VMALLOC_H
--
--#include <plat/vmalloc.h>
--
--#endif	/* __MACH_VMALLOC_H */
-diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
-index 8238fe3..ff139ed 100644
---- a/arch/arm/mach-spear6xx/spear600_evb.c
-+++ b/arch/arm/mach-spear6xx/spear600_evb.c
-@@ -11,6 +11,7 @@
-  * warranty of any kind, whether express or implied.
-  */
- 
-+#include <asm/hardware/vic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach-types.h>
- #include <mach/generic.h>
-@@ -46,6 +47,7 @@ MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
- 	.atag_offset	=	0x100,
- 	.map_io		=	spear6xx_map_io,
- 	.init_irq	=	spear6xx_init_irq,
-+	.handle_irq	=	vic_handle_irq,
- 	.timer		=	&spear6xx_timer,
- 	.init_machine	=	spear600_evb_init,
- MACHINE_END
-diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c
-index 74743ad..f6f03ce 100644
---- a/arch/arm/mach-tegra/board-dt.c
-+++ b/arch/arm/mach-tegra/board-dt.c
-@@ -32,6 +32,7 @@
- #include <linux/i2c.h>
- #include <linux/i2c-tegra.h>
- 
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-@@ -130,6 +131,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
- 	.map_io		= tegra_map_common_io,
- 	.init_early	= tegra_init_early,
- 	.init_irq	= tegra_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.timer		= &tegra_timer,
- 	.init_machine	= tegra_dt_init,
- 	.dt_compat	= tegra_dt_board_compat,
-diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
-index f0bdc5e..fd190a8 100644
---- a/arch/arm/mach-tegra/board-harmony.c
-+++ b/arch/arm/mach-tegra/board-harmony.c
-@@ -31,6 +31,7 @@
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-+#include <asm/hardware/gic.h>
- #include <asm/setup.h>
- 
- #include <mach/tegra_wm8903_pdata.h>
-@@ -187,6 +188,7 @@ MACHINE_START(HARMONY, "harmony")
- 	.map_io         = tegra_map_common_io,
- 	.init_early	= tegra_init_early,
- 	.init_irq       = tegra_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.timer          = &tegra_timer,
- 	.init_machine   = tegra_harmony_init,
- MACHINE_END
-diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
-index 55c55ba..0b7e1cf 100644
---- a/arch/arm/mach-tegra/board-paz00.c
-+++ b/arch/arm/mach-tegra/board-paz00.c
-@@ -29,6 +29,7 @@
- #include <linux/gpio.h>
- #include <linux/rfkill-gpio.h>
- 
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-@@ -190,6 +191,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
- 	.map_io         = tegra_map_common_io,
- 	.init_early	= tegra_init_early,
- 	.init_irq       = tegra_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.timer          = &tegra_timer,
- 	.init_machine   = tegra_paz00_init,
- MACHINE_END
-diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
-index bf13ea3..7328379 100644
---- a/arch/arm/mach-tegra/board-seaboard.c
-+++ b/arch/arm/mach-tegra/board-seaboard.c
-@@ -34,6 +34,7 @@
- 
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-+#include <asm/hardware/gic.h>
- 
- #include "board.h"
- #include "board-seaboard.h"
-@@ -284,6 +285,7 @@ MACHINE_START(SEABOARD, "seaboard")
- 	.map_io         = tegra_map_common_io,
- 	.init_early     = tegra_init_early,
- 	.init_irq       = tegra_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.timer          = &tegra_timer,
- 	.init_machine   = tegra_seaboard_init,
- MACHINE_END
-@@ -293,6 +295,7 @@ MACHINE_START(KAEN, "kaen")
- 	.map_io         = tegra_map_common_io,
- 	.init_early     = tegra_init_early,
- 	.init_irq       = tegra_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.timer          = &tegra_timer,
- 	.init_machine   = tegra_kaen_init,
- MACHINE_END
-@@ -302,6 +305,7 @@ MACHINE_START(WARIO, "wario")
- 	.map_io         = tegra_map_common_io,
- 	.init_early     = tegra_init_early,
- 	.init_irq       = tegra_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.timer          = &tegra_timer,
- 	.init_machine   = tegra_wario_init,
- MACHINE_END
-diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
-index 1a6617b..60a36a2 100644
---- a/arch/arm/mach-tegra/board-trimslice.c
-+++ b/arch/arm/mach-tegra/board-trimslice.c
-@@ -26,6 +26,7 @@
- #include <linux/i2c.h>
- #include <linux/gpio.h>
- 
-+#include <asm/hardware/gic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/setup.h>
-@@ -176,6 +177,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
- 	.map_io         = tegra_map_common_io,
- 	.init_early	= tegra_init_early,
- 	.init_irq       = tegra_init_irq,
-+	.handle_irq	= gic_handle_irq,
- 	.timer          = &tegra_timer,
- 	.init_machine   = tegra_trimslice_init,
- MACHINE_END
-diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
-index dd165c5..ac11262 100644
---- a/arch/arm/mach-tegra/include/mach/entry-macro.S
-+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
-@@ -12,30 +12,15 @@
-  * GNU General Public License for more details.
-  *
-  */
--#include <mach/iomap.h>
--#include <mach/io.h>
--
--#if defined(CONFIG_ARM_GIC)
--#define HAVE_GET_IRQNR_PREAMBLE
--#include <asm/hardware/entry-macro-gic.S>
--
--	/* Uses the GIC interrupt controller built into the cpu */
--#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
- 
- 	.macro	disable_fiq
- 	.endm
- 
--	.macro	get_irqnr_preamble, base, tmp
--	movw \base, #(ICTRL_BASE & 0x0000ffff)
--	movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
-+	.macro	arch_ret_to_user, tmp1, tmp2
- 	.endm
- 
--	.macro  arch_ret_to_user, tmp1, tmp2
--	.endm
--#else
-+#if !defined(CONFIG_ARM_GIC)
- 	/* legacy interrupt controller for AP16 */
--	.macro	disable_fiq
--	.endm
- 
- 	.macro	get_irqnr_preamble, base, tmp
- 	@ enable imprecise aborts
-@@ -46,9 +31,6 @@
- 	orr \base, #0x0000f000
- 	.endm
- 
--	.macro	arch_ret_to_user, tmp1, tmp2
--	.endm
--
- 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
- 	ldr \irqnr, [\base, #0x20]	@ EVT_IRQ_STS
- 	cmp \irqnr, #0x80
-diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
-index 35a011f..f15deff 100644
---- a/arch/arm/mach-tegra/include/mach/io.h
-+++ b/arch/arm/mach-tegra/include/mach/io.h
-@@ -71,12 +71,6 @@
- 
- #ifndef __ASSEMBLER__
- 
--#define __arch_ioremap		tegra_ioremap
--#define __arch_iounmap		tegra_iounmap
--
--void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
--void tegra_iounmap(volatile void __iomem *addr);
--
- #define IO_ADDRESS(n) (IO_TO_VIRT(n))
- 
- #ifdef CONFIG_TEGRA_PCI
-diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
-deleted file mode 100644
-index fd6aa65..0000000
---- a/arch/arm/mach-tegra/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,28 +0,0 @@
--/*
-- * arch/arm/mach-tegra/include/mach/vmalloc.h
-- *
-- * Copyright (C) 2010 Google, Inc.
-- *
-- * Author:
-- *	Colin Cross <ccross@google.com>
-- *	Erik Gilling <konkers@google.com>
-- *
-- * This software is licensed under the terms of the GNU General Public
-- * License version 2, as published by the Free Software Foundation, and
-- * may be copied, distributed, and modified under those terms.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- */
--
--#ifndef __MACH_TEGRA_VMALLOC_H
--#define __MACH_TEGRA_VMALLOC_H
--
--#include <asm/sizes.h>
--
--#define VMALLOC_END        0xFE000000UL
--
--#endif
-diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
-index 5489f8b..d23ee2d 100644
---- a/arch/arm/mach-tegra/io.c
-+++ b/arch/arm/mach-tegra/io.c
-@@ -60,24 +60,3 @@ void __init tegra_map_common_io(void)
- {
- 	iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
- }
--
--/*
-- * Intercept ioremap() requests for addresses in our fixed mapping regions.
-- */
--void __iomem *tegra_ioremap(unsigned long p, size_t size, unsigned int type)
--{
--	void __iomem *v = IO_ADDRESS(p);
--	if (v == NULL)
--		v = __arm_ioremap(p, size, type);
--	return v;
--}
--EXPORT_SYMBOL(tegra_ioremap);
--
--void tegra_iounmap(volatile void __iomem *addr)
--{
--	unsigned long virt = (unsigned long)addr;
--
--	if (virt >= VMALLOC_START && virt < VMALLOC_END)
--		__iounmap(addr);
--}
--EXPORT_SYMBOL(tegra_iounmap);
-diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/mach-u300/include/mach/entry-macro.S
-index 20731ae..7181d6a 100644
---- a/arch/arm/mach-u300/include/mach/entry-macro.S
-+++ b/arch/arm/mach-u300/include/mach/entry-macro.S
-@@ -8,33 +8,9 @@
-  * Low-level IRQ helper macros for ST-Ericsson U300
-  * Author: Linus Walleij <linus.walleij@stericsson.com>
-  */
--#include <mach/hardware.h>
--#include <asm/hardware/vic.h>
- 
- 	.macro	disable_fiq
- 	.endm
- 
--	.macro  get_irqnr_preamble, base, tmp
--	.endm
--
- 	.macro  arch_ret_to_user, tmp1, tmp2
- 	.endm
--
--	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--	ldr	\base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON0_BASE
--	ldr	\irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
--	mov	\irqnr, #0
--	teq	\irqstat, #0
--	bne	1002f
--1001:	ldr	\base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON1_BASE
--	ldr	\irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
--	mov	\irqnr, #32
--	teq	\irqstat, #0
--	beq	1003f
--1002:	tst	\irqstat, #1
--	bne	1003f
--	add	\irqnr, \irqnr, #1
--	movs	\irqstat, \irqstat, lsr #1
--	bne	1002b
--1003:		/* EQ will be set if no irqs pending */
--	.endm
-diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h
-index 8daf136..6b6fef7 100644
---- a/arch/arm/mach-u300/include/mach/system.h
-+++ b/arch/arm/mach-u300/include/mach/system.h
-@@ -27,8 +27,6 @@ static void arch_reset(char mode, const char *cmd)
- 	case 's':
- 	case 'h':
- 		printk(KERN_CRIT "RESET: shutting down/rebooting system\n");
--		/* Disable interrupts */
--		local_irq_disable();
- #ifdef CONFIG_COH901327_WATCHDOG
- 		coh901327_watchdog_reset();
- #endif
-diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h
-deleted file mode 100644
-index ec423b9..0000000
---- a/arch/arm/mach-u300/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,12 +0,0 @@
--/*
-- *
-- * arch/arm/mach-u300/include/mach/vmalloc.h
-- *
-- *
-- * Copyright (C) 2006-2009 ST-Ericsson AB
-- * License terms: GNU General Public License (GPL) version 2
-- * Virtual memory allocations
-- * End must be above the I/O registers and on an even 2MiB boundary.
-- * Author: Linus Walleij <linus.walleij@stericsson.com>
-- */
--#define VMALLOC_END	0xfe800000UL
-diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
-index 89422ee..4a4fd33 100644
---- a/arch/arm/mach-u300/u300.c
-+++ b/arch/arm/mach-u300/u300.c
-@@ -19,6 +19,7 @@
- #include <linux/io.h>
- #include <mach/hardware.h>
- #include <mach/platform.h>
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/memory.h>
-@@ -49,6 +50,7 @@ MACHINE_START(U300, MACH_U300_STRING)
- 	.atag_offset	= BOOT_PARAMS_OFFSET,
- 	.map_io		= u300_map_io,
- 	.init_irq	= u300_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &u300_timer,
- 	.init_machine	= u300_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
-index bdd7b80..de1f5f8 100644
---- a/arch/arm/mach-ux500/board-mop500.c
-+++ b/arch/arm/mach-ux500/board-mop500.c
-@@ -33,6 +33,7 @@
- #include <linux/leds.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-+#include <asm/hardware/gic.h>
- 
- #include <plat/i2c.h>
- #include <plat/ste_dma40.h>
-@@ -695,6 +696,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
- 	.init_irq	= ux500_init_irq,
- 	/* we re-use nomadik timer here */
- 	.timer		= &ux500_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= mop500_init_machine,
- MACHINE_END
- 
-@@ -703,6 +705,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
- 	.map_io		= u8500_map_io,
- 	.init_irq	= ux500_init_irq,
- 	.timer		= &ux500_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= hrefv60_init_machine,
- MACHINE_END
- 
-@@ -712,5 +715,6 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
- 	.init_irq	= ux500_init_irq,
- 	/* we re-use nomadik timer here */
- 	.timer		= &ux500_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= snowball_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
-index 82025ba..fe1569b 100644
---- a/arch/arm/mach-ux500/board-u5500.c
-+++ b/arch/arm/mach-ux500/board-u5500.c
-@@ -12,6 +12,7 @@
- #include <linux/i2c.h>
- #include <linux/mfd/ab5500/ab5500.h>
- 
-+#include <asm/hardware/gic.h>
- #include <asm/mach/arch.h>
- #include <asm/mach-types.h>
- 
-@@ -149,5 +150,6 @@ MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
- 	.map_io		= u5500_map_io,
- 	.init_irq	= ux500_init_irq,
- 	.timer		= &ux500_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= u5500_init_machine,
- MACHINE_END
-diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
-index 071bba9..e16299e 100644
---- a/arch/arm/mach-ux500/include/mach/entry-macro.S
-+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
-@@ -10,8 +10,6 @@
-  * License version 2. This program is licensed "as is" without any
-  * warranty of any kind, whether express or implied.
-  */
--#include <mach/hardware.h>
--#include <asm/hardware/entry-macro-gic.S>
- 
- 		.macro	disable_fiq
- 		.endm
-diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h
-deleted file mode 100644
-index a4945cb..0000000
---- a/arch/arm/mach-ux500/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,18 +0,0 @@
--/*
-- *  Copyright (C) 2009 ST-Ericsson
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#define VMALLOC_END	0xf0000000UL
-diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
-index e340a54..4d8dfc1 100644
---- a/arch/arm/mach-versatile/core.c
-+++ b/arch/arm/mach-versatile/core.c
-@@ -141,11 +141,6 @@ static struct map_desc versatile_io_desc[] __initdata = {
- 	},
- #ifdef CONFIG_MACH_VERSATILE_AB
-  	{
--		.virtual	=  IO_ADDRESS(VERSATILE_GPIO0_BASE),
--		.pfn		= __phys_to_pfn(VERSATILE_GPIO0_BASE),
--		.length		= SZ_4K,
--		.type		= MT_DEVICE
--	}, {
- 		.virtual	=  IO_ADDRESS(VERSATILE_IB2_BASE),
- 		.pfn		= __phys_to_pfn(VERSATILE_IB2_BASE),
- 		.length		= SZ_64M,
-diff --git a/arch/arm/mach-versatile/include/mach/entry-macro.S b/arch/arm/mach-versatile/include/mach/entry-macro.S
-index e6f7c16..b6f0dbf 100644
---- a/arch/arm/mach-versatile/include/mach/entry-macro.S
-+++ b/arch/arm/mach-versatile/include/mach/entry-macro.S
-@@ -7,39 +7,9 @@
-  * License version 2. This program is licensed "as is" without any
-  * warranty of any kind, whether express or implied.
-  */
--#include <mach/hardware.h>
--#include <mach/platform.h>
--#include <asm/hardware/vic.h>
- 
- 		.macro	disable_fiq
- 		.endm
- 
--		.macro  get_irqnr_preamble, base, tmp
--		ldr	\base, =IO_ADDRESS(VERSATILE_VIC_BASE)
--		.endm
--
- 		.macro  arch_ret_to_user, tmp1, tmp2
- 		.endm
--
--		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--		ldr	\irqstat, [\base, #VIC_IRQ_STATUS]	@ get masked status
--		mov	\irqnr, #0
--		teq	\irqstat, #0
--		beq	1003f
--
--1001:		tst	\irqstat, #15
--		bne	1002f
--		add	\irqnr, \irqnr, #4
--		movs	\irqstat, \irqstat, lsr #4
--		bne	1001b
--1002:		tst	\irqstat, #1
--		bne	1003f
--		add	\irqnr, \irqnr, #1
--		movs	\irqstat, \irqstat, lsr #1
--		bne	1002b
--1003:		/* EQ will be set if no irqs pending */
--
--@		clz	\irqnr, \irqstat
--@1003:		/* EQ will be set if we reach MAXIRQNUM */
--		.endm
--
-diff --git a/arch/arm/mach-versatile/include/mach/vmalloc.h b/arch/arm/mach-versatile/include/mach/vmalloc.h
-deleted file mode 100644
-index 7d8e069..0000000
---- a/arch/arm/mach-versatile/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,21 +0,0 @@
--/*
-- *  arch/arm/mach-versatile/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2003 ARM Limited
-- *  Copyright (C) 2000 Russell King.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#define VMALLOC_END		0xd8000000UL
-diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
-index fda4866..c83a1f3 100644
---- a/arch/arm/mach-versatile/versatile_ab.c
-+++ b/arch/arm/mach-versatile/versatile_ab.c
-@@ -27,6 +27,7 @@
- 
- #include <mach/hardware.h>
- #include <asm/irq.h>
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- 
- #include <asm/mach/arch.h>
-@@ -39,6 +40,7 @@ MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
- 	.map_io		= versatile_map_io,
- 	.init_early	= versatile_init_early,
- 	.init_irq	= versatile_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &versatile_timer,
- 	.init_machine	= versatile_init,
- MACHINE_END
-diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c
-index 54e037c..f4d1e0f 100644
---- a/arch/arm/mach-versatile/versatile_dt.c
-+++ b/arch/arm/mach-versatile/versatile_dt.c
-@@ -24,6 +24,7 @@
- #include <linux/init.h>
- #include <linux/of_irq.h>
- #include <linux/of_platform.h>
-+#include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- 
-@@ -45,6 +46,7 @@ DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
- 	.map_io		= versatile_map_io,
- 	.init_early	= versatile_init_early,
- 	.init_irq	= versatile_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &versatile_timer,
- 	.init_machine	= versatile_dt_init,
- 	.dt_compat	= versatile_dt_match,
-diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
-index feaf9cb..4d31eeb 100644
---- a/arch/arm/mach-versatile/versatile_pb.c
-+++ b/arch/arm/mach-versatile/versatile_pb.c
-@@ -28,6 +28,7 @@
- #include <linux/io.h>
- 
- #include <mach/hardware.h>
-+#include <asm/hardware/vic.h>
- #include <asm/irq.h>
- #include <asm/mach-types.h>
- 
-@@ -107,6 +108,7 @@ MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
- 	.map_io		= versatile_map_io,
- 	.init_early	= versatile_init_early,
- 	.init_irq	= versatile_init_irq,
-+	.handle_irq	= vic_handle_irq,
- 	.timer		= &versatile_timer,
- 	.init_machine	= versatile_pb_init,
- MACHINE_END
-diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S
-index 73c1129..a14f9e6 100644
---- a/arch/arm/mach-vexpress/include/mach/entry-macro.S
-+++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S
-@@ -1,5 +1,3 @@
--#include <asm/hardware/entry-macro-gic.S>
--
- 	.macro	disable_fiq
- 	.endm
- 
-diff --git a/arch/arm/mach-vexpress/include/mach/vmalloc.h b/arch/arm/mach-vexpress/include/mach/vmalloc.h
-deleted file mode 100644
-index f43a36e..0000000
---- a/arch/arm/mach-vexpress/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,21 +0,0 @@
--/*
-- *  arch/arm/mach-vexpress/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2003 ARM Limited
-- *  Copyright (C) 2000 Russell King.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#define VMALLOC_END		0xf8000000UL
-diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
-index 1fafc32..7aa07a8 100644
---- a/arch/arm/mach-vexpress/v2m.c
-+++ b/arch/arm/mach-vexpress/v2m.c
-@@ -23,6 +23,7 @@
- #include <asm/hardware/arm_timer.h>
- #include <asm/hardware/timer-sp.h>
- #include <asm/hardware/sp810.h>
-+#include <asm/hardware/gic.h>
- 
- #include <mach/ct-ca9x4.h>
- #include <mach/motherboard.h>
-@@ -448,5 +449,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
- 	.init_early	= v2m_init_early,
- 	.init_irq	= v2m_init_irq,
- 	.timer		= &v2m_timer,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= v2m_init,
- MACHINE_END
-diff --git a/arch/arm/mach-vt8500/include/mach/vmalloc.h b/arch/arm/mach-vt8500/include/mach/vmalloc.h
-deleted file mode 100644
-index 4642290..0000000
---- a/arch/arm/mach-vt8500/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/*
-- *  arch/arm/mach-vt8500/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2000 Russell King.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-- */
--#define VMALLOC_END	0xd0000000UL
-diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h
-index ce228bd..68875a1 100644
---- a/arch/arm/mach-w90x900/include/mach/system.h
-+++ b/arch/arm/mach-w90x900/include/mach/system.h
-@@ -33,7 +33,7 @@ static void arch_reset(char mode, const char *cmd)
- {
- 	if (mode == 's') {
- 		/* Jump into ROM at address 0 */
--		cpu_reset(0);
-+		soft_restart(0);
- 	} else {
- 		__raw_writel(WTE | WTRE | WTCLK, WTCR);
- 	}
-diff --git a/arch/arm/mach-w90x900/include/mach/vmalloc.h b/arch/arm/mach-w90x900/include/mach/vmalloc.h
-deleted file mode 100644
-index b067e44..0000000
---- a/arch/arm/mach-w90x900/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,23 +0,0 @@
--/*
-- * arch/arm/mach-w90x900/include/mach/vmalloc.h
-- *
-- * Copyright (c) 2008 Nuvoton technology corporation
-- * All rights reserved.
-- *
-- * Wan ZongShun <mcuos.com@gmail.com>
-- *
-- * Based on arch/arm/mach-s3c2410/include/mach/vmalloc.h
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- */
--
--#ifndef __ASM_ARCH_VMALLOC_H
--#define __ASM_ARCH_VMALLOC_H
--
--#define VMALLOC_END	  (0xe0000000UL)
--
--#endif /* __ASM_ARCH_VMALLOC_H */
-diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c
-index 7bf143c..b466e24 100644
---- a/arch/arm/mach-w90x900/irq.c
-+++ b/arch/arm/mach-w90x900/irq.c
-@@ -28,6 +28,8 @@
- #include <mach/hardware.h>
- #include <mach/regs-irq.h>
- 
-+#include "nuc9xx.h"
-+
- struct group_irq {
- 	unsigned long		gpen;
- 	unsigned int		enabled;
-diff --git a/arch/arm/mach-w90x900/nuc910.h b/arch/arm/mach-w90x900/nuc910.h
-index 83e9ba5..b14c71a 100644
---- a/arch/arm/mach-w90x900/nuc910.h
-+++ b/arch/arm/mach-w90x900/nuc910.h
-@@ -12,14 +12,7 @@
-  * published by the Free Software Foundation.
-  *
-  */
--
--struct map_desc;
--struct sys_timer;
--
--/* core initialisation functions */
--
--extern void nuc900_init_irq(void);
--extern struct sys_timer nuc900_timer;
-+#include "nuc9xx.h"
- 
- /* extern file from nuc910.c */
- 
-diff --git a/arch/arm/mach-w90x900/nuc950.h b/arch/arm/mach-w90x900/nuc950.h
-index 98a1148..6e9de30 100644
---- a/arch/arm/mach-w90x900/nuc950.h
-+++ b/arch/arm/mach-w90x900/nuc950.h
-@@ -12,14 +12,7 @@
-  * published by the Free Software Foundation.
-  *
-  */
--
--struct map_desc;
--struct sys_timer;
--
--/* core initialisation functions */
--
--extern void nuc900_init_irq(void);
--extern struct sys_timer nuc900_timer;
-+#include "nuc9xx.h"
- 
- /* extern file from nuc950.c */
- 
-diff --git a/arch/arm/mach-w90x900/nuc960.h b/arch/arm/mach-w90x900/nuc960.h
-index f0c07cb..9f6df9a 100644
---- a/arch/arm/mach-w90x900/nuc960.h
-+++ b/arch/arm/mach-w90x900/nuc960.h
-@@ -12,14 +12,7 @@
-  * published by the Free Software Foundation.
-  *
-  */
--
--struct map_desc;
--struct sys_timer;
--
--/* core initialisation functions */
--
--extern void nuc900_init_irq(void);
--extern struct sys_timer nuc900_timer;
-+#include "nuc9xx.h"
- 
- /* extern file from nuc960.c */
- 
-diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
-new file mode 100644
-index 0000000..847c4f3
---- /dev/null
-+++ b/arch/arm/mach-w90x900/nuc9xx.h
-@@ -0,0 +1,23 @@
-+/*
-+ * arch/arm/mach-w90x900/nuc9xx.h
-+ *
-+ * Copied from nuc910.h, which had:
-+ *
-+ * Copyright (c) 2008 Nuvoton corporation
-+ *
-+ * Header file for NUC900 CPU support
-+ *
-+ * Wan ZongShun <mcuos.com@gmail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+struct map_desc;
-+struct sys_timer;
-+
-+/* core initialisation functions */
-+
-+extern void nuc900_init_irq(void);
-+extern struct sys_timer nuc900_timer;
-diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
-index a2c4e2d..fa27c49 100644
---- a/arch/arm/mach-w90x900/time.c
-+++ b/arch/arm/mach-w90x900/time.c
-@@ -33,6 +33,8 @@
- #include <mach/map.h>
- #include <mach/regs-timer.h>
- 
-+#include "nuc9xx.h"
-+
- #define RESETINT	0x1f
- #define PERIOD		(0x01 << 27)
- #define ONESHOT		(0x00 << 27)
-diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
-index 73e9368..ab5cfdd 100644
---- a/arch/arm/mach-zynq/common.c
-+++ b/arch/arm/mach-zynq/common.c
-@@ -112,6 +112,7 @@ static const char *xilinx_dt_match[] = {
- MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
- 	.map_io		= xilinx_map_io,
- 	.init_irq	= xilinx_irq_init,
-+	.handle_irq	= gic_handle_irq,
- 	.init_machine	= xilinx_init_machine,
- 	.timer		= &xttcpss_sys_timer,
- 	.dt_compat	= xilinx_dt_match,
-diff --git a/arch/arm/mach-zynq/include/mach/entry-macro.S b/arch/arm/mach-zynq/include/mach/entry-macro.S
-index 3cfc01b..d621fb7 100644
---- a/arch/arm/mach-zynq/include/mach/entry-macro.S
-+++ b/arch/arm/mach-zynq/include/mach/entry-macro.S
-@@ -20,9 +20,6 @@
-  * GNU General Public License for more details.
-  */
- 
--#include <mach/hardware.h>
--#include <asm/hardware/entry-macro-gic.S>
--
- 		.macro  disable_fiq
- 		.endm
- 
-diff --git a/arch/arm/mach-zynq/include/mach/vmalloc.h b/arch/arm/mach-zynq/include/mach/vmalloc.h
-deleted file mode 100644
-index 2398eff..0000000
---- a/arch/arm/mach-zynq/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,20 +0,0 @@
--/* arch/arm/mach-zynq/include/mach/vmalloc.h
-- *
-- *  Copyright (C) 2011 Xilinx
-- *
-- * This software is licensed under the terms of the GNU General Public
-- * License version 2, as published by the Free Software Foundation, and
-- * may be copied, distributed, and modified under those terms.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- */
--
--#ifndef __MACH_VMALLOC_H__
--#define __MACH_VMALLOC_H__
--
--#define VMALLOC_END       0xE0000000UL
--
--#endif
-diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
-index 1aa664a..98d64fa 100644
---- a/arch/arm/mm/dma-mapping.c
-+++ b/arch/arm/mm/dma-mapping.c
-@@ -128,7 +128,20 @@ static void __dma_free_buffer(struct page *page, size_t size)
-  */
- static pte_t **consistent_pte;
- 
-+#ifdef CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE
-+
-+#if (CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE == 0)
-+#undef CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE
-+#define CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE 2
-+#endif
-+
-+#define DEFAULT_CONSISTENT_DMA_SIZE \
-+	(((CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
-+
-+#else
- #define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M
-+#endif
-+
- 
- unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE;
- 
-diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
-index 2be9139..296ad2e 100644
---- a/arch/arm/mm/idmap.c
-+++ b/arch/arm/mm/idmap.c
-@@ -78,7 +78,7 @@ void identity_mapping_del(pgd_t *pgd, unsigned long addr, unsigned long end)
-  * the user-mode pages.  This will then ensure that we have predictable
-  * results when turning the mmu off
-  */
--void setup_mm_for_reboot(char mode)
-+void setup_mm_for_reboot(void)
- {
- 	/*
- 	 * We need to access to user-mode page tables here. For kernel threads
-diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
-index fbdd12e..786addd 100644
---- a/arch/arm/mm/init.c
-+++ b/arch/arm/mm/init.c
-@@ -20,7 +20,6 @@
- #include <linux/highmem.h>
- #include <linux/gfp.h>
- #include <linux/memblock.h>
--#include <linux/sort.h>
- 
- #include <asm/mach-types.h>
- #include <asm/prom.h>
-@@ -134,30 +133,18 @@ void show_mem(unsigned int filter)
- }
- 
- static void __init find_limits(unsigned long *min, unsigned long *max_low,
--	unsigned long *max_high)
-+			       unsigned long *max_high)
- {
- 	struct meminfo *mi = &meminfo;
- 	int i;
- 
--	*min = -1UL;
--	*max_low = *max_high = 0;
--
--	for_each_bank (i, mi) {
--		struct membank *bank = &mi->bank[i];
--		unsigned long start, end;
--
--		start = bank_pfn_start(bank);
--		end = bank_pfn_end(bank);
--
--		if (*min > start)
--			*min = start;
--		if (*max_high < end)
--			*max_high = end;
--		if (bank->highmem)
--			continue;
--		if (*max_low < end)
--			*max_low = end;
--	}
-+	/* This assumes the meminfo array is properly sorted */
-+	*min = bank_pfn_start(&mi->bank[0]);
-+	for_each_bank (i, mi)
-+		if (mi->bank[i].highmem)
-+				break;
-+	*max_low = bank_pfn_end(&mi->bank[i - 1]);
-+	*max_high = bank_pfn_end(&mi->bank[mi->nr_banks - 1]);
- }
- 
- static void __init arm_bootmem_init(unsigned long start_pfn,
-@@ -319,19 +306,10 @@ static void arm_memory_present(void)
- }
- #endif
- 
--static int __init meminfo_cmp(const void *_a, const void *_b)
--{
--	const struct membank *a = _a, *b = _b;
--	long cmp = bank_pfn_start(a) - bank_pfn_start(b);
--	return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
--}
--
- void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
- {
- 	int i;
- 
--	sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
--
- 	memblock_init();
- 	for (i = 0; i < mi->nr_banks; i++)
- 		memblock_add(mi->bank[i].start, mi->bank[i].size);
-@@ -403,8 +381,6 @@ void __init bootmem_init(void)
- 	 */
- 	arm_bootmem_free(min, max_low, max_high);
- 
--	high_memory = __va(((phys_addr_t)max_low << PAGE_SHIFT) - 1) + 1;
--
- 	/*
- 	 * This doesn't seem to be used by the Linux memory manager any
- 	 * more, but is used by ll_rw_block.  If we can get rid of it, we
-diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
-index bdb248c..12c7ad2 100644
---- a/arch/arm/mm/ioremap.c
-+++ b/arch/arm/mm/ioremap.c
-@@ -36,12 +36,6 @@
- #include <asm/mach/map.h>
- #include "mm.h"
- 
--/*
-- * Used by ioremap() and iounmap() code to mark (super)section-mapped
-- * I/O regions in vm_struct->flags field.
-- */
--#define VM_ARM_SECTION_MAPPING	0x80000000
--
- int ioremap_page(unsigned long virt, unsigned long phys,
- 		 const struct mem_type *mtype)
- {
-@@ -201,12 +195,6 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
- 	if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
- 		return NULL;
- 
--	/*
--	 * Don't allow RAM to be mapped - this causes problems with ARMv6+
--	 */
--	if (WARN_ON(pfn_valid(pfn)))
--		return NULL;
--
- 	type = get_mem_type(mtype);
- 	if (!type)
- 		return NULL;
-@@ -216,6 +204,34 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
- 	 */
- 	size = PAGE_ALIGN(offset + size);
- 
-+	/*
-+	 * Try to reuse one of the static mapping whenever possible.
-+	 */
-+	read_lock(&vmlist_lock);
-+	for (area = vmlist; area; area = area->next) {
-+		if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000))
-+			break;
-+		if (!(area->flags & VM_ARM_STATIC_MAPPING))
-+			continue;
-+		if ((area->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype))
-+			continue;
-+		if (__phys_to_pfn(area->phys_addr) > pfn ||
-+		    __pfn_to_phys(pfn) + size-1 > area->phys_addr + area->size-1)
-+			continue;
-+		/* we can drop the lock here as we know *area is static */
-+		read_unlock(&vmlist_lock);
-+		addr = (unsigned long)area->addr;
-+		addr += __pfn_to_phys(pfn) - area->phys_addr;
-+		return (void __iomem *) (offset + addr);
-+	}
-+	read_unlock(&vmlist_lock);
-+
-+	/*
-+	 * Don't allow RAM to be mapped - this causes problems with ARMv6+
-+	 */
-+	if (WARN_ON(pfn_valid(pfn)))
-+		return NULL;
-+
- 	area = get_vm_area_caller(size, VM_IOREMAP, caller);
-  	if (!area)
-  		return NULL;
-@@ -313,28 +329,34 @@ __arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
- void __iounmap(volatile void __iomem *io_addr)
- {
- 	void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
--#ifndef CONFIG_SMP
--	struct vm_struct **p, *tmp;
-+	struct vm_struct *vm;
- 
--	/*
--	 * If this is a section based mapping we need to handle it
--	 * specially as the VM subsystem does not know how to handle
--	 * such a beast. We need the lock here b/c we need to clear
--	 * all the mappings before the area can be reclaimed
--	 * by someone else.
--	 */
--	write_lock(&vmlist_lock);
--	for (p = &vmlist ; (tmp = *p) ; p = &tmp->next) {
--		if ((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) {
--			if (tmp->flags & VM_ARM_SECTION_MAPPING) {
--				unmap_area_sections((unsigned long)tmp->addr,
--						    tmp->size);
--			}
-+	read_lock(&vmlist_lock);
-+	for (vm = vmlist; vm; vm = vm->next) {
-+		if (vm->addr > addr)
-+			break;
-+		if (!(vm->flags & VM_IOREMAP))
-+			continue;
-+		/* If this is a static mapping we must leave it alone */
-+		if ((vm->flags & VM_ARM_STATIC_MAPPING) &&
-+		    (vm->addr <= addr) && (vm->addr + vm->size > addr)) {
-+			read_unlock(&vmlist_lock);
-+			return;
-+		}
-+#ifndef CONFIG_SMP
-+		/*
-+		 * If this is a section based mapping we need to handle it
-+		 * specially as the VM subsystem does not know how to handle
-+		 * such a beast.
-+		 */
-+		if ((vm->addr == addr) &&
-+		    (vm->flags & VM_ARM_SECTION_MAPPING)) {
-+			unmap_area_sections((unsigned long)vm->addr, vm->size);
- 			break;
- 		}
--	}
--	write_unlock(&vmlist_lock);
- #endif
-+	}
-+	read_unlock(&vmlist_lock);
- 
- 	vunmap(addr);
- }
-diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
-index ad7cce3..70f6d3ea 100644
---- a/arch/arm/mm/mm.h
-+++ b/arch/arm/mm/mm.h
-@@ -21,6 +21,20 @@ const struct mem_type *get_mem_type(unsigned int type);
- 
- extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
- 
-+/*
-+ * ARM specific vm_struct->flags bits.
-+ */
-+
-+/* (super)section-mapped I/O regions used by ioremap()/iounmap() */
-+#define VM_ARM_SECTION_MAPPING	0x80000000
-+
-+/* permanent static mappings from iotable_init() */
-+#define VM_ARM_STATIC_MAPPING	0x40000000
-+
-+/* mapping type (attributes) for permanent static mappings */
-+#define VM_ARM_MTYPE(mt)		((mt) << 20)
-+#define VM_ARM_MTYPE_MASK	(0x1f << 20)
-+
- #endif
- 
- #ifdef CONFIG_ZONE_DMA
-diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
-index dc8c550..27e366a 100644
---- a/arch/arm/mm/mmu.c
-+++ b/arch/arm/mm/mmu.c
-@@ -15,6 +15,7 @@
- #include <linux/nodemask.h>
- #include <linux/memblock.h>
- #include <linux/fs.h>
-+#include <linux/vmalloc.h>
- 
- #include <asm/cputype.h>
- #include <asm/sections.h>
-@@ -529,13 +530,18 @@ EXPORT_SYMBOL(phys_mem_access_prot);
- 
- #define vectors_base()	(vectors_high() ? 0xffff0000 : 0)
- 
--static void __init *early_alloc(unsigned long sz)
-+static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
- {
--	void *ptr = __va(memblock_alloc(sz, sz));
-+	void *ptr = __va(memblock_alloc(sz, align));
- 	memset(ptr, 0, sz);
- 	return ptr;
- }
- 
-+static void __init *early_alloc(unsigned long sz)
-+{
-+	return early_alloc_aligned(sz, sz);
-+}
-+
- static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
- {
- 	if (pmd_none(*pmd)) {
-@@ -685,9 +691,10 @@ static void __init create_mapping(struct map_desc *md)
- 	}
- 
- 	if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
--	    md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
-+	    md->virtual >= PAGE_OFFSET &&
-+	    (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
- 		printk(KERN_WARNING "BUG: mapping for 0x%08llx"
--		       " at 0x%08lx overlaps vmalloc space\n",
-+		       " at 0x%08lx out of vmalloc space\n",
- 		       (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
- 	}
- 
-@@ -729,18 +736,33 @@ static void __init create_mapping(struct map_desc *md)
-  */
- void __init iotable_init(struct map_desc *io_desc, int nr)
- {
--	int i;
-+	struct map_desc *md;
-+	struct vm_struct *vm;
-+
-+	if (!nr)
-+		return;
- 
--	for (i = 0; i < nr; i++)
--		create_mapping(io_desc + i);
-+	vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
-+
-+	for (md = io_desc; nr; md++, nr--) {
-+		create_mapping(md);
-+		vm->addr = (void *)(md->virtual & PAGE_MASK);
-+		vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
-+		vm->phys_addr = __pfn_to_phys(md->pfn); 
-+		vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 
-+		vm->flags |= VM_ARM_MTYPE(md->type);
-+		vm->caller = iotable_init;
-+		vm_area_add_early(vm++);
-+	}
- }
- 
--static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
-+static void * __initdata vmalloc_min =
-+	(void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
- 
- /*
-  * vmalloc=size forces the vmalloc area to be exactly 'size'
-  * bytes. This can be used to increase (or decrease) the vmalloc
-- * area - the default is 128m.
-+ * area - the default is 240m.
-  */
- static int __init early_vmalloc(char *arg)
- {
-@@ -860,6 +882,7 @@ void __init sanity_check_meminfo(void)
- 	}
- #endif
- 	meminfo.nr_banks = j;
-+	high_memory = __va(lowmem_limit - 1) + 1;
- 	memblock_set_current_limit(lowmem_limit);
- }
- 
-@@ -890,10 +913,10 @@ static inline void prepare_page_table(void)
- 
- 	/*
- 	 * Clear out all the kernel space mappings, except for the first
--	 * memory bank, up to the end of the vmalloc region.
-+	 * memory bank, up to the vmalloc region.
- 	 */
- 	for (addr = __phys_to_virt(end);
--	     addr < VMALLOC_END; addr += PMD_SIZE)
-+	     addr < VMALLOC_START; addr += PMD_SIZE)
- 		pmd_clear(pmd_off_k(addr));
- }
- 
-@@ -920,8 +943,8 @@ void __init arm_mm_memblock_reserve(void)
- }
- 
- /*
-- * Set up device the mappings.  Since we clear out the page tables for all
-- * mappings above VMALLOC_END, we will remove any debug device mappings.
-+ * Set up the device mappings.  Since we clear out the page tables for all
-+ * mappings above VMALLOC_START, we will remove any debug device mappings.
-  * This means you have to be careful how you debug this function, or any
-  * called function.  This means you can't use any function or debugging
-  * method which may touch any device, otherwise the kernel _will_ crash.
-@@ -936,7 +959,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
- 	 */
- 	vectors_page = early_alloc(PAGE_SIZE);
- 
--	for (addr = VMALLOC_END; addr; addr += PMD_SIZE)
-+	for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
- 		pmd_clear(pmd_off_k(addr));
- 
- 	/*
-diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
-index 941a98c..4fc6794 100644
---- a/arch/arm/mm/nommu.c
-+++ b/arch/arm/mm/nommu.c
-@@ -29,6 +29,8 @@ void __init arm_mm_memblock_reserve(void)
- 
- void __init sanity_check_meminfo(void)
- {
-+	phys_addr_t end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
-+	high_memory = __va(end - 1) + 1;
- }
- 
- /*
-@@ -43,7 +45,7 @@ void __init paging_init(struct machine_desc *mdesc)
- /*
-  * We don't need to do anything here for nommu machines.
-  */
--void setup_mm_for_reboot(char mode)
-+void setup_mm_for_reboot(void)
- {
- }
- 
-diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile
-index 69b09c1..90f7153 100644
---- a/arch/arm/plat-iop/Makefile
-+++ b/arch/arm/plat-iop/Makefile
-@@ -10,7 +10,6 @@ obj-$(CONFIG_ARCH_IOP32X) += i2c.o
- obj-$(CONFIG_ARCH_IOP32X) += pci.o
- obj-$(CONFIG_ARCH_IOP32X) += setup.o
- obj-$(CONFIG_ARCH_IOP32X) += time.o
--obj-$(CONFIG_ARCH_IOP32X) += io.o
- obj-$(CONFIG_ARCH_IOP32X) += cp6.o
- obj-$(CONFIG_ARCH_IOP32X) += adma.o
- obj-$(CONFIG_ARCH_IOP32X) += pmu.o
-@@ -21,7 +20,6 @@ obj-$(CONFIG_ARCH_IOP33X) += i2c.o
- obj-$(CONFIG_ARCH_IOP33X) += pci.o
- obj-$(CONFIG_ARCH_IOP33X) += setup.o
- obj-$(CONFIG_ARCH_IOP33X) += time.o
--obj-$(CONFIG_ARCH_IOP33X) += io.o
- obj-$(CONFIG_ARCH_IOP33X) += cp6.o
- obj-$(CONFIG_ARCH_IOP33X) += adma.o
- obj-$(CONFIG_ARCH_IOP33X) += pmu.o
-diff --git a/arch/arm/plat-iop/io.c b/arch/arm/plat-iop/io.c
-deleted file mode 100644
-index e15bc17..0000000
---- a/arch/arm/plat-iop/io.c
-+++ /dev/null
-@@ -1,59 +0,0 @@
--/*
-- * iop3xx custom ioremap implementation
-- * Copyright (c) 2006, Intel Corporation.
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms and conditions of the GNU General Public License,
-- * version 2, as published by the Free Software Foundation.
-- *
-- * This program is distributed in the hope it will be useful, but WITHOUT
-- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-- * more details.
-- *
-- * You should have received a copy of the GNU General Public License along with
-- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
-- * Place - Suite 330, Boston, MA 02111-1307 USA.
-- *
-- */
--#include <linux/kernel.h>
--#include <linux/module.h>
--#include <linux/io.h>
--#include <mach/hardware.h>
--
--void * __iomem __iop3xx_ioremap(unsigned long cookie, size_t size,
--	unsigned int mtype)
--{
--	void __iomem * retval;
--
--	switch (cookie) {
--	case IOP3XX_PCI_LOWER_IO_PA ... IOP3XX_PCI_UPPER_IO_PA:
--		retval = (void *) IOP3XX_PCI_IO_PHYS_TO_VIRT(cookie);
--		break;
--	case IOP3XX_PERIPHERAL_PHYS_BASE ... IOP3XX_PERIPHERAL_UPPER_PA:
--		retval = (void *) IOP3XX_PMMR_PHYS_TO_VIRT(cookie);
--		break;
--	default:
--		retval = __arm_ioremap_caller(cookie, size, mtype,
--				__builtin_return_address(0));
--	}
--
--	return retval;
--}
--EXPORT_SYMBOL(__iop3xx_ioremap);
--
--void __iop3xx_iounmap(void __iomem *addr)
--{
--	extern void __iounmap(volatile void __iomem *addr);
--
--	switch ((u32) addr) {
--	case IOP3XX_PCI_LOWER_IO_VA ... IOP3XX_PCI_UPPER_IO_VA:
--	case IOP3XX_PERIPHERAL_VIRT_BASE ... IOP3XX_PERIPHERAL_UPPER_VA:
--		goto skip;
--	}
--	__iounmap(addr);
--
--skip:
--	return;
--}
--EXPORT_SYMBOL(__iop3xx_iounmap);
-diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
-index b9f0f5f..076db84f 100644
---- a/arch/arm/plat-mxc/Makefile
-+++ b/arch/arm/plat-mxc/Makefile
-@@ -5,7 +5,6 @@
- # Common support
- obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
- 
--obj-$(CONFIG_ARM_GIC) += gic.o
- obj-$(CONFIG_MXC_TZIC) += tzic.o
- obj-$(CONFIG_MXC_AVIC) += avic.o
- 
-diff --git a/arch/arm/plat-mxc/gic.c b/arch/arm/plat-mxc/gic.c
-deleted file mode 100644
-index 12f8f81..0000000
---- a/arch/arm/plat-mxc/gic.c
-+++ /dev/null
-@@ -1,41 +0,0 @@
--/*
-- * Copyright 2011 Freescale Semiconductor, Inc.
-- * Copyright 2011 Linaro Ltd.
-- *
-- * The code contained herein is licensed under the GNU General Public
-- * License. You may obtain a copy of the GNU General Public License
-- * Version 2 or later at the following locations:
-- *
-- * http://www.opensource.org/licenses/gpl-license.html
-- * http://www.gnu.org/copyleft/gpl.html
-- */
--
--#include <linux/io.h>
--#include <asm/exception.h>
--#include <asm/localtimer.h>
--#include <asm/hardware/gic.h>
--#ifdef CONFIG_SMP
--#include <asm/smp.h>
--#endif
--
--asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
--{
--	u32 irqstat, irqnr;
--
--	do {
--		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
--		irqnr = irqstat & 0x3ff;
--		if (irqnr == 1023)
--			break;
--
--		if (irqnr > 15 && irqnr < 1021)
--			handle_IRQ(irqnr, regs);
--#ifdef CONFIG_SMP
--		else {
--			writel_relaxed(irqstat, gic_cpu_base_addr +
--						GIC_CPU_EOI);
--			handle_IPI(irqnr, regs);
--		}
--#endif
--	} while (1);
--}
-diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
-index c75f254..6698cae 100644
---- a/arch/arm/plat-mxc/include/mach/common.h
-+++ b/arch/arm/plat-mxc/include/mach/common.h
-@@ -89,7 +89,6 @@ extern void imx_print_silicon_rev(const char *cpu, int srev);
- 
- void avic_handle_irq(struct pt_regs *);
- void tzic_handle_irq(struct pt_regs *);
--void gic_handle_irq(struct pt_regs *);
- 
- #define imx1_handle_irq avic_handle_irq
- #define imx21_handle_irq avic_handle_irq
-diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
-index ca5cf26..def5d30 100644
---- a/arch/arm/plat-mxc/include/mach/entry-macro.S
-+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
-@@ -9,19 +9,8 @@
-  * published by the Free Software Foundation.
-  */
- 
--/* Unused, we use CONFIG_MULTI_IRQ_HANDLER */
--
- 	.macro	disable_fiq
- 	.endm
- 
--	.macro  get_irqnr_preamble, base, tmp
--	.endm
--
- 	.macro  arch_ret_to_user, tmp1, tmp2
- 	.endm
--
--	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
--	.endm
--
--	.macro test_for_ipi, irqnr, irqstat, base, tmp
--	.endm
-diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
-index 97b19e7..2b7c08d 100644
---- a/arch/arm/plat-mxc/include/mach/mx1.h
-+++ b/arch/arm/plat-mxc/include/mach/mx1.h
-@@ -12,8 +12,6 @@
- #ifndef __MACH_MX1_H__
- #define __MACH_MX1_H__
- 
--#include <mach/vmalloc.h>
--
- /*
-  * Memory map
-  */
-diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
-deleted file mode 100644
-index ef6379c..0000000
---- a/arch/arm/plat-mxc/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,22 +0,0 @@
--/*
-- *  Copyright (C) 2000 Russell King.
-- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- */
--
--#ifndef __ASM_ARCH_MXC_VMALLOC_H__
--#define __ASM_ARCH_MXC_VMALLOC_H__
--
--/* vmalloc ending address */
--#define VMALLOC_END       0xf4000000UL
--
--#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
-diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
-index d65fb31..7e5c76e 100644
---- a/arch/arm/plat-mxc/system.c
-+++ b/arch/arm/plat-mxc/system.c
-@@ -71,7 +71,7 @@ void arch_reset(char mode, const char *cmd)
- 	mdelay(50);
- 
- 	/* we'll take a jump through zero as a poor second */
--	cpu_reset(0);
-+	soft_restart(0);
- }
- 
- void mxc_arch_reset_init(void __iomem *base)
-diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
-index aa59f42..734009a 100644
---- a/arch/arm/plat-omap/Kconfig
-+++ b/arch/arm/plat-omap/Kconfig
-@@ -24,6 +24,8 @@ config ARCH_OMAP2PLUS
- 	select CLKDEV_LOOKUP
- 	select GENERIC_IRQ_CHIP
- 	select OMAP_DM_TIMER
-+	select USE_OF
-+	select PROC_DEVICETREE
- 	help
- 	  "Systems based on OMAP2, OMAP3 or OMAP4"
- 
-diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
-index 9852622..500f671 100644
---- a/arch/arm/plat-omap/Makefile
-+++ b/arch/arm/plat-omap/Makefile
-@@ -3,8 +3,15 @@
- #
- 
- # Common support
--obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
--	 usb.o fb.o io.o counter_32k.o
-+obj-y := common.o sram.o clock.o devices.o mux.o \
-+	 usb.o fb.o counter_32k.o
-+
-+ifeq ($(CONFIG_OMAP3_EDMA),y)
-+ obj-y += sdma2edma.o
-+else
-+ obj-y += dma.o
-+endif
-+
- obj-m :=
- obj-n :=
- obj-  :=
-@@ -19,7 +26,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
- 
- obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
- 
--obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
- obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
- obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
- obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
-diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
-index d9f10a3..06383b5 100644
---- a/arch/arm/plat-omap/common.c
-+++ b/arch/arm/plat-omap/common.c
-@@ -14,6 +14,7 @@
- #include <linux/kernel.h>
- #include <linux/init.h>
- #include <linux/io.h>
-+#include <linux/dma-mapping.h>
- #include <linux/omapfb.h>
- 
- #include <plat/common.h>
-@@ -21,6 +22,8 @@
- #include <plat/vram.h>
- #include <plat/dsp.h>
- 
-+#include <plat/omap-secure.h>
-+
- 
- #define NO_LENGTH_CHECK 0xffffffff
- 
-@@ -65,4 +68,12 @@ void __init omap_reserve(void)
- 	omapfb_reserve_sdram_memblock();
- 	omap_vram_reserve_sdram_memblock();
- 	omap_dsp_reserve_sdram_memblock();
-+	omap_secure_ram_reserve_memblock();
-+}
-+
-+void __init omap_init_consistent_dma_size(void)
-+{
-+#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
-+	init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
-+#endif
- }
-diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
-deleted file mode 100644
-index da4f68d..0000000
---- a/arch/arm/plat-omap/cpu-omap.c
-+++ /dev/null
-@@ -1,171 +0,0 @@
--/*
-- *  linux/arch/arm/plat-omap/cpu-omap.c
-- *
-- *  CPU frequency scaling for OMAP
-- *
-- *  Copyright (C) 2005 Nokia Corporation
-- *  Written by Tony Lindgren <tony@atomide.com>
-- *
-- *  Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--#include <linux/types.h>
--#include <linux/kernel.h>
--#include <linux/sched.h>
--#include <linux/cpufreq.h>
--#include <linux/delay.h>
--#include <linux/init.h>
--#include <linux/err.h>
--#include <linux/clk.h>
--#include <linux/io.h>
--
--#include <mach/hardware.h>
--#include <plat/clock.h>
--#include <asm/system.h>
--
--#define VERY_HI_RATE	900000000
--
--static struct cpufreq_frequency_table *freq_table;
--
--#ifdef CONFIG_ARCH_OMAP1
--#define MPU_CLK		"mpu"
--#else
--#define MPU_CLK		"virt_prcm_set"
--#endif
--
--static struct clk *mpu_clk;
--
--/* TODO: Add support for SDRAM timing changes */
--
--static int omap_verify_speed(struct cpufreq_policy *policy)
--{
--	if (freq_table)
--		return cpufreq_frequency_table_verify(policy, freq_table);
--
--	if (policy->cpu)
--		return -EINVAL;
--
--	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
--				     policy->cpuinfo.max_freq);
--
--	policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000;
--	policy->max = clk_round_rate(mpu_clk, policy->max * 1000) / 1000;
--	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
--				     policy->cpuinfo.max_freq);
--	return 0;
--}
--
--static unsigned int omap_getspeed(unsigned int cpu)
--{
--	unsigned long rate;
--
--	if (cpu)
--		return 0;
--
--	rate = clk_get_rate(mpu_clk) / 1000;
--	return rate;
--}
--
--static int omap_target(struct cpufreq_policy *policy,
--		       unsigned int target_freq,
--		       unsigned int relation)
--{
--	struct cpufreq_freqs freqs;
--	int ret = 0;
--
--	/* Ensure desired rate is within allowed range.  Some govenors
--	 * (ondemand) will just pass target_freq=0 to get the minimum. */
--	if (target_freq < policy->min)
--		target_freq = policy->min;
--	if (target_freq > policy->max)
--		target_freq = policy->max;
--
--	freqs.old = omap_getspeed(0);
--	freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
--	freqs.cpu = 0;
--
--	if (freqs.old == freqs.new)
--		return ret;
--
--	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
--#ifdef CONFIG_CPU_FREQ_DEBUG
--	printk(KERN_DEBUG "cpufreq-omap: transition: %u --> %u\n",
--	       freqs.old, freqs.new);
--#endif
--	ret = clk_set_rate(mpu_clk, freqs.new * 1000);
--	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
--
--	return ret;
--}
--
--static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
--{
--	int result = 0;
--
--	mpu_clk = clk_get(NULL, MPU_CLK);
--	if (IS_ERR(mpu_clk))
--		return PTR_ERR(mpu_clk);
--
--	if (policy->cpu != 0)
--		return -EINVAL;
--
--	policy->cur = policy->min = policy->max = omap_getspeed(0);
--
--	clk_init_cpufreq_table(&freq_table);
--	if (freq_table) {
--		result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
--		if (!result)
--			cpufreq_frequency_table_get_attr(freq_table,
--							policy->cpu);
--	} else {
--		policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
--		policy->cpuinfo.max_freq = clk_round_rate(mpu_clk,
--							VERY_HI_RATE) / 1000;
--	}
--
--	/* FIXME: what's the actual transition time? */
--	policy->cpuinfo.transition_latency = 300 * 1000;
--
--	return 0;
--}
--
--static int omap_cpu_exit(struct cpufreq_policy *policy)
--{
--	clk_exit_cpufreq_table(&freq_table);
--	clk_put(mpu_clk);
--	return 0;
--}
--
--static struct freq_attr *omap_cpufreq_attr[] = {
--	&cpufreq_freq_attr_scaling_available_freqs,
--	NULL,
--};
--
--static struct cpufreq_driver omap_driver = {
--	.flags		= CPUFREQ_STICKY,
--	.verify		= omap_verify_speed,
--	.target		= omap_target,
--	.get		= omap_getspeed,
--	.init		= omap_cpu_init,
--	.exit		= omap_cpu_exit,
--	.name		= "omap",
--	.attr		= omap_cpufreq_attr,
--};
--
--static int __init omap_cpufreq_init(void)
--{
--	return cpufreq_register_driver(&omap_driver);
--}
--
--arch_initcall(omap_cpufreq_init);
--
--/*
-- * if ever we want to remove this, upon cleanup call:
-- *
-- * cpufreq_unregister_driver()
-- * cpufreq_frequency_table_put_attr()
-- */
--
-diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
-index c22217c..002fb4d 100644
---- a/arch/arm/plat-omap/dma.c
-+++ b/arch/arm/plat-omap/dma.c
-@@ -1034,6 +1034,18 @@ dma_addr_t omap_get_dma_src_pos(int lch)
- 	if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
- 		offset = p->dma_read(CSAC, lch);
- 
-+	if (!cpu_is_omap15xx()) {
-+		/*
-+		 * CDAC == 0 indicates that the DMA transfer on the channel has
-+		 * not been started (no data has been transferred so far).
-+		 * Return the programmed source start address in this case.
-+		 */
-+		if (likely(p->dma_read(CDAC, lch)))
-+			offset = p->dma_read(CSAC, lch);
-+		else
-+			offset = p->dma_read(CSSA, lch);
-+	}
-+
- 	if (cpu_class_is_omap1())
- 		offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
- 
-@@ -1062,8 +1074,16 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
- 	 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
- 	 * read before the DMA controller finished disabling the channel.
- 	 */
--	if (!cpu_is_omap15xx() && offset == 0)
-+	if (!cpu_is_omap15xx() && offset == 0) {
- 		offset = p->dma_read(CDAC, lch);
-+		/*
-+		 * CDAC == 0 indicates that the DMA transfer on the channel has
-+		 * not been started (no data has been transferred so far).
-+		 * Return the programmed destination start address in this case.
-+		 */
-+		if (unlikely(!offset))
-+			offset = p->dma_read(CDSA, lch);
-+	}
- 
- 	if (cpu_class_is_omap1())
- 		offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
-diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
-index af3b92b..329586a 100644
---- a/arch/arm/plat-omap/dmtimer.c
-+++ b/arch/arm/plat-omap/dmtimer.c
-@@ -134,7 +134,6 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
- int omap_dm_timer_prepare(struct omap_dm_timer *timer)
- {
- 	struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
--	int ret;
- 
- 	timer->fclk = clk_get(&timer->pdev->dev, "fck");
- 	if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
-@@ -146,10 +145,8 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
- 	if (pdata->needs_manual_reset)
- 		omap_dm_timer_reset(timer);
- 
--	ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
--
- 	timer->posted = 1;
--	return ret;
-+	return 0;
- }
- 
- struct omap_dm_timer *omap_dm_timer_request(void)
-@@ -494,6 +491,40 @@ int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
- }
- EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
- 
-+int omap_dm_timer_set_capture(struct omap_dm_timer *timer, bool lht,
-+				bool hlt, bool cm)
-+{
-+	u32 l;
-+
-+	if (unlikely(!timer))
-+		return -EINVAL;
-+
-+	omap_dm_timer_enable(timer);
-+	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
-+
-+	if (lht && hlt)
-+		l |= OMAP_TIMER_CTRL_TCM_BOTHEDGES;
-+	else if (lht)
-+		l |= OMAP_TIMER_CTRL_TCM_LOWTOHIGH;
-+	else if (hlt)
-+		l |= OMAP_TIMER_CTRL_TCM_HIGHTOLOW;
-+	else
-+		l &= ~OMAP_TIMER_CTRL_TCM_BOTHEDGES;
-+
-+	if (cm)
-+		l |= OMAP_TIMER_CTRL_CAPTMODE;
-+	else
-+		l &= ~OMAP_TIMER_CTRL_CAPTMODE;
-+
-+	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
-+
-+	/* Save the context */
-+	timer->context.tclr = l;
-+	omap_dm_timer_disable(timer);
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(omap_dm_timer_set_capture);
-+
- int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
- {
- 	u32 l;
-diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
-index db071bc..b7fccc8 100644
---- a/arch/arm/plat-omap/i2c.c
-+++ b/arch/arm/plat-omap/i2c.c
-@@ -148,7 +148,8 @@ static inline int omap2_i2c_add_bus(int bus_id)
- 	struct omap_i2c_bus_platform_data *pdata;
- 	struct omap_i2c_dev_attr *dev_attr;
- 
--	omap2_i2c_mux_pins(bus_id);
-+	if (!cpu_is_am33xx())
-+		omap2_i2c_mux_pins(bus_id);
- 
- 	l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
- 	WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
-@@ -179,6 +180,8 @@ static inline int omap2_i2c_add_bus(int bus_id)
- 	 */
- 	if (cpu_is_omap34xx())
- 		pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
-+
-+	pdata->device_reset = omap_device_reset;
- 	pdev = omap_device_build(name, bus_id, oh, pdata,
- 			sizeof(struct omap_i2c_bus_platform_data),
- 			NULL, 0, 0);
-diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h
-new file mode 100644
-index 0000000..a16e72c
---- /dev/null
-+++ b/arch/arm/plat-omap/include/plat/am33xx.h
-@@ -0,0 +1,82 @@
-+/*
-+ * This file contains the address info for various AM33XX modules.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ASM_ARCH_AM33XX_H
-+#define __ASM_ARCH_AM33XX_H
-+
-+#define L4_SLOW_AM33XX_BASE	0x48000000
-+
-+#define AM33XX_SCM_BASE		0x44E10000
-+#define AM33XX_CTRL_BASE	AM33XX_SCM_BASE
-+#define AM33XX_PRCM_BASE	0x44E00000
-+
-+#define AM33XX_EMIF0_BASE	0x4C000000
-+
-+#define AM33XX_GPIO0_BASE	0x44E07000
-+#define AM33XX_GPIO1_BASE	0x4804C000
-+#define AM33XX_GPIO2_BASE	0x481AC000
-+#define AM33XX_GPIO3_BASE	0x481AE000
-+
-+#define AM33XX_TIMER0_BASE	0x44E05000
-+#define AM33XX_TIMER1_BASE	0x44E31000
-+#define AM33XX_TIMER2_BASE	0x48040000
-+#define AM33XX_TIMER3_BASE	0x48042000
-+#define AM33XX_TIMER4_BASE	0x48044000
-+#define AM33XX_TIMER5_BASE	0x48046000
-+#define AM33XX_TIMER6_BASE	0x48048000
-+#define AM33XX_TIMER7_BASE	0x4804A000
-+
-+#define AM33XX_WDT1_BASE	0x44E35000
-+
-+#define AM33XX_TSC_BASE		0x44E0D000
-+#define AM33XX_RTC_BASE		0x44E3E000
-+
-+#define AM33XX_ASP0_BASE	0x48038000
-+#define AM33XX_ASP1_BASE	0x4803C000
-+
-+#define AM33XX_MAILBOX0_BASE	0x480C8000
-+
-+#define AM33XX_MMC0_BASE	0x48060100
-+#define AM33XX_MMC1_BASE	0x481D8100
-+#define AM33XX_MMC2_BASE	0x47810100
-+
-+#define AM33XX_I2C0_BASE	0x44E0B000
-+#define AM33XX_I2C1_BASE	0x4802A000
-+#define AM33XX_I2C2_BASE	0x4819C000
-+
-+#define AM33XX_SPI0_BASE	0x48030000
-+#define AM33XX_SPI1_BASE	0x481A0000
-+
-+#define AM33XX_USBSS_BASE	0x47400000
-+#define AM33XX_USB0_BASE	0x47401000
-+#define AM33XX_USB1_BASE	0x47401800
-+
-+#define AM33XX_ELM_BASE		0x48080000
-+
-+#define AM33XX_ASP0_BASE	0x48038000
-+#define AM33XX_ASP1_BASE	0x4803C000
-+
-+#define AM33XX_CPSW_BASE       0x4A100000
-+#define AM33XX_CPSW_MDIO_BASE  0x4A101000
-+#define AM33XX_CPSW_SS_BASE    0x4A101200
-+
-+#define AM33XX_ICSS_BASE	0x4A300000
-+#define AM33XX_ICSS_LEN		0x3FFFF
-+
-+#define AM33XX_EPWMSS0_BASE	0x48300000
-+#define AM33XX_EPWMSS1_BASE	0x48302000
-+#define AM33XX_EPWMSS2_BASE	0x48304000
-+
-+#endif /* __ASM_ARCH_AM33XX_H */
-diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
-index 387a963..7b9a934 100644
---- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
-+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
-@@ -40,6 +40,8 @@ struct omap_clk {
- #define CK_443X		(1 << 11)
- #define CK_TI816X	(1 << 12)
- #define CK_446X		(1 << 13)
-+#define CK_AM33XX	(1 << 14)	/* AM33xx specific clocks */
-+#define CK_1710		(1 << 15)	/* 1710 extra for rate selection */
- 
- 
- #define CK_34XX		(CK_3430ES1 | CK_3430ES2PLUS)
-diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
-index eb73ab4..240a7b9 100644
---- a/arch/arm/plat-omap/include/plat/clock.h
-+++ b/arch/arm/plat-omap/include/plat/clock.h
-@@ -59,6 +59,8 @@ struct clkops {
- #define RATE_IN_4430		(1 << 5)
- #define RATE_IN_TI816X		(1 << 6)
- #define RATE_IN_4460		(1 << 7)
-+#define RATE_IN_AM33XX		(1 << 8)
-+#define RATE_IN_TI814X		(1 << 9)
- 
- #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
- #define RATE_IN_34XX		(RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
-@@ -84,7 +86,7 @@ struct clkops {
- struct clksel_rate {
- 	u32			val;
- 	u8			div;
--	u8			flags;
-+	u16			flags;
- };
- 
- /**
-diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
-index 3ff3e36..257f977 100644
---- a/arch/arm/plat-omap/include/plat/common.h
-+++ b/arch/arm/plat-omap/include/plat/common.h
-@@ -27,97 +27,15 @@
- #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
- #define __ARCH_ARM_MACH_OMAP_COMMON_H
- 
--#include <linux/delay.h>
--
- #include <plat/i2c.h>
- #include <plat/omap_hwmod.h>
- 
--struct sys_timer;
--
--extern void omap_map_common_io(void);
--extern struct sys_timer omap1_timer;
--extern struct sys_timer omap2_timer;
--extern struct sys_timer omap3_timer;
--extern struct sys_timer omap3_secure_timer;
--extern struct sys_timer omap4_timer;
--extern bool omap_32k_timer_init(void);
- extern int __init omap_init_clocksource_32k(void);
- extern unsigned long long notrace omap_32k_sched_clock(void);
- 
- extern void omap_reserve(void);
--
--void omap2420_init_early(void);
--void omap2430_init_early(void);
--void omap3430_init_early(void);
--void omap35xx_init_early(void);
--void omap3630_init_early(void);
--void omap3_init_early(void);	/* Do not use this one */
--void am35xx_init_early(void);
--void ti816x_init_early(void);
--void omap4430_init_early(void);
--
- extern int omap_dss_reset(struct omap_hwmod *);
- 
- void omap_sram_init(void);
- 
--/*
-- * IO bases for various OMAP processors
-- * Except the tap base, rest all the io bases
-- * listed are physical addresses.
-- */
--struct omap_globals {
--	u32		class;		/* OMAP class to detect */
--	void __iomem	*tap;		/* Control module ID code */
--	void __iomem	*sdrc;           /* SDRAM Controller */
--	void __iomem	*sms;            /* SDRAM Memory Scheduler */
--	void __iomem	*ctrl;           /* System Control Module */
--	void __iomem	*ctrl_pad;	/* PAD Control Module */
--	void __iomem	*prm;            /* Power and Reset Management */
--	void __iomem	*cm;             /* Clock Management */
--	void __iomem	*cm2;
--};
--
--void omap2_set_globals_242x(void);
--void omap2_set_globals_243x(void);
--void omap2_set_globals_3xxx(void);
--void omap2_set_globals_443x(void);
--void omap2_set_globals_ti816x(void);
--
--/* These get called from omap2_set_globals_xxxx(), do not call these */
--void omap2_set_globals_tap(struct omap_globals *);
--void omap2_set_globals_sdrc(struct omap_globals *);
--void omap2_set_globals_control(struct omap_globals *);
--void omap2_set_globals_prcm(struct omap_globals *);
--
--void omap242x_map_io(void);
--void omap243x_map_io(void);
--void omap3_map_io(void);
--void omap4_map_io(void);
--
--
--/**
-- * omap_test_timeout - busy-loop, testing a condition
-- * @cond: condition to test until it evaluates to true
-- * @timeout: maximum number of microseconds in the timeout
-- * @index: loop index (integer)
-- *
-- * Loop waiting for @cond to become true or until at least @timeout
-- * microseconds have passed.  To use, define some integer @index in the
-- * calling code.  After running, if @index == @timeout, then the loop has
-- * timed out.
-- */
--#define omap_test_timeout(cond, timeout, index)			\
--({								\
--	for (index = 0; index < timeout; index++) {		\
--		if (cond)					\
--			break;					\
--		udelay(1);					\
--	}							\
--})
--
--extern struct device *omap2_get_mpuss_device(void);
--extern struct device *omap2_get_iva_device(void);
--extern struct device *omap2_get_l3_device(void);
--extern struct device *omap4_get_dsp_device(void);
--
- #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
-diff --git a/arch/arm/plat-omap/include/plat/config_pwm.h b/arch/arm/plat-omap/include/plat/config_pwm.h
-new file mode 100644
-index 0000000..a0c568a
---- /dev/null
-+++ b/arch/arm/plat-omap/include/plat/config_pwm.h
-@@ -0,0 +1,26 @@
-+#ifndef __CONFIG_CONFIG_PWM
-+#define __CONFIG_CONFIG_PWM
-+
-+#define AM33XX_CONFIG_BASE      (0x0)
-+#define AM33XX_CONFIG_SIZE      (AM33XX_CONFIG_BASE + 0x10)
-+#define AM33XX_ECAP_BASE        (0x0100)
-+#define AM33XX_ECAP_SIZE        (AM33XX_ECAP_BASE + 0x080)
-+#define AM33XX_EQEP_BASE        (0x0180)
-+#define AM33XX_EQeP_SIZE        (AM33XX_EQEP_BASE + 0x080)
-+#define AM33XX_EPWM_BASE        (0x0200)
-+#define AM33XX_EPWM_SIZE        (AM33XX_EPWM_BASE + 0x0100)
-+
-+#define PWMSS_CLKCONFIG          (0x08)
-+#define ECAP_CLK_EN              (0x0)
-+#define ECAP_CLK_STOP_REQ        (0x1)
-+#define EQEP_CLK_EN              (0x4)
-+#define EQEP_CLK_STOP_REQ        (0x5)
-+#define EPWM_CLK_EN              (0x8)
-+#define EPWM_CLK_STOP_REQ        (0x9)
-+
-+#define SET                      (1)
-+#define CLEAR                    (0)
-+
-+#define PWM_CON_ID_STRING_LENGTH (12)
-+
-+#endif
-diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
-index 408a12f..16aae2b 100644
---- a/arch/arm/plat-omap/include/plat/cpu.h
-+++ b/arch/arm/plat-omap/include/plat/cpu.h
-@@ -69,6 +69,7 @@ unsigned int omap_rev(void);
-  * cpu_is_omap343x():	True for OMAP3430
-  * cpu_is_omap443x():	True for OMAP4430
-  * cpu_is_omap446x():	True for OMAP4460
-+ * cpu_is_omap447x():	True for OMAP4470
-  */
- #define GET_OMAP_CLASS	(omap_rev() & 0xff)
- 
-@@ -78,6 +79,22 @@ static inline int is_omap ##class (void)		\
- 	return (GET_OMAP_CLASS == (id)) ? 1 : 0;	\
- }
- 
-+#define GET_AM_CLASS	((omap_rev() >> 24) & 0xff)
-+
-+#define IS_AM_CLASS(class, id)				\
-+static inline int is_am ##class (void)			\
-+{							\
-+	return (GET_AM_CLASS == (id)) ? 1 : 0;		\
-+}
-+
-+#define GET_TI_CLASS	((omap_rev() >> 24) & 0xff)
-+
-+#define IS_TI_CLASS(class, id)			\
-+static inline int is_ti ##class (void)		\
-+{							\
-+	return (GET_TI_CLASS == (id)) ? 1 : 0;	\
-+}
-+
- #define GET_OMAP_SUBCLASS	((omap_rev() >> 20) & 0x0fff)
- 
- #define IS_OMAP_SUBCLASS(subclass, id)			\
-@@ -92,12 +109,21 @@ static inline int is_ti ##subclass (void)		\
- 	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
- }
- 
-+#define IS_AM_SUBCLASS(subclass, id)			\
-+static inline int is_am ##subclass (void)		\
-+{							\
-+	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
-+}
-+
- IS_OMAP_CLASS(7xx, 0x07)
- IS_OMAP_CLASS(15xx, 0x15)
- IS_OMAP_CLASS(16xx, 0x16)
- IS_OMAP_CLASS(24xx, 0x24)
- IS_OMAP_CLASS(34xx, 0x34)
- IS_OMAP_CLASS(44xx, 0x44)
-+IS_AM_CLASS(33xx, 0x33)
-+
-+IS_TI_CLASS(81xx, 0x81)
- 
- IS_OMAP_SUBCLASS(242x, 0x242)
- IS_OMAP_SUBCLASS(243x, 0x243)
-@@ -105,8 +131,11 @@ IS_OMAP_SUBCLASS(343x, 0x343)
- IS_OMAP_SUBCLASS(363x, 0x363)
- IS_OMAP_SUBCLASS(443x, 0x443)
- IS_OMAP_SUBCLASS(446x, 0x446)
-+IS_OMAP_SUBCLASS(447x, 0x447)
- 
- IS_TI_SUBCLASS(816x, 0x816)
-+IS_TI_SUBCLASS(814x, 0x814)
-+IS_AM_SUBCLASS(335x, 0x335)
- 
- #define cpu_is_omap7xx()		0
- #define cpu_is_omap15xx()		0
-@@ -116,10 +145,15 @@ IS_TI_SUBCLASS(816x, 0x816)
- #define cpu_is_omap243x()		0
- #define cpu_is_omap34xx()		0
- #define cpu_is_omap343x()		0
-+#define cpu_is_ti81xx()			0
- #define cpu_is_ti816x()			0
-+#define cpu_is_ti814x()			0
-+#define cpu_is_am33xx()			0
-+#define cpu_is_am335x()			0
- #define cpu_is_omap44xx()		0
- #define cpu_is_omap443x()		0
- #define cpu_is_omap446x()		0
-+#define cpu_is_omap447x()		0
- 
- #if defined(MULTI_OMAP1)
- # if defined(CONFIG_ARCH_OMAP730)
-@@ -322,7 +356,11 @@ IS_OMAP_TYPE(3517, 0x3517)
- # undef cpu_is_omap3530
- # undef cpu_is_omap3505
- # undef cpu_is_omap3517
-+# undef cpu_is_ti81xx
- # undef cpu_is_ti816x
-+# undef cpu_is_ti814x
-+# undef cpu_is_am33xx
-+# undef cpu_is_am335x
- # define cpu_is_omap3430()		is_omap3430()
- # define cpu_is_omap3503()		(cpu_is_omap3430() &&		\
- 						(!omap3_has_iva()) &&	\
-@@ -339,16 +377,22 @@ IS_OMAP_TYPE(3517, 0x3517)
- 						!omap3_has_sgx())
- # undef cpu_is_omap3630
- # define cpu_is_omap3630()		is_omap363x()
-+# define cpu_is_ti81xx()		is_ti81xx()
- # define cpu_is_ti816x()		is_ti816x()
-+# define cpu_is_ti814x()		is_ti814x()
-+# define cpu_is_am33xx()		is_am33xx()
-+# define cpu_is_am335x()		is_am335x()
- #endif
- 
- # if defined(CONFIG_ARCH_OMAP4)
- # undef cpu_is_omap44xx
- # undef cpu_is_omap443x
- # undef cpu_is_omap446x
-+# undef cpu_is_omap447x
- # define cpu_is_omap44xx()		is_omap44xx()
- # define cpu_is_omap443x()		is_omap443x()
- # define cpu_is_omap446x()		is_omap446x()
-+# define cpu_is_omap447x()		is_omap447x()
- # endif
- 
- /* Macros to detect if we have OMAP1 or OMAP2 */
-@@ -386,16 +430,34 @@ IS_OMAP_TYPE(3517, 0x3517)
- #define TI8168_REV_ES1_0	TI816X_CLASS
- #define TI8168_REV_ES1_1	(TI816X_CLASS | (0x1 << 8))
- 
-+#define TI814X_CLASS		0x81400034
-+#define TI8148_REV_ES1_0	TI814X_CLASS
-+#define TI8148_REV_ES2_0	(TI814X_CLASS | (0x1 << 8))
-+#define TI8148_REV_ES2_1	(TI814X_CLASS | (0x2 << 8))
-+
-+#define AM335X_CLASS		0x33500034
-+#define AM335X_REV_ES1_0	AM335X_CLASS
-+
- #define OMAP443X_CLASS		0x44300044
- #define OMAP4430_REV_ES1_0	(OMAP443X_CLASS | (0x10 << 8))
- #define OMAP4430_REV_ES2_0	(OMAP443X_CLASS | (0x20 << 8))
- #define OMAP4430_REV_ES2_1	(OMAP443X_CLASS | (0x21 << 8))
- #define OMAP4430_REV_ES2_2	(OMAP443X_CLASS | (0x22 << 8))
-+#define OMAP4430_REV_ES2_3	(OMAP443X_CLASS | (0x23 << 8))
- 
- #define OMAP446X_CLASS		0x44600044
- #define OMAP4460_REV_ES1_0	(OMAP446X_CLASS | (0x10 << 8))
- 
--void omap2_check_revision(void);
-+#define OMAP447X_CLASS		0x44700044
-+#define OMAP4470_REV_ES1_0	(OMAP447X_CLASS | (0x10 << 8))
-+
-+void omap2xxx_check_revision(void);
-+void omap3xxx_check_revision(void);
-+void omap4xxx_check_revision(void);
-+void omap3xxx_check_features(void);
-+void ti81xx_check_features(void);
-+void am33xx_check_features(void);
-+void omap4xxx_check_features(void);
- 
- /*
-  * Runtime detection of OMAP3 features
-diff --git a/arch/arm/plat-omap/include/plat/dma-33xx.h b/arch/arm/plat-omap/include/plat/dma-33xx.h
-new file mode 100644
-index 0000000..bebdaa7
---- /dev/null
-+++ b/arch/arm/plat-omap/include/plat/dma-33xx.h
-@@ -0,0 +1,87 @@
-+/*
-+ * AM33XX SDMA channel definitions
-+ *
-+ * This file is automatically generated from the AM33XX hardware databases.
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
-+#define __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
-+
-+
-+#define AM33XX_DMA_ICSS0_7				0
-+#define AM33XX_DMA_ICSS0_6				1
-+#define AM33XX_DMA_MMCHS1_W				2
-+#define AM33XX_DMA_MMCHS1_R				3
-+#define AM33XX_DMA_AESEIP36T0_CTXIN			4
-+#define AM33XX_DMA_AESEIP36T0_DIN			5
-+#define AM33XX_DMA_AESEIP36T0_DOUT			6
-+#define AM33XX_DMA_AESEIP36T0_CTXOUT			7
-+#define AM33XX_DMA_MCASP0_X				8
-+#define AM33XX_DMA_MCASP0_R				9
-+#define AM33XX_DMA_MCASP1_X				10
-+#define AM33XX_DMA_MCASP1_R				11
-+#define AM33XX_DMA_MCASP2_X				12
-+#define AM33XX_DMA_MCASP2_R				13
-+#define AM33XX_DMA_PWMSS0_EPWM				14
-+#define AM33XX_DMA_PWMSS1_EPWM				15
-+#define AM33XX_DMA_SPIOCP0_CH0W				16
-+#define AM33XX_DMA_SPIOCP0_CH0R				17
-+#define AM33XX_DMA_SPIOCP0_CH1W				18
-+#define AM33XX_DMA_SPIOCP0_CH1R				19
-+#define AM33XX_DMA_SPIOCP3_CH1W				20
-+#define AM33XX_DMA_SPIOCP3_CH1R				21
-+#define AM33XX_DMA_GPIO					22
-+#define AM33XX_DMA_GPIO1				23
-+#define AM33XX_DMA_MMCHS0_W				24
-+#define AM33XX_DMA_MMCHS0_R				25
-+#define AM33XX_DMA_UART0_0				26
-+#define AM33XX_DMA_UART0_1				27
-+#define AM33XX_DMA_UART1_0				28
-+#define AM33XX_DMA_UART1_1				29
-+#define AM33XX_DMA_UART2_0				30
-+#define AM33XX_DMA_UART2_1				31
-+#define AM33XX_DMA_DESEIP16T0_IN			32
-+#define AM33XX_DMA_DESEIP16T0				33
-+#define AM33XX_DMA_DESEIP16T0_OUT			34
-+#define AM33XX_DMA_SHAEIP57T0_CTXIN			35
-+#define AM33XX_DMA_SHAEIP57T0_DIN			36
-+#define AM33XX_DMA_SHAEIP57T0_CTXOUT			37
-+#define AM33XX_DMA_PWMSS0_ECAP				38
-+#define AM33XX_DMA_PWMSS1_ECAP				39
-+#define AM33XX_DMA_DCAN_1				40
-+#define AM33XX_DMA_DCAN_2				41
-+#define AM33XX_DMA_SPIOCP1_CH0W				42
-+#define AM33XX_DMA_SPIOCP1_CH0R				43
-+#define AM33XX_DMA_SPIOCP1_CH1W				44
-+#define AM33XX_DMA_SPIOCP1_CH1R				45
-+#define AM33XX_DMA_PWMSS0_EQEP				46
-+#define AM33XX_DMA_DCAN_3				47
-+#define AM33XX_DMA_TIMER_4				48
-+#define AM33XX_DMA_TIMER_5				49
-+#define AM33XX_DMA_TIMER_6				50
-+#define AM33XX_DMA_TIMER_7				51
-+#define AM33XX_DMA_GPM					52
-+#define AM33XX_DMA_ADC0					53
-+#define AM33XX_DMA_PWMSS1_EQEP				56
-+#define AM33XX_DMA_ADC1					57
-+#define AM33XX_DMA_MSHSI2COCP0_TX			58
-+#define AM33XX_DMA_MSHSI2COCP0_RX			59
-+#define AM33XX_DMA_MSHSI2COCP1_TX			60
-+#define AM33XX_DMA_MSHSI2COCP1_RX			61
-+#define AM33XX_DMA_PWMSS2_ECAP				62
-+#define AM33XX_DMA_PWMSS2_EPW				63
-+#define AM33XX_DMA_MMCHS2_W				64	/* xBar */
-+#define AM33XX_DMA_MMCHS2_R				65	/* xBar */
-+
-+#endif
-diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
-index dc562a5..c865dbc 100644
---- a/arch/arm/plat-omap/include/plat/dma.h
-+++ b/arch/arm/plat-omap/include/plat/dma.h
-@@ -30,6 +30,7 @@
- 
- /* Move omap4 specific defines to dma-44xx.h */
- #include "dma-44xx.h"
-+#include "dma-33xx.h"
- 
- /* DMA channels for omap1 */
- #define OMAP_DMA_NO_DEVICE		0
-diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
-index 9418f00..d9432b0 100644
---- a/arch/arm/plat-omap/include/plat/dmtimer.h
-+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
-@@ -47,6 +47,7 @@
- 
- /* timer interrupt enable bits */
- #define OMAP_TIMER_INT_CAPTURE			(1 << 2)
-+#define OMAP_TIMER_INT_CAPTURE_RESET		(0 << 2)
- #define OMAP_TIMER_INT_OVERFLOW			(1 << 1)
- #define OMAP_TIMER_INT_MATCH			(1 << 0)
- 
-@@ -127,6 +128,8 @@ int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned
- int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
- int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
- int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
-+int omap_dm_timer_set_capture(struct omap_dm_timer *timer,
-+				bool lht, bool hlt, bool cm);
- int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
- 
- int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
-diff --git a/arch/arm/plat-omap/include/plat/elm.h b/arch/arm/plat-omap/include/plat/elm.h
-new file mode 100644
-index 0000000..50b4c8a
---- /dev/null
-+++ b/arch/arm/plat-omap/include/plat/elm.h
-@@ -0,0 +1,33 @@
-+/*
-+ * BCH Error Location Module for TI81xx
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef OMAP_ELM_H
-+#define OMAP_ELM_H
-+
-+enum omap_bch_ecc {
-+	OMAP_BCH4_ECC = 0,
-+	OMAP_BCH8_ECC,
-+	OMAP_BCH16_ECC,
-+};
-+
-+#define BCH8_ECC_BYTES			(512)
-+#define BCH8_ECC_OOB_BYTES		(13)
-+#define BCH_MAX_ECC_BYTES_PER_SECTOR	(28)
-+#define BCH8_ECC_MAX	((BCH8_ECC_BYTES + BCH8_ECC_OOB_BYTES) * 8)
-+
-+int omap_elm_decode_bch_error(int bch_type, char *ecc_calc,
-+		unsigned int *err_loc);
-+void omap_configure_elm(struct mtd_info *mtdi, int bch_type);
-+#endif /* OMAP_ELM_H */
-diff --git a/arch/arm/plat-omap/include/plat/emif.h b/arch/arm/plat-omap/include/plat/emif.h
-new file mode 100644
-index 0000000..314c126
---- /dev/null
-+++ b/arch/arm/plat-omap/include/plat/emif.h
-@@ -0,0 +1,41 @@
-+/*
-+ * EMIF register definitions for TI81xx and AM33xx
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __EMIF_H
-+#define __EMIF_H
-+
-+#define EMIF_MOD_ID_REV			(0x0)
-+#define EMIF4_0_SDRAM_STATUS            (0x04)
-+#define EMIF4_0_SDRAM_CONFIG            (0x08)
-+#define EMIF4_0_SDRAM_CONFIG2           (0x0C)
-+#define EMIF4_0_SDRAM_REF_CTRL          (0x10)
-+#define EMIF4_0_SDRAM_REF_CTRL_SHADOW   (0x14)
-+#define EMIF4_0_SDRAM_TIM_1             (0x18)
-+#define EMIF4_0_SDRAM_TIM_1_SHADOW      (0x1C)
-+#define EMIF4_0_SDRAM_TIM_2             (0x20)
-+#define EMIF4_0_SDRAM_TIM_2_SHADOW      (0x24)
-+#define EMIF4_0_SDRAM_TIM_3             (0x28)
-+#define EMIF4_0_SDRAM_TIM_3_SHADOW      (0x2C)
-+#define EMIF4_0_SDRAM_MGMT_CTRL         (0x38)
-+#define EMIF4_0_SDRAM_MGMT_CTRL_SHD     (0x3C)
-+#define EMIF4_0_DDR_PHY_CTRL_1          (0xE4)
-+#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW   (0xE8)
-+#define EMIF4_0_DDR_PHY_CTRL_2          (0xEC)
-+#define EMIF4_0_IODFT_TLGC              (0x60)
-+
-+#define SELF_REFRESH_ENABLE(m)		(0x2 << 8 | (m << 4))
-+#define SELF_REFRESH_DISABLE		(0x0 << 8)
-+
-+#endif /* __EMIF_H */
-diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
-index 1527929..2b81fc6 100644
---- a/arch/arm/plat-omap/include/plat/gpmc.h
-+++ b/arch/arm/plat-omap/include/plat/gpmc.h
-@@ -92,6 +92,8 @@ enum omap_ecc {
- 	OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
- 		/* 1-bit ecc: stored at beginning of spare area as romcode */
- 	OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
-+	OMAP_ECC_BCH4_CODE_HW, /* gpmc bch detection & s/w method correction */
-+	OMAP_ECC_BCH8_CODE_HW, /* gpmc bch detection & s/w method correction */
- };
- 
- /*
-@@ -131,6 +133,21 @@ struct gpmc_timings {
- 	u16 wr_data_mux_bus;	/* WRDATAONADMUXBUS */
- };
- 
-+
-+struct gpmc_devices_info {
-+	void	*pdata;
-+	int	flag;
-+};
-+
-+#define	GPMC_DEVICE_NAND	(1 << 0)
-+#define	GPMC_DEVICE_ONENAND	(1 << 1)
-+#define	GPMC_DEVICE_NOR		(1 << 2)
-+#define	GPMC_DEVICE_SMC91X	(1 << 3)
-+#define	GPMC_DEVICE_SMS911X	(1 << 4)
-+#define	GPMC_DEVICE_TUSB6010	(1 << 5)
-+
-+extern int omap_init_gpmc(struct gpmc_devices_info *pdata, int pdata_len);
-+
- extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
- extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
- extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
-@@ -155,6 +172,8 @@ extern int gpmc_cs_configure(int cs, int cmd, int wval);
- extern int gpmc_nand_read(int cs, int cmd);
- extern int gpmc_nand_write(int cs, int cmd, int wval);
- 
--int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
--int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
-+int gpmc_enable_hwecc(int ecc, int cs, int mode, int dev_width, int ecc_size);
-+int gpmc_calculate_ecc(int ecc, int cs, const u_char *dat, u_char *ecc_code);
-+int gpmc_suspend(void);
-+int gpmc_resume(void);
- #endif
-diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
-index e87efe1..e897978 100644
---- a/arch/arm/plat-omap/include/plat/hardware.h
-+++ b/arch/arm/plat-omap/include/plat/hardware.h
-@@ -286,6 +286,7 @@
- #include <plat/omap24xx.h>
- #include <plat/omap34xx.h>
- #include <plat/omap44xx.h>
--#include <plat/ti816x.h>
-+#include <plat/ti81xx.h>
-+#include <plat/am33xx.h>
- 
- #endif	/* __ASM_ARCH_OMAP_HARDWARE_H */
-diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
-index 7f2969e..0696bae 100644
---- a/arch/arm/plat-omap/include/plat/io.h
-+++ b/arch/arm/plat-omap/include/plat/io.h
-@@ -73,6 +73,9 @@
- #define OMAP4_L3_IO_OFFSET	0xb4000000
- #define OMAP4_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
- 
-+#define AM33XX_L4_WK_IO_OFFSET	0xb5000000
-+#define AM33XX_L4_WK_IO_ADDRESS(pa)	IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
-+
- #define OMAP4_L3_PER_IO_OFFSET	0xb1100000
- #define OMAP4_L3_PER_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
- 
-@@ -154,6 +157,15 @@
- #define L4_34XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect */
- 
- /*
-+ * ----------------------------------------------------------------------------
-+ * AM33XX specific IO mapping
-+ * ----------------------------------------------------------------------------
-+ */
-+#define L4_WK_AM33XX_PHYS	L4_WK_AM33XX_BASE
-+#define L4_WK_AM33XX_VIRT	(L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
-+#define L4_WK_AM33XX_SIZE	SZ_4M   /* 1MB of 128MB used, want 1MB sect */
-+
-+/*
-  * Need to look at the Size 4M for L4.
-  * VPOM3430 was not working for Int controller
-  */
-@@ -247,8 +259,6 @@
-  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
-  */
- 
--void omap_ioremap_init(void);
--
- extern u8 omap_readb(u32 pa);
- extern u16 omap_readw(u32 pa);
- extern u32 omap_readl(u32 pa);
-@@ -257,83 +267,9 @@ extern void omap_writew(u16 v, u32 pa);
- extern void omap_writel(u32 v, u32 pa);
- 
- struct omap_sdrc_params;
--
--#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
--void omap7xx_map_io(void);
--#else
--static inline void omap_map_io(void)
--{
--}
--#endif
--
--#ifdef CONFIG_ARCH_OMAP15XX
--void omap15xx_map_io(void);
--#else
--static inline void omap15xx_map_io(void)
--{
--}
--#endif
--
--#ifdef CONFIG_ARCH_OMAP16XX
--void omap16xx_map_io(void);
--#else
--static inline void omap16xx_map_io(void)
--{
--}
--#endif
--
--void omap1_init_early(void);
--
--#ifdef CONFIG_SOC_OMAP2420
--extern void omap242x_map_common_io(void);
--#else
--static inline void omap242x_map_common_io(void)
--{
--}
--#endif
--
--#ifdef CONFIG_SOC_OMAP2430
--extern void omap243x_map_common_io(void);
--#else
--static inline void omap243x_map_common_io(void)
--{
--}
--#endif
--
--#ifdef CONFIG_ARCH_OMAP3
--extern void omap34xx_map_common_io(void);
--#else
--static inline void omap34xx_map_common_io(void)
--{
--}
--#endif
--
--#ifdef CONFIG_SOC_OMAPTI816X
--extern void omapti816x_map_common_io(void);
--#else
--static inline void omapti816x_map_common_io(void)
--{
--}
--#endif
--
--#ifdef CONFIG_ARCH_OMAP4
--extern void omap44xx_map_common_io(void);
--#else
--static inline void omap44xx_map_common_io(void)
--{
--}
--#endif
--
--extern void omap2_init_common_infrastructure(void);
- extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
- 				      struct omap_sdrc_params *sdrc_cs1);
- 
--#define __arch_ioremap	omap_ioremap
--#define __arch_iounmap	omap_iounmap
--
--void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
--void omap_iounmap(volatile void __iomem *addr);
--
- extern void __init omap_init_consistent_dma_size(void);
- 
- #endif
-diff --git a/arch/arm/plat-omap/include/plat/irqs-33xx.h b/arch/arm/plat-omap/include/plat/irqs-33xx.h
-new file mode 100644
-index 0000000..3e12d83
---- /dev/null
-+++ b/arch/arm/plat-omap/include/plat/irqs-33xx.h
-@@ -0,0 +1,143 @@
-+/*
-+ * AM33XX interrupts.
-+ *
-+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H
-+#define __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H
-+
-+
-+#define AM33XX_IRQ_ELM			4
-+#define AM33XX_IRQ_PI_NMI		7
-+#define AM33XX_IRQ_CONTROL_PLATFORM	8
-+#define AM33XX_IRQ_L3_FLAGMUX0		9
-+#define AM33XX_IRQ_L3_FLAGMUX1		10
-+#define AM33XX_IRQ_PRCM			11
-+#define AM33XX_IRQ_TPCC0_INT_PO0	12
-+#define AM33XX_IRQ_TPCC0_MPINT_PO	13
-+#define AM33XX_IRQ_TPCC0_ERRINT_PO	14
-+#define AM33XX_IRQ_WDT0			15
-+#define AM33XX_IRQ_ADC_GEN		16
-+#define AM33XX_IRQ_USBSS		17
-+#define AM33XX_IRQ_USB0			18
-+#define AM33XX_IRQ_USB1			19
-+#define AM33XX_IRQ_ICSS0_0		20
-+#define AM33XX_IRQ_ICSS0_1		21
-+#define AM33XX_IRQ_ICSS0_2		22
-+#define AM33XX_IRQ_ICSS0_3		23
-+#define AM33XX_IRQ_ICSS0_4		24
-+#define AM33XX_IRQ_ICSS0_5		25
-+#define AM33XX_IRQ_ICSS0_6		26
-+#define AM33XX_IRQ_ICSS0_7		27
-+#define AM33XX_IRQ_MMCHS1		28
-+#define AM33XX_IRQ_MMCHS2		29
-+#define AM33XX_IRQ_MSHSI2COCP2		30
-+#define AM33XX_IRQ_PWMSS0_ECAP		31
-+#define AM33XX_IRQ_GPIO2_1		32
-+#define AM33XX_IRQ_GPIO2_2		33
-+#define AM33XX_IRQ_USB_P		34
-+#define AM33XX_IRQ_PCI_SLV		35
-+#define AM33XX_IRQ_LCD			36
-+#define AM33XX_IRQ_THALIAIRQ		37
-+#define AM33XX_IRQ_BB_2DHWA		38
-+#define AM33XX_IRQ_PWMSS2_EPWM		39
-+#define AM33XX_IRQ_CPSW_C0_RX		40
-+#define AM33XX_IRQ_CPSW_RX		41
-+#define AM33XX_IRQ_CPSW_TX		42
-+#define AM33XX_IRQ_CPSW_C0		43
-+#define AM33XX_IRQ_UART3		44
-+#define AM33XX_IRQ_UART4		45
-+#define AM33XX_IRQ_UART5		46
-+#define AM33XX_IRQ_PWMSS1_ECAP		47
-+#define AM33XX_IRQ_PCI0			48
-+#define AM33XX_IRQ_PCI1			49
-+#define AM33XX_IRQ_PCI2			50
-+#define AM33XX_IRQ_PCI3			51
-+#define AM33XX_IRQ_DCAN0_0		52
-+#define AM33XX_IRQ_DCAN0_1		53
-+#define AM33XX_IRQ_DCAN0_UERR		54
-+#define AM33XX_IRQ_DCAN1_0		55
-+#define AM33XX_IRQ_DCAN1_1		56
-+#define AM33XX_IRQ_DCAN1_UERR		57
-+#define AM33XX_IRQ_PWMSS0		58
-+#define AM33XX_IRQ_PWMSS1		59
-+#define AM33XX_IRQ_PWMSS2		60
-+#define AM33XX_IRQ_PWMSS2_ECAP		61
-+#define AM33XX_IRQ_GPIO3_1		62
-+#define AM33XX_IRQ_GPIO3_2		63
-+#define AM33XX_IRQ_MMCHS0		64
-+#define AM33XX_IRQ_MCSPIOCP0		65
-+#define AM33XX_IRQ_DMTIMER0		66
-+#define AM33XX_IRQ_DMTIMER1		67
-+#define AM33XX_IRQ_DMTIMER2		68
-+#define AM33XX_IRQ_DMTIMER3		69
-+#define AM33XX_IRQ_MSHSI2COCP0		70
-+#define AM33XX_IRQ_MSHSI2COCP1		71
-+#define AM33XX_IRQ_UART0		72
-+#define AM33XX_IRQ_UART1		73
-+#define AM33XX_IRQ_UART2		74
-+#define AM33XX_IRQ_RTC_TIMER		75
-+#define AM33XX_IRQ_RTC_ALARM		76
-+#define AM33XX_IRQ_MAILBOX		77
-+#define AM33XX_IRQ_M3_M3SP_TXEV		78
-+#define AM33XX_IRQ_PWMSS0_EQEP		79
-+#define AM33XX_IRQ_MCASP0_AX		80
-+#define AM33XX_IRQ_MCASP0_AR		81
-+#define AM33XX_IRQ_MCASP1_AX		82
-+#define AM33XX_IRQ_MCASP1_AR		83
-+#define AM33XX_IRQ_MCASP2_X		84
-+#define AM33XX_IRQ_MCASP2_R		85
-+#define AM33XX_IRQ_PWMSS0_EPWM		86
-+#define AM33XX_IRQ_PWMSS1_EPWM		87
-+#define AM33XX_IRQ_PWMSS1_EQEP		88
-+#define AM33XX_IRQ_PWMSS2_EQEP		89
-+#define AM33XX_IRQ_DMA			90
-+#define AM33XX_IRQ_WDT1			91
-+#define AM33XX_IRQ_DMTIMER4		92
-+#define AM33XX_IRQ_DMTIMER5		93
-+#define AM33XX_IRQ_DMTIMER6		94
-+#define AM33XX_IRQ_DMTIMER7		95
-+#define AM33XX_IRQ_GPIO0_1		96
-+#define AM33XX_IRQ_GPIO0_2		97
-+#define AM33XX_IRQ_GPIO1_1		98
-+#define AM33XX_IRQ_GPIO1_2		99
-+#define AM33XX_IRQ_GPMC0		100
-+#define AM33XX_IRQ_EMI			101
-+#define AM33XX_IRQ_AESEIP36t0_S		102
-+#define AM33XX_IRQ_AESEIP36t0_P		103
-+#define AM33XX_IRQ_AESEIP36t1_S		104
-+#define AM33XX_IRQ_AESEIP36t1_P		105
-+#define AM33XX_IRQ_DESEIP16t0_S		106
-+#define AM33XX_IRQ_DESEIP16t0_P		107
-+#define AM33XX_IRQ_SHAEIP57t0_S		108
-+#define AM33XX_IRQ_SHAEIP57t0_P		109
-+#define AM33XX_IRQ_PKAEIP29t0_S		110
-+#define AM33XX_IRQ_RNGEIP75t0		111
-+#define AM33XX_IRQ_TPTC0		112
-+#define AM33XX_IRQ_TPTC1		113
-+#define AM33XX_IRQ_TPTC2		114
-+#define AM33XX_IRQ_TSC			115
-+#define AM33XX_IRQ_SDMA0		116
-+#define AM33XX_IRQ_SDMA1		117
-+#define AM33XX_IRQ_SDMA2		118
-+#define AM33XX_IRQ_SDMA3		119
-+#define AM33XX_IRQ_SMARTREFLEX0		120
-+#define AM33XX_IRQ_SMARTREFLEX1		121
-+#define AM33XX_IRQ_NETRA_MMU		122
-+#define AM33XX_IRQ_DMA0			123
-+#define AM33XX_IRQ_DMA1			124
-+#define AM33XX_IRQ_SPI1			125
-+#define AM33XX_IRQ_SPI2			126
-+#define AM33XX_IRQ_SPI			127
-+
-+#endif
-diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
-index 30e1071..cc15272 100644
---- a/arch/arm/plat-omap/include/plat/irqs.h
-+++ b/arch/arm/plat-omap/include/plat/irqs.h
-@@ -30,6 +30,7 @@
- 
- /* All OMAP4 specific defines are moved to irqs-44xx.h */
- #include "irqs-44xx.h"
-+#include "irqs-33xx.h"
- 
- /*
-  * IRQ numbers for interrupt handler 1
-@@ -357,7 +358,7 @@
- #define INT_35XX_EMAC_C0_TX_PULSE_IRQ	69
- #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ	70
- #define INT_35XX_USBOTG_IRQ		71
--#define INT_35XX_UART4			84
-+#define INT_35XX_UART4_IRQ		84
- #define INT_35XX_CCDC_VD0_IRQ		88
- #define INT_35XX_CCDC_VD1_IRQ		92
- #define INT_35XX_CCDC_VD2_IRQ		93
-@@ -433,22 +434,8 @@
- 
- #define OMAP_IRQ_BIT(irq)	(1 << ((irq) % 32))
- 
--#define INTCPS_NR_MIR_REGS	3
--#define INTCPS_NR_IRQS		96
--
--#ifndef __ASSEMBLY__
--extern void __iomem *omap_irq_base;
--void omap1_init_irq(void);
--void omap2_init_irq(void);
--void omap3_init_irq(void);
--void ti816x_init_irq(void);
--extern int omap_irq_pending(void);
--void omap_intc_save_context(void);
--void omap_intc_restore_context(void);
--void omap3_intc_suspend(void);
--void omap3_intc_prepare_idle(void);
--void omap3_intc_resume_idle(void);
--#endif
-+#define INTCPS_NR_MIR_REGS	4
-+#define INTCPS_NR_IRQS		128
- 
- #include <mach/hardware.h>
- 
-diff --git a/arch/arm/plat-omap/include/plat/lcdc.h b/arch/arm/plat-omap/include/plat/lcdc.h
-new file mode 100644
-index 0000000..f8bcdec
---- /dev/null
-+++ b/arch/arm/plat-omap/include/plat/lcdc.h
-@@ -0,0 +1,21 @@
-+/*
-+ * Header file for LCD controller
-+ *
-+ * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
-+ * GNU General Public License for more details.
-+ **/
-+
-+#ifndef __OMAP2_LCDC_H
-+#define __OMAP2_LCDC_H
-+
-+struct platform_device *am33xx_register_lcdc(
-+		struct da8xx_lcdc_platform_data *pdata);
-+#endif
-diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
-index cc3921e..e136529 100644
---- a/arch/arm/plat-omap/include/plat/mailbox.h
-+++ b/arch/arm/plat-omap/include/plat/mailbox.h
-@@ -29,6 +29,8 @@ struct omap_mbox_ops {
- 	void		(*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
- 	int		(*fifo_empty)(struct omap_mbox *mbox);
- 	int		(*fifo_full)(struct omap_mbox *mbox);
-+	int		(*fifo_needs_flush)(struct omap_mbox *mbox);
-+	mbox_msg_t	(*fifo_readback)(struct omap_mbox *mbox);
- 	/* irq */
- 	void		(*enable_irq)(struct omap_mbox *mbox,
- 						omap_mbox_irq_t irq);
-@@ -61,6 +63,7 @@ struct omap_mbox {
- 	struct blocking_notifier_head   notifier;
- };
- 
-+int omap_mbox_msg_rx_flush(struct omap_mbox *mbox);
- int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
- void omap_mbox_init_seq(struct omap_mbox *);
- 
-diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
-index 3d51b18..a357eb2 100644
---- a/arch/arm/plat-omap/include/plat/mcspi.h
-+++ b/arch/arm/plat-omap/include/plat/mcspi.h
-@@ -18,9 +18,6 @@ struct omap2_mcspi_dev_attr {
- 
- struct omap2_mcspi_device_config {
- 	unsigned turbo_mode:1;
--
--	/* Do we want one channel enabled at the same time? */
--	unsigned single_channel:1;
- };
- 
- #endif
-diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
-index 94cf70a..e5b4db1 100644
---- a/arch/arm/plat-omap/include/plat/mmc.h
-+++ b/arch/arm/plat-omap/include/plat/mmc.h
-@@ -50,6 +50,11 @@
- #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT		BIT(0)
- #define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ	BIT(1)
- 
-+enum {
-+	MMC_CTRL_VERSION_1 = 0, /* OMAP class devicess */
-+	MMC_CTRL_VERSION_2	/* AM33XX class devices */
-+};
-+
- struct omap_mmc_dev_attr {
- 	u8 flags;
- };
-@@ -96,6 +101,7 @@ struct omap_mmc_platform_data {
- 		 */
- 		u8  wires;	/* Used for the MMC driver on omap1 and 2420 */
- 		u32 caps;	/* Used for the MMC driver on 2430 and later */
-+		u32 pm_caps;	/* PM capabilities of the mmc */
- 
- 		/*
- 		 * nomux means "standard" muxing is wrong on this board, and
-@@ -166,6 +172,8 @@ struct omap_mmc_platform_data {
- 		unsigned int ban_openended:1;
- 
- 	} slots[OMAP_MMC_MAX_SLOTS];
-+
-+	u8 version;
- };
- 
- /* called from board-specific card detection service routine */
-diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
-index 67fc506..9212a2e 100644
---- a/arch/arm/plat-omap/include/plat/nand.h
-+++ b/arch/arm/plat-omap/include/plat/nand.h
-@@ -29,6 +29,9 @@ struct omap_nand_platform_data {
- 	unsigned long		phys_base;
- 	int			devsize;
- 	enum omap_ecc           ecc_opt;
-+	bool			elm_used;
-+	int (*ctrlr_suspend) (void);
-+	int (*ctrlr_resume) (void);
- };
- 
- /* minimum size for IO mapping */
-diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
-new file mode 100644
-index 0000000..64f9d1c
---- /dev/null
-+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
-@@ -0,0 +1,13 @@
-+#ifndef __OMAP_SECURE_H__
-+#define __OMAP_SECURE_H__
-+
-+#include <linux/types.h>
-+
-+#ifdef CONFIG_ARCH_OMAP2PLUS
-+extern int omap_secure_ram_reserve_memblock(void);
-+#else
-+static inline void omap_secure_ram_reserve_memblock(void)
-+{ }
-+#endif
-+
-+#endif /* __OMAP_SECURE_H__ */
-diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
-index 2682043..7f5281e 100644
---- a/arch/arm/plat-omap/include/plat/omap-serial.h
-+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
-@@ -19,6 +19,7 @@
- 
- #include <linux/serial_core.h>
- #include <linux/platform_device.h>
-+#include <linux/pm_qos.h>
- 
- #include <plat/mux.h>
- 
-@@ -33,6 +34,8 @@
- 
- #define OMAP_MODE13X_SPEED	230400
- 
-+#define OMAP_UART_SCR_TX_EMPTY	0x08
-+
- /* WER = 0x7F
-  * Enable module level wakeup in WER reg
-  */
-@@ -51,18 +54,27 @@
- 
- #define OMAP_UART_DMA_CH_FREE	-1
- 
--#define RX_TIMEOUT		(3 * HZ)
--#define OMAP_MAX_HSUART_PORTS	4
-+#define OMAP_MAX_HSUART_PORTS	6
- 
- #define MSR_SAVE_FLAGS		UART_MSR_ANY_DELTA
- 
-+#define UART_ERRATA_i202_MDR1_ACCESS	BIT(0)
-+#define UART_ERRATA_i291_DMA_FORCEIDLE	BIT(1)
-+
- struct omap_uart_port_info {
- 	bool			dma_enabled;	/* To specify DMA Mode */
- 	unsigned int		uartclk;	/* UART clock rate */
--	void __iomem		*membase;	/* ioremap cookie or NULL */
--	resource_size_t		mapbase;	/* resource base */
--	unsigned long		irqflags;	/* request_irq flags */
- 	upf_t			flags;		/* UPF_* flags */
-+	u32			errata;
-+	unsigned int		dma_rx_buf_size;
-+	unsigned int		dma_rx_timeout;
-+	unsigned int		autosuspend_timeout;
-+	unsigned int		dma_rx_poll_rate;
-+
-+	int (*get_context_loss_count)(struct device *);
-+	void (*set_forceidle)(struct platform_device *);
-+	void (*set_noidle)(struct platform_device *);
-+	void (*enable_wakeup)(struct platform_device *, bool);
- };
- 
- struct uart_omap_dma {
-@@ -86,8 +98,9 @@ struct uart_omap_dma {
- 	spinlock_t		rx_lock;
- 	/* timer to poll activity on rx dma */
- 	struct timer_list	rx_timer;
--	int			rx_buf_size;
--	int			rx_timeout;
-+	unsigned int		rx_buf_size;
-+	unsigned int		rx_poll_rate;
-+	unsigned int		rx_timeout;
- };
- 
- struct uart_omap_port {
-@@ -100,6 +113,10 @@ struct uart_omap_port {
- 	unsigned char		mcr;
- 	unsigned char		fcr;
- 	unsigned char		efr;
-+	unsigned char		dll;
-+	unsigned char		dlh;
-+	unsigned char		mdr1;
-+	unsigned char		scr;
- 
- 	int			use_dma;
- 	/*
-@@ -111,6 +128,14 @@ struct uart_omap_port {
- 	unsigned char		msr_saved_flags;
- 	char			name[20];
- 	unsigned long		port_activity;
-+	u32			context_loss_cnt;
-+	u32			errata;
-+	u8			wakeups_enabled;
-+
-+	struct pm_qos_request	pm_qos_request;
-+	u32			latency;
-+	u32			calc_latency;
-+	struct work_struct	qos_work;
- };
- 
- #endif /* __OMAP_SERIAL_H__ */
-diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
-index b9e8588..0d818ac 100644
---- a/arch/arm/plat-omap/include/plat/omap34xx.h
-+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
-@@ -35,6 +35,8 @@
- #define L4_EMU_34XX_BASE	0x54000000
- #define L3_34XX_BASE		0x68000000
- 
-+#define L4_WK_AM33XX_BASE	0x44C00000
-+
- #define OMAP3430_32KSYNCT_BASE	0x48320000
- #define OMAP3430_CM_BASE	0x48004800
- #define OMAP3430_PRM_BASE	0x48306800
-diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
-index ea2b8a6..c0d478e 100644
---- a/arch/arm/plat-omap/include/plat/omap44xx.h
-+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
-@@ -45,6 +45,7 @@
- #define OMAP44XX_WKUPGEN_BASE		0x48281000
- #define OMAP44XX_MCPDM_BASE		0x40132000
- #define OMAP44XX_MCPDM_L3_BASE		0x49032000
-+#define OMAP44XX_SAR_RAM_BASE		0x4a326000
- 
- #define OMAP44XX_MAILBOX_BASE		(L4_44XX_BASE + 0xF4000)
- #define OMAP44XX_HSUSB_OTG_BASE		(L4_44XX_BASE + 0xAB000)
-diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
-index 51423d2..71aa35d 100644
---- a/arch/arm/plat-omap/include/plat/omap_device.h
-+++ b/arch/arm/plat-omap/include/plat/omap_device.h
-@@ -100,6 +100,13 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
- 					 struct omap_device_pm_latency *pm_lats,
- 					 int pm_lats_cnt, int is_early_device);
- 
-+struct omap_device *omap_device_alloc(struct platform_device *pdev,
-+				      struct omap_hwmod **ohs, int oh_cnt,
-+				      struct omap_device_pm_latency *pm_lats,
-+				      int pm_lats_cnt);
-+void omap_device_delete(struct omap_device *od);
-+int omap_device_register(struct platform_device *pdev);
-+
- void __iomem *omap_device_get_rt_va(struct omap_device *od);
- struct device *omap_device_get_by_hwmod_name(const char *oh_name);
- 
-@@ -116,6 +123,7 @@ int omap_device_enable_hwmods(struct omap_device *od);
- 
- int omap_device_disable_clocks(struct omap_device *od);
- int omap_device_enable_clocks(struct omap_device *od);
-+int omap_device_reset(struct device *dev);
- 
- /*
-  * Entries should be kept in latency order ascending
-diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
-index 8b372ed..a3b8b5c 100644
---- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
-+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
-@@ -41,6 +41,8 @@ struct omap_device;
- 
- extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
- extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
-+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
-+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4;
- 
- /*
-  * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
-@@ -70,6 +72,32 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
- #define SYSC_TYPE2_MIDLEMODE_SHIFT	4
- #define SYSC_TYPE2_MIDLEMODE_MASK	(0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
- 
-+/*
-+ * OCP SYSCONFIG bit shifts/masks TYPE3.
-+ * This is applicable for some IPs present in AM33XX
-+ */
-+#define SYSC_TYPE3_SIDLEMODE_SHIFT	0
-+#define SYSC_TYPE3_SIDLEMODE_MASK	(0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
-+#define SYSC_TYPE3_MIDLEMODE_SHIFT	2
-+#define SYSC_TYPE3_MIDLEMODE_MASK	(0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
-+
-+/*
-+ * OCP SYSCONFIG bit shifts/masks TYPE4.
-+ * This is applicable for some IPs present in AM33XX
-+ */
-+#define SYSC_TYPE4_CLOCKACTIVITY_SHIFT	8
-+#define SYSC_TYPE4_CLOCKACTIVITY_MASK	(0x3 << SYSC_CLOCKACTIVITY_SHIFT)
-+#define SYSC_TYPE4_MIDLEMODE_SHIFT	5
-+#define SYSC_TYPE4_MIDLEMODE_MASK	(0x3 << SYSC_MIDLEMODE_SHIFT)
-+#define SYSC_TYPE4_SIDLEMODE_SHIFT	3
-+#define SYSC_TYPE4_SIDLEMODE_MASK	(0x3 << SYSC_SIDLEMODE_SHIFT)
-+#define SYSC_TYPE4_ENAWAKEUP_SHIFT	2
-+#define SYSC_TYPE4_ENAWAKEUP_MASK	(1 << SYSC_ENAWAKEUP_SHIFT)
-+#define SYSC_TYPE4_SOFTRESET_SHIFT	1
-+#define SYSC_TYPE4_SOFTRESET_MASK	(1 << SYSC_SOFTRESET_SHIFT)
-+#define SYSC_TYPE4_AUTOIDLE_SHIFT	0
-+#define SYSC_TYPE4_AUTOIDLE_MASK	(1 << SYSC_AUTOIDLE_SHIFT)
-+
- /* OCP SYSSTATUS bit shifts/masks */
- #define SYSS_RESETDONE_SHIFT		0
- #define SYSS_RESETDONE_MASK		(1 << SYSS_RESETDONE_SHIFT)
-@@ -97,6 +125,7 @@ struct omap_hwmod_mux_info {
- 	struct omap_device_pad		*pads;
- 	int				nr_pads_dynamic;
- 	struct omap_device_pad		**pads_dynamic;
-+	int				*irqs;
- 	bool				enabled;
- };
- 
-@@ -416,10 +445,13 @@ struct omap_hwmod_omap4_prcm {
-  * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
-  * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
-  * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
-+ * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
-+ *     causes the first call to _enable() to only update the pinmux
-  */
- #define _HWMOD_NO_MPU_PORT			(1 << 0)
- #define _HWMOD_WAKEUP_ENABLED			(1 << 1)
- #define _HWMOD_SYSCONFIG_LOADED			(1 << 2)
-+#define _HWMOD_SKIP_ENABLE			(1 << 3)
- 
- /*
-  * omap_hwmod._state definitions
-@@ -565,6 +597,7 @@ int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
- int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
- int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
- 
-+int omap_hwmod_set_master_standbymode(struct omap_hwmod *oh, u8 idlemode);
- int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
- int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
- 
-@@ -604,6 +637,8 @@ int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
- 
- int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
- 
-+int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
-+
- /*
-  * Chip variant-specific hwmod init routines - XXX should be converted
-  * to use initcalls once the initial boot ordering is straightened out
-@@ -612,5 +647,6 @@ extern int omap2420_hwmod_init(void);
- extern int omap2430_hwmod_init(void);
- extern int omap3xxx_hwmod_init(void);
- extern int omap44xx_hwmod_init(void);
-+extern int am33xx_hwmod_init(void);
- 
- #endif
-diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
-index 1ab9fd6..d15ddb2 100644
---- a/arch/arm/plat-omap/include/plat/serial.h
-+++ b/arch/arm/plat-omap/include/plat/serial.h
-@@ -44,6 +44,7 @@
- #define OMAP3_UART2_BASE	OMAP2_UART2_BASE
- #define OMAP3_UART3_BASE	0x49020000
- #define OMAP3_UART4_BASE	0x49042000	/* Only on 36xx */
-+#define OMAP3_UART4_AM35XX_BASE	0x4809E000	/* Only on AM35xx */
- 
- /* OMAP4 serial ports */
- #define OMAP4_UART1_BASE	OMAP2_UART1_BASE
-@@ -51,14 +52,22 @@
- #define OMAP4_UART3_BASE	0x48020000
- #define OMAP4_UART4_BASE	0x4806e000
- 
--/* TI816X serial ports */
--#define TI816X_UART1_BASE	0x48020000
--#define TI816X_UART2_BASE	0x48022000
--#define TI816X_UART3_BASE	0x48024000
-+/* TI81XX serial ports */
-+#define TI81XX_UART1_BASE	0x48020000
-+#define TI81XX_UART2_BASE	0x48022000
-+#define TI81XX_UART3_BASE	0x48024000
- 
- /* AM3505/3517 UART4 */
- #define AM35XX_UART4_BASE	0x4809E000	/* Only on AM3505/3517 */
- 
-+/* AM33XX serial port */
-+#define AM33XX_UART1_BASE	0x44E09000
-+#define AM33XX_UART2_BASE	0x48022000
-+#define AM33XX_UART3_BASE	0x48024000
-+#define AM33XX_UART4_BASE	0x481A6000
-+#define AM33XX_UART5_BASE	0x481A8000
-+#define AM33XX_UART6_BASE	0x481AA000
-+
- /* External port on Zoom2/3 */
- #define ZOOM_UART_BASE		0x10000000
- #define ZOOM_UART_VIRT		0xfa400000
-@@ -89,9 +98,11 @@
- #define OMAP4UART2		OMAP2UART2
- #define OMAP4UART3		43
- #define OMAP4UART4		44
--#define TI816XUART1		81
--#define TI816XUART2		82
--#define TI816XUART3		83
-+#define TI81XXUART1		81
-+#define TI81XXUART2		82
-+#define TI81XXUART3		83
-+#define AM33XXUART1		84
-+#define AM33XXUART4		85
- #define ZOOM_UART		95		/* Only on zoom2/3 */
- 
- /* This is only used by 8250.c for omap1510 */
-@@ -106,15 +117,13 @@
- #ifndef __ASSEMBLER__
- 
- struct omap_board_data;
-+struct omap_uart_port_info;
- 
- extern void omap_serial_init(void);
--extern void omap_serial_init_port(struct omap_board_data *bdata);
- extern int omap_uart_can_sleep(void);
--extern void omap_uart_check_wakeup(void);
--extern void omap_uart_prepare_suspend(void);
--extern void omap_uart_prepare_idle(int num);
--extern void omap_uart_resume_idle(int num);
--extern void omap_uart_enable_irqs(int enable);
-+extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
-+extern void omap_serial_init_port(struct omap_board_data *bdata,
-+		struct omap_uart_port_info *platform_data);
- #endif
- 
- #endif
-diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
-index f500fc3..4558416 100644
---- a/arch/arm/plat-omap/include/plat/sram.h
-+++ b/arch/arm/plat-omap/include/plat/sram.h
-@@ -12,17 +12,24 @@
- #define __ARCH_ARM_OMAP_SRAM_H
- 
- #ifndef __ASSEMBLY__
-+#include <linux/slab.h>
-+#include <linux/genalloc.h>
- #include <asm/fncpy.h>
- 
--extern void *omap_sram_push_address(unsigned long size);
-+extern struct gen_pool *omap_gen_pool;
- 
--/* Macro to push a function to the internal SRAM, using the fncpy API */
--#define omap_sram_push(funcp, size) ({				\
--	typeof(&(funcp)) _res = NULL;				\
--	void *_sram_address = omap_sram_push_address(size);	\
--	if (_sram_address)					\
--		_res = fncpy(_sram_address, &(funcp), size);	\
--	_res;							\
-+/*
-+ * Note that fncpy requires the SRAM address to be aligned to an 8-byte
-+ * boundary, so the min_alloc_order for the pool is set appropriately.
-+ */
-+#define omap_sram_push(funcp, size) ({					\
-+	typeof(&(funcp)) _res;						\
-+	size_t _sz = size;						\
-+	void *_sram = (void *) gen_pool_alloc(omap_gen_pool, _sz);	\
-+	_res = (_sram ? fncpy(_sram, &(funcp), _sz) : NULL);		\
-+	if (!_res)							\
-+		pr_err("Not enough space in SRAM\n");			\
-+	_res;								\
- })
- 
- extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
-@@ -82,8 +89,10 @@ extern u32 omap3_sram_configure_core_dpll(
- extern unsigned long omap3_sram_configure_core_dpll_sz;
- 
- #ifdef CONFIG_PM
-+extern void am33xx_push_sram_idle(void);
- extern void omap_push_sram_idle(void);
- #else
-+static inline void am33xx_push_sram_idle(void) {}
- static inline void omap_push_sram_idle(void) {}
- #endif /* CONFIG_PM */
- 
-@@ -95,6 +104,11 @@ static inline void omap_push_sram_idle(void) {}
-  */
- #define OMAP2_SRAM_PA		0x40200000
- #define OMAP3_SRAM_PA           0x40200000
-+#ifdef CONFIG_OMAP4_ERRATA_I688
-+#define OMAP4_SRAM_PA		0x40304000
-+#define OMAP4_SRAM_VA		0xfe404000
-+#else
- #define OMAP4_SRAM_PA		0x40300000
--
-+#endif
-+#define AM33XX_SRAM_PA		0x40300000
- #endif
-diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h
-deleted file mode 100644
-index 50510f5..0000000
---- a/arch/arm/plat-omap/include/plat/ti816x.h
-+++ /dev/null
-@@ -1,27 +0,0 @@
--/*
-- * This file contains the address data for various TI816X modules.
-- *
-- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation version 2.
-- *
-- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-- * kind, whether express or implied; without even the implied warranty
-- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- */
--
--#ifndef __ASM_ARCH_TI816X_H
--#define __ASM_ARCH_TI816X_H
--
--#define L4_SLOW_TI816X_BASE	0x48000000
--
--#define TI816X_SCM_BASE		0x48140000
--#define TI816X_CTRL_BASE	TI816X_SCM_BASE
--#define TI816X_PRCM_BASE	0x48180000
--
--#define TI816X_ARM_INTC_BASE	0x48200000
--
--#endif /* __ASM_ARCH_TI816X_H */
-diff --git a/arch/arm/plat-omap/include/plat/ti81xx.h b/arch/arm/plat-omap/include/plat/ti81xx.h
-new file mode 100644
-index 0000000..8f9843f
---- /dev/null
-+++ b/arch/arm/plat-omap/include/plat/ti81xx.h
-@@ -0,0 +1,27 @@
-+/*
-+ * This file contains the address data for various TI81XX modules.
-+ *
-+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __ASM_ARCH_TI81XX_H
-+#define __ASM_ARCH_TI81XX_H
-+
-+#define L4_SLOW_TI81XX_BASE	0x48000000
-+
-+#define TI81XX_SCM_BASE		0x48140000
-+#define TI81XX_CTRL_BASE	TI81XX_SCM_BASE
-+#define TI81XX_PRCM_BASE	0x48180000
-+
-+#define TI81XX_ARM_INTC_BASE	0x48200000
-+
-+#endif /* __ASM_ARCH_TI81XX_H */
-diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
-index 2f472e9..8686776 100644
---- a/arch/arm/plat-omap/include/plat/uncompress.h
-+++ b/arch/arm/plat-omap/include/plat/uncompress.h
-@@ -99,9 +99,13 @@ static inline void flush(void)
- #define DEBUG_LL_ZOOM(mach)						\
- 	_DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
- 
--#define DEBUG_LL_TI816X(p, mach)					\
--	_DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT,	\
--		TI816XUART##p)
-+#define DEBUG_LL_TI81XX(p, mach)					\
-+	_DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,	\
-+		TI81XXUART##p)
-+
-+#define DEBUG_LL_AM33XX(p, mach)					\
-+	_DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,	\
-+		AM33XXUART##p)
- 
- static inline void __arch_decomp_setup(unsigned long arch_id)
- {
-@@ -157,6 +161,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
- 		DEBUG_LL_OMAP3(3, cm_t3730);
- 		DEBUG_LL_OMAP3(3, craneboard);
- 		DEBUG_LL_OMAP3(3, devkit8000);
-+		DEBUG_LL_OMAP3(3, encore);
- 		DEBUG_LL_OMAP3(3, igep0020);
- 		DEBUG_LL_OMAP3(3, igep0030);
- 		DEBUG_LL_OMAP3(3, nokia_rm680);
-@@ -171,14 +176,23 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
- 		/* omap4 based boards using UART3 */
- 		DEBUG_LL_OMAP4(3, omap_4430sdp);
- 		DEBUG_LL_OMAP4(3, omap4_panda);
-+		DEBUG_LL_OMAP4(3, pcm049);
- 
- 		/* zoom2/3 external uart */
- 		DEBUG_LL_ZOOM(omap_zoom2);
- 		DEBUG_LL_ZOOM(omap_zoom3);
- 
- 		/* TI8168 base boards using UART3 */
--		DEBUG_LL_TI816X(3, ti8168evm);
-+		DEBUG_LL_TI81XX(3, ti8168evm);
-+
-+		/* TI8148 base boards using UART1 */
-+		DEBUG_LL_TI81XX(1, ti8148evm);
-+
-+		/* AM33XX base boards using UART1 */
-+		DEBUG_LL_AM33XX(1, am335xevm);
- 
-+		/* AM33XX IA boards using UART4 */
-+		DEBUG_LL_AM33XX(4, am335xiaevm);
- 	} while (0);
- }
- 
-diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
-index 17d3c93..9158f5e 100644
---- a/arch/arm/plat-omap/include/plat/usb.h
-+++ b/arch/arm/plat-omap/include/plat/usb.h
-@@ -88,7 +88,8 @@ struct omap_musb_board_data {
- 	u8	mode;
- 	u16	power;
- 	unsigned extvbus:1;
--	void	(*set_phy_power)(u8 on);
-+	u8	instances;
-+	void	(*set_phy_power)(u8 id, u8 on);
- 	void	(*clear_irq)(void);
- 	void	(*set_mode)(u8 mode);
- 	void	(*reset)(void);
-@@ -100,9 +101,6 @@ extern void usb_musb_init(struct omap_musb_board_data *board_data);
- 
- extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
- 
--extern int omap_usbhs_enable(struct device *dev);
--extern void omap_usbhs_disable(struct device *dev);
--
- extern int omap4430_phy_power(struct device *dev, int ID, int on);
- extern int omap4430_phy_set_clk(struct device *dev, int on);
- extern int omap4430_phy_init(struct device *dev);
-@@ -111,9 +109,10 @@ extern int omap4430_phy_suspend(struct device *dev, int suspend);
- #endif
- 
- extern void am35x_musb_reset(void);
--extern void am35x_musb_phy_power(u8 on);
-+extern void am35x_musb_phy_power(u8 id, u8 on);
- extern void am35x_musb_clear_irq(void);
- extern void am35x_set_mode(u8 musb_mode);
-+extern void ti81xx_musb_phy_power(u8 id, u8 on);
- 
- /*
-  * FIXME correct answer depends on hmc_mode,
-@@ -273,6 +272,46 @@ static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
- #define CONF2_OTGPWRDN		(1 << 2)
- #define CONF2_DATPOL		(1 << 1)
- 
-+/* TI81XX specific definitions */
-+#define USBCTRL0	0x620
-+#define USBSTAT0	0x624
-+#define USBCTRL1	0x628
-+#define USBSTAT1	0x62c
-+
-+/* TI816X PHY controls bits */
-+#define TI816X_USBPHY0_NORMAL_MODE	(1 << 0)
-+#define TI816X_USBPHY1_NORMAL_MODE	(1 << 1)
-+#define TI816X_USBPHY_REFCLK_OSC	(1 << 8)
-+
-+/* TI814X PHY controls bits */
-+#define USBPHY_CM_PWRDN		(1 << 0)
-+#define USBPHY_OTG_PWRDN	(1 << 1)
-+#define USBPHY_CHGDET_DIS	(1 << 2)
-+#define USBPHY_CHGDET_RSTRT	(1 << 3)
-+#define USBPHY_SRCONDM		(1 << 4)
-+#define USBPHY_SINKONDP		(1 << 5)
-+#define USBPHY_CHGISINK_EN	(1 << 6)
-+#define USBPHY_CHGVSRC_EN	(1 << 7)
-+#define USBPHY_DMPULLUP		(1 << 8)
-+#define USBPHY_DPPULLUP		(1 << 9)
-+#define USBPHY_CDET_EXTCTL	(1 << 10)
-+#define USBPHY_GPIO_MODE	(1 << 12)
-+#define USBPHY_DPGPIO_PD	(1 << 17)
-+#define USBPHY_DMGPIO_PD	(1 << 18)
-+#define USBPHY_OTGVDET_EN	(1 << 19)
-+#define USBPHY_OTGSESSEND_EN	(1 << 20)
-+#define USBPHY_DATA_POLARITY	(1 << 23)
-+
-+/* TI81XX only PHY bits */
-+#define TI81XX_USBPHY_DPOPBUFCTL	(1 << 13)
-+#define TI81XX_USBPHY_DMOPBUFCTL	(1 << 14)
-+#define TI81XX_USBPHY_DPINPUT		(1 << 15)
-+#define TI81XX_USBPHY_DMINPUT		(1 << 16)
-+
-+/* AM335X only PHY bits */
-+#define AM335X_USBPHY_GPIO_SIG_INV     (1 << 13)
-+#define AM335X_USBPHY_GPIO_SIG_CROSS   (1 << 14)
-+
- #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
- u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
- u32 omap1_usb1_init(unsigned nwires);
-@@ -293,4 +332,49 @@ static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
- }
- #endif
- 
-+/* DMA registers */
-+#define TI81XX_USB_AUTOREQ_REG	0xd0
-+#define TI81XX_USB_TEARDOWN_REG	0xd8
-+#define USB_AUTOREQ_REG		0x14
-+#define USB_TEARDOWN_REG	0x1c
-+#define MOP_SOP_INTR_ENABLE	0x64
-+/* 0x68-0x6c Reserved */
-+#define USB_TX_MODE_REG		0x70	/* Transparent, CDC, [Generic] RNDIS */
-+#define USB_RX_MODE_REG		0x74	/* Transparent, CDC, [Generic] RNDIS */
-+#define EP_COUNT_MODE_REG	0x78
-+#define USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x80 + (((n) - 1) << 2))
-+
-+#define QUEUE_THRESHOLD_INTR_ENABLE_REG	0xc0
-+#define	QUEUE_63_THRESHOLD_REG	0xc4
-+#define QUEUE_63_THRESHOLD_INTR_CLEAR_REG 0xc8
-+#define	QUEUE_65_THRESHOLD_REG	0xd4
-+#define QUEUE_65_THRESHOLD_INTR_CLEAR_REG 0xd8
-+
-+/* Mode register bits */
-+#define USB_MODE_SHIFT(n)	((((n) - 1) << 1))
-+#define USB_MODE_MASK(n)	(3 << USB_MODE_SHIFT(n))
-+#define USB_RX_MODE_SHIFT(n)	USB_MODE_SHIFT(n)
-+#define USB_TX_MODE_SHIFT(n)	USB_MODE_SHIFT(n)
-+#define USB_RX_MODE_MASK(n)	USB_MODE_MASK(n)
-+#define USB_TX_MODE_MASK(n)	USB_MODE_MASK(n)
-+#define USB_TRANSPARENT_MODE	0
-+#define USB_RNDIS_MODE		1
-+#define USB_CDC_MODE		2
-+#define USB_GENERIC_RNDIS_MODE	3
-+
-+/* AutoReq register bits */
-+#define USB_RX_AUTOREQ_SHIFT(n) (((n) - 1) << 1)
-+#define USB_RX_AUTOREQ_MASK(n)	(3 << USB_RX_AUTOREQ_SHIFT(n))
-+#define USB_NO_AUTOREQ		0
-+#define USB_AUTOREQ_ALL_BUT_EOP 1
-+#define USB_AUTOREQ_ALWAYS	3
-+
-+/* Teardown register bits */
-+#define USB_TX_TDOWN_SHIFT(n)	(16 + (n))
-+#define USB_TX_TDOWN_MASK(n)	(1 << USB_TX_TDOWN_SHIFT(n))
-+#define USB_RX_TDOWN_SHIFT(n)	(n)
-+#define USB_RX_TDOWN_MASK(n)	(1 << USB_RX_TDOWN_SHIFT(n))
-+
-+#define USB_CPPI41_NUM_CH	15
-+
- #endif	/* __ASM_ARCH_OMAP_USB_H */
-diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
-deleted file mode 100644
-index 333871f..0000000
---- a/arch/arm/plat-omap/io.c
-+++ /dev/null
-@@ -1,159 +0,0 @@
--/*
-- * Common io.c file
-- * This file is created by Russell King <rmk+kernel@arm.linux.org.uk>
-- *
-- * Copyright (C) 2009 Texas Instruments
-- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--#include <linux/module.h>
--#include <linux/io.h>
--#include <linux/mm.h>
--#include <linux/dma-mapping.h>
--
--#include <plat/omap7xx.h>
--#include <plat/omap1510.h>
--#include <plat/omap16xx.h>
--#include <plat/omap24xx.h>
--#include <plat/omap34xx.h>
--#include <plat/omap44xx.h>
--
--#define BETWEEN(p,st,sz)	((p) >= (st) && (p) < ((st) + (sz)))
--#define XLATE(p,pst,vst)	((void __iomem *)((p) - (pst) + (vst)))
--
--static int initialized;
--
--/*
-- * Intercept ioremap() requests for addresses in our fixed mapping regions.
-- */
--void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
--{
--
--	WARN(!initialized, "Do not use ioremap before init_early\n");
--
--#ifdef CONFIG_ARCH_OMAP1
--	if (cpu_class_is_omap1()) {
--		if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
--			return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
--	}
--	if (cpu_is_omap7xx()) {
--		if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
--			return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
--
--		if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
--			return XLATE(p, OMAP7XX_DSPREG_BASE,
--					OMAP7XX_DSPREG_START);
--	}
--	if (cpu_is_omap15xx()) {
--		if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
--			return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);
--
--		if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
--			return XLATE(p, OMAP1510_DSPREG_BASE,
--					OMAP1510_DSPREG_START);
--	}
--	if (cpu_is_omap16xx()) {
--		if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
--			return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);
--
--		if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
--			return XLATE(p, OMAP16XX_DSPREG_BASE,
--					OMAP16XX_DSPREG_START);
--	}
--#endif
--#ifdef CONFIG_ARCH_OMAP2
--	if (cpu_is_omap24xx()) {
--		if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
--			return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
--		if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
--			return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
--	}
--	if (cpu_is_omap2420()) {
--		if (BETWEEN(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_SIZE))
--			return XLATE(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_VIRT);
--		if (BETWEEN(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE))
--			return XLATE(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE);
--		if (BETWEEN(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_SIZE))
--			return XLATE(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_VIRT);
--	}
--	if (cpu_is_omap2430()) {
--		if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
--			return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
--		if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
--			return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
--		if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
--			return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
--		if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
--			return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
--	}
--#endif
--#ifdef CONFIG_ARCH_OMAP3
--	if (cpu_is_ti816x()) {
--		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
--			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
--	} else if (cpu_is_omap34xx()) {
--		if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
--			return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
--		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
--			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
--		if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
--			return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
--		if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
--			return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
--		if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
--			return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
--		if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
--			return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
--		if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
--			return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
--	}
--#endif
--#ifdef CONFIG_ARCH_OMAP4
--	if (cpu_is_omap44xx()) {
--		if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE))
--			return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
--		if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
--			return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
--		if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
--			return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
--		if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE))
--			return XLATE(p, OMAP44XX_EMIF1_PHYS,		\
--							OMAP44XX_EMIF1_VIRT);
--		if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE))
--			return XLATE(p, OMAP44XX_EMIF2_PHYS,		\
--							OMAP44XX_EMIF2_VIRT);
--		if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE))
--			return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT);
--		if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
--			return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
--		if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
--			return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
--	}
--#endif
--	return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
--}
--EXPORT_SYMBOL(omap_ioremap);
--
--void omap_iounmap(volatile void __iomem *addr)
--{
--	unsigned long virt = (unsigned long)addr;
--
--	if (virt >= VMALLOC_START && virt < VMALLOC_END)
--		__iounmap(addr);
--}
--EXPORT_SYMBOL(omap_iounmap);
--
--void __init omap_init_consistent_dma_size(void)
--{
--#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
--	init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
--#endif
--}
--
--void __init omap_ioremap_init(void)
--{
--	initialized++;
--}
-diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
-index ad80112..c2d550b27 100644
---- a/arch/arm/plat-omap/mailbox.c
-+++ b/arch/arm/plat-omap/mailbox.c
-@@ -59,6 +59,14 @@ static inline int mbox_fifo_full(struct omap_mbox *mbox)
- {
- 	return mbox->ops->fifo_full(mbox);
- }
-+static inline int mbox_fifo_needs_flush(struct omap_mbox *mbox)
-+{
-+	return mbox->ops->fifo_needs_flush(mbox);
-+}
-+static inline mbox_msg_t mbox_fifo_readback(struct omap_mbox *mbox)
-+{
-+	return mbox->ops->fifo_readback(mbox);
-+}
- 
- /* Mailbox IRQ handle functions */
- static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-@@ -116,6 +124,28 @@ out:
- }
- EXPORT_SYMBOL(omap_mbox_msg_send);
- 
-+/*
-+ * Flush the Rx FIFO by reading back the messages
-+ * Since the normal expectation is that the Rx will do the
-+ * reading, add a debug message to indicate if we really flush
-+ * returns the no. of messages read back
-+ */
-+int omap_mbox_msg_rx_flush(struct omap_mbox *mbox)
-+{
-+	int ret = 0;
-+	mbox_msg_t msg;
-+
-+	while (!mbox_fifo_needs_flush(mbox)) {
-+		ret++;
-+		msg = mbox_fifo_readback(mbox);
-+	}
-+	if (ret)
-+		pr_debug("Flushed %s Rx FIFO via %d readbacks\n", mbox->name, ret);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(omap_mbox_msg_rx_flush);
-+
- static void mbox_tx_tasklet(unsigned long tx_data)
- {
- 	struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
-diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
-index e8d9869..3733877 100644
---- a/arch/arm/plat-omap/omap_device.c
-+++ b/arch/arm/plat-omap/omap_device.c
-@@ -97,14 +97,7 @@
- #define USE_WAKEUP_LAT			0
- #define IGNORE_WAKEUP_LAT		1
- 
--static int omap_device_register(struct platform_device *pdev);
- static int omap_early_device_register(struct platform_device *pdev);
--static struct omap_device *omap_device_alloc(struct platform_device *pdev,
--				      struct omap_hwmod **ohs, int oh_cnt,
--				      struct omap_device_pm_latency *pm_lats,
--				      int pm_lats_cnt);
--static void omap_device_delete(struct omap_device *od);
--
- 
- static struct omap_device_pm_latency omap_default_latency[] = {
- 	{
-@@ -509,7 +502,7 @@ static int omap_device_fill_resources(struct omap_device *od,
-  *
-  * Returns an struct omap_device pointer or ERR_PTR() on error;
-  */
--static struct omap_device *omap_device_alloc(struct platform_device *pdev,
-+struct omap_device *omap_device_alloc(struct platform_device *pdev,
- 					struct omap_hwmod **ohs, int oh_cnt,
- 					struct omap_device_pm_latency *pm_lats,
- 					int pm_lats_cnt)
-@@ -591,7 +584,7 @@ oda_exit1:
- 	return ERR_PTR(ret);
- }
- 
--static void omap_device_delete(struct omap_device *od)
-+void omap_device_delete(struct omap_device *od)
- {
- 	if (!od)
- 		return;
-@@ -817,7 +810,7 @@ static struct dev_pm_domain omap_device_pm_domain = {
-  * platform_device_register() on the underlying platform_device.
-  * Returns the return value of platform_device_register().
-  */
--static int omap_device_register(struct platform_device *pdev)
-+int omap_device_register(struct platform_device *pdev)
- {
- 	pr_debug("omap_device: %s: registering\n", pdev->name);
- 
-@@ -1130,6 +1123,28 @@ int omap_device_enable_clocks(struct omap_device *od)
- 	return 0;
- }
- 
-+/**
-+ * omap_device_reset - reset the module.
-+ * @dev: struct device *
-+ *
-+ * Reset all the hwmods associated with the device @dev.
-+ */
-+int omap_device_reset(struct device *dev)
-+{
-+	int r = 0;
-+	int i;
-+	struct platform_device *pdev = to_platform_device(dev);
-+	struct omap_device *odev = to_omap_device(pdev);
-+	struct omap_hwmod *oh;
-+
-+	for (i = 0; i < odev->hwmods_cnt; i++) {
-+		oh = odev->hwmods[i];
-+		r |= omap_hwmod_reset(oh);
-+	}
-+	return r;
-+}
-+
-+
- struct device omap_device_parent = {
- 	.init_name	= "omap",
- 	.parent         = &platform_bus,
-diff --git a/arch/arm/plat-omap/sdma2edma.c b/arch/arm/plat-omap/sdma2edma.c
-new file mode 100644
-index 0000000..c3c3a1e
---- /dev/null
-+++ b/arch/arm/plat-omap/sdma2edma.c
-@@ -0,0 +1,359 @@
-+/*
-+ * sdma2edma.c
-+ *
-+ * SDMA to EDMA3 Wrapper.
-+ *
-+ * NOTE: Since we are invoking EDMA API, comments for all APIs in this file
-+ * are EDMA specific.
-+ *
-+ * Copyright (C) 2010-2011 Texas Instruments.
-+ * Author: Mansoor Ahamed <mansoor.ahamed@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/spinlock.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/io.h>
-+
-+#include <asm/system.h>
-+#include <mach/hardware.h>
-+#include <plat/dma.h>
-+#include <plat/tc.h>
-+
-+/* some edma specific hacks which might change */
-+#include <mach/edma.h>
-+
-+/**
-+ * omap_request_dma - allocate DMA channel and paired parameter RAM
-+ * @dev_id: specific channel to allocate; negative for "any unmapped channel"
-+ * @callback: optional; to be issued on DMA completion or errors
-+ * @data: passed to callback
-+ * @dma_ch_out: allocated channel number returned in this variable
-+ *
-+ * This allocates a DMA channel and its associated parameter RAM slot.
-+ * The parameter RAM is initialized to hold a dummy transfer.
-+ *
-+ * Normal use is to pass a specific channel number as @channel, to make
-+ * use of hardware events mapped to that channel.  When the channel will
-+ * be used only for software triggering or event chaining, channels not
-+ * mapped to hardware events (or mapped to unused events) are preferable.
-+ *
-+ * DMA transfers start from a channel using edma_start(), or by
-+ * chaining.  When the transfer described in that channel's parameter RAM
-+ * slot completes, that slot's data may be reloaded through a link.
-+ *
-+ * DMA errors are only reported to the @callback associated with the
-+ * channel driving that transfer, but transfer completion callbacks can
-+ * be sent to another channel under control of the TCC field in
-+ * the option word of the transfer's parameter RAM set.  Drivers must not
-+ * use DMA transfer completion callbacks for channels they did not allocate.
-+ * (The same applies to TCC codes used in transfer chaining.)
-+ *
-+ * TODO: -
-+ * . In the edma call, last param i.e TC hard coded to EVENTQ_2
-+ * . The callback's ch_status which should be used in McSPI driver
-+ *   to stop/clean EDMA is currently ignored in some driver (eg. McSPI)
-+ */
-+int omap_request_dma(int dev_id, const char *dev_name,
-+		void (*callback)(int lch, u16 ch_status, void *data),
-+		void *data, int *dma_ch_out)
-+{
-+	struct edmacc_param p_ram;
-+	typedef void (*EDMA_CALLBACK)(unsigned, u16, void*);
-+	EDMA_CALLBACK edma_callback = (EDMA_CALLBACK)(callback);
-+
-+	*dma_ch_out = edma_alloc_channel(dev_id, edma_callback, data, EVENTQ_2);
-+	if (*dma_ch_out < 0)
-+		return -1;
-+
-+	/* enable interrupts */
-+	edma_read_slot(*dma_ch_out, &p_ram);
-+	p_ram.opt |= TCINTEN | EDMA_TCC(EDMA_CHAN_SLOT(*dma_ch_out));
-+	edma_write_slot(*dma_ch_out, &p_ram);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(omap_request_dma);
-+
-+/**
-+ * omap_free_dma - deallocate DMA channel
-+ * @lch: dma channel returned from edma_alloc_channel()
-+ *
-+ * This deallocates the DMA channel and associated parameter RAM slot
-+ * allocated by omap_request_dma().
-+ *
-+ * Callers are responsible for ensuring the channel is inactive, and
-+ * will not be reactivated by linking, chaining, or software calls to
-+ * omap_start_dma().
-+ */
-+void omap_free_dma(int lch)
-+{
-+	edma_free_channel((unsigned)lch);
-+}
-+EXPORT_SYMBOL(omap_free_dma);
-+
-+/**
-+ * omap_start_dma - start dma on a channel
-+ * @lch: channel being activated
-+ *
-+ * Channels with event associations will be triggered by their hardware
-+ * events, and channels without such associations will be triggered by
-+ * software.  (At this writing there is no interface for using software
-+ * triggers except with channels that don't support hardware triggers.)
-+ *
-+ */
-+void omap_start_dma(int lch)
-+{
-+	edma_start((unsigned)lch);
-+}
-+EXPORT_SYMBOL(omap_start_dma);
-+
-+/**
-+ * omap_stop_dma - stops dma on the channel passed
-+ * @lch: channel being deactivated
-+ *
-+ * When @lch is a channel, any active transfer is paused and
-+ * all pending hardware events are cleared.  The current transfer
-+ * may not be resumed, and the channel's Parameter RAM should be
-+ * reinitialized before being reused.
-+ */
-+void omap_stop_dma(int lch)
-+{
-+	edma_stop((unsigned)lch);
-+}
-+EXPORT_SYMBOL(omap_stop_dma);
-+
-+/**
-+ * omap_cleanup_dma - Bring back DMA to initial state
-+ * @lch: channel being cleaned up
-+ *
-+ * It cleans ParamEntry and bring back EDMA to initial state if media has
-+ * been removed before EDMA has finished.It is usedful for removable media.
-+ *
-+ *
-+ * FIXME this should not be needed ... edma_stop() should suffice.
-+ *
-+ */
-+void omap_cleanup_dma(int lch)
-+{
-+	edma_clean_channel((unsigned)lch);
-+}
-+EXPORT_SYMBOL(omap_cleanup_dma);
-+
-+/**
-+ * omap_set_dma_transfer_params - configure DMA transfer parameters
-+ * @lch: parameter RAM slot being configured
-+ * @data_type: how many bytes per array (at least one)
-+ * @elem_count: how many arrays per frame (at least one)
-+ * @frame_count: how many frames per block (at least one)
-+ * @sync_mode: ASYNC or ABSYNC
-+ * @dma_trigger: device id (not used)
-+ * @src_or_dst_synch: not used
-+ *
-+ * See the EDMA3 documentation to understand how to configure and link
-+ * transfers using the fields in PaRAM slots.  If you are not doing it
-+ * all at once with edma_write_slot(), you will use this routine
-+ * plus two calls each for source and destination, setting the initial
-+ * address and saying how to index that address.
-+ *
-+ * An example of an A-Synchronized transfer is a serial link using a
-+ * single word shift register.  In that case, @acnt would be equal to
-+ * that word size; the serial controller issues a DMA synchronization
-+ * event to transfer each word, and memory access by the DMA transfer
-+ * controller will be word-at-a-time.
-+ *
-+ * An example of an AB-Synchronized transfer is a device using a FIFO.
-+ * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
-+ * The controller with the FIFO issues DMA synchronization events when
-+ * the FIFO threshold is reached, and the DMA transfer controller will
-+ * transfer one frame to (or from) the FIFO.  It will probably use
-+ * efficient burst modes to access memory.
-+ *
-+ * . dma_trigger and channel number, this is ignored for EDMA
-+ * . Setting bcnt_rld same as bcnt
-+ * TODO
-+ * . what is src_or_dst_synch?
-+ */
-+void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
-+			int frame_count, int sync_mode,
-+			int dma_trigger, int src_or_dst_synch)
-+{
-+	int d_type[3] = {1, 2, 4};
-+	if ((enum sync_dimension)sync_mode > ABSYNC) {
-+		printk(KERN_ERR "SDMA2EDMA: Line:%d : Param \'sync_mode\' out"
-+				" of range\n", __LINE__);
-+		return;
-+	}
-+
-+	/* translate data_type */
-+	data_type = d_type[data_type];
-+
-+	edma_set_transfer_params(lch, (u16)data_type, (u16)elem_count,
-+					(u16)frame_count, (u16)elem_count,
-+					(enum sync_dimension)sync_mode);
-+}
-+EXPORT_SYMBOL(omap_set_dma_transfer_params);
-+
-+/**
-+ * omap_set_dma_dest_params - Set initial DMA destination addr in param RAM slot
-+ * @lch: parameter RAM slot being configured
-+ * @dest_port: not used
-+ * @dest_amode: INCR, except in very rare cases
-+ * @dest_start: physical address of destination (memory, controller FIFO, etc)
-+ * @dst_ei: byte offset between destination arrays in a frame
-+ * @dst_fi: byte offset between destination frames in a block
-+ *
-+ * Note that the destination address is modified during the DMA transfer
-+ * according to edma_set_dest_index().
-+ *
-+ * TODO
-+ * . Not sure about dst_ei and dst_fi
-+ * . fifo_width for edma is not available in sdma API hence setting it to
-+ *   W8BIT
-+ * . dest_port is ignored
-+ */
-+void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
-+			unsigned long dest_start, int dst_ei, int dst_fi)
-+{
-+	if ((enum address_mode)dest_amode > FIFO) {
-+		printk(KERN_ERR "SDMA2EDMA: Line:%d : Param \'dest_amode\' out"
-+				" of range\n", __LINE__);
-+		return;
-+	}
-+
-+	edma_set_dest((unsigned)lch, (dma_addr_t)dest_start,
-+					!dest_amode, W32BIT);
-+	edma_set_dest_index((unsigned)(lch), (s16)dst_ei, (s16)dst_fi);
-+}
-+EXPORT_SYMBOL(omap_set_dma_dest_params);
-+
-+/**
-+ * omap_set_dma_src_params - Set initial DMA source addr in param RAM slot
-+ * @lch: parameter RAM slot being configured
-+ * @src_port: not used
-+ * @src_amode: INCR, except in very rare cases
-+ * @src_start: physical address of destination (memory, controller FIFO, etc)
-+ * @src_ei: byte offset between destination arrays in a frame
-+ * @src_fi: byte offset between destination frames in a block
-+ *
-+ * Note that the source address is modified during the DMA transfer
-+ * according to edma_set_src_index().
-+ *
-+ * TODO
-+ * . Not sure about src_ei and src_fi
-+ * . fifo_width for edma is not available in sdma API hence setting it to
-+ *   W8BIT
-+ * . src_port is ignored
-+ */
-+void omap_set_dma_src_params(int lch, int src_port, int src_amode,
-+			unsigned long src_start, int src_ei, int src_fi)
-+{
-+	if ((enum address_mode)src_amode > FIFO) {
-+		printk(KERN_ERR "SDMA2EDMA: Line:%d : Param \'src_amode\' out "
-+				"of range\n", __LINE__);
-+		return;
-+	}
-+
-+	edma_set_src((unsigned)lch, (dma_addr_t)src_start,
-+					!src_amode, W32BIT);
-+	edma_set_src_index((unsigned)(lch), (s16)src_ei, (s16)src_fi);
-+}
-+EXPORT_SYMBOL(omap_set_dma_src_params);
-+
-+void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
-+{
-+	printk(KERN_WARNING "omap_set_dma_src_burst_mode: un-supported SDMA"
-+				" wrapper\n");
-+}
-+EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
-+
-+void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
-+{
-+	printk(KERN_WARNING "omap_set_dma_dest_burst_mode: un-supported SDMA"
-+				" wrapper\n");
-+}
-+EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
-+
-+dma_addr_t omap_get_dma_dst_pos(int lch)
-+{
-+	printk(KERN_WARNING "omap_get_dma_dst_pos: un-supported in SDMA"
-+				" wrapper\n");
-+	return 0;
-+}
-+EXPORT_SYMBOL(omap_get_dma_dst_pos);
-+
-+int omap_get_dma_active_status(int lch)
-+{
-+	printk(KERN_WARNING "omap_get_dma_active_status: un-supported in SDMA"
-+				" wrapper\n");
-+	return 0;
-+}
-+EXPORT_SYMBOL(omap_get_dma_active_status);
-+
-+void omap_dma_global_context_save(void)
-+{
-+	printk(KERN_WARNING "omap_dma_global_context_save: un-supported in SDMA"
-+				" wrapper\n");
-+}
-+EXPORT_SYMBOL(omap_dma_global_context_save);
-+
-+void omap_dma_global_context_restore(void)
-+{
-+	printk(KERN_WARNING "omap_dma_global_context_restore: un-supported in"
-+				"SDMA wrapper\n");
-+}
-+EXPORT_SYMBOL(omap_dma_global_context_restore);
-+
-+int omap_dma_running(void)
-+{
-+	printk(KERN_WARNING "omap_dma_running: un-supported in SDMA wrapper\n");
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(omap_dma_running);
-+
-+void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
-+{
-+	printk(KERN_WARNING "omap_set_dma_color_mode: un-supported in"
-+				"SDMA wrapper\n");
-+}
-+EXPORT_SYMBOL(omap_set_dma_color_mode);
-+
-+void omap_set_dma_dest_data_pack(int lch, int enable)
-+{
-+	printk(KERN_WARNING "omap_set_dma_dest_data_pack: un-supported in"
-+				"SDMA wrapper\n");
-+}
-+EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
-+
-+void omap_set_dma_src_data_pack(int lch, int enable)
-+{
-+	printk(KERN_WARNING "omap_set_dma_src_data_pack: un-supported in"
-+				"SDMA wrapper\n");
-+}
-+EXPORT_SYMBOL(omap_set_dma_src_data_pack);
-+
-+void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
-+{
-+	printk(KERN_WARNING "omap_set_dma_write_mode: un-supported in"
-+				"SDMA wrapper\n");
-+}
-+EXPORT_SYMBOL(omap_set_dma_write_mode);
-diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
-index 8b28664..09544e1 100644
---- a/arch/arm/plat-omap/sram.c
-+++ b/arch/arm/plat-omap/sram.c
-@@ -40,7 +40,11 @@
- #define OMAP1_SRAM_PA		0x20000000
- #define OMAP2_SRAM_PUB_PA	(OMAP2_SRAM_PA + 0xf800)
- #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
-+#ifdef CONFIG_OMAP4_ERRATA_I688
-+#define OMAP4_SRAM_PUB_PA	OMAP4_SRAM_PA
-+#else
- #define OMAP4_SRAM_PUB_PA	(OMAP4_SRAM_PA + 0x4000)
-+#endif
- 
- #if defined(CONFIG_ARCH_OMAP2PLUS)
- #define SRAM_BOOTLOADER_SZ	0x00
-@@ -65,7 +69,6 @@
- static unsigned long omap_sram_start;
- static void __iomem *omap_sram_base;
- static unsigned long omap_sram_size;
--static void __iomem *omap_sram_ceil;
- 
- /*
-  * Depending on the target RAMFS firewall setup, the public usable amount of
-@@ -82,7 +85,7 @@ static int is_sram_locked(void)
- 			__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
- 			__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
- 		}
--		if (cpu_is_omap34xx()) {
-+		if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
- 			__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
- 			__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
- 			__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
-@@ -94,6 +97,9 @@ static int is_sram_locked(void)
- 		return 1; /* assume locked with no PPA or security driver */
- }
- 
-+struct gen_pool *omap_gen_pool;
-+EXPORT_SYMBOL_GPL(omap_gen_pool);
-+
- /*
-  * The amount of SRAM depends on the core type.
-  * Note that we cannot try to test for SRAM here because writes
-@@ -104,7 +110,7 @@ static void __init omap_detect_sram(void)
- {
- 	if (cpu_class_is_omap2()) {
- 		if (is_sram_locked()) {
--			if (cpu_is_omap34xx()) {
-+			if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
- 				omap_sram_start = OMAP3_SRAM_PUB_PA;
- 				if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
- 				    (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
-@@ -120,12 +126,15 @@ static void __init omap_detect_sram(void)
- 				omap_sram_size = 0x800; /* 2K */
- 			}
- 		} else {
--			if (cpu_is_omap34xx()) {
-+			if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
- 				omap_sram_start = OMAP3_SRAM_PA;
- 				omap_sram_size = 0x10000; /* 64K */
- 			} else if (cpu_is_omap44xx()) {
- 				omap_sram_start = OMAP4_SRAM_PA;
- 				omap_sram_size = 0xe000; /* 56K */
-+			} else if (cpu_is_am33xx()) {
-+				omap_sram_start = AM33XX_SRAM_PA;
-+				omap_sram_size = 0x10000; /* 64K */
- 			} else {
- 				omap_sram_start = OMAP2_SRAM_PA;
- 				if (cpu_is_omap242x())
-@@ -141,11 +150,9 @@ static void __init omap_detect_sram(void)
- 			omap_sram_size = 0x32000;	/* 200K */
- 		else if (cpu_is_omap15xx())
- 			omap_sram_size = 0x30000;	/* 192K */
--		else if (cpu_is_omap1610() || cpu_is_omap1621() ||
--		     cpu_is_omap1710())
-+		else if (cpu_is_omap1610() || cpu_is_omap1611() ||
-+				cpu_is_omap1621() || cpu_is_omap1710())
- 			omap_sram_size = 0x4000;	/* 16K */
--		else if (cpu_is_omap1611())
--			omap_sram_size = SZ_256K;
- 		else {
- 			pr_err("Could not detect SRAM size\n");
- 			omap_sram_size = 0x4000;
-@@ -163,6 +170,10 @@ static void __init omap_map_sram(void)
- 	if (omap_sram_size == 0)
- 		return;
- 
-+#ifdef CONFIG_OMAP4_ERRATA_I688
-+		omap_sram_start += PAGE_SIZE;
-+		omap_sram_size -= SZ_16K;
-+#endif
- 	if (cpu_is_omap34xx()) {
- 		/*
- 		 * SRAM must be marked as non-cached on OMAP3 since the
-@@ -182,39 +193,24 @@ static void __init omap_map_sram(void)
- 		return;
- 	}
- 
--	omap_sram_ceil = omap_sram_base + omap_sram_size;
--
- 	/*
- 	 * Looks like we need to preserve some bootloader code at the
- 	 * beginning of SRAM for jumping to flash for reboot to work...
- 	 */
- 	memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
- 	       omap_sram_size - SRAM_BOOTLOADER_SZ);
--}
--
--/*
-- * Memory allocator for SRAM: calculates the new ceiling address
-- * for pushing a function using the fncpy API.
-- *
-- * Note that fncpy requires the returned address to be aligned
-- * to an 8-byte boundary.
-- */
--void *omap_sram_push_address(unsigned long size)
--{
--	unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
--
--	available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
--
--	if (size > available) {
--		pr_err("Not enough space in SRAM\n");
--		return NULL;
-+	{
-+		/* The first SRAM_BOOTLOADER_SZ of SRAM are reserved */
-+		void *base = (void *)omap_sram_base + SRAM_BOOTLOADER_SZ;
-+		phys_addr_t phys = omap_sram_start + SRAM_BOOTLOADER_SZ;
-+		size_t len = omap_sram_size - SRAM_BOOTLOADER_SZ;
-+
-+		omap_gen_pool = gen_pool_create(ilog2(FNCPY_ALIGN), -1);
-+		if (omap_gen_pool)
-+			WARN_ON(gen_pool_add_virt(omap_gen_pool,
-+					(unsigned long)base, phys, len, -1));
-+		WARN_ON(!omap_gen_pool);
- 	}
--
--	new_ceil -= size;
--	new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
--	omap_sram_ceil = IOMEM(new_ceil);
--
--	return (void *)omap_sram_ceil;
- }
- 
- #ifdef CONFIG_ARCH_OMAP1
-@@ -224,6 +220,9 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
- void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
- {
- 	BUG_ON(!_omap_sram_reprogram_clock);
-+	/* On 730, bit 13 must always be 1 */
-+	if (cpu_is_omap7xx())
-+		ckctl |= 0x2000;
- 	_omap_sram_reprogram_clock(dpllctl, ckctl);
- }
- 
-@@ -340,8 +339,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
- #ifdef CONFIG_PM
- void omap3_sram_restore_context(void)
- {
--	omap_sram_ceil = omap_sram_base + omap_sram_size;
--
- 	_omap3_sram_configure_core_dpll =
- 		omap_sram_push(omap3_sram_configure_core_dpll,
- 			       omap3_sram_configure_core_dpll_sz);
-@@ -359,6 +356,12 @@ static inline int omap34xx_sram_init(void)
- 	return 0;
- }
- 
-+static inline int am33xx_sram_init(void)
-+{
-+	am33xx_push_sram_idle();
-+	return 0;
-+}
-+
- int __init omap_sram_init(void)
- {
- 	omap_detect_sram();
-@@ -370,8 +373,10 @@ int __init omap_sram_init(void)
- 		omap242x_sram_init();
- 	else if (cpu_is_omap2430())
- 		omap243x_sram_init();
--	else if (cpu_is_omap34xx())
-+	else if (cpu_is_omap34xx() && !cpu_is_am33xx())
- 		omap34xx_sram_init();
-+	else if (cpu_is_am33xx())
-+		am33xx_sram_init();
- 
- 	return 0;
- }
-diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
-index 9b9968f..8167ce6 100644
---- a/arch/arm/plat-s5p/Kconfig
-+++ b/arch/arm/plat-s5p/Kconfig
-@@ -11,6 +11,7 @@ config PLAT_S5P
- 	default y
- 	select ARM_VIC if !ARCH_EXYNOS4
- 	select ARM_GIC if ARCH_EXYNOS4
-+	select GIC_NON_BANKED if ARCH_EXYNOS4
- 	select NO_IOPORT
- 	select ARCH_REQUIRE_GPIOLIB
- 	select S3C_GPIO_TRACK
-diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h
-index a235fa0..1171f22 100644
---- a/arch/arm/plat-spear/include/plat/system.h
-+++ b/arch/arm/plat-spear/include/plat/system.h
-@@ -31,7 +31,7 @@ static inline void arch_reset(char mode, const char *cmd)
- {
- 	if (mode == 's') {
- 		/* software reset, Jump into ROM at address 0 */
--		cpu_reset(0);
-+		soft_restart(0);
- 	} else {
- 		/* hardware reset, Use on-chip reset capability */
- 		sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
-diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h
-deleted file mode 100644
-index 8c8b24d..0000000
---- a/arch/arm/plat-spear/include/plat/vmalloc.h
-+++ /dev/null
-@@ -1,19 +0,0 @@
--/*
-- * arch/arm/plat-spear/include/plat/vmalloc.h
-- *
-- * Defining Vmalloc area for SPEAr platform
-- *
-- * Copyright (C) 2009 ST Microelectronics
-- * Viresh Kumar<viresh.kumar@st.com>
-- *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-- */
--
--#ifndef __PLAT_VMALLOC_H
--#define __PLAT_VMALLOC_H
--
--#define VMALLOC_END		0xF0000000UL
--
--#endif /* __PLAT_VMALLOC_H */
-diff --git a/arch/arm/plat-tcc/include/mach/vmalloc.h b/arch/arm/plat-tcc/include/mach/vmalloc.h
-deleted file mode 100644
-index 99414d9..0000000
---- a/arch/arm/plat-tcc/include/mach/vmalloc.h
-+++ /dev/null
-@@ -1,10 +0,0 @@
--/*
-- * Author: <linux@telechips.com>
-- * Created: June 10, 2008
-- *
-- * Copyright (C) 2000 Russell King.
-- * Copyright (C) 2008-2009 Telechips
-- *
-- * Licensed under the terms of the GPL v2.
-- */
--#define VMALLOC_END	0xf0000000UL
-diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
-index ccbe16f..217ea76 100644
---- a/arch/arm/tools/mach-types
-+++ b/arch/arm/tools/mach-types
-@@ -1126,3 +1126,5 @@ atdgp318		MACH_ATDGP318		ATDGP318		3494
- m28evk			MACH_M28EVK		M28EVK			3613
- smdk4212		MACH_SMDK4212		SMDK4212		3638
- smdk4412		MACH_SMDK4412		SMDK4412		3765
-+am335xevm		MACH_AM335XEVM		AM335XEVM		3589
-+am335xiaevm		MACH_AM335XIAEVM	AM335XIAEVM		3684
-diff --git a/drivers/Kconfig b/drivers/Kconfig
-index b5e6f24..ba3886c 100644
---- a/drivers/Kconfig
-+++ b/drivers/Kconfig
-@@ -2,6 +2,8 @@ menu "Device Drivers"
- 
- source "drivers/base/Kconfig"
- 
-+source "drivers/cbus/Kconfig"
-+
- source "drivers/connector/Kconfig"
- 
- source "drivers/mtd/Kconfig"
-@@ -60,6 +62,8 @@ source "drivers/pinctrl/Kconfig"
- 
- source "drivers/gpio/Kconfig"
- 
-+source "drivers/pwm/Kconfig"
-+
- source "drivers/w1/Kconfig"
- 
- source "drivers/power/Kconfig"
-diff --git a/drivers/Makefile b/drivers/Makefile
-index 1b31421..9deecef 100644
---- a/drivers/Makefile
-+++ b/drivers/Makefile
-@@ -8,6 +8,7 @@
- # GPIO must come after pinctrl as gpios may need to mux pins etc
- obj-y				+= pinctrl/
- obj-y				+= gpio/
-+obj-$(CONFIG_GENERIC_PWM)	+= pwm/
- obj-$(CONFIG_PCI)		+= pci/
- obj-$(CONFIG_PARISC)		+= parisc/
- obj-$(CONFIG_RAPIDIO)		+= rapidio/
-@@ -78,7 +79,7 @@ obj-$(CONFIG_GAMEPORT)		+= input/gameport/
- obj-$(CONFIG_INPUT)		+= input/
- obj-$(CONFIG_I2O)		+= message/
- obj-$(CONFIG_RTC_LIB)		+= rtc/
--obj-y				+= i2c/ media/
-+obj-y				+= i2c/ media/ cbus/
- obj-$(CONFIG_PPS)		+= pps/
- obj-$(CONFIG_PTP_1588_CLOCK)	+= ptp/
- obj-$(CONFIG_W1)		+= w1/
-diff --git a/drivers/cbus/Kconfig b/drivers/cbus/Kconfig
-new file mode 100644
-index 0000000..41d96e7
---- /dev/null
-+++ b/drivers/cbus/Kconfig
-@@ -0,0 +1,86 @@
-+#
-+# CBUS device configuration
-+#
-+
-+menu "CBUS support"
-+
-+config CBUS
-+	bool "CBUS support on OMAP"
-+	---help---
-+	  CBUS is a proprietary serial protocol by Nokia.  It is mainly
-+	  used for accessing Energy Management auxiliary chips.
-+
-+	  If you want CBUS support, you should say Y here.
-+
-+config CBUS_TAHVO
-+	depends on CBUS
-+	bool "Support for Tahvo"
-+	---help---
-+	  Tahvo is a mixed signal ASIC with some system features
-+
-+	  If you want Tahvo support, you should say Y here.
-+
-+if CBUS_TAHVO
-+
-+config CBUS_TAHVO_USB
-+	depends on USB
-+	depends on ARCH_OMAP
-+	select USB_OTG_UTILS
-+	tristate "Support for Tahvo USB transceiver"
-+	---help---
-+	  If you want Tahvo support for USB transceiver, say Y or M here.
-+
-+config CBUS_TAHVO_USB_HOST_BY_DEFAULT
-+	depends on CBUS_TAHVO_USB && USB_OTG
-+	boolean "Device in USB host mode by default"
-+	---help---
-+	  Say Y here, if you want the device to enter USB host mode
-+	  by default on bootup.
-+
-+endif # CBUS_TAHVO
-+
-+config CBUS_RETU
-+	depends on CBUS
-+	bool "Support for Retu"
-+	---help---
-+	  Retu is a mixed signal ASIC with some system features
-+
-+	  If you want Retu support, you should say Y here.
-+
-+if CBUS_RETU
-+
-+config CBUS_RETU_POWERBUTTON
-+	depends on INPUT
-+	bool "Support for Retu power button"
-+	---help---
-+	  The power button on Nokia 770 is connected to the Retu ASIC.
-+
-+	  If you want support for the Retu power button, you should say Y here.
-+
-+config CBUS_RETU_RTC
-+	depends on RTC_CLASS
-+	depends on ARCH_OMAP
-+	tristate "Support for Retu pseudo-RTC"
-+	---help---
-+	  Say Y here if you want support for the device that alleges to be an
-+	  RTC in Retu. This will expose a sysfs interface for it.
-+
-+config CBUS_RETU_WDT
-+	depends on SYSFS && WATCHDOG
-+	depends on ARCH_OMAP
-+	tristate "Support for Retu watchdog timer"
-+	---help---
-+	  Say Y here if you want support for the watchdog in Retu. This will
-+	  expose a sysfs interface to grok it.
-+
-+config CBUS_RETU_HEADSET
-+	depends on SYSFS
-+	tristate "Support for headset detection with Retu/Vilma"
-+	---help---
-+	  Say Y here if you want support detecting a headset that's connected
-+	  to Retu/Vilma. Detection state and events are exposed through
-+	  sysfs.
-+
-+endif # CBUS_RETU
-+
-+endmenu
-diff --git a/drivers/cbus/Makefile b/drivers/cbus/Makefile
-new file mode 100644
-index 0000000..483c3ca
---- /dev/null
-+++ b/drivers/cbus/Makefile
-@@ -0,0 +1,13 @@
-+#
-+# Makefile for CBUS.
-+#
-+
-+obj-$(CONFIG_CBUS)		+= cbus.o
-+obj-$(CONFIG_CBUS_TAHVO)	+= tahvo.o
-+obj-$(CONFIG_CBUS_RETU)		+= retu.o
-+obj-$(CONFIG_CBUS_TAHVO_USB)	+= tahvo-usb.o
-+
-+obj-$(CONFIG_CBUS_RETU_POWERBUTTON) += retu-pwrbutton.o
-+obj-$(CONFIG_CBUS_RETU_RTC)	+= retu-rtc.o
-+obj-$(CONFIG_CBUS_RETU_WDT)	+= retu-wdt.o
-+obj-$(CONFIG_CBUS_RETU_HEADSET)	+= retu-headset.o
-diff --git a/drivers/cbus/cbus.c b/drivers/cbus/cbus.c
-new file mode 100644
-index 0000000..45b01fd
---- /dev/null
-+++ b/drivers/cbus/cbus.c
-@@ -0,0 +1,328 @@
-+/*
-+ * drivers/cbus/cbus.c
-+ *
-+ * Support functions for CBUS serial protocol
-+ *
-+ * Copyright (C) 2004-2010 Nokia Corporation
-+ * Contact: Felipe Balbi <felipe.balbi@nokia.com>
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
-+ *	      David Weinehall <david.weinehall@nokia.com>, and
-+ *	      Mikko Ylinen <mikko.k.ylinen@nokia.com>
-+ *
-+ * Several updates and cleanups by Felipe Balbi <felipe.balbi@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/export.h>
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+#include <linux/gpio.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/cbus.h>
-+
-+#include "cbus.h"
-+
-+#define CBUS_XFER_READ		1
-+#define CBUS_XFER_WRITE		0
-+
-+struct cbus_host {
-+	/* host lock */
-+	spinlock_t	lock;
-+
-+	struct device	*dev;
-+
-+	int		clk_gpio;
-+	int		dat_gpio;
-+	int		sel_gpio;
-+};
-+
-+/**
-+ * cbus_send_bit - sends one bit over the bus
-+ * @host: the host we're using
-+ * @bit: one bit of information to send
-+ * @input: whether to set data pin as input after sending
-+ */
-+static int cbus_send_bit(struct cbus_host *host, unsigned bit,
-+		unsigned input)
-+{
-+	int ret = 0;
-+
-+	gpio_set_value(host->dat_gpio, bit ? 1 : 0);
-+	gpio_set_value(host->clk_gpio, 1);
-+
-+	/* The data bit is read on the rising edge of CLK */
-+	if (input)
-+		ret = gpio_direction_input(host->dat_gpio);
-+
-+	gpio_set_value(host->clk_gpio, 0);
-+
-+	return ret;
-+}
-+
-+/**
-+ * cbus_send_data - sends @len amount of data over the bus
-+ * @host: the host we're using
-+ * @data: the data to send
-+ * @len: size of the transfer
-+ * @input: whether to set data pin as input after sending
-+ */
-+static int cbus_send_data(struct cbus_host *host, unsigned data, unsigned len,
-+		unsigned input)
-+{
-+	int ret = 0;
-+	int i;
-+
-+	for (i = len; i > 0; i--) {
-+		ret = cbus_send_bit(host, data & (1 << (i - 1)),
-+				input && (i == 1));
-+		if (ret < 0)
-+			goto out;
-+	}
-+
-+out:
-+	return ret;
-+}
-+
-+/**
-+ * cbus_receive_bit - receives one bit from the bus
-+ * @host: the host we're using
-+ */
-+static int cbus_receive_bit(struct cbus_host *host)
-+{
-+	int ret;
-+
-+	gpio_set_value(host->clk_gpio, 1);
-+	ret = gpio_get_value(host->dat_gpio);
-+	if (ret < 0)
-+		goto out;
-+	gpio_set_value(host->clk_gpio, 0);
-+
-+out:
-+	return ret;
-+}
-+
-+/**
-+ * cbus_receive_data - receives @len data from the bus
-+ * @host: the host we're using
-+ * @len: the length of data to receive
-+ */
-+static int cbus_receive_data(struct cbus_host *host, unsigned len)
-+{
-+	int ret = 0;
-+	int i;
-+
-+	for (i = 16; i > 0; i--) {
-+		int bit = cbus_receive_bit(host);
-+
-+		if (bit < 0)
-+			goto out;
-+
-+		if (bit)
-+			ret |= 1 << (i - 1);
-+	}
-+
-+out:
-+	return ret;
-+}
-+
-+/**
-+ * cbus_transfer - transfers data over the bus
-+ * @host: the host we're using
-+ * @rw: read/write flag
-+ * @dev: device address
-+ * @reg: register address
-+ * @data: if @rw == 0 data to send otherwise 0
-+ */
-+static int cbus_transfer(struct cbus_host *host, unsigned rw, unsigned dev,
-+		unsigned reg, unsigned data)
-+{
-+	unsigned long flags;
-+	int input = 0;
-+	int ret = 0;
-+
-+	/* We don't want interrupts disturbing our transfer */
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	/* Reset state and start of transfer, SEL stays down during transfer */
-+	gpio_set_value(host->sel_gpio, 0);
-+
-+	/* Set the DAT pin to output */
-+	gpio_direction_output(host->dat_gpio, 1);
-+
-+	/* Send the device address */
-+	ret = cbus_send_data(host, dev, 3, 0);
-+	if (ret < 0) {
-+		dev_dbg(host->dev, "failed sending device addr\n");
-+		goto out;
-+	}
-+
-+	/* Send the rw flag */
-+	ret = cbus_send_bit(host, rw, 0);
-+	if (ret < 0) {
-+		dev_dbg(host->dev, "failed sending read/write flag\n");
-+		goto out;
-+	}
-+
-+	/* Send the register address */
-+	if (rw)
-+		input = true;
-+
-+	ret = cbus_send_data(host, reg, 5, input);
-+	if (ret < 0) {
-+		dev_dbg(host->dev, "failed sending register addr\n");
-+		goto out;
-+	}
-+
-+	if (!rw) {
-+		ret = cbus_send_data(host, data, 16, 0);
-+		if (ret < 0) {
-+			dev_dbg(host->dev, "failed sending data\n");
-+			goto out;
-+		}
-+	} else {
-+		gpio_set_value(host->clk_gpio, 1);
-+
-+		ret = cbus_receive_data(host, 16);
-+		if (ret < 0) {
-+			dev_dbg(host->dev, "failed receiving data\n");
-+			goto out;
-+		}
-+	}
-+
-+	/* Indicate end of transfer, SEL goes up until next transfer */
-+	gpio_set_value(host->sel_gpio, 1);
-+	gpio_set_value(host->clk_gpio, 1);
-+	gpio_set_value(host->clk_gpio, 0);
-+
-+out:
-+	spin_unlock_irqrestore(&host->lock, flags);
-+
-+	return ret;
-+}
-+
-+/**
-+ * cbus_read_reg - reads a given register from the device
-+ * @child: the child device
-+ * @dev: device address
-+ * @reg: register address
-+ */
-+int cbus_read_reg(struct device *child, unsigned dev, unsigned reg)
-+{
-+	struct cbus_host	*host = dev_get_drvdata(child->parent);
-+
-+	return cbus_transfer(host, CBUS_XFER_READ, dev, reg, 0);
-+}
-+EXPORT_SYMBOL(cbus_read_reg);
-+
-+/**
-+ * cbus_write_reg - writes to a given register of the device
-+ * @child: the child device
-+ * @dev: device address
-+ * @reg: register address
-+ * @val: data to be written to @reg
-+ */
-+int cbus_write_reg(struct device *child, unsigned dev, unsigned reg,
-+		unsigned val)
-+{
-+	struct cbus_host	*host = dev_get_drvdata(child->parent);
-+
-+	return cbus_transfer(host, CBUS_XFER_WRITE, dev, reg, val);
-+}
-+EXPORT_SYMBOL(cbus_write_reg);
-+
-+static int __devinit cbus_bus_probe(struct platform_device *pdev)
-+{
-+	struct cbus_host *chost;
-+	struct cbus_host_platform_data *pdata = pdev->dev.platform_data;
-+	int ret;
-+
-+	chost = kzalloc(sizeof(*chost), GFP_KERNEL);
-+	if (chost == NULL)
-+		return -ENOMEM;
-+
-+	spin_lock_init(&chost->lock);
-+
-+	chost->clk_gpio = pdata->clk_gpio;
-+	chost->dat_gpio = pdata->dat_gpio;
-+	chost->sel_gpio = pdata->sel_gpio;
-+	chost->dev = &pdev->dev;
-+
-+	ret = gpio_request(chost->clk_gpio, "CBUS clk");
-+	if (ret < 0)
-+		goto exit1;
-+
-+	ret = gpio_request(chost->dat_gpio, "CBUS data");
-+	if (ret < 0)
-+		goto exit2;
-+
-+	ret = gpio_request(chost->sel_gpio, "CBUS sel");
-+	if (ret < 0)
-+		goto exit3;
-+
-+	gpio_direction_output(chost->clk_gpio, 0);
-+	gpio_direction_input(chost->dat_gpio);
-+	gpio_direction_output(chost->sel_gpio, 1);
-+
-+	gpio_set_value(chost->clk_gpio, 1);
-+	gpio_set_value(chost->clk_gpio, 0);
-+
-+	platform_set_drvdata(pdev, chost);
-+
-+	return 0;
-+exit3:
-+	gpio_free(chost->dat_gpio);
-+exit2:
-+	gpio_free(chost->clk_gpio);
-+exit1:
-+	kfree(chost);
-+
-+	return ret;
-+}
-+
-+static int __devexit cbus_bus_remove(struct platform_device *pdev)
-+{
-+	struct cbus_host	*chost = platform_get_drvdata(pdev);
-+
-+	gpio_free(chost->sel_gpio);
-+	gpio_free(chost->dat_gpio);
-+	gpio_free(chost->clk_gpio);
-+
-+	kfree(chost);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver cbus_driver = {
-+	.probe		= cbus_bus_probe,
-+	.remove		= __devexit_p(cbus_bus_remove),
-+	.driver		= {
-+		.name	= "cbus",
-+	},
-+};
-+
-+module_platform_driver(cbus_driver);
-+
-+MODULE_DESCRIPTION("CBUS serial protocol");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä");
-+MODULE_AUTHOR("David Weinehall");
-+MODULE_AUTHOR("Mikko Ylinen");
-+MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
-+
-diff --git a/drivers/cbus/cbus.h b/drivers/cbus/cbus.h
-new file mode 100644
-index 0000000..5380d173
---- /dev/null
-+++ b/drivers/cbus/cbus.h
-@@ -0,0 +1,33 @@
-+/*
-+ * drivers/cbus/cbus.h
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
-+ *	      David Weinehall <david.weinehall@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#ifndef __DRIVERS_CBUS_CBUS_H
-+#define __DRIVERS_CBUS_CBUS_H
-+
-+#define CBUS_RETU_DEVICE_ID	0x01
-+#define CBUS_TAHVO_DEVICE_ID	0x02
-+
-+extern int cbus_read_reg(struct device *, unsigned dev, unsigned reg);
-+extern int cbus_write_reg(struct device *, unsigned dev, unsigned reg,
-+		unsigned val);
-+
-+#endif /* __DRIVERS_CBUS_CBUS_H */
-diff --git a/drivers/cbus/retu-headset.c b/drivers/cbus/retu-headset.c
-new file mode 100644
-index 0000000..576b0e6
---- /dev/null
-+++ b/drivers/cbus/retu-headset.c
-@@ -0,0 +1,350 @@
-+/**
-+ * Retu/Vilma headset detection
-+ *
-+ * Copyright (C) 2006 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/input.h>
-+#include <linux/platform_device.h>
-+
-+#include "retu.h"
-+
-+#define RETU_ADC_CHANNEL_HOOKDET	0x05
-+
-+#define RETU_HEADSET_KEY		KEY_PHONE
-+
-+struct retu_headset {
-+	spinlock_t			lock;
-+	struct mutex			mutex;
-+	struct device			*dev;
-+	struct input_dev		*idev;
-+	unsigned			bias_enabled;
-+	unsigned			detection_enabled;
-+	unsigned			pressed;
-+	struct timer_list		enable_timer;
-+	struct timer_list		detect_timer;
-+	int				irq;
-+};
-+
-+static void retu_headset_set_bias(struct retu_headset *hs, int enable)
-+{
-+	if (enable) {
-+		retu_set_clear_reg_bits(hs->dev, RETU_REG_AUDTXR,
-+					(1 << 0) | (1 << 1), 0);
-+		msleep(2);
-+		retu_set_clear_reg_bits(hs->dev, RETU_REG_AUDTXR,
-+				1 << 3, 0);
-+	} else {
-+		retu_set_clear_reg_bits(hs->dev, RETU_REG_AUDTXR, 0,
-+					(1 << 0) | (1 << 1) | (1 << 3));
-+	}
-+}
-+
-+static void retu_headset_enable(struct retu_headset *hs)
-+{
-+	mutex_lock(&hs->mutex);
-+	if (!hs->bias_enabled) {
-+		hs->bias_enabled = 1;
-+		retu_headset_set_bias(hs, 1);
-+	}
-+	mutex_unlock(&hs->mutex);
-+}
-+
-+static void retu_headset_disable(struct retu_headset *hs)
-+{
-+	mutex_lock(&hs->mutex);
-+	if (hs->bias_enabled) {
-+		hs->bias_enabled = 0;
-+		retu_headset_set_bias(hs, 0);
-+	}
-+	mutex_unlock(&hs->mutex);
-+}
-+
-+static void retu_headset_det_enable(struct retu_headset *hs)
-+{
-+	mutex_lock(&hs->mutex);
-+	if (!hs->detection_enabled) {
-+		hs->detection_enabled = 1;
-+		retu_set_clear_reg_bits(hs->dev, RETU_REG_CC1,
-+				(1 << 10) | (1 << 8), 0);
-+	}
-+	mutex_unlock(&hs->mutex);
-+}
-+
-+static void retu_headset_det_disable(struct retu_headset *hs)
-+{
-+	unsigned long flags;
-+
-+	mutex_lock(&hs->mutex);
-+	if (hs->detection_enabled) {
-+		hs->detection_enabled = 0;
-+		del_timer_sync(&hs->enable_timer);
-+		del_timer_sync(&hs->detect_timer);
-+		spin_lock_irqsave(&hs->lock, flags);
-+		if (hs->pressed)
-+			input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
-+		spin_unlock_irqrestore(&hs->lock, flags);
-+		retu_set_clear_reg_bits(hs->dev, RETU_REG_CC1, 0,
-+				(1 << 10) | (1 << 8));
-+	}
-+	mutex_unlock(&hs->mutex);
-+}
-+
-+static ssize_t retu_headset_hookdet_show(struct device *dev,
-+					 struct device_attribute *attr,
-+					 char *buf)
-+{
-+	int val;
-+
-+	val = retu_read_adc(dev, RETU_ADC_CHANNEL_HOOKDET);
-+	return sprintf(buf, "%d\n", val);
-+}
-+
-+static DEVICE_ATTR(hookdet, S_IRUGO, retu_headset_hookdet_show, NULL);
-+
-+static ssize_t retu_headset_enable_show(struct device *dev,
-+					struct device_attribute *attr,
-+					char *buf)
-+{
-+	struct retu_headset *hs = dev_get_drvdata(dev);
-+
-+	return sprintf(buf, "%u\n", hs->bias_enabled);
-+}
-+
-+static ssize_t retu_headset_enable_store(struct device *dev,
-+					 struct device_attribute *attr,
-+					 const char *buf, size_t count)
-+{
-+	struct retu_headset *hs = dev_get_drvdata(dev);
-+	int enable;
-+
-+	if (sscanf(buf, "%u", &enable) != 1)
-+		return -EINVAL;
-+	if (enable)
-+		retu_headset_enable(hs);
-+	else
-+	        retu_headset_disable(hs);
-+	return count;
-+}
-+
-+static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR | S_IWGRP,
-+		   retu_headset_enable_show, retu_headset_enable_store);
-+
-+static ssize_t retu_headset_enable_det_show(struct device *dev,
-+					    struct device_attribute *attr,
-+					    char *buf)
-+{
-+	struct retu_headset *hs = dev_get_drvdata(dev);
-+
-+	return sprintf(buf, "%u\n", hs->detection_enabled);
-+}
-+
-+static ssize_t retu_headset_enable_det_store(struct device *dev,
-+					     struct device_attribute *attr,
-+					     const char *buf, size_t count)
-+{
-+	struct retu_headset *hs = dev_get_drvdata(dev);
-+	int enable;
-+
-+	if (sscanf(buf, "%u", &enable) != 1)
-+		return -EINVAL;
-+	if (enable)
-+		retu_headset_det_enable(hs);
-+	else
-+	        retu_headset_det_disable(hs);
-+	return count;
-+}
-+
-+static DEVICE_ATTR(enable_det, S_IRUGO | S_IWUSR | S_IWGRP,
-+		   retu_headset_enable_det_show,
-+		   retu_headset_enable_det_store);
-+
-+static irqreturn_t retu_headset_hook_interrupt(int irq, void *_hs)
-+{
-+	struct retu_headset	*hs = _hs;
-+	unsigned long		flags;
-+
-+	spin_lock_irqsave(&hs->lock, flags);
-+	if (!hs->pressed) {
-+		/* Headset button was just pressed down. */
-+		hs->pressed = 1;
-+		input_report_key(hs->idev, RETU_HEADSET_KEY, 1);
-+	}
-+	spin_unlock_irqrestore(&hs->lock, flags);
-+	retu_set_clear_reg_bits(hs->dev, RETU_REG_CC1, 0,
-+			(1 << 10) | (1 << 8));
-+	mod_timer(&hs->enable_timer, jiffies + msecs_to_jiffies(50));
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static void retu_headset_enable_timer(unsigned long arg)
-+{
-+	struct retu_headset *hs = (struct retu_headset *) arg;
-+
-+	retu_set_clear_reg_bits(hs->dev, RETU_REG_CC1,
-+			(1 << 10) | (1 << 8), 0);
-+	mod_timer(&hs->detect_timer, jiffies + msecs_to_jiffies(350));
-+}
-+
-+static void retu_headset_detect_timer(unsigned long arg)
-+{
-+	struct retu_headset *hs = (struct retu_headset *) arg;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&hs->lock, flags);
-+	if (hs->pressed) {
-+		hs->pressed = 0;
-+		input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
-+	}
-+	spin_unlock_irqrestore(&hs->lock, flags);
-+}
-+
-+static int __devinit retu_headset_probe(struct platform_device *pdev)
-+{
-+	struct retu_headset *hs;
-+	int irq;
-+	int r;
-+
-+	hs = kzalloc(sizeof(*hs), GFP_KERNEL);
-+	if (hs == NULL)
-+		return -ENOMEM;
-+
-+	hs->dev = &pdev->dev;
-+
-+	hs->idev = input_allocate_device();
-+	if (hs->idev == NULL) {
-+		r = -ENOMEM;
-+		goto err1;
-+	}
-+	hs->idev->name = "retu-headset";
-+	hs->idev->dev.parent = &pdev->dev;
-+	set_bit(EV_KEY, hs->idev->evbit);
-+	set_bit(RETU_HEADSET_KEY, hs->idev->keybit);
-+	r = input_register_device(hs->idev);
-+	if (r < 0)
-+		goto err2;
-+
-+	r = device_create_file(&pdev->dev, &dev_attr_hookdet);
-+	if (r < 0)
-+		goto err3;
-+	r = device_create_file(&pdev->dev, &dev_attr_enable);
-+	if (r < 0)
-+		goto err4;
-+	r = device_create_file(&pdev->dev, &dev_attr_enable_det);
-+	if (r < 0)
-+		goto err5;
-+	platform_set_drvdata(pdev, hs);
-+
-+	spin_lock_init(&hs->lock);
-+	mutex_init(&hs->mutex);
-+	setup_timer(&hs->enable_timer, retu_headset_enable_timer,
-+		    (unsigned long) hs);
-+	setup_timer(&hs->detect_timer, retu_headset_detect_timer,
-+		    (unsigned long) hs);
-+
-+	irq = platform_get_irq(pdev, 0);
-+	hs->irq = irq;
-+
-+	r = request_threaded_irq(irq, NULL, retu_headset_hook_interrupt, 0,
-+			"hookdet", hs);
-+	if (r != 0) {
-+		dev_err(&pdev->dev, "hookdet IRQ not available\n");
-+		goto err6;
-+	}
-+
-+	return 0;
-+err6:
-+	device_remove_file(&pdev->dev, &dev_attr_enable_det);
-+err5:
-+	device_remove_file(&pdev->dev, &dev_attr_enable);
-+err4:
-+	device_remove_file(&pdev->dev, &dev_attr_hookdet);
-+err3:
-+	input_unregister_device(hs->idev);
-+err2:
-+	input_free_device(hs->idev);
-+err1:
-+	kfree(hs);
-+	return r;
-+}
-+
-+static int __devexit retu_headset_remove(struct platform_device *pdev)
-+{
-+	struct retu_headset *hs = platform_get_drvdata(pdev);
-+
-+	device_remove_file(&pdev->dev, &dev_attr_hookdet);
-+	device_remove_file(&pdev->dev, &dev_attr_enable);
-+	device_remove_file(&pdev->dev, &dev_attr_enable_det);
-+	retu_headset_disable(hs);
-+	retu_headset_det_disable(hs);
-+	free_irq(hs->irq, hs);
-+	input_unregister_device(hs->idev);
-+	input_free_device(hs->idev);
-+
-+	return 0;
-+}
-+
-+static int retu_headset_suspend(struct platform_device *pdev,
-+				pm_message_t mesg)
-+{
-+	struct retu_headset *hs = platform_get_drvdata(pdev);
-+
-+	mutex_lock(&hs->mutex);
-+	if (hs->bias_enabled)
-+		retu_headset_set_bias(hs, 0);
-+	mutex_unlock(&hs->mutex);
-+
-+	return 0;
-+}
-+
-+static int retu_headset_resume(struct platform_device *pdev)
-+{
-+	struct retu_headset *hs = platform_get_drvdata(pdev);
-+
-+	mutex_lock(&hs->mutex);
-+	if (hs->bias_enabled)
-+		retu_headset_set_bias(hs, 1);
-+	mutex_unlock(&hs->mutex);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver retu_headset_driver = {
-+	.probe		= retu_headset_probe,
-+	.remove		= __devexit_p(retu_headset_remove),
-+	.suspend	= retu_headset_suspend,
-+	.resume		= retu_headset_resume,
-+	.driver		= {
-+		.name	= "retu-headset",
-+	},
-+};
-+
-+module_platform_driver(retu_headset_driver);
-+
-+MODULE_ALIAS("platform:retu-headset");
-+MODULE_DESCRIPTION("Retu/Vilma headset detection");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä");
-diff --git a/drivers/cbus/retu-pwrbutton.c b/drivers/cbus/retu-pwrbutton.c
-new file mode 100644
-index 0000000..98ad005
---- /dev/null
-+++ b/drivers/cbus/retu-pwrbutton.c
-@@ -0,0 +1,157 @@
-+/**
-+ * drivers/cbus/retu-pwrbutton.c
-+ *
-+ * Driver for sending retu power button event to input-layer
-+ *
-+ * Copyright (C) 2004-2010 Nokia Corporation
-+ *
-+ * Written by
-+ *	Ari Saastamoinen <ari.saastamoinen@elektrobit.com>
-+ *	Juha Yrjola <juha.yrjola@solidboot.com>
-+ *
-+ * Contact: Felipe Balbi <felipe.balbi@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/input.h>
-+#include <linux/jiffies.h>
-+#include <linux/bitops.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#include "retu.h"
-+
-+#define RETU_STATUS_PWRONX	(1 << 5)
-+
-+#define PWRBTN_DELAY		20
-+#define PWRBTN_UP		0
-+#define PWRBTN_PRESSED		1
-+
-+struct retu_pwrbutton {
-+	struct input_dev	*idev;
-+	struct device		*dev;
-+
-+	int			state;
-+	int			irq;
-+};
-+
-+static irqreturn_t retubutton_irq(int irq, void *_pwr)
-+{
-+	struct retu_pwrbutton *pwr = _pwr;
-+	int state;
-+
-+	if (retu_read_reg(pwr->dev, RETU_REG_STATUS) & RETU_STATUS_PWRONX)
-+		state = PWRBTN_UP;
-+	else
-+		state = PWRBTN_PRESSED;
-+
-+	if (pwr->state != state) {
-+		input_report_key(pwr->idev, KEY_POWER, state);
-+		input_sync(pwr->idev);
-+		pwr->state = state;
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int __devinit retubutton_probe(struct platform_device *pdev)
-+{
-+	struct retu_pwrbutton		*pwr;
-+	int				ret = 0;
-+
-+	pwr = kzalloc(sizeof(*pwr), GFP_KERNEL);
-+	if (!pwr) {
-+		dev_err(&pdev->dev, "not enough memory\n");
-+		ret = -ENOMEM;
-+		goto err0;
-+	}
-+
-+	pwr->dev = &pdev->dev;
-+	pwr->irq = platform_get_irq(pdev, 0);
-+	platform_set_drvdata(pdev, pwr);
-+
-+	ret = request_threaded_irq(pwr->irq, NULL, retubutton_irq, 0,
-+			"retu-pwrbutton", pwr);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "Cannot allocate irq\n");
-+		goto err1;
-+	}
-+
-+	pwr->idev = input_allocate_device();
-+	if (!pwr->idev) {
-+		dev_err(&pdev->dev, "can't allocate input device\n");
-+		ret = -ENOMEM;
-+		goto err2;
-+	}
-+
-+	pwr->idev->evbit[0] = BIT_MASK(EV_KEY);
-+	pwr->idev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER);
-+	pwr->idev->name = "retu-pwrbutton";
-+
-+	ret = input_register_device(pwr->idev);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to register input device\n");
-+		goto err3;
-+	}
-+
-+	return 0;
-+
-+err3:
-+	input_free_device(pwr->idev);
-+
-+err2:
-+	free_irq(pwr->irq, pwr);
-+
-+err1:
-+	kfree(pwr);
-+
-+err0:
-+	return ret;
-+}
-+
-+static int __devexit retubutton_remove(struct platform_device *pdev)
-+{
-+	struct retu_pwrbutton		*pwr = platform_get_drvdata(pdev);
-+
-+	free_irq(pwr->irq, pwr);
-+	input_unregister_device(pwr->idev);
-+	input_free_device(pwr->idev);
-+	kfree(pwr);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver retu_pwrbutton_driver = {
-+	.probe		= retubutton_probe,
-+	.remove		= __devexit_p(retubutton_remove),
-+	.driver		= {
-+		.name	= "retu-pwrbutton",
-+	},
-+};
-+
-+module_platform_driver(retu_pwrbutton_driver);
-+
-+MODULE_ALIAS("platform:retu-pwrbutton");
-+MODULE_DESCRIPTION("Retu Power Button");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Ari Saastamoinen");
-+MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
-+
-diff --git a/drivers/cbus/retu-rtc.c b/drivers/cbus/retu-rtc.c
-new file mode 100644
-index 0000000..965ee55
---- /dev/null
-+++ b/drivers/cbus/retu-rtc.c
-@@ -0,0 +1,279 @@
-+/**
-+ * drivers/cbus/retu-rtc.c
-+ *
-+ * Support for Retu RTC
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Paul Mundt <paul.mundt@nokia.com> and
-+ *            Igor Stoppa <igor.stoppa@nokia.com>
-+ *
-+ * The Retu RTC is essentially a partial read-only RTC that gives us Retu's
-+ * idea of what time actually is. It's left as a userspace excercise to map
-+ * this back to time in the real world and ensure that calibration settings
-+ * are sane to compensate for any horrible drift (on account of not being able
-+ * to set the clock to anything).
-+ *
-+ * Days are semi-writeable. Namely, Retu will only track 255 days for us
-+ * consecutively, after which the counter is explicitly stuck at 255 until
-+ * someone comes along and clears it with a write. In the event that no one
-+ * comes along and clears it, we no longer have any idea what day it is.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/mutex.h>
-+#include <linux/rtc.h>
-+
-+#include "cbus.h"
-+#include "retu.h"
-+
-+struct retu_rtc {
-+	/* device lock */
-+	struct mutex		mutex;
-+	struct device		*dev;
-+	struct rtc_device	*rtc;
-+
-+	u16			alarm_expired;
-+	int			irq_rtcs;
-+	int			irq_rtca;
-+};
-+
-+static void retu_rtc_do_reset(struct retu_rtc *rtc)
-+{
-+	u16 ccr1;
-+
-+	ccr1 = retu_read_reg(rtc->dev, RETU_REG_CC1);
-+	/* RTC in reset */
-+	retu_write_reg(rtc->dev, RETU_REG_CC1, ccr1 | 0x0001);
-+	/* RTC in normal operating mode */
-+	retu_write_reg(rtc->dev, RETU_REG_CC1, ccr1 & ~0x0001);
-+
-+	/* Disable alarm and RTC WD */
-+	retu_write_reg(rtc->dev, RETU_REG_RTCHMAR, 0x7f3f);
-+	/* Set Calibration register to default value */
-+	retu_write_reg(rtc->dev, RETU_REG_RTCCALR, 0x00c0);
-+
-+	rtc->alarm_expired = 0;
-+}
-+
-+static irqreturn_t retu_rtc_interrupt(int irq, void *_rtc)
-+{
-+	struct retu_rtc		*rtc = _rtc;
-+
-+	mutex_lock(&rtc->mutex);
-+	rtc->alarm_expired = 1;
-+	retu_write_reg(rtc->dev, RETU_REG_RTCHMAR, (24 << 8) | 60);
-+	mutex_unlock(&rtc->mutex);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int retu_rtc_init_irq(struct retu_rtc *rtc)
-+{
-+	int irq;
-+	int ret;
-+
-+	irq = platform_get_irq(to_platform_device(rtc->dev), 0);
-+	rtc->irq_rtcs = irq;
-+
-+	irq = platform_get_irq(to_platform_device(rtc->dev), 1);
-+	rtc->irq_rtca = irq;
-+
-+	ret = request_threaded_irq(rtc->irq_rtcs, NULL, retu_rtc_interrupt,
-+			0, "RTCS", rtc);
-+	if (ret != 0)
-+		return ret;
-+
-+	ret = request_threaded_irq(rtc->irq_rtca, NULL, retu_rtc_interrupt,
-+			0, "RTCA", rtc);
-+	if (ret != 0) {
-+		free_irq(rtc->irq_rtcs, rtc);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int retu_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
-+{
-+	struct retu_rtc		*rtc = dev_get_drvdata(dev);
-+	u16			chmar;
-+
-+	mutex_lock(&rtc->mutex);
-+
-+	chmar = ((alm->time.tm_hour & 0x1f) << 8) | (alm->time.tm_min & 0x3f);
-+	retu_write_reg(rtc->dev, RETU_REG_RTCHMAR, chmar);
-+
-+	mutex_unlock(&rtc->mutex);
-+
-+	return 0;
-+}
-+
-+static int retu_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
-+{
-+	struct retu_rtc		*rtc = dev_get_drvdata(dev);
-+	u16			chmar;
-+
-+	mutex_lock(&rtc->mutex);
-+
-+	chmar = retu_read_reg(rtc->dev, RETU_REG_RTCHMAR);
-+
-+	alm->time.tm_hour	= (chmar >> 8) & 0x1f;
-+	alm->time.tm_min	= chmar & 0x3f;
-+	alm->enabled		= !!rtc->alarm_expired;
-+
-+	mutex_unlock(&rtc->mutex);
-+
-+	return 0;
-+}
-+
-+static int retu_rtc_set_time(struct device *dev, struct rtc_time *tm)
-+{
-+	struct retu_rtc		*rtc = dev_get_drvdata(dev);
-+	u16			dsr;
-+	u16			hmr;
-+
-+	dsr = ((tm->tm_mday & 0xff) << 8) | (tm->tm_hour & 0xff);
-+	hmr = ((tm->tm_min & 0xff) << 8) | (tm->tm_sec & 0xff);
-+
-+	mutex_lock(&rtc->mutex);
-+
-+	retu_write_reg(rtc->dev, RETU_REG_RTCDSR, dsr);
-+	retu_write_reg(rtc->dev, RETU_REG_RTCHMR, hmr);
-+
-+	mutex_unlock(&rtc->mutex);
-+
-+	return 0;
-+}
-+
-+static int retu_rtc_read_time(struct device *dev, struct rtc_time *tm)
-+{
-+	struct retu_rtc		*rtc = dev_get_drvdata(dev);
-+	u16			dsr;
-+	u16			hmr;
-+
-+	/*
-+	 * DSR holds days and hours
-+	 * HMR hols minutes and seconds
-+	 *
-+	 * both are 16 bit registers with 8-bit for each field.
-+	 */
-+
-+	mutex_lock(&rtc->mutex);
-+
-+	dsr	= retu_read_reg(rtc->dev, RETU_REG_RTCDSR);
-+	hmr	= retu_read_reg(rtc->dev, RETU_REG_RTCHMR);
-+
-+	tm->tm_sec	= hmr & 0xff;
-+	tm->tm_min	= hmr >> 8;
-+	tm->tm_hour	= dsr & 0xff;
-+	tm->tm_mday	= dsr >> 8;
-+
-+	mutex_unlock(&rtc->mutex);
-+
-+	return 0;
-+}
-+
-+static struct rtc_class_ops retu_rtc_ops = {
-+	.read_time		= retu_rtc_read_time,
-+	.set_time		= retu_rtc_set_time,
-+	.read_alarm		= retu_rtc_read_alarm,
-+	.set_alarm		= retu_rtc_set_alarm,
-+};
-+
-+static int __devinit retu_rtc_probe(struct platform_device *pdev)
-+{
-+	struct retu_rtc		*rtc;
-+	int			r;
-+
-+	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
-+	if (!rtc) {
-+		dev_err(&pdev->dev, "not enough memory\n");
-+		r = -ENOMEM;
-+		goto err0;
-+	}
-+
-+	rtc->dev = &pdev->dev;
-+	platform_set_drvdata(pdev, rtc);
-+	mutex_init(&rtc->mutex);
-+
-+	rtc->alarm_expired = retu_read_reg(rtc->dev, RETU_REG_IDR) &
-+		(0x1 << RETU_INT_RTCA);
-+
-+	r = retu_rtc_init_irq(rtc);
-+	if (r < 0) {
-+		dev_err(&pdev->dev, "failed to request retu irq\n");
-+		goto err1;
-+	}
-+
-+	/* If the calibration register is zero, we've probably lost power */
-+	if (!(retu_read_reg(rtc->dev, RETU_REG_RTCCALR) & 0x00ff))
-+		retu_rtc_do_reset(rtc);
-+
-+	rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &
-+			retu_rtc_ops, THIS_MODULE);
-+	if (IS_ERR(rtc->rtc)) {
-+		dev_err(&pdev->dev, "can't register RTC device\n");
-+		goto err2;
-+	}
-+
-+	return 0;
-+
-+err2:
-+	free_irq(rtc->irq_rtcs, rtc);
-+	free_irq(rtc->irq_rtca, rtc);
-+
-+err1:
-+	kfree(rtc);
-+
-+err0:
-+	return r;
-+}
-+
-+static int __devexit retu_rtc_remove(struct platform_device *pdev)
-+{
-+	struct retu_rtc		*rtc = platform_get_drvdata(pdev);
-+
-+	free_irq(rtc->irq_rtcs, rtc);
-+	free_irq(rtc->irq_rtca, rtc);
-+	rtc_device_unregister(rtc->rtc);
-+	kfree(rtc);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver retu_rtc_driver = {
-+	.probe		= retu_rtc_probe,
-+	.remove		= __devexit_p(retu_rtc_remove),
-+	.driver		= {
-+		.name	= "retu-rtc",
-+	},
-+};
-+
-+module_platform_driver(retu_rtc_driver);
-+
-+MODULE_ALIAS("platform:retu-rtc");
-+MODULE_DESCRIPTION("Retu RTC");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Paul Mundt");
-+MODULE_AUTHOR("Igor Stoppa");
-+MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
-+
-diff --git a/drivers/cbus/retu-wdt.c b/drivers/cbus/retu-wdt.c
-new file mode 100644
-index 0000000..7557bc1
---- /dev/null
-+++ b/drivers/cbus/retu-wdt.c
-@@ -0,0 +1,263 @@
-+/**
-+ * drivers/cbus/retu-wdt.c
-+ *
-+ * Driver for Retu watchdog
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Amit Kucheria <amit.kucheria@nokia.com>
-+ *
-+ * Cleanups by Michael Buesch <mb@bu3sch.de> (C) 2011
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/fs.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+
-+#include <linux/completion.h>
-+#include <linux/errno.h>
-+#include <linux/moduleparam.h>
-+#include <linux/miscdevice.h>
-+#include <linux/watchdog.h>
-+
-+#include <asm/uaccess.h>
-+
-+#include <plat/prcm.h>
-+
-+#include "cbus.h"
-+#include "retu.h"
-+
-+/* Watchdog timeout in seconds */
-+#define RETU_WDT_MIN_TIMER 0
-+#define RETU_WDT_DEFAULT_TIMER 32
-+#define RETU_WDT_MAX_TIMER 63
-+
-+struct retu_wdt_dev {
-+	struct device		*dev;
-+	unsigned int		period_val;	/* Current period of watchdog */
-+	unsigned long		users;
-+	struct miscdevice	miscdev;
-+	struct delayed_work	ping_work;
-+	struct mutex		mutex;
-+};
-+
-+
-+static inline void _retu_modify_counter(struct retu_wdt_dev *wdev,
-+					unsigned int new)
-+{
-+	retu_write_reg(wdev->dev, RETU_REG_WATCHDOG, (u16)new);
-+}
-+
-+static int retu_modify_counter(struct retu_wdt_dev *wdev, unsigned int new)
-+{
-+	if (new < RETU_WDT_MIN_TIMER || new > RETU_WDT_MAX_TIMER)
-+		return -EINVAL;
-+
-+	mutex_lock(&wdev->mutex);
-+	wdev->period_val = new;
-+	_retu_modify_counter(wdev, wdev->period_val);
-+	mutex_unlock(&wdev->mutex);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Since retu watchdog cannot be disabled in hardware, we must kick it
-+ * with a timer until userspace watchdog software takes over. Do this
-+ * unless /dev/watchdog is open or CONFIG_WATCHDOG_NOWAYOUT is set.
-+ */
-+static void retu_wdt_ping_enable(struct retu_wdt_dev *wdev)
-+{
-+	_retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+	schedule_delayed_work(&wdev->ping_work,
-+			      round_jiffies_relative(RETU_WDT_DEFAULT_TIMER * HZ));
-+}
-+
-+static void retu_wdt_ping_disable(struct retu_wdt_dev *wdev)
-+{
-+	_retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+	cancel_delayed_work_sync(&wdev->ping_work);
-+}
-+
-+static void retu_wdt_ping_work(struct work_struct *work)
-+{
-+	struct retu_wdt_dev *wdev = container_of(to_delayed_work(work),
-+					struct retu_wdt_dev, ping_work);
-+	retu_wdt_ping_enable(wdev);
-+}
-+
-+static int retu_wdt_open(struct inode *inode, struct file *file)
-+{
-+	struct miscdevice *mdev = file->private_data;
-+	struct retu_wdt_dev *wdev = container_of(mdev, struct retu_wdt_dev, miscdev);
-+
-+	if (test_and_set_bit(0, &wdev->users))
-+		return -EBUSY;
-+
-+	retu_wdt_ping_disable(wdev);
-+
-+	return nonseekable_open(inode, file);
-+}
-+
-+static int retu_wdt_release(struct inode *inode, struct file *file)
-+{
-+	struct miscdevice *mdev = file->private_data;
-+	struct retu_wdt_dev *wdev = container_of(mdev, struct retu_wdt_dev, miscdev);
-+
-+#ifndef CONFIG_WATCHDOG_NOWAYOUT
-+	retu_wdt_ping_enable(wdev);
-+#endif
-+	clear_bit(0, &wdev->users);
-+
-+	return 0;
-+}
-+
-+static ssize_t retu_wdt_write(struct file *file, const char __user *data,
-+						size_t len, loff_t *ppos)
-+{
-+	struct miscdevice *mdev = file->private_data;
-+	struct retu_wdt_dev *wdev = container_of(mdev, struct retu_wdt_dev, miscdev);
-+
-+	if (len)
-+		retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+
-+	return len;
-+}
-+
-+static long retu_wdt_ioctl(struct file *file, unsigned int cmd,
-+			   unsigned long arg)
-+{
-+	struct miscdevice *mdev = file->private_data;
-+	struct retu_wdt_dev *wdev = container_of(mdev, struct retu_wdt_dev, miscdev);
-+	int new_margin;
-+
-+	static const struct watchdog_info ident = {
-+		.identity = "Retu Watchdog",
-+		.options = WDIOF_SETTIMEOUT,
-+		.firmware_version = 0,
-+	};
-+
-+	switch (cmd) {
-+	default:
-+		return -ENOTTY;
-+	case WDIOC_GETSUPPORT:
-+		return copy_to_user((struct watchdog_info __user *)arg, &ident,
-+							sizeof(ident));
-+	case WDIOC_GETSTATUS:
-+		return put_user(0, (int __user *)arg);
-+	case WDIOC_GETBOOTSTATUS:
-+		if (cpu_is_omap16xx())
-+			return put_user(omap_readw(ARM_SYSST),
-+					(int __user *)arg);
-+		if (cpu_is_omap24xx())
-+			return put_user(omap_prcm_get_reset_sources(),
-+					(int __user *)arg);
-+	case WDIOC_KEEPALIVE:
-+		retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+		break;
-+	case WDIOC_SETTIMEOUT:
-+		if (get_user(new_margin, (int __user *)arg))
-+			return -EFAULT;
-+		retu_modify_counter(wdev, new_margin);
-+		/* Fall through */
-+	case WDIOC_GETTIMEOUT:
-+		return put_user(wdev->period_val, (int __user *)arg);
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct file_operations retu_wdt_fops = {
-+	.owner		= THIS_MODULE,
-+	.write		= retu_wdt_write,
-+	.unlocked_ioctl	= retu_wdt_ioctl,
-+	.open		= retu_wdt_open,
-+	.release	= retu_wdt_release,
-+};
-+
-+static int __devinit retu_wdt_probe(struct platform_device *pdev)
-+{
-+	struct retu_wdt_dev *wdev;
-+	int ret;
-+
-+	wdev = kzalloc(sizeof(struct retu_wdt_dev), GFP_KERNEL);
-+	if (!wdev)
-+		return -ENOMEM;
-+
-+	wdev->dev = &pdev->dev;
-+	wdev->period_val = RETU_WDT_DEFAULT_TIMER;
-+	mutex_init(&wdev->mutex);
-+
-+	platform_set_drvdata(pdev, wdev);
-+
-+	wdev->miscdev.parent = &pdev->dev;
-+	wdev->miscdev.minor = WATCHDOG_MINOR;
-+	wdev->miscdev.name = "watchdog";
-+	wdev->miscdev.fops = &retu_wdt_fops;
-+
-+	ret = misc_register(&wdev->miscdev);
-+	if (ret)
-+		goto err_free_wdev;
-+
-+	INIT_DELAYED_WORK(&wdev->ping_work, retu_wdt_ping_work);
-+
-+	/* Kick the watchdog for kernel booting to finish.
-+	 * If nowayout is not set, we start the ping work. */
-+#ifdef CONFIG_WATCHDOG_NOWAYOUT
-+	retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+#else
-+	retu_wdt_ping_enable(wdev);
-+#endif
-+
-+	return 0;
-+
-+err_free_wdev:
-+	kfree(wdev);
-+
-+	return ret;
-+}
-+
-+static int __devexit retu_wdt_remove(struct platform_device *pdev)
-+{
-+	struct retu_wdt_dev *wdev;
-+
-+	wdev = platform_get_drvdata(pdev);
-+	misc_deregister(&wdev->miscdev);
-+	cancel_delayed_work_sync(&wdev->ping_work);
-+	kfree(wdev);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver retu_wdt_driver = {
-+	.probe		= retu_wdt_probe,
-+	.remove		= __devexit_p(retu_wdt_remove),
-+	.driver		= {
-+		.name	= "retu-wdt",
-+	},
-+};
-+
-+module_platform_driver(retu_wdt_driver);
-+
-+MODULE_ALIAS("platform:retu-wdt");
-+MODULE_DESCRIPTION("Retu WatchDog");
-+MODULE_AUTHOR("Amit Kucheria");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/cbus/retu.c b/drivers/cbus/retu.c
-new file mode 100644
-index 0000000..25fa405
---- /dev/null
-+++ b/drivers/cbus/retu.c
-@@ -0,0 +1,532 @@
-+/**
-+ * drivers/cbus/retu.c
-+ *
-+ * Support functions for Retu ASIC
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
-+ *	      David Weinehall <david.weinehall@nokia.com>, and
-+ *	      Mikko Ylinen <mikko.k.ylinen@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+
-+#include <linux/slab.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/device.h>
-+#include <linux/mutex.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/cbus.h>
-+
-+#include <asm/bitops.h>
-+
-+#include "cbus.h"
-+#include "retu.h"
-+
-+struct retu {
-+	/* Device lock */
-+	struct mutex		mutex;
-+	struct device		*dev;
-+
-+	struct irq_chip		irq_chip;
-+
-+	int			irq_base;
-+	int			irq_end;
-+
-+	int			irq;
-+
-+	int			mask;
-+	bool			mask_pending;
-+
-+	bool			is_vilma;
-+};
-+
-+static struct retu *the_retu;
-+
-+/**
-+ * __retu_read_reg - Read a value from a register in Retu
-+ * @retu: pointer to retu structure
-+ * @reg: the register address to read from
-+ */
-+static int __retu_read_reg(struct retu *retu, unsigned reg)
-+{
-+	return cbus_read_reg(retu->dev, CBUS_RETU_DEVICE_ID, reg);
-+}
-+
-+/**
-+ * __retu_write_reg - Writes a value to a register in Retu
-+ * @retu: pointer to retu structure
-+ * @reg: the register address to write to
-+ * @val: the value to write to the register
-+ */
-+static void __retu_write_reg(struct retu *retu, unsigned reg, u16 val)
-+{
-+	cbus_write_reg(retu->dev, CBUS_RETU_DEVICE_ID, reg, val);
-+}
-+
-+/**
-+ * retu_read_reg - Read a value from a register in Retu
-+ * @child: device pointer for the calling child
-+ * @reg: the register to read from
-+ *
-+ * This function returns the contents of the specified register
-+ */
-+int retu_read_reg(struct device *child, unsigned reg)
-+{
-+	struct retu		*retu = dev_get_drvdata(child->parent);
-+
-+	return __retu_read_reg(retu, reg);
-+}
-+EXPORT_SYMBOL_GPL(retu_read_reg);
-+
-+/**
-+ * retu_write_reg - Write a value to a register in Retu
-+ * @child: the pointer to our calling child
-+ * @reg: the register to write to
-+ * @val: the value to write to the register
-+ *
-+ * This function writes a value to the specified register
-+ */
-+void retu_write_reg(struct device *child, unsigned reg, u16 val)
-+{
-+	struct retu		*retu = dev_get_drvdata(child->parent);
-+
-+	mutex_lock(&retu->mutex);
-+	__retu_write_reg(retu, reg, val);
-+	mutex_unlock(&retu->mutex);
-+}
-+EXPORT_SYMBOL_GPL(retu_write_reg);
-+
-+/**
-+ * retu_set_clear_reg_bits - helper function to read/set/clear bits
-+ * @child: device pointer to calling child
-+ * @reg: the register address
-+ * @set: mask for setting bits
-+ * @clear: mask for clearing bits
-+ */
-+void retu_set_clear_reg_bits(struct device *child, unsigned reg, u16 set,
-+		u16 clear)
-+{
-+	struct retu		*retu = dev_get_drvdata(child->parent);
-+	u16			w;
-+
-+	mutex_lock(&retu->mutex);
-+	w = __retu_read_reg(retu, reg);
-+	w &= ~clear;
-+	w |= set;
-+	__retu_write_reg(retu, reg, w);
-+	mutex_unlock(&retu->mutex);
-+}
-+EXPORT_SYMBOL_GPL(retu_set_clear_reg_bits);
-+
-+#define ADC_MAX_CHAN_NUMBER	13
-+
-+/**
-+ * retu_read_adc - Reads AD conversion result
-+ * @child: device pointer to calling child
-+ * @channel: the ADC channel to read from
-+ */
-+int retu_read_adc(struct device *child, int channel)
-+{
-+	struct retu		*retu = dev_get_drvdata(child->parent);
-+	int			res;
-+
-+	if (!retu)
-+		return -ENODEV;
-+
-+	if (channel < 0 || channel > ADC_MAX_CHAN_NUMBER)
-+		return -EINVAL;
-+
-+	mutex_lock(&retu->mutex);
-+
-+	if ((channel == 8) && retu->is_vilma) {
-+		int scr = __retu_read_reg(retu, RETU_REG_ADCSCR);
-+		int ch = (__retu_read_reg(retu, RETU_REG_ADCR) >> 10) & 0xf;
-+		if (((scr & 0xff) != 0) && (ch != 8))
-+			__retu_write_reg(retu, RETU_REG_ADCSCR, (scr & ~0xff));
-+	}
-+
-+	/* Select the channel and read result */
-+	__retu_write_reg(retu, RETU_REG_ADCR, channel << 10);
-+	res = __retu_read_reg(retu, RETU_REG_ADCR) & 0x3ff;
-+
-+	if (retu->is_vilma)
-+		__retu_write_reg(retu, RETU_REG_ADCR, (1 << 13));
-+
-+	/* Unlock retu */
-+	mutex_unlock(&retu->mutex);
-+
-+	return res;
-+}
-+EXPORT_SYMBOL_GPL(retu_read_adc);
-+
-+static irqreturn_t retu_irq_handler(int irq, void *_retu)
-+{
-+	struct retu		*retu = _retu;
-+
-+	u16			idr;
-+	u16			imr;
-+
-+	mutex_lock(&retu->mutex);
-+	idr = __retu_read_reg(retu, RETU_REG_IDR);
-+	imr = __retu_read_reg(retu, RETU_REG_IMR);
-+	idr &= ~imr;
-+	__retu_write_reg(retu, RETU_REG_IDR, idr);
-+	mutex_unlock(&retu->mutex);
-+
-+	if (!idr) {
-+		dev_vdbg(retu->dev, "No IRQ, spurious?\n");
-+		return IRQ_NONE;
-+	}
-+
-+	while (idr) {
-+		unsigned long	pending = __ffs(idr);
-+		unsigned int	irq;
-+
-+		idr &= ~BIT(pending);
-+		irq = pending + retu->irq_base;
-+		handle_nested_irq(irq);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+/* -------------------------------------------------------------------------- */
-+
-+static void retu_irq_mask(struct irq_data *data)
-+{
-+	struct retu		*retu = irq_data_get_irq_chip_data(data);
-+	int			irq = data->irq;
-+
-+	retu->mask |= (1 << (irq - retu->irq_base));
-+	retu->mask_pending = true;
-+}
-+
-+static void retu_irq_unmask(struct irq_data *data)
-+{
-+	struct retu		*retu = irq_data_get_irq_chip_data(data);
-+	int			irq = data->irq;
-+
-+	retu->mask &= ~(1 << (irq - retu->irq_base));
-+	retu->mask_pending = true;
-+
-+}
-+
-+static void retu_bus_lock(struct irq_data *data)
-+{
-+	struct retu		*retu = irq_data_get_irq_chip_data(data);
-+
-+	mutex_lock(&retu->mutex);
-+}
-+
-+static void retu_bus_sync_unlock(struct irq_data *data)
-+{
-+	struct retu		*retu = irq_data_get_irq_chip_data(data);
-+
-+	if (retu->mask_pending) {
-+		__retu_write_reg(retu, RETU_REG_IMR, retu->mask);
-+		retu->mask_pending = false;
-+	}
-+
-+	mutex_unlock(&retu->mutex);
-+}
-+
-+static inline void retu_irq_setup(int irq)
-+{
-+#ifdef CONFIG_ARM
-+	set_irq_flags(irq, IRQF_VALID);
-+#else
-+	irq_set_noprobe(irq);
-+#endif
-+}
-+
-+static void retu_irq_init(struct retu *retu)
-+{
-+	int			base = retu->irq_base;
-+	int			end = retu->irq_end;
-+	int			irq;
-+
-+	for (irq = base; irq < end; irq++) {
-+		irq_set_chip_data(irq, retu);
-+		irq_set_chip(irq, &retu->irq_chip);
-+		irq_set_nested_thread(irq, 1);
-+		retu_irq_setup(irq);
-+	}
-+}
-+
-+static void retu_irq_exit(struct retu *retu)
-+{
-+	int			base = retu->irq_base;
-+	int			end = retu->irq_end;
-+	int			irq;
-+
-+	for (irq = base; irq < end; irq++) {
-+#ifdef CONFIG_ARM
-+		set_irq_flags(irq, 0);
-+#endif
-+		irq_set_chip_and_handler(irq, NULL, NULL);
-+		irq_set_chip_data(irq, NULL);
-+	}
-+}
-+
-+/* -------------------------------------------------------------------------- */
-+
-+/**
-+ * retu_power_off - Shut down power to system
-+ *
-+ * This function puts the system in power off state
-+ */
-+static void retu_power_off(void)
-+{
-+	struct retu		*retu = the_retu;
-+	unsigned		reg;
-+
-+	reg = __retu_read_reg(retu, RETU_REG_CC1);
-+
-+	/* Ignore power button state */
-+	__retu_write_reg(retu, RETU_REG_CC1, reg | 2);
-+	/* Expire watchdog immediately */
-+	__retu_write_reg(retu, RETU_REG_WATCHDOG, 0);
-+	/* Wait for poweroff*/
-+	for (;;);
-+}
-+
-+static struct resource generic_resources[] = {
-+	{
-+		.start	= -EINVAL,	/* fixed later */
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+	{
-+		.start	= -EINVAL,	/* fixed later */
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+};
-+
-+/**
-+ * retu_allocate_child - Allocates one Retu child
-+ * @name: name of new child
-+ * @parent: parent device for this child
-+ */
-+static struct device *retu_allocate_child(char *name, struct device *parent,
-+		int irq_base, int irq1, int irq2, int num)
-+{
-+	struct platform_device		*pdev;
-+	int				status;
-+
-+	pdev = platform_device_alloc(name, -1);
-+	if (!pdev) {
-+		dev_dbg(parent, "can't allocate %s\n", name);
-+		goto err;
-+	}
-+
-+	pdev->dev.parent = parent;
-+
-+	if (num) {
-+		generic_resources[0].start = irq_base + irq1;
-+		generic_resources[1].start = irq_base + irq2;
-+
-+		status = platform_device_add_resources(pdev,
-+				generic_resources, num);
-+		if (status < 0) {
-+			dev_dbg(parent, "can't add resources to %s\n", name);
-+			goto err;
-+		}
-+	}
-+
-+	status = platform_device_add(pdev);
-+	if (status < 0) {
-+		dev_dbg(parent, "can't add %s\n", name);
-+		goto err;
-+	}
-+
-+	return &pdev->dev;
-+
-+err:
-+	platform_device_put(pdev);
-+
-+	return NULL;
-+}
-+
-+/**
-+ * retu_allocate_children - Allocates Retu's children
-+ */
-+static int retu_allocate_children(struct device *parent, int irq_base)
-+{
-+	struct device	*child;
-+
-+	child = retu_allocate_child("retu-pwrbutton", parent, irq_base,
-+			RETU_INT_PWR, -1, 1);
-+	if (!child)
-+		return -ENOMEM;
-+
-+	child = retu_allocate_child("retu-headset", parent, irq_base,
-+			RETU_INT_HOOK, -1, 1);
-+	if (!child)
-+		return -ENOMEM;
-+
-+	child = retu_allocate_child("retu-rtc", parent, irq_base,
-+			RETU_INT_RTCS, RETU_INT_RTCA, 2);
-+	if (!child)
-+		return -ENOMEM;
-+
-+	child = retu_allocate_child("retu-wdt", parent, -1, -1, -1, 0);
-+	if (!child)
-+		return -ENOMEM;
-+
-+	return 0;
-+}
-+
-+/**
-+ * retu_probe - Probe for Retu ASIC
-+ * @dev: the Retu device
-+ *
-+ * Probe for the Retu ASIC and allocate memory
-+ * for its device-struct if found
-+ */
-+static int __devinit retu_probe(struct platform_device *pdev)
-+{
-+	struct irq_chip	*chip;
-+	struct retu	*retu;
-+
-+	int		ret = -ENOMEM;
-+	int		rev;
-+
-+	retu = kzalloc(sizeof(*retu), GFP_KERNEL);
-+	if (!retu) {
-+		dev_err(&pdev->dev, "not enough memory\n");
-+		goto err0;
-+	}
-+
-+	platform_set_drvdata(pdev, retu);
-+
-+	ret = irq_alloc_descs(-1, 0, MAX_RETU_IRQ_HANDLERS, 0);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to allocate IRQ descs\n");
-+		goto err1;
-+	}
-+
-+	chip = &retu->irq_chip;
-+
-+	chip->name	= "retu",
-+	chip->irq_bus_lock = retu_bus_lock,
-+	chip->irq_bus_sync_unlock = retu_bus_sync_unlock,
-+	chip->irq_mask	= retu_irq_mask,
-+	chip->irq_unmask = retu_irq_unmask,
-+
-+	retu->irq	= platform_get_irq(pdev, 0);
-+	retu->irq_base	= ret;
-+	retu->irq_end	= ret + MAX_RETU_IRQ_HANDLERS;
-+	retu->dev	= &pdev->dev;
-+
-+	the_retu	= retu;
-+
-+	mutex_init(&retu->mutex);
-+
-+	retu_irq_init(retu);
-+
-+	rev = __retu_read_reg(retu, RETU_REG_ASICR) & 0xff;
-+	if (rev & (1 << 7))
-+		retu->is_vilma = true;
-+
-+	dev_info(&pdev->dev, "%s v%d.%d found\n",
-+			retu->is_vilma ? "Vilma" : "Retu",
-+			(rev >> 4) & 0x07, rev & 0x0f);
-+
-+	/* Mask all RETU interrupts */
-+	retu->mask = 0xffff;
-+	__retu_write_reg(retu, RETU_REG_IMR, retu->mask);
-+
-+	ret = request_threaded_irq(retu->irq, NULL, retu_irq_handler,
-+			IRQF_ONESHOT, "retu", retu);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "Unable to register IRQ handler\n");
-+		goto err2;
-+	}
-+
-+	irq_set_irq_wake(retu->irq, 1);
-+
-+	/* Register power off function */
-+	pm_power_off = retu_power_off;
-+
-+	ret = retu_allocate_children(&pdev->dev, retu->irq_base);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "Unable to allocate Retu children\n");
-+		goto err3;
-+	}
-+
-+	return 0;
-+
-+err3:
-+	pm_power_off = NULL;
-+	free_irq(retu->irq, retu);
-+
-+err2:
-+	retu_irq_exit(retu);
-+	irq_free_descs(retu->irq_base, MAX_RETU_IRQ_HANDLERS);
-+
-+err1:
-+	kfree(retu);
-+	the_retu = NULL;
-+
-+err0:
-+	return ret;
-+}
-+
-+static int __devexit retu_remove(struct platform_device *pdev)
-+{
-+	struct retu		*retu = platform_get_drvdata(pdev);
-+
-+	pm_power_off = NULL;
-+	the_retu = NULL;
-+
-+	free_irq(retu->irq, retu);
-+	retu_irq_exit(retu);
-+	irq_free_descs(retu->irq_base, MAX_RETU_IRQ_HANDLERS);
-+	kfree(retu);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id retu_match_table[] __devinitconst = {
-+	{
-+		.compatible = "nokia,retu",
-+	},
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, retu_match);
-+
-+static struct platform_driver retu_driver = {
-+	.probe		= retu_probe,
-+	.remove		= __devexit_p(retu_remove),
-+	.driver		= {
-+		.name	= "retu",
-+		.of_match_table = retu_match_table,
-+	},
-+};
-+
-+module_platform_driver(retu_driver);
-+
-+MODULE_ALIAS("platform:retu");
-+MODULE_DESCRIPTION("Retu ASIC control");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä");
-+MODULE_AUTHOR("David Weinehall");
-+MODULE_AUTHOR("Mikko Ylinen");
-diff --git a/drivers/cbus/retu.h b/drivers/cbus/retu.h
-new file mode 100644
-index 0000000..d35ea77
---- /dev/null
-+++ b/drivers/cbus/retu.h
-@@ -0,0 +1,85 @@
-+/**
-+ * drivers/cbus/retu.h
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
-+ *	      David Weinehall <david.weinehall@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#ifndef __DRIVERS_CBUS_RETU_H
-+#define __DRIVERS_CBUS_RETU_H
-+
-+#include <linux/types.h>
-+
-+/* Registers */
-+#define RETU_REG_ASICR		0x00	/* ASIC ID & revision */
-+#define RETU_REG_IDR		0x01	/* Interrupt ID */
-+#define RETU_REG_IMR		0x02	/* Interrupt mask */
-+#define RETU_REG_RTCDSR		0x03	/* RTC seconds register */
-+#define RETU_REG_RTCHMR		0x04	/* RTC hours and minutes register */
-+#define RETU_REG_RTCHMAR	0x05	/* RTC hours and minutes alarm and time set register */
-+#define RETU_REG_RTCCALR	0x06	/* RTC calibration register */
-+#define RETU_REG_ADCR		0x08	/* ADC result */
-+#define RETU_REG_ADCSCR		0x09	/* ADC sample ctrl */
-+#define RETU_REG_CC1		0x0d	/* Common control register 1 */
-+#define RETU_REG_CC2		0x0e	/* Common control register 2 */
-+#define RETU_REG_CTRL_CLR	0x0f	/* Regulator clear register */
-+#define RETU_REG_CTRL_SET	0x10	/* Regulator set register */
-+#define RETU_REG_STATUS		0x16	/* Status register */
-+#define  RETU_REG_STATUS_BATAVAIL	0x0100 /* Battery available */
-+#define  RETU_REG_STATUS_CHGPLUG	0x1000 /* Charger is plugged in */
-+#define RETU_REG_WATCHDOG	0x17	/* Watchdog register */
-+#define RETU_REG_AUDTXR		0x18	/* Audio Codec Tx register */
-+#define RETU_REG_MAX		0x1f
-+
-+/* Interrupt sources */
-+#define RETU_INT_PWR		0
-+#define RETU_INT_CHAR		1
-+#define RETU_INT_RTCS		2
-+#define RETU_INT_RTCM		3
-+#define RETU_INT_RTCD		4
-+#define RETU_INT_RTCA		5
-+#define RETU_INT_HOOK		6
-+#define RETU_INT_HEAD		7
-+#define RETU_INT_ADCS		8
-+
-+#define	MAX_RETU_IRQ_HANDLERS	16
-+
-+/* ADC channels */
-+#define RETU_ADC_GND		0x00 /* Ground */
-+#define RETU_ADC_BSI		0x01 /* Battery Size Indicator */
-+#define RETU_ADC_BATTEMP	0x02 /* Battery temperature */
-+#define RETU_ADC_CHGVOLT	0x03 /* Charger voltage */
-+#define RETU_ADC_HEADSET	0x04 /* Headset detection */
-+#define RETU_ADC_HOOKDET	0x05 /* Hook detection */
-+#define RETU_ADC_RFGP		0x06 /* RF GP */
-+#define RETU_ADC_WBTX		0x07 /* Wideband Tx detection */
-+#define RETU_ADC_BATTVOLT	0x08 /* Battery voltage measurement */
-+#define RETU_ADC_GND2		0x09 /* Ground */
-+#define RETU_ADC_LIGHTSENS	0x0A /* Light sensor */
-+#define RETU_ADC_LIGHTTEMP	0x0B /* Light sensor temperature */
-+#define RETU_ADC_BKUPVOLT	0x0C /* Backup battery voltage */
-+#define RETU_ADC_TEMP		0x0D /* RETU temperature */
-+
-+
-+int retu_read_reg(struct device *child, unsigned reg);
-+void retu_write_reg(struct device *child, unsigned reg, u16 val);
-+void retu_set_clear_reg_bits(struct device *child, unsigned reg, u16 set,
-+		u16 clear);
-+int retu_read_adc(struct device *child, int channel);
-+
-+#endif /* __DRIVERS_CBUS_RETU_H */
-diff --git a/drivers/cbus/tahvo-usb.c b/drivers/cbus/tahvo-usb.c
-new file mode 100644
-index 0000000..15da853
---- /dev/null
-+++ b/drivers/cbus/tahvo-usb.c
-@@ -0,0 +1,741 @@
-+/**
-+ * drivers/cbus/tahvo-usb.c
-+ *
-+ * Tahvo USB transeiver
-+ *
-+ * Copyright (C) 2005-2006 Nokia Corporation
-+ *
-+ * Parts copied from drivers/i2c/chips/isp1301_omap.c
-+ * Copyright (C) 2004 Texas Instruments
-+ * Copyright (C) 2004 David Brownell
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
-+ *	      Tony Lindgren <tony@atomide.com>, and
-+ *	      Timo Teräs <timo.teras@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/usb/ch9.h>
-+#include <linux/usb/gadget.h>
-+#include <linux/usb.h>
-+#include <linux/usb/otg.h>
-+#include <linux/i2c.h>
-+#include <linux/workqueue.h>
-+#include <linux/kobject.h>
-+#include <linux/clk.h>
-+#include <linux/mutex.h>
-+
-+#include <asm/irq.h>
-+#include <plat/usb.h>
-+
-+#include "cbus.h"
-+#include "tahvo.h"
-+
-+#define DRIVER_NAME     "tahvo-usb"
-+
-+#define USBR_SLAVE_CONTROL	(1 << 8)
-+#define USBR_VPPVIO_SW		(1 << 7)
-+#define USBR_SPEED		(1 << 6)
-+#define USBR_REGOUT		(1 << 5)
-+#define USBR_MASTER_SW2		(1 << 4)
-+#define USBR_MASTER_SW1		(1 << 3)
-+#define USBR_SLAVE_SW		(1 << 2)
-+#define USBR_NSUSPEND		(1 << 1)
-+#define USBR_SEMODE		(1 << 0)
-+
-+/* bits in OTG_CTRL */
-+
-+/* Bits that are controlled by OMAP OTG and are read-only */
-+#define OTG_CTRL_OMAP_MASK	(OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|\
-+				OTG_PD_VBUS|OTG_PU_VBUS|OTG_PU_ID)
-+/* Bits that are controlled by transceiver */
-+#define OTG_CTRL_XCVR_MASK	(OTG_ASESSVLD|OTG_BSESSEND|\
-+				OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
-+/* Bits that are controlled by system */
-+#define OTG_CTRL_SYS_MASK	(OTG_A_BUSREQ|OTG_A_SETB_HNPEN|OTG_B_BUSREQ|\
-+				OTG_B_HNPEN|OTG_BUSDROP)
-+
-+#if defined(CONFIG_USB_OHCI_HCD) && !defined(CONFIG_USB_OTG)
-+#error tahvo-otg.c does not work with OCHI yet!
-+#endif
-+
-+#define TAHVO_MODE_HOST		0
-+#define TAHVO_MODE_PERIPHERAL	1
-+
-+#ifdef CONFIG_USB_OTG
-+#define TAHVO_MODE(tu)		(tu)->tahvo_mode
-+#elif defined(CONFIG_USB_GADGET_OMAP)
-+#define TAHVO_MODE(tu)		TAHVO_MODE_PERIPHERAL
-+#else
-+#define TAHVO_MODE(tu)		TAHVO_MODE_HOST
-+#endif
-+
-+struct tahvo_usb {
-+	struct device		*dev;
-+	struct platform_device *pt_dev;
-+	struct otg_transceiver otg;
-+	int vbus_state;
-+	struct mutex serialize;
-+#ifdef CONFIG_USB_OTG
-+	int tahvo_mode;
-+#endif
-+	struct clk *ick;
-+
-+	int		irq;
-+};
-+static struct tahvo_usb *tahvo_usb_device;
-+
-+/*
-+ * ---------------------------------------------------------------------------
-+ * OTG related functions
-+ *
-+ * These shoud be separated into omap-otg.c driver module, as they are used
-+ * by various transceivers. These functions are needed in the UDC-only case
-+ * as well. These functions are copied from GPL isp1301_omap.c
-+ * ---------------------------------------------------------------------------
-+ */
-+static struct platform_device *tahvo_otg_dev;
-+
-+static irqreturn_t omap_otg_irq(int irq, void *arg)
-+{
-+	u16 otg_irq;
-+
-+	otg_irq = omap_readw(OTG_IRQ_SRC);
-+	if (otg_irq & OPRT_CHG) {
-+		omap_writew(OPRT_CHG, OTG_IRQ_SRC);
-+	} else if (otg_irq & B_SRP_TMROUT) {
-+		omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
-+	} else if (otg_irq & B_HNP_FAIL) {
-+		omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
-+	} else if (otg_irq & A_SRP_DETECT) {
-+		omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
-+	} else if (otg_irq & A_REQ_TMROUT) {
-+		omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
-+	} else if (otg_irq & A_VBUS_ERR) {
-+		omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
-+	} else if (otg_irq & DRIVER_SWITCH) {
-+#ifdef CONFIG_USB_OTG
-+		if ((!(omap_readl(OTG_CTRL) & OTG_DRIVER_SEL)) &&
-+		   tu->otg.host && tu->otg.state == OTG_STATE_A_HOST) {
-+			/* role is host */
-+			usb_bus_start_enum(tu->otg.host,
-+					   tu->otg.host->otg_port);
-+		}
-+#endif
-+		omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
-+	} else
-+		return IRQ_NONE;
-+
-+	return IRQ_HANDLED;
-+
-+}
-+
-+static int tahvo_otg_init(void)
-+{
-+	u32 l;
-+
-+#ifdef CONFIG_USB_OTG
-+	if (!tahvo_otg_dev) {
-+		printk("tahvo-usb: no tahvo_otg_dev\n");
-+		return -ENODEV;
-+	}
-+#endif
-+
-+	l = omap_readl(OTG_SYSCON_1);
-+	l &= ~OTG_IDLE_EN;
-+	omap_writel(l, OTG_SYSCON_1);
-+	udelay(100);
-+
-+	/* some of these values are board-specific... */
-+	l = omap_readl(OTG_SYSCON_2);
-+	l |= OTG_EN
-+		/* for B-device: */
-+		| SRP_GPDATA		/* 9msec Bdev D+ pulse */
-+		| SRP_GPDVBUS		/* discharge after VBUS pulse */
-+		// | (3 << 24)		/* 2msec VBUS pulse */
-+		/* for A-device: */
-+		| (0 << 20)		/* 200ms nominal A_WAIT_VRISE timer */
-+		| SRP_DPW		/* detect 167+ns SRP pulses */
-+		| SRP_DATA | SRP_VBUS;	/* accept both kinds of SRP pulse */
-+	omap_writel(l, OTG_SYSCON_2);
-+
-+	omap_writew(DRIVER_SWITCH | OPRT_CHG
-+			| B_SRP_TMROUT | B_HNP_FAIL
-+				  | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT,
-+					OTG_IRQ_EN);
-+	l = omap_readl(OTG_SYSCON_2);
-+	l |= OTG_EN;
-+	omap_writel(l, OTG_SYSCON_2);
-+
-+	return 0;
-+}
-+
-+static int __devinit omap_otg_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+
-+	tahvo_otg_dev = pdev;
-+	ret = tahvo_otg_init();
-+	if (ret != 0) {
-+		printk(KERN_ERR "tahvo-usb: tahvo_otg_init failed\n");
-+		return ret;
-+	}
-+
-+	return request_irq(tahvo_otg_dev->resource[1].start,
-+			   omap_otg_irq, IRQF_DISABLED, DRIVER_NAME,
-+			   tahvo_usb_device);
-+}
-+
-+static int __devexit omap_otg_remove(struct platform_device *pdev)
-+{
-+	free_irq(tahvo_otg_dev->resource[1].start, tahvo_usb_device);
-+	tahvo_otg_dev = NULL;
-+
-+	return 0;
-+}
-+
-+struct platform_driver omap_otg_driver = {
-+	.probe		= omap_otg_probe,
-+	.remove		= __devexit_p(omap_otg_remove),
-+	.driver		= {
-+		.name	= "omap_otg",
-+	},
-+};
-+
-+/*
-+ * ---------------------------------------------------------------------------
-+ * Tahvo related functions
-+ * These are Nokia proprietary code, except for the OTG register settings,
-+ * which are copied from isp1301.c
-+ * ---------------------------------------------------------------------------
-+ */
-+static ssize_t vbus_state_show(struct device *device,
-+			       struct device_attribute *attr, char *buf)
-+{
-+	struct tahvo_usb *tu = dev_get_drvdata(device);
-+	return sprintf(buf, "%d\n", tu->vbus_state);
-+}
-+static DEVICE_ATTR(vbus_state, 0444, vbus_state_show, NULL);
-+
-+int vbus_active = 0;
-+
-+static void check_vbus_state(struct tahvo_usb *tu)
-+{
-+	int reg, prev_state;
-+
-+	reg = tahvo_read_reg(tu->dev, TAHVO_REG_IDSR);
-+	if (reg & 0x01) {
-+		u32 l;
-+
-+		vbus_active = 1;
-+		switch (tu->otg.state) {
-+		case OTG_STATE_B_IDLE:
-+			/* Enable the gadget driver */
-+			if (tu->otg.gadget)
-+				usb_gadget_vbus_connect(tu->otg.gadget);
-+			/* Set B-session valid and not B-sessio ended to indicate
-+			 * Vbus to be ok. */
-+			l = omap_readl(OTG_CTRL);
-+			l &= ~OTG_BSESSEND;
-+			l |= OTG_BSESSVLD;
-+			omap_writel(l, OTG_CTRL);
-+
-+			tu->otg.state = OTG_STATE_B_PERIPHERAL;
-+			break;
-+		case OTG_STATE_A_IDLE:
-+			/* Session is now valid assuming the USB hub is driving Vbus */
-+			tu->otg.state = OTG_STATE_A_HOST;
-+			break;
-+		default:
-+			break;
-+		}
-+		printk("USB cable connected\n");
-+	} else {
-+		switch (tu->otg.state) {
-+		case OTG_STATE_B_PERIPHERAL:
-+			if (tu->otg.gadget)
-+				usb_gadget_vbus_disconnect(tu->otg.gadget);
-+			tu->otg.state = OTG_STATE_B_IDLE;
-+			break;
-+		case OTG_STATE_A_HOST:
-+			tu->otg.state = OTG_STATE_A_IDLE;
-+			break;
-+		default:
-+			break;
-+		}
-+		printk("USB cable disconnected\n");
-+		vbus_active = 0;
-+	}
-+
-+	prev_state = tu->vbus_state;
-+	tu->vbus_state = reg & 0x01;
-+	if (prev_state != tu->vbus_state)
-+		sysfs_notify(&tu->pt_dev->dev.kobj, NULL, "vbus_state");
-+}
-+
-+static void tahvo_usb_become_host(struct tahvo_usb *tu)
-+{
-+	u32 l;
-+
-+	/* Clear system and transceiver controlled bits
-+	 * also mark the A-session is always valid */
-+	tahvo_otg_init();
-+
-+	l = omap_readl(OTG_CTRL);
-+	l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK);
-+	l |= OTG_ASESSVLD;
-+	omap_writel(l, OTG_CTRL);
-+
-+	/* Power up the transceiver in USB host mode */
-+	tahvo_write_reg(tu->dev, TAHVO_REG_USBR, USBR_REGOUT | USBR_NSUSPEND |
-+			USBR_MASTER_SW2 | USBR_MASTER_SW1);
-+	tu->otg.state = OTG_STATE_A_IDLE;
-+
-+	check_vbus_state(tu);
-+}
-+
-+static void tahvo_usb_stop_host(struct tahvo_usb *tu)
-+{
-+	tu->otg.state = OTG_STATE_A_IDLE;
-+}
-+
-+static void tahvo_usb_become_peripheral(struct tahvo_usb *tu)
-+{
-+	u32 l;
-+
-+	/* Clear system and transceiver controlled bits
-+	 * and enable ID to mark peripheral mode and
-+	 * BSESSEND to mark no Vbus */
-+	tahvo_otg_init();
-+	l = omap_readl(OTG_CTRL);
-+	l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD);
-+	l |= OTG_ID | OTG_BSESSEND;
-+	omap_writel(l, OTG_CTRL);
-+
-+	/* Power up transceiver and set it in USB perhiperal mode */
-+	tahvo_write_reg(tu->dev, TAHVO_REG_USBR, USBR_SLAVE_CONTROL | USBR_REGOUT | USBR_NSUSPEND | USBR_SLAVE_SW);
-+	tu->otg.state = OTG_STATE_B_IDLE;
-+
-+	check_vbus_state(tu);
-+}
-+
-+static void tahvo_usb_stop_peripheral(struct tahvo_usb *tu)
-+{
-+	u32 l;
-+
-+	l = omap_readl(OTG_CTRL);
-+	l &= ~OTG_BSESSVLD;
-+	l |= OTG_BSESSEND;
-+	omap_writel(l, OTG_CTRL);
-+
-+	if (tu->otg.gadget)
-+		usb_gadget_vbus_disconnect(tu->otg.gadget);
-+	tu->otg.state = OTG_STATE_B_IDLE;
-+
-+}
-+
-+static void tahvo_usb_power_off(struct tahvo_usb *tu)
-+{
-+	u32 l;
-+	int id;
-+
-+	/* Disable gadget controller if any */
-+	if (tu->otg.gadget)
-+		usb_gadget_vbus_disconnect(tu->otg.gadget);
-+
-+	/* Disable OTG and interrupts */
-+	if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
-+		id = OTG_ID;
-+	else
-+		id = 0;
-+	l = omap_readl(OTG_CTRL);
-+	l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD);
-+	l |= id | OTG_BSESSEND;
-+	omap_writel(l, OTG_CTRL);
-+	omap_writew(0, OTG_IRQ_EN);
-+
-+	l = omap_readl(OTG_SYSCON_2);
-+	l &= ~OTG_EN;
-+	omap_writel(l, OTG_SYSCON_2);
-+
-+	l = omap_readl(OTG_SYSCON_1);
-+	l |= OTG_IDLE_EN;
-+	omap_writel(l, OTG_SYSCON_1);
-+
-+	/* Power off transceiver */
-+	tahvo_write_reg(tu->dev, TAHVO_REG_USBR, 0);
-+	tu->otg.state = OTG_STATE_UNDEFINED;
-+}
-+
-+
-+static int tahvo_usb_set_power(struct otg_transceiver *dev, unsigned mA)
-+{
-+	struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
-+
-+	dev_dbg(&tu->pt_dev->dev, "set_power %d mA\n", mA);
-+
-+	if (dev->state == OTG_STATE_B_PERIPHERAL) {
-+		/* REVISIT: Can Tahvo charge battery from VBUS? */
-+	}
-+	return 0;
-+}
-+
-+static int tahvo_usb_set_suspend(struct otg_transceiver *dev, int suspend)
-+{
-+	struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
-+	u16 w;
-+
-+	dev_dbg(&tu->pt_dev->dev, "set_suspend\n");
-+
-+	w = tahvo_read_reg(tu->dev, TAHVO_REG_USBR);
-+	if (suspend)
-+		w &= ~USBR_NSUSPEND;
-+	else
-+		w |= USBR_NSUSPEND;
-+	tahvo_write_reg(tu->dev, TAHVO_REG_USBR, w);
-+
-+	return 0;
-+}
-+
-+static int tahvo_usb_start_srp(struct otg_transceiver *dev)
-+{
-+	struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
-+	u32 otg_ctrl;
-+
-+	dev_dbg(&tu->pt_dev->dev, "start_srp\n");
-+
-+	if (!dev || tu->otg.state != OTG_STATE_B_IDLE)
-+		return -ENODEV;
-+
-+	otg_ctrl = omap_readl(OTG_CTRL);
-+	if (!(otg_ctrl & OTG_BSESSEND))
-+		return -EINVAL;
-+
-+	otg_ctrl |= OTG_B_BUSREQ;
-+	otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_SYS_MASK;
-+	omap_writel(otg_ctrl, OTG_CTRL);
-+	tu->otg.state = OTG_STATE_B_SRP_INIT;
-+
-+	return 0;
-+}
-+
-+static int tahvo_usb_start_hnp(struct otg_transceiver *otg)
-+{
-+	struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
-+
-+	dev_dbg(&tu->pt_dev->dev, "start_hnp\n");
-+#ifdef CONFIG_USB_OTG
-+	/* REVISIT: Add this for OTG */
-+#endif
-+	return -EINVAL;
-+}
-+
-+static int tahvo_usb_set_host(struct otg_transceiver *otg, struct usb_bus *host)
-+{
-+	struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
-+	u32 l;
-+
-+	dev_dbg(&tu->pt_dev->dev, "set_host %p\n", host);
-+
-+	if (otg == NULL)
-+		return -ENODEV;
-+
-+#if defined(CONFIG_USB_OTG) || !defined(CONFIG_USB_GADGET_OMAP)
-+
-+	mutex_lock(&tu->serialize);
-+
-+	if (host == NULL) {
-+		if (TAHVO_MODE(tu) == TAHVO_MODE_HOST)
-+			tahvo_usb_power_off(tu);
-+		tu->otg.host = NULL;
-+		mutex_unlock(&tu->serialize);
-+		return 0;
-+	}
-+
-+	l = omap_readl(OTG_SYSCON_1);
-+	l &= ~(OTG_IDLE_EN | HST_IDLE_EN | DEV_IDLE_EN);
-+	omap_writel(l, OTG_SYSCON_1);
-+
-+	if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) {
-+		tu->otg.host = NULL;
-+		tahvo_usb_become_host(tu);
-+	}
-+
-+	tu->otg.host = host;
-+
-+	mutex_unlock(&tu->serialize);
-+#else
-+	/* No host mode configured, so do not allow host controlled to be set */
-+	return -EINVAL;
-+#endif
-+
-+	return 0;
-+}
-+
-+static int tahvo_usb_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget)
-+{
-+	struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
-+
-+	dev_dbg(&tu->pt_dev->dev, "set_peripheral %p\n", gadget);
-+
-+	if (!otg)
-+		return -ENODEV;
-+
-+#if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_GADGET_OMAP)
-+
-+	mutex_lock(&tu->serialize);
-+
-+	if (!gadget) {
-+		if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
-+			tahvo_usb_power_off(tu);
-+		tu->otg.gadget = NULL;
-+		mutex_unlock(&tu->serialize);
-+		return 0;
-+	}
-+
-+	tu->otg.gadget = gadget;
-+	if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
-+		tahvo_usb_become_peripheral(tu);
-+
-+	mutex_unlock(&tu->serialize);
-+#else
-+	/* No gadget mode configured, so do not allow host controlled to be set */
-+	return -EINVAL;
-+#endif
-+
-+	return 0;
-+}
-+
-+static irqreturn_t tahvo_usb_vbus_interrupt(int irq, void *_tu)
-+{
-+	struct tahvo_usb *tu = _tu;
-+
-+	check_vbus_state(tu);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+#ifdef CONFIG_USB_OTG
-+static ssize_t otg_mode_show(struct device *device,
-+			     struct device_attribute *attr, char *buf)
-+{
-+	struct tahvo_usb *tu = dev_get_drvdata(device);
-+	switch (tu->tahvo_mode) {
-+	case TAHVO_MODE_HOST:
-+		return sprintf(buf, "host\n");
-+	case TAHVO_MODE_PERIPHERAL:
-+		return sprintf(buf, "peripheral\n");
-+	}
-+	return sprintf(buf, "unknown\n");
-+}
-+
-+static ssize_t otg_mode_store(struct device *device,
-+			      struct device_attribute *attr,
-+			      const char *buf, size_t count)
-+{
-+	struct tahvo_usb *tu = dev_get_drvdata(device);
-+	int r;
-+
-+	r = strlen(buf);
-+	mutex_lock(&tu->serialize);
-+	if (strncmp(buf, "host", 4) == 0) {
-+		if (tu->tahvo_mode == TAHVO_MODE_PERIPHERAL)
-+			tahvo_usb_stop_peripheral(tu);
-+		tu->tahvo_mode = TAHVO_MODE_HOST;
-+		if (tu->otg.host) {
-+			printk(KERN_INFO "Selected HOST mode: host controller present.\n");
-+			tahvo_usb_become_host(tu);
-+		} else {
-+			printk(KERN_INFO "Selected HOST mode: no host controller, powering off.\n");
-+			tahvo_usb_power_off(tu);
-+		}
-+	} else if (strncmp(buf, "peripheral", 10) == 0) {
-+		if (tu->tahvo_mode == TAHVO_MODE_HOST)
-+			tahvo_usb_stop_host(tu);
-+		tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
-+		if (tu->otg.gadget) {
-+			printk(KERN_INFO "Selected PERIPHERAL mode: gadget driver present.\n");
-+			tahvo_usb_become_peripheral(tu);
-+		} else {
-+			printk(KERN_INFO "Selected PERIPHERAL mode: no gadget driver, powering off.\n");
-+			tahvo_usb_power_off(tu);
-+		}
-+	} else
-+		r = -EINVAL;
-+
-+	mutex_unlock(&tu->serialize);
-+	return r;
-+}
-+
-+static DEVICE_ATTR(otg_mode, 0644, otg_mode_show, otg_mode_store);
-+#endif
-+
-+static int __devinit tahvo_usb_probe(struct platform_device *pdev)
-+{
-+	struct tahvo_usb *tu;
-+	struct device *dev = &pdev->dev;
-+	int ret;
-+	int irq;
-+
-+	dev_dbg(dev, "probe\n");
-+
-+	/* Create driver data */
-+	tu = kzalloc(sizeof(*tu), GFP_KERNEL);
-+	if (!tu)
-+		return -ENOMEM;
-+	tahvo_usb_device = tu;
-+
-+	tu->dev = dev;
-+	tu->pt_dev = pdev;
-+#ifdef CONFIG_USB_OTG
-+	/* Default mode */
-+#ifdef CONFIG_CBUS_TAHVO_USB_HOST_BY_DEFAULT
-+	tu->tahvo_mode = TAHVO_MODE_HOST;
-+#else
-+	tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
-+#endif
-+#endif
-+
-+	mutex_init(&tu->serialize);
-+
-+	tu->ick = clk_get(NULL, "usb_l4_ick");
-+	if (IS_ERR(tu->ick)) {
-+		dev_err(dev, "Failed to get usb_l4_ick\n");
-+		ret = PTR_ERR(tu->ick);
-+		goto err_free_tu;
-+	}
-+	clk_enable(tu->ick);
-+
-+	/* Set initial state, so that we generate kevents only on
-+	 * state changes */
-+	tu->vbus_state = tahvo_read_reg(tu->dev, TAHVO_REG_IDSR) & 0x01;
-+
-+	irq = platform_get_irq(pdev, 0);
-+	tu->irq = irq;
-+
-+	/* We cannot enable interrupt until omap_udc is initialized */
-+	ret = request_threaded_irq(irq, NULL, tahvo_usb_vbus_interrupt,
-+			IRQF_ONESHOT, "tahvo-vbus", tu);
-+	if (ret != 0) {
-+		printk(KERN_ERR "Could not register Tahvo interrupt for VBUS\n");
-+		goto err_release_clk;
-+	}
-+
-+	/* Attributes */
-+	ret = device_create_file(dev, &dev_attr_vbus_state);
-+#ifdef CONFIG_USB_OTG
-+	ret |= device_create_file(dev, &dev_attr_otg_mode);
-+#endif
-+	if (ret)
-+		printk(KERN_ERR "attribute creation failed: %d\n", ret);
-+
-+	/* Create OTG interface */
-+	tahvo_usb_power_off(tu);
-+	tu->otg.state = OTG_STATE_UNDEFINED;
-+	tu->otg.label = DRIVER_NAME;
-+	tu->otg.set_host = tahvo_usb_set_host;
-+	tu->otg.set_peripheral = tahvo_usb_set_peripheral;
-+	tu->otg.set_power = tahvo_usb_set_power;
-+	tu->otg.set_suspend = tahvo_usb_set_suspend;
-+	tu->otg.start_srp = tahvo_usb_start_srp;
-+	tu->otg.start_hnp = tahvo_usb_start_hnp;
-+
-+	ret = otg_set_transceiver(&tu->otg);
-+	if (ret < 0) {
-+		printk(KERN_ERR "Cannot register USB transceiver\n");
-+		goto err_free_irq;
-+	}
-+
-+	dev_set_drvdata(dev, tu);
-+
-+	return 0;
-+
-+err_free_irq:
-+	free_irq(tu->irq, tu);
-+err_release_clk:
-+	clk_disable(tu->ick);
-+	clk_put(tu->ick);
-+err_free_tu:
-+	kfree(tu);
-+	tahvo_usb_device = NULL;
-+
-+	return ret;
-+}
-+
-+static int __devexit tahvo_usb_remove(struct platform_device *pdev)
-+{
-+	struct tahvo_usb *tu = platform_get_drvdata(pdev);
-+
-+	dev_dbg(&pdev->dev, "remove\n");
-+
-+	free_irq(tu->irq, tu);
-+	flush_scheduled_work();
-+	otg_set_transceiver(0);
-+	device_remove_file(&pdev->dev, &dev_attr_vbus_state);
-+#ifdef CONFIG_USB_OTG
-+	device_remove_file(&pdev->dev, &dev_attr_otg_mode);
-+#endif
-+	clk_disable(tu->ick);
-+	clk_put(tu->ick);
-+
-+	kfree(tu);
-+	tahvo_usb_device = NULL;
-+
-+	return 0;
-+}
-+
-+static struct platform_driver tahvo_usb_driver = {
-+	.probe		= tahvo_usb_probe,
-+	.remove		= __devexit_p(tahvo_usb_remove),
-+	.driver		= {
-+		.name	= "tahvo-usb",
-+	},
-+};
-+
-+static int __init tahvo_usb_init(void)
-+{
-+	int ret = 0;
-+
-+	ret = platform_driver_register(&tahvo_usb_driver);
-+	if (ret)
-+		return ret;
-+
-+	ret = platform_driver_register(&omap_otg_driver);
-+	if (ret) {
-+		platform_driver_unregister(&tahvo_usb_driver);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+module_init(tahvo_usb_init);
-+
-+static void __exit tahvo_usb_exit(void)
-+{
-+	platform_driver_unregister(&omap_otg_driver);
-+	platform_driver_unregister(&tahvo_usb_driver);
-+}
-+module_exit(tahvo_usb_exit);
-+
-+MODULE_DESCRIPTION("Tahvo USB OTG Transceiver Driver");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä, Tony Lindgren, and Timo Teräs");
-diff --git a/drivers/cbus/tahvo.c b/drivers/cbus/tahvo.c
-new file mode 100644
-index 0000000..819111a
---- /dev/null
-+++ b/drivers/cbus/tahvo.c
-@@ -0,0 +1,415 @@
-+/**
-+ * drivers/cbus/tahvo.c
-+ *
-+ * Support functions for Tahvo ASIC
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
-+ *	      David Weinehall <david.weinehall@nokia.com>, and
-+ *	      Mikko Ylinen <mikko.k.ylinen@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+
-+#include <linux/slab.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/device.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/cbus.h>
-+#include <linux/mutex.h>
-+
-+#include "cbus.h"
-+#include "tahvo.h"
-+
-+struct tahvo {
-+	/* device lock */
-+	struct mutex	mutex;
-+	struct device	*dev;
-+
-+	struct irq_chip	irq_chip;
-+
-+	int		irq_base;
-+	int		irq_end;
-+	int		irq;
-+
-+	int		mask;
-+
-+	unsigned int	mask_pending:1;
-+	unsigned int	is_betty:1;
-+};
-+
-+/**
-+ * __tahvo_read_reg - Reads a value from a register in Tahvo
-+ * @tahvo: pointer to tahvo structure
-+ * @reg: the register address to read from
-+ */
-+static int __tahvo_read_reg(struct tahvo *tahvo, unsigned reg)
-+{
-+	return cbus_read_reg(tahvo->dev, CBUS_TAHVO_DEVICE_ID, reg);
-+}
-+
-+/**
-+ * __tahvo_write_reg - Writes a value to a register in Tahvo
-+ * @tahvo: pointer to tahvo structure
-+ * @reg: register address to write to
-+ * @val: the value to be written to @reg
-+ */
-+static void __tahvo_write_reg(struct tahvo *tahvo, unsigned reg, u16 val)
-+{
-+	cbus_write_reg(tahvo->dev, CBUS_TAHVO_DEVICE_ID, reg, val);
-+}
-+
-+/**
-+ * tahvo_read_reg - Read a value from a register in Tahvo
-+ * @child: device pointer from the calling child
-+ * @reg: the register to read from
-+ *
-+ * This function returns the contents of the specified register
-+ */
-+int tahvo_read_reg(struct device *child, unsigned reg)
-+{
-+	struct tahvo		*tahvo = dev_get_drvdata(child->parent);
-+
-+	return __tahvo_read_reg(tahvo, reg);
-+}
-+EXPORT_SYMBOL(tahvo_read_reg);
-+
-+/**
-+ * tahvo_write_reg - Write a value to a register in Tahvo
-+ * @child: device pointer from the calling child
-+ * @reg: the register to write to
-+ * @val : the value to write to the register
-+ *
-+ * This function writes a value to the specified register
-+ */
-+void tahvo_write_reg(struct device *child, unsigned reg, u16 val)
-+{
-+	struct tahvo		*tahvo = dev_get_drvdata(child->parent);
-+
-+	mutex_lock(&tahvo->mutex);
-+	__tahvo_write_reg(tahvo, reg, val);
-+	mutex_unlock(&tahvo->mutex);
-+}
-+EXPORT_SYMBOL(tahvo_write_reg);
-+
-+/**
-+ * tahvo_set_clear_reg_bits - set and clear register bits atomically
-+ * @child: device pointer from the calling child
-+ * @reg: the register to write to
-+ * @bits: the bits to set
-+ *
-+ * This function sets and clears the specified Tahvo register bits atomically
-+ */
-+void tahvo_set_clear_reg_bits(struct device *child, unsigned reg, u16 set,
-+		u16 clear)
-+{
-+	struct tahvo		*tahvo = dev_get_drvdata(child->parent);
-+	u16			w;
-+
-+	mutex_lock(&tahvo->mutex);
-+	w = __tahvo_read_reg(tahvo, reg);
-+	w &= ~clear;
-+	w |= set;
-+	__tahvo_write_reg(tahvo, reg, w);
-+	mutex_unlock(&tahvo->mutex);
-+}
-+
-+static irqreturn_t tahvo_irq_handler(int irq, void *_tahvo)
-+{
-+	struct tahvo		*tahvo = _tahvo;
-+	u16			id;
-+	u16			im;
-+
-+	mutex_lock(&tahvo->mutex);
-+	id = __tahvo_read_reg(tahvo, TAHVO_REG_IDR);
-+	im = __tahvo_read_reg(tahvo, TAHVO_REG_IMR);
-+	id &= ~im;
-+	__tahvo_write_reg(tahvo, TAHVO_REG_IDR, id);
-+	mutex_unlock(&tahvo->mutex);
-+
-+	if (!id) {
-+		dev_vdbg(tahvo->dev, "No IRQ, spurious ?\n");
-+		return IRQ_NONE;
-+	}
-+
-+	while (id) {
-+		unsigned long	pending = __ffs(id);
-+		unsigned int	irq;
-+
-+		id &= ~BIT(pending);
-+		irq = pending + tahvo->irq_base;
-+		handle_nested_irq(irq);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+/* -------------------------------------------------------------------------- */
-+
-+static void tahvo_irq_bus_lock(struct irq_data *data)
-+{
-+	struct tahvo		*tahvo = irq_data_get_irq_chip_data(data);
-+
-+	mutex_lock(&tahvo->mutex);
-+}
-+
-+static void tahvo_irq_bus_sync_unlock(struct irq_data *data)
-+{
-+	struct tahvo		*tahvo = irq_data_get_irq_chip_data(data);
-+
-+	if (tahvo->mask_pending) {
-+		__tahvo_write_reg(tahvo, TAHVO_REG_IMR, tahvo->mask);
-+		tahvo->mask_pending = false;
-+	}
-+
-+	mutex_unlock(&tahvo->mutex);
-+}
-+
-+static void tahvo_irq_mask(struct irq_data *data)
-+{
-+	struct tahvo		*tahvo = irq_data_get_irq_chip_data(data);
-+	int			irq = data->irq;
-+
-+	tahvo->mask |= (1 << (irq - tahvo->irq_base));
-+	tahvo->mask_pending = true;
-+}
-+
-+static void tahvo_irq_unmask(struct irq_data *data)
-+{
-+	struct tahvo		*tahvo = irq_data_get_irq_chip_data(data);
-+	int			irq = data->irq;
-+
-+	tahvo->mask &= ~(1 << (irq - tahvo->irq_base));
-+	tahvo->mask_pending = true;
-+}
-+
-+static inline void tahvo_irq_setup(int irq)
-+{
-+#ifdef CONFIG_ARM
-+	set_irq_flags(irq, IRQF_VALID);
-+#else
-+	irq_set_noprobe(irq);
-+#endif
-+}
-+
-+static void tahvo_irq_init(struct tahvo *tahvo)
-+{
-+	int			base = tahvo->irq_base;
-+	int			end = tahvo->irq_end;
-+	int			irq;
-+
-+	for (irq = base; irq < end; irq++) {
-+		irq_set_chip_data(irq, tahvo);
-+		irq_set_chip(irq, &tahvo->irq_chip);
-+		irq_set_nested_thread(irq, 1);
-+		tahvo_irq_setup(irq);
-+	}
-+}
-+
-+/* -------------------------------------------------------------------------- */
-+
-+static struct resource generic_resources[] = {
-+	{
-+		.start		= -EINVAL,	/* fixed later */
-+		.flags		= IORESOURCE_IRQ,
-+	},
-+};
-+
-+static struct device *tahvo_allocate_child(const char *name,
-+		struct device *parent, int irq)
-+{
-+	struct platform_device	*pdev;
-+	int			ret;
-+
-+	pdev = platform_device_alloc(name, -1);
-+	if (!pdev) {
-+		dev_dbg(parent, "can't allocate %s\n", name);
-+		goto err0;
-+	}
-+
-+	pdev->dev.parent = parent;
-+
-+	if (irq > 0) {
-+		generic_resources[0].start = irq;
-+
-+		ret = platform_device_add_resources(pdev, generic_resources,
-+				ARRAY_SIZE(generic_resources));
-+		if (ret < 0) {
-+			dev_dbg(parent, "can't add resources to %s\n", name);
-+			goto err1;
-+		}
-+	}
-+
-+	ret = platform_device_add(pdev);
-+	if (ret < 0) {
-+		dev_dbg(parent, "can't add %s\n", name);
-+		goto err1;
-+	}
-+
-+	return &pdev->dev;
-+
-+err1:
-+	platform_device_put(pdev);
-+
-+err0:
-+	return NULL;
-+}
-+
-+static int tahvo_allocate_children(struct device *parent, int irq_base)
-+{
-+	struct device		*child;
-+
-+	child = tahvo_allocate_child("tahvo-usb", parent,
-+			irq_base + TAHVO_INT_VBUSON);
-+	if (!child)
-+		return -ENOMEM;
-+
-+	child = tahvo_allocate_child("tahvo-pwm", parent, -1);
-+	if (!child)
-+		return -ENOMEM;
-+
-+	return 0;
-+}
-+
-+static int __devinit tahvo_probe(struct platform_device *pdev)
-+{
-+	struct irq_chip		*chip;
-+	struct tahvo		*tahvo;
-+	int			rev;
-+	int			ret;
-+	int			irq;
-+	int			id;
-+
-+	tahvo = kzalloc(sizeof(*tahvo), GFP_KERNEL);
-+	if (!tahvo) {
-+		dev_err(&pdev->dev, "not enough memory\n");
-+		ret = -ENOMEM;
-+		goto err0;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	platform_set_drvdata(pdev, tahvo);
-+
-+	mutex_init(&tahvo->mutex);
-+
-+	ret = irq_alloc_descs(-1, 0, MAX_TAHVO_IRQ_HANDLERS, 0);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to allocate IRQ descs\n");
-+		goto err1;
-+	}
-+
-+	chip = &tahvo->irq_chip;
-+
-+	chip->name	= "tahvo",
-+	chip->irq_bus_lock = tahvo_irq_bus_lock,
-+	chip->irq_bus_sync_unlock = tahvo_irq_bus_sync_unlock,
-+	chip->irq_mask	= tahvo_irq_mask,
-+	chip->irq_unmask = tahvo_irq_unmask,
-+
-+	tahvo->irq_base	= ret;
-+	tahvo->irq_end	= ret + MAX_TAHVO_IRQ_HANDLERS;
-+	tahvo->dev	= &pdev->dev;
-+	tahvo->irq	= irq;
-+
-+	tahvo_irq_init(tahvo);
-+
-+	rev = __tahvo_read_reg(tahvo, TAHVO_REG_ASICR);
-+
-+	id = (rev >> 8) & 0xff;
-+
-+	if (id == 0x0b)
-+		tahvo->is_betty = true;
-+
-+	ret = tahvo_allocate_children(&pdev->dev, tahvo->irq_base);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to allocate children\n");
-+		goto err2;
-+	}
-+
-+	dev_err(&pdev->dev, "%s v%d.%d found\n",
-+			tahvo->is_betty ? "Betty" : "Tahvo",
-+			(rev >> 4) & 0x0f, rev & 0x0f);
-+
-+	/* Mask all TAHVO interrupts */
-+	tahvo->mask = 0xffff;
-+	__tahvo_write_reg(tahvo, TAHVO_REG_IMR, tahvo->mask);
-+
-+	ret = request_threaded_irq(irq, NULL, tahvo_irq_handler,
-+			IRQF_TRIGGER_RISING | IRQF_ONESHOT,
-+			"tahvo", tahvo);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "Unable to register IRQ handler\n");
-+		goto err2;
-+	}
-+
-+	return 0;
-+
-+err2:
-+	irq_free_descs(tahvo->irq_base, MAX_TAHVO_IRQ_HANDLERS);
-+
-+err1:
-+	kfree(tahvo);
-+
-+err0:
-+	return ret;
-+}
-+
-+static int __devexit tahvo_remove(struct platform_device *pdev)
-+{
-+	struct tahvo		*tahvo = platform_get_drvdata(pdev);
-+	int			irq;
-+
-+	irq = platform_get_irq(pdev, 0);
-+
-+	free_irq(irq, 0);
-+	irq_free_descs(tahvo->irq_base, MAX_TAHVO_IRQ_HANDLERS);
-+	kfree(tahvo);
-+
-+	return 0;
-+}
-+
-+
-+static const struct of_device_id tahvo_match_table[] __devinitconst = {
-+	{
-+		.compatible = "nokia,tahvo",
-+	},
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, tahvo_match);
-+
-+static struct platform_driver tahvo_driver = {
-+	.probe		= tahvo_probe,
-+	.remove		= __devexit_p(tahvo_remove),
-+	.driver		= {
-+		.name	= "tahvo",
-+		.of_match_table = tahvo_match_table,
-+	},
-+};
-+
-+module_platform_driver(tahvo_driver);
-+
-+MODULE_ALIAS("platform:tahvo");
-+MODULE_DESCRIPTION("Tahvo ASIC control");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä");
-+MODULE_AUTHOR("David Weinehall");
-+MODULE_AUTHOR("Mikko Ylinen");
-+
-diff --git a/drivers/cbus/tahvo.h b/drivers/cbus/tahvo.h
-new file mode 100644
-index 0000000..f151a43
---- /dev/null
-+++ b/drivers/cbus/tahvo.h
-@@ -0,0 +1,58 @@
-+/*
-+ * drivers/cbus/tahvo.h
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
-+ *	      David Weinehall <david.weinehall@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#ifndef __DRIVERS_CBUS_TAHVO_H
-+#define __DRIVERS_CBUS_TAHVO_H
-+
-+#include <linux/types.h>
-+
-+/* Registers */
-+#define TAHVO_REG_ASICR		0x00	/* ASIC ID & revision */
-+#define TAHVO_REG_IDR		0x01	/* Interrupt ID */
-+#define TAHVO_REG_IDSR		0x02	/* Interrupt status */
-+#define TAHVO_REG_IMR		0x03	/* Interrupt mask */
-+#define TAHVO_REG_CHGCURR	0x04	/* Charge current control PWM (8-bit) */
-+#define TAHVO_REG_LEDPWMR	0x05	/* LED PWM */
-+#define TAHVO_REG_USBR		0x06	/* USB control */
-+#define TAHVO_REG_CHGCTL	0x08	/* Charge control register */
-+#define  TAHVO_REG_CHGCTL_EN		0x0001	/* Global charge enable */
-+#define  TAHVO_REG_CHGCTL_PWMOVR	0x0004	/* PWM override. Force charge PWM to 0%/100% duty cycle. */
-+#define  TAHVO_REG_CHGCTL_PWMOVRZERO	0x0008	/* If set, PWM override is 0% (If unset -> 100%) */
-+#define  TAHVO_REG_CHGCTL_CURMEAS	0x0040	/* Enable battery current measurement. */
-+#define  TAHVO_REG_CHGCTL_CURTIMRST	0x0080	/* Current measure timer reset. */
-+#define TAHVO_REG_BATCURRTIMER	0x0c	/* Battery current measure timer (8-bit) */
-+#define TAHVO_REG_BATCURR	0x0d	/* Battery (dis)charge current (signed 16-bit) */
-+
-+#define TAHVO_REG_MAX		0x0d
-+
-+/* Interrupt sources */
-+#define TAHVO_INT_VBUSON	0
-+#define TAHVO_INT_BATCURR	7 /* Battery current measure timer */
-+
-+#define MAX_TAHVO_IRQ_HANDLERS	8
-+
-+int tahvo_read_reg(struct device *child, unsigned reg);
-+void tahvo_write_reg(struct device *child, unsigned reg, u16 val);
-+void tahvo_set_clear_reg_bits(struct device *child, unsigned reg, u16 set,
-+		u16 clear);
-+
-+#endif /* __DRIVERS_CBUS_TAHVO_H */
-diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
-index a48bc02..ce75fcb 100644
---- a/drivers/cpufreq/Makefile
-+++ b/drivers/cpufreq/Makefile
-@@ -43,6 +43,7 @@ obj-$(CONFIG_UX500_SOC_DB8500)		+= db8500-cpufreq.o
- obj-$(CONFIG_ARM_S3C64XX_CPUFREQ)	+= s3c64xx-cpufreq.o
- obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
- obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
-+obj-$(CONFIG_ARCH_OMAP2PLUS)            += omap-cpufreq.o
- 
- ##################################################################################
- # PowerPC platform drivers
-diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
-index 987a165..2f5801a 100644
---- a/drivers/cpufreq/cpufreq.c
-+++ b/drivers/cpufreq/cpufreq.c
-@@ -204,8 +204,7 @@ static void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci)
- 		pr_debug("saving %lu as reference value for loops_per_jiffy; "
- 			"freq is %u kHz\n", l_p_j_ref, l_p_j_ref_freq);
- 	}
--	if ((val == CPUFREQ_PRECHANGE  && ci->old < ci->new) ||
--	    (val == CPUFREQ_POSTCHANGE && ci->old > ci->new) ||
-+	if ((val == CPUFREQ_POSTCHANGE  && ci->old != ci->new) ||
- 	    (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
- 		loops_per_jiffy = cpufreq_scale(l_p_j_ref, l_p_j_ref_freq,
- 								ci->new);
-diff --git a/drivers/cpufreq/cpufreq_userspace.c b/drivers/cpufreq/cpufreq_userspace.c
-index f231015..bedac1a 100644
---- a/drivers/cpufreq/cpufreq_userspace.c
-+++ b/drivers/cpufreq/cpufreq_userspace.c
-@@ -47,9 +47,11 @@ userspace_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
- 	if (!per_cpu(cpu_is_managed, freq->cpu))
- 		return 0;
- 
--	pr_debug("saving cpu_cur_freq of cpu %u to be %u kHz\n",
--			freq->cpu, freq->new);
--	per_cpu(cpu_cur_freq, freq->cpu) = freq->new;
-+	if (val == CPUFREQ_POSTCHANGE) {
-+		pr_debug("saving cpu_cur_freq of cpu %u to be %u kHz\n",
-+				freq->cpu, freq->new);
-+		per_cpu(cpu_cur_freq, freq->cpu) = freq->new;
-+	}
- 
- 	return 0;
- }
-diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
-new file mode 100644
-index 0000000..0d1d070
---- /dev/null
-+++ b/drivers/cpufreq/omap-cpufreq.c
-@@ -0,0 +1,412 @@
-+/*
-+ *  CPU frequency scaling for OMAP using OPP information
-+ *
-+ *  Copyright (C) 2005 Nokia Corporation
-+ *  Written by Tony Lindgren <tony@atomide.com>
-+ *
-+ *  Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
-+ *
-+ * Copyright (C) 2007-2011 Texas Instruments, Inc.
-+ * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/cpufreq.h>
-+#include <linux/delay.h>
-+#include <linux/init.h>
-+#include <linux/err.h>
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/opp.h>
-+#include <linux/cpu.h>
-+#include <linux/module.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/suspend.h>
-+
-+#include <asm/system.h>
-+#include <asm/smp_plat.h>
-+#include <asm/cpu.h>
-+
-+#include <plat/clock.h>
-+#include <plat/omap-pm.h>
-+#include <plat/common.h>
-+#include <plat/omap_device.h>
-+
-+#include <mach/hardware.h>
-+
-+/* Tolerance for MPU voltage is 4%, we have to pass +4% as a
-+ * maximum voltage while setting the MPU regulator voltage.
-+ * Which is taken from AM33XX datasheet */
-+#define MPU_TOLERANCE	4
-+#define PER_ROUND_VAL	100
-+
-+/* Use 275MHz when entering suspend */
-+#define SLEEP_FREQ	(275 * 1000)
-+
-+
-+#ifdef CONFIG_SMP
-+struct lpj_info {
-+	unsigned long	ref;
-+	unsigned int	freq;
-+};
-+
-+static DEFINE_PER_CPU(struct lpj_info, lpj_ref);
-+static struct lpj_info global_lpj_ref;
-+#endif
-+
-+static struct cpufreq_frequency_table *freq_table;
-+static atomic_t freq_table_users = ATOMIC_INIT(0);
-+static struct clk *mpu_clk;
-+static char *mpu_clk_name;
-+static struct device *mpu_dev;
-+static struct regulator *mpu_reg;
-+static DEFINE_MUTEX(omap_cpu_lock);
-+static bool is_suspended;
-+
-+static int omap_verify_speed(struct cpufreq_policy *policy)
-+{
-+	if (!freq_table)
-+		return -EINVAL;
-+	return cpufreq_frequency_table_verify(policy, freq_table);
-+}
-+
-+static unsigned int omap_getspeed(unsigned int cpu)
-+{
-+	unsigned long rate;
-+
-+	if (cpu >= NR_CPUS)
-+		return 0;
-+
-+	rate = clk_get_rate(mpu_clk) / 1000;
-+	return rate;
-+}
-+
-+static int omap_target(struct cpufreq_policy *policy,
-+		       unsigned int target_freq,
-+		       unsigned int relation)
-+{
-+	unsigned int i;
-+	int ret = 0;
-+	struct cpufreq_freqs freqs;
-+	struct opp *opp;
-+	int volt_old = 0, volt_new = 0;
-+
-+	if (is_suspended)
-+		return -EBUSY;
-+
-+	if (!freq_table) {
-+		dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__,
-+				policy->cpu);
-+		return -EINVAL;
-+	}
-+
-+	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
-+			relation, &i);
-+	if (ret) {
-+		dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n",
-+			__func__, policy->cpu, target_freq, ret);
-+		return ret;
-+	}
-+	freqs.new = freq_table[i].frequency;
-+	if (!freqs.new) {
-+		dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__,
-+			policy->cpu, target_freq);
-+		return -EINVAL;
-+	}
-+
-+	freqs.old = omap_getspeed(policy->cpu);
-+	freqs.cpu = policy->cpu;
-+
-+	if (freqs.old == freqs.new && policy->cur == freqs.new)
-+		return ret;
-+
-+	opp = opp_find_freq_exact(mpu_dev, freqs.new * 1000, true);
-+	if (IS_ERR(opp)) {
-+		dev_err(mpu_dev, "%s: cpu%d: no opp match for freq %d\n",
-+			__func__, policy->cpu, target_freq);
-+		return -EINVAL;
-+	}
-+
-+	volt_new = opp_get_voltage(opp);
-+	if (!volt_new) {
-+		dev_err(mpu_dev, "%s: cpu%d: no opp voltage for freq %d\n",
-+			__func__, policy->cpu, target_freq);
-+		return -EINVAL;
-+	}
-+
-+	volt_old = regulator_get_voltage(mpu_reg);
-+
-+#ifdef CONFIG_CPU_FREQ_DEBUG
-+	pr_info("cpufreq-omap: frequency transition: %u --> %u\n",
-+			freqs.old, freqs.new);
-+	pr_info("cpufreq-omap: voltage transition: %d --> %d\n",
-+			volt_old, volt_new);
-+#endif
-+
-+	if (freqs.new > freqs.old) {
-+		ret = regulator_set_voltage(mpu_reg, volt_new,
-+			volt_new + (volt_new * MPU_TOLERANCE) / PER_ROUND_VAL);
-+		if (ret) {
-+			dev_err(mpu_dev, "%s: unable to set voltage to %d uV (for %u MHz)\n",
-+				__func__, volt_new, freqs.new/1000);
-+			return ret;
-+		}
-+	}
-+
-+	/* notifiers */
-+	for_each_cpu(i, policy->cpus) {
-+		freqs.cpu = i;
-+		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-+	}
-+
-+	ret = clk_set_rate(mpu_clk, freqs.new * 1000);
-+	freqs.new = omap_getspeed(policy->cpu);
-+
-+#ifdef CONFIG_SMP
-+	/*
-+	 * Note that loops_per_jiffy is not updated on SMP systems in
-+	 * cpufreq driver. So, update the per-CPU loops_per_jiffy value
-+	 * on frequency transition. We need to update all dependent CPUs.
-+	 */
-+	for_each_cpu(i, policy->cpus) {
-+		struct lpj_info *lpj = &per_cpu(lpj_ref, i);
-+		if (!lpj->freq) {
-+			lpj->ref = per_cpu(cpu_data, i).loops_per_jiffy;
-+			lpj->freq = freqs.old;
-+		}
-+
-+		per_cpu(cpu_data, i).loops_per_jiffy =
-+			cpufreq_scale(lpj->ref, lpj->freq, freqs.new);
-+	}
-+
-+	/* And don't forget to adjust the global one */
-+	if (!global_lpj_ref.freq) {
-+		global_lpj_ref.ref = loops_per_jiffy;
-+		global_lpj_ref.freq = freqs.old;
-+	}
-+	loops_per_jiffy = cpufreq_scale(global_lpj_ref.ref, global_lpj_ref.freq,
-+					freqs.new);
-+#endif
-+
-+	/* notifiers */
-+	for_each_cpu(i, policy->cpus) {
-+		freqs.cpu = i;
-+		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-+	}
-+
-+	if (freqs.new < freqs.old) {
-+		ret = regulator_set_voltage(mpu_reg, volt_new,
-+			volt_new + (volt_new * MPU_TOLERANCE) / PER_ROUND_VAL);
-+		if (ret) {
-+			unsigned int temp;
-+
-+			dev_err(mpu_dev, "%s: unable to set voltage to %d uV (for %u MHz)\n",
-+				__func__, volt_new, freqs.new/1000);
-+
-+			if (clk_set_rate(mpu_clk, freqs.old * 1000)) {
-+				dev_err(mpu_dev,
-+					"%s: failed restoring clock rate to %u MHz, clock rate is %u MHz",
-+					__func__,
-+					freqs.old/1000, freqs.new/1000);
-+				return ret;
-+			}
-+
-+			temp = freqs.new;
-+			freqs.new = freqs.old;
-+			freqs.old = temp;
-+
-+			for_each_cpu(i, policy->cpus) {
-+				freqs.cpu = i;
-+				cpufreq_notify_transition(&freqs,
-+					CPUFREQ_PRECHANGE);
-+				cpufreq_notify_transition(&freqs,
-+					CPUFREQ_POSTCHANGE);
-+			}
-+			return ret;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static inline void freq_table_free(void)
-+{
-+	if (atomic_dec_and_test(&freq_table_users))
-+		opp_free_cpufreq_table(mpu_dev, &freq_table);
-+}
-+
-+static int omap_pm_notify(struct notifier_block *nb, unsigned long event,
-+                                void *dummy)
-+{
-+	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
-+	static unsigned int saved_frequency;
-+
-+	mutex_lock(&omap_cpu_lock);
-+	switch (event) {
-+	case PM_SUSPEND_PREPARE:
-+		if (is_suspended)
-+			goto out;
-+
-+                saved_frequency = omap_getspeed(0);
-+
-+                mutex_unlock(&omap_cpu_lock);
-+		omap_target(policy, SLEEP_FREQ, CPUFREQ_RELATION_H);
-+		mutex_lock(&omap_cpu_lock);
-+		is_suspended = true;
-+                break;
-+
-+        case PM_POST_SUSPEND:
-+                is_suspended = false;
-+                mutex_unlock(&omap_cpu_lock);
-+		omap_target(policy, saved_frequency, CPUFREQ_RELATION_H);
-+		mutex_lock(&omap_cpu_lock);
-+                break;
-+	}
-+out:
-+	mutex_unlock(&omap_cpu_lock);
-+
-+	return NOTIFY_OK;
-+}
-+
-+static struct notifier_block omap_cpu_pm_notifier = {
-+	.notifier_call = omap_pm_notify,
-+};
-+
-+static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
-+{
-+	int result = 0;
-+
-+	mpu_clk = clk_get(NULL, mpu_clk_name);
-+	if (IS_ERR(mpu_clk))
-+		return PTR_ERR(mpu_clk);
-+
-+	mpu_reg = regulator_get(NULL, "vdd_mpu");
-+	if (IS_ERR(mpu_reg)) {
-+		result = -EINVAL;
-+		goto fail_ck;
-+	}
-+
-+	/* success of regulator_get doesn't gurantee presence of driver for
-+	   physical regulator and presence of physical regulator (this
-+	   situation arises if dummy regulator is enabled),so check voltage
-+	   to verify that physical regulator and it's driver is present
-+	 */
-+	if (regulator_get_voltage(mpu_reg) < 0) {
-+		result = -EINVAL;
-+		goto fail_reg;
-+	}
-+
-+	if (policy->cpu >= NR_CPUS) {
-+		result = -EINVAL;
-+		goto fail_reg;
-+	}
-+
-+	policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
-+
-+	if (atomic_inc_return(&freq_table_users) == 1)
-+		result = opp_init_cpufreq_table(mpu_dev, &freq_table);
-+
-+	if (result) {
-+		dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n",
-+				__func__, policy->cpu, result);
-+		goto fail_reg;
-+	}
-+
-+	result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
-+	if (result)
-+		goto fail_table;
-+
-+	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
-+
-+	policy->min = policy->cpuinfo.min_freq;
-+	policy->max = policy->cpuinfo.max_freq;
-+	policy->cur = omap_getspeed(policy->cpu);
-+
-+	/*
-+	 * On OMAP SMP configuartion, both processors share the voltage
-+	 * and clock. So both CPUs needs to be scaled together and hence
-+	 * needs software co-ordination. Use cpufreq affected_cpus
-+	 * interface to handle this scenario. Additional is_smp() check
-+	 * is to keep SMP_ON_UP build working.
-+	 */
-+	if (is_smp()) {
-+		policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
-+		cpumask_setall(policy->cpus);
-+	}
-+
-+	/* FIXME: what's the actual transition time? */
-+	policy->cpuinfo.transition_latency = 300 * 1000;
-+
-+	register_pm_notifier(&omap_cpu_pm_notifier);
-+
-+	return 0;
-+
-+fail_table:
-+	freq_table_free();
-+fail_reg:
-+	regulator_put(mpu_reg);
-+fail_ck:
-+	clk_put(mpu_clk);
-+	return result;
-+}
-+
-+static int omap_cpu_exit(struct cpufreq_policy *policy)
-+{
-+	freq_table_free();
-+	clk_put(mpu_clk);
-+	return 0;
-+}
-+
-+static struct freq_attr *omap_cpufreq_attr[] = {
-+	&cpufreq_freq_attr_scaling_available_freqs,
-+	NULL,
-+};
-+
-+static struct cpufreq_driver omap_driver = {
-+	.flags		= CPUFREQ_STICKY,
-+	.verify		= omap_verify_speed,
-+	.target		= omap_target,
-+	.get		= omap_getspeed,
-+	.init		= omap_cpu_init,
-+	.exit		= omap_cpu_exit,
-+	.name		= "omap",
-+	.attr		= omap_cpufreq_attr,
-+};
-+
-+static int __init omap_cpufreq_init(void)
-+{
-+	if (cpu_is_omap24xx())
-+		mpu_clk_name = "virt_prcm_set";
-+	else if (cpu_is_omap34xx() && !cpu_is_am33xx())
-+		mpu_clk_name = "dpll1_ck";
-+	else if (cpu_is_omap44xx() || cpu_is_am33xx())
-+		mpu_clk_name = "dpll_mpu_ck";
-+
-+	if (!mpu_clk_name) {
-+		pr_err("%s: unsupported Silicon?\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	mpu_dev = omap_device_get_by_hwmod_name("mpu");
-+	if (!mpu_dev) {
-+		pr_warning("%s: unable to get the mpu device\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	return cpufreq_register_driver(&omap_driver);
-+}
-+
-+static void __exit omap_cpufreq_exit(void)
-+{
-+	cpufreq_unregister_driver(&omap_driver);
-+}
-+
-+MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
-+MODULE_LICENSE("GPL");
-+module_init(omap_cpufreq_init);
-+module_exit(omap_cpufreq_exit);
-diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
-index a6c10e8..8952897 100644
---- a/drivers/gpio/gpio-omap.c
-+++ b/drivers/gpio/gpio-omap.c
-@@ -213,7 +213,7 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
- 	void __iomem *base = bank->base;
- 	u32 gpio_bit = 1 << gpio;
- 
--	if (cpu_is_omap44xx()) {
-+	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
- 			  trigger & IRQ_TYPE_LEVEL_LOW);
- 		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
-@@ -233,7 +233,7 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
- 			  trigger & IRQ_TYPE_EDGE_FALLING);
- 	}
- 	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
--		if (cpu_is_omap44xx()) {
-+		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 			_gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
- 				  trigger != 0);
- 		} else {
-@@ -264,7 +264,7 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
- 			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
- 	}
- 
--	if (cpu_is_omap44xx()) {
-+	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 		bank->level_mask =
- 			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
- 			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
-@@ -591,10 +591,10 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
- 			void __iomem *reg = bank->base;
- 			u32 ctrl;
- 
--			if (cpu_is_omap24xx() || cpu_is_omap34xx())
--				reg += OMAP24XX_GPIO_CTRL;
--			else if (cpu_is_omap44xx())
-+			if (cpu_is_omap44xx() || cpu_is_am33xx())
- 				reg += OMAP4_GPIO_CTRL;
-+			else if (cpu_is_omap24xx() || cpu_is_omap34xx())
-+				reg += OMAP24XX_GPIO_CTRL;
- 			ctrl = __raw_readl(reg);
- 			/* Module is enabled, clocks are not gated */
- 			ctrl &= 0xFFFFFFFE;
-@@ -627,7 +627,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
- 		__raw_writel(1 << offset, reg);
- 	}
- #endif
--#ifdef CONFIG_ARCH_OMAP4
-+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAPAM33XX)
- 	if (bank->method == METHOD_GPIO_44XX) {
- 		/* Disable wake-up during idle for dynamic tick */
- 		void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
-@@ -640,10 +640,10 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
- 			void __iomem *reg = bank->base;
- 			u32 ctrl;
- 
--			if (cpu_is_omap24xx() || cpu_is_omap34xx())
--				reg += OMAP24XX_GPIO_CTRL;
--			else if (cpu_is_omap44xx())
-+			if (cpu_is_omap44xx() || cpu_is_am33xx())
- 				reg += OMAP4_GPIO_CTRL;
-+			else if (cpu_is_omap24xx() || cpu_is_omap34xx())
-+				reg += OMAP24XX_GPIO_CTRL;
- 			ctrl = __raw_readl(reg);
- 			/* Module is disabled, clocks are gated */
- 			ctrl |= 1;
-@@ -1026,7 +1026,7 @@ static inline int init_gpio_info(struct platform_device *pdev)
- static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
- {
- 	if (cpu_class_is_omap2()) {
--		if (cpu_is_omap44xx()) {
-+		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 			__raw_writel(0xffffffff, bank->base +
- 					OMAP4_GPIO_IRQSTATUSCLR0);
- 			__raw_writel(0x00000000, bank->base +
-@@ -1265,7 +1265,7 @@ static int omap_gpio_suspend(void)
- 			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
- 			break;
- #endif
--#ifdef CONFIG_ARCH_OMAP4
-+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAPAM33XX)
- 		case METHOD_GPIO_44XX:
- 			wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
- 			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
-@@ -1312,7 +1312,7 @@ static void omap_gpio_resume(void)
- 			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
- 			break;
- #endif
--#ifdef CONFIG_ARCH_OMAP4
-+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAPAM33XX)
- 		case METHOD_GPIO_44XX:
- 			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
- 			wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
-@@ -1345,7 +1345,7 @@ void omap2_gpio_prepare_for_idle(int off_mode)
- 	int i, c = 0;
- 	int min = 0;
- 
--	if (cpu_is_omap34xx())
-+	if ((cpu_is_omap34xx() && !cpu_is_am33xx()))
- 		min = 1;
- 
- 	for (i = min; i < gpio_bank_count; i++) {
-@@ -1365,7 +1365,8 @@ void omap2_gpio_prepare_for_idle(int off_mode)
- 		if (!(bank->enabled_non_wakeup_gpios))
- 			continue;
- 
--		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-+		if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
-+							!cpu_is_am33xx())) {
- 			bank->saved_datain = __raw_readl(bank->base +
- 					OMAP24XX_GPIO_DATAIN);
- 			l1 = __raw_readl(bank->base +
-@@ -1374,7 +1375,7 @@ void omap2_gpio_prepare_for_idle(int off_mode)
- 					OMAP24XX_GPIO_RISINGDETECT);
- 		}
- 
--		if (cpu_is_omap44xx()) {
-+		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 			bank->saved_datain = __raw_readl(bank->base +
- 						OMAP4_GPIO_DATAIN);
- 			l1 = __raw_readl(bank->base +
-@@ -1388,14 +1389,15 @@ void omap2_gpio_prepare_for_idle(int off_mode)
- 		l1 &= ~bank->enabled_non_wakeup_gpios;
- 		l2 &= ~bank->enabled_non_wakeup_gpios;
- 
--		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-+		if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
-+							!cpu_is_am33xx())) {
- 			__raw_writel(l1, bank->base +
- 					OMAP24XX_GPIO_FALLINGDETECT);
- 			__raw_writel(l2, bank->base +
- 					OMAP24XX_GPIO_RISINGDETECT);
- 		}
- 
--		if (cpu_is_omap44xx()) {
-+		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 			__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
- 			__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
- 		}
-@@ -1414,7 +1416,7 @@ void omap2_gpio_resume_after_idle(void)
- 	int i;
- 	int min = 0;
- 
--	if (cpu_is_omap34xx())
-+	if ((cpu_is_omap34xx() && !cpu_is_am33xx()))
- 		min = 1;
- 	for (i = min; i < gpio_bank_count; i++) {
- 		struct gpio_bank *bank = &gpio_bank[i];
-@@ -1430,7 +1432,8 @@ void omap2_gpio_resume_after_idle(void)
- 		if (!(bank->enabled_non_wakeup_gpios))
- 			continue;
- 
--		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-+		if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
-+							!cpu_is_am33xx())) {
- 			__raw_writel(bank->saved_fallingdetect,
- 				 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
- 			__raw_writel(bank->saved_risingdetect,
-@@ -1438,7 +1441,7 @@ void omap2_gpio_resume_after_idle(void)
- 			l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
- 		}
- 
--		if (cpu_is_omap44xx()) {
-+		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 			__raw_writel(bank->saved_fallingdetect,
- 				 bank->base + OMAP4_GPIO_FALLINGDETECT);
- 			__raw_writel(bank->saved_risingdetect,
-@@ -1472,7 +1475,8 @@ void omap2_gpio_resume_after_idle(void)
- 		if (gen) {
- 			u32 old0, old1;
- 
--			if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-+			if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
-+							!cpu_is_am33xx())) {
- 				old0 = __raw_readl(bank->base +
- 					OMAP24XX_GPIO_LEVELDETECT0);
- 				old1 = __raw_readl(bank->base +
-@@ -1487,7 +1491,7 @@ void omap2_gpio_resume_after_idle(void)
- 					OMAP24XX_GPIO_LEVELDETECT1);
- 			}
- 
--			if (cpu_is_omap44xx()) {
-+			if (cpu_is_omap44xx() || cpu_is_am33xx()) {
- 				old0 = __raw_readl(bank->base +
- 						OMAP4_GPIO_LEVELDETECT0);
- 				old1 = __raw_readl(bank->base +
-diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
-index 257c1a5..e0733b7 100644
---- a/drivers/i2c/busses/i2c-omap.c
-+++ b/drivers/i2c/busses/i2c-omap.c
-@@ -830,11 +830,9 @@ complete:
- 				~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
- 				OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
- 
--		if (stat & OMAP_I2C_STAT_NACK) {
-+		if (stat & OMAP_I2C_STAT_NACK)
- 			err |= OMAP_I2C_STAT_NACK;
--			omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
--					   OMAP_I2C_CON_STP);
--		}
-+
- 		if (stat & OMAP_I2C_STAT_AL) {
- 			dev_err(dev->dev, "Arbitration lost\n");
- 			err |= OMAP_I2C_STAT_AL;
-diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
-index 3488ffe..dab56e5 100644
---- a/drivers/input/touchscreen/Kconfig
-+++ b/drivers/input/touchscreen/Kconfig
-@@ -407,6 +407,17 @@ config TOUCHSCREEN_TOUCHWIN
- 	  To compile this driver as a module, choose M here: the
- 	  module will be called touchwin.
- 
-+config TOUCHSCREEN_TI_TSCADC
-+	tristate "TI Touchscreen Interface"
-+	help
-+	  Say Y here if you have 4/5/8 wire touchscreen controller
-+	  to be connected to the ADC controller on your TI SoC.
-+
-+	  If unsure, say N.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called ti_tscadc.
-+
- config TOUCHSCREEN_ATMEL_TSADCC
- 	tristate "Atmel Touchscreen Interface"
- 	depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
-diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
-index f957676..124360b 100644
---- a/drivers/input/touchscreen/Makefile
-+++ b/drivers/input/touchscreen/Makefile
-@@ -42,6 +42,7 @@ obj-$(CONFIG_TOUCHSCREEN_PENMOUNT)	+= penmount.o
- obj-$(CONFIG_TOUCHSCREEN_S3C2410)	+= s3c2410_ts.o
- obj-$(CONFIG_TOUCHSCREEN_ST1232)	+= st1232.o
- obj-$(CONFIG_TOUCHSCREEN_STMPE)		+= stmpe-ts.o
-+obj-$(CONFIG_TOUCHSCREEN_TI_TSCADC)	+= ti_tscadc.o
- obj-$(CONFIG_TOUCHSCREEN_TNETV107X)	+= tnetv107x-ts.o
- obj-$(CONFIG_TOUCHSCREEN_TOUCHIT213)	+= touchit213.o
- obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT)	+= touchright.o
-diff --git a/drivers/input/touchscreen/ti_tscadc.c b/drivers/input/touchscreen/ti_tscadc.c
-new file mode 100644
-index 0000000..3082e5c
---- /dev/null
-+++ b/drivers/input/touchscreen/ti_tscadc.c
-@@ -0,0 +1,793 @@
-+/*
-+ * TI Touch Screen driver
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/err.h>
-+#include <linux/module.h>
-+#include <linux/input.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/input/ti_tscadc.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/pm_runtime.h>
-+
-+size_t do_adc_sample(struct kobject *, struct attribute *, char *);
-+static DEVICE_ATTR(ain1, S_IRUGO, do_adc_sample, NULL);
-+static DEVICE_ATTR(ain2, S_IRUGO, do_adc_sample, NULL);
-+static DEVICE_ATTR(ain3, S_IRUGO, do_adc_sample, NULL);
-+static DEVICE_ATTR(ain4, S_IRUGO, do_adc_sample, NULL);
-+static DEVICE_ATTR(ain5, S_IRUGO, do_adc_sample, NULL);
-+static DEVICE_ATTR(ain6, S_IRUGO, do_adc_sample, NULL);
-+static DEVICE_ATTR(ain7, S_IRUGO, do_adc_sample, NULL);
-+static DEVICE_ATTR(ain8, S_IRUGO, do_adc_sample, NULL);
-+
-+/* Memory mapped registers here have incorrect offsets!
-+ * Correct after referring TRM */
-+#define TSCADC_REG_IRQEOI		0x020
-+#define TSCADC_REG_RAWIRQSTATUS		0x024
-+#define TSCADC_REG_IRQSTATUS		0x028
-+#define TSCADC_REG_IRQENABLE		0x02C
-+#define TSCADC_REG_IRQCLR		0x030
-+#define TSCADC_REG_IRQWAKEUP		0x034
-+#define TSCADC_REG_CTRL			0x040
-+#define TSCADC_REG_ADCFSM		0x044
-+#define TSCADC_REG_CLKDIV		0x04C
-+#define TSCADC_REG_SE			0x054
-+#define TSCADC_REG_IDLECONFIG		0x058
-+#define TSCADC_REG_CHARGECONFIG		0x05C
-+#define TSCADC_REG_CHARGEDELAY		0x060
-+#define TSCADC_REG_STEPCONFIG(n)	(0x64 + ((n-1) * 8))
-+#define TSCADC_REG_STEPDELAY(n)		(0x68 + ((n-1) * 8))
-+#define TSCADC_REG_STEPCONFIG13		0x0C4
-+#define TSCADC_REG_STEPDELAY13		0x0C8
-+#define TSCADC_REG_STEPCONFIG14		0x0CC
-+#define TSCADC_REG_STEPDELAY14		0x0D0
-+#define TSCADC_REG_FIFO0CNT		0xE4
-+#define TSCADC_REG_FIFO0THR		0xE8
-+#define TSCADC_REG_FIFO1CNT		0xF0
-+#define TSCADC_REG_FIFO1THR		0xF4
-+#define TSCADC_REG_FIFO0		0x100
-+#define TSCADC_REG_FIFO1		0x200
-+
-+/*	Register Bitfields	*/
-+#define TSCADC_IRQWKUP_ENB		BIT(0)
-+#define TSCADC_IRQWKUP_DISABLE		0x00
-+#define TSCADC_STPENB_STEPENB		0x7FFF
-+#define TSCADC_STPENB_STEPENB_TOUCHSCREEN	0x7FFF
-+#define TSCADC_STPENB_STEPENB_GENERAL		0x0400
-+#define TSCADC_IRQENB_FIFO0THRES	BIT(2)
-+#define TSCADC_IRQENB_FIFO0OVERRUN	BIT(3)
-+#define TSCADC_IRQENB_FIFO1THRES	BIT(5)
-+#define TSCADC_IRQENB_EOS		BIT(1)
-+#define TSCADC_IRQENB_PENUP		BIT(9)
-+#define TSCADC_IRQENB_HW_PEN		BIT(0)
-+#define TSCADC_STEPCONFIG_MODE_HWSYNC	0x2
-+#define TSCADC_STEPCONFIG_MODE_SWCONT		0x1
-+#define TSCADC_STEPCONFIG_MODE_SWONESHOT	0x0
-+#define TSCADC_STEPCONFIG_2SAMPLES_AVG	(1 << 4)
-+#define TSCADC_STEPCONFIG_NO_AVG	0
-+#define TSCADC_STEPCONFIG_XPP		BIT(5)
-+#define TSCADC_STEPCONFIG_XNN		BIT(6)
-+#define TSCADC_STEPCONFIG_YPP		BIT(7)
-+#define TSCADC_STEPCONFIG_YNN		BIT(8)
-+#define TSCADC_STEPCONFIG_XNP		BIT(9)
-+#define TSCADC_STEPCONFIG_YPN		BIT(10)
-+#define TSCADC_STEPCONFIG_RFP		(1 << 12)
-+#define TSCADC_STEPCONFIG_INM		(1 << 18)
-+#define TSCADC_STEPCONFIG_INP_4		(1 << 19)
-+#define TSCADC_STEPCONFIG_INP		(1 << 20)
-+#define TSCADC_STEPCONFIG_INP_5		(1 << 21)
-+#define TSCADC_STEPCONFIG_FIFO1		(1 << 26)
-+#define TSCADC_STEPCONFIG_IDLE_INP	(1 << 22)
-+#define TSCADC_STEPCONFIG_OPENDLY	0x018
-+#define TSCADC_STEPCONFIG_SAMPLEDLY	0x88
-+#define TSCADC_STEPCONFIG_Z1		(3 << 19)
-+#define TSCADC_STEPCHARGE_INM_SWAP	BIT(16)
-+#define TSCADC_STEPCHARGE_INM		BIT(15)
-+#define TSCADC_STEPCHARGE_INP_SWAP	BIT(20)
-+#define TSCADC_STEPCHARGE_INP		BIT(19)
-+#define TSCADC_STEPCHARGE_RFM		(1 << 23)
-+#define TSCADC_STEPCHARGE_DELAY		0x1
-+#define TSCADC_CNTRLREG_TSCSSENB	BIT(0)
-+#define TSCADC_CNTRLREG_STEPID		BIT(1)
-+#define TSCADC_CNTRLREG_STEPCONFIGWRT	BIT(2)
-+#define TSCADC_CNTRLREG_TSCENB		BIT(7)
-+#define TSCADC_CNTRLREG_4WIRE		(0x1 << 5)
-+#define TSCADC_CNTRLREG_5WIRE		(0x1 << 6)
-+#define TSCADC_CNTRLREG_8WIRE		(0x3 << 5)
-+#define TSCADC_ADCFSM_STEPID		0x10
-+#define TSCADC_ADCFSM_FSM		BIT(5)
-+
-+#define ADC_CLK				3000000
-+
-+#define MAX_12BIT                       ((1 << 12) - 1)
-+
-+int pen = 1;
-+unsigned int bckup_x = 0, bckup_y = 0;
-+
-+struct tscadc {
-+	struct input_dev	*input;
-+	int			wires;
-+	int			analog_input;
-+	int			x_plate_resistance;
-+	int mode;
-+	int			irq;
-+	void __iomem		*tsc_base;
-+	unsigned int		ctrl;
-+};
-+
-+static unsigned int tscadc_readl(struct tscadc *ts, unsigned int reg)
-+{
-+	return readl(ts->tsc_base + reg);
-+}
-+
-+static void tscadc_writel(struct tscadc *tsc, unsigned int reg,
-+					unsigned int val)
-+{
-+	writel(val, tsc->tsc_base + reg);
-+}
-+
-+/* Configure ADC to sample on channel (1-8) */
-+
-+static void tsc_adc_step_config(struct tscadc *ts_dev, int channel)
-+{
-+	unsigned int	stepconfig = 0, delay = 0, chargeconfig = 0;
-+
-+	/*
-+ 	 * Step Configuration
-+ 	 * software-enabled continous mode
-+ 	 * 2 sample averaging
-+ 	 * sample channel 1 (SEL_INP mux bits = 0)
-+ 	 */
-+	stepconfig = TSCADC_STEPCONFIG_MODE_SWONESHOT |
-+		TSCADC_STEPCONFIG_2SAMPLES_AVG |
-+		((channel-1) << 19);
-+	
-+	delay = TSCADC_STEPCONFIG_SAMPLEDLY | TSCADC_STEPCONFIG_OPENDLY;
-+
-+	tscadc_writel(ts_dev, TSCADC_REG_STEPCONFIG(10), stepconfig);
-+	tscadc_writel(ts_dev, TSCADC_REG_STEPDELAY(10), delay);
-+	
-+	/* Get the ball rolling, this will trigger the FSM to step through
-+ 	 * as soon as TSC_ADC_SS is turned on */
-+	tscadc_writel(ts_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_GENERAL);
-+}
-+
-+static irqreturn_t tsc_adc_interrupt(int irq, void *dev)
-+{
-+	struct tscadc		*ts_dev = (struct tscadc *)dev;
-+	struct input_dev	*input_dev = ts_dev->input;
-+	unsigned int		status, irqclr = 0;
-+	int			i;
-+	int			fsm = 0, fifo0count = 0, fifo1count = 0;
-+	unsigned int		read_sample = 0, ready1 = 0;
-+	unsigned int		prev_val_x = ~0, prev_val_y = ~0;
-+	unsigned int		prev_diff_x = ~0, prev_diff_y = ~0;
-+	unsigned int		cur_diff_x = 0, cur_diff_y = 0;
-+	unsigned int		val_x = 0, val_y = 0, diffx = 0, diffy = 0;
-+
-+	status = tscadc_readl(ts_dev, TSCADC_REG_IRQSTATUS);
-+
-+	// printk("interrupt! status=%x\n", status);
-+	// if (status & TSCADC_IRQENB_EOS) {
-+	// 	irqclr |= TSCADC_IRQENB_EOS;
-+	// }
-+
-+	if (status & TSCADC_IRQENB_FIFO0THRES) {
-+		fifo1count = tscadc_readl(ts_dev, TSCADC_REG_FIFO0CNT);
-+		// printk("fifo 0 count = %d\n", fifo1count);
-+	
-+		for (i = 0; i < fifo1count; i++) {
-+			read_sample = tscadc_readl(ts_dev, TSCADC_REG_FIFO0);
-+			printk("sample: %d: %x\n", i, read_sample);
-+		}
-+		irqclr |= TSCADC_IRQENB_FIFO0THRES;
-+	}
-+
-+
-+	if (status & TSCADC_IRQENB_FIFO1THRES) {
-+		fifo1count = tscadc_readl(ts_dev, TSCADC_REG_FIFO1CNT);
-+
-+		for (i = 0; i < fifo1count; i++) {
-+			read_sample = tscadc_readl(ts_dev, TSCADC_REG_FIFO1);
-+			// read_sample = read_sample & 0xfff;
-+			printk("sample: %d: %d\n", i, read_sample);
-+			panic("sample read from fifo1!");
-+		}
-+		irqclr |= TSCADC_IRQENB_FIFO1THRES;
-+	}
-+
-+	// mdelay(500);
-+
-+	tscadc_writel(ts_dev, TSCADC_REG_IRQSTATUS, irqclr);
-+
-+	/* check pending interrupts */
-+	tscadc_writel(ts_dev, TSCADC_REG_IRQEOI, 0x0);
-+
-+	/* Turn on Step 1 again */
-+	// tscadc_writel(ts_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_GENERAL);
-+	return IRQ_HANDLED;
-+}
-+
-+static void tsc_step_config(struct tscadc *ts_dev)
-+{
-+	unsigned int	stepconfigx = 0, stepconfigy = 0;
-+	unsigned int	delay, chargeconfig = 0;
-+	unsigned int	stepconfigz1 = 0, stepconfigz2 = 0;
-+	int i;
-+
-+	/* Configure the Step registers */
-+
-+	delay = TSCADC_STEPCONFIG_SAMPLEDLY | TSCADC_STEPCONFIG_OPENDLY;
-+
-+	stepconfigx = TSCADC_STEPCONFIG_MODE_HWSYNC |
-+			TSCADC_STEPCONFIG_2SAMPLES_AVG | TSCADC_STEPCONFIG_XPP;
-+
-+	switch (ts_dev->wires) {
-+	case 4:
-+		if (ts_dev->analog_input == 0)
-+			stepconfigx |= TSCADC_STEPCONFIG_INP_4 |
-+				TSCADC_STEPCONFIG_YPN;
-+		else
-+			stepconfigx |= TSCADC_STEPCONFIG_INP |
-+				TSCADC_STEPCONFIG_XNN;
-+		break;
-+	case 5:
-+		stepconfigx |= TSCADC_STEPCONFIG_YNN |
-+				TSCADC_STEPCONFIG_INP_5;
-+		if (ts_dev->analog_input == 0)
-+			stepconfigx |= TSCADC_STEPCONFIG_XNP |
-+				TSCADC_STEPCONFIG_YPN;
-+		else
-+			stepconfigx |= TSCADC_STEPCONFIG_XNN |
-+				TSCADC_STEPCONFIG_YPP;
-+		break;
-+	case 8:
-+		if (ts_dev->analog_input == 0)
-+			stepconfigx |= TSCADC_STEPCONFIG_INP_4 |
-+				TSCADC_STEPCONFIG_YPN;
-+		else
-+			stepconfigx |= TSCADC_STEPCONFIG_INP |
-+				TSCADC_STEPCONFIG_XNN;
-+		break;
-+	}
-+
-+	for (i = 1; i < 7; i++) {
-+		tscadc_writel(ts_dev, TSCADC_REG_STEPCONFIG(i), stepconfigx);
-+		tscadc_writel(ts_dev, TSCADC_REG_STEPDELAY(i), delay);
-+	}
-+
-+	stepconfigy = TSCADC_STEPCONFIG_MODE_HWSYNC |
-+			TSCADC_STEPCONFIG_2SAMPLES_AVG | TSCADC_STEPCONFIG_YNN |
-+			TSCADC_STEPCONFIG_INM | TSCADC_STEPCONFIG_FIFO1;
-+	switch (ts_dev->wires) {
-+	case 4:
-+		if (ts_dev->analog_input == 0)
-+			stepconfigy |= TSCADC_STEPCONFIG_XNP;
-+		else
-+			stepconfigy |= TSCADC_STEPCONFIG_YPP;
-+		break;
-+	case 5:
-+		stepconfigy |= TSCADC_STEPCONFIG_XPP | TSCADC_STEPCONFIG_INP_5;
-+		if (ts_dev->analog_input == 0)
-+			stepconfigy |= TSCADC_STEPCONFIG_XNN |
-+				TSCADC_STEPCONFIG_YPP;
-+		else
-+			stepconfigy |= TSCADC_STEPCONFIG_XNP |
-+				TSCADC_STEPCONFIG_YPN;
-+		break;
-+	case 8:
-+		if (ts_dev->analog_input == 0)
-+			stepconfigy |= TSCADC_STEPCONFIG_XNP;
-+		else
-+			stepconfigy |= TSCADC_STEPCONFIG_YPP;
-+		break;
-+	}
-+
-+	for (i = 7; i < 13; i++) {
-+		tscadc_writel(ts_dev, TSCADC_REG_STEPCONFIG(i), stepconfigy);
-+		tscadc_writel(ts_dev, TSCADC_REG_STEPDELAY(i), delay);
-+	}
-+
-+	chargeconfig = TSCADC_STEPCONFIG_XPP |
-+			TSCADC_STEPCONFIG_YNN |
-+			TSCADC_STEPCONFIG_RFP |
-+			TSCADC_STEPCHARGE_RFM;
-+	if (ts_dev->analog_input == 0)
-+		chargeconfig |= TSCADC_STEPCHARGE_INM_SWAP |
-+			TSCADC_STEPCHARGE_INP_SWAP;
-+	else
-+		chargeconfig |= TSCADC_STEPCHARGE_INM | TSCADC_STEPCHARGE_INP;
-+	tscadc_writel(ts_dev, TSCADC_REG_CHARGECONFIG, chargeconfig);
-+	tscadc_writel(ts_dev, TSCADC_REG_CHARGEDELAY, TSCADC_STEPCHARGE_DELAY);
-+
-+	 /* Configure to calculate pressure */
-+	stepconfigz1 = TSCADC_STEPCONFIG_MODE_HWSYNC |
-+				TSCADC_STEPCONFIG_2SAMPLES_AVG |
-+				TSCADC_STEPCONFIG_XNP |
-+				TSCADC_STEPCONFIG_YPN | TSCADC_STEPCONFIG_INM;
-+	stepconfigz2 = stepconfigz1 | TSCADC_STEPCONFIG_Z1 |
-+				TSCADC_STEPCONFIG_FIFO1;
-+	tscadc_writel(ts_dev, TSCADC_REG_STEPCONFIG13, stepconfigz1);
-+	tscadc_writel(ts_dev, TSCADC_REG_STEPDELAY13, delay);
-+	tscadc_writel(ts_dev, TSCADC_REG_STEPCONFIG14, stepconfigz2);
-+	tscadc_writel(ts_dev, TSCADC_REG_STEPDELAY14, delay);
-+
-+	tscadc_writel(ts_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_TOUCHSCREEN);
-+}
-+
-+static void tsc_idle_config(struct tscadc *ts_config)
-+{
-+	/* Idle mode touch screen config */
-+	unsigned int	 idleconfig;
-+
-+	idleconfig = TSCADC_STEPCONFIG_YNN |
-+			TSCADC_STEPCONFIG_INM | TSCADC_STEPCONFIG_IDLE_INP;
-+	if (ts_config->analog_input == 0)
-+		idleconfig |= TSCADC_STEPCONFIG_XNN;
-+	else
-+		idleconfig |= TSCADC_STEPCONFIG_YPN;
-+
-+	tscadc_writel(ts_config, TSCADC_REG_IDLECONFIG, idleconfig);
-+}
-+
-+static irqreturn_t tsc_interrupt(int irq, void *dev)
-+{
-+	struct tscadc		*ts_dev = (struct tscadc *)dev;
-+	struct input_dev	*input_dev = ts_dev->input;
-+	unsigned int		status, irqclr = 0;
-+	int			i;
-+	int			fsm = 0, fifo0count = 0, fifo1count = 0;
-+	unsigned int		readx1 = 0, ready1 = 0;
-+	unsigned int		prev_val_x = ~0, prev_val_y = ~0;
-+	unsigned int		prev_diff_x = ~0, prev_diff_y = ~0;
-+	unsigned int		cur_diff_x = 0, cur_diff_y = 0;
-+	unsigned int		val_x = 0, val_y = 0, diffx = 0, diffy = 0;
-+	unsigned int		z1 = 0, z2 = 0, z = 0;
-+
-+	status = tscadc_readl(ts_dev, TSCADC_REG_IRQSTATUS);
-+
-+	if (status & TSCADC_IRQENB_FIFO1THRES) {
-+		fifo0count = tscadc_readl(ts_dev, TSCADC_REG_FIFO0CNT);
-+		fifo1count = tscadc_readl(ts_dev, TSCADC_REG_FIFO1CNT);
-+		for (i = 0; i < (fifo0count-1); i++) {
-+			readx1 = tscadc_readl(ts_dev, TSCADC_REG_FIFO0);
-+			readx1 = readx1 & 0xfff;
-+			if (readx1 > prev_val_x)
-+				cur_diff_x = readx1 - prev_val_x;
-+			else
-+				cur_diff_x = prev_val_x - readx1;
-+
-+			if (cur_diff_x < prev_diff_x) {
-+				prev_diff_x = cur_diff_x;
-+				val_x = readx1;
-+			}
-+
-+			prev_val_x = readx1;
-+			ready1 = tscadc_readl(ts_dev, TSCADC_REG_FIFO1);
-+				ready1 &= 0xfff;
-+			if (ready1 > prev_val_y)
-+				cur_diff_y = ready1 - prev_val_y;
-+			else
-+				cur_diff_y = prev_val_y - ready1;
-+
-+			if (cur_diff_y < prev_diff_y) {
-+				prev_diff_y = cur_diff_y;
-+				val_y = ready1;
-+			}
-+
-+			prev_val_y = ready1;
-+		}
-+
-+		if (val_x > bckup_x) {
-+			diffx = val_x - bckup_x;
-+			diffy = val_y - bckup_y;
-+		} else {
-+			diffx = bckup_x - val_x;
-+			diffy = bckup_y - val_y;
-+		}
-+		bckup_x = val_x;
-+		bckup_y = val_y;
-+
-+		z1 = ((tscadc_readl(ts_dev, TSCADC_REG_FIFO0)) & 0xfff);
-+		z2 = ((tscadc_readl(ts_dev, TSCADC_REG_FIFO1)) & 0xfff);
-+
-+		if ((z1 != 0) && (z2 != 0)) {
-+			/*
-+			 * cal pressure using formula
-+			 * Resistance(touch) = x plate resistance *
-+			 * x postion/4096 * ((z2 / z1) - 1)
-+			 */
-+			z = z2 - z1;
-+			z *= val_x;
-+			z *= ts_dev->x_plate_resistance;
-+			z /= z1;
-+			z = (z + 2047) >> 12;
-+
-+			/*
-+			 * Sample found inconsistent by debouncing
-+			 * or pressure is beyond the maximum.
-+			 * Don't report it to user space.
-+			 */
-+			if (pen == 0) {
-+				if ((diffx < 15) && (diffy < 15)
-+						&& (z <= MAX_12BIT)) {
-+					input_report_abs(input_dev, ABS_X,
-+							val_x);
-+					input_report_abs(input_dev, ABS_Y,
-+							val_y);
-+					input_report_abs(input_dev, ABS_PRESSURE,
-+							z);
-+					input_report_key(input_dev, BTN_TOUCH,
-+							1);
-+					input_sync(input_dev);
-+				}
-+			}
-+		}
-+		irqclr |= TSCADC_IRQENB_FIFO1THRES;
-+	}
-+
-+	udelay(315);
-+
-+	status = tscadc_readl(ts_dev, TSCADC_REG_RAWIRQSTATUS);
-+	if (status & TSCADC_IRQENB_PENUP) {
-+		/* Pen up event */
-+		fsm = tscadc_readl(ts_dev, TSCADC_REG_ADCFSM);
-+		if (fsm == 0x10) {
-+			pen = 1;
-+			bckup_x = 0;
-+			bckup_y = 0;
-+			input_report_key(input_dev, BTN_TOUCH, 0);
-+			input_report_abs(input_dev, ABS_PRESSURE, 0);
-+			input_sync(input_dev);
-+		} else {
-+			pen = 0;
-+		}
-+		irqclr |= TSCADC_IRQENB_PENUP;
-+	}
-+	irqclr |= TSCADC_IRQENB_HW_PEN;
-+
-+	tscadc_writel(ts_dev, TSCADC_REG_IRQSTATUS, irqclr);
-+
-+	/* check pending interrupts */
-+	tscadc_writel(ts_dev, TSCADC_REG_IRQEOI, 0x0);
-+
-+	tscadc_writel(ts_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_TOUCHSCREEN);
-+	return IRQ_HANDLED;
-+}
-+
-+/*
-+* The functions for inserting/removing driver as a module.
-+*/
-+
-+size_t do_adc_sample(struct kobject *kobj, struct attribute *attr, char *buf) {
-+	struct platform_device *pdev;
-+	struct device *dev;
-+	struct tscadc *ts_dev;
-+	int channel_num;
-+	int fifo0count = 0;
-+	int read_sample = 0;
-+
-+	pdev = (struct platform_device *)container_of(kobj, struct device, kobj);
-+	dev = &pdev->dev;
-+
-+	ts_dev = dev_get_drvdata(dev);
-+
-+	if(strncmp(attr->name, "ain", 3)) {
-+		printk("Invalid ain num\n");
-+		return -EINVAL;
-+	}
-+
-+	channel_num = attr->name[3] - 0x30;
-+	if(channel_num > 8 || channel_num < 1) {
-+		printk("Invalid channel_num=%d\n", channel_num);
-+		return -EINVAL;
-+	}
-+
-+	tsc_adc_step_config(ts_dev, channel_num);
-+
-+	do {
-+		fifo0count = tscadc_readl(ts_dev, TSCADC_REG_FIFO0CNT);
-+	}
-+	while (!fifo0count);
-+
-+	while (fifo0count--) {
-+			  read_sample = tscadc_readl(ts_dev, TSCADC_REG_FIFO0) & 0xfff;
-+			  // printk("polling sample: %d: %x\n", fifo0count, read_sample);
-+	}
-+	sprintf(buf, "%d", read_sample);
-+
-+	return strlen(attr->name);
-+}
-+
-+static	int __devinit tscadc_probe(struct platform_device *pdev)
-+{
-+	struct tscadc			*ts_dev;
-+	struct input_dev		*input_dev = NULL;
-+	int				err;
-+	int				clk_value;
-+	int				clock_rate, irqenable, ctrl;
-+	struct	tsc_data		*pdata = pdev->dev.platform_data;
-+	struct resource			*res;
-+	struct clk			*clk;
-+
-+	printk("dev addr = %p\n", &pdev->dev);
-+	printk("pdev addr = %p\n", pdev);
-+
-+	device_create_file(&pdev->dev, &dev_attr_ain1);
-+	device_create_file(&pdev->dev, &dev_attr_ain2);
-+	device_create_file(&pdev->dev, &dev_attr_ain3);
-+	device_create_file(&pdev->dev, &dev_attr_ain4);
-+	device_create_file(&pdev->dev, &dev_attr_ain5);
-+	device_create_file(&pdev->dev, &dev_attr_ain6);
-+	device_create_file(&pdev->dev, &dev_attr_ain7);
-+	device_create_file(&pdev->dev, &dev_attr_ain8);
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res) {
-+		dev_err(&pdev->dev, "no memory resource defined.\n");
-+		return -EINVAL;
-+	}
-+
-+	/* Allocate memory for device */
-+	ts_dev = kzalloc(sizeof(struct tscadc), GFP_KERNEL);
-+	if (!ts_dev) {
-+		dev_err(&pdev->dev, "failed to allocate memory.\n");
-+		return -ENOMEM;
-+	}
-+
-+	ts_dev->irq = platform_get_irq(pdev, 0);
-+	if (ts_dev->irq < 0) {
-+		dev_err(&pdev->dev, "no irq ID is specified.\n");
-+		return -ENODEV;
-+	}
-+
-+	if(pdata->mode == TI_TSCADC_TSCMODE) {
-+		input_dev = input_allocate_device();
-+		if (!input_dev) {
-+			dev_err(&pdev->dev, "failed to allocate input device.\n");
-+			err = -ENOMEM;
-+			goto err_free_mem;
-+		}
-+		ts_dev->input = input_dev;
-+	}
-+
-+	res =  request_mem_region(res->start, resource_size(res), pdev->name);
-+	if (!res) {
-+		dev_err(&pdev->dev, "failed to reserve registers.\n");
-+		err = -EBUSY;
-+		goto err_free_mem;
-+	}
-+
-+	ts_dev->tsc_base = ioremap(res->start, resource_size(res));
-+	if (!ts_dev->tsc_base) {
-+		dev_err(&pdev->dev, "failed to map registers.\n");
-+		err = -ENOMEM;
-+		goto err_release_mem;
-+	}
-+
-+	if(pdata->mode == TI_TSCADC_TSCMODE) {
-+		err = request_irq(ts_dev->irq, tsc_interrupt, IRQF_DISABLED,
-+					pdev->dev.driver->name, ts_dev);
-+	}
-+	else {
-+		err = request_irq(ts_dev->irq, tsc_adc_interrupt, IRQF_DISABLED,
-+					pdev->dev.driver->name, ts_dev);
-+	}
-+
-+	if (err) {
-+		dev_err(&pdev->dev, "failed to allocate irq.\n");
-+		goto err_unmap_regs;
-+	}
-+
-+	pm_runtime_enable(&pdev->dev);
-+	pm_runtime_get_sync(&pdev->dev);
-+
-+	clk = clk_get(&pdev->dev, "adc_tsc_fck");
-+	if (IS_ERR(clk)) {
-+		dev_err(&pdev->dev, "failed to get TSC fck\n");
-+		err = PTR_ERR(clk);
-+		goto err_free_irq;
-+	}
-+	clock_rate = clk_get_rate(clk);
-+
-+	/* clk_value of atleast 21MHz required
-+ 	 * Clock verified on BeagleBone to be 24MHz */
-+
-+
-+	clk_value = clock_rate / ADC_CLK;
-+	if (clk_value < 7) {
-+		dev_err(&pdev->dev, "clock input less than min clock requirement\n");
-+		err = -EINVAL;
-+		goto err_fail;
-+	}
-+
-+	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
-+	clk_value = clk_value - 1;
-+	tscadc_writel(ts_dev, TSCADC_REG_CLKDIV, clk_value);
-+
-+	ts_dev->wires = pdata->wires;
-+	ts_dev->analog_input = pdata->analog_input;
-+	ts_dev->x_plate_resistance = pdata->x_plate_resistance;
-+	ts_dev->mode = pdata->mode;
-+
-+	/* Set the control register bits - 12.5.44 TRM */
-+	ctrl = TSCADC_CNTRLREG_STEPCONFIGWRT |
-+				TSCADC_CNTRLREG_STEPID;
-+	if(pdata->mode == TI_TSCADC_TSCMODE) {
-+		ctrl |= TSCADC_CNTRLREG_TSCENB;
-+		switch (ts_dev->wires) {
-+			case 4:
-+				ctrl |= TSCADC_CNTRLREG_4WIRE;
-+				break;
-+			case 5:
-+				ctrl |= TSCADC_CNTRLREG_5WIRE;
-+				break;
-+			case 8:
-+				ctrl |= TSCADC_CNTRLREG_8WIRE;
-+				break;
-+		}
-+	}
-+	tscadc_writel(ts_dev, TSCADC_REG_CTRL, ctrl);
-+	ts_dev->ctrl = ctrl;
-+
-+	/* Touch screen / ADC configuration */
-+	if(pdata->mode == TI_TSCADC_TSCMODE) {
-+		tsc_idle_config(ts_dev);
-+		tsc_step_config(ts_dev);
-+		tscadc_writel(ts_dev, TSCADC_REG_FIFO1THR, 6);
-+		irqenable = TSCADC_IRQENB_FIFO1THRES;
-+		/* Touch screen also needs an input_dev */
-+		input_dev->name = "ti-tsc-adcc";
-+		input_dev->dev.parent = &pdev->dev;
-+		input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
-+		input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
-+		input_set_abs_params(input_dev, ABS_X, 0, MAX_12BIT, 0, 0);
-+		input_set_abs_params(input_dev, ABS_Y, 0, MAX_12BIT, 0, 0);
-+		/* register to the input system */
-+		err = input_register_device(input_dev);
-+		if (err)
-+			goto err_fail;
-+	}
-+	else {
-+		tscadc_writel(ts_dev, TSCADC_REG_FIFO0THR, 0);
-+		irqenable = 0; // TSCADC_IRQENB_FIFO0THRES;
-+	}
-+	tscadc_writel(ts_dev, TSCADC_REG_IRQENABLE, irqenable);
-+
-+	ctrl |= TSCADC_CNTRLREG_TSCSSENB;
-+	tscadc_writel(ts_dev, TSCADC_REG_CTRL, ctrl);	/* Turn on TSC_ADC */
-+
-+	device_init_wakeup(&pdev->dev, true);
-+	platform_set_drvdata(pdev, ts_dev);
-+	return 0;
-+
-+err_fail:
-+	pm_runtime_disable(&pdev->dev);
-+err_free_irq:
-+	free_irq(ts_dev->irq, ts_dev);
-+err_unmap_regs:
-+	iounmap(ts_dev->tsc_base);
-+err_release_mem:
-+	release_mem_region(res->start, resource_size(res));
-+	input_free_device(ts_dev->input);
-+err_free_mem:
-+	kfree(ts_dev);
-+	return err;
-+}
-+
-+static int __devexit tscadc_remove(struct platform_device *pdev)
-+{
-+	struct tscadc		*ts_dev = platform_get_drvdata(pdev);
-+	struct resource		*res;
-+
-+	free_irq(ts_dev->irq, ts_dev);
-+
-+	input_unregister_device(ts_dev->input);
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	iounmap(ts_dev->tsc_base);
-+	release_mem_region(res->start, resource_size(res));
-+
-+	pm_runtime_disable(&pdev->dev);
-+
-+	kfree(ts_dev);
-+
-+	device_init_wakeup(&pdev->dev, 0);
-+	platform_set_drvdata(pdev, NULL);
-+	return 0;
-+}
-+
-+static int tscadc_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+	struct tscadc *ts_dev = platform_get_drvdata(pdev);
-+	unsigned int idle;
-+
-+	if (device_may_wakeup(&pdev->dev)) {
-+		idle = tscadc_readl(ts_dev, TSCADC_REG_IRQENABLE);
-+		tscadc_writel(ts_dev, TSCADC_REG_IRQENABLE,
-+				(idle | TSCADC_IRQENB_HW_PEN));
-+		tscadc_writel(ts_dev, TSCADC_REG_IRQWAKEUP, TSCADC_IRQWKUP_ENB);
-+	}
-+
-+	/* module disable */
-+	idle = 0;
-+	idle = tscadc_readl(ts_dev, TSCADC_REG_CTRL);
-+	idle &= ~(TSCADC_CNTRLREG_TSCSSENB);
-+	tscadc_writel(ts_dev, TSCADC_REG_CTRL, idle);
-+
-+	pm_runtime_put_sync(&pdev->dev);
-+
-+	return 0;
-+
-+}
-+
-+static int tscadc_resume(struct platform_device *pdev)
-+{
-+	struct tscadc *ts_dev = platform_get_drvdata(pdev);
-+	unsigned int restore;
-+
-+	pm_runtime_get_sync(&pdev->dev);
-+
-+	if (device_may_wakeup(&pdev->dev)) {
-+		tscadc_writel(ts_dev, TSCADC_REG_IRQWAKEUP,
-+				TSCADC_IRQWKUP_DISABLE);
-+		tscadc_writel(ts_dev, TSCADC_REG_IRQCLR, TSCADC_IRQENB_HW_PEN);
-+	}
-+
-+	/* context restore */
-+	tscadc_writel(ts_dev, TSCADC_REG_CTRL, ts_dev->ctrl);
-+	tsc_idle_config(ts_dev);
-+	tsc_step_config(ts_dev);
-+	tscadc_writel(ts_dev, TSCADC_REG_FIFO1THR, 6);
-+	restore = tscadc_readl(ts_dev, TSCADC_REG_CTRL);
-+	tscadc_writel(ts_dev, TSCADC_REG_CTRL,
-+			(restore | TSCADC_CNTRLREG_TSCSSENB));
-+
-+	return 0;
-+}
-+
-+static struct platform_driver ti_tsc_driver = {
-+	.probe	  = tscadc_probe,
-+	.remove	 = __devexit_p(tscadc_remove),
-+	.driver	 = {
-+		.name   = "tsc",
-+		.owner  = THIS_MODULE,
-+	},
-+	.suspend = tscadc_suspend,
-+	.resume  = tscadc_resume,
-+};
-+
-+static int __init ti_tsc_init(void)
-+{
-+	return platform_driver_register(&ti_tsc_driver);
-+}
-+module_init(ti_tsc_init);
-+
-+static void __exit ti_tsc_exit(void)
-+{
-+	platform_driver_unregister(&ti_tsc_driver);
-+}
-+module_exit(ti_tsc_exit);
-+
-+MODULE_DESCRIPTION("TI touchscreen controller driver");
-+MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
-index aba706c..8f32b2b 100644
---- a/drivers/iommu/omap-iommu.c
-+++ b/drivers/iommu/omap-iommu.c
-@@ -1229,8 +1229,7 @@ static int __init omap_iommu_init(void)
- 
- 	return platform_driver_register(&omap_iommu_driver);
- }
--/* must be ready before omap3isp is probed */
--subsys_initcall(omap_iommu_init);
-+module_init(omap_iommu_init);
- 
- static void __exit omap_iommu_exit(void)
- {
-diff --git a/drivers/media/rc/ene_ir.c b/drivers/media/rc/ene_ir.c
-index cf10ecf..860c112 100644
---- a/drivers/media/rc/ene_ir.c
-+++ b/drivers/media/rc/ene_ir.c
-@@ -324,7 +324,7 @@ static int ene_rx_get_sample_reg(struct ene_device *dev)
- 		return dev->extra_buf2_address + r_pointer;
- 	}
- 
--	dbg("attempt to read beyong ring bufer end");
-+	dbg("attempt to read beyond ring buffer end");
- 	return 0;
- }
- 
-diff --git a/drivers/media/rc/ene_ir.h b/drivers/media/rc/ene_ir.h
-index fd108d9..6f978e8 100644
---- a/drivers/media/rc/ene_ir.h
-+++ b/drivers/media/rc/ene_ir.h
-@@ -227,7 +227,7 @@ struct ene_device {
- 
- 	/* TX buffer */
- 	unsigned *tx_buffer;			/* input samples buffer*/
--	int tx_pos;				/* position in that bufer */
-+	int tx_pos;				/* position in that buffer */
- 	int tx_len;				/* current len of tx buffer */
- 	int tx_done;				/* done transmitting */
- 						/* one more sample pending*/
-diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
-index f1391c2..d2c55e8 100644
---- a/drivers/mfd/Kconfig
-+++ b/drivers/mfd/Kconfig
-@@ -142,6 +142,21 @@ config TPS6507X
- 	  This driver can also be built as a module.  If so, the module
- 	  will be called tps6507x.
- 
-+config MFD_TPS65217
-+	tristate "TPS65217 Power Management / White LED chips"
-+	depends on I2C
-+	select MFD_CORE
-+	select REGMAP_I2C
-+	help
-+	  If you say yes here you get support for the TPS65217 series of
-+	  Power Management / White LED chips.
-+	  These include voltage regulators, lithium ion/polymer battery
-+	  charger, wled and other features that are often used in portable
-+	  devices.
-+
-+	  This driver can also be built as a module.  If so, the module
-+	  will be called tps65217.
-+
- config MFD_TPS6586X
- 	bool "TPS6586x Power Management chips"
- 	depends on I2C=y && GPIOLIB && GENERIC_HARDIRQS
-diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
-index b2292eb..7a6d111 100644
---- a/drivers/mfd/Makefile
-+++ b/drivers/mfd/Makefile
-@@ -36,6 +36,7 @@ obj-$(CONFIG_MFD_WM8994)	+= wm8994-core.o wm8994-irq.o
- obj-$(CONFIG_TPS6105X)		+= tps6105x.o
- obj-$(CONFIG_TPS65010)		+= tps65010.o
- obj-$(CONFIG_TPS6507X)		+= tps6507x.o
-+obj-$(CONFIG_MFD_TPS65217)	+= tps65217.o
- obj-$(CONFIG_MFD_TPS65910)	+= tps65910.o tps65910-irq.o
- tps65912-objs                   := tps65912-core.o tps65912-irq.o
- obj-$(CONFIG_MFD_TPS65912)	+= tps65912.o
-diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
-index 86e1458..3f565ef 100644
---- a/drivers/mfd/omap-usb-host.c
-+++ b/drivers/mfd/omap-usb-host.c
-@@ -27,8 +27,9 @@
- #include <linux/spinlock.h>
- #include <linux/gpio.h>
- #include <plat/usb.h>
-+#include <linux/pm_runtime.h>
- 
--#define USBHS_DRIVER_NAME	"usbhs-omap"
-+#define USBHS_DRIVER_NAME	"usbhs_omap"
- #define OMAP_EHCI_DEVICE	"ehci-omap"
- #define OMAP_OHCI_DEVICE	"ohci-omap3"
- 
-@@ -147,9 +148,6 @@
- 
- 
- struct usbhs_hcd_omap {
--	struct clk			*usbhost_ick;
--	struct clk			*usbhost_hs_fck;
--	struct clk			*usbhost_fs_fck;
- 	struct clk			*xclk60mhsp1_ck;
- 	struct clk			*xclk60mhsp2_ck;
- 	struct clk			*utmi_p1_fck;
-@@ -159,8 +157,7 @@ struct usbhs_hcd_omap {
- 	struct clk			*usbhost_p2_fck;
- 	struct clk			*usbtll_p2_fck;
- 	struct clk			*init_60m_fclk;
--	struct clk			*usbtll_fck;
--	struct clk			*usbtll_ick;
-+	struct clk			*ehci_logic_fck;
- 
- 	void __iomem			*uhh_base;
- 	void __iomem			*tll_base;
-@@ -169,7 +166,6 @@ struct usbhs_hcd_omap {
- 
- 	u32				usbhs_rev;
- 	spinlock_t			lock;
--	int				count;
- };
- /*-------------------------------------------------------------------------*/
- 
-@@ -319,269 +315,6 @@ err_end:
- 	return ret;
- }
- 
--/**
-- * usbhs_omap_probe - initialize TI-based HCDs
-- *
-- * Allocates basic resources for this USB host controller.
-- */
--static int __devinit usbhs_omap_probe(struct platform_device *pdev)
--{
--	struct device			*dev =  &pdev->dev;
--	struct usbhs_omap_platform_data	*pdata = dev->platform_data;
--	struct usbhs_hcd_omap		*omap;
--	struct resource			*res;
--	int				ret = 0;
--	int				i;
--
--	if (!pdata) {
--		dev_err(dev, "Missing platform data\n");
--		ret = -ENOMEM;
--		goto end_probe;
--	}
--
--	omap = kzalloc(sizeof(*omap), GFP_KERNEL);
--	if (!omap) {
--		dev_err(dev, "Memory allocation failed\n");
--		ret = -ENOMEM;
--		goto end_probe;
--	}
--
--	spin_lock_init(&omap->lock);
--
--	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
--		omap->platdata.port_mode[i] = pdata->port_mode[i];
--
--	omap->platdata.ehci_data = pdata->ehci_data;
--	omap->platdata.ohci_data = pdata->ohci_data;
--
--	omap->usbhost_ick = clk_get(dev, "usbhost_ick");
--	if (IS_ERR(omap->usbhost_ick)) {
--		ret =  PTR_ERR(omap->usbhost_ick);
--		dev_err(dev, "usbhost_ick failed error:%d\n", ret);
--		goto err_end;
--	}
--
--	omap->usbhost_hs_fck = clk_get(dev, "hs_fck");
--	if (IS_ERR(omap->usbhost_hs_fck)) {
--		ret = PTR_ERR(omap->usbhost_hs_fck);
--		dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret);
--		goto err_usbhost_ick;
--	}
--
--	omap->usbhost_fs_fck = clk_get(dev, "fs_fck");
--	if (IS_ERR(omap->usbhost_fs_fck)) {
--		ret = PTR_ERR(omap->usbhost_fs_fck);
--		dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret);
--		goto err_usbhost_hs_fck;
--	}
--
--	omap->usbtll_fck = clk_get(dev, "usbtll_fck");
--	if (IS_ERR(omap->usbtll_fck)) {
--		ret = PTR_ERR(omap->usbtll_fck);
--		dev_err(dev, "usbtll_fck failed error:%d\n", ret);
--		goto err_usbhost_fs_fck;
--	}
--
--	omap->usbtll_ick = clk_get(dev, "usbtll_ick");
--	if (IS_ERR(omap->usbtll_ick)) {
--		ret = PTR_ERR(omap->usbtll_ick);
--		dev_err(dev, "usbtll_ick failed error:%d\n", ret);
--		goto err_usbtll_fck;
--	}
--
--	omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
--	if (IS_ERR(omap->utmi_p1_fck)) {
--		ret = PTR_ERR(omap->utmi_p1_fck);
--		dev_err(dev, "utmi_p1_gfclk failed error:%d\n",	ret);
--		goto err_usbtll_ick;
--	}
--
--	omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
--	if (IS_ERR(omap->xclk60mhsp1_ck)) {
--		ret = PTR_ERR(omap->xclk60mhsp1_ck);
--		dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
--		goto err_utmi_p1_fck;
--	}
--
--	omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
--	if (IS_ERR(omap->utmi_p2_fck)) {
--		ret = PTR_ERR(omap->utmi_p2_fck);
--		dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
--		goto err_xclk60mhsp1_ck;
--	}
--
--	omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
--	if (IS_ERR(omap->xclk60mhsp2_ck)) {
--		ret = PTR_ERR(omap->xclk60mhsp2_ck);
--		dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
--		goto err_utmi_p2_fck;
--	}
--
--	omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
--	if (IS_ERR(omap->usbhost_p1_fck)) {
--		ret = PTR_ERR(omap->usbhost_p1_fck);
--		dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
--		goto err_xclk60mhsp2_ck;
--	}
--
--	omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
--	if (IS_ERR(omap->usbtll_p1_fck)) {
--		ret = PTR_ERR(omap->usbtll_p1_fck);
--		dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
--		goto err_usbhost_p1_fck;
--	}
--
--	omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
--	if (IS_ERR(omap->usbhost_p2_fck)) {
--		ret = PTR_ERR(omap->usbhost_p2_fck);
--		dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
--		goto err_usbtll_p1_fck;
--	}
--
--	omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
--	if (IS_ERR(omap->usbtll_p2_fck)) {
--		ret = PTR_ERR(omap->usbtll_p2_fck);
--		dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
--		goto err_usbhost_p2_fck;
--	}
--
--	omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
--	if (IS_ERR(omap->init_60m_fclk)) {
--		ret = PTR_ERR(omap->init_60m_fclk);
--		dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
--		goto err_usbtll_p2_fck;
--	}
--
--	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
--	if (!res) {
--		dev_err(dev, "UHH EHCI get resource failed\n");
--		ret = -ENODEV;
--		goto err_init_60m_fclk;
--	}
--
--	omap->uhh_base = ioremap(res->start, resource_size(res));
--	if (!omap->uhh_base) {
--		dev_err(dev, "UHH ioremap failed\n");
--		ret = -ENOMEM;
--		goto err_init_60m_fclk;
--	}
--
--	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
--	if (!res) {
--		dev_err(dev, "UHH EHCI get resource failed\n");
--		ret = -ENODEV;
--		goto err_tll;
--	}
--
--	omap->tll_base = ioremap(res->start, resource_size(res));
--	if (!omap->tll_base) {
--		dev_err(dev, "TLL ioremap failed\n");
--		ret = -ENOMEM;
--		goto err_tll;
--	}
--
--	platform_set_drvdata(pdev, omap);
--
--	ret = omap_usbhs_alloc_children(pdev);
--	if (ret) {
--		dev_err(dev, "omap_usbhs_alloc_children failed\n");
--		goto err_alloc;
--	}
--
--	goto end_probe;
--
--err_alloc:
--	iounmap(omap->tll_base);
--
--err_tll:
--	iounmap(omap->uhh_base);
--
--err_init_60m_fclk:
--	clk_put(omap->init_60m_fclk);
--
--err_usbtll_p2_fck:
--	clk_put(omap->usbtll_p2_fck);
--
--err_usbhost_p2_fck:
--	clk_put(omap->usbhost_p2_fck);
--
--err_usbtll_p1_fck:
--	clk_put(omap->usbtll_p1_fck);
--
--err_usbhost_p1_fck:
--	clk_put(omap->usbhost_p1_fck);
--
--err_xclk60mhsp2_ck:
--	clk_put(omap->xclk60mhsp2_ck);
--
--err_utmi_p2_fck:
--	clk_put(omap->utmi_p2_fck);
--
--err_xclk60mhsp1_ck:
--	clk_put(omap->xclk60mhsp1_ck);
--
--err_utmi_p1_fck:
--	clk_put(omap->utmi_p1_fck);
--
--err_usbtll_ick:
--	clk_put(omap->usbtll_ick);
--
--err_usbtll_fck:
--	clk_put(omap->usbtll_fck);
--
--err_usbhost_fs_fck:
--	clk_put(omap->usbhost_fs_fck);
--
--err_usbhost_hs_fck:
--	clk_put(omap->usbhost_hs_fck);
--
--err_usbhost_ick:
--	clk_put(omap->usbhost_ick);
--
--err_end:
--	kfree(omap);
--
--end_probe:
--	return ret;
--}
--
--/**
-- * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
-- * @pdev: USB Host Controller being removed
-- *
-- * Reverses the effect of usbhs_omap_probe().
-- */
--static int __devexit usbhs_omap_remove(struct platform_device *pdev)
--{
--	struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
--
--	if (omap->count != 0) {
--		dev_err(&pdev->dev,
--			"Either EHCI or OHCI is still using usbhs core\n");
--		return -EBUSY;
--	}
--
--	iounmap(omap->tll_base);
--	iounmap(omap->uhh_base);
--	clk_put(omap->init_60m_fclk);
--	clk_put(omap->usbtll_p2_fck);
--	clk_put(omap->usbhost_p2_fck);
--	clk_put(omap->usbtll_p1_fck);
--	clk_put(omap->usbhost_p1_fck);
--	clk_put(omap->xclk60mhsp2_ck);
--	clk_put(omap->utmi_p2_fck);
--	clk_put(omap->xclk60mhsp1_ck);
--	clk_put(omap->utmi_p1_fck);
--	clk_put(omap->usbtll_ick);
--	clk_put(omap->usbtll_fck);
--	clk_put(omap->usbhost_fs_fck);
--	clk_put(omap->usbhost_hs_fck);
--	clk_put(omap->usbhost_ick);
--	kfree(omap);
--
--	return 0;
--}
--
- static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
- {
- 	switch (pmode) {
-@@ -689,30 +422,85 @@ static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count)
- 	}
- }
- 
--static int usbhs_enable(struct device *dev)
-+static int usbhs_runtime_resume(struct device *dev)
- {
- 	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
- 	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
--	unsigned long			flags = 0;
--	int				ret = 0;
--	unsigned long			timeout;
--	unsigned			reg;
-+	unsigned long			flags;
-+
-+	dev_dbg(dev, "usbhs_runtime_resume\n");
- 
--	dev_dbg(dev, "starting TI HSUSB Controller\n");
- 	if (!pdata) {
- 		dev_dbg(dev, "missing platform_data\n");
- 		return  -ENODEV;
- 	}
- 
- 	spin_lock_irqsave(&omap->lock, flags);
--	if (omap->count > 0)
--		goto end_count;
- 
--	clk_enable(omap->usbhost_ick);
--	clk_enable(omap->usbhost_hs_fck);
--	clk_enable(omap->usbhost_fs_fck);
--	clk_enable(omap->usbtll_fck);
--	clk_enable(omap->usbtll_ick);
-+	if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
-+		clk_enable(omap->ehci_logic_fck);
-+
-+	if (is_ehci_tll_mode(pdata->port_mode[0])) {
-+		clk_enable(omap->usbhost_p1_fck);
-+		clk_enable(omap->usbtll_p1_fck);
-+	}
-+	if (is_ehci_tll_mode(pdata->port_mode[1])) {
-+		clk_enable(omap->usbhost_p2_fck);
-+		clk_enable(omap->usbtll_p2_fck);
-+	}
-+	clk_enable(omap->utmi_p1_fck);
-+	clk_enable(omap->utmi_p2_fck);
-+
-+	spin_unlock_irqrestore(&omap->lock, flags);
-+
-+	return 0;
-+}
-+
-+static int usbhs_runtime_suspend(struct device *dev)
-+{
-+	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
-+	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
-+	unsigned long			flags;
-+
-+	dev_dbg(dev, "usbhs_runtime_suspend\n");
-+
-+	if (!pdata) {
-+		dev_dbg(dev, "missing platform_data\n");
-+		return  -ENODEV;
-+	}
-+
-+	spin_lock_irqsave(&omap->lock, flags);
-+
-+	if (is_ehci_tll_mode(pdata->port_mode[0])) {
-+		clk_disable(omap->usbhost_p1_fck);
-+		clk_disable(omap->usbtll_p1_fck);
-+	}
-+	if (is_ehci_tll_mode(pdata->port_mode[1])) {
-+		clk_disable(omap->usbhost_p2_fck);
-+		clk_disable(omap->usbtll_p2_fck);
-+	}
-+	clk_disable(omap->utmi_p2_fck);
-+	clk_disable(omap->utmi_p1_fck);
-+
-+	if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
-+		clk_disable(omap->ehci_logic_fck);
-+
-+	spin_unlock_irqrestore(&omap->lock, flags);
-+
-+	return 0;
-+}
-+
-+static void omap_usbhs_init(struct device *dev)
-+{
-+	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
-+	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
-+	unsigned long			flags;
-+	unsigned			reg;
-+
-+	dev_dbg(dev, "starting TI HSUSB Controller\n");
-+
-+	pm_runtime_get_sync(dev);
-+	spin_lock_irqsave(&omap->lock, flags);
- 
- 	if (pdata->ehci_data->phy_reset) {
- 		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
-@@ -736,50 +524,6 @@ static int usbhs_enable(struct device *dev)
- 	omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
- 	dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
- 
--	/* perform TLL soft reset, and wait until reset is complete */
--	usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
--			OMAP_USBTLL_SYSCONFIG_SOFTRESET);
--
--	/* Wait for TLL reset to complete */
--	timeout = jiffies + msecs_to_jiffies(1000);
--	while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
--			& OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
--		cpu_relax();
--
--		if (time_after(jiffies, timeout)) {
--			dev_dbg(dev, "operation timed out\n");
--			ret = -EINVAL;
--			goto err_tll;
--		}
--	}
--
--	dev_dbg(dev, "TLL RESET DONE\n");
--
--	/* (1<<3) = no idle mode only for initial debugging */
--	usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
--			OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
--			OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
--			OMAP_USBTLL_SYSCONFIG_AUTOIDLE);
--
--	/* Put UHH in NoIdle/NoStandby mode */
--	reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG);
--	if (is_omap_usbhs_rev1(omap)) {
--		reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
--				| OMAP_UHH_SYSCONFIG_SIDLEMODE
--				| OMAP_UHH_SYSCONFIG_CACTIVITY
--				| OMAP_UHH_SYSCONFIG_MIDLEMODE);
--		reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
--
--
--	} else if (is_omap_usbhs_rev2(omap)) {
--		reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR;
--		reg |= OMAP4_UHH_SYSCONFIG_NOIDLE;
--		reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR;
--		reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY;
--	}
--
--	usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
--
- 	reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
- 	/* setup ULPI bypass and burst configurations */
- 	reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
-@@ -825,49 +569,6 @@ static int usbhs_enable(struct device *dev)
- 		reg &= ~OMAP4_P1_MODE_CLEAR;
- 		reg &= ~OMAP4_P2_MODE_CLEAR;
- 
--		if (is_ehci_phy_mode(pdata->port_mode[0])) {
--			ret = clk_set_parent(omap->utmi_p1_fck,
--						omap->xclk60mhsp1_ck);
--			if (ret != 0) {
--				dev_err(dev, "xclk60mhsp1_ck set parent"
--				"failed error:%d\n", ret);
--				goto err_tll;
--			}
--		} else if (is_ehci_tll_mode(pdata->port_mode[0])) {
--			ret = clk_set_parent(omap->utmi_p1_fck,
--						omap->init_60m_fclk);
--			if (ret != 0) {
--				dev_err(dev, "init_60m_fclk set parent"
--				"failed error:%d\n", ret);
--				goto err_tll;
--			}
--			clk_enable(omap->usbhost_p1_fck);
--			clk_enable(omap->usbtll_p1_fck);
--		}
--
--		if (is_ehci_phy_mode(pdata->port_mode[1])) {
--			ret = clk_set_parent(omap->utmi_p2_fck,
--						omap->xclk60mhsp2_ck);
--			if (ret != 0) {
--				dev_err(dev, "xclk60mhsp1_ck set parent"
--					"failed error:%d\n", ret);
--				goto err_tll;
--			}
--		} else if (is_ehci_tll_mode(pdata->port_mode[1])) {
--			ret = clk_set_parent(omap->utmi_p2_fck,
--						omap->init_60m_fclk);
--			if (ret != 0) {
--				dev_err(dev, "init_60m_fclk set parent"
--				"failed error:%d\n", ret);
--				goto err_tll;
--			}
--			clk_enable(omap->usbhost_p2_fck);
--			clk_enable(omap->usbtll_p2_fck);
--		}
--
--		clk_enable(omap->utmi_p1_fck);
--		clk_enable(omap->utmi_p2_fck);
--
- 		if (is_ehci_tll_mode(pdata->port_mode[0]) ||
- 			(is_ohci_port(pdata->port_mode[0])))
- 			reg |= OMAP4_P1_MODE_TLL;
-@@ -913,12 +614,15 @@ static int usbhs_enable(struct device *dev)
- 				(pdata->ehci_data->reset_gpio_port[1], 1);
- 	}
- 
--end_count:
--	omap->count++;
- 	spin_unlock_irqrestore(&omap->lock, flags);
--	return 0;
-+	pm_runtime_put_sync(dev);
-+}
-+
-+static void omap_usbhs_deinit(struct device *dev)
-+{
-+	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
-+	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
- 
--err_tll:
- 	if (pdata->ehci_data->phy_reset) {
- 		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
- 			gpio_free(pdata->ehci_data->reset_gpio_port[0]);
-@@ -926,123 +630,272 @@ err_tll:
- 		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
- 			gpio_free(pdata->ehci_data->reset_gpio_port[1]);
- 	}
--
--	clk_disable(omap->usbtll_ick);
--	clk_disable(omap->usbtll_fck);
--	clk_disable(omap->usbhost_fs_fck);
--	clk_disable(omap->usbhost_hs_fck);
--	clk_disable(omap->usbhost_ick);
--	spin_unlock_irqrestore(&omap->lock, flags);
--	return ret;
- }
- 
--static void usbhs_disable(struct device *dev)
-+
-+/**
-+ * usbhs_omap_probe - initialize TI-based HCDs
-+ *
-+ * Allocates basic resources for this USB host controller.
-+ */
-+static int __devinit usbhs_omap_probe(struct platform_device *pdev)
- {
--	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
--	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
--	unsigned long			flags = 0;
--	unsigned long			timeout;
-+	struct device			*dev =  &pdev->dev;
-+	struct usbhs_omap_platform_data	*pdata = dev->platform_data;
-+	struct usbhs_hcd_omap		*omap;
-+	struct resource			*res;
-+	int				ret = 0;
-+	int				i;
- 
--	dev_dbg(dev, "stopping TI HSUSB Controller\n");
-+	if (!pdata) {
-+		dev_err(dev, "Missing platform data\n");
-+		ret = -ENOMEM;
-+		goto end_probe;
-+	}
- 
--	spin_lock_irqsave(&omap->lock, flags);
-+	omap = kzalloc(sizeof(*omap), GFP_KERNEL);
-+	if (!omap) {
-+		dev_err(dev, "Memory allocation failed\n");
-+		ret = -ENOMEM;
-+		goto end_probe;
-+	}
- 
--	if (omap->count == 0)
--		goto end_disble;
-+	spin_lock_init(&omap->lock);
- 
--	omap->count--;
-+	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
-+		omap->platdata.port_mode[i] = pdata->port_mode[i];
-+
-+	omap->platdata.ehci_data = pdata->ehci_data;
-+	omap->platdata.ohci_data = pdata->ohci_data;
- 
--	if (omap->count != 0)
--		goto end_disble;
-+	pm_runtime_enable(dev);
- 
--	/* Reset OMAP modules for insmod/rmmod to work */
--	usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG,
--			is_omap_usbhs_rev2(omap) ?
--			OMAP4_UHH_SYSCONFIG_SOFTRESET :
--			OMAP_UHH_SYSCONFIG_SOFTRESET);
- 
--	timeout = jiffies + msecs_to_jiffies(100);
--	while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
--				& (1 << 0))) {
--		cpu_relax();
-+	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
-+		if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
-+			is_ehci_hsic_mode(i)) {
-+			omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
-+			if (IS_ERR(omap->ehci_logic_fck)) {
-+				ret = PTR_ERR(omap->ehci_logic_fck);
-+				dev_warn(dev, "ehci_logic_fck failed:%d\n",
-+					 ret);
-+			}
-+			break;
-+		}
- 
--		if (time_after(jiffies, timeout))
--			dev_dbg(dev, "operation timed out\n");
-+	omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
-+	if (IS_ERR(omap->utmi_p1_fck)) {
-+		ret = PTR_ERR(omap->utmi_p1_fck);
-+		dev_err(dev, "utmi_p1_gfclk failed error:%d\n",	ret);
-+		goto err_end;
- 	}
- 
--	while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
--				& (1 << 1))) {
--		cpu_relax();
-+	omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
-+	if (IS_ERR(omap->xclk60mhsp1_ck)) {
-+		ret = PTR_ERR(omap->xclk60mhsp1_ck);
-+		dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
-+		goto err_utmi_p1_fck;
-+	}
- 
--		if (time_after(jiffies, timeout))
--			dev_dbg(dev, "operation timed out\n");
-+	omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
-+	if (IS_ERR(omap->utmi_p2_fck)) {
-+		ret = PTR_ERR(omap->utmi_p2_fck);
-+		dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
-+		goto err_xclk60mhsp1_ck;
- 	}
- 
--	while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
--				& (1 << 2))) {
--		cpu_relax();
-+	omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
-+	if (IS_ERR(omap->xclk60mhsp2_ck)) {
-+		ret = PTR_ERR(omap->xclk60mhsp2_ck);
-+		dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
-+		goto err_utmi_p2_fck;
-+	}
- 
--		if (time_after(jiffies, timeout))
--			dev_dbg(dev, "operation timed out\n");
-+	omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
-+	if (IS_ERR(omap->usbhost_p1_fck)) {
-+		ret = PTR_ERR(omap->usbhost_p1_fck);
-+		dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
-+		goto err_xclk60mhsp2_ck;
- 	}
- 
--	usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
-+	omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
-+	if (IS_ERR(omap->usbtll_p1_fck)) {
-+		ret = PTR_ERR(omap->usbtll_p1_fck);
-+		dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
-+		goto err_usbhost_p1_fck;
-+	}
- 
--	while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
--				& (1 << 0))) {
--		cpu_relax();
-+	omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
-+	if (IS_ERR(omap->usbhost_p2_fck)) {
-+		ret = PTR_ERR(omap->usbhost_p2_fck);
-+		dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
-+		goto err_usbtll_p1_fck;
-+	}
- 
--		if (time_after(jiffies, timeout))
--			dev_dbg(dev, "operation timed out\n");
-+	omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
-+	if (IS_ERR(omap->usbtll_p2_fck)) {
-+		ret = PTR_ERR(omap->usbtll_p2_fck);
-+		dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
-+		goto err_usbhost_p2_fck;
- 	}
- 
--	if (is_omap_usbhs_rev2(omap)) {
--		if (is_ehci_tll_mode(pdata->port_mode[0]))
--			clk_disable(omap->usbtll_p1_fck);
--		if (is_ehci_tll_mode(pdata->port_mode[1]))
--			clk_disable(omap->usbtll_p2_fck);
--		clk_disable(omap->utmi_p2_fck);
--		clk_disable(omap->utmi_p1_fck);
-+	omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
-+	if (IS_ERR(omap->init_60m_fclk)) {
-+		ret = PTR_ERR(omap->init_60m_fclk);
-+		dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
-+		goto err_usbtll_p2_fck;
- 	}
- 
--	clk_disable(omap->usbtll_ick);
--	clk_disable(omap->usbtll_fck);
--	clk_disable(omap->usbhost_fs_fck);
--	clk_disable(omap->usbhost_hs_fck);
--	clk_disable(omap->usbhost_ick);
-+	if (is_ehci_phy_mode(pdata->port_mode[0])) {
-+		/* for OMAP3 , the clk set paretn fails */
-+		ret = clk_set_parent(omap->utmi_p1_fck,
-+					omap->xclk60mhsp1_ck);
-+		if (ret != 0)
-+			dev_err(dev, "xclk60mhsp1_ck set parent"
-+				"failed error:%d\n", ret);
-+	} else if (is_ehci_tll_mode(pdata->port_mode[0])) {
-+		ret = clk_set_parent(omap->utmi_p1_fck,
-+					omap->init_60m_fclk);
-+		if (ret != 0)
-+			dev_err(dev, "init_60m_fclk set parent"
-+				"failed error:%d\n", ret);
-+	}
- 
--	/* The gpio_free migh sleep; so unlock the spinlock */
--	spin_unlock_irqrestore(&omap->lock, flags);
-+	if (is_ehci_phy_mode(pdata->port_mode[1])) {
-+		ret = clk_set_parent(omap->utmi_p2_fck,
-+					omap->xclk60mhsp2_ck);
-+		if (ret != 0)
-+			dev_err(dev, "xclk60mhsp2_ck set parent"
-+					"failed error:%d\n", ret);
-+	} else if (is_ehci_tll_mode(pdata->port_mode[1])) {
-+		ret = clk_set_parent(omap->utmi_p2_fck,
-+						omap->init_60m_fclk);
-+		if (ret != 0)
-+			dev_err(dev, "init_60m_fclk set parent"
-+				"failed error:%d\n", ret);
-+	}
- 
--	if (pdata->ehci_data->phy_reset) {
--		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
--			gpio_free(pdata->ehci_data->reset_gpio_port[0]);
-+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
-+	if (!res) {
-+		dev_err(dev, "UHH EHCI get resource failed\n");
-+		ret = -ENODEV;
-+		goto err_init_60m_fclk;
-+	}
- 
--		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
--			gpio_free(pdata->ehci_data->reset_gpio_port[1]);
-+	omap->uhh_base = ioremap(res->start, resource_size(res));
-+	if (!omap->uhh_base) {
-+		dev_err(dev, "UHH ioremap failed\n");
-+		ret = -ENOMEM;
-+		goto err_init_60m_fclk;
- 	}
--	return;
- 
--end_disble:
--	spin_unlock_irqrestore(&omap->lock, flags);
--}
-+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
-+	if (!res) {
-+		dev_err(dev, "UHH EHCI get resource failed\n");
-+		ret = -ENODEV;
-+		goto err_tll;
-+	}
- 
--int omap_usbhs_enable(struct device *dev)
--{
--	return  usbhs_enable(dev->parent);
-+	omap->tll_base = ioremap(res->start, resource_size(res));
-+	if (!omap->tll_base) {
-+		dev_err(dev, "TLL ioremap failed\n");
-+		ret = -ENOMEM;
-+		goto err_tll;
-+	}
-+
-+	platform_set_drvdata(pdev, omap);
-+
-+	ret = omap_usbhs_alloc_children(pdev);
-+	if (ret) {
-+		dev_err(dev, "omap_usbhs_alloc_children failed\n");
-+		goto err_alloc;
-+	}
-+
-+	omap_usbhs_init(dev);
-+
-+	goto end_probe;
-+
-+err_alloc:
-+	iounmap(omap->tll_base);
-+
-+err_tll:
-+	iounmap(omap->uhh_base);
-+
-+err_init_60m_fclk:
-+	clk_put(omap->init_60m_fclk);
-+
-+err_usbtll_p2_fck:
-+	clk_put(omap->usbtll_p2_fck);
-+
-+err_usbhost_p2_fck:
-+	clk_put(omap->usbhost_p2_fck);
-+
-+err_usbtll_p1_fck:
-+	clk_put(omap->usbtll_p1_fck);
-+
-+err_usbhost_p1_fck:
-+	clk_put(omap->usbhost_p1_fck);
-+
-+err_xclk60mhsp2_ck:
-+	clk_put(omap->xclk60mhsp2_ck);
-+
-+err_utmi_p2_fck:
-+	clk_put(omap->utmi_p2_fck);
-+
-+err_xclk60mhsp1_ck:
-+	clk_put(omap->xclk60mhsp1_ck);
-+
-+err_utmi_p1_fck:
-+	clk_put(omap->utmi_p1_fck);
-+
-+err_end:
-+	clk_put(omap->ehci_logic_fck);
-+	pm_runtime_disable(dev);
-+	kfree(omap);
-+
-+end_probe:
-+	return ret;
- }
--EXPORT_SYMBOL_GPL(omap_usbhs_enable);
- 
--void omap_usbhs_disable(struct device *dev)
-+/**
-+ * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
-+ * @pdev: USB Host Controller being removed
-+ *
-+ * Reverses the effect of usbhs_omap_probe().
-+ */
-+static int __devexit usbhs_omap_remove(struct platform_device *pdev)
- {
--	usbhs_disable(dev->parent);
-+	struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
-+
-+	omap_usbhs_deinit(&pdev->dev);
-+	iounmap(omap->tll_base);
-+	iounmap(omap->uhh_base);
-+	clk_put(omap->init_60m_fclk);
-+	clk_put(omap->usbtll_p2_fck);
-+	clk_put(omap->usbhost_p2_fck);
-+	clk_put(omap->usbtll_p1_fck);
-+	clk_put(omap->usbhost_p1_fck);
-+	clk_put(omap->xclk60mhsp2_ck);
-+	clk_put(omap->utmi_p2_fck);
-+	clk_put(omap->xclk60mhsp1_ck);
-+	clk_put(omap->utmi_p1_fck);
-+	clk_put(omap->ehci_logic_fck);
-+	pm_runtime_disable(&pdev->dev);
-+	kfree(omap);
-+
-+	return 0;
- }
--EXPORT_SYMBOL_GPL(omap_usbhs_disable);
-+
-+static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
-+	.runtime_suspend	= usbhs_runtime_suspend,
-+	.runtime_resume		= usbhs_runtime_resume,
-+};
- 
- static struct platform_driver usbhs_omap_driver = {
- 	.driver = {
- 		.name		= (char *)usbhs_driver_name,
- 		.owner		= THIS_MODULE,
-+		.pm		= &usbhsomap_dev_pm_ops,
- 	},
- 	.remove		= __exit_p(usbhs_omap_remove),
- };
-diff --git a/drivers/mfd/tps65217.c b/drivers/mfd/tps65217.c
-new file mode 100644
-index 0000000..f7d854e
---- /dev/null
-+++ b/drivers/mfd/tps65217.c
-@@ -0,0 +1,242 @@
-+/*
-+ * tps65217.c
-+ *
-+ * TPS65217 chip family multi-function driver
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/device.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/init.h>
-+#include <linux/i2c.h>
-+#include <linux/slab.h>
-+#include <linux/regmap.h>
-+#include <linux/err.h>
-+
-+#include <linux/mfd/core.h>
-+#include <linux/mfd/tps65217.h>
-+
-+/**
-+ * tps65217_reg_read: Read a single tps65217 register.
-+ *
-+ * @tps: Device to read from.
-+ * @reg: Register to read.
-+ * @val: Contians the value
-+ */
-+int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
-+			unsigned int *val)
-+{
-+	return regmap_read(tps->regmap, reg, val);
-+}
-+EXPORT_SYMBOL_GPL(tps65217_reg_read);
-+
-+/**
-+ * tps65217_reg_write: Write a single tps65217 register.
-+ *
-+ * @tps65217: Device to write to.
-+ * @reg: Register to write to.
-+ * @val: Value to write.
-+ * @level: Password protected level
-+ */
-+int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
-+			unsigned int val, unsigned int level)
-+{
-+	int ret;
-+	unsigned int xor_reg_val;
-+
-+	switch (level) {
-+	case TPS65217_PROTECT_NONE:
-+		return regmap_write(tps->regmap, reg, val);
-+	case TPS65217_PROTECT_L1:
-+		xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
-+		ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
-+							xor_reg_val);
-+		if (ret < 0)
-+			return ret;
-+
-+		return regmap_write(tps->regmap, reg, val);
-+	case TPS65217_PROTECT_L2:
-+		xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
-+		ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
-+							xor_reg_val);
-+		if (ret < 0)
-+			return ret;
-+		ret = regmap_write(tps->regmap, reg, val);
-+		if (ret < 0)
-+			return ret;
-+		ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
-+							xor_reg_val);
-+		if (ret < 0)
-+			return ret;
-+		return regmap_write(tps->regmap, reg, val);
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+EXPORT_SYMBOL_GPL(tps65217_reg_write);
-+
-+/**
-+ * tps65217_update_bits: Modify bits w.r.t mask, val and level.
-+ *
-+ * @tps65217: Device to write to.
-+ * @reg: Register to read-write to.
-+ * @mask: Mask.
-+ * @val: Value to write.
-+ * @level: Password protected level
-+ */
-+int tps65217_update_bits(struct tps65217 *tps, unsigned int reg,
-+		unsigned int mask, unsigned int val, unsigned int level)
-+{
-+	int ret;
-+	unsigned int data;
-+
-+	ret = tps65217_reg_read(tps, reg, &data);
-+	if (ret) {
-+		dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
-+		return ret;
-+	}
-+
-+	data &= ~mask;
-+	data |= val & mask;
-+
-+	ret = tps65217_reg_write(tps, reg, data, level);
-+	if (ret)
-+		dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
-+
-+	return ret;
-+}
-+
-+int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
-+		unsigned int mask, unsigned int val, unsigned int level)
-+{
-+	return tps65217_update_bits(tps, reg, mask, val, level);
-+}
-+EXPORT_SYMBOL_GPL(tps65217_set_bits);
-+
-+int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
-+		unsigned int mask, unsigned int level)
-+{
-+	return tps65217_update_bits(tps, reg, mask, 0, level);
-+}
-+EXPORT_SYMBOL_GPL(tps65217_clear_bits);
-+
-+static struct regmap_config tps65217_regmap_config = {
-+	.reg_bits = 8,
-+	.val_bits = 8,
-+};
-+
-+static int __devinit tps65217_probe(struct i2c_client *client,
-+				const struct i2c_device_id *ids)
-+{
-+	struct tps65217 *tps;
-+	struct tps65217_board *pdata = client->dev.platform_data;
-+	int i, ret;
-+	unsigned int version;
-+
-+	tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
-+	if (!tps)
-+		return -ENOMEM;
-+
-+	tps->pdata = pdata;
-+	tps->regmap = regmap_init_i2c(client, &tps65217_regmap_config);
-+	if (IS_ERR(tps->regmap)) {
-+		ret = PTR_ERR(tps->regmap);
-+		dev_err(tps->dev, "Failed to allocate register map: %d\n",
-+			ret);
-+		return ret;
-+	}
-+
-+	i2c_set_clientdata(client, tps);
-+	tps->dev = &client->dev;
-+
-+	ret = tps65217_reg_read(tps, TPS65217_REG_CHIPID, &version);
-+	if (ret < 0) {
-+		dev_err(tps->dev, "Failed to read revision"
-+					" register: %d\n", ret);
-+		goto err_regmap;
-+	}
-+
-+	dev_info(tps->dev, "TPS65217 ID %#x version 1.%d\n",
-+			(version & TPS65217_CHIPID_CHIP_MASK) >> 4,
-+			version & TPS65217_CHIPID_REV_MASK);
-+
-+	for (i = 0; i < TPS65217_NUM_REGULATOR; i++) {
-+		struct platform_device *pdev;
-+
-+		pdev = platform_device_alloc("tps65217-pmic", i);
-+		if (!pdev) {
-+			dev_err(tps->dev, "Cannot create regulator %d\n", i);
-+			continue;
-+		}
-+
-+		pdev->dev.parent = tps->dev;
-+		platform_device_add_data(pdev, &pdata->tps65217_init_data[i],
-+					sizeof(pdata->tps65217_init_data[i]));
-+		tps->regulator_pdev[i] = pdev;
-+
-+		platform_device_add(pdev);
-+	}
-+
-+	return 0;
-+
-+err_regmap:
-+	regmap_exit(tps->regmap);
-+
-+	return ret;
-+}
-+
-+static int __devexit tps65217_remove(struct i2c_client *client)
-+{
-+	struct tps65217 *tps = i2c_get_clientdata(client);
-+	int i;
-+
-+	for (i = 0; i < TPS65217_NUM_REGULATOR; i++)
-+		platform_device_unregister(tps->regulator_pdev[i]);
-+
-+	regmap_exit(tps->regmap);
-+
-+	return 0;
-+}
-+
-+static const struct i2c_device_id tps65217_id_table[] = {
-+	{"tps65217", 0xF0},
-+	{/* end of list */}
-+};
-+MODULE_DEVICE_TABLE(i2c, tps65217_id_table);
-+
-+static struct i2c_driver tps65217_driver = {
-+	.driver		= {
-+		.name	= "tps65217",
-+	},
-+	.id_table	= tps65217_id_table,
-+	.probe		= tps65217_probe,
-+	.remove		= __devexit_p(tps65217_remove),
-+};
-+
-+static int __init tps65217_init(void)
-+{
-+	return i2c_add_driver(&tps65217_driver);
-+}
-+subsys_initcall(tps65217_init);
-+
-+static void __exit tps65217_exit(void)
-+{
-+	i2c_del_driver(&tps65217_driver);
-+}
-+module_exit(tps65217_exit);
-+
-+MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
-+MODULE_DESCRIPTION("TPS65217 chip family multi-function driver");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/mfd/tps65910.c b/drivers/mfd/tps65910.c
-index c1da84b..2d4bc21 100644
---- a/drivers/mfd/tps65910.c
-+++ b/drivers/mfd/tps65910.c
-@@ -18,7 +18,6 @@
- #include <linux/init.h>
- #include <linux/slab.h>
- #include <linux/i2c.h>
--#include <linux/gpio.h>
- #include <linux/mfd/core.h>
- #include <linux/mfd/tps65910.h>
- 
-@@ -138,6 +137,7 @@ static int tps65910_i2c_probe(struct i2c_client *i2c,
- 	struct tps65910_board *pmic_plat_data;
- 	struct tps65910_platform_data *init_data;
- 	int ret = 0;
-+	unsigned char buff;
- 
- 	pmic_plat_data = dev_get_platdata(&i2c->dev);
- 	if (!pmic_plat_data)
-@@ -161,26 +161,38 @@ static int tps65910_i2c_probe(struct i2c_client *i2c,
- 	tps65910->write = tps65910_i2c_write;
- 	mutex_init(&tps65910->io_mutex);
- 
--	ret = mfd_add_devices(tps65910->dev, -1,
--			      tps65910s, ARRAY_SIZE(tps65910s),
--			      NULL, 0);
-+	/* Check that the device is actually there */
-+	ret = tps65910_i2c_read(tps65910, 0x0, 1, &buff);
-+	if (ret < 0) {
-+		dev_err(tps65910->dev, "could not be detected\n");
-+		ret = -ENODEV;
-+		goto err;
-+	}
-+
-+	dev_info(tps65910->dev, "JTAGREVNUM 0x%x\n", buff);
-+
-+	if (buff & ~JTAGVERNUM_VERNUM_MASK) {
-+		dev_err(tps65910->dev, "unknown version\n");
-+		ret = -ENODEV;
-+		goto err;
-+	}
-+
-+	ret = mfd_add_devices(tps65910->dev, -1, tps65910s,
-+			ARRAY_SIZE(tps65910s), NULL, 0);
- 	if (ret < 0)
- 		goto err;
- 
- 	init_data->irq = pmic_plat_data->irq;
--	init_data->irq_base = pmic_plat_data->irq;
-+	init_data->irq_base = pmic_plat_data->irq_base;
- 
- 	tps65910_gpio_init(tps65910, pmic_plat_data->gpio_base);
- 
--	ret = tps65910_irq_init(tps65910, init_data->irq, init_data);
--	if (ret < 0)
--		goto err;
-+	tps65910_irq_init(tps65910, init_data->irq, init_data);
- 
- 	kfree(init_data);
- 	return ret;
- 
- err:
--	mfd_remove_devices(tps65910->dev);
- 	kfree(tps65910);
- 	kfree(init_data);
- 	return ret;
-diff --git a/drivers/misc/lis3lv02d/lis3lv02d.c b/drivers/misc/lis3lv02d/lis3lv02d.c
-index 29d12a7..2381220 100644
---- a/drivers/misc/lis3lv02d/lis3lv02d.c
-+++ b/drivers/misc/lis3lv02d/lis3lv02d.c
-@@ -80,6 +80,17 @@
- #define LIS3_SENSITIVITY_12B		((LIS3_ACCURACY * 1000) / 1024)
- #define LIS3_SENSITIVITY_8B		(18 * LIS3_ACCURACY)
- 
-+/* Sensitivity values for -2G, -4G, -8G and +2G, +4G, +8G scale */
-+#define LIS3DLH_SENSITIVITY_2G		(LIS3_ACCURACY * 1)
-+#define LIS3DLH_SENSITIVITY_4G		(LIS3_ACCURACY * 2)
-+#define LIS3DLH_SENSITIVITY_8G		((LIS3_ACCURACY * 39)/10)
-+
-+#define SHIFT_ADJ_2G			4
-+#define SHIFT_ADJ_4G			3
-+#define SHIFT_ADJ_8G			2
-+
-+#define FS_MASK				(0x3 << 4)
-+
- #define LIS3_DEFAULT_FUZZ_12B		3
- #define LIS3_DEFAULT_FLAT_12B		3
- #define LIS3_DEFAULT_FUZZ_8B		1
-@@ -148,6 +159,12 @@ static inline int lis3lv02d_get_axis(s8 axis, int hw_values[3])
- 		return -hw_values[-axis - 1];
- }
- 
-+static int lis3lv02d_decode(u8 pl, u8 ph, int adj)
-+{
-+	s16 v = pl | ph << 8;
-+	return (int) v >> adj;
-+}
-+
- /**
-  * lis3lv02d_get_xyz - Get X, Y and Z axis values from the accelerometer
-  * @lis3: pointer to the device struct
-@@ -176,9 +193,24 @@ static void lis3lv02d_get_xyz(struct lis3lv02d *lis3, int *x, int *y, int *z)
- 				position[i] = (s8)data[i * 2];
- 		}
- 	} else {
--		position[0] = lis3->read_data(lis3, OUTX);
--		position[1] = lis3->read_data(lis3, OUTY);
--		position[2] = lis3->read_data(lis3, OUTZ);
-+		if (lis3_dev.whoami == WAI_3DLH) {
-+			position[0] =
-+				lis3lv02d_decode(lis3->read_data(lis3, OUTX_L),
-+				lis3->read_data(lis3, OUTX_H),
-+				lis3_dev.shift_adj);
-+			position[1] =
-+				lis3lv02d_decode(lis3->read_data(lis3, OUTY_L),
-+				lis3->read_data(lis3, OUTY_H),
-+				lis3_dev.shift_adj);
-+			position[2] =
-+				lis3lv02d_decode(lis3->read_data(lis3, OUTZ_L),
-+				lis3->read_data(lis3, OUTZ_H),
-+				lis3_dev.shift_adj);
-+		} else {
-+			position[0] = lis3->read_data(lis3, OUTX);
-+			position[1] = lis3->read_data(lis3, OUTY);
-+			position[2] = lis3->read_data(lis3, OUTZ);
-+		}
- 	}
- 
- 	for (i = 0; i < 3; i++)
-@@ -193,6 +225,7 @@ static void lis3lv02d_get_xyz(struct lis3lv02d *lis3, int *x, int *y, int *z)
- static int lis3_12_rates[4] = {40, 160, 640, 2560};
- static int lis3_8_rates[2] = {100, 400};
- static int lis3_3dc_rates[16] = {0, 1, 10, 25, 50, 100, 200, 400, 1600, 5000};
-+static int lis3_3dlh_rates[4] = {50, 100, 400, 1000};
- 
- /* ODR is Output Data Rate */
- static int lis3lv02d_get_odr(struct lis3lv02d *lis3)
-@@ -265,7 +298,7 @@ static int lis3lv02d_selftest(struct lis3lv02d *lis3, s16 results[3])
- 				(LIS3_IRQ1_DATA_READY | LIS3_IRQ2_DATA_READY));
- 	}
- 
--	if (lis3->whoami == WAI_3DC) {
-+	if ((lis3_dev.whoami == WAI_3DC) || (lis3_dev.whoami == WAI_3DLH)) {
- 		ctlreg = CTRL_REG4;
- 		selftest = CTRL4_ST0;
- 	} else {
-@@ -396,6 +429,8 @@ int lis3lv02d_poweron(struct lis3lv02d *lis3)
- 		lis3->read(lis3, CTRL_REG2, &reg);
- 		if (lis3->whoami ==  WAI_12B)
- 			reg |= CTRL2_BDU | CTRL2_BOOT;
-+		else if (lis3->whoami ==  WAI_3DLH)
-+			reg |= CTRL2_BOOT_3DLH;
- 		else
- 			reg |= CTRL2_BOOT_8B;
- 		lis3->write(lis3, CTRL_REG2, reg);
-@@ -724,6 +759,36 @@ void lis3lv02d_joystick_disable(struct lis3lv02d *lis3)
- }
- EXPORT_SYMBOL_GPL(lis3lv02d_joystick_disable);
- 
-+static void lis3lv02d_update_g_range(struct lis3lv02d *lis3)
-+{
-+	u8 reg;
-+	u8 val;
-+	u8 shift;
-+
-+	switch (lis3->g_range) {
-+	case 8:
-+		val = FS_8G_REGVAL;
-+		shift = SHIFT_ADJ_8G;
-+		lis3->scale = LIS3DLH_SENSITIVITY_8G;
-+		break;
-+	case 4:
-+		val = FS_4G_REGVAL;
-+		shift = SHIFT_ADJ_4G;
-+		lis3->scale = LIS3DLH_SENSITIVITY_4G;
-+		break;
-+	case 2:
-+	default:
-+		val = FS_2G_REGVAL;
-+		shift = SHIFT_ADJ_2G;
-+		lis3->scale = LIS3DLH_SENSITIVITY_2G;
-+		break;
-+	}
-+
-+	lis3->shift_adj = shift;
-+	lis3->read(lis3, CTRL_REG4, &reg);
-+	lis3->write(lis3, CTRL_REG4, ((reg & ~FS_MASK) | val));
-+}
-+
- /* Sysfs stuff */
- static void lis3lv02d_sysfs_poweron(struct lis3lv02d *lis3)
- {
-@@ -792,6 +857,13 @@ static ssize_t lis3lv02d_rate_show(struct device *dev,
- 	return sprintf(buf, "%d\n", lis3lv02d_get_odr(lis3));
- }
- 
-+static ssize_t lis3lv02d_range_show(struct device *dev,
-+			       struct device_attribute *attr, char *buf)
-+{
-+	lis3lv02d_sysfs_poweron(&lis3_dev);
-+	return sprintf(buf, "%d\n", lis3_dev.g_range);
-+}
-+
- static ssize_t lis3lv02d_rate_set(struct device *dev,
- 				struct device_attribute *attr, const char *buf,
- 				size_t count)
-@@ -809,15 +881,33 @@ static ssize_t lis3lv02d_rate_set(struct device *dev,
- 	return count;
- }
- 
-+static ssize_t lis3lv02d_range_set(struct device *dev,
-+				struct device_attribute *attr, const char *buf,
-+				size_t count)
-+{
-+	unsigned long range;
-+
-+	if (strict_strtoul(buf, 0, &range))
-+		return -EINVAL;
-+
-+	lis3_dev.g_range = range;
-+	lis3lv02d_update_g_range(&lis3_dev);
-+
-+	return count;
-+}
-+
- static DEVICE_ATTR(selftest, S_IRUSR, lis3lv02d_selftest_show, NULL);
- static DEVICE_ATTR(position, S_IRUGO, lis3lv02d_position_show, NULL);
- static DEVICE_ATTR(rate, S_IRUGO | S_IWUSR, lis3lv02d_rate_show,
- 					    lis3lv02d_rate_set);
-+static DEVICE_ATTR(range, S_IRUGO | S_IWUSR, lis3lv02d_range_show,
-+					    lis3lv02d_range_set);
- 
- static struct attribute *lis3lv02d_attributes[] = {
- 	&dev_attr_selftest.attr,
- 	&dev_attr_position.attr,
- 	&dev_attr_rate.attr,
-+	&dev_attr_range.attr,
- 	NULL
- };
- 
-@@ -954,6 +1044,19 @@ int lis3lv02d_init_device(struct lis3lv02d *lis3)
- 		lis3->odr_mask = CTRL1_ODR0|CTRL1_ODR1|CTRL1_ODR2|CTRL1_ODR3;
- 		lis3->scale = LIS3_SENSITIVITY_8B;
- 		break;
-+	case WAI_3DLH:
-+		pr_info("8 bits 3DLH sensor found\n");
-+		lis3->read_data = lis3lv02d_read_8;
-+		lis3->mdps_max_val = 128;
-+		lis3->pwron_delay = LIS3_PWRON_DELAY_WAI_8B;
-+		lis3->odrs = lis3_3dlh_rates;
-+		lis3->odr_mask = CTRL1_DR0 | CTRL1_DR1;
-+		if (lis3->pdata) {
-+			lis3->g_range = lis3->pdata->g_range;
-+			lis3lv02d_update_g_range(lis3);
-+		} else
-+			lis3->scale = LIS3DLH_SENSITIVITY_2G;
-+		break;
- 	default:
- 		pr_err("unknown sensor type 0x%X\n", lis3->whoami);
- 		return -EINVAL;
-diff --git a/drivers/misc/lis3lv02d/lis3lv02d.h b/drivers/misc/lis3lv02d/lis3lv02d.h
-index 2b1482a..0e6fe06 100644
---- a/drivers/misc/lis3lv02d/lis3lv02d.h
-+++ b/drivers/misc/lis3lv02d/lis3lv02d.h
-@@ -95,13 +95,29 @@ enum lis3lv02d_reg {
- 	DD_THSE_H	= 0x3F,
- };
- 
-+enum lis331dlh_reg {
-+	CTRL_REG5	= 0x24,
-+	HP_FILTER_RESET_3DLH	= 0x25,
-+	REFERENCE	= 0x26,
-+};
-+
- enum lis3_who_am_i {
-+	WAI_3DLH	= 0x32,	/* 8 bits: LIS331DLH */
- 	WAI_3DC		= 0x33,	/* 8 bits: LIS3DC, HP3DC */
- 	WAI_12B		= 0x3A, /* 12 bits: LIS3LV02D[LQ]... */
- 	WAI_8B		= 0x3B, /* 8 bits: LIS[23]02D[LQ]... */
- 	WAI_6B		= 0x52, /* 6 bits: LIS331DLF - not supported */
- };
- 
-+enum lis3_type {
-+	LIS3DC,
-+	HP3DC,
-+	LIS3LV02D,
-+	LIS2302D,
-+	LIS331DLF,
-+	LIS331DLH,
-+};
-+
- enum lis3lv02d_ctrl1_12b {
- 	CTRL1_Xen	= 0x01,
- 	CTRL1_Yen	= 0x02,
-@@ -129,6 +145,32 @@ enum lis3lv02d_ctrl1_3dc {
- 	CTRL1_ODR3	= 0x80,
- };
- 
-+enum lis331dlh_ctrl1 {
-+	CTRL1_DR0	= 0x08,
-+	CTRL1_DR1	= 0x10,
-+	CTRL1_PM0	= 0x20,
-+	CTRL1_PM1	= 0x40,
-+	CTRL1_PM2	= 0x80,
-+};
-+
-+enum lis331dlh_ctrl2 {
-+	CTRL2_HPEN1	= 0x04,
-+	CTRL2_HPEN2	= 0x08,
-+	CTRL2_FDS_3DLH	= 0x10,
-+	CTRL2_BOOT_3DLH	= 0x80,
-+};
-+
-+enum lis331dlh_ctrl4 {
-+	CTRL4_STSIGN	= 0x08,
-+	CTRL4_BLE	= 0x40,
-+	CTRL4_BDU	= 0x80,
-+};
-+
-+enum lis331dlh_ctrl5 {
-+	CTRL5_TURNON0	= 0x01,
-+	CTRL5_TURNON1	= 0x20,
-+};
-+
- enum lis3lv02d_ctrl2 {
- 	CTRL2_DAS	= 0x01,
- 	CTRL2_SIM	= 0x02,
-@@ -148,6 +190,13 @@ enum lis3lv02d_ctrl4_3dc {
- 	CTRL4_FS1	= 0x20,
- };
- 
-+/* Measurement Range */
-+enum lis3lv02d_fs {
-+	FS_2G_REGVAL = 0x00,
-+	FS_4G_REGVAL = 0x10,
-+	FS_8G_REGVAL = 0x30,
-+};
-+
- enum lis302d_ctrl2 {
- 	HP_FF_WU2	= 0x08,
- 	HP_FF_WU1	= 0x04,
-@@ -185,6 +234,10 @@ enum lis3lv02d_ff_wu_cfg {
- 	FF_WU_CFG_AOI	= 0x80,
- };
- 
-+enum lis331dlh_ff_wu_cfg {
-+	FF_WU_CFG_6D	= 0x40,
-+};
-+
- enum lis3lv02d_ff_wu_src {
- 	FF_WU_SRC_XL	= 0x01,
- 	FF_WU_SRC_XH	= 0x02,
-@@ -206,6 +259,10 @@ enum lis3lv02d_dd_cfg {
- 	DD_CFG_IEND	= 0x80,
- };
- 
-+enum lis331dlh_dd_cfg {
-+	DD_CFG_6D	= 0x40,
-+};
-+
- enum lis3lv02d_dd_src {
- 	DD_SRC_XL	= 0x01,
- 	DD_SRC_XH	= 0x02,
-@@ -282,6 +339,8 @@ struct lis3lv02d {
- 
- 	struct lis3lv02d_platform_data *pdata;	/* for passing board config */
- 	struct mutex		mutex;     /* Serialize poll and selftest */
-+	u8			g_range; /* Hold the g range */
-+	u8			shift_adj;
- };
- 
- int lis3lv02d_init_device(struct lis3lv02d *lis3);
-diff --git a/drivers/misc/lis3lv02d/lis3lv02d_i2c.c b/drivers/misc/lis3lv02d/lis3lv02d_i2c.c
-index c02fea0..32b322f 100644
---- a/drivers/misc/lis3lv02d/lis3lv02d_i2c.c
-+++ b/drivers/misc/lis3lv02d/lis3lv02d_i2c.c
-@@ -90,7 +90,10 @@ static int lis3_i2c_init(struct lis3lv02d *lis3)
- 	if (ret < 0)
- 		return ret;
- 
--	reg |= CTRL1_PD0 | CTRL1_Xen | CTRL1_Yen | CTRL1_Zen;
-+	if (lis3->whoami == WAI_3DLH)
-+		reg |= CTRL1_PM0 | CTRL1_Xen | CTRL1_Yen | CTRL1_Zen;
-+	else
-+		reg |= CTRL1_PD0 | CTRL1_Xen | CTRL1_Yen | CTRL1_Zen;
- 	return lis3->write(lis3, CTRL_REG1, reg);
- }
- 
-@@ -232,6 +235,7 @@ static int lis3_i2c_runtime_resume(struct device *dev)
- 
- static const struct i2c_device_id lis3lv02d_id[] = {
- 	{"lis3lv02d", 0 },
-+	{"lis331dlh", LIS331DLH},
- 	{}
- };
- 
-diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
-index e15e47d..60e8951 100644
---- a/drivers/mmc/card/block.c
-+++ b/drivers/mmc/card/block.c
-@@ -1685,7 +1685,7 @@ static void mmc_blk_remove(struct mmc_card *card)
- }
- 
- #ifdef CONFIG_PM
--static int mmc_blk_suspend(struct mmc_card *card, pm_message_t state)
-+static int mmc_blk_suspend(struct mmc_card *card)
- {
- 	struct mmc_blk_data *part_md;
- 	struct mmc_blk_data *md = mmc_get_drvdata(card);
-diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
-index 6be4924..20c1d4b 100644
---- a/drivers/mmc/core/bus.c
-+++ b/drivers/mmc/core/bus.c
-@@ -122,14 +122,14 @@ static int mmc_bus_remove(struct device *dev)
- 	return 0;
- }
- 
--static int mmc_bus_suspend(struct device *dev, pm_message_t state)
-+static int mmc_bus_suspend(struct device *dev)
- {
- 	struct mmc_driver *drv = to_mmc_driver(dev->driver);
- 	struct mmc_card *card = mmc_dev_to_card(dev);
- 	int ret = 0;
- 
- 	if (dev->driver && drv->suspend)
--		ret = drv->suspend(card, state);
-+		ret = drv->suspend(card);
- 	return ret;
- }
- 
-@@ -165,20 +165,20 @@ static int mmc_runtime_idle(struct device *dev)
- 	return pm_runtime_suspend(dev);
- }
- 
-+#else /* !CONFIG_PM_RUNTIME */
-+#define mmc_runtime_suspend	NULL
-+#define mmc_runtime_resume	NULL
-+#define mmc_runtime_idle	NULL
-+#endif /* !CONFIG_PM_RUNTIME */
-+
- static const struct dev_pm_ops mmc_bus_pm_ops = {
- 	.runtime_suspend	= mmc_runtime_suspend,
- 	.runtime_resume		= mmc_runtime_resume,
- 	.runtime_idle		= mmc_runtime_idle,
-+	.suspend		= mmc_bus_suspend,
-+	.resume			= mmc_bus_resume,
- };
- 
--#define MMC_PM_OPS_PTR	(&mmc_bus_pm_ops)
--
--#else /* !CONFIG_PM_RUNTIME */
--
--#define MMC_PM_OPS_PTR	NULL
--
--#endif /* !CONFIG_PM_RUNTIME */
--
- static struct bus_type mmc_bus_type = {
- 	.name		= "mmc",
- 	.dev_attrs	= mmc_dev_attrs,
-@@ -186,9 +186,7 @@ static struct bus_type mmc_bus_type = {
- 	.uevent		= mmc_bus_uevent,
- 	.probe		= mmc_bus_probe,
- 	.remove		= mmc_bus_remove,
--	.suspend	= mmc_bus_suspend,
--	.resume		= mmc_bus_resume,
--	.pm		= MMC_PM_OPS_PTR,
-+	.pm		= &mmc_bus_pm_ops,
- };
- 
- int mmc_register_bus(void)
-diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
-index d5fe43d..ace26f7 100644
---- a/drivers/mmc/host/omap_hsmmc.c
-+++ b/drivers/mmc/host/omap_hsmmc.c
-@@ -59,6 +59,7 @@
- #define OMAP_HSMMC_IE		0x0134
- #define OMAP_HSMMC_ISE		0x0138
- #define OMAP_HSMMC_CAPA		0x0140
-+#define OMAP_HSMMC_PSTATE	0x0124
- 
- #define VS18			(1 << 26)
- #define VS30			(1 << 25)
-@@ -78,7 +79,7 @@
- #define CLKD_SHIFT		6
- #define DTO_MASK		0x000F0000
- #define DTO_SHIFT		16
--#define INT_EN_MASK		0x307F0033
-+#define INT_EN_MASK		0x307F00f3
- #define BWR_ENABLE		(1 << 4)
- #define BRR_ENABLE		(1 << 5)
- #define DTO_ENABLE		(1 << 20)
-@@ -89,6 +90,10 @@
- #define MSBS			(1 << 5)
- #define BCE			(1 << 1)
- #define FOUR_BIT		(1 << 1)
-+#define DVAL_MASK		(3 << 9)
-+#define DVAL_MAX		(3 << 9)	/* 8.4 ms debounce period */
-+#define WPP_MASK		(1 << 8)
-+#define WPP_ACT_LOW		(1 << 8)	/* WPP is Active Low */
- #define DW8			(1 << 5)
- #define CC			0x1
- #define TC			0x02
-@@ -106,6 +111,14 @@
- #define SRD			(1 << 26)
- #define SOFTRESET		(1 << 1)
- #define RESETDONE		(1 << 0)
-+#define CINS			(1 << 6)
-+#define PSTATE_CINS_MASK	BIT(16)
-+#define PSTATE_CINS_SHIFT	16
-+#define PSTATE_WP_MASK		BIT(19)
-+#define PSTATE_WP_SHIFT		19
-+#define IE_CINS			0x00000040
-+#define IE_CINS_SHIFT		6
-+#define PSTATE_CINS     (1 << 16)
- 
- /*
-  * FIXME: Most likely all the data using these _DEVID defines should come
-@@ -120,7 +133,6 @@
- 
- #define MMC_AUTOSUSPEND_DELAY	100
- #define MMC_TIMEOUT_MS		20
--#define OMAP_MMC_MASTER_CLOCK	96000000
- #define OMAP_MMC_MIN_CLOCK	400000
- #define OMAP_MMC_MAX_CLOCK	52000000
- #define DRIVER_NAME		"omap_hsmmc"
-@@ -193,6 +205,8 @@ struct omap_hsmmc_host {
- 	struct	omap_mmc_platform_data	*pdata;
- };
- 
-+static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id);
-+
- static int omap_hsmmc_card_detect(struct device *dev, int slot)
- {
- 	struct omap_mmc_platform_data *mmc = dev->platform_data;
-@@ -224,6 +238,7 @@ static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
- 	struct omap_mmc_platform_data *mmc = dev->platform_data;
- 
- 	disable_irq(mmc->slots[0].card_detect_irq);
-+
- 	return 0;
- }
- 
-@@ -232,6 +247,7 @@ static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
- 	struct omap_mmc_platform_data *mmc = dev->platform_data;
- 
- 	enable_irq(mmc->slots[0].card_detect_irq);
-+
- 	return 0;
- }
- 
-@@ -592,18 +608,20 @@ static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
- 
- static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
- {
-+
- 	OMAP_HSMMC_WRITE(host->base, ISE, 0);
- 	OMAP_HSMMC_WRITE(host->base, IE, 0);
- 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
-+
- }
- 
- /* Calculate divisor for the given clock frequency */
--static u16 calc_divisor(struct mmc_ios *ios)
-+static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
- {
- 	u16 dsor = 0;
- 
- 	if (ios->clock) {
--		dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
-+		dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
- 		if (dsor > 250)
- 			dsor = 250;
- 	}
-@@ -623,7 +641,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
- 
- 	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
- 	regval = regval & ~(CLKD_MASK | DTO_MASK);
--	regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
-+	regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
- 	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
- 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
- 		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
-@@ -1088,7 +1106,7 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
- 			__func__);
- }
- 
--static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
-+static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status, int irq)
- {
- 	struct mmc_data *data;
- 	int end_cmd = 0, end_trans = 0;
-@@ -1170,7 +1188,7 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
- 
- 	status = OMAP_HSMMC_READ(host->base, STAT);
- 	do {
--		omap_hsmmc_do_irq(host, status);
-+		omap_hsmmc_do_irq(host, status, irq);
- 		/* Flush posted write */
- 		status = OMAP_HSMMC_READ(host->base, STAT);
- 	} while (status & INT_EN_MASK);
-@@ -1338,23 +1356,30 @@ static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
- 				       struct scatterlist *sgl)
- {
- 	int blksz, nblk, dma_ch;
-+	int bindex = 0, cindex = 0;
-+	struct omap_mmc_platform_data *pdata = host->pdata;
- 
- 	dma_ch = host->dma_ch;
-+	blksz = host->data->blksz;
-+	nblk = sg_dma_len(sgl) / blksz;
-+
-+	if (pdata->version == MMC_CTRL_VERSION_2) {
-+		bindex = 4;
-+		cindex = blksz;
-+	}
-+
- 	if (data->flags & MMC_DATA_WRITE) {
- 		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
- 			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
- 		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
--			sg_dma_address(sgl), 0, 0);
-+			sg_dma_address(sgl), bindex, cindex);
- 	} else {
- 		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
- 			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
- 		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
--			sg_dma_address(sgl), 0, 0);
-+			sg_dma_address(sgl), bindex, cindex);
- 	}
- 
--	blksz = host->data->blksz;
--	nblk = sg_dma_len(sgl) / blksz;
--
- 	omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
- 			blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
- 			omap_hsmmc_get_dma_sync_dev(host, data),
-@@ -1370,12 +1395,19 @@ static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
- {
- 	struct omap_hsmmc_host *host = cb_data;
- 	struct mmc_data *data;
-+	struct omap_mmc_platform_data *pdata = host->pdata;
- 	int dma_ch, req_in_progress;
- 
--	if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
--		dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
--			ch_status);
--		return;
-+
-+	if (pdata->version == MMC_CTRL_VERSION_2) {
-+		if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
-+			dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
-+	} else {
-+		if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
-+			dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
-+				ch_status);
-+			return;
-+		}
- 	}
- 
- 	spin_lock(&host->irq_lock);
-@@ -1498,11 +1530,8 @@ static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
- 	return 0;
- }
- 
--static void set_data_timeout(struct omap_hsmmc_host *host,
--			     unsigned int timeout_ns,
--			     unsigned int timeout_clks)
-+static void set_data_timeout(struct omap_hsmmc_host *host)
- {
--	unsigned int timeout, cycle_ns;
- 	uint32_t reg, clkd, dto = 0;
- 
- 	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
-@@ -1510,25 +1539,11 @@ static void set_data_timeout(struct omap_hsmmc_host *host,
- 	if (clkd == 0)
- 		clkd = 1;
- 
--	cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
--	timeout = timeout_ns / cycle_ns;
--	timeout += timeout_clks;
--	if (timeout) {
--		while ((timeout & 0x80000000) == 0) {
--			dto += 1;
--			timeout <<= 1;
--		}
--		dto = 31 - dto;
--		timeout <<= 1;
--		if (timeout && dto)
--			dto += 1;
--		if (dto >= 13)
--			dto -= 13;
--		else
--			dto = 0;
--		if (dto > 14)
--			dto = 14;
--	}
-+	/* Use the maximum timeout value allowed in the standard of 14 or 0xE */
-+	dto = 14;
-+
-+	/* Set dto to max value of 14 to avoid SD Card timeouts */
-+	dto = 14;
- 
- 	reg &= ~DTO_MASK;
- 	reg |= dto << DTO_SHIFT;
-@@ -1551,13 +1566,13 @@ omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
- 		 * busy signal.
- 		 */
- 		if (req->cmd->flags & MMC_RSP_BUSY)
--			set_data_timeout(host, 100000000U, 0);
-+			set_data_timeout(host);
- 		return 0;
- 	}
- 
- 	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
- 					| (req->data->blocks << 16));
--	set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
-+	set_data_timeout(host);
- 
- 	if (host->use_dma) {
- 		ret = omap_hsmmc_start_dma_transfer(host, req);
-@@ -1649,6 +1664,8 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
- {
- 	struct omap_hsmmc_host *host = mmc_priv(mmc);
- 	int do_send_init_stream = 0;
-+	struct omap_mmc_platform_data *pdata = host->pdata;
-+	u32 regVal;
- 
- 	pm_runtime_get_sync(host->dev);
- 
-@@ -1673,6 +1690,18 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
- 
- 	/* FIXME: set registers based only on changes to ios */
- 
-+	if (pdata->version == MMC_CTRL_VERSION_2) {
-+		/*
-+		* Set
-+		*	Debounce filter value to max
-+		*	Write protect polarity to Active low level
-+		*/
-+		regVal = OMAP_HSMMC_READ(host->base, CON);
-+		regVal &= ~(DVAL_MASK | WPP_MASK);
-+		regVal |= (DVAL_MAX | WPP_ACT_LOW);
-+		OMAP_HSMMC_WRITE(host->base, CON, regVal);
-+	}
-+
- 	omap_hsmmc_set_bus_width(host);
- 
- 	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
-@@ -1869,7 +1898,7 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
- 	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
- 	struct mmc_host *mmc;
- 	struct omap_hsmmc_host *host = NULL;
--	struct resource *res;
-+	struct resource *res, *dma_tx, *dma_rx;
- 	int ret, irq;
- 
- 	if (pdata == NULL) {
-@@ -1974,7 +2003,10 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
- 
- 	/* Since we do only SG emulation, we can have as many segs
- 	 * as we want. */
--	mmc->max_segs = 1024;
-+	if (pdata->version == MMC_CTRL_VERSION_2)
-+		mmc->max_segs = 1;
-+	else
-+		mmc->max_segs = 1024;
- 
- 	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
- 	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
-@@ -1991,33 +2023,54 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
- 	if (mmc_slot(host).nonremovable)
- 		mmc->caps |= MMC_CAP_NONREMOVABLE;
- 
-+	mmc->pm_caps = mmc_slot(host).pm_caps;
-+
- 	omap_hsmmc_conf_bus_power(host);
- 
- 	/* Select DMA lines */
--	switch (host->id) {
--	case OMAP_MMC1_DEVID:
--		host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
--		host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
--		break;
--	case OMAP_MMC2_DEVID:
--		host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
--		host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
--		break;
--	case OMAP_MMC3_DEVID:
--		host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
--		host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
--		break;
--	case OMAP_MMC4_DEVID:
--		host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
--		host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
--		break;
--	case OMAP_MMC5_DEVID:
--		host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
--		host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
--		break;
--	default:
--		dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
--		goto err_irq;
-+	if (pdata->version == MMC_CTRL_VERSION_2) {
-+		dma_rx = platform_get_resource_byname(pdev,
-+							IORESOURCE_DMA, "rx");
-+		if (!dma_rx) {
-+			ret = -EINVAL;
-+			goto err1;
-+		}
-+
-+		dma_tx = platform_get_resource_byname(pdev,
-+							IORESOURCE_DMA, "tx");
-+		if (!dma_tx) {
-+			ret = -EINVAL;
-+			goto err1;
-+		}
-+		host->dma_line_tx = dma_tx->start;
-+		host->dma_line_rx = dma_rx->start;
-+
-+	} else {
-+		switch (host->id) {
-+		case OMAP_MMC1_DEVID:
-+			host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
-+			host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
-+			break;
-+		case OMAP_MMC2_DEVID:
-+			host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
-+			host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
-+			break;
-+		case OMAP_MMC3_DEVID:
-+			host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
-+			host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
-+			break;
-+		case OMAP_MMC4_DEVID:
-+			host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
-+			host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
-+			break;
-+		case OMAP_MMC5_DEVID:
-+			host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
-+			host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
-+			break;
-+		default:
-+			dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
-+			goto err_irq;
-+		}
- 	}
- 
- 	/* Request IRQ for MMC operations */
-@@ -2179,13 +2232,7 @@ static int omap_hsmmc_suspend(struct device *dev)
- 		cancel_work_sync(&host->mmc_carddetect_work);
- 		ret = mmc_suspend_host(host->mmc);
- 
--		if (ret == 0) {
--			omap_hsmmc_disable_irq(host);
--			OMAP_HSMMC_WRITE(host->base, HCTL,
--				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
--			if (host->got_dbclk)
--				clk_disable(host->dbclk);
--		} else {
-+		if (ret) {
- 			host->suspended = 0;
- 			if (host->pdata->resume) {
- 				ret = host->pdata->resume(&pdev->dev,
-@@ -2194,9 +2241,21 @@ static int omap_hsmmc_suspend(struct device *dev)
- 					dev_dbg(mmc_dev(host->mmc),
- 						"Unmask interrupt failed\n");
- 			}
-+			ret = -EBUSY;
-+			goto err;
- 		}
--		pm_runtime_put_sync(host->dev);
-+
-+		if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
-+			omap_hsmmc_disable_irq(host);
-+			OMAP_HSMMC_WRITE(host->base, HCTL,
-+				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
-+		}
-+		if (host->got_dbclk)
-+			clk_disable(host->dbclk);
-+
- 	}
-+err:
-+	pm_runtime_put_sync(host->dev);
- 	return ret;
- }
- 
-@@ -2216,7 +2275,8 @@ static int omap_hsmmc_resume(struct device *dev)
- 		if (host->got_dbclk)
- 			clk_enable(host->dbclk);
- 
--		omap_hsmmc_conf_bus_power(host);
-+		if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
-+			omap_hsmmc_conf_bus_power(host);
- 
- 		if (host->pdata->resume) {
- 			ret = host->pdata->resume(&pdev->dev, host->slot_id);
-diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
-index 56c7cd4..c9e14a0 100644
---- a/drivers/mtd/devices/Makefile
-+++ b/drivers/mtd/devices/Makefile
-@@ -18,5 +18,6 @@ obj-$(CONFIG_MTD_BLOCK2MTD)	+= block2mtd.o
- obj-$(CONFIG_MTD_DATAFLASH)	+= mtd_dataflash.o
- obj-$(CONFIG_MTD_M25P80)	+= m25p80.o
- obj-$(CONFIG_MTD_SST25L)	+= sst25l.o
-+obj-$(CONFIG_MTD_NAND_OMAP2)	+= omap2_elm.o
- 
--CFLAGS_docg3.o			+= -I$(src)
-\ No newline at end of file
-+CFLAGS_docg3.o			+= -I$(src)
-diff --git a/drivers/mtd/devices/omap2_elm.c b/drivers/mtd/devices/omap2_elm.c
-new file mode 100644
-index 0000000..99e6458
---- /dev/null
-+++ b/drivers/mtd/devices/omap2_elm.c
-@@ -0,0 +1,381 @@
-+/*
-+ * OMAP2 Error Location Module
-+ *
-+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/module.h>
-+#include <linux/interrupt.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/io.h>
-+#include <linux/pm_runtime.h>
-+
-+#include <plat/elm.h>
-+
-+#define ELM_SYSCONFIG			0x010
-+#define ELM_SYSSTATUS			0x014
-+#define ELM_IRQSTATUS			0x018
-+#define ELM_IRQENABLE			0x01c
-+#define ELM_LOCATION_CONFIG		0x020
-+#define ELM_PAGE_CTRL			0x080
-+#define ELM_SYNDROME_FRAGMENT_0		0x400
-+#define ELM_SYNDROME_FRAGMENT_1		0x404
-+#define ELM_SYNDROME_FRAGMENT_2		0x408
-+#define ELM_SYNDROME_FRAGMENT_3		0x40c
-+#define ELM_SYNDROME_FRAGMENT_4		0x410
-+#define ELM_SYNDROME_FRAGMENT_5		0x414
-+#define ELM_SYNDROME_FRAGMENT_6		0x418
-+#define ELM_LOCATION_STATUS		0x800
-+#define ELM_ERROR_LOCATION_0		0x880
-+#define ELM_ERROR_LOCATION_1		0x884
-+#define ELM_ERROR_LOCATION_2		0x888
-+#define ELM_ERROR_LOCATION_3		0x88c
-+#define ELM_ERROR_LOCATION_4		0x890
-+#define ELM_ERROR_LOCATION_5		0x894
-+#define ELM_ERROR_LOCATION_6		0x898
-+#define ELM_ERROR_LOCATION_7		0x89c
-+#define ELM_ERROR_LOCATION_8		0x8a0
-+#define ELM_ERROR_LOCATION_9		0x8a4
-+#define ELM_ERROR_LOCATION_10		0x8a8
-+#define ELM_ERROR_LOCATION_11		0x8ac
-+#define ELM_ERROR_LOCATION_12		0x8b0
-+#define ELM_ERROR_LOCATION_13		0x8b4
-+#define ELM_ERROR_LOCATION_14		0x8b8
-+#define ELM_ERROR_LOCATION_15		0x8bc
-+
-+/* ELM System Configuration Register */
-+#define ELM_SYSCONFIG_SOFTRESET		BIT(1)
-+#define ELM_SYSCONFIG_SIDLE_MASK	(3 << 3)
-+#define ELM_SYSCONFIG_SMART_IDLE	(2 << 3)
-+
-+/* ELM System Status Register */
-+#define ELM_SYSSTATUS_RESETDONE		BIT(0)
-+
-+/* ELM Interrupt Status Register */
-+#define INTR_STATUS_PAGE_VALID		BIT(8)
-+#define INTR_STATUS_LOC_VALID_7		BIT(7)
-+#define INTR_STATUS_LOC_VALID_6		BIT(6)
-+#define INTR_STATUS_LOC_VALID_5		BIT(5)
-+#define INTR_STATUS_LOC_VALID_4		BIT(4)
-+#define INTR_STATUS_LOC_VALID_3		BIT(3)
-+#define INTR_STATUS_LOC_VALID_2		BIT(2)
-+#define INTR_STATUS_LOC_VALID_1		BIT(1)
-+#define INTR_STATUS_LOC_VALID_0		BIT(0)
-+
-+/* ELM Interrupt Enable Register */
-+#define INTR_EN_PAGE_MASK		BIT(8)
-+#define INTR_EN_LOCATION_MASK_7		BIT(7)
-+#define INTR_EN_LOCATION_MASK_6		BIT(6)
-+#define INTR_EN_LOCATION_MASK_5		BIT(5)
-+#define INTR_EN_LOCATION_MASK_4		BIT(4)
-+#define INTR_EN_LOCATION_MASK_3		BIT(3)
-+#define INTR_EN_LOCATION_MASK_2		BIT(2)
-+#define INTR_EN_LOCATION_MASK_1		BIT(1)
-+#define INTR_EN_LOCATION_MASK_0		BIT(0)
-+
-+/* ELM Location Configuration Register */
-+#define ECC_SIZE_MASK			(0x7ff << 16)
-+#define ECC_BCH_LEVEL_MASK		(0x3 << 0)
-+#define ECC_BCH4_LEVEL			(0x0 << 0)
-+#define ECC_BCH8_LEVEL			(0x1 << 0)
-+#define ECC_BCH16_LEVEL			(0x2 << 0)
-+
-+/* ELM Page Definition Register */
-+#define PAGE_MODE_SECTOR_7		BIT(7)
-+#define PAGE_MODE_SECTOR_6		BIT(6)
-+#define PAGE_MODE_SECTOR_5		BIT(5)
-+#define PAGE_MODE_SECTOR_4		BIT(4)
-+#define PAGE_MODE_SECTOR_3		BIT(3)
-+#define PAGE_MODE_SECTOR_2		BIT(2)
-+#define PAGE_MODE_SECTOR_1		BIT(1)
-+#define PAGE_MODE_SECTOR_0		BIT(0)
-+
-+/* ELM syndrome */
-+#define ELM_SYNDROME_VALID		BIT(16)
-+
-+/* ELM_LOCATION_STATUS Register */
-+#define ECC_CORRECTABLE_MASK		BIT(8)
-+#define ECC_NB_ERRORS_MASK		(0x1f << 0)
-+
-+/*  ELM_ERROR_LOCATION_0-15 Registers */
-+#define ECC_ERROR_LOCATION_MASK		(0x1fff << 0)
-+
-+#define OMAP_ECC_SIZE			(0x7ff)
-+
-+#define DRIVER_NAME	"omap2_elm"
-+
-+static void  __iomem *elm_base;
-+static struct completion elm_completion;
-+static struct mtd_info *mtd;
-+static int bch_scheme;
-+
-+static void elm_write_reg(int idx, u32 val)
-+{
-+	writel(val, elm_base + idx);
-+}
-+
-+static u32 elm_read_reg(int idx)
-+{
-+	return readl(elm_base + idx);
-+}
-+
-+/**
-+ * omap_elm_config - Configure ELM for BCH ECC scheme
-+ * @bch_type:	type of BCH ECC scheme
-+ */
-+void omap_elm_config(int bch_type)
-+{
-+	u32 reg_val;
-+	u32 buffer_size = OMAP_ECC_SIZE;
-+
-+	reg_val = (bch_type & ECC_BCH_LEVEL_MASK) | (buffer_size << 16);
-+	elm_write_reg(ELM_LOCATION_CONFIG, reg_val);
-+
-+	/* clearing interrupts */
-+	reg_val = elm_read_reg(ELM_IRQSTATUS);
-+	elm_write_reg(ELM_IRQSTATUS, reg_val & INTR_STATUS_LOC_VALID_0);
-+	elm_write_reg(ELM_IRQSTATUS, INTR_STATUS_LOC_VALID_0);
-+
-+	/* enable in interrupt mode */
-+	reg_val = elm_read_reg(ELM_IRQENABLE);
-+	reg_val |= INTR_EN_LOCATION_MASK_0;
-+	elm_write_reg(ELM_IRQENABLE, reg_val);
-+
-+	/* config in Continuous mode */
-+	reg_val = elm_read_reg(ELM_PAGE_CTRL);
-+	reg_val &= ~PAGE_MODE_SECTOR_0;
-+	elm_write_reg(ELM_PAGE_CTRL, reg_val);
-+}
-+
-+/**
-+ * omap_configure_elm - Configure ELM for BCH ECC scheme
-+ * @mtd_info:	mtd info structure
-+ * @bch_type:	type of BCH ECC scheme
-+ *
-+ * Configures the ELM module to support BCH error correction
-+ */
-+void omap_configure_elm(struct mtd_info *mtd_info, int bch_type)
-+{
-+	omap_elm_config(bch_type);
-+	mtd = mtd_info;
-+	bch_scheme = bch_type;
-+}
-+EXPORT_SYMBOL(omap_configure_elm);
-+
-+/**
-+ * omap_elm_load_syndrome - Load ELM syndrome reg
-+ * @bch_type:	type of BCH ECC scheme
-+ * @syndrome:	Syndrome polynomial
-+ *
-+ * Load the syndrome polynomial to syndrome registers
-+ */
-+void omap_elm_load_syndrome(int bch_type, char *syndrome)
-+{
-+	int reg_val;
-+	int i;
-+
-+	for (i = 0; i < 4; i++) {
-+		reg_val = syndrome[0] | syndrome[1] << 8 |
-+			syndrome[2] << 16 | syndrome[3] << 24;
-+		elm_write_reg(ELM_SYNDROME_FRAGMENT_0 + i * 4, reg_val);
-+		syndrome += 4;
-+	}
-+}
-+
-+/**
-+ * omap_elm_start_processing - Start calculting error location
-+ */
-+void omap_elm_start_processing(void)
-+{
-+	u32 reg_val;
-+
-+	reg_val = elm_read_reg(ELM_SYNDROME_FRAGMENT_6);
-+	reg_val |= ELM_SYNDROME_VALID;
-+	elm_write_reg(ELM_SYNDROME_FRAGMENT_6, reg_val);
-+}
-+
-+void rotate_ecc_bytes(u8 *src, u8 *dst)
-+{
-+	int i;
-+
-+	for (i = 0; i < BCH8_ECC_OOB_BYTES; i++)
-+		dst[BCH8_ECC_OOB_BYTES - 1 - i] = src[i];
-+}
-+
-+/**
-+ * omap_elm_decode_bch_error - Locate error pos
-+ * @bch_type:	Type of BCH ECC scheme
-+ * @ecc_calc:	Calculated ECC bytes from GPMC
-+ * @err_loc:	Error location bytes
-+ */
-+int omap_elm_decode_bch_error(int bch_type, char *ecc_calc,
-+		unsigned int *err_loc)
-+{
-+	u8 ecc_data[BCH_MAX_ECC_BYTES_PER_SECTOR] = {0};
-+	u32 reg_val;
-+	int i, err_no;
-+
-+	rotate_ecc_bytes(ecc_calc, ecc_data);
-+	omap_elm_load_syndrome(bch_type, ecc_data);
-+	omap_elm_start_processing();
-+	wait_for_completion(&elm_completion);
-+	reg_val = elm_read_reg(ELM_LOCATION_STATUS);
-+
-+	if (reg_val & ECC_CORRECTABLE_MASK) {
-+		err_no = reg_val & ECC_NB_ERRORS_MASK;
-+
-+		for (i = 0; i < err_no; i++) {
-+			reg_val = elm_read_reg(ELM_ERROR_LOCATION_0 + i * 4);
-+			err_loc[i] = reg_val;
-+		}
-+
-+		return err_no;
-+	}
-+
-+	return -EINVAL;
-+}
-+EXPORT_SYMBOL(omap_elm_decode_bch_error);
-+
-+static irqreturn_t omap_elm_isr(int this_irq, void *dev_id)
-+{
-+	u32 reg_val;
-+
-+	reg_val = elm_read_reg(ELM_IRQSTATUS);
-+
-+	if (reg_val & INTR_STATUS_LOC_VALID_0) {
-+		elm_write_reg(ELM_IRQSTATUS, reg_val & INTR_STATUS_LOC_VALID_0);
-+		complete(&elm_completion);
-+		return IRQ_HANDLED;
-+	}
-+
-+	return IRQ_NONE;
-+}
-+
-+static int omap_elm_probe(struct platform_device *pdev)
-+{
-+	int  ret_status = 0;
-+	struct resource *res = NULL, *irq = NULL;
-+
-+	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+
-+	if (irq == NULL)
-+		return -EINVAL;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+	if (res == NULL)
-+		return -EINVAL;
-+
-+	if (!request_mem_region(res->start, resource_size(res),
-+				dev_name(&pdev->dev)))
-+		return -EBUSY;
-+
-+	elm_base = ioremap(res->start, resource_size(res));
-+
-+	if (!elm_base) {
-+		dev_dbg(&pdev->dev, "can't ioremap\n");
-+		ret_status = -ENOMEM;
-+		goto err_remap;
-+	}
-+
-+	pm_runtime_enable(&pdev->dev);
-+	if (pm_runtime_get_sync(&pdev->dev)) {
-+		ret_status = -EINVAL;
-+		dev_dbg(&pdev->dev, "can't enable clock\n");
-+		goto err_clk;
-+	}
-+
-+	ret_status = request_irq(irq->start, omap_elm_isr, 0, pdev->name,
-+			&pdev->dev);
-+
-+	if (ret_status) {
-+		pr_err("failure requesting irq %i\n", irq->start);
-+		goto err_irq;
-+	}
-+
-+	init_completion(&elm_completion);
-+	return ret_status;
-+
-+err_irq:
-+	pm_runtime_put_sync(&pdev->dev);
-+	pm_runtime_disable(&pdev->dev);
-+err_clk:
-+	iounmap(elm_base);
-+err_remap:
-+	release_mem_region(res->start, resource_size(res));
-+	return ret_status;
-+}
-+
-+static int omap_elm_remove(struct platform_device *pdev)
-+{
-+	struct resource *res = NULL;
-+
-+	iounmap(elm_base);
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	release_mem_region(res->start, resource_size(res));
-+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+	free_irq(res->start, &pdev->dev);
-+	pm_runtime_put_sync(&pdev->dev);
-+	pm_runtime_disable(&pdev->dev);
-+	return 0;
-+}
-+
-+
-+#ifdef CONFIG_PM
-+static int omap_elm_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+	if (mtd && mtd->suspend)
-+		mtd->suspend(mtd);
-+	pm_runtime_put_sync(&pdev->dev);
-+	return 0;
-+}
-+
-+static int omap_elm_resume(struct platform_device *pdev)
-+{
-+	pm_runtime_get_sync(&pdev->dev);
-+	/* Restore ELM context by configuring */
-+	omap_elm_config(bch_scheme);
-+	return 0;
-+}
-+#endif
-+
-+static struct platform_driver omap_elm_driver = {
-+	.probe		= omap_elm_probe,
-+	.remove		= omap_elm_remove,
-+#ifdef CONFIG_PM
-+	.suspend	= omap_elm_suspend,
-+	.resume		= omap_elm_resume,
-+#endif
-+	.driver		= {
-+		.name	= DRIVER_NAME,
-+		.owner	= THIS_MODULE,
-+	},
-+};
-+
-+static int __init omap_elm_init(void)
-+{
-+
-+	return platform_driver_register(&omap_elm_driver);
-+}
-+
-+static void __exit omap_elm_exit(void)
-+{
-+	platform_driver_unregister(&omap_elm_driver);
-+}
-+
-+module_init(omap_elm_init);
-+module_exit(omap_elm_exit);
-+
-+MODULE_ALIAS("platform:" DRIVER_NAME);
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
-index 3ed9c5e..a5df3ec 100644
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -724,6 +724,8 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
- 		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
- 			       NAND_NCE | NAND_CTRL_CHANGE);
- 
-+		dmb();
-+
- 		/* This applies to read commands */
- 	default:
- 		/*
-@@ -1993,6 +1995,7 @@ static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
- 	const uint8_t *p = buf;
- 	uint32_t *eccpos = chip->ecc.layout->eccpos;
- 
-+	memset(ecc_calc, 0, eccsteps * eccbytes);
- 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- 		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
- 		chip->write_buf(mtd, p, eccsize);
-diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
-index f745f00..a2d3e29 100644
---- a/drivers/mtd/nand/omap2.c
-+++ b/drivers/mtd/nand/omap2.c
-@@ -24,6 +24,7 @@
- #include <plat/dma.h>
- #include <plat/gpmc.h>
- #include <plat/nand.h>
-+#include <plat/elm.h>
- 
- #define	DRIVER_NAME	"omap2-nand"
- #define	OMAP_NAND_TIMEOUT_MS	5000
-@@ -95,6 +96,13 @@
- #define P4e_s(a)	(TF(a & NAND_Ecc_P4e)		<< 0)
- #define P4o_s(a)	(TF(a & NAND_Ecc_P4o)		<< 1)
- 
-+#define MAX_HWECC_BYTES_OOB_64     24
-+#define JFFS2_CLEAN_MARKER_OFFSET  0x2
-+
-+#define BCH_ECC_POS			0x2
-+#define BCH_JFFS2_CLEAN_MARKER_OFFSET	0x3a
-+#define OMAP_BCH8_ECC_SECT_BYTES	14
-+
- /* oob info generated runtime depending on ecc algorithm and layout selected */
- static struct nand_ecclayout omap_oobinfo;
- /* Define some generic bad / good block scan pattern which are used
-@@ -126,7 +134,10 @@ struct omap_nand_info {
- 		OMAP_NAND_IO_WRITE,	/* write */
- 	} iomode;
- 	u_char				*buf;
--	int					buf_len;
-+	int				buf_len;
-+	int				ecc_opt;
-+	int (*ctrlr_suspend) (void);
-+	int (*ctrlr_resume) (void);
- };
- 
- /**
-@@ -783,6 +794,76 @@ static int omap_compare_ecc(u8 *ecc_data1,	/* read from NAND memory */
- }
- 
- /**
-+ * omap_read_page_bch - BCH ecc based page read function
-+ * @mtd:	mtd info structure
-+ * @chip:	nand chip info structure
-+ * @buf:	buffer to store read data
-+ * @page:	page number to read
-+ *
-+ * For BCH ECC scheme, GPMC used for syndrome calculation and ELM module
-+ * used for error correction.
-+ */
-+static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
-+				uint8_t *buf, int page)
-+{
-+	int i, eccsize = chip->ecc.size;
-+	int eccbytes = chip->ecc.bytes;
-+	int eccsteps = chip->ecc.steps;
-+	uint8_t *p = buf;
-+	uint8_t *ecc_calc = chip->buffers->ecccalc;
-+	uint8_t *ecc_code = chip->buffers->ecccode;
-+	uint32_t *eccpos = chip->ecc.layout->eccpos;
-+	uint8_t *oob = &chip->oob_poi[eccpos[0]];
-+	uint32_t data_pos;
-+	uint32_t oob_pos;
-+
-+	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
-+							mtd);
-+	data_pos = 0;
-+	/* oob area start */
-+	oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
-+
-+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
-+				oob += eccbytes) {
-+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
-+		/* read data */
-+		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
-+		chip->read_buf(mtd, p, eccsize);
-+
-+		/* read respective ecc from oob area */
-+		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
-+
-+		if (info->ecc_opt == OMAP_ECC_BCH8_CODE_HW)
-+			chip->read_buf(mtd, oob, 13);
-+		else
-+			chip->read_buf(mtd, oob, eccbytes);
-+		/* read syndrome */
-+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
-+
-+		data_pos += eccsize;
-+		oob_pos += eccbytes;
-+	}
-+
-+	for (i = 0; i < chip->ecc.total; i++)
-+		ecc_code[i] = chip->oob_poi[eccpos[i]];
-+
-+	eccsteps = chip->ecc.steps;
-+	p = buf;
-+
-+	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-+		int stat;
-+
-+		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
-+
-+		if (stat < 0)
-+			mtd->ecc_stats.failed++;
-+		else
-+			mtd->ecc_stats.corrected += stat;
-+	}
-+	return 0;
-+}
-+
-+/**
-  * omap_correct_data - Compares the ECC read with HW generated ECC
-  * @mtd: MTD device structure
-  * @dat: page data
-@@ -803,6 +884,8 @@ static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
- 							mtd);
- 	int blockCnt = 0, i = 0, ret = 0;
- 	int stat = 0;
-+	int j, eccsize, eccflag, count;
-+	unsigned int err_loc[8];
- 
- 	/* Ex NAND_ECC_HW12_2048 */
- 	if ((info->nand.ecc.mode == NAND_ECC_HW) &&
-@@ -811,17 +894,64 @@ static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
- 	else
- 		blockCnt = 1;
- 
--	for (i = 0; i < blockCnt; i++) {
--		if (memcmp(read_ecc, calc_ecc, 3) != 0) {
--			ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
--			if (ret < 0)
--				return ret;
--			/* keep track of the number of corrected errors */
--			stat += ret;
-+	switch (info->ecc_opt) {
-+	case OMAP_ECC_HAMMING_CODE_HW:
-+	case OMAP_ECC_HAMMING_CODE_HW_ROMCODE:
-+		for (i = 0; i < blockCnt; i++) {
-+			if (memcmp(read_ecc, calc_ecc, 3) != 0) {
-+				ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
-+				if (ret < 0)
-+					return ret;
-+
-+				/* keep track of number of corrected errors */
-+				stat += ret;
-+			}
-+			read_ecc += 3;
-+			calc_ecc += 3;
-+			dat      += 512;
- 		}
--		read_ecc += 3;
--		calc_ecc += 3;
--		dat      += 512;
-+		break;
-+	case OMAP_ECC_BCH8_CODE_HW:
-+		eccsize = BCH8_ECC_OOB_BYTES;
-+
-+		for (i = 0; i < blockCnt; i++) {
-+			eccflag = 0;
-+			/* check if area is flashed */
-+			for (j = 0; (j < eccsize) && (eccflag == 0); j++)
-+				if (read_ecc[j] != 0xFF)
-+					eccflag = 1;
-+
-+			if (eccflag == 1) {
-+				eccflag = 0;
-+				/* check if any ecc error */
-+				for (j = 0; (j < eccsize) && (eccflag == 0);
-+						j++)
-+					if (calc_ecc[j] != 0)
-+						eccflag = 1;
-+			}
-+
-+			count = 0;
-+			if (eccflag == 1)
-+				count  = omap_elm_decode_bch_error(0, calc_ecc,
-+						err_loc);
-+
-+			for (j = 0; j < count; j++) {
-+				u32 bit_pos, byte_pos;
-+
-+				bit_pos   = err_loc[j] % 8;
-+				byte_pos  = (BCH8_ECC_MAX - err_loc[j] - 1) / 8;
-+				if (err_loc[j] < BCH8_ECC_MAX)
-+					dat[byte_pos] ^=
-+							1 << bit_pos;
-+				/* else, not interested to correct ecc */
-+			}
-+
-+			stat     += count;
-+			calc_ecc  = calc_ecc + OMAP_BCH8_ECC_SECT_BYTES;
-+			read_ecc  = read_ecc + OMAP_BCH8_ECC_SECT_BYTES;
-+			dat      += BCH8_ECC_BYTES;
-+		}
-+		break;
- 	}
- 	return stat;
- }
-@@ -843,7 +973,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
- {
- 	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
- 							mtd);
--	return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
-+	return gpmc_calculate_ecc(info->ecc_opt, info->gpmc_cs, dat, ecc_code);
- }
- 
- /**
-@@ -858,7 +988,8 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
- 	struct nand_chip *chip = mtd->priv;
- 	unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
- 
--	gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
-+	gpmc_enable_hwecc(info->ecc_opt, info->gpmc_cs, mode,
-+				dev_width, info->nand.ecc.size);
- }
- 
- /**
-@@ -955,10 +1086,24 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
- 	info->mtd.priv		= &info->nand;
- 	info->mtd.name		= dev_name(&pdev->dev);
- 	info->mtd.owner		= THIS_MODULE;
-+	info->ecc_opt		= pdata->ecc_opt;
- 
- 	info->nand.options	= pdata->devsize;
- 	info->nand.options	|= NAND_SKIP_BBTSCAN;
- 
-+	/*
-+	 * If ELM feature is used in OMAP NAND driver, then configure it
-+	 */
-+	if (pdata->elm_used) {
-+		if (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)
-+			omap_configure_elm(&info->mtd, OMAP_BCH8_ECC);
-+	}
-+
-+	if (pdata->ctrlr_suspend)
-+		info->ctrlr_suspend = pdata->ctrlr_suspend;
-+	if (pdata->ctrlr_resume)
-+		info->ctrlr_resume = pdata->ctrlr_resume;
-+
- 	/* NAND write protect off */
- 	gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
- 
-@@ -1054,10 +1199,19 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
- 	/* selsect the ecc type */
- 	if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
- 		info->nand.ecc.mode = NAND_ECC_SOFT;
--	else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
--		(pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
--		info->nand.ecc.bytes            = 3;
--		info->nand.ecc.size             = 512;
-+	else {
-+		if (pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) {
-+			info->nand.ecc.bytes    = 4*7;
-+			info->nand.ecc.size     = 4*512;
-+		} else if (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW) {
-+			info->nand.ecc.bytes     = OMAP_BCH8_ECC_SECT_BYTES;
-+			info->nand.ecc.size      = 512;
-+			info->nand.ecc.read_page = omap_read_page_bch;
-+		} else {
-+			info->nand.ecc.bytes    = 3;
-+			info->nand.ecc.size     = 512;
-+		}
-+
- 		info->nand.ecc.calculate        = omap_calculate_ecc;
- 		info->nand.ecc.hwctl            = omap_enable_hwecc;
- 		info->nand.ecc.correct          = omap_correct_data;
-@@ -1075,23 +1229,48 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
- 		}
- 	}
- 
--	/* rom code layout */
--	if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
-+	/* select ecc lyout */
-+	if (info->nand.ecc.mode != NAND_ECC_SOFT) {
- 
--		if (info->nand.options & NAND_BUSWIDTH_16)
--			offset = 2;
--		else {
--			offset = 1;
-+		if (!(info->nand.options & NAND_BUSWIDTH_16))
- 			info->nand.badblock_pattern = &bb_descrip_flashbased;
-+
-+		offset = JFFS2_CLEAN_MARKER_OFFSET;
-+
-+		if (info->mtd.oobsize == 64)
-+			omap_oobinfo.eccbytes = info->nand.ecc.bytes *
-+						2048/info->nand.ecc.size;
-+		else
-+			omap_oobinfo.eccbytes = info->nand.ecc.bytes;
-+
-+		if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
-+			omap_oobinfo.oobfree->offset =
-+						offset + omap_oobinfo.eccbytes;
-+			omap_oobinfo.oobfree->length = info->mtd.oobsize -
-+				(offset + omap_oobinfo.eccbytes);
-+		} else if (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW) {
-+			offset = BCH_ECC_POS; /* Synchronize with U-boot */
-+			omap_oobinfo.oobfree->offset =
-+				BCH_JFFS2_CLEAN_MARKER_OFFSET;
-+			omap_oobinfo.oobfree->length = info->mtd.oobsize -
-+						offset - omap_oobinfo.eccbytes;
-+		} else {
-+			omap_oobinfo.oobfree->offset = offset;
-+			omap_oobinfo.oobfree->length = info->mtd.oobsize -
-+						offset - omap_oobinfo.eccbytes;
-+			/*
-+			offset is calculated considering the following :
-+			1) 12 bytes ECC for 512 byte access and 24 bytes ECC for
-+			256 byte access in OOB_64 can be supported
-+			2)Ecc bytes lie to the end of OOB area.
-+			3)Ecc layout must match with u-boot's ECC layout.
-+			*/
-+			offset = info->mtd.oobsize - MAX_HWECC_BYTES_OOB_64;
- 		}
--		omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
-+
- 		for (i = 0; i < omap_oobinfo.eccbytes; i++)
- 			omap_oobinfo.eccpos[i] = i+offset;
- 
--		omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
--		omap_oobinfo.oobfree->length = info->mtd.oobsize -
--					(offset + omap_oobinfo.eccbytes);
--
- 		info->nand.ecc.layout = &omap_oobinfo;
- 	}
- 
-@@ -1132,13 +1311,46 @@ static int omap_nand_remove(struct platform_device *pdev)
- 	/* Release NAND device, its internal structures and partitions */
- 	nand_release(&info->mtd);
- 	iounmap(info->nand.IO_ADDR_R);
-+	release_mem_region(info->phys_base, NAND_IO_SIZE);
- 	kfree(&info->mtd);
- 	return 0;
- }
- 
-+#ifdef CONFIG_PM
-+static int omap_nand_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+	struct mtd_info *mtd = platform_get_drvdata(pdev);
-+	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
-+							mtd);
-+
-+	mtd->suspend(mtd);
-+
-+	if (info->ctrlr_suspend)
-+		info->ctrlr_suspend();
-+
-+	return 0;
-+}
-+
-+static int omap_nand_resume(struct platform_device *pdev)
-+{
-+	struct mtd_info *mtd = platform_get_drvdata(pdev);
-+	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
-+							mtd);
-+
-+	if (info->ctrlr_resume)
-+		info->ctrlr_resume();
-+
-+	return 0;
-+}
-+#endif
-+
- static struct platform_driver omap_nand_driver = {
- 	.probe		= omap_nand_probe,
- 	.remove		= omap_nand_remove,
-+#ifdef CONFIG_PM
-+	.suspend	= omap_nand_suspend,
-+	.resume		= omap_nand_resume,
-+#endif
- 	.driver		= {
- 		.name	= DRIVER_NAME,
- 		.owner	= THIS_MODULE,
-diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
-index f6c98fb..6851445 100644
---- a/drivers/net/can/Kconfig
-+++ b/drivers/net/can/Kconfig
-@@ -116,6 +116,8 @@ source "drivers/net/can/sja1000/Kconfig"
- 
- source "drivers/net/can/c_can/Kconfig"
- 
-+source "drivers/net/can/d_can/Kconfig"
-+
- source "drivers/net/can/usb/Kconfig"
- 
- source "drivers/net/can/softing/Kconfig"
-diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
-index 24ebfe8..3377679 100644
---- a/drivers/net/can/Makefile
-+++ b/drivers/net/can/Makefile
-@@ -14,6 +14,7 @@ obj-y				+= softing/
- obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
- obj-$(CONFIG_CAN_MSCAN)		+= mscan/
- obj-$(CONFIG_CAN_C_CAN)		+= c_can/
-+obj-$(CONFIG_CAN_D_CAN)		+= d_can/
- obj-$(CONFIG_CAN_AT91)		+= at91_can.o
- obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
- obj-$(CONFIG_CAN_MCP251X)	+= mcp251x.o
-diff --git a/drivers/net/can/d_can/Kconfig b/drivers/net/can/d_can/Kconfig
-new file mode 100644
-index 0000000..e5e9dcf
---- /dev/null
-+++ b/drivers/net/can/d_can/Kconfig
-@@ -0,0 +1,14 @@
-+menuconfig CAN_D_CAN
-+	tristate "Bosch D_CAN devices"
-+	depends on CAN_DEV && HAS_IOMEM
-+
-+if CAN_D_CAN
-+
-+config CAN_D_CAN_PLATFORM
-+	tristate "Generic Platform Bus based D_CAN driver"
-+	---help---
-+	  This driver adds support for the D_CAN chips connected to
-+	  the "platform bus" (Linux abstraction for directly to the
-+	  processor attached devices) which can be found on am335x
-+	  and dm814x boards from TI (http://www.ti.com).
-+endif
-diff --git a/drivers/net/can/d_can/Makefile b/drivers/net/can/d_can/Makefile
-new file mode 100644
-index 0000000..80560c5
---- /dev/null
-+++ b/drivers/net/can/d_can/Makefile
-@@ -0,0 +1,8 @@
-+#
-+#  Makefile for the Bosch D_CAN controller drivers.
-+#
-+
-+obj-$(CONFIG_CAN_D_CAN) += d_can.o
-+obj-$(CONFIG_CAN_D_CAN_PLATFORM) += d_can_platform.o
-+
-+ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
-diff --git a/drivers/net/can/d_can/d_can.c b/drivers/net/can/d_can/d_can.c
-new file mode 100644
-index 0000000..18a9e10
---- /dev/null
-+++ b/drivers/net/can/d_can/d_can.c
-@@ -0,0 +1,1415 @@
-+/*
-+ * CAN bus driver for Bosch D_CAN controller
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * Borrowed from C_CAN driver
-+ * Copyright (C) 2010 ST Microelectronics
-+ * - Bhupesh Sharma <bhupesh.sharma@st.com>
-+ *
-+ * Borrowed heavily from the C_CAN driver originally written by:
-+ * Copyright (C) 2007
-+ * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
-+ * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
-+ *
-+ * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
-+ * Bosch D_CAN user manual can be obtained from:
-+ * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
-+ * d_can_users_manual_111.pdf
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/netdevice.h>
-+#include <linux/if_arp.h>
-+#include <linux/if_ether.h>
-+#include <linux/list.h>
-+#include <linux/io.h>
-+
-+#include <linux/platform_device.h>
-+#include <linux/can.h>
-+#include <linux/can/dev.h>
-+#include <linux/can/error.h>
-+
-+#include "d_can.h"
-+
-+/* TI D_CAN module registers */
-+#define D_CAN_CTL		0x0	/* CAN control register */
-+#define D_CAN_ES		0x4	/* Error and status */
-+#define D_CAN_PARITYERR_EOI	0x4	/* Parity error EOI */
-+#define D_CAN_ERRC		0x8	/* Error counter */
-+#define D_CAN_BTR		0xC	/* Bit timing */
-+#define D_CAN_INT		0x10	/* Interrupt register */
-+#define D_CAN_TEST		0x14	/* Test register */
-+#define D_CAN_PERR		0x1C	/* Parity Error Code */
-+#define D_CAN_ABOTR		0x80	/* Auto-Bus-On Time */
-+#define D_CAN_TXRQ_X		0x84	/* Transmission Request X */
-+#define D_CAN_TXRQ(n)		(0x88 + ((n) * 4)) /* Transmission request */
-+#define D_CAN_NWDAT_X		0x98	/* New data X register */
-+#define D_CAN_NWDAT(n)		(0x9C + ((n) * 4)) /* New data */
-+#define D_CAN_INTPND_X		0xAC	/* Interrupt Pending X */
-+#define D_CAN_INTPND(n)		(0xB0 + ((n) * 4)) /* Interrupt Pending */
-+#define D_CAN_MSGVAL_X		0xC0		/* Message Valid X */
-+#define D_CAN_MSGVAL(n)		(0xC4 + ((n) * 4)) /* Message Valid */
-+#define D_CAN_INTMUX(n)		(0xD8 + ((n) * 4)) /* Interrupt Multiplexer */
-+#define D_CAN_IFCMD(n)		(0x100 + ((n) * 0x20)) /* Command */
-+#define D_CAN_IFMSK(n)		(0x104 + ((n) * 0x20)) /* Mask */
-+#define D_CAN_IFARB(n)		(0x108 + ((n) * 0x20)) /* Arbitration */
-+#define D_CAN_IFMCTL(n)		(0x10c + ((n) * 0x20)) /* Message ctl */
-+#define D_CAN_IFDATA(n)		(0x110 + ((n) * 0x20)) /* DATA A */
-+#define D_CAN_IFDATB(n)		(0x114 + ((n) * 0x20)) /* DATA B */
-+#define D_CAN_IF3OBS		0x140	/* IF3 Observation */
-+#define D_CAN_IF3UPD(n)		(0x160 + ((n) * 4)) /* Update enable */
-+#define D_CAN_TIOC		0x1E0	/* CAN TX IO Control */
-+#define D_CAN_RIOC		0x1E4	/* CAN RX IO Control */
-+
-+/* Control register Bit fields */
-+#define D_CAN_CTL_WUBA		BIT(26)	/* Automatic wake-up on bus activity */
-+#define D_CAN_CTL_PDR		BIT(24)	/* Request for local low power mode */
-+#define D_CAN_CTL_DE3		BIT(20)	/* Enable DMA request line for IF3 */
-+#define D_CAN_CTL_DE2		BIT(19)	/* Enable DMA request line for IF2 */
-+#define D_CAN_CTL_DE1		BIT(18)	/* Enable DMA request line for IF1 */
-+#define D_CAN_CTL_IE1		BIT(17)	/* Interrupt line 1 enable */
-+#define D_CAN_CTL_INITDBG	BIT(16)	/* Init state for debug access */
-+#define D_CAN_CTL_SWR		BIT(15)	/* S/W reset enable */
-+#define D_CAN_CTL_PMD		(0xF << 10)	/* Parity on/off */
-+#define D_CAN_CTL_ABO		BIT(9)	/* Auto bus on enable */
-+#define D_CAN_CTL_IDS		BIT(8)	/* Interruption debug support enable */
-+#define D_CAN_CTL_TEST		BIT(7)	/* Test mode enable */
-+#define D_CAN_CTL_CCE		BIT(6)	/* Configuration change enable */
-+#define D_CAN_CTL_DISABLE_AR	BIT(5)	/* Disable automatic retransmission */
-+#define D_CAN_CTL_ENABLE_AR	(0 << 5)
-+#define D_CAN_CTL_EIE		BIT(3)	/* Error interrupt enable */
-+#define D_CAN_CTL_SIE		BIT(2)	/* Status change int enable */
-+#define D_CAN_CTL_IE0		BIT(1)	/* Interrupt line 0 enable */
-+#define D_CAN_CTL_INIT		BIT(0)	/* D_CAN initialization mode */
-+
-+/* D_CAN Error and Status and Parity Error EOI reg bit fields */
-+#define D_CAN_ES_PDA		BIT(10)	/* Local power-down ACK */
-+#define D_CAN_ES_WUP		BIT(9)	/* Wkae up pending */
-+#define D_CAN_ES_PER		BIT(8)	/* Parity error detected */
-+#define D_CAN_ES_BOFF		BIT(7)	/* Bus off state */
-+#define D_CAN_ES_EWARN		BIT(6)	/* Warning state */
-+#define D_CAN_ES_EPASS		BIT(5)	/* Error passive state */
-+#define D_CAN_ES_RXOK		BIT(4)	/* Received a msg successfully */
-+#define D_CAN_ES_TXOK		BIT(3)	/* Transmitted a msg successfully */
-+#define D_CAN_ES_LEC_MASK	0x7	/* Last error code */
-+
-+/* Parity error reg bit fields */
-+#define D_CAN_PEEOI		BIT(8)	/* EOI indication for parity error */
-+
-+/* Error counter reg bit fields */
-+#define D_CAN_ERRC_RP_SHIFT	15
-+#define D_CAN_ERRC_RP_MASK	BIT(15)		/* Receive error passive */
-+#define D_CAN_ERRC_REC_SHIFT	8
-+#define D_CAN_ERRC_REC_MASK	(0x7F << 8)	/* Receive err counter */
-+#define D_CAN_ERRC_TEC_SHIFT	0
-+#define D_CAN_ERRC_TEC_MASK	(0xFF << 0)	/* Transmit err counter */
-+
-+/* Bit timing reg bit fields */
-+#define D_CAN_BTR_BRPE_SHIFT	16
-+#define D_CAN_BTR_BRPE_MASK	(0xF << 16)	/* Baud rate prescaler ext */
-+#define D_CAN_BTR_TSEG2_SHIFT	12
-+#define D_CAN_BTR_TSEG2_MASK	(0x7 << 12)	/* Time seg after smpl point */
-+#define D_CAN_BTR_TSEG1_SHIFT	8
-+#define D_CAN_BTR_TSEG1_MASK	(0xF << 8)	/* Time seg before smpl point */
-+#define D_CAN_BTR_SJW_SHIFT	6
-+#define D_CAN_BTR_SJW_MASK	(0x3 << 6)	/* Syncronization jump width */
-+#define D_CAN_BTR_BRP_SHIFT	0
-+#define D_CAN_BTR_BRP_MASK	(0x3F << 0)	/* Baud rate prescaler */
-+
-+/* D_CAN Test register bit fields */
-+#define D_CAN_TEST_RDA		BIT(9)	/* RAM direct access enable */
-+#define D_CAN_TEST_EXL		BIT(8)	/* External loopback mode */
-+#define D_CAN_TEST_RX		BIT(7)	/* Monitors the reveive pin */
-+#define D_CAN_TEST_TX		(0x3 << 5)	/* Control of CAN_TX pin */
-+#define D_CAN_TEST_LBACK	BIT(4)	/* Loopback mode */
-+#define D_CAN_TEST_SILENT	BIT(3)	/* Silent mdoe */
-+
-+/* D_CAN Parity error reg bit fields */
-+#define D_CAN_PERR_WN_MASK	(0x7 << 8)	/* Parity error word nuber */
-+#define D_CAN_PERR_MN_MASK	0xFF		/* Parity error msg object */
-+
-+/* D_CAN X registers bit fields */
-+#define D_CAN_BIT_FIELD(n)	(0x3 << (2 * n)) /* X reg's bit field 1 mask */
-+
-+/* D_CAN IF command reg bit fields */
-+#define D_CAN_IF_CMD_WR		BIT(23)	/* Write/read */
-+#define D_CAN_IF_CMD_MASK	BIT(22)	/* Access to mask bits */
-+#define D_CAN_IF_CMD_ARB	BIT(21)	/* Access to arbitration bits */
-+#define D_CAN_IF_CMD_CONTROL	BIT(20)	/* Acess to control bits */
-+#define D_CAN_IF_CMD_CIP	BIT(19)	/* Clear int pending */
-+#define D_CAN_IF_CMD_TXRQST	BIT(18)	/* Access transmission request */
-+#define D_CAN_IF_CMD_DATAA	BIT(17)	/* Access to Data Bytes 0-3 */
-+#define D_CAN_IF_CMD_DATAB	BIT(16)	/* Access to Data Bytes 4-7 */
-+#define D_CAN_IF_CMD_BUSY	BIT(15)	/* Busy flag */
-+#define D_CAN_IF_CMD_DAM	BIT(14)	/* Activation of DMA */
-+#define D_CAN_IF_CMD_MN_MASK	0xFF	/* No. of msg's used for DMA T/F */
-+#define D_CAN_IF_CMD_ALL	(D_CAN_IF_CMD_MASK | D_CAN_IF_CMD_ARB | \
-+				D_CAN_IF_CMD_CONTROL | D_CAN_IF_CMD_TXRQST | \
-+				D_CAN_IF_CMD_DATAA | D_CAN_IF_CMD_DATAB)
-+
-+/* D_CAN IF mask reg bit fields */
-+#define D_CAN_IF_MASK_MX	BIT(31)	/* Mask Extended Identifier */
-+#define D_CAN_IF_MASK_MD	BIT(30)	/* Mask Message direction */
-+
-+/* D_CAN IF Arbitration */
-+#define D_CAN_IF_ARB_MSGVAL	BIT(31)	/* Message Vaild */
-+#define D_CAN_IF_ARB_MSGXTD	BIT(30)	/* Extended Identifier 0-11 1-29 */
-+#define D_CAN_IF_ARB_DIR_XMIT	BIT(29) /* Message direction 0-R 1-T */
-+
-+/* D_CAN IF Message control */
-+#define D_CAN_IF_MCTL_NEWDAT	BIT(15)	/* New data available */
-+#define D_CAN_IF_MCTL_MSGLST	BIT(14)	/* Message lost, only for receive */
-+#define D_CAN_IF_MCTL_CLR_MSGLST (0 << 14)
-+#define D_CAN_IF_MCTL_INTPND	BIT(13)	/* Interrupt pending */
-+#define D_CAN_IF_MCTL_UMASK	BIT(12)	/* Use acceptance mask */
-+#define D_CAN_IF_MCTL_TXIE	BIT(11)	/* Transmit int enable */
-+#define D_CAN_IF_MCTL_RXIE	BIT(10)	/* Receive int enable */
-+#define D_CAN_IF_MCTL_RMTEN	BIT(9)	/* Remote enable */
-+#define D_CAN_IF_MCTL_TXRQST	BIT(8)	/* Transmit request */
-+#define D_CAN_IF_MCTL_EOB	BIT(7)	/* Data frames */
-+#define D_CAN_IF_MCTL_DLC_MASK	0xF	/* Data length code */
-+
-+/* D_CAN IF3 Observation reg bit fields */
-+#define D_CAN_IF3OBS_UP		BIT(15)	/* Update data status */
-+#define D_CAN_IF3OBS_SDB	BIT(12)	/* DataB read out status */
-+#define D_CAN_IF3OBS_SDA	BIT(11)	/* DataA read out status */
-+#define D_CAN_IF3OBS_SC		BIT(10)	/* Contol bits read out status */
-+#define D_CAN_IF3OBS_SA		BIT(9)	/* Arbitration read out status */
-+#define D_CAN_IF3OBS_SM		BIT(8)	/* Mask bits read out status */
-+#define D_CAN_IF3OBS_DB		BIT(4)	/* Data B read observation */
-+#define D_CAN_IF3OBS_DA		BIT(3)	/* Data A read observation */
-+#define D_CAN_IF3OBS_CTL	BIT(2)	/* Control read observation */
-+#define D_CAN_IF3OBS_ARB	BIT(1)	/* Arbitration data read observation */
-+#define D_CAN_IF3OBS_MASK	BIT(0)	/* Mask data read observation */
-+
-+/* D_CAN TX I/O reg bit fields */
-+#define D_CAN_TIOC_PU		BIT(18)	/* CAN_TX pull up/down select */
-+#define D_CAN_TIOC_PD		BIT(17)	/* CAN_TX pull disable */
-+#define D_CAN_TIOC_OD		BIT(16)	/* CAN_TX open drain enable */
-+#define D_CAN_TIOC_FUNC		BIT(3)	/* CAN_TX function */
-+#define D_CAN_TIOC_DIR		BIT(2)	/* CAN_TX data direction */
-+#define D_CAN_TIOC_OUT		BIT(1)	/* CAN_TX data out write */
-+#define D_CAN_TIOC_IN		BIT(0)	/* CAN_TX data in */
-+
-+/* D_CAN RX I/O reg bit fields */
-+#define D_CAN_RIOC_PU		BIT(18)	/* CAN_RX pull up/down select */
-+#define D_CAN_RIOC_PD		BIT(17)	/* CAN_RX pull disable */
-+#define D_CAN_RIOC_OD		BIT(16)	/* CAN_RX open drain enable */
-+#define D_CAN_RIOC_FUNC		BIT(3)	/* CAN_RX function */
-+#define D_CAN_RIOC_DIR		BIT(2)	/* CAN_RX data direction */
-+#define D_CAN_RIOC_OUT		BIT(1)	/* CAN_RX data out write */
-+#define D_CAN_RTIOC_IN		BIT(0)	/* CAN_RX data in */
-+
-+#define D_CAN_SET_REG		0xFFFFFFFF
-+
-+#define D_CAN_CANMID_IDE	BIT(31)	/* Extended frame format */
-+#define D_CAN_CANMID_AME	BIT(30)	/* Acceptance mask enable */
-+#define D_CAN_CANMID_AAM	BIT(29)	/* Auto answer mode */
-+
-+/*
-+ * IF register masks:
-+ */
-+#define IFX_WRITE_IDR(x)		((x) & 0x1FFFFFFF)
-+
-+#define IFX_CMD_BITS(x)			((x) & 0xFFFFFF00)
-+#define IFX_CMD_MSG_NUMBER(x)		((x) & 0xFF)
-+
-+/* Message objects split */
-+#define D_CAN_NUM_MSG_OBJECTS		64
-+#define D_CAN_NUM_RX_MSG_OBJECTS	32
-+#define D_CAN_NUM_TX_MSG_OBJECTS	32
-+
-+#define D_CAN_MSG_OBJ_RX_FIRST		1
-+#define D_CAN_MSG_OBJ_RX_LAST		(D_CAN_MSG_OBJ_RX_FIRST + \
-+					D_CAN_NUM_RX_MSG_OBJECTS - 1)
-+
-+#define D_CAN_MSG_OBJ_TX_FIRST		(D_CAN_MSG_OBJ_RX_LAST + 1)
-+#define D_CAN_MSG_OBJ_TX_LAST		(D_CAN_MSG_OBJ_TX_FIRST + \
-+					D_CAN_NUM_TX_MSG_OBJECTS - 1)
-+
-+#define D_CAN_MSG_OBJ_RX_SPLIT		17
-+#define D_CAN_MSG_OBJ_RX_LOW_LAST	(D_CAN_MSG_OBJ_RX_SPLIT - 1)
-+
-+#define D_CAN_NEXT_MSG_OBJ_MASK		(D_CAN_NUM_TX_MSG_OBJECTS - 1)
-+
-+/* status interrupt */
-+#define STATUS_INTERRUPT		0x8000
-+
-+/* global interrupt masks */
-+#define ENABLE_ALL_INTERRUPTS		1
-+#define DISABLE_ALL_INTERRUPTS		0
-+
-+/* minimum timeout for checking BUSY status */
-+#define MIN_TIMEOUT_VALUE		6
-+
-+/* Wait for ~1 sec for INIT bit */
-+#define D_CAN_WAIT_COUNT		1000
-+
-+#define D_CAN_IF_RX_NUM			0
-+#define D_CAN_IF_TX_NUM			1
-+
-+#define D_CAN_GET_XREG_NUM(priv, reg)	(__ffs(d_can_read(priv, reg))/4)
-+
-+/* CAN Bittiming constants as per D_CAN specs */
-+static struct can_bittiming_const d_can_bittiming_const = {
-+	.name = D_CAN_DRV_NAME,
-+	.tseg1_min = 1,		/* Time segment 1 = prop_seg + phase_seg1 */
-+	.tseg1_max = 16,
-+	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
-+	.tseg2_max = 8,
-+	.sjw_max = 4,
-+	.brp_min = 1,
-+	.brp_max = 1024,	/* 6-bit BRP field + 4-bit BRPE field*/
-+	.brp_inc = 1,
-+};
-+
-+/* d_can last error code (lec) values */
-+enum d_can_lec_type {
-+	LEC_NO_ERROR = 0,
-+	LEC_STUFF_ERROR,
-+	LEC_FORM_ERROR,
-+	LEC_ACK_ERROR,
-+	LEC_BIT1_ERROR,
-+	LEC_BIT0_ERROR,
-+	LEC_CRC_ERROR,
-+	LEC_UNUSED,
-+};
-+
-+/*
-+ * d_can error types:
-+ * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
-+ */
-+enum d_can_bus_error_types {
-+	D_CAN_NO_ERROR = 0,
-+	D_CAN_BUS_OFF,
-+	D_CAN_ERROR_WARNING,
-+	D_CAN_ERROR_PASSIVE,
-+};
-+
-+static inline void d_can_write(struct d_can_priv *priv, u32 reg, u32 val)
-+{
-+	__raw_writel(val, priv->base + reg);
-+}
-+
-+static inline u32 d_can_read(struct d_can_priv *priv, int reg)
-+{
-+	return __raw_readl(priv->base + reg);
-+}
-+
-+static inline void d_can_set_bit(struct d_can_priv *priv, int reg,
-+	u32 bit_mask)
-+{
-+	d_can_write(priv, reg, d_can_read(priv, reg) | bit_mask);
-+}
-+
-+static inline u32 d_can_get_bit(struct d_can_priv *priv, int reg,
-+	u32 bit_mask)
-+{
-+	return (d_can_read(priv, reg) & bit_mask) ? 1 : 0;
-+}
-+
-+static inline void d_can_clear_bit(struct d_can_priv *priv, int reg,
-+	u32 bit_mask)
-+{
-+	d_can_write(priv, reg, d_can_read(priv, reg) & ~bit_mask);
-+}
-+
-+static inline int get_tx_next_msg_obj(const struct d_can_priv *priv)
-+{
-+	return (priv->tx_next & D_CAN_NEXT_MSG_OBJ_MASK) +
-+			D_CAN_MSG_OBJ_TX_FIRST;
-+}
-+
-+static inline int get_tx_echo_msg_obj(const struct d_can_priv *priv)
-+{
-+	return (priv->tx_echo & D_CAN_NEXT_MSG_OBJ_MASK) +
-+			D_CAN_MSG_OBJ_TX_FIRST;
-+}
-+
-+/*
-+ * API for enabling and disabling the multiple interrupts
-+ * of the DCAN module like error interrupt, status interrupt
-+ * error enable/disable for instance zero and one and etc.
-+ */
-+static void d_can_interrupts(struct d_can_priv *priv, int enable)
-+{
-+	unsigned int cntrl_save = d_can_read(priv, D_CAN_CTL);
-+
-+	if (enable)
-+		cntrl_save |= (D_CAN_CTL_IE1 | D_CAN_CTL_EIE |
-+				D_CAN_CTL_IE0);
-+	else
-+		cntrl_save &= ~(D_CAN_CTL_IE1 | D_CAN_CTL_SIE |
-+				D_CAN_CTL_EIE | D_CAN_CTL_IE0);
-+
-+	d_can_write(priv, D_CAN_CTL, cntrl_save);
-+}
-+
-+static inline int d_can_msg_obj_is_busy(struct d_can_priv *priv, int iface)
-+{
-+	int count = MIN_TIMEOUT_VALUE;
-+
-+	while (count && (d_can_read(priv, D_CAN_IFCMD(iface)) &
-+				D_CAN_IF_CMD_BUSY)) {
-+		count--;
-+		udelay(1);
-+	}
-+
-+	if (!count)
-+		return 1;
-+
-+	return 0;
-+}
-+
-+static inline void d_can_object_get(struct net_device *dev,
-+					int iface, int objno, int mask)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	d_can_write(priv, D_CAN_IFCMD(iface), IFX_CMD_BITS(mask) |
-+					IFX_CMD_MSG_NUMBER(objno));
-+
-+	/*
-+	 * As per specs, after writing the message object number in the
-+	 * IF command register the transfer b/w interface register and
-+	 * message RAM must be complete in 12 CAN-CLK period.
-+	 */
-+	if (d_can_msg_obj_is_busy(priv, iface))
-+		netdev_err(dev, "timed out in object get\n");
-+}
-+
-+static inline void d_can_object_put(struct net_device *dev,
-+					int iface, int objno, int mask)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	d_can_write(priv, D_CAN_IFCMD(iface), D_CAN_IF_CMD_WR |
-+		IFX_CMD_BITS(mask) | IFX_CMD_MSG_NUMBER(objno));
-+
-+	/*
-+	 * As per specs, after writing the message object number in the
-+	 * IF command register the transfer b/w interface register and
-+	 * message RAM must be complete in 12 CAN-CLK period.
-+	 */
-+	if (d_can_msg_obj_is_busy(priv, iface))
-+		netdev_err(dev, "timed out in object put\n");
-+}
-+
-+static void d_can_write_msg_object(struct net_device *dev,
-+			int iface, struct can_frame *frame, int objno)
-+{
-+	int i;
-+	unsigned int id;
-+	u32 dataA = 0;
-+	u32 dataB = 0;
-+	u32 flags = 0;
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	if (!(frame->can_id & CAN_RTR_FLAG))
-+		flags |= D_CAN_IF_ARB_DIR_XMIT;
-+
-+	if (frame->can_id & CAN_EFF_FLAG) {
-+		id = frame->can_id & CAN_EFF_MASK;
-+		flags |= D_CAN_IF_ARB_MSGXTD;
-+	} else
-+		id = ((frame->can_id & CAN_SFF_MASK) << 18);
-+
-+	flags |= D_CAN_IF_ARB_MSGVAL;
-+	d_can_write(priv, D_CAN_IFARB(iface), IFX_WRITE_IDR(id) | flags);
-+
-+	for (i = 0; i < frame->can_dlc; i++) {
-+		if (frame->can_dlc <= 4)
-+			dataA |= (frame->data[i] << (8 * i));
-+		else {
-+			if (i < 4)
-+				dataA |= (frame->data[i] << (8 * i));
-+			else
-+				dataB |= (frame->data[i] << (8 * (i - 4)));
-+		}
-+	}
-+
-+	/* DATA write to Message object registers DATAA and DATAB */
-+	if (frame->can_dlc <= 4)
-+		d_can_write(priv, D_CAN_IFDATA(iface), dataA);
-+	else {
-+		d_can_write(priv, D_CAN_IFDATB(iface), dataB);
-+		d_can_write(priv, D_CAN_IFDATA(iface), dataA);
-+	}
-+
-+	/* enable TX interrupt for this message object */
-+	d_can_write(priv, D_CAN_IFMCTL(iface),
-+			D_CAN_IF_MCTL_TXIE | D_CAN_IF_MCTL_EOB |
-+			D_CAN_IF_MCTL_TXRQST | D_CAN_IF_MCTL_NEWDAT |
-+			frame->can_dlc);
-+
-+	/* Put message data into message RAM */
-+	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_ALL);
-+}
-+
-+/*
-+ * Mark that this particular message object is received and clearing
-+ * the interrupt pending register value.
-+ */
-+static inline void d_can_mark_rx_msg_obj(struct net_device *dev,
-+				int iface, int ctrl_mask, int obj)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	d_can_write(priv, D_CAN_IFMCTL(iface), ctrl_mask
-+		& ~(D_CAN_IF_MCTL_MSGLST | D_CAN_IF_MCTL_INTPND));
-+
-+	d_can_object_put(dev, iface, obj, D_CAN_IF_CMD_CONTROL);
-+}
-+
-+static inline void d_can_activate_all_lower_rx_msg_objs(struct net_device *dev,
-+				int iface, int ctrl_mask)
-+{
-+	int i;
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	for (i = D_CAN_MSG_OBJ_RX_FIRST; i <= D_CAN_MSG_OBJ_RX_LOW_LAST; i++) {
-+		d_can_write(priv, D_CAN_IFMCTL(iface),
-+				ctrl_mask & ~(D_CAN_IF_MCTL_MSGLST |
-+				D_CAN_IF_MCTL_INTPND | D_CAN_IF_MCTL_NEWDAT));
-+		d_can_object_put(dev, iface, i, D_CAN_IF_CMD_CONTROL);
-+	}
-+}
-+
-+static inline void d_can_activate_rx_msg_obj(struct net_device *dev,
-+						int iface, int ctrl_mask,
-+						int obj)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	d_can_write(priv, D_CAN_IFMCTL(iface),
-+			ctrl_mask & ~(D_CAN_IF_MCTL_MSGLST |
-+			D_CAN_IF_MCTL_INTPND | D_CAN_IF_MCTL_NEWDAT));
-+	d_can_object_put(dev, iface, obj, D_CAN_IF_CMD_CONTROL);
-+}
-+
-+static void d_can_handle_lost_msg_obj(struct net_device *dev,
-+					int iface, int objno)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+	struct net_device_stats *stats = &dev->stats;
-+	struct sk_buff *skb;
-+	struct can_frame *frame;
-+
-+	netdev_err(dev, "msg lost in buffer %d\n", objno);
-+
-+	d_can_object_get(dev, iface, objno, D_CAN_IF_CMD_ALL &
-+					~D_CAN_IF_CMD_TXRQST);
-+
-+	d_can_write(priv, D_CAN_IFMCTL(iface), D_CAN_IF_MCTL_CLR_MSGLST);
-+
-+	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_CONTROL);
-+
-+	/* create an error msg */
-+	skb = alloc_can_err_skb(dev, &frame);
-+	if (unlikely(!skb))
-+		return;
-+
-+	frame->can_id |= CAN_ERR_CRTL;
-+	frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
-+	stats->rx_errors++;
-+	stats->rx_over_errors++;
-+
-+	netif_receive_skb(skb);
-+}
-+
-+static int d_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
-+{
-+	int i;
-+	u32 dataA = 0;
-+	u32 dataB = 0;
-+	unsigned int arb_val;
-+	unsigned int mctl_val;
-+	struct d_can_priv *priv = netdev_priv(dev);
-+	struct net_device_stats *stats = &dev->stats;
-+	struct sk_buff *skb;
-+	struct can_frame *frame;
-+
-+	skb = alloc_can_skb(dev, &frame);
-+	if (!skb) {
-+		stats->rx_dropped++;
-+		return -ENOMEM;
-+	}
-+
-+	frame->can_dlc = get_can_dlc(ctrl & 0x0F);
-+
-+	arb_val = d_can_read(priv, D_CAN_IFARB(iface));
-+	mctl_val = d_can_read(priv, D_CAN_IFMCTL(iface));
-+
-+	if (arb_val & D_CAN_IF_ARB_MSGXTD)
-+		frame->can_id = (arb_val & CAN_EFF_MASK) | CAN_EFF_FLAG;
-+	else
-+		frame->can_id = (arb_val >> 18) & CAN_SFF_MASK;
-+
-+	if (mctl_val & D_CAN_IF_MCTL_RMTEN)
-+		frame->can_id |= CAN_RTR_FLAG;
-+	else {
-+		dataA = d_can_read(priv, D_CAN_IFDATA(iface));
-+		dataB = d_can_read(priv, D_CAN_IFDATB(iface));
-+		for (i = 0; i < frame->can_dlc; i++) {
-+			/* Writing MO higher 4 data bytes to skb */
-+			if (frame->can_dlc <= 4)
-+				frame->data[i] = dataA >> (8 * i);
-+			else {
-+				if (i < 4)
-+					frame->data[i] = dataA >> (8 * i);
-+				else
-+					frame->data[i] = dataB >> (8 * (i-4));
-+			}
-+		}
-+	}
-+
-+	netif_receive_skb(skb);
-+
-+	stats->rx_packets++;
-+	stats->rx_bytes += frame->can_dlc;
-+
-+	return 0;
-+}
-+
-+static void d_can_setup_receive_object(struct net_device *dev, int iface,
-+					int objno, unsigned int mask,
-+					unsigned int id, unsigned int mcont)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	d_can_write(priv, D_CAN_IFMSK(iface), IFX_WRITE_IDR(mask));
-+	d_can_write(priv, D_CAN_IFARB(iface), IFX_WRITE_IDR(id) |
-+			D_CAN_IF_ARB_MSGVAL);
-+	d_can_write(priv, D_CAN_IFMCTL(iface), mcont);
-+
-+	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_ALL &
-+					~D_CAN_IF_CMD_TXRQST);
-+
-+	netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, d_can_read(priv,
-+		D_CAN_MSGVAL(D_CAN_GET_XREG_NUM(priv, D_CAN_MSGVAL_X))));
-+}
-+
-+static void d_can_inval_msg_object(struct net_device *dev, int iface, int objno)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	d_can_write(priv, D_CAN_IFARB(iface), 0);
-+	d_can_write(priv, D_CAN_IFMCTL(iface), 0);
-+
-+	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_ARB |
-+					D_CAN_IF_CMD_CONTROL);
-+
-+	netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, d_can_read(priv,
-+		D_CAN_MSGVAL(D_CAN_GET_XREG_NUM(priv, D_CAN_MSGVAL_X))));
-+}
-+
-+static inline int d_can_is_next_tx_obj_busy(struct d_can_priv *priv, int objno)
-+{
-+	u32 txrq_x_reg_val = D_CAN_GET_XREG_NUM(priv, D_CAN_TXRQ_X);
-+
-+	/*
-+	 * as transmission request register's bit n-1 corresponds to
-+	 * message object n, we need to handle the same properly.
-+	 */
-+	if (d_can_read(priv, D_CAN_TXRQ(txrq_x_reg_val)) &
-+			(1 << (objno - D_CAN_MSG_OBJ_TX_FIRST)))
-+		return 1;
-+
-+	return 0;
-+}
-+
-+static netdev_tx_t d_can_start_xmit(struct sk_buff *skb,
-+					struct net_device *dev)
-+{
-+	u32 msg_obj_no;
-+	struct d_can_priv *priv = netdev_priv(dev);
-+	struct can_frame *frame = (struct can_frame *)skb->data;
-+
-+	if (can_dropped_invalid_skb(dev, skb))
-+		return NETDEV_TX_OK;
-+
-+	msg_obj_no = get_tx_next_msg_obj(priv);
-+
-+	/* prepare message object for transmission */
-+	d_can_write_msg_object(dev, D_CAN_IF_TX_NUM, frame, msg_obj_no);
-+	can_put_echo_skb(skb, dev, msg_obj_no - D_CAN_MSG_OBJ_TX_FIRST);
-+
-+	/*
-+	 * we have to stop the queue in case of a wrap around or
-+	 * if the next TX message object is still in use
-+	 */
-+	priv->tx_next++;
-+	if (d_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
-+		((priv->tx_next & D_CAN_NEXT_MSG_OBJ_MASK) == 0))
-+		netif_stop_queue(dev);
-+
-+	return NETDEV_TX_OK;
-+}
-+
-+static int d_can_set_bittiming(struct net_device *dev)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+	const struct can_bittiming *bt = &priv->can.bittiming;
-+	u32 can_btc;
-+
-+	can_btc = ((bt->phase_seg2 - 1) & 0x7) << D_CAN_BTR_TSEG2_SHIFT;
-+	can_btc |= ((bt->phase_seg1 + bt->prop_seg - 1)
-+			& 0xF) << D_CAN_BTR_TSEG1_SHIFT;
-+
-+	can_btc |= ((bt->sjw - 1) & 0x3) << D_CAN_BTR_SJW_SHIFT;
-+
-+	/* Ten bits contains the BRP, 6 bits for BRP and upper 4 bits for brpe*/
-+	can_btc |= ((bt->brp - 1) & 0x3F) << D_CAN_BTR_BRP_SHIFT;
-+	can_btc |= ((((bt->brp - 1) >> 6) & 0xF) << D_CAN_BTR_BRPE_SHIFT);
-+
-+	d_can_write(priv, D_CAN_BTR, can_btc);
-+
-+	netdev_info(dev, "setting CAN BT = %#x\n", can_btc);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Configure D_CAN message objects for Tx and Rx purposes:
-+ * D_CAN provides a total of 64 message objects that can be configured
-+ * either for Tx or Rx purposes. In this driver first 32 message objects
-+ * are used as a reception FIFO and the reception FIFO is signified by the
-+ * EoB bit being SET. The remaining 32 message objects are kept aside for
-+ * Tx purposes. See user guide document for further details on configuring
-+ * message objects.
-+ */
-+static void d_can_configure_msg_objects(struct net_device *dev)
-+{
-+	unsigned int i;
-+
-+	/* first invalidate all message objects */
-+	for (i = D_CAN_MSG_OBJ_RX_FIRST; i <= D_CAN_NUM_MSG_OBJECTS; i++)
-+		d_can_inval_msg_object(dev, D_CAN_IF_RX_NUM, i);
-+
-+	/* setup receive message objects */
-+	for (i = D_CAN_MSG_OBJ_RX_FIRST; i < D_CAN_MSG_OBJ_RX_LAST; i++)
-+		d_can_setup_receive_object(dev, D_CAN_IF_RX_NUM, i, 0, 0,
-+			(D_CAN_IF_MCTL_RXIE | D_CAN_IF_MCTL_UMASK) &
-+			~D_CAN_IF_MCTL_EOB);
-+
-+	/* Last object EoB bit should be 1 for terminate */
-+	d_can_setup_receive_object(dev, D_CAN_IF_RX_NUM, D_CAN_MSG_OBJ_RX_LAST,
-+			0, 0, D_CAN_IF_MCTL_RXIE | D_CAN_IF_MCTL_UMASK |
-+			D_CAN_IF_MCTL_EOB);
-+}
-+
-+static void d_can_test_mode(struct net_device *dev)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	/* Test mode is enabled in this step & the specific TEST bits
-+	 * are enabled accordingly */
-+	d_can_write(priv, D_CAN_CTL, D_CAN_CTL_EIE |
-+			D_CAN_CTL_IE1 |	D_CAN_CTL_IE0 | D_CAN_CTL_TEST);
-+
-+	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
-+		/* silent mode : bus-monitoring mode */
-+		d_can_write(priv, D_CAN_TEST, D_CAN_TEST_SILENT);
-+	} else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
-+		/* loopback mode : useful for self-test function */
-+		d_can_write(priv, D_CAN_TEST, D_CAN_TEST_LBACK);
-+	} else {
-+		/* loopback + silent mode : useful for hot self-test */
-+		d_can_write(priv, D_CAN_TEST, D_CAN_TEST_LBACK |
-+				D_CAN_TEST_SILENT);
-+	}
-+}
-+
-+/*
-+ * Configure D_CAN chip:
-+ * - enable/disable auto-retransmission
-+ * - set operating mode
-+ * - configure message objects
-+ */
-+static void d_can_init(struct net_device *dev)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+	u32 cnt;
-+
-+	netdev_dbg(dev, "resetting d_can ...\n");
-+	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_SWR);
-+
-+	/* Enter initialization mode by setting the Init bit */
-+	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT);
-+
-+	/* enable automatic retransmission */
-+	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_ENABLE_AR);
-+
-+	/* Set the Configure Change Enable ( CCE) bit */
-+	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_CCE);
-+
-+	/* Wait for the Init bit to get set */
-+	cnt = D_CAN_WAIT_COUNT;
-+	while (!d_can_get_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT) && cnt != 0) {
-+		--cnt;
-+		udelay(10);
-+	}
-+
-+	/* set bittiming params */
-+	d_can_set_bittiming(dev);
-+
-+	d_can_clear_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT | D_CAN_CTL_CCE);
-+
-+	/* Wait for the Init bit to get clear */
-+	cnt = D_CAN_WAIT_COUNT;
-+	while (d_can_get_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT) && cnt != 0) {
-+		--cnt;
-+		udelay(10);
-+	}
-+
-+	if (priv->can.ctrlmode & (CAN_CTRLMODE_LOOPBACK |
-+				CAN_CTRLMODE_LISTENONLY))
-+		d_can_test_mode(dev);
-+	else
-+		/* normal mode*/
-+		d_can_write(priv, D_CAN_CTL, D_CAN_CTL_EIE | D_CAN_CTL_IE1 |
-+							D_CAN_CTL_IE0);
-+
-+	/* Enable TX and RX I/O Control pins */
-+	d_can_write(priv, D_CAN_TIOC, D_CAN_TIOC_FUNC);
-+	d_can_write(priv, D_CAN_RIOC, D_CAN_RIOC_FUNC);
-+
-+	/* configure message objects */
-+	d_can_configure_msg_objects(dev);
-+
-+	/* set a LEC value so that we can check for updates later */
-+	d_can_write(priv, D_CAN_ES, LEC_UNUSED);
-+}
-+
-+static void d_can_start(struct net_device *dev)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	/* basic d_can initialization */
-+	d_can_init(dev);
-+
-+	priv->can.state = CAN_STATE_ERROR_ACTIVE;
-+
-+	/* reset tx helper pointers */
-+	priv->tx_next = priv->tx_echo = 0;
-+
-+	/* enable status change, error and module interrupts */
-+	d_can_interrupts(priv, ENABLE_ALL_INTERRUPTS);
-+}
-+
-+static void d_can_stop(struct net_device *dev)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	/* disable all interrupts */
-+	d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
-+
-+	/* set the state as STOPPED */
-+	priv->can.state = CAN_STATE_STOPPED;
-+}
-+
-+static int d_can_set_mode(struct net_device *dev, enum can_mode mode)
-+{
-+	switch (mode) {
-+	case CAN_MODE_START:
-+		d_can_start(dev);
-+		netif_wake_queue(dev);
-+		break;
-+	default:
-+		return -EOPNOTSUPP;
-+	}
-+
-+	return 0;
-+}
-+
-+static int d_can_get_berr_counter(const struct net_device *dev,
-+					struct can_berr_counter *bec)
-+{
-+	unsigned int reg_err_counter;
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	reg_err_counter = d_can_read(priv, D_CAN_ERRC);
-+	bec->rxerr = (reg_err_counter & D_CAN_ERRC_REC_MASK) >>
-+				D_CAN_ERRC_REC_SHIFT;
-+	bec->txerr = reg_err_counter & D_CAN_ERRC_TEC_MASK;
-+
-+	return 0;
-+}
-+
-+/*
-+ * theory of operation:
-+ *
-+ * priv->tx_echo holds the number of the oldest can_frame put for
-+ * transmission into the hardware, but not yet ACKed by the CAN tx
-+ * complete IRQ.
-+ *
-+ * We iterate from priv->tx_echo to priv->tx_next and check if the
-+ * packet has been transmitted, echo it back to the CAN framework.
-+ * If we discover a not yet transmitted package, stop looking for more.
-+ */
-+static void d_can_do_tx(struct net_device *dev)
-+{
-+	u32 msg_obj_no;
-+	struct d_can_priv *priv = netdev_priv(dev);
-+	struct net_device_stats *stats = &dev->stats;
-+	u32 txrq_x_reg_val;
-+	u32 txrq_reg_val;
-+
-+	for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
-+		msg_obj_no = get_tx_echo_msg_obj(priv);
-+		txrq_x_reg_val = D_CAN_GET_XREG_NUM(priv, D_CAN_TXRQ_X);
-+		txrq_reg_val = d_can_read(priv, D_CAN_TXRQ(txrq_x_reg_val));
-+		if (!(txrq_reg_val & (1 << (msg_obj_no -
-+						D_CAN_MSG_OBJ_TX_FIRST)))) {
-+			can_get_echo_skb(dev,
-+					msg_obj_no - D_CAN_MSG_OBJ_TX_FIRST);
-+			stats->tx_bytes += d_can_read(priv,
-+					D_CAN_IFMCTL(D_CAN_IF_TX_NUM))
-+					& D_CAN_IF_MCTL_DLC_MASK;
-+			stats->tx_packets++;
-+			d_can_inval_msg_object(dev, D_CAN_IF_TX_NUM,
-+					msg_obj_no);
-+		} else
-+			break;
-+	}
-+
-+	/* restart queue if wrap-up or if queue stalled on last pkt */
-+	if (((priv->tx_next & D_CAN_NEXT_MSG_OBJ_MASK) != 0)
-+		|| ((priv->tx_echo & D_CAN_NEXT_MSG_OBJ_MASK) == 0))
-+		netif_wake_queue(dev);
-+}
-+
-+/*
-+ * theory of operation:
-+ *
-+ * d_can core saves a received CAN message into the first free message
-+ * object it finds free (starting with the lowest). Bits NEWDAT and
-+ * INTPND are set for this message object indicating that a new message
-+ * has arrived. To work-around this issue, we keep two groups of message
-+ * objects whose partitioning is defined by D_CAN_MSG_OBJ_RX_SPLIT.
-+ *
-+ * To ensure in-order frame reception we use the following
-+ * approach while re-activating a message object to receive further
-+ * frames:
-+ * - if the current message object number is lower than
-+ *   D_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
-+ *   the INTPND bit.
-+ * - if the current message object number is equal to
-+ *   D_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
-+ *   receive message objects.
-+ * - if the current message object number is greater than
-+ *   D_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
-+ *   only this message object.
-+ */
-+static int d_can_do_rx_poll(struct net_device *dev, int quota)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+	unsigned int msg_obj, mctrl_reg_val;
-+	u32 num_rx_pkts = 0;
-+	u32 intpnd_x_reg_val;
-+	u32 intpnd_reg_val;
-+
-+	for (msg_obj = D_CAN_MSG_OBJ_RX_FIRST; msg_obj <= D_CAN_MSG_OBJ_RX_LAST
-+				&& quota > 0; msg_obj++) {
-+
-+		intpnd_x_reg_val = D_CAN_GET_XREG_NUM(priv, D_CAN_INTPND_X);
-+		intpnd_reg_val = d_can_read(priv,
-+					D_CAN_INTPND(intpnd_x_reg_val));
-+
-+		/*
-+		 * as interrupt pending register's bit n-1 corresponds to
-+		 * message object n, we need to handle the same properly.
-+		 */
-+		if (intpnd_reg_val & (1 << (msg_obj - 1))) {
-+
-+			d_can_object_get(dev, D_CAN_IF_RX_NUM, msg_obj,
-+					D_CAN_IF_CMD_ALL &
-+					~D_CAN_IF_CMD_TXRQST);
-+
-+			mctrl_reg_val = d_can_read(priv,
-+					D_CAN_IFMCTL(D_CAN_IF_RX_NUM));
-+
-+			if (!(mctrl_reg_val & D_CAN_IF_MCTL_NEWDAT))
-+				continue;
-+
-+			/* read the data from the message object */
-+			d_can_read_msg_object(dev, D_CAN_IF_RX_NUM,
-+						mctrl_reg_val);
-+
-+			if (mctrl_reg_val & D_CAN_IF_MCTL_EOB)
-+				d_can_setup_receive_object(dev, D_CAN_IF_RX_NUM,
-+					D_CAN_MSG_OBJ_RX_LAST, 0, 0,
-+					D_CAN_IF_MCTL_RXIE | D_CAN_IF_MCTL_UMASK
-+					| D_CAN_IF_MCTL_EOB);
-+
-+			if (mctrl_reg_val & D_CAN_IF_MCTL_MSGLST) {
-+				d_can_handle_lost_msg_obj(dev, D_CAN_IF_RX_NUM,
-+					msg_obj);
-+				num_rx_pkts++;
-+				quota--;
-+				continue;
-+			}
-+
-+			if (msg_obj < D_CAN_MSG_OBJ_RX_LOW_LAST)
-+				d_can_mark_rx_msg_obj(dev, D_CAN_IF_RX_NUM,
-+						mctrl_reg_val, msg_obj);
-+			else if (msg_obj > D_CAN_MSG_OBJ_RX_LOW_LAST)
-+				/* activate this msg obj */
-+				d_can_activate_rx_msg_obj(dev, D_CAN_IF_RX_NUM,
-+						mctrl_reg_val, msg_obj);
-+			else if (msg_obj == D_CAN_MSG_OBJ_RX_LOW_LAST)
-+				/* activate all lower message objects */
-+				d_can_activate_all_lower_rx_msg_objs(dev,
-+						D_CAN_IF_RX_NUM, mctrl_reg_val);
-+
-+			num_rx_pkts++;
-+			quota--;
-+		}
-+	}
-+
-+	return num_rx_pkts;
-+}
-+
-+static inline int d_can_has_handle_berr(struct d_can_priv *priv)
-+{
-+	return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
-+		(priv->current_status & LEC_UNUSED);
-+}
-+
-+static int d_can_handle_state_change(struct net_device *dev,
-+				enum d_can_bus_error_types error_type)
-+{
-+	unsigned int reg_err_counter;
-+	unsigned int rx_err_passive;
-+	struct d_can_priv *priv = netdev_priv(dev);
-+	struct net_device_stats *stats = &dev->stats;
-+	struct can_frame *cf;
-+	struct sk_buff *skb;
-+	struct can_berr_counter bec;
-+
-+	/* propagate the error condition to the CAN stack */
-+	skb = alloc_can_err_skb(dev, &cf);
-+	if (unlikely(!skb))
-+		return 0;
-+
-+	d_can_get_berr_counter(dev, &bec);
-+	reg_err_counter = d_can_read(priv, D_CAN_ERRC);
-+	rx_err_passive = (reg_err_counter & D_CAN_ERRC_RP_MASK) >>
-+				D_CAN_ERRC_RP_SHIFT;
-+
-+	switch (error_type) {
-+	case D_CAN_ERROR_WARNING:
-+		/* error warning state */
-+		priv->can.can_stats.error_warning++;
-+		priv->can.state = CAN_STATE_ERROR_WARNING;
-+		cf->can_id |= CAN_ERR_CRTL;
-+		cf->data[1] = (bec.txerr > bec.rxerr) ?
-+			CAN_ERR_CRTL_TX_WARNING :
-+			CAN_ERR_CRTL_RX_WARNING;
-+		cf->data[6] = bec.txerr;
-+		cf->data[7] = bec.rxerr;
-+
-+		break;
-+	case D_CAN_ERROR_PASSIVE:
-+		/* error passive state */
-+		priv->can.can_stats.error_passive++;
-+		priv->can.state = CAN_STATE_ERROR_PASSIVE;
-+		cf->can_id |= CAN_ERR_CRTL;
-+		if (rx_err_passive)
-+			cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
-+		if (bec.txerr > 127)
-+			cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
-+
-+		cf->data[6] = bec.txerr;
-+		cf->data[7] = bec.rxerr;
-+		break;
-+	case D_CAN_BUS_OFF:
-+		/* bus-off state */
-+		priv->can.state = CAN_STATE_BUS_OFF;
-+		cf->can_id |= CAN_ERR_BUSOFF;
-+		/*
-+		 * disable all interrupts in bus-off mode to ensure that
-+		 * the CPU is not hogged down
-+		 */
-+		d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
-+		can_bus_off(dev);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	netif_receive_skb(skb);
-+	stats->rx_packets++;
-+	stats->rx_bytes += cf->can_dlc;
-+
-+	return 1;
-+}
-+
-+static int d_can_handle_bus_err(struct net_device *dev,
-+				enum d_can_lec_type lec_type)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+	struct net_device_stats *stats = &dev->stats;
-+	struct can_frame *cf;
-+	struct sk_buff *skb;
-+
-+	/*
-+	 * early exit if no lec update or no error.
-+	 * no lec update means that no CAN bus event has been detected
-+	 * since CPU wrote 0x7 value to status reg.
-+	 */
-+	if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
-+		return 0;
-+
-+	/* propagate the error condition to the CAN stack */
-+	skb = alloc_can_err_skb(dev, &cf);
-+	if (unlikely(!skb))
-+		return 0;
-+
-+	/*
-+	 * check for 'last error code' which tells us the
-+	 * type of the last error to occur on the CAN bus
-+	 */
-+
-+	/* common for all type of bus errors */
-+	priv->can.can_stats.bus_error++;
-+	stats->rx_errors++;
-+	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
-+	cf->data[2] |= CAN_ERR_PROT_UNSPEC;
-+
-+	switch (lec_type) {
-+	case LEC_STUFF_ERROR:
-+		netdev_dbg(dev, "stuff error\n");
-+		cf->data[2] |= CAN_ERR_PROT_STUFF;
-+		break;
-+	case LEC_FORM_ERROR:
-+		netdev_dbg(dev, "form error\n");
-+		cf->data[2] |= CAN_ERR_PROT_FORM;
-+		break;
-+	case LEC_ACK_ERROR:
-+		netdev_dbg(dev, "ack error\n");
-+		cf->data[2] |= (CAN_ERR_PROT_LOC_ACK |
-+				CAN_ERR_PROT_LOC_ACK_DEL);
-+		break;
-+	case LEC_BIT1_ERROR:
-+		netdev_dbg(dev, "bit1 error\n");
-+		cf->data[2] |= CAN_ERR_PROT_BIT1;
-+		break;
-+	case LEC_BIT0_ERROR:
-+		netdev_dbg(dev, "bit0 error\n");
-+		cf->data[2] |= CAN_ERR_PROT_BIT0;
-+		break;
-+	case LEC_CRC_ERROR:
-+		netdev_dbg(dev, "CRC error\n");
-+		cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
-+				CAN_ERR_PROT_LOC_CRC_DEL);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	/* set a LEC value so that we can check for updates later */
-+	d_can_write(priv, D_CAN_ES, LEC_UNUSED);
-+
-+	netif_receive_skb(skb);
-+	stats->rx_packets++;
-+	stats->rx_bytes += cf->can_dlc;
-+
-+	return 1;
-+}
-+
-+static int d_can_poll(struct napi_struct *napi, int quota)
-+{
-+	int lec_type = 0;
-+	int work_done = 0;
-+	struct net_device *dev = napi->dev;
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	if (!priv->irqstatus)
-+		goto end;
-+
-+	/* status events have the highest priority */
-+	if (priv->irqstatus == STATUS_INTERRUPT) {
-+		priv->current_status = d_can_read(priv, D_CAN_ES);
-+
-+		/* handle Tx/Rx events */
-+		if (priv->current_status & D_CAN_ES_TXOK)
-+			d_can_write(priv, D_CAN_ES,
-+					priv->current_status & ~D_CAN_ES_TXOK);
-+
-+		if (priv->current_status & D_CAN_ES_RXOK)
-+			d_can_write(priv, D_CAN_ES,
-+					priv->current_status & ~D_CAN_ES_RXOK);
-+
-+		/* handle state changes */
-+		if ((priv->current_status & D_CAN_ES_EWARN) &&
-+				(!(priv->last_status & D_CAN_ES_EWARN))) {
-+			netdev_dbg(dev, "entered error warning state\n");
-+			work_done += d_can_handle_state_change(dev,
-+						D_CAN_ERROR_WARNING);
-+		}
-+		if ((priv->current_status & D_CAN_ES_EPASS) &&
-+				(!(priv->last_status & D_CAN_ES_EPASS))) {
-+			netdev_dbg(dev, "entered error passive state\n");
-+			work_done += d_can_handle_state_change(dev,
-+						D_CAN_ERROR_PASSIVE);
-+		}
-+		if ((priv->current_status & D_CAN_ES_BOFF) &&
-+				(!(priv->last_status & D_CAN_ES_BOFF))) {
-+			netdev_dbg(dev, "entered bus off state\n");
-+			work_done += d_can_handle_state_change(dev,
-+						D_CAN_BUS_OFF);
-+		}
-+
-+		/* handle bus recovery events */
-+		if ((!(priv->current_status & D_CAN_ES_BOFF)) &&
-+				(priv->last_status & D_CAN_ES_BOFF)) {
-+			netdev_dbg(dev, "left bus off state\n");
-+			priv->can.state = CAN_STATE_ERROR_ACTIVE;
-+		}
-+		if ((!(priv->current_status & D_CAN_ES_EPASS)) &&
-+				(priv->last_status & D_CAN_ES_EPASS)) {
-+			netdev_dbg(dev, "left error passive state\n");
-+			priv->can.state = CAN_STATE_ERROR_ACTIVE;
-+		}
-+
-+		priv->last_status = priv->current_status;
-+
-+		/* handle lec errors on the bus */
-+		lec_type = d_can_has_handle_berr(priv);
-+		if (lec_type)
-+			work_done += d_can_handle_bus_err(dev, lec_type);
-+	} else if ((priv->irqstatus >= D_CAN_MSG_OBJ_RX_FIRST) &&
-+			(priv->irqstatus <= D_CAN_MSG_OBJ_RX_LAST)) {
-+		/* handle events corresponding to receive message objects */
-+		work_done += d_can_do_rx_poll(dev, (quota - work_done));
-+	} else if ((priv->irqstatus >= D_CAN_MSG_OBJ_TX_FIRST) &&
-+			(priv->irqstatus <= D_CAN_MSG_OBJ_TX_LAST)) {
-+		/* handle events corresponding to transmit message objects */
-+		d_can_do_tx(dev);
-+	}
-+
-+end:
-+	if (work_done < quota) {
-+		napi_complete(napi);
-+		/* enable all IRQs */
-+		d_can_interrupts(priv, ENABLE_ALL_INTERRUPTS);
-+	}
-+
-+	return work_done;
-+}
-+
-+static irqreturn_t d_can_isr(int irq, void *dev_id)
-+{
-+	struct net_device *dev = (struct net_device *)dev_id;
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	priv->irqstatus = d_can_read(priv, D_CAN_INT);
-+	if (!priv->irqstatus)
-+		return IRQ_NONE;
-+
-+	/* disable all interrupts and schedule the NAPI */
-+	d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
-+	napi_schedule(&priv->napi);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int d_can_open(struct net_device *ndev)
-+{
-+	int err;
-+	struct d_can_priv *priv = netdev_priv(ndev);
-+
-+	/* Open common can device */
-+	err = open_candev(ndev);
-+	if (err) {
-+		netdev_err(ndev, "open_candev() failed %d\n", err);
-+		return err;
-+	}
-+
-+	/* register interrupt handler for Message Object (MO)
-+	 * and Error + status change (ES) */
-+	err = request_irq(ndev->irq, &d_can_isr, IRQF_SHARED, ndev->name,
-+				ndev);
-+	if (err) {
-+		netdev_err(ndev, "failed to request MO_ES interrupt\n");
-+		goto exit_close_candev;
-+	}
-+
-+	/* register interrupt handler for only Message Object */
-+	err = request_irq(priv->irq_obj, &d_can_isr, IRQF_SHARED, ndev->name,
-+				ndev);
-+	if (err) {
-+		netdev_err(ndev, "failed to request MO interrupt\n");
-+		goto exit_free_irq;
-+	}
-+
-+	/* start the d_can controller */
-+	d_can_start(ndev);
-+
-+	napi_enable(&priv->napi);
-+	netif_start_queue(ndev);
-+
-+	priv->opened = true;
-+	return 0;
-+exit_free_irq:
-+	free_irq(ndev->irq, ndev);
-+exit_close_candev:
-+	close_candev(ndev);
-+
-+	return err;
-+}
-+
-+static int d_can_close(struct net_device *ndev)
-+{
-+	struct d_can_priv *priv = netdev_priv(ndev);
-+
-+	netif_stop_queue(ndev);
-+	napi_disable(&priv->napi);
-+	d_can_stop(ndev);
-+	free_irq(ndev->irq, ndev);
-+	free_irq(priv->irq_obj, ndev);
-+	close_candev(ndev);
-+	priv->opened = false;
-+
-+	return 0;
-+}
-+
-+void d_can_reset_ram(struct d_can_priv *d_can, unsigned int instance,
-+					unsigned int enable)
-+{
-+	if (d_can->ram_init)
-+		d_can->ram_init(instance, enable);
-+
-+	/* Give some time delay for DCAN RAM initialization */
-+	udelay(1);
-+}
-+EXPORT_SYMBOL_GPL(d_can_reset_ram);
-+
-+struct net_device *alloc_d_can_dev(int num_objs)
-+{
-+	struct net_device *dev;
-+	struct d_can_priv *priv;
-+
-+	dev = alloc_candev(sizeof(struct d_can_priv), num_objs/2);
-+	if (!dev)
-+		return NULL;
-+
-+	priv = netdev_priv(dev);
-+	netif_napi_add(dev, &priv->napi, d_can_poll, num_objs/2);
-+
-+	priv->dev = dev;
-+	priv->can.bittiming_const = &d_can_bittiming_const;
-+	priv->can.do_set_mode = d_can_set_mode;
-+	priv->can.do_get_berr_counter = d_can_get_berr_counter;
-+	priv->can.ctrlmode_supported = (CAN_CTRLMODE_LOOPBACK |
-+					CAN_CTRLMODE_LISTENONLY |
-+					CAN_CTRLMODE_BERR_REPORTING |
-+					CAN_CTRLMODE_3_SAMPLES);
-+
-+	return dev;
-+}
-+EXPORT_SYMBOL_GPL(alloc_d_can_dev);
-+
-+#ifdef CONFIG_PM
-+int d_can_power_down(struct d_can_priv *d_can)
-+{
-+	unsigned long time_out;
-+	struct net_device *ndev = platform_get_drvdata(d_can->pdev);
-+
-+	d_can_set_bit(d_can, D_CAN_CTL, D_CAN_CTL_PDR);
-+
-+	/* Wait for the PDA bit to get set */
-+	time_out = jiffies + msecs_to_jiffies(D_CAN_WAIT_COUNT);
-+	while (!d_can_get_bit(d_can, D_CAN_ES, D_CAN_ES_PDA) &&
-+				time_after(time_out, jiffies))
-+		cpu_relax();
-+
-+	if (time_after(jiffies, time_out))
-+		return -ETIMEDOUT;
-+
-+	if (d_can->opened)
-+		d_can_stop(ndev);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(d_can_power_down);
-+
-+int d_can_power_up(struct d_can_priv *d_can)
-+{
-+	unsigned long time_out;
-+	struct net_device *ndev = platform_get_drvdata(d_can->pdev);
-+
-+	d_can_clear_bit(d_can, D_CAN_CTL, D_CAN_CTL_PDR);
-+	d_can_clear_bit(d_can, D_CAN_CTL, D_CAN_CTL_INIT);
-+
-+	/* Wait for the PDA bit to get clear */
-+	time_out = jiffies + msecs_to_jiffies(D_CAN_WAIT_COUNT);
-+	while (d_can_get_bit(d_can, D_CAN_ES, D_CAN_ES_PDA) &&
-+				time_after(time_out, jiffies))
-+		cpu_relax();
-+
-+	if (time_after(jiffies, time_out))
-+		return -ETIMEDOUT;
-+
-+	if (d_can->opened)
-+		d_can_start(ndev);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(d_can_power_up);
-+#else
-+#define d_can_power_down NULL
-+#define d_can_power_up NULL
-+#endif
-+
-+void free_d_can_dev(struct net_device *dev)
-+{
-+	free_candev(dev);
-+}
-+EXPORT_SYMBOL_GPL(free_d_can_dev);
-+
-+static const struct net_device_ops d_can_netdev_ops = {
-+	.ndo_open = d_can_open,
-+	.ndo_stop = d_can_close,
-+	.ndo_start_xmit = d_can_start_xmit,
-+};
-+
-+int register_d_can_dev(struct net_device *dev)
-+{
-+	/* we support local echo */
-+	dev->flags |= IFF_ECHO;
-+	dev->netdev_ops = &d_can_netdev_ops;
-+
-+	return register_candev(dev);
-+}
-+EXPORT_SYMBOL_GPL(register_d_can_dev);
-+
-+void unregister_d_can_dev(struct net_device *dev)
-+{
-+	struct d_can_priv *priv = netdev_priv(dev);
-+
-+	/* disable all interrupts */
-+	d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
-+
-+	unregister_candev(dev);
-+}
-+EXPORT_SYMBOL_GPL(unregister_d_can_dev);
-+
-+MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_VERSION(D_CAN_VERSION);
-+MODULE_DESCRIPTION(D_CAN_DRV_DESC);
-diff --git a/drivers/net/can/d_can/d_can.h b/drivers/net/can/d_can/d_can.h
-new file mode 100644
-index 0000000..5013421
---- /dev/null
-+++ b/drivers/net/can/d_can/d_can.h
-@@ -0,0 +1,72 @@
-+/*
-+ * CAN bus driver for Bosch D_CAN controller
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * Borrowed from C_CAN driver
-+ * Copyright (C) 2010 ST Microelectronics
-+ * - Bhupesh Sharma <bhupesh.sharma@st.com>
-+ *
-+ * Borrowed heavily from the C_CAN driver originally written by:
-+ * Copyright (C) 2007
-+ * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
-+ * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
-+ *
-+ * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
-+ * Bosch D_CAN user manual can be obtained from:
-+ * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
-+ * d_can_users_manual_111.pdf
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef D_CAN_H
-+#define D_CAN_H
-+
-+#define D_CAN_DRV_NAME	"d_can"
-+#define D_CAN_VERSION	"1.0"
-+#define D_CAN_DRV_DESC	"CAN bus driver for Bosch D_CAN controller " \
-+			D_CAN_VERSION
-+
-+/* d_can private data structure */
-+struct d_can_priv {
-+	struct can_priv can;	/* must be the first member */
-+	struct napi_struct napi;
-+	struct net_device *dev;
-+	struct platform_device *pdev;
-+	int current_status;
-+	int last_status;
-+	unsigned int irqstatus;
-+	void __iomem *base;
-+	u32 napi_weight;
-+	struct clk *fck;
-+	struct clk *ick;
-+	unsigned int irq;	/* device IRQ number, for all MO and ES	*/
-+	unsigned int irq_obj;	/* device IRQ number for only Msg Object */
-+	unsigned int irq_parity; /* device IRQ number for parity error */
-+	unsigned long irq_flags; /* for request_irq() */
-+	unsigned int tx_next;
-+	unsigned int tx_echo;
-+	unsigned int rx_next;
-+	bool opened;
-+	void *priv;		/* for board-specific data */
-+	void (*ram_init) (unsigned int, unsigned int);
-+};
-+
-+struct net_device *alloc_d_can_dev(int);
-+void free_d_can_dev(struct net_device *dev);
-+int d_can_power_up(struct d_can_priv *d_can);
-+int d_can_power_down(struct d_can_priv *d_can);
-+int register_d_can_dev(struct net_device *dev);
-+void unregister_d_can_dev(struct net_device *dev);
-+void d_can_reset_ram(struct d_can_priv *d_can, unsigned int instance,
-+					unsigned int enable);
-+
-+#endif /* D_CAN_H */
-diff --git a/drivers/net/can/d_can/d_can_platform.c b/drivers/net/can/d_can/d_can_platform.c
-new file mode 100644
-index 0000000..7b8a62c
---- /dev/null
-+++ b/drivers/net/can/d_can/d_can_platform.c
-@@ -0,0 +1,288 @@
-+/*
-+ * Platform CAN bus driver for Bosch D_CAN controller
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * Borrowed from C_CAN driver
-+ * Copyright (C) 2010 ST Microelectronics
-+ * - Bhupesh Sharma <bhupesh.sharma@st.com>
-+ *
-+ * Borrowed heavily from the C_CAN driver originally written by:
-+ * Copyright (C) 2007
-+ * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
-+ * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
-+ *
-+ * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
-+ * Bosch D_CAN user manual can be obtained from:
-+ * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
-+ * d_can_users_manual_111.pdf
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+/*
-+ * Your platform definitions should specify module ram offsets and interrupt
-+ * number to use as follows:
-+ *
-+ * static struct d_can_platform_data am33xx_evm_d_can_pdata = {
-+ *	.num_of_msg_objs	= 64,
-+ *	.dma_support		= false,
-+ *	.ram_init		= d_can_hw_raminit,
-+ * };
-+ *
-+ * Please see include/linux/can/platform/d_can.h for description of
-+ * above fields.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/netdevice.h>
-+#include <linux/if_arp.h>
-+#include <linux/if_ether.h>
-+#include <linux/list.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/can/platform/d_can.h>
-+#include <linux/clk.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/slab.h>
-+#include <linux/can/dev.h>
-+
-+#include "d_can.h"
-+
-+static int __devinit d_can_plat_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+	void __iomem *addr;
-+	struct net_device *ndev;
-+	struct d_can_priv *priv;
-+	struct resource *mem;
-+	struct d_can_platform_data *pdata;
-+	struct clk *fck;
-+
-+	pdata = pdev->dev.platform_data;
-+	if (!pdata) {
-+		dev_err(&pdev->dev, "No platform data\n");
-+		goto exit;
-+	}
-+
-+	/* allocate the d_can device */
-+	ndev = alloc_d_can_dev(pdata->num_of_msg_objs);
-+	if (!ndev) {
-+		ret = -ENOMEM;
-+		dev_err(&pdev->dev, "alloc_d_can_dev failed\n");
-+		goto exit;
-+	}
-+
-+	priv = netdev_priv(ndev);
-+	fck = clk_get(&pdev->dev, "fck");
-+	if (IS_ERR(fck)) {
-+		dev_err(&pdev->dev, "fck is not found\n");
-+		ret = -ENODEV;
-+		goto exit_free_ndev;
-+	}
-+
-+	/* get the platform data */
-+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!mem) {
-+		ret = -ENODEV;
-+		dev_err(&pdev->dev, "No mem resource\n");
-+		goto exit_clk_put;
-+	}
-+
-+	if (!request_mem_region(mem->start, resource_size(mem),
-+				D_CAN_DRV_NAME)) {
-+		dev_err(&pdev->dev, "resource unavailable\n");
-+		ret = -EBUSY;
-+		goto exit_clk_put;
-+	}
-+
-+	addr = ioremap(mem->start, resource_size(mem));
-+	if (!addr) {
-+		dev_err(&pdev->dev, "ioremap failed\n");
-+		ret = -ENOMEM;
-+		goto exit_release_mem;
-+	}
-+
-+	/* IRQ specific to Error and status & can be used for Message Object */
-+	ndev->irq = platform_get_irq_byname(pdev, "d_can_ms");
-+	if (!ndev->irq) {
-+		dev_err(&pdev->dev, "No irq0 resource\n");
-+		goto exit_iounmap;
-+	}
-+
-+	/* IRQ specific for Message Object */
-+	priv->irq_obj = platform_get_irq_byname(pdev, "d_can_mo");
-+	if (!priv->irq_obj) {
-+		dev_err(&pdev->dev, "No irq1 resource\n");
-+		goto exit_iounmap;
-+	}
-+
-+	pm_runtime_enable(&pdev->dev);
-+	pm_runtime_get_sync(&pdev->dev);
-+	priv->pdev = pdev;
-+	priv->base = addr;
-+	priv->can.clock.freq = clk_get_rate(fck);
-+	priv->ram_init = pdata->ram_init;
-+	priv->opened = false;
-+
-+	platform_set_drvdata(pdev, ndev);
-+	SET_NETDEV_DEV(ndev, &pdev->dev);
-+
-+	ret = register_d_can_dev(ndev);
-+	if (ret) {
-+		dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
-+				D_CAN_DRV_NAME, ret);
-+		goto exit_free_device;
-+	}
-+
-+	/* Initialize DCAN RAM */
-+	d_can_reset_ram(priv, pdev->id, 1);
-+
-+	dev_info(&pdev->dev, "device registered (irq=%d, irq_obj=%d)\n",
-+						ndev->irq, priv->irq_obj);
-+
-+	return 0;
-+
-+exit_free_device:
-+	platform_set_drvdata(pdev, NULL);
-+	pm_runtime_disable(&pdev->dev);
-+exit_iounmap:
-+	iounmap(addr);
-+exit_release_mem:
-+	release_mem_region(mem->start, resource_size(mem));
-+exit_clk_put:
-+	clk_put(fck);
-+exit_free_ndev:
-+	free_d_can_dev(ndev);
-+exit:
-+	dev_err(&pdev->dev, "probe failed\n");
-+
-+	return ret;
-+}
-+
-+static int __devexit d_can_plat_remove(struct platform_device *pdev)
-+{
-+	struct net_device *ndev = platform_get_drvdata(pdev);
-+	struct d_can_priv *priv = netdev_priv(ndev);
-+	struct resource *mem;
-+
-+	/* De-initialize DCAN RAM */
-+	d_can_reset_ram(priv, pdev->id, 0);
-+
-+	unregister_d_can_dev(ndev);
-+	platform_set_drvdata(pdev, NULL);
-+
-+	free_d_can_dev(ndev);
-+	iounmap(priv->base);
-+
-+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	release_mem_region(mem->start, resource_size(mem));
-+
-+	pm_runtime_put_sync(&pdev->dev);
-+	pm_runtime_disable(&pdev->dev);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_PM
-+static int d_can_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+	int ret;
-+	struct net_device *ndev = platform_get_drvdata(pdev);
-+	struct d_can_priv *priv = netdev_priv(ndev);
-+
-+	if (netif_running(ndev)) {
-+		netif_stop_queue(ndev);
-+		netif_device_detach(ndev);
-+	}
-+
-+	ret = d_can_power_down(priv);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Not entered power down mode\n");
-+		return ret;
-+	}
-+
-+	priv->can.state = CAN_STATE_SLEEPING;
-+
-+	/* De-initialize DCAN RAM */
-+	d_can_reset_ram(priv, pdev->id, 0);
-+
-+	/* Disable the module */
-+	pm_runtime_put_sync(&pdev->dev);
-+
-+	return 0;
-+}
-+
-+static int d_can_resume(struct platform_device *pdev)
-+{
-+	int ret;
-+
-+	struct net_device *ndev = platform_get_drvdata(pdev);
-+	struct d_can_priv *priv = netdev_priv(ndev);
-+
-+	/* Enable the module */
-+	pm_runtime_get_sync(&pdev->dev);
-+
-+	/* Initialize DCAN RAM */
-+	d_can_reset_ram(priv, pdev->id, 1);
-+
-+	ret = d_can_power_up(priv);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Not came out from power down mode\n");
-+		return ret;
-+	}
-+
-+	priv->can.state = CAN_STATE_ERROR_ACTIVE;
-+
-+	if (netif_running(ndev)) {
-+		netif_device_attach(ndev);
-+		netif_start_queue(ndev);
-+	}
-+
-+	return 0;
-+}
-+#else
-+#define d_can_suspend NULL
-+#define d_can_resume NULL
-+#endif
-+
-+static struct platform_driver d_can_plat_driver = {
-+	.driver = {
-+		.name	= D_CAN_DRV_NAME,
-+		.owner	= THIS_MODULE,
-+	},
-+	.probe		= d_can_plat_probe,
-+	.remove		= __devexit_p(d_can_plat_remove),
-+	.suspend	= d_can_suspend,
-+	.resume		= d_can_resume,
-+};
-+
-+static int __init d_can_plat_init(void)
-+{
-+	printk(KERN_INFO D_CAN_DRV_DESC "\n");
-+	return platform_driver_register(&d_can_plat_driver);
-+}
-+module_init(d_can_plat_init);
-+
-+static void __exit d_can_plat_exit(void)
-+{
-+	printk(KERN_INFO D_CAN_DRV_DESC " unloaded\n");
-+	platform_driver_unregister(&d_can_plat_driver);
-+}
-+module_exit(d_can_plat_exit);
-+
-+MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_VERSION(D_CAN_VERSION);
-+MODULE_DESCRIPTION(D_CAN_DRV_DESC);
-diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c
-index 25695bd..bc1e87e 100644
---- a/drivers/net/can/dev.c
-+++ b/drivers/net/can/dev.c
-@@ -392,7 +392,7 @@ void can_restart(unsigned long data)
- 	stats->rx_bytes += cf->can_dlc;
- 
- restart:
--	dev_dbg(dev->dev.parent, "restarted\n");
-+	netdev_dbg(dev, "restarted\n");
- 	priv->can_stats.restarts++;
- 
- 	/* Now restart the device */
-@@ -400,7 +400,7 @@ restart:
- 
- 	netif_carrier_on(dev);
- 	if (err)
--		dev_err(dev->dev.parent, "Error %d during restart", err);
-+		netdev_err(dev, "error %d during restart", err);
- }
- 
- int can_restart_now(struct net_device *dev)
-@@ -433,7 +433,7 @@ void can_bus_off(struct net_device *dev)
- {
- 	struct can_priv *priv = netdev_priv(dev);
- 
--	dev_dbg(dev->dev.parent, "bus-off\n");
-+	netdev_dbg(dev, "bus-off\n");
- 
- 	netif_carrier_off(dev);
- 	priv->can_stats.bus_off++;
-@@ -545,7 +545,7 @@ int open_candev(struct net_device *dev)
- 	struct can_priv *priv = netdev_priv(dev);
- 
- 	if (!priv->bittiming.tq && !priv->bittiming.bitrate) {
--		dev_err(dev->dev.parent, "bit-timing not yet defined\n");
-+		netdev_err(dev, "bit-timing not yet defined\n");
- 		return -EINVAL;
- 	}
- 
-diff --git a/drivers/net/can/mcp251x.c b/drivers/net/can/mcp251x.c
-index 330140e..b3e231c 100644
---- a/drivers/net/can/mcp251x.c
-+++ b/drivers/net/can/mcp251x.c
-@@ -93,8 +93,9 @@
- #  define CANCTRL_REQOP_LOOPBACK    0x40
- #  define CANCTRL_REQOP_SLEEP	    0x20
- #  define CANCTRL_REQOP_NORMAL	    0x00
--#  define CANCTRL_OSM		    0x08
- #  define CANCTRL_ABAT		    0x10
-+#  define CANCTRL_OSM		    0x08
-+#  define CANCTRL_CLKEN		    0x04
- #define TEC	      0x1c
- #define REC	      0x1d
- #define CNF1	      0x2a
-@@ -287,7 +288,7 @@ static void mcp251x_clean(struct net_device *net)
- /*
-  * Note about handling of error return of mcp251x_spi_trans: accessing
-  * registers via SPI is not really different conceptually than using
-- * normal I/O assembler instructions, although it's much more
-+ * normal I/O assembly instructions, although it's much more
-  * complicated from a practical POV. So it's not advisable to always
-  * check the return value of this function. Imagine that every
-  * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
-@@ -490,7 +491,7 @@ static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
- 
- static void mcp251x_hw_sleep(struct spi_device *spi)
- {
--	mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
-+//	mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
- }
- 
- static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
-@@ -547,13 +548,16 @@ static int mcp251x_set_normal_mode(struct spi_device *spi)
- 
- 	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
- 		/* Put device into loopback mode */
--		mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
-+		mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK | CANCTRL_CLKEN);
- 	} else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
- 		/* Put device into listen-only mode */
--		mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
-+		mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY | CANCTRL_CLKEN);
- 	} else {
- 		/* Put device into normal mode */
--		mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
-+		mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL | CANCTRL_CLKEN);
-+
-+                netdev_info(priv->net, "CANCTRL: 0x%02x\n",
-+                  mcp251x_read_reg(spi, CANCTRL));
- 
- 		/* Wait for the device to enter normal mode */
- 		timeout = jiffies + HZ;
-@@ -585,11 +589,15 @@ static int mcp251x_do_set_bittiming(struct net_device *net)
- 			  (bt->prop_seg - 1));
- 	mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
- 			   (bt->phase_seg2 - 1));
--	dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
-+
-+	netdev_info(net, "CNF: 0x%02x 0x%02x 0x%02x\n",
- 		 mcp251x_read_reg(spi, CNF1),
- 		 mcp251x_read_reg(spi, CNF2),
- 		 mcp251x_read_reg(spi, CNF3));
- 
-+	netdev_info(net, "CANCTRL: 0x%02x\n",
-+		 mcp251x_read_reg(spi, CANCTRL));
-+
- 	return 0;
- }
- 
-@@ -600,6 +608,7 @@ static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
- 
- 	mcp251x_write_reg(spi, RXBCTRL(0),
- 			  RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
-+
- 	mcp251x_write_reg(spi, RXBCTRL(1),
- 			  RXBCTRL_RXM0 | RXBCTRL_RXM1);
- 	return 0;
-@@ -728,7 +737,9 @@ static void mcp251x_tx_work_handler(struct work_struct *ws)
- 	mutex_lock(&priv->mcp_lock);
- 	if (priv->tx_skb) {
- 		if (priv->can.state == CAN_STATE_BUS_OFF) {
-+
- 			mcp251x_clean(net);
-+
- 		} else {
- 			frame = (struct can_frame *)priv->tx_skb->data;
- 
-@@ -827,21 +838,37 @@ static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
- 
- 		/* Update can state */
- 		if (eflag & EFLG_TXBO) {
-+
-+		        netdev_err(net, "err: bus off\n");
-+
- 			new_state = CAN_STATE_BUS_OFF;
- 			can_id |= CAN_ERR_BUSOFF;
- 		} else if (eflag & EFLG_TXEP) {
-+
-+		        netdev_err(net, "err: txep\n");
-+
- 			new_state = CAN_STATE_ERROR_PASSIVE;
- 			can_id |= CAN_ERR_CRTL;
- 			data1 |= CAN_ERR_CRTL_TX_PASSIVE;
-+
- 		} else if (eflag & EFLG_RXEP) {
-+
-+		        netdev_err(net, "err: rxep\n");
-+
- 			new_state = CAN_STATE_ERROR_PASSIVE;
- 			can_id |= CAN_ERR_CRTL;
- 			data1 |= CAN_ERR_CRTL_RX_PASSIVE;
- 		} else if (eflag & EFLG_TXWAR) {
-+
-+		        netdev_err(net, "err: txwar\n");
-+
- 			new_state = CAN_STATE_ERROR_WARNING;
- 			can_id |= CAN_ERR_CRTL;
- 			data1 |= CAN_ERR_CRTL_TX_WARNING;
- 		} else if (eflag & EFLG_RXWAR) {
-+
-+		        netdev_err(net, "err: rxwar\n");
-+
- 			new_state = CAN_STATE_ERROR_WARNING;
- 			can_id |= CAN_ERR_CRTL;
- 			data1 |= CAN_ERR_CRTL_RX_WARNING;
-@@ -918,7 +945,7 @@ static int mcp251x_open(struct net_device *net)
- 
- 	ret = open_candev(net);
- 	if (ret) {
--		dev_err(&spi->dev, "unable to set initial baudrate!\n");
-+		netdev_err(net, "failed to open can device\n");
- 		return ret;
- 	}
- 
-@@ -934,7 +961,7 @@ static int mcp251x_open(struct net_device *net)
- 		  pdata->irq_flags ? pdata->irq_flags : IRQF_TRIGGER_FALLING,
- 		  DEVICE_NAME, priv);
- 	if (ret) {
--		dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
-+		netdev_err(net, "failed to acquire irq %d\n", spi->irq);
- 		if (pdata->transceiver_enable)
- 			pdata->transceiver_enable(0);
- 		close_candev(net);
-@@ -1071,7 +1098,7 @@ static int __devinit mcp251x_can_probe(struct spi_device *spi)
- 
- 	ret = register_candev(net);
- 	if (!ret) {
--		dev_info(&spi->dev, "probed\n");
-+		netdev_info(priv->net, "probed\n");
- 		return ret;
- 	}
- error_probe:
-diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/sge.c b/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
-index 8d5d55a..39b9de7 100644
---- a/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
-+++ b/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
-@@ -684,7 +684,7 @@ out:
- 	/*
- 	 * Update our accounting state to incorporate the new Free List
- 	 * buffers, tell the hardware about them and return the number of
--	 * bufers which we were able to allocate.
-+	 * buffers which we were able to allocate.
- 	 */
- 	cred = fl->avail - cred;
- 	fl->pend_cred += cred;
-diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig
-index de76c70..2594c94 100644
---- a/drivers/net/ethernet/ti/Kconfig
-+++ b/drivers/net/ethernet/ti/Kconfig
-@@ -49,6 +49,27 @@ config TI_DAVINCI_CPDMA
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called davinci_cpdma.  This is recommended.
- 
-+config TI_CPSW
-+	tristate "TI CPSW Switch Support"
-+	depends on ARM && (ARCH_DAVINCI || SOC_OMAPAM33XX)
-+	select TI_DAVINCI_CPDMA
-+	select TI_DAVINCI_MDIO
-+	---help---
-+	  This driver supports TI's CPSW Ethernet Switch.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called cpsw.
-+
-+config TLK110_WORKAROUND
-+       tristate "TI TLK110 v1.0 PHY Workaround"
-+       depends on TI_CPSW
-+       help
-+         This supports workaround for TLK110 rev 1.0 PHY.
-+
-+         This should be used  when TLK110 rev 1.0 PHY is used. In case of
-+         higher version of TLK110 PHY, this workaround is not required
-+         and disable it.
-+
- config TLAN
- 	tristate "TI ThunderLAN support"
- 	depends on (PCI || EISA)
-diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile
-index aedb3af..91bd8bb 100644
---- a/drivers/net/ethernet/ti/Makefile
-+++ b/drivers/net/ethernet/ti/Makefile
-@@ -7,3 +7,5 @@ obj-$(CONFIG_CPMAC) += cpmac.o
- obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o
- obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o
- obj-$(CONFIG_TI_DAVINCI_CPDMA) += davinci_cpdma.o
-+obj-$(CONFIG_TI_CPSW) += ti_cpsw.o
-+ti_cpsw-y := cpsw_ale.o cpsw.o
-diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
-new file mode 100644
-index 0000000..86fe57d
---- /dev/null
-+++ b/drivers/net/ethernet/ti/cpsw.c
-@@ -0,0 +1,1378 @@
-+/*
-+ * Texas Instruments Ethernet Switch Driver
-+ *
-+ * Copyright (C) 2010 Texas Instruments
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#include <linux/kernel.h>
-+#include <linux/io.h>
-+#include <linux/clk.h>
-+#include <linux/timer.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/if_ether.h>
-+#include <linux/etherdevice.h>
-+#include <linux/ethtool.h>
-+#include <linux/netdevice.h>
-+#include <linux/phy.h>
-+#include <linux/workqueue.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+
-+#include <linux/cpsw.h>
-+#include <plat/dmtimer.h>
-+#include "cpsw_ale.h"
-+#include "davinci_cpdma.h"
-+
-+
-+#define CPSW_DEBUG	(NETIF_MSG_HW		| NETIF_MSG_WOL		| \
-+			 NETIF_MSG_DRV		| NETIF_MSG_LINK	| \
-+			 NETIF_MSG_IFUP		| NETIF_MSG_INTR	| \
-+			 NETIF_MSG_PROBE	| NETIF_MSG_TIMER	| \
-+			 NETIF_MSG_IFDOWN	| NETIF_MSG_RX_ERR	| \
-+			 NETIF_MSG_TX_ERR	| NETIF_MSG_TX_DONE	| \
-+			 NETIF_MSG_PKTDATA	| NETIF_MSG_TX_QUEUED	| \
-+			 NETIF_MSG_RX_STATUS)
-+
-+#define msg(level, type, format, ...)				\
-+do {								\
-+	if (netif_msg_##type(priv) && net_ratelimit())		\
-+		dev_##level(priv->dev, format, ## __VA_ARGS__);	\
-+} while (0)
-+
-+#define CPDMA_RXTHRESH		0x0c0
-+#define CPDMA_RXFREE		0x0e0
-+#define CPDMA_TXHDP_VER1	0x100
-+#define CPDMA_TXHDP_VER2	0x200
-+#define CPDMA_RXHDP_VER1	0x120
-+#define CPDMA_RXHDP_VER2	0x220
-+#define CPDMA_TXCP_VER1		0x140
-+#define CPDMA_TXCP_VER2		0x240
-+#define CPDMA_RXCP_VER1		0x160
-+#define CPDMA_RXCP_VER2		0x260
-+
-+#define CPSW_POLL_WEIGHT	64
-+#define CPSW_MIN_PACKET_SIZE	60
-+#define CPSW_MAX_PACKET_SIZE	(1500 + 14 + 4 + 4)
-+#define CPSW_PHY_SPEED		1000
-+
-+/* CPSW control module masks */
-+#define CPSW_INTPACEEN		(0x3 << 16)
-+#define CPSW_INTPRESCALE_MASK	(0x7FF << 0)
-+#define CPSW_CMINTMAX_CNT	63
-+#define CPSW_CMINTMIN_CNT	2
-+#define CPSW_CMINTMAX_INTVL	(1000 / CPSW_CMINTMIN_CNT)
-+#define CPSW_CMINTMIN_INTVL	((1000 / CPSW_CMINTMAX_CNT) + 1)
-+
-+#define cpsw_enable_irq(priv)	\
-+	do {			\
-+		u32 i;		\
-+		for (i = 0; i < priv->num_irqs; i++) \
-+			enable_irq(priv->irqs_table[i]); \
-+	} while (0);
-+#define cpsw_disable_irq(priv)	\
-+	do {			\
-+		u32 i;		\
-+		for (i = 0; i < priv->num_irqs; i++) \
-+			disable_irq_nosync(priv->irqs_table[i]); \
-+	} while (0);
-+
-+#define CPSW_CPDMA_EOI_REG	0x894
-+#define CPSW_TIMER_MASK		0xA0908
-+#define CPSW_TIMER_CAP_REG	0xFD0
-+#define CPSW_RX_TIMER_REQ	5
-+#define CPSW_TX_TIMER_REQ	6
-+
-+struct omap_dm_timer *dmtimer_rx;
-+struct omap_dm_timer *dmtimer_tx;
-+
-+extern u32 omap_ctrl_readl(u16 offset);
-+extern void omap_ctrl_writel(u32 val, u16 offset);
-+
-+static int debug_level;
-+module_param(debug_level, int, 0);
-+MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
-+
-+static int ale_ageout = 10;
-+module_param(ale_ageout, int, 0);
-+MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
-+
-+static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
-+module_param(rx_packet_max, int, 0);
-+MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
-+
-+struct cpsw_ss_regs {
-+	u32	id_ver;
-+	u32	soft_reset;
-+	u32	control;
-+	u32	int_control;
-+	u32	rx_thresh_en;
-+	u32	rx_en;
-+	u32	tx_en;
-+	u32	misc_en;
-+	u32	mem_allign1[8];
-+	u32	rx_thresh_stat;
-+	u32	rx_stat;
-+	u32	tx_stat;
-+	u32	misc_stat;
-+	u32	mem_allign2[8];
-+	u32	rx_imax;
-+	u32	tx_imax;
-+};
-+
-+struct cpsw_regs {
-+	u32	id_ver;
-+	u32	control;
-+	u32	soft_reset;
-+	u32	stat_port_en;
-+	u32	ptype;
-+	u32	soft_idle;
-+};
-+
-+struct cpsw_slave_regs {
-+	u32	max_blks;
-+	u32	blk_cnt;
-+	u32	flow_thresh;
-+	u32	port_vlan;
-+	u32	tx_pri_map;
-+	u32	ts_seq_mtype;
-+#ifdef CONFIG_ARCH_TI814X
-+	u32	ts_ctl;
-+	u32	ts_seq_ltype;
-+	u32	ts_vlan;
-+#endif
-+	u32	sa_lo;
-+	u32	sa_hi;
-+};
-+
-+struct cpsw_host_regs {
-+	u32	max_blks;
-+	u32	blk_cnt;
-+	u32	flow_thresh;
-+	u32	port_vlan;
-+	u32	tx_pri_map;
-+	u32	cpdma_tx_pri_map;
-+	u32	cpdma_rx_chan_map;
-+};
-+
-+struct cpsw_sliver_regs {
-+	u32	id_ver;
-+	u32	mac_control;
-+	u32	mac_status;
-+	u32	soft_reset;
-+	u32	rx_maxlen;
-+	u32	__reserved_0;
-+	u32	rx_pause;
-+	u32	tx_pause;
-+	u32	__reserved_1;
-+	u32	rx_pri_map;
-+};
-+
-+struct cpsw_hw_stats {
-+	u32	rxgoodframes;
-+	u32	rxbroadcastframes;
-+	u32	rxmulticastframes;
-+	u32	rxpauseframes;
-+	u32	rxcrcerrors;
-+	u32	rxaligncodeerrors;
-+	u32	rxoversizedframes;
-+	u32	rxjabberframes;
-+	u32	rxundersizedframes;
-+	u32	rxfragments;
-+	u32	__pad_0[2];
-+	u32	rxoctets;
-+	u32	txgoodframes;
-+	u32	txbroadcastframes;
-+	u32	txmulticastframes;
-+	u32	txpauseframes;
-+	u32	txdeferredframes;
-+	u32	txcollisionframes;
-+	u32	txsinglecollframes;
-+	u32	txmultcollframes;
-+	u32	txexcessivecollisions;
-+	u32	txlatecollisions;
-+	u32	txunderrun;
-+	u32	txcarriersenseerrors;
-+	u32	txoctets;
-+	u32	octetframes64;
-+	u32	octetframes65t127;
-+	u32	octetframes128t255;
-+	u32	octetframes256t511;
-+	u32	octetframes512t1023;
-+	u32	octetframes1024tup;
-+	u32	netoctets;
-+	u32	rxsofoverruns;
-+	u32	rxmofoverruns;
-+	u32	rxdmaoverruns;
-+};
-+
-+struct cpsw_slave {
-+	struct cpsw_slave_regs __iomem	*regs;
-+	struct cpsw_sliver_regs __iomem	*sliver;
-+	int				slave_num;
-+	u32				mac_control;
-+	struct cpsw_slave_data		*data;
-+	struct phy_device		*phy;
-+};
-+
-+struct cpsw_priv {
-+	spinlock_t			lock;
-+	struct platform_device		*pdev;
-+	struct net_device		*ndev;
-+	struct resource			*cpsw_res;
-+	struct resource			*cpsw_ss_res;
-+	struct napi_struct		napi;
-+#define napi_to_priv(napi)	container_of(napi, struct cpsw_priv, napi)
-+	struct device			*dev;
-+	struct cpsw_platform_data	data;
-+	struct cpsw_regs __iomem	*regs;
-+	struct cpsw_ss_regs __iomem	*ss_regs;
-+	struct cpsw_hw_stats __iomem	*hw_stats;
-+	struct cpsw_host_regs __iomem	*host_port_regs;
-+	u32				msg_enable;
-+	u32				coal_intvl;
-+	u32				bus_freq_mhz;
-+	struct net_device_stats		stats;
-+	int				rx_packet_max;
-+	int				host_port;
-+	struct clk			*clk;
-+	u8				mac_addr[ETH_ALEN];
-+	struct cpsw_slave		*slaves;
-+#define for_each_slave(priv, func, arg...)			\
-+	do {							\
-+		int idx;					\
-+		for (idx = 0; idx < (priv)->data.slaves; idx++)	\
-+			(func)((priv)->slaves + idx, ##arg);	\
-+	} while (0)
-+
-+	struct cpdma_ctlr		*dma;
-+	struct cpdma_chan		*txch, *rxch;
-+	struct cpsw_ale			*ale;
-+
-+	/* snapshot of IRQ numbers */
-+	u32 irqs_table[4];
-+	u32 num_irqs;
-+
-+};
-+
-+static int cpsw_set_coalesce(struct net_device *ndev,
-+			struct ethtool_coalesce *coal);
-+
-+static void cpsw_intr_enable(struct cpsw_priv *priv)
-+{
-+	__raw_writel(0xFF, &priv->ss_regs->tx_en);
-+	__raw_writel(0xFF, &priv->ss_regs->rx_en);
-+
-+	cpdma_ctlr_int_ctrl(priv->dma, true);
-+	return;
-+}
-+
-+static void cpsw_intr_disable(struct cpsw_priv *priv)
-+{
-+	__raw_writel(0, &priv->ss_regs->tx_en);
-+	__raw_writel(0, &priv->ss_regs->rx_en);
-+
-+	cpdma_ctlr_int_ctrl(priv->dma, false);
-+	return;
-+}
-+
-+void cpsw_tx_handler(void *token, int len, int status)
-+{
-+	struct sk_buff		*skb = token;
-+	struct net_device	*ndev = skb->dev;
-+	struct cpsw_priv	*priv = netdev_priv(ndev);
-+
-+	if (unlikely(netif_queue_stopped(ndev)))
-+		netif_start_queue(ndev);
-+	priv->stats.tx_packets++;
-+	priv->stats.tx_bytes += len;
-+	dev_kfree_skb_any(skb);
-+}
-+
-+void cpsw_rx_handler(void *token, int len, int status)
-+{
-+	struct sk_buff		*skb = token;
-+	struct net_device	*ndev = skb->dev;
-+	struct cpsw_priv	*priv = netdev_priv(ndev);
-+	int			ret = 0;
-+
-+	if (unlikely(!netif_running(ndev)) ||
-+			unlikely(!netif_carrier_ok(ndev))) {
-+		dev_kfree_skb_any(skb);
-+		return;
-+	}
-+
-+	if (likely(status >= 0)) {
-+		skb_put(skb, len);
-+		skb->protocol = eth_type_trans(skb, ndev);
-+		netif_receive_skb(skb);
-+		priv->stats.rx_bytes += len;
-+		priv->stats.rx_packets++;
-+		skb = NULL;
-+	}
-+
-+
-+	if (unlikely(!netif_running(ndev))) {
-+		if (skb)
-+			dev_kfree_skb_any(skb);
-+		return;
-+	}
-+
-+	if (likely(!skb)) {
-+		skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
-+		if (WARN_ON(!skb))
-+			return;
-+
-+		ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
-+				skb_tailroom(skb), GFP_KERNEL);
-+	}
-+
-+	WARN_ON(ret < 0);
-+
-+}
-+
-+static void set_cpsw_dmtimer_clear(void)
-+{
-+	omap_dm_timer_write_status(dmtimer_rx, OMAP_TIMER_INT_CAPTURE);
-+	omap_dm_timer_write_status(dmtimer_tx, OMAP_TIMER_INT_CAPTURE);
-+
-+	return;
-+}
-+
-+static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
-+{
-+	struct cpsw_priv *priv = dev_id;
-+
-+	if (likely(netif_running(priv->ndev))) {
-+		cpsw_intr_disable(priv);
-+		cpsw_disable_irq(priv);
-+		napi_schedule(&priv->napi);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int cpsw_poll(struct napi_struct *napi, int budget)
-+{
-+	struct cpsw_priv	*priv = napi_to_priv(napi);
-+	int			num_tx, num_rx;
-+
-+	num_tx = cpdma_chan_process(priv->txch, 128);
-+	num_rx = cpdma_chan_process(priv->rxch, budget);
-+
-+	if (num_rx || num_tx)
-+		msg(dbg, intr, "poll %d rx, %d tx pkts\n", num_rx, num_tx);
-+
-+	if (num_rx < budget) {
-+		napi_complete(napi);
-+		cpdma_ctlr_eoi(priv->dma);
-+		set_cpsw_dmtimer_clear();
-+		cpsw_intr_enable(priv);
-+		cpsw_enable_irq(priv);
-+	}
-+
-+	return num_rx;
-+}
-+
-+static inline void soft_reset(const char *module, void __iomem *reg)
-+{
-+	unsigned long timeout = jiffies + HZ;
-+
-+	__raw_writel(1, reg);
-+	do {
-+		cpu_relax();
-+	} while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
-+
-+	WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
-+}
-+
-+#define mac_hi(mac)	(((mac)[0] << 0) | ((mac)[1] << 8) |	\
-+			 ((mac)[2] << 16) | ((mac)[3] << 24))
-+#define mac_lo(mac)	(((mac)[4] << 0) | ((mac)[5] << 8))
-+
-+static void cpsw_set_slave_mac(struct cpsw_slave *slave,
-+			       struct cpsw_priv *priv)
-+{
-+	__raw_writel(mac_hi(priv->mac_addr), &slave->regs->sa_hi);
-+	__raw_writel(mac_lo(priv->mac_addr), &slave->regs->sa_lo);
-+}
-+
-+static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
-+{
-+	if (priv->host_port == 0)
-+		return slave_num + 1;
-+	else
-+		return slave_num;
-+}
-+
-+static void _cpsw_adjust_link(struct cpsw_slave *slave,
-+			      struct cpsw_priv *priv, bool *link)
-+{
-+	struct phy_device	*phy = slave->phy;
-+	u32			mac_control = 0;
-+	u32			slave_port;
-+
-+	if (!phy)
-+		return;
-+
-+	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
-+
-+	if (phy->link) {
-+		/* enable forwarding */
-+		cpsw_ale_control_set(priv->ale, slave_port,
-+			ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
-+
-+		mac_control = priv->data.mac_control;
-+		if (phy->speed == 10)
-+			mac_control |= BIT(18); /* In Band mode */
-+		if (phy->speed == 1000) {
-+			mac_control |= BIT(7);	/* Enable gigabit mode */
-+		}
-+		if (phy->speed == 100)
-+			mac_control |= BIT(15);
-+		if (phy->duplex)
-+			mac_control |= BIT(0);	/* FULLDUPLEXEN	*/
-+		if (phy->interface == PHY_INTERFACE_MODE_RGMII) /* RGMII */
-+			mac_control |= (BIT(15)|BIT(16));
-+		*link = true;
-+	} else {
-+		cpsw_ale_control_set(priv->ale, slave_port,
-+			     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
-+		mac_control = 0;
-+	}
-+
-+	if (mac_control != slave->mac_control) {
-+		phy_print_status(phy);
-+		__raw_writel(mac_control, &slave->sliver->mac_control);
-+	}
-+
-+	slave->mac_control = mac_control;
-+}
-+
-+static void cpsw_adjust_link(struct net_device *ndev)
-+{
-+	struct cpsw_priv	*priv = netdev_priv(ndev);
-+	bool			link = false;
-+
-+	for_each_slave(priv, _cpsw_adjust_link, priv, &link);
-+
-+	if (link) {
-+		netif_carrier_on(ndev);
-+		if (netif_running(ndev))
-+			netif_wake_queue(ndev);
-+	} else {
-+		netif_carrier_off(ndev);
-+		netif_stop_queue(ndev);
-+	}
-+}
-+
-+static inline int __show_stat(char *buf, int maxlen, const char* name, u32 val)
-+{
-+	static char *leader = "........................................";
-+
-+	if (!val)
-+		return 0;
-+	else
-+		return snprintf(buf, maxlen, "%s %s %10d\n", name,
-+				leader + strlen(name), val);
-+}
-+
-+static ssize_t cpsw_hw_stats_show(struct device *dev,
-+				     struct device_attribute *attr,
-+				     char *buf)
-+{
-+	struct net_device	*ndev = to_net_dev(dev);
-+	struct cpsw_priv	*priv = netdev_priv(ndev);
-+	int			len = 0;
-+	struct cpdma_chan_stats	dma_stats;
-+
-+#define show_stat(x) do {						\
-+	len += __show_stat(buf + len, SZ_4K - len, #x,			\
-+			   __raw_readl(&priv->hw_stats->x));		\
-+} while (0)
-+
-+#define show_dma_stat(x) do {						\
-+	len += __show_stat(buf + len, SZ_4K - len, #x, dma_stats.x);	\
-+} while (0)
-+
-+	len += snprintf(buf + len, SZ_4K - len, "CPSW Statistics:\n");
-+	show_stat(rxgoodframes);	show_stat(rxbroadcastframes);
-+	show_stat(rxmulticastframes);	show_stat(rxpauseframes);
-+	show_stat(rxcrcerrors);		show_stat(rxaligncodeerrors);
-+	show_stat(rxoversizedframes);	show_stat(rxjabberframes);
-+	show_stat(rxundersizedframes);	show_stat(rxfragments);
-+	show_stat(rxoctets);		show_stat(txgoodframes);
-+	show_stat(txbroadcastframes);	show_stat(txmulticastframes);
-+	show_stat(txpauseframes);	show_stat(txdeferredframes);
-+	show_stat(txcollisionframes);	show_stat(txsinglecollframes);
-+	show_stat(txmultcollframes);	show_stat(txexcessivecollisions);
-+	show_stat(txlatecollisions);	show_stat(txunderrun);
-+	show_stat(txcarriersenseerrors); show_stat(txoctets);
-+	show_stat(octetframes64);	show_stat(octetframes65t127);
-+	show_stat(octetframes128t255);	show_stat(octetframes256t511);
-+	show_stat(octetframes512t1023);	show_stat(octetframes1024tup);
-+	show_stat(netoctets);		show_stat(rxsofoverruns);
-+	show_stat(rxmofoverruns);	show_stat(rxdmaoverruns);
-+
-+	cpdma_chan_get_stats(priv->rxch, &dma_stats);
-+	len += snprintf(buf + len, SZ_4K - len, "\nRX DMA Statistics:\n");
-+	show_dma_stat(head_enqueue);	show_dma_stat(tail_enqueue);
-+	show_dma_stat(pad_enqueue);	show_dma_stat(misqueued);
-+	show_dma_stat(desc_alloc_fail);	show_dma_stat(pad_alloc_fail);
-+	show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff);
-+	show_dma_stat(empty_dequeue);	show_dma_stat(busy_dequeue);
-+	show_dma_stat(good_dequeue);	show_dma_stat(teardown_dequeue);
-+
-+	cpdma_chan_get_stats(priv->txch, &dma_stats);
-+	len += snprintf(buf + len, SZ_4K - len, "\nTX DMA Statistics:\n");
-+	show_dma_stat(head_enqueue);	show_dma_stat(tail_enqueue);
-+	show_dma_stat(pad_enqueue);	show_dma_stat(misqueued);
-+	show_dma_stat(desc_alloc_fail);	show_dma_stat(pad_alloc_fail);
-+	show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff);
-+	show_dma_stat(empty_dequeue);	show_dma_stat(busy_dequeue);
-+	show_dma_stat(good_dequeue);	show_dma_stat(teardown_dequeue);
-+
-+	return len;
-+}
-+
-+DEVICE_ATTR(hw_stats, S_IRUGO, cpsw_hw_stats_show, NULL);
-+
-+#define PHY_CONFIG_REG	22
-+static void cpsw_set_phy_config(struct cpsw_priv *priv, struct phy_device *phy)
-+{
-+	struct cpsw_platform_data *pdata = priv->pdev->dev.platform_data;
-+	struct mii_bus *miibus;
-+	int phy_addr = 0;
-+	u16 val = 0;
-+	u16 tmp = 0;
-+
-+	if (!phy)
-+		return;
-+
-+	miibus = phy->bus;
-+
-+	if (!miibus)
-+		return;
-+
-+	phy_addr = phy->addr;
-+
-+	/* Disable 1 Gig mode support if it is not supported */
-+	if (!pdata->gigabit_en)
-+		phy->supported &= ~(SUPPORTED_1000baseT_Half |
-+					SUPPORTED_1000baseT_Full);
-+
-+	/* Following lines enable gigbit advertisement capability even in case
-+	 * the advertisement is not enabled by default
-+	 */
-+	val = miibus->read(miibus, phy_addr, MII_BMCR);
-+	val |= (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_FULLDPLX);
-+	miibus->write(miibus, phy_addr, MII_BMCR, val);
-+	tmp = miibus->read(miibus, phy_addr, MII_BMCR);
-+
-+	/* Enable gigabit support only if the speed is 1000Mbps */
-+	if (phy->speed == CPSW_PHY_SPEED) {
-+		tmp = miibus->read(miibus, phy_addr, MII_BMSR);
-+		if (tmp & 0x1) {
-+			val = miibus->read(miibus, phy_addr, MII_CTRL1000);
-+			val |= BIT(9);
-+			miibus->write(miibus, phy_addr, MII_CTRL1000, val);
-+			tmp = miibus->read(miibus, phy_addr, MII_CTRL1000);
-+		}
-+	}
-+
-+	val = miibus->read(miibus, phy_addr, MII_ADVERTISE);
-+	val |= (ADVERTISE_10HALF | ADVERTISE_10FULL | \
-+		ADVERTISE_100HALF | ADVERTISE_100FULL);
-+	miibus->write(miibus, phy_addr, MII_ADVERTISE, val);
-+	tmp = miibus->read(miibus, phy_addr, MII_ADVERTISE);
-+
-+	/* TODO : This check is required. This should be
-+	 * moved to a board init section as its specific
-+	 * to a phy.*/
-+	if (phy->phy_id == 0x0282F014) {
-+		/* This enables TX_CLK-ing in case of 10/100MBps operation */
-+		val = miibus->read(miibus, phy_addr, PHY_CONFIG_REG);
-+		val |= BIT(5);
-+		miibus->write(miibus, phy_addr, PHY_CONFIG_REG, val);
-+		tmp = miibus->read(miibus, phy_addr, PHY_CONFIG_REG);
-+	}
-+
-+	return;
-+}
-+
-+static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
-+{
-+	char name[32];
-+	u32 slave_port;
-+
-+	sprintf(name, "slave-%d", slave->slave_num);
-+
-+	soft_reset(name, &slave->sliver->soft_reset);
-+
-+	/* setup priority mapping */
-+	__raw_writel(0x76543210, &slave->sliver->rx_pri_map);
-+	__raw_writel(0x33221100, &slave->regs->tx_pri_map);
-+
-+	/* setup max packet size, and mac address */
-+	__raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
-+	cpsw_set_slave_mac(slave, priv);
-+
-+	slave->mac_control = 0;	/* no link yet */
-+
-+	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
-+	cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
-+			   1 << slave_port);
-+
-+	slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
-+				 &cpsw_adjust_link, 0, slave->data->phy_if);
-+	if (IS_ERR(slave->phy)) {
-+		msg(err, ifup, "phy %s not found on slave %d\n",
-+		    slave->data->phy_id, slave->slave_num);
-+		slave->phy = NULL;
-+	} else {
-+		printk(KERN_ERR"\nCPSW phy found : id is : 0x%x\n",
-+			slave->phy->phy_id);
-+		cpsw_set_phy_config(priv, slave->phy);
-+		phy_start(slave->phy);
-+	}
-+}
-+
-+static void cpsw_init_host_port(struct cpsw_priv *priv)
-+{
-+	/* soft reset the controller and initialize ale */
-+	soft_reset("cpsw", &priv->regs->soft_reset);
-+	cpsw_ale_start(priv->ale);
-+
-+	/* switch to vlan unaware mode */
-+	cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0);
-+
-+	/* setup host port priority mapping */
-+	__raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
-+	__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
-+
-+	cpsw_ale_control_set(priv->ale, priv->host_port,
-+			     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
-+
-+	cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
-+			  0);
-+			   /* ALE_SECURE); */
-+	cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
-+			   1 << priv->host_port);
-+}
-+
-+static int cpsw_ndo_open(struct net_device *ndev)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+	int i, ret;
-+	u32 reg;
-+
-+	cpsw_intr_disable(priv);
-+	netif_carrier_off(ndev);
-+
-+	ret = clk_enable(priv->clk);
-+	if (ret < 0) {
-+		dev_err(priv->dev, "unable to turn on device clock\n");
-+		return ret;
-+	}
-+
-+	ret = device_create_file(&ndev->dev, &dev_attr_hw_stats);
-+	if (ret < 0) {
-+		dev_err(priv->dev, "unable to add device attr\n");
-+		return ret;
-+	}
-+
-+	if (priv->data.phy_control)
-+		(*priv->data.phy_control)(true);
-+
-+	reg = __raw_readl(&priv->regs->id_ver);
-+
-+	msg(info, ifup, "initializing cpsw version %d.%d (%d)\n",
-+	    (reg >> 8 & 0x7), reg & 0xff, (reg >> 11) & 0x1f);
-+
-+	/* initialize host and slave ports */
-+	cpsw_init_host_port(priv);
-+	for_each_slave(priv, cpsw_slave_open, priv);
-+
-+	/* setup tx dma to fixed prio and zero offset */
-+	cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
-+	cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
-+
-+	/* disable priority elevation and enable statistics on all ports */
-+	__raw_writel(0, &priv->regs->ptype);
-+
-+	/* enable statistics collection only on the host port */
-+	/* __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); */
-+	__raw_writel(0x7, &priv->regs->stat_port_en);
-+
-+	if (WARN_ON(!priv->data.rx_descs))
-+		priv->data.rx_descs = 128;
-+
-+	for (i = 0; i < priv->data.rx_descs; i++) {
-+		struct sk_buff *skb;
-+
-+		ret = -ENOMEM;
-+		skb = netdev_alloc_skb_ip_align(priv->ndev,
-+						priv->rx_packet_max);
-+		if (!skb)
-+			break;
-+		ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
-+					skb_tailroom(skb), GFP_KERNEL);
-+		if (WARN_ON(ret < 0))
-+			break;
-+	}
-+	/* continue even if we didn't manage to submit all receive descs */
-+	msg(info, ifup, "submitted %d rx descriptors\n", i);
-+
-+	/* Enable Interrupt pacing if configured */
-+	if (priv->coal_intvl != 0) {
-+		struct ethtool_coalesce coal;
-+
-+		coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
-+		cpsw_set_coalesce(ndev, &coal);
-+	}
-+
-+	/* Enable Timer for capturing cpsw rx interrupts */
-+	omap_dm_timer_set_int_enable(dmtimer_rx, OMAP_TIMER_INT_CAPTURE);
-+	omap_dm_timer_set_capture(dmtimer_rx, 1, 0, 0);
-+	omap_dm_timer_enable(dmtimer_rx);
-+
-+	/* Enable Timer for capturing cpsw tx interrupts */
-+	omap_dm_timer_set_int_enable(dmtimer_tx, OMAP_TIMER_INT_CAPTURE);
-+	omap_dm_timer_set_capture(dmtimer_tx, 1, 0, 0);
-+	omap_dm_timer_enable(dmtimer_tx);
-+
-+	cpdma_ctlr_start(priv->dma);
-+	cpsw_intr_enable(priv);
-+	napi_enable(&priv->napi);
-+	cpdma_ctlr_eoi(priv->dma);
-+
-+	return 0;
-+}
-+
-+static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
-+{
-+	if (!slave->phy)
-+		return;
-+	phy_stop(slave->phy);
-+	phy_disconnect(slave->phy);
-+	slave->phy = NULL;
-+}
-+
-+static int cpsw_ndo_stop(struct net_device *ndev)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+
-+	msg(info, ifdown, "shutting down cpsw device\n");
-+	cpsw_intr_disable(priv);
-+	cpdma_ctlr_int_ctrl(priv->dma, false);
-+
-+	omap_dm_timer_set_int_enable(dmtimer_rx, 0);
-+	omap_dm_timer_set_int_enable(dmtimer_tx, 0);
-+
-+	netif_stop_queue(priv->ndev);
-+	napi_disable(&priv->napi);
-+	netif_carrier_off(priv->ndev);
-+	cpdma_ctlr_stop(priv->dma);
-+	cpsw_ale_stop(priv->ale);
-+	device_remove_file(&ndev->dev, &dev_attr_hw_stats);
-+	for_each_slave(priv, cpsw_slave_stop, priv);
-+	if (priv->data.phy_control)
-+		(*priv->data.phy_control)(false);
-+	clk_disable(priv->clk);
-+	return 0;
-+}
-+
-+static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
-+				       struct net_device *ndev)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+	int ret;
-+
-+	ndev->trans_start = jiffies;
-+
-+	ret = skb_padto(skb, CPSW_MIN_PACKET_SIZE);
-+	if (unlikely(ret < 0)) {
-+		msg(err, tx_err, "packet pad failed");
-+		goto fail;
-+	}
-+
-+	ret = cpdma_chan_submit(priv->txch, skb, skb->data,
-+				skb->len, GFP_KERNEL);
-+	if (unlikely(ret != 0)) {
-+		msg(err, tx_err, "desc submit failed");
-+		goto fail;
-+	}
-+
-+	return NETDEV_TX_OK;
-+fail:
-+	priv->stats.tx_dropped++;
-+	netif_stop_queue(ndev);
-+	return NETDEV_TX_BUSY;
-+}
-+
-+static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
-+{
-+	/*
-+	 * The switch cannot operate in promiscuous mode without substantial
-+	 * headache.  For promiscuous mode to work, we would need to put the
-+	 * ALE in bypass mode and route all traffic to the host port.
-+	 * Subsequently, the host will need to operate as a "bridge", learn,
-+	 * and flood as needed.  For now, we simply complain here and
-+	 * do nothing about it :-)
-+	 */
-+	if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
-+		dev_err(&ndev->dev, "promiscuity ignored!\n");
-+
-+	/*
-+	 * The switch cannot filter multicast traffic unless it is configured
-+	 * in "VLAN Aware" mode.  Unfortunately, VLAN awareness requires a
-+	 * whole bunch of additional logic that this driver does not implement
-+	 * at present.
-+	 */
-+	if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
-+		dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
-+}
-+
-+static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+	struct sockaddr *addr = (struct sockaddr *)p;
-+
-+	if (!is_valid_ether_addr(addr->sa_data))
-+		return -EADDRNOTAVAIL;
-+
-+	cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port);
-+
-+	memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
-+	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
-+
-+	cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
-+			   0);
-+	/* ALE_SECURE); */
-+	for_each_slave(priv, cpsw_set_slave_mac, priv);
-+	return 0;
-+}
-+
-+static void cpsw_ndo_tx_timeout(struct net_device *ndev)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+
-+	msg(err, tx_err, "transmit timeout, restarting dma");
-+	priv->stats.tx_errors++;
-+	cpsw_intr_disable(priv);
-+	cpdma_ctlr_int_ctrl(priv->dma, false);
-+	cpdma_chan_stop(priv->txch);
-+	cpdma_chan_start(priv->txch);
-+	cpdma_ctlr_int_ctrl(priv->dma, true);
-+	cpsw_intr_enable(priv);
-+	cpdma_ctlr_eoi(priv->dma);
-+}
-+
-+static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+	return &priv->stats;
-+}
-+
-+#ifdef CONFIG_NET_POLL_CONTROLLER
-+static void cpsw_ndo_poll_controller(struct net_device *ndev)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+
-+	cpsw_intr_disable(priv);
-+	cpdma_ctlr_int_ctrl(priv->dma, false);
-+	cpsw_interrupt(ndev->irq, priv);
-+	cpdma_ctlr_int_ctrl(priv->dma, true);
-+	cpsw_intr_enable(priv);
-+	cpdma_ctlr_eoi(priv->dma);
-+}
-+#endif
-+
-+/**
-+ * cpsw_get_coalesce : Get interrupt coalesce settings for this device
-+ * @ndev : CPSW network adapter
-+ * @coal : ethtool coalesce settings structure
-+ *
-+ * Fetch the current interrupt coalesce settings
-+ *
-+ */
-+static int cpsw_get_coalesce(struct net_device *ndev,
-+				struct ethtool_coalesce *coal)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+
-+	coal->rx_coalesce_usecs = priv->coal_intvl;
-+	return 0;
-+}
-+
-+/**
-+ * cpsw_set_coalesce : Set interrupt coalesce settings for this device
-+ * @ndev : CPSW network adapter
-+ * @coal : ethtool coalesce settings structure
-+ *
-+ * Set interrupt coalesce parameters
-+ *
-+ */
-+static int cpsw_set_coalesce(struct net_device *ndev,
-+				struct ethtool_coalesce *coal)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+	u32 int_ctrl;
-+	u32 num_interrupts = 0;
-+	u32 prescale = 0;
-+	u32 addnl_dvdr = 1;
-+	u32 coal_intvl = 0;
-+
-+	if (!coal->rx_coalesce_usecs)
-+		return -EINVAL;
-+
-+	coal_intvl = coal->rx_coalesce_usecs;
-+
-+	int_ctrl =  __raw_readl(&priv->ss_regs->int_control);
-+	prescale = priv->bus_freq_mhz * 4;
-+
-+	if (coal_intvl < CPSW_CMINTMIN_INTVL)
-+		coal_intvl = CPSW_CMINTMIN_INTVL;
-+
-+	if (coal_intvl > CPSW_CMINTMAX_INTVL) {
-+		/*
-+		 * Interrupt pacer works with 4us Pulse, we can
-+		 * throttle further by dilating the 4us pulse.
-+		 */
-+		addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
-+
-+		if (addnl_dvdr > 1) {
-+			prescale *= addnl_dvdr;
-+			if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
-+				coal_intvl = (CPSW_CMINTMAX_INTVL
-+						* addnl_dvdr);
-+		} else {
-+			addnl_dvdr = 1;
-+			coal_intvl = CPSW_CMINTMAX_INTVL;
-+		}
-+	}
-+
-+	num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
-+
-+	int_ctrl |= CPSW_INTPACEEN;
-+	int_ctrl &= (~CPSW_INTPRESCALE_MASK);
-+	int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
-+	__raw_writel(int_ctrl, &priv->ss_regs->int_control);
-+
-+	__raw_writel(num_interrupts, &priv->ss_regs->rx_imax);
-+	__raw_writel(num_interrupts, &priv->ss_regs->tx_imax);
-+
-+	printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
-+	priv->coal_intvl = coal_intvl;
-+
-+	return 0;
-+}
-+
-+static const struct net_device_ops cpsw_netdev_ops = {
-+	.ndo_open		= cpsw_ndo_open,
-+	.ndo_stop		= cpsw_ndo_stop,
-+	.ndo_start_xmit		= cpsw_ndo_start_xmit,
-+	.ndo_change_rx_flags	= cpsw_ndo_change_rx_flags,
-+	.ndo_set_mac_address	= cpsw_ndo_set_mac_address,
-+	.ndo_validate_addr	= eth_validate_addr,
-+	.ndo_tx_timeout		= cpsw_ndo_tx_timeout,
-+	.ndo_get_stats		= cpsw_ndo_get_stats,
-+#ifdef CONFIG_NET_POLL_CONTROLLER
-+	.ndo_poll_controller	= cpsw_ndo_poll_controller,
-+#endif
-+};
-+
-+static void cpsw_get_drvinfo(struct net_device *ndev,
-+			     struct ethtool_drvinfo *info)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+	strcpy(info->driver, "TI CPSW Driver v1.0");
-+	strcpy(info->version, "1.0");
-+	strcpy(info->bus_info, priv->pdev->name);
-+}
-+
-+static u32 cpsw_get_msglevel(struct net_device *ndev)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+	return priv->msg_enable;
-+}
-+
-+static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
-+{
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+	priv->msg_enable = value;
-+}
-+
-+static const struct ethtool_ops cpsw_ethtool_ops = {
-+	.get_drvinfo	= cpsw_get_drvinfo,
-+	.get_msglevel	= cpsw_get_msglevel,
-+	.set_msglevel	= cpsw_set_msglevel,
-+	.get_link	= ethtool_op_get_link,
-+	.get_coalesce	= cpsw_get_coalesce,
-+	.set_coalesce	= cpsw_set_coalesce,
-+};
-+
-+static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
-+{
-+	void __iomem		*regs = priv->regs;
-+	int			slave_num = slave->slave_num;
-+	struct cpsw_slave_data	*data = priv->data.slave_data + slave_num;
-+
-+	slave->data	= data;
-+	slave->regs	= regs + data->slave_reg_ofs;
-+	slave->sliver	= regs + data->sliver_reg_ofs;
-+}
-+
-+static int __devinit cpsw_probe(struct platform_device *pdev)
-+{
-+	struct cpsw_platform_data	*data = pdev->dev.platform_data;
-+	struct net_device		*ndev;
-+	struct cpsw_priv		*priv;
-+	struct cpdma_params		dma_params;
-+	struct cpsw_ale_params		ale_params;
-+	void __iomem			*regs;
-+	int ret = 0, i, k = 0;
-+
-+	if (!data) {
-+		pr_err("cpsw: platform data missing\n");
-+		return -ENODEV;
-+	}
-+
-+	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
-+	if (!ndev) {
-+		pr_err("cpsw: error allocating net_device\n");
-+		return -ENOMEM;
-+	}
-+
-+	platform_set_drvdata(pdev, ndev);
-+	priv = netdev_priv(ndev);
-+	spin_lock_init(&priv->lock);
-+	priv->data = *data;
-+	priv->pdev = pdev;
-+	priv->ndev = ndev;
-+	priv->dev  = &ndev->dev;
-+	priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
-+	priv->rx_packet_max = max(rx_packet_max, 128);
-+
-+	if (is_valid_ether_addr(data->mac_addr)) {
-+		memcpy(priv->mac_addr, data->mac_addr, ETH_ALEN);
-+		printk(KERN_INFO"Detected MACID=%x:%x:%x:%x:%x:%x\n",
-+			priv->mac_addr[0], priv->mac_addr[1],
-+			priv->mac_addr[2], priv->mac_addr[3],
-+			priv->mac_addr[4], priv->mac_addr[5]);
-+	} else {
-+		random_ether_addr(priv->mac_addr);
-+		printk(KERN_INFO"Random MACID=%x:%x:%x:%x:%x:%x\n",
-+			priv->mac_addr[0], priv->mac_addr[1],
-+			priv->mac_addr[2], priv->mac_addr[3],
-+			priv->mac_addr[4], priv->mac_addr[5]);
-+	}
-+
-+	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
-+
-+	priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
-+			       GFP_KERNEL);
-+	if (!priv->slaves) {
-+		dev_err(priv->dev, "failed to allocate slave ports\n");
-+		ret = -EBUSY;
-+		goto clean_ndev_ret;
-+	}
-+	for (i = 0; i < data->slaves; i++)
-+		priv->slaves[i].slave_num = i;
-+
-+	priv->clk = clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(priv->clk))
-+		dev_err(priv->dev, "failed to get device clock\n");
-+
-+	priv->coal_intvl = 0;
-+	priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
-+
-+	priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!priv->cpsw_res) {
-+		dev_err(priv->dev, "error getting i/o resource\n");
-+		ret = -ENOENT;
-+		goto clean_clk_ret;
-+	}
-+
-+	if (!request_mem_region(priv->cpsw_res->start,
-+		resource_size(priv->cpsw_res), ndev->name)) {
-+		dev_err(priv->dev, "failed request i/o region\n");
-+		ret = -ENXIO;
-+		goto clean_clk_ret;
-+	}
-+
-+	regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
-+	if (!regs) {
-+		dev_err(priv->dev, "unable to map i/o region\n");
-+		goto clean_cpsw_iores_ret;
-+	}
-+	priv->regs = regs;
-+	priv->host_port = data->host_port_num;
-+	priv->host_port_regs = regs + data->host_port_reg_ofs;
-+	priv->hw_stats = regs + data->hw_stats_reg_ofs;
-+
-+	priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	if (!priv->cpsw_ss_res) {
-+		dev_err(priv->dev, "error getting i/o resource\n");
-+		ret = -ENOENT;
-+		goto clean_clk_ret;
-+	}
-+
-+	if (!request_mem_region(priv->cpsw_ss_res->start,
-+		resource_size(priv->cpsw_ss_res), ndev->name)) {
-+		dev_err(priv->dev, "failed request i/o region\n");
-+		ret = -ENXIO;
-+		goto clean_clk_ret;
-+	}
-+
-+	regs = ioremap(priv->cpsw_ss_res->start,
-+			resource_size(priv->cpsw_ss_res));
-+	if (!regs) {
-+		dev_err(priv->dev, "unable to map i/o region\n");
-+		goto clean_cpsw_ss_iores_ret;
-+	}
-+	priv->ss_regs = regs;
-+
-+
-+	for_each_slave(priv, cpsw_slave_init, priv);
-+
-+	omap_ctrl_writel(CPSW_TIMER_MASK, CPSW_TIMER_CAP_REG);
-+
-+	dmtimer_rx = omap_dm_timer_request_specific(CPSW_RX_TIMER_REQ);
-+	if (!dmtimer_rx) {
-+		dev_err(priv->dev, "Error getting Rx Timer resource\n");
-+		ret = -ENODEV;
-+		goto clean_iomap_ret;
-+	}
-+	dmtimer_tx = omap_dm_timer_request_specific(CPSW_TX_TIMER_REQ);
-+	if (!dmtimer_tx) {
-+		dev_err(priv->dev, "Error getting Tx Timer resource\n");
-+		ret = -ENODEV;
-+		goto clean_timer_rx_ret;
-+	}
-+
-+	memset(&dma_params, 0, sizeof(dma_params));
-+	dma_params.dev			= &pdev->dev;
-+	dma_params.dmaregs		= (void __iomem *)(((u32)priv->regs) +
-+						data->cpdma_reg_ofs);
-+	dma_params.rxthresh		= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_RXTHRESH);
-+	dma_params.rxfree		= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_RXFREE);
-+
-+	if (data->version == CPSW_VERSION_2) {
-+		dma_params.txhdp	= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_TXHDP_VER2);
-+		dma_params.rxhdp	= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_RXHDP_VER2);
-+		dma_params.txcp		= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_TXCP_VER2);
-+		dma_params.rxcp		= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_RXCP_VER2);
-+	} else {
-+		dma_params.txhdp	= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_TXHDP_VER1);
-+		dma_params.rxhdp	= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_RXHDP_VER1);
-+		dma_params.txcp		= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_TXCP_VER1);
-+		dma_params.rxcp		= (void __iomem *)(((u32)priv->regs) +
-+					data->cpdma_reg_ofs + CPDMA_RXCP_VER1);
-+	}
-+
-+	dma_params.num_chan		= data->channels;
-+	dma_params.has_soft_reset	= true;
-+	dma_params.min_packet_size	= CPSW_MIN_PACKET_SIZE;
-+	dma_params.desc_mem_size	= data->bd_ram_size;
-+	dma_params.desc_align		= 16;
-+	dma_params.has_ext_regs		= true;
-+	dma_params.desc_mem_phys	= data->no_bd_ram ? 0 :
-+			(u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
-+	dma_params.desc_hw_addr		= data->hw_ram_addr ?
-+				data->hw_ram_addr : dma_params.desc_mem_phys ;
-+
-+	priv->dma = cpdma_ctlr_create(&dma_params);
-+	if (!priv->dma) {
-+		dev_err(priv->dev, "error initializing dma\n");
-+		ret = -ENOMEM;
-+		goto clean_timer_ret;
-+	}
-+
-+	priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
-+				       cpsw_tx_handler);
-+	priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
-+				       cpsw_rx_handler);
-+
-+	if (WARN_ON(!priv->txch || !priv->rxch)) {
-+		dev_err(priv->dev, "error initializing dma channels\n");
-+		ret = -ENOMEM;
-+		goto clean_dma_ret;
-+	}
-+
-+	memset(&ale_params, 0, sizeof(ale_params));
-+	ale_params.dev		= &ndev->dev;
-+	ale_params.ale_regs	= (void *)((u32)priv->regs) +
-+					((u32)data->ale_reg_ofs);
-+	ale_params.ale_ageout	= ale_ageout;
-+	ale_params.ale_entries	= data->ale_entries;
-+	ale_params.ale_ports	= data->slaves;
-+
-+	priv->ale = cpsw_ale_create(&ale_params);
-+	if (!priv->ale) {
-+		dev_err(priv->dev, "error initializing ale engine\n");
-+		ret = -ENODEV;
-+		goto clean_dma_ret;
-+	}
-+
-+	while ((i = platform_get_irq(pdev, k)) >= 0) {
-+		if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
-+				dev_name(&pdev->dev), priv)) {
-+			dev_err(priv->dev, "error attaching irq\n");
-+			goto clean_ale_ret;
-+		}
-+		priv->irqs_table[k] = i;
-+		priv->num_irqs = ++k;
-+	}
-+
-+	ndev->flags |= IFF_ALLMULTI;	/* see cpsw_ndo_change_rx_flags() */
-+
-+	ndev->netdev_ops = &cpsw_netdev_ops;
-+	SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
-+	netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
-+
-+	/* register the network device */
-+	SET_NETDEV_DEV(ndev, &pdev->dev);
-+	ret = register_netdev(ndev);
-+	if (ret) {
-+		dev_err(priv->dev, "error registering net device\n");
-+		ret = -ENODEV;
-+		goto clean_irq_ret;
-+	}
-+
-+	msg(notice, probe, "initialized device (regs %x, irq %d)\n",
-+	    priv->cpsw_res->start, ndev->irq);
-+
-+	return 0;
-+
-+clean_irq_ret:
-+	free_irq(ndev->irq, priv);
-+clean_ale_ret:
-+	cpsw_ale_destroy(priv->ale);
-+clean_dma_ret:
-+	cpdma_chan_destroy(priv->txch);
-+	cpdma_chan_destroy(priv->rxch);
-+	cpdma_ctlr_destroy(priv->dma);
-+clean_timer_ret:
-+	omap_dm_timer_free(dmtimer_tx);
-+clean_timer_rx_ret:
-+	omap_dm_timer_free(dmtimer_rx);
-+clean_iomap_ret:
-+	iounmap(priv->regs);
-+clean_cpsw_ss_iores_ret:
-+	release_mem_region(priv->cpsw_ss_res->start,
-+				resource_size(priv->cpsw_ss_res));
-+clean_cpsw_iores_ret:
-+	release_mem_region(priv->cpsw_res->start,
-+				resource_size(priv->cpsw_res));
-+clean_clk_ret:
-+	clk_put(priv->clk);
-+	kfree(priv->slaves);
-+clean_ndev_ret:
-+	free_netdev(ndev);
-+	return ret;
-+}
-+
-+static int __devexit cpsw_remove(struct platform_device *pdev)
-+{
-+	struct net_device *ndev = platform_get_drvdata(pdev);
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+	u32 i;
-+
-+	msg(notice, probe, "removing device\n");
-+	platform_set_drvdata(pdev, NULL);
-+
-+	omap_dm_timer_free(dmtimer_rx);
-+	omap_dm_timer_free(dmtimer_tx);
-+	for (i = 0; i < priv->num_irqs; i++)
-+		free_irq(priv->irqs_table[i], priv);
-+	cpsw_ale_destroy(priv->ale);
-+	cpdma_chan_destroy(priv->txch);
-+	cpdma_chan_destroy(priv->rxch);
-+	cpdma_ctlr_destroy(priv->dma);
-+	iounmap(priv->regs);
-+	release_mem_region(priv->cpsw_res->start,
-+				resource_size(priv->cpsw_res));
-+	release_mem_region(priv->cpsw_ss_res->start,
-+				resource_size(priv->cpsw_ss_res));
-+	clk_put(priv->clk);
-+	kfree(priv->slaves);
-+	unregister_netdev(ndev);
-+	free_netdev(ndev);
-+
-+	return 0;
-+}
-+
-+static int cpsw_suspend(struct device *dev)
-+{
-+	struct platform_device	*pdev = to_platform_device(dev);
-+	struct net_device	*ndev = platform_get_drvdata(pdev);
-+	struct cpsw_priv *priv = netdev_priv(ndev);
-+
-+	if (netif_running(ndev))
-+		cpsw_ndo_stop(ndev);
-+
-+	soft_reset("cpsw", &priv->regs->soft_reset);
-+	soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset);
-+	soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset);
-+	soft_reset("cpsw_ss", &priv->ss_regs->soft_reset);
-+
-+	return 0;
-+}
-+
-+static int cpsw_resume(struct device *dev)
-+{
-+	struct platform_device	*pdev = to_platform_device(dev);
-+	struct net_device	*ndev = platform_get_drvdata(pdev);
-+
-+	if (netif_running(ndev))
-+		cpsw_ndo_open(ndev);
-+	return 0;
-+}
-+
-+static const struct dev_pm_ops cpsw_pm_ops = {
-+	.suspend	= cpsw_suspend,
-+	.resume		= cpsw_resume,
-+};
-+
-+static struct platform_driver cpsw_driver = {
-+	.driver = {
-+		.name	 = "cpsw",
-+		.owner	 = THIS_MODULE,
-+		.pm	 = &cpsw_pm_ops,
-+	},
-+	.probe = cpsw_probe,
-+	.remove = __devexit_p(cpsw_remove),
-+};
-+
-+static int __init cpsw_init(void)
-+{
-+	return platform_driver_register(&cpsw_driver);
-+}
-+late_initcall(cpsw_init);
-+
-+static void __exit cpsw_exit(void)
-+{
-+	platform_driver_unregister(&cpsw_driver);
-+}
-+module_exit(cpsw_exit);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("TI CPSW Ethernet driver");
-diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c
-new file mode 100644
-index 0000000..9639c31
---- /dev/null
-+++ b/drivers/net/ethernet/ti/cpsw_ale.c
-@@ -0,0 +1,702 @@
-+/*
-+ * Texas Instruments 3-Port Ethernet Switch Address Lookup Engine
-+ *
-+ * Copyright (C) 2010 Texas Instruments
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/seq_file.h>
-+#include <linux/slab.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/stat.h>
-+#include <linux/sysfs.h>
-+#include <linux/export.h>
-+#include <linux/module.h>
-+
-+#include "cpsw_ale.h"
-+
-+#define BITMASK(bits)		(BIT(bits) - 1)
-+#define ADDR_FMT_STR		"%02x:%02x:%02x:%02x:%02x:%02x"
-+#define ADDR_FMT_ARGS(addr)	(addr)[0], (addr)[1], (addr)[2], \
-+				(addr)[3], (addr)[4], (addr)[5]
-+#define ALE_ENTRY_BITS		68
-+#define ALE_ENTRY_WORDS		DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
-+
-+/* ALE Registers */
-+#define ALE_IDVER		0x00
-+#define ALE_CONTROL		0x08
-+#define ALE_PRESCALE		0x10
-+#define ALE_UNKNOWNVLAN		0x18
-+#define ALE_TABLE_CONTROL	0x20
-+#define ALE_TABLE		0x34
-+#define ALE_PORTCTL		0x40
-+
-+#define ALE_TABLE_WRITE		BIT(31)
-+
-+#define ALE_TYPE_FREE			0
-+#define ALE_TYPE_ADDR			1
-+#define ALE_TYPE_VLAN			2
-+#define ALE_TYPE_VLAN_ADDR		3
-+
-+#define ALE_UCAST_PERSISTANT		0
-+#define ALE_UCAST_UNTOUCHED		1
-+#define ALE_UCAST_OUI			2
-+#define ALE_UCAST_TOUCHED		3
-+
-+#define ALE_MCAST_FWD			0
-+#define ALE_MCAST_BLOCK_LEARN_FWD	1
-+#define ALE_MCAST_FWD_LEARN		2
-+#define ALE_MCAST_FWD_2			3
-+
-+/* the following remap params into members of cpsw_ale */
-+#define ale_regs	params.ale_regs
-+#define ale_entries	params.ale_entries
-+#define ale_ports	params.ale_ports
-+
-+static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
-+{
-+	int idx;
-+
-+	idx    = start / 32;
-+	start -= idx * 32;
-+	idx    = 2 - idx; /* flip */
-+	return (ale_entry[idx] >> start) & BITMASK(bits);
-+}
-+
-+static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
-+				      u32 value)
-+{
-+	int idx;
-+
-+	value &= BITMASK(bits);
-+	idx    = start / 32;
-+	start -= idx * 32;
-+	idx    = 2 - idx; /* flip */
-+	ale_entry[idx] &= ~(BITMASK(bits) << start);
-+	ale_entry[idx] |=  (value << start);
-+}
-+
-+#define DEFINE_ALE_FIELD(name, start, bits)				\
-+static inline int cpsw_ale_get_##name(u32 *ale_entry)			\
-+{									\
-+	return cpsw_ale_get_field(ale_entry, start, bits);		\
-+}									\
-+static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)	\
-+{									\
-+	cpsw_ale_set_field(ale_entry, start, bits, value);		\
-+}
-+
-+DEFINE_ALE_FIELD(entry_type,		60,	2)
-+DEFINE_ALE_FIELD(vlan_id,		48,	12)
-+DEFINE_ALE_FIELD(mcast_state,		62,	2)
-+DEFINE_ALE_FIELD(port_mask,		66,     3)
-+DEFINE_ALE_FIELD(super,			65,	1)
-+DEFINE_ALE_FIELD(ucast_type,		62,     2)
-+DEFINE_ALE_FIELD(port_num,		66,     2)
-+DEFINE_ALE_FIELD(blocked,		65,     1)
-+DEFINE_ALE_FIELD(secure,		64,     1)
-+DEFINE_ALE_FIELD(vlan_untag_force,	24,	3)
-+DEFINE_ALE_FIELD(vlan_reg_mcast,	16,	3)
-+DEFINE_ALE_FIELD(vlan_unreg_mcast,	8,	3)
-+DEFINE_ALE_FIELD(vlan_member_list,	0,	3)
-+DEFINE_ALE_FIELD(mcast,			40,     1)
-+
-+/* The MAC address field in the ALE entry cannot be macroized as above */
-+static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
-+{
-+	int i;
-+
-+	for (i = 0; i < 6; i++)
-+		addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
-+}
-+
-+static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
-+{
-+	int i;
-+
-+	for (i = 0; i < 6; i++)
-+		cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
-+}
-+
-+static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
-+{
-+	int i;
-+
-+	WARN_ON(idx > ale->ale_entries);
-+
-+	__raw_writel(idx, ale->ale_regs + ALE_TABLE_CONTROL);
-+
-+	for (i = 0; i < ALE_ENTRY_WORDS; i++)
-+		ale_entry[i] = __raw_readl(ale->ale_regs + ALE_TABLE + 4 * i);
-+
-+	return idx;
-+}
-+
-+static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
-+{
-+	int i;
-+
-+	WARN_ON(idx > ale->ale_entries);
-+
-+	for (i = 0; i < ALE_ENTRY_WORDS; i++)
-+		__raw_writel(ale_entry[i], ale->ale_regs + ALE_TABLE + 4 * i);
-+
-+	__raw_writel(idx | ALE_TABLE_WRITE, ale->ale_regs + ALE_TABLE_CONTROL);
-+
-+	return idx;
-+}
-+
-+static int cpsw_ale_match_addr(struct cpsw_ale *ale, u8* addr)
-+{
-+	u32 ale_entry[ALE_ENTRY_WORDS];
-+	int type, idx;
-+
-+	for (idx = 0; idx < ale->ale_entries; idx++) {
-+		u8 entry_addr[6];
-+
-+		cpsw_ale_read(ale, idx, ale_entry);
-+		type = cpsw_ale_get_entry_type(ale_entry);
-+		if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
-+			continue;
-+		cpsw_ale_get_addr(ale_entry, entry_addr);
-+		if (memcmp(entry_addr, addr, 6) == 0)
-+			return idx;
-+	}
-+	return -ENOENT;
-+}
-+
-+static int cpsw_ale_match_free(struct cpsw_ale *ale)
-+{
-+	u32 ale_entry[ALE_ENTRY_WORDS];
-+	int type, idx;
-+
-+	for (idx = 0; idx < ale->ale_entries; idx++) {
-+		cpsw_ale_read(ale, idx, ale_entry);
-+		type = cpsw_ale_get_entry_type(ale_entry);
-+		if (type == ALE_TYPE_FREE)
-+			return idx;
-+	}
-+	return -ENOENT;
-+}
-+
-+static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
-+{
-+	u32 ale_entry[ALE_ENTRY_WORDS];
-+	int type, idx;
-+
-+	for (idx = 0; idx < ale->ale_entries; idx++) {
-+		cpsw_ale_read(ale, idx, ale_entry);
-+		type = cpsw_ale_get_entry_type(ale_entry);
-+		if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
-+			continue;
-+		if (cpsw_ale_get_mcast(ale_entry))
-+			continue;
-+		type = cpsw_ale_get_ucast_type(ale_entry);
-+		if (type != ALE_UCAST_PERSISTANT &&
-+		    type != ALE_UCAST_OUI)
-+			return idx;
-+	}
-+	return -ENOENT;
-+}
-+
-+static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
-+				 int port_mask)
-+{
-+	int mask;
-+
-+	mask = cpsw_ale_get_port_mask(ale_entry);
-+	if ((mask & port_mask) == 0)
-+		return; /* ports dont intersect, not interested */
-+	mask &= ~port_mask;
-+
-+	/* free if only remaining port is host port */
-+	if (mask == BIT(ale->ale_ports))
-+		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
-+	else
-+		cpsw_ale_set_port_mask(ale_entry, mask);
-+}
-+
-+static void cpsw_ale_flush_ucast(struct cpsw_ale *ale, u32 *ale_entry,
-+				 int port_mask)
-+{
-+	int port;
-+
-+	port = cpsw_ale_get_port_num(ale_entry);
-+	if ((BIT(port) & port_mask) == 0)
-+		return; /* ports dont intersect, not interested */
-+	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
-+}
-+
-+int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask)
-+{
-+	u32 ale_entry[ALE_ENTRY_WORDS];
-+	int ret, idx;
-+
-+	for (idx = 0; idx < ale->ale_entries; idx++) {
-+		cpsw_ale_read(ale, idx, ale_entry);
-+		ret = cpsw_ale_get_entry_type(ale_entry);
-+		if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
-+			continue;
-+
-+		if (cpsw_ale_get_mcast(ale_entry))
-+			cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
-+		else
-+			cpsw_ale_flush_ucast(ale, ale_entry, port_mask);
-+
-+		cpsw_ale_write(ale, idx, ale_entry);
-+	}
-+	return 0;
-+}
-+
-+static int cpsw_ale_dump_mcast(u32 *ale_entry, char *buf, int len)
-+{
-+	int outlen = 0;
-+	static const char *str_mcast_state[] = {"f", "blf", "lf", "f"};
-+	int mcast_state = cpsw_ale_get_mcast_state(ale_entry);
-+	int port_mask   = cpsw_ale_get_port_mask(ale_entry);
-+	int super       = cpsw_ale_get_super(ale_entry);
-+
-+	outlen += snprintf(buf + outlen, len - outlen,
-+			   "mcstate: %s(%d), ", str_mcast_state[mcast_state],
-+			   mcast_state);
-+	outlen += snprintf(buf + outlen, len - outlen,
-+			   "port mask: %x, %ssuper\n", port_mask,
-+			   super ? "" : "no ");
-+	return outlen;
-+}
-+
-+static int cpsw_ale_dump_ucast(u32 *ale_entry, char *buf, int len)
-+{
-+	int outlen = 0;
-+	static const char *str_ucast_type[] = {"persistant", "untouched",
-+					       "oui", "touched"};
-+	int ucast_type  = cpsw_ale_get_ucast_type(ale_entry);
-+	int port_num    = cpsw_ale_get_port_num(ale_entry);
-+	int secure      = cpsw_ale_get_secure(ale_entry);
-+	int blocked     = cpsw_ale_get_blocked(ale_entry);
-+
-+	outlen += snprintf(buf + outlen, len - outlen,
-+			   "uctype: %s(%d), ", str_ucast_type[ucast_type],
-+			   ucast_type);
-+	outlen += snprintf(buf + outlen, len - outlen,
-+			   "port: %d%s%s\n", port_num, secure ? ", Secure" : "",
-+			   blocked ? ", Blocked" : "");
-+	return outlen;
-+}
-+
-+static int cpsw_ale_dump_entry(int idx, u32 *ale_entry, char *buf, int len)
-+{
-+	int type, outlen = 0;
-+	u8 addr[6];
-+	static const char *str_type[] = {"free", "addr", "vlan", "vlan+addr"};
-+
-+	type = cpsw_ale_get_entry_type(ale_entry);
-+	if (type == ALE_TYPE_FREE)
-+		return outlen;
-+
-+	if (idx >= 0) {
-+		outlen += snprintf(buf + outlen, len - outlen,
-+				   "index %d, ", idx);
-+	}
-+
-+	outlen += snprintf(buf + outlen, len - outlen, "raw: %08x %08x %08x, ",
-+			   ale_entry[0], ale_entry[1], ale_entry[2]);
-+
-+	outlen += snprintf(buf + outlen, len - outlen,
-+			   "type: %s(%d), ", str_type[type], type);
-+
-+	cpsw_ale_get_addr(ale_entry, addr);
-+	outlen += snprintf(buf + outlen, len - outlen,
-+			   "addr: " ADDR_FMT_STR ", ", ADDR_FMT_ARGS(addr));
-+
-+	if (type == ALE_TYPE_VLAN || type == ALE_TYPE_VLAN_ADDR) {
-+		outlen += snprintf(buf + outlen, len - outlen, "vlan: %d, ",
-+				   cpsw_ale_get_vlan_id(ale_entry));
-+	}
-+
-+	outlen += cpsw_ale_get_mcast(ale_entry) ?
-+		  cpsw_ale_dump_mcast(ale_entry, buf + outlen, len - outlen) :
-+		  cpsw_ale_dump_ucast(ale_entry, buf + outlen, len - outlen);
-+
-+	return outlen;
-+}
-+
-+int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags)
-+{
-+	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
-+	int idx;
-+
-+	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
-+	cpsw_ale_set_addr(ale_entry, addr);
-+	cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
-+	cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
-+	cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
-+	cpsw_ale_set_port_num(ale_entry, port);
-+
-+	idx = cpsw_ale_match_addr(ale, addr);
-+	if (idx < 0)
-+		idx = cpsw_ale_match_free(ale);
-+	if (idx < 0)
-+		idx = cpsw_ale_find_ageable(ale);
-+	if (idx < 0)
-+		return -ENOMEM;
-+
-+	cpsw_ale_write(ale, idx, ale_entry);
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_add_ucast);
-+
-+int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port)
-+{
-+	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
-+	int idx;
-+
-+	idx = cpsw_ale_match_addr(ale, addr);
-+	if (idx < 0)
-+		return -ENOENT;
-+
-+	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
-+	cpsw_ale_write(ale, idx, ale_entry);
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_del_ucast);
-+
-+int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask)
-+{
-+	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
-+	int idx, mask;
-+
-+	idx = cpsw_ale_match_addr(ale, addr);
-+	if (idx >= 0)
-+		cpsw_ale_read(ale, idx, ale_entry);
-+
-+	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
-+	cpsw_ale_set_addr(ale_entry, addr);
-+	cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
-+
-+	mask = cpsw_ale_get_port_mask(ale_entry);
-+	port_mask |= mask;
-+	cpsw_ale_set_port_mask(ale_entry, port_mask);
-+
-+	if (idx < 0)
-+		idx = cpsw_ale_match_free(ale);
-+	if (idx < 0)
-+		idx = cpsw_ale_find_ageable(ale);
-+	if (idx < 0)
-+		return -ENOMEM;
-+
-+	cpsw_ale_write(ale, idx, ale_entry);
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_add_mcast);
-+
-+int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask)
-+{
-+	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
-+	int idx, mask;
-+
-+	idx = cpsw_ale_match_addr(ale, addr);
-+	if (idx < 0)
-+		return -EINVAL;
-+
-+	cpsw_ale_read(ale, idx, ale_entry);
-+	mask = cpsw_ale_get_port_mask(ale_entry);
-+	port_mask = mask & ~port_mask;
-+
-+	if (port_mask == BIT(ale->ale_ports))
-+		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
-+	else
-+		cpsw_ale_set_port_mask(ale_entry, port_mask);
-+
-+	cpsw_ale_write(ale, idx, ale_entry);
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_del_mcast);
-+
-+struct ale_control_info {
-+	const char	*name;
-+	int		offset, port_offset;
-+	int		shift, port_shift;
-+	int		bits;
-+};
-+
-+#define CTRL_GLOBAL(name, bit)		{#name, ALE_CONTROL, 0, bit, 0, 1}
-+#define CTRL_UNK(name, bit)		{#name, ALE_UNKNOWNVLAN, 0, bit, 1, 1}
-+#define CTRL_PORTCTL(name, start, bits)	{#name, ALE_PORTCTL, 4, start, 0, bits}
-+
-+static struct ale_control_info ale_controls[] = {
-+	[ALE_ENABLE]		= CTRL_GLOBAL(enable, 31),
-+	[ALE_CLEAR]		= CTRL_GLOBAL(clear, 30),
-+	[ALE_AGEOUT]		= CTRL_GLOBAL(ageout, 29),
-+	[ALE_VLAN_NOLEARN]	= CTRL_GLOBAL(vlan_nolearn, 7),
-+	[ALE_NO_PORT_VLAN]	= CTRL_GLOBAL(no_port_vlan, 6),
-+	[ALE_OUI_DENY]		= CTRL_GLOBAL(oui_deny, 5),
-+	[ALE_BYPASS]		= CTRL_GLOBAL(bypass, 4),
-+	[ALE_RATE_LIMIT_TX]	= CTRL_GLOBAL(rate_limit_tx, 3),
-+	[ALE_VLAN_AWARE]	= CTRL_GLOBAL(vlan_aware, 2),
-+	[ALE_AUTH_ENABLE]	= CTRL_GLOBAL(auth_enable, 1),
-+	[ALE_RATE_LIMIT]	= CTRL_GLOBAL(rate_limit, 0),
-+
-+	[ALE_PORT_STATE]	     = CTRL_PORTCTL(port_state, 0, 2),
-+	[ALE_PORT_DROP_UNTAGGED]     = CTRL_PORTCTL(drop_untagged, 2, 1),
-+	[ALE_PORT_DROP_UNKNOWN_VLAN] = CTRL_PORTCTL(drop_unknown, 3, 1),
-+	[ALE_PORT_NOLEARN]	     = CTRL_PORTCTL(nolearn, 4, 1),
-+	[ALE_PORT_MCAST_LIMIT]	     = CTRL_PORTCTL(mcast_limit, 16, 8),
-+	[ALE_PORT_BCAST_LIMIT]	     = CTRL_PORTCTL(bcast_limit, 24, 8),
-+
-+	[ALE_PORT_UNKNOWN_VLAN_MEMBER]	   = CTRL_UNK(unknown_vlan_member, 0),
-+	[ALE_PORT_UNKNOWN_MCAST_FLOOD]	   = CTRL_UNK(unknown_mcast_flood, 8),
-+	[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = CTRL_UNK(unknown_reg_flood, 16),
-+	[ALE_PORT_UNTAGGED_EGRESS]	   = CTRL_UNK(untagged_egress, 24),
-+};
-+
-+int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
-+			 int value)
-+{
-+	struct ale_control_info *info = &ale_controls[control];
-+	int offset, shift;
-+	u32 tmp, mask;
-+
-+	if (control < 0 || control >= ARRAY_SIZE(ale_controls))
-+		return -EINVAL;
-+
-+	if (info->port_offset == 0 && info->port_shift == 0)
-+		port = 0; /* global, port is a dont care */
-+
-+	if (port < 0 || port > ale->ale_ports)
-+		return -EINVAL;
-+
-+	mask = BITMASK(info->bits);
-+	if (value & ~mask)
-+		return -EINVAL;
-+
-+	offset = info->offset + (port * info->port_offset);
-+	shift  = info->shift  + (port * info->port_shift);
-+
-+	tmp = __raw_readl(ale->ale_regs + offset);
-+	tmp = (tmp & ~(mask << shift)) | (value << shift);
-+	__raw_writel(tmp, ale->ale_regs + offset);
-+
-+	{
-+		volatile u32 dly = 10000;
-+		while (dly--)
-+			;
-+	}
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_control_set);
-+
-+int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
-+{
-+	struct ale_control_info *info = &ale_controls[control];
-+	int offset, shift;
-+	u32 tmp;
-+
-+	if (control < 0 || control >= ARRAY_SIZE(ale_controls))
-+		return -EINVAL;
-+
-+	if (info->port_offset == 0 && info->port_shift == 0)
-+		port = 0; /* global, port is a dont care */
-+
-+	if (port < 0 || port > ale->ale_ports)
-+		return -EINVAL;
-+
-+	offset = info->offset + (port * info->port_offset);
-+	shift  = info->shift  + (port * info->port_shift);
-+
-+	tmp = __raw_readl(ale->ale_regs + offset) >> shift;
-+	return tmp & BITMASK(info->bits);
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_control_get);
-+
-+static ssize_t cpsw_ale_control_show(struct device *dev,
-+				     struct device_attribute *attr,
-+				     char *buf)
-+{
-+	int i, port, len = 0;
-+	struct ale_control_info *info;
-+	struct cpsw_ale *ale = control_attr_to_ale(attr);
-+
-+	for (i = 0, info = ale_controls; i < ALE_NUM_CONTROLS; i++, info++) {
-+		/* global controls */
-+		if (info->port_shift == 0 &&  info->port_offset == 0) {
-+			len += snprintf(buf + len, SZ_4K - len,
-+					"%s=%d\n", info->name,
-+					cpsw_ale_control_get(ale, 0, i));
-+			continue;
-+		}
-+		/* port specific controls */
-+		for (port = 0; port < ale->ale_ports; port++) {
-+			len += snprintf(buf + len, SZ_4K - len,
-+					"%s.%d=%d\n", info->name, port,
-+					cpsw_ale_control_get(ale, port, i));
-+		}
-+	}
-+	return len;
-+}
-+
-+static ssize_t cpsw_ale_control_store(struct device *dev,
-+				      struct device_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	char ctrl_str[33], *end;
-+	int port = 0, value, len, ret, control;
-+	struct cpsw_ale *ale = control_attr_to_ale(attr);
-+
-+	len = strcspn(buf, ".=");
-+	if (len >= 32)
-+		return -ENOMEM;
-+	strncpy(ctrl_str, buf, len);
-+	ctrl_str[len] = '\0';
-+	buf += len;
-+
-+	if (*buf == '.') {
-+		port = simple_strtoul(buf + 1, &end, 0);
-+		buf = end;
-+	}
-+
-+	if (*buf != '=')
-+		return -EINVAL;
-+
-+	value = simple_strtoul(buf + 1, NULL, 0);
-+
-+	for (control = 0; control < ALE_NUM_CONTROLS; control++)
-+		if (strcmp(ctrl_str, ale_controls[control].name) == 0)
-+			break;
-+
-+	if (control >= ALE_NUM_CONTROLS)
-+		return -ENOENT;
-+
-+	dev_dbg(ale->params.dev, "processing command %s.%d=%d\n",
-+		ale_controls[control].name, port, value);
-+
-+	ret = cpsw_ale_control_set(ale, port, control, value);
-+	if (ret < 0)
-+		return ret;
-+	return count;
-+}
-+
-+DEVICE_ATTR(ale_control, S_IRUGO | S_IWUSR, cpsw_ale_control_show,
-+	    cpsw_ale_control_store);
-+
-+static ssize_t cpsw_ale_table_show(struct device *dev,
-+				   struct device_attribute *attr,
-+				   char *buf)
-+{
-+	int len = SZ_4K, outlen = 0, idx;
-+	u32 ale_entry[ALE_ENTRY_WORDS];
-+	struct cpsw_ale *ale = table_attr_to_ale(attr);
-+
-+	for (idx = 0; idx < ale->ale_entries; idx++) {
-+		cpsw_ale_read(ale, idx, ale_entry);
-+		outlen += cpsw_ale_dump_entry(idx, ale_entry, buf + outlen,
-+					      len - outlen);
-+	}
-+	return outlen;
-+}
-+DEVICE_ATTR(ale_table, S_IRUGO, cpsw_ale_table_show, NULL);
-+
-+static void cpsw_ale_timer(unsigned long arg)
-+{
-+	struct cpsw_ale *ale = (struct cpsw_ale *)arg;
-+
-+	cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
-+
-+	if (ale->ageout) {
-+		ale->timer.expires = jiffies + ale->ageout;
-+		add_timer(&ale->timer);
-+	}
-+}
-+
-+int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout)
-+{
-+	del_timer_sync(&ale->timer);
-+	ale->ageout = ageout * HZ;
-+	if (ale->ageout) {
-+		ale->timer.expires = jiffies + ale->ageout;
-+		add_timer(&ale->timer);
-+	}
-+	return 0;
-+}
-+
-+void cpsw_ale_start(struct cpsw_ale *ale)
-+{
-+	u32 rev;
-+	int ret;
-+
-+	rev = __raw_readl(ale->ale_regs + ALE_IDVER);
-+	dev_dbg(ale->params.dev, "initialized cpsw ale revision %d.%d\n",
-+		(rev >> 8) & 0xff, rev & 0xff);
-+	cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
-+	cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
-+
-+	ale->ale_control_attr = dev_attr_ale_control;
-+	sysfs_attr_init(&ale->ale_control_attr.attr);
-+	ret = device_create_file(ale->params.dev, &ale->ale_control_attr);
-+	WARN_ON(ret < 0);
-+
-+	ale->ale_table_attr = dev_attr_ale_table;
-+	sysfs_attr_init(&ale->ale_table_attr.attr);
-+	ret = device_create_file(ale->params.dev, &ale->ale_table_attr);
-+	WARN_ON(ret < 0);
-+
-+	init_timer(&ale->timer);
-+	ale->timer.data	    = (unsigned long)ale;
-+	ale->timer.function = cpsw_ale_timer;
-+	if (ale->ageout) {
-+		ale->timer.expires = jiffies + ale->ageout;
-+		add_timer(&ale->timer);
-+	}
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_start);
-+
-+void cpsw_ale_stop(struct cpsw_ale *ale)
-+{
-+	cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
-+	del_timer_sync(&ale->timer);
-+	device_remove_file(ale->params.dev, &ale->ale_table_attr);
-+	device_remove_file(ale->params.dev, &ale->ale_control_attr);
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_stop);
-+
-+struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
-+{
-+	struct cpsw_ale *ale;
-+	int ret;
-+
-+	ret = -ENOMEM;
-+	ale = kzalloc(sizeof(*ale), GFP_KERNEL);
-+	if (WARN_ON(!ale))
-+		return NULL;
-+
-+	ale->params = *params;
-+	ale->ageout = ale->params.ale_ageout * HZ;
-+
-+	return ale;
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_create);
-+
-+int cpsw_ale_destroy(struct cpsw_ale *ale)
-+{
-+	if (!ale)
-+		return -EINVAL;
-+	cpsw_ale_stop(ale);
-+	cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
-+	kfree(ale);
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(cpsw_ale_destroy);
-+
-+MODULE_DESCRIPTION("Ethernet Switch Address Lookup Engine driver");
-+MODULE_AUTHOR("Chandan Nath <chandan.nath@ti.com>");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h
-new file mode 100644
-index 0000000..f064a04a
---- /dev/null
-+++ b/drivers/net/ethernet/ti/cpsw_ale.h
-@@ -0,0 +1,93 @@
-+/*
-+ * Texas Instruments 3-Port Ethernet Switch Address Lookup Engine APIs
-+ *
-+ * Copyright (C) 2010 Texas Instruments
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#ifndef __TI_CPSW_ALE_H__
-+#define __TI_CPSW_ALE_H__
-+
-+struct cpsw_ale_params {
-+	struct device		*dev;
-+	void __iomem		*ale_regs;
-+	unsigned long		ale_ageout;	/* in secs */
-+	unsigned long		ale_entries;
-+	unsigned long		ale_ports;
-+};
-+
-+struct cpsw_ale {
-+	struct cpsw_ale_params	params;
-+	struct timer_list	timer;
-+	unsigned long		ageout;
-+	struct device_attribute ale_control_attr;
-+#define control_attr_to_ale(attr)	\
-+	container_of(attr, struct cpsw_ale, ale_control_attr);
-+	struct device_attribute ale_table_attr;
-+#define table_attr_to_ale(attr)		\
-+	container_of(attr, struct cpsw_ale, ale_table_attr);
-+};
-+
-+enum cpsw_ale_control {
-+	/* global */
-+	ALE_ENABLE,
-+	ALE_CLEAR,
-+	ALE_AGEOUT,
-+	ALE_VLAN_NOLEARN,
-+	ALE_NO_PORT_VLAN,
-+	ALE_OUI_DENY,
-+	ALE_BYPASS,
-+	ALE_RATE_LIMIT_TX,
-+	ALE_VLAN_AWARE,
-+	ALE_AUTH_ENABLE,
-+	ALE_RATE_LIMIT,
-+	/* port controls */
-+	ALE_PORT_STATE,
-+	ALE_PORT_DROP_UNTAGGED,
-+	ALE_PORT_DROP_UNKNOWN_VLAN,
-+	ALE_PORT_NOLEARN,
-+	ALE_PORT_UNKNOWN_VLAN_MEMBER,
-+	ALE_PORT_UNKNOWN_MCAST_FLOOD,
-+	ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
-+	ALE_PORT_UNTAGGED_EGRESS,
-+	ALE_PORT_BCAST_LIMIT,
-+	ALE_PORT_MCAST_LIMIT,
-+	ALE_NUM_CONTROLS,
-+};
-+
-+enum cpsw_ale_port_state {
-+	ALE_PORT_STATE_DISABLE	= 0x00,
-+	ALE_PORT_STATE_BLOCK	= 0x01,
-+	ALE_PORT_STATE_LEARN	= 0x02,
-+	ALE_PORT_STATE_FORWARD	= 0x03,
-+};
-+
-+/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
-+#define ALE_SECURE	1
-+#define ALE_BLOCKED	2
-+
-+struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params);
-+int cpsw_ale_destroy(struct cpsw_ale *ale);
-+
-+void cpsw_ale_start(struct cpsw_ale *ale);
-+void cpsw_ale_stop(struct cpsw_ale *ale);
-+
-+int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout);
-+int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask);
-+int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags);
-+int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port);
-+int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask);
-+int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask);
-+
-+int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control);
-+int cpsw_ale_control_set(struct cpsw_ale *ale, int port,
-+			 int control, int value);
-+
-+#endif
-diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c
-index c97d2f5..306d930 100644
---- a/drivers/net/ethernet/ti/davinci_cpdma.c
-+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
-@@ -19,6 +19,7 @@
- #include <linux/err.h>
- #include <linux/dma-mapping.h>
- #include <linux/io.h>
-+#include <linux/export.h>
- 
- #include "davinci_cpdma.h"
- 
-@@ -276,6 +277,7 @@ struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params)
- 		ctlr->num_chan = CPDMA_MAX_CHANNELS;
- 	return ctlr;
- }
-+EXPORT_SYMBOL_GPL(cpdma_ctlr_create);
- 
- int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
- {
-@@ -321,6 +323,7 @@ int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
- 	spin_unlock_irqrestore(&ctlr->lock, flags);
- 	return 0;
- }
-+EXPORT_SYMBOL_GPL(cpdma_ctlr_start);
- 
- int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
- {
-@@ -348,9 +351,21 @@ int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
- 
- 	ctlr->state = CPDMA_STATE_IDLE;
- 
-+	if (ctlr->params.has_soft_reset) {
-+		unsigned long timeout = jiffies + HZ/10;
-+
-+		dma_reg_write(ctlr, CPDMA_SOFTRESET, 1);
-+		while (time_before(jiffies, timeout)) {
-+			if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0)
-+				break;
-+		}
-+		WARN_ON(!time_before(jiffies, timeout));
-+	}
-+
- 	spin_unlock_irqrestore(&ctlr->lock, flags);
- 	return 0;
- }
-+EXPORT_SYMBOL_GPL(cpdma_ctlr_stop);
- 
- int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr)
- {
-@@ -444,6 +459,7 @@ int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr)
- 	kfree(ctlr);
- 	return ret;
- }
-+EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy);
- 
- int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
- {
-@@ -467,11 +483,15 @@ int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
- 	spin_unlock_irqrestore(&ctlr->lock, flags);
- 	return 0;
- }
-+EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl);
- 
- void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr)
- {
- 	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 0);
-+	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 1);
-+	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 2);
- }
-+EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi);
- 
- struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
- 				     cpdma_handler_fn handler)
-@@ -528,6 +548,7 @@ err_chan_busy:
- err_chan_alloc:
- 	return ERR_PTR(ret);
- }
-+EXPORT_SYMBOL_GPL(cpdma_chan_create);
- 
- int cpdma_chan_destroy(struct cpdma_chan *chan)
- {
-@@ -545,6 +566,7 @@ int cpdma_chan_destroy(struct cpdma_chan *chan)
- 	kfree(chan);
- 	return 0;
- }
-+EXPORT_SYMBOL_GPL(cpdma_chan_destroy);
- 
- int cpdma_chan_get_stats(struct cpdma_chan *chan,
- 			 struct cpdma_chan_stats *stats)
-@@ -557,6 +579,7 @@ int cpdma_chan_get_stats(struct cpdma_chan *chan,
- 	spin_unlock_irqrestore(&chan->lock, flags);
- 	return 0;
- }
-+EXPORT_SYMBOL_GPL(cpdma_chan_get_stats);
- 
- int cpdma_chan_dump(struct cpdma_chan *chan)
- {
-@@ -693,6 +716,7 @@ unlock_ret:
- 	spin_unlock_irqrestore(&chan->lock, flags);
- 	return ret;
- }
-+EXPORT_SYMBOL_GPL(cpdma_chan_submit);
- 
- static void __cpdma_chan_free(struct cpdma_chan *chan,
- 			      struct cpdma_desc __iomem *desc,
-@@ -720,9 +744,6 @@ static int __cpdma_chan_process(struct cpdma_chan *chan)
- 	int				status, outlen;
- 	struct cpdma_desc_pool		*pool = ctlr->pool;
- 	dma_addr_t			desc_dma;
--	unsigned long			flags;
--
--	spin_lock_irqsave(&chan->lock, flags);
- 
- 	desc = chan->head;
- 	if (!desc) {
-@@ -751,13 +772,10 @@ static int __cpdma_chan_process(struct cpdma_chan *chan)
- 		chan_write(chan, hdp, desc_phys(pool, chan->head));
- 	}
- 
--	spin_unlock_irqrestore(&chan->lock, flags);
--
- 	__cpdma_chan_free(chan, desc, outlen, status);
- 	return status;
- 
- unlock_ret:
--	spin_unlock_irqrestore(&chan->lock, flags);
- 	return status;
- }
- 
-@@ -776,6 +794,7 @@ int cpdma_chan_process(struct cpdma_chan *chan, int quota)
- 	}
- 	return used;
- }
-+EXPORT_SYMBOL_GPL(cpdma_chan_process);
- 
- int cpdma_chan_start(struct cpdma_chan *chan)
- {
-@@ -803,6 +822,7 @@ int cpdma_chan_start(struct cpdma_chan *chan)
- 	spin_unlock_irqrestore(&chan->lock, flags);
- 	return 0;
- }
-+EXPORT_SYMBOL_GPL(cpdma_chan_start);
- 
- int cpdma_chan_stop(struct cpdma_chan *chan)
- {
-@@ -863,6 +883,7 @@ int cpdma_chan_stop(struct cpdma_chan *chan)
- 	spin_unlock_irqrestore(&chan->lock, flags);
- 	return 0;
- }
-+EXPORT_SYMBOL_GPL(cpdma_chan_stop);
- 
- int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
- {
-@@ -934,6 +955,7 @@ unlock_ret:
- 	spin_unlock_irqrestore(&ctlr->lock, flags);
- 	return ret;
- }
-+EXPORT_SYMBOL_GPL(cpdma_control_get);
- 
- int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
- {
-@@ -970,3 +992,4 @@ unlock_ret:
- 	spin_unlock_irqrestore(&ctlr->lock, flags);
- 	return ret;
- }
-+EXPORT_SYMBOL_GPL(cpdma_control_set);
-diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
-index 7615040..1f14be6 100644
---- a/drivers/net/ethernet/ti/davinci_mdio.c
-+++ b/drivers/net/ethernet/ti/davinci_mdio.c
-@@ -48,6 +48,10 @@
- 
- #define DEF_OUT_FREQ		2200000		/* 2.2 MHz */
- 
-+#define CPGMAC_CLK_CTRL_REG	0x44E00014
-+#define CPGMAC_CLK_SYSC         0x4A101208
-+#define CPSW_NO_IDLE_NO_STDBY   0xA
-+
- struct davinci_mdio_regs {
- 	u32	version;
- 	u32	control;
-@@ -402,6 +406,33 @@ static int __devexit davinci_mdio_remove(struct platform_device *pdev)
- 	return 0;
- }
- 
-+static inline int wait_for_clock_enable(struct davinci_mdio_data *data)
-+{
-+	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
-+	u32 __iomem *cpgmac_clk = ioremap(CPGMAC_CLK_CTRL_REG, 4);
-+	u32 __iomem *cpgmac_sysc = ioremap(CPGMAC_CLK_SYSC, 4);
-+	u32 reg = 0;
-+
-+	while (time_after(timeout, jiffies)) {
-+		reg = readl(cpgmac_clk);
-+		if ((reg & 0x30000) == 0) {
-+			writel(CPSW_NO_IDLE_NO_STDBY, cpgmac_sysc);
-+			goto iounmap_ret;
-+                }
-+	}
-+	dev_err(data->dev,
-+		"timed out waiting for CPGMAC clock enable, value = 0x%x\n",
-+		reg);
-+	iounmap(cpgmac_sysc);
-+	iounmap(cpgmac_clk);
-+	return -ETIMEDOUT;
-+
-+iounmap_ret:
-+	iounmap(cpgmac_sysc);
-+	iounmap(cpgmac_clk);
-+	return 0;
-+}
-+
- static int davinci_mdio_suspend(struct device *dev)
- {
- 	struct davinci_mdio_data *data = dev_get_drvdata(dev);
-@@ -433,12 +464,15 @@ static int davinci_mdio_resume(struct device *dev)
- 	if (data->clk)
- 		clk_enable(data->clk);
- 
-+	/* Need to wait till Module is enabled */
-+	wait_for_clock_enable(data);
-+
- 	/* restart the scan state machine */
- 	ctrl = __raw_readl(&data->regs->control);
- 	ctrl |= CONTROL_ENABLE;
- 	__raw_writel(ctrl, &data->regs->control);
--
- 	data->suspended = false;
-+
- 	spin_unlock(&data->lock);
- 
- 	return 0;
-diff --git a/drivers/net/wireless/wl12xx/Kconfig b/drivers/net/wireless/wl12xx/Kconfig
-index 3fe388b..f3162eb 100644
---- a/drivers/net/wireless/wl12xx/Kconfig
-+++ b/drivers/net/wireless/wl12xx/Kconfig
-@@ -54,5 +54,5 @@ config WL12XX_SDIO_TEST
- 
- config WL12XX_PLATFORM_DATA
- 	bool
--	depends on WL12XX_SDIO != n || WL1251_SDIO != n
- 	default y
-+	select WIRELESS_EXT
-diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
-new file mode 100644
-index 0000000..73c0db0
---- /dev/null
-+++ b/drivers/pwm/Kconfig
-@@ -0,0 +1,29 @@
-+#
-+# PWM infrastructure and devices
-+#
-+
-+menuconfig GENERIC_PWM
-+	tristate "PWM Support"
-+	default n
-+	help
-+	  Enables PWM device support implemented via a generic
-+	  framework.  If unsure, say N.
-+
-+config DAVINCI_EHRPWM
-+	bool "Davinci eHRPWM support"
-+	select HAVE_PWM
-+	depends on GENERIC_PWM && (ARCH_DAVINCI_DA850 || SOC_OMAPAM33XX)
-+	help
-+	  This option enables support for eHRPWM driver. If
-+	  unsure, say N.
-+
-+config ECAP_PWM
-+	tristate "eCAP PWM support"
-+	select HAVE_PWM
-+	depends on GENERIC_PWM && (ARCH_DAVINCI_DA850 || SOC_OMAPAM33XX)
-+	help
-+	  This option enables device driver support for eCAP module found
-+	  on DA8xx Processors & AM335x processor. eCAP module is used to
-+	  generate wide range of PWM waveforms. Maximum frequency generated
-+	  is equal to half the system clock frequency.
-+	  Say Y to enable the eCAP support. If unsure, say N.
-diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
-new file mode 100644
-index 0000000..e888fad
---- /dev/null
-+++ b/drivers/pwm/Makefile
-@@ -0,0 +1,8 @@
-+#
-+# Makefile for pwm devices
-+#
-+obj-$(CONFIG_GENERIC_PWM) := pwm.o
-+
-+obj-$(CONFIG_DAVINCI_EHRPWM)	+= ehrpwm.o
-+
-+obj-$(CONFIG_ECAP_PWM)		+= ecap.o
-diff --git a/drivers/pwm/ecap.c b/drivers/pwm/ecap.c
-new file mode 100644
-index 0000000..63c2405
---- /dev/null
-+++ b/drivers/pwm/ecap.c
-@@ -0,0 +1,461 @@
-+/*
-+ * eCAP driver for PWM output generation
-+ *
-+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed .as is. WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/err.h>
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/pwm/pwm.h>
-+#include <linux/slab.h>
-+#include <linux/pm_runtime.h>
-+
-+#include <plat/clock.h>
-+#include <plat/config_pwm.h>
-+
-+#define TIMER_CTR_REG			0x0
-+#define CAPTURE_1_REG			0x08
-+#define CAPTURE_2_REG			0x0c
-+#define CAPTURE_3_REG			0x10
-+#define CAPTURE_4_REG			0x14
-+#define CAPTURE_CTRL2_REG		0x2A
-+
-+#define ECTRL2_SYNCOSEL_MASK		(0x03 << 6)
-+
-+#define ECTRL2_MDSL_ECAP		BIT(9)
-+#define ECTRL2_CTRSTP_FREERUN		BIT(4)
-+#define ECTRL2_PLSL_LOW			BIT(10)
-+#define ECTRL2_SYNC_EN			BIT(5)
-+
-+struct ecap_regs {
-+	unsigned	tsctr;
-+	unsigned	cap1;
-+	unsigned	cap2;
-+	unsigned	cap3;
-+	unsigned	cap4;
-+	unsigned short	ecctl2;
-+	unsigned short	clkconfig;
-+};
-+
-+struct ecap_pwm {
-+	struct pwm_device pwm;
-+	struct pwm_device_ops ops;
-+	spinlock_t	lock;
-+	struct clk	*clk;
-+	void __iomem	*mmio_base;
-+	u8 version;
-+	void __iomem *config_mem_base;
-+	struct device *dev;
-+	struct ecap_regs ctx;
-+};
-+
-+static inline struct ecap_pwm *to_ecap_pwm(const struct pwm_device *p)
-+{
-+	return pwm_get_drvdata(p);
-+}
-+
-+static int ecap_pwm_stop(struct pwm_device *p)
-+{
-+	unsigned long flags, v;
-+	struct ecap_pwm *ep = to_ecap_pwm(p);
-+
-+	/* Trying to stop a non-running PWM, not allowed */
-+	if (!pwm_is_running(p))
-+		return -EPERM;
-+
-+	spin_lock_irqsave(&ep->lock, flags);
-+	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
-+	v &= ~ECTRL2_CTRSTP_FREERUN;
-+	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
-+	spin_unlock_irqrestore(&ep->lock, flags);
-+
-+	/* For PWM clock should be disabled on stop */
-+	pm_runtime_put_sync(ep->dev);
-+	clear_bit(FLAG_RUNNING, &p->flags);
-+
-+	return 0;
-+}
-+
-+static int ecap_pwm_start(struct pwm_device *p)
-+{
-+	int ret = 0;
-+	unsigned long flags, v;
-+	struct ecap_pwm *ep = to_ecap_pwm(p);
-+
-+	/* Trying to start a running PWM, not allowed */
-+	if (pwm_is_running(p))
-+		return -EPERM;
-+
-+	/* For PWM clock should be enabled on start */
-+	pm_runtime_get_sync(ep->dev);
-+
-+	spin_lock_irqsave(&ep->lock, flags);
-+	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
-+	v |= ECTRL2_CTRSTP_FREERUN;
-+	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
-+	spin_unlock_irqrestore(&ep->lock, flags);
-+	set_bit(FLAG_RUNNING, &p->flags);
-+
-+	return ret;
-+}
-+
-+static int ecap_pwm_set_polarity(struct pwm_device *p, char pol)
-+{
-+	unsigned long flags, v;
-+	struct ecap_pwm *ep = to_ecap_pwm(p);
-+
-+	pm_runtime_get_sync(ep->dev);
-+
-+	spin_lock_irqsave(&ep->lock, flags);
-+	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
-+	v &= ~ECTRL2_PLSL_LOW;
-+	v |= (!pol << 10);
-+	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
-+	spin_unlock_irqrestore(&ep->lock, flags);
-+
-+	pm_runtime_put_sync(ep->dev);
-+	return 0;
-+}
-+
-+static int ecap_pwm_config_period(struct pwm_device *p)
-+{
-+	unsigned long flags, v;
-+	struct ecap_pwm *ep = to_ecap_pwm(p);
-+
-+	 pm_runtime_get_sync(ep->dev);
-+
-+	spin_lock_irqsave(&ep->lock, flags);
-+	writel((p->period_ticks) - 1, ep->mmio_base + CAPTURE_3_REG);
-+	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
-+	v |= (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK);
-+	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
-+	spin_unlock_irqrestore(&ep->lock, flags);
-+
-+	pm_runtime_put_sync(ep->dev);
-+	return 0;
-+}
-+
-+static int ecap_pwm_config_duty(struct pwm_device *p)
-+{
-+	unsigned long flags, v;
-+	struct ecap_pwm *ep = to_ecap_pwm(p);
-+
-+	pm_runtime_get_sync(ep->dev);
-+
-+	spin_lock_irqsave(&ep->lock, flags);
-+	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
-+	v |= (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK);
-+	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
-+
-+	if (p->duty_ticks > 0) {
-+		writel(p->duty_ticks, ep->mmio_base + CAPTURE_4_REG);
-+	} else {
-+		writel(p->duty_ticks, ep->mmio_base + CAPTURE_2_REG);
-+		writel(0, ep->mmio_base + TIMER_CTR_REG);
-+	}
-+	spin_unlock_irqrestore(&ep->lock, flags);
-+
-+	pm_runtime_put_sync(ep->dev);
-+	return 0;
-+}
-+
-+static int ecap_pwm_config(struct pwm_device *p,
-+				struct pwm_config *c)
-+{
-+	int ret = 0;
-+	switch (c->config_mask) {
-+
-+	case BIT(PWM_CONFIG_DUTY_TICKS):
-+		p->duty_ticks = c->duty_ticks;
-+		ret = ecap_pwm_config_duty(p);
-+		break;
-+
-+	case BIT(PWM_CONFIG_PERIOD_TICKS):
-+		p->period_ticks = c->period_ticks;
-+		ret = ecap_pwm_config_period(p);
-+		break;
-+
-+	case BIT(PWM_CONFIG_POLARITY):
-+		ret = ecap_pwm_set_polarity(p, c->polarity);
-+		break;
-+
-+	case BIT(PWM_CONFIG_START):
-+		ret = ecap_pwm_start(p);
-+		break;
-+
-+	case BIT(PWM_CONFIG_STOP):
-+		ret = ecap_pwm_stop(p);
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static int ecap_pwm_request(struct pwm_device *p)
-+{
-+	struct ecap_pwm *ep = to_ecap_pwm(p);
-+
-+	p->tick_hz = clk_get_rate(ep->clk);
-+	return 0;
-+}
-+
-+static int ecap_frequency_transition_cb(struct pwm_device *p)
-+{
-+	struct ecap_pwm *ep = to_ecap_pwm(p);
-+	unsigned long duty_ns, rate;
-+
-+	rate = clk_get_rate(ep->clk);
-+	if (rate == p->tick_hz)
-+		return 0;
-+	p->tick_hz = rate;
-+
-+	duty_ns = p->duty_ns;
-+	if (pwm_is_running(p)) {
-+		pwm_stop(p);
-+		pwm_set_duty_ns(p, 0);
-+		pwm_set_period_ns(p, p->period_ns);
-+		pwm_set_duty_ns(p, duty_ns);
-+		pwm_start(p);
-+	} else {
-+		pwm_set_duty_ns(p, 0);
-+		pwm_set_period_ns(p, p->period_ns);
-+		pwm_set_duty_ns(p, duty_ns);
-+	}
-+		return 0;
-+}
-+
-+static int ecap_probe(struct platform_device *pdev)
-+{
-+	struct ecap_pwm *ep = NULL;
-+	struct resource *r;
-+	int ret = 0;
-+	int val;
-+	char con_id[PWM_CON_ID_STRING_LENGTH] = "epwmss";
-+	struct pwmss_platform_data *pdata = (&pdev->dev)->platform_data;
-+
-+	ep = kzalloc(sizeof(*ep), GFP_KERNEL);
-+
-+	if (!ep) {
-+		dev_err(&pdev->dev, "failed to allocate memory\n");
-+		return -ENOMEM;
-+	}
-+
-+	ep->version = pdata->version;
-+
-+	if (ep->version == PWM_VERSION_1) {
-+		sprintf(con_id, "%s%d_%s", con_id, pdev->id, "fck");
-+		ep->clk = clk_get(&pdev->dev, con_id);
-+	} else
-+		ep->clk = clk_get(&pdev->dev, "ecap");
-+
-+	pm_runtime_enable(&pdev->dev);
-+	ep->dev = &pdev->dev;
-+	if (IS_ERR(ep->clk)) {
-+		ret = PTR_ERR(ep->clk);
-+		goto err_clk_get;
-+	}
-+
-+	if (ep->version == PWM_VERSION_1) {
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+		if (!r) {
-+			dev_err(&pdev->dev, "no memory resource defined\n");
-+			ret = -ENOMEM;
-+			goto err_get_resource;
-+		}
-+
-+		ep->config_mem_base = ioremap(r->start, resource_size(r));
-+
-+		if (!ep->config_mem_base) {
-+
-+			dev_err(&pdev->dev, "failed to ioremap() registers\n");
-+			ret = -ENOMEM;
-+			goto err_get_resource;
-+		}
-+
-+		pm_runtime_get_sync(ep->dev);
-+		val = readw(ep->config_mem_base + PWMSS_CLKCONFIG);
-+		val |= BIT(ECAP_CLK_EN);
-+		writew(val, ep->config_mem_base + PWMSS_CLKCONFIG);
-+		pm_runtime_put_sync(ep->dev);
-+	}
-+
-+	spin_lock_init(&ep->lock);
-+	ep->ops.config = ecap_pwm_config;
-+	ep->ops.request = ecap_pwm_request;
-+	ep->ops.freq_transition_notifier_cb = ecap_frequency_transition_cb;
-+
-+	if (ep->version == PWM_VERSION_1)
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	else
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+	if (!r) {
-+		dev_err(&pdev->dev, "no memory resource defined\n");
-+		ret = -ENODEV;
-+		goto err_request_mem;
-+	}
-+
-+	r = request_mem_region(r->start, resource_size(r), pdev->name);
-+	if (!r) {
-+		dev_err(&pdev->dev, "failed to request memory resource\n");
-+		ret = -EBUSY;
-+		goto err_request_mem;
-+	}
-+
-+	ep->mmio_base = ioremap(r->start, resource_size(r));
-+	if (!ep->mmio_base) {
-+		dev_err(&pdev->dev, "failed to ioremap() registers\n");
-+		ret = -ENODEV;
-+		goto err_ioremap;
-+	}
-+
-+	ep->pwm.ops = &ep->ops;
-+	pwm_set_drvdata(&ep->pwm, ep);
-+	ret =  pwm_register(&ep->pwm, &pdev->dev, -1);
-+	platform_set_drvdata(pdev, ep);
-+	return 0;
-+
-+err_ioremap:
-+	release_mem_region(r->start, resource_size(r));
-+err_request_mem:
-+	if (ep->version == PWM_VERSION_1) {
-+		iounmap(ep->config_mem_base);
-+		ep->config_mem_base = NULL;
-+	}
-+err_get_resource:
-+	clk_put(ep->clk);
-+	pm_runtime_disable(&pdev->dev);
-+err_clk_get:
-+	kfree(ep);
-+	return ret;
-+}
-+
-+#ifdef CONFIG_PM
-+
-+void ecap_save_reg(struct ecap_pwm *ep)
-+{
-+	pm_runtime_get_sync(ep->dev);
-+
-+	ep->ctx.ecctl2 = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
-+	ep->ctx.tsctr = readl(ep->mmio_base + TIMER_CTR_REG);
-+	ep->ctx.cap1 = readl(ep->mmio_base + CAPTURE_1_REG);
-+	ep->ctx.cap2 = readl(ep->mmio_base + CAPTURE_2_REG);
-+	ep->ctx.cap4 = readl(ep->mmio_base + CAPTURE_4_REG);
-+	ep->ctx.cap3 = readl(ep->mmio_base + CAPTURE_3_REG);
-+
-+	ep->ctx.clkconfig = readw(ep->config_mem_base + PWMSS_CLKCONFIG);
-+
-+	pm_runtime_put_sync(ep->dev);
-+}
-+
-+void ecap_restore_reg(struct ecap_pwm *ep)
-+{
-+	writew(ep->ctx.clkconfig, ep->config_mem_base + PWMSS_CLKCONFIG);
-+
-+	writel(ep->ctx.cap3, ep->mmio_base + CAPTURE_3_REG);
-+	writel(ep->ctx.cap4, ep->mmio_base + CAPTURE_4_REG);
-+	writel(ep->ctx.cap2, ep->mmio_base + CAPTURE_2_REG);
-+	writel(ep->ctx.cap1, ep->mmio_base + CAPTURE_1_REG);
-+	writel(ep->ctx.tsctr, ep->mmio_base + TIMER_CTR_REG);
-+	writew(ep->ctx.ecctl2, ep->mmio_base + CAPTURE_CTRL2_REG);
-+}
-+
-+static int ecap_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+	struct ecap_pwm *ep = platform_get_drvdata(pdev);
-+
-+	ecap_save_reg(ep);
-+	pm_runtime_put_sync(ep->dev);
-+
-+	return 0;
-+}
-+
-+static int ecap_resume(struct platform_device *pdev)
-+{
-+	struct ecap_pwm *ep = platform_get_drvdata(pdev);
-+
-+	pm_runtime_get_sync(ep->dev);
-+
-+	ecap_restore_reg(ep);
-+
-+	return 0;
-+}
-+
-+#else
-+#define ecap_suspend NULL
-+#define ecap_resume NULL
-+#endif
-+
-+static int __devexit ecap_remove(struct platform_device *pdev)
-+{
-+	struct ecap_pwm *ep = platform_get_drvdata(pdev);
-+	struct resource *r;
-+	struct pwmss_platform_data *pdata;
-+	int val;
-+
-+	if (ep->version == PWM_VERSION_1) {
-+		pdata = (&pdev->dev)->platform_data;
-+		val = readw(ep->config_mem_base + PWMSS_CLKCONFIG);
-+		val &= ~BIT(ECAP_CLK_EN);
-+		writew(val, ep->config_mem_base + PWMSS_CLKCONFIG);
-+		iounmap(ep->config_mem_base);
-+		ep->config_mem_base = NULL;
-+	}
-+
-+	pwm_unregister(&ep->pwm);
-+	iounmap(ep->mmio_base);
-+
-+	if (ep->version == PWM_VERSION_1)
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	else
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	release_mem_region(r->start, resource_size(r));
-+	platform_set_drvdata(pdev, NULL);
-+	clk_put(ep->clk);
-+	pm_runtime_disable(&pdev->dev);
-+	kfree(ep);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver ecap_driver = {
-+	.driver	= {
-+		.name	= "ecap",
-+		.owner	= THIS_MODULE,
-+	},
-+	.probe		= ecap_probe,
-+	.remove		= __devexit_p(ecap_remove),
-+	.suspend	= ecap_suspend,
-+	.resume		= ecap_resume,
-+};
-+
-+static int __init ecap_init(void)
-+{
-+	return platform_driver_register(&ecap_driver);
-+}
-+
-+static void __exit ecap_exit(void)
-+{
-+	platform_driver_unregister(&ecap_driver);
-+}
-+
-+module_init(ecap_init);
-+module_exit(ecap_exit);
-+
-+MODULE_AUTHOR("Texas Instruments");
-+MODULE_DESCRIPTION("Driver for Davinci eCAP peripheral");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:ecap");
-diff --git a/drivers/pwm/ehrpwm.c b/drivers/pwm/ehrpwm.c
-new file mode 100644
-index 0000000..8bbed87
---- /dev/null
-+++ b/drivers/pwm/ehrpwm.c
-@@ -0,0 +1,1645 @@
-+/*
-+ * eHRPWM driver for simple PWM output generation
-+ *
-+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed .as is. WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/pwm/pwm.h>
-+#include <linux/pwm/ehrpwm.h>
-+#include <linux/pm_runtime.h>
-+
-+#include <plat/clock.h>
-+#include <plat/config_pwm.h>
-+
-+#ifdef DEBUG
-+#define debug(format, args...) printk(format, ##args)
-+#else
-+#define debug(format, args...) { }
-+#endif
-+
-+/******************** Time base sub module*****************************/
-+#define TBCTL				0x0
-+#define TBSTS				0x2
-+#define TBPHS				0x6
-+#define TBCTR				0x8
-+#define TBPRD				0xA
-+
-+#define TBCTL_CLKDIV_MASK		(BIT(12) | BIT(11) | BIT(10))
-+#define TBCTL_HSPCLKDIV_MASK		(BIT(9) | BIT(8) | BIT(7))
-+#define TBCTL_SYNCOSEL_MASK		(BIT(5) | BIT(4))
-+#define TBCTL_CTRMODE_MASK		(BIT(1) | BIT(0))
-+
-+#define	TBCTL_CLKDIV_POS		0xA
-+#define TBCTL_HSPCLKDIV_POS		0x7
-+#define TBCTL_PHSEN_POS			0x2
-+#define TBCTL_SYNCOSEL_POS		0x4
-+#define TBCTL_PHSDIR_POS		0xD
-+#define TBCTL_FRC_SYC_POS		0x6
-+#define TBCTL_LOAD_MD_POS		0x3
-+
-+#define TBCTL_FREERUN_FREE		0x2
-+#define TBCTL_CTRMOD_CTRUP		0x0
-+
-+/******************* Counter-Compare Sub Module ***********************/
-+#define CMPCTL				0xE
-+#define CMPA				0x12
-+#define CMPB				0x14
-+
-+#define CMPCTL_LDBMODE_MASK		(BIT(3) | BIT(2))
-+#define CMPCTL_LDAMODE_MASK		(BIT(1) | BIT(0))
-+
-+#define CMPCTL_SHDAMODE_POS		0x4
-+#define CMPCTL_SHDBMODE_POS		0x6
-+#define CMPCTL_LDBMODE_POS		0x2
-+
-+/*********************** Action Control Sub module ********************/
-+#define AQCTLA				0x16
-+#define AQCTLB				0x18
-+#define AQSFRC				0x1A
-+#define AQCSFRC				0x1c
-+
-+#define ACTCTL_CBD_MASK			(BIT(11) | BIT(10))
-+#define ACTCTL_CBU_MASK			(BIT(9) | BIT(8))
-+#define ACTCTL_CAD_MASK			(BIT(7) | BIT(6))
-+#define ACTCTL_CAU_MASK			(BIT(5) | BIT(4))
-+#define ACTCTL_CPRD_MASK		(BIT(3) | BIT(2))
-+#define ACTCTL_CZRO_MASK		(BIT(1) | BIT(0))
-+
-+#define ACTCTL_CTREQPRD_POS		0x2
-+#define ACTCTL_CTREQCMPAUP_POS		0x4
-+#define ACTCTL_CTREQCMPADN_POS		0x6
-+#define ACTCTL_CTREQCMPBUP_POS		0x8
-+#define ACTCTL_CTREQCMPBDN_POS		0xA
-+
-+#define ACTCTL_CTREQCMP_LOW		0x1
-+#define ACTCTL_CTREQCMP_HIGH		0x2
-+#define ACTCTL_CTREQZRO_LOW		0x1
-+#define ACTCTL_CTREQZRO_HIGH		0x2
-+
-+#define AQSFRC_ACTA_MASK		(BIT(1) | BIT(0))
-+#define AQSFRC_ACTB_MASK		(BIT(4) | BIT(3))
-+#define AQCSFRC_CFRC_LOAD_MASK		(BIT(7) | BIT(6))
-+#define AQCSFRC_OUTB_MASK		(BIT(3) | BIT(2))
-+#define AQCSFRC_OUTA_MASK		(BIT(1) | BIT(0))
-+
-+#define AQSFRC_ACTB_POS			0x3
-+#define AQSFRC_OTFRCA_POS		0x2
-+#define AQSFRC_OTFRCB_POS		0x5
-+#define AQSFRC_LDMD_POS			0x6
-+
-+#define AQCSFRC_OUTB_POS		0x2
-+
-+/******************** Dead Band Generator Sub module *******************/
-+#define DBCTL				0x1E
-+#define DBRED				0x20
-+#define DBFED				0x22
-+
-+#define DBCTL_INMODE_MASK		(BIT(5) | BIT(4))
-+#define DBCTL_PLSEL_MASK		(BIT(3) | BIT(2))
-+#define DBCTL_OUTMODE_MASK		(BIT(1) | BIT(0))
-+
-+#define DBCTL_INMODE_POS		0x4
-+#define DBCTL_POLSEL_POS		0x2
-+
-+/********************** PWM Chopper Sub module ************************/
-+#define PCCTL				0x3C
-+
-+#define PCCTL_CHPDUTY_MASK		(BIT(10) | BIT(9) | BIT(8))
-+#define PCCTL_CHPFREQ_MASK		(BIT(7) | BIT(6) | BIT(5))
-+#define PCCTL_OSHTWTH_MASK		(BIT(4) | BIT(3) | BIT(2) | BIT(1))
-+
-+#define PCCTL_CHPDUTY_POS		0x8
-+#define PCCTL_CHPFRQ_POS		0x5
-+#define PCCTL_OSTWID_POS		0x1
-+
-+/*************************Trip-zone submodule **************************/
-+#define TZSEL				0x24
-+#define TZCTL				0x28
-+#define TZEINT				0x2A
-+#define TZFLG				0x2C
-+#define TZCLR				0x2E
-+#define TZFRC				0x30
-+
-+#define TZCTL_ACTA_MASK			(BIT(1) | BIT(0))
-+#define TZCTL_ACTB_MASK			(BIT(3) | BIT(2))
-+
-+#define TZCTL_ACTB_POS			0x2
-+
-+#define TZEINT_OSHTEVT_POS		0x2
-+#define TZEINT_CBCEVT_POS		0x1
-+
-+/*************************Event-Trigger submodule registers**************/
-+#define ETSEL				0x32
-+#define ETPS				0x34
-+#define ETFLG				0x36
-+#define ETCLR				0x38
-+#define ETFRC				0x3A
-+
-+#define ETSEL_INTSEL_MASK		(BIT(2) | BIT(1) | BIT(0))
-+#define ETPS_INTCNT_MASK		(BIT(3) | BIT(2))
-+#define ETPS_INTPRD_MASK		(BIT(1) | BIT(0))
-+
-+#define ETSEL_EN_INT_EN_POS		0x3
-+
-+/**********************High Resolution Registers ********************/
-+#define TBPHSHR				0x4
-+#define CMPAHR				0x10
-+#define HRCNFG				0x1040
-+
-+#define AM335X_HRCNFG			0x40
-+
-+#define HRCNFG_EDGEMD_MASK		(BIT(1) | BIT(0))
-+#define HRCNFG_LDMD_POS			0x3
-+#define HRCNFG_CTLMD_POS		0x2
-+
-+struct ehrpwm_suspend_params {
-+	struct pwm_device *pch;
-+	unsigned long req_delay_cycles;
-+	unsigned long act_delay;
-+} ehrpwm_suspend_params;
-+
-+static inline unsigned short ehrpwm_read(struct ehrpwm_pwm *ehrpwm,
-+	unsigned int offset)
-+{
-+	return readw(ehrpwm->mmio_base + offset);
-+}
-+
-+static inline void ehrpwm_write(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
-+	unsigned short val)
-+{
-+	writew(val, ehrpwm->mmio_base + offset);
-+}
-+
-+static void ehrpwm_reg_config(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
-+	       unsigned short val, unsigned short mask)
-+{
-+	unsigned short read_val;
-+
-+	read_val = ehrpwm_read(ehrpwm, offset);
-+	read_val = read_val & ~mask;
-+	read_val = read_val | val;
-+	ehrpwm_write(ehrpwm, offset, read_val);
-+}
-+
-+static inline struct ehrpwm_pwm *to_ehrpwm_pwm(const struct pwm_device *p)
-+{
-+	return pwm_get_drvdata(p);
-+}
-+
-+/* Time Base Module Configurations */
-+int ehrpwm_tb_set_prescalar_val(struct pwm_device *p, unsigned char clkdiv,
-+	unsigned char hspclkdiv)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (clkdiv > 0x7 || hspclkdiv > 0x7)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, TBCTL, clkdiv << TBCTL_CLKDIV_POS,
-+		       TBCTL_CLKDIV_MASK);
-+	ehrpwm_reg_config(ehrpwm, TBCTL, hspclkdiv << TBCTL_HSPCLKDIV_POS,
-+		       TBCTL_HSPCLKDIV_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tb_set_prescalar_val);
-+
-+int ehrpwm_tb_config_sync(struct pwm_device *p, unsigned char phsen,
-+	unsigned char syncosel)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (phsen > 1 || syncosel > 0x3)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, TBCTL, phsen << TBCTL_PHSEN_POS, BIT(2));
-+	ehrpwm_reg_config(ehrpwm, TBCTL, syncosel << TBCTL_SYNCOSEL_POS,
-+		       TBCTL_SYNCOSEL_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tb_config_sync);
-+
-+int ehrpwm_tb_set_counter_mode(struct pwm_device *p, unsigned char ctrmode,
-+	       unsigned char phsdir)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (ctrmode > 0x3 || phsdir > 1)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, TBCTL, phsdir << TBCTL_PHSDIR_POS, BIT(13));
-+	ehrpwm_reg_config(ehrpwm, TBCTL, ctrmode, TBCTL_CTRMODE_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tb_set_counter_mode);
-+
-+int ehrpwm_tb_force_sync(struct pwm_device *p)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	ehrpwm_reg_config(ehrpwm, TBCTL, ENABLE << TBCTL_FRC_SYC_POS, BIT(6));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tb_force_sync);
-+
-+int ehrpwm_tb_set_periodload(struct pwm_device *p, unsigned char loadmode)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (loadmode > 0x1)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, TBCTL, loadmode << TBCTL_LOAD_MD_POS, BIT(3));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tb_set_periodload);
-+
-+int ehrpwm_tb_read_status(struct pwm_device *p, unsigned short *val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	*val = ehrpwm_read(ehrpwm, TBSTS);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tb_read_status);
-+
-+int ehrpwm_tb_read_counter(struct pwm_device *p, unsigned short *val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	*val = ehrpwm_read(ehrpwm, TBCTR);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tb_read_counter);
-+
-+int ehrpwm_tb_set_period(struct pwm_device *p,	unsigned short val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	ehrpwm_write(ehrpwm, TBPRD, val);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tb_set_period);
-+
-+int ehrpwm_tb_set_phase(struct pwm_device *p, unsigned short val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	ehrpwm_write(ehrpwm, TBPHS, val);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tb_set_phase);
-+
-+int ehrpwm_cmp_set_cmp_ctl(struct pwm_device *p, unsigned char shdwamode,
-+	unsigned char shdwbmode, unsigned char loadamode,
-+	unsigned char loadbmode)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (shdwamode > 0x1 || shdwbmode > 0x1 || loadamode > 0x3 ||
-+		loadbmode > 0x3)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, CMPCTL, shdwamode << CMPCTL_SHDAMODE_POS,
-+		       BIT(4));
-+	ehrpwm_reg_config(ehrpwm, CMPCTL, shdwbmode << CMPCTL_SHDBMODE_POS,
-+		       BIT(6));
-+	ehrpwm_reg_config(ehrpwm, CMPCTL, loadamode, CMPCTL_LDAMODE_MASK);
-+	ehrpwm_reg_config(ehrpwm, CMPCTL, loadbmode << CMPCTL_LDBMODE_POS,
-+		       CMPCTL_LDBMODE_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_ctl);
-+
-+int ehrpwm_cmp_set_cmp_val(struct pwm_device *p, unsigned char reg,
-+	unsigned short val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned char offset;
-+
-+	if (reg > 0x1)
-+		return -EINVAL;
-+
-+	if (reg == 0)
-+		offset = CMPA;
-+	else
-+		offset = CMPB;
-+
-+	ehrpwm_write(ehrpwm, offset, val);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_val);
-+
-+int ehrpwm_aq_set_act_ctrl(struct pwm_device *p, struct aq_config_params *cfg)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned char reg;
-+
-+	if (!cfg)
-+		return -EINVAL;
-+
-+	if (cfg->ch > 1 || cfg->ctreqzro > 3 || cfg->ctreqprd > 3 ||
-+		cfg->ctreqcmpaup > 3 || cfg->ctreqcmpadown > 3 ||
-+		cfg->ctreqcmpbup > 3 || cfg->ctreqcmpbdown > 3)
-+		return -EINVAL;
-+
-+	if (cfg->ch == 0)
-+		reg = AQCTLA;
-+	else
-+		reg = AQCTLB;
-+
-+	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqzro, ACTCTL_CZRO_MASK);
-+	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqprd << ACTCTL_CTREQPRD_POS,
-+		       ACTCTL_CPRD_MASK);
-+	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpaup <<
-+		       ACTCTL_CTREQCMPAUP_POS, ACTCTL_CAU_MASK);
-+	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpadown <<
-+		       ACTCTL_CTREQCMPADN_POS, ACTCTL_CAD_MASK);
-+	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbup <<
-+		       ACTCTL_CTREQCMPBUP_POS, ACTCTL_CBU_MASK);
-+	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbdown <<
-+		       ACTCTL_CTREQCMPBDN_POS, ACTCTL_CBD_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_aq_set_act_ctrl);
-+
-+int ehrpwm_aq_set_one_shot_act(struct pwm_device  *p, unsigned char ch,
-+	unsigned char act)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (ch > 1 || act > 3)
-+		return -EINVAL;
-+
-+	if (ch == 0)
-+		ehrpwm_reg_config(ehrpwm, AQSFRC, act, AQSFRC_ACTA_MASK);
-+	else
-+		ehrpwm_reg_config(ehrpwm, AQSFRC, act << AQSFRC_ACTB_POS,
-+			       AQSFRC_ACTB_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_aq_set_one_shot_act);
-+
-+int ehrpwm_aq_ot_frc(struct pwm_device *p, unsigned char ch)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (ch > 1)
-+		return -EINVAL;
-+
-+	if (ch == 0)
-+		ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCA_POS,
-+			       BIT(2));
-+	else
-+		ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCB_POS,
-+			       BIT(5));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_aq_ot_frc);
-+
-+int ehrpwm_aq_set_csfrc_load_mode(struct pwm_device *p, unsigned char loadmode)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (loadmode > 0x3)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, AQSFRC, loadmode << AQSFRC_LDMD_POS,
-+		       AQCSFRC_CFRC_LOAD_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_aq_set_csfrc_load_mode);
-+
-+int ehrpwm_aq_continuous_frc(struct pwm_device *p, unsigned char ch,
-+	unsigned char act)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (ch > 1)
-+		return -EINVAL;
-+
-+	if (ch == 0)
-+		ehrpwm_reg_config(ehrpwm, AQCSFRC, act, AQCSFRC_OUTA_MASK);
-+	else
-+		ehrpwm_reg_config(ehrpwm, AQCSFRC, act << AQCSFRC_OUTB_POS,
-+			       AQCSFRC_OUTB_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_aq_continuous_frc);
-+
-+int ehrpwm_db_get_max_delay(struct pwm_device *p, enum config_mask cfgmask,
-+	unsigned long *delay_val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned long delay_ns;
-+	unsigned long max_ticks;
-+
-+	if (cfgmask == CONFIG_NS) {
-+		max_ticks = 0x3ff * ehrpwm->prescale_val;
-+		delay_ns = pwm_ticks_to_ns(p, max_ticks);
-+		*delay_val = delay_ns;
-+	} else if (cfgmask == CONFIG_TICKS) {
-+		*delay_val = 0x3ff * ehrpwm->prescale_val;
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_db_get_max_delay);
-+
-+int ehrpwm_db_get_delay(struct pwm_device *p, unsigned char edge,
-+	enum config_mask cfgmask, unsigned long *delay_val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned long delay_ns;
-+	unsigned long delay_ticks;
-+	unsigned char offset;
-+
-+	if (!ehrpwm)
-+		return -EINVAL;
-+
-+	if (edge == RISING_EDGE_DELAY)
-+		offset = DBRED;
-+	else if (edge == FALLING_EDGE_DELAY)
-+		offset = DBFED;
-+	else
-+		return -EINVAL;
-+
-+	delay_ticks = ehrpwm_read(ehrpwm, offset);
-+	/* Only least 10 bits are required */
-+	delay_ticks = delay_ticks & 0x3ff;
-+	if (cfgmask == CONFIG_TICKS) {
-+		*delay_val = delay_ticks * ehrpwm->prescale_val;
-+	} else if (cfgmask == CONFIG_NS) {
-+		delay_ticks = delay_ticks * ehrpwm->prescale_val;
-+		delay_ns = pwm_ticks_to_ns(p, delay_ticks);
-+		debug("\n delay ns value is %lu", delay_ns);
-+		*delay_val = delay_ns;
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_db_get_delay);
-+
-+int ehrpwm_db_set_delay(struct pwm_device *p, unsigned char edge,
-+		enum config_mask cfgmask, unsigned long delay)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned long delay_ticks;
-+	unsigned char offset = 0;
-+
-+	if (!ehrpwm)
-+		return -EINVAL;
-+
-+	if (edge == RISING_EDGE_DELAY)
-+		offset = DBRED;
-+	else if (edge == FALLING_EDGE_DELAY)
-+		offset = DBFED;
-+	else
-+		return -EINVAL;
-+
-+	if (cfgmask == CONFIG_TICKS) {
-+		delay = delay / ehrpwm->prescale_val;
-+		if (delay > 0x3ff)
-+			return -EINVAL;
-+		ehrpwm_write(ehrpwm, offset, delay);
-+	} else if (cfgmask == CONFIG_NS) {
-+		delay_ticks = pwm_ns_to_ticks(p, delay);
-+		delay_ticks = delay_ticks / ehrpwm->prescale_val;
-+		if (delay_ticks > 0x3ff) {
-+			ehrpwm_db_get_max_delay(p, CONFIG_NS, &delay_ticks);
-+			dev_dbg(p->dev, "%s: Expected delay cannot be"
-+			" attained setting the maximum possible delay of"
-+			" %lu ns", __func__, delay_ticks);
-+			delay_ticks = 0x3ff;
-+		}
-+		debug("\n delay ticks is %lu", delay_ticks);
-+		ehrpwm_write(ehrpwm, offset, delay_ticks);
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_db_set_delay);
-+
-+/* Dead Band Configuration functions */
-+int ehrpwm_db_set_mode(struct pwm_device *p, unsigned char inmode,
-+		unsigned char polsel, unsigned char outmode)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (inmode > 0x3 || polsel > 0x3 || outmode > 0x3)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, DBCTL, inmode << DBCTL_INMODE_POS,
-+		       DBCTL_INMODE_MASK);
-+	ehrpwm_reg_config(ehrpwm, DBCTL, polsel << DBCTL_POLSEL_POS,
-+		       DBCTL_PLSEL_MASK);
-+	ehrpwm_reg_config(ehrpwm, DBCTL, outmode, DBCTL_OUTMODE_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_db_set_mode);
-+
-+/* PWM chopper Configuration functions */
-+int ehrpwm_pc_configure(struct pwm_device *p, unsigned char chpduty,
-+		unsigned char chpfreq, unsigned char oshtwidth)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (chpduty > 0x7 || chpfreq > 0x7 || oshtwidth > 0xf)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, PCCTL, chpduty << PCCTL_CHPDUTY_POS,
-+		       PCCTL_CHPDUTY_MASK);
-+	ehrpwm_reg_config(ehrpwm, PCCTL, chpfreq << PCCTL_CHPFRQ_POS,
-+		       PCCTL_CHPFREQ_MASK);
-+	ehrpwm_reg_config(ehrpwm, PCCTL, oshtwidth << PCCTL_OSTWID_POS,
-+		       PCCTL_OSHTWTH_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_pc_configure);
-+
-+int ehrpwm_pc_en_dis(struct pwm_device *p, unsigned char chpen)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (chpen > 1)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, PCCTL, chpen, BIT(0));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_pc_en_dis);
-+
-+/* Trip Zone configuration functions */
-+int ehrpwm_tz_sel_event(struct pwm_device *p, unsigned char input,
-+	       enum tz_event evt)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	unsigned short val = 0;
-+	unsigned short mask;
-+	unsigned short pos;
-+
-+	if (evt > 4 || input > 7)
-+		return -EINVAL;
-+
-+	switch (evt) {
-+	case TZ_ONE_SHOT_EVENT:
-+		pos = input + 8;
-+		mask = BIT((pos)) | BIT(input);
-+		ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
-+		break;
-+
-+	case TZ_CYCLE_BY_CYCLE:
-+		pos = input;
-+		mask = BIT(pos) | BIT((pos + 8));
-+		ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
-+		break;
-+
-+	case TZ_OSHT_CBC:
-+	case TZ_DIS_EVT:
-+		if (evt == TZ_OSHT_CBC)
-+			val = 1;
-+		else
-+			val = 0;
-+
-+		pos = input + 8;
-+		mask = BIT((pos));
-+		ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
-+		pos = input;
-+		mask = BIT((pos));
-+		ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
-+		break;
-+
-+	default:
-+		dev_dbg(p->dev, "%s: Invalid command", __func__);
-+		return -EINVAL;
-+	}
-+	debug("\n TZ_sel val is %0x", ehrpwm_read(ehrpwm, TZSEL));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tz_sel_event);
-+
-+int ehrpwm_tz_set_action(struct pwm_device *p, unsigned char ch,
-+	unsigned char act)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (act > 0x3 || ch > 1)
-+		return -EINVAL;
-+
-+	if (ch == 0)
-+		ehrpwm_reg_config(ehrpwm, TZCTL, act, TZCTL_ACTA_MASK);
-+	else
-+		ehrpwm_reg_config(ehrpwm, TZCTL, act << TZCTL_ACTB_POS,
-+			       TZCTL_ACTB_MASK);
-+
-+	debug("\n TZCTL reg val is %0x", ehrpwm_read(ehrpwm, TZCTL));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tz_set_action);
-+
-+int ehrpwm_tz_set_int_en_dis(struct pwm_device *p, enum tz_event event,
-+		unsigned char int_en_dis)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (event == TZ_ONE_SHOT_EVENT)
-+		ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
-+			       TZEINT_OSHTEVT_POS, BIT(2));
-+	else if (event == TZ_CYCLE_BY_CYCLE)
-+		ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
-+			       TZEINT_CBCEVT_POS, BIT(1));
-+	else
-+		return -EINVAL;
-+
-+	debug("\n TZEINT reg val is %0x", ehrpwm_read(ehrpwm, TZEINT));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tz_set_int_en_dis);
-+
-+int ehrpwm_tz_force_evt(struct pwm_device *p, enum tz_event event)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (event == TZ_ONE_SHOT_EVENT)
-+		ehrpwm_write(ehrpwm, TZFRC, 0x4);
-+	else if (event == TZ_CYCLE_BY_CYCLE)
-+		ehrpwm_write(ehrpwm, TZFRC, 0x2);
-+	else
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tz_force_evt);
-+
-+inline int ehrpwm_tz_read_status(struct pwm_device *p, unsigned short *status)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	*status = ehrpwm_read(ehrpwm, TZFLG);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tz_read_status);
-+
-+inline int ehrpwm_tz_clr_evt_status(struct pwm_device *p)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned short ret;
-+
-+	ret = ehrpwm_read(ehrpwm, TZFLG);
-+	ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tz_clr_evt_status);
-+
-+inline int ehrpwm_tz_clr_int_status(struct pwm_device *p)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	ehrpwm_write(ehrpwm, TZCLR, 0x1);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tz_clr_int_status);
-+
-+/* Event Trigger Configuration functions */
-+int ehrpwm_et_set_sel_evt(struct pwm_device *p, unsigned char evt,
-+		unsigned char prd)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (evt > 0x7 || prd > 0x3)
-+		return -EINVAL;
-+
-+	ehrpwm_reg_config(ehrpwm, ETSEL, evt, ETSEL_INTSEL_MASK);
-+	ehrpwm_reg_config(ehrpwm, ETPS, prd, ETPS_INTPRD_MASK);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_et_set_sel_evt);
-+
-+inline int ehrpwm_et_int_en_dis(struct pwm_device *p, unsigned char en_dis)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	ehrpwm_reg_config(ehrpwm, ETSEL, en_dis << ETSEL_EN_INT_EN_POS, BIT(3));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_et_int_en_dis);
-+
-+inline int ehrpwm_et_read_evt_cnt(struct pwm_device *p,
-+	unsigned long *evtcnt)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	*evtcnt = ehrpwm_read(ehrpwm, ETPS) & ETPS_INTCNT_MASK;
-+	*evtcnt >>= 0x2;
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_et_read_evt_cnt);
-+
-+inline int ehrpwm_et_read_int_status(struct pwm_device *p,
-+	unsigned long *status)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	*status = ehrpwm_read(ehrpwm, ETFLG) & BIT(0);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_et_read_int_status);
-+
-+inline int ehrpwm_et_frc_int(struct pwm_device *p)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	ehrpwm_write(ehrpwm, ETFRC, ENABLE);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_et_frc_int);
-+
-+inline int ehrpwm_et_clr_int(struct pwm_device *p)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	ehrpwm_write(ehrpwm, ETCLR, ENABLE);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_et_clr_int);
-+
-+/* High Resolution Module configuration */
-+inline int ehrpwm_hr_set_phase(struct pwm_device *p, unsigned char val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	ehrpwm_write(ehrpwm, TBPHSHR, val << 8);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_hr_set_phase);
-+
-+inline int ehrpwm_hr_set_cmpval(struct pwm_device *p, unsigned char val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	ehrpwm_write(ehrpwm, CMPAHR, val << 8);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_hr_set_cmpval);
-+
-+int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode,
-+		unsigned char ctlmode, unsigned char edgemode)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (loadmode > 1 || ctlmode > 1 || edgemode > 3)
-+		return -EINVAL;
-+
-+	if (ehrpwm->version == PWM_VERSION_1) {
-+		ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
-+				loadmode << HRCNFG_LDMD_POS, BIT(3));
-+		ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
-+				ctlmode << HRCNFG_CTLMD_POS, BIT(2));
-+		ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
-+				edgemode, HRCNFG_EDGEMD_MASK);
-+	} else {
-+		ehrpwm_reg_config(ehrpwm, HRCNFG,
-+				loadmode << HRCNFG_LDMD_POS, BIT(3));
-+		ehrpwm_reg_config(ehrpwm, HRCNFG,
-+				ctlmode << HRCNFG_CTLMD_POS, BIT(2));
-+		ehrpwm_reg_config(ehrpwm, HRCNFG,
-+				edgemode, HRCNFG_EDGEMD_MASK);
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_hr_config);
-+
-+inline int ehrpwm_reg_read(struct pwm_device *p, unsigned int reg,
-+	       unsigned short *val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (!(ehrpwm->version == PWM_VERSION_1)) {
-+		if (reg > HRCNFG)
-+			return -EINVAL;
-+	}
-+
-+	*val = ehrpwm_read(ehrpwm, reg);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_reg_read);
-+
-+inline int ehrpwm_reg_write(struct pwm_device *p, unsigned int reg,
-+	       unsigned short val)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (!(ehrpwm->version == PWM_VERSION_1)) {
-+		if (reg > HRCNFG)
-+			return -EINVAL;
-+	}
-+
-+	ehrpwm_write(ehrpwm, reg, val);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_reg_write);
-+
-+static int ehrpwm_pwm_set_pol(struct pwm_device *p)
-+{
-+	unsigned int act_ctrl_reg;
-+	unsigned int cmp_reg;
-+	unsigned int ctreqcmp_mask;
-+	unsigned int ctreqcmp;
-+	unsigned short val;
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	int chan;
-+
-+	chan = p - &ehrpwm->pwm[0];
-+	if (!chan) {
-+		act_ctrl_reg = AQCTLA;
-+		cmp_reg = CMPA;
-+		ctreqcmp_mask = ACTCTL_CAU_MASK;
-+		ctreqcmp = 4;
-+	} else {
-+		act_ctrl_reg = AQCTLB;
-+		cmp_reg = CMPB;
-+		ctreqcmp_mask = ACTCTL_CBU_MASK;
-+		ctreqcmp = 8;
-+	}
-+
-+
-+	pm_runtime_get_sync(ehrpwm->dev);
-+	val = ((p->active_high ? ACTCTL_CTREQCMP_HIGH : ACTCTL_CTREQCMP_LOW)
-+		 << ctreqcmp) | (p->active_high ? ACTCTL_CTREQZRO_LOW :
-+			ACTCTL_CTREQZRO_HIGH);
-+	ehrpwm_write(ehrpwm, act_ctrl_reg, val);
-+	pm_runtime_put_sync(ehrpwm->dev);
-+	return 0;
-+}
-+
-+static int ehrpwm_pwm_start(struct pwm_device *p)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned short val;
-+	unsigned short read_val1;
-+	unsigned short read_val2;
-+	int chan;
-+
-+
-+	/* Trying to start a running PWM, not allowed */
-+	if (pwm_is_running(p))
-+		return -EPERM;
-+
-+	/* For PWM clock should be enabled on start */
-+	pm_runtime_get_sync(ehrpwm->dev);
-+
-+	ehrpwm_pwm_set_pol(p);
-+	chan = p - &ehrpwm->pwm[0];
-+	val = ehrpwm_read(ehrpwm, TBCTL);
-+	val = (val & ~TBCTL_CTRMODE_MASK) | (TBCTL_CTRMOD_CTRUP |
-+		 TBCTL_FREERUN_FREE << 14);
-+	ehrpwm_write(ehrpwm, TBCTL, val);
-+	ehrpwm_tz_set_action(p, chan, 0x3);
-+	read_val1 = ehrpwm_read(ehrpwm, TZFLG);
-+	read_val2 = ehrpwm_read(ehrpwm, TZCTL);
-+	/*
-+	 * State of the other channel is determined by reading the
-+	 * TZCTL register. If the other channel is also in running state,
-+	 * one shot event status is cleared, otherwise one shot action for
-+	 * this channel is set to "DO NOTHING.
-+	 */
-+	read_val2 = read_val2 & (chan ? 0x3 : (0x3 << 2));
-+	read_val2 = chan ? read_val2 : (read_val2 >> 2);
-+	if (!(read_val1 & 0x4) || (read_val2 == 0x3))
-+		ehrpwm_tz_clr_evt_status(p);
-+
-+	set_bit(FLAG_RUNNING, &p->flags);
-+	return 0;
-+}
-+
-+/*
-+ * Stop function is implemented using the Trip Zone module. Action for the
-+ * corresponding channel is set to low and the one shot software force
-+ * event is triggered.
-+ */
-+static int ehrpwm_pwm_stop(struct pwm_device *p)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned short read_val;
-+	int chan;
-+
-+	/* Trying to stop a non-running PWM, not allowed */
-+	if (!pwm_is_running(p))
-+		return -EPERM;
-+
-+	chan = p - &ehrpwm->pwm[0];
-+	/* Set the Trip Zone Action to low */
-+	ehrpwm_tz_set_action(p, chan, 0x2);
-+	read_val = ehrpwm_read(ehrpwm, TZFLG);
-+	/*
-+	 * If the channel is already in stop state, Trip Zone software force is
-+	 * not required
-+	 */
-+	if (!(read_val & 0x4)) {
-+		ehrpwm_tz_clr_evt_status(p);
-+		ehrpwm_tz_force_evt(p, TZ_ONE_SHOT_EVENT);
-+	}
-+
-+	/* For PWM clock should be disabled on stop */
-+	pm_runtime_put_sync(ehrpwm->dev);
-+	clear_bit(FLAG_RUNNING, &p->flags);
-+	return 0;
-+}
-+
-+/*
-+ * Prescalar is used when the period value exceeds the maximum value
-+ * of the 16 bit period register. We always look for the minimum prescalar
-+ * value as it would result in wide range of duty control
-+ */
-+static char get_divider_val(unsigned int desired_ps_val, unsigned int
-+*ps_div_val, unsigned int *tb_div_val)
-+{
-+	char i = 0;
-+	char j = 0;
-+
-+	for (i = 0; i <= 7; i++) {
-+		for (j = 0; j <= 7; j++) {
-+			if (((1 << i) * (j ? (j * 2) : 1)) >= desired_ps_val) {
-+				*ps_div_val = (1 << i) * (j ? (j * 2) : 1);
-+				*tb_div_val = (i << 10) | (j << 7) ;
-+				return 0;
-+			}
-+		}
-+	}
-+
-+	return -1;
-+}
-+
-+static int ehrpwm_pwm_set_prd(struct pwm_device *p)
-+{
-+	unsigned int ps_div_val = 1;
-+	unsigned int tb_div_val = 0;
-+	char ret;
-+	unsigned short val;
-+	unsigned short period_ticks;
-+	struct pwm_device *temp;
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	int chan = 0;
-+	/*
-+	 * Since the device has a singe period register, copy the period
-+	 * value to the other channel also.
-+	 */
-+	chan = p - &ehrpwm->pwm[0];
-+	temp = &ehrpwm->pwm[!chan];
-+	temp->period_ticks = p->period_ticks;
-+	temp->period_ns = p->period_ns;
-+	debug("\n period_ticks is %lu", p->period_ticks);
-+
-+	if (p->period_ticks > 65535) {
-+		ret = get_divider_val(p->period_ticks / 65535 + 1, &ps_div_val,
-+				&tb_div_val);
-+		if (ret) {
-+			dev_err(p->dev, "failed to get the divider value");
-+			return -EINVAL;
-+		}
-+	}
-+
-+	pm_runtime_get_sync(ehrpwm->dev);
-+	val = ehrpwm_read(ehrpwm, TBCTL);
-+	val = (val & ~TBCTL_CLKDIV_MASK & ~TBCTL_HSPCLKDIV_MASK) | tb_div_val;
-+	ehrpwm_write(ehrpwm, TBCTL, val);
-+	period_ticks = p->period_ticks / ps_div_val;
-+
-+	if (period_ticks <= 1) {
-+		dev_err(p->dev, "Required period/frequency cannot be obtained");
-+		pm_runtime_put_sync(ehrpwm->dev);
-+		return -EINVAL;
-+	}
-+	/*
-+	 * Program the period register with 1 less than the actual value since
-+	 * the module generates waveform with period always 1 greater
-+	 * the programmed value.
-+	 */
-+	ehrpwm_write(ehrpwm, TBPRD, (unsigned short)(period_ticks - 1));
-+	pm_runtime_put_sync(ehrpwm->dev);
-+	debug("\n period_ticks is %d", period_ticks);
-+	ehrpwm->prescale_val = ps_div_val;
-+	debug("\n Prescaler value is %d", ehrpwm->prescale_val);
-+
-+	return 0;
-+}
-+
-+static int ehrpwm_hr_duty_config(struct pwm_device *p)
-+{
-+	unsigned char no_of_mepsteps;
-+	unsigned short cmphr_val;
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+
-+	if (!p->tick_hz) {
-+		dev_dbg(p->dev, "%s: p->tick_hz is zero\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	/*
-+	 * Calculate the no of MEP steps. Assume system clock
-+	 * is in the order of MHZ.
-+	 */
-+	no_of_mepsteps = USEC_PER_SEC / ((p->tick_hz / USEC_PER_SEC) * 63);
-+
-+	pm_runtime_get_sync(ehrpwm->dev);
-+	/* Calculate the CMPHR Value */
-+	cmphr_val = p->tick_hz / USEC_PER_SEC;
-+	cmphr_val = (p->duty_ns * cmphr_val) % MSEC_PER_SEC;
-+	cmphr_val = (cmphr_val * no_of_mepsteps) / 1000;
-+	cmphr_val = (cmphr_val << 8) + 0x180;
-+	ehrpwm_write(ehrpwm, CMPAHR, cmphr_val);
-+
-+	if (ehrpwm->version == PWM_VERSION_1)
-+		ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
-+	else
-+		ehrpwm_write(ehrpwm, HRCNFG, 0x2);
-+
-+	pm_runtime_put_sync(ehrpwm->dev);
-+	return 0;
-+}
-+
-+static int ehrpwm_pwm_set_dty(struct pwm_device *p)
-+{
-+	unsigned short duty_ticks = 0;
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	int ret = 0;
-+	int chan;
-+
-+	chan = p - &ehrpwm->pwm[0];
-+
-+	if (!ehrpwm->prescale_val) {
-+		dev_dbg(p->dev, "%s: prescale_val is zero\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	duty_ticks = p->duty_ticks / ehrpwm->prescale_val;
-+	debug("\n Prescaler value is %d", ehrpwm->prescale_val);
-+	debug("\n duty ticks is %d", duty_ticks);
-+	pm_runtime_get_sync(ehrpwm->dev);
-+	/* High resolution module */
-+	if (chan && ehrpwm->prescale_val <= 1) {
-+		ret = ehrpwm_hr_duty_config(p);
-+		if (ehrpwm->version == PWM_VERSION_1)
-+			ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
-+		else
-+			ehrpwm_write(ehrpwm, HRCNFG, 0x2);
-+	}
-+
-+	ehrpwm_write(ehrpwm, (chan ? CMPB : CMPA), duty_ticks);
-+	pm_runtime_put_sync(ehrpwm->dev);
-+	return ret;
-+}
-+
-+int ehrpwm_et_cb_register(struct pwm_device *p, void *data,
-+	p_fcallback cb)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&ehrpwm->lock, flags);
-+	ehrpwm->st_etint.data = data;
-+	ehrpwm->st_etint.pcallback = cb;
-+	spin_unlock_irqrestore(&ehrpwm->lock, flags);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_et_cb_register);
-+
-+int ehrpwm_tz_cb_register(struct pwm_device *p, void *data,
-+	p_fcallback cb)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&ehrpwm->lock, flags);
-+	ehrpwm->st_tzint.data = data;
-+	ehrpwm->st_tzint.pcallback = cb;
-+	spin_unlock_irqrestore(&ehrpwm->lock, flags);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_tz_cb_register);
-+
-+static int ehrpwm_pwm_suspend_cb(struct ehrpwm_pwm *ehrpwm, void *data)
-+{
-+	struct ehrpwm_suspend_params *pwm_suspend_params =
-+				(struct ehrpwm_suspend_params *)data;
-+
-+	if (pwm_suspend_params->act_delay++ >= pwm_suspend_params->
-+			req_delay_cycles) {
-+		pwm_start(pwm_suspend_params->pch);
-+		ehrpwm_et_cb_register(pwm_suspend_params->pch, NULL, NULL);
-+		ehrpwm_et_int_en_dis(pwm_suspend_params->pch, DISABLE);
-+	}
-+
-+	return 0;
-+}
-+
-+int ehrpwm_pwm_suspend(struct pwm_device *p, enum config_mask config_mask,
-+	       unsigned long val)
-+{
-+	unsigned long long req_cycles = 0;
-+
-+	if (!p->period_ns)
-+		return -EINVAL;
-+
-+	ehrpwm_pwm_stop(p);
-+	/* Calculate the delay in terms of cycles */
-+	if (config_mask == CONFIG_NS)
-+		req_cycles =  val / p->period_ns;
-+	else if (config_mask == CONFIG_TICKS)
-+		req_cycles = val;
-+	else
-+		return -EINVAL;
-+
-+	/* Configute the event interrupt */
-+	ehrpwm_et_set_sel_evt(p, 0x2, 0x1);
-+	ehrpwm_suspend_params.pch = p;
-+	ehrpwm_suspend_params.req_delay_cycles = req_cycles;
-+	ehrpwm_suspend_params.act_delay = 0;
-+	ehrpwm_et_cb_register(p, &ehrpwm_suspend_params,
-+		ehrpwm_pwm_suspend_cb);
-+	ehrpwm_et_int_en_dis(p, ENABLE);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ehrpwm_pwm_suspend);
-+
-+static irqreturn_t ehrpwm_trip_zone_irq_handler(int irq, void *data)
-+{
-+	struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
-+	unsigned long flags;
-+	int ret = 0;
-+
-+	spin_lock_irqsave(&ehrpwm->lock, flags);
-+	 ret = ehrpwm_read(ehrpwm, TZFLG);
-+	if (!(ret & 0x1))
-+		return IRQ_NONE;
-+
-+	if (ehrpwm->st_tzint.pcallback)
-+		ret = ehrpwm->st_tzint.pcallback(ehrpwm, ehrpwm->st_tzint.data);
-+
-+	ret = ehrpwm_read(ehrpwm, TZFLG);
-+	ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
-+	ehrpwm_write(ehrpwm, TZCLR, 0x1);
-+	spin_unlock_irqrestore(&ehrpwm->lock, flags);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t ehrpwm_event_irq_handler(int irq, void *data)
-+{
-+	struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&ehrpwm->lock, flags);
-+
-+	if (ehrpwm->st_etint.pcallback)
-+		ehrpwm->st_etint.pcallback(ehrpwm, ehrpwm->st_etint.data);
-+
-+	ehrpwm_write(ehrpwm, ETCLR, 0x1);
-+
-+	spin_unlock_irqrestore(&ehrpwm->lock, flags);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int ehrpwm_pwm_config(struct pwm_device *p,
-+	struct pwm_config *c)
-+{
-+	int ret = 0;
-+
-+	switch (c->config_mask) {
-+	case BIT(PWM_CONFIG_PERIOD_TICKS):
-+		if (p->max_period_ticks &&
-+				(p->max_period_ticks >= c->period_ticks))
-+			p->period_ticks = p->max_period_ticks;
-+		else
-+			p->period_ticks = c->period_ticks;
-+
-+		ret = ehrpwm_pwm_set_prd(p);
-+		break;
-+
-+	case BIT(PWM_CONFIG_DUTY_TICKS):
-+		p->duty_ticks = c->duty_ticks;
-+		ret = ehrpwm_pwm_set_dty(p);
-+		break;
-+
-+	case BIT(PWM_CONFIG_POLARITY):
-+		p->active_high = c->polarity;
-+		ret = ehrpwm_pwm_set_pol(p);
-+		break;
-+
-+	case BIT(PWM_CONFIG_START):
-+		 ret = ehrpwm_pwm_start(p);
-+		 break;
-+
-+	case BIT(PWM_CONFIG_STOP):
-+		ret = ehrpwm_pwm_stop(p);
-+		break;
-+
-+	default:
-+		dev_dbg(p->dev, "%s: Invalid configuration\n", __func__);
-+		ret = -EINVAL;
-+	}
-+
-+	return ret;
-+}
-+
-+static int ehrpwm_pwm_request(struct pwm_device *p)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	int chan;
-+
-+	chan = p - &ehrpwm->pwm[0];
-+
-+	p->tick_hz = clk_get_rate(ehrpwm->clk);
-+	debug("\n The clk freq is %lu", p->tick_hz);
-+	ehrpwm_pwm_stop(p);
-+
-+	return 0;
-+}
-+
-+static int ehrpwm_freq_transition_cb(struct pwm_device *p)
-+{
-+	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
-+	unsigned long duty_ns;
-+
-+	p->tick_hz = clk_get_rate(ehrpwm->clk);
-+	duty_ns = p->duty_ns;
-+	if (pwm_is_running(p)) {
-+		pwm_stop(p);
-+		pwm_set_duty_ns(p, 0);
-+		pwm_set_period_ns(p, p->period_ns);
-+		pwm_set_duty_ns(p, duty_ns);
-+		pwm_start(p);
-+	} else {
-+		pwm_set_duty_ns(p, 0);
-+		pwm_set_period_ns(p, p->period_ns);
-+		pwm_set_duty_ns(p, duty_ns);
-+	}
-+		return 0;
-+}
-+
-+static int ehrpwm_probe(struct platform_device *pdev)
-+{
-+	struct ehrpwm_pwm *ehrpwm = NULL;
-+	struct resource *r;
-+	int ret = 0;
-+	int chan = 0;
-+	struct pwmss_platform_data *pdata = (&pdev->dev)->platform_data;
-+	int ch_mask = 0;
-+	int val;
-+	char con_id[PWM_CON_ID_STRING_LENGTH] = "epwmss";
-+
-+	ehrpwm = kzalloc(sizeof(*ehrpwm), GFP_KERNEL);
-+	if (!ehrpwm) {
-+		dev_err(&pdev->dev, "failed to allocate memory\n");
-+		ret = -ENOMEM;
-+		goto err_mem_failure;
-+	}
-+
-+	ehrpwm->version = pdata->version;
-+
-+	if (ehrpwm->version == PWM_VERSION_1) {
-+		sprintf(con_id, "%s%d_%s", con_id, pdev->id, "fck");
-+		ehrpwm->clk = clk_get(&pdev->dev, con_id);
-+	} else
-+		ehrpwm->clk = clk_get(&pdev->dev, "ehrpwm");
-+
-+	pm_runtime_enable(&pdev->dev);
-+	ehrpwm->dev = &pdev->dev;
-+	if (IS_ERR(ehrpwm->clk)) {
-+		ret = PTR_ERR(ehrpwm->clk);
-+		goto err_clock_failure;
-+	}
-+
-+	if (ehrpwm->version == PWM_VERSION_1) {
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+		if (!r) {
-+			dev_err(&pdev->dev, "no memory resource defined\n");
-+			ret = -ENOMEM;
-+			goto err_resource_mem_failure;
-+		}
-+
-+		ehrpwm->config_mem_base = ioremap(r->start, resource_size(r));
-+
-+		if (!ehrpwm->config_mem_base) {
-+
-+			dev_err(&pdev->dev, "failed to ioremap() registers\n");
-+			ret = -ENODEV;
-+			goto err_free_mem_config;
-+		}
-+
-+		pm_runtime_get_sync(ehrpwm->dev);
-+		val = readw(ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
-+		val |= BIT(EPWM_CLK_EN);
-+		writew(val, ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
-+		pm_runtime_put_sync(ehrpwm->dev);
-+	} else
-+		ch_mask = pdata->channel_mask;
-+
-+	spin_lock_init(&ehrpwm->lock);
-+	ehrpwm->ops.config = ehrpwm_pwm_config;
-+	ehrpwm->ops.request = ehrpwm_pwm_request;
-+	ehrpwm->ops.freq_transition_notifier_cb = ehrpwm_freq_transition_cb;
-+	ehrpwm->prescale_val = 1;
-+
-+	if (ehrpwm->version == PWM_VERSION_1)
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	else
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+	if (!r) {
-+		dev_err(&pdev->dev, "no memory resource defined\n");
-+		ret = -ENODEV;
-+		goto err_resource_mem2_failiure;
-+	}
-+
-+	r = request_mem_region(r->start, resource_size(r), pdev->name);
-+	if (!r) {
-+		dev_err(&pdev->dev, "failed to request memory resource\n");
-+		ret = -EBUSY;
-+		goto err_request_mem2_failure;
-+	}
-+
-+	ehrpwm->mmio_base = ioremap(r->start, resource_size(r));
-+	if (!ehrpwm->mmio_base) {
-+		dev_err(&pdev->dev, "failed to ioremap() registers\n");
-+		ret = -ENODEV;
-+		goto err_free_mem2;
-+	}
-+
-+	ehrpwm->irq[0] = platform_get_irq(pdev, 0);
-+	if (ehrpwm->irq[0] == -ENXIO) {
-+		dev_err(&pdev->dev, "No IRQ resource\n");
-+		ret = -ENXIO;
-+		goto err_free_io;
-+	}
-+
-+	ret = request_irq(ehrpwm->irq[0], ehrpwm_trip_zone_irq_handler,
-+				0, "ehrpwmTZ", ehrpwm);
-+	if (ret)
-+		goto err_free_io;
-+
-+	ehrpwm->irq[1] = platform_get_irq(pdev, 1);
-+	if (ehrpwm->irq[1] == -ENXIO) {
-+		dev_err(&pdev->dev, "No IRQ resource\n");
-+		ret = -ENXIO;
-+		goto err_request_irq;
-+	}
-+
-+	ret = request_irq(ehrpwm->irq[1], ehrpwm_event_irq_handler,
-+				0, "ehrpwm_evt", ehrpwm);
-+	if (ret)
-+		goto err_request_irq;
-+
-+	for (chan = 0; chan < NCHAN; chan++) {
-+		ehrpwm->pwm[chan].ops = &ehrpwm->ops;
-+		pwm_set_drvdata(&ehrpwm->pwm[chan], ehrpwm);
-+		ehrpwm->pwm[chan].tick_hz = clk_get_rate(ehrpwm->clk);
-+
-+		if (pdata->chan_attrib[chan].max_freq) {
-+			int period_ns = NSEC_PER_SEC
-+				/ pdata->chan_attrib[chan].max_freq;
-+
-+			ehrpwm->pwm[chan].max_period_ticks =
-+				pwm_ns_to_ticks(&ehrpwm->pwm[chan], period_ns);
-+		}
-+
-+		if (!(ehrpwm->version == PWM_VERSION_1)) {
-+			if (!(ch_mask & (0x1 << chan)))
-+				continue;
-+		}
-+
-+		ret =  pwm_register(&ehrpwm->pwm[chan], &pdev->dev, chan);
-+		if (ret)
-+			goto err_pwm_register;
-+	}
-+
-+		platform_set_drvdata(pdev, ehrpwm);
-+	return 0;
-+
-+err_pwm_register:
-+	for (chan = 0; chan < NCHAN; chan++) {
-+		if (pwm_is_registered(&ehrpwm->pwm[chan]))
-+			pwm_unregister(&ehrpwm->pwm[chan]);
-+	}
-+
-+err_request_irq:
-+	if (ehrpwm->irq[0] != -ENXIO)
-+		free_irq(ehrpwm->irq[0], ehrpwm);
-+err_free_io:
-+	iounmap(ehrpwm->mmio_base);
-+err_free_mem2:
-+	release_mem_region(r->start, resource_size(r));
-+err_request_mem2_failure:
-+err_resource_mem2_failiure:
-+	if (ehrpwm->version == PWM_VERSION_1) {
-+		iounmap(ehrpwm->config_mem_base);
-+		ehrpwm->config_mem_base = NULL;
-+	}
-+err_free_mem_config:
-+err_resource_mem_failure:
-+	clk_put(ehrpwm->clk);
-+	pm_runtime_disable(ehrpwm->dev);
-+err_clock_failure:
-+	kfree(ehrpwm);
-+err_mem_failure:
-+	return ret;
-+}
-+
-+#ifdef CONFIG_PM
-+
-+void ehrpwm_context_save(struct ehrpwm_pwm *ehrpwm,
-+		struct ehrpwm_context *ehrpwm_ctx)
-+{
-+	pm_runtime_get_sync(ehrpwm->dev);
-+	ehrpwm_ctx->tbctl = ehrpwm_read(ehrpwm, TBCTL);
-+	ehrpwm_ctx->tbprd = ehrpwm_read(ehrpwm, TBPRD);
-+	if (ehrpwm->version == PWM_VERSION_1)
-+		ehrpwm_ctx->hrcfg = ehrpwm_read(ehrpwm, AM335X_HRCNFG);
-+	else
-+		ehrpwm_ctx->hrcfg = ehrpwm_read(ehrpwm, HRCNFG);
-+	ehrpwm_ctx->aqctla = ehrpwm_read(ehrpwm, AQCTLA);
-+	ehrpwm_ctx->aqctlb = ehrpwm_read(ehrpwm, AQCTLB);
-+	ehrpwm_ctx->cmpa = ehrpwm_read(ehrpwm, CMPA);
-+	ehrpwm_ctx->cmpb = ehrpwm_read(ehrpwm, CMPB);
-+	ehrpwm_ctx->tzctl = ehrpwm_read(ehrpwm, TZCTL);
-+	ehrpwm_ctx->tzflg = ehrpwm_read(ehrpwm, TZFLG);
-+	ehrpwm_ctx->tzclr = ehrpwm_read(ehrpwm, TZCLR);
-+	ehrpwm_ctx->tzfrc = ehrpwm_read(ehrpwm, TZFRC);
-+	pm_runtime_put_sync(ehrpwm->dev);
-+}
-+
-+void ehrpwm_context_restore(struct ehrpwm_pwm *ehrpwm,
-+		struct ehrpwm_context *ehrpwm_ctx)
-+{
-+	ehrpwm_write(ehrpwm, TBCTL, ehrpwm_ctx->tbctl);
-+	ehrpwm_write(ehrpwm, TBPRD, ehrpwm_ctx->tbprd);
-+	if (ehrpwm->version == PWM_VERSION_1)
-+		ehrpwm_write(ehrpwm, AM335X_HRCNFG, ehrpwm_ctx->hrcfg);
-+	else
-+		ehrpwm_write(ehrpwm, HRCNFG, ehrpwm_ctx->hrcfg);
-+	ehrpwm_write(ehrpwm, AQCTLA, ehrpwm_ctx->aqctla);
-+	ehrpwm_write(ehrpwm, AQCTLB, ehrpwm_ctx->aqctlb);
-+	ehrpwm_write(ehrpwm, CMPA, ehrpwm_ctx->cmpa);
-+	ehrpwm_write(ehrpwm, CMPB, ehrpwm_ctx->cmpb);
-+	ehrpwm_write(ehrpwm, TZCTL, ehrpwm_ctx->tzctl);
-+	ehrpwm_write(ehrpwm, TZFLG, ehrpwm_ctx->tzflg);
-+	ehrpwm_write(ehrpwm, TZCLR, ehrpwm_ctx->tzclr);
-+	ehrpwm_write(ehrpwm, TZFRC, ehrpwm_ctx->tzfrc);
-+}
-+
-+static int ehrpwm_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+	struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
-+
-+	ehrpwm_context_save(ehrpwm, &ehrpwm->ctx);
-+	pm_runtime_put_sync(ehrpwm->dev);
-+
-+	return 0;
-+}
-+
-+static int ehrpwm_resume(struct platform_device *pdev)
-+{
-+	struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
-+
-+	pm_runtime_get_sync(ehrpwm->dev);
-+	ehrpwm_context_restore(ehrpwm, &ehrpwm->ctx);
-+
-+	return 0;
-+}
-+
-+#else
-+#define ehrpwm_suspend NULL
-+#define ehrpwm_resume NULL
-+#endif /* CONFIG_PM */
-+
-+static int __devexit ehrpwm_remove(struct platform_device *pdev)
-+{
-+	struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
-+	struct resource *r;
-+	unsigned char i;
-+	int val;
-+	struct pwmss_platform_data *pdata;
-+
-+	if (ehrpwm->version == PWM_VERSION_1) {
-+		pdata = (&pdev->dev)->platform_data;
-+		val = readw(ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
-+		val &= ~BIT(EPWM_CLK_EN);
-+		writew(val, ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
-+		iounmap(ehrpwm->config_mem_base);
-+		ehrpwm->config_mem_base = NULL;
-+	}
-+
-+	for (i = 0; i < NCHAN; i++) {
-+		if (pwm_is_registered(&ehrpwm->pwm[i]))
-+			pwm_unregister(&ehrpwm->pwm[i]);
-+	}
-+
-+	for (i = 0; i < 2; i++)
-+		if (ehrpwm->irq[i] != -ENXIO)
-+			free_irq(ehrpwm->irq[i], ehrpwm);
-+	iounmap(ehrpwm->mmio_base);
-+
-+	if (ehrpwm->version == PWM_VERSION_1)
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	else
-+		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+	release_mem_region(r->start, resource_size(r));
-+	platform_set_drvdata(pdev, NULL);
-+	clk_put(ehrpwm->clk);
-+	pm_runtime_disable(ehrpwm->dev);
-+	kfree(ehrpwm);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver ehrpwm_driver = {
-+	.driver	= {
-+		.name	= "ehrpwm",
-+		.owner	= THIS_MODULE,
-+	},
-+	.probe		= ehrpwm_probe,
-+	.remove		= __devexit_p(ehrpwm_remove),
-+	.suspend	= ehrpwm_suspend,
-+	.resume		= ehrpwm_resume,
-+};
-+
-+static int __init ehrpwm_init(void)
-+{
-+	return platform_driver_register(&ehrpwm_driver);
-+}
-+module_init(ehrpwm_init);
-+
-+static void __exit ehrpwm_exit(void)
-+{
-+	platform_driver_unregister(&ehrpwm_driver);
-+}
-+module_exit(ehrpwm_exit);
-+
-+MODULE_AUTHOR("Texas Instruments");
-+MODULE_DESCRIPTION("Driver for Davinci eHRPWM peripheral");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:ehrpwm");
-diff --git a/drivers/pwm/pwm.c b/drivers/pwm/pwm.c
-new file mode 100644
-index 0000000..b23b260
---- /dev/null
-+++ b/drivers/pwm/pwm.c
-@@ -0,0 +1,843 @@
-+/*
-+ * PWM API implementation
-+ *
-+ * Copyright (C) 2011 Bill Gatliff <bgat@billgatliff.com>
-+ * Copyright (C) 2011 Arun Murthy <arun.murthy@stericsson.com>
-+ *
-+ * This program is free software; you may redistribute and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-+ * USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/device.h>
-+#include <linux/fs.h>
-+#include <linux/completion.h>
-+#include <linux/workqueue.h>
-+#include <linux/list.h>
-+#include <linux/sched.h>
-+#include <linux/platform_device.h>
-+#include <linux/cpufreq.h>
-+#include <linux/pwm/pwm.h>
-+
-+static const char *REQUEST_SYSFS = "sysfs";
-+static LIST_HEAD(pwm_device_list);
-+static DEFINE_MUTEX(device_list_mutex);
-+static struct class pwm_class;
-+static struct workqueue_struct *pwm_handler_workqueue;
-+
-+static int pwm_match_name(struct device *dev, void *name)
-+{
-+	return !strcmp(name, dev_name(dev));
-+}
-+
-+static struct pwm_device *__pwm_request(struct pwm_device *p, const char *label)
-+{
-+	int ret;
-+
-+	ret = test_and_set_bit(FLAG_REQUESTED, &p->flags);
-+	if (ret) {
-+		p = ERR_PTR(-EBUSY);
-+		goto done;
-+	}
-+
-+	p->label = label;
-+	p->pid = current->pid;
-+
-+	if (p->ops->request) {
-+		ret = p->ops->request(p);
-+		if (ret) {
-+			p = ERR_PTR(ret);
-+			clear_bit(FLAG_REQUESTED, &p->flags);
-+			goto done;
-+		}
-+	}
-+
-+done:
-+	return p;
-+}
-+
-+static struct pwm_device *__pwm_request_byname(const char *name,
-+					       const char *label)
-+{
-+	struct device *d;
-+	struct pwm_device *p;
-+
-+	d = class_find_device(&pwm_class, NULL, (char *)name, pwm_match_name);
-+	if (!d) {
-+		p = ERR_PTR(-EINVAL);
-+		goto done;
-+	}
-+	if (IS_ERR(d)) {
-+		p = (struct pwm_device *)d;
-+		goto done;
-+	}
-+
-+	p = __pwm_request(dev_get_drvdata(d), label);
-+
-+done:
-+	return p;
-+}
-+
-+struct pwm_device *pwm_request_byname(const char *name, const char *label)
-+{
-+	struct pwm_device *p;
-+
-+	mutex_lock(&device_list_mutex);
-+	p = __pwm_request_byname(name, label);
-+	mutex_unlock(&device_list_mutex);
-+	return p;
-+}
-+EXPORT_SYMBOL(pwm_request_byname);
-+
-+struct pwm_device *pwm_request(const char *bus_id, int id, const char *label)
-+{
-+	char name[256];
-+	int ret;
-+
-+	if (id == -1)
-+		ret = scnprintf(name, sizeof name, "%s", bus_id);
-+	else
-+		ret = scnprintf(name, sizeof name, "%s:%d", bus_id, id);
-+	if (ret <= 0 || ret >= sizeof name)
-+		return ERR_PTR(-EINVAL);
-+
-+	return pwm_request_byname(name, label);
-+}
-+EXPORT_SYMBOL(pwm_request);
-+
-+void pwm_release(struct pwm_device *p)
-+{
-+	mutex_lock(&device_list_mutex);
-+
-+	if (!test_and_clear_bit(FLAG_REQUESTED, &p->flags)) {
-+		pr_debug("%s pwm device is not requested!\n",
-+				dev_name(p->dev));
-+		goto done;
-+	}
-+
-+	pwm_stop(p);
-+	pwm_unsynchronize(p, NULL);
-+	pwm_set_handler(p, NULL, NULL);
-+
-+	p->label = NULL;
-+	p->pid = -1;
-+
-+	if (p->ops->release)
-+		p->ops->release(p);
-+done:
-+	mutex_unlock(&device_list_mutex);
-+}
-+EXPORT_SYMBOL(pwm_release);
-+
-+unsigned long pwm_ns_to_ticks(struct pwm_device *p, unsigned long nsecs)
-+{
-+	unsigned long long ticks;
-+
-+	ticks = nsecs;
-+	ticks *= p->tick_hz;
-+	do_div(ticks, 1000000000);
-+	return ticks;
-+}
-+EXPORT_SYMBOL(pwm_ns_to_ticks);
-+
-+unsigned long pwm_ticks_to_ns(struct pwm_device *p, unsigned long ticks)
-+{
-+	unsigned long long ns;
-+
-+	if (!p->tick_hz) {
-+		pr_debug("%s: frequency is zero\n", dev_name(p->dev));
-+		return 0;
-+	}
-+
-+	ns = ticks;
-+	ns *= 1000000000UL;
-+	do_div(ns, p->tick_hz);
-+	return ns;
-+}
-+EXPORT_SYMBOL(pwm_ticks_to_ns);
-+
-+static void pwm_config_ns_to_ticks(struct pwm_device *p, struct pwm_config *c)
-+{
-+	if (test_bit(PWM_CONFIG_PERIOD_NS, &c->config_mask)) {
-+		c->period_ticks = pwm_ns_to_ticks(p, c->period_ns);
-+		clear_bit(PWM_CONFIG_PERIOD_NS, &c->config_mask);
-+		set_bit(PWM_CONFIG_PERIOD_TICKS, &c->config_mask);
-+	}
-+
-+	if (test_bit(PWM_CONFIG_DUTY_NS, &c->config_mask)) {
-+		c->duty_ticks = pwm_ns_to_ticks(p, c->duty_ns);
-+		clear_bit(PWM_CONFIG_DUTY_NS, &c->config_mask);
-+		set_bit(PWM_CONFIG_DUTY_TICKS, &c->config_mask);
-+	}
-+}
-+
-+static void pwm_config_percent_to_ticks(struct pwm_device *p,
-+					struct pwm_config *c)
-+{
-+	if (test_bit(PWM_CONFIG_DUTY_PERCENT, &c->config_mask)) {
-+		if (test_bit(PWM_CONFIG_PERIOD_TICKS, &c->config_mask))
-+			c->duty_ticks = c->period_ticks;
-+		else
-+			c->duty_ticks = p->period_ticks;
-+
-+		c->duty_ticks *= c->duty_percent;
-+		c->duty_ticks /= 100;
-+		clear_bit(PWM_CONFIG_DUTY_PERCENT, &c->config_mask);
-+		set_bit(PWM_CONFIG_DUTY_TICKS, &c->config_mask);
-+	}
-+}
-+
-+int pwm_config_nosleep(struct pwm_device *p, struct pwm_config *c)
-+{
-+	if (!p->ops->config_nosleep)
-+		return -EINVAL;
-+
-+	pwm_config_ns_to_ticks(p, c);
-+	pwm_config_percent_to_ticks(p, c);
-+
-+	return p->ops->config_nosleep(p, c);
-+}
-+EXPORT_SYMBOL(pwm_config_nosleep);
-+
-+int pwm_config(struct pwm_device *p, struct pwm_config *c)
-+{
-+	int ret = 0;
-+
-+	pwm_config_ns_to_ticks(p, c);
-+	pwm_config_percent_to_ticks(p, c);
-+
-+	switch (c->config_mask & (BIT(PWM_CONFIG_PERIOD_TICKS)
-+				  | BIT(PWM_CONFIG_DUTY_TICKS))) {
-+	case BIT(PWM_CONFIG_PERIOD_TICKS):
-+		if (p->duty_ticks > c->period_ticks) {
-+			ret = -EINVAL;
-+			goto err;
-+		}
-+		break;
-+	case BIT(PWM_CONFIG_DUTY_TICKS):
-+		if (p->period_ticks < c->duty_ticks) {
-+			ret = -EINVAL;
-+			goto err;
-+		}
-+		break;
-+	case BIT(PWM_CONFIG_DUTY_TICKS) | BIT(PWM_CONFIG_PERIOD_TICKS):
-+		if (c->duty_ticks > c->period_ticks) {
-+			ret = -EINVAL;
-+			goto err;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+err:
-+	dev_dbg(p->dev, "%s: config_mask %lu period_ticks %lu duty_ticks %lu"
-+		" polarity %d duty_ns %lu period_ns %lu duty_percent %d\n",
-+		__func__, c->config_mask, c->period_ticks, c->duty_ticks,
-+		c->polarity, c->duty_ns, c->period_ns, c->duty_percent);
-+
-+	if (ret)
-+		return ret;
-+	spin_lock(&p->pwm_lock);
-+	ret = p->ops->config(p, c);
-+	spin_unlock(&p->pwm_lock);
-+	return ret;
-+}
-+EXPORT_SYMBOL(pwm_config);
-+
-+int pwm_set_period_ns(struct pwm_device *p, unsigned long period_ns)
-+{
-+	struct pwm_config c = {
-+		.config_mask = BIT(PWM_CONFIG_PERIOD_TICKS),
-+		.period_ticks = pwm_ns_to_ticks(p, period_ns),
-+	};
-+
-+	spin_lock(&p->pwm_lock);
-+	p->period_ns = period_ns;
-+	spin_unlock(&p->pwm_lock);
-+	return pwm_config(p, &c);
-+}
-+EXPORT_SYMBOL(pwm_set_period_ns);
-+
-+unsigned long pwm_get_period_ns(struct pwm_device *p)
-+{
-+	return pwm_ticks_to_ns(p, p->period_ticks);
-+}
-+EXPORT_SYMBOL(pwm_get_period_ns);
-+
-+int pwm_set_frequency(struct pwm_device *p, unsigned long freq)
-+{
-+	struct pwm_config c;
-+
-+	if (!freq)
-+		return -EINVAL;
-+
-+	c.config_mask = BIT(PWM_CONFIG_PERIOD_TICKS),
-+	c.period_ticks = pwm_ns_to_ticks(p, (NSEC_PER_SEC / freq)),
-+	spin_lock(&p->pwm_lock);
-+	p->period_ns = NSEC_PER_SEC / freq;
-+	spin_unlock(&p->pwm_lock);
-+	return pwm_config(p, &c);
-+}
-+EXPORT_SYMBOL(pwm_set_frequency);
-+
-+unsigned long pwm_get_frequency(struct pwm_device *p)
-+{
-+	unsigned long period_ns;
-+
-+	 period_ns = pwm_ticks_to_ns(p, p->period_ticks);
-+
-+	if (!period_ns) {
-+		pr_debug("%s: frequency is zero\n", dev_name(p->dev));
-+		return 0;
-+	}
-+
-+	return	NSEC_PER_SEC / period_ns;
-+}
-+EXPORT_SYMBOL(pwm_get_frequency);
-+
-+int pwm_set_period_ticks(struct pwm_device *p,
-+					unsigned long ticks)
-+{
-+	struct pwm_config c = {
-+		.config_mask = BIT(PWM_CONFIG_PERIOD_TICKS),
-+		.period_ticks = ticks,
-+	};
-+
-+	spin_lock(&p->pwm_lock);
-+	p->period_ns = pwm_ticks_to_ns(p, ticks);
-+	spin_unlock(&p->pwm_lock);
-+	return pwm_config(p, &c);
-+}
-+EXPORT_SYMBOL(pwm_set_period_ticks);
-+
-+int pwm_set_duty_ns(struct pwm_device *p, unsigned long duty_ns)
-+{
-+	struct pwm_config c = {
-+		.config_mask = BIT(PWM_CONFIG_DUTY_TICKS),
-+		.duty_ticks = pwm_ns_to_ticks(p, duty_ns),
-+	};
-+	spin_lock(&p->pwm_lock);
-+	p->duty_ns = duty_ns;
-+	spin_unlock(&p->pwm_lock);
-+	return pwm_config(p, &c);
-+}
-+EXPORT_SYMBOL(pwm_set_duty_ns);
-+
-+unsigned long pwm_get_duty_ns(struct pwm_device *p)
-+{
-+	return pwm_ticks_to_ns(p, p->duty_ticks);
-+}
-+EXPORT_SYMBOL(pwm_get_duty_ns);
-+
-+int pwm_set_duty_percent(struct pwm_device *p, int percent)
-+{
-+	struct pwm_config c = {
-+		.config_mask = BIT(PWM_CONFIG_DUTY_PERCENT),
-+		.duty_percent = percent,
-+	};
-+
-+	spin_lock(&p->pwm_lock);
-+	p->duty_ns = p->period_ns * percent;
-+	p->duty_ns /= 100;
-+	spin_unlock(&p->pwm_lock);
-+	return pwm_config(p, &c);
-+}
-+EXPORT_SYMBOL(pwm_set_duty_percent);
-+
-+unsigned long pwm_get_duty_percent(struct pwm_device *p)
-+{
-+	unsigned long long duty_percent;
-+
-+	if (!p->period_ns) {
-+		pr_debug("%s: frequency is zero\n", dev_name(p->dev));
-+		return 0;
-+	}
-+
-+	duty_percent = pwm_ticks_to_ns(p, p->duty_ticks);
-+	duty_percent *= 100;
-+	do_div(duty_percent, p->period_ns);
-+	return duty_percent;
-+}
-+EXPORT_SYMBOL(pwm_get_duty_percent);
-+
-+int pwm_set_duty_ticks(struct pwm_device *p,
-+					unsigned long ticks)
-+{
-+	struct pwm_config c = {
-+		.config_mask = BIT(PWM_CONFIG_DUTY_TICKS),
-+		.duty_ticks = ticks,
-+	};
-+
-+	spin_lock(&p->pwm_lock);
-+	p->duty_ns = pwm_ticks_to_ns(p, ticks);
-+	spin_unlock(&p->pwm_lock);
-+	return pwm_config(p, &c);
-+}
-+EXPORT_SYMBOL(pwm_set_duty_ticks);
-+
-+int pwm_set_polarity(struct pwm_device *p, int active_high)
-+{
-+	struct pwm_config c = {
-+		.config_mask = BIT(PWM_CONFIG_POLARITY),
-+		.polarity = active_high,
-+	};
-+	return pwm_config(p, &c);
-+}
-+EXPORT_SYMBOL(pwm_set_polarity);
-+
-+int pwm_start(struct pwm_device *p)
-+{
-+	struct pwm_config c = {
-+		.config_mask = BIT(PWM_CONFIG_START),
-+	};
-+	return pwm_config(p, &c);
-+}
-+EXPORT_SYMBOL(pwm_start);
-+
-+int pwm_stop(struct pwm_device *p)
-+{
-+	struct pwm_config c = {
-+		.config_mask = BIT(PWM_CONFIG_STOP),
-+	};
-+	return pwm_config(p, &c);
-+}
-+EXPORT_SYMBOL(pwm_stop);
-+
-+int pwm_synchronize(struct pwm_device *p, struct pwm_device *to_p)
-+{
-+	if (!p->ops->synchronize)
-+		return -EINVAL;
-+
-+	return p->ops->synchronize(p, to_p);
-+}
-+EXPORT_SYMBOL(pwm_synchronize);
-+
-+int pwm_unsynchronize(struct pwm_device *p, struct pwm_device *from_p)
-+{
-+	if (!p->ops->unsynchronize)
-+		return -EINVAL;
-+
-+	return p->ops->unsynchronize(p, from_p);
-+}
-+EXPORT_SYMBOL(pwm_unsynchronize);
-+
-+static void pwm_handler(struct work_struct *w)
-+{
-+	struct pwm_device *p = container_of(w, struct pwm_device,
-+					    handler_work);
-+	if (p->handler && p->handler(p, p->handler_data))
-+		pwm_stop(p);
-+}
-+
-+static void __pwm_callback(struct pwm_device *p)
-+{
-+	queue_work(pwm_handler_workqueue, &p->handler_work);
-+}
-+
-+int pwm_set_handler(struct pwm_device *p, pwm_handler_t handler, void *data)
-+{
-+	if (p->ops->set_callback) {
-+		p->handler_data = data;
-+		p->handler = handler;
-+		INIT_WORK(&p->handler_work, pwm_handler);
-+		return p->ops->set_callback(p, handler ? __pwm_callback : NULL);
-+	}
-+	return -EINVAL;
-+}
-+EXPORT_SYMBOL(pwm_set_handler);
-+
-+static ssize_t pwm_run_show(struct device *dev,
-+			    struct device_attribute *attr,
-+			    char *buf)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	return sprintf(buf, "%d\n", pwm_is_running(p));
-+}
-+
-+static ssize_t pwm_run_store(struct device *dev,
-+			     struct device_attribute *attr,
-+			     const char *buf, size_t len)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	int ret;
-+
-+	if (sysfs_streq(buf, "1"))
-+		ret = pwm_start(p);
-+	else if (sysfs_streq(buf, "0"))
-+		ret = pwm_stop(p);
-+	else
-+		ret = -EINVAL;
-+
-+	if (ret < 0)
-+		return ret;
-+	return len;
-+}
-+static DEVICE_ATTR(run, S_IRUGO | S_IWUSR, pwm_run_show, pwm_run_store);
-+
-+static ssize_t pwm_tick_hz_show(struct device *dev,
-+				struct device_attribute *attr,
-+				char *buf)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	return sprintf(buf, "%lu\n", p->tick_hz);
-+}
-+static DEVICE_ATTR(tick_hz, S_IRUGO, pwm_tick_hz_show, NULL);
-+
-+static ssize_t pwm_duty_ns_show(struct device *dev,
-+				struct device_attribute *attr,
-+				char *buf)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	return sprintf(buf, "%lu\n", pwm_get_duty_ns(p));
-+}
-+
-+static ssize_t pwm_duty_ns_store(struct device *dev,
-+				 struct device_attribute *attr,
-+				 const char *buf, size_t len)
-+{
-+	unsigned long duty_ns;
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	int ret;
-+
-+	if (!kstrtoul(buf, 10, &duty_ns)) {
-+		ret = pwm_set_duty_ns(p, duty_ns);
-+
-+		if (ret < 0)
-+			return ret;
-+	}
-+
-+	return len;
-+}
-+static DEVICE_ATTR(duty_ns, S_IRUGO | S_IWUSR, pwm_duty_ns_show,
-+	       pwm_duty_ns_store);
-+
-+static ssize_t pwm_duty_percent_show(struct device *dev,
-+				struct device_attribute *attr,
-+				char *buf)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	return sprintf(buf, "%lu\n", pwm_get_duty_percent(p));
-+}
-+
-+static ssize_t pwm_duty_percent_store(struct device *dev,
-+				 struct device_attribute *attr,
-+				 const char *buf,
-+				 size_t len)
-+{
-+	unsigned long duty_ns;
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	int ret;
-+
-+	if (!kstrtoul(buf, 10, &duty_ns)) {
-+		ret = pwm_set_duty_percent(p, duty_ns);
-+
-+		if (ret < 0)
-+			return ret;
-+	}
-+
-+	return len;
-+}
-+
-+static DEVICE_ATTR(duty_percent, S_IRUGO | S_IWUSR, pwm_duty_percent_show,
-+	       pwm_duty_percent_store);
-+
-+static ssize_t pwm_period_ns_show(struct device *dev,
-+				  struct device_attribute *attr,
-+				  char *buf)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	return sprintf(buf, "%lu\n", pwm_get_period_ns(p));
-+}
-+
-+static ssize_t pwm_period_ns_store(struct device *dev,
-+				   struct device_attribute *attr,
-+				   const char *buf, size_t len)
-+{
-+	unsigned long period_ns;
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	int ret;
-+
-+	if (!kstrtoul(buf, 10, &period_ns)) {
-+		ret = pwm_set_period_ns(p, period_ns);
-+
-+		if (ret < 0)
-+			return ret;
-+	}
-+
-+	return len;
-+}
-+static DEVICE_ATTR(period_ns, S_IRUGO | S_IWUSR, pwm_period_ns_show,
-+	       pwm_period_ns_store);
-+
-+static ssize_t pwm_period_freq_show(struct device *dev,
-+				  struct device_attribute *attr,
-+				  char *buf)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	return sprintf(buf, "%lu\n", pwm_get_frequency(p));
-+}
-+
-+static ssize_t pwm_period_freq_store(struct device *dev,
-+				   struct device_attribute *attr,
-+				   const char *buf,
-+				   size_t len)
-+{
-+	unsigned long freq_hz;
-+	int ret;
-+
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	if (!kstrtoul(buf, 10, &freq_hz)) {
-+		ret = pwm_set_frequency(p, freq_hz);
-+
-+		if (ret < 0)
-+			return ret;
-+	}
-+	return len;
-+}
-+
-+static DEVICE_ATTR(period_freq, S_IRUGO | S_IWUSR, pwm_period_freq_show,
-+	       pwm_period_freq_store);
-+
-+static ssize_t pwm_polarity_show(struct device *dev,
-+				 struct device_attribute *attr,
-+				 char *buf)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	return sprintf(buf, "%d\n", p->active_high ? 1 : 0);
-+}
-+
-+static ssize_t pwm_polarity_store(struct device *dev,
-+				  struct device_attribute *attr,
-+				  const char *buf, size_t len)
-+{
-+	unsigned long polarity;
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	int ret;
-+
-+	if (!kstrtoul(buf, 10, &polarity)) {
-+		ret = pwm_set_polarity(p, polarity);
-+
-+		if (ret < 0)
-+			return ret;
-+	}
-+
-+	return len;
-+}
-+static DEVICE_ATTR(polarity, S_IRUGO | S_IWUSR, pwm_polarity_show,
-+	       pwm_polarity_store);
-+
-+static ssize_t pwm_request_show(struct device *dev,
-+				struct device_attribute *attr,
-+				char *buf)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	int ret;
-+
-+	ret = test_bit(FLAG_REQUESTED, &p->flags);
-+
-+	if (ret)
-+		return sprintf(buf, "%s requested by %s\n",
-+				dev_name(p->dev), p->label);
-+	else
-+		return sprintf(buf, "%s is free\n",
-+				dev_name(p->dev));
-+}
-+
-+static ssize_t pwm_request_store(struct device *dev,
-+				 struct device_attribute *attr,
-+				 const char *buf, size_t len)
-+{
-+	struct pwm_device *p = dev_get_drvdata(dev);
-+	unsigned long request;
-+	struct pwm_device *ret;
-+
-+	if (!kstrtoul(buf, 10, &request)) {
-+		if (request) {
-+			mutex_lock(&device_list_mutex);
-+			ret = __pwm_request(p, REQUEST_SYSFS);
-+			mutex_unlock(&device_list_mutex);
-+
-+			if (IS_ERR(ret))
-+				return PTR_ERR(ret);
-+		} else
-+			pwm_release(p);
-+	}
-+
-+	return len;
-+}
-+static DEVICE_ATTR(request, S_IRUGO | S_IWUSR, pwm_request_show,
-+	       pwm_request_store);
-+
-+static const struct attribute *pwm_attrs[] = {
-+	&dev_attr_tick_hz.attr,
-+	&dev_attr_run.attr,
-+	&dev_attr_polarity.attr,
-+	&dev_attr_duty_ns.attr,
-+	&dev_attr_period_ns.attr,
-+	&dev_attr_request.attr,
-+	&dev_attr_duty_percent.attr,
-+	&dev_attr_period_freq.attr,
-+	NULL,
-+};
-+
-+static const struct attribute_group pwm_device_attr_group = {
-+	.attrs = (struct attribute **) pwm_attrs,
-+};
-+
-+static struct class_attribute pwm_class_attrs[] = {
-+	__ATTR_NULL,
-+};
-+
-+static struct class pwm_class = {
-+	.name = "pwm",
-+	.owner = THIS_MODULE,
-+
-+	.class_attrs = pwm_class_attrs,
-+};
-+
-+static int pwm_freq_transition_notifier_cb(struct notifier_block *nb,
-+		unsigned long val, void *data)
-+{
-+	struct pwm_device *p;
-+
-+	p = container_of(nb, struct pwm_device, freq_transition);
-+
-+	if (val == CPUFREQ_POSTCHANGE && pwm_is_requested(p))
-+		p->ops->freq_transition_notifier_cb(p);
-+
-+	return 0;
-+}
-+
-+static inline int pwm_cpufreq_notifier_register(struct pwm_device *p)
-+{
-+	p->freq_transition.notifier_call = pwm_freq_transition_notifier_cb;
-+
-+	return cpufreq_register_notifier(&p->freq_transition,
-+		       CPUFREQ_TRANSITION_NOTIFIER);
-+}
-+
-+int pwm_register_byname(struct pwm_device *p, struct device *parent,
-+			const char *name)
-+{
-+	struct device *d;
-+	int ret;
-+
-+	if (!p->ops || !p->ops->config)
-+		return -EINVAL;
-+
-+	mutex_lock(&device_list_mutex);
-+
-+	d = class_find_device(&pwm_class, NULL, (char *)name, pwm_match_name);
-+	if (d) {
-+		ret = -EEXIST;
-+		goto err_found_device;
-+	}
-+
-+	p->dev = device_create(&pwm_class, parent, MKDEV(0, 0), NULL, name);
-+	if (IS_ERR(p->dev)) {
-+		ret = PTR_ERR(p->dev);
-+		goto err_device_create;
-+	}
-+
-+	ret = sysfs_create_group(&p->dev->kobj, &pwm_device_attr_group);
-+	if (ret)
-+		goto err_create_group;
-+
-+	dev_set_drvdata(p->dev, p);
-+	p->flags = BIT(FLAG_REGISTERED);
-+
-+	ret = pwm_cpufreq_notifier_register(p);
-+
-+	if (ret < 0)
-+		printk(KERN_ERR "Failed to add cpufreq notifier\n");
-+
-+	spin_lock_init(&p->pwm_lock);
-+	goto done;
-+
-+err_create_group:
-+	device_unregister(p->dev);
-+	p->flags = 0;
-+
-+err_device_create:
-+err_found_device:
-+done:
-+	mutex_unlock(&device_list_mutex);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(pwm_register_byname);
-+
-+int pwm_register(struct pwm_device *p, struct device *parent, int id)
-+{
-+	int ret;
-+	char name[256];
-+
-+	if (IS_ERR_OR_NULL(parent))
-+		return -EINVAL;
-+
-+	if (id == -1)
-+		ret = scnprintf(name, sizeof name, "%s", dev_name(parent));
-+	else
-+		ret = scnprintf(name, sizeof name, "%s:%d",
-+			       dev_name(parent), id);
-+	if (ret <= 0 || ret >= sizeof name)
-+		return -EINVAL;
-+
-+	return pwm_register_byname(p, parent, name);
-+}
-+EXPORT_SYMBOL(pwm_register);
-+
-+int pwm_unregister(struct pwm_device *p)
-+{
-+	int ret = 0;
-+
-+	mutex_lock(&device_list_mutex);
-+
-+	if (pwm_is_running(p) || pwm_is_requested(p)) {
-+		ret = -EBUSY;
-+		goto done;
-+	}
-+
-+	sysfs_remove_group(&p->dev->kobj, &pwm_device_attr_group);
-+	device_unregister(p->dev);
-+	p->flags = 0;
-+
-+done:
-+	mutex_unlock(&device_list_mutex);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(pwm_unregister);
-+
-+static int __init pwm_init(void)
-+{
-+	return class_register(&pwm_class);
-+}
-+
-+static void __exit pwm_exit(void)
-+{
-+	class_unregister(&pwm_class);
-+}
-+
-+#ifdef MODULE
-+module_init(pwm_init);
-+module_exit(pwm_exit);
-+MODULE_LICENSE("GPL");
-+#else
-+postcore_initcall(pwm_init);
-+#endif
-diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
-index 9713b1b..529c591 100644
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -259,6 +259,15 @@ config REGULATOR_TPS6507X
- 	  three step-down converters and two general-purpose LDO voltage regulators.
- 	  It supports TI's software based Class-2 SmartReflex implementation.
- 
-+config REGULATOR_TPS65217
-+	tristate "TI TPS65217 Power regulators"
-+	depends on MFD_TPS65217
-+	help
-+	  This driver supports TPS65217 voltage regulator chips. TPS65217
-+	  provides three step-down converters and four general-purpose LDO
-+	  voltage regulators. It supports software based voltage control
-+	  for different voltage domains
-+
- config REGULATOR_TPS65912
- 	tristate "TI TPS65912 Power regulator"
- 	depends on (MFD_TPS65912_I2C || MFD_TPS65912_SPI)
-diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
-index 93a6318..aeae546 100644
---- a/drivers/regulator/Makefile
-+++ b/drivers/regulator/Makefile
-@@ -38,6 +38,7 @@ obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
- obj-$(CONFIG_REGULATOR_TPS6105X) += tps6105x-regulator.o
- obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
- obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
-+obj-$(CONFIG_REGULATOR_TPS65217) += tps65217-regulator.o
- obj-$(CONFIG_REGULATOR_TPS6524X) += tps6524x-regulator.o
- obj-$(CONFIG_REGULATOR_TPS65912) += tps65912-regulator.o
- obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
-diff --git a/drivers/regulator/tps65217-regulator.c b/drivers/regulator/tps65217-regulator.c
-new file mode 100644
-index 0000000..6665566
---- /dev/null
-+++ b/drivers/regulator/tps65217-regulator.c
-@@ -0,0 +1,493 @@
-+/*
-+ * tps65217-regulator.c
-+ *
-+ * Regulator driver for TPS65217 PMIC
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/err.h>
-+#include <linux/platform_device.h>
-+
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/mfd/tps65217.h>
-+
-+#define TPS65217_REGULATOR(_name, _id, _ops, _n)	\
-+	{						\
-+		.name		= _name,		\
-+		.id		= _id,			\
-+		.ops		= &_ops,		\
-+		.n_voltages	= _n,			\
-+		.type		= REGULATOR_VOLTAGE,	\
-+		.owner		= THIS_MODULE,		\
-+	}						\
-+
-+#define TPS65217_INFO(_nm, _min, _max, _f1, _f2, _t, _n, _em, _vr, _vm)	\
-+	{						\
-+		.name		= _nm,			\
-+		.min_uV		= _min,			\
-+		.max_uV		= _max,			\
-+		.vsel_to_uv	= _f1,			\
-+		.uv_to_vsel	= _f2,			\
-+		.table		= _t,			\
-+		.table_len	= _n,			\
-+		.enable_mask	= _em,			\
-+		.set_vout_reg	= _vr,			\
-+		.set_vout_mask	= _vm,			\
-+	}
-+
-+static const int LDO1_VSEL_table[] = {
-+	1000000, 1100000, 1200000, 1250000,
-+	1300000, 1350000, 1400000, 1500000,
-+	1600000, 1800000, 2500000, 2750000,
-+	2800000, 3000000, 3100000, 3300000,
-+};
-+
-+static int tps65217_vsel_to_uv1(unsigned int vsel)
-+{
-+	int uV = 0;
-+
-+	if (vsel > 63)
-+		return -EINVAL;
-+
-+	if (vsel <= 24)
-+		uV = vsel * 25000 + 900000;
-+	else if (vsel <= 52)
-+		uV = (vsel - 24) * 50000 + 1500000;
-+	else if (vsel < 56)
-+		uV = (vsel - 52) * 100000 + 2900000;
-+	else
-+		uV = 3300000;
-+
-+	return uV;
-+}
-+
-+static int tps65217_uv_to_vsel1(int uV, unsigned int *vsel)
-+{
-+	if ((uV < 0) && (uV > 3300000))
-+		return -EINVAL;
-+
-+	if (uV <= 1500000)
-+		*vsel = (uV - 875001) / 25000;
-+	else if (uV <= 2900000)
-+		*vsel = 24 + (uV - 1450001) / 50000;
-+	else if (uV < 3300000)
-+		*vsel = 52 + (uV - 2800001) / 100000;
-+	else
-+		*vsel = 56;
-+
-+	return 0;
-+}
-+
-+static int tps65217_vsel_to_uv2(unsigned int vsel)
-+{
-+	int uV = 0;
-+
-+	if (vsel > 31)
-+		return -EINVAL;
-+
-+	if (vsel <= 8)
-+		uV = vsel * 50000 + 1500000;
-+	else if (vsel <= 13)
-+		uV = (vsel - 8) * 100000 + 1900000;
-+	else
-+		uV = (vsel - 13) * 50000 + 2400000;
-+
-+	return uV;
-+}
-+
-+static int tps65217_uv_to_vsel2(int uV, unsigned int *vsel)
-+{
-+	if ((uV < 0) && (uV > 3300000))
-+		return -EINVAL;
-+
-+	if (uV <= 1900000)
-+		*vsel = (uV - 1450001) / 50000;
-+	else if (uV <= 2400000)
-+		*vsel = 8 + (uV - 1800001) / 100000;
-+	else
-+		*vsel = 13 + (uV - 2350001) / 50000;
-+
-+	return 0;
-+}
-+
-+static struct tps_info tps65217_pmic_regs[] = {
-+	TPS65217_INFO("DCDC1", 900000, 1800000, tps65217_vsel_to_uv1,
-+			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_DC1_EN,
-+			TPS65217_REG_DEFDCDC1, TPS65217_DEFDCDCX_DCDC_MASK),
-+	TPS65217_INFO("DCDC2", 900000, 3300000, tps65217_vsel_to_uv1,
-+			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_DC2_EN,
-+			TPS65217_REG_DEFDCDC2, TPS65217_DEFDCDCX_DCDC_MASK),
-+	TPS65217_INFO("DCDC3", 900000, 1500000, tps65217_vsel_to_uv1,
-+			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_DC3_EN,
-+			TPS65217_REG_DEFDCDC3, TPS65217_DEFDCDCX_DCDC_MASK),
-+	TPS65217_INFO("LDO1", 1000000, 3300000, NULL, NULL, LDO1_VSEL_table,
-+			16, TPS65217_ENABLE_LDO1_EN, TPS65217_REG_DEFLDO1,
-+			TPS65217_DEFLDO1_LDO1_MASK),
-+	TPS65217_INFO("LDO2", 900000, 3300000, tps65217_vsel_to_uv1,
-+			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_LDO2_EN,
-+			TPS65217_REG_DEFLDO2, TPS65217_DEFLDO2_LDO2_MASK),
-+	TPS65217_INFO("LDO3", 1800000, 3300000, tps65217_vsel_to_uv2,
-+			tps65217_uv_to_vsel2, NULL, 32,
-+			TPS65217_ENABLE_LS1_EN | TPS65217_DEFLDO3_LDO3_EN,
-+			TPS65217_REG_DEFLS1, TPS65217_DEFLDO3_LDO3_MASK),
-+	TPS65217_INFO("LDO4", 1800000, 3300000, tps65217_vsel_to_uv2,
-+			tps65217_uv_to_vsel2, NULL, 32,
-+			TPS65217_ENABLE_LS2_EN | TPS65217_DEFLDO4_LDO4_EN,
-+			TPS65217_REG_DEFLS2, TPS65217_DEFLDO4_LDO4_MASK),
-+};
-+
-+static int tps65217_pmic_dcdc_is_enabled(struct regulator_dev *dev)
-+{
-+	int ret;
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int data, dcdc = rdev_get_id(dev);
-+
-+	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
-+		return -EINVAL;
-+
-+	ret = tps65217_reg_read(tps, TPS65217_REG_ENABLE, &data);
-+	if (ret)
-+		return ret;
-+
-+	return (data & tps->info[dcdc]->enable_mask) ? 1 : 0;
-+}
-+
-+static int tps65217_pmic_ldo_is_enabled(struct regulator_dev *dev)
-+{
-+	int ret;
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int data, ldo = rdev_get_id(dev);
-+
-+	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
-+		return -EINVAL;
-+
-+	ret = tps65217_reg_read(tps, TPS65217_REG_ENABLE, &data);
-+	if (ret)
-+		return ret;
-+
-+	return (data & tps->info[ldo]->enable_mask) ? 1 : 0;
-+}
-+
-+static int tps65217_pmic_dcdc_enable(struct regulator_dev *dev)
-+{
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int dcdc = rdev_get_id(dev);
-+
-+	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
-+		return -EINVAL;
-+
-+	/* Enable the regulator and password protection is level 1 */
-+	return tps65217_set_bits(tps, TPS65217_REG_ENABLE,
-+				tps->info[dcdc]->enable_mask,
-+				tps->info[dcdc]->enable_mask,
-+				TPS65217_PROTECT_L1);
-+}
-+
-+static int tps65217_pmic_dcdc_disable(struct regulator_dev *dev)
-+{
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int dcdc = rdev_get_id(dev);
-+
-+	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
-+		return -EINVAL;
-+
-+	/* Disable the regulator and password protection is level 1 */
-+	return tps65217_clear_bits(tps, TPS65217_REG_ENABLE,
-+			tps->info[dcdc]->enable_mask, TPS65217_PROTECT_L1);
-+}
-+
-+static int tps65217_pmic_ldo_enable(struct regulator_dev *dev)
-+{
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int ldo = rdev_get_id(dev);
-+
-+	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
-+		return -EINVAL;
-+
-+	/* Enable the regulator and password protection is level 1 */
-+	return tps65217_set_bits(tps, TPS65217_REG_ENABLE,
-+				tps->info[ldo]->enable_mask,
-+				tps->info[ldo]->enable_mask,
-+				TPS65217_PROTECT_L1);
-+}
-+
-+static int tps65217_pmic_ldo_disable(struct regulator_dev *dev)
-+{
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int ldo = rdev_get_id(dev);
-+
-+	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
-+		return -EINVAL;
-+
-+	/* Disable the regulator and password protection is level 1 */
-+	return tps65217_clear_bits(tps, TPS65217_REG_ENABLE,
-+			tps->info[ldo]->enable_mask, TPS65217_PROTECT_L1);
-+}
-+
-+static int tps65217_pmic_dcdc_get_voltage_sel(struct regulator_dev *dev)
-+{
-+	int ret;
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int selector, dcdc = rdev_get_id(dev);
-+
-+	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
-+		return -EINVAL;
-+
-+	ret = tps65217_reg_read(tps, tps->info[dcdc]->set_vout_reg, &selector);
-+	if (ret)
-+		return ret;
-+
-+	selector &= tps->info[dcdc]->set_vout_mask;
-+
-+	return selector;
-+}
-+
-+static int tps65217_pmic_dcdc_set_voltage(struct regulator_dev *dev,
-+				  int min_uV, int max_uV, unsigned *selector)
-+{
-+	int ret;
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int dcdc = rdev_get_id(dev);
-+
-+	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
-+		return -EINVAL;
-+
-+	if (min_uV < tps->info[dcdc]->min_uV
-+		|| min_uV > tps->info[dcdc]->max_uV)
-+		return -EINVAL;
-+
-+	if (max_uV < tps->info[dcdc]->min_uV
-+		|| max_uV > tps->info[dcdc]->max_uV)
-+		return -EINVAL;
-+
-+	ret = tps->info[dcdc]->uv_to_vsel(min_uV, selector);
-+	if (ret)
-+		return ret;
-+
-+	/* Set the voltage based on vsel value and write protect level is 2 */
-+	ret = tps65217_set_bits(tps, tps->info[dcdc]->set_vout_reg,
-+					tps->info[dcdc]->set_vout_mask,
-+					*selector, TPS65217_PROTECT_L2);
-+	if (ret)
-+		return ret;
-+
-+	/* Set GO bit to initiate voltage transistion */
-+	return tps65217_set_bits(tps, TPS65217_REG_DEFSLEW,
-+				TPS65217_DEFSLEW_GO, TPS65217_DEFSLEW_GO,
-+				TPS65217_PROTECT_L2);
-+}
-+
-+static int tps65217_pmic_ldo_get_voltage_sel(struct regulator_dev *dev)
-+{
-+	int ret;
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int selector, ldo = rdev_get_id(dev);
-+
-+	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
-+		return -EINVAL;
-+
-+	ret = tps65217_reg_read(tps, tps->info[ldo]->set_vout_reg, &selector);
-+	if (ret)
-+		return ret;
-+
-+	selector &= tps->info[ldo]->set_vout_mask;
-+
-+	return selector;
-+}
-+
-+static int tps65217_pmic_ldo_set_voltage_sel(struct regulator_dev *dev,
-+						unsigned selector)
-+{
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	int ldo = rdev_get_id(dev);
-+
-+	if (ldo != TPS65217_LDO_1)
-+		return -EINVAL;
-+
-+	if (selector >= tps->info[ldo]->table_len)
-+		return -EINVAL;
-+
-+	/* Set the voltage based on vsel value and write protect level is 2 */
-+	return tps65217_set_bits(tps, tps->info[ldo]->set_vout_reg,
-+					tps->info[ldo]->set_vout_mask,
-+					selector, TPS65217_PROTECT_L2);
-+}
-+
-+static int tps65217_pmic_ldo_set_voltage(struct regulator_dev *dev,
-+				  int min_uV, int max_uV, unsigned *selector)
-+{
-+	int ret;
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int ldo = rdev_get_id(dev);
-+
-+	if (ldo < TPS65217_LDO_2 || ldo > TPS65217_LDO_4)
-+		return -EINVAL;
-+
-+	if (min_uV < tps->info[ldo]->min_uV
-+		|| min_uV > tps->info[ldo]->max_uV)
-+		return -EINVAL;
-+
-+	if (max_uV < tps->info[ldo]->min_uV
-+		|| max_uV > tps->info[ldo]->max_uV)
-+		return -EINVAL;
-+
-+	ret = tps->info[ldo]->uv_to_vsel(min_uV, selector);
-+	if (ret)
-+		return ret;
-+
-+	/* Set the voltage based on vsel value and write protect level is 2 */
-+	return tps65217_set_bits(tps, tps->info[ldo]->set_vout_reg,
-+					tps->info[ldo]->set_vout_mask,
-+					*selector, TPS65217_PROTECT_L2);
-+}
-+
-+static int tps65217_pmic_dcdc_list_voltage(struct regulator_dev *dev,
-+					unsigned selector)
-+{
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int dcdc = rdev_get_id(dev);
-+
-+	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
-+		return -EINVAL;
-+
-+	if (selector >= tps->info[dcdc]->table_len)
-+		return -EINVAL;
-+
-+	return tps->info[dcdc]->vsel_to_uv(selector);
-+}
-+
-+static int tps65217_pmic_ldo_list_voltage(struct regulator_dev *dev,
-+					unsigned selector)
-+{
-+	struct tps65217 *tps = rdev_get_drvdata(dev);
-+	unsigned int ldo = rdev_get_id(dev);
-+
-+	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
-+		return -EINVAL;
-+
-+	if (selector >= tps->info[ldo]->table_len)
-+		return -EINVAL;
-+
-+	if (tps->info[ldo]->table)
-+		return tps->info[ldo]->table[selector];
-+
-+	return tps->info[ldo]->vsel_to_uv(selector);
-+}
-+
-+/* Operations permitted on DCDCx */
-+static struct regulator_ops tps65217_pmic_dcdc_ops = {
-+	.is_enabled		= tps65217_pmic_dcdc_is_enabled,
-+	.enable			= tps65217_pmic_dcdc_enable,
-+	.disable		= tps65217_pmic_dcdc_disable,
-+	.get_voltage_sel	= tps65217_pmic_dcdc_get_voltage_sel,
-+	.set_voltage		= tps65217_pmic_dcdc_set_voltage,
-+	.list_voltage		= tps65217_pmic_dcdc_list_voltage,
-+};
-+
-+/* Operations permitted on LDO1 */
-+static struct regulator_ops tps65217_pmic_ldo1_ops = {
-+	.is_enabled		= tps65217_pmic_ldo_is_enabled,
-+	.enable			= tps65217_pmic_ldo_enable,
-+	.disable		= tps65217_pmic_ldo_disable,
-+	.get_voltage_sel	= tps65217_pmic_ldo_get_voltage_sel,
-+	.set_voltage_sel	= tps65217_pmic_ldo_set_voltage_sel,
-+	.list_voltage		= tps65217_pmic_ldo_list_voltage,
-+};
-+
-+/* Operations permitted on LDO2, LDO3 and LDO4 */
-+static struct regulator_ops tps65217_pmic_ldo234_ops = {
-+	.is_enabled		= tps65217_pmic_ldo_is_enabled,
-+	.enable			= tps65217_pmic_ldo_enable,
-+	.disable		= tps65217_pmic_ldo_disable,
-+	.get_voltage_sel	= tps65217_pmic_ldo_get_voltage_sel,
-+	.set_voltage		= tps65217_pmic_ldo_set_voltage,
-+	.list_voltage		= tps65217_pmic_ldo_list_voltage,
-+};
-+
-+static struct regulator_desc regulators[] = {
-+	TPS65217_REGULATOR("DCDC1", TPS65217_DCDC_1,
-+				tps65217_pmic_dcdc_ops, 64),
-+	TPS65217_REGULATOR("DCDC2",TPS65217_DCDC_2,
-+				tps65217_pmic_dcdc_ops, 64),
-+	TPS65217_REGULATOR("DCDC3", TPS65217_DCDC_3,
-+				tps65217_pmic_dcdc_ops, 64),
-+	TPS65217_REGULATOR("LDO1", TPS65217_LDO_1,
-+				tps65217_pmic_ldo1_ops, 16),
-+	TPS65217_REGULATOR("LDO2", TPS65217_LDO_2,
-+				tps65217_pmic_ldo234_ops, 64),
-+	TPS65217_REGULATOR("LDO3", TPS65217_LDO_3,
-+				tps65217_pmic_ldo234_ops, 32),
-+	TPS65217_REGULATOR("LDO4", TPS65217_LDO_4,
-+				tps65217_pmic_ldo234_ops, 32),
-+};
-+
-+static int __devinit tps65217_regulator_probe(struct platform_device *pdev)
-+{
-+	struct regulator_dev *rdev;
-+	struct tps65217 *tps;
-+	struct tps_info *info = &tps65217_pmic_regs[pdev->id];
-+
-+	/* Already set by core driver */
-+	tps = dev_to_tps65217(pdev->dev.parent);
-+	tps->info[pdev->id] = info;
-+
-+	rdev = regulator_register(&regulators[pdev->id], &pdev->dev,
-+				  pdev->dev.platform_data, tps);
-+	if (IS_ERR(rdev))
-+		return PTR_ERR(rdev);
-+
-+	platform_set_drvdata(pdev, rdev);
-+
-+	return 0;
-+}
-+
-+static int __devexit tps65217_regulator_remove(struct platform_device *pdev)
-+{
-+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
-+
-+	platform_set_drvdata(pdev, NULL);
-+	regulator_unregister(rdev);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver tps65217_regulator_driver = {
-+	.driver = {
-+		.name = "tps65217-pmic",
-+	},
-+	.probe = tps65217_regulator_probe,
-+	.remove = __devexit_p(tps65217_regulator_remove),
-+};
-+
-+static int __init tps65217_regulator_init(void)
-+{
-+	return platform_driver_register(&tps65217_regulator_driver);
-+}
-+subsys_initcall(tps65217_regulator_init);
-+
-+static void __exit tps65217_regulator_exit(void)
-+{
-+	platform_driver_unregister(&tps65217_regulator_driver);
-+}
-+module_exit(tps65217_regulator_exit);
-+
-+
-+MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
-+MODULE_DESCRIPTION("TPS65217 voltage regulator driver");
-+MODULE_ALIAS("platform:tps65217-pmic");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/regulator/tps65910-regulator.c b/drivers/regulator/tps65910-regulator.c
-index b552aae..fc42a34 100644
---- a/drivers/regulator/tps65910-regulator.c
-+++ b/drivers/regulator/tps65910-regulator.c
-@@ -25,30 +25,6 @@
- #include <linux/gpio.h>
- #include <linux/mfd/tps65910.h>
- 
--#define TPS65910_REG_VRTC		0
--#define TPS65910_REG_VIO		1
--#define TPS65910_REG_VDD1		2
--#define TPS65910_REG_VDD2		3
--#define TPS65910_REG_VDD3		4
--#define TPS65910_REG_VDIG1		5
--#define TPS65910_REG_VDIG2		6
--#define TPS65910_REG_VPLL		7
--#define TPS65910_REG_VDAC		8
--#define TPS65910_REG_VAUX1		9
--#define TPS65910_REG_VAUX2		10
--#define TPS65910_REG_VAUX33		11
--#define TPS65910_REG_VMMC		12
--
--#define TPS65911_REG_VDDCTRL		4
--#define TPS65911_REG_LDO1		5
--#define TPS65911_REG_LDO2		6
--#define TPS65911_REG_LDO3		7
--#define TPS65911_REG_LDO4		8
--#define TPS65911_REG_LDO5		9
--#define TPS65911_REG_LDO6		10
--#define TPS65911_REG_LDO7		11
--#define TPS65911_REG_LDO8		12
--
- #define TPS65910_SUPPLY_STATE_ENABLED	0x1
- 
- /* supported VIO voltages in milivolts */
-@@ -508,9 +484,15 @@ static int tps65910_get_voltage_dcdc(struct regulator_dev *dev)
- 	switch (id) {
- 	case TPS65910_REG_VDD1:
- 		opvsel = tps65910_reg_read(pmic, TPS65910_VDD1_OP);
-+		if (opvsel < 0)
-+			return opvsel;
- 		mult = tps65910_reg_read(pmic, TPS65910_VDD1);
-+		if (mult < 0)
-+			return mult;
- 		mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
- 		srvsel = tps65910_reg_read(pmic, TPS65910_VDD1_SR);
-+		if (srvsel < 0)
-+			return srvsel;
- 		sr = opvsel & VDD1_OP_CMD_MASK;
- 		opvsel &= VDD1_OP_SEL_MASK;
- 		srvsel &= VDD1_SR_SEL_MASK;
-@@ -661,6 +643,7 @@ static int tps65910_set_voltage_dcdc(struct regulator_dev *dev,
- 	struct tps65910_reg *pmic = rdev_get_drvdata(dev);
- 	int id = rdev_get_id(dev), vsel;
- 	int dcdc_mult = 0;
-+	int ret = 0;
- 
- 	switch (id) {
- 	case TPS65910_REG_VDD1:
-@@ -669,10 +652,11 @@ static int tps65910_set_voltage_dcdc(struct regulator_dev *dev,
- 			dcdc_mult--;
- 		vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
- 
--		tps65910_modify_bits(pmic, TPS65910_VDD1,
-+		ret = tps65910_modify_bits(pmic, TPS65910_VDD1,
- 				(dcdc_mult << VDD1_VGAIN_SEL_SHIFT),
- 						VDD1_VGAIN_SEL_MASK);
--		tps65910_reg_write(pmic, TPS65910_VDD1_OP, vsel);
-+		if (!ret)
-+			ret = tps65910_reg_write(pmic, TPS65910_VDD1_OP, vsel);
- 		break;
- 	case TPS65910_REG_VDD2:
- 		dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
-@@ -690,7 +674,7 @@ static int tps65910_set_voltage_dcdc(struct regulator_dev *dev,
- 		tps65910_reg_write(pmic, TPS65911_VDDCTRL_OP, vsel);
- 	}
- 
--	return 0;
-+	return ret;
- }
- 
- static int tps65910_set_voltage(struct regulator_dev *dev, unsigned selector)
-@@ -885,8 +869,6 @@ static __devinit int tps65910_probe(struct platform_device *pdev)
- 	if (!pmic_plat_data)
- 		return -EINVAL;
- 
--	reg_data = pmic_plat_data->tps65910_pmic_init_data;
--
- 	pmic = kzalloc(sizeof(*pmic), GFP_KERNEL);
- 	if (!pmic)
- 		return -ENOMEM;
-@@ -937,7 +919,16 @@ static __devinit int tps65910_probe(struct platform_device *pdev)
- 		goto err_free_info;
- 	}
- 
--	for (i = 0; i < pmic->num_regulators; i++, info++, reg_data++) {
-+	for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS;
-+			i++, info++) {
-+
-+		reg_data = pmic_plat_data->tps65910_pmic_init_data[i];
-+
-+		/* Regulator API handles empty constraints but not NULL
-+		 * constraints */
-+		if (!reg_data)
-+			continue;
-+
- 		/* Register the regulators */
- 		pmic->info[i] = info;
- 
-diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
-index 53eb4e5..34a7129 100644
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -733,7 +733,7 @@ config RTC_DRV_DAVINCI
- 
- config RTC_DRV_OMAP
- 	tristate "TI OMAP1"
--	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
-+	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX || SOC_OMAPAM33XX
- 	help
- 	  Say "yes" here to support the real time clock on TI OMAP1 and
- 	  DA8xx/OMAP-L13x chips.  This driver can also be built as a
-diff --git a/drivers/scsi/gdth.h b/drivers/scsi/gdth.h
-index d969855..d3e4d7c 100644
---- a/drivers/scsi/gdth.h
-+++ b/drivers/scsi/gdth.h
-@@ -359,7 +359,7 @@ typedef struct {
-     u32     cmd_buff_addr2;     /* physical address of cmd buffer 1 */   
-     u32     cmd_buff_u_addr2;   /* reserved for 64 bit addressing */
-     u32     cmd_buff_indx2;     /* cmd buf addr1 unique identifier */
--    u32     cmd_buff_size;      /* size of each cmd bufer in bytes */
-+    u32     cmd_buff_size;      /* size of each cmd buffer in bytes */
-     u32     reserved1;
-     u32     reserved2;
- } __attribute__((packed)) gdth_perf_modes;
-diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
-index 322be7a..460b9b4 100644
---- a/drivers/spi/spi-omap2-mcspi.c
-+++ b/drivers/spi/spi-omap2-mcspi.c
-@@ -40,6 +40,7 @@
- #include <plat/dma.h>
- #include <plat/clock.h>
- #include <plat/mcspi.h>
-+#include <mach/edma.h>
- 
- #define OMAP2_MCSPI_MAX_FREQ		48000000
- 
-@@ -101,6 +102,7 @@ struct omap2_mcspi_dma {
- 
- 	struct completion dma_tx_completion;
- 	struct completion dma_rx_completion;
-+	int dummy_param_slot;
- };
- 
- /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
-@@ -108,7 +110,6 @@ struct omap2_mcspi_dma {
-  */
- #define DMA_MIN_BYTES			160
- 
--
- struct omap2_mcspi {
- 	struct work_struct	work;
- 	/* lock protects queue and registers */
-@@ -303,6 +304,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
- 	u8			* rx;
- 	const u8		* tx;
- 	void __iomem		*chstat_reg;
-+	struct edmacc_param	param;
- 
- 	mcspi = spi_master_get_devdata(spi->master);
- 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
-@@ -332,37 +334,57 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
- 	}
- 
- 	if (tx != NULL) {
--		omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
--				data_type, element_count, 1,
--				OMAP_DMA_SYNC_ELEMENT,
--				mcspi_dma->dma_tx_sync_dev, 0);
--
--		omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
--				OMAP_DMA_AMODE_CONSTANT,
--				tx_reg, 0, 0);
--
--		omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
--				OMAP_DMA_AMODE_POST_INC,
--				xfer->tx_dma, 0, 0);
-+		int a_cnt, b_cnt, c_cnt, b_cntrld;
-+
-+		a_cnt    = 1;
-+		b_cnt    = 1;
-+		c_cnt    = (element_count / a_cnt) / 256;
-+		b_cntrld = SZ_64K - 1;
-+
-+		param.opt          = TCINTEN |
-+			EDMA_TCC(mcspi_dma->dma_tx_channel) | SYNCDIM ;
-+		param.src          = xfer->tx_dma;
-+		param.a_b_cnt      = a_cnt | b_cnt << 16;
-+		param.dst          = tx_reg;
-+		param.src_dst_bidx = a_cnt;
-+		param.link_bcntrld = b_cntrld << 16;
-+		param.src_dst_cidx = b_cnt;
-+		param.ccnt         = element_count;
-+		edma_write_slot(mcspi_dma->dma_tx_channel, &param);
-+		edma_link(mcspi_dma->dma_tx_channel,
-+				mcspi_dma->dummy_param_slot);
- 	}
- 
- 	if (rx != NULL) {
-+		int a_cnt, b_cnt, c_cnt, b_cntrld;
-+
-+		a_cnt    = 1;
-+		c_cnt    = (element_count / a_cnt) / (SZ_64K - 1);
-+		b_cnt    = element_count - c_cnt * (SZ_64K - 1);
-+		b_cntrld = SZ_64K - 1;
-+
-+		if (b_cnt)
-+			c_cnt++;
-+		else
-+			b_cnt = SZ_64K - 1;
-+
- 		elements = element_count - 1;
- 		if (l & OMAP2_MCSPI_CHCONF_TURBO)
- 			elements--;
- 
--		omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
--				data_type, elements, 1,
--				OMAP_DMA_SYNC_ELEMENT,
--				mcspi_dma->dma_rx_sync_dev, 1);
-+		param.opt          = TCINTEN |
-+			EDMA_TCC(mcspi_dma->dma_rx_channel);
-+		param.src          = rx_reg;
-+		param.a_b_cnt      = a_cnt | b_cnt << 16;
-+		param.dst          = xfer->rx_dma;
-+		param.src_dst_bidx = a_cnt << 16;
-+		param.link_bcntrld = b_cntrld << 16;
-+		param.src_dst_cidx = 1 << 16;
-+		param.ccnt         = c_cnt;
-+		edma_write_slot(mcspi_dma->dma_rx_channel, &param);
-+		edma_link(mcspi_dma->dma_rx_channel,
-+				mcspi_dma->dummy_param_slot);
- 
--		omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
--				OMAP_DMA_AMODE_CONSTANT,
--				rx_reg, 0, 0);
--
--		omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
--				OMAP_DMA_AMODE_POST_INC,
--				xfer->rx_dma, 0, 0);
- 	}
- 
- 	if (tx != NULL) {
-@@ -419,23 +441,6 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
- 			}
- 		}
- 
--		if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
--				& OMAP2_MCSPI_CHSTAT_RXS)) {
--			u32 w;
--
--			w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
--			if (word_len <= 8)
--				((u8 *)xfer->rx_buf)[elements] = w;
--			else if (word_len <= 16)
--				((u16 *)xfer->rx_buf)[elements] = w;
--			else /* word_len <= 32 */
--				((u32 *)xfer->rx_buf)[elements] = w;
--		} else {
--			dev_err(&spi->dev, "DMA RX last word empty");
--			count -= (word_len <= 8)  ? 1 :
--				 (word_len <= 16) ? 2 :
--			       /* word_len <= 32 */ 4;
--		}
- 		omap2_mcspi_set_enable(spi, 1);
- 	}
- 	return count;
-@@ -718,13 +723,13 @@ static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
- 	struct omap2_mcspi	*mcspi;
- 	struct omap2_mcspi_dma	*mcspi_dma;
- 
-+	/* We must disable the DMA RX request */
-+	omap2_mcspi_set_dma_req(spi, 1, 0);
- 	mcspi = spi_master_get_devdata(spi->master);
- 	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
- 
- 	complete(&mcspi_dma->dma_rx_completion);
- 
--	/* We must disable the DMA RX request */
--	omap2_mcspi_set_dma_req(spi, 1, 0);
- }
- 
- static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
-@@ -733,13 +738,13 @@ static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
- 	struct omap2_mcspi	*mcspi;
- 	struct omap2_mcspi_dma	*mcspi_dma;
- 
-+	/* We must disable the DMA TX request */
-+	omap2_mcspi_set_dma_req(spi, 0, 0);
- 	mcspi = spi_master_get_devdata(spi->master);
- 	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
- 
- 	complete(&mcspi_dma->dma_tx_completion);
- 
--	/* We must disable the DMA TX request */
--	omap2_mcspi_set_dma_req(spi, 0, 0);
- }
- 
- static int omap2_mcspi_request_dma(struct spi_device *spi)
-@@ -747,6 +752,7 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
- 	struct spi_master	*master = spi->master;
- 	struct omap2_mcspi	*mcspi;
- 	struct omap2_mcspi_dma	*mcspi_dma;
-+	int			ret = 0;
- 
- 	mcspi = spi_master_get_devdata(master);
- 	mcspi_dma = mcspi->dma_channels + spi->chip_select;
-@@ -766,6 +772,18 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
- 		dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
- 		return -EAGAIN;
- 	}
-+	ret = edma_alloc_slot(EDMA_CTLR(mcspi_dma->dma_tx_channel),
-+			EDMA_SLOT_ANY);
-+
-+	if (ret < 0) {
-+		pr_err("Unable to request SPI TX DMA param slot\n");
-+		ret = -EAGAIN;
-+		return ret;
-+	}
-+
-+	mcspi_dma->dummy_param_slot = ret;
-+	edma_link(mcspi_dma->dummy_param_slot,
-+			mcspi_dma->dummy_param_slot);
- 
- 	init_completion(&mcspi_dma->dma_rx_completion);
- 	init_completion(&mcspi_dma->dma_tx_completion);
-@@ -1114,7 +1132,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
- 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	if (r == NULL) {
- 		status = -ENODEV;
--		goto err1;
-+		goto free_master;
- 	}
- 
- 	r->start += pdata->regs_offset;
-@@ -1123,14 +1141,14 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
- 	if (!request_mem_region(r->start, resource_size(r),
- 				dev_name(&pdev->dev))) {
- 		status = -EBUSY;
--		goto err1;
-+		goto free_master;
- 	}
- 
- 	mcspi->base = ioremap(r->start, resource_size(r));
- 	if (!mcspi->base) {
- 		dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
- 		status = -ENOMEM;
--		goto err2;
-+		goto release_region;
- 	}
- 
- 	mcspi->dev = &pdev->dev;
-@@ -1145,7 +1163,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
- 			GFP_KERNEL);
- 
- 	if (mcspi->dma_channels == NULL)
--		goto err2;
-+		goto unmap_io;
- 
- 	for (i = 0; i < master->num_chipselect; i++) {
- 		char dma_ch_name[14];
-@@ -1175,25 +1193,34 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
- 		mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
- 	}
- 
-+	if (status < 0)
-+		goto dma_chnl_free;
-+
- 	pm_runtime_enable(&pdev->dev);
- 
- 	if (status || omap2_mcspi_master_setup(mcspi) < 0)
--		goto err3;
-+		goto diable_pm;
- 
- 	status = spi_register_master(master);
- 	if (status < 0)
--		goto err4;
-+		goto err_spi_register;
- 
- 	return status;
- 
--err4:
-+err_spi_register:
- 	spi_master_put(master);
--err3:
-+diable_pm:
-+	pm_runtime_put_sync(&pdev->dev);
-+	pm_runtime_disable(&pdev->dev);
-+dma_chnl_free:
- 	kfree(mcspi->dma_channels);
--err2:
--	release_mem_region(r->start, resource_size(r));
-+unmap_io:
- 	iounmap(mcspi->base);
--err1:
-+release_region:
-+	release_mem_region(r->start, resource_size(r));
-+free_master:
-+	kfree(master);
-+	platform_set_drvdata(pdev, NULL);
- 	return status;
- }
- 
-@@ -1210,13 +1237,16 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
- 	dma_channels = mcspi->dma_channels;
- 
- 	omap2_mcspi_disable_clocks(mcspi);
-+	pm_runtime_disable(&pdev->dev);
-+	kfree(dma_channels);
-+	base = mcspi->base;
-+	iounmap(base);
-+
- 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	release_mem_region(r->start, resource_size(r));
- 
--	base = mcspi->base;
- 	spi_unregister_master(master);
--	iounmap(base);
--	kfree(dma_channels);
-+	platform_set_drvdata(pdev, NULL);
- 
- 	return 0;
- }
-diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
-index 5e713d3..ca24ab3 100644
---- a/drivers/tty/serial/omap-serial.c
-+++ b/drivers/tty/serial/omap-serial.c
-@@ -37,17 +37,24 @@
- #include <linux/clk.h>
- #include <linux/serial_core.h>
- #include <linux/irq.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/of.h>
- 
- #include <plat/dma.h>
- #include <plat/dmtimer.h>
- #include <plat/omap-serial.h>
- 
-+#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
-+
- static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
- 
- /* Forward declaration of functions */
- static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
--static void serial_omap_rx_timeout(unsigned long uart_no);
-+static void serial_omap_rxdma_poll(unsigned long uart_no);
- static int serial_omap_start_rxdma(struct uart_omap_port *up);
-+static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
-+
-+static struct workqueue_struct *serial_omap_uart_wq;
- 
- static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
- {
-@@ -102,6 +109,8 @@ static void serial_omap_stop_rxdma(struct uart_omap_port *up)
- 		omap_free_dma(up->uart_dma.rx_dma_channel);
- 		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
- 		up->uart_dma.rx_dma_used = false;
-+		pm_runtime_mark_last_busy(&up->pdev->dev);
-+		pm_runtime_put_autosuspend(&up->pdev->dev);
- 	}
- }
- 
-@@ -109,9 +118,12 @@ static void serial_omap_enable_ms(struct uart_port *port)
- {
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
- 
--	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id);
-+	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
-+
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	up->ier |= UART_IER_MSI;
- 	serial_out(up, UART_IER, up->ier);
-+	pm_runtime_put(&up->pdev->dev);
- }
- 
- static void serial_omap_stop_tx(struct uart_port *port)
-@@ -129,30 +141,40 @@ static void serial_omap_stop_tx(struct uart_port *port)
- 		omap_stop_dma(up->uart_dma.tx_dma_channel);
- 		omap_free_dma(up->uart_dma.tx_dma_channel);
- 		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-+		pm_runtime_mark_last_busy(&up->pdev->dev);
-+		pm_runtime_put_autosuspend(&up->pdev->dev);
- 	}
- 
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	if (up->ier & UART_IER_THRI) {
- 		up->ier &= ~UART_IER_THRI;
- 		serial_out(up, UART_IER, up->ier);
- 	}
-+
-+	pm_runtime_mark_last_busy(&up->pdev->dev);
-+	pm_runtime_put_autosuspend(&up->pdev->dev);
- }
- 
- static void serial_omap_stop_rx(struct uart_port *port)
- {
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
- 
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	if (up->use_dma)
- 		serial_omap_stop_rxdma(up);
- 	up->ier &= ~UART_IER_RLSI;
- 	up->port.read_status_mask &= ~UART_LSR_DR;
- 	serial_out(up, UART_IER, up->ier);
-+	pm_runtime_mark_last_busy(&up->pdev->dev);
-+	pm_runtime_put_autosuspend(&up->pdev->dev);
- }
- 
--static inline void receive_chars(struct uart_omap_port *up, int *status)
-+static inline void receive_chars(struct uart_omap_port *up,
-+		unsigned int *status)
- {
- 	struct tty_struct *tty = up->port.state->port.tty;
--	unsigned int flag;
--	unsigned char ch, lsr = *status;
-+	unsigned int flag, lsr = *status;
-+	unsigned char ch = 0;
- 	int max_count = 256;
- 
- 	do {
-@@ -262,7 +284,10 @@ static void serial_omap_start_tx(struct uart_port *port)
- 	int ret = 0;
- 
- 	if (!up->use_dma) {
-+		pm_runtime_get_sync(&up->pdev->dev);
- 		serial_omap_enable_ier_thri(up);
-+		pm_runtime_mark_last_busy(&up->pdev->dev);
-+		pm_runtime_put_autosuspend(&up->pdev->dev);
- 		return;
- 	}
- 
-@@ -272,6 +297,7 @@ static void serial_omap_start_tx(struct uart_port *port)
- 	xmit = &up->port.state->xmit;
- 
- 	if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
-+		pm_runtime_get_sync(&up->pdev->dev);
- 		ret = omap_request_dma(up->uart_dma.uart_dma_tx,
- 				"UART Tx DMA",
- 				(void *)uart_tx_dma_callback, up,
-@@ -354,9 +380,13 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
- 	unsigned int iir, lsr;
- 	unsigned long flags;
- 
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	iir = serial_in(up, UART_IIR);
--	if (iir & UART_IIR_NO_INT)
-+	if (iir & UART_IIR_NO_INT) {
-+		pm_runtime_mark_last_busy(&up->pdev->dev);
-+		pm_runtime_put_autosuspend(&up->pdev->dev);
- 		return IRQ_NONE;
-+	}
- 
- 	spin_lock_irqsave(&up->port.lock, flags);
- 	lsr = serial_in(up, UART_LSR);
-@@ -378,6 +408,9 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
- 		transmit_chars(up);
- 
- 	spin_unlock_irqrestore(&up->port.lock, flags);
-+	pm_runtime_mark_last_busy(&up->pdev->dev);
-+	pm_runtime_put_autosuspend(&up->pdev->dev);
-+
- 	up->port_activity = jiffies;
- 	return IRQ_HANDLED;
- }
-@@ -388,11 +421,12 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
- 	unsigned long flags = 0;
- 	unsigned int ret = 0;
- 
--	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id);
-+	pm_runtime_get_sync(&up->pdev->dev);
-+	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
- 	spin_lock_irqsave(&up->port.lock, flags);
- 	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
- 	spin_unlock_irqrestore(&up->port.lock, flags);
--
-+	pm_runtime_put(&up->pdev->dev);
- 	return ret;
- }
- 
-@@ -402,8 +436,11 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
- 	unsigned char status;
- 	unsigned int ret = 0;
- 
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	status = check_modem_status(up);
--	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id);
-+	pm_runtime_put(&up->pdev->dev);
-+
-+	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
- 
- 	if (status & UART_MSR_DCD)
- 		ret |= TIOCM_CAR;
-@@ -421,7 +458,7 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
- 	unsigned char mcr = 0;
- 
--	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id);
-+	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
- 	if (mctrl & TIOCM_RTS)
- 		mcr |= UART_MCR_RTS;
- 	if (mctrl & TIOCM_DTR)
-@@ -433,8 +470,11 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
- 	if (mctrl & TIOCM_LOOP)
- 		mcr |= UART_MCR_LOOP;
- 
--	mcr |= up->mcr;
--	serial_out(up, UART_MCR, mcr);
-+	pm_runtime_get_sync(&up->pdev->dev);
-+	up->mcr = serial_in(up, UART_MCR);
-+	up->mcr |= mcr;
-+	serial_out(up, UART_MCR, up->mcr);
-+	pm_runtime_put(&up->pdev->dev);
- }
- 
- static void serial_omap_break_ctl(struct uart_port *port, int break_state)
-@@ -442,7 +482,8 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
- 	unsigned long flags = 0;
- 
--	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id);
-+	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	spin_lock_irqsave(&up->port.lock, flags);
- 	if (break_state == -1)
- 		up->lcr |= UART_LCR_SBC;
-@@ -450,6 +491,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
- 		up->lcr &= ~UART_LCR_SBC;
- 	serial_out(up, UART_LCR, up->lcr);
- 	spin_unlock_irqrestore(&up->port.lock, flags);
-+	pm_runtime_put(&up->pdev->dev);
- }
- 
- static int serial_omap_startup(struct uart_port *port)
-@@ -466,8 +508,9 @@ static int serial_omap_startup(struct uart_port *port)
- 	if (retval)
- 		return retval;
- 
--	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id);
-+	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
- 
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	/*
- 	 * Clear the FIFO buffers and disable them.
- 	 * (they will be reenabled in set_termios())
-@@ -505,8 +548,8 @@ static int serial_omap_startup(struct uart_port *port)
- 			(dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
- 			0);
- 		init_timer(&(up->uart_dma.rx_timer));
--		up->uart_dma.rx_timer.function = serial_omap_rx_timeout;
--		up->uart_dma.rx_timer.data = up->pdev->id;
-+		up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
-+		up->uart_dma.rx_timer.data = up->port.line;
- 		/* Currently the buffer size is 4KB. Can increase it */
- 		up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
- 			up->uart_dma.rx_buf_size,
-@@ -523,6 +566,8 @@ static int serial_omap_startup(struct uart_port *port)
- 	/* Enable module level wake up */
- 	serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
- 
-+	pm_runtime_mark_last_busy(&up->pdev->dev);
-+	pm_runtime_put_autosuspend(&up->pdev->dev);
- 	up->port_activity = jiffies;
- 	return 0;
- }
-@@ -532,7 +577,9 @@ static void serial_omap_shutdown(struct uart_port *port)
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
- 	unsigned long flags = 0;
- 
--	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id);
-+	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
-+
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	/*
- 	 * Disable interrupts from this port
- 	 */
-@@ -566,6 +613,8 @@ static void serial_omap_shutdown(struct uart_port *port)
- 			up->uart_dma.rx_buf_dma_phys);
- 		up->uart_dma.rx_buf = NULL;
- 	}
-+
-+	pm_runtime_put(&up->pdev->dev);
- 	free_irq(up->port.irq, up);
- }
- 
-@@ -573,8 +622,6 @@ static inline void
- serial_omap_configure_xonxoff
- 		(struct uart_omap_port *up, struct ktermios *termios)
- {
--	unsigned char efr = 0;
--
- 	up->lcr = serial_in(up, UART_LCR);
- 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
- 	up->efr = serial_in(up, UART_EFR);
-@@ -584,8 +631,7 @@ serial_omap_configure_xonxoff
- 	serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
- 
- 	/* clear SW control mode bits */
--	efr = up->efr;
--	efr &= OMAP_UART_SW_CLR;
-+	up->efr &= OMAP_UART_SW_CLR;
- 
- 	/*
- 	 * IXON Flag:
-@@ -593,7 +639,7 @@ serial_omap_configure_xonxoff
- 	 * Transmit XON1, XOFF1
- 	 */
- 	if (termios->c_iflag & IXON)
--		efr |= OMAP_UART_SW_TX;
-+		up->efr |= OMAP_UART_SW_TX;
- 
- 	/*
- 	 * IXOFF Flag:
-@@ -601,7 +647,7 @@ serial_omap_configure_xonxoff
- 	 * Receiver compares XON1, XOFF1.
- 	 */
- 	if (termios->c_iflag & IXOFF)
--		efr |= OMAP_UART_SW_RX;
-+		up->efr |= OMAP_UART_SW_RX;
- 
- 	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
- 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
-@@ -624,13 +670,21 @@ serial_omap_configure_xonxoff
- 	 * load the new software flow control mode IXON or IXOFF
- 	 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
- 	 */
--	serial_out(up, UART_EFR, efr | UART_EFR_SCD);
-+	serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
- 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
- 
- 	serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
- 	serial_out(up, UART_LCR, up->lcr);
- }
- 
-+static void serial_omap_uart_qos_work(struct work_struct *work)
-+{
-+	struct uart_omap_port *up = container_of(work, struct uart_omap_port,
-+						qos_work);
-+
-+	pm_qos_update_request(&up->pm_qos_request, up->latency);
-+}
-+
- static void
- serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
- 			struct ktermios *old)
-@@ -671,6 +725,16 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
- 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
- 	quot = serial_omap_get_divisor(port, baud);
- 
-+	/* calculate wakeup latency constraint */
-+	up->calc_latency = (1000000 * up->port.fifosize) /
-+				(1000 * baud / 8);
-+	up->latency = up->calc_latency;
-+	schedule_work(&up->qos_work);
-+
-+	up->dll = quot & 0xff;
-+	up->dlh = quot >> 8;
-+	up->mdr1 = UART_OMAP_MDR1_DISABLE;
-+
- 	up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
- 			UART_FCR_ENABLE_FIFO;
- 	if (up->use_dma)
-@@ -680,6 +744,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
- 	 * Ok, we're now changing the port state. Do it with
- 	 * interrupts disabled.
- 	 */
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	spin_lock_irqsave(&up->port.lock, flags);
- 
- 	/*
-@@ -723,6 +788,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
- 		up->ier |= UART_IER_MSI;
- 	serial_out(up, UART_IER, up->ier);
- 	serial_out(up, UART_LCR, cval);		/* reset DLAB */
-+	up->lcr = cval;
-+	up->scr = OMAP_UART_SCR_TX_EMPTY;
- 
- 	/* FIFOs and DMA Settings */
- 
-@@ -749,17 +816,22 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
- 
- 	if (up->use_dma) {
- 		serial_out(up, UART_TI752_TLR, 0);
--		serial_out(up, UART_OMAP_SCR,
--			(UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8));
-+		up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
- 	}
- 
-+	serial_out(up, UART_OMAP_SCR, up->scr);
-+
- 	serial_out(up, UART_EFR, up->efr);
- 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
- 	serial_out(up, UART_MCR, up->mcr);
- 
- 	/* Protocol, Baud Rate, and Interrupt Settings */
- 
--	serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
-+	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
-+		serial_omap_mdr1_errataset(up, up->mdr1);
-+	else
-+		serial_out(up, UART_OMAP_MDR1, up->mdr1);
-+
- 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
- 
- 	up->efr = serial_in(up, UART_EFR);
-@@ -769,8 +841,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
- 	serial_out(up, UART_IER, 0);
- 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
- 
--	serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
--	serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
-+	serial_out(up, UART_DLL, up->dll);	/* LS of divisor */
-+	serial_out(up, UART_DLM, up->dlh);	/* MS of divisor */
- 
- 	serial_out(up, UART_LCR, 0);
- 	serial_out(up, UART_IER, up->ier);
-@@ -780,9 +852,14 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
- 	serial_out(up, UART_LCR, cval);
- 
- 	if (baud > 230400 && baud != 3000000)
--		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE);
-+		up->mdr1 = UART_OMAP_MDR1_13X_MODE;
- 	else
--		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
-+		up->mdr1 = UART_OMAP_MDR1_16X_MODE;
-+
-+	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
-+		serial_omap_mdr1_errataset(up, up->mdr1);
-+	else
-+		serial_out(up, UART_OMAP_MDR1, up->mdr1);
- 
- 	/* Hardware Flow Control Configuration */
- 
-@@ -809,7 +886,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
- 	serial_omap_configure_xonxoff(up, termios);
- 
- 	spin_unlock_irqrestore(&up->port.lock, flags);
--	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id);
-+	pm_runtime_put(&up->pdev->dev);
-+	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
- }
- 
- static void
-@@ -819,7 +897,9 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
- 	unsigned char efr;
- 
--	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id);
-+	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
-+
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
- 	efr = serial_in(up, UART_EFR);
- 	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
-@@ -829,6 +909,15 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
- 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
- 	serial_out(up, UART_EFR, efr);
- 	serial_out(up, UART_LCR, 0);
-+
-+	if (!device_may_wakeup(&up->pdev->dev)) {
-+		if (!state)
-+			pm_runtime_forbid(&up->pdev->dev);
-+		else
-+			pm_runtime_allow(&up->pdev->dev);
-+	}
-+
-+	pm_runtime_put(&up->pdev->dev);
- }
- 
- static void serial_omap_release_port(struct uart_port *port)
-@@ -847,7 +936,7 @@ static void serial_omap_config_port(struct uart_port *port, int flags)
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
- 
- 	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
--							up->pdev->id);
-+							up->port.line);
- 	up->port.type = PORT_OMAP;
- }
- 
-@@ -864,7 +953,7 @@ serial_omap_type(struct uart_port *port)
- {
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
- 
--	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id);
-+	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
- 	return up->name;
- }
- 
-@@ -906,19 +995,26 @@ static inline void wait_for_xmitr(struct uart_omap_port *up)
- static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
- {
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
-+
-+	pm_runtime_get_sync(&up->pdev->dev);
- 	wait_for_xmitr(up);
- 	serial_out(up, UART_TX, ch);
-+	pm_runtime_put(&up->pdev->dev);
- }
- 
- static int serial_omap_poll_get_char(struct uart_port *port)
- {
- 	struct uart_omap_port *up = (struct uart_omap_port *)port;
--	unsigned int status = serial_in(up, UART_LSR);
-+	unsigned int status;
- 
-+	pm_runtime_get_sync(&up->pdev->dev);
-+	status = serial_in(up, UART_LSR);
- 	if (!(status & UART_LSR_DR))
- 		return NO_POLL_CHAR;
- 
--	return serial_in(up, UART_RX);
-+	status = serial_in(up, UART_RX);
-+	pm_runtime_put(&up->pdev->dev);
-+	return status;
- }
- 
- #endif /* CONFIG_CONSOLE_POLL */
-@@ -946,6 +1042,8 @@ serial_omap_console_write(struct console *co, const char *s,
- 	unsigned int ier;
- 	int locked = 1;
- 
-+	pm_runtime_get_sync(&up->pdev->dev);
-+
- 	local_irq_save(flags);
- 	if (up->port.sysrq)
- 		locked = 0;
-@@ -978,6 +1076,8 @@ serial_omap_console_write(struct console *co, const char *s,
- 	if (up->msr_saved_flags)
- 		check_modem_status(up);
- 
-+	pm_runtime_mark_last_busy(&up->pdev->dev);
-+	pm_runtime_put_autosuspend(&up->pdev->dev);
- 	if (locked)
- 		spin_unlock(&up->port.lock);
- 	local_irq_restore(flags);
-@@ -1014,7 +1114,7 @@ static struct console serial_omap_console = {
- 
- static void serial_omap_add_console_port(struct uart_omap_port *up)
- {
--	serial_omap_console_ports[up->pdev->id] = up;
-+	serial_omap_console_ports[up->port.line] = up;
- }
- 
- #define OMAP_CONSOLE	(&serial_omap_console)
-@@ -1060,26 +1160,30 @@ static struct uart_driver serial_omap_reg = {
- 	.cons		= OMAP_CONSOLE,
- };
- 
--static int
--serial_omap_suspend(struct platform_device *pdev, pm_message_t state)
-+#ifdef CONFIG_SUSPEND
-+static int serial_omap_suspend(struct device *dev)
- {
--	struct uart_omap_port *up = platform_get_drvdata(pdev);
-+	struct uart_omap_port *up = dev_get_drvdata(dev);
- 
--	if (up)
-+	if (up) {
- 		uart_suspend_port(&serial_omap_reg, &up->port);
-+		flush_work_sync(&up->qos_work);
-+	}
-+
- 	return 0;
- }
- 
--static int serial_omap_resume(struct platform_device *dev)
-+static int serial_omap_resume(struct device *dev)
- {
--	struct uart_omap_port *up = platform_get_drvdata(dev);
-+	struct uart_omap_port *up = dev_get_drvdata(dev);
- 
- 	if (up)
- 		uart_resume_port(&serial_omap_reg, &up->port);
- 	return 0;
- }
-+#endif
- 
--static void serial_omap_rx_timeout(unsigned long uart_no)
-+static void serial_omap_rxdma_poll(unsigned long uart_no)
- {
- 	struct uart_omap_port *up = ui[uart_no];
- 	unsigned int curr_dma_pos, curr_transmitted_size;
-@@ -1089,9 +1193,9 @@ static void serial_omap_rx_timeout(unsigned long uart_no)
- 	if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
- 			     (curr_dma_pos == 0)) {
- 		if (jiffies_to_msecs(jiffies - up->port_activity) <
--							RX_TIMEOUT) {
-+						up->uart_dma.rx_timeout) {
- 			mod_timer(&up->uart_dma.rx_timer, jiffies +
--				usecs_to_jiffies(up->uart_dma.rx_timeout));
-+				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
- 		} else {
- 			serial_omap_stop_rxdma(up);
- 			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
-@@ -1120,7 +1224,7 @@ static void serial_omap_rx_timeout(unsigned long uart_no)
- 		}
- 	} else  {
- 		mod_timer(&up->uart_dma.rx_timer, jiffies +
--			usecs_to_jiffies(up->uart_dma.rx_timeout));
-+			usecs_to_jiffies(up->uart_dma.rx_poll_rate));
- 	}
- 	up->port_activity = jiffies;
- }
-@@ -1135,6 +1239,7 @@ static int serial_omap_start_rxdma(struct uart_omap_port *up)
- 	int ret = 0;
- 
- 	if (up->uart_dma.rx_dma_channel == -1) {
-+		pm_runtime_get_sync(&up->pdev->dev);
- 		ret = omap_request_dma(up->uart_dma.uart_dma_rx,
- 				"UART Rx DMA",
- 				(void *)uart_rx_dma_callback, up,
-@@ -1158,7 +1263,7 @@ static int serial_omap_start_rxdma(struct uart_omap_port *up)
- 	/* FIXME: Cache maintenance needed here? */
- 	omap_start_dma(up->uart_dma.rx_dma_channel);
- 	mod_timer(&up->uart_dma.rx_timer, jiffies +
--				usecs_to_jiffies(up->uart_dma.rx_timeout));
-+				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
- 	up->uart_dma.rx_dma_used = true;
- 	return ret;
- }
-@@ -1221,6 +1326,19 @@ static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
- 	return;
- }
- 
-+static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
-+{
-+	struct omap_uart_port_info *omap_up_info;
-+
-+	omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
-+	if (!omap_up_info)
-+		return NULL; /* out of memory */
-+
-+	of_property_read_u32(dev->of_node, "clock-frequency",
-+					 &omap_up_info->uartclk);
-+	return omap_up_info;
-+}
-+
- static int serial_omap_probe(struct platform_device *pdev)
- {
- 	struct uart_omap_port	*up;
-@@ -1228,6 +1346,9 @@ static int serial_omap_probe(struct platform_device *pdev)
- 	struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
- 	int ret = -ENOSPC;
- 
-+	if (pdev->dev.of_node)
-+		omap_up_info = of_get_uart_port_info(&pdev->dev);
-+
- 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	if (!mem) {
- 		dev_err(&pdev->dev, "no mem resource?\n");
-@@ -1263,7 +1384,6 @@ static int serial_omap_probe(struct platform_device *pdev)
- 		ret = -ENOMEM;
- 		goto do_release_region;
- 	}
--	sprintf(up->name, "OMAP UART%d", pdev->id);
- 	up->pdev = pdev;
- 	up->port.dev = &pdev->dev;
- 	up->port.type = PORT_OMAP;
-@@ -1273,34 +1393,74 @@ static int serial_omap_probe(struct platform_device *pdev)
- 	up->port.regshift = 2;
- 	up->port.fifosize = 64;
- 	up->port.ops = &serial_omap_pops;
--	up->port.line = pdev->id;
- 
--	up->port.membase = omap_up_info->membase;
--	up->port.mapbase = omap_up_info->mapbase;
-+	if (pdev->dev.of_node)
-+		up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
-+	else
-+		up->port.line = pdev->id;
-+
-+	if (up->port.line < 0) {
-+		dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
-+								up->port.line);
-+		ret = -ENODEV;
-+		goto err;
-+	}
-+
-+	sprintf(up->name, "OMAP UART%d", up->port.line);
-+	up->port.mapbase = mem->start;
-+	up->port.membase = ioremap(mem->start, resource_size(mem));
-+	if (!up->port.membase) {
-+		dev_err(&pdev->dev, "can't ioremap UART\n");
-+		ret = -ENOMEM;
-+		goto err;
-+	}
-+
- 	up->port.flags = omap_up_info->flags;
--	up->port.irqflags = omap_up_info->irqflags;
- 	up->port.uartclk = omap_up_info->uartclk;
-+	if (!up->port.uartclk) {
-+		up->port.uartclk = DEFAULT_CLK_SPEED;
-+		dev_warn(&pdev->dev, "No clock speed specified: using default:"
-+						"%d\n", DEFAULT_CLK_SPEED);
-+	}
- 	up->uart_dma.uart_base = mem->start;
-+	up->errata = omap_up_info->errata;
- 
- 	if (omap_up_info->dma_enabled) {
- 		up->uart_dma.uart_dma_tx = dma_tx->start;
- 		up->uart_dma.uart_dma_rx = dma_rx->start;
- 		up->use_dma = 1;
--		up->uart_dma.rx_buf_size = 4096;
--		up->uart_dma.rx_timeout = 2;
-+		up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
-+		up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
-+		up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
- 		spin_lock_init(&(up->uart_dma.tx_lock));
- 		spin_lock_init(&(up->uart_dma.rx_lock));
- 		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
- 		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
- 	}
- 
--	ui[pdev->id] = up;
-+	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
-+	up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
-+	pm_qos_add_request(&up->pm_qos_request,
-+		PM_QOS_CPU_DMA_LATENCY, up->latency);
-+	serial_omap_uart_wq = create_singlethread_workqueue(up->name);
-+	INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
-+
-+	pm_runtime_use_autosuspend(&pdev->dev);
-+	pm_runtime_set_autosuspend_delay(&pdev->dev,
-+			omap_up_info->autosuspend_timeout);
-+
-+	pm_runtime_irq_safe(&pdev->dev);
-+	pm_runtime_enable(&pdev->dev);
-+	pm_runtime_get_sync(&pdev->dev);
-+
-+	ui[up->port.line] = up;
- 	serial_omap_add_console_port(up);
- 
- 	ret = uart_add_one_port(&serial_omap_reg, &up->port);
- 	if (ret != 0)
- 		goto do_release_region;
- 
-+	pm_runtime_put(&pdev->dev);
- 	platform_set_drvdata(pdev, up);
- 	return 0;
- err:
-@@ -1315,22 +1475,168 @@ static int serial_omap_remove(struct platform_device *dev)
- {
- 	struct uart_omap_port *up = platform_get_drvdata(dev);
- 
--	platform_set_drvdata(dev, NULL);
- 	if (up) {
-+		pm_runtime_disable(&up->pdev->dev);
- 		uart_remove_one_port(&serial_omap_reg, &up->port);
-+		pm_qos_remove_request(&up->pm_qos_request);
-+
- 		kfree(up);
- 	}
-+
-+	platform_set_drvdata(dev, NULL);
-+	return 0;
-+}
-+
-+/*
-+ * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
-+ * The access to uart register after MDR1 Access
-+ * causes UART to corrupt data.
-+ *
-+ * Need a delay =
-+ * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
-+ * give 10 times as much
-+ */
-+static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
-+{
-+	u8 timeout = 255;
-+
-+	serial_out(up, UART_OMAP_MDR1, mdr1);
-+	udelay(2);
-+	serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
-+			UART_FCR_CLEAR_RCVR);
-+	/*
-+	 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
-+	 * TX_FIFO_E bit is 1.
-+	 */
-+	while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
-+				(UART_LSR_THRE | UART_LSR_DR))) {
-+		timeout--;
-+		if (!timeout) {
-+			/* Should *never* happen. we warn and carry on */
-+			dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
-+						serial_in(up, UART_LSR));
-+			break;
-+		}
-+		udelay(1);
-+	}
-+}
-+
-+static void serial_omap_restore_context(struct uart_omap_port *up)
-+{
-+	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
-+		serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
-+	else
-+		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
-+
-+	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
-+	serial_out(up, UART_EFR, UART_EFR_ECB);
-+	serial_out(up, UART_LCR, 0x0); /* Operational mode */
-+	serial_out(up, UART_IER, 0x0);
-+	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
-+	serial_out(up, UART_DLL, up->dll);
-+	serial_out(up, UART_DLM, up->dlh);
-+	serial_out(up, UART_LCR, 0x0); /* Operational mode */
-+	serial_out(up, UART_IER, up->ier);
-+	serial_out(up, UART_FCR, up->fcr);
-+	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
-+	serial_out(up, UART_MCR, up->mcr);
-+	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
-+	serial_out(up, UART_OMAP_SCR, up->scr);
-+	serial_out(up, UART_EFR, up->efr);
-+	serial_out(up, UART_LCR, up->lcr);
-+	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
-+		serial_omap_mdr1_errataset(up, up->mdr1);
-+	else
-+		serial_out(up, UART_OMAP_MDR1, up->mdr1);
-+}
-+
-+#ifdef CONFIG_PM_RUNTIME
-+static int serial_omap_runtime_suspend(struct device *dev)
-+{
-+	struct uart_omap_port *up = dev_get_drvdata(dev);
-+	struct omap_uart_port_info *pdata = dev->platform_data;
-+
-+	if (!up)
-+		return -EINVAL;
-+
-+	if (!pdata || !pdata->enable_wakeup)
-+		return 0;
-+
-+	if (pdata->get_context_loss_count)
-+		up->context_loss_cnt = pdata->get_context_loss_count(dev);
-+
-+	if (device_may_wakeup(dev)) {
-+		if (!up->wakeups_enabled) {
-+			pdata->enable_wakeup(up->pdev, true);
-+			up->wakeups_enabled = true;
-+		}
-+	} else {
-+		if (up->wakeups_enabled) {
-+			pdata->enable_wakeup(up->pdev, false);
-+			up->wakeups_enabled = false;
-+		}
-+	}
-+
-+	/* Errata i291 */
-+	if (up->use_dma && pdata->set_forceidle &&
-+			(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-+		pdata->set_forceidle(up->pdev);
-+
-+	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
-+	schedule_work(&up->qos_work);
-+
-+	return 0;
-+}
-+
-+static int serial_omap_runtime_resume(struct device *dev)
-+{
-+	struct uart_omap_port *up = dev_get_drvdata(dev);
-+	struct omap_uart_port_info *pdata = dev->platform_data;
-+
-+	if (up) {
-+		if (pdata->get_context_loss_count) {
-+			u32 loss_cnt = pdata->get_context_loss_count(dev);
-+
-+			if (up->context_loss_cnt != loss_cnt)
-+				serial_omap_restore_context(up);
-+		}
-+
-+		/* Errata i291 */
-+		if (up->use_dma && pdata->set_noidle &&
-+				(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-+			pdata->set_noidle(up->pdev);
-+
-+		up->latency = up->calc_latency;
-+		schedule_work(&up->qos_work);
-+	}
-+
- 	return 0;
- }
-+#endif
-+
-+static const struct dev_pm_ops serial_omap_dev_pm_ops = {
-+	SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
-+	SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
-+				serial_omap_runtime_resume, NULL)
-+};
-+
-+#if defined(CONFIG_OF)
-+static const struct of_device_id omap_serial_of_match[] = {
-+	{ .compatible = "ti,omap2-uart" },
-+	{ .compatible = "ti,omap3-uart" },
-+	{ .compatible = "ti,omap4-uart" },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, omap_serial_of_match);
-+#endif
- 
- static struct platform_driver serial_omap_driver = {
- 	.probe          = serial_omap_probe,
- 	.remove         = serial_omap_remove,
--
--	.suspend	= serial_omap_suspend,
--	.resume		= serial_omap_resume,
- 	.driver		= {
- 		.name	= DRIVER_NAME,
-+		.pm	= &serial_omap_dev_pm_ops,
-+		.of_match_table = of_match_ptr(omap_serial_of_match),
- 	},
- };
- 
-diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig
-index 6f3ea9b..9016ec1 100644
---- a/drivers/uio/Kconfig
-+++ b/drivers/uio/Kconfig
-@@ -96,9 +96,9 @@ config UIO_NETX
- 
- config UIO_PRUSS
- 	tristate "Texas Instruments PRUSS driver"
--	depends on ARCH_DAVINCI_DA850
-+	depends on ARCH_DAVINCI_DA850 || SOC_OMAPAM33XX
- 	help
--	  PRUSS driver for OMAPL138/DA850/AM18XX devices
-+	  PRUSS driver for OMAPL138/DA850/AM18XX/AM33XX devices
- 	  PRUSS driver requires user space components, examples and user space
- 	  driver is available from below SVN repo - you may use anonymous login
- 
-diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c
-index e67b566..42553d2 100644
---- a/drivers/uio/uio_pruss.c
-+++ b/drivers/uio/uio_pruss.c
-@@ -25,7 +25,14 @@
- #include <linux/clk.h>
- #include <linux/dma-mapping.h>
- #include <linux/slab.h>
-+
-+#ifdef ARCH_DAVINCI_DA850
-+#define ENABLE_SRAM_SUPPORT
-+#endif
-+
-+#ifdef ENABLE_SRAM_SUPPORT
- #include <mach/sram.h>
-+#endif
- 
- #define DRV_NAME "pruss_uio"
- #define DRV_VERSION "1.0"
-@@ -62,7 +69,7 @@ MODULE_PARM_DESC(extram_pool_sz, "external ram pool size to allocate");
- struct uio_pruss_dev {
- 	struct uio_info *info;
- 	struct clk *pruss_clk;
--	dma_addr_t sram_paddr;
-+	phys_addr_t sram_paddr;
- 	dma_addr_t ddr_paddr;
- 	void __iomem *prussio_vaddr;
- 	void *sram_vaddr;
-@@ -105,8 +112,11 @@ static void pruss_cleanup(struct platform_device *dev,
- 		dma_free_coherent(&dev->dev, extram_pool_sz, gdev->ddr_vaddr,
- 			gdev->ddr_paddr);
- 	}
-+#ifdef ENABLE_SRAM_SUPPORT
- 	if (gdev->sram_vaddr)
--		sram_free(gdev->sram_vaddr, sram_pool_sz);
-+		gen_pool_free(davinci_gen_pool,
-+			      (unsigned long)gdev->sram_vaddr, sram_pool_sz);
-+#endif
- 	kfree(gdev->info);
- 	clk_put(gdev->pruss_clk);
- 	kfree(gdev);
-@@ -152,12 +162,17 @@ static int __devinit pruss_probe(struct platform_device *dev)
- 		goto out_free;
- 	}
- 
--	gdev->sram_vaddr = sram_alloc(sram_pool_sz, &(gdev->sram_paddr));
-+#ifdef ENABLE_SRAM_SUPPORT
-+	gdev->sram_vaddr = (void *)gen_pool_alloc(davinci_gen_pool,
-+						  sram_pool_sz);
- 	if (!gdev->sram_vaddr) {
- 		dev_err(&dev->dev, "Could not allocate SRAM pool\n");
- 		goto out_free;
- 	}
- 
-+	gdev->sram_paddr = gen_pool_virt_to_phys(davinci_gen_pool,
-+					(unsigned long)gdev->sram_vaddr);
-+#endif
- 	gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz,
- 				&(gdev->ddr_paddr), GFP_KERNEL | GFP_DMA);
- 	if (!gdev->ddr_vaddr) {
-@@ -179,8 +194,6 @@ static int __devinit pruss_probe(struct platform_device *dev)
- 		p->mem[0].addr = regs_prussio->start;
- 		p->mem[0].size = resource_size(regs_prussio);
- 		p->mem[0].memtype = UIO_MEM_PHYS;
--
--		p->mem[1].addr = gdev->sram_paddr;
- 		p->mem[1].size = sram_pool_sz;
- 		p->mem[1].memtype = UIO_MEM_PHYS;
- 
-diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
-index e238b3b..18373ec 100644
---- a/drivers/usb/core/hub.c
-+++ b/drivers/usb/core/hub.c
-@@ -1300,7 +1300,7 @@ static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id)
- 	 * since that isn't a "real" hub.
- 	 */
- 	if (!hub_is_superspeed(hdev) || !hdev->parent)
--		usb_enable_autosuspend(hdev);
-+		usb_disable_autosuspend(hdev);
- 
- 	if (hdev->level == MAX_TOPO_LEVEL) {
- 		dev_err(&intf->dev,
-diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
-index 3700aa6..dfcda94 100644
---- a/drivers/usb/dwc3/gadget.c
-+++ b/drivers/usb/dwc3/gadget.c
-@@ -1980,7 +1980,7 @@ int __devinit dwc3_gadget_init(struct dwc3 *dwc)
- 	dev_set_name(&dwc->gadget.dev, "gadget");
- 
- 	dwc->gadget.ops			= &dwc3_gadget_ops;
--	dwc->gadget.is_dualspeed	= true;
-+	dwc->gadget.max_speed		= USB_SPEED_SUPER;
- 	dwc->gadget.speed		= USB_SPEED_UNKNOWN;
- 	dwc->gadget.dev.parent		= dwc->dev;
- 
-diff --git a/drivers/usb/gadget/amd5536udc.c b/drivers/usb/gadget/amd5536udc.c
-index 45f422a..e9a2c5c 100644
---- a/drivers/usb/gadget/amd5536udc.c
-+++ b/drivers/usb/gadget/amd5536udc.c
-@@ -1959,7 +1959,7 @@ static int amd5536_start(struct usb_gadget_driver *driver,
- 	u32 tmp;
- 
- 	if (!driver || !bind || !driver->setup
--			|| driver->speed < USB_SPEED_HIGH)
-+			|| driver->max_speed < USB_SPEED_HIGH)
- 		return -EINVAL;
- 	if (!dev)
- 		return -ENODEV;
-@@ -3349,7 +3349,7 @@ static int udc_probe(struct udc *dev)
- 	dev_set_name(&dev->gadget.dev, "gadget");
- 	dev->gadget.dev.release = gadget_release;
- 	dev->gadget.name = name;
--	dev->gadget.is_dualspeed = 1;
-+	dev->gadget.max_speed = USB_SPEED_HIGH;
- 
- 	/* init registers, interrupts, ... */
- 	startup_registers(dev);
-diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
-index 8efe0fa..ac41f71 100644
---- a/drivers/usb/gadget/at91_udc.c
-+++ b/drivers/usb/gadget/at91_udc.c
-@@ -1633,7 +1633,7 @@ static int at91_start(struct usb_gadget_driver *driver,
- 	unsigned long	flags;
- 
- 	if (!driver
--			|| driver->speed < USB_SPEED_FULL
-+			|| driver->max_speed < USB_SPEED_FULL
- 			|| !bind
- 			|| !driver->setup) {
- 		DBG("bad parameter.\n");
-diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
-index 271a9d8..e2fb6d5 100644
---- a/drivers/usb/gadget/atmel_usba_udc.c
-+++ b/drivers/usb/gadget/atmel_usba_udc.c
-@@ -1038,7 +1038,7 @@ static struct usba_udc the_udc = {
- 	.gadget	= {
- 		.ops		= &usba_udc_ops,
- 		.ep_list	= LIST_HEAD_INIT(the_udc.gadget.ep_list),
--		.is_dualspeed	= 1,
-+		.max_speed	= USB_SPEED_HIGH,
- 		.name		= "atmel_usba_udc",
- 		.dev	= {
- 			.init_name	= "gadget",
-diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
-index 9a0c397..bd96ad9 100644
---- a/drivers/usb/gadget/ci13xxx_udc.c
-+++ b/drivers/usb/gadget/ci13xxx_udc.c
-@@ -754,8 +754,11 @@ static ssize_t show_device(struct device *dev, struct device_attribute *attr,
- 
- 	n += scnprintf(buf + n, PAGE_SIZE - n, "speed             = %d\n",
- 		       gadget->speed);
-+	n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed         = %d\n",
-+		       gadget->max_speed);
-+	/* TODO: Scheduled for removal in 3.8. */
- 	n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed      = %d\n",
--		       gadget->is_dualspeed);
-+		       gadget_is_dualspeed(gadget));
- 	n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg            = %d\n",
- 		       gadget->is_otg);
- 	n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral   = %d\n",
-@@ -798,7 +801,7 @@ static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
- 	n += scnprintf(buf + n, PAGE_SIZE - n, "function  = %s\n",
- 		       (driver->function ? driver->function : ""));
- 	n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
--		       driver->speed);
-+		       driver->max_speed);
- 
- 	return n;
- }
-@@ -2871,7 +2874,7 @@ static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
- 
- 	udc->gadget.ops          = &usb_gadget_ops;
- 	udc->gadget.speed        = USB_SPEED_UNKNOWN;
--	udc->gadget.is_dualspeed = 1;
-+	udc->gadget.max_speed    = USB_SPEED_HIGH;
- 	udc->gadget.is_otg       = 0;
- 	udc->gadget.name         = driver->name;
- 
-diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
-index f71b078..a95de6a 100644
---- a/drivers/usb/gadget/composite.c
-+++ b/drivers/usb/gadget/composite.c
-@@ -1535,9 +1535,9 @@ composite_resume(struct usb_gadget *gadget)
- 
- static struct usb_gadget_driver composite_driver = {
- #ifdef CONFIG_USB_GADGET_SUPERSPEED
--	.speed		= USB_SPEED_SUPER,
-+	.max_speed	= USB_SPEED_SUPER,
- #else
--	.speed		= USB_SPEED_HIGH,
-+	.max_speed	= USB_SPEED_HIGH,
- #endif
- 
- 	.unbind		= composite_unbind,
-@@ -1584,8 +1584,8 @@ int usb_composite_probe(struct usb_composite_driver *driver,
- 		driver->iProduct = driver->name;
- 	composite_driver.function =  (char *) driver->name;
- 	composite_driver.driver.name = driver->name;
--	composite_driver.speed = min((u8)composite_driver.speed,
--				     (u8)driver->max_speed);
-+	composite_driver.max_speed =
-+		min_t(u8, composite_driver.max_speed, driver->max_speed);
- 	composite = driver;
- 	composite_gadget_bind = bind;
- 
-diff --git a/drivers/usb/gadget/dbgp.c b/drivers/usb/gadget/dbgp.c
-index 6256420..19d7bb0 100644
---- a/drivers/usb/gadget/dbgp.c
-+++ b/drivers/usb/gadget/dbgp.c
-@@ -404,7 +404,7 @@ fail:
- 
- static struct usb_gadget_driver dbgp_driver = {
- 	.function = "dbgp",
--	.speed = USB_SPEED_HIGH,
-+	.max_speed = USB_SPEED_HIGH,
- 	.unbind = dbgp_unbind,
- 	.setup = dbgp_setup,
- 	.disconnect = dbgp_disconnect,
-diff --git a/drivers/usb/gadget/dummy_hcd.c b/drivers/usb/gadget/dummy_hcd.c
-index ab8f1b4..db815c2 100644
---- a/drivers/usb/gadget/dummy_hcd.c
-+++ b/drivers/usb/gadget/dummy_hcd.c
-@@ -823,19 +823,18 @@ static int dummy_pullup (struct usb_gadget *_gadget, int value)
- 
- 	if (value && dum->driver) {
- 		if (mod_data.is_super_speed)
--			dum->gadget.speed = dum->driver->speed;
-+			dum->gadget.speed = dum->driver->max_speed;
- 		else if (mod_data.is_high_speed)
- 			dum->gadget.speed = min_t(u8, USB_SPEED_HIGH,
--					dum->driver->speed);
-+					dum->driver->max_speed);
- 		else
- 			dum->gadget.speed = USB_SPEED_FULL;
- 		dummy_udc_udpate_ep0(dum);
- 
--		if (dum->gadget.speed < dum->driver->speed)
-+		if (dum->gadget.speed < dum->driver->max_speed)
- 			dev_dbg(udc_dev(dum), "This device can perform faster"
--					" if you connect it to a %s port...\n",
--					(dum->driver->speed == USB_SPEED_SUPER ?
--					 "SuperSpeed" : "HighSpeed"));
-+				" if you connect it to a %s port...\n",
-+				usb_speed_string(dum->driver->max_speed));
- 	}
- 	dum_hcd = gadget_to_dummy_hcd(_gadget);
- 
-@@ -898,7 +897,7 @@ static int dummy_udc_start(struct usb_gadget *g,
- 	struct dummy_hcd	*dum_hcd = gadget_to_dummy_hcd(g);
- 	struct dummy		*dum = dum_hcd->dum;
- 
--	if (driver->speed == USB_SPEED_UNKNOWN)
-+	if (driver->max_speed == USB_SPEED_UNKNOWN)
- 		return -EINVAL;
- 
- 	/*
-@@ -977,7 +976,7 @@ static int dummy_udc_probe (struct platform_device *pdev)
- 
- 	dum->gadget.name = gadget_name;
- 	dum->gadget.ops = &dummy_ops;
--	dum->gadget.is_dualspeed = 1;
-+	dum->gadget.max_speed = USB_SPEED_SUPER;
- 
- 	dev_set_name(&dum->gadget.dev, "gadget");
- 	dum->gadget.dev.parent = &pdev->dev;
-diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
-index 4dff83d..a9f58da 100644
---- a/drivers/usb/gadget/epautoconf.c
-+++ b/drivers/usb/gadget/epautoconf.c
-@@ -149,7 +149,7 @@ ep_matches (
- 	switch (type) {
- 	case USB_ENDPOINT_XFER_INT:
- 		/* INT:  limit 64 bytes full speed, 1024 high/super speed */
--		if (!gadget->is_dualspeed && max > 64)
-+		if (!gadget_is_dualspeed(gadget) && max > 64)
- 			return 0;
- 		/* FALLTHROUGH */
- 
-@@ -157,12 +157,12 @@ ep_matches (
- 		/* ISO:  limit 1023 bytes full speed, 1024 high/super speed */
- 		if (ep->maxpacket < max)
- 			return 0;
--		if (!gadget->is_dualspeed && max > 1023)
-+		if (!gadget_is_dualspeed(gadget) && max > 1023)
- 			return 0;
- 
- 		/* BOTH:  "high bandwidth" works only at high speed */
- 		if ((desc->wMaxPacketSize & cpu_to_le16(3<<11))) {
--			if (!gadget->is_dualspeed)
-+			if (!gadget_is_dualspeed(gadget))
- 				return 0;
- 			/* configure your hardware with enough buffering!! */
- 		}
-@@ -380,6 +380,7 @@ void usb_ep_autoconfig_reset (struct usb_gadget *gadget)
- 
- 	list_for_each_entry (ep, &gadget->ep_list, ep_list) {
- 		ep->driver_data = NULL;
-+		ep->desc = NULL;
- 	}
- #ifdef	MANY_ENDPOINTS
- 	in_epnum = 0;
-diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
-index 0cd764d..5c1e1a9 100644
---- a/drivers/usb/gadget/ether.c
-+++ b/drivers/usb/gadget/ether.c
-@@ -93,6 +93,10 @@ static inline bool has_rndis(void)
- #endif
- }
- 
-+static char manufacturer[50];
-+
-+static u16 vendorID;
-+
- /*-------------------------------------------------------------------------*/
- 
- /*
-@@ -201,8 +205,6 @@ static const struct usb_descriptor_header *otg_desc[] = {
- #define STRING_MANUFACTURER_IDX		0
- #define STRING_PRODUCT_IDX		1
- 
--static char manufacturer[50];
--
- static struct usb_string strings_dev[] = {
- 	[STRING_MANUFACTURER_IDX].s = manufacturer,
- 	[STRING_PRODUCT_IDX].s = PREFIX DRIVER_DESC,
-@@ -323,6 +325,8 @@ static int __init eth_bind(struct usb_composite_dev *cdev)
- 		device_desc.bNumConfigurations = 2;
- 	}
- 
-+	vendorID = device_desc.idVendor;
-+
- 	gcnum = usb_gadget_controller_number(gadget);
- 	if (gcnum >= 0)
- 		device_desc.bcdDevice = cpu_to_le16(0x0300 | gcnum);
-diff --git a/drivers/usb/gadget/f_ecm.c b/drivers/usb/gadget/f_ecm.c
-index 11c07cb..58d9172 100644
---- a/drivers/usb/gadget/f_ecm.c
-+++ b/drivers/usb/gadget/f_ecm.c
-@@ -690,6 +690,7 @@ ecm_bind(struct usb_configuration *c, struct usb_function *f)
- 	status = -ENODEV;
- 
- 	/* allocate instance-specific endpoints */
-+	usb_ep_autoconfig_reset(cdev->gadget);
- 	ep = usb_ep_autoconfig(cdev->gadget, &fs_ecm_in_desc);
- 	if (!ep)
- 		goto fail;
-diff --git a/drivers/usb/gadget/f_rndis.c b/drivers/usb/gadget/f_rndis.c
-index 704d1d9..d2f1b6f 100644
---- a/drivers/usb/gadget/f_rndis.c
-+++ b/drivers/usb/gadget/f_rndis.c
-@@ -684,6 +684,7 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f)
- 	status = -ENODEV;
- 
- 	/* allocate instance-specific endpoints */
-+	usb_ep_autoconfig_reset(cdev->gadget);
- 	ep = usb_ep_autoconfig(cdev->gadget, &fs_in_desc);
- 	if (!ep)
- 		goto fail;
-@@ -766,14 +767,11 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f)
- 
- 	rndis_set_param_medium(rndis->config, NDIS_MEDIUM_802_3, 0);
- 	rndis_set_host_mac(rndis->config, rndis->ethaddr);
--
--#if 0
--// FIXME
-+/*
- 	if (rndis_set_param_vendor(rndis->config, vendorID,
- 				manufacturer))
--		goto fail0;
--#endif
--
-+		goto fail;
-+*/
- 	/* NOTE:  all that is done without knowing or caring about
- 	 * the network link ... which is unavailable to this code
- 	 * until we're activated via set_alt().
-diff --git a/drivers/usb/gadget/f_subset.c b/drivers/usb/gadget/f_subset.c
-index 21ab474..160ba02 100644
---- a/drivers/usb/gadget/f_subset.c
-+++ b/drivers/usb/gadget/f_subset.c
-@@ -307,6 +307,7 @@ geth_bind(struct usb_configuration *c, struct usb_function *f)
- 	status = -ENODEV;
- 
- 	/* allocate instance-specific endpoints */
-+	usb_ep_autoconfig_reset(cdev->gadget);
- 	ep = usb_ep_autoconfig(cdev->gadget, &fs_subset_in_desc);
- 	if (!ep)
- 		goto fail;
-diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
-index 11b5196..17a7047 100644
---- a/drivers/usb/gadget/file_storage.c
-+++ b/drivers/usb/gadget/file_storage.c
-@@ -3584,7 +3584,7 @@ static void fsg_resume(struct usb_gadget *gadget)
- /*-------------------------------------------------------------------------*/
- 
- static struct usb_gadget_driver		fsg_driver = {
--	.speed		= USB_SPEED_SUPER,
-+	.max_speed	= USB_SPEED_SUPER,
- 	.function	= (char *) fsg_string_product,
- 	.unbind		= fsg_unbind,
- 	.disconnect	= fsg_disconnect,
-diff --git a/drivers/usb/gadget/fsl_qe_udc.c b/drivers/usb/gadget/fsl_qe_udc.c
-index e00cf92..b7a1efe 100644
---- a/drivers/usb/gadget/fsl_qe_udc.c
-+++ b/drivers/usb/gadget/fsl_qe_udc.c
-@@ -2336,7 +2336,7 @@ static int fsl_qe_start(struct usb_gadget_driver *driver,
- 	if (!udc_controller)
- 		return -ENODEV;
- 
--	if (!driver || driver->speed < USB_SPEED_FULL
-+	if (!driver || driver->max_speed < USB_SPEED_FULL
- 			|| !bind || !driver->disconnect || !driver->setup)
- 		return -EINVAL;
- 
-@@ -2350,7 +2350,7 @@ static int fsl_qe_start(struct usb_gadget_driver *driver,
- 	/* hook up the driver */
- 	udc_controller->driver = driver;
- 	udc_controller->gadget.dev.driver = &driver->driver;
--	udc_controller->gadget.speed = (enum usb_device_speed)(driver->speed);
-+	udc_controller->gadget.speed = driver->max_speed;
- 	spin_unlock_irqrestore(&udc_controller->lock, flags);
- 
- 	retval = bind(&udc_controller->gadget);
-diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
-index 8e3e509..9085d14 100644
---- a/drivers/usb/gadget/fsl_udc_core.c
-+++ b/drivers/usb/gadget/fsl_udc_core.c
-@@ -1932,7 +1932,7 @@ static int fsl_start(struct usb_gadget_driver *driver,
- 	if (!udc_controller)
- 		return -ENODEV;
- 
--	if (!driver || driver->speed < USB_SPEED_FULL
-+	if (!driver || driver->max_speed < USB_SPEED_FULL
- 			|| !bind || !driver->disconnect || !driver->setup)
- 		return -EINVAL;
- 
-@@ -2523,7 +2523,7 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
- 
- 	/* Setup gadget structure */
- 	udc_controller->gadget.ops = &fsl_gadget_ops;
--	udc_controller->gadget.is_dualspeed = 1;
-+	udc_controller->gadget.max_speed = USB_SPEED_HIGH;
- 	udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
- 	INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
- 	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
-diff --git a/drivers/usb/gadget/fusb300_udc.c b/drivers/usb/gadget/fusb300_udc.c
-index 74da206..5831cb4 100644
---- a/drivers/usb/gadget/fusb300_udc.c
-+++ b/drivers/usb/gadget/fusb300_udc.c
-@@ -1317,7 +1317,7 @@ static int fusb300_udc_start(struct usb_gadget_driver *driver,
- 	int retval;
- 
- 	if (!driver
--			|| driver->speed < USB_SPEED_FULL
-+			|| driver->max_speed < USB_SPEED_FULL
- 			|| !bind
- 			|| !driver->setup)
- 		return -EINVAL;
-@@ -1463,7 +1463,7 @@ static int __init fusb300_probe(struct platform_device *pdev)
- 
- 	dev_set_name(&fusb300->gadget.dev, "gadget");
- 
--	fusb300->gadget.is_dualspeed = 1;
-+	fusb300->gadget.max_speed = USB_SPEED_HIGH;
- 	fusb300->gadget.dev.parent = &pdev->dev;
- 	fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
- 	fusb300->gadget.dev.release = pdev->dev.release;
-diff --git a/drivers/usb/gadget/goku_udc.c b/drivers/usb/gadget/goku_udc.c
-index 7f87805..5af70fc 100644
---- a/drivers/usb/gadget/goku_udc.c
-+++ b/drivers/usb/gadget/goku_udc.c
-@@ -1357,7 +1357,7 @@ static int goku_start(struct usb_gadget_driver *driver,
- 	int			retval;
- 
- 	if (!driver
--			|| driver->speed < USB_SPEED_FULL
-+			|| driver->max_speed < USB_SPEED_FULL
- 			|| !bind
- 			|| !driver->disconnect
- 			|| !driver->setup)
-@@ -1796,6 +1796,7 @@ static int goku_probe(struct pci_dev *pdev, const struct pci_device_id *id)
- 	spin_lock_init(&dev->lock);
- 	dev->pdev = pdev;
- 	dev->gadget.ops = &goku_ops;
-+	dev->gadget.max_speed = USB_SPEED_FULL;
- 
- 	/* the "gadget" abstracts/virtualizes the controller */
- 	dev_set_name(&dev->gadget.dev, "gadget");
-diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
-index 2d978c0..8d1c75a 100644
---- a/drivers/usb/gadget/imx_udc.c
-+++ b/drivers/usb/gadget/imx_udc.c
-@@ -1336,7 +1336,7 @@ static int imx_udc_start(struct usb_gadget_driver *driver,
- 	int retval;
- 
- 	if (!driver
--		|| driver->speed < USB_SPEED_FULL
-+		|| driver->max_speed < USB_SPEED_FULL
- 		|| !bind
- 		|| !driver->disconnect
- 		|| !driver->setup)
-diff --git a/drivers/usb/gadget/inode.c b/drivers/usb/gadget/inode.c
-index 7138540..2a96f57 100644
---- a/drivers/usb/gadget/inode.c
-+++ b/drivers/usb/gadget/inode.c
-@@ -1768,9 +1768,9 @@ gadgetfs_suspend (struct usb_gadget *gadget)
- 
- static struct usb_gadget_driver gadgetfs_driver = {
- #ifdef	CONFIG_USB_GADGET_DUALSPEED
--	.speed		= USB_SPEED_HIGH,
-+	.max_speed	= USB_SPEED_HIGH,
- #else
--	.speed		= USB_SPEED_FULL,
-+	.max_speed	= USB_SPEED_FULL,
- #endif
- 	.function	= (char *) driver_desc,
- 	.unbind		= gadgetfs_unbind,
-@@ -1794,7 +1794,7 @@ static int gadgetfs_probe (struct usb_gadget *gadget)
- }
- 
- static struct usb_gadget_driver probe_driver = {
--	.speed		= USB_SPEED_HIGH,
-+	.max_speed	= USB_SPEED_HIGH,
- 	.unbind		= gadgetfs_nop,
- 	.setup		= (void *)gadgetfs_nop,
- 	.disconnect	= gadgetfs_nop,
-diff --git a/drivers/usb/gadget/langwell_udc.c b/drivers/usb/gadget/langwell_udc.c
-index 6ad0ad6..b0c5b6d 100644
---- a/drivers/usb/gadget/langwell_udc.c
-+++ b/drivers/usb/gadget/langwell_udc.c
-@@ -3265,7 +3265,7 @@ static int langwell_udc_probe(struct pci_dev *pdev,
- 	dev->gadget.ep0 = &dev->ep[0].ep;	/* gadget ep0 */
- 	INIT_LIST_HEAD(&dev->gadget.ep_list);	/* ep_list */
- 	dev->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
--	dev->gadget.is_dualspeed = 1;		/* support dual speed */
-+	dev->gadget.max_speed = USB_SPEED_HIGH;	/* support dual speed */
- #ifdef	OTG_TRANSCEIVER
- 	dev->gadget.is_otg = 1;			/* support otg mode */
- #endif
-diff --git a/drivers/usb/gadget/m66592-udc.c b/drivers/usb/gadget/m66592-udc.c
-index 9aa1cbb..3608b3b 100644
---- a/drivers/usb/gadget/m66592-udc.c
-+++ b/drivers/usb/gadget/m66592-udc.c
-@@ -1472,7 +1472,7 @@ static int m66592_start(struct usb_gadget_driver *driver,
- 	int retval;
- 
- 	if (!driver
--			|| driver->speed < USB_SPEED_HIGH
-+			|| driver->max_speed < USB_SPEED_HIGH
- 			|| !bind
- 			|| !driver->setup)
- 		return -EINVAL;
-@@ -1653,7 +1653,7 @@ static int __init m66592_probe(struct platform_device *pdev)
- 	m66592->gadget.ops = &m66592_gadget_ops;
- 	device_initialize(&m66592->gadget.dev);
- 	dev_set_name(&m66592->gadget.dev, "gadget");
--	m66592->gadget.is_dualspeed = 1;
-+	m66592->gadget.max_speed = USB_SPEED_HIGH;
- 	m66592->gadget.dev.parent = &pdev->dev;
- 	m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
- 	m66592->gadget.dev.release = pdev->dev.release;
-diff --git a/drivers/usb/gadget/mv_udc_core.c b/drivers/usb/gadget/mv_udc_core.c
-index 8924121..9376a74 100644
---- a/drivers/usb/gadget/mv_udc_core.c
-+++ b/drivers/usb/gadget/mv_udc_core.c
-@@ -2312,7 +2312,7 @@ static int __devinit mv_udc_probe(struct platform_device *dev)
- 	udc->gadget.ep0 = &udc->eps[0].ep;	/* gadget ep0 */
- 	INIT_LIST_HEAD(&udc->gadget.ep_list);	/* ep_list */
- 	udc->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
--	udc->gadget.is_dualspeed = 1;		/* support dual speed */
-+	udc->gadget.max_speed = USB_SPEED_HIGH;	/* support dual speed */
- 
- 	/* the "gadget" abstracts/virtualizes the controller */
- 	dev_set_name(&udc->gadget.dev, "gadget");
-diff --git a/drivers/usb/gadget/net2272.c b/drivers/usb/gadget/net2272.c
-index d1b7636..4c81d54 100644
---- a/drivers/usb/gadget/net2272.c
-+++ b/drivers/usb/gadget/net2272.c
-@@ -1459,7 +1459,7 @@ static int net2272_start(struct usb_gadget *_gadget,
- 	unsigned i;
- 
- 	if (!driver || !driver->unbind || !driver->setup ||
--	    driver->speed != USB_SPEED_HIGH)
-+	    driver->max_speed != USB_SPEED_HIGH)
- 		return -EINVAL;
- 
- 	dev = container_of(_gadget, struct net2272, gadget);
-@@ -2235,7 +2235,7 @@ net2272_probe_init(struct device *dev, unsigned int irq)
- 	ret->irq = irq;
- 	ret->dev = dev;
- 	ret->gadget.ops = &net2272_ops;
--	ret->gadget.is_dualspeed = 1;
-+	ret->gadget.max_speed = USB_SPEED_HIGH;
- 
- 	/* the "gadget" abstracts/virtualizes the controller */
- 	dev_set_name(&ret->gadget.dev, "gadget");
-diff --git a/drivers/usb/gadget/net2280.c b/drivers/usb/gadget/net2280.c
-index da2b9d0..cf1f364 100644
---- a/drivers/usb/gadget/net2280.c
-+++ b/drivers/usb/gadget/net2280.c
-@@ -1881,7 +1881,7 @@ static int net2280_start(struct usb_gadget *_gadget,
- 	 * (dev->usb->xcvrdiag & FORCE_FULL_SPEED_MODE)
- 	 * "must not be used in normal operation"
- 	 */
--	if (!driver || driver->speed < USB_SPEED_HIGH
-+	if (!driver || driver->max_speed < USB_SPEED_HIGH
- 			|| !driver->setup)
- 		return -EINVAL;
- 
-@@ -2698,7 +2698,7 @@ static int net2280_probe (struct pci_dev *pdev, const struct pci_device_id *id)
- 	spin_lock_init (&dev->lock);
- 	dev->pdev = pdev;
- 	dev->gadget.ops = &net2280_ops;
--	dev->gadget.is_dualspeed = 1;
-+	dev->gadget.max_speed = USB_SPEED_HIGH;
- 
- 	/* the "gadget" abstracts/virtualizes the controller */
- 	dev_set_name(&dev->gadget.dev, "gadget");
-diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
-index 788989a..8da1492 100644
---- a/drivers/usb/gadget/omap_udc.c
-+++ b/drivers/usb/gadget/omap_udc.c
-@@ -2110,7 +2110,7 @@ static int omap_udc_start(struct usb_gadget_driver *driver,
- 		return -ENODEV;
- 	if (!driver
- 			// FIXME if otg, check:  driver->is_otg
--			|| driver->speed < USB_SPEED_FULL
-+			|| driver->max_speed < USB_SPEED_FULL
- 			|| !bind || !driver->setup)
- 		return -EINVAL;
- 
-@@ -2676,6 +2676,7 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
- 	INIT_LIST_HEAD(&udc->gadget.ep_list);
- 	INIT_LIST_HEAD(&udc->iso);
- 	udc->gadget.speed = USB_SPEED_UNKNOWN;
-+	udc->gadget.max_speed = USB_SPEED_FULL;
- 	udc->gadget.name = driver_name;
- 
- 	device_initialize(&udc->gadget.dev);
-@@ -2794,6 +2795,7 @@ static int __init omap_udc_probe(struct platform_device *pdev)
- 	struct omap_usb_config	*config = pdev->dev.platform_data;
- 	struct clk		*dc_clk;
- 	struct clk		*hhc_clk;
-+	u8			pdev_id;
- 
- 	/* NOTE:  "knows" the order of the resources! */
- 	if (!request_mem_region(pdev->resource[0].start,
-@@ -2862,7 +2864,8 @@ static int __init omap_udc_probe(struct platform_device *pdev)
- 		 * use it.  Except for OTG, we don't _need_ to talk to one;
- 		 * but not having one probably means no VBUS detection.
- 		 */
--		xceiv = otg_get_transceiver();
-+		pdev_id = (pdev->id >= 0) ? pdev->id : 0;
-+		xceiv = otg_get_transceiver(pdev_id);
- 		if (xceiv)
- 			type = xceiv->label;
- 		else if (config->otg) {
-diff --git a/drivers/usb/gadget/pch_udc.c b/drivers/usb/gadget/pch_udc.c
-index e7fb1a3..870897ac 100644
---- a/drivers/usb/gadget/pch_udc.c
-+++ b/drivers/usb/gadget/pch_udc.c
-@@ -2768,7 +2768,7 @@ static int pch_udc_start(struct usb_gadget_driver *driver,
- 	struct pch_udc_dev	*dev = pch_udc;
- 	int			retval;
- 
--	if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind ||
-+	if (!driver || (driver->max_speed == USB_SPEED_UNKNOWN) || !bind ||
- 	    !driver->setup || !driver->unbind || !driver->disconnect) {
- 		dev_err(&dev->pdev->dev,
- 			"%s: invalid driver parameter\n", __func__);
-@@ -3018,7 +3018,7 @@ static int pch_udc_probe(struct pci_dev *pdev,
- 	dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
- 	dev->gadget.dev.release = gadget_release;
- 	dev->gadget.name = KBUILD_MODNAME;
--	dev->gadget.is_dualspeed = 1;
-+	dev->gadget.max_speed = USB_SPEED_HIGH;
- 
- 	retval = device_register(&dev->gadget.dev);
- 	if (retval)
-diff --git a/drivers/usb/gadget/printer.c b/drivers/usb/gadget/printer.c
-index 65a8834..d83134b 100644
---- a/drivers/usb/gadget/printer.c
-+++ b/drivers/usb/gadget/printer.c
-@@ -1141,7 +1141,7 @@ printer_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
- 				break;
- #ifdef CONFIG_USB_GADGET_DUALSPEED
- 			case USB_DT_DEVICE_QUALIFIER:
--				if (!gadget->is_dualspeed)
-+				if (!gadget_is_dualspeed(gadget))
- 					break;
- 				/*
- 				 * assumes ep0 uses the same value for both
-@@ -1155,7 +1155,7 @@ printer_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
- 				break;
- 
- 			case USB_DT_OTHER_SPEED_CONFIG:
--				if (!gadget->is_dualspeed)
-+				if (!gadget_is_dualspeed(gadget))
- 					break;
- 				/* FALLTHROUGH */
- #endif /* CONFIG_USB_GADGET_DUALSPEED */
-@@ -1535,7 +1535,7 @@ fail:
- /*-------------------------------------------------------------------------*/
- 
- static struct usb_gadget_driver printer_driver = {
--	.speed		= DEVSPEED,
-+	.max_speed	= DEVSPEED,
- 
- 	.function	= (char *) driver_desc,
- 	.unbind		= printer_unbind,
-diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c
-index c090a7e..dd47063 100644
---- a/drivers/usb/gadget/pxa25x_udc.c
-+++ b/drivers/usb/gadget/pxa25x_udc.c
-@@ -1264,7 +1264,7 @@ static int pxa25x_start(struct usb_gadget_driver *driver,
- 	int			retval;
- 
- 	if (!driver
--			|| driver->speed < USB_SPEED_FULL
-+			|| driver->max_speed < USB_SPEED_FULL
- 			|| !bind
- 			|| !driver->disconnect
- 			|| !driver->setup)
-diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
-index 18b6b09..f4c44eb 100644
---- a/drivers/usb/gadget/pxa27x_udc.c
-+++ b/drivers/usb/gadget/pxa27x_udc.c
-@@ -1807,7 +1807,7 @@ static int pxa27x_udc_start(struct usb_gadget_driver *driver,
- 	struct pxa_udc *udc = the_controller;
- 	int retval;
- 
--	if (!driver || driver->speed < USB_SPEED_FULL || !bind
-+	if (!driver || driver->max_speed < USB_SPEED_FULL || !bind
- 			|| !driver->disconnect || !driver->setup)
- 		return -EINVAL;
- 	if (!udc)
-diff --git a/drivers/usb/gadget/r8a66597-udc.c b/drivers/usb/gadget/r8a66597-udc.c
-index fc719a3..f5b8d21 100644
---- a/drivers/usb/gadget/r8a66597-udc.c
-+++ b/drivers/usb/gadget/r8a66597-udc.c
-@@ -1746,7 +1746,7 @@ static int r8a66597_start(struct usb_gadget *gadget,
- 	struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
- 
- 	if (!driver
--			|| driver->speed < USB_SPEED_HIGH
-+			|| driver->max_speed < USB_SPEED_HIGH
- 			|| !driver->setup)
- 		return -EINVAL;
- 	if (!r8a66597)
-@@ -1911,7 +1911,7 @@ static int __init r8a66597_probe(struct platform_device *pdev)
- 
- 	r8a66597->gadget.ops = &r8a66597_gadget_ops;
- 	dev_set_name(&r8a66597->gadget.dev, "gadget");
--	r8a66597->gadget.is_dualspeed = 1;
-+	r8a66597->gadget.max_speed = USB_SPEED_HIGH;
- 	r8a66597->gadget.dev.parent = &pdev->dev;
- 	r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
- 	r8a66597->gadget.dev.release = pdev->dev.release;
-diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c
-index d3cdffe..208e574 100644
---- a/drivers/usb/gadget/rndis.c
-+++ b/drivers/usb/gadget/rndis.c
-@@ -314,7 +314,8 @@ static int gen_ndis_query_resp(int configNr, u32 OID, u8 *buf,
- 	/* mandatory */
- 	case OID_GEN_CURRENT_PACKET_FILTER:
- 		pr_debug("%s: OID_GEN_CURRENT_PACKET_FILTER\n", __func__);
--		*outbuf = cpu_to_le32(*rndis_per_dev_params[configNr].filter);
-+		*outbuf =
-+		cpu_to_le32(*(u16 *)rndis_per_dev_params[configNr].filter);
- 		retval = 0;
- 		break;
- 
-@@ -336,7 +337,7 @@ static int gen_ndis_query_resp(int configNr, u32 OID, u8 *buf,
- 
- 	case OID_GEN_PHYSICAL_MEDIUM:
- 		pr_debug("%s: OID_GEN_PHYSICAL_MEDIUM\n", __func__);
--		*outbuf = cpu_to_le32(0);
-+		*outbuf = __constant_cpu_to_le32(2);
- 		retval = 0;
- 		break;
- 
-@@ -413,7 +414,7 @@ static int gen_ndis_query_resp(int configNr, u32 OID, u8 *buf,
- 		if (rndis_per_dev_params[configNr].dev) {
- 			length = ETH_ALEN;
- 			memcpy(outbuf,
--				rndis_per_dev_params[configNr].host_mac,
-+				rndis_per_dev_params[configNr].perm_mac,
- 				length);
- 			retval = 0;
- 		}
-@@ -443,7 +444,7 @@ static int gen_ndis_query_resp(int configNr, u32 OID, u8 *buf,
- 	case OID_802_3_MAXIMUM_LIST_SIZE:
- 		pr_debug("%s: OID_802_3_MAXIMUM_LIST_SIZE\n", __func__);
- 		/* Multicast base address only */
--		*outbuf = cpu_to_le32(1);
-+		*outbuf = __constant_cpu_to_le32(32);
- 		retval = 0;
- 		break;
- 
-@@ -549,6 +550,10 @@ static int gen_ndis_set_resp(u8 configNr, u32 OID, u8 *buf, u32 buf_len,
- 	case OID_802_3_MULTICAST_LIST:
- 		/* I think we can ignore this */
- 		pr_debug("%s: OID_802_3_MULTICAST_LIST\n", __func__);
-+		memset(rndis_per_dev_params[configNr].mcast_addr, 0,
-+			RNDIS_MAX_MULTICAST_SIZE * 6);
-+		memcpy(rndis_per_dev_params[configNr].mcast_addr,
-+			buf, buf_len);
- 		retval = 0;
- 		break;
- 
-@@ -578,6 +583,9 @@ static int rndis_init_response(int configNr, rndis_init_msg_type *buf)
- 		return -ENOMEM;
- 	resp = (rndis_init_cmplt_type *)r->buf;
- 
-+	if (!resp)
-+		return -ENOMEM;
-+
- 	resp->MessageType = cpu_to_le32(REMOTE_NDIS_INITIALIZE_CMPLT);
- 	resp->MessageLength = cpu_to_le32(52);
- 	resp->RequestID = buf->RequestID; /* Still LE in msg buffer */
-@@ -788,7 +796,8 @@ void rndis_uninit(int configNr)
- 
- void rndis_set_host_mac(int configNr, const u8 *addr)
- {
--	rndis_per_dev_params[configNr].host_mac = addr;
-+	rndis_per_dev_params[configNr].host_mac = (u8 *)addr;
-+	memcpy((void *)rndis_per_dev_params[configNr].perm_mac, addr, 6);
- }
- 
- /*
-@@ -830,6 +839,8 @@ int rndis_msg_parser(u8 configNr, u8 *buf)
- 			__func__);
- 		params->state = RNDIS_UNINITIALIZED;
- 		if (params->dev) {
-+			memcpy((void *)rndis_per_dev_params[configNr].host_mac,
-+			(void *)rndis_per_dev_params[configNr].perm_mac, 6);
- 			netif_carrier_off(params->dev);
- 			netif_stop_queue(params->dev);
- 		}
-diff --git a/drivers/usb/gadget/rndis.h b/drivers/usb/gadget/rndis.h
-index 907c330..026da39 100644
---- a/drivers/usb/gadget/rndis.h
-+++ b/drivers/usb/gadget/rndis.h
-@@ -18,7 +18,8 @@
- #include "ndis.h"
- 
- #define RNDIS_MAXIMUM_FRAME_SIZE	1518
--#define RNDIS_MAX_TOTAL_SIZE		1558
-+#define RNDIS_MAX_TOTAL_SIZE		1514
-+#define RNDIS_MAX_MULTICAST_SIZE        32
- 
- /* Remote NDIS Versions */
- #define RNDIS_MAJOR_VERSION		1
-@@ -230,7 +231,8 @@ typedef struct rndis_params
- 	u32			speed;
- 	u32			media_state;
- 
--	const u8		*host_mac;
-+	u8                      perm_mac[6];
-+	u8                      *host_mac;
- 	u16			*filter;
- 	struct net_device	*dev;
- 
-@@ -239,6 +241,7 @@ typedef struct rndis_params
- 	void			(*resp_avail)(void *v);
- 	void			*v;
- 	struct list_head	resp_queue;
-+	u8			mcast_addr[RNDIS_MAX_MULTICAST_SIZE][6];
- } rndis_params;
- 
- /* RNDIS Message parser and other useless functions */
-diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
-index b314482..d098c36 100644
---- a/drivers/usb/gadget/s3c-hsotg.c
-+++ b/drivers/usb/gadget/s3c-hsotg.c
-@@ -2586,7 +2586,7 @@ static int s3c_hsotg_start(struct usb_gadget_driver *driver,
- 		return -EINVAL;
- 	}
- 
--	if (driver->speed < USB_SPEED_FULL)
-+	if (driver->max_speed < USB_SPEED_FULL)
- 		dev_err(hsotg->dev, "%s: bad speed\n", __func__);
- 
- 	if (!bind || !driver->setup) {
-@@ -3362,7 +3362,7 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
- 
- 	dev_set_name(&hsotg->gadget.dev, "gadget");
- 
--	hsotg->gadget.is_dualspeed = 1;
-+	hsotg->gadget.max_speed = USB_SPEED_HIGH;
- 	hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
- 	hsotg->gadget.name = dev_name(dev);
- 
-diff --git a/drivers/usb/gadget/s3c-hsudc.c b/drivers/usb/gadget/s3c-hsudc.c
-index 20a553b..f398b85 100644
---- a/drivers/usb/gadget/s3c-hsudc.c
-+++ b/drivers/usb/gadget/s3c-hsudc.c
-@@ -1142,7 +1142,7 @@ static int s3c_hsudc_start(struct usb_gadget_driver *driver,
- 	int ret;
- 
- 	if (!driver
--		|| driver->speed < USB_SPEED_FULL
-+		|| driver->max_speed < USB_SPEED_FULL
- 		|| !bind
- 		|| !driver->unbind || !driver->disconnect || !driver->setup)
- 		return -EINVAL;
-@@ -1310,7 +1310,7 @@ static int s3c_hsudc_probe(struct platform_device *pdev)
- 	device_initialize(&hsudc->gadget.dev);
- 	dev_set_name(&hsudc->gadget.dev, "gadget");
- 
--	hsudc->gadget.is_dualspeed = 1;
-+	hsudc->gadget.max_speed = USB_SPEED_HIGH;
- 	hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
- 	hsudc->gadget.name = dev_name(dev);
- 	hsudc->gadget.dev.parent = dev;
-diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c
-index b864377..4d860e9 100644
---- a/drivers/usb/gadget/s3c2410_udc.c
-+++ b/drivers/usb/gadget/s3c2410_udc.c
-@@ -1683,9 +1683,9 @@ static int s3c2410_udc_start(struct usb_gadget_driver *driver,
- 	if (udc->driver)
- 		return -EBUSY;
- 
--	if (!bind || !driver->setup || driver->speed < USB_SPEED_FULL) {
-+	if (!bind || !driver->setup || driver->max_speed < USB_SPEED_FULL) {
- 		printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
--			bind, driver->setup, driver->speed);
-+			bind, driver->setup, driver->max_speed);
- 		return -EINVAL;
- 	}
- #if defined(MODULE)
-diff --git a/drivers/usb/gadget/udc-core.c b/drivers/usb/gadget/udc-core.c
-index 6939e17..0b0d12c 100644
---- a/drivers/usb/gadget/udc-core.c
-+++ b/drivers/usb/gadget/udc-core.c
-@@ -371,14 +371,28 @@ static ssize_t usb_udc_softconn_store(struct device *dev,
- }
- static DEVICE_ATTR(soft_connect, S_IWUSR, NULL, usb_udc_softconn_store);
- 
--static ssize_t usb_udc_speed_show(struct device *dev,
-+#define USB_UDC_SPEED_ATTR(name, param)					\
-+ssize_t usb_udc_##param##_show(struct device *dev,			\
-+		struct device_attribute *attr, char *buf)		\
-+{									\
-+	struct usb_udc *udc = container_of(dev, struct usb_udc, dev);	\
-+	return snprintf(buf, PAGE_SIZE, "%s\n",				\
-+			usb_speed_string(udc->gadget->param));		\
-+}									\
-+static DEVICE_ATTR(name, S_IRUSR, usb_udc_##param##_show, NULL)
-+
-+static USB_UDC_SPEED_ATTR(current_speed, speed);
-+static USB_UDC_SPEED_ATTR(maximum_speed, max_speed);
-+
-+/* TODO: Scheduled for removal in 3.8. */
-+static ssize_t usb_udc_is_dualspeed_show(struct device *dev,
- 		struct device_attribute *attr, char *buf)
- {
- 	struct usb_udc		*udc = container_of(dev, struct usb_udc, dev);
--	return snprintf(buf, PAGE_SIZE, "%s\n",
--			usb_speed_string(udc->gadget->speed));
-+	return snprintf(buf, PAGE_SIZE, "%d\n",
-+			gadget_is_dualspeed(udc->gadget));
- }
--static DEVICE_ATTR(speed, S_IRUGO, usb_udc_speed_show, NULL);
-+static DEVICE_ATTR(is_dualspeed, S_IRUSR, usb_udc_is_dualspeed_show, NULL);
- 
- #define USB_UDC_ATTR(name)					\
- ssize_t usb_udc_##name##_show(struct device *dev,		\
-@@ -391,7 +405,6 @@ ssize_t usb_udc_##name##_show(struct device *dev,		\
- }								\
- static DEVICE_ATTR(name, S_IRUGO, usb_udc_##name##_show, NULL)
- 
--static USB_UDC_ATTR(is_dualspeed);
- static USB_UDC_ATTR(is_otg);
- static USB_UDC_ATTR(is_a_peripheral);
- static USB_UDC_ATTR(b_hnp_enable);
-@@ -401,7 +414,8 @@ static USB_UDC_ATTR(a_alt_hnp_support);
- static struct attribute *usb_udc_attrs[] = {
- 	&dev_attr_srp.attr,
- 	&dev_attr_soft_connect.attr,
--	&dev_attr_speed.attr,
-+	&dev_attr_current_speed.attr,
-+	&dev_attr_maximum_speed.attr,
- 
- 	&dev_attr_is_dualspeed.attr,
- 	&dev_attr_is_otg.attr,
-diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
-index e39b029..568cefb 100644
---- a/drivers/usb/host/ehci-omap.c
-+++ b/drivers/usb/host/ehci-omap.c
-@@ -41,6 +41,7 @@
- #include <linux/usb/ulpi.h>
- #include <plat/usb.h>
- #include <linux/regulator/consumer.h>
-+#include <linux/pm_runtime.h>
- 
- /* EHCI Register Set */
- #define EHCI_INSNREG04					(0xA0)
-@@ -190,11 +191,8 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev)
- 		}
- 	}
- 
--	ret = omap_usbhs_enable(dev);
--	if (ret) {
--		dev_err(dev, "failed to start usbhs with err %d\n", ret);
--		goto err_enable;
--	}
-+	pm_runtime_enable(dev);
-+	pm_runtime_get_sync(dev);
- 
- 	/*
- 	 * An undocumented "feature" in the OMAP3 EHCI controller,
-@@ -240,11 +238,8 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev)
- 	return 0;
- 
- err_add_hcd:
--	omap_usbhs_disable(dev);
--
--err_enable:
- 	disable_put_regulator(pdata);
--	usb_put_hcd(hcd);
-+	pm_runtime_put_sync(dev);
- 
- err_io:
- 	iounmap(regs);
-@@ -266,10 +261,12 @@ static int ehci_hcd_omap_remove(struct platform_device *pdev)
- 	struct usb_hcd *hcd	= dev_get_drvdata(dev);
- 
- 	usb_remove_hcd(hcd);
--	omap_usbhs_disable(dev);
- 	disable_put_regulator(dev->platform_data);
- 	iounmap(hcd->regs);
- 	usb_put_hcd(hcd);
-+	pm_runtime_put_sync(dev);
-+	pm_runtime_disable(dev);
-+
- 	return 0;
- }
- 
-diff --git a/drivers/usb/host/ohci-omap3.c b/drivers/usb/host/ohci-omap3.c
-index 516ebc4..1b8133b 100644
---- a/drivers/usb/host/ohci-omap3.c
-+++ b/drivers/usb/host/ohci-omap3.c
-@@ -31,6 +31,7 @@
- 
- #include <linux/platform_device.h>
- #include <plat/usb.h>
-+#include <linux/pm_runtime.h>
- 
- /*-------------------------------------------------------------------------*/
- 
-@@ -134,7 +135,7 @@ static int __devinit ohci_hcd_omap3_probe(struct platform_device *pdev)
- 	int			irq;
- 
- 	if (usb_disabled())
--		goto err_end;
-+		return -ENODEV;
- 
- 	if (!dev->parent) {
- 		dev_err(dev, "Missing parent device\n");
-@@ -172,11 +173,8 @@ static int __devinit ohci_hcd_omap3_probe(struct platform_device *pdev)
- 	hcd->rsrc_len = resource_size(res);
- 	hcd->regs =  regs;
- 
--	ret = omap_usbhs_enable(dev);
--	if (ret) {
--		dev_dbg(dev, "failed to start ohci\n");
--		goto err_end;
--	}
-+	pm_runtime_enable(dev);
-+	pm_runtime_get_sync(dev);
- 
- 	ohci_hcd_init(hcd_to_ohci(hcd));
- 
-@@ -189,9 +187,7 @@ static int __devinit ohci_hcd_omap3_probe(struct platform_device *pdev)
- 	return 0;
- 
- err_add_hcd:
--	omap_usbhs_disable(dev);
--
--err_end:
-+	pm_runtime_put_sync(dev);
- 	usb_put_hcd(hcd);
- 
- err_io:
-@@ -220,9 +216,9 @@ static int __devexit ohci_hcd_omap3_remove(struct platform_device *pdev)
- 
- 	iounmap(hcd->regs);
- 	usb_remove_hcd(hcd);
--	omap_usbhs_disable(dev);
-+	pm_runtime_put_sync(dev);
-+	pm_runtime_disable(dev);
- 	usb_put_hcd(hcd);
--
- 	return 0;
- }
- 
-diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
-index 07a0346..79f09f5 100644
---- a/drivers/usb/musb/Kconfig
-+++ b/drivers/usb/musb/Kconfig
-@@ -5,14 +5,14 @@
- 
- # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
- config USB_MUSB_HDRC
-+	tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
- 	depends on USB && USB_GADGET
--	depends on (ARM || (BF54x && !BF544) || (BF52x && !BF522 && !BF523))
- 	select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN)
-+	select NOP_USB_XCEIV if (SOC_OMAPTI81XX || SOC_OMAPAM33XX)
- 	select TWL4030_USB if MACH_OMAP_3430SDP
- 	select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA
- 	select USB_OTG_UTILS
- 	select USB_GADGET_DUALSPEED
--	tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
- 	help
- 	  Say Y here if your system has a dual role high speed USB
- 	  controller based on the Mentor Graphics silicon IP.  Then
-@@ -31,80 +31,160 @@ config USB_MUSB_HDRC
- 	  To compile this driver as a module, choose M here; the
- 	  module will be called "musb-hdrc".
- 
--choice
--	prompt "Platform Glue Layer"
--	depends on USB_MUSB_HDRC
-+if USB_MUSB_HDRC
- 
--config USB_MUSB_DAVINCI
-+comment "Platform Glue Layer"
-+
-+config USB_MUSB_DAVINCI_GLUE
-+	select USB_MUSB_DAVINCI
- 	tristate "DaVinci"
--	depends on ARCH_DAVINCI_DMx
-+	depends on ARCH_DAVINCI_DMx && USB_MUSB_HDRC
- 
--config USB_MUSB_DA8XX
-+config USB_MUSB_DA8XX_GLUE
-+	select USB_MUSB_DA8XX
- 	tristate "DA8xx/OMAP-L1x"
--	depends on ARCH_DAVINCI_DA8XX
-+	depends on ARCH_DAVINCI_DA8XX && USB_MUSB_HDRC
- 
--config USB_MUSB_TUSB6010
-+config USB_MUSB_TUSB6010_GLUE
-+	select USB_MUSB_TUSB6010
- 	tristate "TUSB6010"
--	depends on ARCH_OMAP
-+	depends on ARCH_OMAP && USB_MUSB_HDRC
- 
--config USB_MUSB_OMAP2PLUS
-+config USB_MUSB_OMAP2PLUS_GLUE
-+	select USB_MUSB_OMAP2PLUS
- 	tristate "OMAP2430 and onwards"
--	depends on ARCH_OMAP2PLUS
-+	depends on ARCH_OMAP2PLUS && USB_MUSB_HDRC
- 
--config USB_MUSB_AM35X
-+config USB_MUSB_AM35X_GLUE
-+	select USB_MUSB_AM35X
- 	tristate "AM35x"
--	depends on ARCH_OMAP
-+	depends on ARCH_OMAP && USB_MUSB_HDRC
- 
--config USB_MUSB_BLACKFIN
-+config USB_MUSB_TI81XX_GLUE
-+	select USB_MUSB_TI81XX
-+	tristate "TI81XX onward"
-+	depends on (SOC_OMAPTI81XX || SOC_OMAPAM33XX) && USB_MUSB_HDRC
-+
-+config USB_MUSB_BLACKFIN_GLUE
-+	select USB_MUSB_BLACKFIN
- 	tristate "Blackfin"
--	depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
-+	depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523) && USB_MUSB_HDRC
- 
--config USB_MUSB_UX500
-+config USB_MUSB_UX500_GLUE
-+	select USB_MUSB_UX500
- 	tristate "U8500 and U5500"
--	depends on (ARCH_U8500 && AB8500_USB)
-+	depends on (ARCH_U8500 && AB8500_USB) && USB_MUSB_HDRC
-+
-+config USB_MUSB_DAVINCI
-+	bool
-+	default n
-+config USB_MUSB_DA8XX
-+	bool
-+	default n
-+config USB_MUSB_TUSB6010
-+	bool
-+	default n
-+config USB_MUSB_OMAP2PLUS
-+	bool
-+	default n
-+config USB_MUSB_AM35X
-+	bool
-+	default n
-+config USB_MUSB_TI81XX
-+	bool
-+	default n
-+config USB_MUSB_BLACKFIN
-+	bool
-+	default n
-+config USB_MUSB_UX500
-+	bool
-+	default n
-+
-+choice
-+	prompt 'MUSB DMA mode'
-+	depends on !MUSB_PIO_ONLY
-+	default USB_UX500_DMA_HW if USB_MUSB_UX500
-+	default USB_INVENTRA_DMA_HW if USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
-+	default USB_TI_CPPI_DMA_HW if USB_MUSB_DAVINCI
-+	default USB_TUSB_OMAP_DMA_HW if USB_MUSB_TUSB6010
-+	default USB_TI_CPPI41_DMA_HW if USB_MUSB_DA8XX || USB_MUSB_AM35X || USB_MUSB_TI81XX
-+	help
-+	  Unfortunately, only one option can be enabled here. Ideally one
-+	  should be able to build all these drivers into one kernel to
-+	  allow using DMA on multiplatform kernels.
-+
-+config USB_UX500_DMA_HW
-+	tristate 'ST Ericsson U8500 and U5500'
-+	select USB_UX500_DMA
-+	depends on USB_MUSB_UX500
-+	help
-+	  Enable DMA transfers on UX500 platforms.
-+
-+config USB_INVENTRA_DMA_HW
-+	tristate 'Inventra'
-+	select USB_INVENTRA_DMA
-+	depends on (USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN) && !USB_MUSB_AM35X
-+	help
-+	  Enable DMA transfers using Mentor's engine.
-+
-+config USB_TI_CPPI_DMA_HW
-+	tristate 'TI CPPI (Davinci)'
-+	select USB_TI_CPPI_DMA
-+	depends on USB_MUSB_DAVINCI
-+	help
-+	  Enable DMA transfers when TI CPPI DMA is available.
-+
-+config USB_TI_CPPI41_DMA_HW
-+	tristate 'TI CPPI4.1'
-+	select USB_TI_CPPI41_DMA
-+	depends on USB_MUSB_DA8XX || USB_MUSB_AM35X || USB_MUSB_TI81XX
-+	select CPPI41
-+	help
-+	 Configure this option to include the CPPI 4.1 support,
-+	 The CPPI 4.1 DMA engine integrated with musb controller
-+	 accelarate the usb packet transmission and receception
-+	 to/from musb endpoints.
-+
-+config USB_TUSB_OMAP_DMA_HW
-+	tristate 'TUSB 6010'
-+	select USB_TUSB_OMAP_DMA
-+	depends on USB_MUSB_TUSB6010
-+	depends on ARCH_OMAP
-+	help
-+	  Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
- 
- endchoice
- 
- config MUSB_PIO_ONLY
- 	bool 'Disable DMA (always use PIO)'
--	depends on USB_MUSB_HDRC
--	default USB_MUSB_TUSB6010 || USB_MUSB_DA8XX || USB_MUSB_AM35X
-+	default USB_MUSB_TUSB6010 || USB_MUSB_DA8XX
- 	help
- 	  All data is copied between memory and FIFO by the CPU.
- 	  DMA controllers are ignored.
- 
--	  Do not select 'n' here unless DMA support for your SOC or board
-+	  Do not choose this unless DMA support for your SOC or board
- 	  is unavailable (or unstable).  When DMA is enabled at compile time,
- 	  you can still disable it at run time using the "use_dma=n" module
- 	  parameter.
- 
--config USB_UX500_DMA
--	bool
--	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
--	default USB_MUSB_UX500
--	help
--	  Enable DMA transfers on UX500 platforms.
--
- config USB_INVENTRA_DMA
- 	bool
--	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
--	default USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
--	help
--	  Enable DMA transfers using Mentor's engine.
-+	default n
- 
- config USB_TI_CPPI_DMA
- 	bool
--	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
--	default USB_MUSB_DAVINCI
--	help
--	  Enable DMA transfers when TI CPPI DMA is available.
-+	default n
-+
-+config USB_TI_CPPI41_DMA
-+	bool
-+	default n
- 
- config USB_TUSB_OMAP_DMA
- 	bool
--	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
--	depends on USB_MUSB_TUSB6010
--	depends on ARCH_OMAP
--	default y
--	help
--	  Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
-+	default n
-+
-+config USB_UX500_DMA
-+	bool
-+	default n
- 
-+endif # USB_MUSB_HDRC
-diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
-index d8fd9d0..da5421b 100644
---- a/drivers/usb/musb/Makefile
-+++ b/drivers/usb/musb/Makefile
-@@ -9,40 +9,25 @@ musb_hdrc-y := musb_core.o
- musb_hdrc-y					+= musb_gadget_ep0.o musb_gadget.o
- musb_hdrc-y					+= musb_virthub.o musb_host.o
- musb_hdrc-$(CONFIG_DEBUG_FS)			+= musb_debugfs.o
--
-+musb_hdrc-$(CONFIG_PROC_FS)			+= musb_procfs.o
- # Hardware Glue Layer
--obj-$(CONFIG_USB_MUSB_OMAP2PLUS)		+= omap2430.o
--obj-$(CONFIG_USB_MUSB_AM35X)			+= am35x.o
--obj-$(CONFIG_USB_MUSB_TUSB6010)			+= tusb6010.o
--obj-$(CONFIG_USB_MUSB_DAVINCI)			+= davinci.o
--obj-$(CONFIG_USB_MUSB_DA8XX)			+= da8xx.o
--obj-$(CONFIG_USB_MUSB_BLACKFIN)			+= blackfin.o
--obj-$(CONFIG_USB_MUSB_UX500)			+= ux500.o
-+obj-$(CONFIG_USB_MUSB_OMAP2PLUS_GLUE)		+= omap2430.o
-+obj-$(CONFIG_USB_MUSB_AM35X_GLUE)		+= am35x.o
-+obj-$(CONFIG_USB_MUSB_TI81XX_GLUE)		+= ti81xx.o
-+obj-$(CONFIG_USB_MUSB_TUSB6010_GLUE)		+= tusb6010.o
-+obj-$(CONFIG_USB_MUSB_DAVINCI_GLUE)			+= davinci.o
-+obj-$(CONFIG_USB_MUSB_DA8XX_GLUE)			+= da8xx.o
-+obj-$(CONFIG_USB_MUSB_BLACKFIN_GLUE)		+= blackfin.o
-+obj-$(CONFIG_USB_MUSB_UX500_GLUE)			+= ux500.o
- 
- # the kconfig must guarantee that only one of the
- # possible I/O schemes will be enabled at a time ...
- # PIO only, or DMA (several potential schemes).
- # though PIO is always there to back up DMA, and for ep0
- 
--ifneq ($(CONFIG_MUSB_PIO_ONLY),y)
--
--  ifeq ($(CONFIG_USB_INVENTRA_DMA),y)
--    musb_hdrc-y			+= musbhsdma.o
--
--  else
--    ifeq ($(CONFIG_USB_TI_CPPI_DMA),y)
--      musb_hdrc-y		+= cppi_dma.o
--
--    else
--      ifeq ($(CONFIG_USB_TUSB_OMAP_DMA),y)
--	musb_hdrc-y		+= tusb6010_omap.o
--
--      else
--        ifeq ($(CONFIG_USB_UX500_DMA),y)
--	  musb_hdrc-y		+= ux500_dma.o
--
--        endif
--      endif
--    endif
--  endif
--endif
-+obj-$(CONFIG_USB_INVENTRA_DMA_HW)		+= musbhsdma.o
-+obj-$(CONFIG_USB_TI_CPPI_DMA_HW)		+= cppi_dma.o
-+obj-$(CONFIG_USB_TI_CPPI41_DMA_HW)		+= cppi41dma.o
-+cppi41dma-y					+= cppi41.o cppi41_dma.o
-+obj-$(CONFIG_USB_TUSB_OMAP_DMA_HW)		+= tusb6010_omap.o
-+obj-$(CONFIG_USB_UX500_DMA_HW)			+= ux500_dma.o
-diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
-index e233d2b..1e81fe8 100644
---- a/drivers/usb/musb/am35x.c
-+++ b/drivers/usb/musb/am35x.c
-@@ -36,6 +36,8 @@
- #include <plat/usb.h>
- 
- #include "musb_core.h"
-+#include "cppi41.h"
-+#include "cppi41_dma.h"
- 
- /*
-  * AM35x specific definitions
-@@ -46,9 +48,7 @@
- #define USB_STAT_REG		0x08
- #define USB_EMULATION_REG	0x0c
- /* 0x10 Reserved */
--#define USB_AUTOREQ_REG		0x14
- #define USB_SRP_FIX_TIME_REG	0x18
--#define USB_TEARDOWN_REG	0x1c
- #define EP_INTR_SRC_REG		0x20
- #define EP_INTR_SRC_SET_REG	0x24
- #define EP_INTR_SRC_CLEAR_REG	0x28
-@@ -80,8 +80,196 @@
- #define AM35X_TX_INTR_MASK	(AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
- #define AM35X_RX_INTR_MASK	(AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
- 
-+/* CPPI 4.1 queue manager registers */
-+#define QMGR_PEND0_REG		0x4090
-+#define QMGR_PEND1_REG		0x4094
-+#define QMGR_PEND2_REG		0x4098
-+
- #define USB_MENTOR_CORE_OFFSET	0x400
- 
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+#define CPPI41_QMGR_REG0SIZE	0x3fff
-+
-+/*
-+ * CPPI 4.1 resources used for USB OTG controller module:
-+ *
-+ * USB   DMA  DMA  QMgr  Tx     Src
-+ *       Tx   Rx         QNum   Port
-+ * ---------------------------------
-+ * EP0   0    0    0     16,17  1
-+ * ---------------------------------
-+ * EP1   1    1    0     18,19  2
-+ * ---------------------------------
-+ * EP2   2    2    0     20,21  3
-+ * ---------------------------------
-+ * EP3   3    3    0     22,23  4
-+ * ---------------------------------
-+ */
-+
-+static u16 tx_comp_q[] = {63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63,
-+				63, 63};
-+static u16 rx_comp_q[] = {65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
-+				65, 65};
-+
-+/* Fair scheduling */
-+u32 dma_sched_table[] = {
-+	0x81018000, 0x83038202, 0x85058404, 0x87078606,
-+	0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x00008e0e
-+};
-+
-+/* DMA block configuration */
-+static const struct cppi41_tx_ch tx_ch_info[] = {
-+	[0] = {
-+		.port_num	= 1,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 32} , {0, 33} }
-+	},
-+	[1] = {
-+		.port_num	= 2,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 34} , {0, 35} }
-+	},
-+	[2] = {
-+		.port_num	= 3,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 36} , {0, 37} }
-+	},
-+	[3] = {
-+		.port_num	= 4,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 38} , {0, 39} }
-+	},
-+	[4] = {
-+		.port_num	= 5,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 40} , {0, 41} }
-+	},
-+	[5] = {
-+		.port_num	= 6,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 42} , {0, 43} }
-+	},
-+	[6] = {
-+		.port_num	= 7,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 44} , {0, 45} }
-+	},
-+	[7] = {
-+		.port_num	= 8,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 46} , {0, 47} }
-+	},
-+	[8] = {
-+		.port_num	= 9,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 48} , {0, 49} }
-+	},
-+	[9] = {
-+		.port_num	= 10,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 50} , {0, 51} }
-+	},
-+	[10] = {
-+		.port_num	= 11,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 52} , {0, 53} }
-+	},
-+	[11] = {
-+		.port_num	= 12,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 54} , {0, 55} }
-+	},
-+	[12] = {
-+		.port_num	= 13,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 56} , {0, 57} }
-+	},
-+	[13] = {
-+		.port_num	= 14,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 58} , {0, 59} }
-+	},
-+	[14] = {
-+		.port_num	= 15,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 60} , {0, 61} }
-+	}
-+};
-+
-+/* Queues 0 to 66 are pre-assigned, others are spare */
-+static const u32 assigned_queues[] = { 0xffffffff, 0xffffffff, 0x7 };
-+
-+int __devinit cppi41_init(struct musb *musb)
-+{
-+	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[musb->id];
-+	u16 numch, blknum, order, i;
-+
-+	/* init cppi info structure  */
-+	cppi_info->dma_block = 0;
-+	for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
-+		cppi_info->ep_dma_ch[i] = i;
-+
-+	cppi_info->q_mgr = 0;
-+	cppi_info->num_tx_comp_q = 15;
-+	cppi_info->num_rx_comp_q = 15;
-+	cppi_info->tx_comp_q = tx_comp_q;
-+	cppi_info->rx_comp_q = rx_comp_q;
-+	cppi_info->bd_intr_ctrl = 0; /* am35x dont support bd interrupt */
-+
-+	blknum = cppi_info->dma_block;
-+
-+	/* Queue manager information */
-+	cppi41_queue_mgr[0].num_queue = 96;
-+	cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
-+						CPPI41_UNASSIGNED_QUEUE;
-+	cppi41_queue_mgr[0].base_fdbq_num = 0;
-+	cppi41_queue_mgr[0].assigned = assigned_queues;
-+
-+	/* init mappings */
-+	cppi41_queue_mgr[0].q_mgr_rgn_base = musb->ctrl_base + 0x4000;
-+	cppi41_queue_mgr[0].desc_mem_rgn_base = musb->ctrl_base + 0x5000;
-+	cppi41_queue_mgr[0].q_mgmt_rgn_base = musb->ctrl_base + 0x6000;
-+	cppi41_queue_mgr[0].q_stat_rgn_base = musb->ctrl_base + 0x6800;
-+
-+	/* init DMA block */
-+	cppi41_dma_block[0].num_tx_ch = 15;
-+	cppi41_dma_block[0].num_rx_ch = 15;
-+	cppi41_dma_block[0].tx_ch_info = tx_ch_info;
-+
-+	cppi41_dma_block[0].global_ctrl_base = musb->ctrl_base + 0x1000;
-+	cppi41_dma_block[0].ch_ctrl_stat_base = musb->ctrl_base + 0x1800;
-+	cppi41_dma_block[0].sched_ctrl_base = musb->ctrl_base + 0x2000;
-+	cppi41_dma_block[0].sched_table_base = musb->ctrl_base + 0x2800;
-+
-+	/* Initialize for Linking RAM region 0 alone */
-+	cppi41_queue_mgr_init(cppi_info->q_mgr, 0, CPPI41_QMGR_REG0SIZE);
-+
-+	numch =  USB_CPPI41_NUM_CH * 2;
-+	order = get_count_order(numch);
-+
-+	/* TODO: check two teardown desc per channel (5 or 7 ?)*/
-+	if (order < 5)
-+		order = 5;
-+
-+	cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
-+			dma_sched_table, numch);
-+	return 0;
-+}
-+void cppi41_free(void)
-+{
-+	u32 numch, blknum, order;
-+	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
-+
-+	numch =  USB_CPPI41_NUM_CH * 2;
-+	order = get_count_order(numch);
-+	blknum = cppi_info->dma_block;
-+
-+	cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
-+			dma_sched_table, numch);
-+	cppi41_queue_mgr_uninit(cppi_info->q_mgr);
-+}
-+#endif /* CONFIG_USB_TI_CPPI41_DMA */
-+
- struct am35x_glue {
- 	struct device		*dev;
- 	struct platform_device	*musb;
-@@ -228,10 +416,36 @@ static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
- 	struct omap_musb_board_data *data = plat->board_data;
- 	unsigned long flags;
- 	irqreturn_t ret = IRQ_NONE;
-+	u32 pend1 = 0, pend2 = 0, tx, rx;
- 	u32 epintr, usbintr;
- 
- 	spin_lock_irqsave(&musb->lock, flags);
- 
-+	/*
-+	 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
-+	 * don't get reflected in the interrupt source/mask registers.
-+	 */
-+	if (is_cppi41_enabled(musb)) {
-+		/*
-+		 * Check for the interrupts from Tx/Rx completion queues; they
-+		 * are level-triggered and will stay asserted until the queues
-+		 * are emptied.  We're using the queue pending register 0 as a
-+		 * substitute for the interrupt status register and reading it
-+		 * directly for speed.
-+		 */
-+		pend1 = musb_readl(reg_base, QMGR_PEND1_REG);
-+		pend2 = musb_readl(reg_base, QMGR_PEND2_REG);
-+
-+		/* AM3517 uses 63,64,65 and 66 queues as completion queue */
-+		if ((pend1 & (1 << 31)) || (pend2 & (7 << 0))) {
-+			tx = (pend1 >> 31)  | ((pend2 & 1) ? (1 << 1) : 0);
-+			rx = (pend2 >> 1) & 0x3;
-+
-+			dev_dbg(musb->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", tx, rx);
-+			cppi41_completion(musb, rx, tx);
-+			ret = IRQ_HANDLED;
-+		}
-+	}
- 	/* Get endpoint interrupts */
- 	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
- 
-@@ -362,8 +576,8 @@ static int am35x_musb_init(struct musb *musb)
- 	if (!rev)
- 		return -ENODEV;
- 
--	usb_nop_xceiv_register();
--	musb->xceiv = otg_get_transceiver();
-+	usb_nop_xceiv_register(musb->id);
-+	musb->xceiv = otg_get_transceiver(musb->id);
- 	if (!musb->xceiv)
- 		return -ENODEV;
- 
-@@ -379,10 +593,14 @@ static int am35x_musb_init(struct musb *musb)
- 
- 	/* Start the on-chip PHY and its PLL. */
- 	if (data->set_phy_power)
--		data->set_phy_power(1);
-+		data->set_phy_power(0, 1);
- 
- 	msleep(5);
- 
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	cppi41_init(musb);
-+#endif
-+
- 	musb->isr = am35x_musb_interrupt;
- 
- 	/* clear level interrupt */
-@@ -403,16 +621,16 @@ static int am35x_musb_exit(struct musb *musb)
- 
- 	/* Shutdown the on-chip PHY and its PLL. */
- 	if (data->set_phy_power)
--		data->set_phy_power(0);
-+		data->set_phy_power(0, 0);
- 
- 	otg_put_transceiver(musb->xceiv);
--	usb_nop_xceiv_unregister();
-+	usb_nop_xceiv_unregister(musb->id);
- 
- 	return 0;
- }
- 
- /* AM35x supports only 32bit read operation */
--void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
-+static void am35x_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
- {
- 	void __iomem *fifo = hw_ep->fifo;
- 	u32		val;
-@@ -442,6 +660,8 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
- }
- 
- static const struct musb_platform_ops am35x_ops = {
-+	.fifo_mode	= 4,
-+	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
- 	.init		= am35x_musb_init,
- 	.exit		= am35x_musb_exit,
- 
-@@ -452,6 +672,12 @@ static const struct musb_platform_ops am35x_ops = {
- 	.try_idle	= am35x_musb_try_idle,
- 
- 	.set_vbus	= am35x_musb_set_vbus,
-+
-+	.read_fifo  = am35x_musb_read_fifo,
-+	.write_fifo = musb_write_fifo,
-+
-+	.dma_controller_create = cppi41_dma_controller_create,
-+	.dma_controller_destroy = cppi41_dma_controller_destroy,
- };
- 
- static u64 am35x_dmamask = DMA_BIT_MASK(32);
-@@ -473,12 +699,13 @@ static int __init am35x_probe(struct platform_device *pdev)
- 		goto err0;
- 	}
- 
--	musb = platform_device_alloc("musb-hdrc", -1);
-+	musb = platform_device_alloc("musb-hdrc", pdev->id);
- 	if (!musb) {
- 		dev_err(&pdev->dev, "failed to allocate musb device\n");
- 		goto err1;
- 	}
- 
-+	dev_set_name(&pdev->dev, "musb-am35x");
- 	phy_clk = clk_get(&pdev->dev, "fck");
- 	if (IS_ERR(phy_clk)) {
- 		dev_err(&pdev->dev, "failed to get PHY clock\n");
-@@ -566,7 +793,7 @@ static int __exit am35x_remove(struct platform_device *pdev)
- 	struct am35x_glue	*glue = platform_get_drvdata(pdev);
- 
- 	platform_device_del(glue->musb);
--	platform_device_put(glue->musb);
-+	/*platform_device_put(glue->musb);*/
- 	clk_disable(glue->clk);
- 	clk_disable(glue->phy_clk);
- 	clk_put(glue->clk);
-@@ -585,7 +812,7 @@ static int am35x_suspend(struct device *dev)
- 
- 	/* Shutdown the on-chip PHY and its PLL. */
- 	if (data->set_phy_power)
--		data->set_phy_power(0);
-+		data->set_phy_power(0, 0);
- 
- 	clk_disable(glue->phy_clk);
- 	clk_disable(glue->clk);
-@@ -602,7 +829,7 @@ static int am35x_resume(struct device *dev)
- 
- 	/* Start the on-chip PHY and its PLL. */
- 	if (data->set_phy_power)
--		data->set_phy_power(1);
-+		data->set_phy_power(0, 1);
- 
- 	ret = clk_enable(glue->phy_clk);
- 	if (ret) {
-@@ -649,6 +876,9 @@ subsys_initcall(am35x_init);
- 
- static void __exit am35x_exit(void)
- {
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	cppi41_free();
-+#endif
- 	platform_driver_unregister(&am35x_driver);
- }
- module_exit(am35x_exit);
-diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
-index 5e7cfba..241a168 100644
---- a/drivers/usb/musb/blackfin.c
-+++ b/drivers/usb/musb/blackfin.c
-@@ -34,7 +34,8 @@ struct bfin_glue {
- /*
-  * Load an endpoint's FIFO
-  */
--void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
-+static void bfin_musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
-+				const u8 *src)
- {
- 	struct musb *musb = hw_ep->musb;
- 	void __iomem *fifo = hw_ep->fifo;
-@@ -98,7 +99,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
- /*
-  * Unload an endpoint's FIFO
-  */
--void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
-+static void bfin_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
- {
- 	struct musb *musb = hw_ep->musb;
- 	void __iomem *fifo = hw_ep->fifo;
-@@ -414,8 +415,8 @@ static int bfin_musb_init(struct musb *musb)
- 	}
- 	gpio_direction_output(musb->config->gpio_vrsel, 0);
- 
--	usb_nop_xceiv_register();
--	musb->xceiv = otg_get_transceiver();
-+	usb_nop_xceiv_register(musb->id);
-+	musb->xceiv = otg_get_transceiver(musb->id);
- 	if (!musb->xceiv) {
- 		gpio_free(musb->config->gpio_vrsel);
- 		return -ENODEV;
-@@ -441,17 +442,23 @@ static int bfin_musb_exit(struct musb *musb)
- 	gpio_free(musb->config->gpio_vrsel);
- 
- 	otg_put_transceiver(musb->xceiv);
--	usb_nop_xceiv_unregister();
-+	usb_nop_xceiv_unregister(musb->id);
- 	return 0;
- }
- 
- static const struct musb_platform_ops bfin_ops = {
-+	.fifo_mode	= 2,
-+	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING |
-+				MUSB_GLUE_DMA_INVENTRA,
- 	.init		= bfin_musb_init,
- 	.exit		= bfin_musb_exit,
- 
- 	.enable		= bfin_musb_enable,
- 	.disable	= bfin_musb_disable,
- 
-+	.read_fifo      = bfin_musb_read_fifo,
-+	.write_fifo     = bfin_musb_write_fifo,
-+
- 	.set_mode	= bfin_musb_set_mode,
- 	.try_idle	= bfin_musb_try_idle,
- 
-@@ -459,6 +466,9 @@ static const struct musb_platform_ops bfin_ops = {
- 	.set_vbus	= bfin_musb_set_vbus,
- 
- 	.adjust_channel_params = bfin_musb_adjust_channel_params,
-+
-+	.dma_controller_create = inventra_dma_controller_create,
-+	.dma_controller_destroy = inventra_dma_controller_destroy,
- };
- 
- static u64 bfin_dmamask = DMA_BIT_MASK(32);
-diff --git a/drivers/usb/musb/cppi41.c b/drivers/usb/musb/cppi41.c
-new file mode 100644
-index 0000000..7b3c0bd
---- /dev/null
-+++ b/drivers/usb/musb/cppi41.c
-@@ -0,0 +1,1124 @@
-+/*
-+ * CPPI 4.1 support
-+ *
-+ * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
-+ *
-+ * Based on the PAL CPPI 4.1 implementation
-+ * Copyright (C) 1998-2006 Texas Instruments Incorporated
-+ *
-+ * This file contains the main implementation for CPPI 4.1 common peripherals,
-+ * including the DMA Controllers and the Queue Managers.
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ */
-+
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/dma-mapping.h>
-+
-+#include "cppi41.h"
-+
-+#undef	CPPI41_DEBUG
-+
-+#ifdef	CPPI41_DEBUG
-+#define DBG(format, args...) printk(format, ##args)
-+#else
-+#define DBG(format, args...)
-+#endif
-+
-+static struct {
-+	void *virt_addr;
-+	dma_addr_t phys_addr;
-+	u32     size;
-+} linking_ram[CPPI41_NUM_QUEUE_MGR];
-+
-+static u32 *allocated_queues[CPPI41_NUM_QUEUE_MGR];
-+
-+/* First 32 packet descriptors are reserved for unallocated memory regions. */
-+static u32 next_desc_index[CPPI41_NUM_QUEUE_MGR] = { 1 << 5 };
-+static u8  next_mem_rgn[CPPI41_NUM_QUEUE_MGR];
-+
-+static struct {
-+	size_t rgn_size;
-+	void *virt_addr;
-+	dma_addr_t phys_addr;
-+	struct cppi41_queue_obj queue_obj;
-+	u8 mem_rgn;
-+	u16 q_mgr;
-+	u16 q_num;
-+	u32 num_desc;
-+} dma_teardown[CPPI41_NUM_DMA_BLOCK];
-+
-+struct cppi41_dma_sched_tbl_t {
-+	u8      pos;
-+	u8      dma_ch;
-+	u8      is_tx;
-+	u8      enb;
-+};
-+
-+struct cppi41_dma_sched_tbl_t dma_sched_tbl[MAX_SCHED_TBL_ENTRY] = {
-+	/*pos  dma_ch#  is_tx  enb/dis*/
-+	{ 0,    0,      0,      1},
-+	{ 1,    0,      1,      1},
-+	{ 2,    1,      0,      1},
-+	{ 3,    1,      1,      1},
-+	{ 4,    2,      0,      1},
-+	{ 5,    2,      1,      1},
-+	{ 6,    3,      0,      1},
-+	{ 7,    3,      1,      1}
-+};
-+
-+struct cppi41_queue_mgr cppi41_queue_mgr[CPPI41_NUM_QUEUE_MGR];
-+EXPORT_SYMBOL(cppi41_queue_mgr);
-+
-+struct cppi41_dma_block cppi41_dma_block[CPPI41_NUM_DMA_BLOCK];
-+EXPORT_SYMBOL(cppi41_dma_block);
-+/******************** CPPI 4.1 Functions (External Interface) *****************/
-+
-+int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size)
-+{
-+	void __iomem *q_mgr_regs;
-+	void *ptr;
-+
-+	if (q_mgr >= cppi41_num_queue_mgr)
-+		return -EINVAL;
-+
-+	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
-+	ptr = dma_alloc_coherent(NULL, rgn0_size * 4,
-+				 &linking_ram[q_mgr].phys_addr,
-+				 GFP_KERNEL | GFP_DMA);
-+	if (ptr == NULL) {
-+		printk(KERN_ERR "ERROR: %s: Unable to allocate "
-+		       "linking RAM.\n", __func__);
-+		return -ENOMEM;
-+	}
-+	linking_ram[q_mgr].virt_addr = ptr;
-+	linking_ram[q_mgr].size = rgn0_size * 4;
-+
-+	cppi_writel(linking_ram[q_mgr].phys_addr,
-+			q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
-+	DBG("Linking RAM region 0 base @ %p, value: %x\n",
-+	    q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG,
-+	    cppi_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG));
-+
-+	cppi_writel(rgn0_size, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
-+	DBG("Linking RAM region 0 size @ %p, value: %x\n",
-+	    q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG,
-+	    cppi_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG));
-+
-+	ptr = kzalloc(BITS_TO_LONGS(cppi41_queue_mgr[q_mgr].num_queue) *
-+			sizeof(long), GFP_KERNEL);
-+	if (ptr == NULL) {
-+		printk(KERN_ERR "ERROR: %s: Unable to allocate queue bitmap.\n",
-+		       __func__);
-+		dma_free_coherent(NULL, rgn0_size * 4,
-+				  linking_ram[q_mgr].virt_addr,
-+				  linking_ram[q_mgr].phys_addr);
-+		return -ENOMEM;
-+	}
-+	allocated_queues[q_mgr] = ptr;
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_queue_mgr_init);
-+
-+int cppi41_queue_mgr_uninit(u8 q_mgr)
-+{
-+	void __iomem *q_mgr_regs;
-+
-+	if (q_mgr >= cppi41_num_queue_mgr)
-+		return -EINVAL;
-+
-+	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
-+
-+	/* free the Queue Mgr linking ram space */
-+	cppi_writel(0,	q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
-+	cppi_writel(0, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
-+	dma_free_coherent(NULL, linking_ram[q_mgr].size,
-+			linking_ram[q_mgr].virt_addr,
-+			linking_ram[q_mgr].phys_addr);
-+
-+	/* free the allocated queues */
-+	kfree(allocated_queues[q_mgr]);
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_queue_mgr_uninit);
-+
-+int cppi41_dma_sched_tbl_init(u8 dma_num, u8 q_mgr,
-+			u32 *sched_tbl, u8 tbl_size)
-+{
-+	struct cppi41_dma_block *dma_block;
-+	int num_reg, k, i, val = 0;
-+
-+	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
-+
-+	num_reg = (tbl_size + 3) / 4;
-+	for (k = i = 0; i < num_reg; i++) {
-+#if 0
-+		for (val = j = 0; j < 4; j++, k++) {
-+			val >>= 8;
-+			if (k < tbl_size)
-+				val |= sched_tbl[k] << 24;
-+		}
-+#endif
-+		val = sched_tbl[i];
-+		cppi_writel(val, dma_block->sched_table_base +
-+			DMA_SCHED_TABLE_WORD_REG(i));
-+		DBG("DMA scheduler table @ %p, value written: %x\n",
-+		dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
-+			val);
-+	}
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_dma_sched_tbl_init);
-+
-+int cppi41_schedtbl_add_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx)
-+{
-+	struct cppi41_dma_block *dma_block;
-+	int num_ch, i, tbl_index = 0, j = 0, found = 0;
-+	u32 val;
-+
-+	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dmanum];
-+
-+	val = 0;
-+	for (num_ch = 0, i = 0; i < MAX_SCHED_TBL_ENTRY; i++) {
-+		if (!found && dma_sched_tbl[i].dma_ch == dma_ch &&
-+			dma_sched_tbl[i].is_tx == is_tx &&
-+			dma_sched_tbl[i].enb == 0) {
-+			dma_sched_tbl[i].enb = 1;
-+			found = 1;
-+		}
-+
-+		if (dma_sched_tbl[i].enb) {
-+			val |= ((dma_sched_tbl[i].dma_ch |
-+				(dma_sched_tbl[i].is_tx ? 0 : (1<<7))) << j*8);
-+			num_ch++;
-+			j++;
-+		}
-+		if (num_ch % 4 == 0) {
-+			cppi_writel(val, dma_block->sched_table_base +
-+				DMA_SCHED_TABLE_WORD_REG(tbl_index));
-+			tbl_index++;
-+			val = j = 0;
-+		}
-+	}
-+
-+	if (num_ch % 4) {
-+		cppi_writel(val, dma_block->sched_table_base +
-+			DMA_SCHED_TABLE_WORD_REG(tbl_index));
-+	}
-+	return num_ch;
-+}
-+EXPORT_SYMBOL(cppi41_schedtbl_add_dma_ch);
-+
-+int cppi41_schedtbl_remove_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx)
-+{
-+	struct cppi41_dma_block *dma_block;
-+	int num_ch, i, tbl_index = 0, j = 0, found = 0;
-+	u32 val;
-+
-+	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dmanum];
-+
-+	val = 0;
-+	for (num_ch = 0, i = 0; i < MAX_SCHED_TBL_ENTRY; i++) {
-+		if (!found && dma_sched_tbl[i].dma_ch == dma_ch &&
-+			dma_sched_tbl[i].is_tx == is_tx &&
-+			dma_sched_tbl[i].enb == 1) {
-+			dma_sched_tbl[i].enb = 0;
-+		}
-+
-+		if (dma_sched_tbl[i].enb) {
-+			val |= ((dma_sched_tbl[i].dma_ch |
-+				(dma_sched_tbl[i].is_tx ? 0 : (1<<7))) << j*8);
-+			num_ch++;
-+			j++;
-+		}
-+		if (num_ch % 4 == 0) {
-+			cppi_writel(val, dma_block->sched_table_base +
-+				DMA_SCHED_TABLE_WORD_REG(tbl_index));
-+			tbl_index++;
-+			val = j = 0;
-+		}
-+	}
-+
-+	if (num_ch % 4) {
-+		cppi_writel(val, dma_block->sched_table_base +
-+			DMA_SCHED_TABLE_WORD_REG(tbl_index));
-+	}
-+	return num_ch;
-+}
-+EXPORT_SYMBOL(cppi41_schedtbl_remove_dma_ch);
-+
-+int cppi41_dma_block_init(u8 dma_num, u8 q_mgr, u8 num_order,
-+				 u32 *sched_tbl, u8 tbl_size)
-+{
-+	const struct cppi41_dma_block *dma_block;
-+	unsigned num_desc, num_reg;
-+	void *ptr;
-+	int error, i;
-+	u16 q_num;
-+	u32 val;
-+
-+	if (dma_num >= cppi41_num_dma_block ||
-+	    q_mgr >= cppi41_num_queue_mgr ||
-+	    !tbl_size || sched_tbl == NULL)
-+		return -EINVAL;
-+
-+	error = cppi41_queue_alloc(CPPI41_FREE_DESC_QUEUE |
-+				   CPPI41_UNASSIGNED_QUEUE, q_mgr, &q_num);
-+	if (error) {
-+		printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
-+		       "descriptor queue.\n", __func__);
-+		return error;
-+	}
-+	DBG("Teardown descriptor queue %d in queue manager 0 "
-+	    "allocated\n", q_num);
-+
-+	/*
-+	 * Tell the hardware about the Teardown descriptor
-+	 * queue manager and queue number.
-+	 */
-+	dma_block = &cppi41_dma_block[dma_num];
-+	cppi_writel((q_mgr << DMA_TD_DESC_QMGR_SHIFT) |
-+		     (q_num << DMA_TD_DESC_QNUM_SHIFT),
-+		     dma_block->global_ctrl_base +
-+		     DMA_TEARDOWN_FREE_DESC_CTRL_REG);
-+	DBG("Teardown free descriptor control @ %p, value: %x\n",
-+	    dma_block->global_ctrl_base + DMA_TEARDOWN_FREE_DESC_CTRL_REG,
-+	    cppi_readl(dma_block->global_ctrl_base +
-+			DMA_TEARDOWN_FREE_DESC_CTRL_REG));
-+
-+	num_desc = 1 << num_order;
-+	dma_teardown[dma_num].rgn_size = num_desc *
-+					 sizeof(struct cppi41_teardown_desc);
-+
-+	/* Pre-allocate teardown descriptors. */
-+	ptr = dma_alloc_coherent(NULL, dma_teardown[dma_num].rgn_size,
-+				 &dma_teardown[dma_num].phys_addr,
-+				 GFP_KERNEL | GFP_DMA);
-+	if (ptr == NULL) {
-+		printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
-+		       "descriptors.\n", __func__);
-+		error = -ENOMEM;
-+		goto free_queue;
-+	}
-+	dma_teardown[dma_num].virt_addr = ptr;
-+
-+	error = cppi41_mem_rgn_alloc(q_mgr, dma_teardown[dma_num].phys_addr, 5,
-+				     num_order, &dma_teardown[dma_num].mem_rgn);
-+	if (error) {
-+		printk(KERN_ERR "ERROR: %s: Unable to allocate queue manager "
-+		       "memory region for teardown descriptors.\n", __func__);
-+		goto free_mem;
-+	}
-+
-+	error = cppi41_queue_init(&dma_teardown[dma_num].queue_obj, 0, q_num);
-+	if (error) {
-+		printk(KERN_ERR "ERROR: %s: Unable to initialize teardown "
-+		       "free descriptor queue.\n", __func__);
-+		goto free_rgn;
-+	}
-+
-+	dma_teardown[dma_num].q_num = q_num;
-+	dma_teardown[dma_num].q_mgr = q_mgr;
-+	dma_teardown[dma_num].num_desc = num_desc;
-+	/*
-+	 * Push all teardown descriptors to the free teardown queue
-+	 * for the CPPI 4.1 system.
-+	 */
-+	cppi41_init_teardown_queue(dma_num);
-+
-+	/* Initialize the DMA scheduler. */
-+	num_reg = (tbl_size + 3) / 4;
-+	for (i = 0; i < num_reg; i++) {
-+		val = sched_tbl[i];
-+		cppi_writel(val, dma_block->sched_table_base +
-+			     DMA_SCHED_TABLE_WORD_REG(i));
-+		DBG("DMA scheduler table @ %p, value written: %x\n",
-+		    dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
-+		    val);
-+	}
-+
-+	cppi_writel((tbl_size - 1) << DMA_SCHED_LAST_ENTRY_SHIFT |
-+		     DMA_SCHED_ENABLE_MASK,
-+		     dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
-+	DBG("DMA scheduler control @ %p, value: %x\n",
-+	    dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG,
-+	    cppi_readl(dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG));
-+
-+	return 0;
-+
-+free_rgn:
-+	cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
-+free_mem:
-+	dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
-+			  dma_teardown[dma_num].virt_addr,
-+			  dma_teardown[dma_num].phys_addr);
-+free_queue:
-+	cppi41_queue_free(q_mgr, q_num);
-+	return error;
-+}
-+EXPORT_SYMBOL(cppi41_dma_block_init);
-+
-+int cppi41_dma_block_uninit(u8 dma_num, u8 q_mgr, u8 num_order,
-+				 u32 *sched_tbl, u8 tbl_size)
-+{
-+	const struct cppi41_dma_block *dma_block;
-+	unsigned num_reg;
-+	int i;
-+
-+	/* popout all teardown descriptors */
-+	cppi41_free_teardown_queue(dma_num);
-+
-+	/* free queue mgr region */
-+	cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
-+	/* free the allocated teardown descriptors */
-+	dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
-+			dma_teardown[dma_num].virt_addr,
-+			dma_teardown[dma_num].phys_addr);
-+
-+	/* free the teardown queue*/
-+	cppi41_queue_free(dma_teardown[dma_num].q_mgr,
-+			dma_teardown[dma_num].q_num);
-+
-+	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
-+	/* disable the dma schedular */
-+	num_reg = (tbl_size + 3) / 4;
-+	for (i = 0; i < num_reg; i++) {
-+		cppi_writel(0, dma_block->sched_table_base +
-+			     DMA_SCHED_TABLE_WORD_REG(i));
-+		DBG("DMA scheduler table @ %p, value written: %x\n",
-+		    dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
-+		    0);
-+	}
-+
-+	cppi_writel(0,	dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_dma_block_uninit);
-+/*
-+ * cppi41_mem_rgn_alloc - allocate a memory region within the queue manager
-+ */
-+int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
-+			 u8 num_order, u8 *mem_rgn)
-+{
-+	void __iomem *desc_mem_regs;
-+	u32 num_desc = 1 << num_order, index, ctrl;
-+	int rgn;
-+
-+	DBG("%s called with rgn_addr = %08x, size_order = %d, num_order = %d\n",
-+	    __func__, rgn_addr, size_order, num_order);
-+
-+	if (q_mgr >= cppi41_num_queue_mgr ||
-+	    size_order < 5 || size_order > 13 ||
-+	    num_order  < 5 || num_order  > 12 ||
-+	    (rgn_addr & ((1 << size_order) - 1)))
-+		return -EINVAL;
-+
-+	rgn = next_mem_rgn[q_mgr];
-+	index = next_desc_index[q_mgr];
-+	if (rgn >= CPPI41_MAX_MEM_RGN || index + num_desc > 0x4000)
-+		return -ENOSPC;
-+
-+	next_mem_rgn[q_mgr] = rgn + 1;
-+	next_desc_index[q_mgr] = index + num_desc;
-+
-+	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
-+
-+	/* Write the base register */
-+	cppi_writel(rgn_addr, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn));
-+	DBG("Descriptor region base @ %p, value: %x\n",
-+	    desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn),
-+	    cppi_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn)));
-+
-+	/* Write the control register */
-+	ctrl = ((index << QMGR_MEM_RGN_INDEX_SHIFT) &
-+		QMGR_MEM_RGN_INDEX_MASK) |
-+	       (((size_order - 5) << QMGR_MEM_RGN_DESC_SIZE_SHIFT) &
-+		QMGR_MEM_RGN_DESC_SIZE_MASK) |
-+	       (((num_order - 5) << QMGR_MEM_RGN_SIZE_SHIFT) &
-+		QMGR_MEM_RGN_SIZE_MASK);
-+	cppi_writel(ctrl, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn));
-+	DBG("Descriptor region control @ %p, value: %x\n",
-+	    desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn),
-+	    cppi_readl(desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn)));
-+
-+	*mem_rgn = rgn;
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_mem_rgn_alloc);
-+
-+/*
-+ * cppi41_mem_rgn_free - free the memory region within the queue manager
-+ */
-+int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn)
-+{
-+	void __iomem *desc_mem_regs;
-+
-+	DBG("%s called.\n", __func__);
-+
-+	if (q_mgr >= cppi41_num_queue_mgr || mem_rgn >= next_mem_rgn[q_mgr])
-+		return -EINVAL;
-+
-+	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
-+
-+	if (cppi_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn)) == 0)
-+		return -ENOENT;
-+
-+	cppi_writel(0, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn));
-+	cppi_writel(0, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(mem_rgn));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_mem_rgn_free);
-+
-+/*
-+ * cppi41_tx_ch_init - initialize a CPPI 4.1 Tx channel object
-+ *
-+ * Verify the channel info (range checking, etc.) and store the channel
-+ * information within the object structure.
-+ */
-+int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
-+		      u8 dma_num, u8 ch_num)
-+{
-+	if (dma_num >= cppi41_num_dma_block ||
-+	    ch_num  >= cppi41_dma_block[dma_num].num_tx_ch)
-+		return -EINVAL;
-+
-+	/* Populate the channel object structure */
-+	tx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
-+				DMA_CH_TX_GLOBAL_CFG_REG(ch_num);
-+	tx_ch_obj->global_cfg = cppi_readl(tx_ch_obj->base_addr);
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_tx_ch_init);
-+
-+/*
-+ * cppi41_rx_ch_init - initialize a CPPI 4.1 Rx channel object
-+ *
-+ * Verify the channel info (range checking, etc.) and store the channel
-+ * information within the object structure.
-+ */
-+int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
-+		      u8 dma_num, u8 ch_num)
-+{
-+	if (dma_num >= cppi41_num_dma_block ||
-+	    ch_num  >= cppi41_dma_block[dma_num].num_rx_ch)
-+		return -EINVAL;
-+
-+	/* Populate the channel object structure */
-+	rx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
-+				DMA_CH_RX_GLOBAL_CFG_REG(ch_num);
-+	rx_ch_obj->global_cfg = cppi_readl(rx_ch_obj->base_addr);
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_rx_ch_init);
-+
-+/*
-+ * We have to cache the last written Rx/Tx channel global configration register
-+ * value due to its bits other than enable/teardown being write-only. Yet there
-+ * is a caveat related to caching the enable bit: this bit may be automatically
-+ * cleared as a result of teardown, so we can't trust its cached value!
-+ * When modifying the write only register fields, we're making use of the fact
-+ * that they read back as zeros, and not clearing them explicitly...
-+ */
-+
-+/*
-+ * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
-+ */
-+void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
-+				 u8 q_mgr, u16 q_num)
-+{
-+	u32 val = dma_ch_obj->global_cfg;
-+
-+	/* Clear the fields to be modified. */
-+	val &= ~(DMA_CH_TX_DEFAULT_QMGR_MASK | DMA_CH_TX_DEFAULT_QNUM_MASK |
-+		 DMA_CH_TX_ENABLE_MASK);
-+
-+	/* Set the default completion queue. */
-+	val |= ((q_mgr << DMA_CH_TX_DEFAULT_QMGR_SHIFT) &
-+		DMA_CH_TX_DEFAULT_QMGR_MASK) |
-+	       ((q_num << DMA_CH_TX_DEFAULT_QNUM_SHIFT) &
-+		DMA_CH_TX_DEFAULT_QNUM_MASK);
-+
-+	/* Get the current state of the enable bit. */
-+	dma_ch_obj->global_cfg = val |= cppi_readl(dma_ch_obj->base_addr);
-+	cppi_writel(val, dma_ch_obj->base_addr);
-+	DBG("Channel global configuration @ %p, value written: %x, "
-+	    "value read: %x\n", dma_ch_obj->base_addr, val,
-+	    cppi_readl(dma_ch_obj->base_addr));
-+
-+}
-+EXPORT_SYMBOL(cppi41_dma_ch_default_queue);
-+
-+/*
-+ * cppi41_rx_ch_configure - configure CPPI 4.1 Rx channel
-+ */
-+void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
-+			    struct cppi41_rx_ch_cfg  *cfg)
-+{
-+	void __iomem *base = rx_ch_obj->base_addr;
-+	u32 val = cppi_readl(rx_ch_obj->base_addr);
-+
-+	val |= ((cfg->sop_offset << DMA_CH_RX_SOP_OFFSET_SHIFT) &
-+		DMA_CH_RX_SOP_OFFSET_MASK) |
-+	       ((cfg->default_desc_type << DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT) &
-+		DMA_CH_RX_DEFAULT_DESC_TYPE_MASK) |
-+	       ((cfg->retry_starved << DMA_CH_RX_ERROR_HANDLING_SHIFT) &
-+		DMA_CH_RX_ERROR_HANDLING_MASK) |
-+	       ((cfg->rx_queue.q_mgr << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT) &
-+		DMA_CH_RX_DEFAULT_RQ_QMGR_MASK) |
-+	       ((cfg->rx_queue.q_num << DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT) &
-+		DMA_CH_RX_DEFAULT_RQ_QNUM_MASK);
-+
-+	val &= ~(0x7 << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
-+	val |= (cfg->rx_max_buf_cnt << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
-+
-+	rx_ch_obj->global_cfg = val;
-+	cppi_writel(val, base);
-+	DBG("Rx channel global configuration @ %p, value written: %x, "
-+	    "value read: %x\n", base, val, cppi_readl(base));
-+
-+	base -= DMA_CH_RX_GLOBAL_CFG_REG(0);
-+
-+	/*
-+	 * Set up the packet configuration register
-+	 * based on the descriptor type...
-+	 */
-+	switch (cfg->default_desc_type) {
-+	case DMA_CH_RX_DEFAULT_DESC_EMBED:
-+		val = ((cfg->cfg.embed_pkt.fd_queue.q_mgr <<
-+			DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT) &
-+		       DMA_CH_RX_EMBED_FDQ_QMGR_MASK) |
-+		      ((cfg->cfg.embed_pkt.fd_queue.q_num <<
-+			DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT) &
-+		       DMA_CH_RX_EMBED_FDQ_QNUM_MASK) |
-+		      ((cfg->cfg.embed_pkt.num_buf_slot <<
-+			DMA_CH_RX_EMBED_NUM_SLOT_SHIFT) &
-+		       DMA_CH_RX_EMBED_NUM_SLOT_MASK) |
-+		      ((cfg->cfg.embed_pkt.sop_slot_num <<
-+			DMA_CH_RX_EMBED_SOP_SLOT_SHIFT) &
-+		       DMA_CH_RX_EMBED_SOP_SLOT_MASK);
-+
-+		cppi_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0));
-+		DBG("Rx channel embedded packet configuration B @ %p, "
-+		    "value written: %x\n",
-+		    base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0), val);
-+
-+		val = ((cfg->cfg.embed_pkt.free_buf_pool[0].b_pool <<
-+			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(0)) &
-+		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(0)) |
-+		      ((cfg->cfg.embed_pkt.free_buf_pool[0].b_mgr <<
-+			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(0)) &
-+		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(0)) |
-+		      ((cfg->cfg.embed_pkt.free_buf_pool[1].b_pool <<
-+			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(1)) &
-+		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(1)) |
-+		      ((cfg->cfg.embed_pkt.free_buf_pool[1].b_mgr <<
-+			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(1)) &
-+		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(1)) |
-+		      ((cfg->cfg.embed_pkt.free_buf_pool[2].b_pool <<
-+			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(2)) &
-+		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(2)) |
-+		      ((cfg->cfg.embed_pkt.free_buf_pool[2].b_mgr <<
-+			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(2)) &
-+		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(2)) |
-+		      ((cfg->cfg.embed_pkt.free_buf_pool[3].b_pool <<
-+			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(3)) &
-+		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(3)) |
-+		      ((cfg->cfg.embed_pkt.free_buf_pool[3].b_mgr <<
-+			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(3)) &
-+		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(3));
-+
-+		cppi_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0));
-+		DBG("Rx channel embedded packet configuration A @ %p, "
-+		    "value written: %x\n",
-+		    base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0), val);
-+		break;
-+	case DMA_CH_RX_DEFAULT_DESC_HOST:
-+		val = ((cfg->cfg.host_pkt.fdb_queue[0].q_num <<
-+			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(0)) &
-+		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(0)) |
-+		      ((cfg->cfg.host_pkt.fdb_queue[0].q_mgr <<
-+			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(0)) &
-+		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(0)) |
-+		      ((cfg->cfg.host_pkt.fdb_queue[1].q_num <<
-+			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(1)) &
-+		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(1)) |
-+		      ((cfg->cfg.host_pkt.fdb_queue[1].q_mgr <<
-+			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(1)) &
-+		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(1));
-+
-+		cppi_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0));
-+		DBG("Rx channel host packet configuration A @ %p, "
-+		    "value written: %x\n",
-+		    base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0), val);
-+
-+		val = ((cfg->cfg.host_pkt.fdb_queue[2].q_num <<
-+			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(2)) &
-+		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(2)) |
-+		      ((cfg->cfg.host_pkt.fdb_queue[2].q_mgr <<
-+			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(2)) &
-+		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(2)) |
-+		      ((cfg->cfg.host_pkt.fdb_queue[3].q_num <<
-+		       DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(3)) &
-+		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(3)) |
-+		      ((cfg->cfg.host_pkt.fdb_queue[3].q_mgr <<
-+			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(3)) &
-+		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(3));
-+
-+		cppi_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0));
-+		DBG("Rx channel host packet configuration B @ %p, "
-+		    "value written: %x\n",
-+		    base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0), val);
-+		break;
-+	case DMA_CH_RX_DEFAULT_DESC_MONO:
-+		val = ((cfg->cfg.mono_pkt.fd_queue.q_num <<
-+			DMA_CH_RX_MONO_FDQ_QNUM_SHIFT) &
-+		       DMA_CH_RX_MONO_FDQ_QNUM_MASK) |
-+		      ((cfg->cfg.mono_pkt.fd_queue.q_mgr <<
-+			DMA_CH_RX_MONO_FDQ_QMGR_SHIFT) &
-+		       DMA_CH_RX_MONO_FDQ_QMGR_MASK) |
-+		      ((cfg->cfg.mono_pkt.sop_offset <<
-+			DMA_CH_RX_MONO_SOP_OFFSET_SHIFT) &
-+		       DMA_CH_RX_MONO_SOP_OFFSET_MASK);
-+
-+		cppi_writel(val, base + DMA_CH_RX_MONO_PKT_CFG_REG(0));
-+		DBG("Rx channel monolithic packet configuration @ %p, "
-+		    "value written: %x\n",
-+		    base + DMA_CH_RX_MONO_PKT_CFG_REG(0), val);
-+		break;
-+	}
-+}
-+EXPORT_SYMBOL(cppi41_rx_ch_configure);
-+
-+void cppi41_rx_ch_set_maxbufcnt(struct cppi41_dma_ch_obj *rx_ch_obj,
-+			    u8 rx_max_buf_cnt)
-+{
-+	void __iomem *base = rx_ch_obj->base_addr;
-+	u32 val = cppi_readl(rx_ch_obj->base_addr);
-+
-+	val = rx_ch_obj->global_cfg;
-+	val &= ~(0x7 << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
-+	val |= (rx_max_buf_cnt << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
-+
-+	rx_ch_obj->global_cfg = val;
-+	cppi_writel(val, base);
-+
-+	DBG("%s: rx-global-cfg @ %p, value written: %x, "
-+	    "value read: %x\n", __func__, base, val, cppi_readl(base));
-+
-+}
-+EXPORT_SYMBOL(cppi41_rx_ch_set_maxbufcnt);
-+/*
-+ * cppi41_dma_ch_teardown - teardown a given Tx/Rx channel
-+ */
-+void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj)
-+{
-+	u32 val = cppi_readl(dma_ch_obj->base_addr);
-+
-+	/* Initiate channel teardown. */
-+	val |= dma_ch_obj->global_cfg & ~DMA_CH_TX_ENABLE_MASK;
-+	dma_ch_obj->global_cfg = val |= DMA_CH_TX_TEARDOWN_MASK;
-+	cppi_writel(val, dma_ch_obj->base_addr);
-+	DBG("Tear down channel @ %p, value written: %x, value read: %x\n",
-+	    dma_ch_obj->base_addr, val, cppi_readl(dma_ch_obj->base_addr));
-+}
-+EXPORT_SYMBOL(cppi41_dma_ch_teardown);
-+
-+/*
-+ * cppi41_dma_ch_enable - enable Tx/Rx DMA channel in hardware
-+ *
-+ * Makes the channel ready for data transmission/reception.
-+ */
-+void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj)
-+{
-+	u32 val = dma_ch_obj->global_cfg | DMA_CH_TX_ENABLE_MASK;
-+
-+	/* Teardown bit remains set after completion, so clear it now... */
-+	dma_ch_obj->global_cfg = val &= ~DMA_CH_TX_TEARDOWN_MASK;
-+	cppi_writel(val, dma_ch_obj->base_addr);
-+	DBG("Enable channel @ %p, value written: %x, value read: %x\n",
-+	    dma_ch_obj->base_addr, val, cppi_readl(dma_ch_obj->base_addr));
-+}
-+EXPORT_SYMBOL(cppi41_dma_ch_enable);
-+
-+/*
-+ * cppi41_dma_ch_disable - disable Tx/Rx DMA channel in hardware
-+ */
-+void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj)
-+{
-+	dma_ch_obj->global_cfg &= ~DMA_CH_TX_ENABLE_MASK;
-+	cppi_writel(dma_ch_obj->global_cfg, dma_ch_obj->base_addr);
-+	DBG("Disable channel @ %p, value written: %x, value read: %x\n",
-+	    dma_ch_obj->base_addr, dma_ch_obj->global_cfg,
-+	    cppi_readl(dma_ch_obj->base_addr));
-+}
-+EXPORT_SYMBOL(cppi41_dma_ch_disable);
-+
-+void cppi41_init_teardown_queue(int dma_num)
-+{
-+	dma_addr_t td_addr;
-+	struct cppi41_teardown_desc *curr_td;
-+	u32 num_desc = dma_teardown[dma_num].num_desc;
-+	int i;
-+
-+	curr_td = dma_teardown[dma_num].virt_addr;
-+	td_addr = dma_teardown[dma_num].phys_addr;
-+
-+	for (i = 0; i < num_desc; i++) {
-+		cppi41_queue_push(&dma_teardown[dma_num].queue_obj, td_addr,
-+				  sizeof(*curr_td), 0);
-+		td_addr += sizeof(*curr_td);
-+	}
-+}
-+EXPORT_SYMBOL(cppi41_init_teardown_queue);
-+
-+void cppi41_free_teardown_queue(int dma_num)
-+{
-+	unsigned long td_addr;
-+	u32 num_desc = dma_teardown[dma_num].num_desc;
-+
-+	while (num_desc--) {
-+		td_addr = cppi41_queue_pop(&dma_teardown[dma_num].queue_obj);
-+
-+		if (td_addr == 0)
-+			break;
-+	}
-+}
-+EXPORT_SYMBOL(cppi41_free_teardown_queue);
-+
-+/**
-+ * alloc_queue - allocate a queue in the given range
-+ * @allocated:	pointer to the bitmap of the allocated queues
-+ * @excluded:	pointer to the bitmap of the queues excluded from allocation
-+ *		(optional)
-+ * @start:	starting queue number
-+ * @count:	number of queues available
-+ *
-+ * Returns queue number on success, -ENOSPC otherwise.
-+ */
-+static int alloc_queue(u32 *allocated, const u32 *excluded, unsigned start,
-+		       unsigned count)
-+{
-+	u32 bit, mask = 0;
-+	int index = -1;
-+
-+	/*
-+	 * We're starting the loop as if we've just wrapped around 32 bits
-+	 * in order to save on preloading the bitmasks.
-+	 */
-+	for (bit = 0; count--; start++, bit <<= 1) {
-+		/* Have we just wrapped around 32 bits? */
-+		if (!bit) {
-+			/* Start over with the next bitmask word */
-+			bit = 1;
-+			index++;
-+			/* Have we just entered the loop? */
-+			if (!index) {
-+				/* Calculate the starting values */
-+				bit <<= start & 0x1f;
-+				index = start >> 5;
-+			}
-+			/*
-+			 * Load the next word of the allocated bitmask OR'ing
-+			 * it with the excluded bitmask if it's been passed.
-+			 */
-+			mask = allocated[index];
-+			if (excluded != NULL)
-+				mask |= excluded[index];
-+		}
-+		/*
-+		 * If the bit in the combined bitmask is zero,
-+		 * we've just found a free queue.
-+		 */
-+		if (!(mask & bit)) {
-+			allocated[index] |= bit;
-+			return start;
-+		}
-+	}
-+	return -ENOSPC;
-+}
-+
-+/*
-+ * cppi41_queue_alloc - allocate a queue of a given type in the queue manager
-+ */
-+int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num)
-+{
-+	int res = -ENOSPC;
-+
-+	if (q_mgr >= cppi41_num_queue_mgr)
-+		return -EINVAL;
-+
-+	/* Mask out the unsupported queue types */
-+	type &= cppi41_queue_mgr[q_mgr].queue_types;
-+	/* First see if a free descriptor queue was requested... */
-+	if (type & CPPI41_FREE_DESC_QUEUE)
-+		res = alloc_queue(allocated_queues[q_mgr], NULL,
-+				  cppi41_queue_mgr[q_mgr].base_fdq_num,  16);
-+
-+	/* Then see if a free descriptor/buffer queue was requested... */
-+	if (res < 0 && (type & CPPI41_FREE_DESC_BUF_QUEUE))
-+		res = alloc_queue(allocated_queues[q_mgr], NULL,
-+				  cppi41_queue_mgr[q_mgr].base_fdbq_num, 16);
-+
-+	/* Last see if an unassigned queue was requested... */
-+	if (res < 0 && (type & CPPI41_UNASSIGNED_QUEUE))
-+		res = alloc_queue(allocated_queues[q_mgr],
-+				  cppi41_queue_mgr[q_mgr].assigned, 0,
-+				  cppi41_queue_mgr[q_mgr].num_queue);
-+
-+	/* See if any queue was allocated... */
-+	if (res < 0)
-+		return res;
-+
-+	/* Return the queue allocated */
-+	*q_num = res;
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_queue_alloc);
-+
-+/*
-+ * cppi41_queue_free - free the given queue in the queue manager
-+ */
-+int cppi41_queue_free(u8 q_mgr, u16 q_num)
-+{
-+	int index = q_num >> 5, bit = 1 << (q_num & 0x1f);
-+
-+	if (allocated_queues[q_mgr] != NULL) {
-+		if (q_mgr >= cppi41_num_queue_mgr ||
-+		    q_num >= cppi41_queue_mgr[q_mgr].num_queue ||
-+		    !(allocated_queues[q_mgr][index] & bit))
-+			return -EINVAL;
-+		allocated_queues[q_mgr][index] &= ~bit;
-+	}
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_queue_free);
-+
-+/*
-+ * cppi41_queue_init - initialize a CPPI 4.1 queue object
-+ */
-+int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num)
-+{
-+	if (q_mgr >= cppi41_num_queue_mgr ||
-+	    q_num >= cppi41_queue_mgr[q_mgr].num_queue)
-+		return -EINVAL;
-+
-+	queue_obj->base_addr = cppi41_queue_mgr[q_mgr].q_mgmt_rgn_base +
-+			       QMGR_QUEUE_STATUS_REG_A(q_num);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_queue_init);
-+
-+/*
-+ * cppi41_queue_push - push a descriptor into the given queue
-+ */
-+void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
-+		       u32 desc_size, u32 pkt_size)
-+{
-+	u32 val;
-+
-+	/*
-+	 * Write to the tail of the queue.
-+	 * TODO: Can't think of a reason why a queue to head may be required.
-+	 * If it is, the API may have to be extended.
-+	 */
-+#if 0
-+	/*
-+	 * Also, can't understand why packet size is required to queue up a
-+	 * descriptor. The spec says packet size *must* be written prior to
-+	 * the packet write operation.
-+	 */
-+	if (pkt_size)
-+		val = (pkt_size << QMGR_QUEUE_PKT_SIZE_SHIFT) &
-+		      QMGR_QUEUE_PKT_SIZE_MASK;
-+	cppi_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_C(0));
-+#endif
-+
-+	val = (((desc_size - 24) >> (2 - QMGR_QUEUE_DESC_SIZE_SHIFT)) &
-+	       QMGR_QUEUE_DESC_SIZE_MASK) |
-+	      (desc_addr & QMGR_QUEUE_DESC_PTR_MASK);
-+
-+	DBG("Pushing value %x to queue @ %p\n", val, queue_obj->base_addr);
-+
-+	cppi_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
-+}
-+EXPORT_SYMBOL(cppi41_queue_push);
-+
-+/*
-+ * cppi41_queue_pop - pop a descriptor from a given queue
-+ */
-+unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj)
-+{
-+	u32 val = cppi_readl(queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
-+
-+	DBG("Popping value %x from queue @ %p\n", val, queue_obj->base_addr);
-+
-+	return val & QMGR_QUEUE_DESC_PTR_MASK;
-+}
-+EXPORT_SYMBOL(cppi41_queue_pop);
-+
-+/*
-+ * cppi41_get_teardown_info - extract information from a teardown descriptor
-+ */
-+int cppi41_get_teardown_info(unsigned long addr, u32 *info)
-+{
-+	struct cppi41_teardown_desc *desc;
-+	int dma_num;
-+
-+	for (dma_num = 0; dma_num < cppi41_num_dma_block; dma_num++)
-+		if (addr >= dma_teardown[dma_num].phys_addr &&
-+		    addr <  dma_teardown[dma_num].phys_addr +
-+			    dma_teardown[dma_num].rgn_size)
-+			break;
-+
-+	if (dma_num == cppi41_num_dma_block)
-+		return -EINVAL;
-+
-+	desc = addr - dma_teardown[dma_num].phys_addr +
-+	       dma_teardown[dma_num].virt_addr;
-+
-+	if ((desc->teardown_info & CPPI41_DESC_TYPE_MASK) !=
-+	    (CPPI41_DESC_TYPE_TEARDOWN << CPPI41_DESC_TYPE_SHIFT))
-+		return -EINVAL;
-+
-+	*info = desc->teardown_info;
-+#if 1
-+	/* Hardware is not giving the current DMA number as of now. :-/ */
-+	*info |= (dma_num << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &
-+		 CPPI41_TEARDOWN_DMA_NUM_MASK;
-+#else
-+	dma_num = (desc->teardown_info & CPPI41_TEARDOWN_DMA_NUM_MASK) >>
-+		 CPPI41_TEARDOWN_DMA_NUM_SHIFT;
-+#endif
-+
-+	cppi41_queue_push(&dma_teardown[dma_num].queue_obj, addr,
-+			  sizeof(struct cppi41_teardown_desc), 0);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(cppi41_get_teardown_info);
-+
-+/*
-+ * cppi41_save_context - save regsiter context before going to suspend.
-+ */
-+void cppi41_save_context(u8 dma_num)
-+{
-+	const struct cppi41_dma_block *dma_block;
-+	struct cppi41_dma_regs *cppi41;
-+	struct cppi41_queue_manager *qmgr;
-+	void __iomem *q_mgr_regs, *desc_mem_regs;
-+	u8 i, q_mgr = 0;
-+
-+	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
-+	cppi41 = (struct cppi41_dma_regs *)&dma_block->cppi41_regs;
-+	qmgr = &cppi41->qmgr;
-+	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
-+	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
-+
-+	/* popout all teardown descriptors */
-+	cppi41_free_teardown_queue(dma_num);
-+
-+	cppi41->teardn_fdq_ctrl = cppi_readl(dma_block->global_ctrl_base +
-+			DMA_TEARDOWN_FREE_DESC_CTRL_REG);
-+	cppi41->emulation_ctrl = cppi_readl(dma_block->global_ctrl_base +
-+			DMA_EMULATION_CTRL_REG);
-+
-+	qmgr->link_ram_rgn0_base = cppi_readl(q_mgr_regs +
-+				QMGR_LINKING_RAM_RGN0_BASE_REG);
-+	qmgr->link_ram_rgn0_size = cppi_readl(q_mgr_regs +
-+				QMGR_LINKING_RAM_RGN0_SIZE_REG);
-+	qmgr->link_ram_rgn1_base = cppi_readl(q_mgr_regs +
-+				QMGR_LINKING_RAM_RGN1_BASE_REG);
-+
-+	for (i = 0 ; i < 8 ; i++) {
-+		qmgr->memr_base[i] = cppi_readl(desc_mem_regs +
-+				QMGR_MEM_RGN_BASE_REG(i));
-+		qmgr->memr_ctrl[i] = cppi_readl(desc_mem_regs +
-+				QMGR_MEM_RGN_CTRL_REG(i));
-+	}
-+
-+	cppi41->sched_ctrl = cppi_readl(dma_block->sched_ctrl_base +
-+				DMA_SCHED_CTRL_REG);
-+
-+}
-+EXPORT_SYMBOL(cppi41_save_context);
-+
-+/*
-+ * cppi41_restore_context - restore regsiter context after resume.
-+ */
-+void cppi41_restore_context(u8 dma_num, u32 *sched_tbl)
-+{
-+	const struct cppi41_dma_block *dma_block;
-+	struct cppi41_dma_regs *cppi41;
-+	struct cppi41_queue_manager *qmgr;
-+	void __iomem *q_mgr_regs, *desc_mem_regs;
-+	unsigned num_reg;
-+	u32 val;
-+	u8 tbl_size;
-+	u8 i, q_mgr = 0;
-+
-+	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
-+	cppi41 = (struct cppi41_dma_regs *)&dma_block->cppi41_regs;
-+	qmgr = &cppi41->qmgr;
-+	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
-+	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
-+	tbl_size = dma_block->num_max_ch;
-+
-+	cppi_writel(cppi41->teardn_fdq_ctrl, dma_block->global_ctrl_base +
-+			DMA_TEARDOWN_FREE_DESC_CTRL_REG);
-+	cppi_writel(cppi41->emulation_ctrl, dma_block->global_ctrl_base +
-+			DMA_EMULATION_CTRL_REG);
-+
-+	cppi_writel(qmgr->link_ram_rgn0_base, q_mgr_regs +
-+				QMGR_LINKING_RAM_RGN0_BASE_REG);
-+	cppi_writel(qmgr->link_ram_rgn0_size, q_mgr_regs +
-+				QMGR_LINKING_RAM_RGN0_SIZE_REG);
-+	cppi_writel(qmgr->link_ram_rgn1_base, q_mgr_regs +
-+				QMGR_LINKING_RAM_RGN1_BASE_REG);
-+
-+	for (i = 0 ; i < 8 ; i++) {
-+		cppi_writel(qmgr->memr_base[i], desc_mem_regs +
-+				QMGR_MEM_RGN_BASE_REG(i));
-+		cppi_writel(qmgr->memr_ctrl[i], desc_mem_regs +
-+				QMGR_MEM_RGN_CTRL_REG(i));
-+	}
-+
-+	/*
-+	 * Push all teardown descriptors to the free teardown queue
-+	 * for the CPPI 4.1 system.
-+	 */
-+	cppi41_init_teardown_queue(dma_num);
-+
-+	/* Initialize the DMA scheduler. */
-+	num_reg = (tbl_size + 3) / 4;
-+	for (i = 0; i < num_reg; i++) {
-+		val = sched_tbl[i];
-+		cppi_writel(val, dma_block->sched_table_base +
-+			     DMA_SCHED_TABLE_WORD_REG(i));
-+	}
-+	cppi_writel(cppi41->sched_ctrl, dma_block->sched_ctrl_base +
-+				DMA_SCHED_CTRL_REG);
-+}
-+EXPORT_SYMBOL(cppi41_restore_context);
-+
-+MODULE_DESCRIPTION("TI CPPI 4.1 support");
-+MODULE_AUTHOR("MontaVista Software");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/usb/musb/cppi41.h b/drivers/usb/musb/cppi41.h
-new file mode 100644
-index 0000000..9f0b3ef
---- /dev/null
-+++ b/drivers/usb/musb/cppi41.h
-@@ -0,0 +1,850 @@
-+/*
-+ * CPPI 4.1 definitions
-+ *
-+ * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ */
-+
-+#include <linux/types.h>
-+
-+/*
-+ * Queue Manager - Control Registers Region
-+ */
-+#define QMGR_REVISION_REG		0x00	/* Major and minor versions */
-+						/* of the module */
-+#define QMGR_QUEUE_DIVERSION_REG	0x08	/* Queue Diversion register */
-+#define QMGR_FREE_DESC_BUF_STARVED_REG(n) (0x20 + ((n) << 2)) /* Free Desc./ */
-+						/* Buffer Starvation Count */
-+#define QMGR_FREE_DESC_STARVED_REG(n)	(0x30 + ((n) << 2)) /* Free Desc. */
-+						/* Starvation Count */
-+#define QMGR_LINKING_RAM_RGN0_BASE_REG	0x80	/* Linking RAM Region 0 Base */
-+						/* Address */
-+#define QMGR_LINKING_RAM_RGN0_SIZE_REG	0x84	/* Linking RAM Region 0 Size */
-+#define QMGR_LINKING_RAM_RGN1_BASE_REG	0x88	/* Linking RAM Region 1 Base */
-+						/* Address */
-+#define QMGR_QUEUE_PENDING_REG(n)	(0x90 + ((n) << 2)) /* Pending status */
-+						/* for all queues */
-+
-+/*
-+ * Queue Manager - Memory Region Registers
-+ */
-+#define QMGR_MEM_RGN_BASE_REG(r)	(0x00 + ((r) << 4))
-+#define QMGR_MEM_RGN_CTRL_REG(r)	(0x04 + ((r) << 4))
-+
-+/* Memory Region R Control Register bits */
-+#define QMGR_MEM_RGN_INDEX_SHIFT	16
-+#define QMGR_MEM_RGN_INDEX_MASK		(0x3fff << QMGR_MEM_RGN_INDEX_SHIFT)
-+#define QMGR_MEM_RGN_DESC_SIZE_SHIFT	8
-+#define QMGR_MEM_RGN_DESC_SIZE_MASK	(0xf << QMGR_MEM_RGN_DESC_SIZE_SHIFT)
-+#define QMGR_MEM_RGN_SIZE_SHIFT		0
-+#define QMGR_MEM_RGN_SIZE_MASK		(7 << QMGR_MEM_RGN_SIZE_SHIFT)
-+
-+/*
-+ * Queue Manager - Queues Region
-+ */
-+#define QMGR_QUEUE_REG_A(n)		(0x00 + ((n) << 4))
-+#define QMGR_QUEUE_REG_B(n)		(0x04 + ((n) << 4))
-+#define QMGR_QUEUE_REG_C(n)		(0x08 + ((n) << 4))
-+#define QMGR_QUEUE_REG_D(n)		(0x0C + ((n) << 4))
-+
-+/* Queue N Register C bits */
-+#define QMGR_QUEUE_HEAD_TAIL_SHIFT	31
-+#define QMGR_QUEUE_HEAD_TAIL_MASK	(1 << QMGR_QUEUE_HEAD_TAIL_SHIFT)
-+#define QMGR_QUEUE_PKT_SIZE_SHIFT	0
-+#define QMGR_QUEUE_PKT_SIZE_MASK	(0x3fff << QMGR_QUEUE_PKT_SIZE_SHIFT)
-+/* Queue N Register D bits */
-+#define QMGR_QUEUE_DESC_PTR_SHIFT	5
-+#define QMGR_QUEUE_DESC_PTR_MASK	(0x7ffffff << QMGR_QUEUE_DESC_PTR_SHIFT)
-+#define QMGR_QUEUE_DESC_SIZE_SHIFT	0
-+#define QMGR_QUEUE_DESC_SIZE_MASK	(0x1f << QMGR_QUEUE_DESC_SIZE_SHIFT)
-+
-+/*
-+ * Queue Manager - Queue Status Region
-+ */
-+#define QMGR_QUEUE_STATUS_REG_A(n)	(0x00 + ((n) << 4))
-+#define QMGR_QUEUE_STATUS_REG_B(n)	(0x04 + ((n) << 4))
-+#define QMGR_QUEUE_STATUS_REG_C(n)	(0x08 + ((n) << 4))
-+
-+/*
-+ * DMA Controller - Global Control Registers Region
-+ */
-+#define DMA_REVISION_REG		0x00	/* Major and minor versions */
-+						/* of the module */
-+#define DMA_TEARDOWN_FREE_DESC_CTRL_REG 0x04	/* Queue  manager and queue */
-+						/* number for Teardown free */
-+						/* descriptor queue */
-+#define DMA_EMULATION_CTRL_REG		0x08	/* Emulation control register */
-+
-+/* Teardown Free Descriptor Queue Control Register bits */
-+#define DMA_TD_DESC_QMGR_SHIFT		12
-+#define DMA_TD_DESC_QMGR_MASK		(3 << DMA_TD_DESC_QMGR_SHIFT)
-+#define DMA_TD_DESC_QNUM_SHIFT		0
-+#define DMA_TD_DESC_QNUM_MASK		(0xfff << DMA_TD_DESC_QNUM_SHIFT)
-+
-+/*
-+ * DMA Controller - Channel Control / Status Registers Region
-+ */
-+#define DMA_CH_TX_GLOBAL_CFG_REG(n)	 (0x00 + ((n) << 5))
-+#define DMA_CH_RX_GLOBAL_CFG_REG(n)	 (0x08 + ((n) << 5))
-+#define DMA_CH_RX_HOST_PKT_CFG_REG_A(n)  (0x0C + ((n) << 5))
-+#define DMA_CH_RX_HOST_PKT_CFG_REG_B(n)  (0x10 + ((n) << 5))
-+#define DMA_CH_RX_EMBED_PKT_CFG_REG_A(n) (0x14 + ((n) << 5))
-+#define DMA_CH_RX_EMBED_PKT_CFG_REG_B(n) (0x18 + ((n) << 5))
-+#define DMA_CH_RX_MONO_PKT_CFG_REG(n)	 (0x1C + ((n) << 5))
-+
-+/* Tx Channel N Global Configuration Register bits */
-+#define DMA_CH_TX_ENABLE_SHIFT		31
-+#define DMA_CH_TX_ENABLE_MASK		(1 << DMA_CH_TX_ENABLE_SHIFT)
-+#define DMA_CH_TX_TEARDOWN_SHIFT	30
-+#define DMA_CH_TX_TEARDOWN_MASK		(1 << DMA_CH_TX_TEARDOWN_SHIFT)
-+#define DMA_CH_TX_DEFAULT_QMGR_SHIFT	12
-+#define DMA_CH_TX_DEFAULT_QMGR_MASK	(3 << DMA_CH_TX_DEFAULT_QMGR_SHIFT)
-+#define DMA_CH_TX_DEFAULT_QNUM_SHIFT	0
-+#define DMA_CH_TX_DEFAULT_QNUM_MASK	(0xfff << DMA_CH_TX_DEFAULT_QNUM_SHIFT)
-+
-+/* Rx Channel N Global Configuration Register bits */
-+#define DMA_CH_RX_ENABLE_SHIFT		31
-+#define DMA_CH_RX_ENABLE_MASK		(1 << DMA_CH_RX_ENABLE_SHIFT)
-+#define DMA_CH_RX_TEARDOWN_SHIFT	30
-+#define DMA_CH_RX_TEARDOWN_MASK		(1 << DMA_CH_RX_TEARDOWN_SHIFT)
-+#define DMA_CH_RX_ERROR_HANDLING_SHIFT	24
-+#define DMA_CH_RX_ERROR_HANDLING_MASK	(1 << DMA_CH_RX_ERROR_HANDLING_SHIFT)
-+#define DMA_CH_RX_SOP_OFFSET_SHIFT	16
-+#define DMA_CH_RX_SOP_OFFSET_MASK	(0xff << DMA_CH_RX_SOP_OFFSET_SHIFT)
-+#define DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT 14
-+#define DMA_CH_RX_DEFAULT_DESC_TYPE_MASK  (3 << \
-+					   DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT)
-+#define DMA_CH_RX_DEFAULT_DESC_EMBED	0
-+#define DMA_CH_RX_DEFAULT_DESC_HOST	1
-+#define DMA_CH_RX_DEFAULT_DESC_MONO	2
-+#define DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT 12
-+#define DMA_CH_RX_DEFAULT_RQ_QMGR_MASK	(3 << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT)
-+#define DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT 0
-+#define DMA_CH_RX_DEFAULT_RQ_QNUM_MASK	(0xfff << \
-+					 DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT)
-+#define DMA_CH_RX_MAX_BUF_CNT_SHIFT	26
-+#define	DMA_CH_RX_MAX_BUF_CNT_0		0
-+#define	DMA_CH_RX_MAX_BUF_CNT_1		1
-+#define	DMA_CH_RX_MAX_BUF_CNT_2		2
-+#define	DMA_CH_RX_MAX_BUF_CNT_3		3
-+
-+/* Rx Channel N Host Packet Configuration Register A/B bits */
-+#define DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n) (12 + 16 * ((n) & 1))
-+#define DMA_CH_RX_HOST_FDQ_QMGR_MASK(n)  (3 << DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n))
-+#define DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n) (0 + 16 * ((n) & 1))
-+#define DMA_CH_RX_HOST_FDQ_QNUM_MASK(n)  (0xfff << \
-+					  DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n))
-+
-+/* Rx Channel N Embedded Packet Configuration Register A bits */
-+#define DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n) (6 + 8 * (n))
-+#define DMA_CH_RX_EMBED_FBP_BMGR_MASK(n)  (3 << \
-+					   DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n))
-+#define DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n) (0 + 8 * (n))
-+#define DMA_CH_RX_EMBED_FBP_PNUM_MASK(n)  (0x1f << \
-+					   DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n))
-+
-+/* Rx Channel N Embedded Packet Configuration Register B bits */
-+#define DMA_CH_RX_EMBED_NUM_SLOT_SHIFT	24
-+#define DMA_CH_RX_EMBED_NUM_SLOT_MASK	(7 << DMA_CH_RX_EMBED_NUM_SLOT_SHIFT)
-+#define DMA_CH_RX_EMBED_SOP_SLOT_SHIFT	16
-+#define DMA_CH_RX_EMBED_SOP_SLOT_MASK	(7 << DMA_CH_RX_EMBED_SOP_SLOT_SHIFT)
-+#define DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT	12
-+#define DMA_CH_RX_EMBED_FDQ_QMGR_MASK	(3 << DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT)
-+#define DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT	0
-+#define DMA_CH_RX_EMBED_FDQ_QNUM_MASK	(0xfff << \
-+					 DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT)
-+
-+/* Rx Channel N Monolithic Packet Configuration Register bits */
-+#define DMA_CH_RX_MONO_SOP_OFFSET_SHIFT 16
-+#define DMA_CH_RX_MONO_SOP_OFFSET_MASK	(0xff << \
-+					 DMA_CH_RX_MONO_SOP_OFFSET_SHIFT)
-+#define DMA_CH_RX_MONO_FDQ_QMGR_SHIFT	12
-+#define DMA_CH_RX_MONO_FDQ_QMGR_MASK	(3 << DMA_CH_RX_MONO_FDQ_QMGR_SHIFT)
-+#define DMA_CH_RX_MONO_FDQ_QNUM_SHIFT	0
-+#define DMA_CH_RX_MONO_FDQ_QNUM_MASK	(0xfff << DMA_CH_RX_MONO_FDQ_QNUM_SHIFT)
-+
-+/*
-+ * DMA Scheduler - Control Region
-+ */
-+#define DMA_SCHED_CTRL_REG		0x00
-+
-+/* DMA Scheduler Control Register bits */
-+#define DMA_SCHED_ENABLE_SHIFT		31
-+#define DMA_SCHED_ENABLE_MASK		(1 << DMA_SCHED_ENABLE_SHIFT)
-+#define DMA_SCHED_LAST_ENTRY_SHIFT	0
-+#define DMA_SCHED_LAST_ENTRY_MASK	(0xff << DMA_SCHED_LAST_ENTRY_SHIFT)
-+
-+#define CPPI41_TXDMA_MAXLEN		(4 * 1024 * 1024 - 1)
-+#define CPPI41_RXDMA_MAXLEN		(64 * 1024)
-+
-+/*
-+ * Queue Status register
-+ */
-+#define CPPI41_QSTATUS_REG0	0x90
-+#define CPPI41_QSTATUS_REG1	0x94
-+#define CPPI41_QSTATUS_REG2	0x98
-+#define CPPI41_QSTATUS_REG3	0x9c
-+#define CPPI41_QSTATUS_REG4	0xa0
-+
-+/*
-+ * DMA Scheduler - Table Region
-+ */
-+#define DMA_SCHED_TABLE_WORD_REG(n)	((n) << 2)
-+#define MAX_SCHED_TBL_ENTRY     8
-+
-+/*
-+ * CPPI 4.1 Host Packet Descriptor
-+ */
-+struct cppi41_host_pkt_desc {
-+	u32 desc_info;		/* Descriptor type, protocol specific word */
-+				/* count, packet length */
-+	u32 tag_info;		/* Source tag (31:16), destination tag (15:0) */
-+	u32 pkt_info;		/* Packet error state, type, protocol flags, */
-+				/* return info, descriptor location */
-+	u32 buf_len;		/* Number of valid data bytes in the buffer */
-+	u32 buf_ptr;		/* Pointer to the buffer associated with */
-+				/* this descriptor */
-+	u32 next_desc_ptr;	/* Pointer to the next buffer descriptor */
-+	u32 orig_buf_len;	/* Original buffer length */
-+	u32 orig_buf_ptr;	/* Original buffer pointer */
-+	u32 stk_comms_info[2];	/* Network stack private communications info */
-+};
-+
-+/*
-+ * CPPI 4.1 Host Buffer Descriptor
-+ */
-+struct cppi41_host_buf_desc {
-+	u32 reserved[2];
-+	u32 buf_recl_info;	/* Return info, descriptor location */
-+	u32 buf_len;		/* Number of valid data bytes in the buffer */
-+	u32 buf_ptr;		/* Pointer to the buffer associated with */
-+				/* this descriptor */
-+	u32 next_desc_ptr;	/* Pointer to the next buffer descriptor */
-+	u32 orig_buf_len;	/* Original buffer length */
-+	u32 orig_buf_ptr;	/* Original buffer pointer */
-+};
-+
-+#define CPPI41_DESC_TYPE_SHIFT		27
-+#define CPPI41_DESC_TYPE_MASK		(0x1f << CPPI41_DESC_TYPE_SHIFT)
-+#define CPPI41_DESC_TYPE_HOST		16
-+#define CPPI41_DESC_TYPE_MONOLITHIC	18
-+#define CPPI41_DESC_TYPE_TEARDOWN	19
-+#define CPPI41_PROT_VALID_WORD_CNT_SHIFT 22
-+#define CPPI41_PROT_VALID_WORD_CNT_MASK	(0x1f << CPPI41_PROT_WORD_CNT_SHIFT)
-+#define CPPI41_PKT_LEN_SHIFT		0
-+#define CPPI41_PKT_LEN_MASK		(0x1fffff << CPPI41_PKT_LEN_SHIFT)
-+
-+#define CPPI41_PKT_ERROR_SHIFT		31
-+#define CPPI41_PKT_ERROR_MASK		(1 << CPPI41_PKT_ERROR_SHIFT)
-+#define CPPI41_PKT_TYPE_SHIFT		26
-+#define CPPI41_PKT_TYPE_MASK		(0x1f << CPPI41_PKT_TYPE_SHIFT)
-+#define CPPI41_PKT_TYPE_ATM_AAL5	0
-+#define CPPI41_PKT_TYPE_ATM_NULL_AAL	1
-+#define CPPI41_PKT_TYPE_ATM_OAM		2
-+#define CPPI41_PKT_TYPE_ATM_TRANSPARENT	3
-+#define CPPI41_PKT_TYPE_EFM		4
-+#define CPPI41_PKT_TYPE_USB		5
-+#define CPPI41_PKT_TYPE_GENERIC		6
-+#define CPPI41_PKT_TYPE_ETHERNET	7
-+#define CPPI41_RETURN_POLICY_SHIFT	15
-+#define CPPI41_RETURN_POLICY_MASK	(1 << CPPI41_RETURN_POLICY_SHIFT)
-+#define CPPI41_RETURN_LINKED		0
-+#define CPPI41_RETURN_UNLINKED		1
-+#define CPPI41_ONCHIP_SHIFT		14
-+#define CPPI41_ONCHIP_MASK		(1 << CPPI41_ONCHIP_SHIFT)
-+#define CPPI41_RETURN_QMGR_SHIFT	12
-+#define CPPI41_RETURN_QMGR_MASK		(3 << CPPI41_RETURN_QMGR_SHIFT)
-+#define CPPI41_RETURN_QNUM_SHIFT	0
-+#define CPPI41_RETURN_QNUM_MASK		(0xfff << CPPI41_RETURN_QNUM_SHIFT)
-+
-+#define CPPI41_SRC_TAG_PORT_NUM_SHIFT	27
-+#define CPPI41_SRC_TAG_PORT_NUM_MASK	(0x1f << CPPI41_SRC_TAG_PORT_NUM_SHIFT)
-+#define CPPI41_SRC_TAG_CH_NUM_SHIFT	21
-+#define CPPI41_SRC_TAG_CH_NUM_MASK	(0x3f << CPPI41_SRC_TAG_CH_NUM_SHIFT)
-+#define CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT 16
-+#define CPPI41_SRC_TAG_SUB_CH_NUM_MASK	(0x1f << \
-+					CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT)
-+#define CPPI41_DEST_TAG_SHIFT		0
-+#define CPPI41_DEST_TAG_MASK		(0xffff << CPPI41_DEST_TAG_SHIFT)
-+#define CPPI41_PKT_INTR_FLAG		(1 << 31)
-+
-+/*
-+ * CPPI 4.1 Teardown Descriptor
-+ */
-+struct cppi41_teardown_desc {
-+	u32 teardown_info;	/* Teardown information */
-+	u32 reserved[7];	/* 28 byte padding */
-+};
-+
-+#define CPPI41_TEARDOWN_TX_RX_SHIFT	16
-+#define CPPI41_TEARDOWN_TX_RX_MASK	(1 << CPPI41_TEARDOWN_TX_RX_SHIFT)
-+#define CPPI41_TEARDOWN_DMA_NUM_SHIFT	10
-+#define CPPI41_TEARDOWN_DMA_NUM_MASK	(0x3f << CPPI41_TEARDOWN_DMA_NUM_SHIFT)
-+#define CPPI41_TEARDOWN_CHAN_NUM_SHIFT	0
-+#define CPPI41_TEARDOWN_CHAN_NUM_MASK	(0x3f << CPPI41_TEARDOWN_CHAN_NUM_SHIFT)
-+
-+#define CPPI41_MAX_MEM_RGN		16
-+
-+/* CPPI 4.1 configuration for AM3517 */
-+#define CPPI41_NUM_QUEUE_MGR		1	/* 4  max */
-+#define CPPI41_NUM_DMA_BLOCK		1	/* 64 max */
-+#define cppi41_num_queue_mgr	CPPI41_NUM_QUEUE_MGR
-+#define cppi41_num_dma_block	CPPI41_NUM_DMA_BLOCK
-+
-+/**
-+ * struct cppi41_queue_manager - CPPI 4.1 DMA queue manager registers for
-+ * context save and restore.
-+ */
-+struct cppi41_queue_manager {
-+	u32	link_ram_rgn0_base;
-+	u32	link_ram_rgn0_size;
-+	u32	link_ram_rgn1_base;
-+
-+	u32	memr_base[8];
-+	u32	memr_ctrl[8];
-+};
-+
-+/**
-+ * struct cppi41_dma_regs - CPPI 4.1 DMA registers for
-+ * context save and restore.
-+ */
-+struct cppi41_dma_regs {
-+	u32	teardn_fdq_ctrl;
-+	u32	emulation_ctrl;
-+
-+	/* CPPI DMA scheduler registers */
-+	u32	sched_ctrl;
-+
-+	/* Queue manager registers */
-+	struct cppi41_queue_manager qmgr;
-+};
-+
-+/**
-+ * struct cppi41_queue - Queue Tuple
-+ *
-+ * The basic queue tuple in CPPI 4.1 used across all data structures
-+ * where a definition of a queue is required.
-+ */
-+struct cppi41_queue {
-+	u8  q_mgr;		/* The queue manager number */
-+	u16 q_num;		/* The queue number */
-+};
-+
-+/**
-+ * struct cppi41_buf_pool - Buffer Pool Tuple
-+ *
-+ * The basic buffer pool tuple in CPPI 4.1 used across all data structures
-+ * where a definition of a buffer pool is required.
-+ */
-+struct cppi41_buf_pool {
-+	u8  b_mgr;		/* The buffer manager number */
-+	u16 b_pool;		/* The buffer pool number */
-+};
-+
-+/**
-+ * struct cppi41_queue_mgr - Queue Manager information
-+ *
-+ * Contains the information about the queue manager which should be copied from
-+ * the hardware spec as is.
-+ */
-+struct cppi41_queue_mgr {
-+	void __iomem *q_mgr_rgn_base; /* Base address of the Control region. */
-+	void __iomem *desc_mem_rgn_base; /* Base address of the descriptor */
-+				/* memory region. */
-+	void __iomem *q_mgmt_rgn_base; /* Base address of the queues region. */
-+	void __iomem *q_stat_rgn_base; /* Base address of the queue status */
-+				/* region. */
-+	u16 num_queue;		/* Number of the queues supported. */
-+	u8 queue_types;		/* Bitmask of the supported queue types. */
-+	u16 base_fdq_num;	/* The base free descriptor queue number. */
-+				/* If present, there's always 16 such queues. */
-+	u16 base_fdbq_num;	/* The base free descriptor/buffer queue */
-+				/* number.  If present, there's always 16 */
-+				/* such queues. */
-+	const u32 *assigned;	/* Pointer to the bitmask of the pre-assigned */
-+				/* queues. */
-+};
-+
-+/* Queue type flags */
-+#define CPPI41_FREE_DESC_QUEUE		0x01
-+#define CPPI41_FREE_DESC_BUF_QUEUE	0x02
-+#define CPPI41_UNASSIGNED_QUEUE		0x04
-+
-+/**
-+ * struct cppi41_embed_pkt_cfg - Rx Channel Embedded packet configuration
-+ *
-+ * An instance of this structure forms part of the Rx channel information
-+ * structure.
-+ */
-+struct cppi41_embed_pkt_cfg {
-+	struct cppi41_queue fd_queue; /* Free Descriptor queue.*/
-+	u8 num_buf_slot;	/* Number of buffer slots in the descriptor */
-+	u8 sop_slot_num;	/* SOP buffer slot number. */
-+	struct cppi41_buf_pool free_buf_pool[4]; /* Free Buffer pool. Element */
-+				/* 0 used for the 1st Rx buffer, etc. */
-+};
-+
-+/**
-+ * struct cppi41_host_pkt_cfg - Rx Channel Host Packet Configuration
-+ *
-+ * An instance of this structure forms part of the Rx channel information
-+ * structure.
-+ */
-+struct cppi41_host_pkt_cfg {
-+	struct cppi41_queue fdb_queue[4]; /* Free Desc/Buffer queue. Element */
-+				/* 0 used for 1st Rx buffer, etc. */
-+};
-+
-+/**
-+ * struct cppi41_mono_pkt_cfg - Rx Channel Monolithic Packet Configuration
-+ *
-+ * An instance of this structure forms part of the Rx channel information
-+ * structure.
-+ */
-+struct cppi41_mono_pkt_cfg {
-+	struct cppi41_queue fd_queue; /* Free descriptor queue */
-+	u8 sop_offset;		/* Number of bytes to skip before writing */
-+				/* payload */
-+};
-+
-+enum cppi41_rx_desc_type {
-+	cppi41_rx_embed_desc,
-+	cppi41_rx_host_desc,
-+	cppi41_rx_mono_desc,
-+};
-+
-+/**
-+ * struct cppi41_rx_ch_cfg - Rx Channel Configuration
-+ *
-+ * Must be allocated and filled by the caller of cppi41_rx_ch_configure().
-+ *
-+ * The same channel can be configured to receive different descripor type
-+ * packets (not simaltaneously). When the Rx packets on a port need to be sent
-+ * to the SR, the channels default descriptor type is set to Embedded and the
-+ * Rx completion queue is set to the queue which CPU polls for input packets.
-+ * When in SR bypass mode, the same channel's default descriptor type will be
-+ * set to Host and the Rx completion queue set to one of the queues which host
-+ * can get interrupted on (via the Queuing proxy/accumulator). In this example,
-+ * the embedded mode configuration fetches free descriptor from the Free
-+ * descriptor queue (as defined by struct cppi41_embed_pkt_cfg) and host
-+ * mode configuration fetches free descriptors/buffers from the free descriptor/
-+ * buffer queue (as defined by struct cppi41_host_pkt_cfg).
-+ *
-+ * NOTE: There seems to be no separate configuration for teardown completion
-+ * descriptor. The assumption is rxQueue tuple is used for this purpose as well.
-+ */
-+struct cppi41_rx_ch_cfg {
-+	enum cppi41_rx_desc_type default_desc_type; /* Describes which queue */
-+				/* configuration is used for the free */
-+				/* descriptors and/or buffers */
-+	u8 sop_offset;		/* Number of bytes to skip in SOP buffer */
-+				/* before writing payload */
-+	u8 retry_starved;	/* 0 = Drop packet on descriptor/buffer */
-+				/* starvartion, 1 = DMA retries FIFO block */
-+				/* transfer at a later time */
-+	u8 rx_max_buf_cnt;	/* The DMA ignores the SOP bit and closes up
-+				 * a packet after a max_buf_cnt buffer has been
-+				 * filled OR if the EOP field is set in the
-+				 * info word 0
-+				 */
-+	struct cppi41_queue rx_queue; /* Rx complete packets queue */
-+	union {
-+		struct cppi41_host_pkt_cfg host_pkt; /* Host packet */
-+				/* configuration. This defines where channel */
-+				/* picks free descriptors from. */
-+		struct cppi41_embed_pkt_cfg embed_pkt; /* Embedded packet */
-+				/* configuration. This defines where channel */
-+				/* picks free descriptors/buffers from. */
-+				/* from. */
-+		struct cppi41_mono_pkt_cfg mono_pkt; /* Monolithic packet */
-+				/* configuration. This defines where channel */
-+				/* picks free descriptors from. */
-+	} cfg;			/* Union of packet configuration structures */
-+				/* to be filled in depending on the */
-+				/* defDescType field. */
-+};
-+
-+/**
-+ * struct cppi41_tx_ch - Tx channel information
-+ *
-+ * NOTE: The queues that feed into the Tx channel are fixed at SoC design time.
-+ */
-+struct cppi41_tx_ch {
-+	u8 port_num;		/* Port number. */
-+	u8 ch_num;		/* Channel number within port. */
-+	u8 sub_ch_num;		/* Sub-channel number within channel. */
-+	u8 num_tx_queue;	/* Number of queues from which the channel */
-+				/* can feed. */
-+	struct cppi41_queue tx_queue[4]; /* List of queues from which the */
-+				/* channel can feed. */
-+};
-+
-+/**
-+ * struct cppi41_dma_block - CPPI 4.1 DMA configuration
-+ *
-+ * Configuration information for CPPI DMA functionality. Includes the Global
-+ * configuration, Channel configuration, and the Scheduler configuration.
-+ */
-+struct cppi41_dma_block {
-+	void __iomem *global_ctrl_base; /* Base address of the Global Control */
-+				/* registers. */
-+	void __iomem *ch_ctrl_stat_base; /* Base address of the Channel */
-+				/* Control/Status registers. */
-+	void __iomem *sched_ctrl_base; /* Base address of the Scheduler */
-+				/* Control register. */
-+	void __iomem *sched_table_base; /* Base address of the Scheduler */
-+				/* Table registers. */
-+	u8 num_tx_ch;		/* Number of the Tx channels. */
-+	u8 num_rx_ch;		/* Number of the Rx channels. */
-+	u8 num_max_ch;		/* maximum dma channels */
-+	const struct cppi41_tx_ch *tx_ch_info;
-+	struct cppi41_dma_regs cppi41_regs; /* registers to save and restore */
-+};
-+
-+extern struct cppi41_queue_mgr cppi41_queue_mgr[];
-+extern struct cppi41_dma_block cppi41_dma_block[];
-+
-+/**
-+ * struct cppi41_dma_ch_obj - CPPI 4.1 DMA Channel object
-+ */
-+struct cppi41_dma_ch_obj {
-+	void __iomem *base_addr; /* The address of the channel global */
-+				/* configuration register */
-+	u32 global_cfg;		/* Tx/Rx global configuration backed-up value */
-+};
-+
-+/**
-+ * struct cppi41_queue_obj - CPPI 4.1 queue object
-+ */
-+struct cppi41_queue_obj {
-+	void __iomem *base_addr; /* The base address of the queue management */
-+				/* registers */
-+};
-+
-+static inline u32 cppi_readl(const void __iomem *addr)
-+	{ return readl(addr); }
-+static inline void cppi_writel(u32 data, void __iomem *addr)
-+	{ writel(data, addr); }
-+/**
-+ * cppi41_queue_mgr_init - CPPI 4.1 queue manager initialization.
-+ * @q_mgr:	the queue manager to initialize
-+ * @rgn0_base:	linking RAM region 0 physical address
-+ * @rgn0_size:	linking RAM region 0 size in 32-bit words (0 to 0x3fff)
-+ *
-+ * Returns 0 on success, error otherwise.
-+ */
-+int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size);
-+
-+/**
-+ * cppi41_queue_mgr_init - CPPI 4.1 queue manager un-initialization.
-+ * @q_mgr:	the queue manager to un-initialize
-+ * Returns 0 on success, error otherwise.
-+ */
-+int cppi41_queue_mgr_uninit(u8 q_mgr);
-+
-+/*
-+ * CPPI 4.1 Queue Manager Memory Region Allocation and De-allocation APIs.
-+ */
-+
-+/**
-+ * cppi41_mem_rgn_alloc - CPPI 4.1 queue manager memory region allocation.
-+ * @q_mgr:	the queue manager whose memory region to allocate
-+ * @rgn_addr:	physical address of the memory region
-+ * @size_order:	descriptor size as a power of two (between 5 and 13)
-+ * @num_order:	number of descriptors as a power of two (between 5 and 12)
-+ * @mem_rgn:	pointer to the index of the memory region allocated
-+ *
-+ * This function allocates a memory region within the queue manager
-+ * consisiting of the descriptors of paricular size and number.
-+ *
-+ * Returns 0 on success, error otherwise.
-+ */
-+int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
-+			 u8 num_order, u8 *mem_rgn);
-+
-+/**
-+ * cppi41_mem_rgn_free - CPPI 4.1 queue manager memory region de-allocation.
-+ * @q_mgr:	the queue manager whose memory region was allocated
-+ * @mem_rgn:	index of the memory region
-+ *
-+ * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
-+ *
-+ * Returns 0 on success, -EINVAL otherwise.
-+ */
-+int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn);
-+
-+/**
-+ * cppi41_dma_block_init - CPPI 4.1 DMA block initialization.
-+ * @dma_num:	number of the DMA block
-+ * @q_mgr:	the queue manager in which to allocate the free teardown
-+ *		descriptor queue
-+ * @num_order:	number of teardown descriptors as a power of two (at least 5)
-+ * @sched_tbl:	the DMA scheduler table
-+ * @tbl_size:	number of entries in the DMA scheduler table
-+ *
-+ * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
-+ *
-+ * Returns 0 on success, error otherwise.
-+ */
-+int cppi41_dma_block_init(u8 dma_num, u8 q_mgr, u8 num_order,
-+				 u32 *sched_tbl, u8 tbl_size);
-+
-+/**
-+ * cppi41_dma_block_init - CPPI 4.1 DMA block un-initialization.
-+ * @dma_num:	number of the DMA block
-+ * @q_mgr:	the queue manager in which to allocate the free teardown
-+ *		descriptor queue
-+ * @num_order:	number of teardown descriptors as a power of two (at least 5)
-+ * @sched_tbl:	the DMA scheduler table
-+ * @tbl_size:	number of entries in the DMA scheduler table
-+ *
-+ * Returns 0 on success, error otherwise.
-+ */
-+int cppi41_dma_block_uninit(u8 dma_num, u8 q_mgr, u8 num_order,
-+				 u32 *sched_tbl, u8 tbl_size);
-+
-+/*
-+ * CPPI 4.1 DMA Channel Management APIs
-+ */
-+
-+/**
-+ * cppi41_tx_ch_init - initialize CPPI 4.1 transmit channel object
-+ * @tx_ch_obj:	pointer to Tx channel object
-+ * @dma_num:	DMA block to which this channel belongs
-+ * @ch_num:	DMA channel number
-+ *
-+ * Returns 0 if valid Tx channel, -EINVAL otherwise.
-+ */
-+int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
-+		      u8 dma_num, u8 ch_num);
-+
-+/**
-+ * cppi41_rx_ch_init - initialize CPPI 4.1 receive channel object
-+ * @rx_ch_obj:	pointer to Rx channel object
-+ * @dma_num:	DMA block to which this channel belongs
-+ * @ch_num:	DMA channel number
-+ *
-+ * Returns 0 if valid Rx channel, -EINVAL otherwise.
-+ */
-+int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
-+		      u8 dma_num, u8 ch_num);
-+
-+/**
-+ * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
-+ * @dma_ch_obj: pointer to DMA channel object
-+ * @q_mgr:	default queue manager
-+ * @q_num:	default queue number
-+ *
-+ * This function configures the specified channel.  The caller is required to
-+ * provide the default queue onto which the teardown descriptors will be queued.
-+ */
-+void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
-+				 u8 q_mgr, u16 q_num);
-+
-+/**
-+ * cppi41_rx_ch_configure - configure CPPI 4.1 receive channel
-+ * @rx_ch_obj:	pointer to Rx channel object
-+ * @cfg:	pointer to Rx channel configuration
-+ *
-+ * This function configures and opens the specified Rx channel.  The caller
-+ * is required to provide channel configuration information by initializing
-+ * a struct cppi41_rx_ch_cfg.
-+ */
-+void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
-+			    struct cppi41_rx_ch_cfg  *cfg);
-+
-+/**
-+ * cppi41_rx_ch_set_maxbufcnt - configure max rx buffer count
-+ * @rx_ch_obj:	pointer to Rx channel object
-+ * rx_max_buf_cnt: maximum rx buffer count
-+ *
-+ * This function configures the maximum rx buffer count in rx dma
-+ * global configuration register. The valid rx_max_buf_cnt value
-+ * must be 0 to 4.
-+ */
-+void cppi41_rx_ch_set_maxbufcnt(struct cppi41_dma_ch_obj *rx_ch_obj,
-+			    u8 rx_max_buf_cnt);
-+/**
-+ * cppi41_dma_ch_enable - enable CPPI 4.1 Tx/Rx DMA channel
-+ * @dma_ch_obj:	pointer to DMA channel object
-+ *
-+ * This function enables  a specified Tx channel.  The caller is required to
-+ * provide a reference to a channel object initialized by an earlier call of
-+ * the cppi41_dma_ch_init() function.  After the successful completion of this
-+ * function, the Tx DMA channel will be active and ready for data transmission.
-+ */
-+void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj);
-+
-+/**
-+ * cppi41_dma_ch_disable - disable CPPI 4.1 Tx/Rx DMA channel
-+ * @dma_ch_obj:	pointer to DMA channel object
-+ *
-+ * This function disables a specific Tx channel.  The caller is required to
-+ * provide a reference to a channel object initialized by an earlier call of
-+ * the cppi41_dma_ch_init() function.  After the successful completion of this
-+ * function, the Tx DMA channel will be deactived.
-+ */
-+void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj);
-+
-+/**
-+ * cppi41_dma_ch_teardown - tear down CPPI 4.1 transmit channel
-+ * @dma_ch_obj:	pointer DMA channel object
-+ *
-+ * This function triggers the teardown of the given DMA channel.
-+ *
-+ * ATTENTION: Channel disable should not be called before the teardown is
-+ * completed as a disable will stop the DMA scheduling on the channel resulting
-+ * in the teardown complete event not being registered at all.
-+ *
-+ * NOTE: A successful channel teardown event is reported via queueing of a
-+ * teardown descriptor.
-+ *
-+ * This function just sets up for the teardown of the channel and returns. The
-+ * caller must detect the channel teardown event to assume that the channel is
-+ * disabled.
-+ *
-+ * See cppi41_get_teardown_info() for the teardown completion processing.
-+ */
-+void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj);
-+
-+/*
-+ * CPPI 4.1 Queue Allocation and De-allocation APIs.
-+ */
-+
-+/**
-+ * cppi41_queue_alloc - allocate CPPI 4.1 queue
-+ * @type:	queue type bitmask
-+ * @q_mgr:	queue manager
-+ * @q_num:	pointer to the queue number
-+ *
-+ * Returns 0 if queue allocated, error otherwise.
-+ */
-+int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num);
-+
-+/**
-+ * cppi41_queue_free - de-allocate CPPI 4.1 queue
-+ * @q_mgr:	queue manager
-+ * @q_num:	queue number
-+ *
-+ * Returns 0 on success, -EINVAL otherwise.
-+ */
-+int cppi41_queue_free(u8 q_mgr, u16 q_num);
-+
-+/*
-+ *  CPPI 4.1 Queue Management APIs
-+ */
-+
-+/**
-+ * cppi41_queue_init - initialize CPPI 4.1 queue object
-+ * @queue_obj:	pointer to the queue object
-+ * @q_mgr:	queue manager
-+ * @q_num:	queue number
-+ *
-+ * Returns 0 if valid queue, -EINVAL otherwise.
-+ */
-+int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num);
-+
-+/**
-+ * cppi41_queue_push - push to CPPI 4.1 queue
-+ * @queue_obj:	pointer to the queue object
-+ * @desc_addr:	descriptor physical address
-+ * @desc_size:	descriptor size
-+ * @pkt_size:	packet size
-+ *
-+ * This function is called to queue a descriptor onto a queue.
-+ * NOTE: pSize parameter is optional. Pass 0 in case not required.
-+ */
-+void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
-+		       u32 desc_size, u32 pkt_size);
-+
-+/**
-+ * cppi41_queue_pop - pop from CPPI 4.1 queue
-+ * @queue_obj:	pointer to the queue object
-+ *
-+ * This function is called to pop a single descriptor from the queue.
-+ *
-+ * Returns a packet descriptor's physical address.
-+ */
-+unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj);
-+
-+/*
-+ * CPPI 4.1 Miscellaneous APIs
-+ */
-+
-+/**
-+ * cppi41_get_teardown_info - CPPI 4.1 teardown completion processing function
-+ *
-+ * @addr:	physical address of teardown descriptor
-+ * @info:	pointer to the teardown information word
-+ *
-+ * This function is called to complete the teardown processing on a channel
-+ * and provides teardown information from the teardown descriptor passed to it.
-+ * It also recycles the teardown descriptor back to the teardown descriptor
-+ * queue.
-+ *
-+ * Returns 0 if valid descriptor, -EINVAL otherwise.
-+ */
-+int cppi41_get_teardown_info(unsigned long addr, u32 *info);
-+
-+/**
-+ * cppi41_dma_sched_tbl_init
-+ */
-+int cppi41_dma_sched_tbl_init(u8 dma_num, u8 q_mgr,
-+				u32 *sched_tbl, u8 tbl_size);
-+
-+/**
-+ * cppi41_schedtbl_add_dma_ch - add a dma channel to schedular table
-+ *
-+ * @dmanum      Number of DMa block
-+ * @qmgr        Queue Manager Number
-+ * @dma_ch      dma channel number
-+ * @is_tx       transmit (is_tx=1) or recieve(is_tx=0)
-+ *
-+ * returns      number of channel in schedular table
-+ */
-+int cppi41_schedtbl_add_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx);
-+
-+/**
-+ * cppi41_schedtbl_remove_dma_ch - remove a dma channel from schedular table
-+ *
-+ * @dmanum      Number of DMa block
-+ * @qmgr        Queue Manager Number
-+ * @dma_ch      dma channel number
-+ * @is_tx       transmit (is_tx=1) or recieve(is_tx=0)
-+ *
-+ * returns      number of channel in schedular table
-+ */
-+int cppi41_schedtbl_remove_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx);
-+
-+/**
-+ * cppi41_init_teardown_queue
-+ */
-+void cppi41_init_teardown_queue(int dma_num);
-+
-+/**
-+ * cppi41_free_teardown_queue
-+ */
-+void cppi41_free_teardown_queue(int dma_num);
-+
-+/**
-+ * cppi41_save_context
-+ */
-+void cppi41_save_context(u8 dma_num);
-+
-+/**
-+ * cppi41_restore_context
-+ */
-+void cppi41_restore_context(u8 dma_num, u32 *sched_tbl);
-diff --git a/drivers/usb/musb/cppi41_dma.c b/drivers/usb/musb/cppi41_dma.c
-new file mode 100644
-index 0000000..69a952d
---- /dev/null
-+++ b/drivers/usb/musb/cppi41_dma.c
-@@ -0,0 +1,1596 @@
-+/*
-+ * Copyright (C) 2005-2006 by Texas Instruments
-+ * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
-+ *
-+ * This file implements a DMA interface using TI's CPPI 4.1 DMA.
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/module.h>
-+
-+#include "cppi41.h"
-+
-+#include "musb_core.h"
-+#include "musb_dma.h"
-+#include "cppi41_dma.h"
-+
-+/* Configuration */
-+#define USB_CPPI41_DESC_SIZE_SHIFT 6
-+#define USB_CPPI41_DESC_ALIGN	(1 << USB_CPPI41_DESC_SIZE_SHIFT)
-+#define USB_CPPI41_CH_NUM_PD	128	/* 4K bulk data at full speed */
-+#define USB_CPPI41_MAX_PD	(USB_CPPI41_CH_NUM_PD * (USB_CPPI41_NUM_CH+1))
-+
-+#undef DEBUG_CPPI_TD
-+#undef USBDRV_DEBUG
-+
-+#ifdef USBDRV_DEBUG
-+#define dprintk(x, ...) printk(x, ## __VA_ARGS__)
-+#else
-+#define dprintk(x, ...)
-+#endif
-+
-+/*
-+ * Data structure definitions
-+ */
-+
-+/*
-+ * USB Packet Descriptor
-+ */
-+struct usb_pkt_desc;
-+
-+struct usb_pkt_desc {
-+	/* Hardware descriptor fields from this point */
-+	struct cppi41_host_pkt_desc hw_desc;	/* 40 bytes */
-+	/* Protocol specific data */
-+	dma_addr_t dma_addr;			/* offs:44 byte */
-+	struct usb_pkt_desc *next_pd_ptr;	/* offs:48 byte*/
-+	u8 ch_num;
-+	u8 ep_num;
-+	u8 eop;
-+	u8 res1;				/* offs:52 */
-+	u8 res2[12];				/* offs:64 */
-+};
-+
-+/**
-+ * struct cppi41_channel - DMA Channel Control Structure
-+ *
-+ * Using the same for Tx/Rx.
-+ */
-+struct cppi41_channel {
-+	struct dma_channel channel;
-+
-+	struct cppi41_dma_ch_obj dma_ch_obj; /* DMA channel object */
-+	struct cppi41_queue src_queue;	/* Tx queue or Rx free descriptor/ */
-+					/* buffer queue */
-+	struct cppi41_queue_obj queue_obj; /* Tx queue object or Rx free */
-+					/* descriptor/buffer queue object */
-+
-+	u32 tag_info;			/* Tx PD Tag Information field */
-+
-+	/* Which direction of which endpoint? */
-+	struct musb_hw_ep *end_pt;
-+	u8 transmit;
-+	u8 ch_num;			/* Channel number of Tx/Rx 0..3 */
-+
-+	/* DMA mode: "transparent", RNDIS, CDC, or Generic RNDIS */
-+	u8 dma_mode;
-+	u8 autoreq;
-+
-+	/* Book keeping for the current transfer request */
-+	dma_addr_t start_addr;
-+	u32 length;
-+	u32 curr_offset;
-+	u16 pkt_size;
-+	u8  transfer_mode;
-+	u8  zlp_queued;
-+	u8  inf_mode;
-+	u8  tx_complete;
-+	u8  hb_mult;
-+};
-+
-+/**
-+ * struct cppi41 - CPPI 4.1 DMA Controller Object
-+ *
-+ * Encapsulates all book keeping and data structures pertaining to
-+ * the CPPI 1.4 DMA controller.
-+ */
-+struct cppi41 {
-+	struct dma_controller controller;
-+	struct musb *musb;
-+
-+	struct cppi41_channel tx_cppi_ch[USB_CPPI41_NUM_CH];
-+	struct cppi41_channel rx_cppi_ch[USB_CPPI41_NUM_CH];
-+	struct work_struct      txdma_work;
-+
-+	struct usb_pkt_desc *pd_pool_head; /* Free PD pool head */
-+	dma_addr_t pd_mem_phys;		/* PD memory physical address */
-+	void *pd_mem;			/* PD memory pointer */
-+	u8 pd_mem_rgn;			/* PD memory region number */
-+
-+	u16 teardownQNum;		/* Teardown completion queue number */
-+	struct cppi41_queue_obj queue_obj; /* Teardown completion queue */
-+					/* object */
-+	u32 pkt_info;			/* Tx PD Packet Information field */
-+	struct usb_cppi41_info *cppi_info; /* cppi channel information */
-+	u8 en_bd_intr;			/* enable bd interrupt */
-+	u32 automode_reg_offs;		/* USB_AUTOREQ_REG offset */
-+	u32 teardown_reg_offs;		/* USB_TEARDOWN_REG offset */
-+	u32 bd_size;
-+	u8  inf_mode;
-+};
-+
-+struct usb_cppi41_info usb_cppi41_info[2];
-+EXPORT_SYMBOL(usb_cppi41_info);
-+
-+#ifdef DEBUG_CPPI_TD
-+static void print_pd_list(struct usb_pkt_desc *pd_pool_head)
-+{
-+	struct usb_pkt_desc *curr_pd = pd_pool_head;
-+	int cnt = 0;
-+
-+	while (curr_pd != NULL) {
-+		if (cnt % 8 == 0)
-+			dprintk("\n%02x ", cnt);
-+		cnt++;
-+		dprintk(" %p", curr_pd);
-+		curr_pd = curr_pd->next_pd_ptr;
-+	}
-+	dprintk("\n");
-+}
-+#endif
-+
-+static struct usb_pkt_desc *usb_get_free_pd(struct cppi41 *cppi)
-+{
-+	struct usb_pkt_desc *free_pd = cppi->pd_pool_head;
-+
-+	if (free_pd != NULL) {
-+		cppi->pd_pool_head = free_pd->next_pd_ptr;
-+		free_pd->next_pd_ptr = NULL;
-+	}
-+	return free_pd;
-+}
-+
-+static void usb_put_free_pd(struct cppi41 *cppi, struct usb_pkt_desc *free_pd)
-+{
-+	free_pd->next_pd_ptr = cppi->pd_pool_head;
-+	cppi->pd_pool_head = free_pd;
-+}
-+
-+/**
-+ * cppi41_controller_start - start DMA controller
-+ * @controller: the controller
-+ *
-+ * This function initializes the CPPI 4.1 Tx/Rx channels.
-+ */
-+static int __devinit cppi41_controller_start(struct dma_controller *controller)
-+{
-+	struct cppi41 *cppi;
-+	struct cppi41_channel *cppi_ch;
-+	void __iomem *reg_base;
-+	struct usb_pkt_desc *curr_pd;
-+	unsigned long pd_addr;
-+	int i;
-+	struct usb_cppi41_info *cppi_info;
-+	struct musb *musb;
-+
-+	cppi = container_of(controller, struct cppi41, controller);
-+	cppi_info = cppi->cppi_info;
-+	musb = cppi->musb;
-+
-+	if (cpu_is_ti816x() || cpu_is_am33xx()) {
-+		cppi->automode_reg_offs = TI81XX_USB_AUTOREQ_REG;
-+		cppi->teardown_reg_offs = TI81XX_USB_TEARDOWN_REG;
-+	} else {
-+		cppi->automode_reg_offs = USB_AUTOREQ_REG;
-+		cppi->teardown_reg_offs = USB_TEARDOWN_REG;
-+	}
-+
-+	/*
-+	 * TODO: We may need to check USB_CPPI41_MAX_PD here since CPPI 4.1
-+	 * requires the descriptor count to be a multiple of 2 ^ 5 (i.e. 32).
-+	 * Similarly, the descriptor size should also be a multiple of 32.
-+	 */
-+
-+	/*
-+	 * Allocate free packet descriptor pool for all Tx/Rx endpoints --
-+	 * dma_alloc_coherent()  will return a page aligned address, so our
-+	 * alignment requirement will be honored.
-+	 */
-+	cppi->bd_size = USB_CPPI41_MAX_PD * sizeof(struct usb_pkt_desc);
-+	cppi->pd_mem = dma_alloc_coherent(cppi->musb->controller,
-+					  cppi->bd_size,
-+					  &cppi->pd_mem_phys,
-+					  GFP_KERNEL | GFP_DMA);
-+	if (cppi->pd_mem == NULL) {
-+		dev_dbg(musb->controller, "ERROR: packet descriptor memory allocation failed\n");
-+		return 0;
-+	}
-+
-+	if (cppi41_mem_rgn_alloc(cppi_info->q_mgr, cppi->pd_mem_phys,
-+				 USB_CPPI41_DESC_SIZE_SHIFT,
-+				 get_count_order(USB_CPPI41_MAX_PD),
-+				 &cppi->pd_mem_rgn)) {
-+		dev_dbg(musb->controller, "ERROR: queue manager memory region allocation "
-+		    "failed\n");
-+		goto free_pds;
-+	}
-+
-+	/* Allocate the teardown completion queue */
-+	if (cppi41_queue_alloc(CPPI41_UNASSIGNED_QUEUE,
-+			       0, &cppi->teardownQNum)) {
-+		dev_dbg(musb->controller, "ERROR: teardown completion queue allocation failed\n");
-+		goto free_mem_rgn;
-+	}
-+	dev_dbg(musb->controller, "Allocated teardown completion queue %d in queue manager 0\n",
-+	    cppi->teardownQNum);
-+
-+	if (cppi41_queue_init(&cppi->queue_obj, 0, cppi->teardownQNum)) {
-+		dev_dbg(musb->controller, "ERROR: teardown completion queue initialization "
-+		    "failed\n");
-+		goto free_queue;
-+	}
-+
-+	/*
-+	 * "Slice" PDs one-by-one from the big chunk and
-+	 * add them to the free pool.
-+	 */
-+	curr_pd = (struct usb_pkt_desc *)cppi->pd_mem;
-+	pd_addr = cppi->pd_mem_phys;
-+	for (i = 0; i < USB_CPPI41_MAX_PD; i++) {
-+		curr_pd->dma_addr = pd_addr;
-+
-+		usb_put_free_pd(cppi, curr_pd);
-+		curr_pd = (struct usb_pkt_desc *)((char *)curr_pd +
-+						  USB_CPPI41_DESC_ALIGN);
-+		pd_addr += USB_CPPI41_DESC_ALIGN;
-+	}
-+
-+	/* Configure the Tx channels */
-+	for (i = 0, cppi_ch = cppi->tx_cppi_ch;
-+	     i < ARRAY_SIZE(cppi->tx_cppi_ch); ++i, ++cppi_ch) {
-+		const struct cppi41_tx_ch *tx_info;
-+
-+		memset(cppi_ch, 0, sizeof(struct cppi41_channel));
-+		cppi_ch->transmit = 1;
-+		cppi_ch->ch_num = i;
-+		cppi_ch->channel.private_data = cppi;
-+
-+		/*
-+		 * Extract the CPPI 4.1 DMA Tx channel configuration and
-+		 * construct/store the Tx PD tag info field for later use...
-+		 */
-+		tx_info = cppi41_dma_block[cppi_info->dma_block].tx_ch_info
-+			  + cppi_info->ep_dma_ch[i];
-+		cppi_ch->src_queue = tx_info->tx_queue[0];
-+		cppi_ch->tag_info = (tx_info->port_num <<
-+				     CPPI41_SRC_TAG_PORT_NUM_SHIFT) |
-+				    (tx_info->ch_num <<
-+				     CPPI41_SRC_TAG_CH_NUM_SHIFT) |
-+				    (tx_info->sub_ch_num <<
-+				     CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT);
-+	}
-+
-+	/* Configure the Rx channels */
-+	for (i = 0, cppi_ch = cppi->rx_cppi_ch;
-+	     i < ARRAY_SIZE(cppi->rx_cppi_ch); ++i, ++cppi_ch) {
-+		memset(cppi_ch, 0, sizeof(struct cppi41_channel));
-+		cppi_ch->ch_num = i;
-+		cppi_ch->channel.private_data = cppi;
-+	}
-+
-+	/* Construct/store Tx PD packet info field for later use */
-+	cppi->pkt_info = (CPPI41_PKT_TYPE_USB << CPPI41_PKT_TYPE_SHIFT) |
-+			 (CPPI41_RETURN_LINKED << CPPI41_RETURN_POLICY_SHIFT);
-+
-+	/* Do necessary configuartion in hardware to get started */
-+	reg_base = cppi->musb->ctrl_base;
-+
-+	/* Disable auto request mode */
-+	musb_writel(reg_base, cppi->automode_reg_offs, 0);
-+
-+	/* Disable the CDC/RNDIS modes */
-+	musb_writel(reg_base, USB_TX_MODE_REG, 0);
-+	musb_writel(reg_base, USB_RX_MODE_REG, 0);
-+
-+	return 1;
-+
-+ free_queue:
-+	if (cppi41_queue_free(0, cppi->teardownQNum))
-+		dev_dbg(musb->controller, "ERROR: failed to free teardown completion queue\n");
-+
-+ free_mem_rgn:
-+	if (cppi41_mem_rgn_free(cppi_info->q_mgr, cppi->pd_mem_rgn))
-+		dev_dbg(musb->controller, "ERROR: failed to free queue manager memory region\n");
-+
-+ free_pds:
-+	dma_free_coherent(cppi->musb->controller,
-+			  cppi->bd_size,
-+			  cppi->pd_mem, cppi->pd_mem_phys);
-+
-+	return 0;
-+}
-+
-+/**
-+ * cppi41_controller_stop - stop DMA controller
-+ * @controller: the controller
-+ *
-+ * De-initialize the DMA Controller as necessary.
-+ */
-+static int cppi41_controller_stop(struct dma_controller *controller)
-+{
-+	struct cppi41 *cppi;
-+	void __iomem *reg_base;
-+	struct usb_cppi41_info *cppi_info;
-+	struct musb *musb;
-+
-+	cppi = container_of(controller, struct cppi41, controller);
-+	cppi_info = cppi->cppi_info;
-+	musb = cppi->musb;
-+
-+	/* Free the teardown completion queue */
-+	if (cppi41_queue_free(cppi_info->q_mgr, cppi->teardownQNum))
-+		dev_dbg(musb->controller, "ERROR: failed to free teardown completion queue\n");
-+
-+	/*
-+	 * Free the packet descriptor region allocated
-+	 * for all Tx/Rx channels.
-+	 */
-+	if (cppi41_mem_rgn_free(cppi_info->q_mgr, cppi->pd_mem_rgn))
-+		dev_dbg(musb->controller, "ERROR: failed to free queue manager memory region\n");
-+
-+	dma_free_coherent(cppi->musb->controller, cppi->bd_size,
-+			  cppi->pd_mem, cppi->pd_mem_phys);
-+
-+	cppi->pd_mem = 0;
-+	cppi->pd_mem_phys = 0;
-+	cppi->pd_pool_head = 0;
-+	cppi->bd_size = 0;
-+
-+	reg_base = cppi->musb->ctrl_base;
-+
-+	/* Disable auto request mode */
-+	musb_writel(reg_base, cppi->automode_reg_offs, 0);
-+
-+	/* Disable the CDC/RNDIS modes */
-+	musb_writel(reg_base, USB_TX_MODE_REG, 0);
-+	musb_writel(reg_base, USB_RX_MODE_REG, 0);
-+
-+	return 1;
-+}
-+
-+/**
-+ * cppi41_channel_alloc - allocate a CPPI channel for DMA.
-+ * @controller: the controller
-+ * @ep:		the endpoint
-+ * @is_tx:	1 for Tx channel, 0 for Rx channel
-+ *
-+ * With CPPI, channels are bound to each transfer direction of a non-control
-+ * endpoint, so allocating (and deallocating) is mostly a way to notice bad
-+ * housekeeping on the software side.  We assume the IRQs are always active.
-+ */
-+static struct dma_channel *cppi41_channel_alloc(struct dma_controller
-+						*controller,
-+						struct musb_hw_ep *ep, u8 is_tx)
-+{
-+	struct cppi41 *cppi;
-+	struct cppi41_channel  *cppi_ch;
-+	u32 ch_num, ep_num = ep->epnum;
-+	struct usb_cppi41_info *cppi_info;
-+	struct musb *musb;
-+
-+	cppi = container_of(controller, struct cppi41, controller);
-+	cppi_info = cppi->cppi_info;
-+	musb = cppi->musb;
-+
-+	/* Remember, ep_num: 1 .. Max_EP, and CPPI ch_num: 0 .. Max_EP - 1 */
-+	ch_num = ep_num - 1;
-+
-+	if (ep_num > USB_CPPI41_NUM_CH) {
-+		dev_dbg(musb->controller, "No %cx DMA channel for EP%d\n",
-+		    is_tx ? 'T' : 'R', ep_num);
-+		return NULL;
-+	}
-+
-+	cppi_ch = (is_tx ? cppi->tx_cppi_ch : cppi->rx_cppi_ch) + ch_num;
-+
-+	/* As of now, just return the corresponding CPPI 4.1 channel handle */
-+	if (is_tx) {
-+		/* Initialize the CPPI 4.1 Tx DMA channel */
-+		if (cppi41_tx_ch_init(&cppi_ch->dma_ch_obj,
-+				      cppi_info->dma_block,
-+				      cppi_info->ep_dma_ch[ch_num])) {
-+			dev_dbg(musb->controller, "ERROR: cppi41_tx_ch_init failed for "
-+			    "channel %d\n", ch_num);
-+			return NULL;
-+		}
-+		/*
-+		 * Teardown descriptors will be pushed to the dedicated
-+		 * completion queue.
-+		 */
-+		cppi41_dma_ch_default_queue(&cppi_ch->dma_ch_obj,
-+					    0, cppi->teardownQNum);
-+	} else {
-+		struct cppi41_rx_ch_cfg rx_cfg;
-+		u8 q_mgr = cppi_info->q_mgr;
-+		int i;
-+
-+		/* Initialize the CPPI 4.1 Rx DMA channel */
-+		if (cppi41_rx_ch_init(&cppi_ch->dma_ch_obj,
-+				      cppi_info->dma_block,
-+				      cppi_info->ep_dma_ch[ch_num])) {
-+			dev_dbg(musb->controller, "ERROR: cppi41_rx_ch_init failed\n");
-+			return NULL;
-+		}
-+
-+		if (cppi41_queue_alloc(CPPI41_FREE_DESC_BUF_QUEUE |
-+				       CPPI41_UNASSIGNED_QUEUE,
-+				       q_mgr, &cppi_ch->src_queue.q_num)) {
-+			dev_dbg(musb->controller, "ERROR: cppi41_queue_alloc failed for "
-+			    "free descriptor/buffer queue\n");
-+			return NULL;
-+		}
-+		dev_dbg(musb->controller, "Allocated free descriptor/buffer queue %d in "
-+		    "queue manager %d\n", cppi_ch->src_queue.q_num, q_mgr);
-+
-+		rx_cfg.default_desc_type = cppi41_rx_host_desc;
-+		rx_cfg.sop_offset = 0;
-+		rx_cfg.retry_starved = 1;
-+		rx_cfg.rx_max_buf_cnt = 0;
-+		rx_cfg.rx_queue.q_mgr = cppi_ch->src_queue.q_mgr = q_mgr;
-+		rx_cfg.rx_queue.q_num = cppi_info->rx_comp_q[ch_num];
-+		for (i = 0; i < 4; i++)
-+			rx_cfg.cfg.host_pkt.fdb_queue[i] = cppi_ch->src_queue;
-+		cppi41_rx_ch_configure(&cppi_ch->dma_ch_obj, &rx_cfg);
-+	}
-+
-+	/* Initialize the CPPI 4.1 DMA source queue */
-+	if (cppi41_queue_init(&cppi_ch->queue_obj, cppi_ch->src_queue.q_mgr,
-+			       cppi_ch->src_queue.q_num)) {
-+		dev_dbg(musb->controller, "ERROR: cppi41_queue_init failed for %s queue",
-+		    is_tx ? "Tx" : "Rx free descriptor/buffer");
-+		if (is_tx == 0 &&
-+		    cppi41_queue_free(cppi_ch->src_queue.q_mgr,
-+				      cppi_ch->src_queue.q_num))
-+			dev_dbg(musb->controller, "ERROR: failed to free Rx descriptor/buffer "
-+			    "queue\n");
-+		 return NULL;
-+	}
-+
-+	/* Enable the DMA channel */
-+	cppi41_dma_ch_enable(&cppi_ch->dma_ch_obj);
-+
-+	if (cppi_ch->end_pt)
-+		dev_dbg(musb->controller, "Re-allocating DMA %cx channel %d (%p)\n",
-+		    is_tx ? 'T' : 'R', ch_num, cppi_ch);
-+
-+	cppi_ch->end_pt = ep;
-+	cppi_ch->ch_num = ch_num;
-+	cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
-+	cppi_ch->channel.max_len = is_tx ?
-+				CPPI41_TXDMA_MAXLEN : CPPI41_RXDMA_MAXLEN;
-+
-+	dev_dbg(musb->controller, "Allocated DMA %cx channel %d for EP%d\n", is_tx ? 'T' : 'R',
-+	    ch_num, ep_num);
-+
-+	return &cppi_ch->channel;
-+}
-+
-+/**
-+ * cppi41_channel_release - release a CPPI DMA channel
-+ * @channel: the channel
-+ */
-+static void cppi41_channel_release(struct dma_channel *channel)
-+{
-+	struct cppi41_channel *cppi_ch;
-+
-+	/* REVISIT: for paranoia, check state and abort if needed... */
-+	cppi_ch = container_of(channel, struct cppi41_channel, channel);
-+
-+	if (cppi_ch->end_pt == NULL)
-+		printk(KERN_INFO "Releasing idle DMA channel %p\n", cppi_ch);
-+
-+	/* But for now, not its IRQ */
-+	cppi_ch->end_pt = NULL;
-+	channel->status = MUSB_DMA_STATUS_UNKNOWN;
-+
-+	cppi41_dma_ch_disable(&cppi_ch->dma_ch_obj);
-+
-+	/* De-allocate Rx free descriptior/buffer queue */
-+	if (cppi_ch->transmit == 0 &&
-+	    cppi41_queue_free(cppi_ch->src_queue.q_mgr,
-+			      cppi_ch->src_queue.q_num))
-+		printk(KERN_ERR "ERROR: failed to free Rx descriptor/buffer queue\n");
-+}
-+
-+static void cppi41_mode_update(struct cppi41_channel *cppi_ch, u8 mode)
-+{
-+	if (mode != cppi_ch->dma_mode) {
-+		struct cppi41 *cppi = cppi_ch->channel.private_data;
-+		void *__iomem reg_base = cppi->musb->ctrl_base;
-+		u32 reg_val;
-+		u8 ep_num = cppi_ch->ch_num + 1;
-+
-+		if (cppi_ch->transmit) {
-+			reg_val = musb_readl(reg_base, USB_TX_MODE_REG);
-+			reg_val &= ~USB_TX_MODE_MASK(ep_num);
-+			reg_val |= mode << USB_TX_MODE_SHIFT(ep_num);
-+			musb_writel(reg_base, USB_TX_MODE_REG, reg_val);
-+		} else {
-+			reg_val = musb_readl(reg_base, USB_RX_MODE_REG);
-+			reg_val &= ~USB_RX_MODE_MASK(ep_num);
-+			reg_val |= mode << USB_RX_MODE_SHIFT(ep_num);
-+			musb_writel(reg_base, USB_RX_MODE_REG, reg_val);
-+		}
-+		cppi_ch->dma_mode = mode;
-+	}
-+}
-+
-+/*
-+ * CPPI 4.1 Tx:
-+ * ============
-+ * Tx is a lot more reasonable than Rx: RNDIS mode seems to behave well except
-+ * how it handles the exactly-N-packets case. It appears that there's a hiccup
-+ * in that case (maybe the DMA completes before a ZLP gets written?) boiling
-+ * down to not being able to rely on the XFER DMA writing any terminating zero
-+ * length packet before the next transfer is started...
-+ *
-+ * The generic RNDIS mode does not have this misfeature, so we prefer using it
-+ * instead.  We then send the terminating ZLP *explictly* using DMA instead of
-+ * doing it by PIO after an IRQ.
-+ *
-+ */
-+
-+/**
-+ * cppi41_next_tx_segment - DMA write for the next chunk of a buffer
-+ * @tx_ch:	Tx channel
-+ *
-+ * Context: controller IRQ-locked
-+ */
-+static unsigned cppi41_next_tx_segment(struct cppi41_channel *tx_ch)
-+{
-+	struct cppi41 *cppi = tx_ch->channel.private_data;
-+	struct musb *musb = cppi->musb;
-+	struct usb_pkt_desc *curr_pd;
-+	u32 length = tx_ch->length - tx_ch->curr_offset;
-+	u32 pkt_size = tx_ch->pkt_size;
-+	unsigned num_pds, n;
-+	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
-+	u16 q_mgr = cppi_info->q_mgr;
-+	u16 tx_comp_q = cppi_info->tx_comp_q[tx_ch->ch_num];
-+	u8 en_bd_intr = cppi->en_bd_intr;
-+
-+	/*
-+	 * Tx can use the generic RNDIS mode where we can probably fit this
-+	 * transfer in one PD and one IRQ.  The only time we would NOT want
-+	 * to use it is when the hardware constraints prevent it...
-+	 */
-+	if ((pkt_size & 0x3f) == 0) {
-+		num_pds  = length ? 1 : 0;
-+		cppi41_mode_update(tx_ch, USB_GENERIC_RNDIS_MODE);
-+	} else {
-+		num_pds  = (length + pkt_size - 1) / pkt_size;
-+		cppi41_mode_update(tx_ch, USB_TRANSPARENT_MODE);
-+	}
-+
-+	pkt_size = length;
-+	/*
-+	 * If length of transmit buffer is 0 or a multiple of the endpoint size,
-+	 * then send the zero length packet.
-+	 */
-+	if (!length || (tx_ch->transfer_mode && length % pkt_size == 0))
-+		num_pds++;
-+
-+	dev_dbg(musb->controller, "TX DMA%u, %s, maxpkt %u, %u PDs, addr %#x, len %u\n",
-+	    tx_ch->ch_num, tx_ch->dma_mode ? "accelerated" : "transparent",
-+	    pkt_size, num_pds, tx_ch->start_addr + tx_ch->curr_offset, length);
-+
-+	for (n = 0; n < num_pds; n++) {
-+		struct cppi41_host_pkt_desc *hw_desc;
-+
-+		/* Get Tx host packet descriptor from the free pool */
-+		curr_pd = usb_get_free_pd(cppi);
-+		if (curr_pd == NULL) {
-+			dev_dbg(musb->controller, "No Tx PDs\n");
-+			break;
-+		}
-+
-+		if (length < pkt_size)
-+			pkt_size = length;
-+
-+		hw_desc = &curr_pd->hw_desc;
-+		hw_desc->desc_info = (CPPI41_DESC_TYPE_HOST <<
-+				      CPPI41_DESC_TYPE_SHIFT) | pkt_size;
-+		hw_desc->tag_info = tx_ch->tag_info;
-+		hw_desc->pkt_info = cppi->pkt_info;
-+		hw_desc->pkt_info |= ((q_mgr << CPPI41_RETURN_QMGR_SHIFT) |
-+				(tx_comp_q << CPPI41_RETURN_QNUM_SHIFT));
-+
-+		hw_desc->buf_ptr = tx_ch->start_addr + tx_ch->curr_offset;
-+		hw_desc->buf_len = pkt_size;
-+		hw_desc->next_desc_ptr = 0;
-+		hw_desc->orig_buf_len = pkt_size;
-+
-+		curr_pd->ch_num = tx_ch->ch_num;
-+		curr_pd->ep_num = tx_ch->end_pt->epnum;
-+
-+		tx_ch->curr_offset += pkt_size;
-+		length -= pkt_size;
-+
-+		if (pkt_size == 0)
-+			tx_ch->zlp_queued = 1;
-+
-+		if (en_bd_intr)
-+			hw_desc->orig_buf_len |= CPPI41_PKT_INTR_FLAG;
-+
-+		dev_dbg(musb->controller, "TX PD %p: buf %08x, len %08x, pkt info %08x\n", curr_pd,
-+		    hw_desc->buf_ptr, hw_desc->buf_len, hw_desc->pkt_info);
-+
-+		cppi41_queue_push(&tx_ch->queue_obj, curr_pd->dma_addr,
-+				  USB_CPPI41_DESC_ALIGN, pkt_size);
-+	}
-+
-+	return n;
-+}
-+
-+static void cppi41_autoreq_update(struct cppi41_channel *rx_ch, u8 autoreq)
-+{
-+	struct cppi41 *cppi = rx_ch->channel.private_data;
-+
-+	if (is_host_active(cppi->musb) &&
-+	    autoreq != rx_ch->autoreq) {
-+		void *__iomem reg_base = cppi->musb->ctrl_base;
-+		u32 reg_val = musb_readl(reg_base, cppi->automode_reg_offs);
-+		u8 ep_num = rx_ch->ch_num + 1;
-+
-+		reg_val &= ~USB_RX_AUTOREQ_MASK(ep_num);
-+		reg_val |= autoreq << USB_RX_AUTOREQ_SHIFT(ep_num);
-+
-+		musb_writel(reg_base, cppi->automode_reg_offs, reg_val);
-+		rx_ch->autoreq = autoreq;
-+	}
-+}
-+
-+static void cppi41_set_ep_size(struct cppi41_channel *rx_ch, u32 pkt_size)
-+{
-+	struct cppi41 *cppi = rx_ch->channel.private_data;
-+	void *__iomem reg_base = cppi->musb->ctrl_base;
-+	u8 ep_num = rx_ch->ch_num + 1;
-+	u32 res = pkt_size % 64;
-+
-+	/* epsize register must be multiple of 64 */
-+	pkt_size += res ? (64 - res) : res;
-+
-+	musb_writel(reg_base, USB_GENERIC_RNDIS_EP_SIZE_REG(ep_num), pkt_size);
-+}
-+
-+/*
-+ * CPPI 4.1 Rx:
-+ * ============
-+ * Consider a 1KB bulk Rx buffer in two scenarios: (a) it's fed two 300 byte
-+ * packets back-to-back, and (b) it's fed two 512 byte packets back-to-back.
-+ * (Full speed transfers have similar scenarios.)
-+ *
-+ * The correct behavior for Linux is that (a) fills the buffer with 300 bytes,
-+ * and the next packet goes into a buffer that's queued later; while (b) fills
-+ * the buffer with 1024 bytes.  How to do that with accelerated DMA modes?
-+ *
-+ * Rx queues in RNDIS mode (one single BD) handle (a) correctly but (b) loses
-+ * BADLY because nothing (!) happens when that second packet fills the buffer,
-+ * much less when a third one arrives -- which makes it not a "true" RNDIS mode.
-+ * In the RNDIS protocol short-packet termination is optional, and it's fine if
-+ * the peripherals (not hosts!) pad the messages out to end of buffer. Standard
-+ * PCI host controller DMA descriptors implement that mode by default... which
-+ * is no accident.
-+ *
-+ * Generic RNDIS mode is the only way to reliably make both cases work.  This
-+ * mode is identical to the "normal" RNDIS mode except for the case where the
-+ * last packet of the segment matches the max USB packet size -- in this case,
-+ * the packet will be closed when a value (0x10000 max) in the Generic RNDIS
-+ * EP Size register is reached.  This mode will work for the network drivers
-+ * (CDC/RNDIS) as well as for the mass storage drivers where there is no short
-+ * packet.
-+ *
-+ * BUT we can only use non-transparent modes when USB packet size is a multiple
-+ * of 64 bytes. Let's see what happens when  this is not the case...
-+ *
-+ * Rx queues (2 BDs with 512 bytes each) have converse problems to RNDIS mode:
-+ * (b) is handled right but (a) loses badly.  DMA doesn't stop after receiving
-+ * a short packet and processes both of those PDs; so both packets are loaded
-+ * into the buffer (with 212 byte gap between them), and the next buffer queued
-+ * will NOT get its 300 bytes of data.  Even in the case when there should be
-+ * no short packets (URB_SHORT_NOT_OK is set), queueing several packets in the
-+ * host mode doesn't win us anything since we have to manually "prod" the Rx
-+ * process after each packet is received by setting ReqPkt bit in endpoint's
-+ * RXCSR; in the peripheral mode without short packets, queueing could be used
-+ * BUT we'll have to *teardown* the channel if a short packet still arrives in
-+ * the peripheral mode, and to "collect" the left-over packet descriptors from
-+ * the free descriptor/buffer queue in both cases...
-+ *
-+ * One BD at a time is the only way to make make both cases work reliably, with
-+ * software handling both cases correctly, at the significant penalty of needing
-+ * an IRQ per packet.  (The lack of I/O overlap can be slightly ameliorated by
-+ * enabling double buffering.)
-+ *
-+ * There seems to be no way to identify for sure the cases where the CDC mode
-+ * is appropriate...
-+ *
-+ */
-+
-+/**
-+ * cppi41_next_rx_segment - DMA read for the next chunk of a buffer
-+ * @rx_ch:	Rx channel
-+ *
-+ * Context: controller IRQ-locked
-+ *
-+ * NOTE: In the transparent mode, we have to queue one packet at a time since:
-+ *	 - we must avoid starting reception of another packet after receiving
-+ *	   a short packet;
-+ *	 - in host mode we have to set ReqPkt bit in the endpoint's RXCSR after
-+ *	   receiving each packet but the last one... ugly!
-+ */
-+static unsigned cppi41_next_rx_segment(struct cppi41_channel *rx_ch)
-+{
-+	struct cppi41 *cppi = rx_ch->channel.private_data;
-+	struct musb *musb = cppi->musb;
-+	struct usb_pkt_desc *curr_pd;
-+	struct cppi41_host_pkt_desc *hw_desc;
-+	u32 length = rx_ch->length - rx_ch->curr_offset;
-+	u32 pkt_size = rx_ch->pkt_size;
-+	u32 max_rx_transfer_size = 64 * 1024;
-+	u32 i, n_bd , pkt_len;
-+	struct usb_gadget_driver *gadget_driver;
-+	u8 en_bd_intr = cppi->en_bd_intr, mode;
-+
-+	if (is_peripheral_active(cppi->musb)) {
-+		/* TODO: temporary fix for CDC/RNDIS which needs to be in
-+		 * GENERIC_RNDIS mode. Without this RNDIS gadget taking
-+		 * more then 2K ms for a 64 byte pings.
-+		 */
-+		gadget_driver = cppi->musb->gadget_driver;
-+
-+		pkt_len = rx_ch->pkt_size;
-+		mode = USB_GENERIC_RNDIS_MODE;
-+		if (!strcmp(gadget_driver->driver.name, "g_file_storage") ||
-+			!strcmp(gadget_driver->driver.name, "g_mass_storage")) {
-+			if (cppi->inf_mode && length > pkt_len) {
-+				pkt_len = 0;
-+				length = length - rx_ch->pkt_size;
-+				cppi41_rx_ch_set_maxbufcnt(&rx_ch->dma_ch_obj,
-+					DMA_CH_RX_MAX_BUF_CNT_1);
-+				rx_ch->inf_mode = 1;
-+			} else {
-+				max_rx_transfer_size = rx_ch->pkt_size;
-+				mode = USB_TRANSPARENT_MODE;
-+			}
-+		} else
-+			if (rx_ch->length < max_rx_transfer_size)
-+				pkt_len = rx_ch->length;
-+
-+		if (mode != USB_TRANSPARENT_MODE)
-+			cppi41_set_ep_size(rx_ch, pkt_len);
-+		cppi41_mode_update(rx_ch, mode);
-+	} else {
-+		/*
-+		 * Rx can use the generic RNDIS mode where we can
-+		 * probably fit this transfer in one PD and one IRQ
-+		 * (or two with a short packet).
-+		 */
-+		if ((pkt_size & 0x3f) == 0) {
-+			cppi41_mode_update(rx_ch, USB_GENERIC_RNDIS_MODE);
-+			cppi41_autoreq_update(rx_ch, USB_AUTOREQ_ALL_BUT_EOP);
-+
-+			pkt_size = (length > 0x10000) ? 0x10000 : length;
-+			cppi41_set_ep_size(rx_ch, pkt_size);
-+		} else {
-+			cppi41_mode_update(rx_ch, USB_TRANSPARENT_MODE);
-+			cppi41_autoreq_update(rx_ch, USB_NO_AUTOREQ);
-+			max_rx_transfer_size = rx_ch->hb_mult * rx_ch->pkt_size;
-+		}
-+	}
-+
-+	dev_dbg(musb->controller, "RX DMA%u, %s, maxpkt %u, addr %#x, rec'd %u/%u\n",
-+	    rx_ch->ch_num, rx_ch->dma_mode ? "accelerated" : "transparent",
-+	    pkt_size, rx_ch->start_addr + rx_ch->curr_offset,
-+	    rx_ch->curr_offset, rx_ch->length);
-+
-+	/* calculate number of bd required */
-+	n_bd = (length + max_rx_transfer_size - 1)/max_rx_transfer_size;
-+
-+	for (i = 0; i < n_bd ; ++i) {
-+		/* Get Rx packet descriptor from the free pool */
-+		curr_pd = usb_get_free_pd(cppi);
-+		if (curr_pd == NULL) {
-+			/* Shouldn't ever happen! */
-+			dev_dbg(musb->controller, "No Rx PDs\n");
-+			goto sched;
-+		}
-+
-+		pkt_len =
-+		(length > max_rx_transfer_size) ? max_rx_transfer_size : length;
-+
-+		hw_desc = &curr_pd->hw_desc;
-+		hw_desc->desc_info = (CPPI41_DESC_TYPE_HOST <<
-+				      CPPI41_DESC_TYPE_SHIFT);
-+		hw_desc->orig_buf_ptr = rx_ch->start_addr + rx_ch->curr_offset;
-+		hw_desc->orig_buf_len = pkt_len;
-+
-+		/* buf_len field of buffer descriptor updated by dma
-+		 * after reception of data is completed
-+		 */
-+		hw_desc->buf_len = 0;
-+
-+		curr_pd->ch_num = rx_ch->ch_num;
-+		curr_pd->ep_num = rx_ch->end_pt->epnum;
-+
-+		curr_pd->eop = (length -= pkt_len) ? 0 : 1;
-+		rx_ch->curr_offset += pkt_len;
-+
-+		if (en_bd_intr)
-+			hw_desc->orig_buf_len |= CPPI41_PKT_INTR_FLAG;
-+		/*
-+		 * Push the free Rx packet descriptor
-+		 * to the free descriptor/buffer queue.
-+		 */
-+		cppi41_queue_push(&rx_ch->queue_obj, curr_pd->dma_addr,
-+			USB_CPPI41_DESC_ALIGN, 0);
-+	}
-+
-+sched:
-+	/*
-+	 * HCD arranged ReqPkt for the first packet.
-+	 * We arrange it for all but the last one.
-+	 */
-+	if (is_host_active(cppi->musb) && rx_ch->channel.actual_len) {
-+		void __iomem *epio = rx_ch->end_pt->regs;
-+		u16 csr = musb_readw(epio, MUSB_RXCSR);
-+
-+		csr |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
-+		musb_writew(epio, MUSB_RXCSR, csr);
-+	}
-+
-+	/* enable schedular if not enabled */
-+	if (is_peripheral_active(cppi->musb) && (n_bd > 0))
-+		cppi41_schedtbl_add_dma_ch(0, 0, rx_ch->ch_num, 0);
-+	return 1;
-+}
-+
-+/**
-+ * cppi41_channel_program - program channel for data transfer
-+ * @channel:	the channel
-+ * @maxpacket:	max packet size
-+ * @mode:	for Rx, 1 unless the USB protocol driver promised to treat
-+ *		all short reads as errors and kick in high level fault recovery;
-+ *		for Tx, 0 unless the protocol driver _requires_ short-packet
-+ *		termination mode
-+ * @dma_addr:	DMA address of buffer
-+ * @length:	length of buffer
-+ *
-+ * Context: controller IRQ-locked
-+ */
-+static int cppi41_channel_program(struct dma_channel *channel,	u16 maxpacket,
-+				  u8 mode, dma_addr_t dma_addr, u32 length)
-+{
-+	struct cppi41_channel *cppi_ch;
-+	unsigned queued;
-+
-+	cppi_ch = container_of(channel, struct cppi41_channel, channel);
-+
-+	switch (channel->status) {
-+	case MUSB_DMA_STATUS_BUS_ABORT:
-+	case MUSB_DMA_STATUS_CORE_ABORT:
-+		/* Fault IRQ handler should have handled cleanup */
-+		WARNING("%cx DMA%d not cleaned up after abort!\n",
-+			cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
-+		break;
-+	case MUSB_DMA_STATUS_BUSY:
-+		WARNING("Program active channel? %cx DMA%d\n",
-+			cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
-+		break;
-+	case MUSB_DMA_STATUS_UNKNOWN:
-+		WARNING("%cx DMA%d not allocated!\n",
-+		    cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
-+		return 0;
-+	case MUSB_DMA_STATUS_FREE:
-+		break;
-+	}
-+
-+	channel->status = MUSB_DMA_STATUS_BUSY;
-+
-+	/* Set the transfer parameters, then queue up the first segment */
-+	cppi_ch->start_addr = dma_addr;
-+	cppi_ch->curr_offset = 0;
-+	cppi_ch->hb_mult = (maxpacket >> 11) & 0x03;
-+	cppi_ch->pkt_size = maxpacket & 0x7ff;
-+	cppi_ch->length = length;
-+	cppi_ch->transfer_mode = mode;
-+	cppi_ch->zlp_queued = 0;
-+	cppi_ch->channel.actual_len = 0;
-+
-+	/* Tx or Rx channel? */
-+	if (cppi_ch->transmit)
-+		queued = cppi41_next_tx_segment(cppi_ch);
-+	else
-+		queued = cppi41_next_rx_segment(cppi_ch);
-+
-+	return	queued > 0;
-+}
-+
-+static struct usb_pkt_desc *usb_get_pd_ptr(struct cppi41 *cppi,
-+					   unsigned long pd_addr)
-+{
-+	if (pd_addr >= cppi->pd_mem_phys && pd_addr < cppi->pd_mem_phys +
-+	    USB_CPPI41_MAX_PD * USB_CPPI41_DESC_ALIGN)
-+		return pd_addr - cppi->pd_mem_phys + cppi->pd_mem;
-+	else
-+		return NULL;
-+}
-+
-+static int usb_check_teardown(struct cppi41_channel *cppi_ch,
-+			      unsigned long pd_addr)
-+{
-+	u32 info;
-+	struct cppi41 *cppi = cppi_ch->channel.private_data;
-+	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
-+	struct musb *musb = cppi->musb;
-+
-+	if (cppi41_get_teardown_info(pd_addr, &info)) {
-+		dev_dbg(musb->controller, "ERROR: not a teardown descriptor\n");
-+		return 0;
-+	}
-+
-+	if ((info & CPPI41_TEARDOWN_TX_RX_MASK) ==
-+	    (!cppi_ch->transmit << CPPI41_TEARDOWN_TX_RX_SHIFT) &&
-+	    (info & CPPI41_TEARDOWN_DMA_NUM_MASK) ==
-+	    (cppi_info->dma_block << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &&
-+	    (info & CPPI41_TEARDOWN_CHAN_NUM_MASK) ==
-+	    (cppi_info->ep_dma_ch[cppi_ch->ch_num] <<
-+	     CPPI41_TEARDOWN_CHAN_NUM_SHIFT))
-+		return 1;
-+
-+	dev_dbg(musb->controller, "ERROR: unexpected values in teardown descriptor\n");
-+	return 0;
-+}
-+
-+/*
-+ * We can't handle the channel teardown via the default completion queue in
-+ * context of the controller IRQ-locked, so we use the dedicated teardown
-+ * completion queue which we can just poll for a teardown descriptor, not
-+ * interfering with the Tx completion queue processing.
-+ */
-+static void usb_tx_ch_teardown(struct cppi41_channel *tx_ch)
-+{
-+	struct cppi41 *cppi = tx_ch->channel.private_data;
-+	struct musb *musb = cppi->musb;
-+	void __iomem *reg_base = musb->ctrl_base;
-+	u32 td_reg, timeout = 0xfffff;
-+	u8 ep_num = tx_ch->ch_num + 1;
-+	unsigned long pd_addr;
-+	struct cppi41_queue_obj tx_queue_obj;
-+	struct usb_cppi41_info *cppi_info;
-+
-+	/* Initiate teardown for Tx DMA channel */
-+	cppi41_dma_ch_teardown(&tx_ch->dma_ch_obj);
-+
-+	/* Wait for a descriptor to be queued and pop it... */
-+	do {
-+		td_reg  = musb_readl(reg_base, cppi->teardown_reg_offs);
-+		td_reg |= USB_TX_TDOWN_MASK(ep_num);
-+		musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
-+
-+		pd_addr = cppi41_queue_pop(&cppi->queue_obj);
-+	} while (!pd_addr && timeout--);
-+
-+	if (pd_addr) {
-+
-+		dev_dbg(musb->controller, "Descriptor (%08lx) popped from teardown completion "
-+			"queue\n", pd_addr);
-+
-+		if (usb_check_teardown(tx_ch, pd_addr)) {
-+			dev_dbg(musb->controller, "Teardown Desc (%lx) rcvd\n", pd_addr);
-+		} else
-+			ERR("Invalid PD(%08lx)popped from TearDn completion"
-+				"queue\n", pd_addr);
-+	} else {
-+		if (timeout <= 0)
-+			ERR("Teardown Desc not rcvd\n");
-+	}
-+
-+	/* read the tx completion queue and remove
-+	 * completion bd if any
-+	 */
-+	cppi_info = cppi->cppi_info;
-+	if (cppi41_queue_init(&tx_queue_obj, cppi_info->q_mgr,
-+			      cppi_info->tx_comp_q[tx_ch->ch_num])) {
-+		ERR("ERROR: cppi41_queue_init failed for "
-+		    "Tx completion queue");
-+		return;
-+	}
-+
-+	while ((pd_addr = cppi41_queue_pop(&tx_queue_obj)) != 0) {
-+		struct usb_pkt_desc *curr_pd;
-+
-+		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
-+		if (curr_pd == NULL) {
-+			ERR("Invalid PD popped from Tx completion queue\n");
-+			continue;
-+		}
-+
-+		dev_dbg(musb->controller, "Tx-PD(%p) popped from completion queue\n", curr_pd);
-+		dev_dbg(musb->controller, "ch(%d)epnum(%d)len(%d)\n", curr_pd->ch_num,
-+			curr_pd->ep_num, curr_pd->hw_desc.buf_len);
-+
-+		usb_put_free_pd(cppi, curr_pd);
-+	}
-+}
-+
-+/*
-+ * For Rx DMA channels, the situation is more complex: there's only a single
-+ * completion queue for all our needs, so we have to temporarily redirect the
-+ * completed descriptors to our teardown completion queue, with a possibility
-+ * of a completed packet landing there as well...
-+ */
-+static void usb_rx_ch_teardown(struct cppi41_channel *rx_ch)
-+{
-+	struct cppi41 *cppi = rx_ch->channel.private_data;
-+	struct musb *musb = cppi->musb;
-+	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
-+	u32 timeout = 0xfffff, pd_addr;
-+	struct cppi41_queue_obj rx_queue_obj;
-+
-+	cppi41_dma_ch_default_queue(&rx_ch->dma_ch_obj, 0, cppi->teardownQNum);
-+
-+	/* Initiate teardown for Rx DMA channel */
-+	cppi41_dma_ch_teardown(&rx_ch->dma_ch_obj);
-+
-+	do {
-+		struct usb_pkt_desc *curr_pd;
-+		unsigned long pd_addr;
-+
-+		/* Wait for a descriptor to be queued and pop it... */
-+		do {
-+			pd_addr = cppi41_queue_pop(&cppi->queue_obj);
-+		} while (!pd_addr && timeout--);
-+
-+		if (timeout <= 0 || !pd_addr) {
-+			ERR("teardown Desc not found\n");
-+			break;
-+		}
-+
-+		dev_dbg(musb->controller, "Descriptor (%08lx) popped from teardown completion "
-+			"queue\n", pd_addr);
-+
-+		/*
-+		 * We might have popped a completed Rx PD, so check if the
-+		 * physical address is within the PD region first.  If it's
-+		 * not the case, it must be a teardown descriptor...
-+		 * */
-+		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
-+		if (curr_pd == NULL) {
-+			if (usb_check_teardown(rx_ch, pd_addr))
-+				break;
-+			continue;
-+		}
-+
-+		/* Paranoia: check if PD is from the right channel... */
-+		if (curr_pd->ch_num != rx_ch->ch_num) {
-+			ERR("Unexpected channel %d in Rx PD\n",
-+			    curr_pd->ch_num);
-+			continue;
-+		}
-+
-+		/* Extract the buffer length from the completed PD */
-+		rx_ch->channel.actual_len += curr_pd->hw_desc.buf_len;
-+
-+		/*
-+		 * Return Rx PDs to the software list --
-+		 * this is protected by critical section.
-+		 */
-+		usb_put_free_pd(cppi, curr_pd);
-+	} while (0);
-+
-+	/* read the rx completion queue and remove
-+	 * completion bd if any
-+	 */
-+	if (cppi41_queue_init(&rx_queue_obj, cppi_info->q_mgr,
-+			      cppi_info->rx_comp_q[rx_ch->ch_num])) {
-+		ERR("ERROR: cppi41_queue_init failed for "
-+		    "Rx completion queue");
-+		return;
-+	}
-+
-+	while ((pd_addr = cppi41_queue_pop(&rx_queue_obj)) != 0) {
-+		struct usb_pkt_desc *curr_pd;
-+
-+		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
-+		if (curr_pd == NULL) {
-+			ERR("Invalid PD popped from Rx completion queue\n");
-+			continue;
-+		}
-+
-+		dev_dbg(musb->controller, "Rx-PD(%p) popped from completion queue\n", curr_pd);
-+		dev_dbg(musb->controller, "ch(%d)epnum(%d)len(%d)\n", curr_pd->ch_num,
-+			curr_pd->ep_num, curr_pd->hw_desc.buf_len);
-+
-+		usb_put_free_pd(cppi, curr_pd);
-+	}
-+
-+	/* Now restore the default Rx completion queue... */
-+	cppi41_dma_ch_default_queue(&rx_ch->dma_ch_obj, cppi_info->q_mgr,
-+				    cppi_info->rx_comp_q[rx_ch->ch_num]);
-+}
-+
-+/*
-+ * cppi41_channel_abort
-+ *
-+ * Context: controller IRQ-locked, endpoint selected.
-+ */
-+static int cppi41_channel_abort(struct dma_channel *channel)
-+{
-+	struct cppi41 *cppi;
-+	struct cppi41_channel *cppi_ch;
-+	struct musb  *musb;
-+	void __iomem *reg_base, *epio;
-+	unsigned long pd_addr;
-+	u32 csr, td_reg;
-+	u8 ch_num, ep_num;
-+
-+	cppi_ch = container_of(channel, struct cppi41_channel, channel);
-+	ch_num = cppi_ch->ch_num;
-+	cppi = cppi_ch->channel.private_data;
-+	musb = cppi->musb;
-+
-+	switch (channel->status) {
-+	case MUSB_DMA_STATUS_BUS_ABORT:
-+	case MUSB_DMA_STATUS_CORE_ABORT:
-+		/* From Rx or Tx fault IRQ handler */
-+	case MUSB_DMA_STATUS_BUSY:
-+		/* The hardware needs shutting down... */
-+		dprintk("%s: DMA busy, status = %x\n",
-+			__func__, channel->status);
-+		break;
-+	case MUSB_DMA_STATUS_UNKNOWN:
-+		dev_dbg(musb->controller, "%cx DMA%d not allocated\n",
-+		    cppi_ch->transmit ? 'T' : 'R', ch_num);
-+		/* FALLTHROUGH */
-+	case MUSB_DMA_STATUS_FREE:
-+		return 0;
-+	}
-+
-+	reg_base = musb->ctrl_base;
-+	epio = cppi_ch->end_pt->regs;
-+	ep_num = ch_num + 1;
-+
-+#ifdef DEBUG_CPPI_TD
-+	printk("Before teardown:");
-+	print_pd_list(cppi->pd_pool_head);
-+#endif
-+
-+	if (cppi_ch->transmit) {
-+		dprintk("Tx channel teardown, cppi_ch = %p\n", cppi_ch);
-+
-+		/* Tear down Tx DMA channel */
-+		usb_tx_ch_teardown(cppi_ch);
-+
-+		/* Issue CPPI FIFO teardown for Tx channel */
-+		td_reg  = musb_readl(reg_base, cppi->teardown_reg_offs);
-+		td_reg |= USB_TX_TDOWN_MASK(ep_num);
-+		musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
-+
-+		/* Flush FIFO of the endpoint */
-+		csr  = musb_readw(epio, MUSB_TXCSR);
-+		csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_H_WZC_BITS;
-+		musb_writew(epio, MUSB_TXCSR, csr);
-+		musb_writew(epio, MUSB_TXCSR, csr);
-+		cppi_ch->tx_complete = 0;
-+	} else { /* Rx */
-+		dprintk("Rx channel teardown, cppi_ch = %p\n", cppi_ch);
-+
-+		/* Flush FIFO of the endpoint */
-+		csr  = musb_readw(epio, MUSB_RXCSR);
-+		csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_H_WZC_BITS;
-+		musb_writew(epio, MUSB_RXCSR, csr);
-+		musb_writew(epio, MUSB_RXCSR, csr);
-+
-+		/* Issue CPPI FIFO teardown for Rx channel */
-+		td_reg  = musb_readl(reg_base, cppi->teardown_reg_offs);
-+		td_reg |= USB_RX_TDOWN_MASK(ep_num);
-+		musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
-+
-+		/* Tear down Rx DMA channel */
-+		usb_rx_ch_teardown(cppi_ch);
-+
-+		/*
-+		 * NOTE: docs don't guarantee any of this works...  we expect
-+		 * that if the USB core stops telling the CPPI core to pull
-+		 * more data from it, then it'll be safe to flush current Rx
-+		 * DMA state iff any pending FIFO transfer is done.
-+		 */
-+
-+		/* For host, ensure ReqPkt is never set again */
-+		cppi41_autoreq_update(cppi_ch, USB_NO_AUTOREQ);
-+
-+		/* For host, clear (just) ReqPkt at end of current packet(s) */
-+		if (is_host_active(cppi->musb))
-+			csr &= ~MUSB_RXCSR_H_REQPKT;
-+		csr |= MUSB_RXCSR_H_WZC_BITS;
-+
-+		/* Clear DMA enable */
-+		csr &= ~MUSB_RXCSR_DMAENAB;
-+		musb_writew(epio, MUSB_RXCSR, csr);
-+
-+		/* Flush the FIFO of endpoint once again */
-+		csr  = musb_readw(epio, MUSB_RXCSR);
-+		csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_H_WZC_BITS;
-+		musb_writew(epio, MUSB_RXCSR, csr);
-+
-+		udelay(50);
-+	}
-+
-+	/*
-+	 * There might be PDs in the Rx/Tx source queue that were not consumed
-+	 * by the DMA controller -- they need to be recycled properly.
-+	 */
-+	while ((pd_addr = cppi41_queue_pop(&cppi_ch->queue_obj)) != 0) {
-+		struct usb_pkt_desc *curr_pd;
-+
-+		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
-+		if (curr_pd == NULL) {
-+			ERR("Invalid PD popped from source queue\n");
-+			continue;
-+		}
-+
-+		/*
-+		 * Return Rx/Tx PDs to the software list --
-+		 * this is protected by critical section.
-+		 */
-+		dprintk("Returning PD %p to the free PD list\n", curr_pd);
-+		usb_put_free_pd(cppi, curr_pd);
-+	}
-+
-+#ifdef DEBUG_CPPI_TD
-+	printk("After teardown:");
-+	print_pd_list(cppi->pd_pool_head);
-+#endif
-+
-+	/* Re-enable the DMA channel */
-+	cppi41_dma_ch_enable(&cppi_ch->dma_ch_obj);
-+
-+	channel->status = MUSB_DMA_STATUS_FREE;
-+
-+	return 0;
-+}
-+
-+void txdma_completion_work(struct work_struct *data)
-+{
-+	struct cppi41 *cppi = container_of(data, struct cppi41, txdma_work);
-+	struct cppi41_channel *tx_ch;
-+	struct musb *musb = cppi->musb;
-+	unsigned index;
-+	u8 resched = 0;
-+	unsigned long flags;
-+
-+	while (1) {
-+		for (index = 0; index < USB_CPPI41_NUM_CH; index++) {
-+			void __iomem *epio;
-+			u16 csr;
-+
-+			tx_ch = &cppi->tx_cppi_ch[index];
-+			spin_lock_irqsave(&musb->lock, flags);
-+			if (tx_ch->tx_complete) {
-+				/* Sometimes a EP can unregister from a DMA
-+				 * channel while the data is still in the FIFO.
-+				 * Probable reason a proper abort was not
-+				 * called before taking such a step.
-+				 * Protect against such cases.
-+				 */
-+				if (!tx_ch->end_pt) {
-+					tx_ch->tx_complete = 0;
-+					continue;
-+				}
-+
-+				epio = tx_ch->end_pt->regs;
-+				csr = musb_readw(epio, MUSB_TXCSR);
-+
-+				if (csr & (MUSB_TXCSR_TXPKTRDY |
-+					MUSB_TXCSR_FIFONOTEMPTY)) {
-+					resched = 1;
-+				} else {
-+					tx_ch->channel.status =
-+						MUSB_DMA_STATUS_FREE;
-+					tx_ch->tx_complete = 0;
-+					musb_dma_completion(musb, index+1, 1);
-+				}
-+			}
-+			spin_unlock_irqrestore(&musb->lock, flags);
-+
-+			if (!resched)
-+				cond_resched();
-+		}
-+
-+		if (resched) {
-+			resched = 0;
-+			cond_resched();
-+		} else {
-+			return ;
-+		}
-+	}
-+
-+}
-+
-+/**
-+ * cppi41_dma_controller_create -
-+ * instantiate an object representing DMA controller.
-+ */
-+struct dma_controller * __devinit
-+cppi41_dma_controller_create(struct musb  *musb, void __iomem *mregs)
-+{
-+	struct cppi41 *cppi;
-+
-+	cppi = kzalloc(sizeof *cppi, GFP_KERNEL);
-+	if (!cppi)
-+		return NULL;
-+
-+	/* Initialize the CPPI 4.1 DMA controller structure */
-+	cppi->musb  = musb;
-+	cppi->controller.start = cppi41_controller_start;
-+	cppi->controller.stop  = cppi41_controller_stop;
-+	cppi->controller.channel_alloc = cppi41_channel_alloc;
-+	cppi->controller.channel_release = cppi41_channel_release;
-+	cppi->controller.channel_program = cppi41_channel_program;
-+	cppi->controller.channel_abort = cppi41_channel_abort;
-+	cppi->cppi_info = (struct usb_cppi41_info *)&usb_cppi41_info[musb->id];;
-+	cppi->en_bd_intr = cppi->cppi_info->bd_intr_ctrl;
-+	INIT_WORK(&cppi->txdma_work, txdma_completion_work);
-+
-+	/* enable infinite mode only for ti81xx silicon rev2 */
-+	if (cpu_is_am33xx() || cpu_is_ti816x()) {
-+		dev_dbg(musb->controller, "cppi41dma supports infinite mode\n");
-+		cppi->inf_mode = 1;
-+	}
-+
-+	return &cppi->controller;
-+}
-+EXPORT_SYMBOL(cppi41_dma_controller_create);
-+
-+/**
-+ * cppi41_dma_controller_destroy -
-+ * destroy a previously instantiated DMA controller
-+ * @controller: the controller
-+ */
-+void cppi41_dma_controller_destroy(struct dma_controller *controller)
-+{
-+	struct cppi41 *cppi;
-+
-+	cppi = container_of(controller, struct cppi41, controller);
-+
-+	/* Free the CPPI object */
-+	kfree(cppi);
-+}
-+EXPORT_SYMBOL(cppi41_dma_controller_destroy);
-+
-+static void usb_process_tx_queue(struct cppi41 *cppi, unsigned index)
-+{
-+	struct cppi41_queue_obj tx_queue_obj;
-+	unsigned long pd_addr;
-+	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
-+	struct musb *musb = cppi->musb;
-+
-+	if (cppi41_queue_init(&tx_queue_obj, cppi_info->q_mgr,
-+			      cppi_info->tx_comp_q[index])) {
-+		dev_dbg(musb->controller, "ERROR: cppi41_queue_init failed for "
-+		    "Tx completion queue");
-+		return;
-+	}
-+
-+	while ((pd_addr = cppi41_queue_pop(&tx_queue_obj)) != 0) {
-+		struct usb_pkt_desc *curr_pd;
-+		struct cppi41_channel *tx_ch;
-+		u8 ch_num, ep_num;
-+		u32 length;
-+
-+		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
-+		if (curr_pd == NULL) {
-+			ERR("Invalid PD popped from Tx completion queue\n");
-+			continue;
-+		}
-+
-+		/* Extract the data from received packet descriptor */
-+		ch_num = curr_pd->ch_num;
-+		ep_num = curr_pd->ep_num;
-+		length = curr_pd->hw_desc.buf_len;
-+
-+		tx_ch = &cppi->tx_cppi_ch[ch_num];
-+		tx_ch->channel.actual_len += length;
-+
-+		/*
-+		 * Return Tx PD to the software list --
-+		 * this is protected by critical section
-+		 */
-+		usb_put_free_pd(cppi, curr_pd);
-+
-+		if ((tx_ch->curr_offset < tx_ch->length) ||
-+		    (tx_ch->transfer_mode && !tx_ch->zlp_queued))
-+			cppi41_next_tx_segment(tx_ch);
-+		else if (tx_ch->channel.actual_len >= tx_ch->length) {
-+			/*
-+			 * We get Tx DMA completion interrupt even when
-+			 * data is still in FIFO and not moved out to
-+			 * USB bus. As we program the next request we
-+			 * flush out and old data in FIFO which affects
-+			 * USB functionality. So far, we have obsered
-+			 * failure with iperf.
-+			 */
-+			tx_ch->tx_complete = 1;
-+			schedule_work(&cppi->txdma_work);
-+		}
-+	}
-+}
-+
-+static void usb_process_rx_queue(struct cppi41 *cppi, unsigned index)
-+{
-+	struct cppi41_queue_obj rx_queue_obj;
-+	unsigned long pd_addr;
-+	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
-+	struct musb *musb = cppi->musb;
-+	u8 en_bd_intr = cppi->en_bd_intr;
-+
-+	if (cppi41_queue_init(&rx_queue_obj, cppi_info->q_mgr,
-+			      cppi_info->rx_comp_q[index])) {
-+		dev_dbg(musb->controller, "ERROR: cppi41_queue_init failed for Rx queue\n");
-+		return;
-+	}
-+
-+	while ((pd_addr = cppi41_queue_pop(&rx_queue_obj)) != 0) {
-+		struct usb_pkt_desc *curr_pd;
-+		struct cppi41_channel *rx_ch;
-+		u8 ch_num, ep_num;
-+		u32 length = 0, orig_buf_len, timeout = 50;
-+
-+		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
-+		if (curr_pd == NULL) {
-+			ERR("Invalid PD popped from Rx completion queue\n");
-+			continue;
-+		}
-+
-+		/* This delay is required to overcome the dma race condition
-+		 * where software reads buffer descriptor before being updated
-+		 * by dma as buffer descriptor's writes by dma still pending in
-+		 * interconnect bridge.
-+		 */
-+		while (timeout--) {
-+			length = curr_pd->hw_desc.desc_info &
-+					CPPI41_PKT_LEN_MASK;
-+			if (length != 0)
-+				break;
-+			udelay(1);
-+		}
-+
-+		if (length == 0)
-+			ERR("!Race condtion: rxBD read before updated by dma");
-+
-+		/* Extract the data from received packet descriptor */
-+		ch_num = curr_pd->ch_num;
-+		ep_num = curr_pd->ep_num;
-+
-+		dev_dbg(musb->controller, "Rx complete: dma channel(%d) ep%d len %d timeout %d\n",
-+			ch_num, ep_num, length, (50-timeout));
-+
-+		rx_ch = &cppi->rx_cppi_ch[ch_num];
-+		rx_ch->channel.actual_len += length;
-+
-+		if (curr_pd->eop) {
-+			curr_pd->eop = 0;
-+			/* disable the rx dma schedular */
-+			if (is_peripheral_active(cppi->musb) && !cppi->inf_mode)
-+				cppi41_schedtbl_remove_dma_ch(0, 0, ch_num, 0);
-+		}
-+
-+		/*
-+		 * Return Rx PD to the software list --
-+		 * this is protected by critical section
-+		 */
-+		usb_put_free_pd(cppi, curr_pd);
-+
-+		orig_buf_len = curr_pd->hw_desc.orig_buf_len;
-+		if (en_bd_intr)
-+			orig_buf_len &= ~CPPI41_PKT_INTR_FLAG;
-+
-+		if (unlikely(rx_ch->channel.actual_len >= rx_ch->length ||
-+			     length < orig_buf_len)) {
-+
-+#if defined(CONFIG_SOC_OMAPTI81XX) || defined(CONFIG_SOC_OMAPAM33XX)
-+			struct musb_hw_ep *ep;
-+			u8 isoc, next_seg = 0;
-+
-+			/* Workaround for early rx completion of
-+			 * cppi41 dma in Generic RNDIS mode for ti81xx
-+			 */
-+			if (is_host_enabled(cppi->musb)) {
-+				u32 pkt_size = rx_ch->pkt_size;
-+				ep = cppi->musb->endpoints + ep_num;
-+				isoc = musb_readb(ep->regs, MUSB_RXTYPE);
-+				isoc = (isoc >> 4) & 0x1;
-+
-+				if (!isoc
-+				&& (rx_ch->dma_mode == USB_GENERIC_RNDIS_MODE)
-+				&& (rx_ch->channel.actual_len < rx_ch->length)
-+				&& !(rx_ch->channel.actual_len % pkt_size))
-+					next_seg = 1;
-+			}
-+			if (next_seg) {
-+				rx_ch->curr_offset = rx_ch->channel.actual_len;
-+				cppi41_next_rx_segment(rx_ch);
-+			} else
-+#endif
-+			{
-+				rx_ch->channel.status = MUSB_DMA_STATUS_FREE;
-+
-+				if (rx_ch->inf_mode) {
-+					cppi41_rx_ch_set_maxbufcnt(
-+					&rx_ch->dma_ch_obj, 0);
-+					rx_ch->inf_mode = 0;
-+				}
-+				/* Rx completion routine callback */
-+				musb_dma_completion(cppi->musb, ep_num, 0);
-+			}
-+		} else {
-+			if (is_peripheral_active(cppi->musb) &&
-+				((rx_ch->length - rx_ch->curr_offset) > 0))
-+				cppi41_next_rx_segment(rx_ch);
-+		}
-+	}
-+}
-+
-+/*
-+ * cppi41_completion - handle interrupts from the Tx/Rx completion queues
-+ *
-+ * NOTE: since we have to manually prod the Rx process in the transparent mode,
-+ *	 we certainly want to handle the Rx queues first.
-+ */
-+void cppi41_completion(struct musb *musb, u32 rx, u32 tx)
-+{
-+	struct cppi41 *cppi;
-+	unsigned index;
-+
-+	cppi = container_of(musb->dma_controller, struct cppi41, controller);
-+
-+	/* Process packet descriptors from the Rx queues */
-+	for (index = 0; rx != 0; rx >>= 1, index++)
-+		if (rx & 1)
-+			usb_process_rx_queue(cppi, index);
-+
-+	/* Process packet descriptors from the Tx completion queues */
-+	for (index = 0; tx != 0; tx >>= 1, index++)
-+		if (tx & 1)
-+			usb_process_tx_queue(cppi, index);
-+}
-+EXPORT_SYMBOL(cppi41_completion);
-+
-+MODULE_DESCRIPTION("CPPI4.1 dma controller driver for musb");
-+MODULE_LICENSE("GPL v2");
-+
-+static int __init cppi41_dma_init(void)
-+{
-+	return 0;
-+}
-+module_init(cppi41_dma_init);
-+
-+static void __exit cppi41_dma__exit(void)
-+{
-+}
-+module_exit(cppi41_dma__exit);
-diff --git a/drivers/usb/musb/cppi41_dma.h b/drivers/usb/musb/cppi41_dma.h
-new file mode 100644
-index 0000000..fd746c3
---- /dev/null
-+++ b/drivers/usb/musb/cppi41_dma.h
-@@ -0,0 +1,55 @@
-+/*
-+ * Copyright (C) 2005-2006 by Texas Instruments
-+ * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ */
-+
-+#ifndef _CPPI41_DMA_H_
-+#define _CPPI41_DMA_H_
-+#include <plat/usb.h>
-+
-+/**
-+ * struct usb_cppi41_info - CPPI 4.1 USB implementation details
-+ * @dma_block:	DMA block number
-+ * @ep_dma_ch:	DMA channel numbers used for EPs 1 .. Max_EP
-+ * @q_mgr:	queue manager number
-+ * @num_tx_comp_q: number of the Tx completion queues
-+ * @num_rx_comp_q: number of the Rx queues
-+ * @tx_comp_q:	pointer to the list of the Tx completion queue numbers
-+ * @rx_comp_q:	pointer to the list of the Rx queue numbers
-+ */
-+struct usb_cppi41_info {
-+	u8 dma_block;
-+	u8 ep_dma_ch[USB_CPPI41_NUM_CH];
-+	u8 q_mgr;
-+	u8 num_tx_comp_q;
-+	u8 num_rx_comp_q;
-+	u16 *tx_comp_q;
-+	u16 *rx_comp_q;
-+	u8 bd_intr_ctrl;
-+};
-+
-+extern struct usb_cppi41_info usb_cppi41_info[];
-+
-+/**
-+ * cppi41_completion - Tx/Rx completion queue interrupt handling hook
-+ * @musb:	the controller
-+ * @rx:	bitmask having bit N set if Rx queue N is not empty
-+ * @tx:	bitmask having bit N set if Tx completion queue N is not empty
-+ */
-+void cppi41_completion(struct musb *musb, u32 rx, u32 tx);
-+
-+#endif	/* _CPPI41_DMA_H_ */
-diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
-index 318fb4e..94db2e9 100644
---- a/drivers/usb/musb/cppi_dma.c
-+++ b/drivers/usb/musb/cppi_dma.c
-@@ -104,7 +104,7 @@ static void cppi_reset_tx(struct cppi_tx_stateram __iomem *tx, u32 ptr)
- 	musb_writel(&tx->tx_complete, 0, ptr);
- }
- 
--static void __init cppi_pool_init(struct cppi *cppi, struct cppi_channel *c)
-+static void __devinit cppi_pool_init(struct cppi *cppi, struct cppi_channel *c)
- {
- 	int	j;
- 
-@@ -149,7 +149,7 @@ static void cppi_pool_free(struct cppi_channel *c)
- 	c->last_processed = NULL;
- }
- 
--static int __init cppi_controller_start(struct dma_controller *c)
-+static int __devinit cppi_controller_start(struct dma_controller *c)
- {
- 	struct cppi	*controller;
- 	void __iomem	*tibase;
-@@ -359,8 +359,9 @@ cppi_dump_rx(int level, struct cppi_channel *c, const char *tag)
- {
- 	void __iomem			*base = c->controller->mregs;
- 	struct cppi_rx_stateram __iomem	*rx = c->state_ram;
-+	struct musb		*musb = c->controller->musb;
- 
--	musb_ep_select(base, c->index + 1);
-+	musb_ep_select(musb, base, c->index + 1);
- 
- 	dev_dbg(c->controller->musb->controller,
- 		"RX DMA%d%s: %d left, csr %04x, "
-@@ -390,8 +391,9 @@ cppi_dump_tx(int level, struct cppi_channel *c, const char *tag)
- {
- 	void __iomem			*base = c->controller->mregs;
- 	struct cppi_tx_stateram __iomem	*tx = c->state_ram;
-+	struct musb		*musb = c->controller->musb;
- 
--	musb_ep_select(base, c->index + 1);
-+	musb_ep_select(musb, base, c->index + 1);
- 
- 	dev_dbg(c->controller->musb->controller,
- 		"TX DMA%d%s: csr %04x, "
-@@ -513,7 +515,7 @@ static inline int cppi_autoreq_update(struct cppi_channel *rx,
- 		if (!(val & MUSB_RXCSR_H_REQPKT)) {
- 			val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
- 			musb_writew(regs, MUSB_RXCSR, val);
--			/* flush writebufer */
-+			/* flush writebuffer */
- 			val = musb_readw(regs, MUSB_RXCSR);
- 		}
- 	}
-@@ -1117,7 +1119,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
- 			 */
- 			WARN_ON(rx->head);
- 		}
--		musb_ep_select(cppi->mregs, rx->index + 1);
-+		musb_ep_select(cppi->musb, cppi->mregs, rx->index + 1);
- 		csr = musb_readw(regs, MUSB_RXCSR);
- 		if (csr & MUSB_RXCSR_DMAENAB) {
- 			dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
-@@ -1315,8 +1317,8 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
- }
- 
- /* Instantiate a software object representing a DMA controller. */
--struct dma_controller *__init
--dma_controller_create(struct musb *musb, void __iomem *mregs)
-+struct dma_controller *__devinit
-+cppi_dma_controller_create(struct musb *musb, void __iomem *mregs)
- {
- 	struct cppi		*controller;
- 	struct device		*dev = musb->controller;
-@@ -1355,7 +1357,7 @@ dma_controller_create(struct musb *musb, void __iomem *mregs)
- 	if (irq > 0) {
- 		if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
- 			dev_err(dev, "request_irq %d failed!\n", irq);
--			dma_controller_destroy(&controller->controller);
-+			cppi_dma_controller_destroy(&controller->controller);
- 			return NULL;
- 		}
- 		controller->irq = irq;
-@@ -1363,11 +1365,12 @@ dma_controller_create(struct musb *musb, void __iomem *mregs)
- 
- 	return &controller->controller;
- }
-+EXPORT_SYMBOL(cppi_dma_controller_create);
- 
- /*
-  *  Destroy a previously-instantiated DMA controller.
-  */
--void dma_controller_destroy(struct dma_controller *c)
-+void cppi_dma_controller_destroy(struct dma_controller *c)
- {
- 	struct cppi	*cppi;
- 
-@@ -1381,6 +1384,7 @@ void dma_controller_destroy(struct dma_controller *c)
- 
- 	kfree(cppi);
- }
-+EXPORT_SYMBOL(cppi_dma_controller_destroy);
- 
- /*
-  * Context: controller irqlocked, endpoint selected
-@@ -1428,7 +1432,7 @@ static int cppi_channel_abort(struct dma_channel *channel)
- 	 * and caller should rely on us not changing it.
- 	 * peripheral code is safe ... check host too.
- 	 */
--	musb_ep_select(mbase, cppi_ch->index + 1);
-+	musb_ep_select(controller->musb, mbase, cppi_ch->index + 1);
- 
- 	if (cppi_ch->transmit) {
- 		struct cppi_tx_stateram __iomem *tx_ram;
-@@ -1561,3 +1565,16 @@ static int cppi_channel_abort(struct dma_channel *channel)
-  * Power Management ... probably turn off cppi during suspend, restart;
-  * check state ram?  Clocking is presumably shared with usb core.
-  */
-+MODULE_DESCRIPTION("CPPI dma controller driver for musb");
-+MODULE_LICENSE("GPL v2");
-+
-+static int __init cppi_dma_init(void)
-+{
-+	return 0;
-+}
-+module_init(cppi_dma_init);
-+
-+static void __exit cppi_dma__exit(void)
-+{
-+}
-+module_exit(cppi_dma__exit);
-diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
-index 2613bfd..8b72c22 100644
---- a/drivers/usb/musb/da8xx.c
-+++ b/drivers/usb/musb/da8xx.c
-@@ -423,8 +423,8 @@ static int da8xx_musb_init(struct musb *musb)
- 	if (!rev)
- 		goto fail;
- 
--	usb_nop_xceiv_register();
--	musb->xceiv = otg_get_transceiver();
-+	usb_nop_xceiv_register(musb->id);
-+	musb->xceiv = otg_get_transceiver(musb->id);
- 	if (!musb->xceiv)
- 		goto fail;
- 
-@@ -458,12 +458,14 @@ static int da8xx_musb_exit(struct musb *musb)
- 	phy_off();
- 
- 	otg_put_transceiver(musb->xceiv);
--	usb_nop_xceiv_unregister();
-+	usb_nop_xceiv_unregister(musb->id);
- 
- 	return 0;
- }
- 
- static const struct musb_platform_ops da8xx_ops = {
-+	.fifo_mode	= 2,
-+	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING,
- 	.init		= da8xx_musb_init,
- 	.exit		= da8xx_musb_exit,
- 
-@@ -474,6 +476,9 @@ static const struct musb_platform_ops da8xx_ops = {
- 	.try_idle	= da8xx_musb_try_idle,
- 
- 	.set_vbus	= da8xx_musb_set_vbus,
-+
-+	.read_fifo	= musb_read_fifo,
-+	.write_fifo	= musb_write_fifo,
- };
- 
- static u64 da8xx_dmamask = DMA_BIT_MASK(32);
-diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
-index 7c569f5..3911d9a 100644
---- a/drivers/usb/musb/davinci.c
-+++ b/drivers/usb/musb/davinci.c
-@@ -284,7 +284,7 @@ static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
- 	 * mask, state, "vector", and EOI registers.
- 	 */
- 	cppi = container_of(musb->dma_controller, struct cppi, controller);
--	if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
-+	if (is_cppi_enabled(musb) && musb->dma_controller && !cppi->irq)
- 		retval = cppi_interrupt(irq, __hci);
- 
- 	/* ack and handle non-CPPI interrupts */
-@@ -382,8 +382,8 @@ static int davinci_musb_init(struct musb *musb)
- 	void __iomem	*tibase = musb->ctrl_base;
- 	u32		revision;
- 
--	usb_nop_xceiv_register();
--	musb->xceiv = otg_get_transceiver();
-+	usb_nop_xceiv_register(musb->id);
-+	musb->xceiv = otg_get_transceiver(musb->id);
- 	if (!musb->xceiv)
- 		return -ENODEV;
- 
-@@ -443,7 +443,7 @@ static int davinci_musb_init(struct musb *musb)
- 
- fail:
- 	otg_put_transceiver(musb->xceiv);
--	usb_nop_xceiv_unregister();
-+	usb_nop_xceiv_unregister(musb->id);
- 	return -ENODEV;
- }
- 
-@@ -492,12 +492,14 @@ static int davinci_musb_exit(struct musb *musb)
- 	phy_off();
- 
- 	otg_put_transceiver(musb->xceiv);
--	usb_nop_xceiv_unregister();
-+	usb_nop_xceiv_unregister(musb->id);
- 
- 	return 0;
- }
- 
- static const struct musb_platform_ops davinci_ops = {
-+	.fifo_mode	= 2,
-+	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI,
- 	.init		= davinci_musb_init,
- 	.exit		= davinci_musb_exit,
- 
-@@ -507,6 +509,12 @@ static const struct musb_platform_ops davinci_ops = {
- 	.set_mode	= davinci_musb_set_mode,
- 
- 	.set_vbus	= davinci_musb_set_vbus,
-+
-+	.read_fifo	= musb_read_fifo,
-+	.write_fifo	= musb_write_fifo,
-+
-+	.dma_controller_create = cppi_dma_controller_create,
-+	.dma_controller_destroy = cppi_dma_controller_destroy,
- };
- 
- static u64 davinci_dmamask = DMA_BIT_MASK(32);
-diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
-index 920f04e..db5afeb 100644
---- a/drivers/usb/musb/musb_core.c
-+++ b/drivers/usb/musb/musb_core.c
-@@ -102,7 +102,6 @@
- 
- #include "musb_core.h"
- 
--#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
- 
- 
- #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
-@@ -120,6 +119,10 @@ MODULE_AUTHOR(DRIVER_AUTHOR);
- MODULE_LICENSE("GPL");
- MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
- 
-+u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
-+EXPORT_SYMBOL_GPL(musb_readb);
-+void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
-+EXPORT_SYMBOL_GPL(musb_writeb);
- 
- /*-------------------------------------------------------------------------*/
- 
-@@ -131,6 +134,44 @@ static inline struct musb *dev_to_musb(struct device *dev)
- /*-------------------------------------------------------------------------*/
- 
- #ifndef CONFIG_BLACKFIN
-+
-+/*
-+ * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
-+ */
-+static inline u8 __tusb_musb_readb(const void __iomem *addr, unsigned offset)
-+{
-+	u16 tmp;
-+	u8 val;
-+
-+	tmp = __raw_readw(addr + (offset & ~1));
-+	if (offset & 1)
-+		val = (tmp >> 8);
-+	else
-+		val = tmp & 0xff;
-+
-+	return val;
-+}
-+
-+static inline void __tusb_musb_writeb(void __iomem *addr, unsigned offset,
-+					u8 data)
-+{
-+	u16 tmp;
-+
-+	tmp = __raw_readw(addr + (offset & ~1));
-+	if (offset & 1)
-+		tmp = (data << 8) | (tmp & 0xff);
-+	else
-+		tmp = (tmp & 0xff00) | data;
-+
-+	__raw_writew(tmp, addr + (offset & ~1));
-+}
-+
-+static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
-+	{ return readb(addr + offset); }
-+
-+static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
-+	{ writeb(data, addr + offset); }
-+
- static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
- {
- 	void __iomem *addr = otg->io_priv;
-@@ -196,6 +237,12 @@ static int musb_ulpi_write(struct otg_transceiver *otg,
- 	return 0;
- }
- #else
-+static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
-+	{ return (u8) (bfin_read16(addr + offset)); }
-+
-+static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
-+	{ bfin_write16(addr + offset, (u16) data); }
-+
- #define musb_ulpi_read		NULL
- #define musb_ulpi_write		NULL
- #endif
-@@ -205,10 +252,6 @@ static struct otg_io_access_ops musb_ulpi_access = {
- 	.write = musb_ulpi_write,
- };
- 
--/*-------------------------------------------------------------------------*/
--
--#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
--
- /*
-  * Load an endpoint's FIFO
-  */
-@@ -249,8 +292,8 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
- 		writesb(fifo, src, len);
- 	}
- }
-+EXPORT_SYMBOL_GPL(musb_write_fifo);
- 
--#if !defined(CONFIG_USB_MUSB_AM35X)
- /*
-  * Unload an endpoint's FIFO
-  */
-@@ -289,10 +332,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
- 		readsb(fifo, dst, len);
- 	}
- }
--#endif
--
--#endif	/* normal PIO */
--
-+EXPORT_SYMBOL_GPL(musb_read_fifo);
- 
- /*-------------------------------------------------------------------------*/
- 
-@@ -318,17 +358,20 @@ static const u8 musb_test_packet[53] = {
- 
- void musb_load_testpacket(struct musb *musb)
- {
--	void __iomem	*regs = musb->endpoints[0].regs;
--
--	musb_ep_select(musb->mregs, 0);
--	musb_write_fifo(musb->control_ep,
-+	musb_ep_select(musb, musb->mregs, 0);
-+	musb->ops->write_fifo(musb->control_ep,
- 			sizeof(musb_test_packet), musb_test_packet);
--	musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
- }
- 
- /*-------------------------------------------------------------------------*/
- 
- /*
-+ * See also USB_OTG_1-3.pdf 6.6.5 Timers
-+ * REVISIT: Are the other timers done in the hardware?
-+ */
-+#define TB_ASE0_BRST		100	/* Min 3.125 ms */
-+
-+/*
-  * Handles OTG hnp timeouts, such as b_ase0_brst
-  */
- void musb_otg_timer_func(unsigned long data)
-@@ -344,12 +387,9 @@ void musb_otg_timer_func(unsigned long data)
- 		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
- 		musb->is_active = 0;
- 		break;
--	case OTG_STATE_A_SUSPEND:
- 	case OTG_STATE_A_WAIT_BCON:
--		dev_dbg(musb->controller, "HNP: %s timeout\n",
--			otg_state_string(musb->xceiv->state));
--		musb_platform_set_vbus(musb, 0);
--		musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
-+		dev_dbg(musb->controller, "HNP: a_wait_bcon timeout; back to a_host\n");
-+		musb_hnp_stop(musb);
- 		break;
- 	default:
- 		dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
-@@ -360,7 +400,7 @@ void musb_otg_timer_func(unsigned long data)
- }
- 
- /*
-- * Stops the HNP transition. Caller must take care of locking.
-+ * Stops the B-device HNP state. Caller must take care of locking.
-  */
- void musb_hnp_stop(struct musb *musb)
- {
-@@ -368,13 +408,15 @@ void musb_hnp_stop(struct musb *musb)
- 	void __iomem	*mbase = musb->mregs;
- 	u8	reg;
- 
--	dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
--
- 	switch (musb->xceiv->state) {
- 	case OTG_STATE_A_PERIPHERAL:
-+	case OTG_STATE_A_WAIT_VFALL:
-+	case OTG_STATE_A_WAIT_BCON:
-+		dev_dbg(musb->controller, "HNP: Switching back to A-host\n");
- 		musb_g_disconnect(musb);
--		dev_dbg(musb->controller, "HNP: back to %s\n",
--			otg_state_string(musb->xceiv->state));
-+		musb->xceiv->state = OTG_STATE_A_IDLE;
-+		MUSB_HST_MODE(musb);
-+		musb->is_active = 0;
- 		break;
- 	case OTG_STATE_B_HOST:
- 		dev_dbg(musb->controller, "HNP: Disabling HR\n");
-@@ -427,7 +469,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 		handled = IRQ_HANDLED;
- 		dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
- 
--		if (devctl & MUSB_DEVCTL_HM) {
-+		if (is_host_enabled(musb) && (devctl & MUSB_DEVCTL_HM)) {
- 			void __iomem *mbase = musb->mregs;
- 
- 			switch (musb->xceiv->state) {
-@@ -470,26 +512,34 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 		} else {
- 			switch (musb->xceiv->state) {
- 			case OTG_STATE_A_SUSPEND:
--				/* possibly DISCONNECT is upcoming */
--				musb->xceiv->state = OTG_STATE_A_HOST;
--				usb_hcd_resume_root_hub(musb_to_hcd(musb));
-+				if (is_host_enabled(musb)) {
-+					/* possibly DISCONNECT is upcoming */
-+					musb->xceiv->state = OTG_STATE_A_HOST;
-+					usb_hcd_resume_root_hub(
-+							musb_to_hcd(musb));
-+				}
- 				break;
- 			case OTG_STATE_B_WAIT_ACON:
- 			case OTG_STATE_B_PERIPHERAL:
--				/* disconnect while suspended?  we may
--				 * not get a disconnect irq...
--				 */
--				if ((devctl & MUSB_DEVCTL_VBUS)
-+				if (is_peripheral_enabled(musb)) {
-+					/* disconnect while suspended?  we may
-+					 * not get a disconnect irq...
-+					 */
-+					if ((devctl & MUSB_DEVCTL_VBUS)
- 						!= (3 << MUSB_DEVCTL_VBUS_SHIFT)
--						) {
--					musb->int_usb |= MUSB_INTR_DISCONNECT;
--					musb->int_usb &= ~MUSB_INTR_SUSPEND;
--					break;
-+							) {
-+						musb->int_usb |=
-+							MUSB_INTR_DISCONNECT;
-+						musb->int_usb &=
-+							~MUSB_INTR_SUSPEND;
-+						break;
-+					}
-+					musb_g_resume(musb);
- 				}
--				musb_g_resume(musb);
- 				break;
- 			case OTG_STATE_B_IDLE:
--				musb->int_usb &= ~MUSB_INTR_SUSPEND;
-+				if (is_peripheral_enabled(musb))
-+					musb->int_usb &= ~MUSB_INTR_SUSPEND;
- 				break;
- 			default:
- 				WARNING("bogus %s RESUME (%s)\n",
-@@ -500,7 +550,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 	}
- 
- 	/* see manual for the order of the tests */
--	if (int_usb & MUSB_INTR_SESSREQ) {
-+	if (is_host_enabled(musb) && (int_usb & MUSB_INTR_SESSREQ)) {
- 		void __iomem *mbase = musb->mregs;
- 
- 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
-@@ -528,7 +578,8 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 		handled = IRQ_HANDLED;
- 	}
- 
--	if (int_usb & MUSB_INTR_VBUSERROR) {
-+	if (is_host_enabled(musb) && (int_usb & MUSB_INTR_VBUSERROR)) {
-+		struct usb_hcd *hcd = musb_to_hcd(musb);
- 		int	ignore = 0;
- 
- 		/* During connection as an A-Device, we may see a short
-@@ -568,6 +619,13 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 				musb->port1_status |=
- 					  USB_PORT_STAT_OVERCURRENT
- 					| (USB_PORT_STAT_C_OVERCURRENT << 16);
-+
-+				if (hcd->status_urb)
-+					usb_hcd_poll_rh_status(hcd);
-+				else
-+					usb_hcd_resume_root_hub(hcd);
-+
-+				MUSB_HST_MODE(musb);
- 			}
- 			break;
- 		default:
-@@ -604,22 +662,6 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 		handled = IRQ_HANDLED;
- 
- 		switch (musb->xceiv->state) {
--		case OTG_STATE_A_PERIPHERAL:
--			/* We also come here if the cable is removed, since
--			 * this silicon doesn't report ID-no-longer-grounded.
--			 *
--			 * We depend on T(a_wait_bcon) to shut us down, and
--			 * hope users don't do anything dicey during this
--			 * undesired detour through A_WAIT_BCON.
--			 */
--			musb_hnp_stop(musb);
--			usb_hcd_resume_root_hub(musb_to_hcd(musb));
--			musb_root_disconnect(musb);
--			musb_platform_try_idle(musb, jiffies
--					+ msecs_to_jiffies(musb->a_wait_bcon
--						? : OTG_TIME_A_WAIT_BCON));
--
--			break;
- 		case OTG_STATE_B_IDLE:
- 			if (!musb->is_active)
- 				break;
-@@ -627,12 +669,11 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 			musb_g_suspend(musb);
- 			musb->is_active = is_otg_enabled(musb)
- 					&& musb->xceiv->gadget->b_hnp_enable;
--			if (musb->is_active) {
-+			if (is_otg_enabled(musb) && musb->is_active) {
- 				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
- 				dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
- 				mod_timer(&musb->otg_timer, jiffies
--					+ msecs_to_jiffies(
--							OTG_TIME_B_ASE0_BRST));
-+					+ msecs_to_jiffies(TB_ASE0_BRST));
- 			}
- 			break;
- 		case OTG_STATE_A_WAIT_BCON:
-@@ -649,6 +690,13 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 			/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
- 			dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
- 			break;
-+		case OTG_STATE_A_PERIPHERAL:
-+			/*
-+			 * We cannot stop HNP here, devctl BDEVICE might be
-+			 * still set.
-+			 */
-+			if (is_otg_enabled(musb))
-+				break;
- 		default:
- 			/* "should not happen" */
- 			musb->is_active = 0;
-@@ -656,7 +704,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 		}
- 	}
- 
--	if (int_usb & MUSB_INTR_CONNECT) {
-+	if (is_host_enabled(musb) && (int_usb & MUSB_INTR_CONNECT)) {
- 		struct usb_hcd *hcd = musb_to_hcd(musb);
- 
- 		handled = IRQ_HANDLED;
-@@ -665,13 +713,16 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 
- 		musb->ep0_stage = MUSB_EP0_START;
- 
--		/* flush endpoints when transitioning from Device Mode */
--		if (is_peripheral_active(musb)) {
--			/* REVISIT HNP; just force disconnect */
-+		if (is_otg_enabled(musb)) {
-+			/* flush endpoints when transitioning from DeviceMode */
-+			if (is_peripheral_active(musb)) {
-+				/* REVISIT HNP; just force disconnect */
-+			}
-+			musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
-+			musb_writew(musb->mregs, MUSB_INTRRXE,
-+						musb->epmask & 0xfffe);
-+			musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
- 		}
--		musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
--		musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
--		musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
- 		musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
- 					|USB_PORT_STAT_HIGH_SPEED
- 					|USB_PORT_STAT_ENABLE
-@@ -683,23 +734,28 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
- 		if (devctl & MUSB_DEVCTL_LSDEV)
- 			musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
- 
-+		if (hcd->status_urb)
-+			usb_hcd_poll_rh_status(hcd);
-+		else
-+			usb_hcd_resume_root_hub(hcd);
-+
-+		MUSB_HST_MODE(musb);
-+
- 		/* indicate new connection to OTG machine */
- 		switch (musb->xceiv->state) {
- 		case OTG_STATE_B_PERIPHERAL:
- 			if (int_usb & MUSB_INTR_SUSPEND) {
- 				dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
-+				musb->xceiv->state = OTG_STATE_B_HOST;
-+				hcd->self.is_b_host = 1;
- 				int_usb &= ~MUSB_INTR_SUSPEND;
--				goto b_host;
- 			} else
- 				dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
- 			break;
- 		case OTG_STATE_B_WAIT_ACON:
--			dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
--b_host:
-+			dev_dbg(musb->controller, "HNP: Waiting to switch to b_host state\n");
- 			musb->xceiv->state = OTG_STATE_B_HOST;
- 			hcd->self.is_b_host = 1;
--			musb->ignore_disconnect = 0;
--			del_timer(&musb->otg_timer);
- 			break;
- 		default:
- 			if ((devctl & MUSB_DEVCTL_VBUS)
-@@ -710,13 +766,6 @@ b_host:
- 			break;
- 		}
- 
--		/* poke the root hub */
--		MUSB_HST_MODE(musb);
--		if (hcd->status_urb)
--			usb_hcd_poll_rh_status(hcd);
--		else
--			usb_hcd_resume_root_hub(hcd);
--
- 		dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
- 				otg_state_string(musb->xceiv->state), devctl);
- 	}
-@@ -730,33 +779,38 @@ b_host:
- 		switch (musb->xceiv->state) {
- 		case OTG_STATE_A_HOST:
- 		case OTG_STATE_A_SUSPEND:
--			usb_hcd_resume_root_hub(musb_to_hcd(musb));
--			musb_root_disconnect(musb);
--			if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
--				musb_platform_try_idle(musb, jiffies
-+			if (is_host_enabled(musb)) {
-+				usb_hcd_resume_root_hub(musb_to_hcd(musb));
-+				musb_root_disconnect(musb);
-+				if (musb->a_wait_bcon != 0 &&
-+						is_otg_enabled(musb))
-+					musb_platform_try_idle(musb, jiffies
- 					+ msecs_to_jiffies(musb->a_wait_bcon));
-+			}
- 			break;
- 		case OTG_STATE_B_HOST:
--			/* REVISIT this behaves for "real disconnect"
--			 * cases; make sure the other transitions from
--			 * from B_HOST act right too.  The B_HOST code
--			 * in hnp_stop() is currently not used...
--			 */
--			musb_root_disconnect(musb);
--			musb_to_hcd(musb)->self.is_b_host = 0;
--			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
--			MUSB_DEV_MODE(musb);
--			musb_g_disconnect(musb);
-+			if (is_otg_enabled(musb))
-+				musb_hnp_stop(musb);
- 			break;
- 		case OTG_STATE_A_PERIPHERAL:
--			musb_hnp_stop(musb);
--			musb_root_disconnect(musb);
-+			if (is_otg_enabled(musb)) {
-+				musb_hnp_stop(musb);
-+				musb_root_disconnect(musb);
-+			}
- 			/* FALLTHROUGH */
- 		case OTG_STATE_B_WAIT_ACON:
-+			if (!is_otg_enabled(musb))
-+				break;
- 			/* FALLTHROUGH */
- 		case OTG_STATE_B_PERIPHERAL:
- 		case OTG_STATE_B_IDLE:
--			musb_g_disconnect(musb);
-+			if (is_peripheral_enabled(musb)) {
-+				printk(KERN_INFO "musb %s gadget disconnected.\n",
-+					musb->gadget_driver
-+					? musb->gadget_driver->driver.name
-+					: "");
-+				musb_g_disconnect(musb);
-+			}
- 			break;
- 		default:
- 			WARNING("unhandled DISCONNECT transition (%s)\n",
-@@ -770,7 +824,7 @@ b_host:
- 	 */
- 	if (int_usb & MUSB_INTR_RESET) {
- 		handled = IRQ_HANDLED;
--		if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
-+		if (is_host_enabled(musb) && (devctl & MUSB_DEVCTL_HM) != 0) {
- 			/*
- 			 * Looks like non-HS BABBLE can be ignored, but
- 			 * HS BABBLE is an error condition. For HS the solution
-@@ -784,36 +838,45 @@ b_host:
- 				ERR("Stopping host session -- babble\n");
- 				musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
- 			}
--		} else if (is_peripheral_capable()) {
-+		} else if (is_peripheral_enabled(musb)) {
- 			dev_dbg(musb->controller, "BUS RESET as %s\n",
- 				otg_state_string(musb->xceiv->state));
- 			switch (musb->xceiv->state) {
- 			case OTG_STATE_A_SUSPEND:
--				/* We need to ignore disconnect on suspend
--				 * otherwise tusb 2.0 won't reconnect after a
--				 * power cycle, which breaks otg compliance.
--				 */
--				musb->ignore_disconnect = 1;
--				musb_g_reset(musb);
-+				if (is_otg_enabled(musb)) {
-+					/* We need to ignore disconnect on
-+					 * suspend otherwise tusb 2.0 won't
-+					 * reconnect after a power cycle,
-+					 * which breaks otg compliance.
-+					 */
-+					musb->ignore_disconnect = 1;
-+					musb_g_reset(musb);
-+				} else {
-+					break;
-+				}
- 				/* FALLTHROUGH */
- 			case OTG_STATE_A_WAIT_BCON:	/* OPT TD.4.7-900ms */
--				/* never use invalid T(a_wait_bcon) */
--				dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
--					otg_state_string(musb->xceiv->state),
--					TA_WAIT_BCON(musb));
--				mod_timer(&musb->otg_timer, jiffies
--					+ msecs_to_jiffies(TA_WAIT_BCON(musb)));
-+				if (is_otg_enabled(musb)) {
-+					dev_dbg(musb->controller,
-+					"HNP: Setting timer as %s\n",
-+					otg_state_string(musb->xceiv->state));
-+					mod_timer(&musb->otg_timer, jiffies
-+						+ msecs_to_jiffies(100));
-+				}
- 				break;
- 			case OTG_STATE_A_PERIPHERAL:
--				musb->ignore_disconnect = 0;
--				del_timer(&musb->otg_timer);
--				musb_g_reset(musb);
-+				if (is_otg_enabled(musb))
-+					musb_hnp_stop(musb);
- 				break;
- 			case OTG_STATE_B_WAIT_ACON:
--				dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
-+				if (is_otg_enabled(musb)) {
-+					dev_dbg(musb->controller,
-+					"HNP: RESET (%s), to b_peripheral\n",
- 					otg_state_string(musb->xceiv->state));
--				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
--				musb_g_reset(musb);
-+					musb->xceiv->state =
-+						OTG_STATE_B_PERIPHERAL;
-+					musb_g_reset(musb);
-+				}
- 				break;
- 			case OTG_STATE_B_IDLE:
- 				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
-@@ -906,7 +969,6 @@ void musb_start(struct musb *musb)
- 
- 	musb->is_active = 0;
- 	devctl = musb_readb(regs, MUSB_DEVCTL);
--	devctl &= ~MUSB_DEVCTL_SESSION;
- 
- 	if (is_otg_enabled(musb)) {
- 		/* session started after:
-@@ -930,7 +992,7 @@ void musb_start(struct musb *musb)
- 	musb_platform_enable(musb);
- 	musb_writeb(regs, MUSB_DEVCTL, devctl);
- }
--
-+EXPORT_SYMBOL(musb_start);
- 
- static void musb_generic_disable(struct musb *musb)
- {
-@@ -1000,40 +1062,12 @@ static void musb_shutdown(struct platform_device *pdev)
- /*-------------------------------------------------------------------------*/
- 
- /*
-- * The silicon either has hard-wired endpoint configurations, or else
-- * "dynamic fifo" sizing.  The driver has support for both, though at this
-- * writing only the dynamic sizing is very well tested.   Since we switched
-- * away from compile-time hardware parameters, we can no longer rely on
-- * dead code elimination to leave only the relevant one in the object file.
-- *
-- * We don't currently use dynamic fifo setup capability to do anything
-- * more than selecting one of a bunch of predefined configurations.
-- */
--#if defined(CONFIG_USB_MUSB_TUSB6010)			\
--	|| defined(CONFIG_USB_MUSB_TUSB6010_MODULE)	\
--	|| defined(CONFIG_USB_MUSB_OMAP2PLUS)		\
--	|| defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE)	\
--	|| defined(CONFIG_USB_MUSB_AM35X)		\
--	|| defined(CONFIG_USB_MUSB_AM35X_MODULE)
--static ushort __initdata fifo_mode = 4;
--#elif defined(CONFIG_USB_MUSB_UX500)			\
--	|| defined(CONFIG_USB_MUSB_UX500_MODULE)
--static ushort __initdata fifo_mode = 5;
--#else
--static ushort __initdata fifo_mode = 2;
--#endif
--
--/* "modprobe ... fifo_mode=1" etc */
--module_param(fifo_mode, ushort, 0);
--MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
--
--/*
-  * tables defining fifo_mode values.  define more if you like.
-  * for host side, make sure both halves of ep1 are set up.
-  */
- 
- /* mode 0 - fits in 2KB */
--static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
-+static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
- { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
- { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
- { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
-@@ -1042,7 +1076,7 @@ static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
- };
- 
- /* mode 1 - fits in 4KB */
--static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
-+static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
- { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
- { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
- { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
-@@ -1051,7 +1085,7 @@ static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
- };
- 
- /* mode 2 - fits in 4KB */
--static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
-+static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
- { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
- { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
- { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
-@@ -1061,7 +1095,7 @@ static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
- };
- 
- /* mode 3 - fits in 4KB */
--static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
-+static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
- { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
- { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
- { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
-@@ -1071,13 +1105,13 @@ static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
- };
- 
- /* mode 4 - fits in 16KB */
--static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
--{ .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
--{ .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
--{ .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
--{ .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
--{ .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
--{ .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
-+static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
-+{ .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512,},
-+{ .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512,},
-+{ .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512,},
-+{ .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512,},
-+{ .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512,},
-+{ .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512,},
- { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
- { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
- { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
-@@ -1101,8 +1135,9 @@ static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
- { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
- };
- 
-+
- /* mode 5 - fits in 8KB */
--static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
-+static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
- { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
- { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
- { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
-@@ -1132,13 +1167,44 @@ static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
- { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
- };
- 
-+/* mode 6 - fits in 32KB */
-+static struct musb_fifo_cfg __devinitdata mode_6_cfg[] = {
-+{ .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
-+{ .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
-+{ .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
-+{ .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
-+{ .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
-+{ .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
-+{ .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 64, },
-+{ .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 64, },
-+{ .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 64, },
-+{ .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 64, },
-+{ .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 64, },
-+{ .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 64, },
-+{ .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 64, },
-+{ .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 64, },
-+{ .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 64, },
-+{ .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 64, },
-+{ .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 64, },
-+{ .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 64, },
-+{ .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
-+{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
-+{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
-+{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
-+{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
-+{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
-+{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
-+{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
-+{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
-+};
-+
- /*
-  * configure a fifo; for non-shared endpoints, this may be called
-  * once for a tx fifo and once for an rx fifo.
-  *
-  * returns negative errno or offset for next fifo.
-  */
--static int __init
-+static int __devinit
- fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
- 		const struct musb_fifo_cfg *cfg, u16 offset)
- {
-@@ -1170,7 +1236,7 @@ fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
- 	/* EP0 reserved endpoint for control, bidirectional;
- 	 * EP1 reserved for bulk, two unidirection halves.
- 	 */
--	if (hw_ep->epnum == 1)
-+	if (is_host_enabled(musb) && hw_ep->epnum == 1)
- 		musb->bulk_ep = hw_ep;
- 	/* REVISIT error check:  be sure ep0 can both rx and tx ... */
- 	switch (cfg->style) {
-@@ -1209,26 +1275,28 @@ fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
- 	return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
- }
- 
--static struct musb_fifo_cfg __initdata ep0_cfg = {
-+static struct musb_fifo_cfg __devinitdata ep0_cfg = {
- 	.style = FIFO_RXTX, .maxpacket = 64,
- };
- 
--static int __init ep_config_from_table(struct musb *musb)
-+static int __devinit ep_config_from_table(struct musb *musb)
- {
- 	const struct musb_fifo_cfg	*cfg;
- 	unsigned		i, n;
- 	int			offset;
- 	struct musb_hw_ep	*hw_ep = musb->endpoints;
- 
--	if (musb->config->fifo_cfg) {
-+	if (musb->config->fifo_mode)
-+		musb->fifo_mode = musb->config->fifo_mode;
-+	else if (musb->config->fifo_cfg) {
- 		cfg = musb->config->fifo_cfg;
- 		n = musb->config->fifo_cfg_size;
- 		goto done;
- 	}
- 
--	switch (fifo_mode) {
-+	switch (musb->fifo_mode) {
- 	default:
--		fifo_mode = 0;
-+		musb->fifo_mode = 0;
- 		/* FALLTHROUGH */
- 	case 0:
- 		cfg = mode_0_cfg;
-@@ -1254,10 +1322,14 @@ static int __init ep_config_from_table(struct musb *musb)
- 		cfg = mode_5_cfg;
- 		n = ARRAY_SIZE(mode_5_cfg);
- 		break;
-+	case 6:
-+		cfg = mode_6_cfg;
-+		n = ARRAY_SIZE(mode_6_cfg);
-+		break;
- 	}
- 
- 	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
--			musb_driver_name, fifo_mode);
-+			musb_driver_name, musb->fifo_mode);
- 
- 
- done:
-@@ -1291,7 +1363,7 @@ done:
- 			n + 1, musb->config->num_eps * 2 - 1,
- 			offset, (1 << (musb->config->ram_bits + 2)));
- 
--	if (!musb->bulk_ep) {
-+	if (is_host_enabled(musb) && !musb->bulk_ep) {
- 		pr_debug("%s: missing bulk\n", musb_driver_name);
- 		return -EINVAL;
- 	}
-@@ -1299,12 +1371,11 @@ done:
- 	return 0;
- }
- 
--
- /*
-  * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
-  * @param musb the controller
-  */
--static int __init ep_config_from_hw(struct musb *musb)
-+static int __devinit ep_config_from_hw(struct musb *musb)
- {
- 	u8 epnum = 0;
- 	struct musb_hw_ep *hw_ep;
-@@ -1316,7 +1387,7 @@ static int __init ep_config_from_hw(struct musb *musb)
- 	/* FIXME pick up ep0 maxpacket size */
- 
- 	for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
--		musb_ep_select(mbase, epnum);
-+		musb_ep_select(musb, mbase, epnum);
- 		hw_ep = musb->endpoints + epnum;
- 
- 		ret = musb_read_fifosize(musb, hw_ep, epnum);
-@@ -1325,20 +1396,22 @@ static int __init ep_config_from_hw(struct musb *musb)
- 
- 		/* FIXME set up hw_ep->{rx,tx}_double_buffered */
- 
--		/* pick an RX/TX endpoint for bulk */
--		if (hw_ep->max_packet_sz_tx < 512
-+		if (is_host_enabled(musb)) {
-+			/* pick an RX/TX endpoint for bulk */
-+			if (hw_ep->max_packet_sz_tx < 512
- 				|| hw_ep->max_packet_sz_rx < 512)
--			continue;
-+				continue;
- 
--		/* REVISIT:  this algorithm is lazy, we should at least
--		 * try to pick a double buffered endpoint.
--		 */
--		if (musb->bulk_ep)
--			continue;
--		musb->bulk_ep = hw_ep;
-+			/* REVISIT:  this algorithm is lazy, we should at least
-+			 * try to pick a double buffered endpoint.
-+			 */
-+			if (musb->bulk_ep)
-+				continue;
-+			musb->bulk_ep = hw_ep;
-+		}
- 	}
- 
--	if (!musb->bulk_ep) {
-+	if (is_host_enabled(musb) && !musb->bulk_ep) {
- 		pr_debug("%s: missing bulk\n", musb_driver_name);
- 		return -EINVAL;
- 	}
-@@ -1351,7 +1424,7 @@ enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
- /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
-  * configure endpoints, or take their config from silicon
-  */
--static int __init musb_core_init(u16 musb_type, struct musb *musb)
-+static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
- {
- 	u8 reg;
- 	char *type;
-@@ -1398,9 +1471,10 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
- 		musb->is_multipoint = 0;
- 		type = "";
- #ifndef	CONFIG_USB_OTG_BLACKLIST_HUB
--		printk(KERN_ERR
--			"%s: kernel must blacklist external hubs\n",
--			musb_driver_name);
-+		if (is_host_enabled(musb))
-+			printk(KERN_ERR
-+				"%s: kernel must blacklist external hubs\n",
-+				musb_driver_name);
- #endif
- 	}
- 
-@@ -1431,23 +1505,31 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
- 	for (i = 0; i < musb->nr_endpoints; i++) {
- 		struct musb_hw_ep	*hw_ep = musb->endpoints + i;
- 
--		hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
--#ifdef CONFIG_USB_MUSB_TUSB6010
--		hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
--		hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
--		hw_ep->fifo_sync_va =
--			musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
--
--		if (i == 0)
--			hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
--		else
--			hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
--#endif
-+		if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
-+			hw_ep->fifo = MUSB_TUSB_FIFO_OFFSET(i) + mbase;
-+			hw_ep->fifo_async = musb->async +
-+					0x400 + MUSB_TUSB_FIFO_OFFSET(i);
-+			hw_ep->fifo_sync = musb->sync +
-+					0x400 + MUSB_TUSB_FIFO_OFFSET(i);
-+			hw_ep->fifo_sync_va = musb->sync_va + 0x400 +
-+					MUSB_TUSB_FIFO_OFFSET(i);
-+
-+			if (i == 0)
-+				hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
-+			else
-+				hw_ep->conf = mbase + 0x400 +
-+						(((i - 1) & 0xf) << 2);
-+		} else {
-+			hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
-+		}
- 
--		hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
--		hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
--		hw_ep->rx_reinit = 1;
--		hw_ep->tx_reinit = 1;
-+		hw_ep->regs = MUSB_EP_OFFSET(musb, i, 0) + mbase;
-+		if (is_host_enabled(musb)) {
-+			hw_ep->target_regs =
-+					musb_read_target_reg_base(i, mbase);
-+			hw_ep->rx_reinit = 1;
-+			hw_ep->tx_reinit = 1;
-+		}
- 
- 		if (hw_ep->max_packet_sz_tx) {
- 			dev_dbg(musb->controller,
-@@ -1546,14 +1628,14 @@ irqreturn_t musb_interrupt(struct musb *musb)
- 	ep_num = 1;
- 	while (reg) {
- 		if (reg & 1) {
--			/* musb_ep_select(musb->mregs, ep_num); */
-+			/* musb_ep_select(musb, musb->mregs, ep_num); */
- 			/* REVISIT just retval = ep->rx_irq(...) */
- 			retval = IRQ_HANDLED;
- 			if (devctl & MUSB_DEVCTL_HM) {
--				if (is_host_capable())
-+				if (is_host_enabled(musb))
- 					musb_host_rx(musb, ep_num);
- 			} else {
--				if (is_peripheral_capable())
-+				if (is_peripheral_enabled(musb))
- 					musb_g_rx(musb, ep_num);
- 			}
- 		}
-@@ -1567,14 +1649,14 @@ irqreturn_t musb_interrupt(struct musb *musb)
- 	ep_num = 1;
- 	while (reg) {
- 		if (reg & 1) {
--			/* musb_ep_select(musb->mregs, ep_num); */
-+			/* musb_ep_select(musb, musb->mregs, ep_num); */
- 			/* REVISIT just retval |= ep->tx_irq(...) */
- 			retval = IRQ_HANDLED;
- 			if (devctl & MUSB_DEVCTL_HM) {
--				if (is_host_capable())
-+				if (is_host_enabled(musb))
- 					musb_host_tx(musb, ep_num);
- 			} else {
--				if (is_peripheral_capable())
-+				if (is_peripheral_enabled(musb))
- 					musb_g_tx(musb, ep_num);
- 			}
- 		}
-@@ -1587,12 +1669,6 @@ irqreturn_t musb_interrupt(struct musb *musb)
- EXPORT_SYMBOL_GPL(musb_interrupt);
- 
- #ifndef CONFIG_MUSB_PIO_ONLY
--static int __initdata use_dma = 1;
--
--/* "modprobe ... use_dma=0" etc */
--module_param(use_dma, bool, 0);
--MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
--
- void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
- {
- 	u8	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
-@@ -1600,40 +1676,37 @@ void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
- 	/* called with controller lock already held */
- 
- 	if (!epnum) {
--#ifndef CONFIG_USB_TUSB_OMAP_DMA
--		if (!is_cppi_enabled()) {
-+		if (!tusb_dma_omap(musb) && !is_cppi_enabled(musb)
-+				&& !is_cppi41_enabled(musb)) {
- 			/* endpoint 0 */
- 			if (devctl & MUSB_DEVCTL_HM)
- 				musb_h_ep0_irq(musb);
- 			else
- 				musb_g_ep0_irq(musb);
- 		}
--#endif
- 	} else {
- 		/* endpoints 1..15 */
- 		if (transmit) {
- 			if (devctl & MUSB_DEVCTL_HM) {
--				if (is_host_capable())
-+				if (is_host_enabled(musb))
- 					musb_host_tx(musb, epnum);
- 			} else {
--				if (is_peripheral_capable())
-+				if (is_peripheral_enabled(musb))
- 					musb_g_tx(musb, epnum);
- 			}
- 		} else {
- 			/* receive */
- 			if (devctl & MUSB_DEVCTL_HM) {
--				if (is_host_capable())
-+				if (is_host_enabled(musb))
- 					musb_host_rx(musb, epnum);
- 			} else {
--				if (is_peripheral_capable())
-+				if (is_peripheral_enabled(musb))
- 					musb_g_rx(musb, epnum);
- 			}
- 		}
- 	}
- }
--
--#else
--#define use_dma			0
-+EXPORT_SYMBOL_GPL(musb_dma_completion);
- #endif
- 
- /*-------------------------------------------------------------------------*/
-@@ -1691,8 +1764,7 @@ musb_vbus_store(struct device *dev, struct device_attribute *attr,
- 	}
- 
- 	spin_lock_irqsave(&musb->lock, flags);
--	/* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
--	musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
-+	musb->a_wait_bcon = val;
- 	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
- 		musb->is_active = 0;
- 	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
-@@ -1711,13 +1783,10 @@ musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
- 
- 	spin_lock_irqsave(&musb->lock, flags);
- 	val = musb->a_wait_bcon;
--	/* FIXME get_vbus_status() is normally #defined as false...
--	 * and is effectively TUSB-specific.
--	 */
- 	vbus = musb_platform_get_vbus_status(musb);
- 	spin_unlock_irqrestore(&musb->lock, flags);
- 
--	return sprintf(buf, "Vbus %s, timeout %lu msec\n",
-+	return sprintf(buf, "Vbus %s, timeout %lu\n",
- 			vbus ? "on" : "off", val);
- }
- static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
-@@ -1762,10 +1831,9 @@ static const struct attribute_group musb_attr_group = {
- static void musb_irq_work(struct work_struct *data)
- {
- 	struct musb *musb = container_of(data, struct musb, irq_work);
--	static int old_state;
- 
--	if (musb->xceiv->state != old_state) {
--		old_state = musb->xceiv->state;
-+	if (musb->xceiv->state != musb->old_state) {
-+		musb->old_state = musb->xceiv->state;
- 		sysfs_notify(&musb->controller->kobj, NULL, "mode");
- 	}
- }
-@@ -1774,7 +1842,7 @@ static void musb_irq_work(struct work_struct *data)
-  * Init support
-  */
- 
--static struct musb *__init
-+static struct musb *__devinit
- allocate_instance(struct device *dev,
- 		struct musb_hdrc_config *config, void __iomem *mbase)
- {
-@@ -1782,22 +1850,30 @@ allocate_instance(struct device *dev,
- 	struct musb_hw_ep	*ep;
- 	int			epnum;
- 	struct usb_hcd	*hcd;
-+	struct musb_hdrc_platform_data *plat = dev->platform_data;
- 
--	hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
--	if (!hcd)
--		return NULL;
--	/* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
--
--	musb = hcd_to_musb(hcd);
--	INIT_LIST_HEAD(&musb->control);
--	INIT_LIST_HEAD(&musb->in_bulk);
--	INIT_LIST_HEAD(&musb->out_bulk);
-+	if (plat->mode != MUSB_PERIPHERAL) {
-+		hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
-+		if (!hcd)
-+			return NULL;
-+		/* usbcore sets dev->driver_data to hcd, and sometimes uses
-+		 * that...
-+		 */
- 
--	hcd->uses_new_polling = 1;
--	hcd->has_tt = 1;
-+		musb = hcd_to_musb(hcd);
-+		INIT_LIST_HEAD(&musb->control);
-+		INIT_LIST_HEAD(&musb->in_bulk);
-+		INIT_LIST_HEAD(&musb->out_bulk);
-+		INIT_LIST_HEAD(&musb->gb_list);
- 
--	musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
--	musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
-+		hcd->uses_new_polling = 1;
-+		hcd->has_tt = 1;
-+		musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
-+	} else {
-+		musb = kzalloc(sizeof *musb, GFP_KERNEL);
-+		if (!musb)
-+			return NULL;
-+	}
- 	dev_set_drvdata(dev, musb);
- 	musb->mregs = mbase;
- 	musb->ctrl_base = mbase;
-@@ -1827,7 +1903,8 @@ static void musb_free(struct musb *musb)
- 	sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
- #endif
- 
--	musb_gadget_cleanup(musb);
-+	if (is_peripheral_enabled(musb))
-+		musb_gadget_cleanup(musb);
- 
- 	if (musb->nIrq >= 0) {
- 		if (musb->irq_wake)
-@@ -1838,10 +1915,19 @@ static void musb_free(struct musb *musb)
- 		struct dma_controller	*c = musb->dma_controller;
- 
- 		(void) c->stop(c);
--		dma_controller_destroy(c);
-+		musb->ops->dma_controller_destroy(c);
- 	}
- 
--	kfree(musb);
-+	if (is_otg_enabled(musb))
-+		del_timer_sync(&musb->otg_timer);
-+
-+	if (is_host_enabled(musb)) {
-+		if (musb->gb_queue)
-+			destroy_workqueue(musb->gb_queue);
-+		usb_put_hcd(musb_to_hcd(musb));
-+	} else {
-+		kfree(musb);
-+	}
- }
- 
- /*
-@@ -1852,12 +1938,13 @@ static void musb_free(struct musb *musb)
-  * @mregs: virtual address of controller registers,
-  *	not yet corrected for platform-specific offsets
-  */
--static int __init
-+static int __devinit
- musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
- {
- 	int			status;
- 	struct musb		*musb;
- 	struct musb_hdrc_platform_data *plat = dev->platform_data;
-+	struct platform_device *pdev = to_platform_device(dev);
- 
- 	/* The driver might handle more features than the board; OK.
- 	 * Fail when the board needs a feature that's not enabled.
-@@ -1884,6 +1971,25 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
- 	musb->board_set_power = plat->set_power;
- 	musb->min_power = plat->min_power;
- 	musb->ops = plat->platform_ops;
-+	musb->id = pdev->id;
-+	musb->first = 1;
-+	if (is_host_enabled(musb))
-+		spin_lock_init(&musb->gb_lock);
-+
-+	musb->fifo_mode = musb->ops->fifo_mode;
-+
-+#ifndef CONFIG_MUSB_PIO_ONLY
-+	musb->orig_dma_mask = dev->dma_mask;
-+#endif
-+	if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
-+		musb_readb = __tusb_musb_readb;
-+		musb_writeb = __tusb_musb_writeb;
-+	} else {
-+		musb_readb = __musb_readb;
-+		musb_writeb = __musb_writeb;
-+	}
-+
-+	dev_info(dev, "dma type: %s\n", get_dma_name(musb));
- 
- 	/* The musb_platform_init() call:
- 	 *   - adjusts musb->mregs and musb->isr if needed,
-@@ -1912,10 +2018,15 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
- 	}
- 
- #ifndef CONFIG_MUSB_PIO_ONLY
--	if (use_dma && dev->dma_mask) {
-+	if (dev->dma_mask) {
- 		struct dma_controller	*c;
- 
--		c = dma_controller_create(musb, musb->mregs);
-+		if (!musb->ops->dma_controller_create) {
-+			dev_err(dev, "no dma_controller_create for non-PIO mode!\n");
-+			status = -ENODEV;
-+			goto fail3;
-+		}
-+		c = musb->ops->dma_controller_create(musb, musb->mregs);
- 		musb->dma_controller = c;
- 		if (c)
- 			(void) c->start(c);
-@@ -1936,8 +2047,6 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
- 	if (status < 0)
- 		goto fail3;
- 
--	setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
--
- 	/* Init IRQ workqueue before request_irq */
- 	INIT_WORK(&musb->irq_work, musb_irq_work);
- 
-@@ -2034,8 +2143,30 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
- 			? "DMA" : "PIO",
- 			musb->nIrq);
- 
-+	if (status == 0) {
-+		u8 drvbuf[19];
-+		sprintf(drvbuf, "driver/musb_hdrc.%d", musb->id);
-+		musb_debug_create(drvbuf, musb);
-+	}
-+
-+	if (is_host_enabled(musb)) {
-+		musb->gb_queue = create_singlethread_workqueue(dev_name(dev));
-+		if (musb->gb_queue == NULL)
-+			goto fail6;
-+		/* Init giveback workqueue */
-+		INIT_WORK(&musb->gb_work, musb_gb_work);
-+	}
-+
-+	/* setup otg_timer */
-+	if (is_otg_enabled(musb))
-+		setup_timer(&musb->otg_timer, musb_otg_timer_func,
-+						(unsigned long) musb);
- 	return 0;
- 
-+fail6:
-+	if (is_host_enabled(musb))
-+		destroy_workqueue(musb->gb_queue);
-+
- fail5:
- 	musb_exit_debugfs(musb);
- 
-@@ -2067,20 +2198,29 @@ fail0:
- /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
-  * bridge to a platform device; this driver then suffices.
-  */
--
--#ifndef CONFIG_MUSB_PIO_ONLY
--static u64	*orig_dma_mask;
--#endif
--
--static int __init musb_probe(struct platform_device *pdev)
-+static int __devinit musb_probe(struct platform_device *pdev)
- {
- 	struct device	*dev = &pdev->dev;
- 	int		irq = platform_get_irq_byname(pdev, "mc");
- 	int		status;
- 	struct resource	*iomem;
- 	void __iomem	*base;
-+	char	res_name[20];
-+
-+	if (pdev->id == -1)
-+		strcpy(res_name, "mc");
-+	else
-+		sprintf(res_name, "musb%d-irq", pdev->id);
-+	irq = platform_get_irq_byname(pdev, res_name);
-+
-+	if (pdev->id == -1)
-+		iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	else {
-+		sprintf(res_name, "musb%d", pdev->id);
-+		iomem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+			res_name);
-+	}
- 
--	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	if (!iomem || irq <= 0)
- 		return -ENODEV;
- 
-@@ -2090,10 +2230,6 @@ static int __init musb_probe(struct platform_device *pdev)
- 		return -ENOMEM;
- 	}
- 
--#ifndef CONFIG_MUSB_PIO_ONLY
--	/* clobbered by use_dma=n */
--	orig_dma_mask = dev->dma_mask;
--#endif
- 	status = musb_init_controller(dev, irq, base);
- 	if (status < 0)
- 		iounmap(base);
-@@ -2105,6 +2241,7 @@ static int __exit musb_remove(struct platform_device *pdev)
- {
- 	struct musb	*musb = dev_to_musb(&pdev->dev);
- 	void __iomem	*ctrl_base = musb->ctrl_base;
-+	u8 drvbuf[19];
- 
- 	/* this gets called on rmmod.
- 	 *  - Host mode: host may still be active
-@@ -2114,20 +2251,22 @@ static int __exit musb_remove(struct platform_device *pdev)
- 	pm_runtime_get_sync(musb->controller);
- 	musb_exit_debugfs(musb);
- 	musb_shutdown(pdev);
-+	sprintf(drvbuf, "driver/musb_hdrc.%d", musb->id);
-+	musb_debug_delete(drvbuf, musb);
- 
- 	pm_runtime_put(musb->controller);
- 	musb_free(musb);
- 	iounmap(ctrl_base);
- 	device_init_wakeup(&pdev->dev, 0);
- #ifndef CONFIG_MUSB_PIO_ONLY
--	pdev->dev.dma_mask = orig_dma_mask;
-+	pdev->dev.dma_mask = musb->orig_dma_mask;
- #endif
- 	return 0;
- }
- 
- #ifdef	CONFIG_PM
- 
--static void musb_save_context(struct musb *musb)
-+void musb_save_context(struct musb *musb)
- {
- 	int i;
- 	void __iomem *musb_base = musb->mregs;
-@@ -2156,6 +2295,7 @@ static void musb_save_context(struct musb *musb)
- 		if (!epio)
- 			continue;
- 
-+		musb_writeb(musb_base, MUSB_INDEX, i);
- 		musb->context.index_regs[i].txmaxp =
- 			musb_readw(epio, MUSB_TXMAXP);
- 		musb->context.index_regs[i].txcsr =
-@@ -2201,8 +2341,9 @@ static void musb_save_context(struct musb *musb)
- 		}
- 	}
- }
-+EXPORT_SYMBOL(musb_save_context);
- 
--static void musb_restore_context(struct musb *musb)
-+void musb_restore_context(struct musb *musb)
- {
- 	int i;
- 	void __iomem *musb_base = musb->mregs;
-@@ -2231,6 +2372,7 @@ static void musb_restore_context(struct musb *musb)
- 		if (!epio)
- 			continue;
- 
-+		musb_writeb(musb_base, MUSB_INDEX, i);
- 		musb_writew(epio, MUSB_TXMAXP,
- 			musb->context.index_regs[i].txmaxp);
- 		musb_writew(epio, MUSB_TXCSR,
-@@ -2281,17 +2423,20 @@ static void musb_restore_context(struct musb *musb)
- 	}
- 	musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
- }
-+EXPORT_SYMBOL(musb_restore_context);
- 
- static int musb_suspend(struct device *dev)
- {
- 	struct musb	*musb = dev_to_musb(dev);
- 	unsigned long	flags;
-+	int ret = 0;
- 
- 	spin_lock_irqsave(&musb->lock, flags);
- 
- 	if (is_peripheral_active(musb)) {
--		/* FIXME force disconnect unless we know USB will wake
--		 * the system up quickly enough to respond ...
-+		/*
-+		 * Don't allow system suspend while peripheral mode
-+		 * is actve and cable is connected to host.
- 		 */
- 	} else if (is_host_active(musb)) {
- 		/* we know all the children are suspended; sometimes
-@@ -2300,7 +2445,7 @@ static int musb_suspend(struct device *dev)
- 	}
- 
- 	spin_unlock_irqrestore(&musb->lock, flags);
--	return 0;
-+	return ret;
- }
- 
- static int musb_resume_noirq(struct device *dev)
-@@ -2324,7 +2469,6 @@ static int musb_runtime_suspend(struct device *dev)
- static int musb_runtime_resume(struct device *dev)
- {
- 	struct musb	*musb = dev_to_musb(dev);
--	static int	first = 1;
- 
- 	/*
- 	 * When pm_runtime_get_sync called for the first time in driver
-@@ -2335,9 +2479,11 @@ static int musb_runtime_resume(struct device *dev)
- 	 * Also context restore without save does not make
- 	 * any sense
- 	 */
--	if (!first)
-+	if (musb->first)
-+		musb->first = 0;
-+	else
- 		musb_restore_context(musb);
--	first = 0;
-+
- 
- 	return 0;
- }
-@@ -2361,6 +2507,7 @@ static struct platform_driver musb_driver = {
- 		.owner		= THIS_MODULE,
- 		.pm		= MUSB_DEV_PM_OPS,
- 	},
-+	.probe      = musb_probe,
- 	.remove		= __exit_p(musb_remove),
- 	.shutdown	= musb_shutdown,
- };
-@@ -2377,7 +2524,7 @@ static int __init musb_init(void)
- 		", "
- 		"otg (peripheral+host)",
- 		musb_driver_name);
--	return platform_driver_probe(&musb_driver, musb_probe);
-+	return platform_driver_register(&musb_driver);
- }
- 
- /* make us init after usbcore and i2c (transceivers, regulators, etc)
-diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
-index b3c065a..3605b97 100644
---- a/drivers/usb/musb/musb_core.h
-+++ b/drivers/usb/musb/musb_core.h
-@@ -39,8 +39,6 @@
- #include <linux/list.h>
- #include <linux/interrupt.h>
- #include <linux/errno.h>
--#include <linux/timer.h>
--#include <linux/clk.h>
- #include <linux/device.h>
- #include <linux/usb/ch9.h>
- #include <linux/usb/gadget.h>
-@@ -62,6 +60,9 @@ struct musb_ep;
- #define MUSB_HWVERS_1900	0x784
- #define MUSB_HWVERS_2000	0x800
- 
-+extern u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
-+extern void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
-+
- #include "musb_debug.h"
- #include "musb_dma.h"
- 
-@@ -97,8 +98,6 @@ struct musb_ep;
- 
- /****************************** PERIPHERAL ROLE *****************************/
- 
--#define	is_peripheral_capable()	(1)
--
- extern irqreturn_t musb_g_ep0_irq(struct musb *);
- extern void musb_g_tx(struct musb *, u8);
- extern void musb_g_rx(struct musb *, u8);
-@@ -110,8 +109,6 @@ extern void musb_g_disconnect(struct musb *);
- 
- /****************************** HOST ROLE ***********************************/
- 
--#define	is_host_capable()	(1)
--
- extern irqreturn_t musb_h_ep0_irq(struct musb *);
- extern void musb_host_tx(struct musb *, u8);
- extern void musb_host_rx(struct musb *, u8);
-@@ -146,15 +143,10 @@ enum musb_g_ep0_state {
- 	MUSB_EP0_STAGE_ACKWAIT,		/* after zlp, before statusin */
- } __attribute__ ((packed));
- 
--/*
-- * OTG protocol constants.  See USB OTG 1.3 spec,
-- * sections 5.5 "Device Timings" and 6.6.5 "Timers".
-- */
-+/* OTG protocol constants */
- #define OTG_TIME_A_WAIT_VRISE	100		/* msec (max) */
--#define OTG_TIME_A_WAIT_BCON	1100		/* min 1 second */
--#define OTG_TIME_A_AIDL_BDIS	200		/* min 200 msec */
--#define OTG_TIME_B_ASE0_BRST	100		/* min 3.125 ms */
--
-+#define OTG_TIME_A_WAIT_BCON	0		/* 0=infinite; min 1000 msec */
-+#define OTG_TIME_A_IDLE_BDIS	200		/* msec (min) */
- 
- /*************************** REGISTER ACCESS ********************************/
- 
-@@ -162,34 +154,12 @@ enum musb_g_ep0_state {
-  * directly with the "flat" model, or after setting up an index register.
-  */
- 
--#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
--		|| defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
--		|| defined(CONFIG_ARCH_OMAP4)
--/* REVISIT indexed access seemed to
-- * misbehave (on DaVinci) for at least peripheral IN ...
-- */
--#define	MUSB_FLAT_REG
--#endif
--
--/* TUSB mapping: "flat" plus ep0 special cases */
--#if defined(CONFIG_USB_MUSB_TUSB6010) || \
--	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
--#define musb_ep_select(_mbase, _epnum) \
--	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
--#define	MUSB_EP_OFFSET			MUSB_TUSB_OFFSET
--
--/* "flat" mapping: each endpoint has its own i/o address */
--#elif	defined(MUSB_FLAT_REG)
--#define musb_ep_select(_mbase, _epnum)	(((void)(_mbase)), ((void)(_epnum)))
--#define	MUSB_EP_OFFSET			MUSB_FLAT_OFFSET
--
--/* "indexed" mapping: INDEX register controls register bank select */
--#else
--#define musb_ep_select(_mbase, _epnum) \
--	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
--#define	MUSB_EP_OFFSET			MUSB_INDEXED_OFFSET
--#endif
-+#define musb_ep_select(_musb, _mbase, _epnum) do { \
-+	if (_musb->ops->flags & MUSB_GLUE_EP_ADDR_INDEXED_MAPPING) \
-+		musb_writeb((_mbase), MUSB_INDEX, (_epnum)); \
-+ } while (0)
- 
-+#define	MUSB_EP_OFFSET	MUSB_OFFSET
- /****************************** FUNCTIONS ********************************/
- 
- #define MUSB_HST_MODE(_musb)\
-@@ -204,32 +174,60 @@ enum musb_g_ep0_state {
- 
- /******************************** TYPES *************************************/
- 
-+#define     MUSB_GLUE_TUSB_STYLE   0x0001
-+#define     MUSB_GLUE_EP_ADDR_FLAT_MAPPING	0x0002
-+#define     MUSB_GLUE_EP_ADDR_INDEXED_MAPPING	0x0004
-+#define		MUSB_GLUE_DMA_INVENTRA				0x0008
-+#define		MUSB_GLUE_DMA_CPPI					0x0010
-+#define		MUSB_GLUE_DMA_TUSB					0x0020
-+#define		MUSB_GLUE_DMA_UX500					0x0040
-+#define		MUSB_GLUE_DMA_CPPI41					0x0080
-+
-+
- /**
-  * struct musb_platform_ops - Operations passed to musb_core by HW glue layer
-+ * @fifo_mode: which fifo_mode is taken by me
-+ * @flags:	each hw glue difference information will be here
-  * @init:	turns on clocks, sets up platform-specific registers, etc
-  * @exit:	undoes @init
-+ * @read_fifo: read data from musb fifo in PIO
-+ * @write_fifo: write data into musb fifo in PIO
-  * @set_mode:	forcefully changes operating mode
-  * @try_ilde:	tries to idle the IP
-+ * @get_hw_revision: get hardware revision
-  * @vbus_status: returns vbus status if possible
-  * @set_vbus:	forces vbus status
-  * @adjust_channel_params: pre check for standard dma channel_program func
-+ * @dma_controller_create: create dma controller for me
-+ * @dma_controller_destroy: destroy dma controller
-  */
- struct musb_platform_ops {
-+	short	fifo_mode;
-+	unsigned short	flags;
- 	int	(*init)(struct musb *musb);
- 	int	(*exit)(struct musb *musb);
- 
- 	void	(*enable)(struct musb *musb);
- 	void	(*disable)(struct musb *musb);
- 
-+	void (*read_fifo)(struct musb_hw_ep *hw_ep, u16 len, u8 *buf);
-+	void (*write_fifo)(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf);
-+
- 	int	(*set_mode)(struct musb *musb, u8 mode);
- 	void	(*try_idle)(struct musb *musb, unsigned long timeout);
- 
-+	u16  (*get_hw_revision)(struct musb *musb);
-+
- 	int	(*vbus_status)(struct musb *musb);
- 	void	(*set_vbus)(struct musb *musb, int on);
- 
- 	int	(*adjust_channel_params)(struct dma_channel *channel,
- 				u16 packet_sz, u8 *mode,
- 				dma_addr_t *dma_addr, u32 *len);
-+	struct dma_controller* (*dma_controller_create)(struct musb *,
-+		void __iomem *);
-+	void (*dma_controller_destroy)(struct dma_controller *);
-+	int (*simulate_babble_intr)(struct musb *musb);
- };
- 
- /*
-@@ -242,10 +240,8 @@ struct musb_hw_ep {
- 	void __iomem		*fifo;
- 	void __iomem		*regs;
- 
--#if defined(CONFIG_USB_MUSB_TUSB6010) || \
--	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
-+	/*Fixme: the following field is only used by tusb*/
- 	void __iomem		*conf;
--#endif
- 
- 	/* index in musb->endpoints[]  */
- 	u8			epnum;
-@@ -260,13 +256,13 @@ struct musb_hw_ep {
- 	struct dma_channel	*tx_channel;
- 	struct dma_channel	*rx_channel;
- 
--#if defined(CONFIG_USB_MUSB_TUSB6010) || \
--	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
--	/* TUSB has "asynchronous" and "synchronous" dma modes */
-+	/*
-+	 * TUSB has "asynchronous" and "synchronous" dma modes
-+	 * Fixme: the following three fields are only valid for TUSB.
-+	 * */
- 	dma_addr_t		fifo_async;
- 	dma_addr_t		fifo_sync;
- 	void __iomem		*fifo_sync_va;
--#endif
- 
- 	void __iomem		*target_regs;
- 
-@@ -311,6 +307,7 @@ struct musb_context_registers {
- 	u8 index, testmode;
- 
- 	u8 devctl, busctl, misc;
-+	u32 otg_interfsel;
- 
- 	struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
- };
-@@ -327,6 +324,9 @@ struct musb {
- 
- 	irqreturn_t		(*isr)(int, void *);
- 	struct work_struct	irq_work;
-+	struct work_struct      work;
-+	struct work_struct	otg_notifier_work;
-+	u8                      enable_babble_work;
- 	u16			hwvers;
- 
- /* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
-@@ -350,7 +350,11 @@ struct musb {
- 	struct list_head	in_bulk;	/* of musb_qh */
- 	struct list_head	out_bulk;	/* of musb_qh */
- 
--	struct timer_list	otg_timer;
-+	struct workqueue_struct *gb_queue;
-+	struct work_struct      gb_work;
-+	spinlock_t              gb_lock;
-+	struct list_head        gb_list;        /* of urbs */
-+
- 	struct notifier_block	nb;
- 
- 	struct dma_controller	*dma_controller;
-@@ -359,12 +363,10 @@ struct musb {
- 	void __iomem		*ctrl_base;
- 	void __iomem		*mregs;
- 
--#if defined(CONFIG_USB_MUSB_TUSB6010) || \
--	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
-+	/*Fixme: the three fields below are only used by tusb*/
- 	dma_addr_t		async;
- 	dma_addr_t		sync;
- 	void __iomem		*sync_va;
--#endif
- 
- 	/* passed down from chip/board specific irq handlers */
- 	u8			int_usb;
-@@ -372,6 +374,7 @@ struct musb {
- 	u16			int_tx;
- 
- 	struct otg_transceiver	*xceiv;
-+	u8			xceiv_event;
- 
- 	int nIrq;
- 	unsigned		irq_wake:1;
-@@ -454,6 +457,19 @@ struct musb {
- #ifdef MUSB_CONFIG_PROC_FS
- 	struct proc_dir_entry *proc_entry;
- #endif
-+	/* id for multiple musb instances */
-+	u8			id;
-+	struct	timer_list	otg_workaround;
-+	unsigned long		last_timer;
-+	int			first;
-+	int			old_state;
-+	struct	timer_list	otg_timer;
-+	u8			en_otg_timer;
-+	u8			en_otgw_timer;
-+#ifndef CONFIG_MUSB_PIO_ONLY
-+	u64			*orig_dma_mask;
-+#endif
-+	short			fifo_mode;
- };
- 
- static inline struct musb *gadget_to_musb(struct usb_gadget *g)
-@@ -496,7 +512,7 @@ static inline int musb_read_fifosize(struct musb *musb,
- 	u8 reg = 0;
- 
- 	/* read from core using indexed model */
--	reg = musb_readb(mbase, MUSB_EP_OFFSET(epnum, MUSB_FIFOSIZE));
-+	reg = musb_readb(mbase, MUSB_EP_OFFSET(musb, epnum, MUSB_FIFOSIZE));
- 	/* 0's returned when no more endpoints */
- 	if (!reg)
- 		return -ENODEV;
-@@ -601,4 +617,47 @@ static inline int musb_platform_exit(struct musb *musb)
- 	return musb->ops->exit(musb);
- }
- 
-+static inline u16 musb_platform_get_hw_revision(struct musb *musb)
-+{
-+	if (!musb->ops->get_hw_revision)
-+		return musb_readw(musb->mregs, MUSB_HWVERS);
-+
-+	return musb->ops->get_hw_revision(musb);
-+}
-+
-+static inline int musb_simulate_babble_intr(struct musb *musb)
-+{
-+	if (!musb->ops->simulate_babble_intr)
-+		return -EINVAL;
-+
-+	return musb->ops->simulate_babble_intr(musb);
-+}
-+
-+static inline const char *get_dma_name(struct musb *musb)
-+{
-+#ifdef CONFIG_MUSB_PIO_ONLY
-+	return "pio";
-+#else
-+	if (musb->ops->flags & MUSB_GLUE_DMA_INVENTRA)
-+		return "dma-inventra";
-+	else if (musb->ops->flags & MUSB_GLUE_DMA_CPPI)
-+		return "dma-cppi3";
-+	else if (musb->ops->flags & MUSB_GLUE_DMA_CPPI41)
-+		return "dma-cppi41";
-+	else if (musb->ops->flags & MUSB_GLUE_DMA_TUSB)
-+		return "dma-tusb-omap";
-+	else
-+		return "?dma?";
-+#endif
-+}
-+
-+extern void musb_gb_work(struct work_struct *data);
-+/*-------------------------- ProcFS definitions ---------------------*/
-+
-+struct proc_dir_entry;
-+
-+extern struct proc_dir_entry *musb_debug_create(char *name, struct musb *data);
-+extern void musb_debug_delete(char *name, struct musb *data);
-+extern void musb_save_context(struct musb *musb);
-+extern void musb_restore_context(struct musb *musb);
- #endif	/* __MUSB_CORE_H__ */
-diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h
-index 742eada..27ba8f7 100644
---- a/drivers/usb/musb/musb_debug.h
-+++ b/drivers/usb/musb/musb_debug.h
-@@ -43,8 +43,8 @@
- #define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
- 
- #ifdef CONFIG_DEBUG_FS
--extern int musb_init_debugfs(struct musb *musb);
--extern void musb_exit_debugfs(struct musb *musb);
-+int musb_init_debugfs(struct musb *musb);
-+void musb_exit_debugfs(struct musb *musb);
- #else
- static inline int musb_init_debugfs(struct musb *musb)
- {
-diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c
-index 61f4ee4..c902b66 100644
---- a/drivers/usb/musb/musb_debugfs.c
-+++ b/drivers/usb/musb/musb_debugfs.c
-@@ -33,11 +33,7 @@
- 
- #include <linux/module.h>
- #include <linux/kernel.h>
--#include <linux/sched.h>
- #include <linux/init.h>
--#include <linux/list.h>
--#include <linux/platform_device.h>
--#include <linux/io.h>
- #include <linux/debugfs.h>
- #include <linux/seq_file.h>
- 
-@@ -46,10 +42,6 @@
- #include "musb_core.h"
- #include "musb_debug.h"
- 
--#ifdef CONFIG_ARCH_DAVINCI
--#include "davinci.h"
--#endif
--
- struct musb_register_map {
- 	char			*name;
- 	unsigned		offset;
-@@ -243,7 +235,7 @@ static const struct file_operations musb_test_mode_fops = {
- 	.release		= single_release,
- };
- 
--int __init musb_init_debugfs(struct musb *musb)
-+int __devinit musb_init_debugfs(struct musb *musb)
- {
- 	struct dentry		*root;
- 	struct dentry		*file;
-@@ -280,7 +272,7 @@ err0:
- 	return ret;
- }
- 
--void /* __init_or_exit */ musb_exit_debugfs(struct musb *musb)
-+void /* __devinit_or_exit */ musb_exit_debugfs(struct musb *musb)
- {
- 	debugfs_remove_recursive(musb_debugfs_root);
- }
-diff --git a/drivers/usb/musb/musb_dma.h b/drivers/usb/musb/musb_dma.h
-index 3a97c4e..06e857e 100644
---- a/drivers/usb/musb/musb_dma.h
-+++ b/drivers/usb/musb/musb_dma.h
-@@ -68,16 +68,35 @@ struct musb_hw_ep;
- #define	is_dma_capable()	(0)
- #endif
- 
-+#ifdef CONFIG_USB_UX500_DMA
-+#define	is_ux500_dma(musb)	(musb->ops->flags & MUSB_GLUE_DMA_UX500)
-+#else
-+#define	is_ux500_dma(musb)	0
-+#endif
-+
-+#ifdef CONFIG_USB_INVENTRA_DMA
-+#define	is_inventra_dma(musb)	(musb->ops->flags & MUSB_GLUE_DMA_INVENTRA)
-+#else
-+#define	is_inventra_dma(musb)	0
-+#endif
-+
- #ifdef CONFIG_USB_TI_CPPI_DMA
--#define	is_cppi_enabled()	1
-+#define	is_cppi_enabled(musb)	(musb->ops->flags & MUSB_GLUE_DMA_CPPI)
-+
-+#else
-+#define	is_cppi_enabled(musb)	0
-+#endif
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+#define is_cppi41_enabled(musb)	(musb->ops->flags & MUSB_GLUE_DMA_CPPI41)
- #else
--#define	is_cppi_enabled()	0
-+#define is_cppi41_enabled(musb)     0
- #endif
- 
- #ifdef CONFIG_USB_TUSB_OMAP_DMA
--#define tusb_dma_omap()			1
-+#define tusb_dma_omap(musb)		(musb->ops->flags & MUSB_GLUE_DMA_TUSB)
- #else
--#define tusb_dma_omap()			0
-+#define tusb_dma_omap(musb)		0
- #endif
- 
- /* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
-@@ -178,9 +197,72 @@ struct dma_controller {
- extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
- 
- 
--extern struct dma_controller *__init
--dma_controller_create(struct musb *, void __iomem *);
-+#ifdef CONFIG_USB_TI_CPPI_DMA
-+extern struct dma_controller *__devinit
-+cppi_dma_controller_create(struct musb *, void __iomem *);
-+
-+extern void cppi_dma_controller_destroy(struct dma_controller *);
-+#else
-+static inline struct dma_controller *__devinit
-+cppi_dma_controller_create(struct musb *musb, void __iomem *mregs)
-+{
-+	return NULL;
-+}
-+
-+static inline void cppi_dma_controller_destroy(struct dma_controller *c)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+extern struct dma_controller *__devinit
-+cppi41_dma_controller_create(struct musb *, void __iomem *);
-+
-+extern void cppi41_dma_controller_destroy(struct dma_controller *);
-+#else
-+static inline struct dma_controller *__devinit
-+cppi41_dma_controller_create(struct musb *musb, void __iomem *mregs)
-+{
-+	return NULL;
-+}
-+
-+static inline void cppi41_dma_controller_destroy(struct dma_controller *c)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_USB_INVENTRA_DMA
-+extern struct dma_controller *__devinit
-+inventra_dma_controller_create(struct musb *, void __iomem *);
-+
-+extern void inventra_dma_controller_destroy(struct dma_controller *);
-+#else
-+static inline struct dma_controller *__devinit
-+inventra_dma_controller_create(struct musb *musb, void __iomem *mregs)
-+{
-+	return NULL;
-+}
- 
--extern void dma_controller_destroy(struct dma_controller *);
-+static inline void inventra_dma_controller_destroy(struct dma_controller *c)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_USB_TUSB_OMAP_DMA
-+extern struct dma_controller *__devinit
-+tusb_dma_controller_create(struct musb *, void __iomem *);
-+
-+extern void tusb_dma_controller_destroy(struct dma_controller *);
-+#else
-+static inline struct dma_controller *__devinit
-+tusb_dma_controller_create(struct musb *musb, void __iomem *mregs)
-+{
-+	return NULL;
-+}
-+
-+static inline void tusb_dma_controller_destroy(struct dma_controller *c)
-+{
-+}
-+#endif
- 
- #endif	/* __MUSB_DMA_H__ */
-diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
-index c860597..305d843 100644
---- a/drivers/usb/musb/musb_gadget.c
-+++ b/drivers/usb/musb/musb_gadget.c
-@@ -40,8 +40,6 @@
- #include <linux/smp.h>
- #include <linux/spinlock.h>
- #include <linux/delay.h>
--#include <linux/moduleparam.h>
--#include <linux/stat.h>
- #include <linux/dma-mapping.h>
- #include <linux/slab.h>
- 
-@@ -278,8 +276,6 @@ static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
- }
- 
- 
--#ifdef CONFIG_USB_INVENTRA_DMA
--
- /* Peripheral tx (IN) using Mentor DMA works as follows:
- 	Only mode 0 is used for transfers <= wPktSize,
- 	mode 1 is used for larger transfers,
-@@ -310,8 +306,6 @@ static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
-  * upleveling from irq-per-packet to irq-per-buffer.
-  */
- 
--#endif
--
- /*
-  * An endpoint is transmitting data. This can be called either from
-  * the IRQ routine or from ep.queue() to kickstart a request on an
-@@ -372,8 +366,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
- 
- 		/* MUSB_TXCSR_P_ISO is still set correctly */
- 
--#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
--		{
-+		if (is_inventra_dma(musb) || is_ux500_dma(musb)) {
- 			if (request_size < musb_ep->packet_sz)
- 				musb_ep->dma->desired_mode = 0;
- 			else
-@@ -410,49 +403,58 @@ static void txstate(struct musb *musb, struct musb_request *req)
- 
- 				musb_writew(epio, MUSB_TXCSR, csr);
- 			}
--		}
-+		} else if (is_cppi_enabled(musb) || is_cppi41_enabled(musb)) {
-+			/* program endpoint CSR first, then setup DMA */
-+			csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
- 
--#elif defined(CONFIG_USB_TI_CPPI_DMA)
--		/* program endpoint CSR first, then setup DMA */
--		csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
--		csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
--		       MUSB_TXCSR_MODE;
--		musb_writew(epio, MUSB_TXCSR,
--			(MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
--				| csr);
-+			if (request_size == 0)
-+				csr &= ~(MUSB_TXCSR_DMAENAB |
-+					MUSB_TXCSR_DMAMODE);
-+			else
-+				csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
-+				       MUSB_TXCSR_MODE;
-+			musb_writew(epio, MUSB_TXCSR,
-+				(MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
-+					| csr);
- 
--		/* ensure writebuffer is empty */
--		csr = musb_readw(epio, MUSB_TXCSR);
-+			/* ensure writebuffer is empty */
-+			csr = musb_readw(epio, MUSB_TXCSR);
- 
--		/* NOTE host side sets DMAENAB later than this; both are
--		 * OK since the transfer dma glue (between CPPI and Mentor
--		 * fifos) just tells CPPI it could start.  Data only moves
--		 * to the USB TX fifo when both fifos are ready.
--		 */
-+			/* NOTE host side sets DMAENAB later than this; both are
-+			 * OK since the transfer dma glue (between CPPI & Mentor
-+			 * fifos) just tells CPPI it could start.  Data only
-+			 * moves to the USB TX fifo when both fifos are ready.
-+			 */
- 
--		/* "mode" is irrelevant here; handle terminating ZLPs like
--		 * PIO does, since the hardware RNDIS mode seems unreliable
--		 * except for the last-packet-is-already-short case.
--		 */
--		use_dma = use_dma && c->channel_program(
--				musb_ep->dma, musb_ep->packet_sz,
--				0,
--				request->dma + request->actual,
--				request_size);
--		if (!use_dma) {
--			c->channel_release(musb_ep->dma);
--			musb_ep->dma = NULL;
--			csr &= ~MUSB_TXCSR_DMAENAB;
--			musb_writew(epio, MUSB_TXCSR, csr);
--			/* invariant: prequest->buf is non-null */
-+			/* "mode" is irrelevant here; handle terminating ZLPs
-+			 * like PIO does, since the hardware RNDIS mode seems
-+			 * unreliable except for the last-packet-is-already-
-+			 * short case.
-+			 */
-+			/* for zero byte transfer use pio mode */
-+			if (request_size == 0)
-+				use_dma = 0;
-+			else {
-+				use_dma = use_dma && c->channel_program(
-+					musb_ep->dma, musb_ep->packet_sz,
-+					0,
-+					request->dma + request->actual,
-+					request_size);
-+				if (!use_dma) {
-+					c->channel_release(musb_ep->dma);
-+					musb_ep->dma = NULL;
-+					csr &= ~MUSB_TXCSR_DMAENAB;
-+					musb_writew(epio, MUSB_TXCSR, csr);
-+				/* invariant: prequest->buf is non-null */
-+				}
-+			}
-+		} else if (tusb_dma_omap(musb)) {
-+			use_dma = use_dma && c->channel_program(
-+					musb_ep->dma, musb_ep->packet_sz,
-+					request->zero,
-+					request->dma + request->actual,
-+					request_size);
- 		}
--#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
--		use_dma = use_dma && c->channel_program(
--				musb_ep->dma, musb_ep->packet_sz,
--				request->zero,
--				request->dma + request->actual,
--				request_size);
--#endif
- 	}
- #endif
- 
-@@ -463,7 +465,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
- 		 */
- 		unmap_dma_buffer(req, musb);
- 
--		musb_write_fifo(musb_ep->hw_ep, fifo_count,
-+		musb->ops->write_fifo(musb_ep->hw_ep, fifo_count,
- 				(u8 *) (request->buf + request->actual));
- 		request->actual += fifo_count;
- 		csr |= MUSB_TXCSR_TXPKTRDY;
-@@ -494,7 +496,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
- 	void __iomem		*epio = musb->endpoints[epnum].regs;
- 	struct dma_channel	*dma;
- 
--	musb_ep_select(mbase, epnum);
-+	musb_ep_select(musb, mbase, epnum);
- 	req = next_request(musb_ep);
- 	request = &req->request;
- 
-@@ -555,11 +557,9 @@ void musb_g_tx(struct musb *musb, u8 epnum)
- 		if ((request->zero && request->length
- 			&& (request->length % musb_ep->packet_sz == 0)
- 			&& (request->actual == request->length))
--#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
--			|| (is_dma && (!dma->desired_mode ||
--				(request->actual &
--					(musb_ep->packet_sz - 1))))
--#endif
-+			|| ((is_inventra_dma(musb) || is_ux500_dma(musb)) &&
-+			is_dma && (!dma->desired_mode || (request->actual &
-+			(musb_ep->packet_sz - 1))))
- 		) {
- 			/*
- 			 * On DMA completion, FIFO may not be
-@@ -576,15 +576,6 @@ void musb_g_tx(struct musb *musb, u8 epnum)
- 
- 		if (request->actual == request->length) {
- 			musb_g_giveback(musb_ep, request, 0);
--			/*
--			 * In the giveback function the MUSB lock is
--			 * released and acquired after sometime. During
--			 * this time period the INDEX register could get
--			 * changed by the gadget_queue function especially
--			 * on SMP systems. Reselect the INDEX to be sure
--			 * we are reading/modifying the right registers
--			 */
--			musb_ep_select(mbase, epnum);
- 			req = musb_ep->desc ? next_request(musb_ep) : NULL;
- 			if (!req) {
- 				dev_dbg(musb->controller, "%s idle now\n",
-@@ -599,8 +590,6 @@ void musb_g_tx(struct musb *musb, u8 epnum)
- 
- /* ------------------------------------------------------------ */
- 
--#ifdef CONFIG_USB_INVENTRA_DMA
--
- /* Peripheral rx (OUT) using Mentor DMA works as follows:
- 	- Only mode 0 is used.
- 
-@@ -628,8 +617,6 @@ void musb_g_tx(struct musb *musb, u8 epnum)
-  * Non-Mentor DMA engines can of course work differently.
-  */
- 
--#endif
--
- /*
-  * Context: controller locked, IRQs blocked, endpoint selected
-  */
-@@ -664,7 +651,8 @@ static void rxstate(struct musb *musb, struct musb_request *req)
- 		return;
- 	}
- 
--	if (is_cppi_enabled() && is_buffer_mapped(req)) {
-+	if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb)) &&
-+					is_buffer_mapped(req)) {
- 		struct dma_controller	*c = musb->dma_controller;
- 		struct dma_channel	*channel = musb_ep->dma;
- 
-@@ -706,8 +694,7 @@ static void rxstate(struct musb *musb, struct musb_request *req)
- 			use_mode_1 = 0;
- 
- 		if (request->actual < request->length) {
--#ifdef CONFIG_USB_INVENTRA_DMA
--			if (is_buffer_mapped(req)) {
-+			if (is_buffer_mapped(req) && is_inventra_dma(musb)) {
- 				struct dma_controller	*c;
- 				struct dma_channel	*channel;
- 				int			use_dma = 0;
-@@ -784,8 +771,7 @@ static void rxstate(struct musb *musb, struct musb_request *req)
- 				if (use_dma)
- 					return;
- 			}
--#elif defined(CONFIG_USB_UX500_DMA)
--			if ((is_buffer_mapped(req)) &&
-+			if (is_ux500_dma(musb) && (is_buffer_mapped(req)) &&
- 				(request->actual < request->length)) {
- 
- 				struct dma_controller *c;
-@@ -831,7 +817,6 @@ static void rxstate(struct musb *musb, struct musb_request *req)
- 
- 					return;
- 			}
--#endif	/* Mentor's DMA */
- 
- 			fifo_count = request->length - request->actual;
- 			dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
-@@ -841,8 +826,7 @@ static void rxstate(struct musb *musb, struct musb_request *req)
- 
- 			fifo_count = min_t(unsigned, len, fifo_count);
- 
--#ifdef	CONFIG_USB_TUSB_OMAP_DMA
--			if (tusb_dma_omap() && is_buffer_mapped(req)) {
-+			if (tusb_dma_omap(musb) && is_buffer_mapped(req)) {
- 				struct dma_controller *c = musb->dma_controller;
- 				struct dma_channel *channel = musb_ep->dma;
- 				u32 dma_addr = request->dma + request->actual;
-@@ -856,7 +840,7 @@ static void rxstate(struct musb *musb, struct musb_request *req)
- 				if (ret)
- 					return;
- 			}
--#endif
-+
- 			/*
- 			 * Unmap the dma buffer back to cpu if dma channel
- 			 * programming fails. This buffer is mapped if the
-@@ -873,7 +857,7 @@ static void rxstate(struct musb *musb, struct musb_request *req)
- 				musb_writew(epio, MUSB_RXCSR, csr);
- 			}
- 
--			musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
-+			musb->ops->read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
- 					(request->buf + request->actual));
- 			request->actual += fifo_count;
- 
-@@ -912,7 +896,7 @@ void musb_g_rx(struct musb *musb, u8 epnum)
- 	else
- 		musb_ep = &hw_ep->ep_out;
- 
--	musb_ep_select(mbase, epnum);
-+	musb_ep_select(musb, mbase, epnum);
- 
- 	req = next_request(musb_ep);
- 	if (!req)
-@@ -968,50 +952,37 @@ void musb_g_rx(struct musb *musb, u8 epnum)
- 			musb_readw(epio, MUSB_RXCSR),
- 			musb_ep->dma->actual_len, request);
- 
--#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
--	defined(CONFIG_USB_UX500_DMA)
--		/* Autoclear doesn't clear RxPktRdy for short packets */
--		if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
--				|| (dma->actual_len
--					& (musb_ep->packet_sz - 1))) {
--			/* ack the read! */
--			csr &= ~MUSB_RXCSR_RXPKTRDY;
--			musb_writew(epio, MUSB_RXCSR, csr);
--		}
-+		if (is_inventra_dma(musb) || tusb_dma_omap(musb)
-+				|| is_ux500_dma(musb)) {
-+			/* Autoclear doesn't clear RxPktRdy for short packets */
-+			if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
-+					|| (dma->actual_len
-+						& (musb_ep->packet_sz - 1))) {
-+				/* ack the read! */
-+				csr &= ~MUSB_RXCSR_RXPKTRDY;
-+				musb_writew(epio, MUSB_RXCSR, csr);
-+			}
- 
--		/* incomplete, and not short? wait for next IN packet */
--		if ((request->actual < request->length)
--				&& (musb_ep->dma->actual_len
--					== musb_ep->packet_sz)) {
--			/* In double buffer case, continue to unload fifo if
-- 			 * there is Rx packet in FIFO.
-- 			 **/
--			csr = musb_readw(epio, MUSB_RXCSR);
--			if ((csr & MUSB_RXCSR_RXPKTRDY) &&
--				hw_ep->rx_double_buffered)
--				goto exit;
--			return;
-+			/* incomplete, and not short? wait for next IN packet */
-+			if ((request->actual < request->length)
-+					&& (musb_ep->dma->actual_len
-+						== musb_ep->packet_sz)) {
-+				/* In double buffer case, continue to unload
-+				 * fifo if there is Rx packet in FIFO.
-+				 **/
-+				csr = musb_readw(epio, MUSB_RXCSR);
-+				if ((csr & MUSB_RXCSR_RXPKTRDY) &&
-+					hw_ep->rx_double_buffered)
-+					rxstate(musb, to_musb_request(request));
-+				return;
-+			}
- 		}
--#endif
- 		musb_g_giveback(musb_ep, request, 0);
--		/*
--		 * In the giveback function the MUSB lock is
--		 * released and acquired after sometime. During
--		 * this time period the INDEX register could get
--		 * changed by the gadget_queue function especially
--		 * on SMP systems. Reselect the INDEX to be sure
--		 * we are reading/modifying the right registers
--		 */
--		musb_ep_select(mbase, epnum);
- 
- 		req = next_request(musb_ep);
- 		if (!req)
- 			return;
- 	}
--#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
--	defined(CONFIG_USB_UX500_DMA)
--exit:
--#endif
- 	/* Analyze request */
- 	rxstate(musb, req);
- }
-@@ -1079,7 +1050,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
- 	/* enable the interrupts for the endpoint, set the endpoint
- 	 * packet size (or fail), set the mode, clear the fifo
- 	 */
--	musb_ep_select(mbase, epnum);
-+	musb_ep_select(musb, mbase, epnum);
- 	if (usb_endpoint_dir_in(desc)) {
- 		u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
- 
-@@ -1218,7 +1189,7 @@ static int musb_gadget_disable(struct usb_ep *ep)
- 	epio = musb->endpoints[epnum].regs;
- 
- 	spin_lock_irqsave(&musb->lock, flags);
--	musb_ep_select(musb->mregs, epnum);
-+	musb_ep_select(musb, musb->mregs, epnum);
- 
- 	/* zero the endpoint sizes */
- 	if (musb_ep->is_in) {
-@@ -1297,7 +1268,7 @@ void musb_ep_restart(struct musb *musb, struct musb_request *req)
- 		req->tx ? "TX/IN" : "RX/OUT",
- 		&req->request, req->request.length, req->epnum);
- 
--	musb_ep_select(musb->mregs, req->epnum);
-+	musb_ep_select(musb, musb->mregs, req->epnum);
- 	if (req->tx)
- 		txstate(musb, req);
- 	else
-@@ -1391,7 +1362,7 @@ static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
- 	else if (is_dma_capable() && musb_ep->dma) {
- 		struct dma_controller	*c = musb->dma_controller;
- 
--		musb_ep_select(musb->mregs, musb_ep->current_epnum);
-+		musb_ep_select(musb, musb->mregs, musb_ep->current_epnum);
- 		if (c->channel_abort)
- 			status = c->channel_abort(musb_ep->dma);
- 		else
-@@ -1439,7 +1410,7 @@ static int musb_gadget_set_halt(struct usb_ep *ep, int value)
- 		goto done;
- 	}
- 
--	musb_ep_select(mbase, epnum);
-+	musb_ep_select(musb, mbase, epnum);
- 
- 	request = next_request(musb_ep);
- 	if (value) {
-@@ -1527,7 +1498,7 @@ static int musb_gadget_fifo_status(struct usb_ep *ep)
- 
- 		spin_lock_irqsave(&musb->lock, flags);
- 
--		musb_ep_select(mbase, epnum);
-+		musb_ep_select(musb, mbase, epnum);
- 		/* FIXME return zero unless RXPKTRDY is set */
- 		retval = musb_readw(epio, MUSB_RXCOUNT);
- 
-@@ -1549,7 +1520,7 @@ static void musb_gadget_fifo_flush(struct usb_ep *ep)
- 	mbase = musb->mregs;
- 
- 	spin_lock_irqsave(&musb->lock, flags);
--	musb_ep_select(mbase, (u8) epnum);
-+	musb_ep_select(musb, mbase, (u8) epnum);
- 
- 	/* disable interrupts */
- 	int_txe = musb_readw(mbase, MUSB_INTRTXE);
-@@ -1782,7 +1753,7 @@ static void musb_gadget_release(struct device *dev)
- }
- 
- 
--static void __init
-+static void __devinit
- init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
- {
- 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
-@@ -1819,7 +1790,7 @@ init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
-  * Initialize the endpoints exposed to peripheral drivers, with backlinks
-  * to the rest of the driver state.
-  */
--static inline void __init musb_g_init_endpoints(struct musb *musb)
-+static inline void __devinit musb_g_init_endpoints(struct musb *musb)
- {
- 	u8			epnum;
- 	struct musb_hw_ep	*hw_ep;
-@@ -1852,7 +1823,7 @@ static inline void __init musb_g_init_endpoints(struct musb *musb)
- /* called once during driver setup to initialize and link into
-  * the driver model; memory is zeroed.
-  */
--int __init musb_gadget_setup(struct musb *musb)
-+int __devinit musb_gadget_setup(struct musb *musb)
- {
- 	int status;
- 
-@@ -1862,7 +1833,7 @@ int __init musb_gadget_setup(struct musb *musb)
- 	 */
- 
- 	musb->g.ops = &musb_gadget_operations;
--	musb->g.is_dualspeed = 1;
-+	musb->g.max_speed = USB_SPEED_HIGH;
- 	musb->g.speed = USB_SPEED_UNKNOWN;
- 
- 	/* this "gadget" abstracts/virtualizes the controller */
-@@ -1921,7 +1892,7 @@ static int musb_gadget_start(struct usb_gadget *g,
- 	unsigned long		flags;
- 	int			retval = -EINVAL;
- 
--	if (driver->speed < USB_SPEED_HIGH)
-+	if (driver->max_speed < USB_SPEED_HIGH)
- 		goto err0;
- 
- 	pm_runtime_get_sync(musb->controller);
-@@ -2007,7 +1978,7 @@ static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
- 		for (i = 0, hw_ep = musb->endpoints;
- 				i < musb->nr_endpoints;
- 				i++, hw_ep++) {
--			musb_ep_select(musb->mregs, i);
-+			musb_ep_select(musb, musb->mregs, i);
- 			if (hw_ep->is_shared_fifo /* || !epnum */) {
- 				nuke(&hw_ep->ep_in, -ESHUTDOWN);
- 			} else {
-@@ -2042,7 +2013,8 @@ static int musb_gadget_stop(struct usb_gadget *g,
- 
- 	spin_lock_irqsave(&musb->lock, flags);
- 
--	musb_hnp_stop(musb);
-+	if (is_otg_enabled(musb))
-+		musb_hnp_stop(musb);
- 
- 	(void) musb_gadget_vbus_draw(&musb->g, 0);
- 
-@@ -2156,17 +2128,20 @@ void musb_g_disconnect(struct musb *musb)
- 
- 	switch (musb->xceiv->state) {
- 	default:
--		dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
--			otg_state_string(musb->xceiv->state));
--		musb->xceiv->state = OTG_STATE_A_IDLE;
--		MUSB_HST_MODE(musb);
--		break;
-+		if (is_otg_enabled(musb)) {
-+			dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
-+				otg_state_string(musb->xceiv->state));
-+			musb->xceiv->state = OTG_STATE_A_IDLE;
-+			break;
-+		}
- 	case OTG_STATE_A_PERIPHERAL:
--		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
--		MUSB_HST_MODE(musb);
-+		if (is_otg_enabled(musb))
-+			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
- 		break;
- 	case OTG_STATE_B_WAIT_ACON:
- 	case OTG_STATE_B_HOST:
-+		if (!is_otg_enabled(musb))
-+			break;
- 	case OTG_STATE_B_PERIPHERAL:
- 	case OTG_STATE_B_IDLE:
- 		musb->xceiv->state = OTG_STATE_B_IDLE;
-diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
-index 6a0d046..3e9ec7c 100644
---- a/drivers/usb/musb/musb_gadget_ep0.c
-+++ b/drivers/usb/musb/musb_gadget_ep0.c
-@@ -37,7 +37,6 @@
- #include <linux/list.h>
- #include <linux/timer.h>
- #include <linux/spinlock.h>
--#include <linux/init.h>
- #include <linux/device.h>
- #include <linux/interrupt.h>
- 
-@@ -88,7 +87,7 @@ static int service_tx_status_request(
- 	case USB_RECIP_DEVICE:
- 		result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
- 		result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
--		if (musb->g.is_otg) {
-+		if (is_otg_enabled(musb) && musb->g.is_otg) {
- 			result[0] |= musb->g.b_hnp_enable
- 				<< USB_DEVICE_B_HNP_ENABLE;
- 			result[0] |= musb->g.a_alt_hnp_support
-@@ -128,14 +127,14 @@ static int service_tx_status_request(
- 			break;
- 		}
- 
--		musb_ep_select(mbase, epnum);
-+		musb_ep_select(musb, mbase, epnum);
- 		if (is_in)
- 			tmp = musb_readw(regs, MUSB_TXCSR)
- 						& MUSB_TXCSR_P_SENDSTALL;
- 		else
- 			tmp = musb_readw(regs, MUSB_RXCSR)
- 						& MUSB_RXCSR_P_SENDSTALL;
--		musb_ep_select(mbase, 0);
-+		musb_ep_select(musb, mbase, 0);
- 
- 		result[0] = tmp ? 1 : 0;
- 		} break;
-@@ -152,7 +151,7 @@ static int service_tx_status_request(
- 
- 		if (len > 2)
- 			len = 2;
--		musb_write_fifo(&musb->endpoints[0], len, result);
-+		musb->ops->write_fifo(&musb->endpoints[0], len, result);
- 	}
- 
- 	return handled;
-@@ -283,7 +282,7 @@ __acquires(musb->lock)
- 				if (musb_ep->wedged)
- 					break;
- 
--				musb_ep_select(mbase, epnum);
-+				musb_ep_select(musb, mbase, epnum);
- 				if (is_in) {
- 					csr  = musb_readw(regs, MUSB_TXCSR);
- 					csr |= MUSB_TXCSR_CLRDATATOG |
-@@ -309,7 +308,7 @@ __acquires(musb->lock)
- 				}
- 
- 				/* select ep0 again */
--				musb_ep_select(mbase, 0);
-+				musb_ep_select(musb, mbase, 0);
- 				} break;
- 			default:
- 				/* class, vendor, etc ... delegate */
-@@ -391,20 +390,26 @@ __acquires(musb->lock)
- 						musb->test_mode = true;
- 					break;
- 				case USB_DEVICE_B_HNP_ENABLE:
--					if (!musb->g.is_otg)
--						goto stall;
--					musb->g.b_hnp_enable = 1;
--					musb_try_b_hnp_enable(musb);
-+					if (is_otg_enabled(musb)) {
-+						if (!musb->g.is_otg)
-+							goto stall;
-+						musb->g.b_hnp_enable = 1;
-+						musb_try_b_hnp_enable(musb);
-+					}
- 					break;
- 				case USB_DEVICE_A_HNP_SUPPORT:
--					if (!musb->g.is_otg)
--						goto stall;
--					musb->g.a_hnp_support = 1;
-+					if (is_otg_enabled(musb)) {
-+						if (!musb->g.is_otg)
-+							goto stall;
-+						musb->g.a_hnp_support = 1;
-+					}
- 					break;
- 				case USB_DEVICE_A_ALT_HNP_SUPPORT:
--					if (!musb->g.is_otg)
--						goto stall;
--					musb->g.a_alt_hnp_support = 1;
-+					if (is_otg_enabled(musb)) {
-+						if (!musb->g.is_otg)
-+							goto stall;
-+						musb->g.a_alt_hnp_support = 1;
-+					}
- 					break;
- 				case USB_DEVICE_DEBUG_MODE:
- 					handled = 0;
-@@ -442,7 +447,7 @@ stall:
- 				if (!musb_ep->desc)
- 					break;
- 
--				musb_ep_select(mbase, epnum);
-+				musb_ep_select(musb, mbase, epnum);
- 				if (is_in) {
- 					csr = musb_readw(regs, MUSB_TXCSR);
- 					if (csr & MUSB_TXCSR_FIFONOTEMPTY)
-@@ -461,7 +466,7 @@ stall:
- 				}
- 
- 				/* select ep0 again */
--				musb_ep_select(mbase, 0);
-+				musb_ep_select(musb, mbase, 0);
- 				handled = 1;
- 				} break;
- 
-@@ -506,8 +511,10 @@ static void ep0_rxstate(struct musb *musb)
- 			req->status = -EOVERFLOW;
- 			count = len;
- 		}
--		musb_read_fifo(&musb->endpoints[0], count, buf);
--		req->actual += count;
-+		if (count > 0) {
-+			musb->ops->read_fifo(&musb->endpoints[0], count, buf);
-+			req->actual += count;
-+		}
- 		csr = MUSB_CSR0_P_SVDRXPKTRDY;
- 		if (count < 64 || req->actual == req->length) {
- 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
-@@ -528,7 +535,7 @@ static void ep0_rxstate(struct musb *musb)
- 			return;
- 		musb->ackpend = 0;
- 	}
--	musb_ep_select(musb->mregs, 0);
-+	musb_ep_select(musb, musb->mregs, 0);
- 	musb_writew(regs, MUSB_CSR0, csr);
- }
- 
-@@ -559,7 +566,7 @@ static void ep0_txstate(struct musb *musb)
- 	fifo_src = (u8 *) request->buf + request->actual;
- 	fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
- 		request->length - request->actual);
--	musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
-+	musb->ops->write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
- 	request->actual += fifo_count;
- 
- 	/* update the flags */
-@@ -585,7 +592,7 @@ static void ep0_txstate(struct musb *musb)
- 	}
- 
- 	/* send it out, triggering a "txpktrdy cleared" irq */
--	musb_ep_select(musb->mregs, 0);
-+	musb_ep_select(musb, musb->mregs, 0);
- 	musb_writew(regs, MUSB_CSR0, csr);
- }
- 
-@@ -601,7 +608,7 @@ musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
- 	struct musb_request	*r;
- 	void __iomem		*regs = musb->control_ep->regs;
- 
--	musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
-+	musb->ops->read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
- 
- 	/* NOTE:  earlier 2.6 versions changed setup packets to host
- 	 * order, but now USB packets always stay in USB byte order.
-@@ -670,7 +677,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
- 	void __iomem	*regs = musb->endpoints[0].regs;
- 	irqreturn_t	retval = IRQ_NONE;
- 
--	musb_ep_select(mbase, 0);	/* select ep0 */
-+	musb_ep_select(musb, mbase, 0);	/* select ep0 */
- 	csr = musb_readw(regs, MUSB_CSR0);
- 	len = musb_readb(regs, MUSB_COUNT0);
- 
-@@ -760,6 +767,9 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
- 
- 			musb_writeb(mbase, MUSB_TESTMODE,
- 					musb->test_mode_nr);
-+			if (MUSB_TEST_PACKET == musb->test_mode_nr)
-+				musb_writew(musb->endpoints[0].regs,
-+					MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
- 		}
- 		/* FALLTHROUGH */
- 
-@@ -880,7 +890,7 @@ setup:
- 
- 			handled = forward_to_driver(musb, &setup);
- 			if (handled < 0) {
--				musb_ep_select(mbase, 0);
-+				musb_ep_select(musb, mbase, 0);
- stall:
- 				dev_dbg(musb->controller, "stall (%d)\n", handled);
- 				musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
-@@ -975,7 +985,7 @@ musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
- 			ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
- 			req->request.length);
- 
--	musb_ep_select(musb->mregs, 0);
-+	musb_ep_select(musb, musb->mregs, 0);
- 
- 	/* sequence #1, IN ... start writing the data */
- 	if (musb->ep0_state == MUSB_EP0_STAGE_TX)
-@@ -1038,7 +1048,7 @@ static int musb_g_ep0_halt(struct usb_ep *e, int value)
- 		goto cleanup;
- 	}
- 
--	musb_ep_select(base, 0);
-+	musb_ep_select(musb, base, 0);
- 	csr = musb->ackpend;
- 
- 	switch (musb->ep0_state) {
-diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
-index 79cb0af..c4d44fa 100644
---- a/drivers/usb/musb/musb_host.c
-+++ b/drivers/usb/musb/musb_host.c
-@@ -101,6 +101,30 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
- 			struct urb *urb, int is_out,
- 			u8 *buf, u32 offset, u32 len);
- 
-+void push_queue(struct musb *musb, struct urb *urb)
-+{
-+	spin_lock(&musb->gb_lock);
-+	list_add_tail(&urb->giveback_list, &musb->gb_list);
-+	spin_unlock(&musb->gb_lock);
-+}
-+
-+struct urb *pop_queue(struct musb *musb)
-+{
-+	struct urb *urb;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&musb->gb_lock, flags);
-+	if (list_empty(&musb->gb_list)) {
-+		spin_unlock_irqrestore(&musb->gb_lock, flags);
-+		return NULL;
-+	}
-+	urb = list_entry(musb->gb_list.next, struct urb, giveback_list);
-+	list_del(&urb->giveback_list);
-+	spin_unlock_irqrestore(&musb->gb_lock, flags);
-+
-+	return urb;
-+}
-+
- /*
-  * Clear TX fifo. Needed to avoid BABBLE errors.
-  */
-@@ -117,13 +141,16 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
- 		if (csr != lastcsr)
- 			dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
- 		lastcsr = csr;
--		csr |= MUSB_TXCSR_FLUSHFIFO;
-+		csr = MUSB_TXCSR_FLUSHFIFO;
- 		musb_writew(epio, MUSB_TXCSR, csr);
- 		csr = musb_readw(epio, MUSB_TXCSR);
--		if (WARN(retries-- < 1,
--				"Could not flush host TX%d fifo: csr: %04x\n",
--				ep->epnum, csr))
-+		if (!(csr & MUSB_TXCSR_FIFONOTEMPTY))
-+			break;
-+		if (retries-- < 1) {
-+			dev_dbg(musb->controller, "Could not flush host TX%d fifo: csr: %04x\n",
-+				ep->epnum, csr);
- 			return;
-+		}
- 		mdelay(1);
- 	}
- }
-@@ -178,7 +205,7 @@ static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
- 	/* NOTE: no locks here; caller should lock and select EP */
- 	txcsr = musb_readw(ep->regs, MUSB_TXCSR);
- 	txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
--	if (is_cppi_enabled())
-+	if (is_cppi_enabled(ep->musb) || is_cppi41_enabled(ep->musb))
- 		txcsr |= MUSB_TXCSR_DMAMODE;
- 	musb_writew(ep->regs, MUSB_TXCSR, txcsr);
- }
-@@ -292,15 +319,14 @@ start:
- 
- 		if (!hw_ep->tx_channel)
- 			musb_h_tx_start(hw_ep);
--		else if (is_cppi_enabled() || tusb_dma_omap())
-+		else if (is_cppi_enabled(musb) || is_cppi41_enabled(musb)
-+				|| tusb_dma_omap(musb))
- 			musb_h_tx_dma_start(hw_ep);
- 	}
- }
- 
- /* Context: caller owns controller lock, IRQs are blocked */
- static void musb_giveback(struct musb *musb, struct urb *urb, int status)
--__releases(musb->lock)
--__acquires(musb->lock)
- {
- 	dev_dbg(musb->controller,
- 			"complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
-@@ -311,10 +337,7 @@ __acquires(musb->lock)
- 			urb->actual_length, urb->transfer_buffer_length
- 			);
- 
--	usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
--	spin_unlock(&musb->lock);
- 	usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
--	spin_lock(&musb->lock);
- }
- 
- /* For bulk/interrupt endpoints only */
-@@ -336,6 +359,15 @@ static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
- 
- 	usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
- }
-+/* Used to complete urb giveback */
-+void musb_gb_work(struct work_struct *data)
-+{
-+	struct musb *musb = container_of(data, struct musb, gb_work);
-+	struct urb *urb;
-+
-+	while ((urb = pop_queue(musb)) != 0)
-+		musb_giveback(musb, urb, 0);
-+}
- 
- /*
-  * Advance this hardware endpoint's queue, completing the specified URB and
-@@ -366,20 +398,36 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb,
- 		break;
- 	}
- 
--	qh->is_ready = 0;
--	musb_giveback(musb, urb, status);
--	qh->is_ready = ready;
-+	usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
- 
-+	/* If URB completed with error then giveback first */
-+	if (status != 0) {
-+		qh->is_ready = 0;
-+		spin_unlock(&musb->lock);
-+		musb_giveback(musb, urb, status);
-+		spin_lock(&musb->lock);
-+		qh->is_ready = ready;
-+	}
- 	/* reclaim resources (and bandwidth) ASAP; deschedule it, and
- 	 * invalidate qh as soon as list_empty(&hep->urb_list)
- 	 */
- 	if (list_empty(&qh->hep->urb_list)) {
- 		struct list_head	*head;
-+		struct dma_controller	*dma = musb->dma_controller;
- 
--		if (is_in)
-+		if (is_in) {
- 			ep->rx_reinit = 1;
--		else
-+			if (ep->rx_channel) {
-+				dma->channel_release(ep->rx_channel);
-+				ep->rx_channel = NULL;
-+			}
-+		} else {
- 			ep->tx_reinit = 1;
-+			if (ep->tx_channel) {
-+				dma->channel_release(ep->tx_channel);
-+				ep->tx_channel = NULL;
-+			}
-+		}
- 
- 		/* Clobber old pointers to this qh */
- 		musb_ep_set_qh(ep, is_in, NULL);
-@@ -417,6 +465,12 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb,
- 		    hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
- 		musb_start_urb(musb, is_in, qh);
- 	}
-+
-+	/* if URB is successfully completed then giveback in workqueue */
-+	if (status == 0) {
-+		push_queue(musb, urb);
-+		queue_work(musb->gb_queue, &musb->gb_work);
-+	}
- }
- 
- static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
-@@ -456,7 +510,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
- 	int			pipe = urb->pipe;
- 	void			*buffer = urb->transfer_buffer;
- 
--	/* musb_ep_select(mbase, epnum); */
-+	/* musb_ep_select(musb, mbase, epnum); */
- 	rx_count = musb_readw(epio, MUSB_RXCOUNT);
- 	dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
- 			urb->transfer_buffer, qh->offset,
-@@ -517,7 +571,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
- 			urb->status = -EREMOTEIO;
- 	}
- 
--	musb_read_fifo(hw_ep, length, buf);
-+	musb->ops->read_fifo(hw_ep, length, buf);
- 
- 	csr = musb_readw(epio, MUSB_RXCSR);
- 	csr |= MUSB_RXCSR_H_WZC_BITS;
-@@ -615,36 +669,38 @@ static bool musb_tx_dma_program(struct dma_controller *dma,
- 	u16			csr;
- 	u8			mode;
- 
--#ifdef	CONFIG_USB_INVENTRA_DMA
--	if (length > channel->max_len)
--		length = channel->max_len;
-+	if (is_inventra_dma(hw_ep->musb)) {
-+		if (length > channel->max_len)
-+			length = channel->max_len;
- 
--	csr = musb_readw(epio, MUSB_TXCSR);
--	if (length > pkt_size) {
--		mode = 1;
--		csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
--		/* autoset shouldn't be set in high bandwidth */
--		if (qh->hb_mult == 1)
--			csr |= MUSB_TXCSR_AUTOSET;
-+		csr = musb_readw(epio, MUSB_TXCSR);
-+		if (length > pkt_size) {
-+			mode = 1;
-+			csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
-+			/* autoset shouldn't be set in high bandwidth */
-+			if (qh->hb_mult == 1)
-+				csr |= MUSB_TXCSR_AUTOSET;
-+		} else {
-+			mode = 0;
-+			csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
-+			csr |= MUSB_TXCSR_DMAENAB; /* against progrmr's guide */
-+		}
-+		channel->desired_mode = mode;
-+		musb_writew(epio, MUSB_TXCSR, csr);
- 	} else {
--		mode = 0;
--		csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
--		csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
--	}
--	channel->desired_mode = mode;
--	musb_writew(epio, MUSB_TXCSR, csr);
--#else
--	if (!is_cppi_enabled() && !tusb_dma_omap())
--		return false;
-+		if (!is_cppi_enabled(hw_ep->musb)
-+			&& !is_cppi41_enabled(hw_ep->musb)
-+			&& !tusb_dma_omap(hw_ep->musb))
-+			return false;
- 
--	channel->actual_len = 0;
-+		channel->actual_len = 0;
- 
--	/*
--	 * TX uses "RNDIS" mode automatically but needs help
--	 * to identify the zero-length-final-packet case.
--	 */
--	mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
--#endif
-+		/*
-+		 * TX uses "RNDIS" mode automatically but needs help
-+		 * to identify the zero-length-final-packet case.
-+		 */
-+		mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
-+	}
- 
- 	qh->segsize = length;
- 
-@@ -654,7 +710,8 @@ static bool musb_tx_dma_program(struct dma_controller *dma,
- 	 */
- 	wmb();
- 
--	if (!dma->channel_program(channel, pkt_size, mode,
-+	if (!dma->channel_program(channel, pkt_size |
-+			(qh->hb_mult << 11), mode,
- 			urb->transfer_dma + offset, length)) {
- 		dma->channel_release(channel);
- 		hw_ep->tx_channel = NULL;
-@@ -692,7 +749,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
- 			qh->h_addr_reg, qh->h_port_reg,
- 			len);
- 
--	musb_ep_select(mbase, epnum);
-+	musb_ep_select(musb, mbase, epnum);
- 
- 	/* candidate for DMA? */
- 	dma_controller = musb->dma_controller;
-@@ -779,9 +836,8 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
- 					| ((hw_ep->max_packet_sz_tx /
- 						packet_sz) - 1) << 11);
- 			else
--				musb_writew(epio, MUSB_TXMAXP,
--						qh->maxpacket |
--						((qh->hb_mult - 1) << 11));
-+				musb_writew(epio, MUSB_TXMAXP, qh->maxpacket |
-+						(qh->hb_mult << 11));
- 			musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
- 		} else {
- 			musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
-@@ -803,7 +859,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
- 		if (load_count) {
- 			/* PIO to load FIFO */
- 			qh->segsize = load_count;
--			musb_write_fifo(hw_ep, load_count, buf);
-+			musb->ops->write_fifo(hw_ep, load_count, buf);
- 		}
- 
- 		/* re-enable interrupt */
-@@ -828,9 +884,9 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
- 		} else {
- 			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
- 
--			if (csr & (MUSB_RXCSR_RXPKTRDY
--					| MUSB_RXCSR_DMAENAB
--					| MUSB_RXCSR_H_REQPKT))
-+			if (csr & (MUSB_RXCSR_RXPKTRDY | (is_cppi_enabled(musb)
-+			|| is_cppi41_enabled(musb)) ? 0 : MUSB_RXCSR_DMAENAB
-+			| MUSB_RXCSR_H_REQPKT))
- 				ERR("broken !rx_reinit, ep%d csr %04x\n",
- 						hw_ep->epnum, csr);
- 
-@@ -840,7 +896,8 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
- 
- 		/* kick things off */
- 
--		if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
-+		if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb) ||
-+			tusb_dma_omap(musb)) && dma_channel) {
- 			/* Candidate for DMA */
- 			dma_channel->actual_len = 0L;
- 			qh->segsize = len;
-@@ -854,7 +911,8 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
- 			 * errors, we dare not queue multiple transfers.
- 			 */
- 			dma_ok = dma_controller->channel_program(dma_channel,
--					packet_sz, !(urb->transfer_flags &
-+					packet_sz | (qh->hb_mult << 11),
-+					 !(urb->transfer_flags &
- 						     URB_SHORT_NOT_OK),
- 					urb->transfer_dma + offset,
- 					qh->segsize);
-@@ -872,6 +930,73 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
- 	}
- }
- 
-+/* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
-+ * the end; avoids starvation for other endpoints.
-+ */
-+static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
-+	int is_in)
-+{
-+	struct dma_channel	*dma;
-+	struct urb		*urb;
-+	void __iomem		*mbase = musb->mregs;
-+	void __iomem		*epio = ep->regs;
-+	struct musb_qh		*cur_qh, *next_qh;
-+	u16			rx_csr, tx_csr;
-+
-+	musb_ep_select(musb, mbase, ep->epnum);
-+	if (is_in) {
-+		dma = is_dma_capable() ? ep->rx_channel : NULL;
-+
-+		/* clear nak timeout bit */
-+		rx_csr = musb_readw(epio, MUSB_RXCSR);
-+		rx_csr |= MUSB_RXCSR_H_WZC_BITS;
-+		rx_csr &= ~MUSB_RXCSR_DATAERROR;
-+		musb_writew(epio, MUSB_RXCSR, rx_csr);
-+
-+		cur_qh = first_qh(&musb->in_bulk);
-+	} else {
-+		dma = is_dma_capable() ? ep->tx_channel : NULL;
-+
-+		/* clear nak timeout bit */
-+		tx_csr = musb_readw(epio, MUSB_TXCSR);
-+		tx_csr |= MUSB_TXCSR_H_WZC_BITS;
-+		tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
-+		musb_writew(epio, MUSB_TXCSR, tx_csr);
-+
-+		cur_qh = first_qh(&musb->out_bulk);
-+	}
-+	if (cur_qh) {
-+		urb = next_urb(cur_qh);
-+		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
-+			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
-+			musb->dma_controller->channel_abort(dma);
-+			urb->actual_length += dma->actual_len;
-+			dma->actual_len = 0L;
-+		}
-+		musb_save_toggle(cur_qh, is_in, urb);
-+
-+		if (is_in) {
-+			/* move cur_qh to end of queue */
-+			list_move_tail(&cur_qh->ring, &musb->in_bulk);
-+
-+			/* get the next qh from musb->in_bulk */
-+			next_qh = first_qh(&musb->in_bulk);
-+
-+			/* set rx_reinit and schedule the next qh */
-+			ep->rx_reinit = 1;
-+		} else {
-+			/* move cur_qh to end of queue */
-+			list_move_tail(&cur_qh->ring, &musb->out_bulk);
-+
-+			/* get the next qh from musb->out_bulk */
-+			next_qh = first_qh(&musb->out_bulk);
-+
-+			/* set tx_reinit and schedule the next qh */
-+			ep->tx_reinit = 1;
-+		}
-+		musb_start_urb(musb, is_in, next_qh);
-+	}
-+}
- 
- /*
-  * Service the default endpoint (ep0) as host.
-@@ -894,7 +1019,7 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
- 		if (fifo_count < len)
- 			urb->status = -EOVERFLOW;
- 
--		musb_read_fifo(hw_ep, fifo_count, fifo_dest);
-+		musb->ops->read_fifo(hw_ep, fifo_count, fifo_dest);
- 
- 		urb->actual_length += fifo_count;
- 		if (len < qh->maxpacket) {
-@@ -933,7 +1058,7 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
- 					fifo_count,
- 					(fifo_count == 1) ? "" : "s",
- 					fifo_dest);
--			musb_write_fifo(hw_ep, fifo_count, fifo_dest);
-+			musb->ops->write_fifo(hw_ep, fifo_count, fifo_dest);
- 
- 			urb->actual_length += fifo_count;
- 			more = true;
-@@ -968,7 +1093,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
- 	/* ep0 only has one queue, "in" */
- 	urb = next_urb(qh);
- 
--	musb_ep_select(mbase, 0);
-+	musb_ep_select(musb, mbase, 0);
- 	csr = musb_readw(epio, MUSB_CSR0);
- 	len = (csr & MUSB_CSR0_RXPKTRDY)
- 			? musb_readb(epio, MUSB_COUNT0)
-@@ -1054,6 +1179,8 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
- 			else
- 				csr = MUSB_CSR0_H_STATUSPKT
- 					| MUSB_CSR0_TXPKTRDY;
-+			/* disable ping token in status phase */
-+				csr |= MUSB_CSR0_H_DIS_PING;
- 
- 			/* flag status stage */
- 			musb->ep0_stage = MUSB_EP0_STATUS;
-@@ -1074,8 +1201,6 @@ done:
- }
- 
- 
--#ifdef CONFIG_USB_INVENTRA_DMA
--
- /* Host side TX (OUT) using Mentor DMA works as follows:
- 	submit_urb ->
- 		- if queue was empty, Program Endpoint
-@@ -1088,8 +1213,6 @@ done:
- 			short packets in mode 1.
- */
- 
--#endif
--
- /* Service a Tx-Available or dma completion irq for the endpoint */
- void musb_host_tx(struct musb *musb, u8 epnum)
- {
-@@ -1107,7 +1230,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
- 	struct dma_channel	*dma;
- 	bool			transfer_pending = false;
- 
--	musb_ep_select(mbase, epnum);
-+	musb_ep_select(musb, mbase, epnum);
- 	tx_csr = musb_readw(epio, MUSB_TXCSR);
- 
- 	/* with CPPI, DMA sometimes triggers "extra" irqs */
-@@ -1136,20 +1259,27 @@ void musb_host_tx(struct musb *musb, u8 epnum)
- 		status = -ETIMEDOUT;
- 
- 	} else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
--		dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
-+		if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
-+				&& !list_is_singular(&musb->out_bulk)) {
- 
--		/* NOTE:  this code path would be a good place to PAUSE a
--		 * transfer, if there's some other (nonperiodic) tx urb
--		 * that could use this fifo.  (dma complicates it...)
--		 * That's already done for bulk RX transfers.
--		 *
--		 * if (bulk && qh->ring.next != &musb->out_bulk), then
--		 * we have a candidate... NAKing is *NOT* an error
--		 */
--		musb_ep_select(mbase, epnum);
--		musb_writew(epio, MUSB_TXCSR,
--				MUSB_TXCSR_H_WZC_BITS
--				| MUSB_TXCSR_TXPKTRDY);
-+			dev_dbg(musb->controller, "TX end %d NAK timeout\n", epnum);
-+			musb_bulk_nak_timeout(musb, hw_ep, 0);
-+		} else {
-+			dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
-+
-+			/* NOTE: this code path would be a good place to PAUSE a
-+			 * transfer, if there's some other (nonperiodic) tx urb
-+			 * that could use this fifo.  (dma complicates it...)
-+			 * That's already done for bulk RX transfers.
-+			 *
-+			 * if (bulk && qh->ring.next != &musb->out_bulk), then
-+			 * we have a candidate... NAKing is *NOT* an error
-+			 */
-+			musb_ep_select(musb, mbase, epnum);
-+			musb_writew(epio, MUSB_TXCSR,
-+					MUSB_TXCSR_H_WZC_BITS
-+					| MUSB_TXCSR_TXPKTRDY);
-+		}
- 		return;
- 	}
- 
-@@ -1170,7 +1300,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
- 				| MUSB_TXCSR_H_NAKTIMEOUT
- 				);
- 
--		musb_ep_select(mbase, epnum);
-+		musb_ep_select(musb, mbase, epnum);
- 		musb_writew(epio, MUSB_TXCSR, tx_csr);
- 		/* REVISIT may need to clear FLUSHFIFO ... */
- 		musb_writew(epio, MUSB_TXCSR, tx_csr);
-@@ -1302,7 +1432,8 @@ void musb_host_tx(struct musb *musb, u8 epnum)
- 	} else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
- 		if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
- 				offset, length)) {
--			if (is_cppi_enabled() || tusb_dma_omap())
-+			if (is_cppi_enabled(musb) || is_cppi41_enabled(musb) ||
-+					tusb_dma_omap(musb))
- 				musb_h_tx_dma_start(hw_ep);
- 			return;
- 		}
-@@ -1322,17 +1453,15 @@ void musb_host_tx(struct musb *musb, u8 epnum)
- 		length = qh->maxpacket;
- 	/* Unmap the buffer so that CPU can use it */
- 	usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
--	musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
-+	musb->ops->write_fifo(hw_ep, length, urb->transfer_buffer + offset);
- 	qh->segsize = length;
- 
--	musb_ep_select(mbase, epnum);
-+	musb_ep_select(musb, mbase, epnum);
- 	musb_writew(epio, MUSB_TXCSR,
- 			MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
- }
- 
- 
--#ifdef CONFIG_USB_INVENTRA_DMA
--
- /* Host side RX (IN) using Mentor DMA works as follows:
- 	submit_urb ->
- 		- if queue was empty, ProgramEndpoint
-@@ -1368,52 +1497,6 @@ void musb_host_tx(struct musb *musb, u8 epnum)
-  *	last packet of one URB's transfer.
-  */
- 
--#endif
--
--/* Schedule next QH from musb->in_bulk and move the current qh to
-- * the end; avoids starvation for other endpoints.
-- */
--static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
--{
--	struct dma_channel	*dma;
--	struct urb		*urb;
--	void __iomem		*mbase = musb->mregs;
--	void __iomem		*epio = ep->regs;
--	struct musb_qh		*cur_qh, *next_qh;
--	u16			rx_csr;
--
--	musb_ep_select(mbase, ep->epnum);
--	dma = is_dma_capable() ? ep->rx_channel : NULL;
--
--	/* clear nak timeout bit */
--	rx_csr = musb_readw(epio, MUSB_RXCSR);
--	rx_csr |= MUSB_RXCSR_H_WZC_BITS;
--	rx_csr &= ~MUSB_RXCSR_DATAERROR;
--	musb_writew(epio, MUSB_RXCSR, rx_csr);
--
--	cur_qh = first_qh(&musb->in_bulk);
--	if (cur_qh) {
--		urb = next_urb(cur_qh);
--		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
--			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
--			musb->dma_controller->channel_abort(dma);
--			urb->actual_length += dma->actual_len;
--			dma->actual_len = 0L;
--		}
--		musb_save_toggle(cur_qh, 1, urb);
--
--		/* move cur_qh to end of queue */
--		list_move_tail(&cur_qh->ring, &musb->in_bulk);
--
--		/* get the next qh from musb->in_bulk */
--		next_qh = first_qh(&musb->in_bulk);
--
--		/* set rx_reinit and schedule the next qh */
--		ep->rx_reinit = 1;
--		musb_start_urb(musb, 1, next_qh);
--	}
--}
--
- /*
-  * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
-  * and high-bandwidth IN transfer cases.
-@@ -1433,7 +1516,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 	u32			status;
- 	struct dma_channel	*dma;
- 
--	musb_ep_select(mbase, epnum);
-+	musb_ep_select(musb, mbase, epnum);
- 
- 	urb = next_urb(qh);
- 	dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
-@@ -1490,10 +1573,10 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 			if (usb_pipebulk(urb->pipe)
- 					&& qh->mux == 1
- 					&& !list_is_singular(&musb->in_bulk)) {
--				musb_bulk_rx_nak_timeout(musb, hw_ep);
-+				musb_bulk_nak_timeout(musb, hw_ep, 1);
- 				return;
- 			}
--			musb_ep_select(mbase, epnum);
-+			musb_ep_select(musb, mbase, epnum);
- 			rx_csr |= MUSB_RXCSR_H_WZC_BITS;
- 			rx_csr &= ~MUSB_RXCSR_DATAERROR;
- 			musb_writew(epio, MUSB_RXCSR, rx_csr);
-@@ -1537,8 +1620,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 
- 	/* FIXME this is _way_ too much in-line logic for Mentor DMA */
- 
--#ifndef CONFIG_USB_INVENTRA_DMA
--	if (rx_csr & MUSB_RXCSR_H_REQPKT)  {
-+	if (!is_inventra_dma(musb) && (rx_csr & MUSB_RXCSR_H_REQPKT))  {
- 		/* REVISIT this happened for a while on some short reads...
- 		 * the cleanup still needs investigation... looks bad...
- 		 * and also duplicates dma cleanup code above ... plus,
-@@ -1555,11 +1637,10 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 				xfer_len, dma ? ", dma" : "");
- 		rx_csr &= ~MUSB_RXCSR_H_REQPKT;
- 
--		musb_ep_select(mbase, epnum);
-+		musb_ep_select(musb, mbase, epnum);
- 		musb_writew(epio, MUSB_RXCSR,
- 				MUSB_RXCSR_H_WZC_BITS | rx_csr);
- 	}
--#endif
- 	if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
- 		xfer_len = dma->actual_len;
- 
-@@ -1567,9 +1648,12 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 			| MUSB_RXCSR_H_AUTOREQ
- 			| MUSB_RXCSR_AUTOCLEAR
- 			| MUSB_RXCSR_RXPKTRDY);
-+
-+		if (is_cppi_enabled(musb) || is_cppi41_enabled(musb))
-+			val |= MUSB_RXCSR_DMAENAB;
-+
- 		musb_writew(hw_ep->regs, MUSB_RXCSR, val);
- 
--#ifdef CONFIG_USB_INVENTRA_DMA
- 		if (usb_pipeisoc(pipe)) {
- 			struct usb_iso_packet_descriptor *d;
- 
-@@ -1584,14 +1668,33 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 
- 			if (++qh->iso_idx >= urb->number_of_packets)
- 				done = true;
--			else
-+			else if (is_cppi_enabled(musb) ||
-+					is_cppi41_enabled(musb)) {
-+				struct dma_controller   *c;
-+				void *buf;
-+				u32 length, ret;
-+
-+				c = musb->dma_controller;
-+				buf = (void *)
-+					urb->iso_frame_desc[qh->iso_idx].offset
-+					+ (u32)urb->transfer_dma;
-+
-+				length =
-+					urb->iso_frame_desc[qh->iso_idx].length;
-+
-+				ret = c->channel_program(dma, qh->maxpacket |
-+						(qh->hb_mult << 11),
-+						0, (u32) buf, length);
- 				done = false;
--
-+			} else {
-+				done = false;
-+			}
- 		} else  {
--		/* done if urb buffer is full or short packet is recd */
--		done = (urb->actual_length + xfer_len >=
--				urb->transfer_buffer_length
--			|| dma->actual_len < qh->maxpacket);
-+			/* done if urb buffer is full or short packet is recd */
-+			done = (urb->actual_length + xfer_len >=
-+					urb->transfer_buffer_length
-+				|| dma->actual_len < qh->maxpacket
-+				|| dma->actual_len % qh->maxpacket);
- 		}
- 
- 		/* send IN token for next packet, without AUTOREQ */
-@@ -1601,13 +1704,11 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 				MUSB_RXCSR_H_WZC_BITS | val);
- 		}
- 
--		dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
-+		dev_dbg(musb->controller,
-+			"ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
- 			done ? "off" : "reset",
- 			musb_readw(epio, MUSB_RXCSR),
- 			musb_readw(epio, MUSB_RXCOUNT));
--#else
--		done = true;
--#endif
- 	} else if (urb->status == -EINPROGRESS) {
- 		/* if no errors, be sure a packet is ready for unloading */
- 		if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
-@@ -1618,14 +1719,13 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 
- /* SCRUB (RX) */
- 			/* do the proper sequence to abort the transfer */
--			musb_ep_select(mbase, epnum);
-+			musb_ep_select(musb, mbase, epnum);
- 			val &= ~MUSB_RXCSR_H_REQPKT;
- 			musb_writew(epio, MUSB_RXCSR, val);
- 			goto finish;
- 		}
- 
- 		/* we are expecting IN packets */
--#ifdef CONFIG_USB_INVENTRA_DMA
- 		if (dma) {
- 			struct dma_controller	*c;
- 			u16			rx_count;
-@@ -1729,7 +1829,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 			 * adjusted first...
- 			 */
- 			ret = c->channel_program(
--				dma, qh->maxpacket,
-+				dma, qh->maxpacket | ((qh->hb_mult - 1) << 11),
- 				dma->desired_mode, buf, length);
- 
- 			if (!ret) {
-@@ -1739,7 +1839,6 @@ void musb_host_rx(struct musb *musb, u8 epnum)
- 				/* REVISIT reset CSR */
- 			}
- 		}
--#endif	/* Mentor DMA */
- 
- 		if (!dma) {
- 			/* Unmap the buffer so that CPU can use it */
-@@ -1849,14 +1948,14 @@ static int musb_schedule(
- 		else
- 			head = &musb->out_bulk;
- 
--		/* Enable bulk RX NAK timeout scheme when bulk requests are
-+		/* Enable bulk RX/TX NAK timeout scheme when bulk requests are
- 		 * multiplexed.  This scheme doen't work in high speed to full
- 		 * speed scenario as NAK interrupts are not coming from a
- 		 * full speed device connected to a high speed device.
- 		 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
- 		 * 4 (8 frame or 8ms) for FS device.
- 		 */
--		if (is_in && qh->dev)
-+		if (qh->dev)
- 			qh->intv_reg =
- 				(USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
- 		goto success;
-@@ -1904,6 +2003,8 @@ static int musb_urb_enqueue(
- 	qh = ret ? NULL : hep->hcpriv;
- 	if (qh)
- 		urb->hcpriv = qh;
-+
-+	INIT_LIST_HEAD(&urb->giveback_list);
- 	spin_unlock_irqrestore(&musb->lock, flags);
- 
- 	/* DMA mapping was already done, if needed, and this urb is on
-@@ -2081,7 +2182,7 @@ static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
- 	int			status = 0;
- 	u16			csr;
- 
--	musb_ep_select(regs, hw_end);
-+	musb_ep_select(ep->musb, regs, hw_end);
- 
- 	if (is_dma_capable()) {
- 		struct dma_channel	*dma;
-@@ -2167,8 +2268,12 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
- 			|| musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
- 		int	ready = qh->is_ready;
- 
-+		usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
-+
- 		qh->is_ready = 0;
-+		spin_unlock(&musb->lock);
- 		musb_giveback(musb, urb, 0);
-+		spin_lock(&musb->lock);
- 		qh->is_ready = ready;
- 
- 		/* If nothing else (usually musb_giveback) is using it
-@@ -2229,8 +2334,13 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
- 		 * other transfers, and since !qh->is_ready nothing
- 		 * will activate any of these as it advances.
- 		 */
--		while (!list_empty(&hep->urb_list))
--			musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
-+		while (!list_empty(&hep->urb_list)) {
-+			urb = next_urb(qh);
-+			usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
-+			spin_unlock(&musb->lock);
-+			musb_giveback(musb, urb, -ESHUTDOWN);
-+			spin_lock(&musb->lock);
-+		}
- 
- 		hep->hcpriv = NULL;
- 		list_del(&qh->ring);
-@@ -2290,7 +2400,7 @@ static int musb_bus_suspend(struct usb_hcd *hcd)
- 	}
- 
- 	if (musb->is_active) {
--		WARNING("trying to suspend as %s while active\n",
-+		dev_dbg(musb->controller, "trying to suspend as %s while active\n",
- 				otg_state_string(musb->xceiv->state));
- 		return -EBUSY;
- 	} else
-@@ -2299,7 +2409,6 @@ static int musb_bus_suspend(struct usb_hcd *hcd)
- 
- static int musb_bus_resume(struct usb_hcd *hcd)
- {
--	/* resuming child port does the work */
- 	return 0;
- }
- 
-diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h
-index 03c6ccd..af554fe 100644
---- a/drivers/usb/musb/musb_io.h
-+++ b/drivers/usb/musb/musb_io.h
-@@ -61,75 +61,26 @@ static inline void writesb(const void __iomem *addr, const void *buf, int len)
- /* NOTE:  these offsets are all in bytes */
- 
- static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
--	{ return __raw_readw(addr + offset); }
-+	{ return readw(addr + offset); }
- 
- static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
--	{ return __raw_readl(addr + offset); }
-+	{ return readl(addr + offset); }
- 
- 
- static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
--	{ __raw_writew(data, addr + offset); }
-+	{ writew(data, addr + offset); }
- 
- static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
--	{ __raw_writel(data, addr + offset); }
--
--
--#ifdef CONFIG_USB_MUSB_TUSB6010
--
--/*
-- * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
-- */
--static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
--{
--	u16 tmp;
--	u8 val;
--
--	tmp = __raw_readw(addr + (offset & ~1));
--	if (offset & 1)
--		val = (tmp >> 8);
--	else
--		val = tmp & 0xff;
--
--	return val;
--}
--
--static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
--{
--	u16 tmp;
--
--	tmp = __raw_readw(addr + (offset & ~1));
--	if (offset & 1)
--		tmp = (data << 8) | (tmp & 0xff);
--	else
--		tmp = (tmp & 0xff00) | data;
--
--	__raw_writew(tmp, addr + (offset & ~1));
--}
-+	{ writel(data, addr + offset); }
- 
- #else
- 
--static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
--	{ return __raw_readb(addr + offset); }
--
--static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
--	{ __raw_writeb(data, addr + offset); }
--
--#endif	/* CONFIG_USB_MUSB_TUSB6010 */
--
--#else
--
--static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
--	{ return (u8) (bfin_read16(addr + offset)); }
--
- static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
- 	{ return bfin_read16(addr + offset); }
- 
- static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
- 	{ return (u32) (bfin_read16(addr + offset)); }
- 
--static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
--	{ bfin_write16(addr + offset, (u16) data); }
--
- static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
- 	{ bfin_write16(addr + offset, data); }
- 
-diff --git a/drivers/usb/musb/musb_procfs.c b/drivers/usb/musb/musb_procfs.c
-new file mode 100644
-index 0000000..e3aa42f
---- /dev/null
-+++ b/drivers/usb/musb/musb_procfs.c
-@@ -0,0 +1,808 @@
-+/*
-+ * MUSB OTG driver debug support
-+ *
-+ * Copyright 2005 Mentor Graphics Corporation
-+ * Copyright (C) 2005-2006 by Texas Instruments
-+ * Copyright (C) 2006-2007 Nokia Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
-+ * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/proc_fs.h>
-+#include <linux/seq_file.h>
-+#include <linux/uaccess.h>	/* FIXME remove procfs writes */
-+#include <mach/hardware.h>
-+
-+#include "musb_core.h"
-+
-+#include "davinci.h"
-+
-+static int dump_qh(struct musb_qh *qh, char *buf, unsigned max)
-+{
-+	int				count;
-+	int				tmp;
-+	struct usb_host_endpoint	*hep = qh->hep;
-+	struct urb			*urb;
-+
-+	count = snprintf(buf, max, "    qh %p dev%d ep%d%s max%d\n",
-+			qh, qh->dev->devnum, qh->epnum,
-+			({ char *s; switch (qh->type) {
-+			case USB_ENDPOINT_XFER_BULK:
-+				s = "-bulk"; break;
-+			case USB_ENDPOINT_XFER_INT:
-+				s = "-int"; break;
-+			case USB_ENDPOINT_XFER_CONTROL:
-+				s = ""; break;
-+			default:
-+				s = "iso"; break;
-+			}; s; }),
-+			qh->maxpacket);
-+	if (count <= 0)
-+		return 0;
-+	buf += count;
-+	max -= count;
-+
-+	list_for_each_entry(urb, &hep->urb_list, urb_list) {
-+		tmp = snprintf(buf, max, "\t%s urb %p %d/%d\n",
-+				usb_pipein(urb->pipe) ? "in" : "out",
-+				urb, urb->actual_length,
-+				urb->transfer_buffer_length);
-+		if (tmp <= 0)
-+			break;
-+		tmp = min(tmp, (int)max);
-+		count += tmp;
-+		buf += tmp;
-+		max -= tmp;
-+	}
-+	return count;
-+}
-+
-+static int
-+dump_queue(struct list_head *q, char *buf, unsigned max)
-+{
-+	int		count = 0;
-+	struct musb_qh	*qh;
-+
-+	list_for_each_entry(qh, q, ring) {
-+		int	tmp;
-+
-+		tmp = dump_qh(qh, buf, max);
-+		if (tmp <= 0)
-+			break;
-+		tmp = min(tmp, (int)max);
-+		count += tmp;
-+		buf += tmp;
-+		max -= tmp;
-+	}
-+	return count;
-+}
-+
-+static int dump_ep(struct musb_ep *ep, char *buffer, unsigned max)
-+{
-+	char		*buf = buffer;
-+	int		code = 0;
-+	void __iomem	*regs = ep->hw_ep->regs;
-+	char		*mode = "1buf";
-+
-+	if (ep->is_in) {
-+		if (ep->hw_ep->tx_double_buffered)
-+			mode = "2buf";
-+	} else {
-+		if (ep->hw_ep->rx_double_buffered)
-+			mode = "2buf";
-+	}
-+
-+	do {
-+		struct usb_request	*req;
-+
-+		code = snprintf(buf, max,
-+				"\n%s (hw%d): %s%s, csr %04x maxp %04x\n",
-+				ep->name, ep->current_epnum,
-+				mode, ep->dma ? " dma" : "",
-+				musb_readw(regs,
-+					(ep->is_in || !ep->current_epnum)
-+						? MUSB_TXCSR
-+						: MUSB_RXCSR),
-+				musb_readw(regs, ep->is_in
-+						? MUSB_TXMAXP
-+						: MUSB_RXMAXP)
-+				);
-+		if (code <= 0)
-+			break;
-+		code = min(code, (int) max);
-+		buf += code;
-+		max -= code;
-+
-+		if ((is_cppi_enabled(ep->musb) || is_cppi41_enabled(ep->musb))
-+				&& ep->current_epnum) {
-+			unsigned	cppi = ep->current_epnum - 1;
-+			void __iomem	*base = ep->musb->ctrl_base;
-+			unsigned	off1 = cppi << 2;
-+			void __iomem	*ram = base;
-+			char		tmp[16];
-+
-+			if (ep->is_in) {
-+				ram += DAVINCI_TXCPPI_STATERAM_OFFSET(cppi);
-+				tmp[0] = 0;
-+			} else {
-+				ram += DAVINCI_RXCPPI_STATERAM_OFFSET(cppi);
-+				snprintf(tmp, sizeof tmp, "%d left, ",
-+					musb_readl(base,
-+					DAVINCI_RXCPPI_BUFCNT0_REG + off1));
-+			}
-+
-+			code = snprintf(buf, max, "%cX DMA%d: %s"
-+					"%08x %08x, %08x %08x; "
-+					"%08x %08x %08x .. %08x\n",
-+				ep->is_in ? 'T' : 'R',
-+				ep->current_epnum - 1, tmp,
-+				musb_readl(ram, 0 * 4),
-+				musb_readl(ram, 1 * 4),
-+				musb_readl(ram, 2 * 4),
-+				musb_readl(ram, 3 * 4),
-+				musb_readl(ram, 4 * 4),
-+				musb_readl(ram, 5 * 4),
-+				musb_readl(ram, 6 * 4),
-+				musb_readl(ram, 7 * 4));
-+			if (code <= 0)
-+				break;
-+			code = min(code, (int) max);
-+			buf += code;
-+			max -= code;
-+		}
-+
-+		if (list_empty(&ep->req_list)) {
-+			code = snprintf(buf, max, "\t(queue empty)\n");
-+			if (code <= 0)
-+				break;
-+			code = min(code, (int) max);
-+			buf += code;
-+			max -= code;
-+			break;
-+		}
-+		list_for_each_entry(req, &ep->req_list, list) {
-+			code = snprintf(buf, max, "\treq %p, %s%s%d/%d\n",
-+					req,
-+					req->zero ? "zero, " : "",
-+					req->short_not_ok ? "!short, " : "",
-+					req->actual, req->length);
-+			if (code <= 0)
-+				break;
-+			code = min(code, (int) max);
-+			buf += code;
-+			max -= code;
-+		}
-+	} while (0);
-+	return buf - buffer;
-+}
-+
-+static int
-+dump_end_info(struct musb *musb, u8 epnum, char *aBuffer, unsigned max)
-+{
-+	int			code = 0;
-+	char			*buf = aBuffer;
-+	struct musb_hw_ep	*hw_ep = &musb->endpoints[epnum];
-+
-+	do {
-+		musb_ep_select(musb, musb->mregs, epnum);
-+		if (is_host_active(musb)) {
-+			int		dump_rx, dump_tx;
-+			void __iomem	*regs = hw_ep->regs;
-+
-+			/* TEMPORARY (!) until we have a real periodic
-+			 * schedule tree ...
-+			 */
-+			if (!epnum) {
-+				/* control is shared, uses RX queue
-+				 * but (mostly) shadowed tx registers
-+				 */
-+				dump_tx = !list_empty(&musb->control);
-+				dump_rx = 0;
-+			} else if (hw_ep == musb->bulk_ep) {
-+				dump_tx = !list_empty(&musb->out_bulk);
-+				dump_rx = !list_empty(&musb->in_bulk);
-+			} else if (hw_ep->in_qh || hw_ep->out_qh) {
-+				if (hw_ep->in_qh)
-+					dump_rx = 1;
-+				else
-+					dump_rx = 0;
-+				dump_tx = !dump_rx;
-+			} else
-+				break;
-+			/* END TEMPORARY */
-+
-+
-+			if (dump_rx) {
-+				code = snprintf(buf, max,
-+					"\nRX%d: %s rxcsr %04x interval %02x "
-+					"max %04x type %02x; "
-+					"dev %d hub %d port %d"
-+					"\n",
-+					epnum,
-+					hw_ep->rx_double_buffered
-+						? "2buf" : "1buf",
-+					musb_readw(regs, MUSB_RXCSR),
-+					musb_readb(regs, MUSB_RXINTERVAL),
-+					musb_readw(regs, MUSB_RXMAXP),
-+					musb_readb(regs, MUSB_RXTYPE),
-+					/* FIXME:  assumes multipoint */
-+					musb_readb(musb->mregs,
-+						MUSB_BUSCTL_OFFSET(epnum,
-+						MUSB_RXFUNCADDR)),
-+					musb_readb(musb->mregs,
-+						MUSB_BUSCTL_OFFSET(epnum,
-+						MUSB_RXHUBADDR)),
-+					musb_readb(musb->mregs,
-+						MUSB_BUSCTL_OFFSET(epnum,
-+						MUSB_RXHUBPORT))
-+					);
-+				if (code <= 0)
-+					break;
-+				code = min(code, (int) max);
-+				buf += code;
-+				max -= code;
-+
-+				if ((is_cppi_enabled(musb) ||
-+						is_cppi41_enabled(musb))
-+						&& epnum
-+						&& hw_ep->rx_channel) {
-+					unsigned	cppi = epnum - 1;
-+					unsigned	off1 = cppi << 2;
-+					void __iomem	*base;
-+					void __iomem	*ram;
-+					char		tmp[16];
-+
-+					base = musb->ctrl_base;
-+					ram = DAVINCI_RXCPPI_STATERAM_OFFSET(
-+							cppi) + base;
-+					snprintf(tmp, sizeof tmp, "%d left, ",
-+						musb_readl(base,
-+						DAVINCI_RXCPPI_BUFCNT0_REG
-+								+ off1));
-+
-+					code = snprintf(buf, max,
-+						"    rx dma%d: %s"
-+						"%08x %08x, %08x %08x; "
-+						"%08x %08x %08x .. %08x\n",
-+						cppi, tmp,
-+						musb_readl(ram, 0 * 4),
-+						musb_readl(ram, 1 * 4),
-+						musb_readl(ram, 2 * 4),
-+						musb_readl(ram, 3 * 4),
-+						musb_readl(ram, 4 * 4),
-+						musb_readl(ram, 5 * 4),
-+						musb_readl(ram, 6 * 4),
-+						musb_readl(ram, 7 * 4));
-+					if (code <= 0)
-+						break;
-+					code = min(code, (int) max);
-+					buf += code;
-+					max -= code;
-+				}
-+
-+				if (hw_ep == musb->bulk_ep
-+						&& !list_empty(
-+							&musb->in_bulk)) {
-+					code = dump_queue(&musb->in_bulk,
-+							buf, max);
-+					if (code <= 0)
-+						break;
-+					code = min(code, (int) max);
-+					buf += code;
-+					max -= code;
-+				} else if (hw_ep->in_qh) {
-+					code = dump_qh(hw_ep->in_qh,
-+							buf, max);
-+					if (code <= 0)
-+						break;
-+					code = min(code, (int) max);
-+					buf += code;
-+					max -= code;
-+				}
-+			}
-+
-+			if (dump_tx) {
-+				code = snprintf(buf, max,
-+					"\nTX%d: %s txcsr %04x interval %02x "
-+					"max %04x type %02x; "
-+					"dev %d hub %d port %d"
-+					"\n",
-+					epnum,
-+					hw_ep->tx_double_buffered
-+						? "2buf" : "1buf",
-+					musb_readw(regs, MUSB_TXCSR),
-+					musb_readb(regs, MUSB_TXINTERVAL),
-+					musb_readw(regs, MUSB_TXMAXP),
-+					musb_readb(regs, MUSB_TXTYPE),
-+					/* FIXME:  assumes multipoint */
-+					musb_readb(musb->mregs,
-+						MUSB_BUSCTL_OFFSET(epnum,
-+						MUSB_TXFUNCADDR)),
-+					musb_readb(musb->mregs,
-+						MUSB_BUSCTL_OFFSET(epnum,
-+						MUSB_TXHUBADDR)),
-+					musb_readb(musb->mregs,
-+						MUSB_BUSCTL_OFFSET(epnum,
-+						MUSB_TXHUBPORT))
-+					);
-+				if (code <= 0)
-+					break;
-+				code = min(code, (int) max);
-+				buf += code;
-+				max -= code;
-+
-+				if ((is_cppi_enabled(musb) ||
-+						is_cppi41_enabled(musb))
-+						&& epnum
-+						&& hw_ep->tx_channel) {
-+					unsigned	cppi = epnum - 1;
-+					void __iomem	*base;
-+					void __iomem	*ram;
-+
-+					base = musb->ctrl_base;
-+					ram = DAVINCI_RXCPPI_STATERAM_OFFSET(
-+							cppi) + base;
-+					code = snprintf(buf, max,
-+						"    tx dma%d: "
-+						"%08x %08x, %08x %08x; "
-+						"%08x %08x %08x .. %08x\n",
-+						cppi,
-+						musb_readl(ram, 0 * 4),
-+						musb_readl(ram, 1 * 4),
-+						musb_readl(ram, 2 * 4),
-+						musb_readl(ram, 3 * 4),
-+						musb_readl(ram, 4 * 4),
-+						musb_readl(ram, 5 * 4),
-+						musb_readl(ram, 6 * 4),
-+						musb_readl(ram, 7 * 4));
-+					if (code <= 0)
-+						break;
-+					code = min(code, (int) max);
-+					buf += code;
-+					max -= code;
-+				}
-+
-+				if (hw_ep == musb->control_ep
-+						&& !list_empty(
-+							&musb->control)) {
-+					code = dump_queue(&musb->control,
-+							buf, max);
-+					if (code <= 0)
-+						break;
-+					code = min(code, (int) max);
-+					buf += code;
-+					max -= code;
-+				} else if (hw_ep == musb->bulk_ep
-+						&& !list_empty(
-+							&musb->out_bulk)) {
-+					code = dump_queue(&musb->out_bulk,
-+							buf, max);
-+					if (code <= 0)
-+						break;
-+					code = min(code, (int) max);
-+					buf += code;
-+					max -= code;
-+				} else if (hw_ep->out_qh) {
-+					code = dump_qh(hw_ep->out_qh,
-+							buf, max);
-+					if (code <= 0)
-+						break;
-+					code = min(code, (int) max);
-+					buf += code;
-+					max -= code;
-+				}
-+			}
-+		}
-+		if (is_peripheral_active(musb)) {
-+			code = 0;
-+
-+			if (hw_ep->ep_in.desc || !epnum) {
-+				code = dump_ep(&hw_ep->ep_in, buf, max);
-+				if (code <= 0)
-+					break;
-+				code = min(code, (int) max);
-+				buf += code;
-+				max -= code;
-+			}
-+			if (hw_ep->ep_out.desc) {
-+				code = dump_ep(&hw_ep->ep_out, buf, max);
-+				if (code <= 0)
-+					break;
-+				code = min(code, (int) max);
-+				buf += code;
-+				max -= code;
-+			}
-+		}
-+	} while (0);
-+
-+	return buf - aBuffer;
-+}
-+
-+/* Dump the current status and compile options.
-+ * @param musb the device driver instance
-+ * @param buffer where to dump the status; it must be big enough to hold the
-+ * result otherwise "BAD THINGS HAPPENS(TM)".
-+ */
-+static int dump_header_stats(struct musb *musb, char *buffer)
-+{
-+	int code, count = 0;
-+	const void __iomem *mbase = musb->mregs;
-+
-+	*buffer = 0;
-+	count = sprintf(buffer, "Status: %sHDRC, Mode=%s "
-+				"(Power=%02x, DevCtl=%02x)\n",
-+			(musb->is_multipoint ? "M" : ""), MUSB_MODE(musb),
-+			musb_readb(mbase, MUSB_POWER),
-+			musb_readb(mbase, MUSB_DEVCTL));
-+	if (count <= 0)
-+		return 0;
-+	buffer += count;
-+
-+	code = sprintf(buffer, "OTG state: %s; %sactive\n",
-+			otg_state_string(musb->xceiv->state),
-+			musb->is_active ? "" : "in");
-+	if (code <= 0)
-+		goto done;
-+	buffer += code;
-+	count += code;
-+
-+	code = sprintf(buffer,
-+			"Options: "
-+#ifdef CONFIG_MUSB_PIO_ONLY
-+			"pio"
-+#elif defined(CONFIG_USB_TI_CPPI_DMA)
-+			"cppi-dma"
-+#elif defined(CONFIG_USB_INVENTRA_DMA)
-+			"musb-dma"
-+#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
-+			"tusb-omap-dma"
-+#else
-+			"?dma?"
-+#endif
-+			", "
-+			"otg (peripheral+host)"
-+			", [eps=%d]\n",
-+		musb->nr_endpoints);
-+	if (code <= 0)
-+		goto done;
-+	count += code;
-+	buffer += code;
-+
-+	code = sprintf(buffer, "Peripheral address: %02x\n",
-+			musb_readb(musb->ctrl_base, MUSB_FADDR));
-+	if (code <= 0)
-+		goto done;
-+	buffer += code;
-+	count += code;
-+
-+	code = sprintf(buffer, "Root port status: %08x\n",
-+			musb->port1_status);
-+	if (code <= 0)
-+		goto done;
-+	buffer += code;
-+	count += code;
-+
-+#ifdef	CONFIG_ARCH_DAVINCI
-+	code = sprintf(buffer,
-+			"DaVinci: ctrl=%02x stat=%1x phy=%03x\n"
-+			"\trndis=%05x auto=%04x intsrc=%08x intmsk=%08x"
-+			"\n",
-+			musb_readl(musb->ctrl_base, DAVINCI_USB_CTRL_REG),
-+			musb_readl(musb->ctrl_base, DAVINCI_USB_STAT_REG),
-+			readl((void __force __iomem *)
-+					IO_ADDRESS(USBPHY_CTL_PADDR)),
-+			musb_readl(musb->ctrl_base, DAVINCI_RNDIS_REG),
-+			musb_readl(musb->ctrl_base, DAVINCI_AUTOREQ_REG),
-+			musb_readl(musb->ctrl_base,
-+					DAVINCI_USB_INT_SOURCE_REG),
-+			musb_readl(musb->ctrl_base,
-+					DAVINCI_USB_INT_MASK_REG));
-+	if (code <= 0)
-+		goto done;
-+	count += code;
-+	buffer += code;
-+#endif	/* DAVINCI */
-+
-+#ifdef CONFIG_USB_TUSB6010
-+	code = sprintf(buffer,
-+			"TUSB6010: devconf %08x, phy enable %08x drive %08x"
-+			"\n\totg %03x timer %08x"
-+			"\n\tprcm conf %08x mgmt %08x; int src %08x mask %08x"
-+			"\n",
-+			musb_readl(musb->ctrl_base, TUSB_DEV_CONF),
-+			musb_readl(musb->ctrl_base, TUSB_PHY_OTG_CTRL_ENABLE),
-+			musb_readl(musb->ctrl_base, TUSB_PHY_OTG_CTRL),
-+			musb_readl(musb->ctrl_base, TUSB_DEV_OTG_STAT),
-+			musb_readl(musb->ctrl_base, TUSB_DEV_OTG_TIMER),
-+			musb_readl(musb->ctrl_base, TUSB_PRCM_CONF),
-+			musb_readl(musb->ctrl_base, TUSB_PRCM_MNGMT),
-+			musb_readl(musb->ctrl_base, TUSB_INT_SRC),
-+			musb_readl(musb->ctrl_base, TUSB_INT_MASK));
-+	if (code <= 0)
-+		goto done;
-+	count += code;
-+	buffer += code;
-+#endif	/* DAVINCI */
-+
-+	if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb))
-+		&& musb->dma_controller) {
-+		code = sprintf(buffer,
-+				"CPPI: txcr=%d txsrc=%01x txena=%01x; "
-+				"rxcr=%d rxsrc=%01x rxena=%01x "
-+				"\n",
-+				musb_readl(musb->ctrl_base,
-+						DAVINCI_TXCPPI_CTRL_REG),
-+				musb_readl(musb->ctrl_base,
-+						DAVINCI_TXCPPI_RAW_REG),
-+				musb_readl(musb->ctrl_base,
-+						DAVINCI_TXCPPI_INTENAB_REG),
-+				musb_readl(musb->ctrl_base,
-+						DAVINCI_RXCPPI_CTRL_REG),
-+				musb_readl(musb->ctrl_base,
-+						DAVINCI_RXCPPI_RAW_REG),
-+				musb_readl(musb->ctrl_base,
-+						DAVINCI_RXCPPI_INTENAB_REG));
-+		if (code <= 0)
-+			goto done;
-+		count += code;
-+		buffer += code;
-+	}
-+
-+	if (is_peripheral_enabled(musb)) {
-+		code = sprintf(buffer, "Gadget driver: %s\n",
-+				musb->gadget_driver
-+					? musb->gadget_driver->driver.name
-+					: "(none)");
-+		if (code <= 0)
-+			goto done;
-+		count += code;
-+		buffer += code;
-+	}
-+
-+done:
-+	return count;
-+}
-+
-+/* Write to ProcFS
-+ *
-+ * C soft-connect
-+ * c soft-disconnect
-+ * I enable HS
-+ * i disable HS
-+ * s stop session
-+ * F force session (OTG-unfriendly)
-+ * E rElinquish bus (OTG)
-+ * H request host mode
-+ * h cancel host request
-+ * T start sending TEST_PACKET
-+ * D<num> set/query the debug level
-+ */
-+static int musb_proc_write(struct file *file, const char __user *buffer,
-+			unsigned long count, void *data)
-+{
-+	char cmd;
-+	u8 reg;
-+	struct musb *musb = (struct musb *)data;
-+	void __iomem *mbase = musb->mregs;
-+
-+	/* MOD_INC_USE_COUNT; */
-+
-+	if (unlikely(copy_from_user(&cmd, buffer, 1)))
-+		return -EFAULT;
-+
-+	switch (cmd) {
-+	case 'S':
-+		if (mbase) {
-+			reg = musb_readb(mbase, MUSB_POWER)
-+					| MUSB_POWER_SUSPENDM;
-+			musb_writeb(mbase, MUSB_POWER, reg);
-+		}
-+		break;
-+
-+	case 'C':
-+		if (mbase) {
-+			reg = musb_readb(mbase, MUSB_POWER)
-+					| MUSB_POWER_SOFTCONN;
-+			musb_writeb(mbase, MUSB_POWER, reg);
-+		}
-+		break;
-+
-+	case 'c':
-+		if (mbase) {
-+			reg = musb_readb(mbase, MUSB_POWER)
-+					& ~MUSB_POWER_SOFTCONN;
-+			musb_writeb(mbase, MUSB_POWER, reg);
-+		}
-+		break;
-+
-+	case 'I':
-+		if (mbase) {
-+			reg = musb_readb(mbase, MUSB_POWER)
-+					| MUSB_POWER_HSENAB;
-+			musb_writeb(mbase, MUSB_POWER, reg);
-+		}
-+		break;
-+
-+	case 'i':
-+		if (mbase) {
-+			reg = musb_readb(mbase, MUSB_POWER)
-+					& ~MUSB_POWER_HSENAB;
-+			musb_writeb(mbase, MUSB_POWER, reg);
-+		}
-+		break;
-+
-+	case 'F':
-+		reg = musb_readb(mbase, MUSB_DEVCTL);
-+		reg |= MUSB_DEVCTL_SESSION;
-+		musb_writeb(mbase, MUSB_DEVCTL, reg);
-+		break;
-+
-+	case 'H':
-+		if (mbase) {
-+			reg = musb_readb(mbase, MUSB_DEVCTL);
-+			reg |= MUSB_DEVCTL_HR;
-+			musb_writeb(mbase, MUSB_DEVCTL, reg);
-+			/* MUSB_HST_MODE( ((struct musb*)data) ); */
-+			/* WARNING("Host Mode\n"); */
-+		}
-+		break;
-+
-+	case 'h':
-+		if (mbase) {
-+			reg = musb_readb(mbase, MUSB_DEVCTL);
-+			reg &= ~MUSB_DEVCTL_HR;
-+			musb_writeb(mbase, MUSB_DEVCTL, reg);
-+		}
-+		break;
-+
-+	case 'T':
-+		if (mbase) {
-+			musb_load_testpacket(musb);
-+			musb_writeb(mbase, MUSB_TESTMODE,
-+					MUSB_TEST_PACKET);
-+			musb_writew(musb->endpoints[0].regs,
-+				MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
-+			dev_dbg(musb->controller,
-+				"musb:testmode sending test packet\n");
-+		}
-+		break;
-+
-+	case 'b':
-+		/* generate software babble interrupt */
-+		musb_simulate_babble_intr(musb);
-+		break;
-+
-+	case 'K':
-+		/* enable babble workaround */
-+		musb->enable_babble_work = 1;
-+		INFO("enabled babble workaround\n");
-+		break;
-+
-+	case 'k':
-+		/* disable babble workaround */
-+		musb->enable_babble_work = 0;
-+		INFO("disabled babble workaround\n");
-+		break;
-+
-+	case '?':
-+		INFO("?: you are seeing it\n");
-+		INFO("S: suspend the usb bus\n");
-+		INFO("C/c: soft connect enable/disable\n");
-+		INFO("I/i: hispeed enable/disable\n");
-+		INFO("F: force session start\n");
-+		INFO("H: host mode\n");
-+		INFO("T: start sending TEST_PACKET\n");
-+		INFO("D: set/read dbug level\n");
-+		INFO("K/k: enable/disable babble workaround\n");
-+		break;
-+
-+	default:
-+		ERR("Command %c not implemented\n", cmd);
-+		break;
-+	}
-+
-+	musb_platform_try_idle(musb, 0);
-+
-+	return count;
-+}
-+
-+static int musb_proc_read(char *page, char **start,
-+			off_t off, int count, int *eof, void *data)
-+{
-+	char *buffer = page;
-+	int code = 0;
-+	unsigned long	flags;
-+	struct musb	*musb = data;
-+	unsigned	epnum;
-+
-+	count -= off;
-+	count -= 1;		/* for NUL at end */
-+	if (count <= 0)
-+		return -EINVAL;
-+
-+	spin_lock_irqsave(&musb->lock, flags);
-+
-+	code = dump_header_stats(musb, buffer);
-+	if (code > 0) {
-+		buffer += code;
-+		count -= code;
-+	}
-+
-+	/* generate the report for the end points */
-+	/* REVISIT ... not unless something's connected! */
-+	for (epnum = 0; count >= 0 && epnum < musb->nr_endpoints;
-+			epnum++) {
-+		code = dump_end_info(musb, epnum, buffer, count);
-+		if (code > 0) {
-+			buffer += code;
-+			count -= code;
-+		}
-+	}
-+
-+	musb_platform_try_idle(musb, 0);
-+
-+	spin_unlock_irqrestore(&musb->lock, flags);
-+	*eof = 1;
-+
-+	return buffer - page;
-+}
-+
-+void musb_debug_delete(char *name, struct musb *musb)
-+{
-+	if (musb->proc_entry)
-+		remove_proc_entry(name, NULL);
-+}
-+
-+struct proc_dir_entry *__devinit
-+musb_debug_create(char *name, struct musb *data)
-+{
-+	struct proc_dir_entry	*pde;
-+
-+	/* FIXME convert everything to seq_file; then later, debugfs */
-+
-+	if (!name)
-+		return NULL;
-+
-+	pde = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUSR, NULL);
-+	data->proc_entry = pde;
-+	if (pde) {
-+		pde->data = data;
-+		/* pde->owner = THIS_MODULE; */
-+
-+		pde->read_proc = musb_proc_read;
-+		pde->write_proc = musb_proc_write;
-+
-+		pde->size = 0;
-+
-+		pr_debug("Registered /proc/%s\n", name);
-+	} else {
-+		pr_debug("Cannot create a valid proc file entry");
-+	}
-+
-+	return pde;
-+}
-diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h
-index 03f2655..b222c08 100644
---- a/drivers/usb/musb/musb_regs.h
-+++ b/drivers/usb/musb/musb_regs.h
-@@ -234,12 +234,8 @@
- #define MUSB_TESTMODE		0x0F	/* 8 bit */
- 
- /* Get offset for a given FIFO from musb->mregs */
--#if defined(CONFIG_USB_MUSB_TUSB6010) ||	\
--	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
--#define MUSB_FIFO_OFFSET(epnum)	(0x200 + ((epnum) * 0x20))
--#else
-+#define MUSB_TUSB_FIFO_OFFSET(epnum)	(0x200 + ((epnum) * 0x20))
- #define MUSB_FIFO_OFFSET(epnum)	(0x20 + ((epnum) * 4))
--#endif
- 
- /*
-  * Additional Control Registers
-@@ -288,21 +284,22 @@
- #define MUSB_FIFOSIZE		0x0F
- #define MUSB_CONFIGDATA		MUSB_FIFOSIZE	/* Re-used for EP0 */
- 
-+#if 0
- /* Offsets to endpoint registers in indexed model (using INDEX register) */
--#define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
-+#define MUSB_INDEXED_OFFSET(_musb, _epnum, _offset)	\
- 	(0x10 + (_offset))
- 
- /* Offsets to endpoint registers in flat models */
--#define MUSB_FLAT_OFFSET(_epnum, _offset)	\
-+#define MUSB_FLAT_OFFSET(_musb, _epnum, _offset)	\
- 	(0x100 + (0x10*(_epnum)) + (_offset))
-+#endif
-+
-+#define MUSB_OFFSET(_musb, _epnum, _offset)	\
-+	((_musb)->ops->flags & MUSB_GLUE_EP_ADDR_INDEXED_MAPPING ? \
-+		(0x10 + (_offset)) : (0x100 + (0x10*(_epnum)) + (_offset)))
-+
- 
--#if defined(CONFIG_USB_MUSB_TUSB6010) ||	\
--	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
--/* TUSB6010 EP0 configuration register is special */
--#define MUSB_TUSB_OFFSET(_epnum, _offset)	\
--	(0x10 + _offset)
- #include "tusb6010.h"		/* Needed "only" for TUSB_EP0_CONF */
--#endif
- 
- #define MUSB_TXCSR_MODE			0x2000
- 
-@@ -506,11 +503,11 @@ static inline u8  musb_read_txhubport(void __iomem *mbase, u8 epnum)
- #define MUSB_TXCOUNT		0x28
- 
- /* Offsets to endpoint registers in indexed model (using INDEX register) */
--#define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
-+#define MUSB_INDEXED_OFFSET(_musb, _epnum, _offset)	\
- 	(0x40 + (_offset))
- 
- /* Offsets to endpoint registers in flat models */
--#define MUSB_FLAT_OFFSET(_epnum, _offset)	\
-+#define MUSB_FLAT_OFFSET(_musb, _epnum, _offset)	\
- 	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
- 
- /* Not implemented - HW has separate Tx/Rx FIFO */
-diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
-index e9f80ad..211c24a 100644
---- a/drivers/usb/musb/musb_virthub.c
-+++ b/drivers/usb/musb/musb_virthub.c
-@@ -82,17 +82,15 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
- 			musb->xceiv->state = OTG_STATE_A_SUSPEND;
- 			musb->is_active = is_otg_enabled(musb)
- 					&& musb->xceiv->host->b_hnp_enable;
--			if (musb->is_active)
--				mod_timer(&musb->otg_timer, jiffies
--					+ msecs_to_jiffies(
--						OTG_TIME_A_AIDL_BDIS));
- 			musb_platform_try_idle(musb, 0);
- 			break;
- 		case OTG_STATE_B_HOST:
--			musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
--			musb->is_active = is_otg_enabled(musb)
-+			if (is_otg_enabled(musb)) {
-+				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
-+				musb->is_active = is_otg_enabled(musb)
- 					&& musb->xceiv->host->b_hnp_enable;
--			musb_platform_try_idle(musb, 0);
-+				musb_platform_try_idle(musb, 0);
-+			}
- 			break;
- 		default:
- 			dev_dbg(musb->controller, "bogus rh suspend? %s\n",
-@@ -116,7 +114,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
- 	u8		power;
- 	void __iomem	*mbase = musb->mregs;
- 
--	if (musb->xceiv->state == OTG_STATE_B_IDLE) {
-+	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE) {
- 		dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
- 		musb->port1_status &= ~USB_PORT_STAT_RESET;
- 		return;
-@@ -186,15 +184,8 @@ void musb_root_disconnect(struct musb *musb)
- 	musb->is_active = 0;
- 
- 	switch (musb->xceiv->state) {
--	case OTG_STATE_A_SUSPEND:
--		if (is_otg_enabled(musb)
--				&& musb->xceiv->host->b_hnp_enable) {
--			musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
--			musb->g.is_a_peripheral = 1;
--			break;
--		}
--		/* FALLTHROUGH */
- 	case OTG_STATE_A_HOST:
-+	case OTG_STATE_A_SUSPEND:
- 		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
- 		musb->is_active = 0;
- 		break;
-@@ -414,6 +405,10 @@ int musb_hub_control(
- 				goto error;
- 			}
- 			musb_writeb(musb->mregs, MUSB_TESTMODE, temp);
-+			if (wIndex == 4) {
-+				musb_writew(musb->endpoints[0].regs,
-+					MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
-+			}
- 			break;
- 		default:
- 			goto error;
-diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
-index 57a6085..9ba7a30 100644
---- a/drivers/usb/musb/musbhsdma.c
-+++ b/drivers/usb/musb/musbhsdma.c
-@@ -30,6 +30,7 @@
-  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  */
-+#include <linux/module.h>
- #include <linux/device.h>
- #include <linux/interrupt.h>
- #include <linux/platform_device.h>
-@@ -205,14 +206,14 @@ static int dma_channel_abort(struct dma_channel *channel)
- {
- 	struct musb_dma_channel *musb_channel = channel->private_data;
- 	void __iomem *mbase = musb_channel->controller->base;
--
-+	struct musb *musb = musb_channel->controller->private_data;
- 	u8 bchannel = musb_channel->idx;
- 	int offset;
- 	u16 csr;
- 
- 	if (channel->status == MUSB_DMA_STATUS_BUSY) {
- 		if (musb_channel->transmit) {
--			offset = MUSB_EP_OFFSET(musb_channel->epnum,
-+			offset = MUSB_EP_OFFSET(musb, musb_channel->epnum,
- 						MUSB_TXCSR);
- 
- 			/*
-@@ -225,7 +226,7 @@ static int dma_channel_abort(struct dma_channel *channel)
- 			csr &= ~MUSB_TXCSR_DMAMODE;
- 			musb_writew(mbase, offset, csr);
- 		} else {
--			offset = MUSB_EP_OFFSET(musb_channel->epnum,
-+			offset = MUSB_EP_OFFSET(musb, musb_channel->epnum,
- 						MUSB_RXCSR);
- 
- 			csr = musb_readw(mbase, offset);
-@@ -336,7 +337,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
- 					    (musb_channel->max_packet_sz - 1)))
- 				    ) {
- 					u8  epnum  = musb_channel->epnum;
--					int offset = MUSB_EP_OFFSET(epnum,
-+					int offset = MUSB_EP_OFFSET(musb, epnum,
- 								    MUSB_TXCSR);
- 					u16 txcsr;
- 
-@@ -344,7 +345,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
- 					 * The programming guide says that we
- 					 * must clear DMAENAB before DMAMODE.
- 					 */
--					musb_ep_select(mbase, epnum);
-+					musb_ep_select(musb, mbase, epnum);
- 					txcsr = musb_readw(mbase, offset);
- 					txcsr &= ~(MUSB_TXCSR_DMAENAB
- 							| MUSB_TXCSR_AUTOSET);
-@@ -366,7 +367,7 @@ done:
- 	return retval;
- }
- 
--void dma_controller_destroy(struct dma_controller *c)
-+void inventra_dma_controller_destroy(struct dma_controller *c)
- {
- 	struct musb_dma_controller *controller = container_of(c,
- 			struct musb_dma_controller, controller);
-@@ -379,9 +380,10 @@ void dma_controller_destroy(struct dma_controller *c)
- 
- 	kfree(controller);
- }
-+EXPORT_SYMBOL(inventra_dma_controller_destroy);
- 
--struct dma_controller *__init
--dma_controller_create(struct musb *musb, void __iomem *base)
-+struct dma_controller *__devinit
-+inventra_dma_controller_create(struct musb *musb, void __iomem *base)
- {
- 	struct musb_dma_controller *controller;
- 	struct device *dev = musb->controller;
-@@ -411,7 +413,7 @@ dma_controller_create(struct musb *musb, void __iomem *base)
- 	if (request_irq(irq, dma_controller_irq, 0,
- 			dev_name(musb->controller), &controller->controller)) {
- 		dev_err(dev, "request_irq %d failed!\n", irq);
--		dma_controller_destroy(&controller->controller);
-+		inventra_dma_controller_destroy(&controller->controller);
- 
- 		return NULL;
- 	}
-@@ -420,3 +422,18 @@ dma_controller_create(struct musb *musb, void __iomem *base)
- 
- 	return &controller->controller;
- }
-+EXPORT_SYMBOL(inventra_dma_controller_create);
-+
-+MODULE_DESCRIPTION("MUSB Inventra dma controller driver");
-+MODULE_LICENSE("GPL v2");
-+
-+static int __init inventra_dma_init(void)
-+{
-+	return 0;
-+}
-+module_init(inventra_dma_init);
-+
-+static void __exit inventra_dma__exit(void)
-+{
-+}
-+module_exit(inventra_dma__exit);
-diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
-index ba85f27..dd907d5 100644
---- a/drivers/usb/musb/omap2430.c
-+++ b/drivers/usb/musb/omap2430.c
-@@ -29,7 +29,6 @@
- #include <linux/sched.h>
- #include <linux/init.h>
- #include <linux/list.h>
--#include <linux/clk.h>
- #include <linux/io.h>
- #include <linux/platform_device.h>
- #include <linux/dma-mapping.h>
-@@ -96,6 +95,7 @@ static void musb_do_idle(unsigned long _musb)
- 	spin_unlock_irqrestore(&musb->lock, flags);
- }
- 
-+#define MUSB_TIMEOUT_A_WAIT_BCON	1100
- 
- static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
- {
-@@ -228,21 +228,25 @@ static int musb_otg_notifications(struct notifier_block *nb,
- 		unsigned long event, void *unused)
- {
- 	struct musb	*musb = container_of(nb, struct musb, nb);
-+
-+	musb->xceiv_event = event;
-+	schedule_work(&musb->otg_notifier_work);
-+
-+	return 0;
-+}
-+
-+static void musb_otg_notifier_work(struct work_struct *data_notifier_work)
-+{
-+	struct musb *musb = container_of(data_notifier_work, struct musb, otg_notifier_work);
- 	struct device *dev = musb->controller;
- 	struct musb_hdrc_platform_data *pdata = dev->platform_data;
- 	struct omap_musb_board_data *data = pdata->board_data;
- 
--	switch (event) {
-+	switch (musb->xceiv_event) {
- 	case USB_EVENT_ID:
- 		dev_dbg(musb->controller, "ID GND\n");
- 
--		if (is_otg_enabled(musb)) {
--			if (musb->gadget_driver) {
--				pm_runtime_get_sync(musb->controller);
--				otg_init(musb->xceiv);
--				omap2430_musb_set_vbus(musb, 1);
--			}
--		} else {
-+		if (!is_otg_enabled(musb) || musb->gadget_driver) {
- 			pm_runtime_get_sync(musb->controller);
- 			otg_init(musb->xceiv);
- 			omap2430_musb_set_vbus(musb, 1);
-@@ -274,10 +278,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
- 		break;
- 	default:
- 		dev_dbg(musb->controller, "ID float\n");
--		return NOTIFY_DONE;
- 	}
--
--	return NOTIFY_OK;
- }
- 
- static int omap2430_musb_init(struct musb *musb)
-@@ -291,12 +292,14 @@ static int omap2430_musb_init(struct musb *musb)
- 	 * up through ULPI.  TWL4030-family PMICs include one,
- 	 * which needs a driver, drivers aren't always needed.
- 	 */
--	musb->xceiv = otg_get_transceiver();
-+	musb->xceiv = otg_get_transceiver(musb->id);
- 	if (!musb->xceiv) {
- 		pr_err("HS USB OTG: no transceiver configured\n");
- 		return -ENODEV;
- 	}
- 
-+	INIT_WORK(&musb->otg_notifier_work, musb_otg_notifier_work);
-+
- 	status = pm_runtime_get_sync(dev);
- 	if (status < 0) {
- 		dev_err(dev, "pm_runtime_get_sync FAILED");
-@@ -329,12 +332,12 @@ static int omap2430_musb_init(struct musb *musb)
- 	if (status)
- 		dev_dbg(musb->controller, "notification register failed\n");
- 
-+	musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
- 	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
- 
- 	return 0;
- 
- err1:
--	pm_runtime_disable(dev);
- 	return status;
- }
- 
-@@ -350,20 +353,19 @@ static void omap2430_musb_enable(struct musb *musb)
- 
- 	case USB_EVENT_ID:
- 		otg_init(musb->xceiv);
--		if (data->interface_type == MUSB_INTERFACE_UTMI) {
--			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
--			/* start the session */
--			devctl |= MUSB_DEVCTL_SESSION;
--			musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
--			while (musb_readb(musb->mregs, MUSB_DEVCTL) &
--						MUSB_DEVCTL_BDEVICE) {
--				cpu_relax();
--
--				if (time_after(jiffies, timeout)) {
--					dev_err(musb->controller,
--					"configured as A device timeout");
--					break;
--				}
-+		if (data->interface_type != MUSB_INTERFACE_UTMI)
-+			break;
-+		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
-+		/* start the session */
-+		devctl |= MUSB_DEVCTL_SESSION;
-+		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
-+		while (musb_readb(musb->mregs, MUSB_DEVCTL) &
-+				MUSB_DEVCTL_BDEVICE) {
-+			cpu_relax();
-+
-+			if (time_after(jiffies, timeout)) {
-+				dev_err(dev, "configured as A device timeout");
-+				break;
- 			}
- 		}
- 		break;
-@@ -394,9 +396,15 @@ static int omap2430_musb_exit(struct musb *musb)
- }
- 
- static const struct musb_platform_ops omap2430_ops = {
-+	.fifo_mode	= 4,
-+	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING |
-+				MUSB_GLUE_DMA_INVENTRA,
- 	.init		= omap2430_musb_init,
- 	.exit		= omap2430_musb_exit,
- 
-+	.read_fifo      = musb_read_fifo,
-+	.write_fifo     = musb_write_fifo,
-+
- 	.set_mode	= omap2430_musb_set_mode,
- 	.try_idle	= omap2430_musb_try_idle,
- 
-@@ -404,6 +412,9 @@ static const struct musb_platform_ops omap2430_ops = {
- 
- 	.enable		= omap2430_musb_enable,
- 	.disable	= omap2430_musb_disable,
-+
-+	.dma_controller_create = inventra_dma_controller_create,
-+	.dma_controller_destroy = inventra_dma_controller_destroy,
- };
- 
- static u64 omap2430_dmamask = DMA_BIT_MASK(32);
-@@ -421,12 +432,13 @@ static int __init omap2430_probe(struct platform_device *pdev)
- 		goto err0;
- 	}
- 
--	musb = platform_device_alloc("musb-hdrc", -1);
-+	musb = platform_device_alloc("musb-hdrc", pdev->id);
- 	if (!musb) {
- 		dev_err(&pdev->dev, "failed to allocate musb device\n");
- 		goto err1;
- 	}
- 
-+	ev_set_name(&pdev->dev, "musb-omap2430");
- 	musb->dev.parent		= &pdev->dev;
- 	musb->dev.dma_mask		= &omap2430_dmamask;
- 	musb->dev.coherent_dma_mask	= omap2430_dmamask;
-@@ -478,7 +490,6 @@ static int __exit omap2430_remove(struct platform_device *pdev)
- 	platform_device_del(glue->musb);
- 	platform_device_put(glue->musb);
- 	pm_runtime_put(&pdev->dev);
--	pm_runtime_disable(&pdev->dev);
- 	kfree(glue);
- 
- 	return 0;
-@@ -491,6 +502,9 @@ static int omap2430_runtime_suspend(struct device *dev)
- 	struct omap2430_glue		*glue = dev_get_drvdata(dev);
- 	struct musb			*musb = glue_to_musb(glue);
- 
-+	musb->context.otg_interfsel = musb_readl(musb->mregs,
-+						OTG_INTERFSEL);
-+
- 	omap2430_low_level_exit(musb);
- 	otg_set_suspend(musb->xceiv, 1);
- 
-@@ -503,6 +517,9 @@ static int omap2430_runtime_resume(struct device *dev)
- 	struct musb			*musb = glue_to_musb(glue);
- 
- 	omap2430_low_level_init(musb);
-+	musb_writel(musb->mregs, OTG_INTERFSEL,
-+					musb->context.otg_interfsel);
-+
- 	otg_set_suspend(musb->xceiv, 0);
- 
- 	return 0;
-diff --git a/drivers/usb/musb/ti81xx.c b/drivers/usb/musb/ti81xx.c
-new file mode 100644
-index 0000000..662aceb
---- /dev/null
-+++ b/drivers/usb/musb/ti81xx.c
-@@ -0,0 +1,1649 @@
-+/*
-+ * Texas Instruments TI81XX "usb platform glue layer"
-+ *
-+ * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
-+ *
-+ * Based on the DaVinci "glue layer" code.
-+ * Copyright (C) 2005-2006 by Texas Instruments
-+ *
-+ * This file is part of the Inventra Controller Driver for Linux.
-+ *
-+ * The Inventra Controller Driver for Linux is free software; you
-+ * can redistribute it and/or modify it under the terms of the GNU
-+ * General Public License version 2 as published by the Free Software
-+ * Foundation.
-+ *
-+ * The Inventra Controller Driver for Linux is distributed in
-+ * the hope that it will be useful, but WITHOUT ANY WARRANTY;
-+ * without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+ * License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with The Inventra Controller Driver for Linux ; if not,
-+ * write to the Free Software Foundation, Inc., 59 Temple Place,
-+ * Suite 330, Boston, MA  02111-1307  USA
-+ *
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/usb/otg.h>
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/module.h>
-+
-+#include "cppi41.h"
-+#include "ti81xx.h"
-+
-+#include "musb_core.h"
-+#include "cppi41_dma.h"
-+
-+#ifdef CONFIG_PM
-+struct ti81xx_usbss_regs {
-+	u32	sysconfig;
-+
-+	u32	irq_en_set;
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	u32	irq_dma_th_tx0[4];
-+	u32	irq_dma_th_rx0[4];
-+	u32	irq_dma_th_tx1[4];
-+	u32	irq_dma_th_rx1[4];
-+	u32	irq_dma_en[2];
-+
-+	u32	irq_frame_th_tx0[4];
-+	u32	irq_frame_th_rx0[4];
-+	u32	irq_frame_th_tx1[4];
-+	u32	irq_frame_th_rx1[4];
-+	u32	irq_frame_en[2];
-+#endif
-+};
-+
-+struct ti81xx_usb_regs {
-+	u32	control;
-+
-+	u32	irq_en_set[2];
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	u32	tx_mode;
-+	u32	rx_mode;
-+	u32	grndis_size[15];
-+	u32	auto_req;
-+	u32	teardn;
-+	u32	th_xdma_idle;
-+#endif
-+	u32	srp_fix;
-+	u32	phy_utmi;
-+	u32	mgc_utmi_loopback;
-+	u32	mode;
-+};
-+#endif
-+
-+struct ti81xx_glue {
-+	struct device *dev;
-+	struct resource *mem_pa;	/* usbss memory resource */
-+	void *mem_va;			/* ioremapped virtual address */
-+	struct platform_device *musb[2];/* child musb pdevs */
-+	u8	irq;			/* usbss irq */
-+	u8	first;			/* ignore first call of resume */
-+
-+#ifdef CONFIG_PM
-+	struct ti81xx_usbss_regs usbss_regs;
-+	struct ti81xx_usb_regs usb_regs[2];
-+#endif
-+};
-+
-+static u64 musb_dmamask = DMA_BIT_MASK(32);
-+static void *usbss_virt_base;
-+static u8 usbss_init_done;
-+struct musb *gmusb[2];
-+
-+u8 usbid_sw_ctrl;
-+#undef USB_TI81XX_DEBUG
-+
-+#ifdef USB_TI81XX_DEBUG
-+#define	dprintk(x, ...) printk(x, ## __VA_ARGS__)
-+#else
-+#define dprintk(x, ...)
-+#endif
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+static irqreturn_t cppi41dma_Interrupt(int irq, void *hci);
-+static u8 cppi41_init_done;
-+static void *cppi41_dma_base;
-+#define CPPI41_ADDR(offs) ((void *)((u32)cppi41_dma_base + (offs - 0x2000)))
-+#endif
-+
-+extern void omap_ctrl_writel(u32 val, u16 offset);
-+extern u32 omap_ctrl_readl(u16 offset);
-+
-+static inline u32 usbss_read(u32 offset)
-+{
-+	if (!usbss_init_done)
-+		return 0;
-+	return readl(usbss_virt_base + offset);
-+}
-+
-+static inline void usbss_write(u32 offset, u32 data)
-+{
-+	if (!usbss_init_done)
-+		return ;
-+	writel(data, usbss_virt_base + offset);
-+}
-+
-+static void usbotg_ss_init(void)
-+{
-+	if (!usbss_init_done) {
-+		usbss_init_done = 1;
-+
-+		/* clear any USBSS interrupts */
-+		usbss_write(USBSS_IRQ_EOI, 0);
-+		usbss_write(USBSS_IRQ_STATUS, usbss_read(USBSS_IRQ_STATUS));
-+	}
-+}
-+static void usbotg_ss_uninit(void)
-+{
-+	if (usbss_init_done) {
-+		usbss_init_done = 0;
-+		usbss_virt_base = 0;
-+	}
-+}
-+void set_frame_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value, u8 en_intr)
-+{
-+	u32     base, reg_val, frame_intr = 0, frame_base = 0;
-+	u32     offs = epnum/4*4;
-+	u8      indx = (epnum % 4) * 8;
-+
-+	if (is_tx)
-+		base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_TX1 :
-+				USBSS_IRQ_FRAME_THRESHOLD_TX0;
-+	else
-+		base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_RX1 :
-+				USBSS_IRQ_FRAME_THRESHOLD_RX0;
-+
-+	reg_val = usbss_read(base + offs);
-+	reg_val &= ~(0xFF << indx);
-+	reg_val |= (value << indx);
-+	usbss_write(base + offs, reg_val);
-+
-+	if (en_intr) {
-+		frame_base = musb->id ? USBSS_IRQ_FRAME_ENABLE_1 :
-+			USBSS_IRQ_FRAME_ENABLE_0;
-+		frame_intr = musb->id ? usbss_read(USBSS_IRQ_FRAME_ENABLE_0) :
-+			usbss_read(USBSS_IRQ_FRAME_ENABLE_1);
-+		frame_intr |= is_tx ? (1 << epnum) : (1 << (16 + epnum));
-+		usbss_write(frame_base, frame_intr);
-+		dev_dbg(musb->controller, "%s: framebase=%x, frame_intr=%x\n",
-+			is_tx ? "tx" : "rx", frame_base, frame_intr);
-+	}
-+}
-+
-+void set_dma_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value)
-+{
-+	u32     base, reg_val;
-+	u32     offs = epnum/4*4;
-+	u8      indx = (epnum % 4) * 8;
-+
-+	if (musb->id == 0)
-+		base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX0 :
-+				USBSS_IRQ_DMA_THRESHOLD_RX0;
-+	else
-+		base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX1 :
-+				USBSS_IRQ_DMA_THRESHOLD_RX1;
-+
-+	reg_val = usbss_read(base + offs);
-+	reg_val &= ~(0xFF << indx);
-+	reg_val |= (value << indx);
-+	dev_dbg(musb->controller, "base=%x, offs=%x, indx=%d, reg_val = (%x)%x\n",
-+		base, offs, indx, reg_val, usbss_read(base + offs));
-+	usbss_write(base + offs, reg_val);
-+}
-+
-+/* ti81xx specific read/write functions */
-+u16 ti81xx_musb_readw(const void __iomem *addr, unsigned offset)
-+{
-+	u32 tmp;
-+	u16 val;
-+
-+	tmp = readl(addr + (offset & ~3));
-+
-+	switch (offset & 0x3) {
-+	case 0:
-+		val = (tmp & 0xffff);
-+		break;
-+	case 1:
-+		val = (tmp >> 8) & 0xffff;
-+		break;
-+	case 2:
-+	case 3:
-+	default:
-+		val = (tmp >> 16) & 0xffff;
-+		break;
-+	}
-+	return val;
-+}
-+
-+void ti81xx_musb_writew(void __iomem *addr, unsigned offset, u16 data)
-+{
-+	__raw_writew(data, addr + offset);
-+}
-+
-+u8 ti81xx_musb_readb(const void __iomem *addr, unsigned offset)
-+{
-+	u32 tmp;
-+	u8 val;
-+
-+	tmp = readl(addr + (offset & ~3));
-+
-+	switch (offset & 0x3) {
-+	case 0:
-+		val = tmp & 0xff;
-+		break;
-+	case 1:
-+		val = (tmp >> 8);
-+		break;
-+	case 2:
-+		val = (tmp >> 16);
-+		break;
-+	case 3:
-+	default:
-+		val = (tmp >> 24);
-+		break;
-+	}
-+	return val;
-+}
-+void ti81xx_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
-+{
-+	__raw_writeb(data, addr + offset);
-+}
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+/*
-+ * CPPI 4.1 resources used for USB OTG controller module:
-+ *
-+ tx/rx completion queues for usb0 */
-+static u16 tx_comp_q[] = {93, 94, 95, 96, 97,
-+				98, 99, 100, 101, 102,
-+				103, 104, 105, 106, 107 };
-+
-+static u16 rx_comp_q[] = {109, 110, 111, 112, 113,
-+				114, 115, 116, 117, 118,
-+				119, 120, 121, 122, 123 };
-+
-+/* tx/rx completion queues for usb1 */
-+static u16 tx_comp_q1[] = {125, 126, 127, 128, 129,
-+				 130, 131, 132, 133, 134,
-+				 135, 136, 137, 138, 139 };
-+
-+static u16 rx_comp_q1[] = {141, 142, 143, 144, 145,
-+				 146, 147, 148, 149, 150,
-+				 151, 152, 153, 154, 155 };
-+
-+/* Fair scheduling */
-+u32 dma_sched_table[] = {
-+	0x81018000, 0x83038202, 0x85058404, 0x87078606,
-+	0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x8f0f8e0e,
-+	0x91119010, 0x93139212, 0x95159414, 0x97179616,
-+	0x99199818, 0x9b1b9a1a, 0x9d1d9c1c, 0x00009e1e,
-+};
-+
-+/* cppi41 dma tx channel info */
-+static const struct cppi41_tx_ch tx_ch_info[] = {
-+	[0] = {
-+		.port_num	= 1,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 32} , {0, 33} }
-+	},
-+	[1] = {
-+		.port_num	= 2,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 34} , {0, 35} }
-+	},
-+	[2] = {
-+		.port_num	= 3,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 36} , {0, 37} }
-+	},
-+	[3] = {
-+		.port_num	= 4,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 38} , {0, 39} }
-+	},
-+	[4] = {
-+		.port_num	= 5,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 40} , {0, 41} }
-+	},
-+	[5] = {
-+		.port_num	= 6,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 42} , {0, 43} }
-+	},
-+	[6] = {
-+		.port_num	= 7,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 44} , {0, 45} }
-+	},
-+	[7] = {
-+		.port_num	= 8,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 46} , {0, 47} }
-+	},
-+	[8] = {
-+		.port_num	= 9,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 48} , {0, 49} }
-+	},
-+	[9] = {
-+		.port_num	= 10,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 50} , {0, 51} }
-+	},
-+	[10] = {
-+		.port_num	= 11,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 52} , {0, 53} }
-+	},
-+	[11] = {
-+		.port_num	= 12,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 54} , {0, 55} }
-+	},
-+	[12] = {
-+		.port_num	= 13,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 56} , {0, 57} }
-+	},
-+	[13] = {
-+		.port_num	= 14,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 58} , {0, 59} }
-+	},
-+	[14] = {
-+		.port_num	= 15,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 60} , {0, 61} }
-+	},
-+	[15] = {
-+		.port_num	= 1,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 62} , {0, 63} }
-+	},
-+	[16] = {
-+		.port_num	= 2,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 64} , {0, 65} }
-+	},
-+	[17] = {
-+		.port_num	= 3,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 66} , {0, 67} }
-+	},
-+	[18] = {
-+		.port_num	= 4,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 68} , {0, 69} }
-+	},
-+	[19] = {
-+		.port_num	= 5,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 70} , {0, 71} }
-+	},
-+	[20] = {
-+		.port_num	= 6,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 72} , {0, 73} }
-+	},
-+	[21] = {
-+		.port_num	= 7,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 74} , {0, 75} }
-+	},
-+	[22] = {
-+		.port_num	= 8,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 76} , {0, 77} }
-+	},
-+	[23] = {
-+		.port_num	= 9,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 78} , {0, 79} }
-+	},
-+	[24] = {
-+		.port_num	= 10,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 80} , {0, 81} }
-+	},
-+	[25] = {
-+		.port_num	= 11,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 82} , {0, 83} }
-+	},
-+	[26] = {
-+		.port_num	= 12,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 84} , {0, 85} }
-+	},
-+	[27] = {
-+		.port_num	= 13,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 86} , {0, 87} }
-+	},
-+	[28] = {
-+		.port_num	= 14,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 88} , {0, 89} }
-+	},
-+	[29] = {
-+		.port_num	= 15,
-+		.num_tx_queue	= 2,
-+		.tx_queue	= { {0, 90} , {0, 91} }
-+	}
-+};
-+
-+/* Queues 0 to 66 are pre-assigned, others are spare */
-+static const u32 assigned_queues[] = {	0xffffffff, /* queue 0..31 */
-+					0xffffffff, /* queue 32..63 */
-+					0xffffffff, /* queue 64..95 */
-+					0xffffffff, /* queue 96..127 */
-+					0x0fffffff  /* queue 128..155 */
-+					};
-+
-+int __devinit cppi41_init(u8 id, u8 irq, int num_instances)
-+{
-+	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[id];
-+	u16 numch, blknum, order;
-+	u32 i;
-+
-+	/* init cppi info structure  */
-+	cppi_info->dma_block = 0;
-+	for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
-+		cppi_info->ep_dma_ch[i] = i + (15 * id);
-+
-+	cppi_info->q_mgr = 0;
-+	cppi_info->num_tx_comp_q = 15;
-+	cppi_info->num_rx_comp_q = 15;
-+	cppi_info->tx_comp_q = id ? tx_comp_q1 : tx_comp_q;
-+	cppi_info->rx_comp_q = id ? rx_comp_q1 : rx_comp_q;
-+	cppi_info->bd_intr_ctrl = 1;
-+
-+	if (cppi41_init_done)
-+		return 0;
-+
-+	blknum = cppi_info->dma_block;
-+
-+	/* Queue manager information */
-+	cppi41_queue_mgr[0].num_queue = 159;
-+	cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
-+						CPPI41_UNASSIGNED_QUEUE;
-+	cppi41_queue_mgr[0].base_fdbq_num = 0;
-+	cppi41_queue_mgr[0].assigned = assigned_queues;
-+
-+	/* init DMA block */
-+	cppi41_dma_block[0].num_tx_ch = 30;
-+	cppi41_dma_block[0].num_rx_ch = 30;
-+	cppi41_dma_block[0].tx_ch_info = tx_ch_info;
-+
-+	/* initilize cppi41 dma & Qmgr address */
-+	cppi41_dma_base = ioremap(TI81XX_USB_CPPIDMA_BASE,
-+					TI81XX_USB_CPPIDMA_LEN);
-+
-+	cppi41_queue_mgr[0].q_mgr_rgn_base = CPPI41_ADDR(QMGR_RGN_OFFS);
-+	cppi41_queue_mgr[0].desc_mem_rgn_base = CPPI41_ADDR(QMRG_DESCRGN_OFFS);
-+	cppi41_queue_mgr[0].q_mgmt_rgn_base = CPPI41_ADDR(QMGR_REG_OFFS);
-+	cppi41_queue_mgr[0].q_stat_rgn_base = CPPI41_ADDR(QMGR_STAT_OFFS);
-+	cppi41_dma_block[0].global_ctrl_base = CPPI41_ADDR(DMA_GLBCTRL_OFFS);
-+	cppi41_dma_block[0].ch_ctrl_stat_base = CPPI41_ADDR(DMA_CHCTRL_OFFS);
-+	cppi41_dma_block[0].sched_ctrl_base = CPPI41_ADDR(DMA_SCHED_OFFS);
-+	cppi41_dma_block[0].sched_table_base = CPPI41_ADDR(DMA_SCHEDTBL_OFFS);
-+
-+	/* Initialize for Linking RAM region 0 alone */
-+	cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);
-+
-+	numch =  USB_CPPI41_NUM_CH * 2 * num_instances;
-+	cppi41_dma_block[0].num_max_ch = numch;
-+
-+	order = get_count_order(numch);
-+
-+	/* TODO: check two teardown desc per channel (5 or 7 ?)*/
-+	if (order < 5)
-+		order = 5;
-+
-+	cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
-+			dma_sched_table, numch);
-+
-+	/* attach to the IRQ */
-+	if (request_irq(irq, cppi41dma_Interrupt, 0, "cppi41_dma", 0))
-+		printk(KERN_INFO "request_irq %d failed!\n", irq);
-+	else
-+		printk(KERN_INFO "registerd cppi-dma Intr @ IRQ %d\n", irq);
-+
-+	cppi41_init_done = 1;
-+
-+	printk(KERN_INFO "Cppi41 Init Done Qmgr-base(%p) dma-base(%p)\n",
-+		cppi41_queue_mgr[0].q_mgr_rgn_base,
-+		cppi41_dma_block[0].global_ctrl_base);
-+
-+	/* enable all usbss the interrupts */
-+	usbss_write(USBSS_IRQ_EOI, 0);
-+	usbss_write(USBSS_IRQ_ENABLE_SET, USBSS_INTR_FLAGS);
-+	usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0xFFFeFFFe);
-+
-+	printk(KERN_INFO "Cppi41 Init Done\n");
-+
-+	return 0;
-+}
-+
-+void cppi41_free(void)
-+{
-+	u32 numch, blknum, order;
-+	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
-+
-+	if (!cppi41_init_done)
-+		return ;
-+
-+	numch = cppi41_dma_block[0].num_max_ch;
-+	order = get_count_order(numch);
-+	blknum = cppi_info->dma_block;
-+
-+	cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
-+			dma_sched_table, numch);
-+	cppi41_queue_mgr_uninit(cppi_info->q_mgr);
-+
-+	iounmap(cppi41_dma_base);
-+	cppi41_dma_base = 0;
-+	cppi41_init_done = 0;
-+}
-+
-+int cppi41_disable_sched_rx(void)
-+{
-+	cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
-+	return 0;
-+}
-+
-+int cppi41_enable_sched_rx(void)
-+{
-+	cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
-+	return 0;
-+}
-+#endif /* CONFIG_USB_TI_CPPI41_DMA */
-+
-+/*
-+ * Because we don't set CTRL.UINT, it's "important" to:
-+ *	- not read/write INTRUSB/INTRUSBE (except during
-+ *	  initial setup, as a workaround);
-+ *	- use INTSET/INTCLR instead.
-+ */
-+
-+/**
-+ * ti81xx_musb_enable - enable interrupts
-+ */
-+void ti81xx_musb_enable(struct musb *musb)
-+{
-+	void __iomem *reg_base = musb->ctrl_base;
-+	u32 epmask, coremask;
-+
-+	/* Workaround: setup IRQs through both register sets. */
-+	epmask = ((musb->epmask & USB_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
-+	       ((musb->epmask & USB_RX_EP_MASK) << USB_INTR_RX_SHIFT);
-+	coremask = (0x01ff << USB_INTR_USB_SHIFT);
-+
-+	coremask &= ~MUSB_INTR_SOF;
-+
-+	musb_writel(reg_base, USB_EP_INTR_SET_REG, epmask);
-+	musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
-+	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
-+	if (is_otg_enabled(musb))
-+		musb_writel(reg_base, USB_CORE_INTR_SET_REG,
-+			    USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
-+}
-+
-+/**
-+ * ti81xx_musb_disable - disable HDRC and flush interrupts
-+ */
-+void ti81xx_musb_disable(struct musb *musb)
-+{
-+	void __iomem *reg_base = musb->ctrl_base;
-+
-+	musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, USB_INTR_USB_MASK);
-+	musb_writel(reg_base, USB_EP_INTR_CLEAR_REG,
-+			 USB_TX_INTR_MASK | USB_RX_INTR_MASK);
-+	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
-+	musb_writel(reg_base, USB_IRQ_EOI, 0);
-+}
-+
-+#define	POLL_SECONDS	2
-+
-+static void otg_timer(unsigned long _musb)
-+{
-+	struct musb		*musb = (void *)_musb;
-+	void __iomem		*mregs = musb->mregs;
-+	u8			devctl;
-+	unsigned long		flags;
-+
-+	/* We poll because DaVinci's won't expose several OTG-critical
-+	* status change events (from the transceiver) otherwise.
-+	 */
-+	devctl = musb_readb(mregs, MUSB_DEVCTL);
-+	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
-+			otg_state_string(musb->xceiv->state));
-+
-+	spin_lock_irqsave(&musb->lock, flags);
-+	switch (musb->xceiv->state) {
-+	case OTG_STATE_A_WAIT_BCON:
-+		devctl &= ~MUSB_DEVCTL_SESSION;
-+		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
-+
-+		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
-+		if (devctl & MUSB_DEVCTL_HM) {
-+			musb->xceiv->state = OTG_STATE_A_IDLE;
-+			MUSB_HST_MODE(musb);
-+		} else {
-+			musb->xceiv->state = OTG_STATE_B_IDLE;
-+			MUSB_DEV_MODE(musb);
-+			mod_timer(&musb->otg_workaround,
-+					jiffies + POLL_SECONDS * HZ);
-+		}
-+		break;
-+	case OTG_STATE_A_WAIT_VFALL:
-+		/*
-+		 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
-+		 * RTL seems to mis-handle session "start" otherwise (or in
-+		 * our case "recover"), in routine "VBUS was valid by the time
-+		 * VBUSERR got reported during enumeration" cases.
-+		 */
-+		if (devctl & MUSB_DEVCTL_VBUS) {
-+			mod_timer(&musb->otg_workaround,
-+					jiffies + POLL_SECONDS * HZ);
-+			break;
-+		}
-+		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
-+		musb_writel(musb->ctrl_base, USB_CORE_INTR_SET_REG,
-+			    MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
-+		break;
-+	case OTG_STATE_B_IDLE:
-+		if (!is_peripheral_enabled(musb))
-+			break;
-+
-+		/*
-+		 * There's no ID-changed IRQ, so we have no good way to tell
-+		 * when to switch to the A-Default state machine (by setting
-+		 * the DEVCTL.SESSION flag).
-+		 *
-+		 * Workaround:  whenever we're in B_IDLE, try setting the
-+		 * session flag every few seconds.  If it works, ID was
-+		 * grounded and we're now in the A-Default state machine.
-+		 *
-+		 * NOTE: setting the session flag is _supposed_ to trigger
-+		 * SRP but clearly it doesn't.
-+		 */
-+		devctl = musb_readb(mregs, MUSB_DEVCTL);
-+		if (devctl & MUSB_DEVCTL_HM) {
-+			musb->xceiv->state = OTG_STATE_A_IDLE;
-+		} else {
-+			mod_timer(&musb->otg_workaround,
-+					jiffies + POLL_SECONDS * HZ);
-+			musb_writeb(musb->mregs, MUSB_DEVCTL, devctl |
-+				MUSB_DEVCTL_SESSION);
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+	spin_unlock_irqrestore(&musb->lock, flags);
-+}
-+
-+void ti81xx_musb_try_idle(struct musb *musb, unsigned long timeout)
-+{
-+	if (!is_otg_enabled(musb))
-+		return;
-+
-+	if (timeout == 0)
-+		timeout = jiffies + msecs_to_jiffies(3);
-+
-+	/* Never idle if active, or when VBUS timeout is not set as host */
-+	if (musb->is_active || (musb->a_wait_bcon == 0 &&
-+				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
-+		dev_dbg(musb->controller, "%s active, deleting timer\n",
-+			otg_state_string(musb->xceiv->state));
-+		del_timer(&musb->otg_workaround);
-+		musb->last_timer = jiffies;
-+		return;
-+	}
-+
-+	if (time_after(musb->last_timer, timeout) &&
-+					timer_pending(&musb->otg_workaround)) {
-+		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
-+		return;
-+	}
-+	musb->last_timer = timeout;
-+
-+	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
-+	    otg_state_string(musb->xceiv->state),
-+		jiffies_to_msecs(timeout - jiffies));
-+	mod_timer(&musb->otg_workaround, timeout);
-+}
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+static irqreturn_t cppi41dma_Interrupt(int irq, void *hci)
-+{
-+	struct musb  *musb = hci;
-+	u32 intr_status;
-+	irqreturn_t ret = IRQ_NONE;
-+	u32 q_cmpl_status_0, q_cmpl_status_1, q_cmpl_status_2;
-+	u32 usb0_tx_intr, usb0_rx_intr;
-+	u32 usb1_tx_intr, usb1_rx_intr;
-+	void *q_mgr_base = cppi41_queue_mgr[0].q_mgr_rgn_base;
-+	unsigned long flags;
-+
-+	musb = hci;
-+	/*
-+	 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
-+	 * don't get reflected in the interrupt source/mask registers.
-+	 */
-+	/*
-+	 * Check for the interrupts from Tx/Rx completion queues; they
-+	 * are level-triggered and will stay asserted until the queues
-+	 * are emptied.  We're using the queue pending register 0 as a
-+	 * substitute for the interrupt status register and reading it
-+	 * directly for speed.
-+	 */
-+	intr_status = usbss_read(USBSS_IRQ_STATUS);
-+
-+	if (intr_status)
-+		usbss_write(USBSS_IRQ_STATUS, intr_status);
-+	else
-+		printk(KERN_DEBUG "spurious usbss intr\n");
-+
-+	q_cmpl_status_0 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG2);
-+	q_cmpl_status_1 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG3);
-+	q_cmpl_status_2 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG4);
-+
-+	/* USB0 tx/rx completion */
-+	/* usb0 tx completion interrupt for ep1..15 */
-+	usb0_tx_intr = (q_cmpl_status_0 >> 29) |
-+			((q_cmpl_status_1 & 0xFFF) << 3);
-+	usb0_rx_intr = ((q_cmpl_status_1 & 0x07FFe000) >> 13);
-+
-+	usb1_tx_intr = (q_cmpl_status_1 >> 29) |
-+			((q_cmpl_status_2 & 0xFFF) << 3);
-+	usb1_rx_intr = ((q_cmpl_status_2 & 0x0fffe000) >> 13);
-+
-+	/* get proper musb handle based usb0/usb1 ctrl-id */
-+
-+	dev_dbg(musb->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb0_tx_intr,
-+				usb0_rx_intr);
-+	if (gmusb[0] && (usb0_tx_intr || usb0_rx_intr)) {
-+		spin_lock_irqsave(&gmusb[0]->lock, flags);
-+		cppi41_completion(gmusb[0], usb0_rx_intr,
-+					usb0_tx_intr);
-+		spin_unlock_irqrestore(&gmusb[0]->lock, flags);
-+		ret = IRQ_HANDLED;
-+	}
-+
-+	dev_dbg(musb->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb1_tx_intr,
-+		usb1_rx_intr);
-+	if (gmusb[1] && (usb1_rx_intr || usb1_tx_intr)) {
-+		spin_lock_irqsave(&gmusb[1]->lock, flags);
-+		cppi41_completion(gmusb[1], usb1_rx_intr,
-+			usb1_tx_intr);
-+		spin_unlock_irqrestore(&gmusb[1]->lock, flags);
-+		ret = IRQ_HANDLED;
-+	}
-+	usbss_write(USBSS_IRQ_EOI, 0);
-+
-+	return ret;
-+}
-+#endif
-+
-+int musb_simulate_babble(struct musb *musb)
-+{
-+	void __iomem *reg_base = musb->ctrl_base;
-+	void __iomem *mbase = musb->mregs;
-+	u8 reg;
-+
-+	/* during babble condition musb controller
-+	 * remove the session
-+	 */
-+	reg = musb_readb(mbase, MUSB_DEVCTL);
-+	reg &= ~MUSB_DEVCTL_SESSION;
-+	musb_writeb(mbase, MUSB_DEVCTL, reg);
-+	mdelay(100);
-+
-+	/* generate s/w babble interrupt */
-+	musb_writel(reg_base, USB_IRQ_STATUS_RAW_1,
-+		MUSB_INTR_BABBLE);
-+	return 0;
-+}
-+EXPORT_SYMBOL(musb_simulate_babble);
-+
-+void musb_babble_workaround(struct musb *musb)
-+{
-+	void __iomem *reg_base = musb->ctrl_base;
-+	struct device *dev = musb->controller;
-+	struct musb_hdrc_platform_data *plat = dev->platform_data;
-+	struct omap_musb_board_data *data = plat->board_data;
-+
-+	/* Reset the controller */
-+	musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
-+	udelay(100);
-+
-+	/* Shutdown the on-chip PHY and its PLL. */
-+	if (data->set_phy_power)
-+		data->set_phy_power(musb->id, 0);
-+	udelay(100);
-+
-+	musb_platform_set_mode(musb, MUSB_HOST);
-+	udelay(100);
-+
-+	/* enable the usbphy */
-+	if (data->set_phy_power)
-+		data->set_phy_power(musb->id, 1);
-+	mdelay(100);
-+
-+	/* save the usbotgss register contents */
-+	musb_platform_enable(musb);
-+
-+	musb_start(musb);
-+}
-+
-+static void evm_deferred_musb_restart(struct work_struct *work)
-+{
-+	struct musb *musb =
-+		container_of(work, struct musb, work);
-+
-+	ERR("deferred musb restart musbid(%d)\n", musb->id);
-+	musb_babble_workaround(musb);
-+}
-+
-+static irqreturn_t ti81xx_interrupt(int irq, void *hci)
-+{
-+	struct musb  *musb = hci;
-+	void __iomem *reg_base = musb->ctrl_base;
-+	unsigned long flags;
-+	irqreturn_t ret = IRQ_NONE;
-+	u32 pend1 = 0, pend2 = 0;
-+	u32 epintr, usbintr;
-+	u8  is_babble = 0;
-+
-+	spin_lock_irqsave(&musb->lock, flags);
-+
-+	/* Acknowledge and handle non-CPPI interrupts */
-+	/* Get endpoint interrupts */
-+	epintr = musb_readl(reg_base, USB_EP_INTR_STATUS_REG);
-+	musb->int_rx = (epintr & USB_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
-+	musb->int_tx = (epintr & USB_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
-+	if (epintr)
-+		musb_writel(reg_base, USB_EP_INTR_STATUS_REG, epintr);
-+
-+	/* Get usb core interrupts */
-+	usbintr = musb_readl(reg_base, USB_CORE_INTR_STATUS_REG);
-+	if (!usbintr && !epintr) {
-+		dev_dbg(musb->controller, "sprious interrupt\n");
-+		goto eoi;
-+	}
-+
-+	if (usbintr)
-+		musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
-+	musb->int_usb =	(usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
-+
-+	dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
-+	/*
-+	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
-+	 * AM3517's missing ID change IRQ.  We need an ID change IRQ to
-+	 * switch appropriately between halves of the OTG state machine.
-+	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
-+	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
-+	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
-+	 */
-+	if ((usbintr & MUSB_INTR_BABBLE) && is_otg_enabled(musb)
-+		&& (musb->xceiv->state == OTG_STATE_A_HOST))
-+		is_babble = 1;
-+	else if ((usbintr & MUSB_INTR_BABBLE) && !is_otg_enabled(musb)
-+		&& is_host_enabled(musb))
-+			is_babble = 1;
-+
-+	if (is_babble) {
-+		if (musb->enable_babble_work)
-+			musb->int_usb |= MUSB_INTR_DISCONNECT;
-+
-+		ERR("CAUTION: musb%d: Babble Interrupt Occured\n", musb->id);
-+		ERR("Please issue long reset to make usb functional !!\n");
-+	}
-+
-+	if (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT)) {
-+		int drvvbus = musb_readl(reg_base, USB_STAT_REG);
-+		void __iomem *mregs = musb->mregs;
-+		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
-+		int err;
-+
-+		err = is_host_enabled(musb) && (musb->int_usb &
-+						MUSB_INTR_VBUSERROR);
-+		if (err) {
-+			/*
-+			 * The Mentor core doesn't debounce VBUS as needed
-+			 * to cope with device connect current spikes. This
-+			 * means it's not uncommon for bus-powered devices
-+			 * to get VBUS errors during enumeration.
-+			 *
-+			 * This is a workaround, but newer RTL from Mentor
-+			 * seems to allow a better one: "re"-starting sessions
-+			 * without waiting for VBUS to stop registering in
-+			 * devctl.
-+			 */
-+			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
-+			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
-+			mod_timer(&musb->otg_workaround,
-+						jiffies + POLL_SECONDS * HZ);
-+			WARNING("VBUS error workaround (delay coming)\n");
-+		} else if (is_host_enabled(musb) && drvvbus) {
-+			musb->is_active = 1;
-+			MUSB_HST_MODE(musb);
-+			musb->xceiv->default_a = 1;
-+			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
-+			del_timer(&musb->otg_workaround);
-+		} else {
-+			musb->is_active = 0;
-+			MUSB_DEV_MODE(musb);
-+			musb->xceiv->default_a = 0;
-+			musb->xceiv->state = OTG_STATE_B_IDLE;
-+		}
-+
-+		/* NOTE: this must complete power-on within 100 ms. */
-+		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
-+				drvvbus ? "on" : "off",
-+				otg_state_string(musb->xceiv->state),
-+				err ? " ERROR" : "",
-+				devctl);
-+		ret = IRQ_HANDLED;
-+	}
-+
-+	if (musb->int_tx || musb->int_rx || musb->int_usb)
-+		ret |= musb_interrupt(musb);
-+
-+ eoi:
-+	/* EOI needs to be written for the IRQ to be re-asserted. */
-+	if (ret == IRQ_HANDLED || epintr || usbintr) {
-+		/* write EOI */
-+		musb_writel(reg_base, USB_IRQ_EOI, 1);
-+	}
-+
-+	/* Poll for ID change */
-+	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
-+		mod_timer(&musb->otg_workaround, jiffies + POLL_SECONDS * HZ);
-+
-+	spin_unlock_irqrestore(&musb->lock, flags);
-+
-+	if (ret != IRQ_HANDLED) {
-+		if (epintr || usbintr)
-+			/*
-+			 * We sometimes get unhandled IRQs in the peripheral
-+			 * mode from EP0 and SOF...
-+			 */
-+			dev_dbg(musb->controller, "Unhandled USB IRQ %08x-%08x\n",
-+					 epintr, usbintr);
-+		else if (printk_ratelimit())
-+			/*
-+			 * We've seen series of spurious interrupts in the
-+			 * peripheral mode after USB reset and then after some
-+			 * time a real interrupt storm starting...
-+			 */
-+			dev_dbg(musb->controller, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
-+					 pend1, pend2);
-+	}
-+
-+	if (is_babble) {
-+		if (!musb->enable_babble_work) {
-+			musb_writeb(musb->mregs, MUSB_DEVCTL,
-+				musb_readb(musb->mregs, MUSB_DEVCTL) |
-+				MUSB_DEVCTL_SESSION);
-+		} else {
-+			ERR("Babble: devtcl(%x)Restarting musb....\n",
-+				 musb_readb(musb->mregs, MUSB_DEVCTL));
-+			schedule_work(&musb->work);
-+		}
-+	}
-+	return ret;
-+}
-+int ti81xx_musb_set_mode(struct musb *musb, u8 musb_mode)
-+{
-+	void __iomem *reg_base = musb->ctrl_base;
-+	u32 regval;
-+
-+	/* TODO: implement this using CONF0 */
-+	if (musb_mode == MUSB_HOST) {
-+		regval = musb_readl(reg_base, USB_MODE_REG);
-+
-+		regval &= ~USBMODE_USBID_HIGH;
-+		if (usbid_sw_ctrl && cpu_is_ti816x())
-+			regval |= USBMODE_USBID_MUXSEL;
-+
-+		musb_writel(reg_base, USB_MODE_REG, regval);
-+		musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
-+		dev_dbg(musb->controller, "host: value of mode reg=%x regval(%x)\n",
-+			musb_readl(reg_base, USB_MODE_REG), regval);
-+	} else if (musb_mode == MUSB_PERIPHERAL) {
-+		/* TODO commmented writing 8 to USB_MODE_REG device
-+			mode is not working */
-+		regval = musb_readl(reg_base, USB_MODE_REG);
-+
-+		regval |= USBMODE_USBID_HIGH;
-+		if (usbid_sw_ctrl && cpu_is_ti816x())
-+			regval |= USBMODE_USBID_MUXSEL;
-+
-+		musb_writel(reg_base, USB_MODE_REG, regval);
-+		dev_dbg(musb->controller, "device: value of mode reg=%x regval(%x)\n",
-+			musb_readl(reg_base, USB_MODE_REG), regval);
-+	} else if (musb_mode == MUSB_OTG) {
-+		musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
-+	} else
-+		return -EIO;
-+
-+	return 0;
-+}
-+
-+int ti81xx_musb_init(struct musb *musb)
-+{
-+	void __iomem *reg_base = musb->ctrl_base;
-+	struct device *dev = musb->controller;
-+	struct musb_hdrc_platform_data *plat = dev->platform_data;
-+	struct omap_musb_board_data *data = plat->board_data;
-+	u32 rev;
-+	u8 mode;
-+
-+	if (musb->id < 2)
-+		gmusb[musb->id] = musb;
-+
-+	usb_nop_xceiv_register(musb->id);
-+
-+	musb->xceiv = otg_get_transceiver(musb->id);
-+	if (!musb->xceiv)
-+		return -ENODEV;
-+
-+	/* mentor is at offset of 0x400 in am3517/ti81xx */
-+	musb->mregs += USB_MENTOR_CORE_OFFSET;
-+
-+	/* Returns zero if e.g. not clocked */
-+	rev = musb_readl(reg_base, USB_REVISION_REG);
-+	if (!rev)
-+		return -ENODEV;
-+
-+	if (is_host_enabled(musb))
-+		setup_timer(&musb->otg_workaround, otg_timer,
-+					(unsigned long) musb);
-+
-+	/* Reset the controller */
-+	musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
-+
-+	/* wait till reset bit clears */
-+	while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
-+		cpu_relax();
-+
-+	/* Start the on-chip PHY and its PLL. */
-+	if (data->set_phy_power)
-+		data->set_phy_power(musb->id, 1);
-+
-+	musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
-+	musb->isr = ti81xx_interrupt;
-+
-+	if (cpu_is_ti816x())
-+		usbid_sw_ctrl = 1;
-+
-+	if (is_otg_enabled(musb)) {
-+		/* if usb-id contolled through software for ti816x then
-+		 * configure the usb0 in peripheral mode and usb1 in
-+		 * host mode
-+		*/
-+		if (usbid_sw_ctrl && cpu_is_ti816x())
-+			mode = musb->id ? MUSB_HOST : MUSB_PERIPHERAL;
-+		else
-+			mode = MUSB_OTG;
-+	} else
-+		/* set musb controller to host mode */
-+		mode = is_host_enabled(musb) ? MUSB_HOST : MUSB_PERIPHERAL;
-+
-+	/* set musb controller to host mode */
-+	musb_platform_set_mode(musb, mode);
-+
-+	/* enable babble workaround */
-+	INIT_WORK(&musb->work, evm_deferred_musb_restart);
-+	musb->enable_babble_work = 0;
-+
-+	musb_writel(reg_base, USB_IRQ_EOI, 0);
-+
-+	return 0;
-+}
-+
-+/* TI81xx supports only 32bit read operation */
-+void ti81xx_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
-+{
-+	void __iomem *fifo = hw_ep->fifo;
-+	u32		val;
-+	int		i;
-+
-+	/* Read for 32bit-aligned destination address */
-+	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
-+		readsl(fifo, dst, len >> 2);
-+		dst += len & ~0x03;
-+		len &= 0x03;
-+	}
-+	/*
-+	 * Now read the remaining 1 to 3 byte or complete length if
-+	 * unaligned address.
-+	 */
-+	if (len > 4) {
-+		for (i = 0; i < (len >> 2); i++) {
-+			*(u32 *) dst = musb_readl(fifo, 0);
-+			dst += 4;
-+		}
-+		len &= 0x03;
-+	}
-+	if (len > 0) {
-+		val = musb_readl(fifo, 0);
-+		memcpy(dst, &val, len);
-+	}
-+}
-+
-+int ti81xx_musb_exit(struct musb *musb)
-+{
-+	struct device *dev = musb->controller;
-+	struct musb_hdrc_platform_data *plat = dev->platform_data;
-+	struct omap_musb_board_data *data = plat->board_data;
-+
-+	if (is_host_enabled(musb))
-+		del_timer_sync(&musb->otg_workaround);
-+
-+	/* Shutdown the on-chip PHY and its PLL. */
-+	if (data->set_phy_power)
-+		data->set_phy_power(musb->id, 0);
-+
-+	otg_put_transceiver(musb->xceiv);
-+	usb_nop_xceiv_unregister(musb->id);
-+
-+	return 0;
-+}
-+
-+static struct musb_platform_ops ti81xx_ops = {
-+	.fifo_mode	= 4,
-+	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
-+	.init		= ti81xx_musb_init,
-+	.exit		= ti81xx_musb_exit,
-+
-+	.enable		= ti81xx_musb_enable,
-+	.disable	= ti81xx_musb_disable,
-+
-+	.try_idle	= ti81xx_musb_try_idle,
-+	.set_mode	= ti81xx_musb_set_mode,
-+
-+	.read_fifo      = ti81xx_musb_read_fifo,
-+	.write_fifo     = musb_write_fifo,
-+
-+	.dma_controller_create	= cppi41_dma_controller_create,
-+	.dma_controller_destroy	= cppi41_dma_controller_destroy,
-+	.simulate_babble_intr	= musb_simulate_babble,
-+};
-+
-+static void __devexit ti81xx_delete_musb_pdev(struct ti81xx_glue *glue, u8 id)
-+{
-+	platform_device_del(glue->musb[id]);
-+	platform_device_put(glue->musb[id]);
-+}
-+
-+static int __devinit ti81xx_create_musb_pdev(struct ti81xx_glue *glue, u8 id)
-+{
-+	struct device *dev = glue->dev;
-+	struct platform_device *pdev = to_platform_device(dev);
-+	struct musb_hdrc_platform_data  *pdata = dev->platform_data;
-+	struct omap_musb_board_data *bdata = pdata->board_data;
-+	struct platform_device	*musb;
-+	struct resource *res;
-+	struct resource	resources[2];
-+	char res_name[10];
-+	int ret = 0;
-+
-+	/* get memory resource */
-+	sprintf(res_name, "musb%d", id);
-+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
-+	if (!res) {
-+		dev_err(dev, "%s get mem resource failed\n", res_name);
-+		ret = -ENODEV;
-+		goto err0;
-+	}
-+	res->parent = NULL;
-+	resources[0] = *res;
-+
-+	/* get irq resource */
-+	sprintf(res_name, "musb%d-irq", id);
-+	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
-+	if (!res) {
-+		dev_err(dev, "%s get irq resource failed\n", res_name);
-+		ret = -ENODEV;
-+		goto err0;
-+	}
-+	res->parent = NULL;
-+	resources[1] = *res;
-+
-+	/* allocate the child platform device */
-+	musb = platform_device_alloc("musb-hdrc", id);
-+	if (!musb) {
-+		dev_err(dev, "failed to allocate musb device\n");
-+		goto err0;
-+	}
-+
-+	musb->id			= id;
-+	musb->dev.parent		= dev;
-+	musb->dev.dma_mask		= &musb_dmamask;
-+	musb->dev.coherent_dma_mask	= musb_dmamask;
-+
-+	glue->musb[id]			= musb;
-+
-+	pdata->platform_ops		= &ti81xx_ops;
-+
-+	ret = platform_device_add_resources(musb, resources, 2);
-+	if (ret) {
-+		dev_err(dev, "failed to add resources\n");
-+		goto err1;
-+	}
-+
-+	if (id == 0)
-+		pdata->mode = bdata->mode & USB0PORT_MODEMASK;
-+	else
-+		pdata->mode = (bdata->mode & USB1PORT_MODEMASK)
-+					>> USB1PORT_MODESHIFT;
-+
-+	dev_info(dev, "musb%d, board_mode=0x%x, plat_mode=0x%x\n",
-+					id, bdata->mode, pdata->mode);
-+
-+	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
-+	if (ret) {
-+		dev_err(dev, "failed to add platform_data\n");
-+		goto err1;
-+	}
-+
-+	ret = platform_device_add(musb);
-+	if (ret) {
-+		dev_err(dev, "failed to register musb device\n");
-+		goto err1;
-+	}
-+
-+	return 0;
-+
-+err1:
-+	platform_device_put(musb);
-+err0:
-+	return ret;
-+}
-+
-+static int __init ti81xx_probe(struct platform_device *pdev)
-+{
-+	struct ti81xx_glue *glue;
-+	struct device *dev = &pdev->dev;
-+	struct musb_hdrc_platform_data *plat = dev->platform_data;
-+	struct omap_musb_board_data *data = plat->board_data;
-+	int ret = 0, i;
-+	struct resource *res;
-+
-+	/* allocate glue */
-+	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
-+	if (!glue) {
-+		dev_err(&pdev->dev, "unable to allocate glue memory\n");
-+		ret = -ENOMEM;
-+		goto err0;
-+	}
-+
-+	/* get memory resource */
-+	glue->mem_pa = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!glue->mem_pa) {
-+		dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
-+		ret = -ENODEV;
-+		goto err1;
-+	}
-+
-+	/* get memory resource */
-+	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "usbss-irq");
-+	if (!res) {
-+		dev_err(&pdev->dev, "failed to get usbss irq resourse\n");
-+		ret = -ENODEV;
-+		goto err1;
-+	}
-+	glue->irq = res->start;
-+
-+	/* iomap for usbss mem space */
-+	glue->mem_va =
-+		ioremap(glue->mem_pa->start, resource_size(glue->mem_pa));
-+	if (!glue->mem_va) {
-+		dev_err(&pdev->dev, "usbss ioremap failed\n");
-+		ret = -ENOMEM;
-+		goto err1;
-+	}
-+	usbss_virt_base = glue->mem_va;
-+
-+	glue->first = 1;
-+	glue->dev = &pdev->dev;
-+	platform_set_drvdata(pdev, glue);
-+
-+	/* enable clocks */
-+	pm_runtime_enable(&pdev->dev);
-+	ret = pm_runtime_get_sync(&pdev->dev);
-+	if (ret < 0) {
-+		dev_err(dev, "pm_runtime_get_sync FAILED");
-+		goto err2;
-+	}
-+
-+	/* usb subsystem init */
-+	usbotg_ss_init();
-+
-+	/* clear any USBSS interrupts */
-+	writel(0, glue->mem_va + USBSS_IRQ_EOI);
-+	writel(readl(glue->mem_va + USBSS_IRQ_STATUS),
-+					glue->mem_va + USBSS_IRQ_STATUS);
-+
-+	/* create the child platform device for mulitple instances of musb */
-+	for (i = 0; i <= data->instances; ++i) {
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+		/* initialize the cppi41dma init */
-+		cppi41_init(i, glue->irq, data->instances+1);
-+#endif
-+		ret = ti81xx_create_musb_pdev(glue, i);
-+		if (ret != 0)
-+			goto err3;
-+	}
-+
-+	return 0;
-+
-+err3:
-+	pm_runtime_put_sync(&pdev->dev);
-+err2:
-+	pm_runtime_disable(&pdev->dev);
-+	iounmap(glue->mem_va);
-+err1:
-+	kfree(glue);
-+err0:
-+	return ret;
-+}
-+
-+static int __exit ti81xx_remove(struct platform_device *pdev)
-+{
-+	struct ti81xx_glue *glue = platform_get_drvdata(pdev);
-+	struct device *dev = &pdev->dev;
-+	struct musb_hdrc_platform_data *plat = dev->platform_data;
-+	struct omap_musb_board_data *data = plat->board_data;
-+	int i;
-+
-+	/* delete the child platform device for mulitple instances of musb */
-+	for (i = 0; i <= data->instances; ++i)
-+		ti81xx_delete_musb_pdev(glue, i);
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	cppi41_free();
-+#endif
-+	/* iounmap */
-+	iounmap(glue->mem_va);
-+	usbotg_ss_uninit();
-+
-+	pm_runtime_put_sync(&pdev->dev);
-+	pm_runtime_disable(&pdev->dev);
-+	kfree(glue);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_PM
-+static void ti81xx_save_context(struct ti81xx_glue *glue)
-+{
-+	struct ti81xx_usbss_regs *usbss = &glue->usbss_regs;
-+	u8 i, j;
-+
-+	/* save USBSS register */
-+	usbss->irq_en_set = usbss_read(USBSS_IRQ_ENABLE_SET);
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	for (i = 0 ; i < 4 ; i++) {
-+		usbss->irq_dma_th_tx0[i] =
-+			usbss_read(USBSS_IRQ_DMA_THRESHOLD_TX0 + (0x4 * i));
-+		usbss->irq_dma_th_rx0[i] =
-+			usbss_read(USBSS_IRQ_DMA_THRESHOLD_RX0 + (0x4 * i));
-+		usbss->irq_dma_th_tx1[i] =
-+			usbss_read(USBSS_IRQ_DMA_THRESHOLD_TX1 + (0x4 * i));
-+		usbss->irq_dma_th_rx1[i] =
-+			usbss_read(USBSS_IRQ_DMA_THRESHOLD_RX1 + (0x4 * i));
-+
-+		usbss->irq_frame_th_tx0[i] =
-+			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_TX0 + (0x4 * i));
-+		usbss->irq_frame_th_rx0[i] =
-+			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_RX0 + (0x4 * i));
-+		usbss->irq_frame_th_tx1[i] =
-+			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_TX1 + (0x4 * i));
-+		usbss->irq_frame_th_rx1[i] =
-+			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_RX1 + (0x4 * i));
-+	}
-+	for (i = 0 ; i < 2 ; i++) {
-+		usbss->irq_dma_en[i] =
-+			usbss_read(USBSS_IRQ_DMA_ENABLE_0 + (0x4 * i));
-+		usbss->irq_frame_en[i] =
-+			usbss_read(USBSS_IRQ_FRAME_ENABLE_0 + (0x4 * i));
-+	}
-+#endif
-+	/* save usbX register */
-+	for (i = 0 ; i < 2 ; i++) {
-+		struct ti81xx_usb_regs *usb = &glue->usb_regs[i];
-+		struct musb *musb = platform_get_drvdata(glue->musb[i]);
-+		void __iomem *cbase = musb->ctrl_base;
-+
-+		/* disable the timers */
-+		if (timer_pending(&musb->otg_workaround) &&
-+					is_host_enabled(musb)) {
-+			del_timer_sync(&musb->otg_workaround);
-+			musb->en_otgw_timer = 1;
-+		}
-+
-+		if (timer_pending(&musb->otg_workaround) &&
-+					is_otg_enabled(musb)) {
-+			del_timer_sync(&musb->otg_timer);
-+			musb->en_otg_timer = 1;
-+		}
-+
-+		musb_save_context(musb);
-+		usb->control = musb_readl(cbase, USB_CTRL_REG);
-+
-+		for (j = 0 ; j < 2 ; j++)
-+			usb->irq_en_set[j] = musb_readl(cbase,
-+					USB_IRQ_ENABLE_SET_0 + (0x4 * j));
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+		usb->tx_mode = musb_readl(cbase, USB_TX_MODE_REG);
-+		usb->rx_mode = musb_readl(cbase, USB_RX_MODE_REG);
-+
-+		for (j = 0 ; j < 15 ; j++)
-+			usb->grndis_size[j] = musb_readl(cbase,
-+					USB_GENERIC_RNDIS_EP_SIZE_REG(j + 1));
-+
-+		usb->auto_req = musb_readl(cbase, TI81XX_USB_AUTOREQ_REG);
-+		usb->teardn = musb_readl(cbase, TI81XX_USB_TEARDOWN_REG);
-+		usb->th_xdma_idle = musb_readl(cbase, USB_TH_XDMA_IDLE_REG);
-+#endif
-+		usb->srp_fix = musb_readl(cbase, USB_SRP_FIX_TIME_REG);
-+		usb->phy_utmi = musb_readl(cbase, USB_PHY_UTMI_REG);
-+		usb->mgc_utmi_loopback = musb_readl(cbase, USB_PHY_UTMI_LB_REG);
-+		usb->mode = musb_readl(cbase, USB_MODE_REG);
-+	}
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	/* save CPPI4.1 DMA register for dma block 0 */
-+	cppi41_save_context(0);
-+#endif
-+}
-+static void ti81xx_restore_context(struct ti81xx_glue *glue)
-+{
-+	struct ti81xx_usbss_regs *usbss = &glue->usbss_regs;
-+	u8 i, j;
-+
-+	/* restore USBSS register */
-+	usbss_write(USBSS_IRQ_ENABLE_SET, usbss->irq_en_set);
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	for (i = 0 ; i < 4 ; i++) {
-+		usbss_write(USBSS_IRQ_DMA_THRESHOLD_TX0 + (0x4 * i),
-+				usbss->irq_dma_th_tx0[i]);
-+		usbss_write(USBSS_IRQ_DMA_THRESHOLD_RX0 + (0x4 * i),
-+				usbss->irq_dma_th_rx0[i]);
-+		usbss_write(USBSS_IRQ_DMA_THRESHOLD_TX1 + (0x4 * i),
-+				usbss->irq_dma_th_tx1[i]);
-+		usbss_write(USBSS_IRQ_DMA_THRESHOLD_RX1 + (0x4 * i),
-+				usbss->irq_dma_th_rx1[i]);
-+
-+		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_TX0 + (0x4 * i),
-+				usbss->irq_frame_th_tx0[i]);
-+		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_RX0 + (0x4 * i),
-+				usbss->irq_frame_th_rx0[i]);
-+		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_TX1 + (0x4 * i),
-+				usbss->irq_frame_th_tx1[i]);
-+		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_RX1 + (0x4 * i),
-+				usbss->irq_frame_th_rx1[i]);
-+	}
-+	for (i = 0 ; i < 2 ; i++) {
-+		usbss_write(USBSS_IRQ_DMA_ENABLE_0 + (0x4 * i),
-+				usbss->irq_dma_en[i]);
-+		usbss_write(USBSS_IRQ_FRAME_ENABLE_0 + (0x4 * i),
-+				usbss->irq_frame_en[i]);
-+	}
-+#endif
-+	/* restore usbX register */
-+	for (i = 0 ; i < 2 ; i++) {
-+		struct ti81xx_usb_regs *usb = &glue->usb_regs[i];
-+		struct musb *musb = platform_get_drvdata(glue->musb[i]);
-+		void __iomem *cbase = musb->ctrl_base;
-+
-+		musb_restore_context(musb);
-+		musb_writel(cbase, USB_CTRL_REG, usb->control);
-+
-+		for (j = 0 ; j < 2 ; j++)
-+			musb_writel(cbase, USB_IRQ_ENABLE_SET_0 + (0x4 * j),
-+					usb->irq_en_set[j]);
-+
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+		musb_writel(cbase, USB_TX_MODE_REG, usb->tx_mode);
-+		musb_writel(cbase, USB_RX_MODE_REG, usb->rx_mode);
-+
-+		for (j = 0 ; j < 15 ; j++)
-+			musb_writel(cbase, USB_GENERIC_RNDIS_EP_SIZE_REG(j + 1),
-+					usb->grndis_size[j]);
-+
-+		musb_writel(cbase, TI81XX_USB_AUTOREQ_REG, usb->auto_req);
-+		musb_writel(cbase, TI81XX_USB_TEARDOWN_REG, usb->teardn);
-+		musb_writel(cbase, USB_TH_XDMA_IDLE_REG, usb->th_xdma_idle);
-+#endif
-+		musb_writel(cbase, USB_SRP_FIX_TIME_REG, usb->srp_fix);
-+		musb_writel(cbase, USB_PHY_UTMI_REG, usb->phy_utmi);
-+		musb_writel(cbase, USB_PHY_UTMI_LB_REG, usb->mgc_utmi_loopback);
-+		musb_writel(cbase, USB_MODE_REG, usb->mode);
-+
-+		/* reenable the timers */
-+		if (musb->en_otgw_timer && is_host_enabled(musb)) {
-+			mod_timer(&musb->otg_workaround,
-+					jiffies + POLL_SECONDS * HZ);
-+			musb->en_otgw_timer = 0;
-+		}
-+		if (musb->en_otg_timer && is_otg_enabled(musb)) {
-+			mod_timer(&musb->otg_timer,
-+					jiffies + POLL_SECONDS * HZ);
-+			musb->en_otg_timer = 0;
-+		}
-+	}
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	/* restore CPPI4.1 DMA register for dma block 0 */
-+	cppi41_restore_context(0, dma_sched_table);
-+#endif
-+	/* controller needs delay for successful resume */
-+	msleep(200);
-+}
-+static int ti81xx_runtime_suspend(struct device *dev)
-+{
-+	struct ti81xx_glue *glue = dev_get_drvdata(dev);
-+	struct musb_hdrc_platform_data *plat = dev->platform_data;
-+	struct omap_musb_board_data *data = plat->board_data;
-+	int i;
-+
-+	/* save wrappers and cppi4.1 dma register */
-+	ti81xx_save_context(glue);
-+
-+	/* Shutdown the on-chip PHY and its PLL. */
-+	for (i = 0; i <= data->instances; ++i) {
-+		if (data->set_phy_power)
-+			data->set_phy_power(i, 0);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ti81xx_runtime_resume(struct device *dev)
-+{
-+	struct ti81xx_glue *glue = dev_get_drvdata(dev);
-+	struct musb_hdrc_platform_data *plat = dev->platform_data;
-+	struct omap_musb_board_data *data = plat->board_data;
-+	int i;
-+
-+	/*
-+	 * ignore first call of resume as all registers are not yet
-+	 * initialized
-+	 */
-+	if (glue->first) {
-+		glue->first = 0;
-+		return 0;
-+	}
-+
-+	/* Start the on-chip PHY and its PLL. */
-+	for (i = 0; i <= data->instances; ++i) {
-+		if (data->set_phy_power)
-+			data->set_phy_power(i, 1);
-+	}
-+
-+	/* restore wrappers and cppi4.1 dma register */
-+	ti81xx_restore_context(glue);
-+
-+	return 0;
-+}
-+
-+static const struct dev_pm_ops ti81xx_pm_ops = {
-+	.runtime_suspend = ti81xx_runtime_suspend,
-+	.runtime_resume	= ti81xx_runtime_resume,
-+};
-+
-+#define DEV_PM_OPS	(&ti81xx_pm_ops)
-+#else
-+#define DEV_PM_OPS	NULL
-+#endif
-+
-+static struct platform_driver ti81xx_musb_driver = {
-+	.remove         = __exit_p(ti81xx_remove),
-+	.driver         = {
-+		.name   = "musb-ti81xx",
-+		.pm	= DEV_PM_OPS,
-+	},
-+};
-+
-+MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
-+MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
-+MODULE_LICENSE("GPL v2");
-+
-+static int __init ti81xx_glue_init(void)
-+{
-+	return platform_driver_probe(&ti81xx_musb_driver, ti81xx_probe);
-+}
-+subsys_initcall(ti81xx_glue_init);
-+
-+static void __exit ti81xx_glue_exit(void)
-+{
-+#ifdef CONFIG_USB_TI_CPPI41_DMA
-+	/* free the usbss irq */
-+	free_irq(TI81XX_IRQ_USBSS, 0);
-+#endif
-+
-+	/* disable the interrupts */
-+	usbss_write(USBSS_IRQ_EOI, 0);
-+	usbss_write(USBSS_IRQ_ENABLE_SET, 0);
-+	usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0);
-+
-+	/* unregister platform driver */
-+	platform_driver_unregister(&ti81xx_musb_driver);
-+}
-+module_exit(ti81xx_glue_exit);
-diff --git a/drivers/usb/musb/ti81xx.h b/drivers/usb/musb/ti81xx.h
-new file mode 100644
-index 0000000..e0dbd3e
---- /dev/null
-+++ b/drivers/usb/musb/ti81xx.h
-@@ -0,0 +1,173 @@
-+/*
-+ * Copyright (C) 2005-2006 by Texas Instruments
-+ *
-+ * The Inventra Controller Driver for Linux is free software; you
-+ * can redistribute it and/or modify it under the terms of the GNU
-+ * General Public License version 2 as published by the Free Software
-+ * Foundation.
-+ */
-+
-+#ifndef __MUSB_HDRDF_H__
-+#define __MUSB_HDRDF_H__
-+
-+#define TI81XX_USB_CPPIDMA_BASE 0x47402000
-+#define TI81XX_USB_CPPIDMA_LEN  0x5FFF
-+#define TI81XX_IRQ_USBSS        17
-+
-+/* Netra USB susbsystem register offsets */
-+#define USBSS_REVISION			0x0000
-+#define USBSS_SYSCONFIG			0x0010
-+/* USBSS EOI interrupt register */
-+#define USBSS_IRQ_EOI			0x0020
-+/* USBSS interrupt generation/status register */
-+#define USBSS_IRQ_STATUS_RAW		0x0024
-+/* USBSS interrupt status register */
-+#define USBSS_IRQ_STATUS		0x0028
-+/* USBSS interrupt enable register */
-+#define USBSS_IRQ_ENABLE_SET		0x002c
-+/* USBSS interrupt clear register */
-+#define USBSS_IRQ_ENABLE_CLEAR		0x0030
-+/* USB0: TxDMA 8bit tx completion interrupt pacing
-+	threshold value for ep1..15 */
-+#define USBSS_IRQ_DMA_THRESHOLD_TX0	0x0100
-+/* USB0: RxDMA 8bit rx completion interrupt pacing
-+	threshold value for ep1..15 */
-+#define USBSS_IRQ_DMA_THRESHOLD_RX0	0x0110
-+/* USB1: TxDMA 8bit tx completion interrupt pacing
-+	threshold value for ep1..15 */
-+#define USBSS_IRQ_DMA_THRESHOLD_TX1	0x0120
-+/* USB1: RxDMA 8bit rx completion interrupt pacing
-+	threshold value for ep1..15 */
-+#define USBSS_IRQ_DMA_THRESHOLD_RX1	0x0130
-+/* USB0: TxDMA threshold enable tx completion for ep1..ep15
-+	RxDMA threshold enable rx completion for ep1..ep15 */
-+#define USBSS_IRQ_DMA_ENABLE_0		0x0140
-+/* USB1: TxDMA threshold enable for ep1..ep15
-+	RxDMA threshold enable for ep1..ep15 */
-+#define USBSS_IRQ_DMA_ENABLE_1		0x0144
-+/* USB0: TxDMA Frame threshold for tx completion for ep1..ep15
-+	RxDMA Frame threshold for rx completion for ep1..ep15 */
-+#define USBSS_IRQ_FRAME_THRESHOLD_TX0	0x0200
-+#define USBSS_IRQ_FRAME_THRESHOLD_RX0	0x0210
-+/* USB1: TxDMA Frame threshold for tx completion for ep1..ep15
-+	RxDMA Frame threshold for rx completion for ep1..ep15 */
-+#define USBSS_IRQ_FRAME_THRESHOLD_TX1	0x0220
-+#define USBSS_IRQ_FRAME_THRESHOLD_RX1	0x0230
-+/* USB0: Frame threshold enable tx completion for ep1..ep15
-+	Frame threshold enable rx completion for ep1..ep15 */
-+#define USBSS_IRQ_FRAME_ENABLE_0	0x0240
-+#define USBSS_IRQ_FRAME_ENABLE_1	0x0244
-+
-+
-+/* USB 2.0 OTG module registers */
-+#define USB_REVISION_REG        0x0000
-+#define USB_CTRL_REG            0x0014
-+#define USB_STAT_REG            0x0018
-+#define	USB_IRQ_MERGED_STATUS	0x0020
-+#define USB_IRQ_EOI		0x0024
-+#define	USB_IRQ_STATUS_RAW_0	0x0028
-+#define	USB_IRQ_STATUS_RAW_1	0x002c
-+#define	USB_IRQ_STATUS_0	0x0030
-+#define	USB_IRQ_STATUS_1	0x0034
-+#define	USB_IRQ_ENABLE_SET_0	0x0038
-+#define	USB_IRQ_ENABLE_SET_1	0x003c
-+#define	USB_IRQ_ENABLE_CLR_0	0x0040
-+#define	USB_IRQ_ENABLE_CLR_1	0x0044
-+
-+#define USB_EP_INTR_SET_REG		(USB_IRQ_ENABLE_SET_0)
-+#define USB_CORE_INTR_SET_REG		(USB_IRQ_ENABLE_SET_1)
-+#define USB_EP_INTR_CLEAR_REG		(USB_IRQ_ENABLE_CLR_0)
-+#define USB_CORE_INTR_CLEAR_REG		(USB_IRQ_ENABLE_CLR_1)
-+#define USB_EP_INTR_STATUS_REG		(USB_IRQ_STATUS_0)
-+#define USB_CORE_INTR_STATUS_REG	(USB_IRQ_STATUS_1)
-+
-+#define USB_GRNDIS_EPSIZE_OFFS	0X0080
-+#define USB_SRP_FIX_TIME_REG    0x00d4
-+#define USB_TH_XDMA_IDLE_REG    0x00dc
-+#define USB_PHY_UTMI_REG	0x00e0
-+#define USB_PHY_UTMI_LB_REG	0x00e4
-+#define USB_MODE_REG		0x00e8
-+
-+#define QUEUE_THRESHOLD_INTR_ENABLE_REG 0xc0
-+#define QUEUE_63_THRESHOLD_REG  0xc4
-+#define QUEUE_63_THRESHOLD_INTR_CLEAR_REG 0xc8
-+#define QUEUE_65_THRESHOLD_REG  0xd4
-+#define QUEUE_65_THRESHOLD_INTR_CLEAR_REG 0xd8
-+
-+/* Control register bits */
-+#define USB_SOFT_RESET_MASK     1
-+
-+/* Mode register bits */
-+#define USB_MODE_SHIFT(n)       ((((n) - 1) << 1))
-+#define USB_MODE_MASK(n)        (3 << USB_MODE_SHIFT(n))
-+#define USB_RX_MODE_SHIFT(n)    USB_MODE_SHIFT(n)
-+#define USB_TX_MODE_SHIFT(n)    USB_MODE_SHIFT(n)
-+#define USB_RX_MODE_MASK(n)     USB_MODE_MASK(n)
-+#define USB_TX_MODE_MASK(n)     USB_MODE_MASK(n)
-+#define USB_TRANSPARENT_MODE    0
-+#define USB_RNDIS_MODE          1
-+#define USB_CDC_MODE            2
-+#define USB_GENERIC_RNDIS_MODE  3
-+
-+/* AutoReq register bits */
-+#define USB_RX_AUTOREQ_SHIFT(n) (((n) - 1) << 1)
-+#define USB_RX_AUTOREQ_MASK(n)  (3 << USB_RX_AUTOREQ_SHIFT(n))
-+#define USB_NO_AUTOREQ          0
-+#define USB_AUTOREQ_ALL_BUT_EOP 1
-+#define USB_AUTOREQ_ALWAYS      3
-+
-+/* Teardown register bits */
-+#define USB_TX_TDOWN_SHIFT(n)   (16 + (n))
-+#define USB_TX_TDOWN_MASK(n)    (1 << USB_TX_TDOWN_SHIFT(n))
-+#define USB_RX_TDOWN_SHIFT(n)   (n)
-+#define USB_RX_TDOWN_MASK(n)    (1 << USB_RX_TDOWN_SHIFT(n))
-+
-+/* USB interrupt register bits */
-+#define USB_INTR_USB_SHIFT      0
-+#define USB_INTR_USB_MASK       (0x1ff << USB_INTR_USB_SHIFT) /* 8 Mentor */
-+				/* interrupts and DRVVBUS interrupt */
-+#define USB_INTR_DRVVBUS        0x100
-+#define USB_INTR_RX_SHIFT       16
-+#define USB_INTR_TX_SHIFT       0
-+
-+#define USB_MENTOR_CORE_OFFSET  0x400
-+#define USB_CPPI41_NUM_CH       15
-+
-+#define MAX_MUSB_INSTANCE	2
-+/* CPPI 4.1 queue manager registers */
-+#define QMGR_PEND0_REG		0x4090
-+#define QMGR_PEND1_REG		0x4094
-+#define QMGR_PEND2_REG		0x4098
-+
-+#define QMGR_RGN_OFFS		0x4000
-+#define QMRG_DESCRGN_OFFS	0x5000
-+#define QMGR_REG_OFFS		0x6000
-+#define QMGR_STAT_OFFS		0x7000
-+#define DMA_GLBCTRL_OFFS	0x2000
-+#define DMA_CHCTRL_OFFS		0x2800
-+#define DMA_SCHED_OFFS		0x3000
-+#define DMA_SCHEDTBL_OFFS	0x3800
-+
-+#define USB_TX_EP_MASK		0xffff		/* EP0 + 15 Tx EPs */
-+#define USB_RX_EP_MASK		0xfffe		/* 15 Rx EPs */
-+
-+#define USB_TX_INTR_MASK	(USB_TX_EP_MASK << USB_INTR_TX_SHIFT)
-+#define USB_RX_INTR_MASK	(USB_RX_EP_MASK << USB_INTR_RX_SHIFT)
-+
-+#define A_WAIT_BCON_TIMEOUT	1100		/* in ms */
-+
-+#define USBSS_INTR_RX_STARV	0x00000001
-+#define USBSS_INTR_PD_CMPL	0x00000004
-+#define USBSS_INTR_TX_CMPL	0x00000500
-+#define USBSS_INTR_RX_CMPL	0x00000A00
-+#define USBSS_INTR_FLAGS	(USBSS_INTR_PD_CMPL | USBSS_INTR_TX_CMPL \
-+					| USBSS_INTR_RX_CMPL)
-+
-+#define	USBMODE_USBID_MUXSEL	0x80
-+#define	USBMODE_USBID_HIGH	0x100
-+
-+#define	USB0PORT_MODEMASK	0x0f
-+#define	USB1PORT_MODEMASK	0xf0
-+#define USB1PORT_MODESHIFT	4
-+extern void usb_nop_xceiv_register(int id);
-+#endif
-diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
-index ec14801..9dd16b9 100644
---- a/drivers/usb/musb/tusb6010.c
-+++ b/drivers/usb/musb/tusb6010.c
-@@ -40,11 +40,11 @@ static void tusb_musb_set_vbus(struct musb *musb, int is_on);
-  * Checks the revision. We need to use the DMA register as 3.0 does not
-  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
-  */
--u8 tusb_get_revision(struct musb *musb)
-+static u16 tusb_get_revision(struct musb *musb)
- {
- 	void __iomem	*tbase = musb->ctrl_base;
- 	u32		die_id;
--	u8		rev;
-+	u16		rev;
- 
- 	rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
- 	if (TUSB_REV_MAJOR(rev) == 3) {
-@@ -56,11 +56,12 @@ u8 tusb_get_revision(struct musb *musb)
- 
- 	return rev;
- }
-+EXPORT_SYMBOL_GPL(tusb_get_revision);
- 
- static int tusb_print_revision(struct musb *musb)
- {
- 	void __iomem	*tbase = musb->ctrl_base;
--	u8		rev;
-+	u16		rev;
- 
- 	rev = tusb_get_revision(musb);
- 
-@@ -171,7 +172,8 @@ static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
- 	}
- }
- 
--void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
-+static void tusb_musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
-+		const u8 *buf)
- {
- 	struct musb *musb = hw_ep->musb;
- 	void __iomem	*ep_conf = hw_ep->conf;
-@@ -221,7 +223,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
- 		tusb_fifo_write_unaligned(fifo, buf, len);
- }
- 
--void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
-+static void tusb_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
- {
- 	struct musb *musb = hw_ep->musb;
- 	void __iomem	*ep_conf = hw_ep->conf;
-@@ -854,7 +856,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
- 
- 		dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
- 		real_dma_src = ~real_dma_src & dma_src;
--		if (tusb_dma_omap() && real_dma_src) {
-+		if (tusb_dma_omap(musb) && real_dma_src) {
- 			int	tx_source = (real_dma_src & 0xffff);
- 			int	i;
- 
-@@ -1074,8 +1076,8 @@ static int tusb_musb_init(struct musb *musb)
- 	void __iomem		*sync = NULL;
- 	int			ret;
- 
--	usb_nop_xceiv_register();
--	musb->xceiv = otg_get_transceiver();
-+	usb_nop_xceiv_register(musb->id);
-+	musb->xceiv = otg_get_transceiver(musb->id);
- 	if (!musb->xceiv)
- 		return -ENODEV;
- 
-@@ -1128,7 +1130,7 @@ done:
- 			iounmap(sync);
- 
- 		otg_put_transceiver(musb->xceiv);
--		usb_nop_xceiv_unregister();
-+		usb_nop_xceiv_unregister(musb->id);
- 	}
- 	return ret;
- }
-@@ -1144,11 +1146,14 @@ static int tusb_musb_exit(struct musb *musb)
- 	iounmap(musb->sync_va);
- 
- 	otg_put_transceiver(musb->xceiv);
--	usb_nop_xceiv_unregister();
-+	usb_nop_xceiv_unregister(musb->id);
- 	return 0;
- }
- 
- static const struct musb_platform_ops tusb_ops = {
-+	.fifo_mode	= 4,
-+	.flags		= MUSB_GLUE_TUSB_STYLE |
-+				MUSB_GLUE_EP_ADDR_INDEXED_MAPPING,
- 	.init		= tusb_musb_init,
- 	.exit		= tusb_musb_exit,
- 
-@@ -1158,8 +1163,15 @@ static const struct musb_platform_ops tusb_ops = {
- 	.set_mode	= tusb_musb_set_mode,
- 	.try_idle	= tusb_musb_try_idle,
- 
-+	.get_hw_revision	= tusb_get_revision,
-+
- 	.vbus_status	= tusb_musb_vbus_status,
- 	.set_vbus	= tusb_musb_set_vbus,
-+	.read_fifo	= tusb_musb_read_fifo,
-+	.write_fifo	= tusb_musb_write_fifo,
-+
-+	.dma_controller_create = tusb_dma_controller_create,
-+	.dma_controller_destroy = tusb_dma_controller_destroy,
- };
- 
- static u64 tusb_dmamask = DMA_BIT_MASK(32);
-diff --git a/drivers/usb/musb/tusb6010.h b/drivers/usb/musb/tusb6010.h
-index 35c933a..72cdad2 100644
---- a/drivers/usb/musb/tusb6010.h
-+++ b/drivers/usb/musb/tusb6010.h
-@@ -12,20 +12,6 @@
- #ifndef __TUSB6010_H__
- #define __TUSB6010_H__
- 
--extern u8 tusb_get_revision(struct musb *musb);
--
--#ifdef CONFIG_USB_TUSB6010
--#define musb_in_tusb()			1
--#else
--#define musb_in_tusb()			0
--#endif
--
--#ifdef CONFIG_USB_TUSB_OMAP_DMA
--#define tusb_dma_omap()			1
--#else
--#define tusb_dma_omap()			0
--#endif
--
- /* VLYNQ control register. 32-bit at offset 0x000 */
- #define TUSB_VLYNQ_CTRL			0x004
- 
-diff --git a/drivers/usb/musb/tusb6010_omap.c b/drivers/usb/musb/tusb6010_omap.c
-index b67b4bc..4af0c2d 100644
---- a/drivers/usb/musb/tusb6010_omap.c
-+++ b/drivers/usb/musb/tusb6010_omap.c
-@@ -178,12 +178,12 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
- 			dma_unmap_single(dev, chdat->dma_addr,
- 						chdat->transfer_len,
- 						DMA_TO_DEVICE);
--			musb_write_fifo(hw_ep, pio, buf);
-+			musb->ops->write_fifo(hw_ep, pio, buf);
- 		} else {
- 			dma_unmap_single(dev, chdat->dma_addr,
- 						chdat->transfer_len,
- 						DMA_FROM_DEVICE);
--			musb_read_fifo(hw_ep, pio, buf);
-+			musb->ops->read_fifo(hw_ep, pio, buf);
- 		}
- 		channel->actual_len += pio;
- 	}
-@@ -211,7 +211,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
- 
- 		if (chdat->tx) {
- 			dev_dbg(musb->controller, "terminating short tx packet\n");
--			musb_ep_select(mbase, chdat->epnum);
-+			musb_ep_select(musb, mbase, chdat->epnum);
- 			csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
- 			csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
- 				| MUSB_TXCSR_P_WZC_BITS;
-@@ -386,14 +386,14 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
- 	 * Prepare MUSB for DMA transfer
- 	 */
- 	if (chdat->tx) {
--		musb_ep_select(mbase, chdat->epnum);
-+		musb_ep_select(musb, mbase, chdat->epnum);
- 		csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
- 		csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
- 			| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
- 		csr &= ~MUSB_TXCSR_P_UNDERRUN;
- 		musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
- 	} else {
--		musb_ep_select(mbase, chdat->epnum);
-+		musb_ep_select(musb, mbase, chdat->epnum);
- 		csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
- 		csr |= MUSB_RXCSR_DMAENAB;
- 		csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
-@@ -642,7 +642,7 @@ static void tusb_omap_dma_release(struct dma_channel *channel)
- 	channel = NULL;
- }
- 
--void dma_controller_destroy(struct dma_controller *c)
-+void tusb_dma_controller_destroy(struct dma_controller *c)
- {
- 	struct tusb_omap_dma	*tusb_dma;
- 	int			i;
-@@ -661,9 +661,10 @@ void dma_controller_destroy(struct dma_controller *c)
- 
- 	kfree(tusb_dma);
- }
-+EXPORT_SYMBOL(tusb_dma_controller_destroy);
- 
--struct dma_controller *__init
--dma_controller_create(struct musb *musb, void __iomem *base)
-+struct dma_controller *__devinit
-+tusb_dma_controller_create(struct musb *musb, void __iomem *base)
- {
- 	void __iomem		*tbase = musb->ctrl_base;
- 	struct tusb_omap_dma	*tusb_dma;
-@@ -697,7 +698,7 @@ dma_controller_create(struct musb *musb, void __iomem *base)
- 	tusb_dma->controller.channel_program = tusb_omap_dma_program;
- 	tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
- 
--	if (tusb_get_revision(musb) >= TUSB_REV_30)
-+	if (musb_platform_get_hw_revision(musb) >= TUSB_REV_30)
- 		tusb_dma->multichannel = 1;
- 
- 	for (i = 0; i < MAX_DMAREQ; i++) {
-@@ -721,7 +722,22 @@ dma_controller_create(struct musb *musb, void __iomem *base)
- 	return &tusb_dma->controller;
- 
- cleanup:
--	dma_controller_destroy(&tusb_dma->controller);
-+	tusb_dma_controller_destroy(&tusb_dma->controller);
- out:
- 	return NULL;
- }
-+EXPORT_SYMBOL(tusb_dma_controller_create);
-+
-+MODULE_DESCRIPTION("TUSB dma controller driver for musb");
-+MODULE_LICENSE("GPL v2");
-+
-+static int __init tusb_dma_init(void)
-+{
-+	return 0;
-+}
-+module_init(tusb_dma_init);
-+
-+static void __exit tusb_dma__exit(void)
-+{
-+}
-+module_exit(tusb_dma__exit);
-diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
-index f7e04bf..8209e23 100644
---- a/drivers/usb/musb/ux500.c
-+++ b/drivers/usb/musb/ux500.c
-@@ -54,6 +54,7 @@ static int ux500_musb_exit(struct musb *musb)
- }
- 
- static const struct musb_platform_ops ux500_ops = {
-+	.fifo_mode	= 5,
- 	.init		= ux500_musb_init,
- 	.exit		= ux500_musb_exit,
- };
-diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
-index ef4333f..a163632 100644
---- a/drivers/usb/musb/ux500_dma.c
-+++ b/drivers/usb/musb/ux500_dma.c
-@@ -37,7 +37,6 @@ struct ux500_dma_channel {
- 	struct dma_channel channel;
- 	struct ux500_dma_controller *controller;
- 	struct musb_hw_ep *hw_ep;
--	struct work_struct channel_work;
- 	struct dma_chan *dma_chan;
- 	unsigned int cur_len;
- 	dma_cookie_t cookie;
-@@ -56,31 +55,11 @@ struct ux500_dma_controller {
- 	dma_addr_t phy_base;
- };
- 
--/* Work function invoked from DMA callback to handle tx transfers. */
--static void ux500_tx_work(struct work_struct *data)
--{
--	struct ux500_dma_channel *ux500_channel = container_of(data,
--		struct ux500_dma_channel, channel_work);
--	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
--	struct musb *musb = hw_ep->musb;
--	unsigned long flags;
--
--	dev_dbg(musb->controller, "DMA tx transfer done on hw_ep=%d\n",
--		hw_ep->epnum);
--
--	spin_lock_irqsave(&musb->lock, flags);
--	ux500_channel->channel.actual_len = ux500_channel->cur_len;
--	ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
--	musb_dma_completion(musb, hw_ep->epnum,
--				ux500_channel->is_tx);
--	spin_unlock_irqrestore(&musb->lock, flags);
--}
--
- /* Work function invoked from DMA callback to handle rx transfers. */
--static void ux500_rx_work(struct work_struct *data)
-+void ux500_dma_callback(void *private_data)
- {
--	struct ux500_dma_channel *ux500_channel = container_of(data,
--		struct ux500_dma_channel, channel_work);
-+	struct dma_channel *channel = private_data;
-+	struct ux500_dma_channel *ux500_channel = channel->private_data;
- 	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
- 	struct musb *musb = hw_ep->musb;
- 	unsigned long flags;
-@@ -94,14 +73,7 @@ static void ux500_rx_work(struct work_struct *data)
- 	musb_dma_completion(musb, hw_ep->epnum,
- 		ux500_channel->is_tx);
- 	spin_unlock_irqrestore(&musb->lock, flags);
--}
--
--void ux500_dma_callback(void *private_data)
--{
--	struct dma_channel *channel = (struct dma_channel *)private_data;
--	struct ux500_dma_channel *ux500_channel = channel->private_data;
- 
--	schedule_work(&ux500_channel->channel_work);
- }
- 
- static bool ux500_configure_channel(struct dma_channel *channel,
-@@ -330,7 +302,6 @@ static int ux500_dma_controller_start(struct dma_controller *c)
- 	void **param_array;
- 	struct ux500_dma_channel *channel_array;
- 	u32 ch_count;
--	void (*musb_channel_work)(struct work_struct *);
- 	dma_cap_mask_t mask;
- 
- 	if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
-@@ -347,7 +318,6 @@ static int ux500_dma_controller_start(struct dma_controller *c)
- 	channel_array = controller->rx_channel;
- 	ch_count = data->num_rx_channels;
- 	param_array = data->dma_rx_param_array;
--	musb_channel_work = ux500_rx_work;
- 
- 	for (dir = 0; dir < 2; dir++) {
- 		for (ch_num = 0; ch_num < ch_count; ch_num++) {
-@@ -374,15 +344,12 @@ static int ux500_dma_controller_start(struct dma_controller *c)
- 				return -EBUSY;
- 			}
- 
--			INIT_WORK(&ux500_channel->channel_work,
--				musb_channel_work);
- 		}
- 
- 		/* Prepare the loop for TX channels */
- 		channel_array = controller->tx_channel;
- 		ch_count = data->num_tx_channels;
- 		param_array = data->dma_tx_param_array;
--		musb_channel_work = ux500_tx_work;
- 		is_tx = 1;
- 	}
- 
-diff --git a/drivers/usb/otg/nop-usb-xceiv.c b/drivers/usb/otg/nop-usb-xceiv.c
-index c1e3600..31b4fa3 100644
---- a/drivers/usb/otg/nop-usb-xceiv.c
-+++ b/drivers/usb/otg/nop-usb-xceiv.c
-@@ -37,24 +37,24 @@ struct nop_usb_xceiv {
- 	struct device		*dev;
- };
- 
--static struct platform_device *pd;
-+static struct platform_device *pd[2] = {NULL, NULL};
- 
--void usb_nop_xceiv_register(void)
-+void usb_nop_xceiv_register(int id)
- {
--	if (pd)
-+	if (pd[id])
- 		return;
--	pd = platform_device_register_simple("nop_usb_xceiv", -1, NULL, 0);
--	if (!pd) {
-+	pd[id] = platform_device_register_simple("nop_usb_xceiv", id, NULL, 0);
-+	if (!pd[id]) {
- 		printk(KERN_ERR "Unable to register usb nop transceiver\n");
- 		return;
- 	}
- }
- EXPORT_SYMBOL(usb_nop_xceiv_register);
- 
--void usb_nop_xceiv_unregister(void)
-+void usb_nop_xceiv_unregister(int id)
- {
--	platform_device_unregister(pd);
--	pd = NULL;
-+	platform_device_unregister(pd[id]);
-+	pd[id] = NULL;
- }
- EXPORT_SYMBOL(usb_nop_xceiv_unregister);
- 
-@@ -122,6 +122,7 @@ static int __devinit nop_usb_xceiv_probe(struct platform_device *pdev)
- 	nop->otg.set_host	= nop_set_host;
- 	nop->otg.set_peripheral	= nop_set_peripheral;
- 	nop->otg.set_suspend	= nop_set_suspend;
-+	nop->otg.id		= pdev->id;
- 
- 	err = otg_set_transceiver(&nop->otg);
- 	if (err) {
-@@ -144,7 +145,7 @@ static int __devexit nop_usb_xceiv_remove(struct platform_device *pdev)
- {
- 	struct nop_usb_xceiv *nop = platform_get_drvdata(pdev);
- 
--	otg_set_transceiver(NULL);
-+	otg_reset_transceiver(&nop->otg);
- 
- 	platform_set_drvdata(pdev, NULL);
- 	kfree(nop);
-diff --git a/drivers/usb/otg/otg.c b/drivers/usb/otg/otg.c
-index 307c27b..15eefbf 100644
---- a/drivers/usb/otg/otg.c
-+++ b/drivers/usb/otg/otg.c
-@@ -15,7 +15,7 @@
- 
- #include <linux/usb/otg.h>
- 
--static struct otg_transceiver *xceiv;
-+static struct otg_transceiver *xceiv[2];
- 
- /**
-  * otg_get_transceiver - find the (single) OTG transceiver
-@@ -26,11 +26,11 @@ static struct otg_transceiver *xceiv;
-  *
-  * For use by USB host and peripheral drivers.
-  */
--struct otg_transceiver *otg_get_transceiver(void)
-+struct otg_transceiver *otg_get_transceiver(int id)
- {
--	if (xceiv)
--		get_device(xceiv->dev);
--	return xceiv;
-+	if (xceiv[id])
-+		get_device(xceiv[id]->dev);
-+	return xceiv[id];
- }
- EXPORT_SYMBOL(otg_get_transceiver);
- 
-@@ -59,13 +59,30 @@ EXPORT_SYMBOL(otg_put_transceiver);
-  */
- int otg_set_transceiver(struct otg_transceiver *x)
- {
--	if (xceiv && x)
-+	if ( x && xceiv[x->id])
- 		return -EBUSY;
--	xceiv = x;
-+	xceiv[x->id] = x;
- 	return 0;
- }
- EXPORT_SYMBOL(otg_set_transceiver);
- 
-+
-+/**
-+ * otg_set_transceiver - declare the (single) OTG transceiver
-+ * @x: the USB OTG transceiver to be used; or NULL
-+ *
-+ * This call is exclusively for use by transceiver drivers, which
-+ * coordinate the activities of drivers for host and peripheral
-+ * controllers, and in some cases for VBUS current regulation.
-+ */
-+int otg_reset_transceiver(struct otg_transceiver *x)
-+{
-+	if (x && xceiv[x->id])
-+		xceiv[x->id] = NULL;
-+	return 0;
-+}
-+EXPORT_SYMBOL(otg_reset_transceiver);
-+
- const char *otg_state_string(enum usb_otg_state state)
- {
- 	switch (state) {
-diff --git a/drivers/usb/renesas_usbhs/mod_gadget.c b/drivers/usb/renesas_usbhs/mod_gadget.c
-index aa0d183..3906c42 100644
---- a/drivers/usb/renesas_usbhs/mod_gadget.c
-+++ b/drivers/usb/renesas_usbhs/mod_gadget.c
-@@ -755,7 +755,7 @@ static int usbhsg_gadget_start(struct usb_gadget *gadget,
- 
- 	if (!driver		||
- 	    !driver->setup	||
--	    driver->speed < USB_SPEED_FULL)
-+	    driver->max_speed < USB_SPEED_FULL)
- 		return -EINVAL;
- 
- 	/* first hook up the driver ... */
-@@ -816,11 +816,6 @@ static int usbhsg_stop(struct usbhs_priv *priv)
- 	return usbhsg_try_stop(priv, USBHSG_STATUS_STARTED);
- }
- 
--static void usbhs_mod_gadget_release(struct device *pdev)
--{
--	/* do nothing */
--}
--
- int usbhs_mod_gadget_probe(struct usbhs_priv *priv)
- {
- 	struct usbhsg_gpriv *gpriv;
-@@ -869,10 +864,9 @@ int usbhs_mod_gadget_probe(struct usbhs_priv *priv)
- 	 */
- 	dev_set_name(&gpriv->gadget.dev, "gadget");
- 	gpriv->gadget.dev.parent	= dev;
--	gpriv->gadget.dev.release	= usbhs_mod_gadget_release;
- 	gpriv->gadget.name		= "renesas_usbhs_udc";
- 	gpriv->gadget.ops		= &usbhsg_gadget_ops;
--	gpriv->gadget.is_dualspeed	= 1;
-+	gpriv->gadget.max_speed		= USB_SPEED_HIGH;
- 	ret = device_register(&gpriv->gadget.dev);
- 	if (ret < 0)
- 		goto err_add_udc;
-diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
-index d83e967..64754de 100644
---- a/drivers/video/Kconfig
-+++ b/drivers/video/Kconfig
-@@ -30,7 +30,7 @@ config VGASTATE
- config VIDEO_OUTPUT_CONTROL
- 	tristate "Lowlevel video output switch controls"
- 	help
--	  This framework adds support for low-level control of the video 
-+	  This framework adds support for low-level control of the video
- 	  output switch.
- 
- menuconfig FB
-@@ -691,7 +691,7 @@ config FB_STI
- 	  BIOS routines contained in a ROM chip in HP PA-RISC based machines.
- 	  Enabling this option will implement the linux framebuffer device
- 	  using calls to the STI BIOS routines for initialisation.
--	
-+
- 	  If you enable this option, you will get a planar framebuffer device
- 	  /dev/fb which will work on the most common HP graphic cards of the
- 	  NGLE family, including the artist chips (in the 7xx and Bxxx series),
-@@ -1132,36 +1132,36 @@ config FB_I810
- 	select FB_CFB_IMAGEBLIT
- 	select VGASTATE
- 	help
--	  This driver supports the on-board graphics built in to the Intel 810 
-+	  This driver supports the on-board graphics built in to the Intel 810
-           and 815 chipsets.  Say Y if you have and plan to use such a board.
- 
-           To compile this driver as a module, choose M here: the
- 	  module will be called i810fb.
- 
--          For more information, please read 
-+          For more information, please read
- 	  <file:Documentation/fb/intel810.txt>
- 
- config FB_I810_GTF
- 	bool "use VESA Generalized Timing Formula"
- 	depends on FB_I810
- 	help
--	  If you say Y, then the VESA standard, Generalized Timing Formula 
-+	  If you say Y, then the VESA standard, Generalized Timing Formula
-           or GTF, will be used to calculate the required video timing values
--	  per video mode.  Since the GTF allows nondiscrete timings 
-+	  per video mode.  Since the GTF allows nondiscrete timings
-           (nondiscrete being a range of values as opposed to discrete being a
--          set of values), you'll be able to use any combination of horizontal 
-+          set of values), you'll be able to use any combination of horizontal
- 	  and vertical resolutions, and vertical refresh rates without having
- 	  to specify your own timing parameters.  This is especially useful
--	  to maximize the performance of an aging display, or if you just 
--          have a display with nonstandard dimensions. A VESA compliant 
-+	  to maximize the performance of an aging display, or if you just
-+          have a display with nonstandard dimensions. A VESA compliant
- 	  monitor is recommended, but can still work with non-compliant ones.
--	  If you need or want this, then select this option. The timings may 
--	  not be compliant with Intel's recommended values. Use at your own 
-+	  If you need or want this, then select this option. The timings may
-+	  not be compliant with Intel's recommended values. Use at your own
- 	  risk.
- 
--          If you say N, the driver will revert to discrete video timings 
-+          If you say N, the driver will revert to discrete video timings
- 	  using a set recommended by Intel in their documentation.
--  
-+
-           If unsure, say N.
- 
- config FB_I810_I2C
-@@ -1279,10 +1279,10 @@ config FB_MATROX_G
- 	  G450/G550 secondary head and digital output are supported without
- 	  additional modules.
- 
--	  The driver starts in monitor mode. You must use the matroxset tool 
--	  (available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to 
--	  swap primary and secondary head outputs, or to change output mode.  
--	  Secondary head driver always start in 640x480 resolution and you 
-+	  The driver starts in monitor mode. You must use the matroxset tool
-+	  (available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
-+	  swap primary and secondary head outputs, or to change output mode.
-+	  Secondary head driver always start in 640x480 resolution and you
- 	  must use fbset to change it.
- 
- 	  Do not forget that second head supports only 16 and 32 bpp
-@@ -1365,7 +1365,7 @@ config FB_RADEON_I2C
- 	select FB_DDC
- 	default y
- 	help
--	  Say Y here if you want DDC/I2C support for your Radeon board. 
-+	  Say Y here if you want DDC/I2C support for your Radeon board.
- 
- config FB_RADEON_BACKLIGHT
- 	bool "Support for backlight control"
-@@ -1599,7 +1599,7 @@ config FB_NEOMAGIC
- 	select VGASTATE
- 	help
- 	  This driver supports notebooks with NeoMagic PCI chips.
--	  Say Y if you have such a graphics card. 
-+	  Say Y if you have such a graphics card.
- 
- 	  To compile this driver as a module, choose M here: the
- 	  module will be called neofb.
-@@ -1654,7 +1654,7 @@ config FB_VOODOO1
- 	select FB_CFB_COPYAREA
- 	select FB_CFB_IMAGEBLIT
- 	---help---
--	  Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or 
-+	  Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
- 	  Voodoo2 (cvg) based graphics card.
- 
- 	  To compile this driver as a module, choose M here: the
-@@ -2229,7 +2229,7 @@ config FB_SH7760
- 
- config FB_DA8XX
- 	tristate "DA8xx/OMAP-L1xx Framebuffer support"
--	depends on FB && ARCH_DAVINCI_DA8XX
-+	depends on FB && (ARCH_DAVINCI_DA8XX || SOC_OMAPAM33XX)
- 	select FB_CFB_FILLRECT
- 	select FB_CFB_COPYAREA
- 	select FB_CFB_IMAGEBLIT
-@@ -2238,6 +2238,17 @@ config FB_DA8XX
- 	  found on DA8xx/OMAP-L1xx SoCs.
- 	  If unsure, say N.
- 
-+config FB_DA8XX_CONSISTENT_DMA_SIZE
-+	int "Consistent DMA memory size (MB)"
-+	depends on (FB_DA8XX && MACH_AM335XEVM)
-+	range 1 14
-+	default 4
-+	help
-+	  Increase the DMA consistent memory size according to your video
-+	  memory needs, for example if you want to use multiple planes.
-+	  The size must be 2MB aligned.
-+	  If unsure say 1.
-+
- config FB_VIRTUAL
- 	tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
- 	depends on FB
-@@ -2409,6 +2420,17 @@ config FB_PUV3_UNIGFX
- 	  Choose this option if you want to use the Unigfx device as a
- 	  framebuffer device. Without the support of PCI & AGP.
- 
-+config FB_ST7735
-+	tristate "ST7735 framebuffer support"
-+	depends on FB && SPI
-+	select FB_SYS_FILLRECT
-+	select FB_SYS_COPYAREA
-+	select FB_SYS_IMAGEBLIT
-+	select FB_SYS_FOPS
-+	select FB_DEFERRED_IO
-+	help
-+	  Framebuffer support for the ST7735 display controller in SPI mode.
-+
- source "drivers/video/omap/Kconfig"
- source "drivers/video/omap2/Kconfig"
- 
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index 9b9d8ff..c6d9851 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -143,6 +143,7 @@ obj-$(CONFIG_FB_MSM)              += msm/
- obj-$(CONFIG_FB_NUC900)           += nuc900fb.o
- obj-$(CONFIG_FB_JZ4740)		  += jz4740_fb.o
- obj-$(CONFIG_FB_PUV3_UNIGFX)      += fb-puv3.o
-+obj-$(CONFIG_FB_ST7735)		  += st7735fb.o
- 
- # Platform or fallback drivers go here
- obj-$(CONFIG_FB_UVESA)            += uvesafb.o
-diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
-index 278aeaa..df9dac7 100644
---- a/drivers/video/backlight/Kconfig
-+++ b/drivers/video/backlight/Kconfig
-@@ -342,6 +342,14 @@ config BACKLIGHT_AAT2870
- 	  If you have a AnalogicTech AAT2870 say Y to enable the
- 	  backlight driver.
- 
-+config BACKLIGHT_TLC59108
-+	tristate "TLC59108 LCD Backlight Driver"
-+	depends on I2C && BACKLIGHT_CLASS_DEVICE
-+	default n
-+	help
-+	  If you have an LCD Panel with backlight control via TLC59108,
-+	  say Y to enable its LCD control driver.
-+
- endif # BACKLIGHT_CLASS_DEVICE
- 
- endif # BACKLIGHT_LCD_SUPPORT
-diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
-index fdd1fc4..ba31474 100644
---- a/drivers/video/backlight/Makefile
-+++ b/drivers/video/backlight/Makefile
-@@ -39,4 +39,5 @@ obj-$(CONFIG_BACKLIGHT_ADP8870)	+= adp8870_bl.o
- obj-$(CONFIG_BACKLIGHT_88PM860X) += 88pm860x_bl.o
- obj-$(CONFIG_BACKLIGHT_PCF50633)	+= pcf50633-backlight.o
- obj-$(CONFIG_BACKLIGHT_AAT2870) += aat2870_bl.o
-+obj-$(CONFIG_BACKLIGHT_TLC59108)	+= tlc59108.o
- 
-diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
-index 8b5b2a4..48092b4 100644
---- a/drivers/video/backlight/pwm_bl.c
-+++ b/drivers/video/backlight/pwm_bl.c
-@@ -17,7 +17,7 @@
- #include <linux/fb.h>
- #include <linux/backlight.h>
- #include <linux/err.h>
--#include <linux/pwm.h>
-+#include <linux/pwm/pwm.h>
- #include <linux/pwm_backlight.h>
- #include <linux/slab.h>
- 
-@@ -49,13 +49,14 @@ static int pwm_backlight_update_status(struct backlight_device *bl)
- 		brightness = pb->notify(pb->dev, brightness);
- 
- 	if (brightness == 0) {
--		pwm_config(pb->pwm, 0, pb->period);
--		pwm_disable(pb->pwm);
-+		pwm_set_duty_ns(pb->pwm, 0);
-+		pwm_stop(pb->pwm);
- 	} else {
- 		brightness = pb->lth_brightness +
- 			(brightness * (pb->period - pb->lth_brightness) / max);
--		pwm_config(pb->pwm, brightness, pb->period);
--		pwm_enable(pb->pwm);
-+		pwm_set_period_ns(pb->pwm, pb->period);
-+		pwm_set_duty_ns(pb->pwm, brightness);
-+		pwm_start(pb->pwm);
- 	}
- 
- 	if (pb->notify_after)
-@@ -117,7 +118,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
- 		(data->pwm_period_ns / data->max_brightness);
- 	pb->dev = &pdev->dev;
- 
--	pb->pwm = pwm_request(data->pwm_id, "backlight");
-+	pb->pwm = pwm_request(data->pwm_id, data->ch, "backlight");
- 	if (IS_ERR(pb->pwm)) {
- 		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
- 		ret = PTR_ERR(pb->pwm);
-@@ -143,7 +144,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
- 	return 0;
- 
- err_bl:
--	pwm_free(pb->pwm);
-+	pwm_release(pb->pwm);
- err_pwm:
- 	kfree(pb);
- err_alloc:
-@@ -159,9 +160,9 @@ static int pwm_backlight_remove(struct platform_device *pdev)
- 	struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
- 
- 	backlight_device_unregister(bl);
--	pwm_config(pb->pwm, 0, pb->period);
--	pwm_disable(pb->pwm);
--	pwm_free(pb->pwm);
-+	pwm_set_duty_ns(pb->pwm, 0);
-+	pwm_stop(pb->pwm);
-+	pwm_release(pb->pwm);
- 	kfree(pb);
- 	if (data->exit)
- 		data->exit(&pdev->dev);
-@@ -177,10 +178,8 @@ static int pwm_backlight_suspend(struct platform_device *pdev,
- 
- 	if (pb->notify)
- 		pb->notify(pb->dev, 0);
--	pwm_config(pb->pwm, 0, pb->period);
--	pwm_disable(pb->pwm);
--	if (pb->notify_after)
--		pb->notify_after(pb->dev, 0);
-+	pwm_set_duty_ns(pb->pwm, 0);
-+	pwm_stop(pb->pwm);
- 	return 0;
- }
- 
-diff --git a/drivers/video/backlight/tlc59108.c b/drivers/video/backlight/tlc59108.c
-new file mode 100755
-index 0000000..d7e9a4f
---- /dev/null
-+++ b/drivers/video/backlight/tlc59108.c
-@@ -0,0 +1,170 @@
-+/*
-+ * ti81xxhdmi_tlc59108.c
-+ *
-+ * Copyright (C) 2011 Texas Instruments
-+ * Author: Senthil Natarajan
-+ *
-+ * tlc59108 HDMI Driver
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program.  If not, see <http://www.gnu.org/licenses/>.
-+ * History:
-+ *
-+ * Senthil Natarajan<senthil.n@ti.com> July 2011 I2C driver for tlc59108
-+ *						 backlight control
-+ */
-+
-+#include <linux/i2c.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/backlight.h>
-+#include <linux/fb.h>
-+
-+#define tlc59108_MODULE_NAME	"tlc59108"
-+#define TLC59108_MODE1   0x00
-+#define TLC59108_PWM2    0x04
-+#define TLC59108_LEDOUT0 0x0c
-+#define TLC59108_LEDOUT1 0x0d
-+#define TLC59108_MAX_BRIGHTNESS 0xFF
-+
-+struct tlc59108_bl {
-+	struct i2c_client *client;
-+	struct backlight_device *bl;
-+};
-+
-+static void tlc59108_bl_set_backlight(struct tlc59108_bl *data, int brightness)
-+{
-+	/* Set Mode1 Register */
-+	i2c_smbus_write_byte_data(data->client, TLC59108_MODE1, 0x00);
-+
-+	/* Set LEDOUT0 Register */
-+	i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT0, 0x21);
-+
-+	/* Set Backlight Duty Cycle*/
-+	i2c_smbus_write_byte_data(data->client, TLC59108_PWM2,
-+				  brightness & 0xff);
-+}
-+
-+static int tlc59108_bl_get_brightness(struct backlight_device *dev)
-+{
-+	struct backlight_properties *props = &dev->props;
-+
-+	return props->brightness;
-+}
-+
-+static int tlc59108_bl_update_status(struct backlight_device *dev)
-+{
-+	struct backlight_properties *props = &dev->props;
-+	struct tlc59108_bl *data = dev_get_drvdata(&dev->dev);
-+	int brightness = props->brightness;
-+
-+	tlc59108_bl_set_backlight(data, brightness);
-+
-+	return 0;
-+}
-+
-+static const struct backlight_ops bl_ops = {
-+	.get_brightness		= tlc59108_bl_get_brightness,
-+	.update_status		= tlc59108_bl_update_status,
-+};
-+
-+static int tlc59108_probe(struct i2c_client *c, const struct i2c_device_id *id)
-+{
-+	struct backlight_properties props;
-+	struct tlc59108_bl *data = kzalloc(sizeof(struct tlc59108_bl),
-+					   GFP_KERNEL);
-+	int ret = 0;
-+
-+	if (!data)
-+		return -ENOMEM;
-+
-+	i2c_set_clientdata(c, data);
-+	data->client = c;
-+
-+	/* FIXME: This is definitely how it should be done.
-+	 * Someone more familiar with the framework needs to make it proper
-+	 */
-+	if (cpu_is_am335x()) {
-+		/* Set LED4 to always on in LEDOUT1 Register*/
-+		ret = i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT1, 0x01);
-+		if(ret < 0)
-+			pr_err("Could not set LED4 to fully on\n");
-+	}
-+
-+	memset(&props, 0, sizeof(struct backlight_properties));
-+	props.max_brightness = TLC59108_MAX_BRIGHTNESS;
-+	props.type = BACKLIGHT_RAW;
-+	data->bl = backlight_device_register("tlc59108-bl", &c->dev, data,
-+					     &bl_ops, &props);
-+	if (IS_ERR(data->bl)) {
-+		ret = PTR_ERR(data->bl);
-+		goto err_reg;
-+	}
-+
-+	data->bl->props.brightness = TLC59108_MAX_BRIGHTNESS;
-+
-+	backlight_update_status(data->bl);
-+
-+	return 0;
-+
-+err_reg:
-+	data->bl = NULL;
-+	kfree(data);
-+	return ret;
-+}
-+
-+static int tlc59108_remove(struct i2c_client *c)
-+{
-+	struct tlc59108_bl *data = i2c_get_clientdata(c);
-+
-+	backlight_device_unregister(data->bl);
-+	data->bl = NULL;
-+
-+	kfree(data);
-+
-+	return 0;
-+}
-+
-+/* I2C Device ID table */
-+static const struct i2c_device_id tlc59108_id[] = {
-+	{ "tlc59108", 0 },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(i2c, tlc59108_id);
-+
-+/* I2C driver data */
-+static struct i2c_driver tlc59108_driver = {
-+	.driver = {
-+		.owner = THIS_MODULE,
-+		.name = tlc59108_MODULE_NAME,
-+	},
-+	.probe = tlc59108_probe,
-+	.remove = tlc59108_remove,
-+	.id_table = tlc59108_id,
-+};
-+
-+static int __init tlc59108_init(void)
-+{
-+	return i2c_add_driver(&tlc59108_driver);
-+}
-+
-+static void __exit tlc59108_exit(void)
-+{
-+	i2c_del_driver(&tlc59108_driver);
-+}
-+
-+module_init(tlc59108_init);
-+module_exit(tlc59108_exit);
-+
-+MODULE_DESCRIPTION("LCD/Backlight control for TLC59108");
-+MODULE_AUTHOR("Senthil Natarajan <senthil.n@ti.com>");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c
-index 56720fb..46b03f5 100644
---- a/drivers/video/bf54x-lq043fb.c
-+++ b/drivers/video/bf54x-lq043fb.c
-@@ -4,7 +4,7 @@
-  * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
-  *
-  * Created:
-- * Description:  ADSP-BF54x Framebufer driver
-+ * Description:  ADSP-BF54x Framebuffer driver
-  *
-  *
-  * Modified:
-diff --git a/drivers/video/bfin-t350mcqb-fb.c b/drivers/video/bfin-t350mcqb-fb.c
-index d5e1267..7a0c05f 100644
---- a/drivers/video/bfin-t350mcqb-fb.c
-+++ b/drivers/video/bfin-t350mcqb-fb.c
-@@ -4,7 +4,7 @@
-  * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
-  *
-  * Created:
-- * Description:  Blackfin LCD Framebufer driver
-+ * Description:  Blackfin LCD Framebuffer driver
-  *
-  *
-  * Modified:
-diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
-index 29577bf..86b19ac 100644
---- a/drivers/video/da8xx-fb.c
-+++ b/drivers/video/da8xx-fb.c
-@@ -30,8 +30,12 @@
- #include <linux/clk.h>
- #include <linux/cpufreq.h>
- #include <linux/console.h>
-+#include <linux/spinlock.h>
- #include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/pm_runtime.h>
- #include <video/da8xx-fb.h>
-+#include <asm/mach-types.h>
- 
- #define DRIVER_NAME "da8xx_lcdc"
- 
-@@ -82,6 +86,8 @@
- #define LCD_V2_LIDD_CLK_EN		BIT(1)
- #define LCD_V2_CORE_CLK_EN		BIT(0)
- #define LCD_V2_LPP_B10			26
-+#define LCD_V2_TFT_24BPP_MODE		BIT(25)
-+#define LCD_V2_TFT_24BPP_UNPACK		BIT(26)
- 
- /* LCD Raster Timing 2 Register */
- #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
-@@ -126,6 +132,8 @@
- #define RIGHT_MARGIN	64
- #define UPPER_MARGIN	32
- #define LOWER_MARGIN	32
-+#define WAIT_FOR_FRAME_DONE	true
-+#define NO_WAIT_FOR_FRAME_DONE	false
- 
- static resource_size_t da8xx_fb_reg_base;
- static struct resource *lcdc_regs;
-@@ -134,15 +142,16 @@ static irq_handler_t lcdc_irq_handler;
- 
- static inline unsigned int lcdc_read(unsigned int addr)
- {
--	return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
-+	return (unsigned int)readl(da8xx_fb_reg_base + (addr));
- }
- 
- static inline void lcdc_write(unsigned int val, unsigned int addr)
- {
--	__raw_writel(val, da8xx_fb_reg_base + (addr));
-+	writel(val, da8xx_fb_reg_base + (addr));
- }
- 
- struct da8xx_fb_par {
-+	struct device *dev;
- 	resource_size_t p_palette_base;
- 	unsigned char *v_palette_base;
- 	dma_addr_t		vram_phys;
-@@ -152,15 +161,23 @@ struct da8xx_fb_par {
- 	unsigned int		dma_end;
- 	struct clk *lcdc_clk;
- 	int irq;
--	unsigned short pseudo_palette[16];
-+	unsigned long pseudo_palette[32];
- 	unsigned int palette_sz;
- 	unsigned int pxl_clk;
- 	int blank;
- 	wait_queue_head_t	vsync_wait;
- 	int			vsync_flag;
- 	int			vsync_timeout;
-+	spinlock_t		lock_for_chan_update;
-+
-+	/*
-+	 * LCDC has 2 ping pong DMA channels, channel 0
-+	 * and channel 1.
-+	 */
-+	unsigned int		which_dma_channel_done;
- #ifdef CONFIG_CPU_FREQ
- 	struct notifier_block	freq_transition;
-+	unsigned int		lcd_fck_rate;
- #endif
- 	void (*panel_power_ctrl)(int);
- };
-@@ -174,7 +191,7 @@ static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
- 	.activate = 0,
- 	.height = -1,
- 	.width = -1,
--	.pixclock = 46666,	/* 46us - AUO display */
-+	.pixclock = 33333,/*Pico Sec*/
- 	.accel_flags = 0,
- 	.left_margin = LEFT_MARGIN,
- 	.right_margin = RIGHT_MARGIN,
-@@ -209,6 +226,9 @@ struct da8xx_panel {
- 	unsigned char	invert_pxl_clk;	/* Invert Pixel clock */
- };
- 
-+static vsync_callback_t vsync_cb_handler;
-+static void *vsync_cb_arg;
-+
- static struct da8xx_panel known_lcd_panels[] = {
- 	/* Sharp LCD035Q3DG01 */
- 	[0] = {
-@@ -232,12 +252,54 @@ static struct da8xx_panel known_lcd_panels[] = {
- 		.hfp = 2,
- 		.hbp = 2,
- 		.hsw = 41,
--		.vfp = 2,
--		.vbp = 2,
-+		.vfp = 3,
-+		.vbp = 3,
- 		.vsw = 10,
- 		.pxl_clk = 7833600,
- 		.invert_pxl_clk = 0,
- 	},
-+	/* ThreeFive S9700RTWV35TR */
-+	[2] = {
-+		.name = "TFC_S9700RTWV35TR_01B",
-+		.width = 800,
-+		.height = 480,
-+		.hfp = 39,
-+		.hbp = 39,
-+		.hsw = 47,
-+		.vfp = 13,
-+		.vbp = 29,
-+		.vsw = 2,
-+		.pxl_clk = 30000000,
-+		.invert_pxl_clk = 0,
-+	},
-+	[3] = {
-+		 /* 1024 x 768 @ 60 Hz  Reduced blanking VESA CVT 0.79M3-R */ 
-+		.name = "1024x768@60",
-+		.width = 1024,
-+		.height = 768,
-+		.hfp = 48,
-+		.hbp = 80,
-+		.hsw = 32,
-+		.vfp = 3,
-+		.vbp = 15,
-+		.vsw = 4,
-+		.pxl_clk = 56000000,
-+		.invert_pxl_clk = 0,
-+	},
-+	[4] = {
-+		 /* CDTech S035Q01 */ 
-+		.name = "CDTech_S035Q01",
-+		.width = 320,
-+		.height = 240,
-+		.hfp = 58,
-+		.hbp = 21,
-+		.hsw = 47,
-+		.vfp = 23,
-+		.vbp = 11,
-+		.vsw = 2,
-+		.pxl_clk = 8000000,
-+		.invert_pxl_clk = 0,
-+	},	
- };
- 
- /* Enable the Raster Engine of the LCD Controller */
-@@ -245,27 +307,58 @@ static inline void lcd_enable_raster(void)
- {
- 	u32 reg;
- 
-+	/* Put LCDC in reset for several cycles */
-+	if (lcd_revision == LCD_VERSION_2)
-+		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
-+
-+	mdelay(1);
-+
- 	/* Bring LCDC out of reset */
- 	if (lcd_revision == LCD_VERSION_2)
- 		lcdc_write(0, LCD_CLK_RESET_REG);
- 
-+	mdelay(1);
-+
-+	/* Above reset sequence doesnot reset register context */
- 	reg = lcdc_read(LCD_RASTER_CTRL_REG);
- 	if (!(reg & LCD_RASTER_ENABLE))
- 		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
- }
- 
- /* Disable the Raster Engine of the LCD Controller */
--static inline void lcd_disable_raster(void)
-+static inline void lcd_disable_raster(bool wait_for_frame_done)
- {
- 	u32 reg;
-+	u32 loop_cnt = 0;
-+	u32 stat;
-+	u32 i = 0;
-+
-+	if (wait_for_frame_done)
-+		loop_cnt = 5000;
- 
- 	reg = lcdc_read(LCD_RASTER_CTRL_REG);
- 	if (reg & LCD_RASTER_ENABLE)
- 		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
- 
--	if (lcd_revision == LCD_VERSION_2)
--		/* Write 1 to reset LCDC */
--		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
-+	/* Wait for the current frame to complete */
-+	do {
-+		if (lcd_revision == LCD_VERSION_1)
-+			stat = lcdc_read(LCD_STAT_REG);
-+		else
-+			stat = lcdc_read(LCD_RAW_STAT_REG);
-+
-+		mdelay(1);
-+	} while (!(stat & BIT(0)) && (i++ < loop_cnt));
-+
-+	if (lcd_revision == LCD_VERSION_1)
-+		lcdc_write(stat, LCD_STAT_REG);
-+	else
-+		lcdc_write(stat, LCD_MASKED_STAT_REG);
-+
-+	if ((loop_cnt != 0) && (i >= loop_cnt)) {
-+		printk(KERN_ERR "LCD Controller timed out\n");
-+		return;
-+	}
- }
- 
- static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
-@@ -292,7 +385,8 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
- 		} else {
- 			reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
- 				LCD_V2_END_OF_FRAME0_INT_ENA |
--				LCD_V2_END_OF_FRAME1_INT_ENA;
-+				LCD_V2_END_OF_FRAME1_INT_ENA |
-+				LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
- 			lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
- 		}
- 		reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
-@@ -329,8 +423,8 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
- 	lcd_enable_raster();
- }
- 
--/* Configure the Burst Size of DMA */
--static int lcd_cfg_dma(int burst_size)
-+/* Configure the Burst Size and fifo threhold of DMA */
-+static int lcd_cfg_dma(int burst_size,  int fifo_th)
- {
- 	u32 reg;
- 
-@@ -354,6 +448,9 @@ static int lcd_cfg_dma(int burst_size)
- 	default:
- 		return -EINVAL;
- 	}
-+
-+	reg |= (fifo_th << 8);
-+
- 	lcdc_write(reg, LCD_DMA_CTRL_REG);
- 
- 	return 0;
-@@ -510,6 +607,13 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
- 	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
- 	if (raster_order)
- 		reg |= LCD_RASTER_ORDER;
-+
-+	if (bpp == 24)
-+		reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
-+	else if (bpp == 32)
-+		reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
-+				| LCD_V2_TFT_24BPP_UNPACK);
-+
- 	lcdc_write(reg, LCD_RASTER_CTRL_REG);
- 
- 	switch (bpp) {
-@@ -517,6 +621,8 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
- 	case 2:
- 	case 4:
- 	case 16:
-+	case 24:
-+	case 32:
- 		par->palette_sz = 16 * 2;
- 		break;
- 
-@@ -575,6 +681,23 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
- 			update_hw = 1;
- 			palette[0] = 0x4000;
- 		}
-+	} else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
-+		    ((info->var.bits_per_pixel == 24) && regno < 24)) {
-+		red >>= (24 - info->var.red.length);
-+		red <<= info->var.red.offset;
-+
-+		green >>= (24 - info->var.green.length);
-+		green <<= info->var.green.offset;
-+
-+		blue >>= (24 - info->var.blue.length);
-+		blue <<= info->var.blue.offset;
-+
-+		par->pseudo_palette[regno] = red | green | blue;
-+
-+		if (palette[0] != 0x4000) {
-+			update_hw = 1;
-+			palette[0] = 0x4000;
-+		}
- 	}
- 
- 	/* Update the palette in the h/w as needed. */
-@@ -587,7 +710,7 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
- static void lcd_reset(struct da8xx_fb_par *par)
- {
- 	/* Disable the Raster if previously Enabled */
--	lcd_disable_raster();
-+	lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
- 
- 	/* DMA has to be disabled */
- 	lcdc_write(0, LCD_DMA_CTRL_REG);
-@@ -636,8 +759,8 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
- 		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
- 			~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
- 
--	/* Configure the DMA burst size. */
--	ret = lcd_cfg_dma(cfg->dma_burst_sz);
-+	/* Configure the DMA burst size and fifo threshold. */
-+	ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
- 	if (ret < 0)
- 		return ret;
- 
-@@ -653,7 +776,9 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
- 	if (ret < 0)
- 		return ret;
- 
--	if (QVGA != cfg->p_disp_panel->panel_type)
-+
-+	if ((QVGA != cfg->p_disp_panel->panel_type) &&
-+			(WVGA != cfg->p_disp_panel->panel_type))
- 		return -EINVAL;
- 
- 	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
-@@ -676,6 +801,32 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
- 	return 0;
- }
- 
-+int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
-+{
-+	if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
-+		vsync_cb_handler = handler;
-+		vsync_cb_arg = arg;
-+	} else {
-+		return -EEXIST;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(register_vsync_cb);
-+
-+int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
-+{
-+	if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
-+		vsync_cb_handler = NULL;
-+		vsync_cb_arg = NULL;
-+	} else {
-+		return -ENXIO;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(unregister_vsync_cb);
-+
- /* IRQ handler for version 2 of LCDC */
- static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
- {
-@@ -684,7 +835,8 @@ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
- 	u32 reg_int;
- 
- 	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
--		lcd_disable_raster();
-+		printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
-+		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
- 		lcdc_write(stat, LCD_MASKED_STAT_REG);
- 		lcd_enable_raster();
- 	} else if (stat & LCD_PL_LOAD_DONE) {
-@@ -694,7 +846,7 @@ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
- 		 * interrupt via the following write to the status register. If
- 		 * this is done after then one gets multiple PL done interrupts.
- 		 */
--		lcd_disable_raster();
-+		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
- 
- 		lcdc_write(stat, LCD_MASKED_STAT_REG);
- 
-@@ -709,21 +861,27 @@ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
- 		lcdc_write(stat, LCD_MASKED_STAT_REG);
- 
- 		if (stat & LCD_END_OF_FRAME0) {
-+			par->which_dma_channel_done = 0;
- 			lcdc_write(par->dma_start,
- 				   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
- 			lcdc_write(par->dma_end,
- 				   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
- 			par->vsync_flag = 1;
- 			wake_up_interruptible(&par->vsync_wait);
-+			if (vsync_cb_handler)
-+				vsync_cb_handler(vsync_cb_arg);
- 		}
- 
- 		if (stat & LCD_END_OF_FRAME1) {
-+			par->which_dma_channel_done = 1;
- 			lcdc_write(par->dma_start,
- 				   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
- 			lcdc_write(par->dma_end,
- 				   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- 			par->vsync_flag = 1;
- 			wake_up_interruptible(&par->vsync_wait);
-+			if (vsync_cb_handler)
-+				vsync_cb_handler(vsync_cb_arg);
- 		}
- 	}
- 
-@@ -739,9 +897,12 @@ static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
- 	u32 reg_ras;
- 
- 	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
--		lcd_disable_raster();
-+		printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
-+		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
-+		clk_disable(par->lcdc_clk);
- 		lcdc_write(stat, LCD_STAT_REG);
- 		lcd_enable_raster();
-+		clk_enable(par->lcdc_clk);
- 	} else if (stat & LCD_PL_LOAD_DONE) {
- 		/*
- 		 * Must disable raster before changing state of any control bit.
-@@ -749,7 +910,7 @@ static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
- 		 * interrupt via the following write to the status register. If
- 		 * this is done after then one gets multiple PL done interrupts.
- 		 */
--		lcd_disable_raster();
-+		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
- 
- 		lcdc_write(stat, LCD_STAT_REG);
- 
-@@ -822,6 +983,24 @@ static int fb_check_var(struct fb_var_screeninfo *var,
- 		var->transp.offset = 0;
- 		var->transp.length = 0;
- 		break;
-+	case 24:
-+		var->red.offset = 16;
-+		var->red.length = 8;
-+		var->green.offset = 8;
-+		var->green.length = 8;
-+		var->blue.offset = 0;
-+		var->blue.length = 8;
-+		break;
-+	case 32:
-+		var->transp.offset = 24;
-+		var->transp.length = 8;
-+		var->red.offset = 16;
-+		var->red.length = 8;
-+		var->green.offset = 8;
-+		var->green.length = 8;
-+		var->blue.offset = 0;
-+		var->blue.length = 8;
-+		break;
- 	default:
- 		err = -EINVAL;
- 	}
-@@ -840,11 +1019,12 @@ static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
- 	struct da8xx_fb_par *par;
- 
- 	par = container_of(nb, struct da8xx_fb_par, freq_transition);
--	if (val == CPUFREQ_PRECHANGE) {
--		lcd_disable_raster();
--	} else if (val == CPUFREQ_POSTCHANGE) {
--		lcd_calc_clk_divider(par);
--		lcd_enable_raster();
-+	if (val == CPUFREQ_POSTCHANGE) {
-+		if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
-+			lcd_disable_raster(WAIT_FOR_FRAME_DONE);
-+			lcd_calc_clk_divider(par);
-+			lcd_enable_raster();
-+		}
- 	}
- 
- 	return 0;
-@@ -878,7 +1058,7 @@ static int __devexit fb_remove(struct platform_device *dev)
- 		if (par->panel_power_ctrl)
- 			par->panel_power_ctrl(0);
- 
--		lcd_disable_raster();
-+		lcd_disable_raster(WAIT_FOR_FRAME_DONE);
- 		lcdc_write(0, LCD_RASTER_CTRL_REG);
- 
- 		/* disable DMA  */
-@@ -891,8 +1071,8 @@ static int __devexit fb_remove(struct platform_device *dev)
- 		dma_free_coherent(NULL, par->vram_size, par->vram_virt,
- 				  par->vram_phys);
- 		free_irq(par->irq, par);
--		clk_disable(par->lcdc_clk);
--		clk_put(par->lcdc_clk);
-+		pm_runtime_put_sync(&dev->dev);
-+		pm_runtime_disable(&dev->dev);
- 		framebuffer_release(info);
- 		iounmap((void __iomem *)da8xx_fb_reg_base);
- 		release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
-@@ -931,6 +1111,14 @@ static int fb_wait_for_vsync(struct fb_info *info)
- 	if (ret == 0)
- 		return -ETIMEDOUT;
- 
-+	if (par->panel_power_ctrl) {
-+		/* Switch off panel power and backlight */
-+		par->panel_power_ctrl(0);
-+
-+		/* Switch on panel power and backlight */
-+		par->panel_power_ctrl(1);
-+	}
-+
- 	return 0;
- }
- 
-@@ -991,7 +1179,7 @@ static int cfb_blank(int blank, struct fb_info *info)
- 		if (par->panel_power_ctrl)
- 			par->panel_power_ctrl(0);
- 
--		lcd_disable_raster();
-+		lcd_disable_raster(WAIT_FOR_FRAME_DONE);
- 		break;
- 	default:
- 		ret = -EINVAL;
-@@ -1013,6 +1201,7 @@ static int da8xx_pan_display(struct fb_var_screeninfo *var,
- 	struct fb_fix_screeninfo    *fix = &fbi->fix;
- 	unsigned int end;
- 	unsigned int start;
-+	unsigned long irq_flags;
- 
- 	if (var->xoffset != fbi->var.xoffset ||
- 			var->yoffset != fbi->var.yoffset) {
-@@ -1030,6 +1219,21 @@ static int da8xx_pan_display(struct fb_var_screeninfo *var,
- 			end	= start + fbi->var.yres * fix->line_length - 1;
- 			par->dma_start	= start;
- 			par->dma_end	= end;
-+			spin_lock_irqsave(&par->lock_for_chan_update,
-+					irq_flags);
-+			if (par->which_dma_channel_done == 0) {
-+				lcdc_write(par->dma_start,
-+					   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
-+				lcdc_write(par->dma_end,
-+					   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
-+			} else if (par->which_dma_channel_done == 1) {
-+				lcdc_write(par->dma_start,
-+					   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
-+				lcdc_write(par->dma_end,
-+					   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
-+			}
-+			spin_unlock_irqrestore(&par->lock_for_chan_update,
-+					irq_flags);
- 		}
- 	}
- 
-@@ -1090,9 +1294,11 @@ static int __devinit fb_probe(struct platform_device *device)
- 		ret = -ENODEV;
- 		goto err_ioremap;
- 	}
--	ret = clk_enable(fb_clk);
--	if (ret)
--		goto err_clk_put;
-+
-+	pm_runtime_irq_safe(&device->dev);
-+	pm_runtime_enable(&device->dev);
-+	pm_runtime_get_sync(&device->dev);
-+
- 
- 	/* Determine LCD IP Version */
- 	switch (lcdc_read(LCD_PID_REG)) {
-@@ -1100,6 +1306,7 @@ static int __devinit fb_probe(struct platform_device *device)
- 		lcd_revision = LCD_VERSION_1;
- 		break;
- 	case 0x4F200800:
-+	case 0x4F201000:
- 		lcd_revision = LCD_VERSION_2;
- 		break;
- 	default:
-@@ -1120,7 +1327,7 @@ static int __devinit fb_probe(struct platform_device *device)
- 	if (i == ARRAY_SIZE(known_lcd_panels)) {
- 		dev_err(&device->dev, "GLCD: No valid panel found\n");
- 		ret = -ENODEV;
--		goto err_clk_disable;
-+		goto err_pm_runtime_disable;
- 	} else
- 		dev_info(&device->dev, "GLCD: Found %s panel\n",
- 					fb_pdata->type);
-@@ -1132,11 +1339,15 @@ static int __devinit fb_probe(struct platform_device *device)
- 	if (!da8xx_fb_info) {
- 		dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
- 		ret = -ENOMEM;
--		goto err_clk_disable;
-+		goto err_pm_runtime_disable;
- 	}
- 
- 	par = da8xx_fb_info->par;
-+	par->dev = &device->dev;
- 	par->lcdc_clk = fb_clk;
-+#ifdef CONFIG_CPU_FREQ
-+	par->lcd_fck_rate = clk_get_rate(fb_clk);
-+#endif
- 	par->pxl_clk = lcdc_info->pxl_clk;
- 	if (fb_pdata->panel_power_ctrl) {
- 		par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
-@@ -1210,6 +1421,11 @@ static int __devinit fb_probe(struct platform_device *device)
- 	da8xx_fb_var.hsync_len = lcdc_info->hsw;
- 	da8xx_fb_var.vsync_len = lcdc_info->vsw;
- 
-+	da8xx_fb_var.right_margin = lcdc_info->hfp;
-+	da8xx_fb_var.left_margin  = lcdc_info->hbp;
-+	da8xx_fb_var.lower_margin = lcdc_info->vfp;
-+	da8xx_fb_var.upper_margin = lcdc_info->vbp;
-+
- 	/* Initialize fbinfo */
- 	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
- 	da8xx_fb_info->fix = da8xx_fb_fix;
-@@ -1233,6 +1449,8 @@ static int __devinit fb_probe(struct platform_device *device)
- 	/* initialize the vsync wait queue */
- 	init_waitqueue_head(&par->vsync_wait);
- 	par->vsync_timeout = HZ / 5;
-+	par->which_dma_channel_done = -1;
-+	spin_lock_init(&par->lock_for_chan_update);
- 
- 	/* Register the Frame Buffer  */
- 	if (register_framebuffer(da8xx_fb_info) < 0) {
-@@ -1264,8 +1482,8 @@ static int __devinit fb_probe(struct platform_device *device)
- irq_freq:
- #ifdef CONFIG_CPU_FREQ
- 	lcd_da8xx_cpufreq_deregister(par);
--#endif
- err_cpu_freq:
-+#endif
- 	unregister_framebuffer(da8xx_fb_info);
- 
- err_dealloc_cmap:
-@@ -1281,13 +1499,12 @@ err_release_fb_mem:
- err_release_fb:
- 	framebuffer_release(da8xx_fb_info);
- 
--err_clk_disable:
--	clk_disable(fb_clk);
--
--err_clk_put:
--	clk_put(fb_clk);
-+err_pm_runtime_disable:
-+	pm_runtime_put_sync(&device->dev);
-+	pm_runtime_disable(&device->dev);
- 
- err_ioremap:
-+
- 	iounmap((void __iomem *)da8xx_fb_reg_base);
- 
- err_request_mem:
-@@ -1297,6 +1514,64 @@ err_request_mem:
- }
- 
- #ifdef CONFIG_PM
-+
-+struct lcdc_context {
-+	u32 clk_enable;
-+	u32 ctrl;
-+	u32 dma_ctrl;
-+	u32 raster_timing_0;
-+	u32 raster_timing_1;
-+	u32 raster_timing_2;
-+	u32 int_enable_set;
-+	u32 dma_frm_buf_base_addr_0;
-+	u32 dma_frm_buf_ceiling_addr_0;
-+	u32 dma_frm_buf_base_addr_1;
-+	u32 dma_frm_buf_ceiling_addr_1;
-+	u32 raster_ctrl;
-+} reg_context;
-+
-+static void lcd_context_save(void)
-+{
-+	reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
-+	reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
-+	reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
-+	reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
-+	reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
-+	reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
-+	reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
-+	reg_context.dma_frm_buf_base_addr_0 =
-+		lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
-+	reg_context.dma_frm_buf_ceiling_addr_0 =
-+		lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
-+	reg_context.dma_frm_buf_base_addr_1 =
-+		lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
-+	reg_context.dma_frm_buf_ceiling_addr_1 =
-+		lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
-+	reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
-+	return;
-+}
-+
-+static void lcd_context_restore(void)
-+{
-+	lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
-+	lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
-+	lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
-+	lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
-+	lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
-+	lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
-+	lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
-+	lcdc_write(reg_context.dma_frm_buf_base_addr_0,
-+			LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
-+	lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
-+			LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
-+	lcdc_write(reg_context.dma_frm_buf_base_addr_1,
-+			LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
-+	lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
-+			LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
-+	lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
-+	return;
-+}
-+
- static int fb_suspend(struct platform_device *dev, pm_message_t state)
- {
- 	struct fb_info *info = platform_get_drvdata(dev);
-@@ -1307,8 +1582,10 @@ static int fb_suspend(struct platform_device *dev, pm_message_t state)
- 		par->panel_power_ctrl(0);
- 
- 	fb_set_suspend(info, 1);
--	lcd_disable_raster();
--	clk_disable(par->lcdc_clk);
-+	lcd_disable_raster(WAIT_FOR_FRAME_DONE);
-+	lcd_context_save();
-+
-+	pm_runtime_put(&dev->dev);
- 	console_unlock();
- 
- 	return 0;
-@@ -1319,11 +1596,16 @@ static int fb_resume(struct platform_device *dev)
- 	struct da8xx_fb_par *par = info->par;
- 
- 	console_lock();
-+
-+	pm_runtime_get_sync(&dev->dev);
-+
-+	msleep(1);
-+	lcd_context_restore();
-+	lcd_enable_raster();
-+
- 	if (par->panel_power_ctrl)
- 		par->panel_power_ctrl(1);
- 
--	clk_enable(par->lcdc_clk);
--	lcd_enable_raster();
- 	fb_set_suspend(info, 0);
- 	console_unlock();
- 
-diff --git a/drivers/video/st7735fb.c b/drivers/video/st7735fb.c
-new file mode 100644
-index 0000000..500cc88
---- /dev/null
-+++ b/drivers/video/st7735fb.c
-@@ -0,0 +1,516 @@
-+/*
-+ * linux/drivers/video/st7735fb.c -- FB driver for ST7735 LCD controller
-+ * Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
-+ *
-+ * Copyright (C) 2011, Matt Porter
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive for
-+ * more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/mm.h>
-+#include <linux/vmalloc.h>
-+#include <linux/slab.h>
-+#include <linux/init.h>
-+#include <linux/fb.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+#include <linux/uaccess.h>
-+
-+#include <video/st7735fb.h>
-+
-+static struct st7735_function st7735_cfg_script[] = {
-+	{ ST7735_START, ST7735_START},
-+	{ ST7735_CMD, ST7735_SWRESET},
-+	{ ST7735_DELAY, 150},
-+	{ ST7735_CMD, ST7735_SLPOUT},
-+	{ ST7735_DELAY, 500},
-+	{ ST7735_CMD, ST7735_FRMCTR1},
-+	{ ST7735_DATA, 0x01},
-+	{ ST7735_DATA, 0x2c},
-+	{ ST7735_DATA, 0x2d},
-+	{ ST7735_CMD, ST7735_FRMCTR2},
-+	{ ST7735_DATA, 0x01},
-+	{ ST7735_DATA, 0x2c},
-+	{ ST7735_DATA, 0x2d},
-+	{ ST7735_CMD, ST7735_FRMCTR3},
-+	{ ST7735_DATA, 0x01},
-+	{ ST7735_DATA, 0x2c},
-+	{ ST7735_DATA, 0x2d},
-+	{ ST7735_DATA, 0x01},
-+	{ ST7735_DATA, 0x2c},
-+	{ ST7735_DATA, 0x2d},
-+	{ ST7735_CMD, ST7735_INVCTR},
-+	{ ST7735_DATA, 0x07},
-+	{ ST7735_CMD, ST7735_PWCTR1},
-+	{ ST7735_DATA, 0xa2},
-+	{ ST7735_DATA, 0x02},
-+	{ ST7735_DATA, 0x84},
-+	{ ST7735_CMD, ST7735_PWCTR2},
-+	{ ST7735_DATA, 0xc5},
-+	{ ST7735_CMD, ST7735_PWCTR3},
-+	{ ST7735_DATA, 0x0a},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_CMD, ST7735_PWCTR4},
-+	{ ST7735_DATA, 0x8a},
-+	{ ST7735_DATA, 0x2a},
-+	{ ST7735_CMD, ST7735_PWCTR5},
-+	{ ST7735_DATA, 0x8a},
-+	{ ST7735_DATA, 0xee},
-+	{ ST7735_CMD, ST7735_VMCTR1},
-+	{ ST7735_DATA, 0x0e},
-+	{ ST7735_CMD, ST7735_INVOFF},
-+	{ ST7735_CMD, ST7735_MADCTL},
-+	{ ST7735_DATA, 0xc8},
-+	{ ST7735_CMD, ST7735_COLMOD},
-+	{ ST7735_DATA, 0x05},
-+	{ ST7735_CMD, ST7735_CASET},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x7f},
-+	{ ST7735_CMD, ST7735_RASET},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x9f},
-+	{ ST7735_CMD, ST7735_GMCTRP1},
-+	{ ST7735_DATA, 0x02},
-+	{ ST7735_DATA, 0x1c},
-+	{ ST7735_DATA, 0x07},
-+	{ ST7735_DATA, 0x12},
-+	{ ST7735_DATA, 0x37},
-+	{ ST7735_DATA, 0x32},
-+	{ ST7735_DATA, 0x29},
-+	{ ST7735_DATA, 0x2d},
-+	{ ST7735_DATA, 0x29},
-+	{ ST7735_DATA, 0x25},
-+	{ ST7735_DATA, 0x2b},
-+	{ ST7735_DATA, 0x39},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x01},
-+	{ ST7735_DATA, 0x03},
-+	{ ST7735_DATA, 0x10},
-+	{ ST7735_CMD, ST7735_GMCTRN1},
-+	{ ST7735_DATA, 0x03},
-+	{ ST7735_DATA, 0x1d},
-+	{ ST7735_DATA, 0x07},
-+	{ ST7735_DATA, 0x06},
-+	{ ST7735_DATA, 0x2e},
-+	{ ST7735_DATA, 0x2c},
-+	{ ST7735_DATA, 0x29},
-+	{ ST7735_DATA, 0x2d},
-+	{ ST7735_DATA, 0x2e},
-+	{ ST7735_DATA, 0x2e},
-+	{ ST7735_DATA, 0x37},
-+	{ ST7735_DATA, 0x3f},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x00},
-+	{ ST7735_DATA, 0x02},
-+	{ ST7735_DATA, 0x10},
-+	{ ST7735_CMD, ST7735_DISPON},
-+	{ ST7735_DELAY, 100},
-+	{ ST7735_CMD, ST7735_NORON},
-+	{ ST7735_DELAY, 10},
-+	{ ST7735_END, ST7735_END},
-+};
-+
-+static struct fb_fix_screeninfo st7735fb_fix __devinitdata = {
-+	.id =		"ST7735", 
-+	.type =		FB_TYPE_PACKED_PIXELS,
-+	.visual =	FB_VISUAL_PSEUDOCOLOR,
-+	.xpanstep =	0,
-+	.ypanstep =	0,
-+	.ywrapstep =	0, 
-+	.line_length =	WIDTH*BPP/8,
-+	.accel =	FB_ACCEL_NONE,
-+};
-+
-+static struct fb_var_screeninfo st7735fb_var __devinitdata = {
-+	.xres =			WIDTH,
-+	.yres =			HEIGHT,
-+	.xres_virtual =		WIDTH,
-+	.yres_virtual =		HEIGHT,
-+	.bits_per_pixel =	BPP,
-+	.nonstd	=		1,
-+};
-+
-+static int st7735_write(struct st7735fb_par *par, u8 data)
-+{
-+	u8 txbuf[2]; /* allocation from stack must go */
-+
-+	txbuf[0] = data;
-+
-+	return spi_write(par->spi, &txbuf[0], 1);
-+}
-+
-+static void st7735_write_data(struct st7735fb_par *par, u8 data)
-+{
-+	int ret = 0;
-+
-+	/* Set data mode */
-+	gpio_set_value(par->dc, 1);
-+
-+	ret = st7735_write(par, data);
-+	if (ret < 0)
-+		pr_err("%s: write data %02x failed with status %d\n",
-+			par->info->fix.id, data, ret);
-+}
-+
-+static int st7735_write_data_buf(struct st7735fb_par *par,
-+					u8 *txbuf, int size)
-+{
-+	/* Set data mode */
-+	gpio_set_value(par->dc, 1);
-+
-+	/* Write entire buffer */
-+	return spi_write(par->spi, txbuf, size);
-+}
-+
-+static void st7735_write_cmd(struct st7735fb_par *par, u8 data)
-+{
-+	int ret = 0;
-+
-+	/* Set command mode */
-+	gpio_set_value(par->dc, 0);
-+
-+	ret = st7735_write(par, data);
-+	if (ret < 0)
-+		pr_err("%s: write command %02x failed with status %d\n",
-+			par->info->fix.id, data, ret);
-+}
-+
-+static void st7735_run_cfg_script(struct st7735fb_par *par)
-+{
-+	int i = 0;
-+	int end_script = 0;
-+
-+	do {
-+		switch (st7735_cfg_script[i].cmd)
-+		{
-+		case ST7735_START:
-+			break;
-+		case ST7735_CMD:
-+			st7735_write_cmd(par,
-+				st7735_cfg_script[i].data & 0xff);
-+			break;
-+		case ST7735_DATA:
-+			st7735_write_data(par,
-+				st7735_cfg_script[i].data & 0xff);
-+			break;
-+		case ST7735_DELAY:
-+			mdelay(st7735_cfg_script[i].data);
-+			break;
-+		case ST7735_END:
-+			end_script = 1;
-+		}
-+		i++;
-+	} while (!end_script);
-+}
-+
-+static void st7735_set_addr_win(struct st7735fb_par *par,
-+				int xs, int ys, int xe, int ye)
-+{
-+	st7735_write_cmd(par, ST7735_CASET);
-+	st7735_write_data(par, 0x00);
-+	st7735_write_data(par, xs+2);
-+	st7735_write_data(par, 0x00);
-+	st7735_write_data(par, xe+2);
-+	st7735_write_cmd(par, ST7735_RASET);
-+	st7735_write_data(par, 0x00);
-+	st7735_write_data(par, ys+1);
-+	st7735_write_data(par, 0x00);
-+	st7735_write_data(par, ye+1);
-+}
-+
-+static void st7735_reset(struct st7735fb_par *par)
-+{
-+	/* Reset controller */
-+	gpio_set_value(par->rst, 0);
-+	udelay(10);
-+	gpio_set_value(par->rst, 1);
-+	mdelay(120);
-+}
-+
-+static void st7735fb_update_display(struct st7735fb_par *par)
-+{
-+	int ret = 0;
-+	u8 *vmem = par->info->screen_base;
-+
-+	/*
-+		TODO:
-+		Allow a subset of pages to be passed in
-+		(for deferred I/O).  Check pages against
-+		pan display settings to see if they
-+		should be updated.
-+	*/
-+	/* For now, just write the full 40KiB on each update */
-+
-+	/* Set row/column data window */
-+	st7735_set_addr_win(par, 0, 0, WIDTH-1, HEIGHT-1);
-+
-+	/* Internal RAM write command */
-+	st7735_write_cmd(par, ST7735_RAMWR);
-+
-+	/* Blast framebuffer to ST7735 internal display RAM */
-+	ret = st7735_write_data_buf(par, vmem, WIDTH*HEIGHT*BPP/8);
-+	if (ret < 0)
-+		pr_err("%s: spi_write failed to update display buffer\n",
-+			par->info->fix.id);
-+}
-+
-+static void st7735fb_deferred_io(struct fb_info *info,
-+				struct list_head *pagelist)
-+{
-+	st7735fb_update_display(info->par);
-+}
-+
-+static int st7735fb_init_display(struct st7735fb_par *par)
-+{
-+	/* TODO: Need some error checking on gpios */
-+
-+        /* Request GPIOs and initialize to default values */
-+        gpio_request_one(par->rst, GPIOF_OUT_INIT_HIGH,
-+			"ST7735 Reset Pin");
-+        gpio_request_one(par->dc, GPIOF_OUT_INIT_LOW,
-+			"ST7735 Data/Command Pin");
-+
-+	st7735_reset(par);
-+
-+	st7735_run_cfg_script(par);
-+
-+	return 0;
-+}
-+
-+void st7735fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
-+{
-+	struct st7735fb_par *par = info->par;
-+
-+	sys_fillrect(info, rect);
-+
-+	st7735fb_update_display(par);
-+}
-+
-+void st7735fb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 
-+{
-+	struct st7735fb_par *par = info->par;
-+
-+	sys_copyarea(info, area);
-+
-+	st7735fb_update_display(par);
-+}
-+
-+void st7735fb_imageblit(struct fb_info *info, const struct fb_image *image) 
-+{
-+	struct st7735fb_par *par = info->par;
-+
-+	sys_imageblit(info, image);
-+
-+	st7735fb_update_display(par);
-+}
-+
-+static ssize_t st7735fb_write(struct fb_info *info, const char __user *buf,
-+		size_t count, loff_t *ppos)
-+{
-+	struct st7735fb_par *par = info->par;
-+	unsigned long p = *ppos;
-+	void *dst;
-+	int err = 0;
-+	unsigned long total_size;
-+
-+	if (info->state != FBINFO_STATE_RUNNING)
-+		return -EPERM;
-+
-+	total_size = info->fix.smem_len;
-+
-+	if (p > total_size)
-+		return -EFBIG;
-+
-+	if (count > total_size) {
-+		err = -EFBIG;
-+		count = total_size;
-+	}
-+
-+	if (count + p > total_size) {
-+		if (!err)
-+			err = -ENOSPC;
-+
-+		count = total_size - p;
-+	}
-+
-+	dst = (void __force *) (info->screen_base + p);
-+
-+	if (copy_from_user(dst, buf, count))
-+		err = -EFAULT;
-+
-+	if  (!err)
-+		*ppos += count;
-+
-+	st7735fb_update_display(par);
-+
-+	return (err) ? err : count;
-+}
-+
-+static struct fb_ops st7735fb_ops = {
-+	.owner		= THIS_MODULE,
-+	.fb_read	= fb_sys_read,
-+	.fb_write	= st7735fb_write,
-+	.fb_fillrect	= st7735fb_fillrect,
-+	.fb_copyarea	= st7735fb_copyarea,
-+	.fb_imageblit	= st7735fb_imageblit,
-+};
-+
-+static struct fb_deferred_io st7735fb_defio = {
-+	.delay		= HZ,
-+	.deferred_io	= st7735fb_deferred_io,
-+};
-+
-+static int __devinit st7735fb_probe (struct spi_device *spi)
-+{
-+	int chip = spi_get_device_id(spi)->driver_data;
-+	struct st7735fb_platform_data *pdata = spi->dev.platform_data;
-+	int vmem_size = WIDTH*HEIGHT*BPP/8;
-+	u8 *vmem;
-+	struct fb_info *info;
-+	struct st7735fb_par *par;
-+	int retval = -ENOMEM;
-+
-+	if (chip != ST7735_DISPLAY_AF_TFT18) {
-+		pr_err("%s: only the %s device is supported\n", DRVNAME,
-+			to_spi_driver(spi->dev.driver)->id_table->name);
-+		return -EINVAL;
-+	}
-+
-+	if (!pdata) {
-+		pr_err("%s: platform data required for rst and dc info\n",
-+			DRVNAME);
-+		return -EINVAL;
-+	}
-+
-+	vmem = vzalloc(vmem_size);
-+	if (!vmem)
-+		return retval;
-+
-+	info = framebuffer_alloc(sizeof(struct st7735fb_par), &spi->dev);
-+	if (!info)
-+		goto fballoc_fail;
-+
-+	info->screen_base = (u8 __force __iomem *)vmem;
-+	info->fbops = &st7735fb_ops;
-+	info->fix = st7735fb_fix;
-+	info->fix.smem_len = vmem_size;
-+	info->var = st7735fb_var;
-+	/* Choose any packed pixel format as long as it's RGB565 */
-+	info->var.red.offset = 11;
-+	info->var.red.length = 5;
-+	info->var.green.offset = 5;
-+	info->var.green.length = 6;
-+	info->var.blue.offset = 0;
-+	info->var.blue.length = 5;
-+	info->var.transp.offset = 0;
-+	info->var.transp.length = 0;
-+	info->flags = FBINFO_FLAG_DEFAULT |
-+#ifdef __LITTLE_ENDIAN
-+			FBINFO_FOREIGN_ENDIAN |
-+#endif
-+			FBINFO_VIRTFB;
-+
-+	info->fbdefio = &st7735fb_defio;
-+	fb_deferred_io_init(info);
-+
-+	par = info->par;
-+	par->info = info;
-+	par->spi = spi;
-+	par->rst = pdata->rst_gpio;
-+	par->dc = pdata->dc_gpio;
-+
-+	retval = register_framebuffer(info);
-+	if (retval < 0)
-+		goto fbreg_fail;
-+
-+	spi_set_drvdata(spi, info);
-+
-+	retval = st7735fb_init_display(par);
-+	if (retval < 0)
-+		goto init_fail;
-+
-+	printk(KERN_INFO
-+		"fb%d: %s frame buffer device,\n\tusing %d KiB of video memory\n",
-+		info->node, info->fix.id, vmem_size);
-+
-+	return 0;
-+
-+
-+	/* TODO: release gpios on fail */
-+init_fail:
-+	spi_set_drvdata(spi, NULL);
-+
-+fbreg_fail:
-+	framebuffer_release(info);
-+
-+fballoc_fail:
-+	vfree(vmem);
-+
-+	return retval;
-+}
-+
-+static int __devexit st7735fb_remove(struct spi_device *spi)
-+{
-+	struct fb_info *info = spi_get_drvdata(spi);
-+
-+	spi_set_drvdata(spi, NULL);
-+
-+	if (info) {
-+		unregister_framebuffer(info);
-+		vfree(info->screen_base);	
-+		framebuffer_release(info);
-+	}
-+
-+	/* TODO: release gpios */
-+
-+	return 0;
-+}
-+
-+static const struct spi_device_id st7735fb_ids[] = {
-+	{ "adafruit_tft18", ST7735_DISPLAY_AF_TFT18 },
-+	{ },
-+};
-+
-+MODULE_DEVICE_TABLE(spi, st7735fb_ids);
-+
-+static struct spi_driver st7735fb_driver = {
-+	.driver = {
-+		.name   = "st7735fb",
-+		.owner  = THIS_MODULE,
-+	},
-+	.id_table = st7735fb_ids,
-+	.probe  = st7735fb_probe,
-+	.remove = __devexit_p(st7735fb_remove),
-+};
-+
-+static int __init st7735fb_init(void)
-+{
-+	return spi_register_driver(&st7735fb_driver);
-+}
-+
-+static void __exit st7735fb_exit(void)
-+{
-+	spi_unregister_driver(&st7735fb_driver);
-+}
-+
-+/* ------------------------------------------------------------------------- */
-+
-+module_init(st7735fb_init);
-+module_exit(st7735fb_exit);
-+
-+MODULE_DESCRIPTION("FB driver for ST7735 display controller");
-+MODULE_AUTHOR("Matt Porter");
-+MODULE_LICENSE("GPL");
-diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c
-index 3ce7613..d0dc109 100644
---- a/fs/ext4/inode.c
-+++ b/fs/ext4/inode.c
-@@ -1881,7 +1881,7 @@ static void ext4_end_io_buffer_write(struct buffer_head *bh, int uptodate);
-  * a[0] = 'a';
-  * truncate(f, 4096);
-  * we have in the page first buffer_head mapped via page_mkwrite call back
-- * but other bufer_heads would be unmapped but dirty(dirty done via the
-+ * but other buffer_heads would be unmapped but dirty (dirty done via the
-  * do_wp_page). So writepage should write the first block. If we modify
-  * the mmap area beyond 1024 we will again get a page_fault and the
-  * page_mkwrite callback will do the block allocation and mark the
-diff --git a/fs/jbd/checkpoint.c b/fs/jbd/checkpoint.c
-index 5c93ffc..05f0754 100644
---- a/fs/jbd/checkpoint.c
-+++ b/fs/jbd/checkpoint.c
-@@ -554,7 +554,7 @@ int cleanup_journal_tail(journal_t *journal)
-  * them.
-  *
-  * Called with j_list_lock held.
-- * Returns number of bufers reaped (for debug)
-+ * Returns number of buffers reaped (for debug)
-  */
- 
- static int journal_clean_one_cp_list(struct journal_head *jh, int *released)
-diff --git a/fs/jbd2/checkpoint.c b/fs/jbd2/checkpoint.c
-index 16a698b..d49d202 100644
---- a/fs/jbd2/checkpoint.c
-+++ b/fs/jbd2/checkpoint.c
-@@ -565,7 +565,7 @@ int jbd2_cleanup_journal_tail(journal_t *journal)
-  *
-  * Called with the journal locked.
-  * Called with j_list_lock held.
-- * Returns number of bufers reaped (for debug)
-+ * Returns number of buffers reaped (for debug)
-  */
- 
- static int journal_clean_one_cp_list(struct journal_head *jh, int *released)
-diff --git a/fs/xfs/xfs_buf.c b/fs/xfs/xfs_buf.c
-index cf0ac05..33e06d2 100644
---- a/fs/xfs/xfs_buf.c
-+++ b/fs/xfs/xfs_buf.c
-@@ -1370,7 +1370,7 @@ restart:
- 			goto restart;
- 		}
- 		/*
--		 * clear the LRU reference count so the bufer doesn't get
-+		 * clear the LRU reference count so the buffer doesn't get
- 		 * ignored in xfs_buf_rele().
- 		 */
- 		atomic_set(&bp->b_lru_ref, 0);
-diff --git a/include/linux/can/platform/d_can.h b/include/linux/can/platform/d_can.h
-new file mode 100644
-index 0000000..fe9df47
---- /dev/null
-+++ b/include/linux/can/platform/d_can.h
-@@ -0,0 +1,40 @@
-+/*
-+ * D_CAN controller driver platform header
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
-+ * Bosch D_CAN user manual can be obtained from:
-+ * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
-+ * d_can_users_manual_111.pdf
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __CAN_PLATFORM_TI_D_CAN_H__
-+#define __CAN_PLATFORM_TI_D_CAN_H__
-+
-+/**
-+ * struct d_can_platform_data - DCAN Platform Data
-+ *
-+ * @num_of_msg_objs:	Number of message objects
-+ * @dma_support:	DMA support is required/not
-+ * @ram_init:		DCAN RAM initialization
-+ *
-+ * Platform data structure to get all platform specific settings.
-+ * this structure also accounts the fact that the IP may have different
-+ * RAM and mailbox offsets for different SOC's
-+ */
-+struct d_can_platform_data {
-+	u32 num_of_msg_objs;
-+	bool dma_support;
-+	void (*ram_init) (unsigned int, unsigned int);
-+};
-+#endif
-diff --git a/include/linux/cpsw.h b/include/linux/cpsw.h
-new file mode 100644
-index 0000000..f1bb9d3
---- /dev/null
-+++ b/include/linux/cpsw.h
-@@ -0,0 +1,54 @@
-+#ifndef __CPSW_H__
-+#define __CPSW_H__
-+
-+#include <linux/if_ether.h>
-+
-+enum {
-+	CPSW_VERSION_1 = 0,    /* TI8148 */
-+	CPSW_VERSION_2,        /* AM33XX */
-+};
-+
-+struct cpsw_slave_data {
-+	u32		slave_reg_ofs;
-+	u32		sliver_reg_ofs;
-+	const char	*phy_id;
-+	int		phy_if;
-+	u8	mac_addr[ETH_ALEN];
-+};
-+
-+struct cpsw_platform_data {
-+	u32	ss_reg_ofs;	/* Subsystem control register offset */
-+	int	channels;	/* number of cpdma channels (symmetric) */
-+	u32	cpdma_reg_ofs;	/* cpdma register offset */
-+
-+	int	slaves;		/* number of slave cpgmac ports */
-+	struct cpsw_slave_data	*slave_data;
-+
-+	u32	ale_reg_ofs;	/* address lookup engine reg offset */
-+	int	ale_entries;	/* ale table size */
-+
-+	u32	host_port_reg_ofs; /* cpsw cpdma host port registers */
-+
-+	u32	hw_stats_reg_ofs;  /* cpsw hardware statistics counters */
-+
-+	u32	bd_ram_ofs;   /* embedded buffer descriptor RAM offset*/
-+	u32	bd_ram_size;  /*buffer descriptor ram size */
-+	u32	hw_ram_addr; /*if the HW address for BD RAM is different */
-+
-+	u8	mac_addr[ETH_ALEN];
-+
-+	int	rx_descs;
-+
-+	void	(*phy_control)(bool enabled);
-+
-+	u32	mac_control;
-+
-+	u32	gigabit_en; /* Is gigabit capable AND enabled */
-+	u32	rmii_en; /* Is RMII mode capable AND enabled */
-+	u32	host_port_num; /* The port number for the host port */
-+
-+	bool	no_bd_ram; /* no embedded BD ram*/
-+	u8	version;
-+};
-+
-+#endif /* __CPSW_H__ */
-diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
-index 92a0dc7..fd38249 100644
---- a/include/linux/i2c-omap.h
-+++ b/include/linux/i2c-omap.h
-@@ -35,6 +35,7 @@ struct omap_i2c_bus_platform_data {
- 	u32		rev;
- 	u32		flags;
- 	void		(*set_mpu_wkup_lat)(struct device *dev, long set);
-+	int		(*device_reset) (struct device *dev);
- };
- 
- #endif
-diff --git a/include/linux/input/ti_tscadc.h b/include/linux/input/ti_tscadc.h
-new file mode 100644
-index 0000000..fc239c6
---- /dev/null
-+++ b/include/linux/input/ti_tscadc.h
-@@ -0,0 +1,26 @@
-+/**
-+ * struct tsc_data	Touchscreen wire configuration
-+ * @wires:		Wires refer to application modes
-+ *			i.e. 4/5/8 wire touchscreen support
-+ *			on the platform
-+ * @analog_input:	Analog inputs refer to the order in which the
-+ *			connections are made to the AFE. If the connections
-+ *			are as : XPUL = AN0,XNUR = AN1,YPLL = AN2,
-+ *			YNLR = AN3, then this variable is set to 1.
-+ *			Else if the connections are as :
-+ *			XPUL = AN0,YPLL = AN1,XNUR = AN2,
-+ *			YNLR = AN3, then set this variable to
-+ *			0.
-+ * @x_plate_resistance:	X plate resistance.
-+ */
-+#include <linux/device.h>
-+
-+#define TI_TSCADC_TSCMODE 0
-+#define TI_TSCADC_GENMODE 1
-+
-+struct tsc_data {
-+	int wires;
-+	int analog_input;
-+	int x_plate_resistance;
-+	int mode;
-+};
-diff --git a/include/linux/lis3lv02d.h b/include/linux/lis3lv02d.h
-index f1664c6..32d4912 100644
---- a/include/linux/lis3lv02d.h
-+++ b/include/linux/lis3lv02d.h
-@@ -25,6 +25,7 @@
-  * @axis_x:		Sensor orientation remapping for x-axis
-  * @axis_y:		Sensor orientation remapping for y-axis
-  * @axis_z:		Sensor orientation remapping for z-axis
-+ * @g_range:		Value contains the acceleration range, +/-2, +/-4 and +/-8
-  * @driver_features:	Enable bits for different features. Disabled by default
-  * @default_rate:	Default sampling rate. 0 means reset default
-  * @setup_resources:	Interrupt line setup call back function
-@@ -113,6 +114,7 @@ struct lis3lv02d_platform_data {
- 	s8 axis_x;
- 	s8 axis_y;
- 	s8 axis_z;
-+	u8 g_range;
- #define LIS3_USE_BLOCK_READ	0x02
- 	u16 driver_features;
- 	int default_rate;
-diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
-new file mode 100644
-index 0000000..e030ef9
---- /dev/null
-+++ b/include/linux/mfd/tps65217.h
-@@ -0,0 +1,283 @@
-+/*
-+ * linux/mfd/tps65217.h
-+ *
-+ * Functions to access TPS65217 power management chip.
-+ *
-+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __LINUX_MFD_TPS65217_H
-+#define __LINUX_MFD_TPS65217_H
-+
-+#include <linux/i2c.h>
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/machine.h>
-+
-+/* I2C ID for TPS65217 part */
-+#define TPS65217_I2C_ID			0x24
-+
-+/* All register addresses */
-+#define TPS65217_REG_CHIPID		0X00
-+#define TPS65217_REG_PPATH		0X01
-+#define TPS65217_REG_INT		0X02
-+#define TPS65217_REG_CHGCONFIG0		0X03
-+#define TPS65217_REG_CHGCONFIG1		0X04
-+#define TPS65217_REG_CHGCONFIG2		0X05
-+#define TPS65217_REG_CHGCONFIG3		0X06
-+#define TPS65217_REG_WLEDCTRL1		0X07
-+#define TPS65217_REG_WLEDCTRL2		0X08
-+#define TPS65217_REG_MUXCTRL		0X09
-+#define TPS65217_REG_STATUS		0X0A
-+#define TPS65217_REG_PASSWORD		0X0B
-+#define TPS65217_REG_PGOOD		0X0C
-+#define TPS65217_REG_DEFPG		0X0D
-+#define TPS65217_REG_DEFDCDC1		0X0E
-+#define TPS65217_REG_DEFDCDC2		0X0F
-+#define TPS65217_REG_DEFDCDC3		0X10
-+#define TPS65217_REG_DEFSLEW		0X11
-+#define TPS65217_REG_DEFLDO1		0X12
-+#define TPS65217_REG_DEFLDO2		0X13
-+#define TPS65217_REG_DEFLS1		0X14
-+#define TPS65217_REG_DEFLS2		0X15
-+#define TPS65217_REG_ENABLE		0X16
-+#define TPS65217_REG_DEFUVLO		0X18
-+#define TPS65217_REG_SEQ1		0X19
-+#define TPS65217_REG_SEQ2		0X1A
-+#define TPS65217_REG_SEQ3		0X1B
-+#define TPS65217_REG_SEQ4		0X1C
-+#define TPS65217_REG_SEQ5		0X1D
-+#define TPS65217_REG_SEQ6		0X1E
-+
-+/* Register field definitions */
-+#define TPS65217_CHIPID_CHIP_MASK	0xF0
-+#define TPS65217_CHIPID_REV_MASK	0x0F
-+
-+#define TPS65217_PPATH_ACSINK_ENABLE	BIT(7)
-+#define TPS65217_PPATH_USBSINK_ENABLE	BIT(6)
-+#define TPS65217_PPATH_AC_PW_ENABLE	BIT(5)
-+#define TPS65217_PPATH_USB_PW_ENABLE	BIT(4)
-+#define TPS65217_PPATH_AC_CURRENT_MASK	0x0C
-+#define TPS65217_PPATH_USB_CURRENT_MASK	0x03
-+
-+#define TPS65217_INT_PBM		BIT(6)
-+#define TPS65217_INT_ACM		BIT(5)
-+#define TPS65217_INT_USBM		BIT(4)
-+#define TPS65217_INT_PBI		BIT(2)
-+#define TPS65217_INT_ACI		BIT(1)
-+#define TPS65217_INT_USBI		BIT(0)
-+
-+#define TPS65217_CHGCONFIG0_TREG	BIT(7)
-+#define TPS65217_CHGCONFIG0_DPPM	BIT(6)
-+#define TPS65217_CHGCONFIG0_TSUSP	BIT(5)
-+#define TPS65217_CHGCONFIG0_TERMI	BIT(4)
-+#define TPS65217_CHGCONFIG0_ACTIVE	BIT(3)
-+#define TPS65217_CHGCONFIG0_CHGTOUT	BIT(2)
-+#define TPS65217_CHGCONFIG0_PCHGTOUT	BIT(1)
-+#define TPS65217_CHGCONFIG0_BATTEMP	BIT(0)
-+
-+#define TPS65217_CHGCONFIG1_TMR_MASK	0xC0
-+#define TPS65217_CHGCONFIG1_TMR_ENABLE	BIT(5)
-+#define TPS65217_CHGCONFIG1_NTC_TYPE	BIT(4)
-+#define TPS65217_CHGCONFIG1_RESET	BIT(3)
-+#define TPS65217_CHGCONFIG1_TERM	BIT(2)
-+#define TPS65217_CHGCONFIG1_SUSP	BIT(1)
-+#define TPS65217_CHGCONFIG1_CHG_EN	BIT(0)
-+
-+#define TPS65217_CHGCONFIG2_DYNTMR	BIT(7)
-+#define TPS65217_CHGCONFIG2_VPREGHG	BIT(6)
-+#define TPS65217_CHGCONFIG2_VOREG_MASK	0x30
-+
-+#define TPS65217_CHGCONFIG3_ICHRG_MASK	0xC0
-+#define TPS65217_CHGCONFIG3_DPPMTH_MASK	0x30
-+#define TPS65217_CHGCONFIG2_PCHRGT	BIT(3)
-+#define TPS65217_CHGCONFIG2_TERMIF	0x06
-+#define TPS65217_CHGCONFIG2_TRANGE	BIT(0)
-+
-+#define TPS65217_WLEDCTRL1_ISINK_ENABLE	BIT(3)
-+#define TPS65217_WLEDCTRL1_ISEL		BIT(2)
-+#define TPS65217_WLEDCTRL1_FDIM_MASK	0x03
-+
-+#define TPS65217_WLEDCTRL2_DUTY_MASK	0x7F
-+
-+#define TPS65217_MUXCTRL_MUX_MASK	0x07
-+
-+#define TPS65217_STATUS_OFF		BIT(7)
-+#define TPS65217_STATUS_ACPWR		BIT(3)
-+#define TPS65217_STATUS_USBPWR		BIT(2)
-+#define TPS65217_STATUS_PB		BIT(0)
-+
-+#define TPS65217_PASSWORD_REGS_UNLOCK	0x7D
-+
-+#define TPS65217_PGOOD_LDO3_PG		BIT(6)
-+#define TPS65217_PGOOD_LDO4_PG		BIT(5)
-+#define TPS65217_PGOOD_DC1_PG		BIT(4)
-+#define TPS65217_PGOOD_DC2_PG		BIT(3)
-+#define TPS65217_PGOOD_DC3_PG		BIT(2)
-+#define TPS65217_PGOOD_LDO1_PG		BIT(1)
-+#define TPS65217_PGOOD_LDO2_PG		BIT(0)
-+
-+#define TPS65217_DEFPG_LDO1PGM		BIT(3)
-+#define TPS65217_DEFPG_LDO2PGM		BIT(2)
-+#define TPS65217_DEFPG_PGDLY_MASK	0x03
-+
-+#define TPS65217_DEFDCDCX_XADJX		BIT(7)
-+#define TPS65217_DEFDCDCX_DCDC_MASK	0x3F
-+
-+#define TPS65217_DEFSLEW_GO		BIT(7)
-+#define TPS65217_DEFSLEW_GODSBL		BIT(6)
-+#define TPS65217_DEFSLEW_PFM_EN1	BIT(5)
-+#define TPS65217_DEFSLEW_PFM_EN2	BIT(4)
-+#define TPS65217_DEFSLEW_PFM_EN3	BIT(3)
-+#define TPS65217_DEFSLEW_SLEW_MASK	0x07
-+
-+#define TPS65217_DEFLDO1_LDO1_MASK	0x0F
-+
-+#define TPS65217_DEFLDO2_TRACK		BIT(6)
-+#define TPS65217_DEFLDO2_LDO2_MASK	0x3F
-+
-+#define TPS65217_DEFLDO3_LDO3_EN	BIT(5)
-+#define TPS65217_DEFLDO3_LDO3_MASK	0x1F
-+
-+#define TPS65217_DEFLDO4_LDO4_EN	BIT(5)
-+#define TPS65217_DEFLDO4_LDO4_MASK	0x1F
-+
-+#define TPS65217_ENABLE_LS1_EN		BIT(6)
-+#define TPS65217_ENABLE_LS2_EN		BIT(5)
-+#define TPS65217_ENABLE_DC1_EN		BIT(4)
-+#define TPS65217_ENABLE_DC2_EN		BIT(3)
-+#define TPS65217_ENABLE_DC3_EN		BIT(2)
-+#define TPS65217_ENABLE_LDO1_EN		BIT(1)
-+#define TPS65217_ENABLE_LDO2_EN		BIT(0)
-+
-+#define TPS65217_DEFUVLO_UVLOHYS	BIT(2)
-+#define TPS65217_DEFUVLO_UVLO_MASK	0x03
-+
-+#define TPS65217_SEQ1_DC1_SEQ_MASK	0xF0
-+#define TPS65217_SEQ1_DC2_SEQ_MASK	0x0F
-+
-+#define TPS65217_SEQ2_DC3_SEQ_MASK	0xF0
-+#define TPS65217_SEQ2_LDO1_SEQ_MASK	0x0F
-+
-+#define TPS65217_SEQ3_LDO2_SEQ_MASK	0xF0
-+#define TPS65217_SEQ3_LDO3_SEQ_MASK	0x0F
-+
-+#define TPS65217_SEQ4_LDO4_SEQ_MASK	0xF0
-+
-+#define TPS65217_SEQ5_DLY1_MASK		0xC0
-+#define TPS65217_SEQ5_DLY2_MASK		0x30
-+#define TPS65217_SEQ5_DLY3_MASK		0x0C
-+#define TPS65217_SEQ5_DLY4_MASK		0x03
-+
-+#define TPS65217_SEQ6_DLY5_MASK		0xC0
-+#define TPS65217_SEQ6_DLY6_MASK		0x30
-+#define TPS65217_SEQ6_SEQUP		BIT(2)
-+#define TPS65217_SEQ6_SEQDWN		BIT(1)
-+#define TPS65217_SEQ6_INSTDWN		BIT(0)
-+
-+#define TPS65217_MAX_REGISTER		0x1E
-+#define TPS65217_PROTECT_NONE		0
-+#define TPS65217_PROTECT_L1		1
-+#define TPS65217_PROTECT_L2		2
-+
-+
-+enum tps65217_regulator_id {
-+	/* DCDC's */
-+	TPS65217_DCDC_1,
-+	TPS65217_DCDC_2,
-+	TPS65217_DCDC_3,
-+	/* LDOs */
-+	TPS65217_LDO_1,
-+	TPS65217_LDO_2,
-+	TPS65217_LDO_3,
-+	TPS65217_LDO_4,
-+};
-+
-+#define TPS65217_MAX_REG_ID		TPS65217_LDO_4
-+
-+/* Number of step-down converters available */
-+#define TPS65217_NUM_DCDC		3
-+/* Number of LDO voltage regulators available */
-+#define TPS65217_NUM_LDO		4
-+/* Number of total regulators available */
-+#define TPS65217_NUM_REGULATOR		(TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
-+
-+/**
-+ * struct tps65217_board - packages regulator init data
-+ * @tps65217_regulator_data: regulator initialization values
-+ *
-+ * Board data may be used to initialize regulator.
-+ */
-+struct tps65217_board {
-+	struct regulator_init_data *tps65217_init_data;
-+};
-+
-+/**
-+ * struct tps_info - packages regulator constraints
-+ * @name:		Voltage regulator name
-+ * @min_uV:		minimum micro volts
-+ * @max_uV:		minimum micro volts
-+ * @vsel_to_uv:		Function pointer to get voltage from selector
-+ * @uv_to_vsel:		Function pointer to get selector from voltage
-+ * @table:		Table for non-uniform voltage step-size
-+ * @table_len:		Length of the voltage table
-+ * @enable_mask:	Regulator enable mask bits
-+ * @set_vout_reg:	Regulator output voltage set register
-+ * @set_vout_mask:	Regulator output voltage set mask
-+ *
-+ * This data is used to check the regualtor voltage limits while setting.
-+ */
-+struct tps_info {
-+	const char *name;
-+	int min_uV;
-+	int max_uV;
-+	int (*vsel_to_uv)(unsigned int vsel);
-+	int (*uv_to_vsel)(int uV, unsigned int *vsel);
-+	const int *table;
-+	unsigned int table_len;
-+	unsigned int enable_mask;
-+	unsigned int set_vout_reg;
-+	unsigned int set_vout_mask;
-+};
-+
-+/**
-+ * struct tps65217 - tps65217 sub-driver chip access routines
-+ *
-+ * Device data may be used to access the TPS65217 chip
-+ */
-+
-+struct tps65217 {
-+	struct device *dev;
-+	struct tps65217_board *pdata;
-+	struct regulator_desc desc[TPS65217_NUM_REGULATOR];
-+	struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
-+	struct tps_info *info[TPS65217_NUM_REGULATOR];
-+	struct regmap *regmap;
-+
-+	/* Client devices */
-+	struct platform_device *regulator_pdev[TPS65217_NUM_REGULATOR];
-+};
-+
-+static inline struct tps65217 *dev_to_tps65217(struct device *dev)
-+{
-+	return dev_get_drvdata(dev);
-+}
-+
-+int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
-+					unsigned int *val);
-+int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
-+			unsigned int val, unsigned int level);
-+int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
-+		unsigned int mask, unsigned int val, unsigned int level);
-+int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
-+		unsigned int mask, unsigned int level);
-+
-+#endif /*  __LINUX_MFD_TPS65217_H */
-diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
-index 8bf2cb9..cfc1f76 100644
---- a/include/linux/mfd/tps65910.h
-+++ b/include/linux/mfd/tps65910.h
-@@ -17,10 +17,17 @@
- #ifndef __LINUX_MFD_TPS65910_H
- #define __LINUX_MFD_TPS65910_H
- 
-+#include <linux/gpio.h>
-+#include <linux/regulator/machine.h>
-+
- /* TPS chip id list */
- #define TPS65910			0
- #define TPS65911			1
- 
-+/* I2C Slave Address 7-bit */
-+#define TPS65910_I2C_ID0 0x12 /* Smart Reflex */
-+#define TPS65910_I2C_ID1 0x2D /* general-purpose control */
-+
- /* TPS regulator type list */
- #define REGULATOR_LDO			0
- #define REGULATOR_DCDC			1
-@@ -740,6 +747,34 @@
- #define TPS65910_GPIO_STS				BIT(1)
- #define TPS65910_GPIO_SET				BIT(0)
- 
-+/* Regulator Index Definitions */
-+#define TPS65910_REG_VRTC				0
-+#define TPS65910_REG_VIO				1
-+#define TPS65910_REG_VDD1				2
-+#define TPS65910_REG_VDD2				3
-+#define TPS65910_REG_VDD3				4
-+#define TPS65910_REG_VDIG1				5
-+#define TPS65910_REG_VDIG2				6
-+#define TPS65910_REG_VPLL				7
-+#define TPS65910_REG_VDAC				8
-+#define TPS65910_REG_VAUX1				9
-+#define TPS65910_REG_VAUX2				10
-+#define TPS65910_REG_VAUX33				11
-+#define TPS65910_REG_VMMC				12
-+
-+#define TPS65911_REG_VDDCTRL				4
-+#define TPS65911_REG_LDO1				5
-+#define TPS65911_REG_LDO2				6
-+#define TPS65911_REG_LDO3				7
-+#define TPS65911_REG_LDO4				8
-+#define TPS65911_REG_LDO5				9
-+#define TPS65911_REG_LDO6				10
-+#define TPS65911_REG_LDO7				11
-+#define TPS65911_REG_LDO8				12
-+
-+/* Max number of TPS65910/11 regulators */
-+#define TPS65910_NUM_REGS				13
-+
- /**
-  * struct tps65910_board
-  * Board platform data may be used to initialize regulators.
-@@ -751,7 +786,7 @@ struct tps65910_board {
- 	int irq_base;
- 	int vmbch_threshold;
- 	int vmbch2_threshold;
--	struct regulator_init_data *tps65910_pmic_init_data;
-+	struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
- };
- 
- /**
-diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
-index c8ef9bc..80caf1d 100644
---- a/include/linux/mmc/card.h
-+++ b/include/linux/mmc/card.h
-@@ -455,7 +455,7 @@ struct mmc_driver {
- 	struct device_driver drv;
- 	int (*probe)(struct mmc_card *);
- 	void (*remove)(struct mmc_card *);
--	int (*suspend)(struct mmc_card *, pm_message_t);
-+	int (*suspend)(struct mmc_card *);
- 	int (*resume)(struct mmc_card *);
- };
- 
-diff --git a/include/linux/platform_data/cbus.h b/include/linux/platform_data/cbus.h
-new file mode 100644
-index 0000000..7a977e1
---- /dev/null
-+++ b/include/linux/platform_data/cbus.h
-@@ -0,0 +1,31 @@
-+/*
-+ * cbus.h - CBUS platform_data definition
-+ *
-+ * Copyright (C) 2004 - 2009 Nokia Corporation
-+ *
-+ * Written by Felipe Balbi <felipe.balbi@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#ifndef __INCLUDE_LINUX_CBUS_H
-+#define __INCLUDE_LINUX_CBUS_H
-+
-+struct cbus_host_platform_data {
-+	int	dat_gpio;
-+	int	clk_gpio;
-+	int	sel_gpio;
-+};
-+
-+#endif /* __INCLUDE_LINUX_CBUS_H */
-diff --git a/include/linux/pwm/ehrpwm.h b/include/linux/pwm/ehrpwm.h
-new file mode 100644
-index 0000000..53a4481
---- /dev/null
-+++ b/include/linux/pwm/ehrpwm.h
-@@ -0,0 +1,190 @@
-+#ifndef __EHRPWM_H__
-+#define __EHRPWM_H__
-+
-+#include <linux/pwm/pwm.h>
-+
-+#define NCHAN 2
-+
-+struct ehrpwm_pwm;
-+
-+typedef int (*p_fcallback) (struct ehrpwm_pwm *, void *data);
-+
-+struct et_int {
-+	void *data;
-+	p_fcallback pcallback;
-+};
-+
-+struct tz_int {
-+	void *data;
-+	p_fcallback pcallback;
-+};
-+
-+struct ehrpwm_context {
-+	u32 tbctl;
-+	u32 tbprd;
-+	u32 hrcfg;
-+	u32 aqctla;
-+	u32 aqctlb;
-+	u32 cmpa;
-+	u32 cmpb;
-+	u32 tzctl;
-+	u32 tzflg;
-+	u32 tzclr;
-+	u32 tzfrc;
-+};
-+
-+struct ehrpwm_pwm {
-+	struct pwm_device pwm[NCHAN];
-+	struct pwm_device_ops ops;
-+	spinlock_t      lock;
-+	struct clk      *clk;
-+	void __iomem    *mmio_base;
-+	unsigned short prescale_val;
-+	int irq[2];
-+	struct et_int st_etint;
-+	struct tz_int st_tzint;
-+	u8 version;
-+	void __iomem *config_mem_base;
-+	struct device *dev;
-+	struct ehrpwm_context ctx;
-+};
-+
-+enum tz_event {
-+	TZ_ONE_SHOT_EVENT = 0,
-+	TZ_CYCLE_BY_CYCLE,
-+	TZ_OSHT_CBC,
-+	TZ_DIS_EVT,
-+};
-+
-+enum config_mask {
-+	CONFIG_NS,
-+	CONFIG_TICKS,
-+};
-+
-+enum db_edge_delay {
-+	RISING_EDGE_DELAY,
-+	FALLING_EDGE_DELAY,
-+};
-+
-+struct aq_config_params {
-+	unsigned char ch;
-+	unsigned char ctreqzro;
-+	unsigned char ctreqprd;
-+	unsigned char ctreqcmpaup;
-+	unsigned char ctreqcmpadown;
-+	unsigned char ctreqcmpbup;
-+	unsigned char ctreqcmpbdown;
-+};
-+
-+int ehrpwm_tb_set_prescalar_val(struct pwm_device *p, unsigned char
-+	clkdiv, unsigned char hspclkdiv);
-+
-+int ehrpwm_tb_config_sync(struct pwm_device *p, unsigned char phsen,
-+	unsigned char syncosel);
-+
-+int ehrpwm_tb_set_counter_mode(struct pwm_device *p, unsigned char
-+	ctrmode, unsigned char phsdir);
-+
-+int ehrpwm_tb_force_sync(struct pwm_device *p);
-+
-+int ehrpwm_tb_set_periodload(struct pwm_device *p, unsigned char
-+	       loadmode);
-+
-+int ehrpwm_tb_read_status(struct pwm_device *p, unsigned short *val);
-+
-+int ehrpwm_tb_read_counter(struct pwm_device *p, unsigned short *val);
-+
-+int ehrpwm_tb_set_period(struct pwm_device *p,	unsigned short val);
-+
-+int ehrpwm_tb_set_phase(struct pwm_device *p, unsigned short val);
-+
-+int ehrpwm_cmp_set_cmp_ctl(struct pwm_device *p, unsigned char
-+	       shdwamode, unsigned char shdwbmode, unsigned char loadamode,
-+	unsigned char loadbmode);
-+
-+int ehrpwm_cmp_set_cmp_val(struct pwm_device *p, unsigned char reg,
-+	unsigned short val);
-+
-+int ehrpwm_aq_set_act_ctrl(struct pwm_device *p,
-+	       struct aq_config_params *cfg);
-+
-+int ehrpwm_aq_set_one_shot_act(struct pwm_device  *p, unsigned char ch,
-+	unsigned char act);
-+
-+int ehrpwm_aq_ot_frc(struct pwm_device *p, unsigned char ch);
-+
-+int ehrpwm_aq_set_csfrc_load_mode(struct pwm_device *p, unsigned char
-+	       loadmode);
-+
-+int ehrpwm_aq_continuous_frc(struct pwm_device *p, unsigned char ch,
-+	unsigned char act);
-+
-+int ehrpwm_db_get_max_delay(struct pwm_device *p,
-+	       enum config_mask cfgmask, unsigned long *delay_val);
-+
-+int ehrpwm_db_get_delay(struct pwm_device *p, unsigned char edge,
-+	enum config_mask cfgmask, unsigned long *delay_val);
-+
-+int ehrpwm_db_set_delay(struct pwm_device *p, unsigned char edge,
-+		enum config_mask cfgmask, unsigned long delay);
-+
-+int ehrpwm_db_set_mode(struct pwm_device *p, unsigned char inmode,
-+		unsigned char polsel, unsigned char outmode);
-+
-+int ehrpwm_pc_configure(struct pwm_device *p, unsigned char chpduty,
-+		unsigned char chpfreq, unsigned char oshtwidth);
-+
-+int ehrpwm_pc_en_dis(struct pwm_device *p, unsigned char chpen);
-+
-+int ehrpwm_tz_sel_event(struct pwm_device *p, unsigned char input,
-+	       enum tz_event evt);
-+
-+int ehrpwm_tz_set_action(struct pwm_device *p, unsigned char ch,
-+	unsigned char act);
-+
-+int ehrpwm_tz_set_int_en_dis(struct pwm_device *p, enum tz_event event,
-+		unsigned char int_en_dis);
-+
-+int ehrpwm_tz_force_evt(struct pwm_device *p, enum tz_event event);
-+
-+int ehrpwm_tz_read_status(struct pwm_device *p, unsigned short *status);
-+
-+int ehrpwm_tz_clr_evt_status(struct pwm_device *p);
-+
-+int ehrpwm_tz_clr_int_status(struct pwm_device *p);
-+
-+int ehrpwm_et_set_sel_evt(struct pwm_device *p, unsigned char evt,
-+		unsigned char prd);
-+
-+int ehrpwm_et_int_en_dis(struct pwm_device *p, unsigned char en_dis);
-+
-+int ehrpwm_et_read_evt_cnt(struct pwm_device *p, unsigned long *evtcnt);
-+
-+int pwm_et_read_int_status(struct pwm_device *p,
-+	unsigned long *status);
-+
-+int ehrpwm_et_frc_int(struct pwm_device *p);
-+
-+int ehrpwm_et_clr_int(struct pwm_device *p);
-+
-+int ehrpwm_hr_set_phase(struct pwm_device *p, unsigned char val);
-+
-+int ehrpwm_hr_set_cmpval(struct pwm_device *p, unsigned char val);
-+
-+int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode,
-+		unsigned char ctlmode, unsigned char edgemode);
-+
-+int ehrpwm_et_cb_register(struct pwm_device *p, void *data,
-+	p_fcallback cb);
-+
-+int ehrpwm_tz_cb_register(struct pwm_device *p, void *data,
-+	p_fcallback cb);
-+
-+int ehrpwm_pwm_suspend(struct pwm_device *p, enum
-+	       config_mask config_mask,
-+	       unsigned long val);
-+
-+#define ENABLE 1
-+#define DISABLE 0
-+
-+#endif
-diff --git a/include/linux/pwm/pwm.h b/include/linux/pwm/pwm.h
-new file mode 100644
-index 0000000..99c08f5
---- /dev/null
-+++ b/include/linux/pwm/pwm.h
-@@ -0,0 +1,194 @@
-+/*
-+ * Copyright (C) 2011 Bill Gatliff < bgat@billgatliff.com>
-+ * Copyright (C) 2011 Arun Murthy <arun.murth@stericsson.com>
-+ *
-+ * This program is free software; you may redistribute and/or modify
-+ * it under the terms of the GNU General Public License version 2, as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-+ * USA
-+ */
-+#ifndef __LINUX_PWM_H
-+#define __LINUX_PWM_H
-+
-+enum {
-+	FLAG_REGISTERED		= 0,
-+	FLAG_REQUESTED		= 1,
-+	FLAG_STOP		= 2,
-+	FLAG_RUNNING		= 3,
-+};
-+
-+enum {
-+	PWM_CONFIG_DUTY_TICKS	= 0,
-+	PWM_CONFIG_PERIOD_TICKS	= 1,
-+	PWM_CONFIG_POLARITY	= 2,
-+	PWM_CONFIG_START	= 3,
-+	PWM_CONFIG_STOP		= 4,
-+
-+	PWM_CONFIG_HANDLER	= 5,
-+
-+	PWM_CONFIG_DUTY_NS	= 6,
-+	PWM_CONFIG_DUTY_PERCENT	= 7,
-+	PWM_CONFIG_PERIOD_NS	= 8,
-+};
-+
-+struct pwm_config;
-+struct pwm_device;
-+
-+typedef int (*pwm_handler_t)(struct pwm_device *p, void *data);
-+typedef void (*pwm_callback_t)(struct pwm_device *p);
-+
-+struct pwm_device_ops {
-+	int	(*request)		(struct pwm_device *p);
-+	void	(*release)		(struct pwm_device *p);
-+	int	(*config)		(struct pwm_device *p,
-+					 struct pwm_config *c);
-+	int	(*config_nosleep)	(struct pwm_device *p,
-+					 struct pwm_config *c);
-+	int	(*synchronize)		(struct pwm_device *p,
-+					 struct pwm_device *to_p);
-+	int	(*unsynchronize)	(struct pwm_device *p,
-+					 struct pwm_device *from_p);
-+	int	(*set_callback)		(struct pwm_device *p,
-+					 pwm_callback_t callback);
-+	int	(*freq_transition_notifier_cb) (struct pwm_device *p);
-+};
-+
-+struct pwm_config {
-+	unsigned long config_mask;
-+	unsigned long duty_ticks;
-+	unsigned long period_ticks;
-+	int polarity;
-+
-+	pwm_handler_t handler;
-+
-+	unsigned long duty_ns;
-+	unsigned long period_ns;
-+	int duty_percent;
-+};
-+
-+struct pwm_device {
-+	struct list_head list;
-+
-+	struct device *dev;
-+	struct pwm_device_ops *ops;
-+
-+	void *data;
-+
-+	const char *label;
-+	pid_t pid;
-+
-+	volatile unsigned long flags;
-+
-+	unsigned long tick_hz;
-+
-+	pwm_callback_t callback;
-+
-+	struct work_struct handler_work;
-+	pwm_handler_t handler;
-+	void *handler_data;
-+
-+	int active_high;
-+	unsigned long period_ticks;
-+	unsigned long duty_ticks;
-+	unsigned long period_ns;
-+	unsigned long duty_ns;
-+	struct notifier_block freq_transition;
-+	unsigned long max_period_ticks;
-+	spinlock_t pwm_lock;
-+};
-+
-+#include <linux/semaphore.h>
-+#include <linux/pwm/ehrpwm.h>
-+
-+enum {
-+	PWM_VERSION_0,
-+	PWM_VERSION_1,
-+};
-+
-+struct pwm_chan_attrib {
-+	int max_freq;
-+};
-+
-+#define PWM_CHANNEL NCHAN
-+
-+struct pwmss_platform_data {
-+	int channel_mask;
-+	u8 version;
-+	struct pwm_chan_attrib chan_attrib[PWM_CHANNEL];
-+};
-+
-+struct pwm_device *pwm_request_byname(const char *name, const char *label);
-+struct pwm_device *pwm_request(const char *bus_id, int id, const char *label);
-+void pwm_release(struct pwm_device *p);
-+
-+static inline int pwm_is_registered(struct pwm_device *p)
-+{
-+	return test_bit(FLAG_REGISTERED, &p->flags);
-+}
-+
-+static inline int pwm_is_requested(struct pwm_device *p)
-+{
-+	return test_bit(FLAG_REQUESTED, &p->flags);
-+}
-+
-+static inline int pwm_is_running(struct pwm_device *p)
-+{
-+	return test_bit(FLAG_RUNNING, &p->flags);
-+}
-+
-+static inline void pwm_set_drvdata(struct pwm_device *p, void *data)
-+{
-+	p->data = data;
-+}
-+
-+static inline void *pwm_get_drvdata(const struct pwm_device *p)
-+{
-+	return p->data;
-+}
-+
-+unsigned long pwm_ns_to_ticks(struct pwm_device *p, unsigned long nsecs);
-+unsigned long pwm_ticks_to_ns(struct pwm_device *p, unsigned long ticks);
-+
-+int pwm_config_nosleep(struct pwm_device *p, struct pwm_config *c);
-+int pwm_config(struct pwm_device *p, struct pwm_config *c);
-+
-+int pwm_set_period_ns(struct pwm_device *p, unsigned long period_ns);
-+unsigned long pwm_get_period_ns(struct pwm_device *p);
-+int pwm_set_duty_ns(struct pwm_device *p, unsigned long duty_ns);
-+unsigned long pwm_get_duty_ns(struct pwm_device *p);
-+int pwm_set_duty_percent(struct pwm_device *p, int percent);
-+int pwm_set_polarity(struct pwm_device *p, int active_high);
-+
-+int pwm_start(struct pwm_device *p);
-+int pwm_stop(struct pwm_device *p);
-+
-+int pwm_synchronize(struct pwm_device *p, struct pwm_device *to_p);
-+int pwm_unsynchronize(struct pwm_device *p, struct pwm_device *from_p);
-+int pwm_set_handler(struct pwm_device *p, pwm_handler_t handler, void *data);
-+
-+int pwm_register(struct pwm_device *p, struct device *parent, int id);
-+int pwm_register_byname(struct pwm_device *p, struct device *parent,
-+			const char *name);
-+int pwm_unregister(struct pwm_device *p);
-+
-+#ifdef CONFIG_GPIO_PWM
-+struct pwm_device *gpio_pwm_create(int gpio);
-+int gpio_pwm_destroy(struct pwm_device *p);
-+#endif
-+int pwm_set_frequency(struct pwm_device *p, unsigned long freq);
-+unsigned long pwm_get_frequency(struct pwm_device *p);
-+int pwm_set_period_ticks(struct pwm_device *p,
-+					unsigned long ticks);
-+unsigned long pwm_get_duty_percent(struct pwm_device *p);
-+int pwm_set_duty_ticks(struct pwm_device *p,
-+					unsigned long ticks);
-+#endif
-diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h
-index 63d2df4..b2777cd 100644
---- a/include/linux/pwm_backlight.h
-+++ b/include/linux/pwm_backlight.h
-@@ -7,7 +7,8 @@
- #include <linux/backlight.h>
- 
- struct platform_pwm_backlight_data {
--	int pwm_id;
-+	const char *pwm_id;
-+	int ch;
- 	unsigned int max_brightness;
- 	unsigned int dft_brightness;
- 	unsigned int lth_brightness;
-diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
-index 2cf4226..6b8fba3 100644
---- a/include/linux/rcupdate.h
-+++ b/include/linux/rcupdate.h
-@@ -800,13 +800,14 @@ static __always_inline bool __is_kfree_rcu_offset(unsigned long offset)
- 	return offset < 4096;
- }
- 
-+/*
-+ * Intended to be called only from the kfree_rcu() macro.
-+ */
- static __always_inline
- void __kfree_rcu(struct rcu_head *head, unsigned long offset)
- {
- 	typedef void (*rcu_callback)(struct rcu_head *);
- 
--	BUILD_BUG_ON(!__builtin_constant_p(offset));
--
- 	/* See the kfree_rcu() header comment. */
- 	BUILD_BUG_ON(!__is_kfree_rcu_offset(offset));
- 
-diff --git a/include/linux/usb.h b/include/linux/usb.h
-index 7503352..7626e5a 100644
---- a/include/linux/usb.h
-+++ b/include/linux/usb.h
-@@ -1211,6 +1211,7 @@ struct urb {
- 	struct list_head urb_list;	/* list head for use by the urb's
- 					 * current owner */
- 	struct list_head anchor_list;	/* the URB may be anchored */
-+	struct list_head giveback_list;	/* to postpone the giveback call */
- 	struct usb_anchor *anchor;
- 	struct usb_device *dev;		/* (in) pointer to associated device */
- 	struct usb_host_endpoint *ep;	/* (internal) pointer to endpoint */
-diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
-index 1d3a675..317d892 100644
---- a/include/linux/usb/gadget.h
-+++ b/include/linux/usb/gadget.h
-@@ -477,8 +477,8 @@ struct usb_gadget_ops {
-  *	driver setup() requests
-  * @ep_list: List of other endpoints supported by the device.
-  * @speed: Speed of current connection to USB host.
-- * @is_dualspeed: True if the controller supports both high and full speed
-- *	operation.  If it does, the gadget driver must also support both.
-+ * @max_speed: Maximal speed the UDC can handle.  UDC must support this
-+ *      and all slower speeds.
-  * @is_otg: True if the USB device port uses a Mini-AB jack, so that the
-  *	gadget driver must provide a USB OTG descriptor.
-  * @is_a_peripheral: False unless is_otg, the "A" end of a USB cable
-@@ -518,7 +518,7 @@ struct usb_gadget {
- 	struct usb_ep			*ep0;
- 	struct list_head		ep_list;	/* of usb_ep */
- 	enum usb_device_speed		speed;
--	unsigned			is_dualspeed:1;
-+	enum usb_device_speed		max_speed;
- 	unsigned			is_otg:1;
- 	unsigned			is_a_peripheral:1;
- 	unsigned			b_hnp_enable:1;
-@@ -549,7 +549,7 @@ static inline struct usb_gadget *dev_to_usb_gadget(struct device *dev)
- static inline int gadget_is_dualspeed(struct usb_gadget *g)
- {
- #ifdef CONFIG_USB_GADGET_DUALSPEED
--	/* runtime test would check "g->is_dualspeed" ... that might be
-+	/* runtime test would check "g->max_speed" ... that might be
- 	 * useful to work around hardware bugs, but is mostly pointless
- 	 */
- 	return 1;
-@@ -567,7 +567,7 @@ static inline int gadget_is_superspeed(struct usb_gadget *g)
- {
- #ifdef CONFIG_USB_GADGET_SUPERSPEED
- 	/*
--	 * runtime test would check "g->is_superspeed" ... that might be
-+	 * runtime test would check "g->max_speed" ... that might be
- 	 * useful to work around hardware bugs, but is mostly pointless
- 	 */
- 	return 1;
-@@ -760,7 +760,7 @@ static inline int usb_gadget_disconnect(struct usb_gadget *gadget)
- /**
-  * struct usb_gadget_driver - driver for usb 'slave' devices
-  * @function: String describing the gadget's function
-- * @speed: Highest speed the driver handles.
-+ * @max_speed: Highest speed the driver handles.
-  * @setup: Invoked for ep0 control requests that aren't handled by
-  *	the hardware level driver. Most calls must be handled by
-  *	the gadget driver, including descriptor and configuration
-@@ -824,7 +824,7 @@ static inline int usb_gadget_disconnect(struct usb_gadget *gadget)
-  */
- struct usb_gadget_driver {
- 	char			*function;
--	enum usb_device_speed	speed;
-+	enum usb_device_speed	max_speed;
- 	void			(*unbind)(struct usb_gadget *);
- 	int			(*setup)(struct usb_gadget *,
- 					const struct usb_ctrlrequest *);
-diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
-index eb50525..2c59816 100644
---- a/include/linux/usb/musb.h
-+++ b/include/linux/usb/musb.h
-@@ -62,6 +62,7 @@ struct musb_hdrc_eps_bits {
- struct musb_hdrc_config {
- 	struct musb_fifo_cfg	*fifo_cfg;	/* board fifo configuration */
- 	unsigned		fifo_cfg_size;	/* size of the fifo configuration */
-+	unsigned short		fifo_mode;	/* fifo mode to be selected */
- 
- 	/* MUSB configuration-specific details */
- 	unsigned	multipoint:1;	/* multipoint device */
-diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
-index d87f44f..da6be3c 100644
---- a/include/linux/usb/otg.h
-+++ b/include/linux/usb/otg.h
-@@ -63,6 +63,7 @@ struct otg_transceiver {
- 	struct device		*dev;
- 	const char		*label;
- 	unsigned int		 flags;
-+	u8			id;
- 
- 	u8			default_a;
- 	enum usb_otg_state	state;
-@@ -116,17 +117,18 @@ struct otg_transceiver {
- 
- /* for board-specific init logic */
- extern int otg_set_transceiver(struct otg_transceiver *);
-+extern int otg_reset_transceiver(struct otg_transceiver *);
- 
- #if defined(CONFIG_NOP_USB_XCEIV) || (defined(CONFIG_NOP_USB_XCEIV_MODULE) && defined(MODULE))
- /* sometimes transceivers are accessed only through e.g. ULPI */
--extern void usb_nop_xceiv_register(void);
--extern void usb_nop_xceiv_unregister(void);
-+extern void usb_nop_xceiv_register(int id);
-+extern void usb_nop_xceiv_unregister(int id);
- #else
--static inline void usb_nop_xceiv_register(void)
-+static inline void usb_nop_xceiv_register(int id)
- {
- }
- 
--static inline void usb_nop_xceiv_unregister(void)
-+static inline void usb_nop_xceiv_unregister(int id)
- {
- }
- #endif
-@@ -166,11 +168,11 @@ otg_shutdown(struct otg_transceiver *otg)
- 
- /* for usb host and peripheral controller drivers */
- #ifdef CONFIG_USB_OTG_UTILS
--extern struct otg_transceiver *otg_get_transceiver(void);
-+extern struct otg_transceiver *otg_get_transceiver(int id);
- extern void otg_put_transceiver(struct otg_transceiver *);
- extern const char *otg_state_string(enum usb_otg_state state);
- #else
--static inline struct otg_transceiver *otg_get_transceiver(void)
-+static inline struct otg_transceiver *otg_get_transceiver(int id)
- {
- 	return NULL;
- }
-diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
-index 4bde182..dcdfc2b 100644
---- a/include/linux/vmalloc.h
-+++ b/include/linux/vmalloc.h
-@@ -131,6 +131,7 @@ extern long vwrite(char *buf, char *addr, unsigned long count);
-  */
- extern rwlock_t vmlist_lock;
- extern struct vm_struct *vmlist;
-+extern __init void vm_area_add_early(struct vm_struct *vm);
- extern __init void vm_area_register_early(struct vm_struct *vm, size_t align);
- 
- #ifdef CONFIG_SMP
-diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h
-index 4b69739..e6911c6 100644
---- a/include/linux/wl12xx.h
-+++ b/include/linux/wl12xx.h
-@@ -54,6 +54,8 @@ struct wl12xx_platform_data {
- 	int board_ref_clock;
- 	int board_tcxo_clock;
- 	unsigned long platform_quirks;
-+	int bt_enable_gpio;
-+	int wlan_enable_gpio;
- };
- 
- /* Platform does not support level trigger interrupts */
-diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h
-index 89d43b3..6a6a69f 100644
---- a/include/video/da8xx-fb.h
-+++ b/include/video/da8xx-fb.h
-@@ -13,7 +13,8 @@
- #define DA8XX_FB_H
- 
- enum panel_type {
--	QVGA = 0
-+	QVGA = 0,
-+	WVGA,
- };
- 
- enum panel_shade {
-@@ -28,7 +29,7 @@ enum raster_load_mode {
- };
- 
- struct display_panel {
--	enum panel_type panel_type; /* QVGA */
-+	enum panel_type panel_type;
- 	int max_bpp;
- 	int min_bpp;
- 	enum panel_shade panel_shade;
-@@ -82,6 +83,9 @@ struct lcd_ctrl_config {
- 
- 	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
- 	unsigned char raster_order;
-+
-+	/* DMA FIFO threshold */
-+	int fifo_th;
- };
- 
- struct lcd_sync_arg {
-@@ -100,5 +104,9 @@ struct lcd_sync_arg {
- #define FBIPUT_HSYNC		_IOW('F', 9, int)
- #define FBIPUT_VSYNC		_IOW('F', 10, int)
- 
-+typedef void (*vsync_callback_t)(void *arg);
-+int register_vsync_cb(vsync_callback_t handler, void *arg, int idx);
-+int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx);
-+
- #endif  /* ifndef DA8XX_FB_H */
- 
-diff --git a/include/video/st7735fb.h b/include/video/st7735fb.h
-new file mode 100644
-index 0000000..250f036
---- /dev/null
-+++ b/include/video/st7735fb.h
-@@ -0,0 +1,86 @@
-+/*
-+ * linux/include/video/st7735fb.h -- FB driver for ST7735 LCD controller
-+ *
-+ * Copyright (C) 2011, Matt Porter
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive for
-+ * more details.
-+ */
-+
-+#define DRVNAME		"st7735fb"
-+#define WIDTH		128
-+#define HEIGHT		160
-+#define BPP		16
-+
-+/* Supported display modules */
-+#define ST7735_DISPLAY_AF_TFT18		0	/* Adafruit SPI TFT 1.8" */
-+
-+/* Init script function */
-+struct st7735_function {
-+	u16 cmd;
-+	u16 data;
-+};
-+
-+/* Init script commands */
-+enum st7735_cmd {
-+	ST7735_START,
-+	ST7735_END,
-+	ST7735_CMD,
-+	ST7735_DATA,
-+	ST7735_DELAY
-+};
-+
-+struct st7735fb_par {
-+	struct spi_device *spi;
-+	struct fb_info *info;
-+	int rst;
-+	int dc;
-+};
-+
-+struct st7735fb_platform_data {
-+	int rst_gpio;
-+	int dc_gpio;
-+};
-+
-+/* ST7735 Commands */
-+#define ST7735_NOP	0x0
-+#define ST7735_SWRESET	0x01
-+#define ST7735_RDDID	0x04
-+#define ST7735_RDDST	0x09
-+#define ST7735_SLPIN	0x10
-+#define ST7735_SLPOUT	0x11
-+#define ST7735_PTLON	0x12
-+#define ST7735_NORON	0x13
-+#define ST7735_INVOFF	0x20
-+#define ST7735_INVON	0x21
-+#define ST7735_DISPOFF	0x28
-+#define ST7735_DISPON	0x29
-+#define ST7735_CASET	0x2A
-+#define ST7735_RASET	0x2B
-+#define ST7735_RAMWR	0x2C
-+#define ST7735_RAMRD	0x2E
-+#define ST7735_COLMOD	0x3A
-+#define ST7735_MADCTL	0x36
-+#define ST7735_FRMCTR1	0xB1
-+#define ST7735_FRMCTR2	0xB2
-+#define ST7735_FRMCTR3	0xB3
-+#define ST7735_INVCTR	0xB4
-+#define ST7735_DISSET5	0xB6
-+#define ST7735_PWCTR1	0xC0
-+#define ST7735_PWCTR2	0xC1
-+#define ST7735_PWCTR3	0xC2
-+#define ST7735_PWCTR4	0xC3
-+#define ST7735_PWCTR5	0xC4
-+#define ST7735_VMCTR1	0xC5
-+#define ST7735_RDID1	0xDA
-+#define ST7735_RDID2	0xDB
-+#define ST7735_RDID3	0xDC
-+#define ST7735_RDID4	0xDD
-+#define ST7735_GMCTRP1	0xE0
-+#define ST7735_GMCTRN1	0xE1
-+#define ST7735_PWCTR6	0xFC
-+
-+
-+
-+
-diff --git a/lib/decompress_bunzip2.c b/lib/decompress_bunzip2.c
-index a7b80c1..3380297 100644
---- a/lib/decompress_bunzip2.c
-+++ b/lib/decompress_bunzip2.c
-@@ -691,7 +691,7 @@ STATIC int INIT bunzip2(unsigned char *buf, int len,
- 		outbuf = malloc(BZIP2_IOBUF_SIZE);
- 
- 	if (!outbuf) {
--		error("Could not allocate output bufer");
-+		error("Could not allocate output buffer");
- 		return RETVAL_OUT_OF_MEMORY;
- 	}
- 	if (buf)
-@@ -699,7 +699,7 @@ STATIC int INIT bunzip2(unsigned char *buf, int len,
- 	else
- 		inbuf = malloc(BZIP2_IOBUF_SIZE);
- 	if (!inbuf) {
--		error("Could not allocate input bufer");
-+		error("Could not allocate input buffer");
- 		i = RETVAL_OUT_OF_MEMORY;
- 		goto exit_0;
- 	}
-diff --git a/lib/decompress_unlzma.c b/lib/decompress_unlzma.c
-index 476c65a..32adb73 100644
---- a/lib/decompress_unlzma.c
-+++ b/lib/decompress_unlzma.c
-@@ -562,7 +562,7 @@ STATIC inline int INIT unlzma(unsigned char *buf, int in_len,
- 	else
- 		inbuf = malloc(LZMA_IOBUF_SIZE);
- 	if (!inbuf) {
--		error("Could not allocate input bufer");
-+		error("Could not allocate input buffer");
- 		goto exit_0;
- 	}
- 
-diff --git a/mm/vmalloc.c b/mm/vmalloc.c
-index 27be2f0..21fdf46 100644
---- a/mm/vmalloc.c
-+++ b/mm/vmalloc.c
-@@ -1118,6 +1118,32 @@ void *vm_map_ram(struct page **pages, unsigned int count, int node, pgprot_t pro
- EXPORT_SYMBOL(vm_map_ram);
- 
- /**
-+ * vm_area_add_early - add vmap area early during boot
-+ * @vm: vm_struct to add
-+ *
-+ * This function is used to add fixed kernel vm area to vmlist before
-+ * vmalloc_init() is called.  @vm->addr, @vm->size, and @vm->flags
-+ * should contain proper values and the other fields should be zero.
-+ *
-+ * DO NOT USE THIS FUNCTION UNLESS YOU KNOW WHAT YOU'RE DOING.
-+ */
-+void __init vm_area_add_early(struct vm_struct *vm)
-+{
-+	struct vm_struct *tmp, **p;
-+
-+	BUG_ON(vmap_initialized);
-+	for (p = &vmlist; (tmp = *p) != NULL; p = &tmp->next) {
-+		if (tmp->addr >= vm->addr) {
-+			BUG_ON(tmp->addr < vm->addr + vm->size);
-+			break;
-+		} else
-+			BUG_ON(tmp->addr + tmp->size > vm->addr);
-+	}
-+	vm->next = *p;
-+	*p = vm;
-+}
-+
-+/**
-  * vm_area_register_early - register vmap area early during boot
-  * @vm: vm_struct to register
-  * @align: requested alignment
-@@ -1139,8 +1165,7 @@ void __init vm_area_register_early(struct vm_struct *vm, size_t align)
- 
- 	vm->addr = (void *)addr;
- 
--	vm->next = vmlist;
--	vmlist = vm;
-+	vm_area_add_early(vm);
- }
- 
- void __init vmalloc_init(void)
-diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
-index 87d5ef1..d0dbac1 100644
---- a/sound/soc/codecs/tlv320aic3x.c
-+++ b/sound/soc/codecs/tlv320aic3x.c
-@@ -1147,6 +1147,11 @@ static int aic3x_set_power(struct snd_soc_codec *codec, int power)
- 		codec->cache_only = 1;
- 		ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
- 					     aic3x->supplies);
-+		/* Enable cache sync if regulator disable
-+		 * event is not triggerd.
-+		 * ToDo : Revisit later to fix it
-+		 */
-+		codec->cache_sync = 1;
- 	}
- out:
- 	return ret;
-diff --git a/sound/soc/davinci/Kconfig b/sound/soc/davinci/Kconfig
-index 9e11a14..6b8dc37 100644
---- a/sound/soc/davinci/Kconfig
-+++ b/sound/soc/davinci/Kconfig
-@@ -6,6 +6,14 @@ config SND_DAVINCI_SOC
- 	  the DAVINCI AC97 or I2S interface. You will also need
- 	  to select the audio interfaces to support below.
- 
-+config SND_AM33XX_SOC
-+	tristate "SoC Audio for the AM33XX chip"
-+	depends on SOC_OMAPAM33XX
-+	help
-+	  Say Y or M if you want to add support for codecs attached to
-+	  the AM33XX I2S interface. You will also need to select the
-+	  audio interfaces to support below.
-+
- config SND_DAVINCI_SOC_I2S
- 	tristate
- 
-@@ -25,6 +33,15 @@ config SND_DAVINCI_SOC_EVM
- 	  Say Y if you want to add support for SoC audio on TI
- 	  DaVinci DM6446, DM355 or DM365 EVM platforms.
- 
-+config  SND_AM335X_SOC_EVM
-+	tristate "SoC Audio support for AM335X EVM"
-+	depends on SND_AM33XX_SOC
-+	select SND_DAVINCI_SOC_MCASP
-+	select SND_SOC_TLV320AIC3X
-+	help
-+	  Say Y if you want to add support for SoC audio on
-+	  AM335X EVM
-+
- choice
- 	prompt "DM365 codec select"
- 	depends on SND_DAVINCI_SOC_EVM
-diff --git a/sound/soc/davinci/Makefile b/sound/soc/davinci/Makefile
-index a93679d..a7af786 100644
---- a/sound/soc/davinci/Makefile
-+++ b/sound/soc/davinci/Makefile
-@@ -5,6 +5,7 @@ snd-soc-davinci-mcasp-objs:= davinci-mcasp.o
- snd-soc-davinci-vcif-objs:= davinci-vcif.o
- 
- obj-$(CONFIG_SND_DAVINCI_SOC) += snd-soc-davinci.o
-+obj-$(CONFIG_SND_AM33XX_SOC) += snd-soc-davinci.o
- obj-$(CONFIG_SND_DAVINCI_SOC_I2S) += snd-soc-davinci-i2s.o
- obj-$(CONFIG_SND_DAVINCI_SOC_MCASP) += snd-soc-davinci-mcasp.o
- obj-$(CONFIG_SND_DAVINCI_SOC_VCIF) += snd-soc-davinci-vcif.o
-@@ -17,4 +18,5 @@ obj-$(CONFIG_SND_DAVINCI_SOC_EVM) += snd-soc-evm.o
- obj-$(CONFIG_SND_DM6467_SOC_EVM) += snd-soc-evm.o
- obj-$(CONFIG_SND_DA830_SOC_EVM) += snd-soc-evm.o
- obj-$(CONFIG_SND_DA850_SOC_EVM) += snd-soc-evm.o
-+obj-$(CONFIG_SND_AM335X_SOC_EVM) += snd-soc-evm.o
- obj-$(CONFIG_SND_DAVINCI_SOC_SFFSDR) += snd-soc-sffsdr.o
-diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
-index f78c3f0..f6a62c3 100644
---- a/sound/soc/davinci/davinci-evm.c
-+++ b/sound/soc/davinci/davinci-evm.c
-@@ -22,9 +22,8 @@
- #include <asm/dma.h>
- #include <asm/mach-types.h>
- 
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- #include <mach/edma.h>
--#include <mach/mux.h>
- 
- #include "davinci-pcm.h"
- #include "davinci-i2s.h"
-@@ -56,6 +55,9 @@ static int evm_hw_params(struct snd_pcm_substream *substream,
- 	else if (machine_is_davinci_da830_evm() ||
- 				machine_is_davinci_da850_evm())
- 		sysclk = 24576000;
-+	/* On AM335X, CODEC gets MCLK from external Xtal (12MHz). */
-+	else if (machine_is_am335xevm())
-+		sysclk = 12000000;
- 
- 	else
- 		return -EINVAL;
-@@ -239,6 +241,17 @@ static struct snd_soc_dai_link da850_evm_dai = {
- 	.ops = &evm_ops,
- };
- 
-+static struct snd_soc_dai_link am335x_evm_dai = {
-+	.name = "TLV320AIC3X",
-+	.stream_name = "AIC3X",
-+	.cpu_dai_name = "davinci-mcasp.1",
-+	.codec_dai_name = "tlv320aic3x-hifi",
-+	.codec_name = "tlv320aic3x-codec.2-001b",
-+	.platform_name = "davinci-pcm-audio",
-+	.init = evm_aic3x_init,
-+	.ops = &evm_ops,
-+};
-+
- /* davinci dm6446 evm audio machine driver */
- static struct snd_soc_card dm6446_snd_soc_card_evm = {
- 	.name = "DaVinci DM6446 EVM",
-@@ -279,6 +292,12 @@ static struct snd_soc_card da850_snd_soc_card = {
- 	.num_links = 1,
- };
- 
-+static struct snd_soc_card am335x_snd_soc_card = {
-+	.name = "AM335X EVM",
-+	.dai_link = &am335x_evm_dai,
-+	.num_links = 1,
-+};
-+
- static struct platform_device *evm_snd_device;
- 
- static int __init evm_init(void)
-@@ -305,6 +324,9 @@ static int __init evm_init(void)
- 	} else if (machine_is_davinci_da850_evm()) {
- 		evm_snd_dev_data = &da850_snd_soc_card;
- 		index = 0;
-+	} else if (machine_is_am335xevm()) {
-+		evm_snd_dev_data = &am335x_snd_soc_card;
-+		index = 0;
- 	} else
- 		return -EINVAL;
- 
-diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
-index 300e121..81a3e16 100644
---- a/sound/soc/davinci/davinci-i2s.c
-+++ b/sound/soc/davinci/davinci-i2s.c
-@@ -23,7 +23,7 @@
- #include <sound/initval.h>
- #include <sound/soc.h>
- 
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- 
- #include "davinci-pcm.h"
- #include "davinci-i2s.h"
-diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
-index 7173df2..0136cc4 100644
---- a/sound/soc/davinci/davinci-mcasp.c
-+++ b/sound/soc/davinci/davinci-mcasp.c
-@@ -21,7 +21,7 @@
- #include <linux/slab.h>
- #include <linux/delay.h>
- #include <linux/io.h>
--#include <linux/clk.h>
-+#include <linux/pm_runtime.h>
- 
- #include <sound/core.h>
- #include <sound/pcm.h>
-@@ -108,6 +108,10 @@
- #define DAVINCI_MCASP_WFIFOSTS		(0x1014)
- #define DAVINCI_MCASP_RFIFOCTL		(0x1018)
- #define DAVINCI_MCASP_RFIFOSTS		(0x101C)
-+#define MCASP_VER3_WFIFOCTL		(0x1000)
-+#define MCASP_VER3_WFIFOSTS		(0x1004)
-+#define MCASP_VER3_RFIFOCTL		(0x1008)
-+#define MCASP_VER3_RFIFOSTS		(0x100C)
- 
- /*
-  * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
-@@ -380,14 +384,34 @@ static void mcasp_start_tx(struct davinci_audio_dev *dev)
- static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
- {
- 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
--		if (dev->txnumevt)	/* enable FIFO */
--			mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
-+		if (dev->txnumevt) {	/* flush and enable FIFO */
-+			if (dev->version == MCASP_VERSION_3) {
-+				mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
- 								FIFO_ENABLE);
-+				mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
-+								FIFO_ENABLE);
-+			} else {
-+				mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
-+								FIFO_ENABLE);
-+				mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
-+								FIFO_ENABLE);
-+			}
-+		}
- 		mcasp_start_tx(dev);
- 	} else {
--		if (dev->rxnumevt)	/* enable FIFO */
--			mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
-+		if (dev->rxnumevt) {	/* flush and enable FIFO */
-+			if (dev->version == MCASP_VERSION_3) {
-+				mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
-+								FIFO_ENABLE);
-+				mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
-+								FIFO_ENABLE);
-+			} else {
-+				mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
-+								FIFO_ENABLE);
-+				mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
- 								FIFO_ENABLE);
-+			}
-+		}
- 		mcasp_start_rx(dev);
- 	}
- }
-@@ -407,14 +431,24 @@ static void mcasp_stop_tx(struct davinci_audio_dev *dev)
- static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
- {
- 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
--		if (dev->txnumevt)	/* disable FIFO */
--			mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
--								FIFO_ENABLE);
-+		if (dev->txnumevt) {	/* disable FIFO */
-+			if (dev->version == MCASP_VERSION_3)
-+				mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
-+						FIFO_ENABLE);
-+			else
-+				mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
-+						FIFO_ENABLE);
-+		}
- 		mcasp_stop_tx(dev);
- 	} else {
--		if (dev->rxnumevt)	/* disable FIFO */
--			mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
--								FIFO_ENABLE);
-+		if (dev->rxnumevt) {	/* disable FIFO */
-+			if (dev->version == MCASP_VERSION_3)
-+				mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
-+						FIFO_ENABLE);
-+			else
-+				mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
-+						FIFO_ENABLE);
-+		}
- 		mcasp_stop_rx(dev);
- 	}
- }
-@@ -565,7 +599,7 @@ static int davinci_config_channel_size(struct davinci_audio_dev *dev,
- 					TXSSZ(fmt), TXSSZ(0x0F));
- 	mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
- 							TXROT(7));
--	mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
-+	mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(0),
- 							RXROT(7));
- 	mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
- 	mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
-@@ -613,20 +647,36 @@ static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
- 		if (dev->txnumevt * tx_ser > 64)
- 			dev->txnumevt = 1;
- 
--		mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
-+		if (dev->version == MCASP_VERSION_3) {
-+			mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
- 								NUMDMA_MASK);
--		mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
-+			mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
-+				((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
-+		} else {
-+			mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
-+							tx_ser, NUMDMA_MASK);
-+			mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
- 				((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
-+		}
- 	}
- 
- 	if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
- 		if (dev->rxnumevt * rx_ser > 64)
- 			dev->rxnumevt = 1;
- 
--		mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
-+		if (dev->version == MCASP_VERSION_3) {
-+			mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
- 								NUMDMA_MASK);
--		mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
--				((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
-+			mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
-+					((dev->rxnumevt * rx_ser) << 8),
-+					NUMEVT_MASK);
-+		} else {
-+			mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
-+							rx_ser,	NUMDMA_MASK);
-+			mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
-+					((dev->rxnumevt * rx_ser) << 8),
-+					NUMEVT_MASK);
-+		}
- 	}
- }
- 
-@@ -776,20 +826,18 @@ static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
- 	case SNDRV_PCM_TRIGGER_RESUME:
- 	case SNDRV_PCM_TRIGGER_START:
- 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
--		if (!dev->clk_active) {
--			clk_enable(dev->clk);
--			dev->clk_active = 1;
--		}
-+		ret = pm_runtime_get_sync(dev->dev);
-+		if (ret < 0)
-+			dev_err(dev->dev, "failed to get runtime pm\n");
-+
- 		davinci_mcasp_start(dev, substream->stream);
- 		break;
- 
- 	case SNDRV_PCM_TRIGGER_SUSPEND:
- 		davinci_mcasp_stop(dev, substream->stream);
--		if (dev->clk_active) {
--			clk_disable(dev->clk);
--			dev->clk_active = 0;
--		}
--
-+		ret = pm_runtime_put_sync(dev->dev);
-+		if (ret < 0)
-+			dev_err(dev->dev, "failed to put runtime pm\n");
- 		break;
- 
- 	case SNDRV_PCM_TRIGGER_STOP:
-@@ -887,15 +935,14 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
- 	}
- 
- 	pdata = pdev->dev.platform_data;
--	dev->clk = clk_get(&pdev->dev, NULL);
--	if (IS_ERR(dev->clk)) {
--		ret = -ENODEV;
-+	pm_runtime_enable(&pdev->dev);
-+
-+	ret = pm_runtime_get_sync(&pdev->dev);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to get runtime pm\n");
- 		goto err_release_region;
- 	}
- 
--	clk_enable(dev->clk);
--	dev->clk_active = 1;
--
- 	dev->base = ioremap(mem->start, resource_size(mem));
- 	if (!dev->base) {
- 		dev_err(&pdev->dev, "ioremap failed\n");
-@@ -911,16 +958,35 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
- 	dev->version = pdata->version;
- 	dev->txnumevt = pdata->txnumevt;
- 	dev->rxnumevt = pdata->rxnumevt;
-+	dev->dev	= &pdev->dev;
-+
-+	if (dev->version == MCASP_VERSION_3) {
-+		dev->xrsrctl = kzalloc((sizeof(unsigned int) *
-+							dev->num_serializer),
-+							GFP_KERNEL);
-+		if (!dev->xrsrctl) {
-+			ret = -ENOMEM;
-+			dev_err(&pdev->dev, "err: mem alloc xrsrctl\n");
-+			goto err_release_clk;
-+		}
-+	}
- 
- 	dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
- 	dma_data->asp_chan_q = pdata->asp_chan_q;
- 	dma_data->ram_chan_q = pdata->ram_chan_q;
- 	dma_data->sram_size = pdata->sram_size_playback;
--	dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
-+	if (dev->version == MCASP_VERSION_3)
-+		dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset);
-+	else
-+		dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
- 							mem->start);
- 
--	/* first TX, then RX */
--	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-+	if (dev->version == MCASP_VERSION_3)
-+		res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
-+	else
-+		/* first TX, then RX */
-+		res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-+
- 	if (!res) {
- 		dev_err(&pdev->dev, "no DMA resource\n");
- 		ret = -ENODEV;
-@@ -933,10 +999,17 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
- 	dma_data->asp_chan_q = pdata->asp_chan_q;
- 	dma_data->ram_chan_q = pdata->ram_chan_q;
- 	dma_data->sram_size = pdata->sram_size_capture;
--	dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
-+	if (dev->version == MCASP_VERSION_3)
-+		dma_data->dma_addr = (dma_addr_t) (pdata->rx_dma_offset);
-+	else
-+		dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
- 							mem->start);
- 
--	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-+	if (dev->version == MCASP_VERSION_3)
-+		res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
-+	else
-+		res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-+
- 	if (!res) {
- 		dev_err(&pdev->dev, "no DMA resource\n");
- 		ret = -ENODEV;
-@@ -952,11 +1025,13 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
- 	return 0;
- 
- err_iounmap:
-+	if (dev->version == MCASP_VERSION_3)
-+		kfree(dev->xrsrctl);
- 	iounmap(dev->base);
- err_release_clk:
--	clk_disable(dev->clk);
--	clk_put(dev->clk);
-+	pm_runtime_put_sync(&pdev->dev);
- err_release_region:
-+	pm_runtime_disable(&pdev->dev);
- 	release_mem_region(mem->start, resource_size(mem));
- err_release_data:
- 	kfree(dev);
-@@ -970,21 +1045,129 @@ static int davinci_mcasp_remove(struct platform_device *pdev)
- 	struct resource *mem;
- 
- 	snd_soc_unregister_dai(&pdev->dev);
--	clk_disable(dev->clk);
--	clk_put(dev->clk);
--	dev->clk = NULL;
--
-+	pm_runtime_put_sync(&pdev->dev);
-+	pm_runtime_disable(&pdev->dev);
- 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	release_mem_region(mem->start, resource_size(mem));
--
-+	if (dev->version == MCASP_VERSION_3)
-+		kfree(dev->xrsrctl);
- 	kfree(dev);
- 
- 	return 0;
- }
- 
-+#ifdef CONFIG_PM
-+static int davinci_mcasp_suspend(struct platform_device *pdev,
-+							pm_message_t state)
-+{
-+	int ret = 0, idx;
-+	struct davinci_audio_dev *dev = dev_get_drvdata(&pdev->dev);
-+
-+	if (dev->version == MCASP_VERSION_3) {
-+		dev->gblctlx = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_GBLCTLX_REG);
-+		dev->txmask = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_TXMASK_REG);
-+		dev->txfmt = mcasp_get_reg(dev->base + DAVINCI_MCASP_TXFMT_REG);
-+		dev->txfmctl = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_TXFMCTL_REG);
-+		dev->aclkxctl = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_ACLKXCTL_REG);
-+		dev->ahclkxctl = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_AHCLKXCTL_REG);
-+		dev->txtdm = mcasp_get_reg(dev->base + DAVINCI_MCASP_TXTDM_REG);
-+		dev->wfifoctl = mcasp_get_reg(dev->base + MCASP_VER3_WFIFOCTL);
-+
-+		dev->gblctlr = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_GBLCTLR_REG);
-+		dev->rxmask = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_RXMASK_REG);
-+		dev->rxfmt = mcasp_get_reg(dev->base + DAVINCI_MCASP_RXFMT_REG);
-+		dev->rxfmctl = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_RXFMCTL_REG);
-+		dev->aclkrctl = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_ACLKRCTL_REG);
-+		dev->ahclkrctl = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_AHCLKRCTL_REG);
-+		dev->rxtdm = mcasp_get_reg(dev->base + DAVINCI_MCASP_RXTDM_REG);
-+		dev->rfifoctl = mcasp_get_reg(dev->base + MCASP_VER3_RFIFOCTL);
-+
-+		for (idx = 0; idx < dev->num_serializer; idx++) {
-+			dev->xrsrctl[idx] = mcasp_get_reg(dev->base +
-+						DAVINCI_MCASP_XRSRCTL_REG(idx));
-+		}
-+
-+		dev->pfunc = mcasp_get_reg(dev->base + DAVINCI_MCASP_PFUNC_REG);
-+		dev->pdir = mcasp_get_reg(dev->base + DAVINCI_MCASP_PDIR_REG);
-+	}
-+
-+	ret = pm_runtime_put_sync(&pdev->dev);
-+	if (ret < 0)
-+		dev_err(&pdev->dev, "failed to get runtime pm\n");
-+
-+	/* only values < 0 indicate errors */
-+	return IS_ERR_VALUE(ret) ? ret : 0;
-+}
-+
-+static int davinci_mcasp_resume(struct platform_device *pdev)
-+{
-+	int ret = 0, idx;
-+	struct davinci_audio_dev *dev = dev_get_drvdata(&pdev->dev);
-+
-+	ret = pm_runtime_get_sync(&pdev->dev);
-+	if (ret < 0)
-+		dev_err(&pdev->dev, "failed to get runtime pm\n");
-+
-+	if (dev->version == MCASP_VERSION_3) {
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG,
-+								dev->gblctlx);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG,
-+								dev->txmask);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMT_REG, dev->txfmt);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
-+								dev->txfmctl);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
-+								dev->aclkxctl);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
-+								dev->ahclkxctl);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, dev->txtdm);
-+		mcasp_set_reg(dev->base + MCASP_VER3_WFIFOCTL, dev->wfifoctl);
-+
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG,
-+								dev->gblctlr);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
-+								dev->rxmask);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_RXFMT_REG, dev->rxfmt);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
-+								dev->rxfmctl);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
-+								dev->aclkrctl);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
-+								dev->ahclkrctl);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, dev->rxtdm);
-+		mcasp_set_reg(dev->base + MCASP_VER3_RFIFOCTL, dev->rfifoctl);
-+
-+		for (idx = 0; idx < dev->num_serializer; idx++) {
-+			mcasp_set_reg((dev->base +
-+						DAVINCI_MCASP_XRSRCTL_REG(idx)),
-+						dev->xrsrctl[idx]);
-+		}
-+
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, dev->pfunc);
-+		mcasp_set_reg(dev->base + DAVINCI_MCASP_PDIR_REG, dev->pdir);
-+	}
-+	/* only values < 0 indicate errors */
-+	return IS_ERR_VALUE(ret) ? ret : 0;
-+}
-+#endif
-+
- static struct platform_driver davinci_mcasp_driver = {
- 	.probe		= davinci_mcasp_probe,
- 	.remove		= davinci_mcasp_remove,
-+#ifdef CONFIG_PM
-+	.suspend	= davinci_mcasp_suspend,
-+	.resume		= davinci_mcasp_resume,
-+#endif
- 	.driver		= {
- 		.name	= "davinci-mcasp",
- 		.owner	= THIS_MODULE,
-diff --git a/sound/soc/davinci/davinci-mcasp.h b/sound/soc/davinci/davinci-mcasp.h
-index 4681acc..abbb7cc 100644
---- a/sound/soc/davinci/davinci-mcasp.h
-+++ b/sound/soc/davinci/davinci-mcasp.h
-@@ -19,7 +19,7 @@
- #define DAVINCI_MCASP_H
- 
- #include <linux/io.h>
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- #include "davinci-pcm.h"
- 
- #define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_96000
-@@ -38,6 +38,7 @@ enum {
- 
- struct davinci_audio_dev {
- 	struct davinci_pcm_dma_params dma_params[2];
-+	struct device *dev;
- 	void __iomem *base;
- 	int sample_rate;
- 	struct clk *clk;
-@@ -54,6 +55,30 @@ struct davinci_audio_dev {
- 	/* McASP FIFO related */
- 	u8	txnumevt;
- 	u8	rxnumevt;
-+
-+	/* backup related */
-+	unsigned int *xrsrctl;
-+	unsigned int pfunc;
-+	unsigned int pdir;
-+
-+	unsigned int gblctlx;
-+	unsigned int txmask;
-+	unsigned int txfmt;
-+	unsigned int txfmctl;
-+	unsigned int aclkxctl;
-+	unsigned int ahclkxctl;
-+	unsigned int txtdm;
-+	unsigned int wfifoctl;
-+
-+	unsigned int gblctlr;
-+	unsigned int rxmask;
-+	unsigned int rxfmt;
-+	unsigned int rxfmctl;
-+	unsigned int aclkrctl;
-+	unsigned int ahclkrctl;
-+	unsigned int rxtdm;
-+	unsigned int rfifoctl;
-+
- };
- 
- #endif	/* DAVINCI_MCASP_H */
-diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
-index d5fe08c..83d5312 100644
---- a/sound/soc/davinci/davinci-pcm.c
-+++ b/sound/soc/davinci/davinci-pcm.c
-@@ -265,16 +265,18 @@ static int allocate_sram(struct snd_pcm_substream *substream, unsigned size,
- {
- 	struct snd_dma_buffer *buf = &substream->dma_buffer;
- 	struct snd_dma_buffer *iram_dma = NULL;
--	dma_addr_t iram_phys = 0;
-+	phys_addr_t iram_phys;
- 	void *iram_virt = NULL;
- 
- 	if (buf->private_data || !size)
- 		return 0;
- 
- 	ppcm->period_bytes_max = size;
--	iram_virt = sram_alloc(size, &iram_phys);
-+	iram_virt = (void *)gen_pool_alloc(davinci_gen_pool, size);
- 	if (!iram_virt)
- 		goto exit1;
-+	iram_phys = gen_pool_virt_to_phys(davinci_gen_pool,
-+					(unsigned long)iram_virt);
- 	iram_dma = kzalloc(sizeof(*iram_dma), GFP_KERNEL);
- 	if (!iram_dma)
- 		goto exit2;
-@@ -286,7 +288,7 @@ static int allocate_sram(struct snd_pcm_substream *substream, unsigned size,
- 	return 0;
- exit2:
- 	if (iram_virt)
--		sram_free(iram_virt, size);
-+		gen_pool_free(davinci_gen_pool, (unsigned long)iram_virt, size);
- exit1:
- 	return -ENOMEM;
- }
-@@ -820,7 +822,8 @@ static void davinci_pcm_free(struct snd_pcm *pcm)
- 		buf->area = NULL;
- 		iram_dma = buf->private_data;
- 		if (iram_dma) {
--			sram_free(iram_dma->area, iram_dma->bytes);
-+			gen_pool_free(davinci_gen_pool,
-+			      (unsigned long)iram_dma->area, iram_dma->bytes);
- 			kfree(iram_dma);
- 		}
- 	}
-diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h
-index c0d6c9b..2c3eadd 100644
---- a/sound/soc/davinci/davinci-pcm.h
-+++ b/sound/soc/davinci/davinci-pcm.h
-@@ -13,7 +13,7 @@
- #define _DAVINCI_PCM_H
- 
- #include <mach/edma.h>
--#include <mach/asp.h>
-+#include <asm/hardware/asp.h>
- 
- 
- struct davinci_pcm_dma_params {
-diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c
-index adb372d..216e33a 100644
---- a/tools/perf/util/hist.c
-+++ b/tools/perf/util/hist.c
-@@ -230,18 +230,6 @@ struct hist_entry *__hists__add_entry(struct hists *hists,
- 		if (!cmp) {
- 			he->period += period;
- 			++he->nr_events;
--
--			/* If the map of an existing hist_entry has
--			 * become out-of-date due to an exec() or
--			 * similar, update it.  Otherwise we will
--			 * mis-adjust symbol addresses when computing
--			 * the history counter to increment.
--			 */
--			if (he->ms.map != entry->ms.map) {
--				he->ms.map = entry->ms.map;
--				if (he->ms.map)
--					he->ms.map->referenced = true;
--			}
- 			goto out;
- 		}
- 
diff --git a/patches/linux-3.2.16/series b/patches/linux-3.2.16/series
deleted file mode 100644
index c3fa90b..0000000
--- a/patches/linux-3.2.16/series
+++ /dev/null
@@ -1 +0,0 @@
-0000-arago-beaglebone.patch
diff --git a/patches/linux-3.7-rc6/0000-linux-master.patch b/patches/linux-3.7-rc6/0000-linux-master.patch
deleted file mode 100644
index d0fc85b..0000000
--- a/patches/linux-3.7-rc6/0000-linux-master.patch
+++ /dev/null
@@ -1,503 +0,0 @@
-diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
-index 1e6956a..14db93e 100644
---- a/arch/alpha/kernel/osf_sys.c
-+++ b/arch/alpha/kernel/osf_sys.c
-@@ -445,7 +445,7 @@ struct procfs_args {
-  * unhappy with OSF UFS. [CHECKME]
-  */
- static int
--osf_ufs_mount(char *dirname, struct ufs_args __user *args, int flags)
-+osf_ufs_mount(const char *dirname, struct ufs_args __user *args, int flags)
- {
- 	int retval;
- 	struct cdfs_args tmp;
-@@ -465,7 +465,7 @@ osf_ufs_mount(char *dirname, struct ufs_args __user *args, int flags)
- }
- 
- static int
--osf_cdfs_mount(char *dirname, struct cdfs_args __user *args, int flags)
-+osf_cdfs_mount(const char *dirname, struct cdfs_args __user *args, int flags)
- {
- 	int retval;
- 	struct cdfs_args tmp;
-@@ -485,7 +485,7 @@ osf_cdfs_mount(char *dirname, struct cdfs_args __user *args, int flags)
- }
- 
- static int
--osf_procfs_mount(char *dirname, struct procfs_args __user *args, int flags)
-+osf_procfs_mount(const char *dirname, struct procfs_args __user *args, int flags)
- {
- 	struct procfs_args tmp;
- 
-diff --git a/arch/m68k/include/asm/signal.h b/arch/m68k/include/asm/signal.h
-index 67e489d..2df26b5 100644
---- a/arch/m68k/include/asm/signal.h
-+++ b/arch/m68k/include/asm/signal.h
-@@ -41,7 +41,7 @@ struct k_sigaction {
- static inline void sigaddset(sigset_t *set, int _sig)
- {
- 	asm ("bfset %0{%1,#1}"
--		: "+od" (*set)
-+		: "+o" (*set)
- 		: "id" ((_sig - 1) ^ 31)
- 		: "cc");
- }
-@@ -49,7 +49,7 @@ static inline void sigaddset(sigset_t *set, int _sig)
- static inline void sigdelset(sigset_t *set, int _sig)
- {
- 	asm ("bfclr %0{%1,#1}"
--		: "+od" (*set)
-+		: "+o" (*set)
- 		: "id" ((_sig - 1) ^ 31)
- 		: "cc");
- }
-@@ -65,7 +65,7 @@ static inline int __gen_sigismember(sigset_t *set, int _sig)
- 	int ret;
- 	asm ("bfextu %1{%2,#1},%0"
- 		: "=d" (ret)
--		: "od" (*set), "id" ((_sig-1) ^ 31)
-+		: "o" (*set), "id" ((_sig-1) ^ 31)
- 		: "cc");
- 	return ret;
- }
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index b1ae480..b7078af 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -238,7 +238,7 @@ static int __devexit ahci_remove(struct platform_device *pdev)
- 	return 0;
- }
- 
--#ifdef CONFIG_PM
-+#ifdef CONFIG_PM_SLEEP
- static int ahci_suspend(struct device *dev)
- {
- 	struct ahci_platform_data *pdata = dev_get_platdata(dev);
-diff --git a/drivers/ata/libata-acpi.c b/drivers/ata/libata-acpi.c
-index fd9ecf7..5b0ba3f 100644
---- a/drivers/ata/libata-acpi.c
-+++ b/drivers/ata/libata-acpi.c
-@@ -1105,10 +1105,15 @@ static int ata_acpi_bind_device(struct ata_port *ap, struct scsi_device *sdev,
- 	struct acpi_device *acpi_dev;
- 	struct acpi_device_power_state *states;
- 
--	if (ap->flags & ATA_FLAG_ACPI_SATA)
--		ata_dev = &ap->link.device[sdev->channel];
--	else
-+	if (ap->flags & ATA_FLAG_ACPI_SATA) {
-+		if (!sata_pmp_attached(ap))
-+			ata_dev = &ap->link.device[sdev->id];
-+		else
-+			ata_dev = &ap->pmp_link[sdev->channel].device[sdev->id];
-+	}
-+	else {
- 		ata_dev = &ap->link.device[sdev->id];
-+	}
- 
- 	*handle = ata_dev_acpi_handle(ata_dev);
- 
-diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
-index 3cc7096..f46fbd3 100644
---- a/drivers/ata/libata-core.c
-+++ b/drivers/ata/libata-core.c
-@@ -2942,6 +2942,10 @@ const struct ata_timing *ata_timing_find_mode(u8 xfer_mode)
- 
- 	if (xfer_mode == t->mode)
- 		return t;
-+
-+	WARN_ONCE(true, "%s: unable to find timing for xfer_mode 0x%x\n",
-+			__func__, xfer_mode);
-+
- 	return NULL;
- }
- 
-diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c
-index 26201eb..371fd2c 100644
---- a/drivers/ata/pata_arasan_cf.c
-+++ b/drivers/ata/pata_arasan_cf.c
-@@ -317,6 +317,12 @@ static int cf_init(struct arasan_cf_dev *acdev)
- 		return ret;
- 	}
- 
-+	ret = clk_set_rate(acdev->clk, 166000000);
-+	if (ret) {
-+		dev_warn(acdev->host->dev, "clock set rate failed");
-+		return ret;
-+	}
-+
- 	spin_lock_irqsave(&acdev->host->lock, flags);
- 	/* configure CF interface clock */
- 	writel((pdata->cf_if_clk <= CF_IF_CLK_200M) ? pdata->cf_if_clk :
-@@ -908,7 +914,7 @@ static int __devexit arasan_cf_remove(struct platform_device *pdev)
- 	return 0;
- }
- 
--#ifdef CONFIG_PM
-+#ifdef CONFIG_PM_SLEEP
- static int arasan_cf_suspend(struct device *dev)
- {
- 	struct ata_host *host = dev_get_drvdata(dev);
-diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
-index 0d7c4c2..400bf1c 100644
---- a/drivers/ata/sata_highbank.c
-+++ b/drivers/ata/sata_highbank.c
-@@ -260,7 +260,7 @@ static const struct of_device_id ahci_of_match[] = {
- };
- MODULE_DEVICE_TABLE(of, ahci_of_match);
- 
--static int __init ahci_highbank_probe(struct platform_device *pdev)
-+static int __devinit ahci_highbank_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
- 	struct ahci_host_priv *hpriv;
-@@ -378,7 +378,7 @@ static int __devexit ahci_highbank_remove(struct platform_device *pdev)
- 	return 0;
- }
- 
--#ifdef CONFIG_PM
-+#ifdef CONFIG_PM_SLEEP
- static int ahci_highbank_suspend(struct device *dev)
- {
- 	struct ata_host *host = dev_get_drvdata(dev);
-diff --git a/drivers/ata/sata_svw.c b/drivers/ata/sata_svw.c
-index 44a4256..08608de 100644
---- a/drivers/ata/sata_svw.c
-+++ b/drivers/ata/sata_svw.c
-@@ -142,6 +142,39 @@ static int k2_sata_scr_write(struct ata_link *link,
- 	return 0;
- }
- 
-+static int k2_sata_softreset(struct ata_link *link,
-+			     unsigned int *class, unsigned long deadline)
-+{
-+	u8 dmactl;
-+	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
-+
-+	dmactl = readb(mmio + ATA_DMA_CMD);
-+
-+	/* Clear the start bit */
-+	if (dmactl & ATA_DMA_START) {
-+		dmactl &= ~ATA_DMA_START;
-+		writeb(dmactl, mmio + ATA_DMA_CMD);
-+	}
-+
-+	return ata_sff_softreset(link, class, deadline);
-+}
-+
-+static int k2_sata_hardreset(struct ata_link *link,
-+			     unsigned int *class, unsigned long deadline)
-+{
-+	u8 dmactl;
-+	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
-+
-+	dmactl = readb(mmio + ATA_DMA_CMD);
-+
-+	/* Clear the start bit */
-+	if (dmactl & ATA_DMA_START) {
-+		dmactl &= ~ATA_DMA_START;
-+		writeb(dmactl, mmio + ATA_DMA_CMD);
-+	}
-+
-+	return sata_sff_hardreset(link, class, deadline);
-+}
- 
- static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
- {
-@@ -346,6 +379,8 @@ static struct scsi_host_template k2_sata_sht = {
- 
- static struct ata_port_operations k2_sata_ops = {
- 	.inherits		= &ata_bmdma_port_ops,
-+	.softreset              = k2_sata_softreset,
-+	.hardreset              = k2_sata_hardreset,
- 	.sff_tf_load		= k2_sata_tf_load,
- 	.sff_tf_read		= k2_sata_tf_read,
- 	.sff_check_status	= k2_stat_check_status,
-diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
-index f11d8e3..47150f5 100644
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -466,7 +466,7 @@ config GPIO_ADP5588_IRQ
- 
- config GPIO_ADNP
- 	tristate "Avionic Design N-bit GPIO expander"
--	depends on I2C && OF
-+	depends on I2C && OF_GPIO
- 	help
- 	  This option enables support for N GPIOs found on Avionic Design
- 	  I2C GPIO expanders. The register space will be extended by powers
-diff --git a/drivers/gpio/gpio-mcp23s08.c b/drivers/gpio/gpio-mcp23s08.c
-index 0f42518..ce1c847 100644
---- a/drivers/gpio/gpio-mcp23s08.c
-+++ b/drivers/gpio/gpio-mcp23s08.c
-@@ -77,7 +77,7 @@ struct mcp23s08_driver_data {
- 
- /*----------------------------------------------------------------------*/
- 
--#ifdef CONFIG_I2C
-+#if IS_ENABLED(CONFIG_I2C)
- 
- static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg)
- {
-@@ -399,7 +399,7 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
- 		break;
- #endif /* CONFIG_SPI_MASTER */
- 
--#ifdef CONFIG_I2C
-+#if IS_ENABLED(CONFIG_I2C)
- 	case MCP_TYPE_008:
- 		mcp->ops = &mcp23008_ops;
- 		mcp->chip.ngpio = 8;
-@@ -473,7 +473,7 @@ fail:
- 
- /*----------------------------------------------------------------------*/
- 
--#ifdef CONFIG_I2C
-+#if IS_ENABLED(CONFIG_I2C)
- 
- static int __devinit mcp230xx_probe(struct i2c_client *client,
- 				    const struct i2c_device_id *id)
-diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
-index cf7afb9..be65c04 100644
---- a/drivers/gpio/gpio-mvebu.c
-+++ b/drivers/gpio/gpio-mvebu.c
-@@ -92,6 +92,11 @@ static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
- 	return mvchip->membase + GPIO_OUT_OFF;
- }
- 
-+static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
-+{
-+	return mvchip->membase + GPIO_BLINK_EN_OFF;
-+}
-+
- static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
- {
- 	return mvchip->membase + GPIO_IO_CONF_OFF;
-@@ -206,6 +211,23 @@ static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
- 	return (u >> pin) & 1;
- }
- 
-+static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
-+{
-+	struct mvebu_gpio_chip *mvchip =
-+		container_of(chip, struct mvebu_gpio_chip, chip);
-+	unsigned long flags;
-+	u32 u;
-+
-+	spin_lock_irqsave(&mvchip->lock, flags);
-+	u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
-+	if (value)
-+		u |= 1 << pin;
-+	else
-+		u &= ~(1 << pin);
-+	writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
-+	spin_unlock_irqrestore(&mvchip->lock, flags);
-+}
-+
- static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
- {
- 	struct mvebu_gpio_chip *mvchip =
-@@ -244,6 +266,7 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
- 	if (ret)
- 		return ret;
- 
-+	mvebu_gpio_blink(chip, pin, 0);
- 	mvebu_gpio_set(chip, pin, value);
- 
- 	spin_lock_irqsave(&mvchip->lock, flags);
-diff --git a/fs/file.c b/fs/file.c
-index 708d997..7cb71b9 100644
---- a/fs/file.c
-+++ b/fs/file.c
-@@ -685,7 +685,6 @@ void do_close_on_exec(struct files_struct *files)
- 	struct fdtable *fdt;
- 
- 	/* exec unshares first */
--	BUG_ON(atomic_read(&files->count) != 1);
- 	spin_lock(&files->file_lock);
- 	for (i = 0; ; i++) {
- 		unsigned long set;
-diff --git a/fs/notify/fanotify/fanotify_user.c b/fs/notify/fanotify/fanotify_user.c
-index 721d692..6fcaeb8 100644
---- a/fs/notify/fanotify/fanotify_user.c
-+++ b/fs/notify/fanotify/fanotify_user.c
-@@ -258,7 +258,8 @@ static ssize_t copy_event_to_user(struct fsnotify_group *group,
- 	if (ret)
- 		goto out_close_fd;
- 
--	fd_install(fd, f);
-+	if (fd != FAN_NOFD)
-+		fd_install(fd, f);
- 	return fanotify_event_metadata.event_len;
- 
- out_close_fd:
-diff --git a/fs/xfs/xfs_aops.c b/fs/xfs/xfs_aops.c
-index e562dd4..e57e2da 100644
---- a/fs/xfs/xfs_aops.c
-+++ b/fs/xfs/xfs_aops.c
-@@ -481,11 +481,17 @@ static inline int bio_add_buffer(struct bio *bio, struct buffer_head *bh)
-  *
-  * The fix is two passes across the ioend list - one to start writeback on the
-  * buffer_heads, and then submit them for I/O on the second pass.
-+ *
-+ * If @fail is non-zero, it means that we have a situation where some part of
-+ * the submission process has failed after we have marked paged for writeback
-+ * and unlocked them. In this situation, we need to fail the ioend chain rather
-+ * than submit it to IO. This typically only happens on a filesystem shutdown.
-  */
- STATIC void
- xfs_submit_ioend(
- 	struct writeback_control *wbc,
--	xfs_ioend_t		*ioend)
-+	xfs_ioend_t		*ioend,
-+	int			fail)
- {
- 	xfs_ioend_t		*head = ioend;
- 	xfs_ioend_t		*next;
-@@ -506,6 +512,18 @@ xfs_submit_ioend(
- 		next = ioend->io_list;
- 		bio = NULL;
- 
-+		/*
-+		 * If we are failing the IO now, just mark the ioend with an
-+		 * error and finish it. This will run IO completion immediately
-+		 * as there is only one reference to the ioend at this point in
-+		 * time.
-+		 */
-+		if (fail) {
-+			ioend->io_error = -fail;
-+			xfs_finish_ioend(ioend);
-+			continue;
-+		}
-+
- 		for (bh = ioend->io_buffer_head; bh; bh = bh->b_private) {
- 
- 			if (!bio) {
-@@ -1060,7 +1078,18 @@ xfs_vm_writepage(
- 
- 	xfs_start_page_writeback(page, 1, count);
- 
--	if (ioend && imap_valid) {
-+	/* if there is no IO to be submitted for this page, we are done */
-+	if (!ioend)
-+		return 0;
-+
-+	ASSERT(iohead);
-+
-+	/*
-+	 * Any errors from this point onwards need tobe reported through the IO
-+	 * completion path as we have marked the initial page as under writeback
-+	 * and unlocked it.
-+	 */
-+	if (imap_valid) {
- 		xfs_off_t		end_index;
- 
- 		end_index = imap.br_startoff + imap.br_blockcount;
-@@ -1079,20 +1108,15 @@ xfs_vm_writepage(
- 				  wbc, end_index);
- 	}
- 
--	if (iohead) {
--		/*
--		 * Reserve log space if we might write beyond the on-disk
--		 * inode size.
--		 */
--		if (ioend->io_type != XFS_IO_UNWRITTEN &&
--		    xfs_ioend_is_append(ioend)) {
--			err = xfs_setfilesize_trans_alloc(ioend);
--			if (err)
--				goto error;
--		}
- 
--		xfs_submit_ioend(wbc, iohead);
--	}
-+	/*
-+	 * Reserve log space if we might write beyond the on-disk inode size.
-+	 */
-+	err = 0;
-+	if (ioend->io_type != XFS_IO_UNWRITTEN && xfs_ioend_is_append(ioend))
-+		err = xfs_setfilesize_trans_alloc(ioend);
-+
-+	xfs_submit_ioend(wbc, iohead, err);
- 
- 	return 0;
- 
-diff --git a/fs/xfs/xfs_attr_leaf.c b/fs/xfs/xfs_attr_leaf.c
-index d330111..70eec18 100644
---- a/fs/xfs/xfs_attr_leaf.c
-+++ b/fs/xfs/xfs_attr_leaf.c
-@@ -1291,6 +1291,7 @@ xfs_attr_leaf_rebalance(xfs_da_state_t *state, xfs_da_state_blk_t *blk1,
- 	leaf2 = blk2->bp->b_addr;
- 	ASSERT(leaf1->hdr.info.magic == cpu_to_be16(XFS_ATTR_LEAF_MAGIC));
- 	ASSERT(leaf2->hdr.info.magic == cpu_to_be16(XFS_ATTR_LEAF_MAGIC));
-+	ASSERT(leaf2->hdr.count == 0);
- 	args = state->args;
- 
- 	trace_xfs_attr_leaf_rebalance(args);
-@@ -1361,6 +1362,7 @@ xfs_attr_leaf_rebalance(xfs_da_state_t *state, xfs_da_state_blk_t *blk1,
- 		 * I assert that since all callers pass in an empty
- 		 * second buffer, this code should never execute.
- 		 */
-+		ASSERT(0);
- 
- 		/*
- 		 * Figure the total bytes to be added to the destination leaf.
-@@ -1422,10 +1424,24 @@ xfs_attr_leaf_rebalance(xfs_da_state_t *state, xfs_da_state_blk_t *blk1,
- 			args->index2 = 0;
- 			args->blkno2 = blk2->blkno;
- 		} else {
-+			/*
-+			 * On a double leaf split, the original attr location
-+			 * is already stored in blkno2/index2, so don't
-+			 * overwrite it overwise we corrupt the tree.
-+			 */
- 			blk2->index = blk1->index
- 				    - be16_to_cpu(leaf1->hdr.count);
--			args->index = args->index2 = blk2->index;
--			args->blkno = args->blkno2 = blk2->blkno;
-+			args->index = blk2->index;
-+			args->blkno = blk2->blkno;
-+			if (!state->extravalid) {
-+				/*
-+				 * set the new attr location to match the old
-+				 * one and let the higher level split code
-+				 * decide where in the leaf to place it.
-+				 */
-+				args->index2 = blk2->index;
-+				args->blkno2 = blk2->blkno;
-+			}
- 		}
- 	} else {
- 		ASSERT(state->inleaf == 1);
-diff --git a/fs/xfs/xfs_buf.c b/fs/xfs/xfs_buf.c
-index 933b793..4b0b8dd 100644
---- a/fs/xfs/xfs_buf.c
-+++ b/fs/xfs/xfs_buf.c
-@@ -1197,9 +1197,14 @@ xfs_buf_bio_end_io(
- {
- 	xfs_buf_t		*bp = (xfs_buf_t *)bio->bi_private;
- 
--	xfs_buf_ioerror(bp, -error);
-+	/*
-+	 * don't overwrite existing errors - otherwise we can lose errors on
-+	 * buffers that require multiple bios to complete.
-+	 */
-+	if (!bp->b_error)
-+		xfs_buf_ioerror(bp, -error);
- 
--	if (!error && xfs_buf_is_vmapped(bp) && (bp->b_flags & XBF_READ))
-+	if (!bp->b_error && xfs_buf_is_vmapped(bp) && (bp->b_flags & XBF_READ))
- 		invalidate_kernel_vmap_range(bp->b_addr, xfs_buf_vmap_len(bp));
- 
- 	_xfs_buf_ioend(bp, 1);
-@@ -1279,6 +1284,11 @@ next_chunk:
- 		if (size)
- 			goto next_chunk;
- 	} else {
-+		/*
-+		 * This is guaranteed not to be the last io reference count
-+		 * because the caller (xfs_buf_iorequest) holds a count itself.
-+		 */
-+		atomic_dec(&bp->b_io_remaining);
- 		xfs_buf_ioerror(bp, EIO);
- 		bio_put(bio);
- 	}
diff --git a/patches/linux-3.7-rc6/series b/patches/linux-3.7-rc6/series
deleted file mode 100644
index 2c0930a..0000000
--- a/patches/linux-3.7-rc6/series
+++ /dev/null
@@ -1,128 +0,0 @@
-0000-linux-master.patch
-0001-video-st7735fb-add-st7735-framebuffer-driver.patch
-0002-regulator-tps65910-fix-BUG_ON-shown-with-vrtc-regula.patch
-0003-dmaengine-add-helper-function-to-request-a-slave-DMA.patch
-0004-of-Add-generic-device-tree-DMA-helpers.patch
-0005-of-dma-fix-build-break-for-CONFIG_OF.patch
-0006-of-dma-fix-typos-in-generic-dma-binding-definition.patch
-0007-dmaengine-fix-build-failure-due-to-missing-semi-colo.patch
-0008-dmaengine-edma-fix-slave-config-dependency-on-direct.patch
-0009-ARM-davinci-move-private-EDMA-API-to-arm-common.patch
-0010-ARM-edma-remove-unused-transfer-controller-handlers.patch
-0011-ARM-edma-add-DT-and-runtime-PM-support-for-AM33XX.patch
-0012-ARM-edma-add-AM33XX-crossbar-event-support.patch
-0013-dmaengine-edma-enable-build-for-AM33XX.patch
-0014-dmaengine-edma-Add-TI-EDMA-device-tree-binding.patch
-0015-ARM-dts-add-AM33XX-EDMA-support.patch
-0016-dmaengine-add-dma_request_slave_channel_compat.patch
-0017-mmc-omap_hsmmc-convert-to-dma_request_slave_channel_.patch
-0018-mmc-omap_hsmmc-limit-max_segs-with-the-EDMA-DMAC.patch
-0019-mmc-omap_hsmmc-add-generic-DMA-request-support-to-th.patch
-0020-ARM-dts-add-AM33XX-MMC-support.patch
-0021-spi-omap2-mcspi-convert-to-dma_request_slave_channel.patch
-0022-spi-omap2-mcspi-add-generic-DMA-request-support-to-t.patch
-0023-ARM-dts-add-AM33XX-SPI-support.patch
-0024-Documentation-bindings-add-spansion.patch
-0025-ARM-dts-add-BeagleBone-Adafruit-1.8-LCD-support.patch
-0026-misc-add-gpevt-driver.patch
-0027-ARM-dts-add-BeagleBone-gpevt-support.patch
-0028-ARM-configs-working-AM33XX-edma-dmaengine-defconfig.patch
-0029-ARM-configs-working-da850-edma-dmaengine-defconfig.patch
-0030-misc-gpevt-null-terminate-the-of_match_table.patch
-0031-proposed-probe-fix-works-for-me-on-evm.patch
-0033-ARM-OMAP3-hwmod-Add-AM33XX-HWMOD-data-for-davinci_md.patch
-0034-net-davinci_mdio-Fix-type-mistake-in-calling-runtime.patch
-0035-net-cpsw-Add-parent-child-relation-support-between-c.patch
-0036-arm-dts-am33xx-Add-cpsw-and-mdio-module-nodes-for-AM.patch
-0038-i2c-pinctrl-ify-i2c-omap.c.patch
-0039-arm-dts-AM33XX-Configure-pinmuxs-for-user-leds-contr.patch
-0040-beaglebone-DT-set-default-triggers-for-LEDS.patch
-0041-beaglebone-add-a-cpu-led-trigger.patch
-0043-arm-dts-AM33XX-Add-device-tree-OPP-table.patch
-0045-input-TSC-ti_tscadc-Correct-register-usage.patch
-0046-input-TSC-ti_tscadc-Add-Step-configuration-as-platfo.patch
-0047-input-TSC-ti_tscadc-set-FIFO0-threshold-Interrupt.patch
-0048-input-TSC-ti_tscadc-Remove-definition-of-End-Of-Inte.patch
-0049-input-TSC-ti_tscadc-Rename-the-existing-touchscreen-.patch
-0050-MFD-ti_tscadc-Add-support-for-TI-s-TSC-ADC-MFDevice.patch
-0051-input-TSC-ti_tsc-Convert-TSC-into-a-MFDevice.patch
-0052-IIO-ADC-tiadc-Add-support-of-TI-s-ADC-driver.patch
-0053-input-ti_am335x_tsc-Make-steps-enable-configurable.patch
-0054-input-ti_am335x_tsc-Order-of-TSC-wires-connect-made-.patch
-0055-input-ti_am335x_tsc-Add-variance-filters.patch
-0056-ti_tscadc-Update-with-IIO-map-interface-deal-with-pa.patch
-0057-ti_tscadc-Match-mfd-sub-devices-to-regmap-interface.patch
-0059-ARM-OMAP3-hwmod-Corrects-resource-data-for-PWM-devic.patch
-0060-pwm_backlight-Add-device-tree-support-for-Low-Thresh.patch
-0061-pwm-pwm-tiecap-Add-device-tree-binding-support-in-AP.patch
-0062-Control-module-EHRPWM-clk-enabling.patch
-0063-pwm-pwm-tiecap-Enable-clock-gating.patch
-0064-PWM-ti-ehrpwm-fix-up-merge-conflict.patch
-0065-pwm-pwm_test-Driver-support-for-PWM-module-testing.patch
-0066-arm-dts-DT-support-for-EHRPWM-and-ECAP-device.patch
-0067-pwm-pwm-tiehrpwm-Add-device-tree-binding-support-EHR.patch
-0069-pinctrl-pinctrl-single-must-be-initialized-early.patch
-0070-Bone-DTS-working-i2c2-i2c3-in-the-tree.patch
-0071-am33xx-Convert-I2C-from-omap-to-am33xx-names.patch
-0072-beaglebone-fix-backlight-entry-in-DT.patch
-0074-Shut-up-musb.patch
-0075-musb-Fix-crashes-and-other-weirdness.patch
-0076-musb-revert-parts-of-032ec49f.patch
-0077-usb-musb-dsps-get-the-PHY-using-phandle-api.patch
-0078-drivers-usb-otg-add-device-tree-support-to-otg-libra.patch
-0079-usb-otg-nop-add-dt-support.patch
-0080-usb-musb-dsps-add-phy-control-logic-to-glue.patch
-0081-usb-musb-dsps-enable-phy-control-for-am335x.patch
-0082-ARM-am33xx-fix-mem-regions-in-USB-hwmod.patch
-0084-omap2-clk-Add-missing-lcdc-clock-definition.patch
-0085-da8xx-Allow-use-by-am33xx-based-devices.patch
-0086-da8xx-Fix-revision-check-on-the-da8xx-driver.patch
-0087-da8xx-De-constify-members-in-the-platform-config.patch
-0088-da8xx-Add-standard-panel-definition.patch
-0089-da8xx-Add-CDTech_S035Q01-panel-used-by-LCD3-bone-cap.patch
-0090-da8xx-fb-add-panel-definition-for-beaglebone-LCD7-ca.patch
-0092-mmc-omap_hsmmc-Enable-HSPE-bit-for-high-speed-cards.patch
-0093-am33xx.dtsi-enable-MMC-HSPE-bit-for-all-3-controller.patch
-0094-omap-hsmmc-Correct-usage-of-of_find_node_by_name.patch
-0096-ARM-AM33XX-hwmod-Remove-wrong-INIT_NO_RESET-IDLE-fla.patch
-0098-f2fs-add-document.patch
-0099-f2fs-add-on-disk-layout.patch
-0100-f2fs-add-superblock-and-major-in-memory-structure.patch
-0101-f2fs-add-super-block-operations.patch
-0102-f2fs-add-checkpoint-operations.patch
-0103-f2fs-add-node-operations.patch
-0104-f2fs-add-segment-operations.patch
-0105-f2fs-add-file-operations.patch
-0106-f2fs-add-address-space-operations-for-data.patch
-0107-f2fs-add-core-inode-operations.patch
-0108-f2fs-add-inode-operations-for-special-inodes.patch
-0109-f2fs-add-core-directory-operations.patch
-0110-f2fs-add-xattr-and-acl-functionalities.patch
-0111-f2fs-add-garbage-collection-functions.patch
-0112-f2fs-add-recovery-routines-for-roll-forward.patch
-0113-f2fs-update-Kconfig-and-Makefile.patch
-0114-f2fs-gc.h-make-should_do_checkpoint-inline.patch
-0115-f2fs-move-statistics-code-into-one-file.patch
-0116-f2fs-move-proc-files-to-debugfs.patch
-0117-f2fs-compile-fix.patch
-0119-i2c-EEPROM-Export-memory-accessor.patch
-0120-omap-Export-omap_hwmod_lookup-omap_device_build-omap.patch
-0121-gpio-keys-Pinctrl-fy.patch
-0122-tps65217-Allow-placement-elsewhere-than-parent-mfd-d.patch
-0123-pwm-export-of_pwm_request.patch
-0124-i2c-Export-capability-to-probe-devices.patch
-0125-pwm-backlight-Pinctrl-fy.patch
-0126-spi-Export-OF-interfaces-for-capebus-use.patch
-0127-w1-gpio-Pinctrl-fy.patch
-0128-w1-gpio-Simplify-get-rid-of-defines.patch
-0129-arm-dt-Enable-DT-proc-updates.patch
-0130-ARM-CUSTOM-Build-a-uImage-with-dtb-already-appended.patch
-0131-beaglebone-create-a-shared-dtsi-for-beaglebone-based.patch
-0132-beaglebone-enable-emmc-for-bonelt.patch
-0133-capebus-Core-capebus-support.patch
-0134-capebus-Add-beaglebone-board-support.patch
-0135-capebus-Beaglebone-generic-board.patch
-0136-capebus-Add-beaglebone-geiger-cape.patch
-0137-capebus-Beaglebone-capebus-DT-update.patch
-0138-beaglebone-Update-default-config-for-capebus.patch
-0139-capebus-Geiger-Cape-config-bugfixs.patch
diff --git a/patches/linux-3.7-rc6/0001-video-st7735fb-add-st7735-framebuffer-driver.patch b/patches/linux-3.7/0001-video-st7735fb-add-st7735-framebuffer-driver.patch
index 70cfb9c..20d32c9 100644
--- a/patches/linux-3.7-rc6/0001-video-st7735fb-add-st7735-framebuffer-driver.patch
+++ b/patches/linux-3.7/0001-video-st7735fb-add-st7735-framebuffer-driver.patch
@@ -1,4 +1,3 @@
-From f24d7d872ab89aa8aec4ea0bf36c1c612906907b Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Tue, 11 Sep 2012 15:30:10 -0400
 Subject: [PATCH] video: st7735fb: add st7735 framebuffer driver
diff --git a/patches/linux-3.7-rc6/0002-regulator-tps65910-fix-BUG_ON-shown-with-vrtc-regula.patch b/patches/linux-3.7/0002-regulator-tps65910-fix-BUG_ON-shown-with-vrtc-regula.patch
index d96dd9b..e7cc14d 100644
--- a/patches/linux-3.7-rc6/0002-regulator-tps65910-fix-BUG_ON-shown-with-vrtc-regula.patch
+++ b/patches/linux-3.7/0002-regulator-tps65910-fix-BUG_ON-shown-with-vrtc-regula.patch
@@ -1,4 +1,3 @@
-From 99ab21ddea0d88d7d60a2210c0aa7c582571fb5b Mon Sep 17 00:00:00 2001
 From: "AnilKumar, Chimata" <anilkumar@ti.com>
 Date: Mon, 15 Oct 2012 12:15:58 +0000
 Subject: [PATCH] regulator: tps65910: fix BUG_ON() shown with vrtc regulator
diff --git a/patches/linux-3.7-rc6/0003-dmaengine-add-helper-function-to-request-a-slave-DMA.patch b/patches/linux-3.7/0003-dmaengine-add-helper-function-to-request-a-slave-DMA.patch
index 78b2693..3368d21 100644
--- a/patches/linux-3.7-rc6/0003-dmaengine-add-helper-function-to-request-a-slave-DMA.patch
+++ b/patches/linux-3.7/0003-dmaengine-add-helper-function-to-request-a-slave-DMA.patch
@@ -1,4 +1,3 @@
-From 510f4fd7a8ba825a4b376c27ba86fa5b976fb974 Mon Sep 17 00:00:00 2001
 From: Jon Hunter <jon-hunter@ti.com>
 Date: Fri, 14 Sep 2012 17:41:57 -0500
 Subject: [PATCH] dmaengine: add helper function to request a slave DMA
diff --git a/patches/linux-3.7-rc6/0004-of-Add-generic-device-tree-DMA-helpers.patch b/patches/linux-3.7/0004-of-Add-generic-device-tree-DMA-helpers.patch
index fb08560..71a2fc0 100644
--- a/patches/linux-3.7-rc6/0004-of-Add-generic-device-tree-DMA-helpers.patch
+++ b/patches/linux-3.7/0004-of-Add-generic-device-tree-DMA-helpers.patch
@@ -1,4 +1,3 @@
-From 21793273a36ca45c4162f41978a3ec8eb1984c42 Mon Sep 17 00:00:00 2001
 From: Jon Hunter <jon-hunter@ti.com>
 Date: Fri, 14 Sep 2012 17:41:56 -0500
 Subject: [PATCH] of: Add generic device tree DMA helpers
diff --git a/patches/linux-3.7-rc6/0005-of-dma-fix-build-break-for-CONFIG_OF.patch b/patches/linux-3.7/0005-of-dma-fix-build-break-for-CONFIG_OF.patch
index 1801a9c..04d864c 100644
--- a/patches/linux-3.7-rc6/0005-of-dma-fix-build-break-for-CONFIG_OF.patch
+++ b/patches/linux-3.7/0005-of-dma-fix-build-break-for-CONFIG_OF.patch
@@ -1,4 +1,3 @@
-From 7ea168ca4862bc9a803bfd9e1415c1b71f6349e0 Mon Sep 17 00:00:00 2001
 From: Vinod Koul <vinod.koul@linux.intel.com>
 Date: Tue, 25 Sep 2012 09:57:36 +0530
 Subject: [PATCH] of: dma- fix build break for !CONFIG_OF
diff --git a/patches/linux-3.7-rc6/0006-of-dma-fix-typos-in-generic-dma-binding-definition.patch b/patches/linux-3.7/0006-of-dma-fix-typos-in-generic-dma-binding-definition.patch
index a92573f..bfbfad4 100644
--- a/patches/linux-3.7-rc6/0006-of-dma-fix-typos-in-generic-dma-binding-definition.patch
+++ b/patches/linux-3.7/0006-of-dma-fix-typos-in-generic-dma-binding-definition.patch
@@ -1,4 +1,3 @@
-From b455947ab768efeaca48e47746206b830f13b04a Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Wed, 19 Sep 2012 10:49:48 -0400
 Subject: [PATCH] of: dma: fix typos in generic dma binding definition
diff --git a/patches/linux-3.7-rc6/0007-dmaengine-fix-build-failure-due-to-missing-semi-colo.patch b/patches/linux-3.7/0007-dmaengine-fix-build-failure-due-to-missing-semi-colo.patch
index e49b823..52ab593 100644
--- a/patches/linux-3.7-rc6/0007-dmaengine-fix-build-failure-due-to-missing-semi-colo.patch
+++ b/patches/linux-3.7/0007-dmaengine-fix-build-failure-due-to-missing-semi-colo.patch
@@ -1,4 +1,3 @@
-From ae2d9b7b36e62046f28b0b9092e68fcc1f84a96a Mon Sep 17 00:00:00 2001
 From: Vinod Koul <vinod.koul@linux.intel.com>
 Date: Tue, 25 Sep 2012 16:18:55 +0530
 Subject: [PATCH] dmaengine: fix build failure due to missing semi-colon
diff --git a/patches/linux-3.7-rc6/0008-dmaengine-edma-fix-slave-config-dependency-on-direct.patch b/patches/linux-3.7/0008-dmaengine-edma-fix-slave-config-dependency-on-direct.patch
index 41e012f..6e695b9 100644
--- a/patches/linux-3.7-rc6/0008-dmaengine-edma-fix-slave-config-dependency-on-direct.patch
+++ b/patches/linux-3.7/0008-dmaengine-edma-fix-slave-config-dependency-on-direct.patch
@@ -1,4 +1,3 @@
-From 10e28276286e519e3be5d9ffb783bf77d48fc3ed Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Tue, 18 Sep 2012 18:57:15 +0000
 Subject: [PATCH] dmaengine: edma: fix slave config dependency on direction
diff --git a/patches/linux-3.7-rc6/0009-ARM-davinci-move-private-EDMA-API-to-arm-common.patch b/patches/linux-3.7/0009-ARM-davinci-move-private-EDMA-API-to-arm-common.patch
index f766eb2..5581ab2 100644
--- a/patches/linux-3.7-rc6/0009-ARM-davinci-move-private-EDMA-API-to-arm-common.patch
+++ b/patches/linux-3.7/0009-ARM-davinci-move-private-EDMA-API-to-arm-common.patch
@@ -1,4 +1,3 @@
-From 11d28a7c4cf53a9d5eff3d01ff5f7a2436d29790 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Wed, 22 Aug 2012 09:24:24 -0400
 Subject: [PATCH] ARM: davinci: move private EDMA API to arm/common
@@ -42,10 +41,10 @@ Signed-off-by: Matt Porter <mporter@ti.com>
  create mode 100644 include/linux/platform_data/edma.h
 
 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index ade7e92..6737b69 100644
+index 9759fec..be22f68 100644
 --- a/arch/arm/Kconfig
 +++ b/arch/arm/Kconfig
-@@ -924,6 +924,7 @@ config ARCH_DAVINCI
+@@ -925,6 +925,7 @@ config ARCH_DAVINCI
  	select GENERIC_IRQ_CHIP
  	select HAVE_IDE
  	select NEED_MACH_GPIO_H
@@ -1796,7 +1795,7 @@ index b680c83..a611716 100644
  #include <mach/mux.h>
  #include <mach/irqs.h>
 diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
-index cd0c8b1..90f5639 100644
+index 14e9947b..5b0a263 100644
 --- a/arch/arm/mach-davinci/dm644x.c
 +++ b/arch/arm/mach-davinci/dm644x.c
 @@ -12,11 +12,11 @@
diff --git a/patches/linux-3.7-rc6/0010-ARM-edma-remove-unused-transfer-controller-handlers.patch b/patches/linux-3.7/0010-ARM-edma-remove-unused-transfer-controller-handlers.patch
index f05c02a..05f7b56 100644
--- a/patches/linux-3.7-rc6/0010-ARM-edma-remove-unused-transfer-controller-handlers.patch
+++ b/patches/linux-3.7/0010-ARM-edma-remove-unused-transfer-controller-handlers.patch
@@ -1,4 +1,3 @@
-From 9b14772219c6edaf900645ad688abf8591f6c6a7 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Wed, 22 Aug 2012 09:31:49 -0400
 Subject: [PATCH] ARM: edma: remove unused transfer controller handlers
diff --git a/patches/linux-3.7-rc6/0011-ARM-edma-add-DT-and-runtime-PM-support-for-AM33XX.patch b/patches/linux-3.7/0011-ARM-edma-add-DT-and-runtime-PM-support-for-AM33XX.patch
index e197daf..440d17a 100644
--- a/patches/linux-3.7-rc6/0011-ARM-edma-add-DT-and-runtime-PM-support-for-AM33XX.patch
+++ b/patches/linux-3.7/0011-ARM-edma-add-DT-and-runtime-PM-support-for-AM33XX.patch
@@ -1,4 +1,3 @@
-From 98622c01c7b234d869066035776c906feff18a53 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 6 Sep 2012 17:40:42 -0400
 Subject: [PATCH] ARM: edma: add DT and runtime PM support for AM33XX
@@ -562,7 +561,7 @@ index a611716..801e162 100644
  	/* {event queue no, Priority} */
  	{0, 7},
 diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
-index 90f5639..4799fd9 100644
+index 5b0a263..d4e04c5 100644
 --- a/arch/arm/mach-davinci/dm644x.c
 +++ b/arch/arm/mach-davinci/dm644x.c
 @@ -497,7 +497,7 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
diff --git a/patches/linux-3.7-rc6/0012-ARM-edma-add-AM33XX-crossbar-event-support.patch b/patches/linux-3.7/0012-ARM-edma-add-AM33XX-crossbar-event-support.patch
index 87ee271..e4177fd 100644
--- a/patches/linux-3.7-rc6/0012-ARM-edma-add-AM33XX-crossbar-event-support.patch
+++ b/patches/linux-3.7/0012-ARM-edma-add-AM33XX-crossbar-event-support.patch
@@ -1,4 +1,3 @@
-From 824b8ee82f35528d0ab1a6cf66973694a694100c Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Wed, 17 Oct 2012 16:13:17 -0400
 Subject: [PATCH] ARM: edma: add AM33XX crossbar event support
diff --git a/patches/linux-3.7-rc6/0013-dmaengine-edma-enable-build-for-AM33XX.patch b/patches/linux-3.7/0013-dmaengine-edma-enable-build-for-AM33XX.patch
index 7e7fe48..b3d58ab 100644
--- a/patches/linux-3.7-rc6/0013-dmaengine-edma-enable-build-for-AM33XX.patch
+++ b/patches/linux-3.7/0013-dmaengine-edma-enable-build-for-AM33XX.patch
@@ -1,4 +1,3 @@
-From b0668c88fe5e7a8df4d1c8944673c2af2065d350 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 6 Sep 2012 17:42:35 -0400
 Subject: [PATCH] dmaengine: edma: enable build for AM33XX
diff --git a/patches/linux-3.7-rc6/0014-dmaengine-edma-Add-TI-EDMA-device-tree-binding.patch b/patches/linux-3.7/0014-dmaengine-edma-Add-TI-EDMA-device-tree-binding.patch
index 83a5c93..0b78112 100644
--- a/patches/linux-3.7-rc6/0014-dmaengine-edma-Add-TI-EDMA-device-tree-binding.patch
+++ b/patches/linux-3.7/0014-dmaengine-edma-Add-TI-EDMA-device-tree-binding.patch
@@ -1,4 +1,3 @@
-From 406954740157c140ce175107e437d15f5d74a1ba Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 20 Sep 2012 07:46:04 -0400
 Subject: [PATCH] dmaengine: edma: Add TI EDMA device tree binding
diff --git a/patches/linux-3.7-rc6/0015-ARM-dts-add-AM33XX-EDMA-support.patch b/patches/linux-3.7/0015-ARM-dts-add-AM33XX-EDMA-support.patch
index 85a10ac..fc3dca8 100644
--- a/patches/linux-3.7-rc6/0015-ARM-dts-add-AM33XX-EDMA-support.patch
+++ b/patches/linux-3.7/0015-ARM-dts-add-AM33XX-EDMA-support.patch
@@ -1,4 +1,3 @@
-From 0a343eb46473df01ad66d7975f4b17ee8a0ba833 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Wed, 10 Oct 2012 10:01:33 -0400
 Subject: [PATCH] ARM: dts: add AM33XX EDMA support
diff --git a/patches/linux-3.7-rc6/0016-dmaengine-add-dma_request_slave_channel_compat.patch b/patches/linux-3.7/0016-dmaengine-add-dma_request_slave_channel_compat.patch
index cc70c89..776ddf8 100644
--- a/patches/linux-3.7-rc6/0016-dmaengine-add-dma_request_slave_channel_compat.patch
+++ b/patches/linux-3.7/0016-dmaengine-add-dma_request_slave_channel_compat.patch
@@ -1,4 +1,3 @@
-From 4b29b8fc42201109ebfe6dc14e5b778f33f8331f Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 11 Oct 2012 12:58:44 -0400
 Subject: [PATCH] dmaengine: add dma_request_slave_channel_compat()
diff --git a/patches/linux-3.7-rc6/0017-mmc-omap_hsmmc-convert-to-dma_request_slave_channel_.patch b/patches/linux-3.7/0017-mmc-omap_hsmmc-convert-to-dma_request_slave_channel_.patch
index 60efa50..519d7c7 100644
--- a/patches/linux-3.7-rc6/0017-mmc-omap_hsmmc-convert-to-dma_request_slave_channel_.patch
+++ b/patches/linux-3.7/0017-mmc-omap_hsmmc-convert-to-dma_request_slave_channel_.patch
@@ -1,4 +1,3 @@
-From eac7b54ca639d29ca6e2bdf421aa609b6a17ca0f Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 6 Sep 2012 17:47:21 -0400
 Subject: [PATCH] mmc: omap_hsmmc: convert to
diff --git a/patches/linux-3.7-rc6/0018-mmc-omap_hsmmc-limit-max_segs-with-the-EDMA-DMAC.patch b/patches/linux-3.7/0018-mmc-omap_hsmmc-limit-max_segs-with-the-EDMA-DMAC.patch
index 36ab8ae..cf10fa8 100644
--- a/patches/linux-3.7-rc6/0018-mmc-omap_hsmmc-limit-max_segs-with-the-EDMA-DMAC.patch
+++ b/patches/linux-3.7/0018-mmc-omap_hsmmc-limit-max_segs-with-the-EDMA-DMAC.patch
@@ -1,4 +1,3 @@
-From f64e173af16724e4dbdc727821ae060a3fab459e Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 20 Sep 2012 08:55:41 -0400
 Subject: [PATCH] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
diff --git a/patches/linux-3.7-rc6/0019-mmc-omap_hsmmc-add-generic-DMA-request-support-to-th.patch b/patches/linux-3.7/0019-mmc-omap_hsmmc-add-generic-DMA-request-support-to-th.patch
index e01d8fe..ff2892f 100644
--- a/patches/linux-3.7-rc6/0019-mmc-omap_hsmmc-add-generic-DMA-request-support-to-th.patch
+++ b/patches/linux-3.7/0019-mmc-omap_hsmmc-add-generic-DMA-request-support-to-th.patch
@@ -1,4 +1,3 @@
-From fc9e3599817da4fb14ed9e9bb876cb4dc901a47c Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 20 Sep 2012 07:47:47 -0400
 Subject: [PATCH] mmc: omap_hsmmc: add generic DMA request support to the DT
diff --git a/patches/linux-3.7-rc6/0020-ARM-dts-add-AM33XX-MMC-support.patch b/patches/linux-3.7/0020-ARM-dts-add-AM33XX-MMC-support.patch
index 9a2423c..9b8506d 100644
--- a/patches/linux-3.7-rc6/0020-ARM-dts-add-AM33XX-MMC-support.patch
+++ b/patches/linux-3.7/0020-ARM-dts-add-AM33XX-MMC-support.patch
@@ -1,4 +1,3 @@
-From 2eafee121ee4f7c3175da0fc3415c8c79474beee Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Wed, 10 Oct 2012 15:14:03 -0400
 Subject: [PATCH] ARM: dts: add AM33XX MMC support
diff --git a/patches/linux-3.7-rc6/0021-spi-omap2-mcspi-convert-to-dma_request_slave_channel.patch b/patches/linux-3.7/0021-spi-omap2-mcspi-convert-to-dma_request_slave_channel.patch
index 1636f82..d4081a5 100644
--- a/patches/linux-3.7-rc6/0021-spi-omap2-mcspi-convert-to-dma_request_slave_channel.patch
+++ b/patches/linux-3.7/0021-spi-omap2-mcspi-convert-to-dma_request_slave_channel.patch
@@ -1,4 +1,3 @@
-From 588d993abc0c750ebe9a9547ead82d07e74127ad Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 20 Sep 2012 00:37:54 -0400
 Subject: [PATCH] spi: omap2-mcspi: convert to
diff --git a/patches/linux-3.7-rc6/0022-spi-omap2-mcspi-add-generic-DMA-request-support-to-t.patch b/patches/linux-3.7/0022-spi-omap2-mcspi-add-generic-DMA-request-support-to-t.patch
index 1f52e69..e6baf04 100644
--- a/patches/linux-3.7-rc6/0022-spi-omap2-mcspi-add-generic-DMA-request-support-to-t.patch
+++ b/patches/linux-3.7/0022-spi-omap2-mcspi-add-generic-DMA-request-support-to-t.patch
@@ -1,4 +1,3 @@
-From b51a573d3fa257c4dad23baf9d9ffe8aea220b11 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 20 Sep 2012 09:21:16 -0400
 Subject: [PATCH] spi: omap2-mcspi: add generic DMA request support to the DT
diff --git a/patches/linux-3.7-rc6/0023-ARM-dts-add-AM33XX-SPI-support.patch b/patches/linux-3.7/0023-ARM-dts-add-AM33XX-SPI-support.patch
index 8388d26..d8c8d74 100644
--- a/patches/linux-3.7-rc6/0023-ARM-dts-add-AM33XX-SPI-support.patch
+++ b/patches/linux-3.7/0023-ARM-dts-add-AM33XX-SPI-support.patch
@@ -1,4 +1,3 @@
-From 3fa0e6f705cc2725d267ed19b0c76541e9d7a96b Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 11 Oct 2012 08:51:46 -0400
 Subject: [PATCH] ARM: dts: add AM33XX SPI support
diff --git a/patches/linux-3.7-rc6/0024-Documentation-bindings-add-spansion.patch b/patches/linux-3.7/0024-Documentation-bindings-add-spansion.patch
index 8287397..a603210 100644
--- a/patches/linux-3.7-rc6/0024-Documentation-bindings-add-spansion.patch
+++ b/patches/linux-3.7/0024-Documentation-bindings-add-spansion.patch
@@ -1,4 +1,3 @@
-From edd68fd797edcb247d1bcfc8f9a6dd843af35843 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Wed, 17 Oct 2012 17:12:09 -0400
 Subject: [PATCH] Documentation: bindings: add spansion
diff --git a/patches/linux-3.7-rc6/0025-ARM-dts-add-BeagleBone-Adafruit-1.8-LCD-support.patch b/patches/linux-3.7/0025-ARM-dts-add-BeagleBone-Adafruit-1.8-LCD-support.patch
index a31b2a9..dc40167 100644
--- a/patches/linux-3.7-rc6/0025-ARM-dts-add-BeagleBone-Adafruit-1.8-LCD-support.patch
+++ b/patches/linux-3.7/0025-ARM-dts-add-BeagleBone-Adafruit-1.8-LCD-support.patch
@@ -1,4 +1,3 @@
-From 03118b0a0ad5e5249b94d87f68c1f4694155b78a Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 11 Oct 2012 08:52:54 -0400
 Subject: [PATCH] ARM: dts: add BeagleBone Adafruit 1.8 LCD support
diff --git a/patches/linux-3.7-rc6/0026-misc-add-gpevt-driver.patch b/patches/linux-3.7/0026-misc-add-gpevt-driver.patch
index 41df270..757e48c 100644
--- a/patches/linux-3.7-rc6/0026-misc-add-gpevt-driver.patch
+++ b/patches/linux-3.7/0026-misc-add-gpevt-driver.patch
@@ -1,4 +1,3 @@
-From 041c51572bd5c7eb9e2f581e223fd4cfa4921656 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Wed, 17 Oct 2012 10:48:22 -0400
 Subject: [PATCH] misc: add gpevt driver
diff --git a/patches/linux-3.7-rc6/0027-ARM-dts-add-BeagleBone-gpevt-support.patch b/patches/linux-3.7/0027-ARM-dts-add-BeagleBone-gpevt-support.patch
index 48f0f4b..1fe8639 100644
--- a/patches/linux-3.7-rc6/0027-ARM-dts-add-BeagleBone-gpevt-support.patch
+++ b/patches/linux-3.7/0027-ARM-dts-add-BeagleBone-gpevt-support.patch
@@ -1,4 +1,3 @@
-From de9cf3f43a2bc994e0c1f4d21c8b0ff63eb3dfda Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Wed, 17 Oct 2012 17:12:45 -0400
 Subject: [PATCH] ARM: dts: add BeagleBone gpevt support
diff --git a/patches/linux-3.7-rc6/0028-ARM-configs-working-AM33XX-edma-dmaengine-defconfig.patch b/patches/linux-3.7/0028-ARM-configs-working-AM33XX-edma-dmaengine-defconfig.patch
index 6f69da0..87c49dc 100644
--- a/patches/linux-3.7-rc6/0028-ARM-configs-working-AM33XX-edma-dmaengine-defconfig.patch
+++ b/patches/linux-3.7/0028-ARM-configs-working-AM33XX-edma-dmaengine-defconfig.patch
@@ -1,4 +1,3 @@
-From 21a9326ab1c0c135deee4490c2a5f8a07140c318 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Fri, 12 Oct 2012 16:52:55 -0400
 Subject: [PATCH] ARM: configs: working AM33XX edma dmaengine defconfig
diff --git a/patches/linux-3.7-rc6/0029-ARM-configs-working-da850-edma-dmaengine-defconfig.patch b/patches/linux-3.7/0029-ARM-configs-working-da850-edma-dmaengine-defconfig.patch
index b30da0c..17a54af 100644
--- a/patches/linux-3.7-rc6/0029-ARM-configs-working-da850-edma-dmaengine-defconfig.patch
+++ b/patches/linux-3.7/0029-ARM-configs-working-da850-edma-dmaengine-defconfig.patch
@@ -1,4 +1,3 @@
-From 3e2a5b5bd5dc697a3c060f6527f22543be1be880 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Mon, 15 Oct 2012 10:17:43 -0400
 Subject: [PATCH] ARM: configs: working da850 edma dmaengine defconfig
diff --git a/patches/linux-3.7-rc6/0030-misc-gpevt-null-terminate-the-of_match_table.patch b/patches/linux-3.7/0030-misc-gpevt-null-terminate-the-of_match_table.patch
index 5edd618..eb61b79 100644
--- a/patches/linux-3.7-rc6/0030-misc-gpevt-null-terminate-the-of_match_table.patch
+++ b/patches/linux-3.7/0030-misc-gpevt-null-terminate-the-of_match_table.patch
@@ -1,4 +1,3 @@
-From 07a646411ade49a270c87332d482f4ac6f0ecfba Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Thu, 18 Oct 2012 10:29:57 -0400
 Subject: [PATCH] misc: gpevt: null terminate the of_match_table
diff --git a/patches/linux-3.7-rc6/0031-proposed-probe-fix-works-for-me-on-evm.patch b/patches/linux-3.7/0031-proposed-probe-fix-works-for-me-on-evm.patch
index db77068..3ba2b8f 100644
--- a/patches/linux-3.7-rc6/0031-proposed-probe-fix-works-for-me-on-evm.patch
+++ b/patches/linux-3.7/0031-proposed-probe-fix-works-for-me-on-evm.patch
@@ -1,4 +1,3 @@
-From 93ae8a949f58bbd1d8c77baf116c5db2654d11c6 Mon Sep 17 00:00:00 2001
 From: Matt Porter <mporter@ti.com>
 Date: Fri, 19 Oct 2012 11:24:40 -0400
 Subject: [PATCH] proposed probe fix - works for me on evm
diff --git a/patches/linux-3.7-rc6/0033-ARM-OMAP3-hwmod-Add-AM33XX-HWMOD-data-for-davinci_md.patch b/patches/linux-3.7/0033-ARM-OMAP3-hwmod-Add-AM33XX-HWMOD-data-for-davinci_md.patch
index 37d6082..0202d23 100644
--- a/patches/linux-3.7-rc6/0033-ARM-OMAP3-hwmod-Add-AM33XX-HWMOD-data-for-davinci_md.patch
+++ b/patches/linux-3.7/0033-ARM-OMAP3-hwmod-Add-AM33XX-HWMOD-data-for-davinci_md.patch
@@ -1,4 +1,3 @@
-From 8889710c8dc2c6e67fec6124bb2c397bac5ae43d Mon Sep 17 00:00:00 2001
 From: Mugunthan V N <mugunthanvnm@ti.com>
 Date: Tue, 5 Jun 2012 13:18:01 +0530
 Subject: [PATCH] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio
diff --git a/patches/linux-3.7-rc6/0034-net-davinci_mdio-Fix-type-mistake-in-calling-runtime.patch b/patches/linux-3.7/0034-net-davinci_mdio-Fix-type-mistake-in-calling-runtime.patch
index a15b51d..69872f5 100644
--- a/patches/linux-3.7-rc6/0034-net-davinci_mdio-Fix-type-mistake-in-calling-runtime.patch
+++ b/patches/linux-3.7/0034-net-davinci_mdio-Fix-type-mistake-in-calling-runtime.patch
@@ -1,4 +1,3 @@
-From 009cf7834fb1707dd687934131d70750d037c376 Mon Sep 17 00:00:00 2001
 From: Vaibhav Hiremath <hvaibhav@ti.com>
 Date: Mon, 3 Sep 2012 21:14:52 +0530
 Subject: [PATCH] net: davinci_mdio: Fix type mistake in calling runtime-pm
diff --git a/patches/linux-3.7-rc6/0035-net-cpsw-Add-parent-child-relation-support-between-c.patch b/patches/linux-3.7/0035-net-cpsw-Add-parent-child-relation-support-between-c.patch
index 47f1029..a25eaac 100644
--- a/patches/linux-3.7-rc6/0035-net-cpsw-Add-parent-child-relation-support-between-c.patch
+++ b/patches/linux-3.7/0035-net-cpsw-Add-parent-child-relation-support-between-c.patch
@@ -1,4 +1,3 @@
-From a96742d124907b9056fadaa90590331b93ca25dc Mon Sep 17 00:00:00 2001
 From: Vaibhav Hiremath <hvaibhav@ti.com>
 Date: Mon, 3 Sep 2012 21:25:38 +0530
 Subject: [PATCH] net: cpsw: Add parent<->child relation support between cpsw
diff --git a/patches/linux-3.7-rc6/0036-arm-dts-am33xx-Add-cpsw-and-mdio-module-nodes-for-AM.patch b/patches/linux-3.7/0036-arm-dts-am33xx-Add-cpsw-and-mdio-module-nodes-for-AM.patch
index a61d47c..6b21ee5 100644
--- a/patches/linux-3.7-rc6/0036-arm-dts-am33xx-Add-cpsw-and-mdio-module-nodes-for-AM.patch
+++ b/patches/linux-3.7/0036-arm-dts-am33xx-Add-cpsw-and-mdio-module-nodes-for-AM.patch
@@ -1,4 +1,3 @@
-From bd5fdad1c484959dadf1daf6b1d433b9e1653390 Mon Sep 17 00:00:00 2001
 From: Mugunthan V N <mugunthanvnm@ti.com>
 Date: Sun, 29 Jul 2012 20:56:29 +0530
 Subject: [PATCH] arm/dts: am33xx: Add cpsw and mdio module nodes for AM33XX
diff --git a/patches/linux-3.7-rc6/0038-i2c-pinctrl-ify-i2c-omap.c.patch b/patches/linux-3.7/0038-i2c-pinctrl-ify-i2c-omap.c.patch
index e936d15..dda67a6 100644
--- a/patches/linux-3.7-rc6/0038-i2c-pinctrl-ify-i2c-omap.c.patch
+++ b/patches/linux-3.7/0038-i2c-pinctrl-ify-i2c-omap.c.patch
@@ -1,4 +1,3 @@
-From 610430c8c2229f0b70e7f52188ea7dc8c368a6d6 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Fri, 14 Sep 2012 17:51:11 +0300
 Subject: [PATCH] i2c: pinctrl-ify i2c-omap.c
@@ -10,19 +9,19 @@ Conflicts:
  1 file changed, 10 insertions(+)
 
 diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
-index db31eae..4c38aa0 100644
+index 3525c9e..b4952b7 100644
 --- a/drivers/i2c/busses/i2c-omap.c
 +++ b/drivers/i2c/busses/i2c-omap.c
-@@ -44,6 +44,8 @@
+@@ -43,6 +43,8 @@
+ #include <linux/slab.h>
  #include <linux/i2c-omap.h>
  #include <linux/pm_runtime.h>
- #include <linux/pm_qos.h>
 +#include <linux/pinctrl/consumer.h>
 +#include <linux/err.h>
  
  /* I2C controller revisions */
  #define OMAP_I2C_OMAP1_REV_2		0x20
-@@ -1064,6 +1066,7 @@ omap_i2c_probe(struct platform_device *pdev)
+@@ -1060,6 +1062,7 @@ omap_i2c_probe(struct platform_device *pdev)
  	const struct of_device_id *match;
  	int irq;
  	int r;
@@ -30,7 +29,7 @@ index db31eae..4c38aa0 100644
  
  	/* NOTE: driver uses the static register mapping */
  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-@@ -1202,6 +1205,13 @@ omap_i2c_probe(struct platform_device *pdev)
+@@ -1200,6 +1203,13 @@ omap_i2c_probe(struct platform_device *pdev)
  
  	of_i2c_register_devices(adap);
  
diff --git a/patches/linux-3.7-rc6/0039-arm-dts-AM33XX-Configure-pinmuxs-for-user-leds-contr.patch b/patches/linux-3.7/0039-arm-dts-AM33XX-Configure-pinmuxs-for-user-leds-contr.patch
index 5b16009..adb03e0 100644
--- a/patches/linux-3.7-rc6/0039-arm-dts-AM33XX-Configure-pinmuxs-for-user-leds-contr.patch
+++ b/patches/linux-3.7/0039-arm-dts-AM33XX-Configure-pinmuxs-for-user-leds-contr.patch
@@ -1,4 +1,3 @@
-From b76bec0181666391a0e7ad495a72865f1f35173d Mon Sep 17 00:00:00 2001
 From: "AnilKumar, Chimata" <anilkumar@ti.com>
 Date: Fri, 31 Aug 2012 09:29:18 +0000
 Subject: [PATCH] arm/dts: AM33XX: Configure pinmuxs for user leds control on
diff --git a/patches/linux-3.7-rc6/0040-beaglebone-DT-set-default-triggers-for-LEDS.patch b/patches/linux-3.7/0040-beaglebone-DT-set-default-triggers-for-LEDS.patch
index c901a64..8857338 100644
--- a/patches/linux-3.7-rc6/0040-beaglebone-DT-set-default-triggers-for-LEDS.patch
+++ b/patches/linux-3.7/0040-beaglebone-DT-set-default-triggers-for-LEDS.patch
@@ -1,4 +1,3 @@
-From 1d95712aeeea071a0090699bb863004e5fae01d3 Mon Sep 17 00:00:00 2001
 From: Koen Kooi <koen@dominion.thruhere.net>
 Date: Wed, 5 Sep 2012 09:49:21 +0200
 Subject: [PATCH] beaglebone DT: set default triggers for LEDS
diff --git a/patches/linux-3.7-rc6/0041-beaglebone-add-a-cpu-led-trigger.patch b/patches/linux-3.7/0041-beaglebone-add-a-cpu-led-trigger.patch
index e30b5cd..c1b2059 100644
--- a/patches/linux-3.7-rc6/0041-beaglebone-add-a-cpu-led-trigger.patch
+++ b/patches/linux-3.7/0041-beaglebone-add-a-cpu-led-trigger.patch
@@ -1,4 +1,3 @@
-From 1313bf938b17dca177b11f7317e8b1765c2008b0 Mon Sep 17 00:00:00 2001
 From: Koen Kooi <koen@dominion.thruhere.net>
 Date: Mon, 15 Oct 2012 16:53:28 +0200
 Subject: [PATCH] beaglebone: add a cpu led trigger
diff --git a/patches/linux-3.7-rc6/0043-arm-dts-AM33XX-Add-device-tree-OPP-table.patch b/patches/linux-3.7/0043-arm-dts-AM33XX-Add-device-tree-OPP-table.patch
index 6977708..f89a4c8 100644
--- a/patches/linux-3.7-rc6/0043-arm-dts-AM33XX-Add-device-tree-OPP-table.patch
+++ b/patches/linux-3.7/0043-arm-dts-AM33XX-Add-device-tree-OPP-table.patch
@@ -1,4 +1,3 @@
-From 6983ddebcd85a68ce206f513adea0edd80e22052 Mon Sep 17 00:00:00 2001
 From: "AnilKumar, Chimata" <anilkumar@ti.com>
 Date: Fri, 31 Aug 2012 09:37:20 +0000
 Subject: [PATCH] arm/dts: AM33XX: Add device tree OPP table
diff --git a/patches/linux-3.7/0044-am33xx-DT-add-commented-out-OPP-values-for-ES2.0.patch b/patches/linux-3.7/0044-am33xx-DT-add-commented-out-OPP-values-for-ES2.0.patch
new file mode 100644
index 0000000..119174b
--- /dev/null
+++ b/patches/linux-3.7/0044-am33xx-DT-add-commented-out-OPP-values-for-ES2.0.patch
@@ -0,0 +1,24 @@
+From: Koen Kooi <koen@dominion.thruhere.net>
+Date: Thu, 6 Dec 2012 11:55:52 +0100
+Subject: [PATCH] am33xx DT: add commented out OPP values for ES2.0
+
+Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
+---
+ arch/arm/boot/dts/am33xx.dtsi |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
+index 9755276..ce429a0 100644
+--- a/arch/arm/boot/dts/am33xx.dtsi
++++ b/arch/arm/boot/dts/am33xx.dtsi
+@@ -33,6 +33,10 @@
+ 			 */
+ 			operating-points = <
+ 				/* kHz    uV */
++				/* ES 2.0 Nitro and Turbo OPPs"
++				1000000	1350000
++				800000	1300000
++				*/
+ 				720000  1285000
+ 				600000  1225000
+ 				500000  1125000
diff --git a/patches/linux-3.7-rc6/0045-input-TSC-ti_tscadc-Correct-register-usage.patch b/patches/linux-3.7/0046-input-TSC-ti_tscadc-Correct-register-usage.patch
index 5046ca3..f8ede3c 100644
--- a/patches/linux-3.7-rc6/0045-input-TSC-ti_tscadc-Correct-register-usage.patch
+++ b/patches/linux-3.7/0046-input-TSC-ti_tscadc-Correct-register-usage.patch
@@ -1,4 +1,3 @@
-From 26a11407fe194a39a80f8a36964d23f03ef61f7e Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Tue, 16 Oct 2012 07:25:38 +0000
 Subject: [PATCH] input: TSC: ti_tscadc: Correct register usage
diff --git a/patches/linux-3.7-rc6/0046-input-TSC-ti_tscadc-Add-Step-configuration-as-platfo.patch b/patches/linux-3.7/0047-input-TSC-ti_tscadc-Add-Step-configuration-as-platfo.patch
index bf40198..f8f43e3 100644
--- a/patches/linux-3.7-rc6/0046-input-TSC-ti_tscadc-Add-Step-configuration-as-platfo.patch
+++ b/patches/linux-3.7/0047-input-TSC-ti_tscadc-Add-Step-configuration-as-platfo.patch
@@ -1,4 +1,3 @@
-From b932cb2194e4e7ffc21e5c19b56d2b018ef88f5a Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Tue, 16 Oct 2012 07:25:39 +0000
 Subject: [PATCH] input: TSC: ti_tscadc: Add Step configuration as platform
diff --git a/patches/linux-3.7-rc6/0047-input-TSC-ti_tscadc-set-FIFO0-threshold-Interrupt.patch b/patches/linux-3.7/0048-input-TSC-ti_tscadc-set-FIFO0-threshold-Interrupt.patch
index e61ea48..fa1162b 100644
--- a/patches/linux-3.7-rc6/0047-input-TSC-ti_tscadc-set-FIFO0-threshold-Interrupt.patch
+++ b/patches/linux-3.7/0048-input-TSC-ti_tscadc-set-FIFO0-threshold-Interrupt.patch
@@ -1,4 +1,3 @@
-From ac7eef064eb1619eaf030e9f36e784230a8d7baa Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Tue, 16 Oct 2012 07:25:40 +0000
 Subject: [PATCH] input: TSC: ti_tscadc: set FIFO0 threshold Interrupt
diff --git a/patches/linux-3.7-rc6/0048-input-TSC-ti_tscadc-Remove-definition-of-End-Of-Inte.patch b/patches/linux-3.7/0049-input-TSC-ti_tscadc-Remove-definition-of-End-Of-Inte.patch
index ab04b48..7160244 100644
--- a/patches/linux-3.7-rc6/0048-input-TSC-ti_tscadc-Remove-definition-of-End-Of-Inte.patch
+++ b/patches/linux-3.7/0049-input-TSC-ti_tscadc-Remove-definition-of-End-Of-Inte.patch
@@ -1,4 +1,3 @@
-From e1c5c484bc32790c868f8de1300780b950d4514d Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Tue, 16 Oct 2012 07:25:41 +0000
 Subject: [PATCH] input: TSC: ti_tscadc: Remove definition of End Of Interrupt
diff --git a/patches/linux-3.7-rc6/0049-input-TSC-ti_tscadc-Rename-the-existing-touchscreen-.patch b/patches/linux-3.7/0050-input-TSC-ti_tscadc-Rename-the-existing-touchscreen-.patch
index 0b482cd..8f8ac8f 100644
--- a/patches/linux-3.7-rc6/0049-input-TSC-ti_tscadc-Rename-the-existing-touchscreen-.patch
+++ b/patches/linux-3.7/0050-input-TSC-ti_tscadc-Rename-the-existing-touchscreen-.patch
@@ -1,4 +1,3 @@
-From 0f0fedfede0d4c004f4612e4725b311b7bdcb061 Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Tue, 16 Oct 2012 07:25:42 +0000
 Subject: [PATCH] input: TSC: ti_tscadc: Rename the existing touchscreen
diff --git a/patches/linux-3.7-rc6/0050-MFD-ti_tscadc-Add-support-for-TI-s-TSC-ADC-MFDevice.patch b/patches/linux-3.7/0051-MFD-ti_tscadc-Add-support-for-TI-s-TSC-ADC-MFDevice.patch
index 7bade04..1e20a54 100644
--- a/patches/linux-3.7-rc6/0050-MFD-ti_tscadc-Add-support-for-TI-s-TSC-ADC-MFDevice.patch
+++ b/patches/linux-3.7/0051-MFD-ti_tscadc-Add-support-for-TI-s-TSC-ADC-MFDevice.patch
@@ -1,4 +1,3 @@
-From f0239cfc7dffbfe1409dfb670899cb188ed257a1 Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Tue, 16 Oct 2012 07:25:43 +0000
 Subject: [PATCH] MFD: ti_tscadc: Add support for TI's TSC/ADC MFDevice
diff --git a/patches/linux-3.7-rc6/0051-input-TSC-ti_tsc-Convert-TSC-into-a-MFDevice.patch b/patches/linux-3.7/0052-input-TSC-ti_tsc-Convert-TSC-into-a-MFDevice.patch
index 11bdb5f..4b9e4fa 100644
--- a/patches/linux-3.7-rc6/0051-input-TSC-ti_tsc-Convert-TSC-into-a-MFDevice.patch
+++ b/patches/linux-3.7/0052-input-TSC-ti_tsc-Convert-TSC-into-a-MFDevice.patch
@@ -1,4 +1,3 @@
-From 0191d4a7838cc6c437d8811ec630e26f10abe116 Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Tue, 16 Oct 2012 07:25:44 +0000
 Subject: [PATCH] input: TSC: ti_tsc: Convert TSC into a MFDevice
diff --git a/patches/linux-3.7-rc6/0052-IIO-ADC-tiadc-Add-support-of-TI-s-ADC-driver.patch b/patches/linux-3.7/0053-IIO-ADC-tiadc-Add-support-of-TI-s-ADC-driver.patch
index 55e3b66..ab6df93 100644
--- a/patches/linux-3.7-rc6/0052-IIO-ADC-tiadc-Add-support-of-TI-s-ADC-driver.patch
+++ b/patches/linux-3.7/0053-IIO-ADC-tiadc-Add-support-of-TI-s-ADC-driver.patch
@@ -1,4 +1,3 @@
-From 1c87d22d7a5671164abd42a6478cf536a3637fee Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Tue, 16 Oct 2012 07:25:45 +0000
 Subject: [PATCH] IIO : ADC: tiadc: Add support of TI's ADC driver
diff --git a/patches/linux-3.7-rc6/0053-input-ti_am335x_tsc-Make-steps-enable-configurable.patch b/patches/linux-3.7/0054-input-ti_am335x_tsc-Make-steps-enable-configurable.patch
index cc791d4..a2fe55c 100644
--- a/patches/linux-3.7-rc6/0053-input-ti_am335x_tsc-Make-steps-enable-configurable.patch
+++ b/patches/linux-3.7/0054-input-ti_am335x_tsc-Make-steps-enable-configurable.patch
@@ -1,4 +1,3 @@
-From c2e4f935c7eb7e48e81eee2f11582ea686e9199a Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Mon, 22 Oct 2012 10:15:16 +0000
 Subject: [PATCH] input: ti_am335x_tsc: Make steps enable configurable
diff --git a/patches/linux-3.7-rc6/0054-input-ti_am335x_tsc-Order-of-TSC-wires-connect-made-.patch b/patches/linux-3.7/0055-input-ti_am335x_tsc-Order-of-TSC-wires-connect-made-.patch
index 0f7105a..7c99ed2 100644
--- a/patches/linux-3.7-rc6/0054-input-ti_am335x_tsc-Order-of-TSC-wires-connect-made-.patch
+++ b/patches/linux-3.7/0055-input-ti_am335x_tsc-Order-of-TSC-wires-connect-made-.patch
@@ -1,4 +1,3 @@
-From 27f22a592f264d221ecd8ddc1dc8f7d49ea4108a Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Mon, 22 Oct 2012 10:15:17 +0000
 Subject: [PATCH] input: ti_am335x_tsc: Order of TSC wires connect, made
diff --git a/patches/linux-3.7-rc6/0055-input-ti_am335x_tsc-Add-variance-filters.patch b/patches/linux-3.7/0056-input-ti_am335x_tsc-Add-variance-filters.patch
index 4be6c7d..c1da777 100644
--- a/patches/linux-3.7-rc6/0055-input-ti_am335x_tsc-Add-variance-filters.patch
+++ b/patches/linux-3.7/0056-input-ti_am335x_tsc-Add-variance-filters.patch
@@ -1,4 +1,3 @@
-From 18d663634d89727e277e5055af890bbfa13eeffc Mon Sep 17 00:00:00 2001
 From: "Patil, Rachna" <rachna@ti.com>
 Date: Mon, 22 Oct 2012 10:15:18 +0000
 Subject: [PATCH] input: ti_am335x_tsc: Add variance filters
diff --git a/patches/linux-3.7-rc6/0056-ti_tscadc-Update-with-IIO-map-interface-deal-with-pa.patch b/patches/linux-3.7/0057-ti_tscadc-Update-with-IIO-map-interface-deal-with-pa.patch
index d0ebf97..58d6720 100644
--- a/patches/linux-3.7-rc6/0056-ti_tscadc-Update-with-IIO-map-interface-deal-with-pa.patch
+++ b/patches/linux-3.7/0057-ti_tscadc-Update-with-IIO-map-interface-deal-with-pa.patch
@@ -1,4 +1,3 @@
-From 8f4be87c38d30e43f4e83fd104a64e642589f9b2 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 13 Oct 2012 16:37:24 +0300
 Subject: [PATCH] ti_tscadc: Update with IIO map interface & deal with partial
diff --git a/patches/linux-3.7-rc6/0057-ti_tscadc-Match-mfd-sub-devices-to-regmap-interface.patch b/patches/linux-3.7/0058-ti_tscadc-Match-mfd-sub-devices-to-regmap-interface.patch
index 645adc4..d5e8362 100644
--- a/patches/linux-3.7-rc6/0057-ti_tscadc-Match-mfd-sub-devices-to-regmap-interface.patch
+++ b/patches/linux-3.7/0058-ti_tscadc-Match-mfd-sub-devices-to-regmap-interface.patch
@@ -1,4 +1,3 @@
-From e2ca20cc059c217cd78963a77189004645de55c7 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Fri, 26 Oct 2012 14:01:05 +0300
 Subject: [PATCH] ti_tscadc: Match mfd sub devices to regmap interface
diff --git a/patches/linux-3.7-rc6/0059-ARM-OMAP3-hwmod-Corrects-resource-data-for-PWM-devic.patch b/patches/linux-3.7/0060-ARM-OMAP3-hwmod-Corrects-resource-data-for-PWM-devic.patch
index a50a7c1..b868bfe 100644
--- a/patches/linux-3.7-rc6/0059-ARM-OMAP3-hwmod-Corrects-resource-data-for-PWM-devic.patch
+++ b/patches/linux-3.7/0060-ARM-OMAP3-hwmod-Corrects-resource-data-for-PWM-devic.patch
@@ -1,4 +1,3 @@
-From ef11a2c0cc3cc0c1b8ea1d96a4ead994b0175f02 Mon Sep 17 00:00:00 2001
 From: "Philip, Avinash" <avinashphilip@ti.com>
 Date: Mon, 2 Jul 2012 13:51:39 +0530
 Subject: [PATCH] ARM: OMAP3+: hwmod: Corrects resource data for PWM devices.
diff --git a/patches/linux-3.7-rc6/0060-pwm_backlight-Add-device-tree-support-for-Low-Thresh.patch b/patches/linux-3.7/0061-pwm_backlight-Add-device-tree-support-for-Low-Thresh.patch
index 4a6d3c3..8e5d982 100644
--- a/patches/linux-3.7-rc6/0060-pwm_backlight-Add-device-tree-support-for-Low-Thresh.patch
+++ b/patches/linux-3.7/0061-pwm_backlight-Add-device-tree-support-for-Low-Thresh.patch
@@ -1,4 +1,3 @@
-From 9deb78bb727ab7c632f240dc57af845f39e618c8 Mon Sep 17 00:00:00 2001
 From: "Philip, Avinash" <avinashphilip@ti.com>
 Date: Mon, 16 Jul 2012 14:59:41 +0530
 Subject: [PATCH] pwm_backlight: Add device tree support for Low Threshold
diff --git a/patches/linux-3.7-rc6/0061-pwm-pwm-tiecap-Add-device-tree-binding-support-in-AP.patch b/patches/linux-3.7/0062-pwm-pwm-tiecap-Add-device-tree-binding-support-in-AP.patch
index 1bf1097..a72fbe6 100644
--- a/patches/linux-3.7-rc6/0061-pwm-pwm-tiecap-Add-device-tree-binding-support-in-AP.patch
+++ b/patches/linux-3.7/0062-pwm-pwm-tiecap-Add-device-tree-binding-support-in-AP.patch
@@ -1,4 +1,3 @@
-From 6a9abd983cbbd369707b4b7edc3b9b45aa80a4b1 Mon Sep 17 00:00:00 2001
 From: "Philip, Avinash" <avinashphilip@ti.com>
 Date: Fri, 29 Jun 2012 10:52:57 +0530
 Subject: [PATCH] pwm: pwm-tiecap: Add device-tree binding support in APWM
diff --git a/patches/linux-3.7-rc6/0062-Control-module-EHRPWM-clk-enabling.patch b/patches/linux-3.7/0063-Control-module-EHRPWM-clk-enabling.patch
index 6ea83fe..6a268e8 100644
--- a/patches/linux-3.7-rc6/0062-Control-module-EHRPWM-clk-enabling.patch
+++ b/patches/linux-3.7/0063-Control-module-EHRPWM-clk-enabling.patch
@@ -1,4 +1,3 @@
-From 6f3f226f97712e86991a805aa5e05e8734aa9f21 Mon Sep 17 00:00:00 2001
 From: "Philip, Avinash" <avinashphilip@ti.com>
 Date: Tue, 22 May 2012 11:34:58 +0530
 Subject: [PATCH] Control module : EHRPWM clk enabling
diff --git a/patches/linux-3.7-rc6/0063-pwm-pwm-tiecap-Enable-clock-gating.patch b/patches/linux-3.7/0064-pwm-pwm-tiecap-Enable-clock-gating.patch
index 8adb2c9..f98ce61 100644
--- a/patches/linux-3.7-rc6/0063-pwm-pwm-tiecap-Enable-clock-gating.patch
+++ b/patches/linux-3.7/0064-pwm-pwm-tiecap-Enable-clock-gating.patch
@@ -1,4 +1,3 @@
-From 33ed8e5aaf8a28e904bf0f3174cfc3a4cb3c5e50 Mon Sep 17 00:00:00 2001
 From: "Philip, Avinash" <avinashphilip@ti.com>
 Date: Tue, 24 Jul 2012 14:58:09 +0530
 Subject: [PATCH] pwm: pwm-tiecap: Enable clock gating
diff --git a/patches/linux-3.7-rc6/0064-PWM-ti-ehrpwm-fix-up-merge-conflict.patch b/patches/linux-3.7/0065-PWM-ti-ehrpwm-fix-up-merge-conflict.patch
index c036093..9cc2a3f 100644
--- a/patches/linux-3.7-rc6/0064-PWM-ti-ehrpwm-fix-up-merge-conflict.patch
+++ b/patches/linux-3.7/0065-PWM-ti-ehrpwm-fix-up-merge-conflict.patch
@@ -1,4 +1,3 @@
-From f650c07353651edeb2f3b56fc5628ca48e60609d Mon Sep 17 00:00:00 2001
 From: Koen Kooi <koen@dominion.thruhere.net>
 Date: Mon, 17 Sep 2012 10:34:22 +0200
 Subject: [PATCH] PWM: ti-ehrpwm: fix up merge conflict
diff --git a/patches/linux-3.7-rc6/0065-pwm-pwm_test-Driver-support-for-PWM-module-testing.patch b/patches/linux-3.7/0066-pwm-pwm_test-Driver-support-for-PWM-module-testing.patch
index 1036f6d..5e012cc 100644
--- a/patches/linux-3.7-rc6/0065-pwm-pwm_test-Driver-support-for-PWM-module-testing.patch
+++ b/patches/linux-3.7/0066-pwm-pwm_test-Driver-support-for-PWM-module-testing.patch
@@ -1,4 +1,3 @@
-From a1655d02663d4cef923a9a75c60fb34f2e35c783 Mon Sep 17 00:00:00 2001
 From: "Philip, Avinash" <avinashphilip@ti.com>
 Date: Tue, 17 Jul 2012 21:35:11 +0530
 Subject: [PATCH] pwm: pwm_test: Driver support for PWM module testing
diff --git a/patches/linux-3.7-rc6/0066-arm-dts-DT-support-for-EHRPWM-and-ECAP-device.patch b/patches/linux-3.7/0067-arm-dts-DT-support-for-EHRPWM-and-ECAP-device.patch
index a4ff6bd..612da05 100644
--- a/patches/linux-3.7-rc6/0066-arm-dts-DT-support-for-EHRPWM-and-ECAP-device.patch
+++ b/patches/linux-3.7/0067-arm-dts-DT-support-for-EHRPWM-and-ECAP-device.patch
@@ -1,4 +1,3 @@
-From 335aa3e5347097e0ef7ba046e59d9bb9cffa8a48 Mon Sep 17 00:00:00 2001
 From: "Philip, Avinash" <avinashphilip@ti.com>
 Date: Wed, 11 Jul 2012 11:01:33 +0530
 Subject: [PATCH] arm/dts: DT support for EHRPWM and ECAP device.
@@ -13,10 +12,10 @@ Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
  1 file changed, 60 insertions(+)
 
 diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
-index 9755276..433065e 100644
+index ce429a0..8484559 100644
 --- a/arch/arm/boot/dts/am33xx.dtsi
 +++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -376,5 +376,65 @@
+@@ -380,5 +380,65 @@
  			};
  
  		};
diff --git a/patches/linux-3.7-rc6/0067-pwm-pwm-tiehrpwm-Add-device-tree-binding-support-EHR.patch b/patches/linux-3.7/0068-pwm-pwm-tiehrpwm-Add-device-tree-binding-support-EHR.patch
index 4da3741..8c31560 100644
--- a/patches/linux-3.7-rc6/0067-pwm-pwm-tiehrpwm-Add-device-tree-binding-support-EHR.patch
+++ b/patches/linux-3.7/0068-pwm-pwm-tiehrpwm-Add-device-tree-binding-support-EHR.patch
@@ -1,4 +1,3 @@
-From 2d9a549a27aad6c8a87878c3620e1c0812af8da1 Mon Sep 17 00:00:00 2001
 From: "Philip, Avinash" <avinashphilip@ti.com>
 Date: Mon, 2 Jul 2012 14:03:53 +0530
 Subject: [PATCH] pwm: pwm-tiehrpwm: Add device-tree binding support EHRPWM
diff --git a/patches/linux-3.7/0069-ARM-OMAP2-PWM-limit-am33xx_register_ehrpwm-to-soc_is.patch b/patches/linux-3.7/0069-ARM-OMAP2-PWM-limit-am33xx_register_ehrpwm-to-soc_is.patch
new file mode 100644
index 0000000..0998781
--- /dev/null
+++ b/patches/linux-3.7/0069-ARM-OMAP2-PWM-limit-am33xx_register_ehrpwm-to-soc_is.patch
@@ -0,0 +1,26 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 27 Nov 2012 10:53:23 -0600
+Subject: [PATCH] ARM: OMAP2: PWM: limit am33xx_register_ehrpwm to
+ soc_is_am33xx, fixes boot on Beagle/Panda
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/devices.c |    5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index 9faecb9..07af6c8 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -733,8 +733,9 @@ static int __init omap2_init_devices(void)
+ 	omap_init_aes();
+ 	omap_init_vout();
+ 	omap_init_ocp2scp();
+-
+-	am33xx_register_ehrpwm();
++	if (soc_is_am33xx()) {
++		am33xx_register_ehrpwm();
++	}
+ 	return 0;
+ }
+ arch_initcall(omap2_init_devices);
diff --git a/patches/linux-3.7-rc6/0069-pinctrl-pinctrl-single-must-be-initialized-early.patch b/patches/linux-3.7/0071-pinctrl-pinctrl-single-must-be-initialized-early.patch
index 0862d29..45918e8 100644
--- a/patches/linux-3.7-rc6/0069-pinctrl-pinctrl-single-must-be-initialized-early.patch
+++ b/patches/linux-3.7/0071-pinctrl-pinctrl-single-must-be-initialized-early.patch
@@ -1,4 +1,3 @@
-From 3a0f046cac46f4b1cc0a8e544dba30afcae91f3d Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 15 Sep 2012 12:00:41 +0300
 Subject: [PATCH] pinctrl: pinctrl-single must be initialized early.
diff --git a/patches/linux-3.7-rc6/0070-Bone-DTS-working-i2c2-i2c3-in-the-tree.patch b/patches/linux-3.7/0072-Bone-DTS-working-i2c2-i2c3-in-the-tree.patch
index 4472434..612c935 100644
--- a/patches/linux-3.7-rc6/0070-Bone-DTS-working-i2c2-i2c3-in-the-tree.patch
+++ b/patches/linux-3.7/0072-Bone-DTS-working-i2c2-i2c3-in-the-tree.patch
@@ -1,4 +1,3 @@
-From cc8421dbb5b79561a93b29d4f29959f61471757e Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 15 Sep 2012 12:05:04 +0300
 Subject: [PATCH] Bone DTS working i2c2 (i2c3 in the tree)
diff --git a/patches/linux-3.7-rc6/0071-am33xx-Convert-I2C-from-omap-to-am33xx-names.patch b/patches/linux-3.7/0073-am33xx-Convert-I2C-from-omap-to-am33xx-names.patch
index 007caf1..9751754 100644
--- a/patches/linux-3.7-rc6/0071-am33xx-Convert-I2C-from-omap-to-am33xx-names.patch
+++ b/patches/linux-3.7/0073-am33xx-Convert-I2C-from-omap-to-am33xx-names.patch
@@ -1,4 +1,3 @@
-From bd2807f5f8e0cf858f95e7d930de4aec2d753d4c Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 15 Sep 2012 14:49:11 +0300
 Subject: [PATCH] am33xx: Convert I2C from omap to am33xx names
@@ -62,10 +61,10 @@ index 43e23a8..6032648 100644
  			clock-frequency = <400000>;
  
 diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
-index 433065e..535a66c 100644
+index 8484559..a2270aa 100644
 --- a/arch/arm/boot/dts/am33xx.dtsi
 +++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -225,33 +225,33 @@
+@@ -229,33 +229,33 @@
  			status = "disabled";
  		};
  
diff --git a/patches/linux-3.7-rc6/0072-beaglebone-fix-backlight-entry-in-DT.patch b/patches/linux-3.7/0074-beaglebone-fix-backlight-entry-in-DT.patch
index 58f62c9..410150c 100644
--- a/patches/linux-3.7-rc6/0072-beaglebone-fix-backlight-entry-in-DT.patch
+++ b/patches/linux-3.7/0074-beaglebone-fix-backlight-entry-in-DT.patch
@@ -1,4 +1,3 @@
-From b1eb01e79784564526df857c50491fcd47a124b5 Mon Sep 17 00:00:00 2001
 From: Koen Kooi <koen@dominion.thruhere.net>
 Date: Tue, 18 Sep 2012 11:23:47 +0200
 Subject: [PATCH] beaglebone: fix backlight entry in DT
diff --git a/patches/linux-3.7-rc6/0074-Shut-up-musb.patch b/patches/linux-3.7/0076-Shut-up-musb.patch
index e533862..37caa4c 100644
--- a/patches/linux-3.7-rc6/0074-Shut-up-musb.patch
+++ b/patches/linux-3.7/0076-Shut-up-musb.patch
@@ -1,4 +1,3 @@
-From f52622777ab0362a9b6abe4a781ea3138285cb91 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Thu, 4 Oct 2012 12:02:13 +0300
 Subject: [PATCH] Shut up musb!
diff --git a/patches/linux-3.7-rc6/0075-musb-Fix-crashes-and-other-weirdness.patch b/patches/linux-3.7/0077-musb-Fix-crashes-and-other-weirdness.patch
index 6febda8..15a438e 100644
--- a/patches/linux-3.7-rc6/0075-musb-Fix-crashes-and-other-weirdness.patch
+++ b/patches/linux-3.7/0077-musb-Fix-crashes-and-other-weirdness.patch
@@ -1,4 +1,3 @@
-From 51880a937820eeb67105545a7202668c1b2a4663 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Thu, 4 Oct 2012 17:53:53 +0300
 Subject: [PATCH] musb: Fix crashes, and other weirdness.
@@ -8,10 +7,10 @@ Subject: [PATCH] musb: Fix crashes, and other weirdness.
  1 file changed, 26 insertions(+)
 
 diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
-index 535a66c..9bb71cb 100644
+index a2270aa..0b53cde 100644
 --- a/arch/arm/boot/dts/am33xx.dtsi
 +++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -285,6 +285,32 @@
+@@ -289,6 +289,32 @@
  			status = "disabled";
  		};
  
diff --git a/patches/linux-3.7-rc6/0076-musb-revert-parts-of-032ec49f.patch b/patches/linux-3.7/0078-musb-revert-parts-of-032ec49f.patch
index 6b3083e..b59a7d8 100644
--- a/patches/linux-3.7-rc6/0076-musb-revert-parts-of-032ec49f.patch
+++ b/patches/linux-3.7/0078-musb-revert-parts-of-032ec49f.patch
@@ -1,4 +1,3 @@
-From 482b626629b125679eab02d90e067e1223201506 Mon Sep 17 00:00:00 2001
 From: Daniel Mack <zonque@gmail.com>
 Date: Wed, 17 Oct 2012 15:34:24 +0200
 Subject: [PATCH] musb: revert parts of 032ec49f
diff --git a/patches/linux-3.7-rc6/0077-usb-musb-dsps-get-the-PHY-using-phandle-api.patch b/patches/linux-3.7/0079-usb-musb-dsps-get-the-PHY-using-phandle-api.patch
index ec0953e..f29aa81 100644
--- a/patches/linux-3.7-rc6/0077-usb-musb-dsps-get-the-PHY-using-phandle-api.patch
+++ b/patches/linux-3.7/0079-usb-musb-dsps-get-the-PHY-using-phandle-api.patch
@@ -1,4 +1,3 @@
-From f2a9a492881a8eb7b4e9368510e29bcf04e16adb Mon Sep 17 00:00:00 2001
 From: Ravi Babu <ravibabu@ti.com>
 Date: Thu, 2 Aug 2012 16:13:32 +0530
 Subject: [PATCH] usb: musb: dsps: get the PHY using phandle api
diff --git a/patches/linux-3.7-rc6/0078-drivers-usb-otg-add-device-tree-support-to-otg-libra.patch b/patches/linux-3.7/0080-drivers-usb-otg-add-device-tree-support-to-otg-libra.patch
index 4ef518d..419b5eb 100644
--- a/patches/linux-3.7-rc6/0078-drivers-usb-otg-add-device-tree-support-to-otg-libra.patch
+++ b/patches/linux-3.7/0080-drivers-usb-otg-add-device-tree-support-to-otg-libra.patch
@@ -1,4 +1,3 @@
-From 5a2e1bc30bd48edd71c3eaef3d5141d6fbe3edb2 Mon Sep 17 00:00:00 2001
 From: Ajay Kumar Gupta <ajay.gupta@ti.com>
 Date: Tue, 10 Jul 2012 14:10:38 +0530
 Subject: [PATCH] drivers: usb: otg: add device tree support to otg library
diff --git a/patches/linux-3.7-rc6/0079-usb-otg-nop-add-dt-support.patch b/patches/linux-3.7/0081-usb-otg-nop-add-dt-support.patch
index ac46e10..4534f6a 100644
--- a/patches/linux-3.7-rc6/0079-usb-otg-nop-add-dt-support.patch
+++ b/patches/linux-3.7/0081-usb-otg-nop-add-dt-support.patch
@@ -1,4 +1,3 @@
-From fb37c173324d76c12dd1b0e7758f1e2012f6dabf Mon Sep 17 00:00:00 2001
 From: Ajay Kumar Gupta <ajay.gupta@ti.com>
 Date: Tue, 10 Jul 2012 14:51:53 +0530
 Subject: [PATCH] usb: otg: nop: add dt support
diff --git a/patches/linux-3.7-rc6/0080-usb-musb-dsps-add-phy-control-logic-to-glue.patch b/patches/linux-3.7/0082-usb-musb-dsps-add-phy-control-logic-to-glue.patch
index 81953b7..c54df7c 100644
--- a/patches/linux-3.7-rc6/0080-usb-musb-dsps-add-phy-control-logic-to-glue.patch
+++ b/patches/linux-3.7/0082-usb-musb-dsps-add-phy-control-logic-to-glue.patch
@@ -1,4 +1,3 @@
-From eca00fad21c1ef2bf0df883fa2c001e2242bfe29 Mon Sep 17 00:00:00 2001
 From: Ajay Kumar Gupta <ajay.gupta@ti.com>
 Date: Thu, 5 Jul 2012 14:06:42 +0530
 Subject: [PATCH] usb: musb: dsps: add phy control logic to glue
diff --git a/patches/linux-3.7-rc6/0081-usb-musb-dsps-enable-phy-control-for-am335x.patch b/patches/linux-3.7/0083-usb-musb-dsps-enable-phy-control-for-am335x.patch
index 3935eb9..98c91ab 100644
--- a/patches/linux-3.7-rc6/0081-usb-musb-dsps-enable-phy-control-for-am335x.patch
+++ b/patches/linux-3.7/0083-usb-musb-dsps-enable-phy-control-for-am335x.patch
@@ -1,4 +1,3 @@
-From 849303a736b86ac5de2570a52ddac5ef9c2290f0 Mon Sep 17 00:00:00 2001
 From: Ajay Kumar Gupta <ajay.gupta@ti.com>
 Date: Thu, 5 Jul 2012 14:35:06 +0530
 Subject: [PATCH] usb: musb: dsps: enable phy control for am335x
diff --git a/patches/linux-3.7-rc6/0082-ARM-am33xx-fix-mem-regions-in-USB-hwmod.patch b/patches/linux-3.7/0084-ARM-am33xx-fix-mem-regions-in-USB-hwmod.patch
index 5fd84b3..0a0132c 100644
--- a/patches/linux-3.7-rc6/0082-ARM-am33xx-fix-mem-regions-in-USB-hwmod.patch
+++ b/patches/linux-3.7/0084-ARM-am33xx-fix-mem-regions-in-USB-hwmod.patch
@@ -1,4 +1,3 @@
-From 23ec7954c2eb161d52ce3df4fac3f7a188319120 Mon Sep 17 00:00:00 2001
 From: Daniel Mack <zonque@gmail.com>
 Date: Wed, 17 Oct 2012 16:39:00 +0200
 Subject: [PATCH] ARM: am33xx: fix mem regions in USB hwmod
diff --git a/patches/linux-3.7-rc6/0084-omap2-clk-Add-missing-lcdc-clock-definition.patch b/patches/linux-3.7/0086-omap2-clk-Add-missing-lcdc-clock-definition.patch
index 0e85066..75cda70 100644
--- a/patches/linux-3.7-rc6/0084-omap2-clk-Add-missing-lcdc-clock-definition.patch
+++ b/patches/linux-3.7/0086-omap2-clk-Add-missing-lcdc-clock-definition.patch
@@ -1,4 +1,3 @@
-From 5cb5d4cb5e66b2aab310bb097e23cd7b424c590d Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 13 Oct 2012 16:12:22 +0300
 Subject: [PATCH] omap2-clk: Add missing lcdc clock definition
diff --git a/patches/linux-3.7-rc6/0085-da8xx-Allow-use-by-am33xx-based-devices.patch b/patches/linux-3.7/0087-da8xx-Allow-use-by-am33xx-based-devices.patch
index f796803..97a9b4b 100644
--- a/patches/linux-3.7-rc6/0085-da8xx-Allow-use-by-am33xx-based-devices.patch
+++ b/patches/linux-3.7/0087-da8xx-Allow-use-by-am33xx-based-devices.patch
@@ -1,4 +1,3 @@
-From a7cd16691ffbb0a9e4fe2d9602d51ae57d741753 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 13 Oct 2012 16:18:37 +0300
 Subject: [PATCH] da8xx: Allow use by am33xx based devices
diff --git a/patches/linux-3.7-rc6/0086-da8xx-Fix-revision-check-on-the-da8xx-driver.patch b/patches/linux-3.7/0088-da8xx-Fix-revision-check-on-the-da8xx-driver.patch
index 72d81c3..f8bdbaa 100644
--- a/patches/linux-3.7-rc6/0086-da8xx-Fix-revision-check-on-the-da8xx-driver.patch
+++ b/patches/linux-3.7/0088-da8xx-Fix-revision-check-on-the-da8xx-driver.patch
@@ -1,4 +1,3 @@
-From fab03445e416c75fab4cbe2a46a241445965122f Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 13 Oct 2012 16:21:05 +0300
 Subject: [PATCH] da8xx: Fix revision check on the da8xx driver
diff --git a/patches/linux-3.7-rc6/0087-da8xx-De-constify-members-in-the-platform-config.patch b/patches/linux-3.7/0089-da8xx-De-constify-members-in-the-platform-config.patch
index d2773a9..66fe3e0 100644
--- a/patches/linux-3.7-rc6/0087-da8xx-De-constify-members-in-the-platform-config.patch
+++ b/patches/linux-3.7/0089-da8xx-De-constify-members-in-the-platform-config.patch
@@ -1,4 +1,3 @@
-From d4638819046e8c3ea545eb8b63cc90466cd2dd1d Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 13 Oct 2012 16:22:47 +0300
 Subject: [PATCH] da8xx: De-constify members in the platform config.
diff --git a/patches/linux-3.7-rc6/0088-da8xx-Add-standard-panel-definition.patch b/patches/linux-3.7/0090-da8xx-Add-standard-panel-definition.patch
index 326ee0b..e53aa39 100644
--- a/patches/linux-3.7-rc6/0088-da8xx-Add-standard-panel-definition.patch
+++ b/patches/linux-3.7/0090-da8xx-Add-standard-panel-definition.patch
@@ -1,4 +1,3 @@
-From 8267defaabc2e24f3e57a1804982905b11e4a25f Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 13 Oct 2012 16:24:19 +0300
 Subject: [PATCH] da8xx: Add standard panel definition
diff --git a/patches/linux-3.7-rc6/0089-da8xx-Add-CDTech_S035Q01-panel-used-by-LCD3-bone-cap.patch b/patches/linux-3.7/0091-da8xx-Add-CDTech_S035Q01-panel-used-by-LCD3-bone-cap.patch
index 5bff28d..9bfe02d 100644
--- a/patches/linux-3.7-rc6/0089-da8xx-Add-CDTech_S035Q01-panel-used-by-LCD3-bone-cap.patch
+++ b/patches/linux-3.7/0091-da8xx-Add-CDTech_S035Q01-panel-used-by-LCD3-bone-cap.patch
@@ -1,4 +1,3 @@
-From efa286cb8ea36c5c01aaa632449690528aefcfe9 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Wed, 17 Oct 2012 15:43:55 +0300
 Subject: [PATCH] da8xx: Add CDTech_S035Q01 panel (used by LCD3 bone cape)
diff --git a/patches/linux-3.7-rc6/0090-da8xx-fb-add-panel-definition-for-beaglebone-LCD7-ca.patch b/patches/linux-3.7/0092-da8xx-fb-add-panel-definition-for-beaglebone-LCD7-ca.patch
index 463ea9a..87f3ea8 100644
--- a/patches/linux-3.7-rc6/0090-da8xx-fb-add-panel-definition-for-beaglebone-LCD7-ca.patch
+++ b/patches/linux-3.7/0092-da8xx-fb-add-panel-definition-for-beaglebone-LCD7-ca.patch
@@ -1,4 +1,3 @@
-From 84ee386766bf356bfdb5adddeb17de5ffc2f948c Mon Sep 17 00:00:00 2001
 From: Koen Kooi <koen@dominion.thruhere.net>
 Date: Wed, 17 Oct 2012 11:32:24 +0200
 Subject: [PATCH] da8xx-fb: add panel definition for beaglebone LCD7 cape
diff --git a/patches/linux-3.7-rc6/0092-mmc-omap_hsmmc-Enable-HSPE-bit-for-high-speed-cards.patch b/patches/linux-3.7/0094-mmc-omap_hsmmc-Enable-HSPE-bit-for-high-speed-cards.patch
index 92007c3..6cf21e8 100644
--- a/patches/linux-3.7-rc6/0092-mmc-omap_hsmmc-Enable-HSPE-bit-for-high-speed-cards.patch
+++ b/patches/linux-3.7/0094-mmc-omap_hsmmc-Enable-HSPE-bit-for-high-speed-cards.patch
@@ -1,4 +1,3 @@
-From 8f6c8615eb09d567eef77036e0d378b65b67ae40 Mon Sep 17 00:00:00 2001
 From: "Hebbar, Gururaja" <gururaja.hebbar@ti.com>
 Date: Tue, 4 Sep 2012 13:09:11 +0000
 Subject: [PATCH] mmc: omap_hsmmc: Enable HSPE bit for high speed cards
diff --git a/patches/linux-3.7-rc6/0093-am33xx.dtsi-enable-MMC-HSPE-bit-for-all-3-controller.patch b/patches/linux-3.7/0095-am33xx.dtsi-enable-MMC-HSPE-bit-for-all-3-controller.patch
index dd416dd..d27bff6 100644
--- a/patches/linux-3.7-rc6/0093-am33xx.dtsi-enable-MMC-HSPE-bit-for-all-3-controller.patch
+++ b/patches/linux-3.7/0095-am33xx.dtsi-enable-MMC-HSPE-bit-for-all-3-controller.patch
@@ -1,4 +1,3 @@
-From 6a28b2af338fb9b5800829474e26bcbc40005b1a Mon Sep 17 00:00:00 2001
 From: Koen Kooi <koen@dominion.thruhere.net>
 Date: Thu, 18 Oct 2012 10:11:48 +0200
 Subject: [PATCH] am33xx.dtsi: enable MMC HSPE bit for all 3 controllers
@@ -9,10 +8,10 @@ Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
  1 file changed, 3 insertions(+)
 
 diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
-index 9bb71cb..8bddc9c 100644
+index 0b53cde..5e418c7 100644
 --- a/arch/arm/boot/dts/am33xx.dtsi
 +++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -263,6 +263,7 @@
+@@ -267,6 +267,7 @@
  			ti,hwmods = "mmc1";
  			ti,dual-volt;
  			ti,needs-special-reset;
@@ -20,7 +19,7 @@ index 9bb71cb..8bddc9c 100644
  			dmas = <&edma 24
  				&edma 25>;
  			dma-names = "tx", "rx";
-@@ -272,6 +273,7 @@
+@@ -276,6 +277,7 @@
  			compatible = "ti,omap3-hsmmc";
  			ti,hwmods = "mmc2";
  			ti,needs-special-reset;
@@ -28,7 +27,7 @@ index 9bb71cb..8bddc9c 100644
  			dmas = <&edma 2
  				&edma 3>;
  			dma-names = "tx", "rx";
-@@ -282,6 +284,7 @@
+@@ -286,6 +288,7 @@
  			compatible = "ti,omap3-hsmmc";
  			ti,hwmods = "mmc3";
  			ti,needs-special-reset;
diff --git a/patches/linux-3.7-rc6/0094-omap-hsmmc-Correct-usage-of-of_find_node_by_name.patch b/patches/linux-3.7/0096-omap-hsmmc-Correct-usage-of-of_find_node_by_name.patch
index 71658ad..3128772 100644
--- a/patches/linux-3.7-rc6/0094-omap-hsmmc-Correct-usage-of-of_find_node_by_name.patch
+++ b/patches/linux-3.7/0096-omap-hsmmc-Correct-usage-of-of_find_node_by_name.patch
@@ -1,4 +1,3 @@
-From 21e193d74c69102be68cbc76baf581abffcaef2a Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Fri, 26 Oct 2012 15:48:00 +0300
 Subject: [PATCH] omap-hsmmc: Correct usage of of_find_node_by_name
diff --git a/patches/linux-3.7-rc6/0096-ARM-AM33XX-hwmod-Remove-wrong-INIT_NO_RESET-IDLE-fla.patch b/patches/linux-3.7/0098-ARM-AM33XX-hwmod-Remove-wrong-INIT_NO_RESET-IDLE-fla.patch
index 66399f4..5e39bdb 100644
--- a/patches/linux-3.7-rc6/0096-ARM-AM33XX-hwmod-Remove-wrong-INIT_NO_RESET-IDLE-fla.patch
+++ b/patches/linux-3.7/0098-ARM-AM33XX-hwmod-Remove-wrong-INIT_NO_RESET-IDLE-fla.patch
@@ -1,4 +1,3 @@
-From 0e2a3d8d4c5c17660c8e3410826c4d9f7f222968 Mon Sep 17 00:00:00 2001
 From: Vaibhav Hiremath <hvaibhav@ti.com>
 Date: Fri, 19 Oct 2012 02:01:39 +0530
 Subject: [PATCH] ARM: AM33XX: hwmod: Remove wrong INIT_NO_RESET/IDLE flags
diff --git a/patches/linux-3.7-rc6/0098-f2fs-add-document.patch b/patches/linux-3.7/0100-f2fs-add-document.patch
index 367300f..5934e17 100644
--- a/patches/linux-3.7-rc6/0098-f2fs-add-document.patch
+++ b/patches/linux-3.7/0100-f2fs-add-document.patch
@@ -1,4 +1,3 @@
-From c7823b127b80e70f1eabc0af8ddcab7640cc9d41 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:25:11 +0000
 Subject: [PATCH] f2fs: add document
diff --git a/patches/linux-3.7-rc6/0099-f2fs-add-on-disk-layout.patch b/patches/linux-3.7/0101-f2fs-add-on-disk-layout.patch
index be4892c..fc1aac2 100644
--- a/patches/linux-3.7-rc6/0099-f2fs-add-on-disk-layout.patch
+++ b/patches/linux-3.7/0101-f2fs-add-on-disk-layout.patch
@@ -1,4 +1,3 @@
-From 902033dcdb656694672091702bc88f5020b69443 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:26:00 +0000
 Subject: [PATCH] f2fs: add on-disk layout
diff --git a/patches/linux-3.7-rc6/0100-f2fs-add-superblock-and-major-in-memory-structure.patch b/patches/linux-3.7/0102-f2fs-add-superblock-and-major-in-memory-structure.patch
index 4f978c2..25cfa81 100644
--- a/patches/linux-3.7-rc6/0100-f2fs-add-superblock-and-major-in-memory-structure.patch
+++ b/patches/linux-3.7/0102-f2fs-add-superblock-and-major-in-memory-structure.patch
@@ -1,4 +1,3 @@
-From 3cfaeeaa816257ae02bbd9486355ad02abbc4c08 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:26:49 +0000
 Subject: [PATCH] f2fs: add superblock and major in-memory structure
diff --git a/patches/linux-3.7-rc6/0101-f2fs-add-super-block-operations.patch b/patches/linux-3.7/0103-f2fs-add-super-block-operations.patch
index 84e9529..420a742 100644
--- a/patches/linux-3.7-rc6/0101-f2fs-add-super-block-operations.patch
+++ b/patches/linux-3.7/0103-f2fs-add-super-block-operations.patch
@@ -1,4 +1,3 @@
-From b75928193c6e929da5808d20204910c4c7b4eed7 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:27:13 +0000
 Subject: [PATCH] f2fs: add super block operations
diff --git a/patches/linux-3.7-rc6/0102-f2fs-add-checkpoint-operations.patch b/patches/linux-3.7/0104-f2fs-add-checkpoint-operations.patch
index 7da534b..0bbb10b 100644
--- a/patches/linux-3.7-rc6/0102-f2fs-add-checkpoint-operations.patch
+++ b/patches/linux-3.7/0104-f2fs-add-checkpoint-operations.patch
@@ -1,4 +1,3 @@
-From d7db5b2e4d88ad2fa8f6d03c653e081593e8602d Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:28:03 +0000
 Subject: [PATCH] f2fs: add checkpoint operations
diff --git a/patches/linux-3.7-rc6/0103-f2fs-add-node-operations.patch b/patches/linux-3.7/0105-f2fs-add-node-operations.patch
index 0acac64..f8f47b6 100644
--- a/patches/linux-3.7-rc6/0103-f2fs-add-node-operations.patch
+++ b/patches/linux-3.7/0105-f2fs-add-node-operations.patch
@@ -1,4 +1,3 @@
-From ccdfa2eae0b5f0324955f0f24f34e47dc926bad7 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:28:19 +0000
 Subject: [PATCH] f2fs: add node operations
diff --git a/patches/linux-3.7-rc6/0104-f2fs-add-segment-operations.patch b/patches/linux-3.7/0106-f2fs-add-segment-operations.patch
index 958a1e2..27b1327 100644
--- a/patches/linux-3.7-rc6/0104-f2fs-add-segment-operations.patch
+++ b/patches/linux-3.7/0106-f2fs-add-segment-operations.patch
@@ -1,4 +1,3 @@
-From 781489b7a9285a53af3273801286908a68d5ab50 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:28:47 +0000
 Subject: [PATCH] f2fs: add segment operations
diff --git a/patches/linux-3.7-rc6/0105-f2fs-add-file-operations.patch b/patches/linux-3.7/0107-f2fs-add-file-operations.patch
index 0416dee..1739ca8 100644
--- a/patches/linux-3.7-rc6/0105-f2fs-add-file-operations.patch
+++ b/patches/linux-3.7/0107-f2fs-add-file-operations.patch
@@ -1,4 +1,3 @@
-From 4d8f1a7a068621436faf7b1b17e6a330e0eb3a79 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:29:21 +0000
 Subject: [PATCH] f2fs: add file operations
diff --git a/patches/linux-3.7-rc6/0106-f2fs-add-address-space-operations-for-data.patch b/patches/linux-3.7/0108-f2fs-add-address-space-operations-for-data.patch
index 998552a..b2a51bf 100644
--- a/patches/linux-3.7-rc6/0106-f2fs-add-address-space-operations-for-data.patch
+++ b/patches/linux-3.7/0108-f2fs-add-address-space-operations-for-data.patch
@@ -1,4 +1,3 @@
-From 451af621e358f0ac96c3fe8b2dfd940fbebcda29 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:29:49 +0000
 Subject: [PATCH] f2fs: add address space operations for data
diff --git a/patches/linux-3.7-rc6/0107-f2fs-add-core-inode-operations.patch b/patches/linux-3.7/0109-f2fs-add-core-inode-operations.patch
index 60484b6..d0c5018 100644
--- a/patches/linux-3.7-rc6/0107-f2fs-add-core-inode-operations.patch
+++ b/patches/linux-3.7/0109-f2fs-add-core-inode-operations.patch
@@ -1,4 +1,3 @@
-From dcf1bc84b5065c486a3eb6d516b3f7d150138120 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:30:16 +0000
 Subject: [PATCH] f2fs: add core inode operations
diff --git a/patches/linux-3.7-rc6/0108-f2fs-add-inode-operations-for-special-inodes.patch b/patches/linux-3.7/0110-f2fs-add-inode-operations-for-special-inodes.patch
index 4992a4e..0171957 100644
--- a/patches/linux-3.7-rc6/0108-f2fs-add-inode-operations-for-special-inodes.patch
+++ b/patches/linux-3.7/0110-f2fs-add-inode-operations-for-special-inodes.patch
@@ -1,4 +1,3 @@
-From 9a81dfce3a0c412925ec2fb68becab30e774089e Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:30:45 +0000
 Subject: [PATCH] f2fs: add inode operations for special inodes
diff --git a/patches/linux-3.7-rc6/0109-f2fs-add-core-directory-operations.patch b/patches/linux-3.7/0111-f2fs-add-core-directory-operations.patch
index ac2824b..60b6b2f 100644
--- a/patches/linux-3.7-rc6/0109-f2fs-add-core-directory-operations.patch
+++ b/patches/linux-3.7/0111-f2fs-add-core-directory-operations.patch
@@ -1,4 +1,3 @@
-From 39207d517eb7f9f43205c6fc2f0c3a9a6d398f97 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:31:34 +0000
 Subject: [PATCH] f2fs: add core directory operations
diff --git a/patches/linux-3.7-rc6/0110-f2fs-add-xattr-and-acl-functionalities.patch b/patches/linux-3.7/0112-f2fs-add-xattr-and-acl-functionalities.patch
index eead241..165a8f4 100644
--- a/patches/linux-3.7-rc6/0110-f2fs-add-xattr-and-acl-functionalities.patch
+++ b/patches/linux-3.7/0112-f2fs-add-xattr-and-acl-functionalities.patch
@@ -1,4 +1,3 @@
-From 8e21f5b0090aea281121c14542c55c7043e5168b Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:31:46 +0000
 Subject: [PATCH] f2fs: add xattr and acl functionalities
diff --git a/patches/linux-3.7-rc6/0111-f2fs-add-garbage-collection-functions.patch b/patches/linux-3.7/0113-f2fs-add-garbage-collection-functions.patch
index ef99275..736984b 100644
--- a/patches/linux-3.7-rc6/0111-f2fs-add-garbage-collection-functions.patch
+++ b/patches/linux-3.7/0113-f2fs-add-garbage-collection-functions.patch
@@ -1,4 +1,3 @@
-From 441b0d2cd8b763ad0f4b5e6294c354e5ac4beee2 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:32:20 +0000
 Subject: [PATCH] f2fs: add garbage collection functions
diff --git a/patches/linux-3.7-rc6/0112-f2fs-add-recovery-routines-for-roll-forward.patch b/patches/linux-3.7/0114-f2fs-add-recovery-routines-for-roll-forward.patch
index 39a629a..6edde8e 100644
--- a/patches/linux-3.7-rc6/0112-f2fs-add-recovery-routines-for-roll-forward.patch
+++ b/patches/linux-3.7/0114-f2fs-add-recovery-routines-for-roll-forward.patch
@@ -1,4 +1,3 @@
-From a458712f9bd670469b3aa1c474bbdc48465af27c Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:32:56 +0000
 Subject: [PATCH] f2fs: add recovery routines for roll-forward
diff --git a/patches/linux-3.7-rc6/0113-f2fs-update-Kconfig-and-Makefile.patch b/patches/linux-3.7/0115-f2fs-update-Kconfig-and-Makefile.patch
index 263eef8..24c8d01 100644
--- a/patches/linux-3.7-rc6/0113-f2fs-update-Kconfig-and-Makefile.patch
+++ b/patches/linux-3.7/0115-f2fs-update-Kconfig-and-Makefile.patch
@@ -1,4 +1,3 @@
-From 4c78c6c29f9986e46020c04c8741db373565f473 Mon Sep 17 00:00:00 2001
 From: ??? <jaegeuk.kim@samsung.com>
 Date: Tue, 23 Oct 2012 02:33:28 +0000
 Subject: [PATCH] f2fs: update Kconfig and Makefile
diff --git a/patches/linux-3.7-rc6/0114-f2fs-gc.h-make-should_do_checkpoint-inline.patch b/patches/linux-3.7/0116-f2fs-gc.h-make-should_do_checkpoint-inline.patch
index 66d5782..bc3fa43 100644
--- a/patches/linux-3.7-rc6/0114-f2fs-gc.h-make-should_do_checkpoint-inline.patch
+++ b/patches/linux-3.7/0116-f2fs-gc.h-make-should_do_checkpoint-inline.patch
@@ -1,4 +1,3 @@
-From 26e33463d5f5705a2d0159209aff0404b97095c6 Mon Sep 17 00:00:00 2001
 From: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
 Date: Tue, 23 Oct 2012 18:21:46 +0000
 Subject: [PATCH] f2fs: gc.h: make should_do_checkpoint() inline
diff --git a/patches/linux-3.7-rc6/0115-f2fs-move-statistics-code-into-one-file.patch b/patches/linux-3.7/0117-f2fs-move-statistics-code-into-one-file.patch
index ec8bdd0..cee899f 100644
--- a/patches/linux-3.7-rc6/0115-f2fs-move-statistics-code-into-one-file.patch
+++ b/patches/linux-3.7/0117-f2fs-move-statistics-code-into-one-file.patch
@@ -1,4 +1,3 @@
-From b6f5f093ec14b476ba7d0282488391add23365f6 Mon Sep 17 00:00:00 2001
 From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 Date: Tue, 23 Oct 2012 18:22:41 +0000
 Subject: [PATCH] f2fs: move statistics code into one file
diff --git a/patches/linux-3.7-rc6/0116-f2fs-move-proc-files-to-debugfs.patch b/patches/linux-3.7/0118-f2fs-move-proc-files-to-debugfs.patch
index aa87b59..1ae0d1a 100644
--- a/patches/linux-3.7-rc6/0116-f2fs-move-proc-files-to-debugfs.patch
+++ b/patches/linux-3.7/0118-f2fs-move-proc-files-to-debugfs.patch
@@ -1,4 +1,3 @@
-From 205e2ea14ae2f19cae72407e023d736c5c781027 Mon Sep 17 00:00:00 2001
 From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 Date: Tue, 23 Oct 2012 19:20:28 +0000
 Subject: [PATCH] f2fs: move proc files to debugfs
diff --git a/patches/linux-3.7-rc6/0117-f2fs-compile-fix.patch b/patches/linux-3.7/0119-f2fs-compile-fix.patch
index d93a4ea..70024ff 100644
--- a/patches/linux-3.7-rc6/0117-f2fs-compile-fix.patch
+++ b/patches/linux-3.7/0119-f2fs-compile-fix.patch
@@ -1,4 +1,3 @@
-From 7988df6c5e0a9d19cbe68831a9e1ce11e85e35ad Mon Sep 17 00:00:00 2001
 From: Koen Kooi <koen@dominion.thruhere.net>
 Date: Wed, 24 Oct 2012 11:34:54 +0200
 Subject: [PATCH] f2fs: compile fix
diff --git a/patches/linux-3.7/0121-6lowpan-lowpan_is_iid_16_bit_compressable-does-not-d.patch b/patches/linux-3.7/0121-6lowpan-lowpan_is_iid_16_bit_compressable-does-not-d.patch
new file mode 100644
index 0000000..5833c3c
--- /dev/null
+++ b/patches/linux-3.7/0121-6lowpan-lowpan_is_iid_16_bit_compressable-does-not-d.patch
@@ -0,0 +1,40 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Mon, 25 Jun 2012 19:45:33 +0000
+Subject: [PATCH] 6lowpan: lowpan_is_iid_16_bit_compressable() does not detect
+ compressable address correctly
+
+The current test is not RFC6282 compliant. The same issue has been found
+out and fixed in Contiki. This patch is basicaly a port of their fix.
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.h |   14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/net/ieee802154/6lowpan.h b/net/ieee802154/6lowpan.h
+index 8c2251f..efd1a57 100644
+--- a/net/ieee802154/6lowpan.h
++++ b/net/ieee802154/6lowpan.h
+@@ -87,14 +87,16 @@
+ #define is_addr_link_local(a) (((a)->s6_addr16[0]) == 0x80FE)
+ 
+ /*
+- * check whether we can compress the IID to 16 bits,
+- * it's possible for unicast adresses with first 49 bits are zero only.
+- */
++* check whether we can compress the IID to 16 bits,
++* it's possible for unicast adresses with first 49 bits are zero only.
++*/
+ #define lowpan_is_iid_16_bit_compressable(a)	\
+ 	((((a)->s6_addr16[4]) == 0) &&		\
+-	 (((a)->s6_addr16[5]) == 0) &&		\
+-	 (((a)->s6_addr16[6]) == 0) &&		\
+-	 ((((a)->s6_addr[14]) & 0x80) == 0))
++	 (((a)->s6_addr[10]) == 0) &&		\
++	 (((a)->s6_addr[11]) == 0xff) &&	\
++	 (((a)->s6_addr[12]) == 0xfe) &&	\
++	 (((a)->s6_addr[13]) == 0))
++
+ 
+ /* multicast address */
+ #define is_addr_mcast(a) (((a)->s6_addr[0]) == 0xFF)
diff --git a/patches/linux-3.7/0122-6lowpan-next-header-is-not-properly-set-upon-decompr.patch b/patches/linux-3.7/0122-6lowpan-next-header-is-not-properly-set-upon-decompr.patch
new file mode 100644
index 0000000..ba2d639
--- /dev/null
+++ b/patches/linux-3.7/0122-6lowpan-next-header-is-not-properly-set-upon-decompr.patch
@@ -0,0 +1,30 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Mon, 25 Jun 2012 19:45:45 +0000
+Subject: [PATCH] 6lowpan: next header is not properly set upon decompression
+ of a UDP header.
+
+This causes a drop of the UDP packet.
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |    5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index 6d42c17..b53a71a4 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -913,9 +913,12 @@ lowpan_process_data(struct sk_buff *skb)
+ 	}
+ 
+ 	/* UDP data uncompression */
+-	if (iphc0 & LOWPAN_IPHC_NH_C)
++	if (iphc0 & LOWPAN_IPHC_NH_C) {
+ 		if (lowpan_uncompress_udp_header(skb))
+ 			goto drop;
++		hdr.nexthdr = UIP_PROTO_UDP;
++	}
++
+ 
+ 	/* Not fragmented package */
+ 	hdr.payload_len = htons(skb->len);
diff --git a/patches/linux-3.7/0123-6lowpan-always-enable-link-layer-acknowledgments.patch b/patches/linux-3.7/0123-6lowpan-always-enable-link-layer-acknowledgments.patch
new file mode 100644
index 0000000..3b333ca
--- /dev/null
+++ b/patches/linux-3.7/0123-6lowpan-always-enable-link-layer-acknowledgments.patch
@@ -0,0 +1,30 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Mon, 25 Jun 2012 19:48:12 +0000
+Subject: [PATCH] 6lowpan: always enable link-layer acknowledgments
+
+This feature is especially important when using fragmentation, because
+the reassembly mechanism can not recover from the loss of a fragment.
+
+Note that some hardware ignore this flag and not will not transmit any
+acknowledgments if this is set.
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index b53a71a4..49d91df 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -589,6 +589,10 @@ static int lowpan_header_create(struct sk_buff *skb,
+ 
+ 		mac_cb(skb)->flags = IEEE802154_FC_TYPE_DATA;
+ 
++		/* request acknowledgment when possible */
++		if (!lowpan_is_addr_broadcast(daddr))
++			mac_cb(skb)->flags |= MAC_CB_FLAG_ACKREQ;
++
+ 		return dev_hard_header(skb, lowpan_dev_info(dev)->real_dev,
+ 				type, (void *)&da, (void *)&sa, skb->len);
+ 	}
diff --git a/patches/linux-3.7/0124-mac802154-turn-on-ACK-when-enabled-by-the-upper-laye.patch b/patches/linux-3.7/0124-mac802154-turn-on-ACK-when-enabled-by-the-upper-laye.patch
new file mode 100644
index 0000000..e809fd5
--- /dev/null
+++ b/patches/linux-3.7/0124-mac802154-turn-on-ACK-when-enabled-by-the-upper-laye.patch
@@ -0,0 +1,22 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Tue, 17 Jul 2012 17:59:39 -0400
+Subject: [PATCH] mac802154: turn on ACK when enabled by the upper layers
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/mac802154/wpan.c |    2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/net/mac802154/wpan.c b/net/mac802154/wpan.c
+index f30f6d4..d6aea7f 100644
+--- a/net/mac802154/wpan.c
++++ b/net/mac802154/wpan.c
+@@ -149,6 +149,8 @@ static int mac802154_header_create(struct sk_buff *skb,
+ 
+ 	head[pos++] = mac_cb(skb)->seq; /* DSN/BSN */
+ 	fc = mac_cb_type(skb);
++	if (mac_cb_is_ackreq(skb))
++		fc |= IEEE802154_FC_ACK_REQ;
+ 
+ 	if (!saddr) {
+ 		spin_lock_bh(&priv->mib_lock);
diff --git a/patches/linux-3.7/0125-6lowpan-use-short-IEEE-802.15.4-addresses-for-broadc.patch b/patches/linux-3.7/0125-6lowpan-use-short-IEEE-802.15.4-addresses-for-broadc.patch
new file mode 100644
index 0000000..ec2ade7
--- /dev/null
+++ b/patches/linux-3.7/0125-6lowpan-use-short-IEEE-802.15.4-addresses-for-broadc.patch
@@ -0,0 +1,52 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Tue, 4 Sep 2012 23:48:13 -0400
+Subject: [PATCH] 6lowpan: use short IEEE 802.15.4 addresses for broadcast
+ destination
+
+It is intended that the IEEE 802.15.4 standard uses the 0xFFFF short address (2
+bytes) for message broadcasting.
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |   21 +++++++++++++--------
+ 1 file changed, 13 insertions(+), 8 deletions(-)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index 49d91df..8a2ee95 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -577,21 +577,26 @@ static int lowpan_header_create(struct sk_buff *skb,
+ 	 * this isn't implemented in mainline yet, so currently we assign 0xff
+ 	 */
+ 	{
++		mac_cb(skb)->flags = IEEE802154_FC_TYPE_DATA;
++
+ 		/* prepare wpan address data */
+ 		sa.addr_type = IEEE802154_ADDR_LONG;
+ 		sa.pan_id = 0xff;
+-
+-		da.addr_type = IEEE802154_ADDR_LONG;
+-		da.pan_id = 0xff;
+-
+-		memcpy(&(da.hwaddr), daddr, 8);
+ 		memcpy(&(sa.hwaddr), saddr, 8);
+ 
+-		mac_cb(skb)->flags = IEEE802154_FC_TYPE_DATA;
++		da.pan_id = 0xff;
++		/* if the destination address is the broadcast address,
++		   use short address */
++		if (lowpan_is_addr_broadcast(daddr)) {
++			da.addr_type = IEEE802154_ADDR_SHORT;
++			da.short_addr = IEEE802154_ADDR_BROADCAST;
++		} else {
++			da.addr_type = IEEE802154_ADDR_LONG;
++			memcpy(&(da.hwaddr), daddr, 8);
+ 
+-		/* request acknowledgment when possible */
+-		if (!lowpan_is_addr_broadcast(daddr))
++			/* request acknowledgment */
+ 			mac_cb(skb)->flags |= MAC_CB_FLAG_ACKREQ;
++		}
+ 
+ 		return dev_hard_header(skb, lowpan_dev_info(dev)->real_dev,
+ 				type, (void *)&da, (void *)&sa, skb->len);
diff --git a/patches/linux-3.7/0126-6lowpan-fix-first-fragment-FRAG1-handling.patch b/patches/linux-3.7/0126-6lowpan-fix-first-fragment-FRAG1-handling.patch
new file mode 100644
index 0000000..6abdd9d
--- /dev/null
+++ b/patches/linux-3.7/0126-6lowpan-fix-first-fragment-FRAG1-handling.patch
@@ -0,0 +1,136 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Sat, 8 Sep 2012 00:15:54 -0400
+Subject: [PATCH] 6lowpan: fix first fragment (FRAG1) handling
+
+The first fragment, FRAG1, must contain some payload according to the
+specs. However, as it is currently written, the first fragment will
+remain empty and only contain the 6lowpan headers.
+
+This patch also extract the transport layer information from the first
+fragment. This information is later on use when uncompressing UDP
+header.
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |   54 +++++++++++++++++++++++++++++++++++-----------
+ 1 file changed, 42 insertions(+), 12 deletions(-)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index 8a2ee95..38cecaf 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -654,7 +654,7 @@ static void lowpan_fragment_timer_expired(unsigned long entry_addr)
+ }
+ 
+ static struct lowpan_fragment *
+-lowpan_alloc_new_frame(struct sk_buff *skb, u8 len, u16 tag)
++lowpan_alloc_new_frame(struct sk_buff *skb, u16 len, u16 tag)
+ {
+ 	struct lowpan_fragment *frame;
+ 
+@@ -735,6 +735,18 @@ lowpan_process_data(struct sk_buff *skb)
+ 		/* adds the 3 MSB to the 8 LSB to retrieve the 11 bits length */
+ 		len = ((iphc0 & 7) << 8) | slen;
+ 
++		if ((iphc0 & LOWPAN_DISPATCH_MASK) == LOWPAN_DISPATCH_FRAG1) {
++			pr_debug("%s received a FRAG1 packet (tag: %d, "
++				 "size of the entire IP packet: %d)"
++				 , __func__, tag, len);
++		} else { /* FRAGN */
++			if (lowpan_fetch_skb_u8(skb, &offset))
++				goto unlock_and_drop;
++			pr_debug("%s received a FRAGN packet (tag: %d, "
++				 "size of the entire IP packet: %d, "
++				 "offset: %d)", __func__, tag, len, offset * 8);
++		}
++
+ 		/*
+ 		 * check if frame assembling with the same tag is
+ 		 * already in progress
+@@ -749,17 +761,13 @@ lowpan_process_data(struct sk_buff *skb)
+ 
+ 		/* alloc new frame structure */
+ 		if (!found) {
++			pr_debug("%s first fragment received for tag %d, "
++				 "begin packet reassembly", __func__, tag);
+ 			frame = lowpan_alloc_new_frame(skb, len, tag);
+ 			if (!frame)
+ 				goto unlock_and_drop;
+ 		}
+ 
+-		if ((iphc0 & LOWPAN_DISPATCH_MASK) == LOWPAN_DISPATCH_FRAG1)
+-			goto unlock_and_drop;
+-
+-		if (lowpan_fetch_skb_u8(skb, &offset)) /* fetch offset */
+-			goto unlock_and_drop;
+-
+ 		/* if payload fits buffer, copy it */
+ 		if (likely((offset * 8 + skb->len) <= frame->length))
+ 			skb_copy_to_linear_data_offset(frame->skb, offset * 8,
+@@ -777,6 +785,10 @@ lowpan_process_data(struct sk_buff *skb)
+ 			list_del(&frame->list);
+ 			spin_unlock_bh(&flist_lock);
+ 
++			pr_debug("%s successfully reassembled fragment "
++				 "(tag %d)", __func__, tag);
++
++
+ 			dev_kfree_skb(skb);
+ 			skb = frame->skb;
+ 			kfree(frame);
+@@ -976,13 +988,13 @@ static int lowpan_get_mac_header_length(struct sk_buff *skb)
+ 
+ static int
+ lowpan_fragment_xmit(struct sk_buff *skb, u8 *head,
+-			int mlen, int plen, int offset)
++			int mlen, int plen, int offset, int type)
+ {
+ 	struct sk_buff *frag;
+ 	int hlen, ret;
+ 
+-	/* if payload length is zero, therefore it's a first fragment */
+-	hlen = (plen == 0 ? LOWPAN_FRAG1_HEAD_SIZE :  LOWPAN_FRAGN_HEAD_SIZE);
++	hlen = (type == LOWPAN_DISPATCH_FRAG1 ? LOWPAN_FRAG1_HEAD_SIZE :
++			LOWPAN_FRAGN_HEAD_SIZE);
+ 
+ 	lowpan_raw_dump_inline(__func__, "6lowpan fragment header", head, hlen);
+ 
+@@ -1025,7 +1037,18 @@ lowpan_skb_fragmentation(struct sk_buff *skb)
+ 	head[2] = tag >> 8;
+ 	head[3] = tag & 0xff;
+ 
+-	err = lowpan_fragment_xmit(skb, head, header_length, 0, 0);
++	err = lowpan_fragment_xmit(skb, head, header_length, LOWPAN_FRAG_SIZE,
++				   0, LOWPAN_DISPATCH_FRAG1);
++
++	if (err) {
++#if DEBUG
++		pr_debug("%s unable to send FRAG1 packet (tag: %d)",
++			 __func__, tag);
++#endif /* DEBUG */
++		goto exit;
++	}
++
++	offset = LOWPAN_FRAG_SIZE;
+ 
+ 	/* next fragment header */
+ 	head[0] &= ~LOWPAN_DISPATCH_FRAG1;
+@@ -1040,10 +1063,17 @@ lowpan_skb_fragmentation(struct sk_buff *skb)
+ 			len = payload_length - offset;
+ 
+ 		err = lowpan_fragment_xmit(skb, head, header_length,
+-							len, offset);
++					   len, offset, LOWPAN_DISPATCH_FRAGN);
++		if (err) {
++			pr_debug("%s unable to send a subsequent FRAGN packet "
++				 "(tag: %d, offset: %d", __func__, tag, offset);
++			goto exit;
++		}
++
+ 		offset += len;
+ 	}
+ 
++exit:
+ 	return err;
+ }
+ 
diff --git a/patches/linux-3.7/0127-6lowpan-store-fragment-tag-values-per-device-instead.patch b/patches/linux-3.7/0127-6lowpan-store-fragment-tag-values-per-device-instead.patch
new file mode 100644
index 0000000..06052e6
--- /dev/null
+++ b/patches/linux-3.7/0127-6lowpan-store-fragment-tag-values-per-device-instead.patch
@@ -0,0 +1,64 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Fri, 6 Jul 2012 17:39:22 -0400
+Subject: [PATCH] 6lowpan: store fragment tag values per device instead of net
+ stack wide
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |    9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index 38cecaf..eb8003b 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -104,6 +104,7 @@ static const u8 lowpan_llprefix[] = {0xfe, 0x80};
+ struct lowpan_dev_info {
+ 	struct net_device	*real_dev; /* real WPAN device ptr */
+ 	struct mutex		dev_list_mtx; /* mutex for list ops */
++	unsigned short fragment_tag;
+ };
+ 
+ struct lowpan_dev_record {
+@@ -120,7 +121,6 @@ struct lowpan_fragment {
+ 	struct list_head	list;		/* fragments list */
+ };
+ 
+-static unsigned short fragment_tag;
+ static LIST_HEAD(lowpan_fragments);
+ static DEFINE_SPINLOCK(flist_lock);
+ 
+@@ -1022,14 +1022,14 @@ lowpan_fragment_xmit(struct sk_buff *skb, u8 *head,
+ }
+ 
+ static int
+-lowpan_skb_fragmentation(struct sk_buff *skb)
++lowpan_skb_fragmentation(struct sk_buff *skb, struct net_device *dev)
+ {
+ 	int  err, header_length, payload_length, tag, offset = 0;
+ 	u8 head[5];
+ 
+ 	header_length = lowpan_get_mac_header_length(skb);
+ 	payload_length = skb->len - header_length;
+-	tag = fragment_tag++;
++	tag = lowpan_dev_info(dev)->fragment_tag++;
+ 
+ 	/* first fragment header */
+ 	head[0] = LOWPAN_DISPATCH_FRAG1 | ((payload_length >> 8) & 0x7);
+@@ -1095,7 +1095,7 @@ static netdev_tx_t lowpan_xmit(struct sk_buff *skb, struct net_device *dev)
+ 	}
+ 
+ 	pr_debug("frame is too big, fragmentation is needed\n");
+-	err = lowpan_skb_fragmentation(skb);
++	err = lowpan_skb_fragmentation(skb, dev);
+ error:
+ 	dev_kfree_skb(skb);
+ out:
+@@ -1216,6 +1216,7 @@ static int lowpan_newlink(struct net *src_net, struct net_device *dev,
+ 		return -ENODEV;
+ 
+ 	lowpan_dev_info(dev)->real_dev = real_dev;
++	lowpan_dev_info(dev)->fragment_tag = 0;
+ 	mutex_init(&lowpan_dev_info(dev)->dev_list_mtx);
+ 
+ 	entry = kzalloc(sizeof(struct lowpan_dev_record), GFP_KERNEL);
diff --git a/patches/linux-3.7/0128-6lowpan-obtain-IEEE802.15.4-sequence-number-from-the.patch b/patches/linux-3.7/0128-6lowpan-obtain-IEEE802.15.4-sequence-number-from-the.patch
new file mode 100644
index 0000000..69a86be
--- /dev/null
+++ b/patches/linux-3.7/0128-6lowpan-obtain-IEEE802.15.4-sequence-number-from-the.patch
@@ -0,0 +1,47 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Fri, 6 Jul 2012 17:46:37 -0400
+Subject: [PATCH] 6lowpan: obtain IEEE802.15.4 sequence number from the MAC
+ layer
+
+This patch sets the sequence number in the frame format. Without this
+fix, the sequence number is always set to 0. This makes trafic analysis
+very hard.
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |    8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index eb8003b..24b83fa 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -578,6 +578,7 @@ static int lowpan_header_create(struct sk_buff *skb,
+ 	 */
+ 	{
+ 		mac_cb(skb)->flags = IEEE802154_FC_TYPE_DATA;
++		mac_cb(skb)->seq = ieee802154_mlme_ops(dev)->get_dsn(dev);
+ 
+ 		/* prepare wpan address data */
+ 		sa.addr_type = IEEE802154_ADDR_LONG;
+@@ -1123,6 +1124,12 @@ static u16 lowpan_get_short_addr(const struct net_device *dev)
+ 	return ieee802154_mlme_ops(real_dev)->get_short_addr(real_dev);
+ }
+ 
++static u8 lowpan_get_dsn(const struct net_device *dev)
++{
++	struct net_device *real_dev = lowpan_dev_info(dev)->real_dev;
++	return ieee802154_mlme_ops(real_dev)->get_dsn(real_dev);
++}
++
+ static struct header_ops lowpan_header_ops = {
+ 	.create	= lowpan_header_create,
+ };
+@@ -1136,6 +1143,7 @@ static struct ieee802154_mlme_ops lowpan_mlme = {
+ 	.get_pan_id = lowpan_get_pan_id,
+ 	.get_phy = lowpan_get_phy,
+ 	.get_short_addr = lowpan_get_short_addr,
++	.get_dsn = lowpan_get_dsn,
+ };
+ 
+ static void lowpan_setup(struct net_device *dev)
diff --git a/patches/linux-3.7/0129-6lowpan-add-a-new-parameter-in-sysfs-to-turn-on-off-.patch b/patches/linux-3.7/0129-6lowpan-add-a-new-parameter-in-sysfs-to-turn-on-off-.patch
new file mode 100644
index 0000000..e1100aa
--- /dev/null
+++ b/patches/linux-3.7/0129-6lowpan-add-a-new-parameter-in-sysfs-to-turn-on-off-.patch
@@ -0,0 +1,44 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Thu, 12 Jul 2012 17:47:39 -0400
+Subject: [PATCH] 6lowpan: add a new parameter in sysfs to turn on/off ACK
+ request at MAC layer
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |    9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index 24b83fa..f8fcdae 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -62,6 +62,8 @@
+ 
+ #include "6lowpan.h"
+ 
++static bool req_802154_ack;
++
+ /* TTL uncompression values */
+ static const u8 lowpan_ttl_values[] = {0, 1, 64, 255};
+ 
+@@ -596,7 +598,8 @@ static int lowpan_header_create(struct sk_buff *skb,
+ 			memcpy(&(da.hwaddr), daddr, 8);
+ 
+ 			/* request acknowledgment */
+-			mac_cb(skb)->flags |= MAC_CB_FLAG_ACKREQ;
++			if (req_802154_ack)
++				mac_cb(skb)->flags |= MAC_CB_FLAG_ACKREQ;
+ 		}
+ 
+ 		return dev_hard_header(skb, lowpan_dev_info(dev)->real_dev,
+@@ -1366,6 +1369,10 @@ static void __exit lowpan_cleanup_module(void)
+ }
+ 
+ module_init(lowpan_init_module);
++
++module_param(req_802154_ack, bool, 0644);
++MODULE_PARM_DESC(req_802154_ack, "request link-layer (i.e. IEEE 802.15.4) acknowledgments");
++
+ module_exit(lowpan_cleanup_module);
+ MODULE_LICENSE("GPL");
+ MODULE_ALIAS_RTNL_LINK("lowpan");
diff --git a/patches/linux-3.7/0130-6lowpan-use-the-PANID-provided-by-the-device-instead.patch b/patches/linux-3.7/0130-6lowpan-use-the-PANID-provided-by-the-device-instead.patch
new file mode 100644
index 0000000..8e90874
--- /dev/null
+++ b/patches/linux-3.7/0130-6lowpan-use-the-PANID-provided-by-the-device-instead.patch
@@ -0,0 +1,29 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Mon, 24 Sep 2012 23:11:46 -0400
+Subject: [PATCH] 6lowpan: use the PANID provided by the device instead of a
+ static value
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |    6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index f8fcdae..9711038 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -584,10 +584,12 @@ static int lowpan_header_create(struct sk_buff *skb,
+ 
+ 		/* prepare wpan address data */
+ 		sa.addr_type = IEEE802154_ADDR_LONG;
+-		sa.pan_id = 0xff;
++		sa.pan_id = ieee802154_mlme_ops(dev)->get_pan_id(dev);
++
+ 		memcpy(&(sa.hwaddr), saddr, 8);
++		/* intra-PAN communications */
++		da.pan_id = ieee802154_mlme_ops(dev)->get_pan_id(dev);
+ 
+-		da.pan_id = 0xff;
+ 		/* if the destination address is the broadcast address,
+ 		   use short address */
+ 		if (lowpan_is_addr_broadcast(daddr)) {
diff --git a/patches/linux-3.7/0131-6lowpan-modify-udp-compression-uncompression-to-matc.patch b/patches/linux-3.7/0131-6lowpan-modify-udp-compression-uncompression-to-matc.patch
new file mode 100644
index 0000000..e99cc9a
--- /dev/null
+++ b/patches/linux-3.7/0131-6lowpan-modify-udp-compression-uncompression-to-matc.patch
@@ -0,0 +1,89 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Mon, 24 Sep 2012 22:56:51 -0400
+Subject: [PATCH] 6lowpan: modify udp compression/uncompression to match the
+ standard
+
+The previous code would just compress the UDP header and send the compressed
+UDP header along with the uncompressed one.
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |   36 +++++++++++++++++++++++++++++++++---
+ 1 file changed, 33 insertions(+), 3 deletions(-)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index 9711038..9c7ac2e 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -286,6 +286,9 @@ lowpan_compress_udp_header(u8 **hc06_ptr, struct sk_buff *skb)
+ 	/* checksum is always inline */
+ 	memcpy(*hc06_ptr, &uh->check, 2);
+ 	*hc06_ptr += 2;
++
++	/* skip the UDP header */
++	skb_pull(skb, sizeof(struct udphdr));
+ }
+ 
+ static inline int lowpan_fetch_skb_u8(struct sk_buff *skb, u8 *val)
+@@ -311,9 +314,8 @@ static inline int lowpan_fetch_skb_u16(struct sk_buff *skb, u16 *val)
+ }
+ 
+ static int
+-lowpan_uncompress_udp_header(struct sk_buff *skb)
++lowpan_uncompress_udp_header(struct sk_buff *skb, struct udphdr *uh)
+ {
+-	struct udphdr *uh = udp_hdr(skb);
+ 	u8 tmp;
+ 
+ 	if (!uh)
+@@ -354,12 +356,19 @@ lowpan_uncompress_udp_header(struct sk_buff *skb)
+ 			break;
+ 		}
+ 
++
+ 		pr_debug("uncompressed UDP ports: src = %d, dst = %d\n",
+ 			 uh->source, uh->dest);
+ 
+ 		/* copy checksum */
+ 		memcpy(&uh->check, &skb->data[0], 2);
+ 		skb_pull(skb, 2);
++
++		/* UDP lenght needs to be infered from the lower layers
++		   here, we obtain the hint from the remaining size of the
++		   frame */
++		uh->len = htons(skb->len + sizeof(struct udphdr));
++		pr_debug("uncompressed UDP length: src = %d", uh->len);
+ 	} else {
+ 		pr_debug("ERROR: unsupported NH format\n");
+ 		goto err;
+@@ -941,8 +950,29 @@ lowpan_process_data(struct sk_buff *skb)
+ 
+ 	/* UDP data uncompression */
+ 	if (iphc0 & LOWPAN_IPHC_NH_C) {
+-		if (lowpan_uncompress_udp_header(skb))
++		struct udphdr uh;
++		struct sk_buff *new;
++		if (lowpan_uncompress_udp_header(skb, &uh))
+ 			goto drop;
++
++		/* place the real UDP header instead of the
++		   compressed UDP header */
++		new = skb_copy_expand(skb, sizeof(struct udphdr),
++				      skb_tailroom(skb), GFP_ATOMIC);
++		kfree_skb(skb);
++
++		if (!new)
++			return -ENOMEM;
++
++		skb = new ;
++
++		skb_push(skb, sizeof(struct udphdr));
++		skb_reset_transport_header(skb);
++		skb_copy_to_linear_data(skb, &uh, sizeof(struct udphdr));
++
++		lowpan_raw_dump_table(__func__, "raw UDP header dump",
++				      (u8 *)&uh, sizeof(uh));
++
+ 		hdr.nexthdr = UIP_PROTO_UDP;
+ 	}
+ 
diff --git a/patches/linux-3.7/0132-6lowpan-make-memory-allocation-atomic-during-6lowpan.patch b/patches/linux-3.7/0132-6lowpan-make-memory-allocation-atomic-during-6lowpan.patch
new file mode 100644
index 0000000..a4fc7be
--- /dev/null
+++ b/patches/linux-3.7/0132-6lowpan-make-memory-allocation-atomic-during-6lowpan.patch
@@ -0,0 +1,26 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Mon, 3 Sep 2012 23:26:27 -0400
+Subject: [PATCH] 6lowpan: make memory allocation atomic during 6lowpan header
+ creation
+
+This is prevent various crashes when using the serial driver (not yet in
+the tree).
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/ieee802154/6lowpan.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index 9c7ac2e..70ff171 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -396,7 +396,7 @@ static int lowpan_header_create(struct sk_buff *skb,
+ 		/* TODO:
+ 		 * if this package isn't ipv6 one, where should it be routed?
+ 		 */
+-	head = kzalloc(100, GFP_KERNEL);
++	head = kzalloc(100, GFP_ATOMIC);
+ 	if (head == NULL)
+ 		return -ENOMEM;
+ 
diff --git a/patches/linux-3.7/0133-mac802154-make-mem-alloc-ATOMIC-to-prevent-schedulin.patch b/patches/linux-3.7/0133-mac802154-make-mem-alloc-ATOMIC-to-prevent-schedulin.patch
new file mode 100644
index 0000000..1159c0a
--- /dev/null
+++ b/patches/linux-3.7/0133-mac802154-make-mem-alloc-ATOMIC-to-prevent-schedulin.patch
@@ -0,0 +1,25 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Tue, 10 Jul 2012 11:36:28 -0400
+Subject: [PATCH] mac802154: make mem alloc ATOMIC to prevent "scheduling
+ while atomic" crashes
+
+These crashes occur mainly with the serial driver (not yet in the tree).
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/mac802154/wpan.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/net/mac802154/wpan.c b/net/mac802154/wpan.c
+index d6aea7f..49ba8df 100644
+--- a/net/mac802154/wpan.c
++++ b/net/mac802154/wpan.c
+@@ -143,7 +143,7 @@ static int mac802154_header_create(struct sk_buff *skb,
+ 	if (!daddr)
+ 		return -EINVAL;
+ 
+-	head = kzalloc(MAC802154_FRAME_HARD_HEADER_LEN, GFP_KERNEL);
++	head = kzalloc(MAC802154_FRAME_HARD_HEADER_LEN, GFP_ATOMIC);
+ 	if (head == NULL)
+ 		return -ENOMEM;
+ 
diff --git a/patches/linux-3.7/0134-mac802154-remove-unnecessary-spinlocks.patch b/patches/linux-3.7/0134-mac802154-remove-unnecessary-spinlocks.patch
new file mode 100644
index 0000000..0bc9c07
--- /dev/null
+++ b/patches/linux-3.7/0134-mac802154-remove-unnecessary-spinlocks.patch
@@ -0,0 +1,50 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Thu, 20 Sep 2012 23:44:19 -0400
+Subject: [PATCH] mac802154: remove unnecessary spinlocks
+
+These spinlock protects an int variable, that is always accessible in an
+atomic fashion.
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/mac802154/mib.c |   14 ++------------
+ 1 file changed, 2 insertions(+), 12 deletions(-)
+
+diff --git a/net/mac802154/mib.c b/net/mac802154/mib.c
+index f47781a..2339f8d 100644
+--- a/net/mac802154/mib.c
++++ b/net/mac802154/mib.c
+@@ -103,15 +103,10 @@ void mac802154_dev_set_short_addr(struct net_device *dev, u16 val)
+ u16 mac802154_dev_get_short_addr(const struct net_device *dev)
+ {
+ 	struct mac802154_sub_if_data *priv = netdev_priv(dev);
+-	u16 ret;
+ 
+ 	BUG_ON(dev->type != ARPHRD_IEEE802154);
+ 
+-	spin_lock_bh(&priv->mib_lock);
+-	ret = priv->short_addr;
+-	spin_unlock_bh(&priv->mib_lock);
+-
+-	return ret;
++	return priv->short_addr;
+ }
+ 
+ void mac802154_dev_set_ieee_addr(struct net_device *dev)
+@@ -131,15 +126,10 @@ void mac802154_dev_set_ieee_addr(struct net_device *dev)
+ u16 mac802154_dev_get_pan_id(const struct net_device *dev)
+ {
+ 	struct mac802154_sub_if_data *priv = netdev_priv(dev);
+-	u16 ret;
+ 
+ 	BUG_ON(dev->type != ARPHRD_IEEE802154);
+ 
+-	spin_lock_bh(&priv->mib_lock);
+-	ret = priv->pan_id;
+-	spin_unlock_bh(&priv->mib_lock);
+-
+-	return ret;
++	return priv->pan_id;
+ }
+ 
+ void mac802154_dev_set_pan_id(struct net_device *dev, u16 val)
diff --git a/patches/linux-3.7/0135-mac802154-re-introduce-MAC-primitives-required-to-se.patch b/patches/linux-3.7/0135-mac802154-re-introduce-MAC-primitives-required-to-se.patch
new file mode 100644
index 0000000..510c783
--- /dev/null
+++ b/patches/linux-3.7/0135-mac802154-re-introduce-MAC-primitives-required-to-se.patch
@@ -0,0 +1,100 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Thu, 20 Sep 2012 23:48:11 -0400
+Subject: [PATCH] mac802154: re-introduce MAC primitives required to
+ send/receive packets
+
+- mlme_assoc_req() and mlme_assoc_resp() are just place holder for the
+  moment (they prevent the two corresponding function pointers in the
+  mac802154_mlme_wpan structure to be left uninitialized)
+- mac802514_dev_get_bsn() and mac802514_dev_get_dsn() MAC primitives
+  were present in the Linux-Zigbee kernel and are being re-introduced.
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ net/mac802154/mac802154.h |    2 ++
+ net/mac802154/mac_cmd.c   |   22 +++++++++++++++++++++-
+ net/mac802154/mib.c       |   19 +++++++++++++++++++
+ 3 files changed, 42 insertions(+), 1 deletion(-)
+
+diff --git a/net/mac802154/mac802154.h b/net/mac802154/mac802154.h
+index a4dcaf1..18d4044 100644
+--- a/net/mac802154/mac802154.h
++++ b/net/mac802154/mac802154.h
+@@ -114,5 +114,7 @@ void mac802154_dev_set_ieee_addr(struct net_device *dev);
+ u16 mac802154_dev_get_pan_id(const struct net_device *dev);
+ void mac802154_dev_set_pan_id(struct net_device *dev, u16 val);
+ void mac802154_dev_set_page_channel(struct net_device *dev, u8 page, u8 chan);
++u8 mac802154_dev_get_dsn(const struct net_device *dev);
++u8 mac802154_dev_get_bsn(const struct net_device *dev);
+ 
+ #endif /* MAC802154_H */
+diff --git a/net/mac802154/mac_cmd.c b/net/mac802154/mac_cmd.c
+index d8d2770..8e46e7b 100644
+--- a/net/mac802154/mac_cmd.c
++++ b/net/mac802154/mac_cmd.c
+@@ -33,6 +33,22 @@
+ 
+ #include "mac802154.h"
+ 
++static int mac802154_mlme_assoc_req(struct net_device *dev,
++			struct ieee802154_addr *addr,
++			u8 channel, u8 page, u8 cap)
++{
++	/* TBD */
++	return 0;
++}
++
++static int mac802154_mlme_assoc_resp(struct net_device *dev,
++			struct ieee802154_addr *addr,
++			u16 short_addr, u8 status)
++{
++	/* TBD */
++	return 0;
++}
++
+ static int mac802154_mlme_start_req(struct net_device *dev,
+ 				    struct ieee802154_addr *addr,
+ 				    u8 channel, u8 page,
+@@ -70,7 +86,11 @@ struct ieee802154_reduced_mlme_ops mac802154_mlme_reduced = {
+ 
+ struct ieee802154_mlme_ops mac802154_mlme_wpan = {
+ 	.get_phy = mac802154_get_phy,
+-	.start_req = mac802154_mlme_start_req,
+ 	.get_pan_id = mac802154_dev_get_pan_id,
+ 	.get_short_addr = mac802154_dev_get_short_addr,
++	.get_dsn = mac802154_dev_get_dsn,
++	.get_bsn = mac802154_dev_get_bsn,
++	.start_req = mac802154_mlme_start_req,
++	.assoc_req = mac802154_mlme_assoc_req,
++	.assoc_resp = mac802154_mlme_assoc_resp
+ };
+diff --git a/net/mac802154/mib.c b/net/mac802154/mib.c
+index 2339f8d..70ab6ca 100644
+--- a/net/mac802154/mib.c
++++ b/net/mac802154/mib.c
+@@ -149,6 +149,25 @@ void mac802154_dev_set_pan_id(struct net_device *dev, u16 val)
+ 	}
+ }
+ 
++u8 mac802154_dev_get_dsn(const struct net_device *dev)
++{
++	struct mac802154_sub_if_data *priv = netdev_priv(dev);
++
++	BUG_ON(dev->type != ARPHRD_IEEE802154);
++
++	return priv->dsn++;
++}
++
++u8 mac802154_dev_get_bsn(const struct net_device *dev)
++{
++	struct mac802154_sub_if_data *priv = netdev_priv(dev);
++
++	BUG_ON(dev->type != ARPHRD_IEEE802154);
++
++	return priv->bsn++;
++}
++
++
+ static void phy_chan_notify(struct work_struct *work)
+ {
+ 	struct phy_chan_notify_work *nw = container_of(work,
diff --git a/patches/linux-3.7/0136-serial-initial-import-of-the-IEEE-802.15.4-serial-dr.patch b/patches/linux-3.7/0136-serial-initial-import-of-the-IEEE-802.15.4-serial-dr.patch
new file mode 100644
index 0000000..3b798e2
--- /dev/null
+++ b/patches/linux-3.7/0136-serial-initial-import-of-the-IEEE-802.15.4-serial-dr.patch
@@ -0,0 +1,1323 @@
+From: Tony Cheneau <tony.cheneau@amnesiak.org>
+Date: Tue, 11 Sep 2012 23:42:51 -0400
+Subject: [PATCH] serial: initial import of the IEEE 802.15.4 serial driver
+
+The initial code has been imported from the Linux ZigBee project. It
+supports RedBee Econotag device type.
+
+Patches from Mariano Alvira has been applied against the drivers.
+
+Initialisation of the driver now send CLOSE command before sending OPEN
+command. This effectively re-initiate the devices (empty buffers).
+
+Signed-off-by: Tony Cheneau <tony.cheneau@amnesiak.org>
+---
+ drivers/net/ieee802154/Kconfig  |    4 +
+ drivers/net/ieee802154/Makefile |    1 +
+ drivers/net/ieee802154/serial.c | 1228 +++++++++++++++++++++++++++++++++++++++
+ include/linux/nl802154.h        |    3 +-
+ include/uapi/linux/tty.h        |    1 +
+ net/ieee802154/6lowpan.c        |    2 +
+ 6 files changed, 1238 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/net/ieee802154/serial.c
+
+diff --git a/drivers/net/ieee802154/Kconfig b/drivers/net/ieee802154/Kconfig
+index 08ae465..c982fa8 100644
+--- a/drivers/net/ieee802154/Kconfig
++++ b/drivers/net/ieee802154/Kconfig
+@@ -45,3 +45,7 @@ config IEEE802154_MRF24J40
+ 
+          This driver can also be built as a module. To do so, say M here.
+          the module will be called 'mrf24j40'.
++
++config IEEE802154_SERIAL
++	depends on IEEE802154_DRIVERS && MAC802154
++	tristate "Simple LR-WPAN UART driver"
+diff --git a/drivers/net/ieee802154/Makefile b/drivers/net/ieee802154/Makefile
+index abb0c08..5c7d9cb 100644
+--- a/drivers/net/ieee802154/Makefile
++++ b/drivers/net/ieee802154/Makefile
+@@ -2,3 +2,4 @@ obj-$(CONFIG_IEEE802154_FAKEHARD) += fakehard.o
+ obj-$(CONFIG_IEEE802154_FAKELB) += fakelb.o
+ obj-$(CONFIG_IEEE802154_AT86RF230) += at86rf230.o
+ obj-$(CONFIG_IEEE802154_MRF24J40) += mrf24j40.o
++obj-$(CONFIG_IEEE802154_SERIAL) += serial.o
+diff --git a/drivers/net/ieee802154/serial.c b/drivers/net/ieee802154/serial.c
+new file mode 100644
+index 0000000..950893a
+--- /dev/null
++++ b/drivers/net/ieee802154/serial.c
+@@ -0,0 +1,1228 @@
++/*
++ * ZigBee TTY line discipline.
++ *
++ * Provides interface between ZigBee stack and IEEE 802.15.4 compatible
++ * firmware over serial line. Communication protocol is described below.
++ *
++ * Copyright (C) 2007, 2008, 2009 Siemens AG
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2
++ * as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Written by:
++ * Maxim Gorbachyov <maxim.gorbachev@siemens.com>
++ * Maxim Osipov <maxim.osipov@siemens.com>
++ * Sergey Lapin <slapin@ossfans.org>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/completion.h>
++#include <linux/tty.h>
++#include <linux/skbuff.h>
++#include <linux/sched.h>
++#include <net/mac802154.h>
++#include <net/wpan-phy.h>
++
++
++/* NOTE: be sure to use here the same values as in the firmware */
++#define START_BYTE1	'z'
++#define START_BYTE2	'b'
++#define MAX_DATA_SIZE	127
++
++#define TIMEOUT 1000
++
++#define IDLE_MODE	0x00
++#define RX_MODE		0x02
++#define TX_MODE		0x03
++#define FORCE_TRX_OFF	0xF0
++
++#define STATUS_SUCCESS	0
++#define STATUS_RX_ON	1
++#define STATUS_TX_ON	2
++#define STATUS_TRX_OFF	3
++#define STATUS_IDLE	4
++#define STATUS_BUSY	5
++#define STATUS_BUSY_RX	6
++#define STATUS_BUSY_TX	7
++#define STATUS_ERR	8
++
++#define STATUS_WAIT	((u8) -1) /* waiting for the answer */
++
++/* We re-use PPP ioctl for our purposes */
++#define	PPPIOCGUNIT	_IOR('t', 86, int)	/* get ppp unit number */
++
++/*
++ * The following messages are used to control ZigBee firmware.
++ * All communication has request/response format,
++ * except of asynchronous incoming data stream (DATA_RECV_* messages).
++ */
++enum {
++	NO_ID			= 0, /* means no pending id */
++
++	/* Driver to Firmware */
++	CMD_OPEN		= 0x01, /* u8 id */
++	CMD_CLOSE		= 0x02, /* u8 id */
++	CMD_SET_CHANNEL		= 0x04, /* u8 id, u8 channel */
++	CMD_ED			= 0x05, /* u8 id */
++	CMD_SET_STATE		= 0x07, /* u8 id, u8 flag */
++	DATA_XMIT_BLOCK		= 0x09, /* u8 id, u8 len, u8 data[len] */
++	RESP_RECV_BLOCK		= 0x0b, /* u8 id, u8 status */
++	CMD_ADDRESS		= 0x0d, /* u8 id */
++	CMD_SET_PAN_ID = 0x0f, /* u8 id, u8 u8 panid (MSB first) */
++	CMD_SET_SHORT_ADDRESS = 0x10, /* u8 id, u8 u8 address  (MSB first)*/
++	CMD_SET_LONG_ADDRESS = 0x11, /* u8 id, u8 u8 u8 u8 u8 u8 u8 u8 address (MSB first) */
++
++	/* Firmware to Driver */
++	RESP_OPEN		= 0x81, /* u8 id, u8 status */
++	RESP_CLOSE		= 0x82, /* u8 id, u8 status */
++	RESP_SET_CHANNEL	= 0x84, /* u8 id, u8 status */
++	RESP_ED			= 0x85, /* u8 id, u8 status, u8 level */
++	RESP_SET_STATE		= 0x87, /* u8 id, u8 status */
++	RESP_XMIT_BLOCK		= 0x89, /* u8 id, u8 status */
++	DATA_RECV_BLOCK		= 0x8b, /* u8 id, u8 lq, u8 len, u8 data[len] */
++	RESP_ADDRESS		= 0x8d, /* u8 id, u8 status, u8 u8 u8 u8 u8 u8 u8 u8 address */
++	RESP_SET_PAN_ID     = 0x8f, /* u8 id, u8 status */
++	RESP_SET_SHORT_ADDRESS = 0x90, /* u8 id, u8 status */
++	RESP_SET_LONG_ADDRESS = 0x91, /* u8 id, u8 status */
++};
++
++enum {
++	STATE_WAIT_START1,
++	STATE_WAIT_START2,
++	STATE_WAIT_COMMAND,
++	STATE_WAIT_PARAM1,
++	STATE_WAIT_PARAM2,
++	STATE_WAIT_DATA
++};
++
++struct zb_device {
++	/* Relative devices */
++	struct tty_struct	*tty;
++	struct ieee802154_dev	*dev;
++
++	/* locks the ldisc for the command */
++	struct mutex		mutex;
++
++	/* command completition */
++	wait_queue_head_t	wq;
++	u8			status;
++	u8			ed;
++
++	/* Internal state */
++	struct completion	open_done;
++	struct completion	close_done;
++	unsigned char		opened;
++	u8			pending_id;
++	unsigned int		pending_size;
++	u8			*pending_data;
++	/* FIXME: WE NEED LOCKING!!! */
++
++	/* Command (rx) processing */
++	int			state;
++	unsigned char		id;
++	unsigned char		param1;
++	unsigned char		param2;
++	unsigned char		index;
++	unsigned char		data[MAX_DATA_SIZE];
++};
++
++/*****************************************************************************
++ * ZigBee serial device protocol handling
++ *****************************************************************************/
++static int _open_dev(struct zb_device *zbdev);
++static int _close_dev(struct zb_device *zbdev);
++
++static void
++cleanup(struct zb_device *zbdev)
++{
++    zbdev->state = STATE_WAIT_START1;
++    zbdev->id = 0;
++    zbdev->param1 = 0;
++    zbdev->param2 = 0;
++    zbdev->index = 0;
++    zbdev->pending_id = 0;
++    zbdev->pending_size = 0;
++
++    if (zbdev->pending_data)
++    {
++        kfree(zbdev->pending_data);
++        zbdev->pending_data = NULL;
++    }
++}
++
++static int
++_send_pending_data(struct zb_device *zbdev)
++{
++	struct tty_struct *tty;
++
++	BUG_ON(!zbdev);
++	tty = zbdev->tty;
++	if (!tty)
++		return -ENODEV;
++
++	zbdev->status = STATUS_WAIT;
++
++	/* Debug info */
++	printk(KERN_INFO "%s, %d bytes\n", __func__,
++			zbdev->pending_size);
++#ifdef DEBUG
++	print_hex_dump_bytes("send_pending_data ", DUMP_PREFIX_NONE,
++			zbdev->pending_data, zbdev->pending_size);
++#endif
++
++	if (tty->driver->ops->write(tty, zbdev->pending_data,
++				zbdev->pending_size) != zbdev->pending_size) {
++		printk(KERN_ERR "%s: device write failed\n", __func__);
++		return -1;
++	}
++
++	return 0;
++}
++
++static int
++send_cmd(struct zb_device *zbdev, u8 id)
++{
++	u8 len = 0;
++	/* 4 because of 2 start bytes, id and optional extra */
++	u8 buf[4];
++
++	/* Check arguments */
++	BUG_ON(!zbdev);
++
++	if (!zbdev->opened) {
++		if (!_close_dev(zbdev) || !_open_dev(zbdev))
++			return -EAGAIN;
++	}
++
++	pr_debug("%s(): id = %u\n", __func__, id);
++	if (zbdev->pending_size) {
++		printk(KERN_ERR "%s(): cmd is already pending, id = %u\n",
++			__func__, zbdev->pending_id);
++		//BUG();
++        cleanup(zbdev);
++        return -EAGAIN;
++	}
++
++	/* Prepare a message */
++	buf[len++] = START_BYTE1;
++	buf[len++] = START_BYTE2;
++	buf[len++] = id;
++
++	zbdev->pending_id = id;
++	zbdev->pending_size = len;
++	zbdev->pending_data = kzalloc(zbdev->pending_size, GFP_ATOMIC);
++	if (!zbdev->pending_data) {
++		printk(KERN_ERR "%s(): unable to allocate memory\n", __func__);
++		zbdev->pending_id = 0;
++		zbdev->pending_size = 0;
++		return -ENOMEM;
++	}
++	memcpy(zbdev->pending_data, buf, len);
++
++	return _send_pending_data(zbdev);
++}
++
++static int
++send_cmd2(struct zb_device *zbdev, u8 id, u8 extra)
++{
++	u8 len = 0;
++	/* 4 because of 2 start bytes, id and optional extra */
++	u8 buf[4];
++
++	/* Check arguments */
++	BUG_ON(!zbdev);
++
++	if (!zbdev->opened) {
++		if (!_close_dev(zbdev) || !_open_dev(zbdev))
++			return -EAGAIN;
++	}
++
++	pr_debug("%s(): id = %u\n", __func__, id);
++	if (zbdev->pending_size) {
++		printk(KERN_ERR "%s(): cmd is already pending, id = %u\n",
++			__func__, zbdev->pending_id);
++//		BUG();
++        cleanup(zbdev);
++        return -EAGAIN;
++	}
++
++	/* Prepare a message */
++	buf[len++] = START_BYTE1;
++	buf[len++] = START_BYTE2;
++	buf[len++] = id;
++	buf[len++] = extra;
++
++	zbdev->pending_id = id;
++	zbdev->pending_size = len;
++	zbdev->pending_data = kzalloc(zbdev->pending_size, GFP_ATOMIC);
++	if (!zbdev->pending_data) {
++		printk(KERN_ERR "%s(): unable to allocate memory\n", __func__);
++		zbdev->pending_id = 0;
++		zbdev->pending_size = 0;
++		return -ENOMEM;
++	}
++	memcpy(zbdev->pending_data, buf, len);
++
++	return _send_pending_data(zbdev);
++}
++
++static int
++send_cmd3(struct zb_device *zbdev, u8 id, u8 extra1, u8 extra2)
++{
++	u8 len = 0;
++	/* 5 because of 2 start bytes, id, extra1, extra2 */
++	u8 buf[5];
++
++	/* Check arguments */
++	BUG_ON(!zbdev);
++
++	if (!zbdev->opened) {
++		if (!_close_dev(zbdev) || !_open_dev(zbdev))
++			return -EAGAIN;
++	}
++
++	pr_debug("%s(): id = %u\n", __func__, id);
++	if (zbdev->pending_size) {
++		printk(KERN_ERR "%s(): cmd is already pending, id = %u\n",
++			__func__, zbdev->pending_id);
++//		BUG();
++        cleanup(zbdev);
++        return -EAGAIN;
++	}
++
++	/* Prepare a message */
++	buf[len++] = START_BYTE1;
++	buf[len++] = START_BYTE2;
++	buf[len++] = id;
++	buf[len++] = extra1;
++	buf[len++] = extra2;
++
++	zbdev->pending_id = id;
++	zbdev->pending_size = len;
++	zbdev->pending_data = kzalloc(zbdev->pending_size, GFP_ATOMIC);
++	if (!zbdev->pending_data) {
++		printk(KERN_ERR "%s(): unable to allocate memory\n", __func__);
++		zbdev->pending_id = 0;
++		zbdev->pending_size = 0;
++		return -ENOMEM;
++	}
++	memcpy(zbdev->pending_data, buf, len);
++
++	return _send_pending_data(zbdev);
++}
++
++static int
++send_block(struct zb_device *zbdev, u8 len, u8 *data)
++{
++	u8 i = 0, buf[4];	/* 4 because of 2 start bytes, id and len */
++
++	/* Check arguments */
++	BUG_ON(!zbdev);
++
++	if (!zbdev->opened) {
++		if (!_close_dev(zbdev) || !_open_dev(zbdev))
++			return -EAGAIN;
++	}
++
++	pr_debug("%s(): id = %u\n", __func__, DATA_XMIT_BLOCK);
++	if (zbdev->pending_size) {
++		printk(KERN_ERR "%s(): cmd is already pending, id = %u\n",
++			__func__, zbdev->pending_id);
++		//BUG();
++        cleanup(zbdev);
++        return -EAGAIN;
++	}
++
++	/* Prepare a message */
++	buf[i++] = START_BYTE1;
++	buf[i++] = START_BYTE2;
++	buf[i++] = DATA_XMIT_BLOCK;
++	buf[i++] = len;
++
++	zbdev->pending_id = DATA_XMIT_BLOCK;
++	zbdev->pending_size = i + len;
++	zbdev->pending_data = kzalloc(zbdev->pending_size, GFP_ATOMIC);
++	if (!zbdev->pending_data) {
++		printk(KERN_ERR "%s(): unable to allocate memory\n", __func__);
++		zbdev->pending_id = 0;
++		zbdev->pending_size = 0;
++		return -ENOMEM;
++	}
++	memcpy(zbdev->pending_data, buf, i);
++	memcpy(zbdev->pending_data + i, data, len);
++
++	return _send_pending_data(zbdev);
++}
++
++
++static int
++is_command(unsigned char c)
++{
++	switch (c) {
++	/* ids we can get here: */
++	case RESP_OPEN:
++	case RESP_CLOSE:
++	case RESP_SET_CHANNEL:
++	case RESP_ED:
++	case RESP_XMIT_BLOCK:
++	case DATA_RECV_BLOCK:
++	case RESP_ADDRESS:
++	case RESP_SET_PAN_ID:
++	case RESP_SET_SHORT_ADDRESS:
++	case RESP_SET_LONG_ADDRESS:
++		return 1;
++	}
++	return 0;
++}
++
++static int
++_match_pending_id(struct zb_device *zbdev)
++{
++	return ((CMD_OPEN == zbdev->pending_id &&
++			RESP_OPEN == zbdev->id) ||
++		(CMD_CLOSE == zbdev->pending_id &&
++			RESP_CLOSE == zbdev->id) ||
++		(CMD_SET_CHANNEL == zbdev->pending_id &&
++			RESP_SET_CHANNEL == zbdev->id) ||
++		(CMD_ED == zbdev->pending_id &&
++			RESP_ED == zbdev->id) ||
++		(DATA_XMIT_BLOCK == zbdev->pending_id &&
++			RESP_XMIT_BLOCK == zbdev->id) ||
++		(DATA_RECV_BLOCK == zbdev->id) ||
++		(CMD_ADDRESS == zbdev->pending_id &&
++			RESP_ADDRESS == zbdev->id)) ||
++		(CMD_SET_PAN_ID == zbdev->pending_id &&
++			RESP_SET_PAN_ID ==  zbdev->id) ||
++		(CMD_SET_SHORT_ADDRESS == zbdev->pending_id &&
++			RESP_SET_SHORT_ADDRESS == zbdev->id) ||
++		(CMD_SET_LONG_ADDRESS == zbdev->pending_id &&
++			RESP_SET_LONG_ADDRESS  == zbdev->id);
++}
++
++static void serial_net_rx(struct zb_device *zbdev)
++{
++	/* zbdev->param1 is LQI
++	 * zbdev->param2 is length of data
++	 * zbdev->data is data itself
++	 */
++	struct sk_buff *skb;
++	skb = alloc_skb(zbdev->param2, GFP_ATOMIC);
++	skb_put(skb, zbdev->param2);
++	skb_copy_to_linear_data(skb, zbdev->data, zbdev->param2);
++	ieee802154_rx_irqsafe(zbdev->dev, skb, zbdev->param1);
++}
++
++static void
++process_command(struct zb_device *zbdev)
++{
++	/* Command processing */
++	if (!_match_pending_id(zbdev))
++    {
++        cleanup(zbdev);
++		return;
++    }
++
++	if (RESP_OPEN == zbdev->id && STATUS_SUCCESS == zbdev->param1) {
++		zbdev->opened = 1;
++		pr_debug("Opened device\n");
++		complete(&zbdev->open_done);
++		/* Input is not processed during output, so
++		 * using completion is not possible during output.
++		 * so we need to handle open as any other command
++		 * and hope for best
++		 */
++		return;
++	}
++
++	if (RESP_CLOSE == zbdev->id && STATUS_SUCCESS == zbdev->param1) {
++		zbdev->opened = 0;
++		pr_debug("Closed device\n");
++		complete(&zbdev->close_done);
++		/* Input is not processed during output, so
++		 * using completion is not possible during output.
++		 * so we need to handle open as any other command
++		 * and hope for best
++		 */
++		return;
++	}
++
++	if (!zbdev->opened)
++    {
++        cleanup(zbdev);
++		return;
++    }
++
++
++	zbdev->pending_id = 0;
++	kfree(zbdev->pending_data);
++	zbdev->pending_data = NULL;
++	zbdev->pending_size = 0;
++
++	if (zbdev->id != DATA_RECV_BLOCK) {
++		/* XXX: w/around for old FW, REMOVE */
++		if (zbdev->param1 == STATUS_IDLE)
++			zbdev->status = STATUS_SUCCESS;
++		else
++			zbdev->status = zbdev->param1;
++	}
++
++    switch (zbdev->id) {
++	case RESP_ED:
++		zbdev->ed = zbdev->param2;
++		break;
++	case DATA_RECV_BLOCK:
++		pr_debug("Received block, lqi %02x, len %02x\n",
++				zbdev->param1, zbdev->param2);
++		/* zbdev->param1 is LQ, zbdev->param2 is length */
++		serial_net_rx(zbdev);
++		break;
++	case RESP_ADDRESS:
++		pr_debug("Received address, %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
++			zbdev->data[0], zbdev->data[1], zbdev->data[2], zbdev->data[3],
++			zbdev->data[4], zbdev->data[5], zbdev->data[6], zbdev->data[7]);
++		break;
++	}
++
++    cleanup(zbdev);
++
++    wake_up(&zbdev->wq);
++}
++
++static void
++process_char(struct zb_device *zbdev, unsigned char c)
++{
++	/* Data processing */
++	switch (zbdev->state) {
++	case STATE_WAIT_START1:
++		if (START_BYTE1 == c)
++			zbdev->state = STATE_WAIT_START2;
++        else
++            cleanup(zbdev);
++		break;
++
++	case STATE_WAIT_START2:
++		if (START_BYTE2 == c)
++			zbdev->state = STATE_WAIT_COMMAND;
++		else
++			cleanup(zbdev);
++		break;
++
++	case STATE_WAIT_COMMAND:
++		if (is_command(c)) {
++			zbdev->id = c;
++			zbdev->state = STATE_WAIT_PARAM1;
++		} else {
++			cleanup(zbdev);
++			printk(KERN_ERR "%s, unexpected command id: %x\n",
++					__func__, c);
++		}
++		break;
++
++	case STATE_WAIT_PARAM1:
++		zbdev->param1 = c;
++		if ((RESP_ED == zbdev->id) || (DATA_RECV_BLOCK == zbdev->id))
++			zbdev->state = STATE_WAIT_PARAM2;
++		else if (RESP_ADDRESS == zbdev->id) {
++			zbdev->param2 = 8;
++			zbdev->state = STATE_WAIT_DATA;
++		} else
++			process_command(zbdev);
++		break;
++
++	case STATE_WAIT_PARAM2:
++		zbdev->param2 = c;
++		if (RESP_ED == zbdev->id)
++			process_command(zbdev);
++		else if (DATA_RECV_BLOCK == zbdev->id)
++			zbdev->state = STATE_WAIT_DATA;
++		else
++			cleanup(zbdev);
++		break;
++
++	case STATE_WAIT_DATA:
++            if ((zbdev->index < sizeof(zbdev->data)) &&
++               (zbdev->param2 <= sizeof(zbdev->data))) {
++
++			zbdev->data[zbdev->index] = c;
++			zbdev->index++;
++			/*
++			 * Pending data is received,
++			 * param2 is length for DATA_RECV_BLOCK
++			 */
++			if (zbdev->index == zbdev->param2) {
++                zbdev->state = STATE_WAIT_START1;
++				process_command(zbdev);
++			}
++		} else {
++			printk(KERN_ERR "%s(): data size is greater "
++				"than buffer available\n", __func__);
++			cleanup(zbdev);
++		}
++		break;
++
++	default:
++		cleanup(zbdev);
++	}
++}
++
++/*****************************************************************************
++ * Device operations for IEEE 802.15.4 PHY side interface ZigBee stack
++ *****************************************************************************/
++
++static int _open_dev(struct zb_device *zbdev)
++{
++	int retries;
++	u8 len = 0;
++	/* 4 because of 2 start bytes, id and optional extra */
++	u8 buf[4];
++
++	/* Check arguments */
++	BUG_ON(!zbdev);
++	if (zbdev->opened)
++		return 1;
++
++	pr_debug("%s()\n", __func__);
++	if (zbdev->pending_size) {
++		printk(KERN_ERR "%s(): cmd is already pending, id = %u\n",
++			__func__, zbdev->pending_id);
++            //BUG();
++            cleanup(zbdev);
++            return -EAGAIN;
++	}
++
++	/* Prepare a message */
++	buf[len++] = START_BYTE1;
++	buf[len++] = START_BYTE2;
++	buf[len++] = CMD_OPEN;
++
++
++    zbdev->pending_id = CMD_OPEN;
++    zbdev->pending_size = len;
++    zbdev->pending_data = kzalloc(zbdev->pending_size, GFP_KERNEL);
++    if (!zbdev->pending_data) {
++        printk(KERN_ERR "%s(): unable to allocate memory\n", __func__);
++        zbdev->pending_id = 0;
++        zbdev->pending_size = 0;
++        return -ENOMEM;
++    }
++    memcpy(zbdev->pending_data, buf, len);
++
++	retries = 5;
++	while (!zbdev->opened && retries) {
++
++		if (_send_pending_data(zbdev) != 0)
++			return 0;
++
++		/* 3 second before retransmission */
++		wait_for_completion_interruptible_timeout(
++				&zbdev->open_done, msecs_to_jiffies(TIMEOUT));
++		--retries;
++	}
++
++    cleanup(zbdev);
++
++	if (zbdev->opened) {
++		printk(KERN_INFO "Opened connection to device\n");
++		return 1;
++	}
++
++	return 0;
++}
++
++static int _close_dev(struct zb_device *zbdev)
++{
++	int retries;
++	u8 len = 0;
++	/* 4 because of 2 start bytes, id and optional extra */
++	u8 buf[4];
++
++	/* Check arguments */
++	BUG_ON(!zbdev);
++
++	pr_debug("%s()\n", __func__);
++	if (zbdev->pending_size) {
++		printk(KERN_ERR "%s(): cmd is already pending, id = %u\n",
++			__func__, zbdev->pending_id);
++		//BUG();
++        cleanup(zbdev);
++        return -EAGAIN;
++	}
++
++	/* Prepare a message */
++	buf[len++] = START_BYTE1;
++	buf[len++] = START_BYTE2;
++	buf[len++] = CMD_CLOSE;
++
++    zbdev->pending_id = CMD_CLOSE;
++    zbdev->pending_size = len;
++    zbdev->pending_data = kzalloc(zbdev->pending_size, GFP_KERNEL);
++    if (!zbdev->pending_data) {
++        printk(KERN_ERR "%s(): unable to allocate memory\n", __func__);
++        zbdev->pending_id = 0;
++        zbdev->pending_size = 0;
++        return -ENOMEM;
++    }
++    memcpy(zbdev->pending_data, buf, len);
++
++	retries = 5;
++    do{
++
++        if (_send_pending_data(zbdev) !=0)
++            return 0;
++
++		/* 1 second before retransmission */
++		wait_for_completion_interruptible_timeout(
++				&zbdev->close_done, msecs_to_jiffies(TIMEOUT));
++		--retries;
++	} while (zbdev->opened && retries) ;
++
++    cleanup(zbdev);
++
++	if (!zbdev->opened)
++    {
++		printk(KERN_INFO "Closed connection to device\n");
++        return 1;
++    }
++
++    return 0;
++}
++
++/* Valid channels: 1-16 */
++static int
++ieee802154_serial_set_channel(struct ieee802154_dev *dev, int page, int channel)
++{
++	struct zb_device *zbdev;
++	int ret = 0;
++
++	pr_debug("%s %d\n", __func__, channel);
++
++	zbdev = dev->priv;
++	if (NULL == zbdev) {
++		printk(KERN_ERR "%s: wrong phy\n", __func__);
++		return -EINVAL;
++	}
++
++	BUG_ON(page != 0);
++	/* Our channels are actually from 11 to 26
++	 * We have IEEE802.15.4 channel no from 0 to 26.
++	 * channels 0-10 are not valid for us */
++	BUG_ON(channel < 11 || channel > 26);
++	/* ...  but our crappy firmware numbers channels from 1 to 16
++	 * which is a mystery. We suould enforce that using PIB API
++	 * but additional checking here won't kill, and gcc will
++	 * optimize this stuff anyway. */
++	BUG_ON((channel - 10) < 1 && (channel - 10) > 16);
++	if (mutex_lock_interruptible(&zbdev->mutex))
++		return -EINTR;
++	ret = send_cmd2(zbdev, CMD_SET_CHANNEL, channel - 10);
++	if (ret)
++		goto out;
++
++	if (wait_event_interruptible_timeout(zbdev->wq,
++				zbdev->status != STATUS_WAIT,
++				msecs_to_jiffies(TIMEOUT)) > 0) {
++		if (zbdev->status != STATUS_SUCCESS)
++			ret = -EBUSY;
++	} else
++		ret = -EINTR;
++
++	if (!ret)
++		zbdev->dev->phy->current_channel = channel;
++out:
++	mutex_unlock(&zbdev->mutex);
++	pr_debug("%s end\n", __func__);
++	return ret;
++}
++
++static int
++ieee802154_serial_ed(struct ieee802154_dev *dev, u8 *level)
++{
++	struct zb_device *zbdev;
++	int ret = 0;
++
++	pr_debug("%s\n", __func__);
++
++	zbdev = dev->priv;
++	if (NULL == zbdev) {
++		printk(KERN_ERR "%s: wrong phy\n", __func__);
++		return -EINVAL;
++	}
++
++	if (mutex_lock_interruptible(&zbdev->mutex))
++		return -EINTR;
++
++	ret = send_cmd(zbdev, CMD_ED);
++	if (ret)
++		goto out;
++
++	if (wait_event_interruptible_timeout(zbdev->wq,
++				zbdev->status != STATUS_WAIT,
++				msecs_to_jiffies(TIMEOUT)) > 0) {
++		*level = zbdev->ed;
++		if (zbdev->status != STATUS_SUCCESS)
++			ret = -EBUSY;
++	} else
++		ret = -ETIMEDOUT;
++out:
++
++	mutex_unlock(&zbdev->mutex);
++	pr_debug("%s end\n", __func__);
++	return ret;
++}
++
++static int
++ieee802154_serial_set_laddr(struct zb_device *zbdev, u8 addr[IEEE802154_ADDR_LEN])
++{
++	int ret = 0;
++	uint8_t len = 0;
++	/* 11 because of 2 start bytes, id and 8 bytes addr */
++	uint8_t buf[11];
++
++	pr_debug("%s\n", __func__);
++
++	if (mutex_lock_interruptible(&zbdev->mutex))
++		return -EINTR;
++
++
++	if (zbdev->pending_size) {
++		printk(KERN_ERR "%s(): cmd is already pending, id = %u\n",
++			__func__, zbdev->pending_id);
++        cleanup(zbdev);
++        return -EAGAIN;
++	}
++
++	/* Prepare a message */
++	buf[len++] = START_BYTE1;
++	buf[len++] = START_BYTE2;
++	buf[len++] = CMD_SET_LONG_ADDRESS;
++
++	memcpy(&buf[len], addr, IEEE802154_ADDR_LEN);
++
++	zbdev->pending_id = CMD_SET_LONG_ADDRESS;
++	zbdev->pending_size = len + IEEE802154_ADDR_LEN;
++	zbdev->pending_data = kzalloc(zbdev->pending_size, GFP_ATOMIC);
++	if (!zbdev->pending_data) {
++		printk(KERN_ERR "%s(): unable to allocate memory\n", __func__);
++		zbdev->pending_id = 0;
++		zbdev->pending_size = 0;
++		return -ENOMEM;
++	}
++	memcpy(zbdev->pending_data, buf, len);
++
++	ret =  _send_pending_data(zbdev);
++
++	if (ret)
++		goto out;
++
++	if (wait_event_interruptible_timeout(zbdev->wq,
++				zbdev->status != STATUS_WAIT,
++				msecs_to_jiffies(TIMEOUT)) > 0) {
++		if (zbdev->status != STATUS_SUCCESS)
++			ret = -EBUSY;
++	} else
++		ret = -ETIMEDOUT;
++
++out:
++	mutex_unlock(&zbdev->mutex);
++	pr_debug("%s end\n", __func__);
++	return ret;
++}
++
++static int
++ieee802154_serial_get_laddr(struct ieee802154_dev *dev, u8 addr[IEEE802154_ADDR_LEN])
++{
++	struct zb_device *zbdev;
++	int ret = 0;
++
++	pr_debug("%s\n", __func__);
++
++	zbdev = dev->priv;
++	if (NULL == zbdev) {
++		printk(KERN_ERR "%s: wrong phy\n", __func__);
++		return -EINVAL;
++	}
++
++	if (mutex_lock_interruptible(&zbdev->mutex))
++		return -EINTR;
++
++	ret = send_cmd(zbdev, CMD_ADDRESS);
++	if (ret)
++		goto out;
++
++	if (wait_event_interruptible_timeout(zbdev->wq,
++				zbdev->status != STATUS_WAIT,
++				msecs_to_jiffies(TIMEOUT)) > 0) {
++		memcpy(addr, zbdev->data, IEEE802154_ADDR_LEN);
++		if (zbdev->status != STATUS_SUCCESS)
++			ret = -EBUSY;
++	} else
++		ret = -ETIMEDOUT;
++out:
++
++	mutex_unlock(&zbdev->mutex);
++	pr_debug("%s end\n", __func__);
++	return ret;
++}
++
++static int
++ieee802154_serial_set_hw_addr_filt(struct ieee802154_dev *dev,
++					  struct ieee802154_hw_addr_filt *filt,
++					    unsigned long changed)
++{
++	struct zb_device *zbdev;
++	int ret = 0;
++
++	pr_debug("%s\n", __func__);
++
++	zbdev = dev->priv;
++
++	if (NULL == zbdev) {
++		printk(KERN_ERR "%s: wrong phy\n", __func__);
++		return -EINVAL;
++	}
++
++	if (mutex_lock_interruptible(&zbdev->mutex))
++		return -EINTR;
++
++	switch (changed)
++	{
++		case IEEE802515_AFILT_SADDR_CHANGED:
++			send_cmd3(zbdev, CMD_SET_SHORT_ADDRESS, filt->short_addr & 0xff, filt->short_addr >> 8);
++			break;
++		case IEEE802515_AFILT_PANID_CHANGED:
++			send_cmd3(zbdev, CMD_SET_PAN_ID, filt->pan_id & 0xff, filt->pan_id >> 8);
++			break;
++		case IEEE802515_AFILT_IEEEADDR_CHANGED:
++			ret = ieee802154_serial_set_laddr(zbdev, filt->ieee_addr);
++			break;
++		default:
++			printk(KERN_ERR "%s: unable to apply change, not supported\n", __func__);
++			break;
++	}
++
++	mutex_unlock(&zbdev->mutex);
++	pr_debug("%s end\n", __func__);
++	return ret;
++}
++
++static int
++ieee802154_serial_start(struct ieee802154_dev *dev)
++{
++	struct zb_device *zbdev;
++	int ret = 0;
++
++	pr_debug("%s\n", __func__);
++
++	zbdev = dev->priv;
++	if (NULL == zbdev) {
++		printk(KERN_ERR "%s: wrong phy\n", __func__);
++		return -EINVAL;
++	}
++
++	pr_debug("%s end (retval: %d)\n", __func__, ret);
++	return ret;
++}
++
++static void
++ieee802154_serial_stop(struct ieee802154_dev *dev)
++{
++	struct zb_device *zbdev;
++	pr_debug("%s\n", __func__);
++
++	zbdev = dev->priv;
++	if (NULL == zbdev) {
++		printk(KERN_ERR "%s: wrong phy\n", __func__);
++		return;
++	}
++
++	pr_debug("%s end\n", __func__);
++}
++
++static int
++ieee802154_serial_xmit(struct ieee802154_dev *dev, struct sk_buff *skb)
++{
++	struct zb_device *zbdev;
++	int ret;
++
++	pr_debug("%s\n", __func__);
++
++	zbdev = dev->priv;
++	if (NULL == zbdev) {
++		printk(KERN_ERR "%s: wrong phy\n", __func__);
++		return -EINVAL;
++	}
++
++	if (mutex_lock_interruptible(&zbdev->mutex))
++		return -EINTR;
++
++	ret = send_block(zbdev, skb->len, skb->data);
++	if (ret)
++		goto out;
++
++	if (wait_event_interruptible_timeout(zbdev->wq,
++				zbdev->status != STATUS_WAIT,
++				msecs_to_jiffies(TIMEOUT)) > 0) {
++		if (zbdev->status != STATUS_SUCCESS) {
++			ret = -EBUSY;
++			goto out;
++		}
++	} else {
++		ret = -ETIMEDOUT;
++		goto out;
++	}
++
++out:
++
++	mutex_unlock(&zbdev->mutex);
++	pr_debug("%s end\n", __func__);
++	return ret;
++}
++
++/*****************************************************************************
++ * Line discipline interface for IEEE 802.15.4 serial device
++ *****************************************************************************/
++
++static struct ieee802154_ops serial_ops = {
++	.owner = THIS_MODULE,
++	.xmit		= ieee802154_serial_xmit,
++	.ed		= ieee802154_serial_ed,
++	.set_channel	= ieee802154_serial_set_channel,
++	.start		= ieee802154_serial_start,
++	.stop		= ieee802154_serial_stop,
++//	.set_hw_addr_filt = ieee802154_serial_set_hw_addr_filt,
++	.ieee_addr	= ieee802154_serial_get_laddr,
++};
++
++/*
++ * Called when a tty is put into ZB line discipline. Called in process context.
++ * Returns 0 on success.
++ */
++static int
++ieee802154_tty_open(struct tty_struct *tty)
++{
++	struct zb_device *zbdev = tty->disc_data;
++	struct ieee802154_dev *dev;
++	int err;
++
++	pr_debug("Openning ldisc\n");
++	if (!capable(CAP_NET_ADMIN))
++		return -EPERM;
++
++	if (tty->disc_data)
++		return -EBUSY;
++
++	dev = ieee802154_alloc_device(sizeof(*zbdev), &serial_ops);
++	if (!dev)
++		return -ENOMEM;
++
++	zbdev = dev->priv;
++	zbdev->dev = dev;
++
++	mutex_init(&zbdev->mutex);
++	init_completion(&zbdev->open_done);
++	init_completion(&zbdev->close_done);
++	init_waitqueue_head(&zbdev->wq);
++
++	dev->extra_tx_headroom = 0;
++	/* only 2.4 GHz band */
++	dev->phy->channels_supported[0] = 0x7fff800;
++
++	dev->flags = IEEE802154_HW_OMIT_CKSUM;
++
++	dev->parent = tty->dev;
++
++	zbdev->tty = tty_kref_get(tty);
++
++	cleanup(zbdev);
++
++	tty->disc_data = zbdev;
++	tty->receive_room = MAX_DATA_SIZE;
++    // TC: why was it removed ?
++    // why does it crash one of my computer each times, and the other one is fine
++    // tty->low_latency = 1;
++
++	/* FIXME: why is this needed. Note don't use ldisc_ref here as the
++	   open path is before the ldisc is referencable */
++
++	if (tty->ldisc->ops->flush_buffer)
++		tty->ldisc->ops->flush_buffer(tty);
++	tty_driver_flush_buffer(tty);
++
++	err = ieee802154_register_device(dev);
++	if (err) {
++		printk(KERN_ERR "%s: device register failed\n", __func__);
++		goto out_free;
++	}
++
++	return 0;
++
++
++out_free:
++	tty->disc_data = NULL;
++	tty_kref_put(tty);
++	zbdev->tty = NULL;
++
++	ieee802154_unregister_device(zbdev->dev);
++	ieee802154_free_device(zbdev->dev);
++
++	return err;
++}
++
++/*
++ * Called when the tty is put into another line discipline or it hangs up. We
++ * have to wait for any cpu currently executing in any of the other zb_tty_*
++ * routines to finish before we can call zb_tty_close and free the
++ * zb_serial_dev struct. This routine must be called from process context, not
++ * interrupt or softirq context.
++ */
++static void
++ieee802154_tty_close(struct tty_struct *tty)
++{
++	struct zb_device *zbdev;
++
++	zbdev = tty->disc_data;
++	if (NULL == zbdev) {
++		printk(KERN_WARNING "%s: match is not found\n", __func__);
++		return;
++	}
++
++	tty->disc_data = NULL;
++	tty_kref_put(tty);
++	zbdev->tty = NULL;
++	mutex_destroy(&zbdev->mutex);
++
++	ieee802154_unregister_device(zbdev->dev);
++
++	tty_ldisc_flush(tty);
++	tty_driver_flush_buffer(tty);
++
++	ieee802154_free_device(zbdev->dev);
++}
++
++/*
++ * Called on tty hangup in process context.
++ */
++static int
++ieee802154_tty_hangup(struct tty_struct *tty)
++{
++	ieee802154_tty_close(tty);
++	return 0;
++}
++
++/*
++ * Called in process context only. May be re-entered
++ * by multiple ioctl calling threads.
++ */
++static int
++ieee802154_tty_ioctl(struct tty_struct *tty, struct file *file,
++		unsigned int cmd, unsigned long arg)
++{
++	struct zb_device *zbdev;
++
++	pr_debug("cmd = 0x%x\n", cmd);
++
++	zbdev = tty->disc_data;
++	if (NULL == zbdev) {
++		pr_debug("match is not found\n");
++		return -EINVAL;
++	}
++
++	switch (cmd) {
++	case TCFLSH:
++		return tty_perform_flush(tty, arg);
++	default:
++		/* Try the mode commands */
++		return tty_mode_ioctl(tty, file, cmd, arg);
++	}
++}
++
++
++/*
++ * This can now be called from hard interrupt level as well
++ * as soft interrupt level or mainline.
++ */
++static void
++ieee802154_tty_receive(struct tty_struct *tty, const unsigned char *buf,
++		char *cflags, int count)
++{
++	struct zb_device *zbdev;
++	int i;
++
++	/* Debug info */
++	printk(KERN_INFO "%s, received %d bytes\n", __func__,
++			count);
++#ifdef DEBUG
++	print_hex_dump_bytes("ieee802154_tty_receive ", DUMP_PREFIX_NONE,
++			buf, count);
++#endif
++
++	/* Actual processing */
++	zbdev = tty->disc_data;
++	if (NULL == zbdev) {
++		printk(KERN_ERR "%s(): record for tty is not found\n",
++				__func__);
++		return;
++	}
++	for (i = 0; i < count; ++i)
++		process_char(zbdev, buf[i]);
++#if 0
++	if (tty->driver->flush_chars)
++		tty->driver->flush_chars(tty);
++#endif
++	tty_unthrottle(tty);
++}
++
++/*
++ * Line discipline device structure
++ */
++static struct tty_ldisc_ops ieee802154_ldisc = {
++	.owner  = THIS_MODULE,
++	.magic	= TTY_LDISC_MAGIC,
++	.name	= "ieee802154-ldisc",
++	.open	= ieee802154_tty_open,
++	.close	= ieee802154_tty_close,
++	.hangup	= ieee802154_tty_hangup,
++	.receive_buf = ieee802154_tty_receive,
++	.ioctl	= ieee802154_tty_ioctl,
++};
++
++/*****************************************************************************
++ * Module service routinues
++ *****************************************************************************/
++
++static int __init ieee802154_serial_init(void)
++{
++	printk(KERN_INFO "Initializing ZigBee TTY interface\n");
++
++	if (tty_register_ldisc(N_IEEE802154, &ieee802154_ldisc) != 0) {
++		printk(KERN_ERR "%s: line discipline register failed\n",
++				__func__);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static void __exit ieee802154_serial_cleanup(void)
++{
++	if (tty_unregister_ldisc(N_IEEE802154) != 0)
++		printk(KERN_CRIT
++			"failed to unregister ZigBee line discipline.\n");
++}
++
++module_init(ieee802154_serial_init);
++module_exit(ieee802154_serial_cleanup);
++
++MODULE_LICENSE("GPL");
++MODULE_ALIAS_LDISC(N_IEEE802154);
+diff --git a/include/linux/nl802154.h b/include/linux/nl802154.h
+index fd4f2d1..25ed3ec 100644
+--- a/include/linux/nl802154.h
++++ b/include/linux/nl802154.h
+@@ -21,6 +21,8 @@
+ #ifndef NL802154_H
+ #define NL802154_H
+ 
++#include <net/netlink.h>
++
+ #define IEEE802154_NL_NAME "802.15.4 MAC"
+ #define IEEE802154_MCAST_COORD_NAME "coordinator"
+ #define IEEE802154_MCAST_BEACON_NAME "beacon"
+@@ -132,7 +134,6 @@ enum {
+ 
+ 	IEEE802154_DEV_WPAN,
+ 	IEEE802154_DEV_MONITOR,
+-
+ 	__IEEE802154_DEV_MAX,
+ };
+ 
+diff --git a/include/uapi/linux/tty.h b/include/uapi/linux/tty.h
+index dac199a..96233b1 100644
+--- a/include/uapi/linux/tty.h
++++ b/include/uapi/linux/tty.h
+@@ -34,5 +34,6 @@
+ #define N_TI_WL		22	/* for TI's WL BT, FM, GPS combo chips */
+ #define N_TRACESINK	23	/* Trace data routing for MIPI P1149.7 */
+ #define N_TRACEROUTER	24	/* Trace data routing for MIPI P1149.7 */
++#define N_IEEE802154	25	/* Serial / USB serial IEEE802154.4 devices */
+ 
+ #endif /* _UAPI_LINUX_TTY_H */
+diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
+index 70ff171..85bf4a9 100644
+--- a/net/ieee802154/6lowpan.c
++++ b/net/ieee802154/6lowpan.c
+@@ -59,6 +59,8 @@
+ #include <net/ieee802154.h>
+ #include <net/ieee802154_netdev.h>
+ #include <net/ipv6.h>
++#include <net/mac802154.h>
++
+ 
+ #include "6lowpan.h"
+ 
diff --git a/patches/linux-3.7-rc6/0119-i2c-EEPROM-Export-memory-accessor.patch b/patches/linux-3.7/0138-i2c-EEPROM-Export-memory-accessor.patch
index dc19a4a..171e5c0 100644
--- a/patches/linux-3.7-rc6/0119-i2c-EEPROM-Export-memory-accessor.patch
+++ b/patches/linux-3.7/0138-i2c-EEPROM-Export-memory-accessor.patch
@@ -1,4 +1,3 @@
-From d13ed856c7be4d21b920a440f1784e3c13752954 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 13 Oct 2012 16:06:48 +0300
 Subject: [PATCH] i2c-EEPROM: Export memory accessor
diff --git a/patches/linux-3.7-rc6/0120-omap-Export-omap_hwmod_lookup-omap_device_build-omap.patch b/patches/linux-3.7/0139-omap-Export-omap_hwmod_lookup-omap_device_build-omap.patch
index 854ce11..1ff3680 100644
--- a/patches/linux-3.7-rc6/0120-omap-Export-omap_hwmod_lookup-omap_device_build-omap.patch
+++ b/patches/linux-3.7/0139-omap-Export-omap_hwmod_lookup-omap_device_build-omap.patch
@@ -1,4 +1,3 @@
-From 1222463525efa67a795b293e46429f510768a2df Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 13 Oct 2012 16:34:44 +0300
 Subject: [PATCH] omap: Export
diff --git a/patches/linux-3.7-rc6/0121-gpio-keys-Pinctrl-fy.patch b/patches/linux-3.7/0140-gpio-keys-Pinctrl-fy.patch
index 3cf53f7..5faafc4 100644
--- a/patches/linux-3.7-rc6/0121-gpio-keys-Pinctrl-fy.patch
+++ b/patches/linux-3.7/0140-gpio-keys-Pinctrl-fy.patch
@@ -1,4 +1,3 @@
-From ae6cef3b75d1ab9a32fdd95d7a9ed516aa587972 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Wed, 17 Oct 2012 20:17:36 +0300
 Subject: [PATCH] gpio-keys: Pinctrl-fy
diff --git a/patches/linux-3.7-rc6/0122-tps65217-Allow-placement-elsewhere-than-parent-mfd-d.patch b/patches/linux-3.7/0141-tps65217-Allow-placement-elsewhere-than-parent-mfd-d.patch
index bdf9716..2ae0319 100644
--- a/patches/linux-3.7-rc6/0122-tps65217-Allow-placement-elsewhere-than-parent-mfd-d.patch
+++ b/patches/linux-3.7/0141-tps65217-Allow-placement-elsewhere-than-parent-mfd-d.patch
@@ -1,4 +1,3 @@
-From 60b3cfc365647a38b67719be3a134c392f1f6fe6 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Wed, 17 Oct 2012 20:17:57 +0300
 Subject: [PATCH] tps65217: Allow placement elsewhere than parent mfd device.
diff --git a/patches/linux-3.7-rc6/0123-pwm-export-of_pwm_request.patch b/patches/linux-3.7/0142-pwm-export-of_pwm_request.patch
index 2223575..cd81c81 100644
--- a/patches/linux-3.7-rc6/0123-pwm-export-of_pwm_request.patch
+++ b/patches/linux-3.7/0142-pwm-export-of_pwm_request.patch
@@ -1,4 +1,3 @@
-From fbcf0d6f0fb39e6d70d41f32844a9c13622010ea Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Fri, 19 Oct 2012 10:38:00 +0300
 Subject: [PATCH] pwm: export of_pwm_request
diff --git a/patches/linux-3.7-rc6/0124-i2c-Export-capability-to-probe-devices.patch b/patches/linux-3.7/0143-i2c-Export-capability-to-probe-devices.patch
index d72b464..3a888e2 100644
--- a/patches/linux-3.7-rc6/0124-i2c-Export-capability-to-probe-devices.patch
+++ b/patches/linux-3.7/0143-i2c-Export-capability-to-probe-devices.patch
@@ -1,4 +1,3 @@
-From b431efb8fef34dc5ea688fcf98851f4a2d42ef72 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Sat, 20 Oct 2012 14:08:17 +0300
 Subject: [PATCH] i2c: Export capability to probe devices
diff --git a/patches/linux-3.7-rc6/0125-pwm-backlight-Pinctrl-fy.patch b/patches/linux-3.7/0144-pwm-backlight-Pinctrl-fy.patch
index ccf1ddc..c18e0d5 100644
--- a/patches/linux-3.7-rc6/0125-pwm-backlight-Pinctrl-fy.patch
+++ b/patches/linux-3.7/0144-pwm-backlight-Pinctrl-fy.patch
@@ -1,4 +1,3 @@
-From cd1f5ff870b0977e4d6a4454c2758806f5f524c2 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Tue, 23 Oct 2012 11:48:58 +0300
 Subject: [PATCH] pwm-backlight: Pinctrl-fy
diff --git a/patches/linux-3.7-rc6/0126-spi-Export-OF-interfaces-for-capebus-use.patch b/patches/linux-3.7/0145-spi-Export-OF-interfaces-for-capebus-use.patch
index deac5fc..754ebfb 100644
--- a/patches/linux-3.7-rc6/0126-spi-Export-OF-interfaces-for-capebus-use.patch
+++ b/patches/linux-3.7/0145-spi-Export-OF-interfaces-for-capebus-use.patch
@@ -1,4 +1,3 @@
-From 0f227d7527b91f7c3536842549fc8de50c16b956 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Tue, 23 Oct 2012 13:23:14 +0300
 Subject: [PATCH] spi: Export OF interfaces for capebus use.
diff --git a/patches/linux-3.7-rc6/0127-w1-gpio-Pinctrl-fy.patch b/patches/linux-3.7/0146-w1-gpio-Pinctrl-fy.patch
index c735d63..6292b73 100644
--- a/patches/linux-3.7-rc6/0127-w1-gpio-Pinctrl-fy.patch
+++ b/patches/linux-3.7/0146-w1-gpio-Pinctrl-fy.patch
@@ -1,4 +1,3 @@
-From 24e009b4e579b589dd3a3bed2577e22517b21054 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Wed, 24 Oct 2012 09:54:37 +0300
 Subject: [PATCH] w1-gpio: Pinctrl-fy
diff --git a/patches/linux-3.7-rc6/0128-w1-gpio-Simplify-get-rid-of-defines.patch b/patches/linux-3.7/0147-w1-gpio-Simplify-get-rid-of-defines.patch
index dd5640f..125cf6d 100644
--- a/patches/linux-3.7-rc6/0128-w1-gpio-Simplify-get-rid-of-defines.patch
+++ b/patches/linux-3.7/0147-w1-gpio-Simplify-get-rid-of-defines.patch
@@ -1,4 +1,3 @@
-From 90429eda58f60e4684b5aba4ad8a6ff72da8f94e Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Wed, 24 Oct 2012 16:49:53 +0300
 Subject: [PATCH] w1-gpio: Simplify & get rid of defines
diff --git a/patches/linux-3.7-rc6/0129-arm-dt-Enable-DT-proc-updates.patch b/patches/linux-3.7/0148-arm-dt-Enable-DT-proc-updates.patch
index 0442646..a21d13a 100644
--- a/patches/linux-3.7-rc6/0129-arm-dt-Enable-DT-proc-updates.patch
+++ b/patches/linux-3.7/0148-arm-dt-Enable-DT-proc-updates.patch
@@ -1,4 +1,3 @@
-From 291e077b7d6d86c75b1ecbd894072d6256140a7e Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Fri, 26 Oct 2012 16:11:46 +0300
 Subject: [PATCH] arm-dt: Enable DT proc updates.
diff --git a/patches/linux-3.7-rc6/0130-ARM-CUSTOM-Build-a-uImage-with-dtb-already-appended.patch b/patches/linux-3.7/0149-ARM-CUSTOM-Build-a-uImage-with-dtb-already-appended.patch
index f5470f4..ebca33b 100644
--- a/patches/linux-3.7-rc6/0130-ARM-CUSTOM-Build-a-uImage-with-dtb-already-appended.patch
+++ b/patches/linux-3.7/0149-ARM-CUSTOM-Build-a-uImage-with-dtb-already-appended.patch
@@ -1,4 +1,3 @@
-From 99b06dce3bcdf014160203950451b9f84269c3e2 Mon Sep 17 00:00:00 2001
 From: Grant Likely <grant.likely@secretlab.ca>
 Date: Tue, 2 Aug 2011 15:30:09 +0100
 Subject: [PATCH] ARM: CUSTOM: Build a uImage with dtb already appended
diff --git a/patches/linux-3.7-rc6/0131-beaglebone-create-a-shared-dtsi-for-beaglebone-based.patch b/patches/linux-3.7/0150-beaglebone-create-a-shared-dtsi-for-beaglebone-based.patch
index 7d33a69..769e162 100644
--- a/patches/linux-3.7-rc6/0131-beaglebone-create-a-shared-dtsi-for-beaglebone-based.patch
+++ b/patches/linux-3.7/0150-beaglebone-create-a-shared-dtsi-for-beaglebone-based.patch
@@ -1,4 +1,3 @@
-From 69ae0a2048568b5ebc61c947153b4935b644f4b3 Mon Sep 17 00:00:00 2001
 From: Koen Kooi <koen@dominion.thruhere.net>
 Date: Tue, 30 Oct 2012 12:30:18 +0100
 Subject: [PATCH] beaglebone: create a shared dtsi for beaglebone based boards
diff --git a/patches/linux-3.7-rc6/0132-beaglebone-enable-emmc-for-bonelt.patch b/patches/linux-3.7/0151-beaglebone-enable-emmc-for-bonelt.patch
index dfe59fe..d0aaa27 100644
--- a/patches/linux-3.7-rc6/0132-beaglebone-enable-emmc-for-bonelt.patch
+++ b/patches/linux-3.7/0151-beaglebone-enable-emmc-for-bonelt.patch
@@ -1,4 +1,3 @@
-From 8b82f3581e17f14f6d7ac5bce043bb6bde7f9fe5 Mon Sep 17 00:00:00 2001
 From: Koen Kooi <koen@dominion.thruhere.net>
 Date: Wed, 24 Oct 2012 11:47:13 +0200
 Subject: [PATCH] beaglebone: enable emmc for bonelt
diff --git a/patches/linux-3.7/0152-da8xx-dt-Create-da8xx-DT-adapter-device.patch b/patches/linux-3.7/0152-da8xx-dt-Create-da8xx-DT-adapter-device.patch
new file mode 100644
index 0000000..06ea0b4
--- /dev/null
+++ b/patches/linux-3.7/0152-da8xx-dt-Create-da8xx-DT-adapter-device.patch
@@ -0,0 +1,232 @@
+From: Pantelis Antoniou <panto@antoniou-consulting.com>
+Date: Thu, 1 Nov 2012 15:19:35 +0200
+Subject: [PATCH] da8xx-dt: Create da8xx DT adapter device
+
+omap_device is going private.
+
+Move the da8xx-dt adapter device to arch/arm/mach-omap2.
+
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
+---
+ arch/arm/mach-omap2/Makefile   |    3 +
+ arch/arm/mach-omap2/da8xx-dt.c |  197 ++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 200 insertions(+)
+ create mode 100644 arch/arm/mach-omap2/da8xx-dt.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index fe40d9e..3a9a0ff 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -200,6 +200,9 @@ ifneq ($(CONFIG_DRM_OMAP),)
+ obj-y					+= drm.o
+ endif
+ 
++# AM3XX Device Tree adapters for legacy drivers
++obj-$(CONFIG_SOC_AM33XX)		+= da8xx-dt.o
++
+ # Specific board support
+ obj-$(CONFIG_MACH_OMAP_GENERIC)		+= board-generic.o
+ obj-$(CONFIG_MACH_OMAP_H4)		+= board-h4.o
+diff --git a/arch/arm/mach-omap2/da8xx-dt.c b/arch/arm/mach-omap2/da8xx-dt.c
+new file mode 100644
+index 0000000..d3c6f48
+--- /dev/null
++++ b/arch/arm/mach-omap2/da8xx-dt.c
+@@ -0,0 +1,197 @@
++/*
++ * DA8XX-DT: Device tree adapter using the legacy driver
++ *
++ * Copyright (C) 2012 Pantelis Antoniou <panto@antoniou-consulting.com>
++ * Copyright (C) 2012 Texas Instruments Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <video/da8xx-fb.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/clk.h>
++#include <plat/clock.h>
++#include <plat/omap_device.h>
++
++struct da8xx_priv {
++	struct da8xx_lcdc_platform_data lcd_pdata;
++	struct lcd_ctrl_config lcd_cfg;
++	struct display_panel lcd_panel;
++	struct platform_device *lcdc_pdev;
++	struct omap_hwmod *lcdc_oh;
++	struct resource lcdc_res[1];
++	int power_dn_gpio;
++};
++
++static const struct of_device_id of_da8xx_dt_match[] = {
++	{ .compatible = "da8xx-dt", },
++	{},
++};
++
++static int __devinit da8xx_dt_probe(struct platform_device *pdev)
++{
++	struct da8xx_priv *priv;
++	struct clk *disp_pll;
++	struct pinctrl *pinctrl;
++	u32 disp_pll_val;
++	const char *panel_type;
++	int ret = -EINVAL;
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (priv == NULL) {
++		dev_err(&pdev->dev, "Failed to allocate priv\n");
++		return -ENOMEM;
++	}
++	priv->power_dn_gpio = -1;
++
++	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++	if (IS_ERR(pinctrl))
++		dev_warn(&pdev->dev,
++			"pins are not configured from the driver\n");
++
++	ret = of_property_read_u32(pdev->dev.of_node, "disp-pll",
++			&disp_pll_val);
++	if (ret != 0) {
++		dev_err(&pdev->dev, "Failed to read disp-pll property\n");
++		return ret;
++	}
++
++	ret = of_property_read_string(pdev->dev.of_node, "panel-type",
++			&panel_type);
++	if (ret != 0) {
++		dev_err(&pdev->dev, "Failed to read panel-type property\n");
++		return ret;
++	}
++
++	/* conf_disp_pll(disp_pll); */
++	disp_pll = clk_get(NULL, "dpll_disp_ck");
++	if (IS_ERR(disp_pll)) {
++		dev_err(&pdev->dev, "Cannot clk_get disp_pll\n");
++		return PTR_ERR(disp_pll);
++	}
++	ret = clk_set_rate(disp_pll, disp_pll_val);
++	clk_put(disp_pll);
++	if (ret != 0) {
++		dev_err(&pdev->dev, "Failed to set disp_pll\n");
++		return ret;
++	}
++
++	ret = of_get_named_gpio_flags(pdev->dev.of_node, "powerdn-gpio",
++			0, NULL);
++	if (IS_ERR_VALUE(ret)) {
++		dev_info(&pdev->dev, "No power down GPIO\n");
++	} else {
++		priv->power_dn_gpio = ret;
++
++		ret = devm_gpio_request(&pdev->dev, priv->power_dn_gpio,
++				"da8xx-dt:PDN");
++		if (ret != 0) {
++			dev_err(&pdev->dev, "Failed to gpio_request\n");
++			return ret;
++		}
++
++		ret = gpio_direction_output(priv->power_dn_gpio, 1);
++		if (ret != 0) {
++			dev_err(&pdev->dev, "Failed to set powerdn to 1\n");
++			return ret;
++		}
++	}
++
++	/* display_panel */
++	priv->lcd_panel.panel_type	= QVGA;
++	priv->lcd_panel.max_bpp		= 16;
++	priv->lcd_panel.min_bpp		= 16;
++	priv->lcd_panel.panel_shade	= COLOR_ACTIVE;
++
++	/* lcd_ctrl_config */
++	priv->lcd_cfg.p_disp_panel	= &priv->lcd_panel;
++	priv->lcd_cfg.ac_bias		= 255;
++	priv->lcd_cfg.ac_bias_intrpt	= 0;
++	priv->lcd_cfg.dma_burst_sz	= 16;
++	priv->lcd_cfg.bpp		= 16;
++	priv->lcd_cfg.fdd		= 0x80;
++	priv->lcd_cfg.tft_alt_mode	= 0;
++	priv->lcd_cfg.stn_565_mode	= 0;
++	priv->lcd_cfg.mono_8bit_mode	= 0;
++	priv->lcd_cfg.invert_line_clock	= 1;
++	priv->lcd_cfg.invert_frm_clock	= 1;
++	priv->lcd_cfg.sync_edge		= 0;
++	priv->lcd_cfg.sync_ctrl		= 1;
++	priv->lcd_cfg.raster_order	= 0;
++
++	/* da8xx_lcdc_platform_data */
++	strcpy(priv->lcd_pdata.manu_name, "BBToys");
++	priv->lcd_pdata.controller_data = &priv->lcd_cfg;
++	strcpy(priv->lcd_pdata.type, panel_type);
++
++	priv->lcdc_oh = omap_hwmod_lookup("lcdc");
++	if (priv->lcdc_oh == NULL) {
++		dev_err(&pdev->dev, "Failed to lookup omap_hwmod lcdc\n");
++		return -ENODEV;
++	}
++
++	priv->lcdc_pdev = omap_device_build("da8xx_lcdc", 0, priv->lcdc_oh,
++			&priv->lcd_pdata,
++			sizeof(struct da8xx_lcdc_platform_data),
++			NULL, 0, 0);
++	if (priv->lcdc_pdev == NULL) {
++		dev_err(&pdev->dev, "Failed to build LCDC device\n");
++		return -ENODEV;
++	}
++
++	dev_info(&pdev->dev, "Registered bone LCDC OK.\n");
++
++	platform_set_drvdata(pdev, priv);
++
++	return 0;
++}
++
++static int __devexit da8xx_dt_remove(struct platform_device *pdev)
++{
++	return -EINVAL;	/* not supporting removal yet */
++}
++
++static struct platform_driver da8xx_dt_driver = {
++	.probe		= da8xx_dt_probe,
++	.remove		= __devexit_p(da8xx_dt_remove),
++	.driver		= {
++		.name	= "da8xx-dt",
++		.owner	= THIS_MODULE,
++		.of_match_table = of_da8xx_dt_match,
++	},
++};
++
++static __init int da8xx_dt_init(void)
++{
++	return platform_driver_register(&da8xx_dt_driver);
++}
++
++static __exit void da8xx_dt_exit(void)
++{
++	platform_driver_unregister(&da8xx_dt_driver);
++}
++
++postcore_initcall(da8xx_dt_init);
++module_exit(da8xx_dt_exit);
diff --git a/patches/linux-3.7/0153-ti-tscadc-dt-Create-ti-tscadc-dt-DT-adapter-device.patch b/patches/linux-3.7/0153-ti-tscadc-dt-Create-ti-tscadc-dt-DT-adapter-device.patch
new file mode 100644
index 0000000..28e6ac6
--- /dev/null
+++ b/patches/linux-3.7/0153-ti-tscadc-dt-Create-ti-tscadc-dt-DT-adapter-device.patch
@@ -0,0 +1,188 @@
+From: Pantelis Antoniou <panto@antoniou-consulting.com>
+Date: Thu, 1 Nov 2012 15:44:39 +0200
+Subject: [PATCH] ti-tscadc-dt: Create ti-tscadc-dt DT adapter device
+
+omap_device is going private.
+
+Move the ti-tscadc-dt adapter device to arch/arm/mach-omap2.
+
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
+---
+ arch/arm/mach-omap2/Makefile       |    1 +
+ arch/arm/mach-omap2/ti-tscadc-dt.c |  155 ++++++++++++++++++++++++++++++++++++
+ 2 files changed, 156 insertions(+)
+ create mode 100644 arch/arm/mach-omap2/ti-tscadc-dt.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 3a9a0ff..1eab37b 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -202,6 +202,7 @@ endif
+ 
+ # AM3XX Device Tree adapters for legacy drivers
+ obj-$(CONFIG_SOC_AM33XX)		+= da8xx-dt.o
++obj-$(CONFIG_SOC_AM33XX)		+= ti-tscadc-dt.o
+ 
+ # Specific board support
+ obj-$(CONFIG_MACH_OMAP_GENERIC)		+= board-generic.o
+diff --git a/arch/arm/mach-omap2/ti-tscadc-dt.c b/arch/arm/mach-omap2/ti-tscadc-dt.c
+new file mode 100644
+index 0000000..0a1a17a
+--- /dev/null
++++ b/arch/arm/mach-omap2/ti-tscadc-dt.c
+@@ -0,0 +1,155 @@
++/*
++ * TI-TSCADC-DT: Device tree adapter using the legacy driver
++ *
++ * Copyright (C) 2012 Pantelis Antoniou <panto@antoniou-consulting.com>
++ * Copyright (C) 2012 Texas Instruments Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/clk.h>
++#include <linux/input/ti_am335x_tsc.h>
++#include <linux/platform_data/ti_am335x_adc.h>
++#include <linux/mfd/ti_am335x_tscadc.h>
++#include <plat/clock.h>
++#include <plat/omap_device.h>
++
++struct ti_tscadc_priv {
++	struct omap_hwmod *tsc_oh;
++	struct tsc_data tsc_data;
++	struct adc_data adc_data;
++	struct mfd_tscadc_board tscadc_data;
++	struct platform_device *tscadc_pdev;
++};
++
++static const struct of_device_id of_ti_tscadc_dt_match[] = {
++	{ .compatible = "ti-tscadc-dt", },
++	{},
++};
++
++static int __devinit ti_tscadc_dt_probe(struct platform_device *pdev)
++{
++	struct ti_tscadc_priv *priv;
++	struct pinctrl *pinctrl;
++	u32 val;
++	int ret;
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (priv == NULL) {
++		dev_err(&pdev->dev, "Failed to allocate priv\n");
++		return -ENOMEM;
++	}
++
++	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++	if (IS_ERR(pinctrl))
++		dev_warn(&pdev->dev,
++			"pins are not configured from the driver\n");
++
++	ret = of_property_read_u32(pdev->dev.of_node, "tsc-wires", &val);
++	if (ret != 0) {
++		dev_info(&pdev->dev, "no tsc-wires property; disabling TSC\n");
++		val = 0;
++	}
++	priv->tsc_data.wires = val;
++
++	if (priv->tsc_data.wires > 0) {
++		ret = of_property_read_u32(pdev->dev.of_node,
++				"tsc-x-plate-resistance", &val);
++		if (ret != 0) {
++			dev_err(&pdev->dev, "Failed to read "
++					"tsc-x-plate-resistance property\n");
++			return ret;
++		}
++		priv->tsc_data.x_plate_resistance = val;
++
++		ret = of_property_read_u32(pdev->dev.of_node,
++				"tsc-steps", &val);
++		if (ret != 0) {
++			dev_err(&pdev->dev, "Failed to read "
++					"tsc-steps property\n");
++			return ret;
++		}
++		priv->tsc_data.steps_to_configure = val;
++	}
++
++	ret = of_property_read_u32(pdev->dev.of_node, "adc-channels", &val);
++	if (ret != 0) {
++		dev_info(&pdev->dev, "No adc-channels property; "
++				"disabling adc\n");
++		val = 0;
++	}
++	priv->adc_data.adc_channels = val;
++
++	priv->tscadc_data.tsc_init = &priv->tsc_data;
++	priv->tscadc_data.adc_init = &priv->adc_data;
++
++	priv->tsc_oh = omap_hwmod_lookup("adc_tsc");
++	if (priv->tsc_oh == NULL) {
++		dev_err(&pdev->dev, "Could not lookup HWMOD %s\n", "adc_tsc");
++		return -ENODEV;
++	}
++
++	priv->tscadc_pdev = omap_device_build("ti_tscadc", -1, priv->tsc_oh,
++			&priv->tscadc_data, sizeof(priv->tscadc_data),
++			NULL, 0, 0);
++	if (priv->tscadc_pdev == NULL) {
++		dev_err(&pdev->dev, "Could not create tsc_adc device\n");
++		return -ENODEV;
++	}
++
++	dev_info(&pdev->dev, "TI tscadc pdev created OK\n");
++
++	platform_set_drvdata(pdev, priv);
++
++	return 0;
++}
++
++static int __devexit ti_tscadc_dt_remove(struct platform_device *pdev)
++{
++	return -EINVAL;	/* not supporting removal yet */
++}
++
++static struct platform_driver ti_tscadc_dt_driver = {
++	.probe		= ti_tscadc_dt_probe,
++	.remove		= __devexit_p(ti_tscadc_dt_remove),
++	.driver		= {
++		.name	= "ti_tscadc-dt",
++		.owner	= THIS_MODULE,
++		.of_match_table = of_ti_tscadc_dt_match,
++	},
++};
++
++static __init int ti_tscadc_dt_init(void)
++{
++	return platform_driver_register(&ti_tscadc_dt_driver);
++}
++
++static __exit void ti_tscadc_dt_exit(void)
++{
++	platform_driver_unregister(&ti_tscadc_dt_driver);
++}
++
++postcore_initcall(ti_tscadc_dt_init);
++module_exit(ti_tscadc_dt_exit);
diff --git a/patches/linux-3.7-rc6/0133-capebus-Core-capebus-support.patch b/patches/linux-3.7/0154-capebus-Core-capebus-support.patch
index cf81437..14b1f73 100644
--- a/patches/linux-3.7-rc6/0133-capebus-Core-capebus-support.patch
+++ b/patches/linux-3.7/0154-capebus-Core-capebus-support.patch
@@ -1,8 +1,20 @@
-From cad1e139fd88a35c63f0119541de52e5d9cb45fc Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Tue, 30 Oct 2012 21:06:06 +0200
 Subject: [PATCH] capebus: Core capebus support
 
+Introducing capebus; a bus that allows small boards (capes) to connect
+to a complex SoC using simple expansion connectors.
+
+Up to now to support these kind of boards, one had to hack the board files,
+and do all sort of gymnastics to handle all the different cases of
+conflict resolution.
+
+Capebus provides abstractions that keep the pain to a minimum.
+
+This part of the series is introducing the core capebus functionality
+dealing with the basic bus & driver probe functions.
+
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
 ---
  drivers/Kconfig                  |    2 +
  drivers/Makefile                 |    3 +
diff --git a/patches/linux-3.7-rc6/0134-capebus-Add-beaglebone-board-support.patch b/patches/linux-3.7/0155-capebus-Add-beaglebone-board-support.patch
index edf46cb..2cafc5d 100644
--- a/patches/linux-3.7-rc6/0134-capebus-Add-beaglebone-board-support.patch
+++ b/patches/linux-3.7/0155-capebus-Add-beaglebone-board-support.patch
@@ -1,16 +1,28 @@
-From 2f38e4b945ff8671b3a8341872188cfd0b5ff1f2 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Tue, 30 Oct 2012 21:07:50 +0200
 Subject: [PATCH] capebus: Add beaglebone board support
 
+Introduce beaglebone capebus board support.
+
+This patch creates the beaglebone's board cape bus controller.
+
+The board controller is responsible for the probing of capes
+at the well defined I2C address for capes, parsing the EEPROM
+info and matching them to specific cape drivers.
+
+On top of that, adapter DT enabled devices are created for
+am33xx devices that have no DT bindings yet, as well as generic
+devices that can be used as building blocks for the cape drivers.
+
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
 ---
  drivers/capebus/boards/Kconfig                |    6 +
  drivers/capebus/boards/Makefile               |    3 +
  drivers/capebus/boards/capebus-bone-generic.c |  237 +++++++
- drivers/capebus/boards/capebus-bone-pdevs.c   |  602 ++++++++++++++++
+ drivers/capebus/boards/capebus-bone-pdevs.c   |  328 +++++++++
  drivers/capebus/boards/capebus-bone.c         |  931 +++++++++++++++++++++++++
  include/linux/capebus/capebus-bone.h          |  120 ++++
- 6 files changed, 1899 insertions(+)
+ 6 files changed, 1625 insertions(+)
  create mode 100644 drivers/capebus/boards/Kconfig
  create mode 100644 drivers/capebus/boards/Makefile
  create mode 100644 drivers/capebus/boards/capebus-bone-generic.c
@@ -284,10 +296,10 @@ index 0000000..b1b79eb
 +EXPORT_SYMBOL(bone_capebus_remove_generic);
 diff --git a/drivers/capebus/boards/capebus-bone-pdevs.c b/drivers/capebus/boards/capebus-bone-pdevs.c
 new file mode 100644
-index 0000000..a55aad6
+index 0000000..f32134a
 --- /dev/null
 +++ b/drivers/capebus/boards/capebus-bone-pdevs.c
-@@ -0,0 +1,602 @@
+@@ -0,0 +1,328 @@
 +/*
 + * TI Beaglebone capebus controller - Platform adapters
 + *
@@ -321,282 +333,18 @@ index 0000000..a55aad6
 +#include <linux/of.h>
 +#include <linux/of_device.h>
 +#include <linux/of_gpio.h>
-+#include <video/da8xx-fb.h>
 +#include <linux/pinctrl/pinctrl.h>
 +#include <linux/pinctrl/pinmux.h>
 +#include <linux/pinctrl/consumer.h>
 +#include <linux/atomic.h>
 +#include <linux/clk.h>
 +#include <asm/barrier.h>
-+#include <plat/clock.h>
-+#include <plat/omap_device.h>
-+#include <linux/clkdev.h>
-+#include <linux/input/ti_am335x_tsc.h>
-+#include <linux/platform_data/ti_am335x_adc.h>
-+#include <linux/mfd/ti_am335x_tscadc.h>
 +#include <linux/i2c.h>
 +#include <linux/of_i2c.h>
 +#include <linux/spi/spi.h>
 +
 +#include <linux/capebus/capebus-bone.h>
 +
-+#if defined(CONFIG_FB_DA8XX) || defined(CONFIG_FB_DA8XX_MODULE)
-+
-+struct da8xx_priv {
-+	struct da8xx_lcdc_platform_data lcd_pdata;
-+	struct lcd_ctrl_config lcd_cfg;
-+	struct display_panel lcd_panel;
-+	struct platform_device *lcdc_pdev;
-+	struct omap_hwmod *lcdc_oh;
-+	struct resource lcdc_res[1];
-+	int power_dn_gpio;
-+};
-+
-+static const struct of_device_id of_da8xx_dt_match[] = {
-+	{ .compatible = "da8xx-dt", },
-+	{},
-+};
-+
-+static int __devinit da8xx_dt_probe(struct platform_device *pdev)
-+{
-+	struct da8xx_priv *priv;
-+	struct clk *disp_pll;
-+	struct pinctrl *pinctrl;
-+	u32 disp_pll_val;
-+	const char *panel_type;
-+	int ret = -EINVAL;
-+
-+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+	if (priv == NULL) {
-+		dev_err(&pdev->dev, "Failed to allocate priv\n");
-+		return -ENOMEM;
-+	}
-+	priv->power_dn_gpio = -1;
-+
-+	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-+	if (IS_ERR(pinctrl))
-+		dev_warn(&pdev->dev,
-+			"pins are not configured from the driver\n");
-+
-+	ret = of_property_read_u32(pdev->dev.of_node, "disp-pll", &disp_pll_val);
-+	if (ret != 0) {
-+		dev_err(&pdev->dev, "Failed to read disp-pll property\n");
-+		return ret;
-+	}
-+
-+	ret = of_property_read_string(pdev->dev.of_node, "panel-type", &panel_type);
-+	if (ret != 0) {
-+		dev_err(&pdev->dev, "Failed to read panel-type property\n");
-+		return ret;
-+	}
-+
-+	/* conf_disp_pll(disp_pll); */
-+	disp_pll = clk_get(NULL, "dpll_disp_ck");
-+	if (IS_ERR(disp_pll)) {
-+		dev_err(&pdev->dev, "Cannot clk_get disp_pll\n");
-+		return PTR_ERR(disp_pll);
-+	}
-+	ret = clk_set_rate(disp_pll, disp_pll_val);
-+	clk_put(disp_pll);
-+	if (ret != 0) {
-+		dev_err(&pdev->dev, "Failed to set disp_pll\n");
-+		return ret;
-+	}
-+
-+	ret = of_get_named_gpio_flags(pdev->dev.of_node, "powerdn-gpio",
-+			0, NULL);
-+	if (IS_ERR_VALUE(ret)) {
-+		dev_info(&pdev->dev, "No power down GPIO\n");
-+	} else {
-+		priv->power_dn_gpio = ret;
-+
-+		ret = devm_gpio_request(&pdev->dev, priv->power_dn_gpio, "bone-dvi-cape:DVI_PDN");
-+		if (ret != 0) {
-+			dev_err(&pdev->dev, "Failed to gpio_request\n");
-+			return ret;
-+		}
-+
-+		ret = gpio_direction_output(priv->power_dn_gpio, 1);
-+		if (ret != 0) {
-+			dev_err(&pdev->dev, "Failed to set powerdn to 1\n");
-+			return ret;
-+		}
-+	}
-+
-+	/* display_panel */
-+	priv->lcd_panel.panel_type	= QVGA;
-+	priv->lcd_panel.max_bpp		= 16;
-+	priv->lcd_panel.min_bpp		= 16;
-+	priv->lcd_panel.panel_shade	= COLOR_ACTIVE;
-+
-+	/* lcd_ctrl_config */
-+	priv->lcd_cfg.p_disp_panel	= &priv->lcd_panel;
-+	priv->lcd_cfg.ac_bias		= 255;
-+	priv->lcd_cfg.ac_bias_intrpt	= 0;
-+	priv->lcd_cfg.dma_burst_sz	= 16;
-+	priv->lcd_cfg.bpp		= 16;
-+	priv->lcd_cfg.fdd		= 0x80;
-+	priv->lcd_cfg.tft_alt_mode	= 0;
-+	priv->lcd_cfg.stn_565_mode	= 0;
-+	priv->lcd_cfg.mono_8bit_mode	= 0;
-+	priv->lcd_cfg.invert_line_clock	= 1;
-+	priv->lcd_cfg.invert_frm_clock	= 1;
-+	priv->lcd_cfg.sync_edge		= 0;
-+	priv->lcd_cfg.sync_ctrl		= 1;
-+	priv->lcd_cfg.raster_order	= 0;
-+
-+	/* da8xx_lcdc_platform_data */
-+	strcpy(priv->lcd_pdata.manu_name, "BBToys");
-+	priv->lcd_pdata.controller_data = &priv->lcd_cfg;
-+	strcpy(priv->lcd_pdata.type, panel_type);
-+
-+	priv->lcdc_oh = omap_hwmod_lookup("lcdc");
-+	if (priv->lcdc_oh == NULL) {
-+		dev_err(&pdev->dev, "Failed to lookup omap_hwmod lcdc\n");
-+		return -ENODEV;
-+	}
-+
-+	priv->lcdc_pdev = omap_device_build("da8xx_lcdc", 0, priv->lcdc_oh,
-+			&priv->lcd_pdata,
-+			sizeof(struct da8xx_lcdc_platform_data),
-+			NULL, 0, 0);
-+	if (priv->lcdc_pdev == NULL) {
-+		dev_err(&pdev->dev, "Failed to build LCDC device\n");
-+		return -ENODEV;
-+	}
-+
-+	dev_info(&pdev->dev, "Registered bone LCDC OK.\n");
-+
-+	platform_set_drvdata(pdev, priv);
-+
-+	return 0;
-+}
-+
-+static int __devexit da8xx_dt_remove(struct platform_device *pdev)
-+{
-+	return -EINVAL;	/* not supporting removal yet */
-+}
-+
-+static struct platform_driver da8xx_dt_driver = {
-+	.probe		= da8xx_dt_probe,
-+	.remove		= __devexit_p(da8xx_dt_remove),
-+	.driver		= {
-+		.name	= "da8xx-dt",
-+		.owner	= THIS_MODULE,
-+		.of_match_table = of_da8xx_dt_match,
-+	},
-+};
-+
-+#endif
-+
-+#if defined(CONFIG_MFD_TI_AM335X_TSCADC) || defined(CONFIG_MFD_TI_AM335X_TSCADC_MODULE)
-+
-+struct ti_tscadc_priv {
-+	struct omap_hwmod *tsc_oh;
-+	struct tsc_data tsc_data;
-+	struct adc_data adc_data;
-+	struct mfd_tscadc_board tscadc_data;
-+	struct platform_device *tscadc_pdev;
-+};
-+
-+static const struct of_device_id of_ti_tscadc_dt_match[] = {
-+	{ .compatible = "ti-tscadc-dt", },
-+	{},
-+};
-+
-+static int __devinit ti_tscadc_dt_probe(struct platform_device *pdev)
-+{
-+	struct ti_tscadc_priv *priv;
-+	struct pinctrl *pinctrl;
-+	u32 val;
-+	int ret;
-+
-+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+	if (priv == NULL) {
-+		dev_err(&pdev->dev, "Failed to allocate priv\n");
-+		return -ENOMEM;
-+	}
-+
-+	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-+	if (IS_ERR(pinctrl))
-+		dev_warn(&pdev->dev,
-+			"pins are not configured from the driver\n");
-+
-+	ret = of_property_read_u32(pdev->dev.of_node, "tsc-wires", &val);
-+	if (ret != 0) {
-+		dev_info(&pdev->dev, "no tsc-wires property; disabling TSC\n");
-+		val = 0;
-+	}
-+	priv->tsc_data.wires = val;
-+
-+	if (priv->tsc_data.wires > 0) {
-+		ret = of_property_read_u32(pdev->dev.of_node,
-+				"tsc-x-plate-resistance", &val);
-+		if (ret != 0) {
-+			dev_err(&pdev->dev, "Failed to read "
-+					"tsc-x-plate-resistance property\n");
-+			return ret;
-+		}
-+		priv->tsc_data.x_plate_resistance = val;
-+
-+		ret = of_property_read_u32(pdev->dev.of_node,
-+				"tsc-steps", &val);
-+		if (ret != 0) {
-+			dev_err(&pdev->dev, "Failed to read "
-+					"tsc-steps property\n");
-+			return ret;
-+		}
-+		priv->tsc_data.steps_to_configure = val;
-+	}
-+
-+	ret = of_property_read_u32(pdev->dev.of_node, "adc-channels", &val);
-+	if (ret != 0) {
-+		dev_info(&pdev->dev, "No adc-channels property; disabling adc\n");
-+		val = 0;
-+	}
-+	priv->adc_data.adc_channels = val;
-+
-+	priv->tscadc_data.tsc_init = &priv->tsc_data;
-+	priv->tscadc_data.adc_init = &priv->adc_data;
-+
-+	priv->tsc_oh = omap_hwmod_lookup("adc_tsc");
-+	if (priv->tsc_oh == NULL) {
-+		dev_err(&pdev->dev, "Could not lookup HWMOD %s\n", "adc_tsc");
-+		return -ENODEV;
-+	}
-+
-+	priv->tscadc_pdev = omap_device_build("ti_tscadc", -1, priv->tsc_oh,
-+			&priv->tscadc_data, sizeof(priv->tscadc_data),
-+			NULL, 0, 0);
-+	if (priv->tscadc_pdev == NULL) {
-+		dev_err(&pdev->dev, "Could not create tsc_adc device\n");
-+		return -ENODEV;
-+	}
-+
-+	dev_info(&pdev->dev, "TI tscadc pdev created OK\n");
-+
-+	platform_set_drvdata(pdev, priv);
-+
-+	return 0;
-+}
-+
-+static int __devexit ti_tscadc_dt_remove(struct platform_device *pdev)
-+{
-+	return -EINVAL;	/* not supporting removal yet */
-+}
-+
-+static struct platform_driver ti_tscadc_dt_driver = {
-+	.probe		= ti_tscadc_dt_probe,
-+	.remove		= __devexit_p(ti_tscadc_dt_remove),
-+	.driver		= {
-+		.name	= "ti_tscadc-dt",
-+		.owner	= THIS_MODULE,
-+		.of_match_table = of_ti_tscadc_dt_match,
-+	},
-+};
-+
-+#endif
-+
 +struct i2c_priv {
 +	struct i2c_adapter *i2c_adapter;
 +	phandle parent_handle;
@@ -810,16 +558,6 @@ index 0000000..a55aad6
 +};
 +
 +static struct bone_capebus_pdev_driver pdev_drivers[] = {
-+#if defined(CONFIG_FB_DA8XX) || defined(CONFIG_FB_DA8XX_MODULE)
-+	{
-+		.driver		= &da8xx_dt_driver,
-+	},
-+#endif
-+#if defined(CONFIG_MFD_TI_AM335X_TSCADC) || defined(CONFIG_MFD_TI_AM335X_TSCADC_MODULE)
-+	{
-+		.driver		= &ti_tscadc_dt_driver,
-+	},
-+#endif
 +	{
 +		.driver		= &i2c_dt_driver,
 +	},
diff --git a/patches/linux-3.7-rc6/0135-capebus-Beaglebone-generic-board.patch b/patches/linux-3.7/0156-capebus-Beaglebone-generic-cape-support.patch
index a122522..959deee 100644
--- a/patches/linux-3.7-rc6/0135-capebus-Beaglebone-generic-board.patch
+++ b/patches/linux-3.7/0156-capebus-Beaglebone-generic-cape-support.patch
@@ -1,13 +1,22 @@
-From 48eaefd05e5487625d5b58c959daf785af664b95 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Tue, 30 Oct 2012 21:09:49 +0200
-Subject: [PATCH] capebus: Beaglebone generic board
+Subject: [PATCH] capebus: Beaglebone generic cape support
 
+Introducing beaglebone generic cape support.
+
+With this you can create almost any kind of cape driver
+that doesn't require complex interconnection of the parts.
+
+Most beaglebone capes can be created with this, including
+all the display capes (DVI/VGA/LCD) with touchscreen or not,
+capes that only use i2c or spi devices, gpio-keys, leds etc.
+
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
 ---
- drivers/capebus/capes/Kconfig             |    6 ++
+ drivers/capebus/capes/Kconfig             |    6 +++
  drivers/capebus/capes/Makefile            |    1 +
- drivers/capebus/capes/bone-generic-cape.c |   96 +++++++++++++++++++++++++++++
- 3 files changed, 103 insertions(+)
+ drivers/capebus/capes/bone-generic-cape.c |   75 +++++++++++++++++++++++++++++
+ 3 files changed, 82 insertions(+)
  create mode 100644 drivers/capebus/capes/Kconfig
  create mode 100644 drivers/capebus/capes/Makefile
  create mode 100644 drivers/capebus/capes/bone-generic-cape.c
@@ -33,10 +42,10 @@ index 0000000..83da381
 +obj-$(CONFIG_CAPEBUS_BONE_GENERIC)	+= bone-generic-cape.o
 diff --git a/drivers/capebus/capes/bone-generic-cape.c b/drivers/capebus/capes/bone-generic-cape.c
 new file mode 100644
-index 0000000..70be50a
+index 0000000..b364614
 --- /dev/null
 +++ b/drivers/capebus/capes/bone-generic-cape.c
-@@ -0,0 +1,96 @@
+@@ -0,0 +1,75 @@
 +/*
 + * Generic cape support
 + *
@@ -60,28 +69,7 @@ index 0000000..70be50a
 +
 +#include <linux/module.h>
 +#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/timer.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/bitops.h>
 +#include <linux/err.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_gpio.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/atomic.h>
-+#include <linux/clk.h>
-+#include <asm/barrier.h>
-+#include <plat/clock.h>
-+#include <plat/omap_device.h>
-+#include <linux/clkdev.h>
-+#include <linux/input/ti_am335x_tsc.h>
-+#include <linux/platform_data/ti_am335x_adc.h>
-+#include <linux/mfd/ti_am335x_tscadc.h>
 +
 +#include <linux/capebus/capebus-bone.h>
 +
diff --git a/patches/linux-3.7-rc6/0136-capebus-Add-beaglebone-geiger-cape.patch b/patches/linux-3.7/0157-capebus-Beaglebone-geiger-cape-support.patch
index b927473..0ff2143 100644
--- a/patches/linux-3.7-rc6/0136-capebus-Add-beaglebone-geiger-cape.patch
+++ b/patches/linux-3.7/0157-capebus-Beaglebone-geiger-cape-support.patch
@@ -1,13 +1,19 @@
-From fbcfeae4d5b070b1300d5b42036a5714fc35cd34 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Tue, 30 Oct 2012 21:12:20 +0200
-Subject: [PATCH] capebus: Add beaglebone geiger cape
+Subject: [PATCH] capebus: Beaglebone geiger cape support
 
+Support beaglebone's geiger cape.
+
+The geiger cape allows you to measure the amount of
+ionising radiation in your area, and as an example
+of how to create a complex non-generic cape driver.
+
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
 ---
  drivers/capebus/capes/Kconfig            |    7 +
  drivers/capebus/capes/Makefile           |    1 +
- drivers/capebus/capes/bone-geiger-cape.c |  506 ++++++++++++++++++++++++++++++
- 3 files changed, 514 insertions(+)
+ drivers/capebus/capes/bone-geiger-cape.c |  517 ++++++++++++++++++++++++++++++
+ 3 files changed, 525 insertions(+)
  create mode 100644 drivers/capebus/capes/bone-geiger-cape.c
 
 diff --git a/drivers/capebus/capes/Kconfig b/drivers/capebus/capes/Kconfig
@@ -34,13 +40,28 @@ index 83da381..d6f94ce 100644
 +obj-$(CONFIG_CAPEBUS_BONE_GEIGER)	+= bone-geiger-cape.o
 diff --git a/drivers/capebus/capes/bone-geiger-cape.c b/drivers/capebus/capes/bone-geiger-cape.c
 new file mode 100644
-index 0000000..880eaae
+index 0000000..9b3a83d
 --- /dev/null
 +++ b/drivers/capebus/capes/bone-geiger-cape.c
-@@ -0,0 +1,506 @@
+@@ -0,0 +1,517 @@
 +/*
 + * Driver for beaglebone Geiger cape
 + *
++ * Copyright (C) 2012 Pantelis Antoniou <panto@antoniou-consulting.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 + */
 +
 +#include <linux/module.h>
@@ -61,9 +82,6 @@ index 0000000..880eaae
 +#include <linux/atomic.h>
 +#include <linux/clk.h>
 +#include <linux/interrupt.h>
-+#include <asm/barrier.h>
-+#include <plat/clock.h>
-+#include <plat/omap_device.h>
 +#include <linux/clkdev.h>
 +#include <linux/pwm.h>
 +#include <linux/math64.h>
@@ -72,7 +90,6 @@ index 0000000..880eaae
 +#include <linux/input/ti_am335x_tsc.h>
 +#include <linux/platform_data/ti_am335x_adc.h>
 +#include <linux/mfd/ti_am335x_tscadc.h>
-+#include <plat/omap_device.h>
 +#include <linux/iio/iio.h>
 +#include <linux/iio/machine.h>
 +#include <linux/iio/consumer.h>
diff --git a/patches/linux-3.7-rc6/0137-capebus-Beaglebone-capebus-DT-update.patch b/patches/linux-3.7/0158-capebus-Beaglebone-capebus-DT-update.patch
index 6bd80a7..329b541 100644
--- a/patches/linux-3.7-rc6/0137-capebus-Beaglebone-capebus-DT-update.patch
+++ b/patches/linux-3.7/0158-capebus-Beaglebone-capebus-DT-update.patch
@@ -1,8 +1,11 @@
-From 7433fff737ca214acb70407dfec888312a19057f Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Tue, 30 Oct 2012 21:16:57 +0200
 Subject: [PATCH] capebus: Beaglebone capebus DT update
 
+Update the common beaglebone's DTS with the required DT
+entries for all known working capes as of now.
+
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
 ---
  arch/arm/boot/dts/am335x-bone-common.dtsi |  689 +++++++++++++++++++++++++++--
  1 file changed, 659 insertions(+), 30 deletions(-)
diff --git a/patches/linux-3.7/0159-capebus-Document-DT-bindings.patch b/patches/linux-3.7/0159-capebus-Document-DT-bindings.patch
new file mode 100644
index 0000000..f0125ec
--- /dev/null
+++ b/patches/linux-3.7/0159-capebus-Document-DT-bindings.patch
@@ -0,0 +1,471 @@
+From: Pantelis Antoniou <panto@antoniou-consulting.com>
+Date: Wed, 31 Oct 2012 16:16:44 +0200
+Subject: [PATCH] capebus: Document DT bindings
+
+Describe capebus DT bindings in detail.
+
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
+---
+ .../capebus/bone-capebus-slot-override.txt         |   28 ++++++
+ .../devicetree/bindings/capebus/bone-capebus.txt   |   50 ++++++++++
+ .../bindings/capebus/bone-geiger-cape.txt          |   78 ++++++++++++++++
+ .../bindings/capebus/bone-generic-cape.txt         |   97 ++++++++++++++++++++
+ .../devicetree/bindings/capebus/da8xx-dt.txt       |   31 +++++++
+ .../devicetree/bindings/capebus/i2c-dt.txt         |   42 +++++++++
+ .../devicetree/bindings/capebus/spi-dt.txt         |   37 ++++++++
+ .../devicetree/bindings/capebus/ti-tscadc-dt.txt   |   34 +++++++
+ 8 files changed, 397 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/capebus/bone-capebus-slot-override.txt
+ create mode 100644 Documentation/devicetree/bindings/capebus/bone-capebus.txt
+ create mode 100644 Documentation/devicetree/bindings/capebus/bone-geiger-cape.txt
+ create mode 100644 Documentation/devicetree/bindings/capebus/bone-generic-cape.txt
+ create mode 100644 Documentation/devicetree/bindings/capebus/da8xx-dt.txt
+ create mode 100644 Documentation/devicetree/bindings/capebus/i2c-dt.txt
+ create mode 100644 Documentation/devicetree/bindings/capebus/spi-dt.txt
+ create mode 100644 Documentation/devicetree/bindings/capebus/ti-tscadc-dt.txt
+
+diff --git a/Documentation/devicetree/bindings/capebus/bone-capebus-slot-override.txt b/Documentation/devicetree/bindings/capebus/bone-capebus-slot-override.txt
+new file mode 100644
+index 0000000..733d977
+--- /dev/null
++++ b/Documentation/devicetree/bindings/capebus/bone-capebus-slot-override.txt
+@@ -0,0 +1,28 @@
++* Beagle bone capebus slot override bindings
++
++The beagle bone capebus node can have slot override nodes. These nodes describe
++  an override that will take place in the specified slot.
++  Many boards during the prototype phase don't have an EEPROM (or are even
++  wired in such a way that an eeprom cannot be added). In that case you can
++  specify an override that will make everything work as if a real EEPROM was
++  there.
++
++Required properties:
++- compatible: Override node must have the form "bone-capebus-slot-override"
++- slot: Identifies the slot# to override.
++- board-name: The cape's name as if provided by the board-name EEPROM field
++
++Optional properties:
++- version: The cape's version as if provided by the version EEPROM field.
++- manufacturer: The cape's manufacturer as if provided by the manufacturer
++  EEPROM field.
++
++Example:
++
++override@1 {
++	compatible = "bone-capebus-slot-override";
++	slot = <1>;
++	board-name = "Adafruit 1.8 Cape";
++	version = "00A0";
++	manufacturer = "Adafruit";
++};
+diff --git a/Documentation/devicetree/bindings/capebus/bone-capebus.txt b/Documentation/devicetree/bindings/capebus/bone-capebus.txt
+new file mode 100644
+index 0000000..6d8a08d
+--- /dev/null
++++ b/Documentation/devicetree/bindings/capebus/bone-capebus.txt
+@@ -0,0 +1,50 @@
++* Beagle bone capebus bindings
++
++The beaglebone capebus implementation is using a single capebus
++node contained in the root node. A beaglebone cape is identified
++at by reading an EEPROM at on of 4 possible addresses on the I2C2 bus.
++
++Required properties:
++- compatible: Every beaglebone compatible capebus node shall have the 
++  form "bone-capebus";
++- slots: An array of phandles pointing to the I2C node of an EEPROM that 
++  contains the cape information.
++
++Optional properties:
++
++The child nodes of the capebus node can contain either cape nodes
++or override nodes. Those cape nodes are described in their respective
++binding files.
++
++- override nodes: Describe an override that will take place in the specified
++  slot. Many boards during the prototype phase don't have an EEPROM (or are even
++  wired in such a way that an eeprom cannot be added). In that case you can
++  specify an override that will make everything work as if a real EEPROM was
++  there.
++
++Override node required properties:
++- compatible: For override node must have the form "bone-capebus-slot-override"
++- slot: Identifies the slot# to override.
++- board-name: The cape's name as if provided by the board-name EEPROM field
++
++Override node optional properties:
++- version: The cape's version as if provided by the version EEPROM field.
++- manufacturer: The cape's manufacturer as if provided by the manufacturer
++  EEPROM field.
++
++Example:
++
++capebus: capebus@0 {
++	compatible = "bone-capebus";
++
++	slots = <&cape_eeprom_0 &cape_eeprom_1 &cape_eeprom_2 &cape_eeprom_3>;
++
++	[cape-nodes]
++	[override-nodes]
++
++	bone_adafruit_cape: cape@5 {
++		compatible = "bone-generic-cape";
++		// read the bone-generic-cape bindings for the rest
++		...
++	};
++};
+diff --git a/Documentation/devicetree/bindings/capebus/bone-geiger-cape.txt b/Documentation/devicetree/bindings/capebus/bone-geiger-cape.txt
+new file mode 100644
+index 0000000..a2ed81c
+--- /dev/null
++++ b/Documentation/devicetree/bindings/capebus/bone-geiger-cape.txt
+@@ -0,0 +1,78 @@
++* Beagle bone geiger cape
++
++  A geiger cape is your run of the mill particle detector measuring
++  ionizing radiation. It is also the first example of how a non-generic
++  cape can be supported by capebus.
++
++  The geiger cape can not be created via instantiation of a generic cape 
++  since the component need to work together.
++
++Required properties:
++- compatible: Generic cape nodes must have the form "bone-geiger-cape"
++- board-name: The cape's name as if provided by the board-name EEPROM field
++- pwms: Pointer to the PWM we require
++- pwm-names: Name of the PWM.
++- pwm-frequency: Frequency of the PWM in Hz
++- pwm-duty-cycle: Duty cycle in percent
++- event-blink-delay: Blink delay of the event led
++- gpios: GPIO on which an event is detected
++- vsense-name: Name of the analog input for vsense
++- vsense-scale: Vsense scale to convert to mVolts
++- ti-tscadc-dt compatible node for the ADC configuration
++- gpio-leds compatible node for the LED configuration
++
++Optional properties:
++
++The geiger cape supports the standard pinctrl properties.
++
++Example:
++
++bone_geiger_cape: cape@1 {
++	compatible = "bone-geiger-cape";
++	board-name = "Geiger Cape";
++
++	/* note that these can't be versioned... */
++	pinctrl-names = "default";
++	pinctrl-0 = <&bone_geiger_cape_pins>;
++
++	pwms = <&ehrpwm1 0 500000 0>;
++	pwm-names = "bone-geiger-cape";
++
++	pwm-frequency  = <20000>;	/* 20KHz */
++	pwm-duty-cycle = <60>;		/* 60% */
++
++	event-blink-delay = <30>;	/* 30ms */
++
++	gpios = <&gpio4 17 0>;		/* pulse */
++
++	vsense-name = "AIN5";		/* analog vsense */
++	vsense-scale = <37325>;		/* scaling */
++
++	tscadc {
++		compatible = "ti-tscadc-dt";
++
++		ti,hwmods = "adc_tsc";
++
++		adc-channels = <8>;
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&bone_geiger_cape_led_pins>;
++
++		geiger-led0 {
++			label = "geiger:green:usr0";
++			gpios = <&gpio3 23 0>;
++			linux,default-trigger = "geiger-run";
++			default-state = "off";
++		};
++
++		geiger-led1 {
++			label = "geiger:red:usr1";
++			gpios = <&gpio3 25 0>;
++			linux,default-trigger = "geiger-event";
++			default-state = "off";
++		};
++	};
++};
+diff --git a/Documentation/devicetree/bindings/capebus/bone-generic-cape.txt b/Documentation/devicetree/bindings/capebus/bone-generic-cape.txt
+new file mode 100644
+index 0000000..71ad2f4
+--- /dev/null
++++ b/Documentation/devicetree/bindings/capebus/bone-generic-cape.txt
+@@ -0,0 +1,97 @@
++* Beagle bone generic cape
++
++  A generic cape is one form of cape that doesn't require any per-cape
++  driver for it to function. It is enough for the cape's node to be
++  instantiated in the right manner and the functions that the cape provides
++  will be available to Linux. A large number of capes fall in this category
++  like LCD/DVI/VGA capes, audio capes, capes with a number of gpio buttons,
++  capes with standard I2C/SPI/W1 parts etc.
++  All that's required is to describe the parts of the cape in the DT and 
++  how they utilize the SoC peripherals and it will work, without having
++  to write any other driver, or modify the board support package.
++
++  As a sidenote, a large part of the complexity of capes have to do
++  with version management. A cape as it goes through various steps of evolution
++  changes. These changes are codified by the version field on the EEPROM.
++  It is important that version management can be kept as simple as possible.
++
++  The generic concept works by instantiating the child nodes that are
++  contained in the cape node. By default nodes that are present in the
++  root of the node are activated for any version. Version nodes can 
++  contain per-version changes. In the example the da8xx-dt node differs
++  in the way it's instantiated, and this is expressed by the version nodes.
++
++Required properties:
++- compatible: Generic cape nodes must have the form "bone-generic-cape"
++- board-name: The cape's name as if provided by the board-name EEPROM field
++
++Optional properties:
++- version: Only valid in a version node, and it contains the list of compatible
++  versions this node contains.
++
++The standard supported nodes of the generic cape are:
++
++gpio-leds, tps65217-backlight, gpio-keys, w1-gpio, pwm-backlight
++
++The following nodes are supported via a capebus specific bridge devices, and
++their bindings described in their respective files:
++
++ti-tscadc-dt, da8xx-dt, i2c-dt, spi-dt
++
++Example:
++
++bone_dvi_cape: cape@0 {
++
++	compatible = "bone-generic-cape";
++	board-name = "BeagleBone DVI-D CAPE";
++
++	/* hacky, since this is not a proper DT platform device */
++	/* but until we have DT bindings... */
++	version@00A0 {
++		version = "00A0";
++		dvi {
++			compatible = "da8xx-dt";
++			pinctrl-names = "default";
++			pinctrl-0 = <&bone_dvi_cape_dvi_00A0_pins>;
++			ti,hwmods = "lcdc";
++
++			disp-pll = <560000000>;
++			panel-type = "1024x768@60";
++			powerdn-gpio = <&gpio2 7 0>;
++		};
++	};
++
++	version@00A1 {
++		version = "00A1", "01";
++		dvi {
++			compatible = "da8xx-dt";
++			pinctrl-names = "default";
++			pinctrl-0 = <&bone_dvi_cape_dvi_00A1_pins>;
++			ti,hwmods = "lcdc";
++
++			disp-pll = <560000000>;
++			panel-type = "1024x768@60";
++			powerdn-gpio = <&gpio2 31 0>;
++		};
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&bone_dvi_cape_led_pins>;
++
++		dvi-led0 {
++			label = "dvi:green:usr0";
++			gpios = <&gpio2 18 0>;
++			linux,default-trigger = "heartbeat";
++			default-state = "off";
++		};
++
++		dvi-led1 {
++			label = "dvi:green:usr1";
++			gpios = <&gpio2 19 0>;
++			linux,default-trigger = "mmc0";
++			default-state = "off";
++		};
++	};
++};
+diff --git a/Documentation/devicetree/bindings/capebus/da8xx-dt.txt b/Documentation/devicetree/bindings/capebus/da8xx-dt.txt
+new file mode 100644
+index 0000000..0b84063
+--- /dev/null
++++ b/Documentation/devicetree/bindings/capebus/da8xx-dt.txt
+@@ -0,0 +1,31 @@
++* DA8XX DT bindins
++
++  This is an adapter device for use in device tree cases, since the
++  drivers DT bindings are not yet ready. It is bound to get away once
++  they are in place. Note that there is no capebus prefix, since there's
++  not really any dependence on capebus; the drivers can be moved out of
++  capebus if need be.
++
++Required properties:
++- compatible: Must have the form "da8xx-dt"
++- ti,hwmods: Must have the form "lcdc" (until hwmod DT is complete)
++- disp-pll: PLL value
++- panel-type: Name of the panel type connected
++
++Optional properties:
++powerdn-gpio: GPIO controlling power
++
++Note that the pinctrl bindings are supported.
++
++Example:
++
++dvi {
++	compatible = "da8xx-dt";
++	pinctrl-names = "default";
++	pinctrl-0 = <&bone_dvi_cape_dvi_00A0_pins>;
++	ti,hwmods = "lcdc";
++
++	disp-pll = <560000000>;
++	panel-type = "1024x768@60";
++	powerdn-gpio = <&gpio2 7 0>;
++};
+diff --git a/Documentation/devicetree/bindings/capebus/i2c-dt.txt b/Documentation/devicetree/bindings/capebus/i2c-dt.txt
+new file mode 100644
+index 0000000..79a042a
+--- /dev/null
++++ b/Documentation/devicetree/bindings/capebus/i2c-dt.txt
+@@ -0,0 +1,42 @@
++* I2C DT bindings
++
++  This is an adapter device for use in device tree cases.
++  What we want to do is to add a number of I2C devices connected
++  to a specified i2c adapter node, and instantiate them on
++  successful cape match. Not only that, normally I2C adapters
++  are disabled in the DT tree, so in that case we enable them
++  first and then go about our business.
++
++Required properties:
++- compatible: Must have the form "i2c-dt"
++- parent: The phandle of the i2c adapter node
++- #address-cells: The same as the parent i2c adapter node
++- #size-cells: The same as the parent i2c adapter node
++
++Example:
++
++i2c2-devices {
++	compatible = "i2c-dt";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	parent = <&i2c2>;
++
++	/* Ambient light sensor */
++	tsl2550@39 {
++		compatible = "tsl,tsl2550";
++		reg = <0x39>;
++	};
++
++	/* Humidity Sensor */
++	sht21@40 {
++		compatible = "sensiron,sht21";
++		reg = <0x40>;
++	};
++
++	/* Barometric pressure sensor */
++	bmp085@77 {
++		compatible = "bosch,bmp085";
++		reg = <0x77>;
++	};
++};
+diff --git a/Documentation/devicetree/bindings/capebus/spi-dt.txt b/Documentation/devicetree/bindings/capebus/spi-dt.txt
+new file mode 100644
+index 0000000..fd70fc4
+--- /dev/null
++++ b/Documentation/devicetree/bindings/capebus/spi-dt.txt
+@@ -0,0 +1,37 @@
++* SPI DT bindings
++
++  This is an adapter device for use in device tree cases.
++  What we want to do is to add a number of SPI devices connected
++  to a specified spi node, and instantiate them on
++  successful cape match. Not only that, normally SPI nodes
++  are disabled in the DT tree, so in that case we enable them
++  first and then go about our business.
++
++Required properties:
++- compatible: Must have the form "spi-dt"
++- parent: The phandle of the spi node
++- #address-cells: The same as the parent spi node
++- #size-cells: The same as the parent spi node
++
++Example:
++
++spi1-devices {
++	compatible = "spi-dt";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	parent = <&spi1>;
++
++	lcd@0 {
++		compatible = "adafruit,tft-lcd-1.8-red", "sitronix,st7735";
++		spi-max-frequency = <8000000>;
++		reg = <0>;
++		spi-cpol;
++		spi-cpha;
++		pinctrl-names = "default";
++		pinctrl-0 = <&lcd_pins>;
++		st7735-rst = <&gpio4 19 0>;
++		st7735-dc = <&gpio4 21 0>;
++	};
++
++};
+diff --git a/Documentation/devicetree/bindings/capebus/ti-tscadc-dt.txt b/Documentation/devicetree/bindings/capebus/ti-tscadc-dt.txt
+new file mode 100644
+index 0000000..44ad4f2
+--- /dev/null
++++ b/Documentation/devicetree/bindings/capebus/ti-tscadc-dt.txt
+@@ -0,0 +1,34 @@
++* TI's TSCADC Device Tree adapter
++
++  This is an adapter device for use in device tree cases, since the
++  drivers DT bindings are not yet ready. It is bound to get away once
++  they are in place. Note that there is no capebus prefix, since there's
++  not really any dependence on capebus; the drivers can be moved out of
++  capebus if need be.
++
++Required properties:
++- compatible: Must have the form "ti-tscadc-dt"
++- ti,hwmods: Must have the form "adc_tsc" (until hwmod DT is complete)
++
++Optional properties:
++- adc-channels: Number of ADC channels the driver should provide.
++- tsc-wires: Number of touchscreen wires
++- tsc-x-plate-resistance: Touchscreen X plate resistance value
++- tsc-steps: Touchscreen steps
++
++Note if either adc-channels or tsc-wires are missing their respective
++values are set to 0.
++
++Example:
++
++tscadc {
++	compatible = "ti-tscadc-dt";
++
++	ti,hwmods = "adc_tsc";
++
++	tsc-wires = <4>;
++	tsc-x-plate-resistance = <200>;
++	tsc-steps = <6>;
++
++	adc-channels = <4>;
++};
diff --git a/patches/linux-3.7/0160-capebus-Documentation-capebus-summary.patch b/patches/linux-3.7/0160-capebus-Documentation-capebus-summary.patch
new file mode 100644
index 0000000..e8cc83a
--- /dev/null
+++ b/patches/linux-3.7/0160-capebus-Documentation-capebus-summary.patch
@@ -0,0 +1,58 @@
+From: Pantelis Antoniou <panto@antoniou-consulting.com>
+Date: Wed, 31 Oct 2012 16:49:14 +0200
+Subject: [PATCH] capebus: Documentation; capebus-summary
+
+Small summary of capebus.
+
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
+---
+ Documentation/capebus/capebus-summary |   40 +++++++++++++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+ create mode 100644 Documentation/capebus/capebus-summary
+
+diff --git a/Documentation/capebus/capebus-summary b/Documentation/capebus/capebus-summary
+new file mode 100644
+index 0000000..742e33c
+--- /dev/null
++++ b/Documentation/capebus/capebus-summary
+@@ -0,0 +1,40 @@
++Overview of Linux kernel Capebus support
++========================================
++
++30-Oct-2012
++
++What is Capebus?
++----------------
++Capebus is an abstract concept. There's no such thing as a vanilla physical
++capebus, what is there is a concept and a method on how various capebus
++based implementations can be made.
++
++Capebus is created to address the problem of many SoCs that can provide a
++multitude of hardware interfaces but in order to keep costs down the main
++boards only support a limited number of them. The rest are typically brought
++out to pin connectors on to which other boards, named capes are connected and
++allow those peripherals to be used.
++
++These capes connect to the SoC interfaces but might also contain various other
++parts that may need some kind of driver to work.
++
++Since SoCs have limited pins and pin muxing options, not all capes can work
++together so some kind of resource tracking (at least for the pins in use) is
++required.
++
++Before capebus all of this took place in the board support file, and frankly
++for boards with too many capes it was becoming unmanageable.
++
++Capebus provides a virtual bus, which along with a board specific controller,
++cape drivers can be written using the standard Linux device model.
++
++What kind of systems/boards capebus supports?
++---------------------------------------------
++
++The core capebus infrastructure is not depended on any specific board.
++However capebus needs a board controller to provide services to the cape devices
++it controls. Services like addressing and resource reservation are provided
++by the board controller.
++
++Capebus at the moment only support TI's Beaglebone platform.
++
diff --git a/patches/linux-3.7-rc6/0138-beaglebone-Update-default-config-for-capebus.patch b/patches/linux-3.7/0161-beaglebone-Update-default-config-for-capebus.patch
index 49a5602..a48595a 100644
--- a/patches/linux-3.7-rc6/0138-beaglebone-Update-default-config-for-capebus.patch
+++ b/patches/linux-3.7/0161-beaglebone-Update-default-config-for-capebus.patch
@@ -1,8 +1,8 @@
-From 116c5c49c91c1638620714ddfb74eb21b79505c3 Mon Sep 17 00:00:00 2001
 From: Pantelis Antoniou <panto@antoniou-consulting.com>
 Date: Tue, 30 Oct 2012 21:17:39 +0200
 Subject: [PATCH] beaglebone: Update default config for capebus
 
+Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
 ---
  defconfig | 3893 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
  1 file changed, 3893 insertions(+)
diff --git a/patches/linux-3.7-rc6/0139-capebus-Geiger-Cape-config-bugfixs.patch b/patches/linux-3.7/0162-capebus-Geiger-Cape-config-bugfixs.patch
index 3af0453..1fc46b7 100644
--- a/patches/linux-3.7-rc6/0139-capebus-Geiger-Cape-config-bugfixs.patch
+++ b/patches/linux-3.7/0162-capebus-Geiger-Cape-config-bugfixs.patch
@@ -1,4 +1,3 @@
-From 441e11b11ca8dcca74fb85715a204a52899feb49 Mon Sep 17 00:00:00 2001
 From: Matt Ranostay <mranostay@gmail.com>
 Date: Sun, 18 Nov 2012 23:26:20 +0000
 Subject: [PATCH] capebus: Geiger Cape config bugfixs
@@ -11,10 +10,10 @@ Signed-off-by: Matt Ranostay <mranostay@gmail.com>
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/capebus/capes/bone-geiger-cape.c b/drivers/capebus/capes/bone-geiger-cape.c
-index 880eaae..9e53d8d 100644
+index 9b3a83d..d972622 100644
 --- a/drivers/capebus/capes/bone-geiger-cape.c
 +++ b/drivers/capebus/capes/bone-geiger-cape.c
-@@ -417,8 +417,8 @@ static int bonegeiger_probe(struct cape_dev *dev, const struct cape_device_id *i
+@@ -428,8 +428,8 @@ static int bonegeiger_probe(struct cape_dev *dev, const struct cape_device_id *i
  				"vsense-name", &info->vsense_name) != 0) {
  		info->vsense_name = "AIN5";
  		dev_warn(&dev->dev, "Could not read vsense-name property; "
diff --git a/patches/linux-3.7/0163-am335x-bone-Add-spi0-pins-defines.patch b/patches/linux-3.7/0163-am335x-bone-Add-spi0-pins-defines.patch
new file mode 100644
index 0000000..6e46fc0
--- /dev/null
+++ b/patches/linux-3.7/0163-am335x-bone-Add-spi0-pins-defines.patch
@@ -0,0 +1,43 @@
+From: Matt Ranostay <mranostay@gmail.com>
+Date: Sat, 24 Nov 2012 03:26:03 -0800
+Subject: [PATCH] am335x-bone: Add spi0 pins defines
+
+Sometimes you need use the other SPI bus in the device tree due to
+pin muxing this allows easy references for switching.
+
+Signed-off-by: Matt Ranostay <mranostay@gmail.com>
+---
+ arch/arm/boot/dts/am335x-bone-common.dtsi |   13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
+index 46d5f27..0378046 100644
+--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
++++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
+@@ -24,6 +24,14 @@
+ 	};
+ 
+ 	am3358_pinmux: pinmux@44e10800 {
++		spi0_pins: pinmux_spi0_pins {
++			pinctrl-single,pins = <
++				0x150 0x10      /* spi0_sclk.gpio0_2, OUTPUT_PULLUP | MODE0 */
++				0x154 0x30      /* spi0_d0.gpio0_3, INPUT_PULLUP | MODE0 */
++				0x158 0x10      /* spi0_d1.i2c1_sda, OUTPUT_PULLUP | MODE0 */
++				0x15c 0x10      /* spi0_cs0.i2c1_scl, OUTPUT_PULLUP | MODE0 */
++			>;
++		};
+ 		spi1_pins: pinmux_spi1_pins {
+ 			pinctrl-single,pins = <
+ 				0x190 0x13	/* mcasp0_aclkx.spi1_sclk, OUTPUT_PULLUP | MODE3 */
+@@ -401,6 +409,11 @@
+ 	vmmc-supply = <&ldo3_reg>;
+ };
+ 
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>;
++};
++
+ &spi1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spi1_pins>;
diff --git a/patches/linux-3.7/0164-Allow-more-than-one-instance-of-generic-devices.patch b/patches/linux-3.7/0164-Allow-more-than-one-instance-of-generic-devices.patch
new file mode 100644
index 0000000..d266cec
--- /dev/null
+++ b/patches/linux-3.7/0164-Allow-more-than-one-instance-of-generic-devices.patch
@@ -0,0 +1,64 @@
+From: Pantelis Antoniou <panto@antoniou-consulting.com>
+Date: Fri, 30 Nov 2012 12:23:29 +0200
+Subject: [PATCH] Allow more than one instance of generic devices
+
+Generate unique name to allow more than one instance of devices.
+---
+ drivers/capebus/capebus-driver.c |   19 ++++++++++++++++++-
+ include/linux/capebus.h          |    7 ++++---
+ 2 files changed, 22 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/capebus/capebus-driver.c b/drivers/capebus/capebus-driver.c
+index 82b1d1b..a299c77 100644
+--- a/drivers/capebus/capebus-driver.c
++++ b/drivers/capebus/capebus-driver.c
+@@ -441,13 +441,30 @@ capebus_of_platform_compatible_device_create(struct cape_dev *dev,
+ {
+ 	struct device_node *node;
+ 	struct platform_device *pdev;
++	char *name, *buf;
+ 
+ 	node = capebus_of_compatible_device_property_match(dev, matches, prop,
+ 			prop_value);
+ 	if (node == NULL)
+ 		return ERR_PTR(-ENXIO);
+ 
+-	pdev = of_platform_device_create(node, pdev_name, dev->bus->dev.parent);
++	/* create system-wide unique name */
++	buf = kasprintf(GFP_KERNEL, "%d:%d-%s.%d",
++			dev->bus->busno, dev->slot->slotno,
++			pdev_name, dev->slot->next_pdevid++);
++	if (buf == NULL)
++		return ERR_PTR(-ENOMEM);
++
++	name = devm_kzalloc(&dev->dev, strlen(buf) + 1, GFP_KERNEL);
++	kfree(buf);
++
++	if (name == NULL)
++		return ERR_PTR(-ENOMEM);
++
++	/* safe */
++	strcpy(name, buf);
++
++	pdev = of_platform_device_create(node, name, &dev->dev);
+ 
+ 	/* release the reference to the node */
+ 	of_node_put(node);
+diff --git a/include/linux/capebus.h b/include/linux/capebus.h
+index 7524401..2f8ab7b 100644
+--- a/include/linux/capebus.h
++++ b/include/linux/capebus.h
+@@ -43,9 +43,10 @@ struct cape_slot;
+ 
+ struct cape_slot {
+ 	struct list_head	node;
+-	struct cape_bus 	*bus;	/* the bus this slot is on */
+-	int 			slotno;	/* index of this slot */
+-	struct cape_dev		*dev;	/* the device (if found) */
++	struct cape_bus 	*bus;		/* the bus this slot is on */
++	int 			slotno;		/* index of this slot      */
++	struct cape_dev		*dev;		/* the device (if found)   */
++	unsigned int		next_pdevid;	/* next assigned pdev_id   */
+ };
+ 
+ struct cape_driver {
diff --git a/patches/linux-3.7/0165-Mark-the-device-as-PRIVATE.patch b/patches/linux-3.7/0165-Mark-the-device-as-PRIVATE.patch
new file mode 100644
index 0000000..4a4c293
--- /dev/null
+++ b/patches/linux-3.7/0165-Mark-the-device-as-PRIVATE.patch
@@ -0,0 +1,52 @@
+From: Pantelis Antoniou <panto@antoniou-consulting.com>
+Date: Fri, 30 Nov 2012 12:23:31 +0200
+Subject: [PATCH] Mark the device as PRIVATE
+
+Turns out if you enable CONFIG_NET_DMA the ip stack will try
+to grab all the available non-private DMA channels sometime late in the
+boot sequence.
+
+That's bad enough, what is worse is that it brindly iterates over
+any possible channel; if the driver returns ENODEV on any of the
+channels dmaengine will remove the device from the list of available
+dma devices.
+
+Very crazy bug.
+---
+ drivers/dma/edma.c |    8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
+index 47ba7bf..75ab2d5 100644
+--- a/drivers/dma/edma.c
++++ b/drivers/dma/edma.c
+@@ -394,8 +394,11 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
+ 	a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
+ 					chan, EVENTQ_DEFAULT);
+ 
++	/* NOTE: DO NOT RETURN ENODEV */
++	/* It causes dmaengine to remove the device from it's list */
++
+ 	if (a_ch_num < 0) {
+-		ret = -ENODEV;
++		ret = -EINVAL;
+ 		goto err_no_chan;
+ 	}
+ 
+@@ -403,7 +406,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
+ 		dev_err(dev, "failed to allocate requested channel %u:%u\n",
+ 			EDMA_CTLR(echan->ch_num),
+ 			EDMA_CHAN_SLOT(echan->ch_num));
+-		ret = -ENODEV;
++		ret = -EINVAL;
+ 		goto err_wrong_chan;
+ 	}
+ 
+@@ -564,6 +567,7 @@ static int __devinit edma_probe(struct platform_device *pdev)
+ 
+ 	dma_cap_zero(ecc->dma_slave.cap_mask);
+ 	dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
++	dma_cap_set(DMA_PRIVATE, ecc->dma_slave.cap_mask);
+ 
+ 	edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
+ 
diff --git a/patches/linux-3.7/0166-DT-overlay.patch b/patches/linux-3.7/0166-DT-overlay.patch
new file mode 100644
index 0000000..f41f1b8
--- /dev/null
+++ b/patches/linux-3.7/0166-DT-overlay.patch
@@ -0,0 +1,448 @@
+From: Pantelis Antoniou <panto@antoniou-consulting.com>
+Date: Fri, 30 Nov 2012 12:23:32 +0200
+Subject: [PATCH] DT overlay
+
+For things like uarts and mmc hosts you need to overlay DT.
+---
+ drivers/capebus/boards/capebus-bone-generic.c |    6 +
+ drivers/capebus/boards/capebus-bone-pdevs.c   |  389 +++++++++++++++++++++++++
+ 2 files changed, 395 insertions(+)
+
+diff --git a/drivers/capebus/boards/capebus-bone-generic.c b/drivers/capebus/boards/capebus-bone-generic.c
+index b1b79eb..8c2c6cc 100644
+--- a/drivers/capebus/boards/capebus-bone-generic.c
++++ b/drivers/capebus/boards/capebus-bone-generic.c
+@@ -141,6 +141,12 @@ static const struct bone_capebus_generic_device_data gendevs[] = {
+ 				{ .compatible = "spi-dt", }, { },
+ 			},
+ 		.units	 = 0,	/* no limit */
++	}, {
++		.name	= "dt-overlay",
++		.of_match = (const struct of_device_id []) {
++				{ .compatible = "dt-overlay", }, { },
++			},
++		.units	 = 0,	/* no limit */
+ 	}
+ };
+ 
+diff --git a/drivers/capebus/boards/capebus-bone-pdevs.c b/drivers/capebus/boards/capebus-bone-pdevs.c
+index f32134a..f97100b 100644
+--- a/drivers/capebus/boards/capebus-bone-pdevs.c
++++ b/drivers/capebus/boards/capebus-bone-pdevs.c
+@@ -22,6 +22,7 @@
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+ #include <linux/string.h>
++#include <linux/ctype.h>
+ #include <linux/timer.h>
+ #include <linux/errno.h>
+ #include <linux/init.h>
+@@ -38,6 +39,7 @@
+ #include <linux/clk.h>
+ #include <asm/barrier.h>
+ #include <linux/i2c.h>
++#include <linux/of.h>
+ #include <linux/of_i2c.h>
+ #include <linux/spi/spi.h>
+ 
+@@ -246,6 +248,390 @@ static struct platform_driver spi_dt_driver = {
+ 	},
+ };
+ 
++/*******************************************************************/
++
++static int of_is_printable_string(const void *data, int len)
++{
++	const char *s = data;
++	const char *ss, *se;
++
++	/* zero length is not */
++	if (len == 0)
++		return 0;
++
++	/* must terminate with zero */
++	if (s[len - 1] != '\0')
++		return 0;
++
++	se = s + len;
++
++	while (s < se) {
++		ss = s;
++		while (s < se && *s && isprint(*s))
++			s++;
++
++		/* not zero, or not done yet */
++		if (*s != '\0' || s == ss)
++			return 0;
++
++		s++;
++	}
++
++	return 1;
++}
++
++static char *of_dump_prop(struct property *prop)
++{
++	const void *data = prop->value;
++	int len = prop->length;
++	int i, tbuflen;
++	const char *p = data;
++	const char *s;
++	char *buf, *bufp, *bufe;
++
++	/* play it safe */
++	buf = kmalloc(PAGE_SIZE + len * 8, GFP_KERNEL);
++	if (buf == NULL)
++		return NULL;
++	bufp = buf;
++	bufe = buf + PAGE_SIZE + len * 8;
++
++#undef append_sprintf
++#define append_sprintf(format, ...) \
++	do { \
++		tbuflen = snprintf(NULL, 0, format, ## __VA_ARGS__); \
++		if (bufp + tbuflen + 1 >= bufe) \
++			goto err_out; \
++		snprintf(bufp, tbuflen + 1, format, ## __VA_ARGS__); \
++		bufp += tbuflen; \
++	} while(0)
++
++	if (len == 0) {
++		/* nothing; just terminate */
++		*buf = '\0';
++		return buf;
++	}
++
++	append_sprintf(" = ");
++
++	if (of_is_printable_string(data, len)) {
++		s = data;
++		do {
++			append_sprintf("\"%s\"", s);
++			s += strlen(s) + 1;
++			if (s < (const char *)data + len)
++				append_sprintf(", ");
++		} while (s < (const char *)data + len);
++
++	} else if ((len % 4) == 0) {
++		append_sprintf("<");
++		for (i = 0; i < len; i += 4)
++			append_sprintf("0x%08x%s",
++				be32_to_cpu(*(uint32_t *)(p + i)),
++				i < (len - 4) ? " " : "");
++		append_sprintf(">");
++	} else {
++		append_sprintf("[");
++		for (i = 0; i < len; i++)
++			append_sprintf("%02x%s", *(p + i),
++					i < len - 1 ? " " : "");
++		append_sprintf("]");
++	}
++
++	return buf;
++err_out:
++	kfree(buf);
++	return NULL;
++#undef append_sprintf
++}
++
++static void of_dump_tree(struct device *dev, int level,
++		struct device_node *node)
++{
++	struct device_node *child;
++	struct property *prop;
++	static const char *leveltab = "\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t";
++	int maxlevel = strlen(leveltab);
++	const char *thislevel;
++	const char *nextlevel;
++	char *propstr;
++
++	thislevel = leveltab + maxlevel - level;
++	if (thislevel < leveltab)
++		thislevel = leveltab;
++	nextlevel = thislevel - 1;
++	if (nextlevel < leveltab)
++		nextlevel = leveltab;
++
++	dev_info(dev, "%s%s {\n", thislevel, node->name);
++
++	for_each_property_of_node(node, prop) {
++
++		if (strcmp(prop->name, "name") == 0)
++			continue;
++
++		propstr = of_dump_prop(prop);
++		dev_info(dev, "%s%s%s;\n", nextlevel, prop->name,
++				propstr ? propstr : "*ERROR*");
++		kfree(propstr);
++	}
++
++	for_each_child_of_node(node, child)
++		of_dump_tree(dev, level + 1, child);
++
++	dev_info(dev, "%s};", thislevel);
++}
++
++struct dt_fragment {
++	struct list_head node;
++	struct device_node *target_node;
++	int status_changed : 1;
++	int status_new : 1;
++
++	struct device_node *saved_tree;
++};
++
++struct dt_overlay_priv {
++	struct list_head frag_list;
++};
++
++static const struct of_device_id of_dt_overlay_match[] = {
++	{ .compatible = "dt-overlay", },
++	{},
++};
++
++#define for_each_property_of_node_safe(dn, pp, ppn) \
++	for (pp = dn->properties, ppn = pp ? pp->next : NULL; pp != NULL; pp = ppn, ppn = pp->next)
++
++static void of_overlay_node(struct device *dev, struct device_node *target, struct device_node *overlay)
++{
++	struct device_node *child;
++	struct device_node **childp;
++	struct property *prop, *propn;
++	struct property **propp;
++	char *propstr;
++	int found;
++
++	dev_info(dev, "Overlaying target %p with overlay %p\n", target, overlay);
++
++	while ((prop = overlay->properties) != NULL) {
++		/* remove head prop */
++		overlay->properties = prop->next;
++		prop->next = NULL;
++
++		found = 0;
++		propp = &target->properties;
++		while (*propp) {
++
++			/* found? */
++			if (of_prop_cmp((*propp)->name, prop->name) == 0) {
++				found = 1;
++				break;
++			}
++
++			propp = &(*propp)->next;
++		}
++
++		if (found) {
++			propn = (*propp)->next;
++			prop->next = propn;
++			/* propn is now dead */
++
++		}
++
++		*propp = prop;
++
++		propstr = of_dump_prop(prop);
++		dev_info(dev, "%c %s%s;\n", found ? 'U' : 'I', prop->name, propstr);
++		kfree(propstr);
++	}
++
++	/* remove each child */
++	while ((child = overlay->child) != NULL) {
++		overlay->child = child->sibling;
++		child->sibling = NULL;
++
++		found = 0;
++		childp = &target->child;
++		while (*childp) {
++
++			/* found? */
++			if ((*childp)->name && of_node_cmp((*childp)->name, child->name) == 0) {
++				found = 1;
++				break;
++			}
++
++			childp = &(*childp)->sibling;
++		}
++
++		if (found) {
++			dev_info(dev, "overlaying node '%s'\n", child->name);
++			of_overlay_node(dev, (*childp), child);
++		} else {
++			*childp = child;
++			child->parent = target;
++
++			dev_info(dev, "inserted node '%s'\n", child->name);
++		}
++	}
++}
++
++static int __devinit dt_overlay_probe(struct platform_device *pdev)
++{
++	struct dt_overlay_priv *priv = NULL;
++	struct dt_fragment *frag;
++	int ret = -EINVAL;
++	struct device_node *target_node, *node, *tnode;
++	u32 val;
++	int prev_status, new_status;
++	struct platform_device *target_pdev, *parent_pdev;
++	struct list_head *lh, *lhp;
++	unsigned long flags;
++
++	frag = NULL;
++	target_node = NULL;
++	ret = 0;
++
++	if (pdev->dev.of_node == NULL) {
++		dev_err(&pdev->dev, "Only support OF case\n");
++		return -ENOMEM;
++	}
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (priv == NULL) {
++		dev_err(&pdev->dev, "Failed to allocate priv\n");
++		return -ENOMEM;
++	}
++	INIT_LIST_HEAD(&priv->frag_list);
++
++	frag = NULL;
++	target_node = NULL;
++	ret = 0;
++
++	/* iterate over fragment children */
++	for_each_child_of_node(pdev->dev.of_node, node) {
++
++		frag = NULL;
++		target_node = NULL;
++
++		frag = devm_kzalloc(&pdev->dev, sizeof(*frag), GFP_KERNEL);
++		if (frag == NULL) {
++			dev_err(&pdev->dev, "Failed to allocate frag\n");
++			ret = -ENOMEM;
++			goto err_fail;
++		}
++
++		ret = of_property_read_u32(node, "target", &val);
++		if (ret != 0) {
++			dev_err(&pdev->dev, "Failed to find target property\n");
++			goto err_fail;
++		}
++
++		target_node = of_find_node_by_phandle(val);
++		if (target_node == NULL) {
++			dev_err(&pdev->dev, "Failed to find target node\n");
++			ret = -EINVAL;
++			goto err_fail;
++		}
++
++		frag->target_node = target_node;
++
++		prev_status = of_device_is_available(target_node);
++
++		tnode = of_get_child_by_name(node, "content");
++
++		dev_info(&pdev->dev, "overlay %p (before)\n", tnode);
++		of_dump_tree(&pdev->dev, 1, tnode);
++		dev_info(&pdev->dev, "\n");
++
++		dev_info(&pdev->dev, "target %p (before)\n", target_node);
++		of_dump_tree(&pdev->dev, 1, target_node);
++		dev_info(&pdev->dev, "\n");
++
++		write_lock_irqsave(&devtree_lock, flags);
++		of_overlay_node(&pdev->dev, target_node, tnode);
++		write_unlock_irqrestore(&devtree_lock, flags);
++
++		dev_info(&pdev->dev, "target %p (after)\n", target_node);
++		of_dump_tree(&pdev->dev, 1, target_node);
++		dev_info(&pdev->dev, "\n");
++
++		of_node_put(tnode);
++
++		new_status = of_device_is_available(target_node);
++
++		dev_info(&pdev->dev, "target prev %d new %d\n",
++				prev_status, new_status);
++
++		if (prev_status != new_status) {
++
++			if (new_status) {
++				parent_pdev = of_find_device_by_node(target_node->parent);
++
++				target_pdev = of_platform_device_create(target_node, NULL,
++						parent_pdev ? &parent_pdev->dev : NULL);
++				if (target_pdev == NULL) {
++					dev_info(&pdev->dev, "failed to enable platform_device\n");
++					platform_device_put(parent_pdev);
++					goto err_fail;
++				}
++			} else {
++				target_pdev = of_find_device_by_node(target_node);
++				if (target_pdev != NULL) {
++					dev_info(&pdev->dev, "Cannot find platform_device yet\n");
++					ret = -ENODEV;
++					goto err_fail;
++				}
++				platform_device_unregister(target_pdev);
++				platform_device_put(target_pdev);
++			}
++
++			frag->status_changed = 1;
++			frag->status_new = new_status;
++
++		}
++
++		list_add_tail(&frag->node, &priv->frag_list);
++	}
++
++	dev_info(&pdev->dev, "Completed.\n");
++
++	platform_set_drvdata(pdev, priv);
++
++	return 0;
++
++err_fail:
++	of_node_put(target_node);
++	devm_kfree(&pdev->dev, frag);
++
++	/* remove all in reverse */
++	list_for_each_prev_safe(lh, lhp, &priv->frag_list) {
++		frag = list_entry(lh, struct dt_fragment, node);
++		list_del(lh);
++
++		/* TODO: remove overlay */
++
++		of_node_put(frag->target_node);
++		devm_kfree(&pdev->dev, frag);
++	}
++	return ret;
++}
++
++static int __devexit dt_overlay_remove(struct platform_device *pdev)
++{
++	return -EINVAL;	/* not supporting removal yet */
++}
++
++static struct platform_driver dt_overlay_driver = {
++	.probe		= dt_overlay_probe,
++	.remove		= __devexit_p(dt_overlay_remove),
++	.driver		= {
++		.name	= "dt-overlay",
++		.owner	= THIS_MODULE,
++		.of_match_table = of_dt_overlay_match,
++	},
++};
++
+ /*
+  *
+  */
+@@ -263,6 +649,9 @@ static struct bone_capebus_pdev_driver pdev_drivers[] = {
+ 		.driver		= &spi_dt_driver,
+ 	},
+ 	{
++		.driver		= &dt_overlay_driver,
++	},
++	{
+ 		.driver		= NULL,
+ 	}
+ };
diff --git a/patches/linux-3.7/0167-Bug-fixes-pinctl-gpio-reset.patch b/patches/linux-3.7/0167-Bug-fixes-pinctl-gpio-reset.patch
new file mode 100644
index 0000000..826e5a7
--- /dev/null
+++ b/patches/linux-3.7/0167-Bug-fixes-pinctl-gpio-reset.patch
@@ -0,0 +1,138 @@
+From: Pantelis Antoniou <panto@antoniou-consulting.com>
+Date: Fri, 30 Nov 2012 12:23:33 +0200
+Subject: [PATCH] Bug fixes, pinctl & gpio-reset
+
+---
+ arch/arm/plat-omap/include/plat/mmc.h |    3 +++
+ drivers/mmc/host/omap_hsmmc.c         |   41 ++++++++++++++++++++++++++++++++-
+ 2 files changed, 43 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
+index 346af5b..594fc12 100644
+--- a/arch/arm/plat-omap/include/plat/mmc.h
++++ b/arch/arm/plat-omap/include/plat/mmc.h
+@@ -131,6 +131,9 @@ struct omap_mmc_platform_data {
+ 
+ 		int switch_pin;			/* gpio (card detect) */
+ 		int gpio_wp;			/* gpio (write protect) */
++		int gpio_reset;			/* gpio (reset) */
++		int gpio_reset_active_low;	/* 1 if reset is active low */
++		u32 gpio_reset_hold_us;		/* time to hold in us */
+ 
+ 		int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
+ 		int (*set_power)(struct device *dev, int slot,
+diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
+index 7a1283c..8a15610 100644
+--- a/drivers/mmc/host/omap_hsmmc.c
++++ b/drivers/mmc/host/omap_hsmmc.c
+@@ -38,6 +38,8 @@
+ #include <linux/gpio.h>
+ #include <linux/regulator/consumer.h>
+ #include <linux/pm_runtime.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/err.h>
+ #include <mach/hardware.h>
+ #include <plat/mmc.h>
+ #include <plat/cpu.h>
+@@ -383,6 +385,7 @@ static inline int omap_hsmmc_have_reg(void)
+ static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
+ {
+ 	int ret;
++	unsigned long flags;
+ 
+ 	if (gpio_is_valid(pdata->slots[0].switch_pin)) {
+ 		if (pdata->slots[0].cover)
+@@ -412,6 +415,24 @@ static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
+ 	} else
+ 		pdata->slots[0].gpio_wp = -EINVAL;
+ 
++	if (gpio_is_valid(pdata->slots[0].gpio_reset)) {
++		flags = pdata->slots[0].gpio_reset_active_low ?
++				GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
++		ret = gpio_request_one(pdata->slots[0].gpio_reset, flags,
++				"mmc_reset");
++		if (ret)
++			goto err_free_wp;
++
++		/* hold reset */
++		udelay(pdata->slots[0].gpio_reset_hold_us);
++
++		gpio_set_value(pdata->slots[0].gpio_reset,
++				!pdata->slots[0].gpio_reset_active_low);
++
++	} else
++		pdata->slots[0].gpio_reset = -EINVAL;
++
++
+ 	return 0;
+ 
+ err_free_wp:
+@@ -425,6 +446,8 @@ err_free_sp:
+ 
+ static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
+ {
++	if (gpio_is_valid(pdata->slots[0].gpio_reset))
++		gpio_free(pdata->slots[0].gpio_reset);
+ 	if (gpio_is_valid(pdata->slots[0].gpio_wp))
+ 		gpio_free(pdata->slots[0].gpio_wp);
+ 	if (gpio_is_valid(pdata->slots[0].switch_pin))
+@@ -779,7 +802,7 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
+ 	 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
+ 	 * a val of 0x3, rest 0x0.
+ 	 */
+-	if (cmd == host->mrq->stop)
++	if (host->mrq && cmd == host->mrq->stop)
+ 		cmdtype = 0x3;
+ 
+ 	cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
+@@ -821,6 +844,8 @@ static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_req
+ 	int dma_ch;
+ 	unsigned long flags;
+ 
++	BUG_ON(mrq == NULL);
++
+ 	spin_lock_irqsave(&host->irq_lock, flags);
+ 	host->req_in_progress = 0;
+ 	dma_ch = host->dma_ch;
+@@ -1704,6 +1729,7 @@ static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
+ 	struct omap_mmc_platform_data *pdata;
+ 	struct device_node *np = dev->of_node;
+ 	u32 bus_width;
++	enum of_gpio_flags reset_flags;
+ 
+ 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+ 	if (!pdata)
+@@ -1716,6 +1742,14 @@ static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
+ 	pdata->nr_slots = 1;
+ 	pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
+ 	pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
++	reset_flags = 0;
++	pdata->slots[0].gpio_reset = of_get_named_gpio_flags(np,
++			"reset-gpios", 0, &reset_flags);
++	pdata->slots[0].gpio_reset_active_low =
++		(reset_flags & OF_GPIO_ACTIVE_LOW) != 0;
++	pdata->slots[0].gpio_reset_hold_us = 100;	/* default */
++	of_property_read_u32(np, "reset-gpio-hold-us",
++			&pdata->slots[0].gpio_reset_hold_us);
+ 
+ 	if (of_find_property(np, "ti,non-removable", NULL)) {
+ 		pdata->slots[0].nonremovable = true;
+@@ -1753,6 +1787,7 @@ static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
+ 	const struct of_device_id *match;
+ 	dma_cap_mask_t mask;
+ 	unsigned tx_req, rx_req;
++	struct pinctrl *pinctrl;
+ 
+ 	match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
+ 	if (match) {
+@@ -1773,6 +1808,10 @@ static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
+ 		return -ENXIO;
+ 	}
+ 
++	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++	if (IS_ERR(pinctrl))
++		dev_warn(&pdev->dev, "unable to select pin group\n");
++
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (res == NULL || irq < 0)
diff --git a/patches/linux-3.7/0168-ARM-HSMMC-fix-error-path-when-no-gpio_reset.patch b/patches/linux-3.7/0168-ARM-HSMMC-fix-error-path-when-no-gpio_reset.patch
new file mode 100644
index 0000000..6ba5f1a
--- /dev/null
+++ b/patches/linux-3.7/0168-ARM-HSMMC-fix-error-path-when-no-gpio_reset.patch
@@ -0,0 +1,35 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Wed, 5 Dec 2012 11:12:21 -0600
+Subject: [PATCH] ARM: HSMMC: fix error path when no gpio_reset
+
+fixes: https://github.com/beagleboard/kernel/issues/12
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ drivers/mmc/host/omap_hsmmc.c |    6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
+index 8a15610..ec73df7 100644
+--- a/drivers/mmc/host/omap_hsmmc.c
++++ b/drivers/mmc/host/omap_hsmmc.c
+@@ -421,7 +421,7 @@ static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
+ 		ret = gpio_request_one(pdata->slots[0].gpio_reset, flags,
+ 				"mmc_reset");
+ 		if (ret)
+-			goto err_free_wp;
++			goto err_free_reset;
+ 
+ 		/* hold reset */
+ 		udelay(pdata->slots[0].gpio_reset_hold_us);
+@@ -442,6 +442,10 @@ err_free_cd:
+ err_free_sp:
+ 		gpio_free(pdata->slots[0].switch_pin);
+ 	return ret;
++err_free_reset:
++	gpio_free(pdata->slots[0].gpio_reset);
++	pdata->slots[0].gpio_reset = -EINVAL;
++	return 0;
+ }
+ 
+ static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
diff --git a/patches/linux-3.7/0169-capebus-Add-PRUSS-DT-bindings.patch b/patches/linux-3.7/0169-capebus-Add-PRUSS-DT-bindings.patch
new file mode 100644
index 0000000..ad6705f
--- /dev/null
+++ b/patches/linux-3.7/0169-capebus-Add-PRUSS-DT-bindings.patch
@@ -0,0 +1,135 @@
+From: Matt Ranostay <mranostay@gmail.com>
+Date: Thu, 6 Dec 2012 20:59:14 -0800
+Subject: [PATCH] capebus: Add PRUSS DT bindings
+
+Allow capebus to enable using the PRU cores
+
+Signed-off-by: Matt Ranostay <mranostay@gmail.com>
+---
+ drivers/capebus/boards/capebus-bone-generic.c |    6 ++
+ drivers/capebus/boards/capebus-bone-pdevs.c   |   88 +++++++++++++++++++++++++
+ 2 files changed, 94 insertions(+)
+
+diff --git a/drivers/capebus/boards/capebus-bone-generic.c b/drivers/capebus/boards/capebus-bone-generic.c
+index 8c2c6cc..af6d4a3 100644
+--- a/drivers/capebus/boards/capebus-bone-generic.c
++++ b/drivers/capebus/boards/capebus-bone-generic.c
+@@ -142,6 +142,12 @@ static const struct bone_capebus_generic_device_data gendevs[] = {
+ 			},
+ 		.units	 = 0,	/* no limit */
+ 	}, {
++		.name	= "pruss-dt",
++		.of_match = (const struct of_device_id []) {
++				{ .compatible = "pruss-dt", }, { },
++			},
++		.units	 = 0,	/* no limit */
++	}, {
+ 		.name	= "dt-overlay",
+ 		.of_match = (const struct of_device_id []) {
+ 				{ .compatible = "dt-overlay", }, { },
+diff --git a/drivers/capebus/boards/capebus-bone-pdevs.c b/drivers/capebus/boards/capebus-bone-pdevs.c
+index f97100b..3eaca93 100644
+--- a/drivers/capebus/boards/capebus-bone-pdevs.c
++++ b/drivers/capebus/boards/capebus-bone-pdevs.c
+@@ -250,6 +250,91 @@ static struct platform_driver spi_dt_driver = {
+ 
+ /*******************************************************************/
+ 
++struct pruss_priv {
++	phandle parent_handle;
++};
++
++static const struct of_device_id of_pruss_dt_match[] = {
++	{ .compatible = "pruss-dt", },
++	{},
++};
++
++static int __devinit pruss_dt_probe(struct platform_device *pdev)
++{
++	struct pruss_priv *priv = NULL;
++	int ret = -EINVAL;
++	struct device_node *master_node;
++	u32 val;
++
++	if (pdev->dev.of_node == NULL) {
++		dev_err(&pdev->dev, "Only support OF case\n");
++		return -ENOMEM;
++	}
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (priv == NULL) {
++		dev_err(&pdev->dev, "Failed to allocate priv\n");
++		return -ENOMEM;
++	}
++
++	ret = of_property_read_u32(pdev->dev.of_node, "parent", &val);
++	if (ret != 0) {
++		dev_err(&pdev->dev, "Failed to find parent property\n");
++		goto err_prop_fail;
++	}
++	priv->parent_handle = val;
++
++	master_node = of_find_node_by_phandle(priv->parent_handle);
++	if (master_node == NULL) {
++		dev_err(&pdev->dev, "Failed to find PRUSS node\n");
++		ret = -EINVAL;
++		goto err_node_fail;
++	}
++
++	ret = capebus_of_platform_device_enable(master_node);
++	if (ret != 0) {
++		dev_info(&pdev->dev, "PRUSS platform device failed to enable\n");
++		goto err_enable_fail;
++	}
++
++	of_node_put(master_node);
++
++	dev_info(&pdev->dev, "Registered bone PRUSS OK.\n");
++
++	platform_set_drvdata(pdev, priv);
++
++	return 0;
++
++err_enable_fail:
++	/* nothing */
++err_node_fail:
++	/* nothing */
++err_prop_fail:
++	devm_kfree(&pdev->dev, priv);
++	return ret;
++}
++
++static int __devexit pruss_dt_remove(struct platform_device *pdev)
++{
++	return -EINVAL;	/* not supporting removal yet */
++}
++
++static struct platform_driver pruss_dt_driver = {
++	.probe		= pruss_dt_probe,
++	.remove		= __devexit_p(pruss_dt_remove),
++	.driver		= {
++		.name	= "pruss-dt",
++		.owner	= THIS_MODULE,
++		.of_match_table = of_pruss_dt_match,
++	},
++};
++
++/*******************************************************************/
++
++
++
++
++
+ static int of_is_printable_string(const void *data, int len)
+ {
+ 	const char *s = data;
+@@ -649,6 +734,9 @@ static struct bone_capebus_pdev_driver pdev_drivers[] = {
+ 		.driver		= &spi_dt_driver,
+ 	},
+ 	{
++		.driver		= &pruss_dt_driver,
++	},
++	{
+ 		.driver		= &dt_overlay_driver,
+ 	},
+ 	{
diff --git a/patches/linux-3.7/0171-Import-working-HDMI-driver-from-3.2-kernel.patch b/patches/linux-3.7/0171-Import-working-HDMI-driver-from-3.2-kernel.patch
new file mode 100644
index 0000000..9bb80a1
--- /dev/null
+++ b/patches/linux-3.7/0171-Import-working-HDMI-driver-from-3.2-kernel.patch
@@ -0,0 +1,72647 @@
+From: Joel A Fernandes <joelagnel@ti.com>
+Date: Tue, 13 Nov 2012 11:41:09 -0500
+Subject: [PATCH] Import working HDMI driver from 3.2 kernel
+
+Fixes ontop of the original driver:
+6a3b828 hdmi: Fix Video port mapping in NXP driver
+ac8ac07 Replace entire code with version recommended by NXP, add late_initcall to tda988x.c
+
+Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
+---
+ drivers/video/nxp/MakeModules                      |   59 +
+ drivers/video/nxp/Makefile                         |  204 +
+ .../nxp/comps/tmbslHdmiTx/inc/tmbslHdmiTx_types.h  | 1804 +++++
+ .../tmbslTDA9989/inc/tmbslHdmiTx_funcMapping.h     |  141 +
+ .../tmbslTDA9989/inc/tmbslTDA9989_Functions.h      | 3060 ++++++++
+ .../nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Edid.c | 1572 ++++
+ .../comps/tmbslTDA9989/src/tmbslTDA9989_Edid_l.h   |   62 +
+ .../nxp/comps/tmbslTDA9989/src/tmbslTDA9989_HDCP.c |  655 ++
+ .../comps/tmbslTDA9989/src/tmbslTDA9989_HDCP_l.h   |   72 +
+ .../comps/tmbslTDA9989/src/tmbslTDA9989_InOut.c    | 5101 +++++++++++++
+ .../comps/tmbslTDA9989/src/tmbslTDA9989_InOut_l.h  |  112 +
+ .../nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Misc.c | 2512 +++++++
+ .../comps/tmbslTDA9989/src/tmbslTDA9989_Misc_l.h   |   62 +
+ .../comps/tmbslTDA9989/src/tmbslTDA9989_State.c    |  240 +
+ .../comps/tmbslTDA9989/src/tmbslTDA9989_State_l.h  |   56 +
+ .../comps/tmbslTDA9989/src/tmbslTDA9989_local.c    |  670 ++
+ .../comps/tmbslTDA9989/src/tmbslTDA9989_local.h    | 2056 ++++++
+ .../tmbslTDA9989/src/tmbslTDA9989_local_otp.h      |   54 +
+ .../nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_IW.h     |  305 +
+ .../nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_Linux.c  |  436 ++
+ .../nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_cfg.h    |  107 +
+ .../docs/02_sw_req_an/tmdlHdmiCEC_API.zip          |  Bin 0 -> 148480 bytes
+ .../docs/14_user_doc/HDMI_CEC_User_Manual.pdf      |  Bin 0 -> 171295 bytes
+ .../video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC.h  |   46 +
+ .../comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Functions.h  | 3166 ++++++++
+ .../nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Types.h  | 1083 +++
+ .../video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC.c  | 7575 ++++++++++++++++++++
+ .../nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.c  |  280 +
+ .../nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.h  |  221 +
+ .../tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c  |  570 ++
+ .../comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_cfg.c  |  624 ++
+ .../video/nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_IW.h |  290 +
+ .../nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_cfg.h      |  298 +
+ .../docs/02_sw_req_an/tmdlHdmiTx_API.zip           |  Bin 0 -> 131083 bytes
+ .../TRANSMITTER_TDA998X_SW_UM_Devlib.pdf           |  Bin 0 -> 610544 bytes
+ .../video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx.h    |   52 +
+ .../comps/tmdlHdmiTx/inc/tmdlHdmiTx_Functions.h    | 1806 +++++
+ .../nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Types.h    | 1066 +++
+ .../video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx.c    | 7166 ++++++++++++++++++
+ .../nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.c    |  342 +
+ .../nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.h    |  702 ++
+ drivers/video/nxp/inc/tmFlags.h                    |  237 +
+ drivers/video/nxp/inc/tmNxCompId.h                 | 1743 +++++
+ drivers/video/nxp/inc/tmNxTypes.h                  |  366 +
+ drivers/video/nxp/linux_hdmi_release_note.txt      |  417 ++
+ drivers/video/nxp/tda998x.c                        | 2307 ++++++
+ drivers/video/nxp/tda998x.h                        |  143 +
+ drivers/video/nxp/tda998x_cec.c                    | 2157 ++++++
+ drivers/video/nxp/tda998x_cec.h                    |  140 +
+ drivers/video/nxp/tda998x_ioctl.h                  | 1123 +++
+ drivers/video/nxp/tda998x_version.h                |   17 +
+ drivers/video/nxp/test/Makefile                    |   28 +
+ drivers/video/nxp/test/demo_tda.c                  |  758 ++
+ 53 files changed, 54063 insertions(+)
+ create mode 100755 drivers/video/nxp/MakeModules
+ create mode 100755 drivers/video/nxp/Makefile
+ create mode 100755 drivers/video/nxp/comps/tmbslHdmiTx/inc/tmbslHdmiTx_types.h
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/inc/tmbslHdmiTx_funcMapping.h
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/inc/tmbslTDA9989_Functions.h
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Edid.c
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Edid_l.h
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_HDCP.c
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_HDCP_l.h
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_InOut.c
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_InOut_l.h
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Misc.c
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Misc_l.h
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_State.c
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_State_l.h
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local.c
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local.h
+ create mode 100755 drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local_otp.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_IW.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_Linux.c
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_cfg.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/docs/02_sw_req_an/tmdlHdmiCEC_API.zip
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/docs/14_user_doc/HDMI_CEC_User_Manual.pdf
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Functions.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Types.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC.c
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.c
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_cfg.c
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_IW.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_cfg.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/docs/02_sw_req_an/tmdlHdmiTx_API.zip
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/docs/14_user_doc/TRANSMITTER_TDA998X_SW_UM_Devlib.pdf
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Functions.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Types.h
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx.c
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.c
+ create mode 100755 drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.h
+ create mode 100755 drivers/video/nxp/inc/tmFlags.h
+ create mode 100755 drivers/video/nxp/inc/tmNxCompId.h
+ create mode 100755 drivers/video/nxp/inc/tmNxTypes.h
+ create mode 100755 drivers/video/nxp/linux_hdmi_release_note.txt
+ create mode 100755 drivers/video/nxp/tda998x.c
+ create mode 100755 drivers/video/nxp/tda998x.h
+ create mode 100755 drivers/video/nxp/tda998x_cec.c
+ create mode 100755 drivers/video/nxp/tda998x_cec.h
+ create mode 100755 drivers/video/nxp/tda998x_ioctl.h
+ create mode 100755 drivers/video/nxp/tda998x_version.h
+ create mode 100755 drivers/video/nxp/test/Makefile
+ create mode 100755 drivers/video/nxp/test/demo_tda.c
+
+diff --git a/drivers/video/nxp/MakeModules b/drivers/video/nxp/MakeModules
+new file mode 100755
+index 0000000..fae8495
+--- /dev/null
++++ b/drivers/video/nxp/MakeModules
+@@ -0,0 +1,59 @@
++PACKAGE_NAME:=hdmi
++
++RULES:=compile
++
++ARCH:=arm
++CROSS_COMPILE:=/home/joel/oe-arm-angstrom-linux-gnueabi-
++VARS:= ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE)
++# VARS:= V=1 ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE)
++
++# module to be put in driver/video/hdmi
++
++LINUX_DIR=/home/joel/work/code/kernel/linux-dvi-audio/git/
++LINUXKERNEL_SRC=$(LINUX_DIR)
++
++all: $(RULES)
++
++compile:
++	@echo "\t-----> $(PACKAGE_NAME):$@"
++#	@rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*
++# 	@mv tda998x_version.h temp && cat temp | awk '$$2~"PATCHLEVEL" {$$3=$$3+1};{print};' >tda998x_version.h && rm temp
++	$(MAKE) -C $(LINUXKERNEL_SRC) M=`pwd` $(VARS) modules
++#	@touch $@
++
++uptx:
++	adb shell hdmi_off
++	adb shell rm hdmitx.ko
++	adb shell rmmod hdmitx
++	adb push hdmitx.ko hdmitx.ko
++	adb shell insmod hdmitx.ko verbose=1
++	adb shell hdmi_on
++
++upcec:
++	adb shell rm hdmicec.ko
++	adb shell rmmod hdmicec
++	adb push hdmicec.ko hdmicec.ko
++	adb shell insmod hdmicec.ko verbose=1 device=4
++
++strip:
++	strip -g -I elf32-little hdmitx.ko -o hdmitx_striped.ko
++	strip -g -I elf32-little hdmicec.ko -o hdmicec_striped.ko
++
++clean:
++	@echo "\t-----> $(PACKAGE_NAME):$@"
++	@rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.* *.symvers *.order
++	@if [ -e comps/tmdlHdmiTx/src ]; then cd comps/tmdlHdmiTx/src && rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*; fi
++	@if [ -e comps/tmdlHdmiTx/cfg/TDA9989 ]; then cd comps/tmdlHdmiTx/cfg/TDA9989 && rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*; fi
++	@if [ -e comps/tmdlHdmiCEC/src ]; then cd comps/tmdlHdmiCEC/src && rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*; fi
++	@if [ -e comps/tmdlHdmiCEC/cfg ]; then cd comps/tmdlHdmiCEC/cfg && rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*; fi
++	@if [ -e comps/tmdlTDA9983/src ]; then cd comps/tmdlTDA9983/src && rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*; fi
++	@if [ -e comps/tmdlTDA9983/cfg ]; then cd comps/tmdlTDA9983/cfg && rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*; fi
++	@if [ -e comps/tmbslTDA9989/src ]; then cd comps/tmbslTDA9989/src && rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*; fi
++	@if [ -e comps/tmbslTDA9984NoHdcp/src ]; then cd comps/tmbslTDA9984NoHdcp/src && rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*; fi
++	@if [ -e comps/tmbslTDA9983/src ]; then cd comps/tmbslTDA9983/src && rm -rf *.o *.ko *.mod.c .*.cmd .tmp_versions *.c.* *.h.*; fi
++
++	@if [ -e .compiled ]; then rm .compiled; fi
++
++# install: .install
++# .install:
++# 	cp ....
+diff --git a/drivers/video/nxp/Makefile b/drivers/video/nxp/Makefile
+new file mode 100755
+index 0000000..f583226
+--- /dev/null
++++ b/drivers/video/nxp/Makefile
+@@ -0,0 +1,204 @@
++
++############### select your chip + platform here ###################
++
++# TDA_TX := TDA19989
++TDA_TX := TDA19988
++# TDA_TX := TDA9984
++# TDA_TX := TDA9983
++# TDA_TX := TDA9981
++
++TDA_PLATFORM := ZOOMII
++# TDA_PLATFORM := OTHERS
++
++############### features on demand #################################
++
++#TDA_HDCP := 0
++TDA_HDCP := TMFL_HDCP_SUPPORT
++TDA_CEC := TDA9950
++
++# add this if INTERRUPT is wired, otherwise polling with timer is used
++#EXTRA_CFLAGS += -DIRQ
++
++# add this to get PC video format
++# EXTRA_CFLAGS += -DFORMAT_PC 
++
++# add this to disable automatic set of input/output video resolution 
++# EXTRA_CFLAGS += -DUSER_SET_INPUT_OUTPUT
++
++####################################################################
++
++EXTRA_CFLAGS += -DFUNC_PTR=" " -DCONST_DAT="const " -DRAM_DAT=" "
++EXTRA_CFLAGS += -DTDA_NAME=$(TDA_TX)
++EXTRA_CFLAGS += -DTMFL_LINUX_OS_KERNEL_DRIVER
++EXTRA_CFLAGS += -DTMFL_NO_RTOS
++# EXTRA_CFLAGS += -DI2C_DBG
++
++ifeq ($(TDA_PLATFORM),ZOOMII)
++EXTRA_CFLAGS += -DTMFL_CFG_ZOOMII
++EXTRA_CFLAGS += -DZOOMII_PATCH
++EXTRA_CFLAGS += -DTWL4030_HACK
++# EXTRA_CFLAGS += -DANDROID_DSS
++EXTRA_CFLAGS += -DGUI_OVER_HDMI
++endif
++
++ifeq ($(TDA_TX),TDA19988)
++EXTRA_CFLAGS += -DTMFL_TDA19988
++TDA_TX       := TDA19989
++endif
++
++ifeq ($(TDA_TX),TDA19989)
++EXTRA_CFLAGS += -DTMFL_TDA19989 -DTMFL_TDA9989
++ifeq ($(TDA_HDCP),TMFL_HDCP_SUPPORT)
++EXTRA_CFLAGS += -D$(TDA_HDCP)
++else
++EXTRA_CFLAGS += -DNO_HDCP
++endif
++endif
++
++ifeq ($(TDA_TX),TDA9984)
++EXTRA_CFLAGS += -DNO_HDCP
++endif
++
++ifeq ($(TDA_TX),TDA9981)
++EXTRA_CFLAGS += -DTMFL_TDA9981_SUPPORT -DTMFL_RX_SENSE_ON
++endif
++
++########## devlib ##################################################
++
++ifeq ($(TDA_TX),TDA19989)
++TXSRC := comps/tmdlHdmiTx/src
++TXCFG := comps/tmdlHdmiTx/cfg/TDA9989
++CECSRC := comps/tmdlHdmiCEC/src
++CECCFG := comps/tmdlHdmiCEC/cfg
++endif
++
++ifeq ($(TDA_TX),TDA9984)
++TXSRC := comps/tmdlHdmiTx/src
++TXCFG := comps/tmdlHdmiTx/cfg/TDA9989
++endif
++
++ifeq ($(TDA_TX),TDA9983)
++TXSRC := comps/tmdlTDA9983/src
++TXCFG := comps/tmdlTDA9983/cfg
++endif
++
++ifeq ($(TDA_TX),TDA9981)
++TXSRC := comps/tmdlTDA9983/src
++TXCFG := comps/tmdlTDA9983/cfg
++endif
++
++########## board service layer #####################################
++
++ifeq ($(TDA_TX),TDA19989)
++BSL := comps/tmbslTDA9989/src
++endif
++
++ifeq ($(TDA_TX),TDA9984)
++BSL := comps/tmbslTDA9984NoHdcp/src
++endif
++
++ifeq ($(TDA_TX),TDA9983)
++BSL := comps/tmbslTDA9983/src
++endif
++
++ifeq ($(TDA_TX),TDA9981)
++BSL := comps/tmbslTDA9983/src
++endif
++
++####################################################################
++
++obj-y += hdmitx.o
++ifeq ($(TDA_CEC),TDA9950)
++obj-m += hdmicec.o
++endif
++
++# Linux module
++hdmitx-objs := tda998x.o
++hdmicec-objs := tda998x_cec.o
++
++# NXP comps
++ifeq ($(TDA_TX),TDA19989)
++hdmitx-objs += $(TXSRC)/tmdlHdmiTx.o
++hdmitx-objs += $(TXSRC)/tmdlHdmiTx_local.o
++hdmitx-objs += $(TXCFG)/tmdlHdmiTx_cfg.o
++hdmitx-objs += $(BSL)/tmbslTDA9989_local.o
++hdmitx-objs += $(BSL)/tmbslTDA9989_InOut.o
++hdmitx-objs += $(BSL)/tmbslTDA9989_HDCP.o
++hdmitx-objs += $(BSL)/tmbslTDA9989_State.o
++hdmitx-objs += $(BSL)/tmbslTDA9989_Misc.o
++hdmitx-objs += $(BSL)/tmbslTDA9989_Edid.o
++hdmicec-objs += $(CECSRC)/tmdlHdmiCEC.o
++hdmicec-objs += $(CECSRC)/tmdlHdmiCEC_local.o
++hdmicec-objs += $(CECCFG)/tmdlHdmiCEC_Linux.o
++endif
++
++ifeq ($(TDA_TX),TDA9984)
++hdmitx-objs += $(TXSRC)/tmdlHdmiTx.o
++hdmitx-objs += $(TXSRC)/tmdlHdmiTx_local.o
++hdmitx-objs += $(TXCFG)/tmdlHdmiTx_Linux.o
++hdmitx-objs += $(BSL)/tmbslTDA9984_local.o 
++hdmitx-objs += $(BSL)/tmbslTDA9984_InOut.o
++hdmitx-objs += $(BSL)/tmbslTDA9984_HDCP.o
++hdmitx-objs += $(BSL)/tmbslTDA9984_State.o
++hdmitx-objs += $(BSL)/tmbslTDA9984_Misc.o
++hdmitx-objs += $(BSL)/tmbslTDA9984_Edid.o
++endif
++
++ifeq ($(TDA_TX),TDA9983)
++hdmitx-objs += $(BSL)/tmbslHdmiTx_2.o
++hdmitx-objs += $(BSL)/tmbslHdmiTx_1.o
++hdmitx-objs += $(BSL)/tmbslHdmiTx_local.o
++hdmitx-objs += $(TXSRC)/tmdlHdmiTx.o
++hdmitx-objs += $(TXCFG)/tmdlHdmiTx_Linux.o
++endif
++
++ifeq ($(TDA_TX),TDA9981)
++hdmitx-objs += $(BSL)/tmbslHdmiTx_2.o
++hdmitx-objs += $(BSL)/tmbslHdmiTx_1.o
++hdmitx-objs += $(BSL)/tmbslHdmiTx_local.o
++hdmitx-objs += $(TXSRC)/tmdlHdmiTx.o
++hdmitx-objs += $(TXCFG)/tmdlHdmiTx_Linux.o
++endif
++
++####################################################################
++
++EXTRA_CFLAGS += -I$(obj)
++EXTRA_CFLAGS += -I$(obj)/inc
++
++ifeq ($(TDA_TX),TDA19989)
++EXTRA_CFLAGS += -I$(obj)/comps/tmbslHdmiTx/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlHdmiTx/src
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlHdmiTx/cfg
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlHdmiTx/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmbslTDA9989/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmbslTDA9989/src
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlHdmiCEC/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlHdmiCEC/src
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlHdmiCEC/cfg
++endif
++
++ifeq ($(TDA_TX),TDA9984)
++EXTRA_CFLAGS += -I$(obj)/comps/tmbslHdmiTx/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlHdmiTx/src
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlHdmiTx/cfg
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlHdmiTx/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmbslTDA9984NoHdcp/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmbslTDA9984NoHdcp/src
++endif
++
++ifeq ($(TDA_TX),TDA9983)
++EXTRA_CFLAGS += -I$(obj)/comps/tmbslTDA9983/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlTDA9983/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlTDA9983/src
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlTDA9983/cfg
++endif
++
++ifeq ($(TDA_TX),TDA9981)
++EXTRA_CFLAGS += -I$(obj)/comps/tmbslTDA9983/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlTDA9983/inc
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlTDA9983/src
++EXTRA_CFLAGS += -I$(obj)/comps/tmdlTDA9983/cfg
++endif
++
++
++
+diff --git a/drivers/video/nxp/comps/tmbslHdmiTx/inc/tmbslHdmiTx_types.h b/drivers/video/nxp/comps/tmbslHdmiTx/inc/tmbslHdmiTx_types.h
+new file mode 100755
+index 0000000..6827b24
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslHdmiTx/inc/tmbslHdmiTx_types.h
+@@ -0,0 +1,1804 @@
++/**
++ * Copyright (C) 2007 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslHdmiTx_types.h
++ *
++ * \version       $Revision: 18 $
++ *
++ * \date          $Date: 17/03/08 $
++ *
++ * \brief         HDMI Transmitter common types
++ *
++ * \section refs  Reference Documents
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   $History: tmbslHdmiTx_types.h $
++ *
++ *
++ * **************** Version 18  ******************
++ * User: G.Burnouf     Date: 01/04/08
++ * Updated in $/Source/tmbslHdmiTx/inc
++ * PR1468 : add new function tmbslTDA9984GetSinkCategory
++ * 
++ *
++ * **************** Version 17  ******************
++ * User: G.Burnouf     Date: 17/03/08
++ * Updated in $/Source/tmbslHdmiTx/inc
++ * PR1430 : Increase size of table for 
++ *          Short Audio Descriptor 
++ *
++ * **************** Version 16  ******************
++ * User: G.Burnouf     Date: 06/03/08
++ * Updated in $/Source/tmbslHdmiTx/inc
++ * PR1406 : new reset audio fifo sequence
++ *
++ * **************** Version 15  ******************
++ * User: G.Burnouf     Date: 05/02/08
++ * Updated in $/Source/tmbslHdmiTx/inc
++ * PR1251 : add new type for function 
++ *          tmbslTDA9984EdidGetBasicDisplayParam
++ *
++ ******************  Version 14  ******************
++ * User: G.Burnouf     Date: 14/01/08
++ * Updated in $/Source/tmbslHdmiTx/inc
++ * PR580 - Change BSL error base address
++ *
++ ******************  Version 13  ******************
++ * User: G.Burnouf     Date: 10/01/08
++ * Updated in $/Source/tmbslHdmiTx/inc
++ * PR606 - Apply audio port config in function 
++ *         of audio format
++ *
++ * **************** Version 12  ******************
++ * User: G.Burnouf     Date: 10/12/07   Time: 08:30
++ * Updated in $/Source/tmbslHdmiTx/inc
++ * PR1145 : return DTD and monitor description
++ *
++ * *****************  Version 11  *****************
++ * User: G.Burnouf     Date: 04/12/07
++ * Updated in $/Source/tmbslHdmiTx/inc
++ * PR948 : add new formats, 1080p24/25/30
++ *
++ * *****************  Version 10 *****************
++ * User: C. Diehl	  Date: 27/11/07 
++ * Updated in $/Source/tmbslHdmiTx/inc
++ * PR1030 : - Align with the common interface 
++ *            reworked for the LIPP4200
++ * 
++ * *****************  Version 9  *****************
++ * User: J.Lamotte	  Date: 23/11/07   Time: 09:35
++ * Updated in $/Source/tmbslHdmiTx/src
++ * PR1078 : - update HDMI_TX_SVD_MAX_CNT from 30 
++ *            to 113
++ * 
++ * *****************  Version 8  *****************
++ * User: G.Burnouf	  Date: 13/11/07   Time: 09:29
++ * Updated in $/Source/tmbslHdmiTx/src
++ * PR1008 : - update type tmbslHdmiTxHwFeature_t
++ * 
++ * *****************  Version 7  *****************
++ * User: G.Burnouf	  Date: 16/10/07   Time: 14:32
++ * Updated in $/Source/tmbslHdmiTx/src
++ * PR882 : - add type tmbslHdmiTxPowerState_t
++ *         - add type tmbslHdmiTxPktGmt_t for gamut
++ *         - add new interrupt callback for VS
++ * 
++ * *****************  Version 6  *****************
++ * User: G.Burnouf	  Date: 05/10/07   Time: 14:32
++ * Updated in $/Source/tmbslHdmiTx/src
++ * PR824 : add type for enum _tmbslHdmiTxCallbackInt
++ * 
++ * *****************  Version 5  *****************
++ * User: J.Turpin	  Date: 13/09/07   Time: 14:32
++ * Updated in $/Source/tmbslHdmiTx/src
++ * PR693 : add black pattern functionality
++ *		 - add HDMITX_PATTERN_BLACK in 
++ *			enum tmbslHdmiTxTestPattern_t
++ * 
++ * *****************  Version 4  *****************
++ * User: G.Burnouf   Date: 06/09/07   Time: 17:22
++ * Updated in $/Source/tmbslTDA9984/Inc
++ * PR656 : - add HBR format
++ *         - add format I2s Philips left and right justified 
++ *
++ * *****************  Version 3  *****************
++ * User: G. Burnouf      Date: 07/08/07   Time: 10:30
++ * Updated in $/Source/tmbslTDA9984/Inc
++ * PR572 - change type name of tmbslTDA9984_ to tmbslHdmiTx_
++ *
++ * *****************  Version 2  *****************
++ * User: B.Vereecke      Date: 07/08/07   Time: 10:30
++ * Updated in $/Source/tmbslTDA9984/Inc
++ * PR551 - Add a new Pattern type in tmbslHdmiTxTestPattern_t
++ *			it is used for set the bluescreen
++ *
++ * *****************  Version 1  *****************
++ * User: G. Burnouf    Date: 05/07/07   Time: 17:00
++ * Updated in $/Source/tmbslTDA9984/Inc
++ * PR 414 : Add new edid management
++ *
++   \endverbatim
++ *
++*/
++
++#ifndef TMBSLHDMITX_TYPES_H
++#define TMBSLHDMITX_TYPES_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#include "tmNxCompId.h"
++
++
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       MACRO DEFINITIONS                                    */
++/*============================================================================*/
++
++/**
++ * The maximum number of supported HDMI Transmitter units
++ */
++#define HDMITX_UNITS_MAX       2
++	
++/** \name Errors
++ *  The group of error codes returned by all API and internal functions
++ */
++/*@{*/
++/** The base offset for all error codes.
++ *  This needs defining as non-zero if this component is integrated with others
++ *  and all component error ranges are to be kept separate.
++ */
++#define TMBSL_ERR_HDMI_BASE	CID_BSL_HDMITX
++
++/** Define the OK code if not defined already */
++#ifndef TM_OK
++#define TM_OK   0
++#endif
++
++/** SW interface compatibility error */
++#define TMBSL_ERR_HDMI_COMPATIBILITY            (TMBSL_ERR_HDMI_BASE + 0x001U)
++
++/** SW major version error */
++#define TMBSL_ERR_HDMI_MAJOR_VERSION            (TMBSL_ERR_HDMI_BASE + 0x002U)
++
++/** SW component version error */
++#define TMBSL_ERR_HDMI_COMP_VERSION             (TMBSL_ERR_HDMI_BASE + 0x003U)
++
++/** Invalid device unit number */
++#define TMBSL_ERR_HDMI_BAD_UNIT_NUMBER          (TMBSL_ERR_HDMI_BASE + 0x005U)
++
++/** Invalid input parameter other than unit number */
++#define TMBSL_ERR_HDMI_BAD_PARAMETER            (TMBSL_ERR_HDMI_BASE + 0x009U)
++
++/* Ressource not available */
++#define TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE   (TMBSL_ERR_HDMI_BASE + 0x00CU)
++
++/** Inconsistent input parameters */
++#define TMBSL_ERR_HDMI_INCONSISTENT_PARAMS      (TMBSL_ERR_HDMI_BASE + 0x010U)
++
++/** Component is not initialized */
++#define TMBSL_ERR_HDMI_NOT_INITIALIZED          (TMBSL_ERR_HDMI_BASE + 0x011U)
++
++/** Command not supported for current device */
++#define TMBSL_ERR_HDMI_NOT_SUPPORTED            (TMBSL_ERR_HDMI_BASE + 0x013U)
++
++/** Initialization failed */
++#define TMBSL_ERR_HDMI_INIT_FAILED              (TMBSL_ERR_HDMI_BASE + 0x014U)
++
++/** Component is busy and cannot do a new operation */
++#define TMBSL_ERR_HDMI_BUSY                     (TMBSL_ERR_HDMI_BASE + 0x015U)
++
++/** I2C read error */
++#define TMBSL_ERR_HDMI_I2C_READ                 (TMBSL_ERR_HDMI_BASE + 0x017U)
++
++/** I2C write error */
++#define TMBSL_ERR_HDMI_I2C_WRITE                (TMBSL_ERR_HDMI_BASE + 0x018U)
++
++/** Assertion failure */
++#define TMBSL_ERR_HDMI_ASSERTION                (TMBSL_ERR_HDMI_BASE + 0x049U)
++
++/** Bad EDID block checksum */
++#define TMBSL_ERR_HDMI_INVALID_STATE            (TMBSL_ERR_HDMI_BASE + 0x066U)
++#define TMBSL_ERR_HDMI_INVALID_CHECKSUM         TMBSL_ERR_HDMI_INVALID_STATE
++
++/** No connection to HPD pin */
++#define TMBSL_ERR_HDMI_NULL_CONNECTION          (TMBSL_ERR_HDMI_BASE + 0x067U)
++
++/** Not allowed in DVI mode */
++#define TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED  (TMBSL_ERR_HDMI_BASE + 0x068U)
++
++/** Maximum error code defined */
++#define TMBSL_ERR_HDMI_MAX              TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED
++
++/*============================================================================*/
++
++#define HDMITX_ENABLE_VP_TABLE_LEN	3
++#define HDMITX_GROUND_VP_TABLE_LEN	3
++
++/** EDID block size */
++#define EDID_BLOCK_SIZE		    128
++
++/** size descriptor block of monitor descriptor */
++#define EDID_MONITOR_DESCRIPTOR_SIZE   13
++
++/*@}*/
++
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++/**
++* \brief TX IP/IC versions
++*/
++typedef enum
++{
++     BSLHDMITX_UNKNOWN = 0x00, /**< IC/IP is not recognized */
++     BSLHDMITX_TDA9984,        /**< IC is a TDA9984         */
++     BSLHDMITX_TDA9989,        /**< IC is a TDA9989 (TDA9989N2 64 balls)         */
++     BSLHDMITX_TDA9981,        /**< IC is a TDA9981         */
++     BSLHDMITX_TDA9983,        /**< IC is a TDA9983         */
++     BSLHDMITX_TDA19989,       /**< IC is a TDA19989        */
++     BSLHDMITX_TDA19988,       /**< ok, u got it, it's a 19988 :p  */
++} tmbslHdmiTxVersion_t;
++
++
++/**
++ * \brief System function pointer type, to call user I2C read/write functions
++ * \param slaveAddr     The I2C slave address
++ * \param firstRegister The first device register address to read or write 
++ * \param lenData       Length of data to read or write (i.e. no. of registers)
++ * \param pData         Pointer to data to write, or to buffer to receive data
++ * \return              The call result:
++ *                      - TM_OK: the call was successful
++ *                      - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing
++ *                      - TMBSL_ERR_HDMI_I2C_READ:  failed when reading
++ */
++typedef struct _tmbslHdmiTxSysArgs_t
++{
++    UInt8 slaveAddr;
++    UInt8 firstRegister;
++    UInt8 lenData;
++    UInt8 *pData;
++} tmbslHdmiTxSysArgs_t;
++typedef tmErrorCode_t (FUNC_PTR * ptmbslHdmiTxSysFunc_t)
++                                 (tmbslHdmiTxSysArgs_t *pSysArgs);
++
++/**
++ * \brief System function pointer type, to call user I2C EDID read function
++ * \param segPtrAddr    The EDID segment pointer address 0 to 7Fh
++ * \param segPtr        The EDID segment pointer 0 to 7Fh
++ * \param dataRegAddr   The EDID data register address 0 to 7Fh
++ * \param wordOffset    The first word offset 0 to FFh to read
++ * \param lenData       Length of data to read (i.e. number of registers),
++                        1 to max starting at wordOffset
++ * \param pData         Pointer to buffer to receive lenData data bytes
++ * \return              The call result:
++ *                      - TM_OK: the call was successful
++ *                      - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing
++ *                      - TMBSL_ERR_HDMI_I2C_READ:  failed when reading
++ */
++typedef struct _tmbslHdmiTxSysArgsEdid_t
++{
++    UInt8 segPtrAddr;
++    UInt8 segPtr;
++    UInt8 dataRegAddr;
++    UInt8 wordOffset;
++    UInt8 lenData;
++    UInt8 *pData;
++} tmbslHdmiTxSysArgsEdid_t;
++
++
++/**
++ * \brief EDID function pointer type, to call application EDID read function
++ * \param pSysArgs pointer to the structure containing necessary information to read EDID
++ */
++typedef tmErrorCode_t (FUNC_PTR * ptmbslHdmiTxSysFuncEdid_t)
++                                 (tmbslHdmiTxSysArgsEdid_t *pSysArgs);
++
++/**
++ * \brief Timer function pointer type, to call an application timer
++ * \param ms delay in milliseconds
++ */
++typedef Void (FUNC_PTR * ptmbslHdmiTxSysFuncTimer_t) (UInt16 ms);
++
++/*============================================================================*/
++/**
++ * \brief Callback function pointer type, to call a user interrupt handler
++ * \param txUnit: The transmitter unit that interrupted, 0 to max
++ */
++typedef Void (FUNC_PTR * ptmbslHdmiTxCallback_t) (tmUnitSelect_t txUnit);
++
++/*============================================================================*/
++/**
++ * EIA/CEA-861B video format type
++ */
++typedef enum
++{
++    HDMITX_VFMT_NULL               = 0,     /**< Not a valid format...        */
++    HDMITX_VFMT_NO_CHANGE          = 0,     /**< ...or no change required     */
++    HDMITX_VFMT_TV_MIN             = 1,     /**< Lowest valid TV format       */
++    HDMITX_VFMT_01_640x480p_60Hz   = 1,     /**< Format 01 640  x 480p  60Hz  */
++    HDMITX_VFMT_02_720x480p_60Hz   = 2,     /**< Format 02 720  x 480p  60Hz  */
++    HDMITX_VFMT_03_720x480p_60Hz   = 3,     /**< Format 03 720  x 480p  60Hz  */
++    HDMITX_VFMT_04_1280x720p_60Hz  = 4,     /**< Format 04 1280 x 720p  60Hz  */
++    HDMITX_VFMT_05_1920x1080i_60Hz = 5,     /**< Format 05 1920 x 1080i 60Hz  */
++    HDMITX_VFMT_06_720x480i_60Hz   = 6,     /**< Format 06 720  x 480i  60Hz  */
++    HDMITX_VFMT_07_720x480i_60Hz   = 7,     /**< Format 07 720  x 480i  60Hz  */
++    HDMITX_VFMT_08_720x240p_60Hz   = 8,     /**< Format 08 720  x 240p  60Hz  */
++    HDMITX_VFMT_09_720x240p_60Hz   = 9,     /**< Format 09 720  x 240p  60Hz  */
++    HDMITX_VFMT_10_720x480i_60Hz   = 10,    /**< Format 10 720  x 480i  60Hz  */
++    HDMITX_VFMT_11_720x480i_60Hz   = 11,    /**< Format 11 720  x 480i  60Hz  */
++    HDMITX_VFMT_12_720x240p_60Hz   = 12,    /**< Format 12 720  x 240p  60Hz  */
++    HDMITX_VFMT_13_720x240p_60Hz   = 13,    /**< Format 13 720  x 240p  60Hz  */
++    HDMITX_VFMT_14_1440x480p_60Hz  = 14,    /**< Format 14 1440 x 480p  60Hz  */
++    HDMITX_VFMT_15_1440x480p_60Hz  = 15,    /**< Format 15 1440 x 480p  60Hz  */
++    HDMITX_VFMT_16_1920x1080p_60Hz = 16,    /**< Format 16 1920 x 1080p 60Hz  */
++    HDMITX_VFMT_17_720x576p_50Hz   = 17,    /**< Format 17 720  x 576p  50Hz  */
++    HDMITX_VFMT_18_720x576p_50Hz   = 18,    /**< Format 18 720  x 576p  50Hz  */
++    HDMITX_VFMT_19_1280x720p_50Hz  = 19,    /**< Format 19 1280 x 720p  50Hz  */
++    HDMITX_VFMT_20_1920x1080i_50Hz = 20,    /**< Format 20 1920 x 1080i 50Hz  */
++    HDMITX_VFMT_21_720x576i_50Hz   = 21,    /**< Format 21 720  x 576i  50Hz  */
++    HDMITX_VFMT_22_720x576i_50Hz   = 22,    /**< Format 22 720  x 576i  50Hz  */
++    HDMITX_VFMT_23_720x288p_50Hz   = 23,    /**< Format 23 720  x 288p  50Hz  */
++    HDMITX_VFMT_24_720x288p_50Hz   = 24,    /**< Format 24 720  x 288p  50Hz  */
++    HDMITX_VFMT_25_720x576i_50Hz   = 25,    /**< Format 25 720  x 576i  50Hz  */
++    HDMITX_VFMT_26_720x576i_50Hz   = 26,    /**< Format 26 720  x 576i  50Hz  */
++    HDMITX_VFMT_27_720x288p_50Hz   = 27,    /**< Format 27 720  x 288p  50Hz  */
++    HDMITX_VFMT_28_720x288p_50Hz   = 28,    /**< Format 28 720  x 288p  50Hz  */
++    HDMITX_VFMT_29_1440x576p_50Hz  = 29,    /**< Format 29 1440 x 576p  50Hz  */
++    HDMITX_VFMT_30_1440x576p_50Hz  = 30,    /**< Format 30 1440 x 576p  50Hz  */
++    HDMITX_VFMT_31_1920x1080p_50Hz = 31,    /**< Format 31 1920 x 1080p 50Hz  */
++    HDMITX_VFMT_32_1920x1080p_24Hz = 32,    /**< Format 32 1920 x 1080p 24Hz  */
++
++    HDMITX_VFMT_TV_NO_REG_MIN      = 32,    /**< Lowest TV format without prefetched table */
++
++    HDMITX_VFMT_33_1920x1080p_25Hz = 33,    /**< Format 33 1920 x 1080p 25Hz  */
++    HDMITX_VFMT_34_1920x1080p_30Hz = 34,    /**< Format 34 1920 x 1080p 30Hz  */
++    HDMITX_VFMT_35_2880x480p_60Hz  = 35,   /**< Format 35 2880 x 480p  60Hz 4:3  */
++    HDMITX_VFMT_36_2880x480p_60Hz  = 36,   /**< Format 36 2880 x 480p  60Hz 16:9 */
++    HDMITX_VFMT_37_2880x576p_50Hz  = 37,   /**< Format 37 2880 x 576p  50Hz 4:3  */
++    HDMITX_VFMT_38_2880x576p_50Hz  = 38,   /**< Format 38 2880 x 576p  50Hz 16:9 */
++    
++    HDMITX_VFMT_INDEX_60_1280x720p_24Hz = 39,/**< Index of HDMITX_VFMT_60_1280x720p_24Hz */
++    HDMITX_VFMT_60_1280x720p_24Hz  = 60,   /**< Format 60 1280 x 720p  23.97/24Hz 16:9 */
++    HDMITX_VFMT_61_1280x720p_25Hz  = 61,   /**< Format 61 1280 x 720p  25Hz 16:9 */
++    HDMITX_VFMT_62_1280x720p_30Hz  = 62,   /**< Format 60 1280 x 720p  29.97/30Hz 16:9 */
++
++    HDMITX_VFMT_TV_MAX             = 62,    /**< Highest valid TV format value      */
++    HDMITX_VFMT_TV_NUM             = 42,    /**< Number of TV formats + null, it is also the Index of PC_MIN */
++
++    HDMITX_VFMT_PC_MIN             = 128,   /**< Lowest valid PC format       */
++    HDMITX_VFMT_PC_640x480p_60Hz   = 128,   /**< PC format 128                */
++    HDMITX_VFMT_PC_800x600p_60Hz   = 129,   /**< PC format 129                */
++    HDMITX_VFMT_PC_1152x960p_60Hz  = 130,   /**< PC format 130                */
++    HDMITX_VFMT_PC_1024x768p_60Hz  = 131,   /**< PC format 131                */
++    HDMITX_VFMT_PC_1280x768p_60Hz  = 132,   /**< PC format 132                */
++    HDMITX_VFMT_PC_1280x1024p_60Hz = 133,   /**< PC format 133                */
++    HDMITX_VFMT_PC_1360x768p_60Hz  = 134,   /**< PC format 134                */
++    HDMITX_VFMT_PC_1400x1050p_60Hz = 135,   /**< PC format 135                */
++    HDMITX_VFMT_PC_1600x1200p_60Hz = 136,   /**< PC format 136                */
++    HDMITX_VFMT_PC_1024x768p_70Hz  = 137,   /**< PC format 137                */
++    HDMITX_VFMT_PC_640x480p_72Hz   = 138,   /**< PC format 138                */
++    HDMITX_VFMT_PC_800x600p_72Hz   = 139,   /**< PC format 139                */
++    HDMITX_VFMT_PC_640x480p_75Hz   = 140,   /**< PC format 140                */
++    HDMITX_VFMT_PC_1024x768p_75Hz  = 141,   /**< PC format 141                */
++    HDMITX_VFMT_PC_800x600p_75Hz   = 142,   /**< PC format 142                */
++    HDMITX_VFMT_PC_1024x864p_75Hz  = 143,   /**< PC format 143                */
++    HDMITX_VFMT_PC_1280x1024p_75Hz = 144,   /**< PC format 144                */
++    HDMITX_VFMT_PC_640x350p_85Hz   = 145,   /**< PC format 145                */
++    HDMITX_VFMT_PC_640x400p_85Hz   = 146,   /**< PC format 146                */
++    HDMITX_VFMT_PC_720x400p_85Hz   = 147,   /**< PC format 147                */
++    HDMITX_VFMT_PC_640x480p_85Hz   = 148,   /**< PC format 148                */
++    HDMITX_VFMT_PC_800x600p_85Hz   = 149,   /**< PC format 149                */
++    HDMITX_VFMT_PC_1024x768p_85Hz  = 150,   /**< PC format 150                */
++    HDMITX_VFMT_PC_1152x864p_85Hz  = 151,   /**< PC format 151                */
++    HDMITX_VFMT_PC_1280x960p_85Hz  = 152,   /**< PC format 152                */
++    HDMITX_VFMT_PC_1280x1024p_85Hz = 153,   /**< PC format 153                */
++    HDMITX_VFMT_PC_1024x768i_87Hz  = 154,   /**< PC format 154                */
++    HDMITX_VFMT_PC_MAX             = 154,   /**< Highest valid PC format      */
++    HDMITX_VFMT_PC_NUM     = (1+154-128)    /**< Number of PC formats         */
++} tmbslHdmiTxVidFmt_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984AudioInSetConfig() parameter types
++ */
++/** Audio input formats */
++typedef enum
++{
++    HDMITX_AFMT_SPDIF      = 0,         /**< SPDIF               */
++    HDMITX_AFMT_I2S        = 1,         /**< I2S                 */
++    HDMITX_AFMT_OBA        = 2,         /**< One bit audio / DSD */
++    HDMITX_AFMT_DST        = 3,         /**< DST                 */
++    HDMITX_AFMT_HBR        = 4,         /**< HBR                 */
++    HDMITX_AFMT_NUM        = 5,         /**< Number of Audio input format */
++    HDMITX_AFMT_INVALID    = 5          /**< Invalid format      */
++} tmbslHdmiTxaFmt_t;
++
++/** I2s formats */
++typedef enum
++{
++    HDMITX_I2SFOR_PHILIPS_L   = 0,	/**< Philips like format */
++    HDMITX_I2SFOR_OTH_L       = 2,	/**< Other non Philips left justified */
++    HDMITX_I2SFOR_OTH_R	      = 3,	/**< Other non Philips right justified */
++    HDMITX_I2SFOR_INVALID     = 4	/**< Invalid format*/
++} tmbslHdmiTxI2sFor_t;
++
++/** DSD clock polarities */
++typedef enum
++{
++    HDMITX_CLKPOLDSD_ACLK       = 0,    /**< Same as ACLK */
++    HDMITX_CLKPOLDSD_NACLK      = 1,    /**< Not ACLK, i.e. inverted */
++    HDMITX_CLKPOLDSD_NO_CHANGE  = 2,    /**< No change    */
++    HDMITX_CLKPOLDSD_INVALID    = 3     /**< Invalid      */
++} tmbslHdmiTxClkPolDsd_t;
++
++/** DSD data swap values */
++typedef enum
++{
++    HDMITX_SWAPDSD_OFF          = 0,    /**< No swap   */
++    HDMITX_SWAPDSD_ON           = 1,    /**< Swap      */
++    HDMITX_SWAPDSD_NO_CHANGE    = 2,    /**< No change */
++    HDMITX_SWAPDSD_INVALID      = 3     /**< Invalid   */
++} tmbslHdmiTxSwapDsd_t;
++
++/** DST data transfer rates */
++typedef enum
++{
++    HDMITX_DSTRATE_SINGLE       = 0,    /**< Single transfer rate */
++    HDMITX_DSTRATE_DOUBLE       = 1,    /**< Double data rate */
++    HDMITX_DSTRATE_NO_CHANGE    = 2,    /**< No change */
++    HDMITX_DSTRATE_INVALID      = 3     /**< Invalid   */
++} tmbslHdmiTxDstRate_t;
++
++/** I2S, SPDIF and DSD channel allocation values */
++enum _tmbslHdmiTxChan
++{
++    HDMITX_CHAN_MIN        = 0,
++    HDMITX_CHAN_MAX        = 31,
++    HDMITX_CHAN_NO_CHANGE  = 32,
++    HDMITX_CHAN_INVALID    = 33
++};
++
++/** Audio layout values */
++enum _tmbslHdmiTxLayout
++{
++    HDMITX_LAYOUT_MIN       = 0,
++    HDMITX_LAYOUT_MAX       = 1,
++    HDMITX_LAYOUT_NO_CHANGE = 2,
++    HDMITX_LAYOUT_INVALID   = 3
++};
++
++/** Audio FIFO read latency values */
++enum _tmbslHdmiTxlatency_rd
++{
++    HDMITX_LATENCY_MIN         = 0x000,
++    HDMITX_LATENCY_CURRENT     = 0x080,
++    HDMITX_LATENCY_MAX         = 0x0FF,
++    HDMITX_LATENCY_NO_CHANGE   = 0x100,
++    HDMITX_LATENCY_INVALID     = 0x101
++};
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984AudioInSetCts() parameter types
++ */
++/** Clock Time Stamp reference source */
++typedef enum
++{
++    HDMITX_CTSREF_ACLK      = 0,    /**< Clock input pin for I2S       */
++    HDMITX_CTSREF_MCLK      = 1,    /**< Clock input pin for EXTREF    */
++    HDMITX_CTSREF_FS64SPDIF = 2,    /**< 64xsample rate, for SPDIF     */
++    HDMITX_CTSREF_INVALID   = 3     /**< Invalid value                 */
++} tmbslHdmiTxctsRef_t;
++
++/** Audio sample rate kHz indexes */
++typedef enum
++{
++    HDMITX_AFS_32k           = 0,     /**< 32kHz    */
++    HDMITX_AFS_44_1k         = 1,     /**< 44.1kHz  */
++    HDMITX_AFS_48K           = 2,     /**< 48kHz    */
++    HDMITX_AFS_88_2K         = 3,     /**< 88.2kHz  */
++    HDMITX_AFS_96K           = 4,     /**< 96kHz    */
++    HDMITX_AFS_176_4K        = 5,     /**< 176.4kHz */
++    HDMITX_AFS_192K          = 6,     /**< 192kHz   */
++    HDMITX_AFS_768K          = 7,     /**< 768kHz   */
++    HDMITX_AFS_NOT_INDICATED = 8,     /**< Not Indicated (Channel Status) */
++    HDMITX_AFS_INVALID       = 8,     /**< Invalid  */
++    HDMITX_AFS_NUM           = 8      /**< # rates  */
++} tmbslHdmiTxafs_t;
++
++/** Vertical output frequencies */
++typedef enum
++{
++    HDMITX_VFREQ_24Hz      = 0,     /**< 24Hz          */
++	HDMITX_VFREQ_25Hz      = 1,     /**< 25Hz          */
++	HDMITX_VFREQ_30Hz      = 2,     /**< 30Hz          */
++    HDMITX_VFREQ_50Hz      = 3,     /**< 50Hz          */
++    HDMITX_VFREQ_59Hz      = 4,     /**< 59.94Hz       */
++    HDMITX_VFREQ_60Hz      = 5,     /**< 60Hz          */
++#ifndef FORMAT_PC
++    HDMITX_VFREQ_INVALID   = 6,     /**< Invalid       */
++    HDMITX_VFREQ_NUM       = 6      /**< No. of values */
++#else /* FORMAT_PC */
++    HDMITX_VFREQ_70Hz      = 6,     /**< 70Hz          */
++    HDMITX_VFREQ_72Hz      = 7,     /**< 72Hz          */
++    HDMITX_VFREQ_75Hz      = 8,     /**< 75Hz          */
++    HDMITX_VFREQ_85Hz      = 9,     /**< 85Hz          */
++    HDMITX_VFREQ_87Hz      = 10,    /**< 87Hz          */
++    HDMITX_VFREQ_INVALID   = 11,    /**< Invalid       */
++    HDMITX_VFREQ_NUM       = 11     /**< No. of values */
++#endif /* FORMAT_PC */
++} tmbslHdmiTxVfreq_t;
++
++/** Clock Time Stamp predivider - scales N */
++typedef enum
++{
++    HDMITX_CTSK1           = 0,     /**< k=1 */
++    HDMITX_CTSK2           = 1,     /**< k=2 */
++    HDMITX_CTSK3           = 2,     /**< k=3 */
++    HDMITX_CTSK4           = 3,     /**< k=4 */
++    HDMITX_CTSK8           = 4,     /**< k=8 */
++    HDMITX_CTSK_USE_CTSX   = 5,     /**< Calculate from ctsX factor */
++    HDMITX_CTSK_INVALID    = 6      /**< Invalid */
++} tmbslHdmiTxctsK_t;
++
++/** Clock Time Stamp postdivider measured time stamp */
++typedef enum
++{
++    HDMITX_CTSMTS          = 0,     /**< =mts   */
++    HDMITX_CTSMTS2         = 1,     /**< =mts%2 */
++    HDMITX_CTSMTS4         = 2,     /**< =mts%4 */
++    HDMITX_CTSMTS8         = 3,     /**< =mts%8 */
++    HDMITX_CTSMTS_USE_CTSX = 4,     /**< Calculate from ctsX factor */
++    HDMITX_CTSMTS_INVALID  = 5      /**< Invalid */
++} tmbslHdmiTxctsM_t;
++
++/** Cycle Time Stamp values */
++enum _tmbslHdmiTxCts
++{
++    HDMITX_CTS_AUTO        = 0,
++    HDMITX_CTS_MIN         = 0x000001
++};
++
++/** Cycle Time Stamp X factors */ 
++enum _tmbslHdmiTxCtsX
++{
++    HDMITX_CTSX_16         = 0,
++    HDMITX_CTSX_32         = 1,
++    HDMITX_CTSX_48         = 2,
++    HDMITX_CTSX_64         = 3,
++    HDMITX_CTSX_128        = 4,
++    HDMITX_CTSX_NUM        = 5,
++    HDMITX_CTSX_UNUSED     = 5,     /**< CTX value unused when K and Mts used */
++    HDMITX_CTSX_INVALID    = 6
++};
++
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984AudioOutSetChanStatus() parameter types
++ */
++ 
++typedef enum
++{
++  HDMITX_AUDIO_DATA_PCM     = 0,  /**< Main data field represents linear PCM samples.    */
++  HDMITX_AUDIO_DATA_OTHER   = 1,  /**< Main data field used for purposes other purposes. */
++  HDMITX_AUDIO_DATA_INVALID = 2   /**< Invalid value */  
++} tmbslHdmiTxAudioData_t;
++
++/** BYTE 0: Channel Status Format information */
++typedef enum
++{
++    HDMITX_CSFI_PCM_2CHAN_NO_PRE    = 0,  /**< PCM 2 channels without pre-emphasis           */
++    HDMITX_CSFI_PCM_2CHAN_PRE       = 1,  /**< PCM 2 channels with 50us/15us pre-emphasis    */
++    HDMITX_CSFI_PCM_2CHAN_PRE_RSVD1 = 2,  /**< PCM Reserved for 2 channels with pre-emphasis */
++    HDMITX_CSFI_PCM_2CHAN_PRE_RSVD2 = 3,  /**< PCM Reserved for 2 channels with pre-emphasis */
++    HDMITX_CSFI_NOTPCM_DEFAULT      = 4,  /**< Non-PCM Default state                         */
++    HDMITX_CSFI_INVALID             = 5   /**< Invalid value                                 */
++} tmbslHdmiTxCSformatInfo_t;
++
++/** BYTE 0: Channel Status Copyright assertion */
++typedef enum
++{
++    HDMITX_CSCOPYRIGHT_PROTECTED   = 0,  /**< Copyright protected     */
++    HDMITX_CSCOPYRIGHT_UNPROTECTED = 1,  /**< Not copyright protected */
++    HDMITX_CSCOPYRIGHT_INVALID     = 2   /**< Invalid value           */
++} tmbslHdmiTxCScopyright_t;
++
++/** BYTE 3: Channel Status Clock Accuracy */
++typedef enum
++{
++    HDMITX_CSCLK_LEVEL_II    = 0,     /**< Level II                     */
++    HDMITX_CSCLK_LEVEL_I     = 1,     /**< Level I                      */
++    HDMITX_CSCLK_LEVEL_III   = 2,     /**< Level III                    */
++    HDMITX_CSCLK_NOT_MATCHED = 3,     /**< Not matched to sample freq.  */
++    HDMITX_CSCLK_INVALID     = 4      /**< Invalid                      */
++} tmbslHdmiTxCSclkAcc_t;
++
++/** BYTE 4: Channel Status Maximum sample word length */
++typedef enum
++{
++    HDMITX_CSMAX_LENGTH_20   = 0,  /**< Max word length is 20 bits   */
++    HDMITX_CSMAX_LENGTH_24   = 1,  /**< Max word length is 24 bits   */
++    HDMITX_CSMAX_INVALID     = 2   /**< Invalid value                */
++} tmbslHdmiTxCSmaxWordLength_t;
++
++
++/** BYTE 4: Channel Status Sample word length */
++typedef enum
++{
++    HDMITX_CSWORD_DEFAULT          = 0,     /**< Word length is not indicated                    */
++    HDMITX_CSWORD_20_OF_24         = 1,     /**< Sample length is 20 bits out of max 24 possible */
++    HDMITX_CSWORD_16_OF_20         = 1,     /**< Sample length is 16 bits out of max 20 possible */
++    HDMITX_CSWORD_22_OF_24         = 2,     /**< Sample length is 22 bits out of max 24 possible */
++    HDMITX_CSWORD_18_OF_20         = 2,     /**< Sample length is 18 bits out of max 20 possible */
++    HDMITX_CSWORD_RESVD            = 3,     /**< Reserved - shall not be used */
++    HDMITX_CSWORD_23_OF_24         = 4,     /**< Sample length is 23 bits out of max 24 possible */
++    HDMITX_CSWORD_19_OF_20         = 4,     /**< Sample length is 19 bits out of max 20 possible */
++    HDMITX_CSWORD_24_OF_24         = 5,     /**< Sample length is 24 bits out of max 24 possible */
++    HDMITX_CSWORD_20_OF_20         = 5,     /**< Sample length is 20 bits out of max 20 possible */
++    HDMITX_CSWORD_21_OF_24         = 6,     /**< Sample length is 21 bits out of max 24 possible */
++    HDMITX_CSWORD_17_OF_20         = 6,     /**< Sample length is 17 bits out of max 20 possible */
++    HDMITX_CSWORD_INVALID          = 7      /**< Invalid */
++} tmbslHdmiTxCSwordLength_t;
++
++/** BYTE 4: Channel Status Original sample frequency */
++typedef enum
++{
++    HDMITX_CSOFREQ_NOT_INDICATED = 0,   /**< Not Indicated */
++    HDMITX_CSOFREQ_192k          = 1,   /**< 192kHz        */
++    HDMITX_CSOFREQ_12k           = 2,   /**< 12kHz         */
++    HDMITX_CSOFREQ_176_4k        = 3,   /**< 176.4kHz      */
++    HDMITX_CSOFREQ_RSVD1         = 4,   /**< Reserved      */
++    HDMITX_CSOFREQ_96k           = 5,   /**< 96kHz         */
++    HDMITX_CSOFREQ_8k            = 6,   /**< 8kHz          */
++    HDMITX_CSOFREQ_88_2k         = 7,   /**< 88.2kHz       */
++    HDMITX_CSOFREQ_16k           = 8,   /**< 16kHz         */
++    HDMITX_CSOFREQ_24k           = 9,   /**< 24kHz         */
++    HDMITX_CSOFREQ_11_025k       = 10,  /**< 11.025kHz     */
++    HDMITX_CSOFREQ_22_05k        = 11,  /**< 22.05kHz      */
++    HDMITX_CSOFREQ_32k           = 12,  /**< 32kHz         */
++    HDMITX_CSOFREQ_48k           = 13,  /**< 48kHz         */
++    HDMITX_CSOFREQ_RSVD2         = 14,  /**< Reserved      */
++    HDMITX_CSOFREQ_44_1k         = 15,  /**< 44.1kHz       */
++    HDMITX_CSAFS_INVALID         = 16   /**< Invalid value */
++} tmbslHdmiTxCSorigAfs_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984AudioOutSetChanStatusMapping() parameter types
++ */
++/** Channel Status source/channel number limits */
++enum _tmbslHdmiTxChanStatusChanLimits
++{
++    HDMITX_CS_CHANNELS_MAX  = 0x0F,
++    HDMITX_CS_SOURCES_MAX   = 0x0F
++};
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984AudioOutSetMute() parameter type
++ */
++/** Audio mute state */
++typedef enum
++{
++    HDMITX_AMUTE_OFF       = 0,    /**< Mute off */
++    HDMITX_AMUTE_ON        = 1,    /**< Mute on  */
++    HDMITX_AMUTE_INVALID   = 2     /**< Invalid  */
++} tmbslHdmiTxaMute_t;
++
++/** Number of 3 byte Short Audio Descriptors stored in pEdidAFmts */
++#define HDMI_TX_SAD_MAX_CNT     30
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984EdidGetBlockData() parameter types
++ */
++/** An enum to represent the current EDID status */
++enum _tmbslHdmiTxEdidSta_t
++{
++    HDMITX_EDID_READ                = 0,    /* All blocks read OK */
++    HDMITX_EDID_READ_INCOMPLETE     = 1,    /* All blocks read OK but buffer too
++                                               small to return all of them */
++    HDMITX_EDID_ERROR_CHK_BLOCK_0   = 2,    /* Block 0 checksum error */
++
++    HDMITX_EDID_ERROR_CHK           = 3,    /* Block 0 OK, checksum error in one
++                                               or more other blocks */
++    HDMITX_EDID_NOT_READ            = 4,    /* EDID not read */
++
++    HDMITX_EDID_STATUS_INVALID      = 5     /**< Invalid   */
++
++};
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984EdidGetSinkType() parameter types
++ */
++/** Sink device type */
++typedef enum
++{
++    HDMITX_SINK_DVI                = 0,    /**< DVI  */
++    HDMITX_SINK_HDMI               = 1,    /**< HDMI */
++    HDMITX_SINK_EDID               = 2,    /**< As currently defined in EDID */
++    HDMITX_SINK_INVALID            = 3     /**< Invalid   */
++} tmbslHdmiTxSinkType_t;
++
++/*============================================================================*/
++/**
++ * \brief The tmbslTDA9984EdidGetVideoPreferred() parameter type
++ * Detailed timining description structure
++ */
++typedef struct _tmbslHdmiTxEdidDtd_t
++{
++    UInt16  uPixelClock;        /**< Pixel Clock/10,000         */
++    UInt16  uHActivePixels;     /**< Horizontal Active Pixels   */
++    UInt16  uHBlankPixels;      /**< Horizontal Blanking Pixels */
++    UInt16  uVActiveLines;      /**< Vertical Active Lines      */
++    UInt16  uVBlankLines;       /**< Vertical Blanking Lines    */
++    UInt16  uHSyncOffset;       /**< Horizontal Sync Offset     */
++    UInt16  uHSyncWidth;        /**< Horiz. Sync Pulse Width    */
++    UInt16  uVSyncOffset;       /**< Vertical Sync Offset       */
++    UInt16  uVSyncWidth;        /**< Vertical Sync Pulse Width  */
++    UInt16  uHImageSize;        /**< Horizontal Image Size      */
++    UInt16  uVImageSize;        /**< Vertical Image Size        */
++    UInt16  uHBorderPixels;     /**< Horizontal Border          */
++    UInt16  uVBorderPixels;     /**< Vertical Border            */
++    UInt8   Flags;              /**< Interlace/sync info        */
++} tmbslHdmiTxEdidDtd_t;
++
++
++/*============================================================================*/
++/**
++ * First monitor descriptor structure
++ */
++typedef struct _tmbslHdmiTxEdidFirstMD_t
++{   
++    Bool    bDescRecord;                                    /**< True when parameters of struct are available   */
++    UInt8   uMonitorName[EDID_MONITOR_DESCRIPTOR_SIZE];     /**< Monitor Name                                   */
++} tmbslHdmiTxEdidFirstMD_t;
++
++/*============================================================================*/
++/**
++ * Second monitor descriptor structure
++ */
++typedef struct _tmbslHdmiTxEdidSecondMD_t
++{
++    Bool    bDescRecord;                                    /**< True when parameters of struct are available   */
++    UInt8   uMinVerticalRate;                               /**< Min vertical rate in Hz                        */
++    UInt8   uMaxVerticalRate;                               /**< Max vertical rate in Hz                        */
++    UInt8   uMinHorizontalRate;                             /**< Min horizontal rate in Hz                      */
++    UInt8   uMaxHorizontalRate;                             /**< Max horizontal rate in Hz                      */
++    UInt8   uMaxSupportedPixelClk;                          /**< Max suuported pixel clock rate in MHz          */
++} tmbslHdmiTxEdidSecondMD_t;
++
++/*============================================================================*/
++/**
++ * Other monitor descriptor structure
++ */
++typedef struct _tmbslHdmiTxEdidOtherMD_t
++{
++    Bool    bDescRecord;                                    /**< True when parameters of struct are available   */
++    UInt8   uOtherDescriptor[EDID_MONITOR_DESCRIPTOR_SIZE]; /**< Other monitor Descriptor                       */
++} tmbslHdmiTxEdidOtherMD_t;
++
++/*============================================================================*/
++/**
++ * basic display parameters structure
++ */
++typedef struct _tmbslHdmiTxEdidBDParam_t
++{
++    UInt8   uVideoInputDef;      /**< Video Input Definition                       */
++    UInt8   uMaxHorizontalSize;  /**< Max. Horizontal Image Size in cm             */
++    UInt8   uMaxVerticalSize;    /**< Max. Vertical Image Size in cm               */
++    UInt8   uGamma;              /**< Gamma                                        */
++    UInt8   uFeatureSupport;     /**< Feature support                              */
++} tmbslHdmiTxEdidBDParam_t;
++
++/*============================================================================*/
++/**
++ * \brief The tmbslTDA9984EdidGetAudioCapabilities() parameter type
++ */
++typedef struct _tmbslHdmiTxEdidSad_t
++{
++    UInt8   ModeChans;  /* Bits[6:3]: EIA/CEA861 mode; Bits[2:0]: channels */
++    UInt8   Freqs;      /* Bits for each supported frequency */
++    UInt8   Byte3;      /* EIA/CEA861B p83: data depending on audio mode */
++}tmbslHdmiTxEdidSad_t;
++
++/*============================================================================*/
++/**
++ * \brief struc to store parameter provide by function tmbslTDA9984EdidRequestBlockData()
++ */
++typedef struct _tmbslHdmiTxEdidToApp_t
++{
++    UInt8   *pRawEdid;  /* pointer on a tab to store edid requested by application */
++    Int     numBlocks;  /* number of edid block requested by application */
++}tmbslHdmiTxEdidToApp_t;
++
++/*============================================================================*/
++/**
++ *  tmbslTDA9984EdidGetVideoCapabilities() parameter types
++ */
++/** Number of 1 byte Short Video Descriptors stored in pEdidVFmts */
++#define HDMI_TX_SVD_MAX_CNT     113
++
++/** number of detailed timing descriptor stored in BSL */
++#define NUMBER_DTD_STORED       10
++
++
++
++/** Flag set in Short Video Descriptor to indicate native format */
++#define HDMI_TX_SVD_NATIVE_MASK 0x80
++#define HDMI_TX_SVD_NATIVE_NOT  0x7F
++
++/** Video capability flags */
++enum _tmbslHdmiTxVidCap_t
++{
++    HDMITX_VIDCAP_UNDERSCAN   = 0x80,   /**< Underscan supported */
++    HDMITX_VIDCAP_YUV444      = 0x40,   /**< YCbCr 4:4:4 supported */
++    HDMITX_VIDCAP_YUV422      = 0x20,   /**< YCbCr 4:2:2 supported */
++    HDMITX_VIDCAP_UNUSED      = 0x1F    /**< Unused flags */
++};
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984HdcpCheck() parameter type
++ */
++/** HDCP check result */
++typedef enum
++{
++    HDMITX_HDCP_CHECK_NOT_STARTED       = 0,    /**< Check not started */
++    HDMITX_HDCP_CHECK_IN_PROGRESS       = 1,    /**< No failures, more to do */
++    HDMITX_HDCP_CHECK_PASS              = 2,    /**< Final check has passed */
++    HDMITX_HDCP_CHECK_FAIL_FIRST        = 3,    /**< First check failure code */
++    HDMITX_HDCP_CHECK_FAIL_DRIVER_STATE = 3,    /**< Driver not AUTHENTICATED */
++    HDMITX_HDCP_CHECK_FAIL_DEVICE_T0    = 4,    /**< A T0 interrupt occurred */
++    HDMITX_HDCP_CHECK_FAIL_DEVICE_RI    = 5,    /**< Device RI changed */
++    HDMITX_HDCP_CHECK_FAIL_DEVICE_FSM   = 6,    /**< Device FSM not 10h */
++    HDMITX_HDCP_CHECK_NUM               = 7     /**< Number of check results */
++}tmbslHdmiTxHdcpCheck_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984HdcpConfigure() parameter type
++ */
++/** HDCP DDC slave addresses */
++enum _tmbslHdmiTxHdcpSlaveAddress
++{
++    HDMITX_HDCP_SLAVE_PRIMARY    = 0x74,
++    HDMITX_HDCP_SLAVE_SECONDARY  = 0x76
++};
++
++/** HDCP transmitter modes */
++typedef enum
++{
++    HDMITX_HDCP_TXMODE_NOT_SET   = 0,
++    HDMITX_HDCP_TXMODE_REPEATER  = 1,
++    HDMITX_HDCP_TXMODE_TOP_LEVEL = 2,
++    HDMITX_HDCP_TXMODE_MAX       = 2
++}tmbslHdmiTxHdcpTxMode_t;
++
++/** HDCP option flags */
++typedef enum
++{
++    HDMITX_HDCP_OPTION_FORCE_PJ_IGNORED = 0x01,/* Not set: obey PJ result     */
++    HDMITX_HDCP_OPTION_FORCE_SLOW_DDC   = 0x02,/* Not set: obey BCAPS setting */
++    HDMITX_HDCP_OPTION_FORCE_NO_1_1     = 0x04,/* Not set: obey BCAPS setting */
++    HDMITX_HDCP_OPTION_FORCE_REPEATER   = 0x08,/* Not set: obey BCAPS setting */
++    HDMITX_HDCP_OPTION_FORCE_NO_REPEATER= 0x10,/* Not set: obey BCAPS setting */
++    HDMITX_HDCP_OPTION_FORCE_V_EQU_VBAR = 0x20,/* Not set: obey V=V' result   */
++    HDMITX_HDCP_OPTION_FORCE_VSLOW_DDC  = 0x40,/* Set: 50kHz DDC */
++    HDMITX_HDCP_OPTION_DEFAULT          = 0x00,/* All the above Not Set vals */
++    HDMITX_HDCP_OPTION_MASK             = 0x7F,/* Only these bits are allowed */
++    HDMITX_HDCP_OPTION_MASK_BAD         = 0x80 /* These bits are not allowed  */
++}tmbslHdmiTxHdcpOptions_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984HdcpDownloadKeys() parameter type
++ */
++/** HDCP decryption mode */
++typedef enum
++{
++    HDMITX_HDCP_DECRYPT_DISABLE  = 0,
++    HDMITX_HDCP_DECRYPT_ENABLE   = 1,
++    HDMITX_HDCP_DECRYPT_MAX      = 1
++}tmbslHdmiTxDecrypt_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984HdcpHandleBSTATUS() parameter type
++ */
++/** BSTATUS bit fields */
++enum _tmbslHdmiTxHdcpHandleBSTATUS
++{
++    HDMITX_HDCP_BSTATUS_HDMI_MODE               = 0x1000,
++    HDMITX_HDCP_BSTATUS_MAX_CASCADE_EXCEEDED    = 0x0800,
++    HDMITX_HDCP_BSTATUS_CASCADE_DEPTH           = 0x0700,
++    HDMITX_HDCP_BSTATUS_MAX_DEVS_EXCEEDED       = 0x0080,
++    HDMITX_HDCP_BSTATUS_DEVICE_COUNT            = 0x007F
++};
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984HdcpHandleSHA_1() parameter types
++ */
++/** KSV list sizes */
++enum _tmbslHdmiTxHdcpHandleSHA_1
++{
++    HDMITX_KSV_LIST_MAX_DEVICES = 128,
++    HDMITX_KSV_BYTES_PER_DEVICE = 5
++};
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984HotPlugGetStatus() parameter type
++ */
++/** Current hotplug status */
++typedef enum
++{
++    HDMITX_HOTPLUG_INACTIVE    = 0,    /**< Hotplug inactive */
++    HDMITX_HOTPLUG_ACTIVE      = 1,    /**< Hotplug active   */
++    HDMITX_HOTPLUG_INVALID     = 2     /**< Invalid Hotplug  */
++} tmbslHdmiTxHotPlug_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984RxSenseGetStatus() parameter type
++ */
++/** Current RX Sense status */
++typedef enum
++{
++    HDMITX_RX_SENSE_INACTIVE    = 0,    /**< RxSense inactive */
++    HDMITX_RX_SENSE_ACTIVE      = 1,    /**< RxSense active   */
++    HDMITX_RX_SENSE_INVALID     = 2     /**< Invalid RxSense  */
++} tmbslHdmiTxRxSense_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984HwGetCapabilities() parameter type
++ */
++/** List of HW features that may be supported by HW */
++typedef enum
++{
++    HDMITX_FEATURE_HW_HDCP             = 0,  /**< HDCP   feature */
++    HDMITX_FEATURE_HW_SCALER           = 1,  /**< Scaler feature */
++    HDMITX_FEATURE_HW_AUDIO_OBA        = 2,  /**< One Bit Audio feature */
++    HDMITX_FEATURE_HW_AUDIO_DST        = 3,  /**< DST Audio feature */
++    HDMITX_FEATURE_HW_AUDIO_HBR        = 4,  /**< HBR Audio feature */
++    HDMITX_FEATURE_HW_HDMI_1_1         = 5,  /**< HDMI 1.1 feature */
++    HDMITX_FEATURE_HW_HDMI_1_2A        = 6,  /**< HDMI 1.2a feature */
++    HDMITX_FEATURE_HW_HDMI_1_3A        = 7,  /**< HDMI 1.3a feature */
++    HDMITX_FEATURE_HW_DEEP_COLOR_30    = 8,  /**< 30 bits deep color support */
++    HDMITX_FEATURE_HW_DEEP_COLOR_36    = 9,  /**< 36 bits deep color support */
++    HDMITX_FEATURE_HW_DEEP_COLOR_48    = 11, /**< 48 bits deep color support */
++    HDMITX_FEATURE_HW_UPSAMPLER        = 12, /**< Up sampler feature */
++    HDMITX_FEATURE_HW_DOWNSAMPLER      = 13, /**< Down sampler feature */
++    HDMITX_FEATURE_HW_COLOR_CONVERSION = 14  /**< Color conversion matrix */
++} tmbslHdmiTxHwFeature_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984Init() parameter types
++ */
++/** Supported range of I2C slave addresses */
++enum _tmbslHdmiTxSlaveAddress
++{
++    HDMITX_SLAVE_ADDRESS_MIN    = 1,
++    HDMITX_SLAVE_ADDRESS_MAX    = 127
++};
++
++/**
++ * Indexes into the funcCallback[] array of interrupt callback function pointers
++ */
++typedef enum _tmbslHdmiTxCallbackInt
++{
++    HDMITX_CALLBACK_INT_SECURITY        = 0,  /**< HDCP encryption switched off     */
++    HDMITX_CALLBACK_INT_ENCRYPT         = 0,  /**< HDCP encrypt as above (Obsolete) */
++    HDMITX_CALLBACK_INT_HPD             = 1,  /**< Transition on HPD input          */
++    HDMITX_CALLBACK_INT_T0              = 2,  /**< HDCP state machine in state T0   */
++    HDMITX_CALLBACK_INT_BCAPS           = 3,  /**< BCAPS available                  */
++    HDMITX_CALLBACK_INT_BSTATUS         = 4,  /**< BSTATUS available                */
++    HDMITX_CALLBACK_INT_SHA_1           = 5,  /**< sha-1(ksv,bstatus,m0)=V'         */
++    HDMITX_CALLBACK_INT_PJ              = 6,  /**< pj=pj' check fails               */
++    HDMITX_CALLBACK_INT_R0              = 7,  /**< R0 interrupt                     */
++    HDMITX_CALLBACK_INT_SW_INT          = 8,  /**< SW DEBUG interrupt               */
++    HDMITX_CALLBACK_INT_RX_SENSE        = 9,  /**< RX SENSE interrupt               */
++    HDMITX_CALLBACK_INT_EDID_BLK_READ   = 10, /**< EDID BLK READ interrupt          */
++    HDMITX_CALLBACK_INT_PLL_LOCK        = 11, /**< Pll Lock (Serial or Formatter)   */
++    HDMITX_CALLBACK_INT_VS_RPT          = 12, /**< VS Interrupt for Gamut packets   */
++    HDMITX_CALLBACK_INT_NUM             = 13  /**< Number of callbacks              */
++}tmbslHdmiTxCallbackInt_t;
++
++/** Pixel rate */
++typedef enum
++{
++    HDMITX_PIXRATE_DOUBLE               = 0,        /**< Double pixel rate */
++    HDMITX_PIXRATE_SINGLE               = 1,        /**< Single pixel rate */
++    HDMITX_PIXRATE_SINGLE_REPEATED      = 2,        /**< Single pixel repeated */
++    HDMITX_PIXRATE_NO_CHANGE            = 3,        /**< No Change */
++    HDMITX_PIXRATE_INVALID              = 4         /**< Invalid   */
++} tmbslHdmiTxPixRate_t;
++
++/**
++ * \brief The tmbslTDA9984Init() parameter structure
++ */
++typedef struct _tmbslHdmiTxCallbackList_t
++{
++    /** Interrupt callback function pointers (each ptr if null = not used) */
++    ptmbslHdmiTxCallback_t funcCallback[HDMITX_CALLBACK_INT_NUM];
++
++} tmbslHdmiTxCallbackList_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984MatrixSetCoeffs() parameter type
++ */
++/** Parameter structure array size */
++enum _tmbslHdmiTxMatCoeff
++{
++    HDMITX_MAT_COEFF_NUM = 9
++};
++
++
++/** \brief The tmbslTDA9984MatrixSetCoeffs() parameter structure */
++/** Array of coefficients (values -1024 to +1023) */
++typedef struct _tmbslHdmiTxMatCoeff_t
++{
++    /** Array of coefficients (values -1024 to +1023) */
++    Int16 Coeff[HDMITX_MAT_COEFF_NUM];
++} tmbslHdmiTxMatCoeff_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984MatrixSetConversion() parameter type
++ */
++/** Video input mode */
++typedef enum
++{
++    HDMITX_VINMODE_CCIR656     = 0,    /**< ccir656  */
++    HDMITX_VINMODE_RGB444      = 1,    /**< RGB444    */
++    HDMITX_VINMODE_YUV444      = 2,    /**< YUV444    */
++    HDMITX_VINMODE_YUV422      = 3,    /**< YUV422    */
++    HDMITX_VINMODE_NO_CHANGE   = 4,    /**< No change */
++    HDMITX_VINMODE_INVALID     = 5     /**< Invalid   */
++} tmbslHdmiTxVinMode_t;
++
++/** Video output mode */
++typedef enum
++{
++    HDMITX_VOUTMODE_RGB444      = 0,    /**< RGB444    */
++    HDMITX_VOUTMODE_YUV422      = 1,    /**< YUV422    */
++    HDMITX_VOUTMODE_YUV444      = 2,    /**< YUV444    */
++    HDMITX_VOUTMODE_NO_CHANGE   = 3,    /**< No change */
++    HDMITX_VOUTMODE_INVALID     = 4     /**< Invalid   */
++} tmbslHdmiTxVoutMode_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984MatrixSetMode() parameter types
++ */
++/** Matrix  control values */
++typedef enum
++{
++    HDMITX_MCNTRL_ON        = 0,   /**< Matrix on  */
++    HDMITX_MCNTRL_OFF       = 1,   /**< Matrix off */
++    HDMITX_MCNTRL_NO_CHANGE = 2,   /**< Matrix unchanged */
++    HDMITX_MCNTRL_MAX       = 2,   /**< Max value  */
++    HDMITX_MCNTRL_INVALID   = 3    /**< Invalid    */
++} tmbslHdmiTxmCntrl_t;
++
++/** Matrix  scale values */
++typedef enum
++{
++    HDMITX_MSCALE_256       = 0,   /**< Factor 1/256  */
++    HDMITX_MSCALE_512       = 1,   /**< Factor 1/512  */
++    HDMITX_MSCALE_1024      = 2,   /**< Factor 1/1024 */
++    HDMITX_MSCALE_NO_CHANGE = 3,   /**< Factor unchanged */
++    HDMITX_MSCALE_MAX       = 3,   /**< Max value     */
++    HDMITX_MSCALE_INVALID   = 4    /**< Invalid value */
++} tmbslHdmiTxmScale_t;
++
++/*============================================================================*/
++/**
++ * Data Island Packet structure
++ */
++/** Parameter structure array sizes */
++enum _tmbslHdmiTxPkt
++{
++    HDMITX_PKT_DATA_BYTE_CNT = 28
++};
++
++/** \brief The parameter structure for tmbslTDA9984Pkt*() APIs */
++typedef struct _tmbslHdmiTxPkt_t
++{
++    UInt8 dataByte[HDMITX_PKT_DATA_BYTE_CNT];       /**< Packet Data   */
++} tmbslHdmiTxPkt_t;
++
++/*============================================================================*/
++/**
++ * \brief The Audio Infoframe Parameter structure
++ */
++typedef struct _tmbslHdmiTxPktAif_t
++{
++    UInt8 CodingType;       /**< Coding Type 0 to 0Fh */
++    UInt8 ChannelCount;     /**< Channel Count 0 to 07h */
++    UInt8 SampleFreq;       /**< Sample Frequency 0 to 07h */
++    UInt8 SampleSize;       /**< Sample Size 0 to 03h */
++    UInt8 ChannelAlloc;     /**< Channel Allocation 0 to FFh */
++    Bool  DownMixInhibit;   /**< Downmix inhibit flag 0/1 */
++    UInt8 LevelShift;       /**< Level Shift 0 to 0Fh */
++} tmbslHdmiTxPktAif_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984PktSetMpegInfoframe() parameter types
++ */
++/** MPEG frame types */
++typedef enum
++{
++    HDMITX_MPEG_FRAME_UNKNOWN   = 0,    /**< Unknown  */
++    HDMITX_MPEG_FRAME_I         = 1,    /**< i-frame   */
++    HDMITX_MPEG_FRAME_B         = 2,    /**< b-frame */
++    HDMITX_MPEG_FRAME_P         = 3,    /**< p-frame */
++    HDMITX_MPEG_FRAME_INVALID   = 4     /**< Invalid   */
++} tmbslHdmiTxMpegFrame_t;
++
++/** \brief The MPEG Infoframe Parameter structure */
++typedef struct _tmbslHdmiTxPktMpeg_t
++{
++    UInt32                  bitRate;        /**< MPEG bit rate in Hz */
++    tmbslHdmiTxMpegFrame_t  frameType;      /**< MPEG frame type */
++    Bool                    bFieldRepeat;   /**< 0: new field, 1:repeated field */
++}tmbslHdmiTxPktMpeg_t;
++
++/*============================================================================*/
++/**
++  * Source Product Description Infoframe Parameter types
++  */
++/** SDI frame types */
++typedef enum
++{
++    HDMITX_SPD_INFO_UNKNOWN     = 0,
++    HDMITX_SPD_INFO_DIGITAL_STB = 1,
++    HDMITX_SPD_INFO_DVD         = 2,
++    HDMITX_SPD_INFO_DVHS        = 3,
++    HDMITX_SPD_INFO_HDD_VIDEO   = 4,
++    HDMITX_SPD_INFO_DVC         = 5,
++    HDMITX_SPD_INFO_DSC         = 6,
++    HDMITX_SPD_INFO_VIDEO_CD    = 7,
++    HDMITX_SPD_INFO_GAME        = 8,
++    HDMITX_SPD_INFO_PC          = 9,
++    HDMITX_SPD_INFO_INVALID     = 10
++} tmbslHdmiTxSourceDev_t;
++
++#define HDMI_TX_SPD_VENDOR_SIZE 8
++#define HDMI_TX_SPD_DESCR_SIZE  16
++#define HDMI_TX_SPD_LENGTH      25
++ 
++/** \brief The Source Product Description Infoframe Parameter structure */
++typedef struct _tmbslHdmiTxPktSpd_t
++{
++    UInt8                   VendorName[HDMI_TX_SPD_VENDOR_SIZE]; /**< Vendor name */
++    UInt8                   ProdDescr[HDMI_TX_SPD_DESCR_SIZE]; /**< Product Description */
++    tmbslHdmiTxSourceDev_t  SourceDevInfo;                     /**< Source Device Info */
++} tmbslHdmiTxPktSpd_t;
++
++/*============================================================================*/
++/**
++  * \brief The Video Infoframe Parameter structure
++  */
++typedef struct _tmbslHdmiTxPktVif_t
++{
++    UInt8  Colour;               /**< 0 to 03h */
++    Bool   ActiveInfo;           /**< 0/1 */
++    UInt8  BarInfo;              /**< 0 to 03h */
++    UInt8  ScanInfo;             /**< 0 to 03h */
++    UInt8  Colorimetry;          /**< 0 to 03h */
++    UInt8  PictureAspectRatio;   /**< 0 to 03h */
++    UInt8  ActiveFormatRatio;    /**< 0 to 0Fh */
++    UInt8  Scaling;              /**< 0 to 03h */
++    UInt8  VidFormat;            /**< 0 to 7Fh */
++    UInt8  PixelRepeat;          /**< 0 to 0Fh */
++    UInt16 EndTopBarLine;       
++    UInt16 StartBottomBarLine;  
++    UInt16 EndLeftBarPixel;
++    UInt16 StartRightBarPixel;
++} tmbslHdmiTxPktVif_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984ScalerGetMode() parameter types
++ */
++/** Scaler modes */
++typedef enum
++{
++    HDMITX_SCAMODE_OFF       = 0,    /**< Off  */
++    HDMITX_SCAMODE_ON        = 1,    /**< On   */
++    HDMITX_SCAMODE_AUTO      = 2,    /**< Auto */
++    HDMITX_SCAMODE_NO_CHANGE = 3,    /**< No change */
++    HDMITX_SCAMODE_INVALID   = 4     /**< Invalid   */
++} tmbslHdmiTxScaMode_t;
++
++/*============================================================================*/
++/**
++ * \brief The tmbslTDA9984ScalerGet() parameter type
++ */
++typedef struct _tmbslHdmiTxScalerDiag_t
++{
++    UInt16 maxBuffill_p;     /**< Filling primary video buffer           */
++    UInt16 maxBuffill_d;     /**< Filling video deinterlaced buffer      */
++    UInt8 maxFifofill_pi;    /**< Filling primary video input FIFO       */
++    UInt8 minFifofill_po1;   /**< Filling primary video output FIFO #1   */
++    UInt8 minFifofill_po2;   /**< Filling primary video output FIFO #2   */
++    UInt8 minFifofill_po3;   /**< Filling primary video output FIFO #3   */
++    UInt8 minFifofill_po4;   /**< Filling primary video output FIFO #4   */
++    UInt8 maxFifofill_di;    /**< Filling deinterlaced video input FIFO  */
++    UInt8 maxFifofill_do;    /**< Filling deinterlaced video output FIFO */
++} tmbslHdmiTxScalerDiag_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984ScalerSetCoeffs() parameter types
++ */
++/** Scaler lookup table selection */
++typedef enum
++{
++    HDMITX_SCALUT_DEFAULT_TAB1     = 0,    /**< Use default table 1 */
++    HDMITX_SCALUT_DEFAULT_TAB2     = 1,    /**< Use default table 2 */
++    HDMITX_SCALUT_USE_VSLUT        = 2,    /**< Use vsLut parameter */
++    HDMITX_SCALUT_INVALID          = 3     /**< Invalid value       */
++} tmbslHdmiTxScaLut_t;
++ 
++/** Scaler control parameter structure array size */
++enum _tmbslHdmiTxvsLut
++{
++    HDMITX_VSLUT_COEFF_NUM         = 45
++};
++/*============================================================================*/
++/**
++ * tmbslTDA9984ScalerSetFieldOrder() parameter types
++ */
++/** IntExt values */
++typedef enum
++{
++    HDMITX_INTEXT_INTERNAL         = 0,    /**< Internal  */
++    HDMITX_INTEXT_EXTERNAL         = 1,    /**< External  */
++    HDMITX_INTEXT_NO_CHANGE        = 2,    /**< No change */
++    HDMITX_INTEXT_INVALID          = 3     /**< Invalid   */
++} tmbslHdmiTxIntExt_t;
++
++/** TopSel values */
++typedef enum
++{
++    HDMITX_TOPSEL_INTERNAL         = 0,    /**< Internal  */
++    HDMITX_TOPSEL_VRF              = 1,    /**< VRF       */
++    HDMITX_TOPSEL_NO_CHANGE        = 2,    /**< No change */
++    HDMITX_TOPSEL_INVALID          = 3     /**< Invalid   */
++} tmbslHdmiTxTopSel_t;
++
++/** TopTgl values */
++typedef enum
++{
++    HDMITX_TOPTGL_NO_ACTION        = 0,    /**< NO action */
++    HDMITX_TOPTGL_TOGGLE           = 1,    /**< Toggle    */
++    HDMITX_TOPTGL_NO_CHANGE        = 2,    /**< No change */
++    HDMITX_TOPTGL_INVALID          = 3     /**< Invalid   */
++} tmbslHdmiTxTopTgl_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984ScalerSetPhase() parameter types
++ */
++/** Phases_h values */
++typedef enum
++{
++    HDMITX_H_PHASES_16        = 0,    /**< 15 horizontal phases */
++    HDMITX_H_PHASES_15        = 1,    /**< 16 horizontal phases */
++    HDMITX_H_PHASES_INVALID   = 2     /**< Invalid   */
++} tmbslHdmiTxHPhases_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984ScalerSetFine() parameter types
++ */
++/** Reference pixel values */
++enum _tmbslHdmiTxScalerFinePixelLimits
++{
++    HDMITX_SCALER_FINE_PIXEL_MIN        = 0x0000,
++    HDMITX_SCALER_FINE_PIXEL_MAX        = 0x1FFF,
++    HDMITX_SCALER_FINE_PIXEL_NO_CHANGE  = 0x2000,
++    HDMITX_SCALER_FINE_PIXEL_INVALID    = 0x2001
++};
++
++/** Reference line values */
++enum _tmbslHdmiTxScalerFineLineLimits
++{
++    HDMITX_SCALER_FINE_LINE_MIN         = 0x0000,
++    HDMITX_SCALER_FINE_LINE_MAX         = 0x07FF,
++    HDMITX_SCALER_FINE_LINE_NO_CHANGE   = 0x0800,
++    HDMITX_SCALER_FINE_LINE_INVALID     = 0x0801
++};
++/*============================================================================*/
++/**
++ * tmbslTDA9984ScalerSetSync() parameter types
++ */
++/** Video sync method */
++typedef enum
++{
++    HDMITX_VSMETH_V_H          = 0,    /**< V and H    */
++    HDMITX_VSMETH_V_XDE        = 1,    /**< V and X-DE */
++    HDMITX_VSMETH_NO_CHANGE    = 2,    /**< No change  */
++    HDMITX_VSMETH_INVALID      = 3     /**< Invalid    */
++} tmbslHdmiTxVsMeth_t;
++ 
++/** Line/pixel counters sync */
++typedef enum
++{
++    HDMITX_VSONCE_EACH_FRAME   = 0,    /**< Sync on each frame */
++    HDMITX_VSONCE_ONCE         = 1,    /**< Sync once only     */
++    HDMITX_VSONCE_NO_CHANGE    = 2,    /**< No change  */
++    HDMITX_VSONCE_INVALID      = 3     /**< Invalid    */
++} tmbslHdmiTxVsOnce_t;
++ 
++/*============================================================================*/
++/**
++ * tmbslTDA9984TmdsSetOutputs() parameter types
++ */
++/** TMDS output mode */
++typedef enum
++{
++    HDMITX_TMDSOUT_NORMAL      = 0,    /**< Normal outputs   */
++    HDMITX_TMDSOUT_NORMAL1     = 1,    /**< Normal outputs, same as 0  */
++    HDMITX_TMDSOUT_FORCED0     = 2,    /**< Forced 0 outputs */
++    HDMITX_TMDSOUT_FORCED1     = 3,    /**< Forced 1 outputs */
++    HDMITX_TMDSOUT_INVALID     = 4     /**< Invalid          */
++} tmbslHdmiTxTmdsOut_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984TmdsSetSerializer() parameter types
++ */
++/** Serializer phase limits */
++enum _tmbslHdmiTxTmdsPhase
++{
++    HDMITX_TMDSPHASE_MIN       = 0,
++    HDMITX_TMDSPHASE_MAX       = 15,
++    HDMITX_TMDSPHASE_INVALID   = 16
++};
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984TestSetPattern() parameter types
++ */
++/** Test pattern types */
++typedef enum
++{
++    HDMITX_PATTERN_OFF     = 0, /**< Insert test pattern     */
++    HDMITX_PATTERN_CBAR4   = 1, /**< Insert 4-bar colour bar */
++    HDMITX_PATTERN_CBAR8   = 2, /**< Insert 8-bar colour bar */
++	HDMITX_PATTERN_BLUE	   = 3, /**< Insert Blue screen		 */
++	HDMITX_PATTERN_BLACK   = 4, /**< Insert Blue screen		 */
++    HDMITX_PATTERN_INVALID = 5  /**< Invalid pattern		 */
++} tmbslHdmiTxTestPattern_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984TestSetMode() parameter types
++ */
++/** Test modes */
++typedef enum
++{
++    HDMITX_TESTMODE_PAT     = 0,/**< Insert test pattern                    */
++    HDMITX_TESTMODE_656     = 1,/**< Inject CCIR-656 video via audio port   */
++    HDMITX_TESTMODE_SERPHOE = 2,/**< Activate srl_tst_ph2_o & srl_tst_ph3_o */
++    HDMITX_TESTMODE_NOSC    = 3,/**< Input nosc predivider = PLL-ref input  */
++    HDMITX_TESTMODE_HVP     = 4,/**< Test high voltage protection cells     */
++    HDMITX_TESTMODE_PWD     = 5,/**< Test PLLs in sleep mode                */
++    HDMITX_TESTMODE_DIVOE   = 6,/**< Enable scaler PLL divider test output  */
++    HDMITX_TESTMODE_INVALID = 7 /**< Invalid test */
++} tmbslHdmiTxTestMode_t;
++
++/** Test states */
++typedef enum
++{
++    HDMITX_TESTSTATE_OFF     = 0,  /**< Disable the selected test */
++    HDMITX_TESTSTATE_ON      = 1,  /**< Enable the selected test  */
++    HDMITX_TESTSTATE_INVALID = 2   /**< Invalid value */
++} tmbslHdmiTxTestState_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984VideoInSetBlanking() parameter types
++ */
++/** Blankit Source */
++typedef enum
++{
++    HDMITX_BLNKSRC_NOT_DE       = 0,       /**< Source=Not DE        */
++    HDMITX_BLNKSRC_VS_HS        = 1,       /**< Source=VS And HS     */
++    HDMITX_BLNKSRC_VS_NOT_HS    = 2,       /**< Source=VS And Not HS */
++    HDMITX_BLNKSRC_VS_HEMB_VEMB = 3,       /**< Source=Hemb And Vemb */
++    HDMITX_BLNKSRC_NO_CHANGE    = 4,       /**< No change */
++    HDMITX_BLNKSRC_INVALID      = 5        /**< Invalid   */
++} tmbslHdmiTxBlnkSrc_t;
++ 
++/** Blanking Codes */
++typedef enum
++{
++    HDMITX_BLNKCODE_ALL_0       = 0,       /**< Code=All Zero */
++    HDMITX_BLNKCODE_RGB444      = 1,       /**< Code=RGB444   */
++    HDMITX_BLNKCODE_YUV444      = 2,       /**< Code=YUV444   */
++    HDMITX_BLNKCODE_YUV422      = 3,       /**< Code=YUV422   */
++    HDMITX_BLNKCODE_NO_CHANGE   = 4,       /**< No change */
++    HDMITX_BLNKCODE_INVALID     = 5        /**< Invalid   */
++} tmbslHdmiTxBlnkCode_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984VideoInSetConfig() parameter types
++ */
++/** Sample edge */
++typedef enum
++{
++    HDMITX_PIXEDGE_CLK_POS      = 0,        /**< Pixel Clock Positive Edge */
++    HDMITX_PIXEDGE_CLK_NEG      = 1,        /**< Pixel Clock Negative Edge */
++    HDMITX_PIXEDGE_NO_CHANGE    = 2,        /**< No Change */
++    HDMITX_PIXEDGE_INVALID      = 3         /**< Invalid   */
++} tmbslHdmiTxPixEdge_t;
++
++/** Upsample modes */
++typedef enum
++{
++    HDMITX_UPSAMPLE_BYPASS      = 0,        /**< Bypass */
++    HDMITX_UPSAMPLE_COPY        = 1,        /**< Copy */
++    HDMITX_UPSAMPLE_INTERPOLATE = 2,        /**< Interpolate */
++    HDMITX_UPSAMPLE_AUTO        = 3,        /**< Auto: driver chooses best value */
++    HDMITX_UPSAMPLE_NO_CHANGE   = 4,        /**< No Change */
++    HDMITX_UPSAMPLE_INVALID     = 5         /**< Invalid   */
++} tmbslHdmiTxUpsampleMode_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984VideoInSetFine() parameter types
++ */
++/** Subpacket count */
++typedef enum
++{
++    HDMITX_PIXSUBPKT_FIX_0      = 0,        /**< Fix At 0 */
++    HDMITX_PIXSUBPKT_FIX_1      = 1,        /**< Fix At 1 */
++    HDMITX_PIXSUBPKT_FIX_2      = 2,        /**< Fix At 2 */
++    HDMITX_PIXSUBPKT_FIX_3      = 3,        /**< Fix At 3 */
++    HDMITX_PIXSUBPKT_SYNC_FIRST = 4,        /**< First Sync value */
++    HDMITX_PIXSUBPKT_SYNC_HEMB  = 4,        /**< Sync By Hemb */
++    HDMITX_PIXSUBPKT_SYNC_DE    = 5,        /**< Sync By Rising Edge DE */
++    HDMITX_PIXSUBPKT_SYNC_HS    = 6,        /**< Sync By Rising Edge HS */
++    HDMITX_PIXSUBPKT_NO_CHANGE  = 7,        /**< No Change */
++    HDMITX_PIXSUBPKT_INVALID    = 8,        /**< Invalid   */
++    HDMITX_PIXSUBPKT_SYNC_FIXED = 3         /**< Not used as a parameter value,
++                                             *  but used internally when 
++                                             *  Fix at 0/1/2/3 values are set */
++} tmbslHdmiTxPixSubpkt_t;
++
++/** Toggling */
++typedef enum
++{
++    HDMITX_PIXTOGL_NO_ACTION    = 0,        /**< No Action  */
++    HDMITX_PIXTOGL_ENABLE       = 1,        /**< Toggle     */
++    HDMITX_PIXTOGL_NO_CHANGE    = 2,        /**< No Change  */
++    HDMITX_PIXTOGL_INVALID      = 3         /**< Invalid    */
++} tmbslHdmiTxPixTogl_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984VideoInSetMapping() parameter types
++ */
++/** Video input port parameter structure array size and limits */
++enum _tmbslHdmiTxVinPortMap
++{
++    HDMITX_VIN_PORT_MAP_TABLE_LEN    = 6,
++
++    HDMITX_VIN_PORT_SWAP_NO_CHANGE   = 6,
++    HDMITX_VIN_PORT_SWAP_INVALID     = 7,
++
++    HDMITX_VIN_PORT_MIRROR_NO_CHANGE = 2,
++    HDMITX_VIN_PORT_MIRROR_INVALID   = 3
++};
++
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984VideoInSetSyncAuto() parameter types
++ */
++/** Sync source - was Embedded sync HDMITX_PIXEMBSYNC_ */
++typedef enum
++{
++    HDMITX_SYNCSRC_EMBEDDED  = 0,        /**< Embedded sync */
++    HDMITX_SYNCSRC_EXT_VREF  = 1,        /**< External sync Vref, Href, Fref */
++    HDMITX_SYNCSRC_EXT_VS    = 2,        /**< External sync Vs, Hs */
++    HDMITX_SYNCSRC_NO_CHANGE = 3,        /**< No Change     */
++    HDMITX_SYNCSRC_INVALID   = 4         /**< Invalid       */
++} tmbslHdmiTxSyncSource_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984VideoInSetSyncManual() parameter types
++ */
++/** Video output frame pixel values */
++enum _tmbslHdmiTxVoutFinePixelLimits
++{
++    HDMITX_VOUT_FINE_PIXEL_MIN        = 0x0000,
++    HDMITX_VOUT_FINE_PIXEL_MAX        = 0x1FFF,
++    HDMITX_VOUT_FINE_PIXEL_NO_CHANGE  = 0x2000,
++    HDMITX_VOUT_FINE_PIXEL_INVALID    = 0x2001
++};
++
++/** Video output frame line values */
++enum _tmbslHdmiTxVoutFineLineLimits
++{
++    HDMITX_VOUT_FINE_LINE_MIN         = 0x0000,
++    HDMITX_VOUT_FINE_LINE_MAX         = 0x07FF,
++    HDMITX_VOUT_FINE_LINE_NO_CHANGE   = 0x0800,
++    HDMITX_VOUT_FINE_LINE_INVALID     = 0x0801
++};
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984VideoOutSetConfig() parameter types
++ */
++/** Prefilter */
++typedef enum
++{
++    HDMITX_VOUT_PREFIL_OFF         = 0,    /**< Off */
++    HDMITX_VOUT_PREFIL_121         = 1,    /**< 121 */
++    HDMITX_VOUT_PREFIL_109         = 2,    /**< 109 */
++    HDMITX_VOUT_PREFIL_CCIR601     = 3,    /**< CCIR601   */
++    HDMITX_VOUT_PREFIL_NO_CHANGE   = 4,    /**< No Change */
++    HDMITX_VOUT_PREFIL_INVALID     = 5     /**< Invalid   */
++} tmbslHdmiTxVoutPrefil_t;
++
++/** YUV blanking */
++typedef enum
++{
++    HDMITX_VOUT_YUV_BLNK_16        = 0,    /**< 16 */
++    HDMITX_VOUT_YUV_BLNK_0         = 1,    /**< 0  */
++    HDMITX_VOUT_YUV_BLNK_NO_CHANGE = 2,    /**< No Change */
++    HDMITX_VOUT_YUV_BLNK_INVALID   = 3     /**< Invalid   */
++} tmbslHdmiTxVoutYuvBlnk_t;
++
++/** Video quantization range */
++typedef enum
++{
++    HDMITX_VOUT_QRANGE_FS          = 0,    /**< Full Scale */
++    HDMITX_VOUT_QRANGE_RGB_YUV     = 1,    /**< RGB Or YUV */
++    HDMITX_VOUT_QRANGE_YUV         = 2,    /**< YUV        */
++    HDMITX_VOUT_QRANGE_NO_CHANGE   = 3,    /**< No Change  */
++    HDMITX_VOUT_QRANGE_INVALID     = 4     /**< Invalid    */
++} tmbslHdmiTxVoutQrange_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984VideoOutSetSync() parameter types
++ */
++/** Video sync source */
++typedef enum
++{
++    HDMITX_VSSRC_INTERNAL      = 0,    /**< Internal  */
++    HDMITX_VSSRC_EXTERNAL      = 1,    /**< External  */
++    HDMITX_VSSRC_NO_CHANGE     = 2,    /**< No change */
++    HDMITX_VSSRC_INVALID       = 3     /**< Invalid   */
++} tmbslHdmiTxVsSrc_t;
++ 
++/** Video sync toggle */
++typedef enum
++{
++    HDMITX_VSTGL_TABLE         = 0,    /**< Vs/Hs polarity from table */
++    HDMITX_VSTGL_UNUSED_1      = 1,    /**< Unused          */
++    HDMITX_VSTGL_UNUSED_2      = 2,    /**< Unused          */
++    HDMITX_VSTGL_UNUSED_3      = 3,    /**< Unused          */
++    HDMITX_VSTGL_NO_ACTION     = 4,    /**< No toggle       */
++    HDMITX_VSTGL_HS            = 5,    /**< Toggle Hs       */
++    HDMITX_VSTGL_VS            = 6,    /**< Toggle Vs       */
++    HDMITX_VSTGL_HS_VS         = 7,    /**< Toggle Hs & Vs  */
++    HDMITX_VSTGL_NO_CHANGE     = 8,    /**< No change       */
++    HDMITX_VSTGL_INVALID       = 9     /**< Invalid         */
++} tmbslHdmiTxVsTgl_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984VideoSetInOut() parameter types
++ */
++/** Pixel repetition values */
++enum _tmbslHdmiTxPixRepeat
++{
++    HDMITX_PIXREP_NONE       = 0,    /**< No repetition  */
++    HDMITX_PIXREP_MIN        = 0,    /**< 1 repetition   */
++
++    HDMITX_PIXREP_0 = 0,
++    HDMITX_PIXREP_1 = 1,
++    HDMITX_PIXREP_2 = 2,
++    HDMITX_PIXREP_3 = 3,
++    HDMITX_PIXREP_4 = 4,
++    HDMITX_PIXREP_5 = 5,
++    HDMITX_PIXREP_6 = 6,
++    HDMITX_PIXREP_7 = 7,
++    HDMITX_PIXREP_8 = 8,
++    HDMITX_PIXREP_9 = 9,
++
++    HDMITX_PIXREP_MAX        = 9,    /**< 10 repetitions */
++    HDMITX_PIXREP_DEFAULT    = 10,   /**< Default repetitions for output format */
++    HDMITX_PIXREP_NO_CHANGE  = 11,   /**< No change */
++    HDMITX_PIXREP_INVALID    = 12    /**< Invalid   */
++};
++
++/** Matrix modes */
++typedef enum
++{
++    HDMITX_MATMODE_OFF       = 0,    /**< Off  */
++    HDMITX_MATMODE_AUTO      = 1,    /**< Auto */
++    HDMITX_MATMODE_NO_CHANGE = 2,    /**< No change */
++    HDMITX_MATMODE_INVALID   = 3     /**< Invalid   */
++} tmbslHdmiTxMatMode_t;
++ 
++/** Datapath bitwidth */
++typedef enum
++{
++    HDMITX_VOUT_DBITS_12           = 0,    /**< 12 bits */
++    HDMITX_VOUT_DBITS_8            = 1,    /**< 8 bits  */
++    HDMITX_VOUT_DBITS_10           = 2,    /**< 10 bits */
++    HDMITX_VOUT_DBITS_NO_CHANGE    = 3,    /**< No change */
++    HDMITX_VOUT_DBITS_INVALID      = 4     /**< Invalid   */
++} tmbslHdmiTxVoutDbits_t;
++
++/** Color depth */
++typedef enum
++{
++    HDMITX_COLORDEPTH_24           = 0,    /**< 24 bits per pixel */
++    HDMITX_COLORDEPTH_30           = 1,    /**< 30 bits per pixel */
++    HDMITX_COLORDEPTH_36           = 2,    /**< 36 bits per pixel */
++    HDMITX_COLORDEPTH_48           = 3,    /**< 48 bits per pixel */
++    HDMITX_COLORDEPTH_NO_CHANGE    = 4,    /**< No change */
++    HDMITX_COLORDEPTH_INVALID      = 5     /**< Invalid   */
++} tmbslHdmiTxColorDepth;
++
++/** the supported transmission formats of 3D video data */
++typedef enum
++{
++    HDMITX_3D_NONE                 = 0,    /**< 3D video data not present */
++    HDMITX_3D_FRAME_PACKING        = 1,    /**< 3D video data Frame Packing structure */
++    HDMITX_3D_TOP_AND_BOTTOM       = 2,    /**< 3D video data Top and Bottom structure */
++    HDMITX_3D_SIDE_BY_SIDE_HALF    = 3,    /**< 3D video data Side by Side Half structure */
++    HDMITX_3D_INVALID              = 4     /**< Invalid */
++} tmbslHdmiTx3DStructure_t;
++
++/*============================================================================*/
++/**
++ * tmbslTDA9984MatrixSetInputOffset() parameter type
++ */
++/** Parameter structure array size */
++enum _tmbslHdmiTxMatOffset
++{
++    HDMITX_MAT_OFFSET_NUM = 3
++};
++
++/** \brief The tmbslTDA9984MatrixSetInputOffset() parameter structure */
++typedef struct _tmbslHdmiTxMatOffset_t
++{
++    /** Offset array  (values -1024 to +1023) */
++    Int16 Offset[HDMITX_MAT_OFFSET_NUM];
++} tmbslHdmiTxMatOffset_t;
++
++/** Matrix numeric limits */
++enum _tmbslHdmiTxMatLimits
++{
++    HDMITX_MAT_OFFSET_MIN      = -1024,
++    HDMITX_MAT_OFFSET_MAX      = 1023
++};
++
++/*============================================================================*/
++/**
++ * tmbslTDA9989PowerSetState() and tmbslTDA9989PowerGetState() parameter types
++ */
++typedef enum
++{
++    HDMITX_POWER_STATE_STAND_BY             = 0,   /**< Stand by mode        */
++    HDMITX_POWER_STATE_SLEEP_MODE           = 1,   /**< Sleep mode           */
++    HDMITX_POWER_STATE_ON                   = 2,   /**< On mode      */
++    HDMITX_POWER_STATE_INVALID              = 3    /**< Invalid format       */
++} tmbslHdmiTxPowerState_t;
++
++/**
++ * \brief Structure describing gamut metadata packet (P0 or P1 profiles)
++ */
++typedef struct
++{
++    UInt8  HB[3];  /**< Header bytes (HB0, HB1 & HB2) */
++    UInt8  PB[28]; /**< Payload bytes 0..27 */
++} tmbslHdmiTxPktGamut_t;
++
++
++/**
++ * \brief Structure describing RAW AVI infoframe
++ */
++typedef struct
++{
++    UInt8  HB[3];  /**< Header bytes (HB0, HB1 & HB2) */
++    UInt8  PB[28]; /**< Payload bytes 0..27 */
++} tmbslHdmiTxPktRawAvi_t;
++
++
++/** Sink category */
++typedef enum
++{
++    HDMITX_SINK_CAT_NOT_REPEATER    = 0, /**< Not repeater  */
++    HDMITX_SINK_CAT_REPEATER        = 1, /**< repeater      */   
++    HDMITX_SINK_CAT_INVALID         = 3  /**< Invalid       */
++} tmbslHdmiTxSinkCategory_t;
++
++
++typedef struct
++{
++    Bool   latency_available;
++    Bool   Ilatency_available;
++    UInt8  Edidvideo_latency;
++    UInt8  Edidaudio_latency;
++    UInt8  EdidIvideo_latency;
++    UInt8  EdidIaudio_latency;
++
++} tmbslHdmiTxEdidLatency_t;
++
++/**
++ * \brief Structure defining additional VSDB data
++ */
++typedef struct
++{
++    UInt8 maxTmdsClock;      /* maximum supported TMDS clock */
++    UInt8 cnc0;              /* content type Graphics (text) */
++    UInt8 cnc1;              /* content type Photo */
++    UInt8 cnc2;              /* content type Cinema */
++    UInt8 cnc3;              /* content type Game */
++    UInt8 hdmiVideoPresent;  /* additional video format */
++    UInt8 h3DPresent;        /* 3D support by the HDMI Sink */
++    UInt8 h3DMultiPresent;   /* 3D multi strctures present */
++    UInt8 imageSize;         /* additional info for the values in the image size area */
++    UInt8 hdmi3DLen;         /* total length of 3D video formats */
++    UInt8 hdmiVicLen;        /* total length of extended video formats */
++    UInt8 ext3DData[21];     /* max_len-10, ie: 31-10=21 */
++} tmbslHdmiTxEdidExtraVsdbData_t;
++
++/**
++ * \brief Enum defining possible quantization range
++ */
++typedef enum
++{
++    HDMITX_VQR_DEFAULT = 0, /* Follow HDMI spec. */
++    HDMITX_RGB_FULL    = 1, /* Force RGB FULL , DVI only */
++    HDMITX_RGB_LIMITED = 2  /* Force RGB LIMITED , DVI only */
++} tmbslHdmiTxVQR_t;
++
++
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMBSLHDMITX_TYPES_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/inc/tmbslHdmiTx_funcMapping.h b/drivers/video/nxp/comps/tmbslTDA9989/inc/tmbslHdmiTx_funcMapping.h
+new file mode 100755
+index 0000000..8fc3084
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/inc/tmbslHdmiTx_funcMapping.h
+@@ -0,0 +1,141 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslHdmiTx_funcMapping.h
++ *
++ * \version       $Revision: 2 $
++ *
++*/
++
++
++
++#ifndef TMDLHDMITXTDA9989_CFG_H
++#define TMDLHDMITXTDA9989_CFG_H
++
++#include "tmbslTDA9989_Functions.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define tmbslHdmiTxInit                             tmbslTDA9989Init
++#define tmbslHdmiTxEdidRequestBlockData             tmbslTDA9989EdidRequestBlockData
++#define tmbslHdmiTxVideoOutSetConfig                tmbslTDA9989VideoOutSetConfig
++#define tmbslHdmiTxAudioInResetCts                  tmbslTDA9989AudioInResetCts
++#define tmbslHdmiTxAudioInSetConfig                 tmbslTDA9989AudioInSetConfig
++#define tmbslHdmiTxAudioInSetCts                    tmbslTDA9989AudioInSetCts
++#define tmbslHdmiTxAudioOutSetChanStatus            tmbslTDA9989AudioOutSetChanStatus
++#define tmbslHdmiTxAudioOutSetChanStatusMapping     tmbslTDA9989AudioOutSetChanStatusMapping
++#define tmbslHdmiTxAudioOutSetMute                  tmbslTDA9989AudioOutSetMute
++#define tmbslHdmiTxDeinit                           tmbslTDA9989Deinit
++#define tmbslHdmiTxEdidGetAudioCapabilities         tmbslTDA9989EdidGetAudioCapabilities
++#define tmbslHdmiTxEdidGetBlockCount                tmbslTDA9989EdidGetBlockCount
++#define tmbslHdmiTxEdidGetStatus                    tmbslTDA9989EdidGetStatus
++#define tmbslHdmiTxEdidGetSinkType                  tmbslTDA9989EdidGetSinkType
++#define tmbslHdmiTxEdidGetSourceAddress             tmbslTDA9989EdidGetSourceAddress
++#define tmbslHdmiTxEdidGetVideoCapabilities         tmbslTDA9989EdidGetVideoCapabilities
++#define tmbslHdmiTxEdidGetVideoPreferred            tmbslTDA9989EdidGetVideoPreferred
++#define tmbslHdmiTxHdcpCheck                        tmbslTDA9989HdcpCheck
++#define tmbslHdmiTxHdcpConfigure                    tmbslTDA9989HdcpConfigure
++#define tmbslHdmiTxHdcpDownloadKeys                 tmbslTDA9989HdcpDownloadKeys
++#define tmbslHdmiTxHdcpEncryptionOn                 tmbslTDA9989HdcpEncryptionOn
++#define tmbslHdmiTxHdcpGetOtp                       tmbslTDA9989HdcpGetOtp
++#define tmbslHdmiTxHdcpGetT0FailState               tmbslTDA9989HdcpGetT0FailState
++#define tmbslHdmiTxHdcpHandleBCAPS                  tmbslTDA9989HdcpHandleBCAPS
++#define tmbslHdmiTxHdcpHandleBKSV                   tmbslTDA9989HdcpHandleBKSV
++#define tmbslHdmiTxHdcpHandleBKSVResult             tmbslTDA9989HdcpHandleBKSVResult
++#define tmbslHdmiTxHdcpHandleBSTATUS                tmbslTDA9989HdcpHandleBSTATUS
++#define tmbslHdmiTxHdcpHandleENCRYPT                tmbslTDA9989HdcpHandleENCRYPT
++#define tmbslHdmiTxHdcpHandlePJ                     tmbslTDA9989HdcpHandlePJ
++#define tmbslHdmiTxHdcpHandleSHA_1                  tmbslTDA9989HdcpHandleSHA_1
++#define tmbslHdmiTxHdcpHandleSHA_1Result            tmbslTDA9989HdcpHandleSHA_1Result
++#define tmbslHdmiTxHdcpHandleT0                     tmbslTDA9989HdcpHandleT0
++#define tmbslHdmiTxHdcpInit                         tmbslTDA9989HdcpInit
++#define tmbslHdmiTxHdcpRun                          tmbslTDA9989HdcpRun
++#define tmbslHdmiTxHdcpStop                         tmbslTDA9989HdcpStop
++#define tmbslHdmiTxHotPlugGetStatus                 tmbslTDA9989HotPlugGetStatus
++#define tmbslHdmiTxRxSenseGetStatus                 tmbslTDA9989RxSenseGetStatus
++#define tmbslHdmiTxHwGetRegisters                   tmbslTDA9989HwGetRegisters
++#define tmbslHdmiTxHwGetVersion                     tmbslTDA9989HwGetVersion
++#define tmbslHdmiTxHwGetCapabilities                tmbslTDA9989HwGetCapabilities
++#define tmbslHdmiTxHwHandleInterrupt                tmbslTDA9989HwHandleInterrupt
++#define tmbslHdmiTxHwSetRegisters                   tmbslTDA9989HwSetRegisters
++#define tmbslHdmiTxHwStartup                        tmbslTDA9989HwStartup
++#define tmbslHdmiTxMatrixSetCoeffs                  tmbslTDA9989MatrixSetCoeffs
++#define tmbslHdmiTxMatrixSetConversion              tmbslTDA9989MatrixSetConversion
++#define tmbslHdmiTxMatrixSetInputOffset             tmbslTDA9989MatrixSetInputOffset
++#define tmbslHdmiTxMatrixSetMode                    tmbslTDA9989MatrixSetMode
++#define tmbslHdmiTxMatrixSetOutputOffset            tmbslTDA9989MatrixSetOutputOffset
++#define tmbslHdmiTxPktSetAclkRecovery               tmbslTDA9989PktSetAclkRecovery
++#define tmbslHdmiTxPktSetAcp                        tmbslTDA9989PktSetAcp
++#define tmbslHdmiTxPktSetAudioInfoframe             tmbslTDA9989PktSetAudioInfoframe
++#define tmbslHdmiTxPktSetGeneralCntrl               tmbslTDA9989PktSetGeneralCntrl
++#define tmbslHdmiTxPktSetIsrc1                      tmbslTDA9989PktSetIsrc1
++#define tmbslHdmiTxPktSetIsrc2                      tmbslTDA9989PktSetIsrc2
++#define tmbslHdmiTxPktSetMpegInfoframe              tmbslTDA9989PktSetMpegInfoframe
++#define tmbslHdmiTxPktSetNullInsert                 tmbslTDA9989PktSetNullInsert
++#define tmbslHdmiTxPktSetNullSingle                 tmbslTDA9989PktSetNullSingle
++#define tmbslHdmiTxPktSetSpdInfoframe               tmbslTDA9989PktSetSpdInfoframe
++#define tmbslHdmiTxPktSetVideoInfoframe             tmbslTDA9989PktSetVideoInfoframe
++#define tmbslHdmiTxPktSetVsInfoframe                tmbslTDA9989PktSetVsInfoframe
++#define tmbslHdmiTxPktSetRawVideoInfoframe          tmbslTDA9989PktSetRawVideoInfoframe
++#define tmbslHdmiTxPowerGetState                    tmbslTDA9989PowerGetState
++#define tmbslHdmiTxPowerSetState                    tmbslTDA9989PowerSetState
++#define tmbslHdmiTxReset                            tmbslTDA9989Reset
++#define tmbslHdmiTxScalerGet                        tmbslTDA9989ScalerGet
++#define tmbslHdmiTxScalerGetMode                    tmbslTDA9989ScalerGetMode
++#define tmbslHdmiTxScalerInDisable                  tmbslTDA9989ScalerInDisable
++#define tmbslHdmiTxScalerSetCoeffs                  tmbslTDA9989ScalerSetCoeffs
++#define tmbslHdmiTxScalerSetFieldOrder              tmbslTDA9989ScalerSetFieldOrder
++#define tmbslHdmiTxScalerSetFine                    tmbslTDA9989ScalerSetFine
++#define tmbslHdmiTxScalerSetPhase                   tmbslTDA9989ScalerSetPhase
++#define tmbslHdmiTxScalerSetLatency                 tmbslTDA9989ScalerSetLatency
++#define tmbslHdmiTxScalerSetSync                    tmbslTDA9989ScalerSetSync
++#define tmbslHdmiTxSwGetVersion                     tmbslTDA9989SwGetVersion
++#define tmbslHdmiTxSysTimerWait                     tmbslTDA9989SysTimerWait
++#define tmbslHdmiTxTmdsSetOutputs                   tmbslTDA9989TmdsSetOutputs
++#define tmbslHdmiTxTmdsSetSerializer                tmbslTDA9989TmdsSetSerializer
++#define tmbslHdmiTxTestSetPattern                   tmbslTDA9989TestSetPattern
++#define tmbslHdmiTxTestSetMode                      tmbslTDA9989TestSetMode
++#define tmbslHdmiTxVideoInSetBlanking               tmbslTDA9989VideoInSetBlanking
++#define tmbslHdmiTxVideoInSetConfig                 tmbslTDA9989VideoInSetConfig
++#define tmbslHdmiTxVideoInSetFine                   tmbslTDA9989VideoInSetFine
++#define tmbslHdmiTxVideoInSetMapping                tmbslTDA9989VideoInSetMapping
++#define tmbslHdmiTxSetVideoPortConfig               tmbslTDA9989SetVideoPortConfig
++#define tmbslHdmiTxSetAudioPortConfig               tmbslTDA9989SetAudioPortConfig
++#define tmbslHdmiTxSetAudioClockPortConfig          tmbslTDA9989SetAudioClockPortConfig
++#define tmbslHdmiTxVideoInSetSyncAuto               tmbslTDA9989VideoInSetSyncAuto
++#define tmbslHdmiTxVideoInSetSyncManual             tmbslTDA9989VideoInSetSyncManual
++#define tmbslHdmiTxVideoOutDisable                  tmbslTDA9989VideoOutDisable
++#define tmbslHdmiTxVideoOutSetSync                  tmbslTDA9989VideoOutSetSync
++#define tmbslHdmiTxVideoSetInOut                    tmbslTDA9989VideoSetInOut
++#define tmbslHdmiTxFlagSwInt                        tmbslTDA9989FlagSwInt
++#define tmbslHdmiTxSet5vpower                       tmbslTDA9989Set5vpower
++#define tmbslHdmiTxEnableCallback                   tmbslTDA9989EnableCallback
++#define tmbslHdmiTxSetColorDepth                    tmbslTDA9989SetColorDepth
++#define tmbslHdmiTxSetDefaultPhase                  tmbslTDA9989SetDefaultPhase
++#define tmbslHdmiTxPktFillGamut                     tmbslTDA9989PktFillGamut
++#define tmbslHdmiTxPktSendGamut                     tmbslTDA9989PktSendGamut
++#define tmbslHdmiTxEdidGetMonitorDescriptors        tmbslTDA9989EdidGetMonitorDescriptors
++#define tmbslHdmiTxEdidGetDetailedTimingDescriptors tmbslTDA9989EdidGetDetailedTimingDescriptors
++#define tmbslHdmiTxEdidGetBasicDisplayParam         tmbslTDA9989EdidGetBasicDisplayParam
++#define tmbslHdmiTxHdcpGetSinkCategory              tmbslTDA9989HdcpGetSinkCategory
++#define tmbslHdmiTxEdidGetLatencyInfo               tmbslTDA9989EdidGetLatencyInfo
++#define tmbslHdmiTxEdidGetExtraVsdbData             tmbslTDA9989EdidGetExtraVsdbData
++#ifdef TMFL_TDA19989
++#define tmbslHdmiTxHdcpPowerDown                    tmbslTDA9989HdcpPowerDown
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMITXTDA9989_CFG_H */
++
++/*============================================================================*/
++/*                               END OF FILE                                  */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/inc/tmbslTDA9989_Functions.h b/drivers/video/nxp/comps/tmbslTDA9989/inc/tmbslTDA9989_Functions.h
+new file mode 100755
+index 0000000..0f9a3e3
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/inc/tmbslTDA9989_Functions.h
+@@ -0,0 +1,3060 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_functions.h
++ *
++ * \version       $Revision: 2 $
++ *
++ *
++*/
++
++#ifndef TMBSLTDA9989_FUNCTIONS_H
++#define TMBSLTDA9989_FUNCTIONS_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#include "tmNxCompId.h"
++#include "tmbslHdmiTx_types.h"
++
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++
++/*============================================================================*/
++/**
++    \brief      Reset the Clock Time Stamp generator in HDMI mode only
++
++    \param[in]  txUnit      Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: in DVI mode
++ */
++tmErrorCode_t
++tmbslTDA9989AudioInResetCts
++(
++    tmUnitSelect_t      txUnit
++);
++
++/**
++    \brief      Set audio input configuration in HDMI mode only
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  aFmt        Audio input format
++    \param[in]  i2sFormat   I2s format type
++    \param[in]  chanI2s     I2S channel allocation
++    \param[in]  chanDsd     DSD channel allocation
++    \param[in]  clkPolDsd   DSD clock polarity
++    \param[in]  swapDsd     DSD data swap
++    \param[in]  layout      Sample layout
++    \param[in]  latency_rd  Audio FIFO read latency
++    \param[in]  dstRate     Dst rate (not used)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: in DVI mode
++ */
++tmErrorCode_t
++tmbslTDA9989AudioInSetConfig
++(
++    tmUnitSelect_t           txUnit,
++    tmbslHdmiTxaFmt_t        aFmt,
++    tmbslHdmiTxI2sFor_t      i2sFormat,
++    UInt8                    chanI2s,
++    UInt8                    chanDsd,
++    tmbslHdmiTxClkPolDsd_t   clkPolDsd,
++    tmbslHdmiTxSwapDsd_t     swapDsd,
++    UInt8                    layout,
++    UInt16                   latency_rd,
++    tmbslHdmiTxDstRate_t     dstRate
++);
++
++
++/**
++    \brief      Set the Clock Time Stamp generator in HDMI mode only
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  ctsRef      Clock Time Stamp reference source
++    \param[in]  afs         Audio input sample frequency
++    \param[in]  voutFmt     Video output format
++    \param[in]  voutFreq    Vertical output frequency
++    \param[in]  uCts        Manual Cycle Time Stamp
++    \param[in]  uCtsX       Clock Time Stamp factor x
++    \param[in]  ctsK        Clock Time Stamp predivider k
++    \param[in]  ctsM        Clock Time Stamp postdivider m
++    \param[in]  dstRate     Dst rate (not used)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: in DVI mode
++ */
++tmErrorCode_t
++tmbslTDA9989AudioInSetCts
++(
++    tmUnitSelect_t       txUnit,
++    tmbslHdmiTxctsRef_t  ctsRef,
++    tmbslHdmiTxafs_t     afs, 
++    tmbslHdmiTxVidFmt_t  voutFmt, 
++    tmbslHdmiTxVfreq_t   voutFreq, 
++    UInt32               uCts, 
++    UInt16               uCtsX,
++    tmbslHdmiTxctsK_t    ctsK,
++    tmbslHdmiTxctsM_t    ctsM,
++    tmbslHdmiTxDstRate_t dstRate
++);
++
++/**
++    \brief      Set the Channel Status Bytes 0,1,3 & 4
++
++    \param[in]  txUnit              Transmitter unit number
++    \param[in]  copyright           Byte 0 Copyright bit (bit2)
++    \param[in]  formatInfo          Byte 0 Audio sample format (bit1) and additional info (bit345)
++    \param[in]  categoryCode        Byte 1 Category code (bits8-15)
++    \param[in]  sampleFreq          Byte 3 Sample Frequency (bits24-27)
++    \param[in]  clockAccuracy       Byte 3 Clock Accuracy (bits38-31)
++    \param[in]  maxWordLength       Byte 4 Maximum word length (bit32)
++    \param[in]  wordLength          Byte 4 Word length (bits33-35)
++    \param[in]  origSampleFreq      Byte 4 Original Sample Frequency (bits36-39)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: in DVI mode
++
++    \note       The consumer use bit (bit0) and Mode bits (bits6-7) are forced to zero.
++                Use tmbslTDA9989AudioOutSetChanStatusMapping to set CS Byte 2.
++
++ */
++tmErrorCode_t
++tmbslTDA9989AudioOutSetChanStatus
++(
++    tmUnitSelect_t               txUnit,
++    tmbslHdmiTxAudioData_t       pcmIdentification,
++    tmbslHdmiTxCSformatInfo_t    formatInfo,
++    tmbslHdmiTxCScopyright_t     copyright,
++    UInt8                        categoryCode,
++    tmbslHdmiTxafs_t             sampleFreq,
++    tmbslHdmiTxCSclkAcc_t        clockAccuracy,
++    tmbslHdmiTxCSmaxWordLength_t maxWordLength,
++    tmbslHdmiTxCSwordLength_t    wordLength,
++    tmbslHdmiTxCSorigAfs_t       origSampleFreq
++);
++
++/**
++    \brief      Set the Channel Status Byte2 for Audio Port 0
++
++    \param[in]  txUnit              Transmitter unit number
++    \param[in]  sourceLeft          L Source Number: 0 don't take into account, 1-15
++    \param[in]  channelLeft         L Channel Number: 0 don't take into account, 1-15
++    \param[in]  sourceRight         R Source Number: 0 don't take into account, 1-15
++    \param[in]  channelRight        R Channel Number: 0 don't take into account, 1-15
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: in DVI mode
++
++    \note       Use tmbslTDA9989AudioOutSetChanStatus to set all other CS bytes
++                This function only sets the mapping for Audio Port 0.
++
++ */
++tmErrorCode_t
++tmbslTDA9989AudioOutSetChanStatusMapping
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           sourceLeft[4],
++    UInt8           channelLeft[4],
++    UInt8           sourceRight[4],
++    UInt8           channelRight[4]
++);
++
++/**
++    \brief      Mute or un-mute the audio output by controlling the audio FIFO,
++                in HDMI mode only
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  aMute       Audio mute: On, Off
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: in DVI mode
++
++    \note       tmbslTDA9989PktSetGeneralCntrl must be used to control the audio
++                mute in outgoing data island packets
++
++ */
++tmErrorCode_t
++tmbslTDA9989AudioOutSetMute
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxaMute_t aMute
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Disable an HDMI Transmitter output and destroy its driver 
++                instance
++
++    \param[in]  txUnit Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number 
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: the unit is not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t 
++tmbslTDA9989Deinit
++(
++    tmUnitSelect_t      txUnit
++);
++
++
++/**
++    \brief      Get supported audio format(s) from previously read EDID
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pEdidAFmts  Pointer to the array of structures to receive the 
++                            supported Short Audio Descriptors
++    \param[in]  aFmtLength  Number of SADs supported in buffer pEdidAFmts,
++                            up to HDMI_TX_SAD_MAX_CNT
++    \param[out] pAFmtsAvail Pointer to receive the number of SADs available
++    \param[out] pAudioFlags Pointer to the byte to receive the Audio Capability
++                            Flags
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++    
++    \note \verbatim
++                Supported Short Audio Descriptors array:
++                EdidAFmts[0].ModeChans      SAD 1  - Mode byte
++                EdidAFmts[0].Freqs	        SAD 1  - Frequencies byte
++                EdidAFmts[0].Byte3          SAD 1  - Byte 3
++                ...
++                EdidAFmts[n-1].ModeChans    SAD n  - Mode byte
++                EdidAFmts[n-1].Freqs	    SAD n  - Frequencies byte
++                EdidAFmts[n-1].Byte3        SAD n  - Byte 3
++                (Where n is the smaller of aFmtLength and pAFmtAvail)
++    \endverbatim
++ */
++tmErrorCode_t
++tmbslTDA9989EdidGetAudioCapabilities
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxEdidSad_t    *pEdidAFmts,
++    UInt                    aFmtLength,
++    UInt                    *pAFmtsAvail,
++    UInt8                   *pAudioFlags
++);
++
++/*============================================================================*/
++/**
++    \brief      Get the EDID block count
++
++    \param[in]  txUnit              Transmitter unit number
++    \param[out] puEdidBlockCount    Pointer to data byte in which to return the
++                                    block count
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t
++tmbslTDA9989EdidGetBlockCount
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *puEdidBlockCount
++);
++
++/*============================================================================*/
++/**
++    \brief      Get the EDID status
++
++    \param[in]  txUnit              Transmitter unit number
++    \param[out] puEdidBlockCount    Pointer to data byte in which to return the
++                                    edid status
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t
++tmbslTDA9989EdidGetStatus
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *puEdidStatus
++);
++
++/**
++    \brief      Request read of EDID blocks from the sink device via DDC
++                function not synchronous edid will available on 
++                EDID_BLK_READ callback
++                
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pRawEdid    Pointer to a buffer supplied by the caller to accept
++                            the raw EDID data.
++    \param[in]  numBlocks   Number of blocks to read
++    \param[in]  lenRawEdid  Length in bytes of the supplied buffer
++    \param[out] pEdidStatus Pointer to status value E_EDID_READ or E_EDID_ERROR
++                            valid only when the return value is TM_OK
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE: EDID not read
++
++    \note       NA
++
++ */
++
++tmErrorCode_t
++tmbslTDA9989EdidRequestBlockData
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pRawEdid, 
++    Int             numBlocks,  /* Only relevant if pRawEdid valid */
++    Int             lenRawEdid  /* Only relevant if pRawEdid valid */
++);
++
++
++/**
++    \brief      Get Sink Type by analysis of EDID content
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pSinkType   Pointer to returned Sink Type: DVI or HDMI
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : edid not read
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NULL_CONNECTION: HPD pin is inactive
++    
++    \sa         tmbslTDA9989EdidGetBlockData
++ */
++tmErrorCode_t
++tmbslTDA9989EdidGetSinkType
++(
++    tmUnitSelect_t              txUnit,
++    tmbslHdmiTxSinkType_t      *pSinkType 
++);
++
++/*============================================================================*/
++/**
++    \brief      Get Source Physical Address by analysis of EDID content
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[out] pSourceAddress  Pointer to returned Source Physical Address (ABCDh)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++    
++    \sa         tmbslTDA9989EdidGetBlockData
++ */
++tmErrorCode_t
++tmbslTDA9989EdidGetSourceAddress
++(
++    tmUnitSelect_t  txUnit,
++    UInt16          *pSourceAddress 
++);
++
++/**
++    \brief      Get supported video format(s) from previously read EDID
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pEdidVFmts  Pointer to the array to receive the supported Short
++                            Video Descriptors
++    \param[in]  vFmtLength  Number of SVDs supported in buffer pEdidVFmts,
++                            up to HDMI_TX_SVD_MAX_CNT
++    \param[out] pVFmtsAvail Pointer to receive the number of SVDs available
++    \param[out] pVidFlags   Ptr to the byte to receive Video Capability Flags
++                            b7: underscan supported
++                            b6: YCbCr 4:4:4 supported
++                            b5: YCbCr 4:2:2 supported
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NULL_CONNECTION: HPD pin is inactive
++    
++    \note \verbatim
++                Supported Short Video Descriptors array:
++                    (HDMI_TX_SVD_NATIVE_MASK bit set to indicate native format)
++                EdidVFmts[0]   EIA/CEA Short Video Descriptor 1, or 0
++                ...
++                EdidVFmts[n-1]  EIA/CEA Short Video Descriptor 32, or 0
++                (Where n is the smaller of vFmtLength and pVFmtAvail)
++    \endverbatim
++    \sa         tmbslTDA9989EdidGetBlockData
++ */
++tmErrorCode_t
++tmbslTDA9989EdidGetVideoCapabilities
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pEdidVFmts,
++    UInt            vFmtLength,
++    UInt            *pVFmtsAvail,
++    UInt8           *pVidFlags
++);
++/**
++    \brief      Get detailed timing descriptor from previously read EDID
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pEdidDTD    Pointer to the array to receive the Detailed timing descriptor
++
++    \param[in]  nb_size     Number of DTD supported in buffer pEdidDTD
++
++    \param[out] pDTDAvail Pointer to receive the number of DTD available
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++*/
++tmErrorCode_t
++tmbslTDA9989EdidGetDetailedTimingDescriptors
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxEdidDtd_t    *pEdidDTD,
++    UInt8                   nb_size,
++    UInt8                   *pDTDAvail
++);
++
++/**
++    \brief      Get detailed Monitor descriptor from previously read EDID
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[out] pEdidFirstMD    Pointer to the First Monitor descriptor
++    \param[out] pEdidSecondMD   Pointer to the Second Monitor descriptor
++    \param[out] pEdidOtherMD    Pointer to the Other Monitor descriptor
++    \param[in]  sizeOtherMD     Not used
++    \param[out] pOtherMDAvail   Not used
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++*/
++tmErrorCode_t
++tmbslTDA9989EdidGetMonitorDescriptors
++(
++    tmUnitSelect_t              txUnit,
++    tmbslHdmiTxEdidFirstMD_t    *pEdidFirstMD,
++    tmbslHdmiTxEdidSecondMD_t   *pEdidSecondMD,
++    tmbslHdmiTxEdidOtherMD_t    *pEdidOtherMD,
++    UInt8                       sizeOtherMD,
++    UInt8                       *pOtherMDAvail
++);
++
++/**
++    \brief      Get basic display parameters from previously read EDID
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[out] pEdidBDParam    Pointer to the Basic Display Parameters
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++*/
++tmErrorCode_t
++tmbslTDA9989EdidGetBasicDisplayParam
++(
++    tmUnitSelect_t              txUnit,
++    tmbslHdmiTxEdidBDParam_t    *pEdidBDParam
++);
++
++
++/**
++    \brief      Get preferred video format from previously read EDID
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pEdidDTD    Pointer to the structure to receive the Detailed
++                            Timing Descriptor parameters of the preferred video
++                            format
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NULL_CONNECTION: HPD pin is inactive
++
++    \note \verbatim      
++                Detailed Timing Descriptor parameters output structure:
++                UInt16 uPixelClock      Pixel Clock (MHz/10,000)
++                UInt16 uHActivePixels   Horizontal Active Pixels
++                UInt16 uHBlankPixels    Horizontal Blanking Pixels
++                UInt16 uVActiveLines    Vertical Active Lines
++                UInt16 uVBlankLines     Vertical Blanking Lines
++                UInt16 uHSyncOffset     Horizontal Sync Offset (Pixels)
++                UInt16 uHSyncWidth      Horizontal Sync Pulse Width (Pixels)
++                UInt16 uVSyncOffset     Vertical Sync Offset (Lines)
++                UInt16 uVSyncWidth      Vertical Sync Pulse Width (Lines)
++                UInt16 uHImageSize      Horizontal Image Size (mm)
++                UInt16 uVImageSize      Vertical Image Size (mm)
++                UInt16 uHBorderPixels   Horizontal Border (Pixels)
++                UInt16 uVborderPixels   Vertical Border (Pixels)
++                UInt8 Flags             Interlace/sync info
++    \endverbatim
++    \sa         tmbslTDA9989EdidGetBlockData
++ */
++tmErrorCode_t
++tmbslTDA9989EdidGetVideoPreferred
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxEdidDtd_t    *pEdidDTD
++);
++
++/**
++    \brief      Check the result of an HDCP encryption attempt, called at
++                intervals (set by uTimeSinceLastCallMs) after tmbslTDA9989HdcpRun
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit                  Transmitter unit number
++    \param[in]  uTimeSinceLastCallMs    Time in ms since this was last called
++    \param[out] pResult                 The outcome of the check
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++ */
++tmErrorCode_t
++tmbslTDA9989HdcpCheck
++(
++    tmUnitSelect_t	        txUnit,
++    UInt16                  uTimeSinceLastCallMs,
++    tmbslHdmiTxHdcpCheck_t  *pResult
++);
++
++/**
++    \brief      Configure various HDCP parameters
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  slaveAddress    DDC I2C slave address
++    \param[in]  txMode          Mode of our transmitter device
++    \param[in]  options         Options flags to control behaviour of HDCP
++    \param[in]  uCheckIntervalMs HDCP check interval in milliseconds
++    \param[in]  uChecksToDo     Number of HDCP checks to do after HDCP starts
++                                A value of 2 or more is valid for checking
++                                May be set to 0 to disabling checking
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++
++    \note       Must be called before all other HDCP APIs
++ */
++tmErrorCode_t
++tmbslTDA9989HdcpConfigure
++(
++    tmUnitSelect_t	         txUnit,
++    UInt8                    slaveAddress,
++    tmbslHdmiTxHdcpTxMode_t  txMode,
++    tmbslHdmiTxHdcpOptions_t options,
++    UInt16                   uCheckIntervalMs,
++    UInt8                    uChecksToDo
++);
++
++/**
++    \brief      Download keys and AKSV data from OTP memory to the device
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  seed            Seed value
++    \param[in]  keyDecryption   State of key decryption 0 to 1 (disabled, enabled)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++ */
++tmErrorCode_t
++tmbslTDA9989HdcpDownloadKeys
++(
++    tmUnitSelect_t	        txUnit,
++    UInt16                  seed,
++    tmbslHdmiTxDecrypt_t    keyDecryption
++);
++
++/*============================================================================*/
++/**
++    \brief      Switch HDCP encryption on or off without disturbing Infoframes
++                (Not normally used)
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit  Transmitter unit number
++    \param[in]  bOn     Encryption state: 1=on, 0=off
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpEncryptionOn
++(
++    tmUnitSelect_t	txUnit,
++    Bool            bOn
++);
++
++/*============================================================================*/
++/**
++    \brief      Get HDCP OTP registers
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  otpAddress  OTP start address 0-FF
++    \param[out] pOtpData    Ptr to a three-byte array to hold the data read:
++                            [0] = OTP_DATA_MSB
++                            [1] = OTP_DATA_ISB
++                            [2] = OTP_DATA_LSB
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpGetOtp
++(
++    tmUnitSelect_t	        txUnit,
++    UInt8                   otpAddress,
++    UInt8                   *pOtpData
++);
++
++/*============================================================================*/
++/**
++    \brief      Return the failure state that caused the last T0 interrupt
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pFailState  Ptr to the unit's last T0 fail state
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpGetT0FailState
++(
++    tmUnitSelect_t	txUnit,
++    UInt8           *pFailState
++);
++
++/*============================================================================*/
++/**
++    \brief      Handle BCAPS interrupt
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++
++    \param[in]  txUnit  Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++
++    \note       The user BCAPS interrupt handler (registered with 
++                tmbslTDA9989Init) calls this API before calling 
++                tmbslTDA9989HdcpHandleBKSV
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleBCAPS
++(
++    tmUnitSelect_t	txUnit
++);
++
++/*============================================================================*/
++/**
++    \brief      Read BKSV registers
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[out] pBksv           Pointer to 5-byte BKSV array returned to caller
++                                (1st byte is MSB)
++    \param[out] pbCheckRequired Pointer to a result variable to tell the caller
++                                whether to check for BKSV in a revocation list:
++                                0 or 1 (check not required, check required)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++
++    \note       The user BCAPS interrupt handler (registered with 
++                tmbslTDA9989Init) calls this API after calling 
++                tmbslTDA9989HdcpHandleBCAPS
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleBKSV
++(
++    tmUnitSelect_t	txUnit,
++    UInt8           *pBksv,
++    Bool            *pbCheckRequired  
++);
++
++/*============================================================================*/
++/**
++    \brief      Declare BKSV result to be secure or not secure
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  bSecure         Result of user's check of BKSV against a 
++                                revocation list:
++                                0 (not secure: BKSV found in revocation list)
++                                1 (secure: BKSV not found in revocation list)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++
++    \note       The user BCAPS interrupt handler (registered with 
++                tmbslTDA9989Init) calls this API after calling 
++                tmbslTDA9989HdcpHandleBKSV
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleBKSVResult
++(
++    tmUnitSelect_t	txUnit,
++    Bool            bSecure
++);
++
++/**
++    \brief      Handle BSTATUS interrupt
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pBstatus    Pointer to 16-bit BSTATUS value returned to caller
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++
++    \note       Called by user's BSTATUS interrupt handler registered with 
++                tmbslTDA9989Init
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleBSTATUS
++(
++    tmUnitSelect_t	txUnit,
++    UInt16          *pBstatus
++);
++
++/*============================================================================*/
++/**
++    \brief      Handle ENCRYPT interrupt
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit  Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++
++    \note       Called by user's ENCRYPT interrupt handler registered with 
++                tmbslTDA9989Init
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleENCRYPT
++(
++    tmUnitSelect_t	txUnit
++);
++
++/*============================================================================*/
++/**
++    \brief      Handle PJ interrupt
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++
++    \param[in]  txUnit  Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++
++    \note       Called by user's PJ interrupt handler registered with 
++                tmbslTDA9989Init
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandlePJ
++(
++    tmUnitSelect_t	txUnit
++);
++
++/**
++    \brief      Handle SHA-1 interrupt
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  maxKsvDevices   Maximum number of 5-byte devices that will fit
++                                in *pKsvList: 0 to 128 devices
++                                If 0, no KSV read is done and it is treated as
++                                secure
++    \param[out] pKsvList        Pointer to KSV list array supplied by caller:
++                                Sets of 5-byte KSVs, 1 per device, 1st byte is
++                                LSB of 1st device
++                                May be null if maxKsvDevices is 0
++    \param[out] pnKsvDevices    Pointer to number of KSV devices copied to
++                                *pKsvList: 0 to 128
++                                If 0, no KSV check is needed and it is treated
++                                as secure
++                                May be null if maxKsvDevices is 0
++    \param[out] pDepth          Connection tree depth
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: two parameters disagree
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++
++    \note       Called by user's SHA-1 interrupt handler registered with 
++                tmbslTDA9989Init
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleSHA_1
++(
++    tmUnitSelect_t	txUnit,
++    UInt8           maxKsvDevices,
++    UInt8           *pKsvList,
++    UInt8           *pnKsvDevices,
++    UInt8           *pDepth
++);
++
++/*============================================================================*/
++/**
++    \brief      Declare KSV list result to be secure or not secure
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  bSecure         Result of user's check of KSV list against a 
++                                revocation list:
++                                0 (not secure: one or more KSVs are in r.list)
++                                1 (secure: no KSV found in revocation list)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++
++    \note       The user SHA_1 interrupt handler (registered with 
++                tmbslTDA9989Init) calls this API after calling 
++                tmbslTDA9989HdcpHandleSHA_1
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleSHA_1Result
++(
++    tmUnitSelect_t	txUnit,
++    Bool            bSecure
++);
++
++/*============================================================================*/
++/**
++    \brief      Handle T0 interrupt
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit      Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++
++    \note       Called by user's T0 interrupt handler registered with 
++                tmbslTDA9989Init
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleT0
++(
++    tmUnitSelect_t	txUnit
++);
++
++/*============================================================================*/
++/**
++    \brief      Prepare for HDCP operation
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  voutFmt     Video output format
++    \param[in]  voutFreq    Vertical output frequency
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++
++    \note       Must be called before tmbslTDA9989HdcpRun
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpInit
++(
++    tmUnitSelect_t	    txUnit,
++    tmbslHdmiTxVidFmt_t voutFmt,
++    tmbslHdmiTxVfreq_t  voutFreq
++);
++
++/*============================================================================*/
++/**
++    \brief      Start HDCP operation
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit  Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++
++    \note       Must be called after tmbslTDA9989HdcpInit
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpRun
++(
++    tmUnitSelect_t	txUnit
++);
++
++/*============================================================================*/
++/**
++    \brief      Stop HDCP operation, and cease encrypting the output
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit  Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++
++    \note       This will trigger an Encrypt interrupt
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpStop
++(
++    tmUnitSelect_t	txUnit
++);
++/**
++    \brief      Get the hot plug input status last read by tmbslTDA9989Init
++                or tmbslTDA9989HwHandleInterrupt
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[out] pHotPlugStatus  Pointer to returned Hot Plug Detect status
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t
++tmbslTDA9989HotPlugGetStatus
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxHotPlug_t *pHotPlugStatus,
++    Bool                  client /* Used to determine whether the request comes from the application */
++);
++
++/**
++    \brief      Get the rx sense input status last read by tmbslTDA9989Init
++                or tmbslTDA9989HwHandleInterrupt
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[out] pRxSenseStatus  Pointer to returned Rx Sense Detect status
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t
++tmbslTDA9989RxSenseGetStatus
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxRxSense_t *pRxSenseStatus,
++    Bool                  client /* Used to determine whether the request comes from the application */
++);
++
++/*============================================================================*/
++/**
++    \brief      Get one or more hardware I2C register values
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  regPage     The device register's page: 00h, 01h, 02h, 11h, 12h
++    \param[in]  regAddr     The starting register address on the page: 0 to FFh
++    \param[out] pRegBuf     Pointer to buffer to receive the register data
++    \param[in]  nRegs       Number of contiguous registers to read: 1 to 254
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989HwGetRegisters
++(
++    tmUnitSelect_t	txUnit,
++    Int             regPage,
++    Int             regAddr,
++    UInt8          *pRegBuf,
++    Int             nRegs
++);
++
++/*============================================================================*/
++/**
++    \brief      Get the transmitter device version read at initialization
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[out] puDeviceVersion Pointer to returned hardware version
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t
++tmbslTDA9989HwGetVersion
++(
++    tmUnitSelect_t  txUnit,
++    UInt8          *puDeviceVersion
++);
++
++
++/**
++    \brief      Get the transmitter device feature read at initialization
++
++    \param[in]  txUnit            Transmitter unit number
++    \param[in]  deviceFeature     Hardware feature to check
++    \param[out]  pFeatureSupported Hardware feature supported or not
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989HwGetCapabilities
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxHwFeature_t  deviceCapability,
++    Bool                    *pFeatureSupported
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Handle all hardware interrupts from a transmitter unit
++
++    \param[in]  txUnit      Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++    \note       This function must be called at task level not interrupt level,
++                as I2C access is required
++ */
++tmErrorCode_t
++tmbslTDA9989HwHandleInterrupt
++(
++    tmUnitSelect_t      txUnit
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Set one or more hardware I2C registers
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  regPage     The device register's page: 00h, 01h, 02h, 11h, 12h
++    \param[in]  regAddr     The starting register address on the page: 0 to FFh
++    \param[in]  pRegBuf     Ptr to buffer from which to write the register data
++    \param[in]  nRegs       Number of contiguous registers to write: 0 to 254.
++                            The page register (255) may not be written - it is
++                            written to automatically here. If nRegs is 0, the
++                            page register is the only register written.
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989HwSetRegisters 
++(
++    tmUnitSelect_t	txUnit,
++    Int             regPage, 
++    Int             regAddr, 
++    UInt8          *pRegBuf, 
++    Int             nRegs
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Handle hardware startup by resetting Device Instance Data
++ */
++void
++tmbslTDA9989HwStartup
++(
++    void
++);
++
++/**
++    \brief      Create an instance of an HDMI Transmitter: initialize the 
++                driver, reset the transmitter device and get the current
++                Hot Plug state
++
++    \param[in]  txUnit           Transmitter unit number
++    \param[in]  uHwAddress       Device I2C slave address
++    \param[in]  sysFuncWrite     System function to write I2C
++    \param[in]  sysFuncRead      System function to read I2C
++    \param[in]  sysFuncEdidRead  System function to read EDID blocks via I2C
++    \param[in]  sysFuncTimer     System function to run a timer
++    \param[in]  funcIntCallbacks Pointer to interrupt callback function list
++                                 The list pointer is null for no callbacks;
++                                 each pointer in the list may also be null.
++    \param[in]  bEdidAltAddr     Use alternative i2c address for EDID data
++                                 register between Driver and TDA9983/2:
++                                 0 - use default address (A0)
++                                 1 - use alternative address (A2)
++    \param[in]  vinFmt           EIA/CEA Video input format: 1 to 31, 0 = No Change
++    \param[in]  pixRate          Single data (repeated or not) or double data rate
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: the unit number is wrong or
++                    the transmitter instance is already initialised
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter is invalid or out 
++                    of range
++                  - TMBSL_ERR_HDMI_INIT_FAILED: the unit instance is already 
++                    initialised
++                  - TMBSL_ERR_HDMI_COMPATIBILITY: the driver is not compatiable 
++                    with the internal device version code
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989Init
++(
++    tmUnitSelect_t	           txUnit,
++    UInt8                      uHwAddress,
++    ptmbslHdmiTxSysFunc_t      sysFuncWrite,
++    ptmbslHdmiTxSysFunc_t      sysFuncRead,
++    ptmbslHdmiTxSysFuncEdid_t  sysFuncEdidRead,
++    ptmbslHdmiTxSysFuncTimer_t sysFuncTimer,
++    tmbslHdmiTxCallbackList_t *funcIntCallbacks,
++    Bool                       bEdidAltAddr,
++    tmbslHdmiTxVidFmt_t        vinFmt,
++    tmbslHdmiTxPixRate_t       pixRate
++);
++
++/**
++    \brief      Set colour space converter matrix coefficients
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  pMatCoeff   Pointer to Matrix Coefficient structure
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++    \note       Matrix Coefficient parameter structure:
++                Int16 Coeff[9]: Array of coefficients (values -1024 to +1023)
++ */
++tmErrorCode_t
++tmbslTDA9989MatrixSetCoeffs
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxMatCoeff_t   *pMatCoeff
++);
++
++/**
++    \brief      Set colour space conversion using preset values
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  vinFmt          Input video format
++    \param[in]  vinMode         Input video mode
++    \param[in]  voutFmt         Output video format
++    \param[in]  voutMode        Output video mode
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t
++tmbslTDA9989MatrixSetConversion
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxVidFmt_t     vinFmt,
++    tmbslHdmiTxVinMode_t    vinMode,
++    tmbslHdmiTxVidFmt_t     voutFmt,
++    tmbslHdmiTxVoutMode_t   voutMode,
++    tmbslHdmiTxVQR_t        dviVqr
++);
++ 
++/**
++    \brief      Set colour space converter matrix offset at input
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  pMatOffset  Pointer to Matrix Offset structure
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++    \note       Matrix Offset structure parameter structure:
++                Int16 Offset[3]: Offset array (values -1024 to +1023)
++ */
++tmErrorCode_t
++tmbslTDA9989MatrixSetInputOffset
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxMatOffset_t  *pMatOffset
++);
++
++/**
++    \brief      Set colour space converter matrix mode
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  mControl    Matrix Control: On, Off, No change
++    \param[in]  mScale      Matrix Scale Factor: 1/256, 1/512, 1/1024, No change
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++    \note       NA
++
++    \sa         NA
++ */
++tmErrorCode_t
++tmbslTDA9989MatrixSetMode
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxmCntrl_t mControl,
++    tmbslHdmiTxmScale_t mScale
++);
++
++/*============================================================================*/
++/**
++    \brief      Set colour space converter matrix offset at output
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  pMatOffset  Pointer to Matrix Offset structure
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++    \note       Matrix Offset parameter structure:
++                nt16 Offset[3]: Offset array (values -1024 to +1023)
++ */
++tmErrorCode_t
++tmbslTDA9989MatrixSetOutputOffset
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxMatOffset_t  *pMatOffset
++);
++
++/*============================================================================*/
++/**
++    \brief      Enable audio clock recovery packet insertion 
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  bEnable     Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: when in DVI mode
++
++    \note       tmbslTDA9989AudioInSetCts sets CTS and N values
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetAclkRecovery
++(
++    tmUnitSelect_t	txUnit,
++    Bool            bEnable
++);
++
++/**
++    \brief      Set audio content protection packet & enable/disable packet 
++                insertion
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  pPkt        Pointer to Data Island Packet structure
++    \param[in]  byteCnt     Packet buffer byte count
++    \param[in]  uAcpType    Content protection type
++    \param[in]  bEnable     Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: pointer suppied with byte count of zero
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: not possible with this device
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       Data Island Packet parameter structure:
++                UInt8 dataByte[28]      Packet Data
++
++    \sa         NA
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetAcp
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPkt_t    *pPkt,
++    UInt                byteCnt,
++    UInt8               uAcpType,
++    Bool                bEnable
++);
++
++/**
++    \brief      Set audio info frame packet & enable/disable packet insertion
++
++    \param[in]  txUnit  Transmitter unit number
++    \param[in]  pPkt    Pointer to Audio Infoframe structure
++    \param[in]  bEnable Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       Audio Infoframe structure:
++                UInt8 CodingType
++                UInt8 ChannelCount
++                UInt8 SampleFreq
++                UInt8 SampleSize
++                UInt8 ChannelAlloc
++                Bool DownMixInhibit
++                UInt8 LevelShift
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetAudioInfoframe
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPktAif_t *pPkt,
++    Bool                bEnable
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Set contents of general control packet & enable/disable 
++                packet insertion
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  paMute      Pointer to Audio Mute; if Null, no change to packet
++                            contents is made
++    \param[in]  bEnable     Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       tmbslTDA9989AudioOutSetMute must be used to mute the audio output
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetGeneralCntrl
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxaMute_t  *paMute,
++    Bool                bEnable
++);
++
++/*============================================================================*/
++/**
++    \brief      Set ISRC1 packet & enable/disable packet insertion
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  pPkt        Pointer to Data Island Packet structure
++    \param[in]  byteCnt     Packet buffer byte count
++    \param[in]  bIsrcCont   ISRC continuation flag
++    \param[in]  bIsrcValid  ISRC valid flag
++    \param[in]  uIsrcStatus ISRC Status
++    \param[in]  bEnable     Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: pointer suppied with byte count of zero
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: not possible with this device
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       Data Island Packet parameter structure:
++                UInt8 dataByte[28]  Packet Data
++
++    \sa         NA
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetIsrc1
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPkt_t    *pPkt,
++    UInt                byteCnt,
++    Bool                bIsrcCont,
++    Bool                bIsrcValid,
++    UInt8               uIsrcStatus,
++    Bool                bEnable
++);
++
++/*============================================================================*/
++/**
++    \brief      Set ISRC2 packet & enable/disable packet insertion
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  pPkt        Pointer to Data Island Packet structure
++    \param[in]  byteCnt     Packet buffer byte count
++    \param[in]  bEnable     Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: pointer suppied with byte count of zero
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: not possible with this device
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       Data Island Packet parameter structure:
++                UInt8 dataByte[28]      Packet Data
++
++    \sa         NA
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetIsrc2
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPkt_t    *pPkt,
++    UInt                byteCnt,
++    Bool                bEnable
++);
++
++/**
++    \brief      Set MPEG infoframe packet & enable/disable packet insertion
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  pPkt            Pointer to MPEG Infoframe structure
++    \param[in]  bEnable         Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: not possible with this device
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       MPEG Infoframe structure:
++                UInt32                  bitRate
++                tmbslHdmiTxMpegFrame_t  frameType
++                Bool                    bFieldRepeat
++
++    \sa         NA
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetMpegInfoframe
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxPktMpeg_t    *pPkt,
++    Bool                    bEnable
++);
++
++/*============================================================================*/
++/**
++    \brief      Enable NULL packet insertion
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  bEnable     Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetNullInsert
++(
++    tmUnitSelect_t  txUnit,
++    Bool            bEnable
++);
++
++/*============================================================================*/
++/**
++    \brief      Set single Null packet insertion (flag auto-resets after 
++                transmission)
++
++    \param[in]  txUnit      Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       Operation resets after single transmission
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetNullSingle
++(
++    tmUnitSelect_t  txUnit
++);
++
++/**
++    \brief      Set audio info frame packet & enable/disable packet insertion
++
++    \param[in]  txUnit  Transmitter unit number
++    \param[in]  pPkt    Pointer to Audio Infoframe structure
++    \param[in]  bEnable Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: not possible with this device
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       Audio Infoframe structure:
++                UInt8                   VendorName[8]
++                UInt8                   ProdDescr[16]
++                tmbslHdmiTxSourceDev_t  SourceDevInfo
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetSpdInfoframe
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPktSpd_t *pPkt,
++    Bool                bEnable
++);
++
++/**
++    \brief      Set video infoframe packet & enable/disable packet insertion
++
++    \param[in]  txUnit  Transmitter unit number
++    \param[in]  pPkt    Pointer to Video Infoframe structure
++    \param[in]  bEnable Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       Video Infoframe structure:
++                UInt8 Colour
++                Bool ActiveInfo
++                UInt8 BarInfo
++                UInt8 ScanInfo
++                UInt8 Colorimetry
++                UInt8 PictureAspectRatio
++                UInt8 ActiveFormatRatio
++                UInt8 Scaling
++                UInt8 VidFormat
++                UInt8 PixelRepeat
++                UInt16 EndTopBarLine
++                UInt16 StartBottomBarLine
++                UInt16 EndLeftBarPixel
++                UInt16 StartRightBarPixel   (incorrectly named in [HDMI1.2])
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetVideoInfoframe
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPktVif_t *pPkt,
++    Bool                bEnable
++);
++
++/*============================================================================*/
++/**
++    \brief      Set Vendor Specific Infoframe packet & enable/disable packet insertion
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  pPkt        Pointer to Data Island Packet structure
++    \param[in]  byteCnt     Packet buffer byte count
++    \param[in]  uVersion    Version number for packet header
++    \param[in]  bEnable     Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: pointer suppied with byte count of zero
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: not possible with this device
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       Data Island Packet parameter structure:
++                UInt8 dataByte[28]      Packet Data (only use 27 bytes max)
++
++    \sa         NA
++ */
++tmErrorCode_t
++tmbslTDA9989PktSetVsInfoframe
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPkt_t    *pPkt,
++    UInt                byteCnt,
++    UInt8               uVersion,
++    Bool                bEnable
++);
++
++/*============================================================================*/
++/**
++    \brief      Set raw video Infoframe packet & enable/disable packet insertion
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  pPkt        Pointer to raw Packet structure
++    \param[in]  bEnable     Enable or disable packet insertion
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++    \note       Data Island Packet parameter structure:
++                UInt8 dataByte[28]      Packet Data
++
++    \sa         NA
++ */
++tmErrorCode_t tmbslTDA9989PktSetRawVideoInfoframe
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxPktRawAvi_t *pPkt,
++    Bool                    bEnable
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Get the power state of the transmitter
++
++    \param[in]  txUnit       Transmitter unit number
++    \param[out] pePowerState Pointer to the power state of the device now
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++    \note       Power states:
++                - tmPowerOn
++                - tmPowerStandby
++ */
++tmErrorCode_t
++tmbslTDA9989PowerGetState
++(
++    tmUnitSelect_t          txUnit,
++	tmPowerState_t	        *pePowerState
++);
++
++/*============================================================================*/
++/**
++    \brief      Set the power state of the transmitter
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  ePowerState Power state to set
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number 
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++    \note       Power states (Off and Suspend are treated the same as Standby):
++                - tmPowerOn
++                - tmPowerStandby
++                - tmPowerSuspend
++                - tmPowerOff
++ */
++tmErrorCode_t
++tmbslTDA9989PowerSetState
++(
++    tmUnitSelect_t          txUnit,
++	tmPowerState_t          ePowerState
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Reset the HDMI transmitter
++
++    \param[in]  txUnit      Transmitter unit number
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++    \note       NA
++
++    \sa         tmbslTDA9989Init
++ */
++tmErrorCode_t
++tmbslTDA9989Reset
++(
++    tmUnitSelect_t      txUnit
++);
++
++/**
++    \brief      Get diagnostic counters from the scaler
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pScalerDiag Pointer to structure to receive scaler diagnostic
++                            registers
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++
++    \note       scaler diagnostic registers structure:
++                UInt16 maxBuffill_p     Filling primary video buffer
++                UInt16 maxBuffill_d     Filling video deinterlaced buffer
++                UInt8  maxFifofill_pi   Filling primary video input FIFO
++                UInt8  minFifofill_po1  Filling primary video output FIFO #1
++                UInt8  minFifofill_po2  Filling primary video output FIFO #2
++                UInt8  minFifofill_po3  Filling primary video output FIFO #3
++                UInt8  minFifofill_po4  Filling primary video output FIFO #4
++                UInt8  maxFifofill_di   Filling deinterlaced video input FIFO
++                UInt8  maxFifofill_do   Filling deinterlaced video output FIFO
++ */
++tmErrorCode_t
++tmbslTDA9989ScalerGet
++(
++    tmUnitSelect_t           txUnit,
++    tmbslHdmiTxScalerDiag_t *pScalerDiag
++);
++
++
++
++/**
++    \brief      Get the current scaler mode
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[out] pScalerMode Pointer to variable to receive scaler mode
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++*/
++tmErrorCode_t
++tmbslTDA9989ScalerGetMode
++(
++    tmUnitSelect_t		      txUnit,
++    tmbslHdmiTxScaMode_t      *pScalerMode
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Enable or disable scaler input frame
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  bDisable    Enable or disable scaler input
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989ScalerInDisable
++(
++    tmUnitSelect_t  txUnit,
++    Bool            bDisable
++);
++
++/**
++    \brief      Set the active coefficient lookup table for the vertical scaler
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  lutSel      Coefficient lookup table selection
++    \param[in]  pVsLut      Table of HDMITX_VSLUT_COEFF_NUM coefficient values
++                            (may be null if lutSel not HDMITX_SCALUT_USE_VSLUT)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: two parameters disagree
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989ScalerSetCoeffs
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxScaLut_t   lutSel,
++    UInt8                *pVsLut
++);
++
++/**
++    \brief      Set scaler field positions
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  topExt      Internal, External, No Change
++    \param[in]  deExt       Internal, External, No Change
++    \param[in]  topSel      Internal, VRF, No Change
++    \param[in]  topTgl      No Action, Toggle, No Change
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t   
++tmbslTDA9989ScalerSetFieldOrder 
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxIntExt_t topExt,
++    tmbslHdmiTxIntExt_t deExt,
++    tmbslHdmiTxTopSel_t topSel,
++    tmbslHdmiTxTopTgl_t topTgl 
++);
++
++/**
++    \brief      Set scaler fine adjustment options
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit       Transmitter unit number
++    \param[in]  uRefPix      Ref. pixel preset 0 to 1FFFh (2000h = No Change)
++    \param[in]  uRefLine     Ref. line preset 0 to 7FFh (800h = No Change)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989ScalerSetFine
++(
++    tmUnitSelect_t  txUnit,
++    UInt16          uRefPix,    
++    UInt16          uRefLine   
++);
++
++/**
++    \brief      Set scaler phase for scaling 1080p
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit                  Transmitter unit number
++    \param[in]  tmbslHdmiTxHPhases_t   Ref. 0 to 15_horizontal_phases 1 to 16_horizontal_phases
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++
++tmErrorCode_t   
++tmbslTDA9989ScalerSetPhase
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxHPhases_t horizontalPhases   
++);
++
++/**
++    \brief      configure scaler latency to set run in run out
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  UInt8       Ref. 0 to 255
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t   
++tmbslTDA9989ScalerSetLatency
++(
++    tmUnitSelect_t        txUnit,
++    UInt8                 scaler_latency
++);
++
++/**
++    \brief      Set scaler synchronization options
++                On a TDA9989 this function is not supported and 
++                return result TMBSL_ERR_HDMI_NOT_SUPPORTED
++
++    \param[in]  txUnit       Transmitter unit number
++    \param[in]  method       Sync. combination method
++    \param[in]  once         Line/pixel counters sync once or each frame
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989ScalerSetSync
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxVsMeth_t method,
++    tmbslHdmiTxVsOnce_t once
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Get the driver software version and compatibility numbers 
++
++    \param[out] pSWVersion   Pointer to the software version structure returned
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t   
++tmbslTDA9989SwGetVersion 
++(
++    ptmSWVersion_t      pSWVersion
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Get the driver software version and compatibility numbers 
++
++    \param[in]  txUnit       Transmitter unit number
++    \param[in]  waitMs       Period in milliseconds to wait
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t   
++tmbslTDA9989SysTimerWait 
++(
++    tmUnitSelect_t      txUnit,
++    UInt16              waitMs
++);
++
++/**
++    \brief      Set the TMDS outputs to normal active operation or to a forced
++                state 
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  tmdsOut     TMDS output mode
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t   
++tmbslTDA9989TmdsSetOutputs 
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxTmdsOut_t    tmdsOut
++);
++
++/**
++    \brief      Fine-tune the TMDS serializer 
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  uPhase2     Serializer phase 2
++    \param[in]  uPhase3     Serializer phase 3
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++ */
++tmErrorCode_t   
++tmbslTDA9989TmdsSetSerializer 
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           uPhase2,
++    UInt8           uPhase3
++);
++
++/**
++    \brief      Set a colour bar test pattern
++
++    \param[in]  txUnit     Transmitter unit number
++    \param[in]  pattern    Test pattern
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989TestSetPattern
++(
++    tmUnitSelect_t           txUnit,
++    tmbslHdmiTxTestPattern_t pattern 
++);
++
++/**
++    \brief      Set or clear one or more simultaneous test modes
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  testMode    Mode: tst_pat, tst_656, tst_serphoe, tst_nosc,
++                            tst_hvp, tst_pwd, tst_divoe
++    \param[in]  testState   State: 1=On, 0=Off
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989TestSetMode
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxTestMode_t   testMode,
++    tmbslHdmiTxTestState_t  testState
++);
++
++/**
++    \brief      Enable blanking between active data
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  blankitSource   Blankit Source: Not DE, VS And HS, 
++                                VS And Not HS, Hemb And Vemb, No Change
++    \param[in]  blankingCodes   Blanking Codes: All Zero, RGB444, YUV444,
++                                YUV422, No Change
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++    \note       NA
++
++    \sa         NA
++ */
++tmErrorCode_t
++tmbslTDA9989VideoInSetBlanking
++(
++    tmUnitSelect_t         txUnit,
++    tmbslHdmiTxBlnkSrc_t   blankitSource,
++    tmbslHdmiTxBlnkCode_t  blankingCodes
++);
++
++/**
++    \brief      Configure video input options and control the upsampler
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  vinMode         Video input mode
++    \param[in]  voutFmt         EIA/CEA Video output format: 1 to 31, 0 = No Change
++    \param[in]  sampleEdge      Sample edge:
++                                Pixel Clock Positive Edge, 
++                                Pixel Clock Negative Edge, No Change
++    \param[in]  pixRate         Single data or double data rate
++    \param[in]  upsampleMode    Upsample mode
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989VideoInSetConfig
++(
++    tmUnitSelect_t              txUnit,
++    tmbslHdmiTxVinMode_t       vinMode,
++    tmbslHdmiTxVidFmt_t        voutFmt,
++    tmbslHdmiTx3DStructure_t   structure3D,
++    tmbslHdmiTxPixEdge_t       sampleEdge,
++    tmbslHdmiTxPixRate_t       pixRate,
++    tmbslHdmiTxUpsampleMode_t  upsampleMode 
++);
++
++/**
++    \brief      Set fine image position
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  subpacketCount  Subpacket Count fixed values and sync options
++    \param[in]  toggleClk1      Toggle clock 1 phase w.r.t. clock 2
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++    \note       NA     
++
++    \sa         NA
++ */
++tmErrorCode_t
++tmbslTDA9989VideoInSetFine
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxPixSubpkt_t    subpacketCount,
++    tmbslHdmiTxPixTogl_t      toggleClk1 
++);
++
++/**
++    \brief      Set video input port swapping and mirroring
++
++    \param[in]  txUnit          Transmitter unit number
++    \param[in]  pSwapTable      Pointer to 6-byte port swap table
++    \param[in]  pMirrorTable    Pointer to 6-byte port mirror table  
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++    \note       UInt8 pSwapTable[6]
++                
++                Each table position 0 to 5 represents a group of 4 port bits:
++                [0]=23:20, [1]=16:19, [2]=15:12, [3]=11:8, [4]=4:7, [5]=0:3
++                Table position values are 0 to 6, denoting the group of 4 port
++                bits to swap to: 0=23:20, 1=16:19, 2=15:12, 3=11:8, 4=4:7, 5=0:3.
++                For example, to swap port bits 15:12 to bits 4:7: pSwapTable[2]=4
++
++                UInt8 pMirrorTable[6]
++
++                Each table position 0 to 5 represents a group of 4 port bits:
++                [0]=23:20, [1]=16:19, [2]=15:12, [3]=11:8, [4]=4:7, [5]=0:3.
++                Cell values are 0 to 2 (Not Mirrored, Mirrored, No Change).
++                For example, to mirror port bits 11:8 to bits 8:11:
++                pMirrorTable[3]=1.
++ */
++tmErrorCode_t
++tmbslTDA9989VideoInSetMapping
++#ifdef TMFL_RGB_DDR_12BITS
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pSwapTable,
++    UInt8           *pMirrorTable,
++    UInt8           *pMux
++);
++#else
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pSwapTable,
++    UInt8           *pMirrorTable
++);
++#endif
++/**
++    \brief      Set video input port (enable, ground)
++
++    \param[in]  txUnit                Transmitter unit number
++    \param[in]  pEnaVideoPortTable    Pointer to 3-byte video port enable table
++    \param[in]  pGndVideoPortTable    Pointer to 3-byte video port ground table  
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++    \note       UInt8 pEnaVideoPortTable[3]
++                
++                Each table position 0 to 2 represents a group of 8 port bits:
++                [0]=7:0, [1]=15:8, [2]=23:16
++                bitn = '1' means enable port n
++				bitn = '0' means disable port n
++				For example, to enable port 0 to 7 only : pEnaVideoPortTable[0]= 0xFF
++                pEnaVideoPortTable[1]= 0x00, pEnaVideoPortTable[2]= 0x00    
++                
++				UInt8 pGndVideoPortTable[3]
++
++                Each table position 0 to 2 represents a group of 8 port bits:
++                [0]=7:0, [1]=15:8, [2]=23:16
++                bitn = '1' means pulldown port n
++				bitn = '0' means not pulldown port n
++				For example, to pulldown port 8 to 15 only : pEnaVideoPortTable[0]= 0x00
++                pEnaVideoPortTable[1]= 0xFF, pEnaVideoPortTable[2]= 0x00
++ */
++tmErrorCode_t
++tmbslTDA9989SetVideoPortConfig
++(
++    tmUnitSelect_t  txUnit,
++	UInt8			*pEnaVideoPortTable,
++	UInt8			*pGndVideoPortTable
++);
++
++/*============================================================================*/
++/**
++    \brief      Set audio input port (enable, ground)
++
++    \param[in]  txUnit                Transmitter unit number
++    \param[in]  pEnaAudioPortTable    Pointer to 1-byte audio port enable configuration
++    \param[in]  pGndAudioPortTable    Pointer to 1-byte audio port ground configuration  
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++    \note       UInt8 pEnaAudioPortTable[1]
++                bitn = '1' means enable port n
++				bitn = '0' means disable port n
++				For example, to enable all audio port (0:7) : pEnaAudioPortTable[0]= 0xFF
++                
++				UInt8 pGndAudioPortTable[1]
++                bitn = '1' means pulldown port n
++				bitn = '0' means not pulldown port n
++				For example, to pulldown audio port (0:7) : pEnaAudioPortTable[0]= 0xFF
++*/
++tmErrorCode_t
++tmbslTDA9989SetAudioPortConfig
++(
++    tmUnitSelect_t  txUnit,
++	UInt8			*pEnaAudioPortTable,
++	UInt8			*pGndAudioPortTable
++);
++
++/*============================================================================*/
++/**
++    \brief      Set audio input Clock port (enable, ground)
++
++    \param[in]  txUnit                Transmitter unit number
++    \param[in]  pEnaAudioClockPortTable    Pointer to 1-byte audio Clock port enable configuration
++    \param[in]  pGndAudioClockPortTable    Pointer to 1-byte audio Clock port ground configuration  
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++    \note       UInt8 pEnaAudioClockPortTable[1]
++                bitn = '1' means enable port n
++				bitn = '0' means disable port n
++				For example, to enable all audio Clock port (0) : pEnaAudioPortTable[0]= 0x01
++                
++				UInt8 pGndAudioClockPortTable[1]
++                bitn = '1' means pulldown port n
++				bitn = '0' means not pulldown port n
++				For example, to pulldown audio Clock port (0:7) : pEnaAudioPortTable[0]= 0x01
++*/
++tmErrorCode_t
++tmbslTDA9989SetAudioClockPortConfig
++(
++    tmUnitSelect_t  txUnit,
++	UInt8			*pEnaAudioClockPortTable,
++	UInt8			*pGndAudioClockPortTable
++);
++
++/**
++    \brief      Configure video input sync automatically
++
++    \param[in]  txUnit       Transmitter unit number
++    \param[in]  syncSource   Sync Source:
++                             Embedded, External Vref, External Vs
++                             No Change
++    \param[in]  vinFmt       EIA/CEA Video input format: 1 to 31, 0 = No Change
++    \param[in]  vinMode      Input video mode
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989VideoInSetSyncAuto
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxSyncSource_t   syncSource,
++    tmbslHdmiTxVidFmt_t       vinFmt,
++    tmbslHdmiTxVinMode_t      vinMode,
++    tmbslHdmiTx3DStructure_t  structure3D
++);
++
++/**
++    \brief      Configure video input sync with manual parameters
++
++    \param[in]  txUnit       Transmitter unit number
++    \param[in]  syncSource   Sync Source:
++                             Embedded, External Vref, External Vs
++                             No Change
++    \param[in]  syncMethod   Sync method: V And H, V And X-DE, No Change
++    \param[in]  toggleV      VS Toggle:
++                             No Action, Toggle VS/Vref, No Change
++    \param[in]  toggleH      HS Toggle:
++                             No Action, Toggle HS/Href, No Change
++    \param[in]  toggleX      DE/FREF Toggle:
++                             No Action, Toggle DE/Fref, No Change
++    \param[in]  uRefPix      Ref. pixel preset 0 to 1FFFh (2000h = No Change)
++    \param[in]  uRefLine     Ref. line preset 0 to 7FFh (800h = No Change)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989VideoInSetSyncManual
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxSyncSource_t   syncSource,
++    tmbslHdmiTxVsMeth_t       syncMethod,
++    tmbslHdmiTxPixTogl_t      toggleV,
++    tmbslHdmiTxPixTogl_t      toggleH,
++    tmbslHdmiTxPixTogl_t      toggleX,
++    UInt16                    uRefPix,    
++    UInt16                    uRefLine   
++);
++
++
++/*============================================================================*/
++/**
++    \brief      Enable or disable output video frame
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  bDisable    Enable or disable scaler input
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989VideoOutDisable
++(
++    tmUnitSelect_t  txUnit,
++    Bool            bDisable
++);
++
++/**
++    \brief      Configure sink type, configure video output colour and
++                quantization, control the downsampler, and force RGB output
++                and mute audio in DVI mode
++
++    \param[in]  txUnit          Transmitter unit number:
++    \param[in]  sinkType        Sink device type: DVI or HDMI or copy from EDID
++    \param[in]  voutMode        Video output mode
++    \param[in]  preFilter       Prefilter: Off, 121, 109, CCIR601, No Change
++    \param[in]  yuvBlank        YUV blanking: 16, 0, No Change
++    \param[in]  quantization    Video quantization range:
++                                Full Scale, RGB Or YUV, YUV, No Change
++
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989VideoOutSetConfig
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxSinkType_t     sinkType,
++    tmbslHdmiTxVoutMode_t     voutMode,
++    tmbslHdmiTxVoutPrefil_t   preFilter,
++    tmbslHdmiTxVoutYuvBlnk_t  yuvBlank,
++    tmbslHdmiTxVoutQrange_t   quantization 
++);
++
++/**
++    \brief      Set video synchronization
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  srcH        Horizontal sync source: Internal, Exter'l, No Change
++    \param[in]  srcV        Vertical sync source: Internal, Exter'l, No Change
++    \param[in]  srcX        X sync source: Internal, Exter'l, No Change
++    \param[in]  toggle      Sync toggle: Hs, Vs, Off, No Change
++    \param[in]  once        Line/pixel counters sync once or each frame
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989VideoOutSetSync
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxVsSrc_t      srcH,
++    tmbslHdmiTxVsSrc_t      srcV,
++    tmbslHdmiTxVsSrc_t      srcX,
++    tmbslHdmiTxVsTgl_t      toggle,
++    tmbslHdmiTxVsOnce_t     once
++);
++
++/**
++    \brief      Set main video input and output parameters
++
++    \param[in]  txUnit       Transmitter unit number
++    \param[in]  vinFmt       EIA/CEA Video input format: 1 to 31, 0 = No Change
++    \param[in]  scaMode      Scaler mode: Off, On, Auto, No Change
++                             On TDA9989, only scaler mode off is possible
++    \param[in]  voutFmt      EIA/CEA Video output format: 1 to 31, 0 = No Change
++    \param[in]  uPixelRepeat Pixel repetition factor: 0 to 9, 10 = default,
++                             11 = no change
++    \param[in]  matMode      Matrix mode: 0 = off, 1 = auto
++    \param[in]  datapathBits Datapath bitwidth: 0 to 3 (8, 10, 12, No Change)
++    \param[in]  Desired VQR in dvi mode
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: params are inconsistent
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989VideoSetInOut
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxVidFmt_t     vinFmt,
++    tmbslHdmiTx3DStructure_t structure3D,
++    tmbslHdmiTxScaMode_t    scaMode,
++    tmbslHdmiTxVidFmt_t     voutFmt,
++    UInt8                   uPixelRepeat,
++    tmbslHdmiTxMatMode_t    matMode,
++    tmbslHdmiTxVoutDbits_t  datapathBits,
++    tmbslHdmiTxVQR_t        dviVqr 
++);
++
++/**
++    \brief      Use only for debug to flag the software debug interrupt
++
++    \param[in]  txUnit       Transmitter unit number
++    \param[in]  uSwInt       Interrupt to be generated (not relevant)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++tmErrorCode_t
++tmbslTDA9989FlagSwInt
++(
++    tmUnitSelect_t	            txUnit,
++    UInt32                          uSwInt
++);
++
++
++/**
++    \brief      Enable or disable 5v power
++
++    \param[in]  txUnit    Transmitter unit number
++    \param[in]  pwrEnable 5v Power enable(True)/disable(False)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: functionnality not supported by this device
++ */
++tmErrorCode_t
++tmbslTDA9989Set5vpower
++(
++    tmUnitSelect_t txUnit,
++    Bool           pwrEnable
++);
++
++/**
++    \brief      Enable or disable a callback source
++
++    \param[in]  txUnit         Transmitter unit number
++    \param[in]  callbackSource Callback source
++    \param[in]  enable         Callback source enable(True)/disable(False)
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: impossible to disable this interrupt
++ */
++tmErrorCode_t
++tmbslTDA9989EnableCallback
++(
++    tmUnitSelect_t           txUnit,
++    tmbslHdmiTxCallbackInt_t callbackSource,
++    Bool                     enable
++);
++
++/**
++    \brief      Configure the deep color mode
++
++    \param[in]  txUnit     Transmitter unit number
++    \param[in]  colorDepth Number of bits per pixel to be processed
++    \param[in]  termEnable Enable transmitter termination
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: mode not supported
++ */
++tmErrorCode_t
++tmbslTDA9989SetColorDepth
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxColorDepth colorDepth,
++    Bool                  termEnable
++);
++
++/**
++    \brief      Configure the default phase for a specific deep color mode
++
++    \param[in]  txUnit      Transmitter unit number
++    \param[in]  bEnable     Enable(true)/disable(False) default phase
++    \param[in]  colorDepth  Concerned deepcolor mode
++    \param[in]  videoFormat Number of bits per pixel to be processed
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++                  - TMBSL_ERR_HDMI_NOT_SUPPORTED: functionnality not supported by this device
++ */
++tmErrorCode_t
++tmbslTDA9989SetDefaultPhase
++(
++    tmUnitSelect_t        txUnit,
++    Bool                  bEnable,
++    tmbslHdmiTxColorDepth colorDepth,
++    UInt8                 videoFormat
++);
++
++
++
++/**
++    \brief      Control (Enable/Disable) VS interrupt
++
++    \param[in]  txUnit       Transmitter unit number
++    \param[in]  uIntFlag     Enable/Disable VS interrupt
++
++    \return     The call result:
++                - TM_OK: the call was successful
++                - Else a problem has been detected:
++                  - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++                  - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++                  - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++                  - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++ */
++
++tmErrorCode_t 
++tmbslTDA9989CtlVsInterrupt
++(
++    tmUnitSelect_t  txUnit,
++    Bool            uIntFlag
++);
++
++/*============================================================================*/
++/**
++    \brief Fill Gamut metadata packet into one of the gamut HW buffer. this
++           function is not sending any gamut metadata into the HDMI stream,
++           it is only loading data into the HW.
++
++    \param txUnit Transmitter unit number
++    \param pPkt   pointer to the gamut packet structure
++    \param bufSel number of the gamut buffer to fill
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C
++              bus
++
++ ******************************************************************************/
++tmErrorCode_t tmbslTDA9989PktFillGamut
++(
++    tmUnitSelect_t         txUnit,
++    tmbslHdmiTxPktGamut_t *pPkt,
++    UInt8                  bufSel
++);
++
++/*============================================================================*/
++/**
++    \brief Enable transmission of gamut metadata packet. Calling this function
++           tells HW which gamut buffer to send into the HDMI stream. HW will
++           only take into account this command at the next VS, not during the
++           current one.
++
++    \param txUnit Transmitter unit number
++    \param bufSel Number of the gamut buffer to be sent
++    \param enable Enable/disable gamut packet transmission
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C
++              bus
++
++ ******************************************************************************/
++tmErrorCode_t tmbslTDA9989PktSendGamut
++(
++    tmUnitSelect_t         txUnit,
++    UInt8                  bufSel,
++    Bool                   bEnable
++);
++
++
++/**
++    \brief Return the category of equipement connected
++
++    \param txUnit   Transmitter unit number
++    \param category return category type
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: params are inconsistent
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE hdcp not started
++
++*/
++tmErrorCode_t tmbslTDA9989HdcpGetSinkCategory
++(
++    tmUnitSelect_t              txUnit,
++    tmbslHdmiTxSinkCategory_t   *category
++);
++
++
++/**
++    \brief Return the sink latency information if any
++
++    \param txUnit         Transmitter unit number
++    \param pEdidLatency   latency data structure to return
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: params are inconsistent
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE hdcp not started
++
++*/
++tmErrorCode_t tmbslTDA9989EdidGetLatencyInfo
++(
++    tmUnitSelect_t             txUnit,
++    tmbslHdmiTxEdidLatency_t * pEdidLatency
++);
++
++
++/**
++    \brief Return the sink additional VSDB data information if any
++
++    \param txUnit         Transmitter unit number
++    \param p3Ddata        3D data structure to return
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: params are inconsistent
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE hdcp not started
++
++*/
++tmErrorCode_t tmbslTDA9989EdidGetExtraVsdbData
++(
++    tmUnitSelect_t                  txUnit,
++    tmbslHdmiTxEdidExtraVsdbData_t  **pExtraVsdbData
++);
++
++
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++/**
++    \brief Optimized power by frozing useless clocks related to HDCP
++
++    \param txUnit         Transmitter unit number
++    \param request        power down request
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMBSL_ERR_HDMI_INCONSISTENT_PARAMS: params are inconsistent
++
++*/
++tmErrorCode_t
++tmbslTDA9989HdcpPowerDown
++(
++    tmUnitSelect_t      txUnit,
++    Bool                requested
++);
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMBSLTDA9989_FUNCTIONS_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Edid.c b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Edid.c
+new file mode 100755
+index 0000000..488b950
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Edid.c
+@@ -0,0 +1,1572 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_edid.c
++ *
++ * \version       $Revision: 2 $
++ *
++*/
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#include "tmbslHdmiTx_types.h"
++#include "tmbslTDA9989_Functions.h"
++#include "tmbslTDA9989_local.h"
++#include "tmbslTDA9989_State_l.h"
++#include "tmbslTDA9989_Edid_l.h"
++
++
++/*============================================================================*/
++/*                     TYPES DECLARATIONS                                     */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS                               */
++/*============================================================================*/
++#define EDID_NUMBER_MAX_DTD_BLK_1           6
++/** EDID block 0 parse start point */
++#define EDID_BLK0_BASE_DTD                  0x36
++
++#define EDID_BLK1_OFFSET_BASE_DTD           2
++
++/** EDID block 0 extension block count */
++#define EDID_BLK0_EXT_CNT                   0x7E
++
++/** EDID extension block parse start point */
++#define EDID_BLK_EXT_BASE                   0x04
++
++/** CEA extension block type */
++#define EDID_CEA_EXTENSION                  0x02
++
++/** CEA Block Map */
++#define EDID_BLOCK_MAP                      0xF0
++
++/** NB Max of descriptor DTD or monitor in block 0 */
++#define EDID_NB_MAX_DESCRIP_BLK_IN_BLK_0    4
++
++#define EDID_MONITOR_NAME_DESC_DATA_TYPE    252
++
++#define EDID_MONITOR_RANGE_DESC_DATA_TYPE   253
++
++/*============================================================================*/
++/*                       DEFINES DECLARATIONS                               */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                       VARIABLES DECLARATIONS                               */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                       FUNCTION PROTOTYPES                                  */
++/*============================================================================*/
++
++static tmErrorCode_t    requestEdidBlock(tmHdmiTxobject_t   *pDis);
++
++static tmErrorCode_t    parseEdidBlock (tmHdmiTxobject_t *pDis, 
++                                        Int blockNumber);
++static Bool             storeDtdBlock (tmHdmiTxobject_t    *pDis,
++                                        UInt8               blockPtr);
++
++static Bool             storeMonitorDescriptor (tmHdmiTxobject_t    *pDis,
++                                                UInt8                blockPtr);
++
++
++
++/*============================================================================*/
++/* tmbslTDA9989HwGetCapabilities                                              */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HwGetCapabilities
++(
++ tmUnitSelect_t          txUnit,
++ tmbslHdmiTxHwFeature_t  deviceCapability,
++ Bool                    *pFeatureSupported
++ )
++{
++  tmHdmiTxobject_t      *pDis;
++  tmErrorCode_t          err = TM_OK;
++
++  /* Check unit parameter and point to its object */
++  err = checkUnitSetDis(txUnit, &pDis);
++  RETIF(err != TM_OK, err)
++
++    RETIF_BADPARAM(pFeatureSupported == Null)
++
++    *pFeatureSupported = False;
++
++
++  switch (deviceCapability)
++    {
++    case HDMITX_FEATURE_HW_HDCP:
++      if((pDis->uDeviceFeatures & E_MASKREG_P00_VERSION_not_h) == 0)
++	{
++	  *pFeatureSupported = True;
++	}
++      break;
++    case HDMITX_FEATURE_HW_SCALER:
++      if((pDis->uDeviceFeatures & E_MASKREG_P00_VERSION_not_s) == 0)
++	{
++	  *pFeatureSupported = True;
++	}
++      break;
++    case HDMITX_FEATURE_HW_AUDIO_OBA:
++      *pFeatureSupported = True;
++      break;
++    case HDMITX_FEATURE_HW_AUDIO_DST:
++      *pFeatureSupported = False;
++      break;
++    case HDMITX_FEATURE_HW_AUDIO_HBR:
++      *pFeatureSupported = False;
++      break;
++    case HDMITX_FEATURE_HW_HDMI_1_1:
++      *pFeatureSupported = True;
++      break;
++    case HDMITX_FEATURE_HW_HDMI_1_2A:
++      *pFeatureSupported = True;
++      break;
++    case HDMITX_FEATURE_HW_HDMI_1_3A:
++      *pFeatureSupported = False;
++      break;
++
++    case HDMITX_FEATURE_HW_DEEP_COLOR_30:
++      *pFeatureSupported = False;
++      break;
++
++    case HDMITX_FEATURE_HW_DEEP_COLOR_36:
++      *pFeatureSupported = False;
++      break;
++
++    case HDMITX_FEATURE_HW_DEEP_COLOR_48:
++      *pFeatureSupported = False;
++      break;
++
++    case HDMITX_FEATURE_HW_UPSAMPLER:
++      *pFeatureSupported = True;
++      break;
++
++    case HDMITX_FEATURE_HW_DOWNSAMPLER:
++      *pFeatureSupported = True;
++      break;
++
++    case HDMITX_FEATURE_HW_COLOR_CONVERSION:
++      *pFeatureSupported = True;
++      break;
++
++    default:
++      *pFeatureSupported = False;
++      break;
++    }
++
++
++  return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetAudioCapabilities                                        */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidGetAudioCapabilities
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxEdidSad_t    *pEdidAFmts,
++    UInt                    aFmtLength,
++    UInt                    *pAFmtsAvail,
++    UInt8                   *pAudioFlags
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++    UInt                i;          /* Loop index */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pEdidAFmts == Null)
++    RETIF_BADPARAM(aFmtLength < 1)
++    RETIF_BADPARAM(pAFmtsAvail == Null)
++    RETIF_BADPARAM(pAudioFlags == Null)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        /* allow if edid are read or if there are a chk error on an other block than block 0 */
++
++        /* Copy the Device Instance Structure EdidAFmts descriptors to
++        * pEdidAFmts until we run out or no more space in structure.
++        */
++        if (pDis->EdidSadCnt > 0)
++        {
++            for (i = 0; (i < (UInt)pDis->EdidSadCnt) && (i < aFmtLength); i++)
++            {
++                pEdidAFmts[i].ModeChans = pDis->EdidAFmts[i].ModeChans;
++                pEdidAFmts[i].Freqs     = pDis->EdidAFmts[i].Freqs;
++                pEdidAFmts[i].Byte3     = pDis->EdidAFmts[i].Byte3;
++            }
++        }
++        else
++        {
++            /* No pEdidAFmts to copy so set a zero format to be safe */
++            pEdidAFmts[0].ModeChans = 0;
++            pEdidAFmts[0].Freqs     = 0;
++            pEdidAFmts[0].Byte3     = 0;
++        }
++
++        /* Fill Audio Flags parameter */
++        *pAudioFlags = ((pDis->EdidCeaFlags & 0x40) << 1);  /* Basic audio */
++        if (pDis->EdidSinkAi == True)
++        {
++            *pAudioFlags += 0x40;                           /* Mask in AI support */
++        }
++
++        /* Fill number of SADs available parameter */
++        *pAFmtsAvail = pDis->EdidSadCnt;
++    }
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++    return err;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetBlockCount                                               */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidGetBlockCount
++(
++    tmUnitSelect_t      txUnit,
++    UInt8               *puEdidBlockCount
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(puEdidBlockCount == Null)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        /* allow if edid are read or if there are a chk error on an other block than block 0 */
++        *puEdidBlockCount = pDis->EdidBlockCnt;
++    }
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetStatus                                                  */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidGetStatus
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *puEdidStatus
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(puEdidStatus == Null)
++
++    if (puEdidStatus)
++    {
++        *puEdidStatus = pDis->EdidStatus;
++    }
++ 
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidRequestBlockData                                           */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidRequestBlockData
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pRawEdid, 
++    Int             numBlocks,  /* Only relevant if pRawEdid valid */
++    Int             lenRawEdid  /* Only relevant if pRawEdid valid */
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++    UInt8               regval;     /* Byte value write to register */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    #ifdef TMFL_TDA9989_PIXEL_CLOCK_ON_DDC
++
++    if ( (pDis->vinFmt == HDMITX_VFMT_16_1920x1080p_60Hz) || (pDis->vinFmt == HDMITX_VFMT_31_1920x1080p_50Hz)) {
++
++               err = setHwRegisterField(pDis, 
++                                 E_REG_P02_PLL_SERIAL_3_RW, 
++                                 E_MASKREG_P02_PLL_SERIAL_3_srl_ccir,
++                                 0x01);
++               RETIF_REG_FAIL(err)
++
++           }
++
++    #endif /* TMFL_TDA9989_PIXEL_CLOCK_ON_DDC */
++
++#ifdef TMFL_RGB_DDR_12BITS
++    /* RAM on */
++    setHwRegisterField(pDis, E_REG_P12_TX4_RW, E_MASKREG_P12_TX4_pd_ram, 0);
++#endif
++
++    /* enable edid read */
++    err = setHwRegister(pDis, E_REG_P00_INT_FLAGS_2_RW, 
++                        E_MASKREG_P00_INT_FLAGS_2_edid_blk_rd);
++
++    /* Check remaining parameter(s)
++     * We do allow a null pRawEdid pointer, in which case buffer length is 
++     * irrelevant. If pRawEdid pointer is valid, there is no point in
++     * continuing if insufficient space for at least one block.
++     */
++    RETIF_BADPARAM((pRawEdid != Null) && (lenRawEdid < EDID_BLOCK_SIZE))
++    /* Sensible value of numBlocks? */
++    RETIF((pRawEdid != Null) && ((numBlocks < 1) || (numBlocks > 255)),
++          TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++    /* Enough space for the data requested? */
++    RETIF((pRawEdid != Null) && (lenRawEdid < (numBlocks * EDID_BLOCK_SIZE)),
++          TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++
++    /* Read the HPD pin via the hpd_in flag in the first interrupt status
++    * register and return a TMBSL_ERR_HDMI_NULL_CONNECTION error if it is
++    * not set.
++    * We must use the flag in the Device Instance Structure to avoid 
++    * clearing pending interrupt flags.
++    */
++    RETIF(pDis->hotPlugStatus != HDMITX_HOTPLUG_ACTIVE,
++        TMBSL_ERR_HDMI_NULL_CONNECTION)
++
++    if (pDis->EdidReadStarted == False)
++    {
++
++        /* Reset the EdidStatus in the Device Instance Structure */
++        pDis->EdidStatus = HDMITX_EDID_NOT_READ;
++
++        pDis->EdidReadStarted = True;
++
++        /* Reset stored parameters from EDID in the Device Instance Structure */
++        pDis->EdidSinkType = HDMITX_SINK_DVI;
++        pDis->EdidSinkAi = False;
++        pDis->EdidCeaFlags = 0;
++        pDis->EdidCeaXVYCCFlags = 0;
++        pDis->EdidSvdCnt = 0;
++        pDis->EdidSadCnt = 0;
++        pDis->EdidSourceAddress = 0;                /* 0.0.0.0 */
++		pDis->NbDTDStored = 0;
++        pDis->EdidFirstMonitorDescriptor.bDescRecord = False;
++        pDis->EdidSecondMonitorDescriptor.bDescRecord = False;
++        pDis->EdidOtherMonitorDescriptor.bDescRecord = False;        
++
++        pDis->EdidLatency.latency_available = False;
++        pDis->EdidLatency.Ilatency_available = False;
++
++        pDis->EdidExtraVsdbData.hdmiVideoPresent = False;
++
++
++        pDis->EdidToApp.pRawEdid = pRawEdid;
++        pDis->EdidToApp.numBlocks = numBlocks;
++
++        /* Enable the T0 interrupt for detecting the Read_EDID failure */
++        regval = E_MASKREG_P00_INT_FLAGS_0_t0 ;
++        err = setHwRegister(pDis, E_REG_P00_INT_FLAGS_0_RW, regval);
++        RETIF(err != TM_OK, err);
++
++
++        /* Launch the read of first EDID block into Device Instance workspace */
++        pDis->EdidBlockRequested = 0;
++        err = requestEdidBlock(pDis);
++    }
++    else
++    {
++        /* Not allowed if read edid is on going */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++
++    return err;
++}
++
++
++/*============================================================================*/
++/* EdidBlockAvailable                                                         */
++/*============================================================================*/
++
++tmErrorCode_t
++EdidBlockAvailable (tmUnitSelect_t txUnit, Bool * pSendEDIDCallback)
++{
++
++    tmErrorCode_t       err;        /* Error code */
++    UInt8               chksum;     /* Checksum value */
++    UInt8               LoopIndex;  /* Loop index */
++    UInt8               extBlockCnt;
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++
++    err = TM_OK;
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pSendEDIDCallback == Null)
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    if (pDis->EdidReadStarted == True)
++    {
++
++        err = tmbslTDA9989HwGetRegisters(txUnit, kPageIndexToPage[E_PAGE_09], 
++                                         SPA2ADDR(E_REG_P09_EDID_DATA_0_R), pDis->EdidBlock, EDID_BLOCK_SIZE);
++        RETIF(err != TM_OK, err)
++
++        if(pSendEDIDCallback)
++        {
++            *pSendEDIDCallback = False;
++        }
++
++        if (pDis->EdidStatus == HDMITX_EDID_NOT_READ)
++        {
++            err = getHwRegisters(pDis, E_REG_P09_EDID_DATA_0_R, pDis->EdidBlock,
++                                EDID_BLOCK_SIZE);
++            RETIF_REG_FAIL(err)
++
++            /* Add up all the values of the EDID block bytes, including the
++            * checksum byte
++            */
++            chksum = 0;
++            for (LoopIndex = 0; LoopIndex < EDID_BLOCK_SIZE; LoopIndex++)
++            {
++                chksum = chksum + pDis->EdidBlock[LoopIndex];
++            }
++
++            /* IF the EDID block does not yield a checksum of zero
++            */
++            if(chksum != 0)
++            {
++                if (pDis->EdidBlockRequested == 0)
++                {
++                    /* THEN return a HDMITX_EDID_ERROR error.*/
++                    pDis->EdidStatus = HDMITX_EDID_ERROR_CHK_BLOCK_0;
++                }
++                else
++                {
++                    /* THEN return a HDMITX_EDID_ERROR_CHK error.*/
++                    pDis->EdidStatus = HDMITX_EDID_ERROR_CHK;
++                }
++            }
++        }
++
++        if (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK_BLOCK_0)
++        {
++            /* PR11 : On i2c error or bad checksum in block 0 */
++            /* allow driver to go in state CONNECTED */
++            /* On the other block, we also accept INVALID_CHECKSUM which means
++            * there was a checksum error */
++
++            if(pSendEDIDCallback)
++            {
++                *pSendEDIDCallback = True;
++            }
++
++            setState(pDis, EV_GETBLOCKDATA);
++            if (pDis->rxSenseStatus == HDMITX_RX_SENSE_ACTIVE)
++            {
++                setState(pDis, EV_SINKON);
++            }
++            pDis->EdidReadStarted = False;
++            return err;
++        }
++
++        /* Check if block 0 */
++        if (pDis->EdidBlockRequested == 0)
++        {
++            /* Could check block 0 header (0x00,6 x 0xFF,0x00) here but not
++            * certain to be future proof [CEA861C A.2.3]
++            */
++
++            /* Read block count from penultimate byte of block and store in DIS */
++            extBlockCnt = pDis->EdidBlock[EDID_BLK0_EXT_CNT];
++            
++            pDis->EdidBlockCnt = extBlockCnt + 1;   /* Total = Block 0 + extensions */
++
++        }
++
++        /* If pointer was supplied, copy block from DIS to buffer */
++        if (pDis->EdidToApp.pRawEdid != Null)
++        {
++            /* Check if we've copied as many as requested yet? */
++            if (pDis->EdidBlockRequested < pDis->EdidToApp.numBlocks) 
++            {
++                lmemcpy(pDis->EdidToApp.pRawEdid + (pDis->EdidBlockRequested * EDID_BLOCK_SIZE),
++                    pDis->EdidBlock,
++                    EDID_BLOCK_SIZE);
++            }
++        }
++        parseEdidBlock(pDis, pDis->EdidBlockRequested);
++
++        /* If extension blocks are present, process them */
++        if ( (pDis->EdidBlockRequested + 1) < pDis->EdidBlockCnt)
++        {
++            pDis->EdidBlockRequested = pDis->EdidBlockRequested + 1;
++            /* Launch an edid block read */
++            err = requestEdidBlock(pDis);
++        }
++        else
++        {
++            if (pDis->EdidStatus == HDMITX_EDID_NOT_READ)
++            {
++                pDis->EdidStatus = HDMITX_EDID_READ;
++
++#ifdef TMFL_RGB_DDR_12BITS
++                /* RAM off */
++                setHwRegisterField(pDis, E_REG_P12_TX4_RW, E_MASKREG_P12_TX4_pd_ram, 1);
++#endif
++            }
++
++            if(pSendEDIDCallback)
++            {
++                *pSendEDIDCallback = True;
++            }
++
++            setState(pDis, EV_GETBLOCKDATA);
++
++            if (pDis->rxSenseStatus == HDMITX_RX_SENSE_ACTIVE)
++            {
++                setState(pDis, EV_SINKON);
++            }
++            pDis->EdidReadStarted = False;
++        }
++    }
++    else
++    {
++        /* function called in an invalid state */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++
++    return err;
++
++}
++
++/*============================================================================*/
++/* ClearEdidRequest                                                           */
++/*============================================================================*/
++
++tmErrorCode_t
++ClearEdidRequest (tmUnitSelect_t txUnit)
++{
++
++    tmErrorCode_t       err;        /* Error code */
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++
++    err = TM_OK;
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++
++    /* Reset the EdidStatus in the Device Instance Structure */
++    pDis->EdidStatus = HDMITX_EDID_NOT_READ;
++
++    pDis->EdidReadStarted = False;
++
++    /* Reset stored parameters from EDID in the Device Instance Structure */
++    pDis->EdidSinkType = HDMITX_SINK_DVI;
++    pDis->EdidSinkAi = False;
++    pDis->EdidCeaFlags = 0;
++    pDis->EdidCeaXVYCCFlags = 0;
++    pDis->EdidSvdCnt = 0;
++    pDis->EdidSadCnt = 0;
++    pDis->EdidSourceAddress = 0;                /* 0.0.0.0 */
++	pDis->NbDTDStored = 0;
++    pDis->EdidFirstMonitorDescriptor.bDescRecord = False;
++    pDis->EdidSecondMonitorDescriptor.bDescRecord = False;
++    pDis->EdidOtherMonitorDescriptor.bDescRecord = False;    
++
++    pDis->EdidLatency.latency_available = False;
++    pDis->EdidLatency.Ilatency_available = False;
++
++    pDis->EdidExtraVsdbData.hdmiVideoPresent = False;
++
++    /* Launch the read of first EDID block into Device Instance workspace */
++    pDis->EdidBlockRequested = 0;
++
++
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetSinkType                                                 */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidGetSinkType
++(
++    tmUnitSelect_t              txUnit,
++    tmbslHdmiTxSinkType_t      *pSinkType 
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pSinkType == Null)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        /* allow if edid are read or if there are a chk error on an other block than block 0 */
++
++        *pSinkType = pDis->EdidSinkType;
++    }
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++    return err;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetSourceAddress                                            */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989EdidGetSourceAddress
++(
++    tmUnitSelect_t  txUnit,
++    UInt16          *pSourceAddress 
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pSourceAddress == Null)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        /* allow if edid are read or if there are a chk error on an other block than block 0 */
++
++        *pSourceAddress = pDis->EdidSourceAddress;
++    }
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++    return err;
++
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetDetailedTimingDescriptors                               */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidGetDetailedTimingDescriptors
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxEdidDtd_t    *pEdidDTD,
++    UInt8                   nb_size,
++    UInt8                   *pDTDAvail
++)
++{
++
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pEdidDTD == Null)
++    RETIF_BADPARAM(pDTDAvail == Null)
++    RETIF_BADPARAM(nb_size == 0)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        /* allow if edid are read or if there are a chk error on an other block than block 0 */
++		if (nb_size > pDis->NbDTDStored)
++		{
++			*pDTDAvail = pDis->NbDTDStored;
++		}
++		else
++		{
++			*pDTDAvail = nb_size;
++		}
++
++		lmemcpy(pEdidDTD, pDis->EdidDTD, sizeof(tmbslHdmiTxEdidDtd_t) * (*pDTDAvail));
++	}
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetMonitorDescriptors                                      */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidGetMonitorDescriptors
++(
++    tmUnitSelect_t              txUnit,
++    tmbslHdmiTxEdidFirstMD_t    *pEdidFirstMD,
++    tmbslHdmiTxEdidSecondMD_t   *pEdidSecondMD,
++    tmbslHdmiTxEdidOtherMD_t    *pEdidOtherMD,
++    UInt8                       sizeOtherMD,
++    UInt8                       *pOtherMDAvail
++)
++{
++
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pEdidFirstMD == Null)
++    RETIF_BADPARAM(pEdidSecondMD == Null)
++    RETIF_BADPARAM(pEdidOtherMD == Null)
++
++	DUMMY_ACCESS(pOtherMDAvail);
++	DUMMY_ACCESS(sizeOtherMD);
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++       *pOtherMDAvail = 1;
++       lmemcpy(pEdidFirstMD, &(pDis->EdidFirstMonitorDescriptor), sizeof(tmbslHdmiTxEdidFirstMD_t));
++       lmemcpy(pEdidSecondMD, &(pDis->EdidSecondMonitorDescriptor), sizeof(tmbslHdmiTxEdidSecondMD_t));
++       lmemcpy(pEdidOtherMD, &(pDis->EdidOtherMonitorDescriptor), sizeof(tmbslHdmiTxEdidOtherMD_t));
++	}
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++       *pOtherMDAvail = 0;
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++
++    return TM_OK;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetBasicDisplayParam                                       */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidGetBasicDisplayParam
++(
++    tmUnitSelect_t              txUnit,
++    tmbslHdmiTxEdidBDParam_t    *pEdidBDParam
++)
++{
++
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pEdidBDParam == Null)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        lmemcpy(pEdidBDParam, &(pDis->EDIDBasicDisplayParam), sizeof(tmbslHdmiTxEdidBDParam_t));
++    }
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetVideoCapabilities                                        */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidGetVideoCapabilities
++(
++    tmUnitSelect_t          txUnit,
++    UInt8                   *pEdidVFmts,
++    UInt                    vFmtLength,
++    UInt                    *pVFmtsAvail,
++    UInt8                   *pVidFlags
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++    UInt                i;          /* Loop index */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pEdidVFmts == Null)
++    RETIF_BADPARAM(vFmtLength < 1)
++    RETIF_BADPARAM(pVFmtsAvail == Null)
++    RETIF_BADPARAM(pVidFlags == Null)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        /* allow if edid are read or if there are a chk error on an other block than block 0 */
++
++        /* Copy the Device Instance Structure EdidVFmts descriptors to
++        * pEdidVFmts until we run out or no more space in structure.
++        */
++        if (pDis->EdidSvdCnt > 0)
++        {
++            for (i = 0; (i < (UInt)pDis->EdidSvdCnt) && (i < vFmtLength); i++)
++            {
++                pEdidVFmts[i] = pDis->EdidVFmts[i];
++            }
++        }
++        else
++        {
++            /* No pEdidVFmts to copy so set a zero format to be safe */
++            pEdidVFmts[0] = HDMITX_VFMT_NULL;
++        }
++
++        /* Fill Video Flags parameter */
++        *pVidFlags = ((pDis->EdidCeaFlags & 0x80) |         /* Underscan */
++                    ((pDis->EdidCeaFlags & 0x30) << 1) );  /* YUV444, YUV422 */
++
++
++       /* Add info regarding xvYCC support */
++        *pVidFlags = *pVidFlags | (pDis->EdidCeaXVYCCFlags & 0x03);
++
++        /* Fill number of SVDs available parameter */
++        *pVFmtsAvail = pDis->EdidSvdCnt;
++    }
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetVideoPreferred                                           */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989EdidGetVideoPreferred
++(
++    tmUnitSelect_t         txUnit,
++    tmbslHdmiTxEdidDtd_t *pEdidDTD
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pEdidDTD == Null)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        /* allow if edid are read or if there are a chk error on an other block than block 0 */
++
++        /* Populate the Detailed Timing Descriptor structure pEdidDTD from
++        * EdidDtd in the Device Instance Structure.
++        */
++        lmemcpy(pEdidDTD, &pDis->EdidDTD, sizeof(tmbslHdmiTxEdidDtd_t));
++    }
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++    return err;
++
++}
++
++
++/*============================================================================*/
++/*                          STATIC FUNCTION                                   */
++/*============================================================================*/
++
++/*============================================================================*/
++/* requestEdidBlock - reads an entire edid block                              */
++/*============================================================================*/
++static tmErrorCode_t
++requestEdidBlock
++(   
++    tmHdmiTxobject_t    *pDis      /* Device instance strucure to use */
++    )
++{
++    tmErrorCode_t   err;        /* Error code */
++    UInt8           segptr;     /* Segment ptr value */
++    UInt8           offset;     /* Word offset value */
++
++    /* Check block number is valid [CEA861C A.2.1] */
++    RETIF_BADPARAM(pDis->EdidBlockRequested >= 255)
++
++    err = setHwRegister(pDis, E_REG_P09_DDC_ADDR_RW, DDC_EDID_ADDRESS);
++    RETIF_REG_FAIL(err)
++
++    /* For even blocks we need an offset of 0, odd blocks we need 128 */
++    offset = (((UInt8)pDis->EdidBlockRequested & 1) == 1) ? 128 : 0;
++
++    err = setHwRegister(pDis, E_REG_P09_DDC_OFFS_RW, offset);
++    RETIF_REG_FAIL(err)
++
++    err = setHwRegister(pDis, E_REG_P09_DDC_SEGM_ADDR_RW, DDC_SGMT_PTR_ADDRESS);
++    RETIF_REG_FAIL(err)
++
++    /* Calculate which segment of the EDID we need (2 blocks per segment) */
++    segptr = (UInt8)pDis->EdidBlockRequested / 2;
++
++    err = setHwRegister(pDis, E_REG_P09_DDC_SEGM_RW, segptr);
++    RETIF_REG_FAIL(err)
++
++    /* Enable reading EDID */
++    err = setHwRegister(pDis, E_REG_P09_EDID_CTRL_RW, 0x1);
++    RETIF_REG_FAIL(err)
++
++    /* The flag to start the EDID reading must cleared by software*/
++    err = setHwRegister(pDis, E_REG_P09_EDID_CTRL_RW, 0x0);
++    RETIF_REG_FAIL(err)
++
++    return err;
++}
++
++/*============================================================================*/
++/* parseEdidBlock                                                             */
++/*============================================================================*/
++static tmErrorCode_t
++parseEdidBlock
++(   
++    tmHdmiTxobject_t    *pDis,      /* Device instance strucure holding block */
++    Int                 blockNumber /* Block number */
++    )
++{
++    UInt8           i;                  /* Loop index */
++    UInt8           blockPtr, endPtr;   /* Parsing pointers */       
++    UInt8           blockType, blockLength;
++    Bool            dtdFound;
++    UInt8           NbBlkRead, offset3D=0;
++
++    /* Check block number is valid [CEA861C A.2.1] */
++    RETIF_BADPARAM(blockNumber >= 255)
++
++    NbBlkRead = 0;
++    dtdFound = True;
++    blockPtr = 0;
++
++    if (blockNumber == 0)
++    {
++        pDis->EDIDBasicDisplayParam.uVideoInputDef = pDis->EdidBlock[0x14];
++        pDis->EDIDBasicDisplayParam.uMaxHorizontalSize = pDis->EdidBlock[0x15];
++        pDis->EDIDBasicDisplayParam.uMaxVerticalSize = pDis->EdidBlock[0x16];
++        pDis->EDIDBasicDisplayParam.uGamma = pDis->EdidBlock[0x17];
++        pDis->EDIDBasicDisplayParam.uFeatureSupport = pDis->EdidBlock[0x18];
++        
++        /* Block 0 - contains DTDs but no video data block (SVDs) */
++        for (i = 0; (i < 2) && (dtdFound); i++) /* search 2 possible DTD blocks in block 0 */
++        {   
++            blockPtr = (UInt8)(EDID_BLK0_BASE_DTD + (i * EDID_DTD_BLK_SIZE));
++            if ((blockPtr + EDID_DTD_BLK_SIZE - 1) < EDID_BLOCK_SIZE)
++            {
++                dtdFound = storeDtdBlock(pDis, blockPtr);
++                if (dtdFound)
++                {
++                    NbBlkRead++;
++                }
++            }
++        }
++
++        dtdFound = True;
++
++        /* Parse monitor descriptor */
++        for (i = NbBlkRead; (i < EDID_NB_MAX_DESCRIP_BLK_IN_BLK_0) && (dtdFound); i++)
++        {
++            blockPtr = (UInt8)(EDID_BLK0_BASE_DTD + (i * EDID_DTD_BLK_SIZE));
++            if ((blockPtr + EDID_DTD_BLK_SIZE - 1) < EDID_BLOCK_SIZE)
++            {
++                dtdFound = storeMonitorDescriptor(pDis, blockPtr);
++            }
++        }
++    }
++    else if (blockNumber >= 1)
++    {   
++       switch (pDis->EdidBlock[0])
++       {
++          /* CEA EXTENSION */
++          case EDID_CEA_EXTENSION:
++             /* Read CEA flag bits here - lockout when read once??? */
++             pDis->EdidCeaFlags = pDis->EdidBlock[3];
++             
++             blockPtr = EDID_BLK_EXT_BASE;   /* data block start always fixed */
++             endPtr = pDis->EdidBlock[2];    /* byte after end of data blocks */
++             if (endPtr >= (EDID_BLK_EXT_BASE + 2) && (endPtr <= EDID_BLOCK_SIZE))
++                /* Only try reading if data blocks take up 2 bytes or more, since 
++                 * a video data block must be at least 2 bytes
++                 */
++             {
++                while (blockPtr < endPtr)
++                {
++                   blockType   = (UInt8)((pDis->EdidBlock[blockPtr] & 0xE0) >> 5);
++                   blockLength = (pDis->EdidBlock[blockPtr] & 0x1F);
++                   
++                   switch((Int)blockType)
++                   {
++                      case E_CEA_VIDEO_BLOCK:  /* We have a video data block */
++                         for (i = 1; i <= blockLength; i++)
++                         {
++                           if ((blockPtr + i) < (EDID_BLOCK_SIZE))
++                           {
++                            /* If space, store non-zero SVDs */
++                            if ((pDis->EdidBlock[blockPtr + i] != 0) &&
++                                (pDis->EdidSvdCnt < HDMI_TX_SVD_MAX_CNT))
++                            {
++                               pDis->EdidVFmts[pDis->EdidSvdCnt] =
++                                  pDis->EdidBlock[blockPtr + i];
++                               pDis->EdidSvdCnt++;
++                            }
++                         }
++                            else
++                            {
++                             /* do nothing */
++                            }
++                         }
++                         break;
++                      case E_CEA_AUDIO_BLOCK:  /* We have an audio data block */
++                         for (i = 1; (i + 2) <= blockLength; i += 3) 
++                         {   /* Must loop in steps of 3 (SAD size) */
++                            /* If space, store non-zero SADs */
++                            if ((blockPtr) < (EDID_BLOCK_SIZE -(i +2)))
++                            {
++                            if (((pDis->EdidBlock[blockPtr + i] & 0x78) != 0) &&
++                                (pDis->EdidSadCnt < HDMI_TX_SAD_MAX_CNT))
++                            {
++                               pDis->EdidAFmts[pDis->EdidSadCnt].ModeChans =
++                                  pDis->EdidBlock[blockPtr + i];
++                               pDis->EdidAFmts[pDis->EdidSadCnt].Freqs =
++                                  pDis->EdidBlock[blockPtr + i + 1];
++                               pDis->EdidAFmts[pDis->EdidSadCnt].Byte3 =
++                                  pDis->EdidBlock[blockPtr + i + 2];
++                               pDis->EdidSadCnt++;
++                            }
++                         }
++                            else
++                            {
++                             /* do nothing */
++                            }
++                         }
++                         break;
++                      case E_CEA_VSDB:         /* We have a VSDB */
++                         /* 5 bytes expected, but this is EDID land so double check*/
++                         if (blockLength >= 5)
++                         {
++                            if ((blockPtr) < (EDID_BLOCK_SIZE - 5))
++                            {
++                            if ((pDis->EdidBlock[blockPtr + 1] == 0x03) &&
++                                (pDis->EdidBlock[blockPtr + 2] == 0x0C) &&
++                                (pDis->EdidBlock[blockPtr + 3] == 0x00))
++                            {
++                               pDis->EdidSinkType = HDMITX_SINK_HDMI;
++                                   if ((blockPtr) < (EDID_BLOCK_SIZE - 5))
++                                   {
++                               pDis->EdidSourceAddress = 
++                                  ((UInt16)pDis->EdidBlock[blockPtr + 4] << 8) +
++                                  pDis->EdidBlock[blockPtr + 5];
++                            }
++                            else
++                            {
++                                /* do nothing */
++                                   }
++                                }
++                                else
++                                {
++                               pDis->EdidSinkType = HDMITX_SINK_DVI;
++                            }
++                         }
++                            else
++                            {
++                                /* do nothing */
++                            }
++                         }
++
++                         if (blockLength >= 6)   /* Space for byte with AI flag */
++                         {   /* Mask AI bit */
++                            if ((blockPtr ) < (EDID_BLOCK_SIZE - 6))
++                            {
++                            if((pDis->EdidBlock[blockPtr + 6] & 0x80) == 0x80)
++                            {
++                               pDis->EdidSinkAi = True;
++                            }
++                         }
++                            else
++                            {
++                              /* do nothing */
++                            }
++                         }
++
++                         /* Read Max_TMDS_Clock */
++                         if (blockLength >= 7)  
++                             pDis->EdidExtraVsdbData.maxTmdsClock = pDis->EdidBlock[blockPtr + 7];
++                         else
++                             pDis->EdidExtraVsdbData.maxTmdsClock = 0;
++
++
++                         /* latency, HDMI Video present and content type fields */
++                         if (blockLength >= 8) {
++                             if ((blockPtr) < (EDID_BLOCK_SIZE - 10))
++                             {
++                             /* Read CNC0~3 */
++                             pDis->EdidExtraVsdbData.cnc0 = pDis->EdidBlock[blockPtr + 8] & 0x01;  /* 1=True, 0=False */
++                             pDis->EdidExtraVsdbData.cnc1 = (pDis->EdidBlock[blockPtr + 8] & 0x02) >> 1;
++                             pDis->EdidExtraVsdbData.cnc2 = (pDis->EdidBlock[blockPtr + 8] & 0x04) >> 2;
++                             pDis->EdidExtraVsdbData.cnc3 = (pDis->EdidBlock[blockPtr + 8] & 0x08) >> 3;
++                                                          
++                             if( (pDis->EdidBlock[blockPtr + 8] & 0xC0) == 0xC0 ) {
++                                 /* Read video_latency, audio_latency, I_video_latency, I_audio_latency */
++
++                                     if ((blockPtr) < (EDID_BLOCK_SIZE - 12))
++                                     {
++                                 pDis->EdidLatency.Edidvideo_latency = pDis->EdidBlock[blockPtr + 9];
++                                 pDis->EdidLatency.Edidaudio_latency = pDis->EdidBlock[blockPtr + 10];
++                                 pDis->EdidLatency.EdidIvideo_latency = pDis->EdidBlock[blockPtr + 11];
++                                 pDis->EdidLatency.EdidIaudio_latency = pDis->EdidBlock[blockPtr + 12];
++
++                                 pDis->EdidLatency.latency_available = True;
++                                 pDis->EdidLatency.Ilatency_available = True;
++
++                                 offset3D = 13;  /* offset to the '3D_present' field */
++
++                                     }
++                                     else
++                                     {
++                                        /* do nothing */
++                                     }									 
++                             }
++                             else if ((pDis->EdidBlock[blockPtr + 8] & 0x80) == 0x80) {
++                                 /* Read video_latency, audio_latency */
++
++                                 pDis->EdidLatency.Edidvideo_latency = pDis->EdidBlock[blockPtr + 9];
++                                 pDis->EdidLatency.Edidaudio_latency = pDis->EdidBlock[blockPtr + 10];
++
++                                 pDis->EdidLatency.latency_available = True;
++
++                                 offset3D = 11;
++                             }
++                             else {
++                                pDis->EdidLatency.latency_available = False;
++                                pDis->EdidLatency.Ilatency_available = False;
++                                offset3D = 9;
++                             }
++
++                             /* Read HDMI_Video_present */
++                             pDis->EdidExtraVsdbData.hdmiVideoPresent = (pDis->EdidBlock[blockPtr + 8] & 0x20) >> 5;
++
++                             }
++                             else
++                             {
++                                 /* do nothing */
++                             }
++                         }
++                         else {
++                             pDis->EdidLatency.latency_available      = False;
++                             pDis->EdidLatency.Ilatency_available     = False;
++                             pDis->EdidExtraVsdbData.hdmiVideoPresent = False;
++                             pDis->EdidExtraVsdbData.cnc0 = False;
++                             pDis->EdidExtraVsdbData.cnc1 = False;
++                             pDis->EdidExtraVsdbData.cnc2 = False;
++                             pDis->EdidExtraVsdbData.cnc3 = False;
++                         }
++
++
++                         /* 3D data fields according to HDMI 1.4a standard */
++                         if (pDis->EdidExtraVsdbData.hdmiVideoPresent) {
++
++                             /* read 3D_present */
++                             pDis->EdidExtraVsdbData.h3DPresent = (pDis->EdidBlock[blockPtr + offset3D] & 0x80) >> 7;
++                             /* read 3D_Multi_present */
++                             pDis->EdidExtraVsdbData.h3DMultiPresent = (pDis->EdidBlock[blockPtr + offset3D] & 0x60) >> 5;
++                             /* read image_Size */
++                             pDis->EdidExtraVsdbData.imageSize = (pDis->EdidBlock[blockPtr + offset3D] & 0x18) >> 3;
++                             
++                             /* read HDMI_3D_LEN and HDMI_XX_LEN */
++                             offset3D += 1;
++                             pDis->EdidExtraVsdbData.hdmi3DLen  = pDis->EdidBlock[blockPtr + offset3D] & 0x1F;
++                             pDis->EdidExtraVsdbData.hdmiVicLen = (pDis->EdidBlock[blockPtr + offset3D] & 0xE0) >> 5;
++
++                             if((pDis->EdidExtraVsdbData.hdmi3DLen + pDis->EdidExtraVsdbData.hdmiVicLen) > 0)
++                             {
++                                 /* copy the rest of the bytes*/
++                                 lmemcpy(pDis->EdidExtraVsdbData.ext3DData, &(pDis->EdidBlock[blockPtr + offset3D + 1]), blockLength-offset3D);
++                             }
++                         }
++                         else {
++                             pDis->EdidExtraVsdbData.h3DPresent       = False;
++                             pDis->EdidExtraVsdbData.h3DMultiPresent  = 0;
++                             pDis->EdidExtraVsdbData.imageSize        = 0;
++                             pDis->EdidExtraVsdbData.hdmi3DLen        = 0;
++                             pDis->EdidExtraVsdbData.hdmiVicLen       = 0;
++                         }
++
++
++                         break;
++
++
++                     case E_CEA_EXTENDED: /* Use extended Tag */
++
++                        /* we need to read the extended tag code */
++
++                          if ((blockPtr ) < (EDID_BLOCK_SIZE -2))
++                          {
++                          switch ( pDis->EdidBlock[blockPtr + 1]) 
++                          {
++                            case EXT_CEA_COLORIMETRY_DB:
++
++                                /* look at xvYCC709 and xvYCC601 support */
++                                pDis->EdidCeaXVYCCFlags = pDis->EdidBlock[blockPtr + 2];
++
++                            break;
++                          }
++                          }
++                          else
++                          {
++                             /* do nothing */
++                          }
++                        break;  /* E_CEA_EXTENDED */
++
++
++
++                      default:
++                         break;
++                   }
++                   blockPtr += (blockLength + 1);  /* Point to next block */
++                }
++             }
++             dtdFound = True;
++
++             for (i = 0; (i < EDID_NUMBER_MAX_DTD_BLK_1) && (dtdFound); i++) /* search possible DTD blocks in block 1 */
++             {   
++                blockPtr = ((UInt8)pDis->EdidBlock[EDID_BLK1_OFFSET_BASE_DTD]) + ((UInt8)(i * EDID_DTD_BLK_SIZE));
++                if ((blockPtr + EDID_DTD_BLK_SIZE - 1) < EDID_BLOCK_SIZE)
++                {
++                   dtdFound = storeDtdBlock(pDis, blockPtr);
++                }
++             }
++
++             break;
++            
++
++          case EDID_BLOCK_MAP:
++             /* BLOCK MAP */
++
++              if (pDis->EdidBlockCnt > 1) {
++                  if ((pDis->EdidBlockCnt - 1) < EDID_BLOCK_SIZE)
++                  {
++                  if (pDis->EdidBlock[pDis->EdidBlockCnt - 1] == EDID_CEA_EXTENSION) {
++                   /* Some devices have been incorrectly designed so that the block map is not counted in the */
++                   /* extension count. Design of compliant devices should take compatibility with those non-compliant */
++                   /* devices into consideration. */
++                      pDis->EdidBlockCnt = pDis->EdidBlockCnt + 1;
++                  }
++              }
++                  else
++                  {
++                      /* do nothing */
++                  }
++              }
++
++
++             break;
++             
++
++       }
++       
++    }
++    
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* storeDtdBlock                                                              */
++/*============================================================================*/
++static Bool
++storeDtdBlock
++(   
++    tmHdmiTxobject_t    *pDis,      /* Device instance strucure holding block */
++    UInt8               blockPtr                     
++)
++{
++
++    Bool    dtdFound = False;
++
++    if (blockPtr >= (EDID_BLOCK_SIZE-17))
++    {
++        /* do nothing */
++        return dtdFound;
++    }
++
++    /* First, select blocks that are DTDs [CEA861C A.2.10] */
++    if (((pDis->EdidBlock[blockPtr+0] != 0) ||
++         (pDis->EdidBlock[blockPtr+1] != 0) ||
++         (pDis->EdidBlock[blockPtr+2] != 0) ||
++         (pDis->EdidBlock[blockPtr+4] != 0))
++		&&
++		 (pDis->NbDTDStored < NUMBER_DTD_STORED))
++    {   /* Store the first DTD we find, others will be skipped */
++        pDis->EdidDTD[pDis->NbDTDStored].uPixelClock =
++            ((UInt16)pDis->EdidBlock[blockPtr+1] << 8) |
++                (UInt16)pDis->EdidBlock[blockPtr+0];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uHActivePixels =
++            (((UInt16)pDis->EdidBlock[blockPtr+4] & 0x00F0) << 4) |
++                (UInt16)pDis->EdidBlock[blockPtr+2];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uHBlankPixels = 
++            (((UInt16)pDis->EdidBlock[blockPtr+4] & 0x000F) << 8) |
++                (UInt16)pDis->EdidBlock[blockPtr+3];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uVActiveLines =
++            (((UInt16)pDis->EdidBlock[blockPtr+7] & 0x00F0) << 4) |
++                (UInt16)pDis->EdidBlock[blockPtr+5];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uVBlankLines =
++            (((UInt16)pDis->EdidBlock[blockPtr+7] & 0x000F) << 8) |
++                (UInt16)pDis->EdidBlock[blockPtr+6];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uHSyncOffset =
++            (((UInt16)pDis->EdidBlock[blockPtr+11] & 0x00C0) << 2) |
++                (UInt16)pDis->EdidBlock[blockPtr+8];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uHSyncWidth =
++            (((UInt16)pDis->EdidBlock[blockPtr+11] & 0x0030) << 4) |
++                (UInt16)pDis->EdidBlock[blockPtr+9];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uVSyncOffset =
++            (((UInt16)pDis->EdidBlock[blockPtr+11] & 0x000C) << 2) |
++            (((UInt16)pDis->EdidBlock[blockPtr+10] & 0x00F0) >> 4);
++
++        pDis->EdidDTD[pDis->NbDTDStored].uVSyncWidth =
++            (((UInt16)pDis->EdidBlock[blockPtr+11] & 0x0003) << 4) |
++                ((UInt16)pDis->EdidBlock[blockPtr+10] & 0x000F);
++
++        pDis->EdidDTD[pDis->NbDTDStored].uHImageSize =
++            (((UInt16)pDis->EdidBlock[blockPtr+14] & 0x00F0) << 4) |
++                (UInt16)pDis->EdidBlock[blockPtr+12];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uVImageSize = 
++            (((UInt16)pDis->EdidBlock[blockPtr+14] & 0x000F) << 8) |
++                (UInt16)pDis->EdidBlock[blockPtr+13];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uHBorderPixels =
++            (UInt16)pDis->EdidBlock[blockPtr+15];
++
++        pDis->EdidDTD[pDis->NbDTDStored].uVBorderPixels =
++            (UInt16)pDis->EdidBlock[blockPtr+16];
++
++        pDis->EdidDTD[pDis->NbDTDStored].Flags = pDis->EdidBlock[blockPtr+17];
++
++        pDis->NbDTDStored++;
++
++        dtdFound = True;    /* Stop any more DTDs being parsed */
++    }
++
++    return (dtdFound);
++}
++
++
++/*============================================================================*/
++/* storeMonitorBlock                                                          */
++/*============================================================================*/
++static Bool
++storeMonitorDescriptor
++(   
++    tmHdmiTxobject_t    *pDis,      /* Device instance strucure holding block */
++    UInt8               blockPtr                     
++)
++{
++
++    Bool    dtdFound = False;
++
++    if (blockPtr >= (EDID_BLOCK_SIZE-5))
++    {
++        /* do nothing */
++        return dtdFound;
++    }
++
++    /* First, select blocks that are DTDs [CEA861C A.2.10] */
++    if ((pDis->EdidBlock[blockPtr+0] == 0) &&
++        (pDis->EdidBlock[blockPtr+1] == 0) &&
++        (pDis->EdidBlock[blockPtr+2] == 0)
++       )
++    {
++        if (pDis->EdidBlock[blockPtr+3] == EDID_MONITOR_NAME_DESC_DATA_TYPE)
++        {
++            if (pDis->EdidFirstMonitorDescriptor.bDescRecord == False)
++            {
++                pDis->EdidFirstMonitorDescriptor.bDescRecord = True;
++                lmemcpy(&(pDis->EdidFirstMonitorDescriptor.uMonitorName) , 
++                        &(pDis->EdidBlock[blockPtr+5]), EDID_MONITOR_DESCRIPTOR_SIZE);
++                dtdFound = True;
++            }
++            else if ((pDis->EdidOtherMonitorDescriptor.bDescRecord == False))
++            {
++                pDis->EdidOtherMonitorDescriptor.bDescRecord = True;
++                lmemcpy(&(pDis->EdidOtherMonitorDescriptor.uOtherDescriptor) , 
++                        &(pDis->EdidBlock[blockPtr+5]), EDID_MONITOR_DESCRIPTOR_SIZE);
++                dtdFound = True;
++            }
++        }
++        else if (pDis->EdidBlock[blockPtr+3] == EDID_MONITOR_RANGE_DESC_DATA_TYPE)
++        {
++            if (pDis->EdidSecondMonitorDescriptor.bDescRecord == False)
++            {
++                if (blockPtr < (EDID_BLOCK_SIZE-9))
++                {
++                pDis->EdidSecondMonitorDescriptor.bDescRecord = True;
++                pDis->EdidSecondMonitorDescriptor.uMinVerticalRate = pDis->EdidBlock[blockPtr+5];
++                pDis->EdidSecondMonitorDescriptor.uMaxVerticalRate = pDis->EdidBlock[blockPtr+6];
++                pDis->EdidSecondMonitorDescriptor.uMinHorizontalRate = pDis->EdidBlock[blockPtr+7];
++                pDis->EdidSecondMonitorDescriptor.uMaxHorizontalRate = pDis->EdidBlock[blockPtr+8];
++                pDis->EdidSecondMonitorDescriptor.uMaxSupportedPixelClk = pDis->EdidBlock[blockPtr+9];
++                dtdFound = True;
++                }
++                else
++                {
++                    /* do nothing */
++                }
++            }
++        }
++    }
++
++    return (dtdFound);
++
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetLatencyInfo                                             */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EdidGetLatencyInfo
++(
++    tmUnitSelect_t  txUnit,
++    tmbslHdmiTxEdidLatency_t * pEdidLatency
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pEdidLatency == Null)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        /* allow if edid are read or if there are a chk error on an other block than block 0 */
++
++        *pEdidLatency = pDis->EdidLatency;
++    }
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++    return err;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989EdidGetExtraVsdbData                                             */
++/*============================================================================*/
++tmErrorCode_t tmbslTDA9989EdidGetExtraVsdbData
++(
++    tmUnitSelect_t                  txUnit,
++    tmbslHdmiTxEdidExtraVsdbData_t  **pExtraVsdbData
++)
++{
++    tmHdmiTxobject_t    *pDis;      /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pExtraVsdbData == Null)
++
++    if ((pDis->EdidStatus == HDMITX_EDID_READ) ||
++        (pDis->EdidStatus == HDMITX_EDID_ERROR_CHK))
++    {
++        /* allow if edid are read or if there are a chk error on an other block than block 0 */
++        *pExtraVsdbData = &(pDis->EdidExtraVsdbData);
++    }
++    else
++    {
++        /* Not allowed if EdidStatus value is not valid */
++        err = TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE; 
++    }
++    return err;
++}
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Edid_l.h b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Edid_l.h
+new file mode 100755
+index 0000000..25cad98
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Edid_l.h
+@@ -0,0 +1,62 @@
++/**
++ * Copyright (C) 2009 Koninklijke Philips Electronics N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of Koninklijke Philips Electronics N.V. and is confidential in
++ * nature. Under no circumstances is this software to be  exposed to or placed
++ * under an Open Source License of any type without the expressed written
++ * permission of Koninklijke Philips Electronics N.V.
++ *
++ * \file          tmbslTDA9989_Edid_l.h
++ *
++ * \version       $Revision: 2 $
++ *
++ * \date          $Date: 04/07/07 17:00 $
++ *
++ *
++*/
++
++#ifndef TMBSLTDA9989_EDID_L_H
++#define TMBSLTDA9989_EDID_L_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       MACRO DEFINITIONS                                    */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                       EXTERN DATA DEFINITION                               */
++/*============================================================================*/
++
++extern tmErrorCode_t
++EdidBlockAvailable (tmUnitSelect_t txUnit, Bool * pSendEDIDCallback);
++
++extern tmErrorCode_t
++ClearEdidRequest (tmUnitSelect_t txUnit);
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMBSLTDA9989_EDID_L_H */
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_HDCP.c b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_HDCP.c
+new file mode 100755
+index 0000000..33ab4d1
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_HDCP.c
+@@ -0,0 +1,655 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_HDCP.c
++ *
++ * \version       $Revision: 2 $
++ *
++ */
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#include "tmbslHdmiTx_types.h"
++#include "tmbslTDA9989_Functions.h"
++#include "tmbslTDA9989_local.h"
++#include "tmbslTDA9989_State_l.h"
++#include "tmbslTDA9989_InOut_l.h"
++
++/*============================================================================*/
++/*                     TYPES DECLARATIONS                                     */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS EXPORTED                      */
++/*============================================================================*/
++
++/**
++ * Table of registers to switch HDMI HDCP mode off for DVI
++ */
++
++CONST_DAT tmHdmiTxRegMaskVal_t kVoutHdcpOff[] =
++   {
++      {E_REG_P00_TBG_CNTRL_1_W,   E_MASKREG_P00_TBG_CNTRL_1_dwin_dis, 1},
++      {E_REG_P12_TX33_RW,    E_MASKREG_P12_TX33_hdmi,       0},
++      {0,0,0}
++   };
++
++/**
++ * Table of registers to switch HDMI HDCP mode on for HDMI
++ */
++CONST_DAT tmHdmiTxRegMaskVal_t kVoutHdcpOn[] =
++   {
++      {E_REG_P00_TBG_CNTRL_1_W,   E_MASKREG_P00_TBG_CNTRL_1_dwin_dis, 0},
++      {E_REG_P11_ENC_CNTRL_RW,    E_MASKREG_P11_ENC_CNTRL_ctl_code,   1},
++      {E_REG_P12_TX33_RW,    E_MASKREG_P12_TX33_hdmi,       1},
++      {0,0,0}
++   };
++
++#ifdef __LINUX_ARM_ARCH__
++
++#include <linux/kernel.h>
++
++typedef struct {
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpCheck)
++   (
++    tmUnitSelect_t          txUnit,
++    UInt16                  uTimeSinceLastCallMs,
++    tmbslHdmiTxHdcpCheck_t  *pResult
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpConfigure)
++   (
++    tmUnitSelect_t           txUnit,
++    UInt8                    slaveAddress,
++    tmbslHdmiTxHdcpTxMode_t  txMode,
++    tmbslHdmiTxHdcpOptions_t options,
++    UInt16                   uCheckIntervalMs,
++    UInt8                    uChecksToDo
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpDownloadKeys)
++   (
++    tmUnitSelect_t          txUnit,
++    UInt16                  seed,
++    tmbslHdmiTxDecrypt_t    keyDecryption
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpEncryptionOn)
++   (
++    tmUnitSelect_t  txUnit,
++    Bool            bOn
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpGetOtp)
++   (
++    tmUnitSelect_t          txUnit,
++    UInt8                   otpAddress,
++    UInt8                   *pOtpData
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpGetT0FailState)
++   (
++    tmUnitSelect_t  txUnit,
++    UInt8           *pFailState
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpHandleBCAPS)
++   (
++    tmUnitSelect_t  txUnit
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpHandleBKSV)
++   (
++    tmUnitSelect_t  txUnit,
++    UInt8           *pBksv,
++    Bool            *pbCheckRequired  /* May be null, but only for testing */
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpHandleBKSVResult)
++   (
++    tmUnitSelect_t  txUnit,
++    Bool            bSecure
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpHandleBSTATUS)
++   (
++    tmUnitSelect_t  txUnit,
++    UInt16          *pBstatus   /* May be null */
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpHandleENCRYPT)
++   (
++    tmUnitSelect_t  txUnit
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpHandlePJ)
++   (
++    tmUnitSelect_t  txUnit
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpHandleSHA_1)
++   (
++    tmUnitSelect_t  txUnit,
++    UInt8           maxKsvDevices,
++    UInt8           *pKsvList,          /* May be null if maxKsvDevices is 0 */
++    UInt8           *pnKsvDevices,      /* May be null if maxKsvDevices is 0 */
++    UInt8           *pDepth             /* Connection tree depth returned with KSV list */
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpHandleSHA_1Result)
++   (
++    tmUnitSelect_t  txUnit,
++    Bool            bSecure
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpHandleT0)
++   (
++    tmUnitSelect_t  txUnit
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpInit)
++   (
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxVidFmt_t voutFmt,
++    tmbslHdmiTxVfreq_t  voutFreq
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpRun)
++   (
++    tmUnitSelect_t  txUnit
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpStop)
++   (
++    tmUnitSelect_t  txUnit
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989HdcpGetSinkCategory)
++   (
++    tmUnitSelect_t txUnit,
++    tmbslHdmiTxSinkCategory_t *category
++    );
++   tmErrorCode_t
++   (*tmbslTDA9989handleBKSVResultSecure)
++   (
++    tmUnitSelect_t txUnit
++    );
++   tmErrorCode_t (*f1)(tmHdmiTxobject_t *pDis);
++   int (*f2)(tmHdmiTxobject_t *pDis);
++} hdcp_private_t;
++
++#include <linux/module.h> /* need for EXPORT_SYMBOL */
++
++hdcp_private_t *h;
++
++void register_hdcp_private(hdcp_private_t *hdcp)
++{
++   h = hdcp;
++}
++EXPORT_SYMBOL(register_hdcp_private);
++ 
++tmErrorCode_t rej_f1(tmHdmiTxobject_t *pDis) {
++   return (h?h->f1(pDis):0);
++}
++
++int rej_f2(tmHdmiTxobject_t *pDis) {
++   return (h?h->f2(pDis):0);
++}
++
++tmErrorCode_t rej_f3(tmUnitSelect_t txUnit) {
++   return (h?h->tmbslTDA9989handleBKSVResultSecure(txUnit):TM_OK);
++}
++
++#endif
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpCheck                                                      */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpCheck
++(
++ tmUnitSelect_t          txUnit,
++ UInt16                  uTimeSinceLastCallMs,
++ tmbslHdmiTxHdcpCheck_t  *pResult
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpCheck
++             (
++              txUnit,
++              uTimeSinceLastCallMs,
++              pResult
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpConfigure                                                   */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpConfigure
++(
++ tmUnitSelect_t           txUnit,
++ UInt8                    slaveAddress,
++ tmbslHdmiTxHdcpTxMode_t  txMode,
++ tmbslHdmiTxHdcpOptions_t options,
++ UInt16                   uCheckIntervalMs,
++ UInt8                    uChecksToDo
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpConfigure
++             (
++              txUnit,
++              slaveAddress,
++              txMode,
++              options,
++              uCheckIntervalMs,
++              uChecksToDo
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpDownloadKeys                                                */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpDownloadKeys
++(
++ tmUnitSelect_t          txUnit,
++ UInt16                  seed,
++ tmbslHdmiTxDecrypt_t    keyDecryption
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpDownloadKeys
++             (
++              txUnit,
++              seed,
++              keyDecryption
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpEncryptionOn                                                */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpEncryptionOn
++(
++ tmUnitSelect_t  txUnit,
++ Bool            bOn
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpEncryptionOn
++             (
++              txUnit,
++              bOn
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpGetOtp                                                      */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpGetOtp
++(
++ tmUnitSelect_t          txUnit,
++ UInt8                   otpAddress,
++ UInt8                   *pOtpData
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpGetOtp
++             (
++              txUnit,
++              otpAddress,
++              pOtpData
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpGetT0FailState                                              */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpGetT0FailState
++(
++ tmUnitSelect_t  txUnit,
++ UInt8           *pFailState
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpGetT0FailState
++             (
++              txUnit,
++              pFailState
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpHandleBCAPS                                                 */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleBCAPS
++(
++ tmUnitSelect_t  txUnit
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpHandleBCAPS
++             (
++              txUnit
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpHandleBKSV                                                  */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleBKSV
++(
++ tmUnitSelect_t  txUnit,
++ UInt8           *pBksv,
++ Bool            *pbCheckRequired  /* May be null, but only for testing */
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpHandleBKSV
++             (
++              txUnit,
++              pBksv,
++              pbCheckRequired  /* May be null, but only for testing */
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpHandleBKSVResult                                            */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleBKSVResult
++(
++ tmUnitSelect_t  txUnit,
++ Bool            bSecure
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpHandleBKSVResult
++             (
++              txUnit,
++              bSecure
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpHandleBSTATUS                                               */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleBSTATUS
++(
++ tmUnitSelect_t  txUnit,
++ UInt16          *pBstatus   /* May be null */
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpHandleBSTATUS
++             (
++              txUnit,
++              pBstatus   /* May be null */
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpHandleENCRYPT                                               */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleENCRYPT
++(
++ tmUnitSelect_t  txUnit
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpHandleENCRYPT
++             (
++              txUnit
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpHandlePJ                                                    */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandlePJ
++(
++ tmUnitSelect_t  txUnit
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpHandlePJ
++             (
++              txUnit
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpHandleSHA_1                                                 */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleSHA_1
++(
++ tmUnitSelect_t  txUnit,
++ UInt8           maxKsvDevices,
++ UInt8           *pKsvList,          /* May be null if maxKsvDevices is 0 */
++ UInt8           *pnKsvDevices,      /* May be null if maxKsvDevices is 0 */
++ UInt8           *pDepth             /* Connection tree depth returned with KSV list */
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpHandleSHA_1
++             (
++              txUnit,
++              maxKsvDevices,
++              pKsvList,          /* May be null if maxKsvDevices is 0 */
++              pnKsvDevices,      /* May be null if maxKsvDevices is 0 */
++              pDepth             /* Connection tree depth returned with KSV list */
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpHandleSHA_1Result                                           */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleSHA_1Result
++(
++ tmUnitSelect_t  txUnit,
++ Bool            bSecure
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpHandleSHA_1Result
++             (
++              txUnit,
++              bSecure
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpHandleT0                                                    */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpHandleT0
++(
++ tmUnitSelect_t  txUnit
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpHandleT0
++             (
++              txUnit
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpInit                                                        */
++/* RETIF_REG_FAIL NOT USED HERE AS ALL ERRORS SHOULD BE TRAPPED IN ALL BUILDS */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpInit
++(
++ tmUnitSelect_t      txUnit,
++ tmbslHdmiTxVidFmt_t voutFmt,
++ tmbslHdmiTxVfreq_t  voutFreq
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpInit
++             (
++              txUnit,
++              voutFmt,
++              voutFreq
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpRun                                                         */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpRun
++(
++ tmUnitSelect_t  txUnit
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpRun
++             (
++              txUnit
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpStop                                                        */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpStop
++(
++ tmUnitSelect_t  txUnit
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpStop
++             (
++              txUnit
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HdcpGetSinkCategory                                            */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpGetSinkCategory
++(
++ tmUnitSelect_t              txUnit,
++ tmbslHdmiTxSinkCategory_t   *category
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989HdcpGetSinkCategory
++             (
++              txUnit,
++              category
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++
++
++
++/*============================================================================*/
++/* tmbslTDA9989handleBKSVResultSecure                                         */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989handleBKSVResultSecure
++(
++ tmUnitSelect_t  txUnit
++ )
++{
++#ifdef __LINUX_ARM_ARCH__
++   if (h) return h->tmbslTDA9989handleBKSVResultSecure
++             (
++              txUnit
++              );
++/*   else {printk("%s is empty\n",__func__);}*/
++#endif
++   return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_HDCP_l.h b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_HDCP_l.h
+new file mode 100755
+index 0000000..7e74ab6
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_HDCP_l.h
+@@ -0,0 +1,72 @@
++/**
++ * Copyright (C) 2008 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_HDCP_l.h
++ *
++ * \version       %version: 2 %
++ *
++ * \date          %date_modified: %
++ *
++ * \brief         BSL driver component local definitions for the TDA998x
++ *                HDMI Transmitter.
++ *
++ * \section info  Change Information
++ *
++ *
++*/
++
++#ifndef TMBSLTDA9989_HDCP_L_H
++#define TMBSLTDA9989_HDCP_L_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#ifdef __LINUX_ARM_ARCH__
++
++#define HDCP_F1 { \
++   int rej_f2(tmHdmiTxobject_t *pDis);          \
++   regVal = rej_f2(pDis);                       \
++   }
++
++#define HDCP_F2 { \
++   tmErrorCode_t rej_f1(tmHdmiTxobject_t *pDis);    \
++   err = rej_f1(pDis);                                  \
++   RETIF(err != TM_OK, err);                            \
++}
++
++#define HDCP_F3 { \
++   if (fInterruptStatus & (1 << HDMITX_CALLBACK_INT_R0)) \
++      {                                                  \
++         tmErrorCode_t rej_f3(tmUnitSelect_t txUnit);    \
++         err = rej_f3(txUnit);                           \
++         RETIF(err != TM_OK, err);                       \
++      }                                                  \
++}
++
++#else
++
++#define HDCP_F1 {regVal = 0;}
++
++#define HDCP_F2 {}
++
++#define HDCP_F3 {}
++
++#endif /*TMFL_HDCP_SUPPORT*/
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMBSLTDA9989_HDCP_L_H */
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_InOut.c b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_InOut.c
+new file mode 100755
+index 0000000..8ff0b65
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_InOut.c
+@@ -0,0 +1,5101 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_InOut.c
++ *
++ * \version       %version: 3 %
++ *
++ *
++*/
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#include <linux/kernel.h>
++#include <linux/module.h>
++#endif
++
++#include "tmbslHdmiTx_types.h"
++#include "tmbslTDA9989_Functions.h"
++#include "tmbslTDA9989_local.h"
++#include "tmbslTDA9989_HDCP_l.h"
++#include "tmbslTDA9989_State_l.h"
++#include "tmbslTDA9989_Misc_l.h"
++#include "tmbslTDA9989_InOut_l.h"
++
++/*============================================================================*/
++/*                     TYPES DECLARATIONS                                     */
++/*============================================================================*/
++
++#define SSD_UNUSED_VALUE 0xF0
++
++#ifdef FORMAT_PC
++#define DEPTH_COLOR_PC 1  /* PC_FORMAT only 8 bits available */
++#endif /* FORMAT_PC */
++
++#define REG_VAL_SEL_AIP_SPDIF   0
++#define REG_VAL_SEL_AIP_I2S     1
++#define REG_VAL_SEL_AIP_OBA     2
++#define REG_VAL_SEL_AIP_DST     3
++#define REG_VAL_SEL_AIP_HBR     5
++
++struct vic2reg {
++   unsigned char vic;
++   unsigned char reg;
++};
++
++struct sync_desc {
++   UInt16 Vs2;
++   UInt8 pix_rep;
++   UInt8 v_toggle;
++   UInt8 h_toggle;
++   UInt16 hfp;    /* Output values for Vs/Hs input sync */
++   UInt16 vfp;
++   UInt16 href; /* Output values for all other input sync sources */
++   UInt16 vref;
++};
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS EXPORTED                      */
++/*============================================================================*/
++
++extern CONST_DAT tmHdmiTxRegMaskVal_t kVoutHdcpOff[];
++extern CONST_DAT tmHdmiTxRegMaskVal_t kVoutHdcpOn[];
++
++/**
++ * Lookup table of input port control registers and their swap and mirror masks
++ */
++CONST_DAT tmbslTDA9989RegVip
++ kRegVip[HDMITX_VIN_PORT_MAP_TABLE_LEN] =
++{
++    {E_REG_P00_VIP_CNTRL_0_W,
++        E_MASKREG_P00_VIP_CNTRL_0_swap_a,
++        E_MASKREG_P00_VIP_CNTRL_0_mirr_a
++    }, /* Port group 0 */
++    {E_REG_P00_VIP_CNTRL_0_W,
++        E_MASKREG_P00_VIP_CNTRL_0_swap_b,
++        E_MASKREG_P00_VIP_CNTRL_0_mirr_b
++    }, /* Port group 1 */
++    {E_REG_P00_VIP_CNTRL_1_W,
++        E_MASKREG_P00_VIP_CNTRL_1_swap_c,
++        E_MASKREG_P00_VIP_CNTRL_1_mirr_c
++    }, /* Port group 2 */
++    {E_REG_P00_VIP_CNTRL_1_W,
++        E_MASKREG_P00_VIP_CNTRL_1_swap_d,
++        E_MASKREG_P00_VIP_CNTRL_1_mirr_d
++    }, /* Port group 3 */
++    {E_REG_P00_VIP_CNTRL_2_W,
++        E_MASKREG_P00_VIP_CNTRL_2_swap_e,
++        E_MASKREG_P00_VIP_CNTRL_2_mirr_e
++    }, /* Port group 4 */
++    {E_REG_P00_VIP_CNTRL_2_W,
++        E_MASKREG_P00_VIP_CNTRL_2_swap_f,
++        E_MASKREG_P00_VIP_CNTRL_2_mirr_f
++    }  /* Port group 5 */
++};
++
++/**
++ * Table of PLL settings registers to configure for all video input format (vinFmt)
++ */
++CONST_DAT tmHdmiTxRegMaskVal_t kCommonPllCfg[] =
++{
++    {E_REG_P02_PLL_SERIAL_1_RW, E_MASKREG_ALL,  0x00},
++    {E_REG_P02_PLL_SERIAL_2_RW, E_MASKREG_ALL,  0x01},
++    {E_REG_P02_PLL_SERIAL_3_RW, E_MASKREG_ALL,  0x00},
++    {E_REG_P02_SERIALIZER_RW,   E_MASKREG_ALL,  0x00},
++    {E_REG_P02_BUFFER_OUT_RW,   E_MASKREG_ALL,  0x00},
++    {E_REG_P02_PLL_SCG1_RW,     E_MASKREG_ALL,  0x00},
++    {E_REG_P02_AUDIO_DIV_RW,    E_MASKREG_ALL,  0x03},
++    /*{E_REG_P02_TEST2_RW,        E_MASKREG_ALL,  0x00},*/
++    {E_REG_P02_SEL_CLK_RW,      E_MASKREG_ALL,  0x09},
++    {0,0,0}
++};
++
++/**
++ * Table of PLL settings registers to configure double mode pixel rate,
++ * vinFmt other than 480i or 576i
++ */
++CONST_DAT tmHdmiTxRegMaskVal_t kDoublePrateVfmtOtherPllCfg[] =
++{
++    {E_REG_P02_PLL_SCG2_RW,     E_MASKREG_ALL,  0x00},
++    {0,0,0}
++};
++
++/**
++ * Table of PLL settings registers to configure for single mode pixel rate,
++ * vinFmt 480i or 576i only
++ */
++CONST_DAT tmHdmiTxRegMaskVal_t kSinglePrateVfmt480i576iPllCfg[] =
++{
++    {E_REG_P02_PLL_SCG2_RW,     E_MASKREG_ALL,  0x11},
++    {0,0,0}
++};
++
++/**
++ * Table of PLL settings registers to configure single mode pixel rate,
++ * vinFmt other than 480i or 576i
++ */
++CONST_DAT tmHdmiTxRegMaskVal_t kSinglePrateVfmtOtherPllCfg[] =
++{
++    {E_REG_P02_PLL_SCG2_RW,     E_MASKREG_ALL,  0x10},
++    {0,0,0}
++};
++
++/**
++ * Table of PLL settings registers to configure for single repeated mode pixel rate,
++ * vinFmt 480i or 576i only
++ */
++CONST_DAT tmHdmiTxRegMaskVal_t kSrepeatedPrateVfmt480i576iPllCfg[] =
++{
++    {E_REG_P02_PLL_SCG2_RW,     E_MASKREG_ALL,  0x01},
++    {0,0,0}
++};
++
++/**
++ * Table of PLL settings registers to configure for 480i and 576i vinFmt
++ */
++CONST_DAT tmHdmiTxRegMaskVal_t kVfmt480i576iPllCfg[] =
++{
++    {E_REG_P02_PLL_SCGN1_RW,    E_MASKREG_ALL,  0x14},
++    {E_REG_P02_PLL_SCGN2_RW,    E_MASKREG_ALL,  0x00},
++    {E_REG_P02_PLL_SCGR1_RW,    E_MASKREG_ALL,  0x0A},
++    {E_REG_P02_PLL_SCGR2_RW,    E_MASKREG_ALL,  0x00},
++    {0,0,0}
++};
++
++/**
++ * Table of PLL settings registers to configure for other vinFmt than 480i and 576i
++ */
++CONST_DAT tmHdmiTxRegMaskVal_t kVfmtOtherPllCfg[] =
++{
++    {E_REG_P02_PLL_SCGN1_RW,    E_MASKREG_ALL,  0xFA},
++    {E_REG_P02_PLL_SCGN2_RW,    E_MASKREG_ALL,  0x00},
++    {E_REG_P02_PLL_SCGR1_RW,    E_MASKREG_ALL,  0x5B},
++    {E_REG_P02_PLL_SCGR2_RW,    E_MASKREG_ALL,  0x00},
++    {0,0,0}
++};
++
++/**
++ * Lookup table to convert from EIA/CEA TV video formats used in the EDID and
++ * in API parameters to pixel clock frequencies, according to SCS Table
++ * "HDMI Pixel Clock Frequencies per EIA/CEA-861B Video Output Format".
++ * The other index is the veritical frame frequency.
++ */
++ 
++CONST_DAT UInt8 kVfmtToPixClk_TV[HDMITX_VFMT_TV_MAX][HDMITX_VFREQ_NUM] =
++{
++  /* HDMITX_VFREQ_24Hz HDMITX_VFREQ_25Hz HDMITX_VFREQ_30Hz  HDMITX_VFREQ_50Hz HDMITX_VFREQ_59Hz HDMITX_VFREQ_60Hz */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_25175,   E_PIXCLK_25200},     /* HDMITX_VFMT_01_640x480p_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_27027},     /* HDMITX_VFMT_02_720x480p_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_27027},     /* HDMITX_VFMT_03_720x480p_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_74175,   E_PIXCLK_74250},     /* HDMITX_VFMT_04_1280x720p_60Hz  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_74175,   E_PIXCLK_74250},     /* HDMITX_VFMT_05_1920x1080i_60Hz */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_27027},     /* HDMITX_VFMT_06_720x480i_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_27027},     /* HDMITX_VFMT_07_720x480i_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_27027},     /* HDMITX_VFMT_08_720x240p_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_27027},     /* HDMITX_VFMT_09_720x240p_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_54054},     /* HDMITX_VFMT_10_720x480i_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_54054},     /* HDMITX_VFMT_11_720x480i_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_54054},     /* HDMITX_VFMT_12_720x240p_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_54054},     /* HDMITX_VFMT_13_720x240p_60Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_54054},     /* HDMITX_VFMT_14_1440x480p_60Hz  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_54054},     /* HDMITX_VFMT_15_1440x480p_60Hz  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_148350,  E_PIXCLK_148500},    /* HDMITX_VFMT_16_1920x1080p_60Hz */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_17_720x576p_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_18_720x576p_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_74250,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_19_1280x720p_50Hz  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_74250,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_20_1920x1080i_50Hz */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_21_720x576i_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_22_720x576i_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_23_720x288p_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_27000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_24_720x288p_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_25_720x576i_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_26_720x576i_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_27_720x288p_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_28_720x288p_50Hz   */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_29_1440x576p_50Hz  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_54000,   E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_30_1440x576p_50Hz  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_148500,  E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_31_1920x1080p_50Hz */
++    {E_PIXCLK_74250,   E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_32_1920x1080p_24Hz */
++    {E_PIXCLK_INVALID, E_PIXCLK_74250,   E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_33_1920x1080p_25Hz */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_74250,   E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},    /* HDMITX_VFMT_34_1920x1080p_30Hz */
++
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_108000, E_PIXCLK_108108},     /* HDMITX_VFMT_35_2880x480p_60Hz  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_108000, E_PIXCLK_108108},     /* HDMITX_VFMT_36_2880x480p_60Hz  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_108000,  E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_37_2880x576p_50Hz  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_108000,  E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_38_2880x576p_50Hz  */
++
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_39_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_40_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_41_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_42_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_43_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_44_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_45_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_46_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_47_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_48_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_49_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_50_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_51_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_52_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_53_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_54_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_55_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_56_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_57_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_58_  */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_59_  */
++
++    {E_PIXCLK_59400,   E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_60_1280x720p_24Hz */
++    {E_PIXCLK_INVALID, E_PIXCLK_74250,   E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID},   /* HDMITX_VFMT_61_1280x720p_25Hz */
++    {E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_74250,   E_PIXCLK_INVALID, E_PIXCLK_INVALID, E_PIXCLK_INVALID}    /* HDMITX_VFMT_62_1280x720p_30Hz */
++};
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS                               */
++/*============================================================================*/
++
++
++/**
++ * Lookup table to convert PC formats used in API parameters to pixel clock 
++ * frequencies.
++ * The other index is the veritical frame frequency.
++ */
++#ifdef FORMAT_PC
++CONST_DAT UInt8 kVfmtToPixClk_PC[HDMITX_VFMT_PC_NUM] =
++{
++  /* HDMITX_VFREQ_60Hz HDMITX_VFREQ_70Hz HDMITX_VFREQ_72Hz HDMITX_VFREQ_75Hz HDMITX_VFREQ_85Hz HDMITX_VFREQ_87Hz*/
++    E_PIXCLK_25175  ,   /* HDMITX_VFMT_PC_640x480p_60Hz   */
++    E_PIXCLK_40000  ,   /* HDMITX_VFMT_PC_800x600p_60Hz   */
++    E_PIXCLK_INVALID,   /* HDMITX_VFMT_PC_1152x960p_60Hz  */
++    E_PIXCLK_65000  ,   /* HDMITX_VFMT_PC_1024x768p_60Hz */
++    E_PIXCLK_79500  ,   /* HDMITX_VFMT_PC_1280x768p_60Hz */
++    E_PIXCLK_108000 ,   /* HDMITX_VFMT_PC_1280x1024p_60Hz */
++    E_PIXCLK_85500  ,   /* HDMITX_VFMT_PC_1360x768p_60Hz  */
++    E_PIXCLK_121750 ,   /* HDMITX_VFMT_PC_1400x1050p_60Hz */
++    E_PIXCLK_162000 ,   /* HDMITX_VFMT_PC_1600x1200p_60Hz */
++    E_PIXCLK_75000  ,   /* HDMITX_VFMT_PC_1024x768p_70Hz  */
++    E_PIXCLK_31500  ,   /* HDMITX_VFMT_PC_640x480p_72Hz   */
++    E_PIXCLK_50000  ,   /* HDMITX_VFMT_PC_800x600p_72Hz   */
++    E_PIXCLK_31500  ,   /* HDMITX_VFMT_PC_640x480p_75Hz   */
++    E_PIXCLK_78750  ,   /* HDMITX_VFMT_PC_1024x768p_75Hz  */
++    E_PIXCLK_49500  ,   /* HDMITX_VFMT_PC_800x600p_75Hz   */
++    E_PIXCLK_INVALID,   /* HDMITX_VFMT_PC_1024x864p_75Hz  */
++    E_PIXCLK_INVALID,   /* HDMITX_VFMT_PC_1280x1024p_75Hz */
++    E_PIXCLK_INVALID,   /* HDMITX_VFMT_PC_640x350p_85Hz   */
++    E_PIXCLK_INVALID,   /* HDMITX_VFMT_PC_640x400p_85Hz   */
++    E_PIXCLK_INVALID,   /* HDMITX_VFMT_PC_720x400p_85Hz   */
++    E_PIXCLK_36000  ,   /* HDMITX_VFMT_PC_640x480p_85Hz   */
++    E_PIXCLK_56250  ,   /* HDMITX_VFMT_PC_800x600p_85Hz   */
++    E_PIXCLK_INVALID,   /* HDMITX_VFMT_PC_1024x768p_85Hz  */
++    E_PIXCLK_INVALID,   /* HDMITX_VFMT_PC_1152x864p_85Hz  */
++    E_PIXCLK_INVALID,   /* HDMITX_VFMT_PC_1280x960p_85Hz  */
++    E_PIXCLK_INVALID,    /* HDMITX_VFMT_PC_1280x1024p_85Hz */ /* PR1570 FIXED */
++    E_PIXCLK_INVALID    /* HDMITX_VFMT_PC_1024x768i_87Hz  */
++};
++#endif
++
++/**
++ * Lookup table to convert from EIA/CEA TV video formats used in the EDID and in
++ * API parameters to the format used in the E_REG_P00_VIDFORMAT_W register
++ */
++
++#ifdef TMFL_RGB_DDR_12BITS
++static CONST_DAT struct vic2reg vic2reg_TV[] = {
++   {HDMITX_VFMT_01_640x480p_60Hz,  E_REGVFMT_640x480p_60Hz},
++   {HDMITX_VFMT_02_720x480p_60Hz,  E_REGVFMT_720x480p_60Hz},
++   {HDMITX_VFMT_03_720x480p_60Hz,  E_REGVFMT_720x480p_60Hz},
++   {HDMITX_VFMT_04_1280x720p_60Hz, E_REGVFMT_1280x720p_60Hz},
++   {HDMITX_VFMT_05_1920x1080i_60Hz,E_REGVFMT_1920x1080i_60Hz},
++   {HDMITX_VFMT_06_720x480i_60Hz,  E_REGVFMT_720x480i_60Hz},
++   {HDMITX_VFMT_07_720x480i_60Hz,  E_REGVFMT_720x480i_60Hz},
++   {HDMITX_VFMT_08_720x240p_60Hz,  E_REGVFMT_720x240p_60Hz},
++   {HDMITX_VFMT_09_720x240p_60Hz,  E_REGVFMT_720x240p_60Hz},
++   {HDMITX_VFMT_10_720x480i_60Hz,  E_REGVFMT_2880x480i_60Hz_PR4},
++   {HDMITX_VFMT_11_720x480i_60Hz,  E_REGVFMT_2880x480i_60Hz_PR4},
++   {HDMITX_VFMT_14_1440x480p_60Hz, E_REGVFMT_1440x480p_60Hz},
++   {HDMITX_VFMT_15_1440x480p_60Hz, E_REGVFMT_1440x480p_60Hz},
++   {HDMITX_VFMT_16_1920x1080p_60Hz,E_REGVFMT_1920x1080p_60Hz},
++   {HDMITX_VFMT_17_720x576p_50Hz,  E_REGVFMT_720x576p_50Hz},
++   {HDMITX_VFMT_18_720x576p_50Hz,  E_REGVFMT_720x576p_50Hz},
++   {HDMITX_VFMT_19_1280x720p_50Hz, E_REGVFMT_1280x720p_50Hz},
++   {HDMITX_VFMT_20_1920x1080i_50Hz,E_REGVFMT_1920x1080i_50Hz},
++   {HDMITX_VFMT_21_720x576i_50Hz,  E_REGVFMT_720x576i_50Hz},
++   {HDMITX_VFMT_22_720x576i_50Hz,  E_REGVFMT_720x576i_50Hz},
++   {HDMITX_VFMT_23_720x288p_50Hz,  E_REGVFMT_720x288p_50Hz},
++   {HDMITX_VFMT_24_720x288p_50Hz,  E_REGVFMT_720x288p_50Hz},
++   {HDMITX_VFMT_25_720x576i_50Hz,  E_REGVFMT_2880x576i_50Hz}, /* FIXME PR 2 */
++   {HDMITX_VFMT_26_720x576i_50Hz,  E_REGVFMT_2880x576i_50Hz}, /* FIXME PR 2 */
++   {HDMITX_VFMT_29_1440x576p_50Hz, E_REGVFMT_1440x576p_50Hz},
++   {HDMITX_VFMT_30_1440x576p_50Hz, E_REGVFMT_1440x576p_50Hz},
++   {HDMITX_VFMT_31_1920x1080p_50Hz,E_REGVFMT_1920x1080p_50Hz},
++   {HDMITX_VFMT_32_1920x1080p_24Hz,E_REGVFMT_1920x1080p_24Hz},
++   {HDMITX_VFMT_33_1920x1080p_25Hz,E_REGVFMT_1920x1080p_25Hz},
++   {HDMITX_VFMT_34_1920x1080p_30Hz,E_REGVFMT_1920x1080p_30Hz},
++   {HDMITX_VFMT_35_2880x480p_60Hz, E_REGVFMT_2880x480p_60Hz},
++   {HDMITX_VFMT_36_2880x480p_60Hz, E_REGVFMT_2880x480p_60Hz},
++   {HDMITX_VFMT_37_2880x576p_50Hz, E_REGVFMT_720x576p_50Hz},
++   {HDMITX_VFMT_38_2880x576p_50Hz, E_REGVFMT_720x576p_50Hz},
++   {HDMITX_VFMT_60_1280x720p_24Hz, E_REGVFMT_1280x720p_24Hz},
++   {HDMITX_VFMT_61_1280x720p_25Hz, E_REGVFMT_1280x720p_25Hz},
++   {HDMITX_VFMT_62_1280x720p_30Hz, E_REGVFMT_1280x720p_30Hz}
++};
++static CONST_DAT struct vic2reg vic2reg_TV_FP[] = {
++   {HDMITX_VFMT_01_640x480p_60Hz,  E_REGVFMT_720x480p_60Hz_FP},
++   {HDMITX_VFMT_02_720x480p_60Hz,  E_REGVFMT_720x480p_60Hz_FP},
++   {HDMITX_VFMT_03_720x480p_60Hz,  E_REGVFMT_720x480p_60Hz_FP},
++   {HDMITX_VFMT_04_1280x720p_60Hz, E_REGVFMT_1280x720p_60Hz_FP},
++   {HDMITX_VFMT_05_1920x1080i_60Hz,E_REGVFMT_1920x1080i_60Hz_FP},
++   {HDMITX_VFMT_17_720x576p_50Hz,  E_REGVFMT_720x576p_50Hz_FP},
++   {HDMITX_VFMT_18_720x576p_50Hz,  E_REGVFMT_720x576p_50Hz_FP},
++   {HDMITX_VFMT_19_1280x720p_50Hz, E_REGVFMT_1280x720p_50Hz_FP},
++   {HDMITX_VFMT_20_1920x1080i_50Hz,E_REGVFMT_1920x1080i_50Hz_FP},
++   {HDMITX_VFMT_32_1920x1080p_24Hz,E_REGVFMT_1920x1080p_24Hz_FP},
++   {HDMITX_VFMT_33_1920x1080p_25Hz,E_REGVFMT_1920x1080p_25Hz_FP},
++   {HDMITX_VFMT_34_1920x1080p_30Hz,E_REGVFMT_1920x1080p_30Hz_FP},
++   {HDMITX_VFMT_60_1280x720p_24Hz, E_REGVFMT_1280x720p_24Hz_FP},
++   {HDMITX_VFMT_61_1280x720p_25Hz, E_REGVFMT_1280x720p_25Hz_FP},
++   {HDMITX_VFMT_62_1280x720p_30Hz, E_REGVFMT_1280x720p_30Hz_FP}
++};
++#else
++static CONST_DAT struct vic2reg vic2reg_TV[] = {
++   {HDMITX_VFMT_01_640x480p_60Hz,  E_REGVFMT_640x480p_60Hz},
++   {HDMITX_VFMT_02_720x480p_60Hz,  E_REGVFMT_720x480p_60Hz},
++   {HDMITX_VFMT_03_720x480p_60Hz,  E_REGVFMT_720x480p_60Hz},
++   {HDMITX_VFMT_04_1280x720p_60Hz, E_REGVFMT_1280x720p_60Hz},
++   {HDMITX_VFMT_05_1920x1080i_60Hz,E_REGVFMT_1920x1080i_60Hz},
++   {HDMITX_VFMT_06_720x480i_60Hz,  E_REGVFMT_720x480i_60Hz},
++   {HDMITX_VFMT_07_720x480i_60Hz,  E_REGVFMT_720x480i_60Hz},
++   {HDMITX_VFMT_08_720x240p_60Hz,  E_REGVFMT_720x240p_60Hz},
++   {HDMITX_VFMT_09_720x240p_60Hz,  E_REGVFMT_720x240p_60Hz},
++   {HDMITX_VFMT_16_1920x1080p_60Hz,E_REGVFMT_1920x1080p_60Hz},
++   {HDMITX_VFMT_17_720x576p_50Hz,  E_REGVFMT_720x576p_50Hz},
++   {HDMITX_VFMT_18_720x576p_50Hz,  E_REGVFMT_720x576p_50Hz},
++   {HDMITX_VFMT_19_1280x720p_50Hz, E_REGVFMT_1280x720p_50Hz},
++   {HDMITX_VFMT_20_1920x1080i_50Hz,E_REGVFMT_1920x1080i_50Hz},
++   {HDMITX_VFMT_21_720x576i_50Hz,  E_REGVFMT_720x576i_50Hz},
++   {HDMITX_VFMT_22_720x576i_50Hz,  E_REGVFMT_720x576i_50Hz},
++   {HDMITX_VFMT_23_720x288p_50Hz,  E_REGVFMT_720x288p_50Hz},
++   {HDMITX_VFMT_24_720x288p_50Hz,  E_REGVFMT_720x288p_50Hz},
++   {HDMITX_VFMT_31_1920x1080p_50Hz,E_REGVFMT_1920x1080p_50Hz},
++   {HDMITX_VFMT_32_1920x1080p_24Hz,E_REGVFMT_1920x1080p_24Hz},
++   {HDMITX_VFMT_33_1920x1080p_25Hz,E_REGVFMT_1920x1080p_25Hz},
++   {HDMITX_VFMT_34_1920x1080p_30Hz,E_REGVFMT_1920x1080p_30Hz},
++   {HDMITX_VFMT_35_2880x480p_60Hz, E_REGVFMT_720x480p_60Hz},
++   {HDMITX_VFMT_36_2880x480p_60Hz, E_REGVFMT_720x480p_60Hz},
++   {HDMITX_VFMT_37_2880x576p_50Hz, E_REGVFMT_720x576p_50Hz},
++   {HDMITX_VFMT_38_2880x576p_50Hz, E_REGVFMT_720x576p_50Hz},
++   {HDMITX_VFMT_60_1280x720p_24Hz, E_REGVFMT_1280x720p_24Hz},
++   {HDMITX_VFMT_61_1280x720p_25Hz, E_REGVFMT_1280x720p_25Hz},
++   {HDMITX_VFMT_62_1280x720p_30Hz, E_REGVFMT_1280x720p_30Hz}
++};
++static CONST_DAT struct vic2reg vic2reg_TV_FP[] = {
++   {HDMITX_VFMT_04_1280x720p_60Hz, E_REGVFMT_1280x720p_60Hz_FP},
++   {HDMITX_VFMT_05_1920x1080i_60Hz,E_REGVFMT_1920x1080i_60Hz_FP},
++   {HDMITX_VFMT_19_1280x720p_50Hz, E_REGVFMT_1280x720p_50Hz_FP},
++   {HDMITX_VFMT_20_1920x1080i_50Hz,E_REGVFMT_1920x1080i_50Hz_FP},
++   {HDMITX_VFMT_32_1920x1080p_24Hz,E_REGVFMT_1920x1080p_24Hz_FP},
++   {HDMITX_VFMT_33_1920x1080p_25Hz,E_REGVFMT_1920x1080p_25Hz_FP},
++   {HDMITX_VFMT_34_1920x1080p_30Hz,E_REGVFMT_1920x1080p_30Hz_FP},
++   {HDMITX_VFMT_60_1280x720p_24Hz, E_REGVFMT_1280x720p_24Hz_FP},
++   {HDMITX_VFMT_61_1280x720p_25Hz, E_REGVFMT_1280x720p_25Hz_FP},
++   {HDMITX_VFMT_62_1280x720p_30Hz, E_REGVFMT_1280x720p_30Hz_FP}
++};
++#endif
++
++#ifdef FORMAT_PC
++static CONST_DAT struct vic2reg vic2reg_PC[HDMITX_VFMT_PC_NUM] = {
++   {HDMITX_VFMT_PC_640x480p_60Hz,  E_REGVFMT_640x480p_60Hz},
++   {HDMITX_VFMT_PC_800x600p_60Hz,  E_REGVFMT_800x600p_60Hz},
++   {HDMITX_VFMT_PC_1024x768p_60Hz, E_REGVFMT_1024x768p_60Hz},
++   {HDMITX_VFMT_PC_1280x768p_60Hz, E_REGVFMT_1280x768p_60Hz},
++   {HDMITX_VFMT_PC_1280x1024p_60Hz,E_REGVFMT_1280x1024p_60Hz},
++   {HDMITX_VFMT_PC_1360x768p_60Hz, E_REGVFMT_1360x768p_60Hz},
++   {HDMITX_VFMT_PC_1400x1050p_60Hz,E_REGVFMT_1400x1050p_60Hz},
++   {HDMITX_VFMT_PC_1600x1200p_60Hz,E_REGVFMT_1600x1200p_60Hz},
++   {HDMITX_VFMT_PC_1024x768p_70Hz, E_REGVFMT_1024x768p_70Hz},
++   {HDMITX_VFMT_PC_640x480p_72Hz,  E_REGVFMT_640x480p_72Hz},
++   {HDMITX_VFMT_PC_800x600p_72Hz,  E_REGVFMT_800x600p_72Hz},
++   {HDMITX_VFMT_PC_640x480p_75Hz,  E_REGVFMT_640x480p_75Hz},
++   {HDMITX_VFMT_PC_1024x768p_75Hz, E_REGVFMT_1024x768p_75Hz},
++   {HDMITX_VFMT_PC_800x600p_75Hz,  E_REGVFMT_800x600p_75Hz},
++   {HDMITX_VFMT_PC_640x480p_85Hz,  E_REGVFMT_640x480p_85Hz},
++   {HDMITX_VFMT_PC_800x600p_85Hz,  E_REGVFMT_800x600p_85Hz},
++   {HDMITX_VFMT_PC_1280x1024p_85Hz,E_REGVFMT_1280x1024p_85Hz}
++};
++#endif /* FORMAT PC */ 
++    
++
++/**
++ * Lookup table to convert from video format codes used in the 
++ * E_REG_P00_VIDFORMAT_W register to corresponding VS_PIX_STRT_2
++ * register values, to correct the output window for interlaced
++ * output formats, with or without the scaler.
++ *
++ * The correction is VS_PIX_STRT_2=VS_PIX_STRT_2+VS_PIX_STRT_1.
++ * The same value is also applied to VS_PIX_END_2.
++ */
++
++/**
++ * Lookup table to convert from video format codes used in the 
++ * E_REG_P00_VIDFORMAT_W register to corresponding 
++ * pixel repetition values in the PLL_SERIAL_2 register.
++ * 0=no repetition (pixel sent once)
++ * 1=one repetition (pixel sent twice) etc
++ */
++
++/**
++ * Lookup table to convert from video format codes used in the 
++ * E_REG_P00_VIDFORMAT_W register to corresponding 
++ * trios of 2-bit values in the srl_nosc, scg_nosc and de_nosc
++ * PLL control registers
++ * 
++ * Rational for dummies by André ;)
++ * ----------------------------- 
++ *    the TMDS serializer multiply x10 the pixclk (this is a PLL;)
++ *    <format>   -->   <pixclk>   -->   <PLL>   -->   <div by>
++ *    576i or 480i     13.5 Mhz (*2)    270 Mhz       4
++ *    576p             27 Mhz           270 Mhz       4
++ *    720p or 1080i    74.25 Mhz        742 Mhz       2
++ *    1080p            148.5 Mhz        1485 Mhz      1
++ * 
++ */
++
++static CONST_DAT UInt8 pll[] = {
++   /* prefetch */
++   2,  /* E_REGVFMT_640x480p_60Hz   */
++   2,  /* E_REGVFMT_720x480p_60Hz   */
++   1,  /* E_REGVFMT_1280x720p_60Hz  */
++   1,  /* E_REGVFMT_1920x1080i_60Hz */
++   3,  /* E_REGVFMT_720x480i_60Hz   */
++   0,  /* E_REGVFMT_720x240p_60Hz   */ /** \todo Need nosc PLL value */
++   0,  /* E_REGVFMT_1920x1080p_60Hz */
++   2,  /* E_REGVFMT_720x576p_50Hz   */
++   1,  /* E_REGVFMT_1280x720p_50Hz  */
++   1,  /* E_REGVFMT_1920x1080i_50Hz */
++   3,  /* E_REGVFMT_720x576i_50Hz   */
++   0,  /* E_REGVFMT_720x288p_50Hz   */ /** \todo Need nosc PLL value */
++   0,  /* E_REGVFMT_1920x1080p_50Hz */
++#ifdef TMFL_RGB_DDR_12BITS
++   0,  /* E_REGVFMT_1920x1080p_24Hz   */
++   1,  /* E_REGVFMT_1440x576p_50Hz    */
++   1,  /* E_REGVFMT_1440x480p_50Hz    */
++   0,  /* E_REGVFMT_2880x480p_50Hz    */
++   0,  /* E_REGVFMT_2880x576p_50Hz    */
++   1,  /* E_REGVFMT_2880x480i_60Hz    */
++   2,  /* E_REGVFMT_2880x480i_60Hz_PR2*/
++   2,  /* E_REGVFMT_2880x480i_60Hz_PR4*/
++   1,  /* E_REGVFMT_2880x576i_50Hz    */
++   2,  /* E_REGVFMT_2880x576i_50Hz_PR2*/
++   1,  /* E_REGVFMT_720x480p_60Hz_FP  */
++   0,  /* E_REGVFMT_1280x720p_60Hz_FP */
++   1,  /* E_REGVFMT_720x576p_50Hz_FP  */
++   0,  /* E_REGVFMT_1280x720p_50Hz_FP */
++   0,  /* E_REGVFMT_1920x1080p_23Hz_FP*/
++   0,  /* E_REGVFMT_1920x1080p_25Hz_FP*/
++   0,  /* E_REGVFMT_1920x1080p_29Hz_FP*/
++   0,  /* E_REGVFMT_1920x1080i_60Hz_FP*/
++   0,  /* E_REGVFMT_1920x1080i_50Hz_FP*/
++#endif
++        /* extra list */
++#ifndef TMFL_RGB_DDR_12BITS
++   1,  /* E_REGVFMT_1920x1080p_24Hz */
++#endif
++   1,  /* E_REGVFMT_1920x1080p_25Hz */
++   1,  /* E_REGVFMT_1920x1080p_30Hz */
++   1,  /* E_REGVFMT_1280x720p_24Hz  */
++   1,  /* E_REGVFMT_1280x720p_25Hz  */
++   1,  /* E_REGVFMT_1280x720p_30Hz  */
++#ifndef TMFL_RGB_DDR_12BITS
++   0,  /* E_REGVFMT_1280x720p_60Hz_FP */
++   0,  /* E_REGVFMT_1920x1080i_60Hz_FP */
++   0,  /* E_REGVFMT_1280x720p_50Hz_FP */
++   0,  /* E_REGVFMT_1920x1080i_50Hz_FP */
++   0,  /* E_REGVFMT_1920x1080p_24Hz_FP */
++   0,  /* E_REGVFMT_1920x1080p_25Hz_FP */
++   0,  /* E_REGVFMT_1920x1080p_30Hz_FP */
++#endif
++   0,  /* E_REGVFMT_1280x720p_24Hz_FP */
++   0,  /* E_REGVFMT_1280x720p_25Hz_FP */
++   0,  /* E_REGVFMT_1280x720p_30Hz_FP */
++#ifdef FORMAT_PC
++   2,   /* E_REGVFMT_640x480p_72Hz   */
++   2,   /* E_REGVFMT_640x480p_75Hz   */
++   2,   /* E_REGVFMT_640x480p_85Hz   */
++   1,   /* E_REGVFMT_800x600p_60Hz   */
++   1,   /* E_REGVFMT_800x600p_72Hz   */
++   1,   /* E_REGVFMT_800x600p_75Hz   */
++   1,   /* E_REGVFMT_800x600p_85Hz   */
++   1,   /* E_REGVFMT_1024x768p_60Hz  */
++   1,   /* E_REGVFMT_1024x768p_70Hz  */
++   1,   /* E_REGVFMT_1024x768p_75Hz  */
++   0,   /* E_REGVFMT_1280x768p_60Hz  */
++   0,   /* E_REGVFMT_1280x1024p_60Hz */
++   0,   /* E_REGVFMT_1360x768p_60Hz  */
++   0,   /* E_REGVFMT_1400x1050p_60Hz */
++   0,   /* E_REGVFMT_1600x1200p_60Hz */
++   1    /* E_REGVFMT_1280x1024p_85Hz */
++#endif /* FORMAT_PC */
++};
++
++
++
++/**
++ * Lokup table to convert from video format codes used in the 
++ * E_REG_P00_VIDFORMAT_W register to RefPix and RefLine values
++ * according to sync source
++ */
++/* prefetch list */
++static CONST_DAT struct sync_desc ref_sync[] =
++{
++   /*
++     designer world <==> CEA-861 reader world
++     ----------------------------------------
++     t_hs_s : hfp+1
++     t_vsl_s1 : vfp+1
++     t_de_s : href+1
++     t_vw_s1 : vref+1
++
++     For the story, designer have defined VsPixRef and VsLineRef concept
++     that are the position of VSync in pixel and line starting from the top
++     of the frame.
++     So we have in fact : VSync that is hfp + vfp*total_h_active away from top
++
++   */
++   /* Vs2    PR  Vtg Htg HFP VFP HREF VREF */
++   {0,       0,  1,  1,  17,   2, 161, 36}, /* E_REGVFMT_640x480p_60Hz   */
++   {0,       0,  1,  1,  17,   8, 139, 43}, /* E_REGVFMT_720x480p_60Hz   */
++   {0,       0,  0,  0,  111,  2, 371, 26}, /* E_REGVFMT_1280x720p_60Hz  */
++   {1100+88, 0,  0,  0,  89,   2, 281, 21}, /* E_REGVFMT_1920x1080i_60Hz */
++   {429+19,  1,  1,  1,  20,   5, 139, 22}, /* E_REGVFMT_720x480i_60Hz   */
++   {0,       1,  1,  1,  20,   5, 139, 22}, /* E_REGVFMT_720x240p_60Hz   */
++   {0,       0,  0,  0,  89,   2, 281, 42}, /* E_REGVFMT_1920x1080p_60Hz */
++   {0,       0,  1,  1,  13,   2, 145, 45}, /* E_REGVFMT_720x576p_50Hz   */
++   {0,       0,  0,  0,  441,  2, 701, 26}, /* E_REGVFMT_1280x720p_50Hz  */
++   {1320+528,0,  0,  0,  529,  2, 721, 21}, /* E_REGVFMT_1920x1080i_50Hz */
++   {432+12,  1,  1,  1,  13,   2, 145, 23}, /* E_REGVFMT_720x576i_50Hz   */
++   {0,       1,  1,  1,  13,   2, 145, 23}, /* E_REGVFMT_720x288p_50Hz   */
++   {0,       0,  0,  0,  529,  2, 721, 42}, /* E_REGVFMT_1920x1080p_50Hz */
++#ifdef TMFL_RGB_DDR_12BITS
++   {0,       0,  0,  0,  639,  2, 831, 42}, /* E_REGVFMT_1920x1080p_24Hz  */
++   {0,       0,  1,  1,  25,   2, 289, 45}, /* E_REGVFMT_1440x576p_50Hz   */
++   {0,       0,  1,  1,  33,   8, 277, 43}, /* E_REGVFMT_1440x480p_50Hz   */
++   {0,       0,  1,  1,  65,   8, 553, 43}, /* E_REGVFMT_2880x480p_50Hz   */
++   {0,       0,  1,  1,  49,   2, 577, 45}, /* E_REGVFMT_2880x576p_50Hz   */
++   {1716+76, 0,  1,  1,  77,   5, 553, 22}, /* E_REGVFMT_2880x480i_60Hz   */
++   {858+38,  1,  1,  1,  39,   5, 277, 22}, /* E_REGVFMT_2880x480i_60Hz_PR2*/
++   {429+19,  2,  1,  1,  20,   5, 139, 22}, /* E_REGVFMT_2880x480i_60Hz_PR4*/
++   {1728+48, 0,  1,  1,  49,   2, 577, 23}, /* E_REGVFMT_2880x576i_50Hz   */
++   {864+24,  1,  1,  1,  25,   2, 289, 23}  /* E_REGVFMT_2880x576i_50Hz_PR*/
++#endif
++};
++
++/* extra list */
++static CONST_DAT struct sync_desc ref_sync_extra[] =
++{
++   /* Vs2    PR  Vtg Htg HFP VFP HREF VREF */
++#ifndef TMFL_RGB_DDR_12BITS
++   {0,       0,  0,  0,  639,  2, 831, 42}, /* E_REGVFMT_1920x1080p_24Hz */
++#endif
++   {0,       0,  0,  0,  529,  2, 721, 42}, /* E_REGVFMT_1920x1080p_25Hz */
++   {0,       0,  0,  0,  89,   2, 281, 42}, /* E_REGVFMT_1920x1080p_30Hz */    
++   {0,       0,  0,  0,  1761, 2, 2021,26}, /* E_REGVFMT_1280x720p_24Hz  */
++   {0,       0,  0,  0,  2421, 2, 2681,26}, /* E_REGVFMT_1280x720p_25Hz  */
++   {0,       0,  0,  0,  1761, 2, 2021,26}  /* E_REGVFMT_1280x720p_30Hz  */
++};
++
++#ifdef FORMAT_PC    
++   /* PC list */
++static CONST_DAT struct sync_desc ref_sync_PC[] =
++{
++   /* Vs2    PR  Vtg Htg HFP VFP HREF VREF */
++   {0,       0,  1,  1,  25,   2, 195, 32}, /* E_REGVFMT_640x480p_72Hz   */
++   {0,       0,  1,  1,  17,   2, 203, 20}, /* E_REGVFMT_640x480p_75Hz   */
++   {0,       0,  1,  1,  57,   2, 195, 29}, /* E_REGVFMT_640x480p_85Hz   */
++   {0,       0,  0,  0,  41,   2, 259, 28}, /* E_REGVFMT_800x600p_60Hz   */
++   {0,       0,  0,  0,  57,   2, 243, 30}, /* E_REGVFMT_800x600p_72Hz   */
++   {0,       0,  0,  0,  17,   2, 259, 25}, /* E_REGVFMT_800x600p_75Hz   */
++   {0,       0,  0,  0,  33,   2, 251, 31}, /* E_REGVFMT_800x600p_85Hz   */
++   {0,       0,  1,  1,  25,   2, 323, 36}, /* E_REGVFMT_1024x768p_60Hz  */
++   {0,       0,  1,  1,  25,   2, 307, 36}, /* E_REGVFMT_1024x768p_70Hz  */
++   {0,       0,  0,  0,  17,   2, 291, 32}, /* E_REGVFMT_1024x768p_75Hz  */
++   {0,       0,  0,  1,  65,   2, 387, 28}, /* E_REGVFMT_1280x768p_60Hz  */
++   {0,       0,  0,  0,  49,   2, 411, 42}, /* E_REGVFMT_1280x1024p_60Hz */
++   {0,       0,  0,  0,  65,   2, 435, 25}, /* E_REGVFMT_1360x768p_60Hz  */
++   {0,       0,  0,  1,  89,   2, 467, 37}, /* E_REGVFMT_1400x1050p_60Hz */
++   {0,       0,  0,  0,  65,   2, 563, 50}, /* E_REGVFMT_1600x1200p_60Hz */
++   {0,       0,  0,  0,  65,   2, 451, 48}  /* E_REGVFMT_1280x1024p_85Hz */
++};
++#endif/* FORMAT_PC */
++
++static CONST_DAT tmHdmiTxVidReg_t format_param_extra[] = {
++   /*  NPIX    NLINE  VsLineStart  VsPixStart  VsLineEnd   VsPixEnd    HsStart     HsEnd   ActiveVideoStart   ActiveVideoEnd DeStart DeEnd */
++   /*  npix    nline  vsl_s1       vsp_s1      vsl_e1      vsp_e1      hs_e        hs_e    vw_s1              vw_e1          de_s    de_e */
++#ifndef TMFL_RGB_DDR_12BITS
++   {2750,  1125,     1,          638,         6,           638,        638,    682,    41,         1121,   830,   2750, 0, 0},/* E_REGVFMT_1920x1080p_24Hz */
++#endif
++   {2640,  1125,     1,          528,         6,           528,        528,    572,    41,         1121,   720,   2640, 0, 0},/* E_REGVFMT_1920x1080p_25Hz */
++   {2200,  1125,     1,          88,          6,           88,         88,     132,    41,         1121,   280,   2200, 0, 0},/* E_REGVFMT_1920x1080p_30Hz */
++   {3300,   750,     1,         1760,         6,          1760,       1760,   1800,    25,          745,  2020,   3300, 0, 0},/* E_REGVFMT_1280x720p_24Hz  */
++   {3960,   750,     1,         2420,         6,          2420,       2420,   2460,    25,          745,  2680,   3960, 0, 0},/* E_REGVFMT_1280x720p_25Hz  */
++   {3300,   750,     1,         1760,         6,          1760,       1760,   1800,    25,          745,  2020,   3300, 0, 0},/* E_REGVFMT_1280x720p_30Hz  */
++#ifndef TMFL_RGB_DDR_12BITS
++   {1650,   1500,    1,          110,         6,           110,        110,    150,    25,         1495,   370,   1650, 746, 776},/* E_REGVFMT_1280x720p_60Hz_FP  */
++   {2200,   2250,    1,          88,          6,           88,         88,     132,    20,         2248,   280,   2200, 0, 0},/* E_REGVFMT_1920x1080i_60Hz_FP */
++   {1980,   1500,    1,          440,         6,           440,        440,    480,    25,         1495,   700,   1980, 746, 776},/* E_REGVFMT_1280x720p_50Hz_FP  */
++   {2640,   2250,    1,          528,         6,           528,        528,    572,    20,         2248,   720,   2640, 0, 0},/* E_REGVFMT_1920x1080i_50Hz_FP */
++   {2750,   2250,    1,          638,         6,           638,        638,    682,    41,         2246,   830,   2750, 1122, 1167},/* E_REGVFMT_1920x1080p_24Hz_FP */
++   {2640,   2250,    1,          528,         6,           528,        528,    572,    41,         2246,   720,   2640, 1122, 1167},/* E_REGVFMT_1920x1080p_25Hz_FP */
++   {2200,   2250,    1,          88,          6,           88,         88,     132,    41,         2246,   280,   2200, 1122, 1167},/* E_REGVFMT_1920x1080p_30Hz_FP */
++#endif
++   {3300,   1500,    1,         1760,         6,          1760,       1760,   1800,    25,         1495,  2020,   3300, 0, 0},/* E_REGVFMT_1280x720p_24Hz_FP  */
++   {3960,   1500,    1,         2420,         6,          2420,       2420,   2460,    25,         1495,  2680,   3960, 0, 0},/* E_REGVFMT_1280x720p_25Hz_FP  */
++   {3300,   1500,    1,         1760,         6,          1760,       1760,   1800,    25,         1495,  2020,   3300, 0, 0},/* E_REGVFMT_1280x720p_30Hz_FP  */
++};
++
++#ifdef FORMAT_PC
++static CONST_DAT tmHdmiTxVidReg_t format_param_PC[HDMITX_VFMT_PC_NUM] =
++{
++   /*  NPIX    NLINE  VsLineStart  VsPixStart  VsLineEnd   VsPixEnd    HsStart     HsEnd   ActiveVideoStart   ActiveVideoEnd DeStart DeEnd */
++   /*  npix    nline  vsl_s1       vsp_s1      vsl_e1      vsp_e1      hs_e        hs_e    vw_s1              vw_e1          de_s    de_e */
++    {832,   520,      1,          24,          4,           24,         24,     64,     31,         511,    192,    832, 0, 0},/* E_REGVFMT_640x480p_72Hz   */
++    {840,   500,      1,          16,          4,           16,         16,     80,     19,         499,    200,    840, 0, 0},/* E_REGVFMT_640x480p_75Hz   */
++    {832,   509,      1,          56,          4,           56,         56,     112,    28,         508,    192,    832, 0, 0},/* E_REGVFMT_640x480p_85Hz   */
++    {1056,  628,      1,          40,          5,           40,         40,     168,    27,         627,    256,   1056, 0, 0},/* E_REGVFMT_800x600p_60Hz   */
++    {1040,  666,      1,          56,          7,           56,         56,     176,    29,         619,    240,   1040, 0, 0},/* E_REGVFMT_800x600p_72Hz   */
++    {1056,  625,      1,          16,          4,           16,         16,     96,     24,         624,    256,   1056, 0, 0},/* E_REGVFMT_800x600p_75Hz   */
++    {1048,  631,      1,          32,          4,           32,         32,     96,     30,         630,    248,   1048, 0, 0},/* E_REGVFMT_800x600p_85Hz   */
++    {1344,  806,      1,          24,          7,           24,         24,     160,    35,         803,    320,   1344, 0, 0},/* E_REGVFMT_1024x768p_60Hz  */
++    {1328,  806,      1,          24,          7,           24,         24,     160,    35,         803,    304,   1328, 0, 0},/* E_REGVFMT_1024x768p_70Hz  */
++    {1312,  800,      1,          16,          4,           16,         16,     112,    31,         799,    288,   1312, 0, 0},/* E_REGVFMT_1024x768p_75Hz  */
++    {1664,  798,      1,          64,          8,           64,         64,     192,    27,         795,    384,   1664, 0, 0},/* E_REGVFMT_1280x768p_60Hz  */
++    {1688,  1066,     1,          48,          4,           48,         48,     160,    41,         1065,   408,   1688, 0, 0},/* E_REGVFMT_1280x1024p_60Hz */
++    {1792,  795,      1,          64,          7,           64,         64,     176,    24,         792,    432,   1792, 0, 0},/* E_REGVFMT_1360x768p_60Hz  */
++    {1864,  1089,     1,          88,          5,           88,         88,     232,    36,         1086,   464,   1864, 0, 0},/* E_REGVFMT_1400x1050p_60Hz */
++    {2160,  1250,     1,          64,          4,           64,         64,     256,    49,         1249,   560,   2160, 0, 0},/* E_REGVFMT_1600x1200p_60Hz */
++    {1728,  1072,     1,          64,          4,           64,         64,     224,    47,         1071,   448,   1728, 0, 0} /* E_REGVFMT_1280x1024p_85Hz */
++};
++#endif/* FORMAT_PC */
++
++ /**
++ *  Lookup table for each pixel clock frequency's CTS value in kHz
++ *  according to SCS table "Audio Clock Recovery CTS Values"
++ */
++static CONST_DAT UInt32 kPixClkToAcrCts[E_PIXCLK_NUM][HDMITX_AFS_NUM] =
++{
++ /* HDMITX_AFS_32k  _AFS_48K       _AFS_96K        _AFS_192K */
++ /*         _AFS_44_1k      _AFS_88_2K      _AFS_176_4K       */
++   { 28125,  31250,  28125,  31250,  28125,  31250,  28125}, /* E_PIXCLK_25175 */
++   { 25200,  28000,  25200,  28000,  25200,  28000,  25200}, /* E_PIXCLK_25200 */
++   { 27000,  30000,  27000,  30000,  27000,  30000,  27000}, /* E_PIXCLK_27000 */
++   { 27027,  30030,  27027,  30030,  27027,  30030,  27027}, /* E_PIXCLK_27027 */
++   { 54000,  60000,  54000,  60000,  54000,  60000,  54000}, /* E_PIXCLK_54000 */
++   { 54054,  60060,  54054,  60060,  54054,  60060,  54054}, /* E_PIXCLK_54054 */
++   { 59400,  65996,  59400,  65996,  59400,  65996,  59400}, /* E_PIXCLK_59400 */
++   {210937, 234375, 140625, 234375, 140625, 234375, 140625}, /* E_PIXCLK_74175 */
++   { 74250,  82500,  74250,  82500,  74250,  82500,  74250}, /* E_PIXCLK_74250 */
++   {421875, 234375, 140625, 234375, 140625, 234375, 140625}, /* E_PIXCLK_148350*/
++   {148500, 165000, 148500, 165000, 148500, 165000, 148500}  /* E_PIXCLK_148500*/
++#ifdef FORMAT_PC
++  ,{ 31500,  35000,  31500,  35000,  31500,  35000,  31500}, /* E_PIXCLK_31500 */
++   { 36000,  40000,  36000,  40000,  36000,  40000,  36000}, /* E_PIXCLK_36000 */
++   { 40000,  44444,  40000,  44444,  40000,  44444,  40000}, /* E_PIXCLK_40000 */
++   { 49500,  55000,  49500,  55000,  49500,  55000,  49500}, /* E_PIXCLK_49500 */
++   { 50000,  55556,  50000,  55556,  50000,  55556,  50000}, /* E_PIXCLK_50000 */
++   { 56250,  62500,  56250,  62500,  56250,  62500,  56250}, /* E_PIXCLK_56250 */
++   { 65000,  72222,  65000,  72222,  65000,  72222,  65000}, /* E_PIXCLK_65000 */
++   { 75000,  83333,  75000,  83333,  75000,  83333,  75000}, /* E_PIXCLK_75000 */
++   { 78750,  87500,  78750,  87500,  78750,  87500,  78750}, /* E_PIXCLK_78750 */
++   {162000, 180000, 162000, 180000, 162000, 180000, 162000}, /* E_PIXCLK_162000*/
++   {157500, 175000, 157500, 175000, 157500, 175000, 157500}  /* E_PIXCLK_157500 */
++#endif /* FORMAT_PC */
++};
++
++/**
++ *  Lookup table for each pixel clock frequency's Audio Clock Regeneration N,
++ *  according to SCS Table "Audio Clock Recovery N Values"
++ */
++static CONST_DAT UInt32 kPixClkToAcrN[E_PIXCLK_NUM][HDMITX_AFS_NUM] =
++{
++ /* HDMITX_AFS_32k  _AFS_48K       _AFS_96K        _AFS_192K */
++ /*         _AFS_44_1k      _AFS_88_2K      _AFS_176_4K       */
++   { 4576,   7007,   6864,  14014,  13728,  28028,  27456}, /* E_PIXCLK_25175 */
++   { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_25200 */
++   { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_27000 */
++   { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_27027 */
++   { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_54000 */
++   { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_54054 */
++   { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_59400 */
++   {11648,  17836,  11648,  35672,  23296,  71344,  46592}, /* E_PIXCLK_74175 */
++   { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_74250 */
++   {11648,   8918,   5824,  17836,  11648,  35672,  23296}, /* E_PIXCLK_148350*/
++   { 4096,   6272,   6144,  12544,  12288,  25088,  24576}  /* E_PIXCLK_148500*/
++#ifdef FORMAT_PC
++  ,{ 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_31500 */
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_36000 */
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_40000 */
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_49500 */
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_50000 */
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_56250 */
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_65000 */
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_75000 */
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_78750 */
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576},  /* E_PIXCLK_162000*/
++   { 4096,  6272,  6144,  12544,  12288,  25088,  24576}  /* E_PIXCLK_157500*/
++#endif /* FORMAT_PC */
++};
++
++/**
++ *  Lookup table for each pixel clock frequency's Audio Divider, according to
++ *  SCS Table "Audio Clock Recovery Divider Values"
++ */
++static CONST_DAT UInt8 kPixClkToAdiv[E_PIXCLK_NUM][HDMITX_AFS_NUM] =
++{
++ /* HDMITX_AFS_32k  _AFS_48K       _AFS_96K        _AFS_192K */
++ /*         _AFS_44_1k      _AFS_88_2K      _AFS_176_4K       */
++   {2,      2,      2,      1,      1,      0,      0},     /* E_PIXCLK_25175 */
++   {2,      2,      2,      1,      1,      0,      0},     /* E_PIXCLK_25200 */
++   {2,      2,      2,      1,      1,      0,      0},     /* E_PIXCLK_27000 */
++   {2,      2,      2,      1,      1,      0,      0},     /* E_PIXCLK_27027 */
++   {3,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_54000 */
++   {3,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_54054 */
++   {3,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_59400 */
++   {4,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_74175 */
++   {4,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_74250 */
++   {5,      4,      4,      3,      3,      2,      2},     /* E_PIXCLK_148350 */
++   {5,      4,      4,      3,      3,      2,      2}      /* E_PIXCLK_148500 */
++#ifdef FORMAT_PC
++  ,{2,      2,      2,      1,      1,      0,      0}, /* E_PIXCLK_31500  */
++   {3,      2,      2,      1,      1,      0,      0}, /* E_PIXCLK_36000  */
++   {3,      2,      2,      1,      1,      0,      0}, /* E_PIXCLK_40000  */
++   {3,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_49500  */
++   {3,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_50000  */
++   {3,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_56250  */
++   {4,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_65000  */
++   {4,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_75000  */
++   {4,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_78750  */
++   {5,      4,      4,      3,      3,      2,      2}, /* E_PIXCLK_162000 */
++   {5,      4,      4,      3,      3,      2,      2}  /* E_PIXCLK_157500 */
++#endif /* FORMAT_PC */
++
++};
++
++/**
++ *  Lookup table for converting a sampling frequency into the values
++ *  required in channel status byte 3 according to IEC60958-3
++ */
++static CONST_DAT UInt8 kAfsToCSbyte3[HDMITX_AFS_NUM+1] =
++{
++    3,      /* HDMITX_AFS_32k */
++    0,      /* HDMITX_AFS_44_1k */
++    2,      /* HDMITX_AFS_48k */
++    8,      /* HDMITX_AFS_88_2k */
++    10,     /* HDMITX_AFS_96k */
++    12,     /* HDMITX_AFS_176_4k */
++    14,     /* HDMITX_AFS_192k */
++    9,      /* HDMITX_AFS_768k */
++    1,      /* HDMITX_AFS_NOT_INDICATED */
++};
++
++
++
++/**
++ *  Lookup table for each CTS X factor's k and m register values
++ */
++static CONST_DAT UInt8 kCtsXToMK[HDMITX_CTSX_NUM][2] =
++{
++/*   Register values    Actual values */
++/*   m  k               m, k */ 
++    {3, 0},          /* 8, 1 */
++    {3, 1},          /* 8, 2 */
++    {3, 2},          /* 8, 3 */
++    {3, 3},          /* 8, 4 */
++    {0, 0}           /* 1, 1 */
++};
++
++/**
++ * Table of registers to reset and release the CTS generator
++ */
++static CONST_DAT tmHdmiTxRegMaskVal_t kResetCtsGenerator[] =
++{
++    {E_REG_P11_AIP_CNTRL_0_RW,  E_MASKREG_P11_AIP_CNTRL_0_rst_cts,  1},
++    {E_REG_P11_AIP_CNTRL_0_RW,  E_MASKREG_P11_AIP_CNTRL_0_rst_cts,  0},
++    {0,0,0}
++};
++
++/**
++ * Table of registers to bypass colour processing (up/down sampler & matrix)
++ */
++static CONST_DAT tmHdmiTxRegMaskVal_t kBypassColourProc[] =
++{
++    /* Bypass upsampler for RGB colourbars */
++    {E_REG_P00_HVF_CNTRL_0_W,   E_MASKREG_P00_HVF_CNTRL_0_intpol,   0},
++    /* Bypass matrix for RGB colourbars */
++    {E_REG_P00_MAT_CONTRL_W,    E_MASKREG_P00_MAT_CONTRL_mat_bp,    1},
++    /* Bypass downsampler for RGB colourbars */
++    {E_REG_P00_HVF_CNTRL_1_W,   E_MASKREG_P00_HVF_CNTRL_1_for,      0},
++    {0,0,0}
++};
++
++/**
++ * Table of registers to configure video input mode CCIR656*/
++static CONST_DAT tmHdmiTxRegMaskVal_t kVinModeCCIR656[] =
++{
++    {E_REG_P00_VIP_CNTRL_4_W,   E_MASKREG_P00_VIP_CNTRL_4_ccir656,      1},
++    {E_REG_P00_HVF_CNTRL_1_W,   E_MASKREG_P00_HVF_CNTRL_1_semi_planar,  1},
++    /*{E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_sel_clk1,         1},*/
++    {E_REG_P02_PLL_SERIAL_3_RW, E_MASKREG_P02_PLL_SERIAL_3_srl_ccir,    1},
++    {E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_sel_vrf_clk,      1},
++    {0,0,0}
++};
++
++ /* Table of registers to configure video input mode for CCIR656 DDR with 1280*720p and 1920*1080i formats*/
++static CONST_DAT tmHdmiTxRegMaskVal_t kVinModeCCIR656_DDR_above720p[] =
++{
++    {E_REG_P00_VIP_CNTRL_4_W,   E_MASKREG_P00_VIP_CNTRL_4_ccir656,      1},
++    {E_REG_P00_HVF_CNTRL_1_W,   E_MASKREG_P00_HVF_CNTRL_1_semi_planar,  1},/*To be defined*/
++    /*{E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_sel_clk1,         0},To be defined*/
++    {E_REG_P02_PLL_SERIAL_3_RW, E_MASKREG_P02_PLL_SERIAL_3_srl_ccir,    0},
++    {E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_sel_vrf_clk,      0},
++    {0,0,0}
++};
++/**
++ * Table of registers to configure video input mode RGB444 or YUV444
++ */
++static CONST_DAT tmHdmiTxRegMaskVal_t kVinMode444[] =
++{
++    {E_REG_P00_VIP_CNTRL_4_W,   E_MASKREG_P00_VIP_CNTRL_4_ccir656,      0},
++    {E_REG_P00_HVF_CNTRL_1_W,   E_MASKREG_P00_HVF_CNTRL_1_semi_planar,  0},
++   /* {E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_sel_clk1,         0},*/
++    {E_REG_P02_PLL_SERIAL_3_RW, E_MASKREG_P02_PLL_SERIAL_3_srl_ccir,    0},
++    {E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_sel_vrf_clk,      0},
++    {0,0,0}
++};
++
++/**
++ * Table of registers to configure video input mode YUV422
++ */
++static CONST_DAT tmHdmiTxRegMaskVal_t kVinModeYUV422[] =
++{
++    {E_REG_P00_VIP_CNTRL_4_W,   E_MASKREG_P00_VIP_CNTRL_4_ccir656,      0},
++    {E_REG_P00_HVF_CNTRL_1_W,   E_MASKREG_P00_HVF_CNTRL_1_semi_planar,  1},
++    /*{E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_sel_clk1,         0},*/
++    {E_REG_P02_PLL_SERIAL_3_RW, E_MASKREG_P02_PLL_SERIAL_3_srl_ccir,    0},
++    {E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_sel_vrf_clk,      0},
++    {0,0,0}
++};
++
++
++/**
++ *  Lookup table for colour space conversion matrix register sets.
++ *  Each array consists of 31 register values from MAT_CONTROL through
++ *  to MAT_OO3_LSB
++ */
++static CONST_DAT UInt8 kMatrixPreset[MATRIX_PRESET_QTY][MATRIX_PRESET_SIZE] =
++{
++    {0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x6F, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x3, 0x6F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3,
++     0x6F, 0x0, 0x40, 0x0, 0x40, 0x0, 0x40
++    },  /* RGB Full to RGB Limited */
++
++    {0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x4, 0x1, 0x7, 0x0,
++     0x64, 0x6, 0x88, 0x1, 0xC2, 0x7, 0xB7, 0x6, 0xD6, 0x7, 0x68, 0x1,
++     0xC2, 0x0, 0x40, 0x2, 0x0, 0x2, 0x0
++    },  /* RGB Full to BT601 */
++
++    {0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x75, 0x0, 0xBB, 0x0,
++     0x3F, 0x6, 0x68, 0x1, 0xC2, 0x7, 0xD7, 0x6, 0xA6, 0x7, 0x99, 0x1,
++     0xC2, 0x0, 0x40, 0x2, 0x0, 0x2, 0x0
++    },  /* RGB Full to BT709 */
++
++    {0x1, 0x7, 0xC0, 0x7, 0xC0, 0x7, 0xC0, 0x2, 0x54, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x2, 0x54, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2,
++     0x54, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
++    },  /* RGB Limited to RGB Full */
++
++    {0x2, 0x7, 0xC0, 0x7, 0xC0, 0x7, 0xC0, 0x2, 0x59, 0x1, 0x32, 0x0,
++     0x75, 0x6, 0x4A, 0x2, 0x0C, 0x7, 0xAB, 0x6, 0xA5, 0x7, 0x4F, 0x2,
++     0x0C, 0x0, 0x40, 0x2, 0x0, 0x2, 0x0
++    },  /* RGB Limited to BT601 */
++
++    {0x2, 0x7, 0xC0, 0x7, 0xC0, 0x7, 0xC0, 0x2, 0xDC, 0x0, 0xDA, 0x0,
++     0x4A, 0x6, 0x24, 0x2, 0x0C, 0x7, 0xD0, 0x6, 0x6C, 0x7, 0x88, 0x2,
++     0x0C, 0x0, 0x40, 0x2, 0x0, 0x2, 0x0
++    },  /* RGB Limited to BT709 */
++
++    {0x0, 0x7, 0xC0, 0x6, 0x0, 0x6, 0x0, 0x1, 0x2A, 0x7, 0x30, 0x7,
++     0x9C, 0x1, 0x2A, 0x1, 0x99, 0x0, 0x0, 0x1, 0x2A, 0x0, 0x0, 0x2,
++     0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
++    },  /* BT601 to RGB Full */
++
++    {0x1, 0x7, 0xC0, 0x6, 0x0, 0x6, 0x0, 0x2, 0x0, 0x6, 0x9A, 0x7,
++     0x54, 0x2, 0x0, 0x2, 0xBE, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x3,
++     0x77, 0x0, 0x40, 0x0, 0x40, 0x0, 0x40
++    },  /* BT601 to RGB Limited */
++
++    {0x1, 0x7, 0xC0, 0x6, 0x0, 0x6, 0x0, 0x2, 0x0, 0x7, 0x96, 0x7,
++     0xC5, 0x0, 0x0, 0x2, 0x0D, 0x0, 0x26, 0x0, 0x0, 0x0, 0x3B, 0x2,
++     0x0A, 0x0, 0x40, 0x2, 0x0, 0x2, 0x0
++    },  /* BT601 to BT709 */
++
++    {0x0, 0x7, 0xC0, 0x6, 0x0, 0x6, 0x0, 0x1, 0x2A, 0x7, 0x77, 0x7,
++     0xC9, 0x1, 0x2A, 0x1, 0xCB, 0x0, 0x0, 0x1, 0x2A, 0x0, 0x0, 0x2,
++     0x1D, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
++    },  /* BT709 to RGB Full */
++
++    {0x1, 0x7, 0xC0, 0x6, 0x0, 0x6, 0x0, 0x2, 0x0, 0x7, 0x16, 0x7,
++     0xA2, 0x2, 0x0, 0x3, 0x14, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x3,
++     0xA1, 0x0, 0x40, 0x0, 0x40, 0x0, 0x40
++    },  /* BT709 to RGB Limited */
++
++    {0x1, 0x7, 0xC0, 0x6, 0x0, 0x6, 0x0, 0x2, 0x0, 0x0, 0x62, 0x0,
++     0x33, 0x0, 0x0, 0x1, 0xF7, 0x7, 0xDB, 0x0, 0x0, 0x7, 0xC7, 0x1,
++     0xFB, 0x0, 0x40, 0x2, 0x0, 0x2, 0x0
++    }  /* BT709 to BT601 */
++}; 
++
++/**
++ *  This table gives us the index into the kMatrixPreset array, based
++ *  on the input and output colourspaces.
++ *  The co-ordinates into this array are tmbslTDA9989Colourspace_t enums.
++ *  The value of -1 is returned for matching input/output colourspaces.
++ */
++static CONST_DAT Int kMatrixIndex[HDMITX_CS_NUM][HDMITX_CS_NUM] =
++{
++    {-1, E_MATRIX_RGBF_2_RGBL, E_MATRIX_RGBF_2_BT601, E_MATRIX_RGBF_2_BT709},
++    {E_MATRIX_RGBL_2_RGBF, -1, E_MATRIX_RGBL_2_BT601, E_MATRIX_RGBL_2_BT709},
++    {E_MATRIX_BT601_2_RGBF, E_MATRIX_BT601_2_RGBL, -1, E_MATRIX_BT601_2_BT709},
++    {E_MATRIX_BT709_2_RGBF, E_MATRIX_BT709_2_RGBL, E_MATRIX_BT709_2_BT601, -1}
++};
++
++/**
++ *  Blue filter Lookup table for colour space conversion.
++ *  Each array consists of 31 register values from MAT_CONTROL through
++ *  to MAT_OO3_LSB
++ */
++static CONST_DAT UInt8 MatrixCoeffBlueScreen[][MATRIX_PRESET_SIZE] =
++{
++    {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0
++    },  /* blue screen for RGB output color space */
++
++    {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x1, 0x0, 0x3, 0x0
++    },  /* blue screen for YCbCr422 output color space */
++
++    {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x1, 0x0, 0x3, 0x0
++    },  /* blue screen for YCbCr444 output color space */
++};
++
++/**
++ *  Black filter Lookup table for colour space conversion.
++ *  Each array consists of 31 register values from MAT_CONTROL through
++ *  to MAT_OO3_LSB
++ */
++static CONST_DAT UInt8 MatrixCoeffBlackScreen[][MATRIX_PRESET_SIZE] =
++{
++    {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
++    },  /* black screen for RGB output color space */
++
++    {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x2, 0x0, 0x2, 0x0
++    },  /* black screen for YCbCr422 output color space */
++
++    {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++     0x0, 0x0, 0x0, 0x2, 0x0, 0x2, 0x0
++    },  /* black screen for YCbCr444 output color space */
++};
++
++
++/*============================================================================*/
++/*                       DEFINES DECLARATIONS                               */
++/*============================================================================*/
++#define HDMITX_LAT_SCO_MAX_VAL 40
++#define HDMITX_LAT_SCO_MIN_VAL 34
++
++/*============================================================================*/
++/*                       VARIABLES DECLARATIONS                               */
++/*============================================================================*/
++
++/* Register values per device to restore colour processing after test pattern */
++static RAM_DAT  UInt8   gMatContrl[HDMITX_UNITS_MAX];
++static RAM_DAT  UInt8   gHvfCntrl0[HDMITX_UNITS_MAX];
++static RAM_DAT  UInt8   gHvfCntrl1[HDMITX_UNITS_MAX];
++
++/*============================================================================*/
++/*                       FUNCTION PROTOTYPES                                  */
++/*============================================================================*/
++
++static tmErrorCode_t setDeVs(tmHdmiTxobject_t *pDis,
++                             tmbslHdmiTxVidFmt_t voutFmt,
++                             tmbslHdmiTx3DStructure_t structure3D);
++static tmErrorCode_t setPixelRepeat(tmHdmiTxobject_t *pDis, 
++                                    tmbslHdmiTxVidFmt_t voutFmt,
++                                    UInt8 uPixelRepeat,
++                                    tmbslHdmiTx3DStructure_t structure3D);
++static tmErrorCode_t setSampling(tmHdmiTxobject_t *pDis);
++static UInt8 calculateChecksum(UInt8 *pData, Int numBytes);
++static UInt8 reg_vid_fmt(tmbslHdmiTxVidFmt_t fmt,              \
++                         tmbslHdmiTx3DStructure_t structure3D, \
++                         UInt8 *idx,                           \
++                         UInt8 *idx3d,                         \
++                         struct sync_desc **sync);
++UInt8 pix_clk(tmbslHdmiTxVidFmt_t fmt, tmbslHdmiTxVfreq_t freq, UInt8 *pclk);
++static tmErrorCode_t InputConfig(tmHdmiTxobject_t *pDis,
++                                 tmbslHdmiTxVinMode_t vinMode,
++                                 tmbslHdmiTxPixEdge_t sampleEdge,
++                                 tmbslHdmiTxPixRate_t pixRate,
++                                 tmbslHdmiTxUpsampleMode_t upsampleMode, 
++                                 UInt8 uPixelRepeat,
++                                 tmbslHdmiTxVidFmt_t voutFmt,
++                                 tmbslHdmiTx3DStructure_t structure3D);
++/*============================================================================*/
++/* tmbslTDA9989AudioInResetCts                                                 */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989AudioInResetCts
++(
++    tmUnitSelect_t              txUnit
++)
++{
++    tmHdmiTxobject_t *pDis;     /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;      /* Error code */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return if sink is not an HDMI device */
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI, 
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Reset and release the CTS generator */
++    err = setHwRegisterFieldTable(pDis, &kResetCtsGenerator[0]);
++    return err;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989AudioInSetConfig                                                */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989AudioInSetConfig
++(
++    tmUnitSelect_t           txUnit,
++    tmbslHdmiTxaFmt_t        aFmt,
++    tmbslHdmiTxI2sFor_t      i2sFormat,
++    UInt8                    chanI2s,
++    UInt8                    chanDsd,
++    tmbslHdmiTxClkPolDsd_t   clkPolDsd,
++    tmbslHdmiTxSwapDsd_t     swapDsd,
++    UInt8                    layout,
++    UInt16                   uLatency_rd,
++    tmbslHdmiTxDstRate_t     dstRate
++)
++{
++    tmHdmiTxobject_t *pDis;     /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;      /* Error code */
++    UInt8             regVal;   /* Value to write in register */
++
++    DUMMY_ACCESS(dstRate);
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return if sink is not an HDMI device */
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI, 
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameters */
++#ifdef TMFL_HBR_SUPPORT
++    RETIF_BADPARAM((aFmt != HDMITX_AFMT_SPDIF) &&
++                   (aFmt != HDMITX_AFMT_I2S)   &&
++                   (aFmt != HDMITX_AFMT_OBA)   &&
++                   (aFmt != HDMITX_AFMT_HBR))
++
++#else /* TMFL_HBR_SUPPORT */
++    RETIF_BADPARAM((aFmt != HDMITX_AFMT_SPDIF) &&
++                   (aFmt != HDMITX_AFMT_I2S)   &&
++                   (aFmt != HDMITX_AFMT_OBA))
++
++
++#endif /* TMFL_HBR_SUPPORT */
++
++    RETIF_BADPARAM(chanI2s     >= HDMITX_CHAN_INVALID)
++    RETIF_BADPARAM(chanDsd     >= HDMITX_CHAN_INVALID)
++    RETIF_BADPARAM(clkPolDsd   >= HDMITX_CLKPOLDSD_INVALID)
++    RETIF_BADPARAM(swapDsd     >= HDMITX_SWAPDSD_INVALID)
++    RETIF_BADPARAM(layout      >= HDMITX_LAYOUT_INVALID)
++    RETIF_BADPARAM(uLatency_rd >= HDMITX_LATENCY_INVALID)
++
++    if ((aFmt == HDMITX_AFMT_I2S) 
++#ifdef TMFL_HBR_SUPPORT 
++        || (aFmt == HDMITX_AFMT_HBR)
++#endif /* TMFL_HBR_SUPPORT */
++        )
++    {
++        RETIF_BADPARAM((i2sFormat != HDMITX_I2SFOR_PHILIPS_L) &&
++                       (i2sFormat != HDMITX_I2SFOR_OTH_L)     &&
++                       (i2sFormat != HDMITX_I2SFOR_OTH_R)
++                       )
++    }
++
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++    /* 
++       power management :
++       freeze/wakeup SPDIF clock
++    */
++    err = setHwRegisterField(pDis, E_REG_FEAT_POWER_DOWN,               \
++                             E_MASKREG_FEAT_POWER_DOWN_spdif,           \
++                             (aFmt != HDMITX_AFMT_SPDIF));
++    RETIF_REG_FAIL(err);
++#endif
++
++    switch (aFmt)
++    {
++        case HDMITX_AFMT_SPDIF:
++            regVal = (UInt8)REG_VAL_SEL_AIP_SPDIF;
++            /* configure MUX_AP */
++            err = setHwRegister(pDis, E_REG_P00_MUX_AP_RW, TDA19989_MUX_AP_SELECT_SPDIF);
++            RETIF_REG_FAIL(err)
++            break;
++
++        case HDMITX_AFMT_I2S:
++            regVal = (UInt8)REG_VAL_SEL_AIP_I2S;
++            /* configure MUX_AP */
++            err = setHwRegister(pDis, E_REG_P00_MUX_AP_RW, TDA19989_MUX_AP_SELECT_I2S);
++            RETIF_REG_FAIL(err)
++            break;
++
++        case HDMITX_AFMT_OBA:
++            regVal = (UInt8)REG_VAL_SEL_AIP_OBA;
++            break;
++
++        case HDMITX_AFMT_HBR:
++            regVal = (UInt8)REG_VAL_SEL_AIP_HBR;
++            break;
++            
++        default:
++            return TMBSL_ERR_HDMI_BAD_PARAMETER;
++    }
++
++
++    /* Set the audio input processor format to aFmt. */
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_AIP_CLKSEL_W,
++                             E_MASKREG_P00_AIP_CLKSEL_sel_aip,
++                             regVal);
++    RETIF_REG_FAIL(err)
++
++    /* Channel status on 1 channel  */
++    err = setHwRegisterField(pDis,
++                             E_REG_P11_CA_I2S_RW,
++                             E_MASKREG_P11_CA_I2S_hbr_chstat_4,
++                             0);
++    RETIF_REG_FAIL(err)
++
++    /* Select the audio format */
++    if ((aFmt == HDMITX_AFMT_I2S) 
++#ifdef TMFL_HBR_SUPPORT
++        || (aFmt == HDMITX_AFMT_HBR)
++#endif /* TMFL_HBR_SUPPORT */
++       )
++    {
++        if (chanI2s != HDMITX_CHAN_NO_CHANGE)
++        {
++            err = setHwRegisterField(pDis,
++                  E_REG_P11_CA_I2S_RW,
++                  E_MASKREG_P11_CA_I2S_ca_i2s,
++                  (UInt8)chanI2s);
++        }
++
++        /* Select the I2S format */
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_I2S_FORMAT_RW,
++                                 E_MASKREG_P00_I2S_FORMAT_i2s_format,
++                                 (UInt8)i2sFormat);
++        RETIF_REG_FAIL(err)
++
++//#ifdef TMFL_HBR_SUPPORT 
++      //if (aFmt == HDMITX_AFMT_HBR)
++      // {
++            /* Channel status on 1 channel  */
++      //      err = setHwRegisterField(pDis,
++      //                       E_REG_P11_CA_I2S_RW,
++      //                       E_MASKREG_P11_CA_I2S_hbr_chstat_4,
++      //                       1);
++      //      RETIF_REG_FAIL(err)
++      //  }
++//#endif /* TMFL_HBR_SUPPORT */
++    }
++    else if (aFmt == HDMITX_AFMT_OBA)
++    {
++        if (chanDsd != HDMITX_CHAN_NO_CHANGE)
++        {
++            err = setHwRegister(pDis, E_REG_P11_CA_DSD_RW, chanDsd);
++            RETIF_REG_FAIL(err)
++        }
++        if (clkPolDsd != HDMITX_CLKPOLDSD_NO_CHANGE)
++        {
++            err = setHwRegisterField(pDis,
++                                     E_REG_P00_AIP_CLKSEL_W,
++                                     E_MASKREG_P00_AIP_CLKSEL_sel_pol_clk,
++                                     (UInt8)clkPolDsd);
++            RETIF_REG_FAIL(err)
++        }
++        if (swapDsd != HDMITX_SWAPDSD_NO_CHANGE)
++        {
++            err = setHwRegisterField(pDis,
++                                     E_REG_P11_AIP_CNTRL_0_RW,
++                                     E_MASKREG_P11_AIP_CNTRL_0_swap,
++                                     (UInt8)swapDsd);
++            RETIF_REG_FAIL(err)
++        }
++    }
++
++    /* Set layout and latency */
++    if (layout != HDMITX_LAYOUT_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P11_AIP_CNTRL_0_RW,
++                                 E_MASKREG_P11_AIP_CNTRL_0_layout,
++                                 layout);
++        RETIF_REG_FAIL(err)
++    }
++    if (uLatency_rd != HDMITX_LATENCY_NO_CHANGE)
++    {
++        err = setHwRegister(pDis, E_REG_P11_LATENCY_RD_RW, (UInt8)uLatency_rd);
++        RETIF_REG_FAIL(err)
++    }
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989AudioInSetCts                                                   */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989AudioInSetCts
++(
++    tmUnitSelect_t       txUnit,
++    tmbslHdmiTxctsRef_t  ctsRef,
++    tmbslHdmiTxafs_t     afs, 
++    tmbslHdmiTxVidFmt_t  voutFmt, 
++    tmbslHdmiTxVfreq_t   voutFreq, 
++    UInt32               uCts, 
++    UInt16               uCtsX,
++    tmbslHdmiTxctsK_t    ctsK,
++    tmbslHdmiTxctsM_t    ctsM,
++    tmbslHdmiTxDstRate_t dstRate
++)
++{
++    tmHdmiTxobject_t *pDis;     /* Pointer to Device Instance Structure */
++    tmErrorCode_t   err;        /* Error code */
++    UInt8           regVal;     /* Register value */
++    UInt8           pixClk;     /* Pixel clock index */
++    UInt32          acrN;       /* Audio clock recovery N */
++
++    DUMMY_ACCESS(dstRate);
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return if sink is not an HDMI device */
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI, 
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM(ctsRef   >= HDMITX_CTSREF_INVALID)
++    RETIF_BADPARAM(afs      >= HDMITX_AFS_INVALID)
++    RETIF_BADPARAM(!IS_VALID_FMT(voutFmt))
++    RETIF_BADPARAM(voutFreq >= HDMITX_VFREQ_INVALID)
++    RETIF_BADPARAM(uCtsX    >= HDMITX_CTSX_INVALID)
++    RETIF_BADPARAM(ctsK     >= HDMITX_CTSK_INVALID)
++    RETIF_BADPARAM(ctsM     >= HDMITX_CTSMTS_INVALID)
++   
++    
++    if (IS_TV(voutFmt))
++    {
++       if (voutFreq == HDMITX_VFREQ_50Hz)
++          {
++             RETIF(((voutFmt < HDMITX_VFMT_17_720x576p_50Hz)        \
++                    || (voutFmt > HDMITX_VFMT_31_1920x1080p_50Hz)),
++                   TMBSL_ERR_HDMI_INCONSISTENT_PARAMS);
++          }
++       else if (voutFreq == HDMITX_VFREQ_24Hz)
++          {
++             RETIF((voutFmt != HDMITX_VFMT_32_1920x1080p_24Hz)      \
++                   && (voutFmt != HDMITX_VFMT_60_1280x720p_24Hz),
++                   TMBSL_ERR_HDMI_INCONSISTENT_PARAMS);
++          }
++       else if (voutFreq == HDMITX_VFREQ_25Hz)
++          {
++             RETIF((voutFmt != HDMITX_VFMT_33_1920x1080p_25Hz)      \
++                   && (voutFmt != HDMITX_VFMT_20_1920x1080i_50Hz)   \
++                   && (voutFmt != HDMITX_VFMT_61_1280x720p_25Hz),
++                   TMBSL_ERR_HDMI_INCONSISTENT_PARAMS);
++          }
++       else if (voutFreq == HDMITX_VFREQ_30Hz)
++          {
++             RETIF((voutFmt != HDMITX_VFMT_34_1920x1080p_30Hz)      \
++                   && (voutFmt != HDMITX_VFMT_05_1920x1080i_60Hz)   \
++                   && (voutFmt != HDMITX_VFMT_62_1280x720p_30Hz),
++                   TMBSL_ERR_HDMI_INCONSISTENT_PARAMS);
++          }
++       else
++          {
++             RETIF(voutFmt >= HDMITX_VFMT_17_720x576p_50Hz,
++                   TMBSL_ERR_HDMI_INCONSISTENT_PARAMS);
++          }
++    }
++
++#ifdef FORMAT_PC
++    if (IS_PC(voutFmt))
++    {
++        if (voutFreq == HDMITX_VFREQ_60Hz)
++        {
++            RETIF(voutFmt > HDMITX_VFMT_PC_1600x1200p_60Hz,
++                                       TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++        }
++        else if (voutFreq == HDMITX_VFREQ_70Hz)
++        {
++            RETIF(voutFmt != HDMITX_VFMT_PC_1024x768p_70Hz,
++                                       TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++        }
++        else if (voutFreq == HDMITX_VFREQ_72Hz)
++        {
++            RETIF( ((voutFmt < HDMITX_VFMT_PC_640x480p_72Hz) ||
++                    (voutFmt > HDMITX_VFMT_PC_800x600p_72Hz)),
++                                       TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++        }
++        else if (voutFreq == HDMITX_VFREQ_75Hz)
++        {
++            RETIF( ((voutFmt < HDMITX_VFMT_PC_640x480p_75Hz) ||
++                    (voutFmt > HDMITX_VFMT_PC_1280x1024p_75Hz)),
++                                       TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++        }
++        else if (voutFreq == HDMITX_VFREQ_85Hz)
++        {
++            RETIF( ((voutFmt < HDMITX_VFMT_PC_640x350p_85Hz) ||
++                    (voutFmt > HDMITX_VFMT_PC_1280x1024p_85Hz)),
++                                       TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++        }
++        else
++        {
++            RETIF(voutFmt != HDMITX_VFMT_PC_1024x768i_87Hz,
++                                       TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++        }
++    }
++#endif /* FORMAT_PC */
++
++    /* Check for auto or manual CTS */
++    if (uCts == HDMITX_CTS_AUTO)
++    {
++        /* Auto */
++        err = setHwRegisterField(pDis,
++                                 E_REG_P11_AIP_CNTRL_0_RW,
++                                 E_MASKREG_P11_AIP_CNTRL_0_acr_man,
++                                 0);
++        RETIF_REG_FAIL(err)
++    }
++    else
++    {
++        /* Manual */
++        err = setHwRegisterField(pDis,
++                                 E_REG_P11_AIP_CNTRL_0_RW,
++                                 E_MASKREG_P11_AIP_CNTRL_0_acr_man,
++                                 1);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Derive M and K from X? */
++    if ((ctsM == HDMITX_CTSMTS_USE_CTSX) || (ctsK == HDMITX_CTSK_USE_CTSX))
++    {
++        RETIF_BADPARAM(uCtsX == HDMITX_CTSX_UNUSED)
++        ctsM = (tmbslHdmiTxctsM_t) kCtsXToMK[uCtsX][0];
++        ctsK = (tmbslHdmiTxctsK_t)kCtsXToMK[uCtsX][1];
++    }
++
++    /* Set the Post-divider measured timestamp factor */
++    regVal = (UInt8)ctsM;
++    err = setHwRegisterField(pDis,
++                             E_REG_P11_CTS_N_RW,
++                             E_MASKREG_P11_CTS_N_m_sel,
++                             regVal);
++    RETIF_REG_FAIL(err)
++
++    /* Set the Pre-divider scale */
++    regVal = (UInt8)ctsK;
++    err = setHwRegisterField(pDis,
++                             E_REG_P11_CTS_N_RW,
++                             E_MASKREG_P11_CTS_N_k_sel,
++                             regVal);
++    RETIF_REG_FAIL(err);
++
++    /* Use voutFmt and voutFreq to index into a lookup table to get
++     * the current pixel clock value. */
++    pix_clk(voutFmt, voutFreq, &pixClk);
++
++    if (pixClk != E_PIXCLK_INVALID)
++    {
++        /* Set the Audio Clock Recovery N multiplier based on the audio sample
++         * frequency afs and current pixel clock. */
++        acrN = kPixClkToAcrN[pixClk][afs];
++
++        /* Set ACR N multiplier [19 to 16] */
++        regVal = (UInt8)(acrN >> 16);
++        err = setHwRegister(pDis, E_REG_P11_ACR_N_2_RW, regVal);
++        RETIF_REG_FAIL(err)
++        /* Set ACR N multiplier [15 to 8] */
++        regVal = (UInt8)(acrN >> 8);
++        err = setHwRegister(pDis, E_REG_P11_ACR_N_1_RW, regVal);
++        RETIF_REG_FAIL(err)
++        /* Set ACR N multiplier [7 to 0] */
++        regVal = (UInt8)acrN;
++        err = setHwRegister(pDis, E_REG_P11_ACR_N_0_RW, regVal);
++        RETIF_REG_FAIL(err)
++
++        /* Set the CDC Audio Divider register based on the audio sample frequency
++         * afs and current pixel clock. */
++        regVal = kPixClkToAdiv[pixClk][afs];
++        err = setHwRegister(pDis, E_REG_P02_AUDIO_DIV_RW, regVal);
++        RETIF_REG_FAIL(err)
++
++        /* If auto CTS, get CTS value based on the audio sample
++         * frequency afs and current pixel clock. */
++        if (uCts == HDMITX_CTS_AUTO)
++        {
++            uCts = kPixClkToAcrCts[pixClk][afs];
++        }
++    }
++
++    /* Set manual or pixel clock CTS */
++    if (uCts != HDMITX_CTS_AUTO)
++    {
++        /* Set manual ACR CTS [19 to 16 */
++        regVal = (UInt8)(uCts >> 16);
++        err = setHwRegister(pDis, E_REG_P11_ACR_CTS_2_RW, regVal);
++        RETIF_REG_FAIL(err)
++        /* Set manual ACR CTS [15 to 8] */
++        regVal = (UInt8)(uCts >> 8);
++        err = setHwRegister(pDis, E_REG_P11_ACR_CTS_1_RW, regVal);
++        RETIF_REG_FAIL(err)
++        /* Set manual ACR CTS [7 to 0] */
++        regVal = (UInt8)uCts;
++        err = setHwRegister(pDis, E_REG_P11_ACR_CTS_0_RW, regVal);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Set the CTS clock reference register according to ctsRef */
++    regVal = (UInt8)ctsRef;
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_AIP_CLKSEL_W,
++                             E_MASKREG_P00_AIP_CLKSEL_sel_fs,
++                             regVal);
++    RETIF_REG_FAIL(err)
++
++    /* Reset and release the CTS generator */
++    err = setHwRegisterFieldTable(pDis, &kResetCtsGenerator[0]);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989AudioOutSetChanStatus                                           */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989AudioOutSetChanStatus
++(
++    tmUnitSelect_t               txUnit,
++    tmbslHdmiTxAudioData_t       pcmIdentification,
++    tmbslHdmiTxCSformatInfo_t    formatInfo,
++    tmbslHdmiTxCScopyright_t     copyright,
++    UInt8                        categoryCode,
++    tmbslHdmiTxafs_t             sampleFreq,
++    tmbslHdmiTxCSclkAcc_t        clockAccuracy,
++    tmbslHdmiTxCSmaxWordLength_t maxWordLength,
++    tmbslHdmiTxCSwordLength_t    wordLength,
++    tmbslHdmiTxCSorigAfs_t       origSampleFreq
++)
++{
++    tmHdmiTxobject_t *pDis;     /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;      /* Error code */
++    UInt8             buf[4];   /* Buffer to hold channel status data */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return if sink is not an HDMI device */
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI, 
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM(formatInfo     >= HDMITX_CSFI_INVALID)
++    RETIF_BADPARAM(copyright      >= HDMITX_CSCOPYRIGHT_INVALID)
++    RETIF_BADPARAM(sampleFreq     >  HDMITX_AFS_NOT_INDICATED)
++    RETIF_BADPARAM(clockAccuracy  >= HDMITX_CSCLK_INVALID)
++    RETIF_BADPARAM(maxWordLength  >= HDMITX_CSMAX_INVALID)
++    RETIF_BADPARAM(wordLength     >= HDMITX_CSWORD_INVALID)
++    RETIF_BADPARAM(wordLength     == HDMITX_CSWORD_RESVD)
++    RETIF_BADPARAM(origSampleFreq >= HDMITX_CSAFS_INVALID)
++    RETIF_BADPARAM(pcmIdentification >=HDMITX_AUDIO_DATA_INVALID)
++
++    /* Prepare Byte 0 */
++    buf[0] = ((UInt8)formatInfo << 3) | ((UInt8)copyright << 2) | ((UInt8)pcmIdentification<< 1);
++
++    /* Prepare Byte 1 */
++    buf[1] = categoryCode;
++
++    /* Prepare Byte 3  - note Byte 2 not in sequence in TDA9983 register map */
++    buf[2] = ((UInt8)clockAccuracy << 4) | kAfsToCSbyte3[sampleFreq];
++
++    /* Prepare Byte 4 */
++    buf[3] = ((UInt8)origSampleFreq << 4) | ((UInt8)wordLength << 1) |
++              (UInt8)maxWordLength;
++
++    /* Write 4 Channel Status bytes */
++    err = setHwRegisters(pDis, E_REG_P11_CH_STAT_B_0_RW, &buf[0], 4);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989AudioOutSetChanStatusMapping                                    */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989AudioOutSetChanStatusMapping
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           sourceLeft[4],
++    UInt8           channelLeft[4],
++    UInt8           sourceRight[4],
++    UInt8           channelRight[4]
++)
++{
++    tmHdmiTxobject_t *pDis;     /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;      /* Error code */
++    UInt8             buf[2];   /* Buffer to hold channel status data */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return if sink is not an HDMI device */
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI, 
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM(sourceLeft[0]   > HDMITX_CS_SOURCES_MAX)
++    RETIF_BADPARAM(channelLeft[0]  > HDMITX_CS_CHANNELS_MAX)
++    RETIF_BADPARAM(sourceRight[0]  > HDMITX_CS_SOURCES_MAX)
++    RETIF_BADPARAM(channelRight[0] > HDMITX_CS_CHANNELS_MAX)
++
++    /* Prepare Left byte */
++    buf[0] = ((UInt8)channelLeft[0] << 4) | (UInt8)sourceLeft[0];
++
++    /* Prepare Right byte */
++    buf[1] = ((UInt8)channelRight[0] << 4) | (UInt8)sourceRight[0];
++
++    /* Write 2 Channel Status bytes */
++    err = setHwRegisters(pDis, E_REG_P11_CH_STAT_B_2_ap0_l_RW, &buf[0], 2);
++    return err;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989AudioOutSetMute                                                 */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989AudioOutSetMute
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxaMute_t  aMute
++)
++{
++    tmHdmiTxobject_t *pDis;             /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;              /* Error code */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return if sink is not an HDMI device */
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI, 
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM(aMute >= HDMITX_AMUTE_INVALID)
++
++    /* audio mute workaround, un-map audio input before muting */
++    if (aMute == HDMITX_AMUTE_ON)
++    {
++        err = setHwRegisterField(pDis,
++                                E_REG_P00_SR_REG_W,
++                                E_MASKREG_P00_SR_REG_sr_audio,
++                                (UInt8)aMute);
++        RETIF(err != TM_OK, err)
++
++
++        err = setHwRegisterField(pDis,
++                                E_REG_P00_SR_REG_W,
++                                E_MASKREG_P00_SR_REG_sr_audio,
++                                (UInt8) !aMute);
++        RETIF(err != TM_OK, err)
++
++    }
++
++    /* Reset the audio FIFO to mute audio */
++    err = setHwRegisterField(pDis,
++                             E_REG_P11_AIP_CNTRL_0_RW,
++                             E_MASKREG_P11_AIP_CNTRL_0_rst_fifo,
++                             (UInt8)aMute);
++    RETIF(err != TM_OK, err)
++
++
++    return TM_OK;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989ScalerGet                                                       */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989ScalerGet
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxScalerDiag_t  *pScalerDiag
++)
++{
++    DUMMY_ACCESS(txUnit); /* else not referenced */
++    DUMMY_ACCESS(pScalerDiag); /* else not referenced */
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989ScalerGetMode                                                   */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989ScalerGetMode
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxScaMode_t      *pScalerMode
++)
++{
++    DUMMY_ACCESS(txUnit); /* else not referenced */
++    DUMMY_ACCESS(pScalerMode); /* else is declared but not used */
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989ScalerInDisable                                                 */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989ScalerInDisable
++(
++    tmUnitSelect_t  txUnit,
++    Bool            bDisable
++)
++{
++    DUMMY_ACCESS(txUnit); /* else not referenced */
++    DUMMY_ACCESS(bDisable);
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989ScalerSetCoeffs                                                 */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989ScalerSetCoeffs
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxScaLut_t   lutSel,
++    UInt8                *pVsLut
++)
++{
++    DUMMY_ACCESS(txUnit); /* else not referenced */
++    DUMMY_ACCESS(lutSel); /* else is declared but not used */
++    DUMMY_ACCESS(pVsLut); /* else is declared but not used */
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989ScalerSetFieldOrder                                             */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989ScalerSetFieldOrder 
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxIntExt_t topExt,
++    tmbslHdmiTxIntExt_t deExt,
++    tmbslHdmiTxTopSel_t topSel,
++    tmbslHdmiTxTopTgl_t topTgl 
++)
++{
++    DUMMY_ACCESS(txUnit); /* else not referenced */
++    DUMMY_ACCESS(deExt); /* else is declared but not used */
++    DUMMY_ACCESS(topExt); /* else is declared but not used */
++    DUMMY_ACCESS(topSel); /* else is declared but not used */
++    DUMMY_ACCESS(topTgl); /* else is declared but not used */
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989ScalerSetPhase                                                 */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989ScalerSetPhase
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxHPhases_t  horizontalPhases   
++)
++{
++    DUMMY_ACCESS(txUnit); /* else not referenced */
++    DUMMY_ACCESS(horizontalPhases); /* else is declared but not used */
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989ScalerSetLatency                                                 */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989ScalerSetLatency
++(
++    tmUnitSelect_t        txUnit,
++    UInt8                 scaler_latency
++)
++{
++    DUMMY_ACCESS(txUnit); /* else not referenced */
++    DUMMY_ACCESS(scaler_latency); /* else is declared but not used */
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989ScalerSetFine                                                   */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989ScalerSetFine
++(
++    tmUnitSelect_t  txUnit,
++    UInt16          uRefPix,    
++    UInt16          uRefLine   
++)
++{
++    DUMMY_ACCESS(txUnit); /* else not referenced */
++    DUMMY_ACCESS(uRefPix); /* else is declared but not used */
++    DUMMY_ACCESS(uRefLine); /* else is declared but not used */
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989ScalerSetSync                                                   */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989ScalerSetSync
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxVsMeth_t method,
++    tmbslHdmiTxVsOnce_t once
++)
++{
++    DUMMY_ACCESS(txUnit); /* else not referenced */
++    DUMMY_ACCESS(method); /* else is declared but not used */
++    DUMMY_ACCESS(once); /* else is declared but not used */
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++
++}
++
++/*============================================================================*/
++/* tmbslTDA9989TmdsSetOutputs                                                  */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989TmdsSetOutputs 
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxTmdsOut_t    tmdsOut
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(tmdsOut >= HDMITX_TMDSOUT_INVALID)
++
++    /* Set the TMDS output mode */
++    err = setHwRegisterField(pDis,
++                             E_REG_P02_BUFFER_OUT_RW,
++                             E_MASKREG_P02_BUFFER_OUT_srl_force,
++                             (UInt8)tmdsOut);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989TmdsSetSerializer                                               */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989TmdsSetSerializer 
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           uPhase2,
++    UInt8           uPhase3
++)
++{
++
++    DUMMY_ACCESS(txUnit);
++    DUMMY_ACCESS(uPhase2);
++    DUMMY_ACCESS(uPhase3);
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989TestSetPattern                                                  */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989TestSetPattern
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxTestPattern_t pattern 
++)
++{
++    tmHdmiTxobject_t *pDis;                        /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;                        /* Error code */
++    UInt8             serviceMode;                /* Register value */
++    UInt8             bars8;                    /* Register value */
++    UInt8              buf[MATRIX_PRESET_SIZE];    /* Temp buffer */
++    UInt8              i;                        /* Loop index */
++    UInt8              *MatrixCoeff=Null;    
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check pattern parameters */
++    switch (pattern)
++    {
++    case HDMITX_PATTERN_CBAR4:
++        serviceMode = 1;
++        bars8 = 0;
++        break;
++    case HDMITX_PATTERN_BLUE:
++        MatrixCoeff = (UInt8*)&MatrixCoeffBlueScreen[pDis->voutMode][0]; //point to the blue matrix 
++        serviceMode = 1;
++        bars8 = 1;
++        break;
++    case HDMITX_PATTERN_BLACK:
++        MatrixCoeff = (UInt8*)&MatrixCoeffBlackScreen[pDis->voutMode][0]; //point to the black matrix 
++    case HDMITX_PATTERN_CBAR8:
++        serviceMode = 1;
++        bars8 = 1;
++        break;
++    case HDMITX_PATTERN_OFF:
++        serviceMode = 0;
++        bars8 = 0;
++        break;
++    default:
++        return TMBSL_ERR_HDMI_BAD_PARAMETER;
++    }
++
++    if (serviceMode)
++    {
++        if (!pDis->prevPattern) /* if a pattern is on, registers are already saved */
++        {
++            /* The kBypassColourProc registers are saved in tmbslTDA9989VideoSetInOut API */
++            /* Bypass up/down sampler and matrix for RGB colourbars */
++            setHwRegisterFieldTable(pDis, &kBypassColourProc[0]);
++        }
++        if (( pattern == HDMITX_PATTERN_BLUE )||( pattern == HDMITX_PATTERN_BLACK )) /* blue or black screen pattern */
++        {
++
++            /* To create blue or black screen, we use the internal color bar 8 on which we apply a matrix to change it to blue or black */
++            /* Set the first block byte separately, as it is shadowed and can't
++            * be set by setHwRegisters */
++
++            /* Set the first block byte separately, as it is shadowed and can't
++            * be set by setHwRegisters */
++            err = setHwRegister(pDis,                    
++                                E_REG_P00_MAT_CONTRL_W,
++                                MatrixCoeff[0]);
++            RETIF_REG_FAIL(err)
++
++            for (i = 0; i < MATRIX_PRESET_SIZE; i++)
++            {
++                buf[i] = MatrixCoeff[i];
++            }
++            
++            /* Set the rest of the block */
++            err = setHwRegisters(pDis,
++                                E_REG_P00_MAT_OI1_MSB_W,
++                                &buf[1],
++                                MATRIX_PRESET_SIZE - 1);
++            RETIF_REG_FAIL(err)
++            pDis->prevFilterPattern = True;
++        }
++        else /* colour bars patterns */
++        {
++            /* Set number of colour bars */
++            err = setHwRegisterField(pDis, 
++                                    E_REG_P00_HVF_CNTRL_0_W,
++                                    E_MASKREG_P00_HVF_CNTRL_0_rwb,
++                                    bars8);
++            RETIF_REG_FAIL(err)
++            
++            /* Bypass up/down sampler and matrix for RGB colourbars */
++            setHwRegisterFieldTable(pDis, &kBypassColourProc[0]);
++        }
++        pDis->prevPattern = True;
++    }
++    else /* serviceMode == 0 */
++    {
++        if (pDis->prevFilterPattern)
++        {
++            /* Restore the previous Matrix when pattern goes off */
++            err = tmbslTDA9989MatrixSetConversion ( txUnit, pDis->vinFmt, pDis->vinMode, pDis->voutFmt, pDis->voutMode,pDis->dviVqr);
++            RETIF_REG_FAIL(err)
++
++            pDis->prevFilterPattern = False;
++        }
++        /* Restore kBypassColourProc registers when pattern goes off */
++        setHwRegister(pDis, E_REG_P00_MAT_CONTRL_W,  gMatContrl[txUnit]);
++        setHwRegister(pDis, E_REG_P00_HVF_CNTRL_0_W, gHvfCntrl0[txUnit]);
++        setHwRegister(pDis, E_REG_P00_HVF_CNTRL_1_W, gHvfCntrl1[txUnit]);
++        pDis->prevPattern = False;
++    }
++
++    /* Set Service Mode on or off */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P00_HVF_CNTRL_0_W,
++                             E_MASKREG_P00_HVF_CNTRL_0_sm,
++                             serviceMode);
++#ifdef TMFL_HDCP_SUPPORT
++   pDis->HDCPIgnoreEncrypt = True;  /* Skip the next encrypt IT */
++#endif /* TMFL_HDCP_SUPPORT */
++
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989VideoInSetBlanking                                              */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989VideoInSetBlanking
++(
++    tmUnitSelect_t         txUnit,
++    tmbslHdmiTxBlnkSrc_t   blankitSource,
++    tmbslHdmiTxBlnkCode_t  blankingCodes
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(blankitSource >= HDMITX_BLNKSRC_INVALID)
++    RETIF_BADPARAM(blankingCodes >= HDMITX_BLNKCODE_INVALID)
++
++    /* For each parameter that is not No Change, set its register */
++    if (blankitSource != HDMITX_BLNKSRC_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_4_W,
++                                 E_MASKREG_P00_VIP_CNTRL_4_blankit,
++                                 (UInt8)blankitSource);
++        RETIF_REG_FAIL(err)
++    }
++    if (blankingCodes != HDMITX_BLNKCODE_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_4_W,
++                                 E_MASKREG_P00_VIP_CNTRL_4_blc,
++                                 (UInt8)blankingCodes);
++        RETIF_REG_FAIL(err)
++    }
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989VideoInSetConfig                                                */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989VideoInSetConfig
++(
++    tmUnitSelect_t             txUnit,
++    tmbslHdmiTxVinMode_t       vinMode,
++    tmbslHdmiTxVidFmt_t        voutFmt,
++    tmbslHdmiTx3DStructure_t   structure3D,
++    tmbslHdmiTxPixEdge_t       sampleEdge,
++    tmbslHdmiTxPixRate_t       pixRate,
++    tmbslHdmiTxUpsampleMode_t  upsampleMode 
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(vinMode      >= HDMITX_VINMODE_INVALID)
++    RETIF_BADPARAM(sampleEdge   >= HDMITX_PIXEDGE_INVALID)
++    RETIF_BADPARAM(pixRate      >= HDMITX_PIXRATE_INVALID)
++    RETIF_BADPARAM(upsampleMode >= HDMITX_UPSAMPLE_INVALID)
++
++    err = InputConfig(pDis,
++                      vinMode,
++                      sampleEdge,
++                      pixRate,
++                      upsampleMode, 
++                      HDMITX_PIXREP_NO_CHANGE,
++                      voutFmt,
++                      structure3D);
++    RETIF_REG_FAIL(err)
++
++    return TM_OK;
++}
++/*============================================================================*/
++/* tmbslTDA9989VideoInSetFine                                                  */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989VideoInSetFine
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxPixSubpkt_t    subpacketCount,
++    tmbslHdmiTxPixTogl_t      toggleClk1 
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(subpacketCount >= HDMITX_PIXSUBPKT_INVALID)
++    RETIF_BADPARAM(toggleClk1     >= HDMITX_PIXTOGL_INVALID)
++
++    /* IF subpacketCount is Fix at 0/1/2/3 THEN set subpacket count register
++     * to 0/1/2/3 and set subpacket sync register to 3
++     */
++    if (subpacketCount <= HDMITX_PIXSUBPKT_FIX_3)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_5_W,
++                                 E_MASKREG_P00_VIP_CNTRL_5_sp_cnt,
++                                 (UInt8)subpacketCount);
++        RETIF_REG_FAIL(err)
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_3_W,
++                                 E_MASKREG_P00_VIP_CNTRL_3_sp_sync,
++                                 HDMITX_PIXSUBPKT_SYNC_FIXED);
++        RETIF_REG_FAIL(err)
++    }
++    /* ELSE IF subpacketCount is Sync by Hemb/ Sync by Rising Edge DE/ 
++     * Sync by Rising Edge HS THEN set the unused subpacket count to zero and
++     * set subpacket sync register to 0/1/2
++     */
++    else if (subpacketCount != HDMITX_PIXSUBPKT_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_5_W,
++                                 E_MASKREG_P00_VIP_CNTRL_5_sp_cnt,
++                                 HDMITX_PIXSUBPKT_FIX_0);
++        RETIF_REG_FAIL(err)
++       
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_3_W,
++                                 E_MASKREG_P00_VIP_CNTRL_3_sp_sync,
++                         (UInt8)(subpacketCount - HDMITX_PIXSUBPKT_SYNC_FIRST));
++        RETIF_REG_FAIL(err)
++    }
++
++    /* IF toggleClk1 is not No Change THEN set ckcase bitfield */
++    if (toggleClk1 != HDMITX_PIXTOGL_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_5_W,
++                                 E_MASKREG_P00_VIP_CNTRL_5_ckcase,
++                                 (UInt8)toggleClk1);
++        RETIF_REG_FAIL(err)
++    }
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989VideoInSetMapping                                               */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989VideoInSetMapping
++#ifdef TMFL_RGB_DDR_12BITS
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pSwapTable,
++    UInt8           *pMirrorTable,
++    UInt8           *pMux
++)
++#else
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pSwapTable,
++    UInt8           *pMirrorTable
++)
++#endif
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++    Int               i;          /* Loop counter */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(pSwapTable == Null)
++    RETIF_BADPARAM(pMirrorTable == Null)
++    for (i = 0; i < HDMITX_VIN_PORT_MAP_TABLE_LEN; i++)
++    {
++        RETIF_BADPARAM(pSwapTable[i] >= HDMITX_VIN_PORT_SWAP_INVALID)
++        RETIF_BADPARAM(pMirrorTable[i] >= HDMITX_VIN_PORT_MIRROR_INVALID)
++    }
++
++    /* IF pswapTable[n] is not No Change THEN set the port swap registers from
++     * pswapTable[n]
++     */
++    for (i = 0; i < HDMITX_VIN_PORT_MAP_TABLE_LEN; i++)
++    {
++        if (pSwapTable[0] < HDMITX_VIN_PORT_SWAP_NO_CHANGE)
++        {
++            err = setHwRegisterField(pDis,
++                                     kRegVip[i].Register,
++                                     kRegVip[i].MaskSwap,
++                                     pSwapTable[i]);
++            RETIF_REG_FAIL(err)
++        }
++    }
++
++    /* IF pMirrorTable[n] is not No Change THEN set the port mirror registers
++     * from pMirrorTable[n]
++     */
++    for (i = 0; i < HDMITX_VIN_PORT_MAP_TABLE_LEN; i++)
++    {
++        if (pMirrorTable[0] < HDMITX_VIN_PORT_MIRROR_NO_CHANGE)
++        {
++            err = setHwRegisterField(pDis,
++                                     kRegVip[i].Register,
++                                     kRegVip[i].MaskMirror,
++                                     pMirrorTable[i]);
++            RETIF_REG_FAIL(err)
++        }
++    }
++
++#ifdef TMFL_RGB_DDR_12BITS
++    /*
++      mux for RGB_DDR_12bits
++    */
++    err = setHwRegister(pDis,E_REG_P00_MUX_VP_VIP_OUT_RW, *pMux);
++    RETIF_REG_FAIL(err);
++#endif
++    
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989SetVideoPortConfig                                              */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989SetVideoPortConfig
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pEnaVideoPortTable,
++    UInt8           *pGndVideoPortTable
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(pEnaVideoPortTable == Null)
++    RETIF_BADPARAM(pGndVideoPortTable == Null)
++
++    err = setHwRegister(pDis,
++                        E_REG_P00_ENA_VP_0_RW,
++                        pEnaVideoPortTable[0]);
++    RETIF_REG_FAIL(err)
++
++    err = setHwRegister(pDis,
++                        E_REG_P00_ENA_VP_1_RW,
++                        pEnaVideoPortTable[1]);
++    RETIF_REG_FAIL(err)
++
++    err = setHwRegister(pDis,
++                        E_REG_P00_ENA_VP_2_RW,
++                        pEnaVideoPortTable[2]);
++    RETIF_REG_FAIL(err)
++
++ /*   err = setHwRegister(pDis,
++                        E_REG_P00_GND_VP_0_RW,
++                        pGndVideoPortTable[0]);
++    RETIF_REG_FAIL(err)*/
++
++ /*  err = setHwRegister(pDis,
++                        E_REG_P00_GND_VP_1_RW,
++                        pGndVideoPortTable[1]);
++    RETIF_REG_FAIL(err)*/
++
++ /* err = setHwRegister(pDis,
++                        E_REG_P00_GND_VP_2_RW,
++                        pGndVideoPortTable[2]);
++    RETIF_REG_FAIL(err)*/
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989SetAudioPortConfig                                              */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989SetAudioPortConfig
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pEnaAudioPortTable,
++    UInt8           *pGndAudioPortTable
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(pEnaAudioPortTable == Null)
++    RETIF_BADPARAM(pGndAudioPortTable == Null)
++
++    err = setHwRegister(pDis,
++                        E_REG_P00_ENA_AP_RW,
++                        pEnaAudioPortTable[0]);
++    RETIF_REG_FAIL(err)
++
++ /*   err = setHwRegister(pDis,
++                        E_REG_P00_GND_AP_RW,
++                        pGndAudioPortTable[0]);
++    RETIF_REG_FAIL(err)*/
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989SetAudioClockPortConfig                                              */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989SetAudioClockPortConfig
++(
++    tmUnitSelect_t  txUnit,
++    UInt8           *pEnaAudioClockPortTable,
++    UInt8           *pGndAudioClockPortTable
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(pEnaAudioClockPortTable == Null)
++    RETIF_BADPARAM(pGndAudioClockPortTable == Null)
++
++    err = setHwRegister(pDis,
++                        E_REG_P00_ENA_ACLK_RW,
++                        pEnaAudioClockPortTable[0]);
++    RETIF_REG_FAIL(err)
++
++    /*err = setHwRegister(pDis,
++                        E_REG_P00_GND_ACLK_RW,
++                        pGndAudioClockPortTable[0]);
++    RETIF_REG_FAIL(err)*/
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* set_video replace E_REG_P00_VIDFORMAT_W register                           */
++/* use it for new video format                                                */
++/*============================================================================*/
++tmErrorCode_t set_video(tmHdmiTxobject_t *pDis,tmbslHdmiTxVidFmt_t reg_idx,tmHdmiTxVidReg_t *format_param)
++{
++   tmErrorCode_t err;
++   UInt8 regVal;
++
++   regVal = 0x00;/* PR1570 FIXED */
++   err = setHwRegister(pDis, E_REG_P00_VIDFORMAT_W, regVal);
++   RETIF_REG_FAIL(err);
++
++   regVal = (UInt8)format_param[reg_idx].nPix;
++   err = setHwRegister(pDis, E_REG_P00_NPIX_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)(format_param[reg_idx].nPix>>8);
++   err = setHwRegister(pDis, E_REG_P00_NPIX_MSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].nLine;
++   err = setHwRegister(pDis, E_REG_P00_NLINE_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)(format_param[reg_idx].nLine>>8);
++   err = setHwRegister(pDis, E_REG_P00_NLINE_MSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].VsLineStart;
++   err = setHwRegister(pDis, E_REG_P00_VS_LINE_STRT_1_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].VsPixStart;
++   err = setHwRegister(pDis, E_REG_P00_VS_PIX_STRT_1_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)(format_param[reg_idx].VsPixStart>>8);
++   err = setHwRegister(pDis, E_REG_P00_VS_PIX_STRT_1_MSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].VsLineEnd;
++   err = setHwRegister(pDis, E_REG_P00_VS_LINE_END_1_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].VsPixEnd;
++   err = setHwRegister(pDis, E_REG_P00_VS_PIX_END_1_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)(format_param[reg_idx].VsPixEnd>>8);
++   err = setHwRegister(pDis, E_REG_P00_VS_PIX_END_1_MSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].HsStart;
++   err = setHwRegister(pDis, E_REG_P00_HS_PIX_START_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)(format_param[reg_idx].HsStart>>8);
++   err = setHwRegister(pDis, E_REG_P00_HS_PIX_START_MSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].HsEnd;
++   err = setHwRegister(pDis, E_REG_P00_HS_PIX_STOP_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)(format_param[reg_idx].HsEnd>>8);
++   err = setHwRegister(pDis, E_REG_P00_HS_PIX_STOP_MSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].ActiveVideoStart;
++   err = setHwRegister(pDis, E_REG_P00_VWIN_START_1_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   err = setHwRegister(pDis, E_REG_P00_VWIN_START_1_MSB_W, 0);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].ActiveVideoEnd;
++   err = setHwRegister(pDis, E_REG_P00_VWIN_END_1_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)(format_param[reg_idx].ActiveVideoEnd>>8);
++   err = setHwRegister(pDis, E_REG_P00_VWIN_END_1_MSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].DeStart;
++   err = setHwRegister(pDis, E_REG_P00_DE_START_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)(format_param[reg_idx].DeStart>>8);
++   err = setHwRegister(pDis, E_REG_P00_DE_START_MSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)format_param[reg_idx].DeEnd;
++   err = setHwRegister(pDis, E_REG_P00_DE_STOP_LSB_W, regVal);
++   RETIF_REG_FAIL(err);
++   
++   regVal = (UInt8)(format_param[reg_idx].DeEnd>>8);
++   err = setHwRegister(pDis, E_REG_P00_DE_STOP_MSB_W, regVal);
++   RETIF_REG_FAIL(err);
++
++#ifdef TMFL_RGB_DDR_12BITS
++   if (format_param[reg_idx].ActiveSpaceStart) {
++      /* enable active space */
++      err = setHwRegisterField(pDis, E_REG_P00_ENABLE_SPACE_W, 0x01, 0x01);
++      RETIF_REG_FAIL(err);
++      
++      /* set active space to black */
++      err = setHwRegister(pDis, E_REG_P00_VSPACE_Y_DATA_W, 0x00);
++      RETIF_REG_FAIL(err);
++      
++      err = setHwRegister(pDis, E_REG_P00_VSPACE_U_DATA_W, 0x80);
++      RETIF_REG_FAIL(err);
++      
++      err = setHwRegister(pDis, E_REG_P00_VSPACE_V_DATA_W, 0x80);
++      RETIF_REG_FAIL(err);
++      
++      /* active space definition */
++      regVal = (UInt8)format_param[reg_idx].ActiveSpaceStart;
++      err = setHwRegister(pDis, E_REG_P00_VSPACE_START_LSB_W, regVal);
++      RETIF_REG_FAIL(err);
++      
++      regVal = (UInt8)((format_param[reg_idx].ActiveSpaceStart>>8) & 0x0F);
++      err = setHwRegister(pDis, E_REG_P00_VSPACE_START_MSB_W, regVal);
++      RETIF_REG_FAIL(err);
++      
++      regVal = (UInt8)format_param[reg_idx].ActiveSpaceEnd;
++      err = setHwRegister(pDis, E_REG_P00_VSPACE_END_LSB_W, regVal);
++      RETIF_REG_FAIL(err);
++      
++      regVal = (UInt8)((format_param[reg_idx].ActiveSpaceEnd>>8) & 0x0F);
++      err = setHwRegister(pDis, E_REG_P00_VSPACE_END_MSB_W, regVal);
++      RETIF_REG_FAIL(err);
++   }
++   else {
++      /* let incoming pixels feel the active space (if any) */
++      err = setHwRegisterField(pDis, E_REG_P00_ENABLE_SPACE_W, 0x01, 0x00);
++      RETIF_REG_FAIL(err);
++   }
++#endif
++
++   return TM_OK;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989VideoInSetSyncAuto                                              */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989VideoInSetSyncAuto
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxSyncSource_t   syncSource,
++    tmbslHdmiTxVidFmt_t       vinFmt,
++    tmbslHdmiTxVinMode_t      vinMode,
++    tmbslHdmiTx3DStructure_t  structure3D
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++    UInt8             reg_idx,reg_idx3D;  /* Video i/p fmt value used for comparison */
++    UInt8             embedded;   /* Register value */
++    UInt8             syncMethod; /* Sync method */
++    UInt8             toggleV;    /* V toggle */
++    UInt8             toggleH;    /* H toggle */
++    UInt8             toggleX;    /* X toggle */
++    UInt16            uRefPix;    /* Output refpix */
++    UInt16            uRefLine;   /* Output refline */
++#ifdef FORMAT_PC
++    UInt8             regVal;/* PR1570 FIXED */
++#endif /* FORMAT_PC */
++    struct sync_desc *sync;
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err);
++    
++    /* Check parameters - syncSource must be specified */
++    RETIF_BADPARAM(syncSource >= HDMITX_SYNCSRC_NO_CHANGE);
++    RETIF_BADPARAM(!IS_VALID_FMT(vinFmt));
++    
++    /* Look up the VIDFORMAT register format from the register format table */
++    /* Quit if the input format does not map to the register format */
++    RETIF_BADPARAM(reg_vid_fmt(vinFmt,structure3D,&reg_idx,&reg_idx3D,&sync));
++
++    /* Select values according to sync source */
++    embedded = 0;
++    switch (syncSource)
++    {
++    case HDMITX_SYNCSRC_EXT_VS:
++        syncMethod = 0;
++        toggleV    = sync[BASE(reg_idx)].v_toggle;
++        toggleH    = sync[BASE(reg_idx)].h_toggle;
++        toggleX    = 0;
++        uRefPix    = sync[BASE(reg_idx)].hfp;
++        uRefLine   = sync[BASE(reg_idx)].vfp;
++        break;
++    case HDMITX_SYNCSRC_EMBEDDED:
++        embedded++;
++        /* fall thru */
++    case HDMITX_SYNCSRC_EXT_VREF:
++    default:
++        syncMethod = 1;
++        toggleV    = 1;
++        toggleH    = 1;
++        toggleX    = 1;
++        uRefPix    = sync[BASE(reg_idx)].href;
++        uRefLine   = sync[BASE(reg_idx)].vref;
++        break;
++    }
++    /* Table has +1 added to refpix values which are not needed in 
++       RGB444, YUV444 and YUV422 modes, but +2 is required in those cases */
++    if (vinMode != HDMITX_VINMODE_CCIR656) 
++    {
++        uRefPix = uRefPix + 2;
++    }
++
++    /* ---------------------------------------------------------- */
++    /* Synchronicity software workaround issue number 106         */
++    /* ---------------------------------------------------------- */
++    if (vinMode == HDMITX_VINMODE_CCIR656) {
++        if (syncSource == HDMITX_SYNCSRC_EXT_VS) {
++            if (pDis->pixRate == HDMITX_PIXRATE_DOUBLE) {
++
++                switch (reg_idx) {
++                case E_REGVFMT_720x480p_60Hz:
++                case E_REGVFMT_720x480i_60Hz:
++                case E_REGVFMT_720x576p_50Hz:
++                case E_REGVFMT_720x576i_50Hz:
++                    uRefPix = uRefPix + 1;
++                break;
++                default:
++                /* do nothing... well I would say : FIXME */
++                break;
++                }
++
++            }
++        }
++    }
++
++
++    /* Set embedded sync */
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_VIP_CNTRL_3_W,
++                             E_MASKREG_P00_VIP_CNTRL_3_emb,
++                             embedded);
++    RETIF_REG_FAIL(err)
++
++    /* Set sync method */
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_TBG_CNTRL_0_W,
++                             E_MASKREG_P00_TBG_CNTRL_0_sync_mthd,
++                             syncMethod);
++    RETIF_REG_FAIL(err)
++
++/*     printk("DBG auto toggle X:%d V:%d H:%d\n",toggleX,toggleV,toggleH); */
++    /* Set VH toggle */
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_VIP_CNTRL_3_W,
++                             E_MASKREG_P00_VIP_CNTRL_3_v_tgl,
++                             toggleV);
++    RETIF_REG_FAIL(err)
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_VIP_CNTRL_3_W,
++                             E_MASKREG_P00_VIP_CNTRL_3_h_tgl,
++                             toggleH);
++    RETIF_REG_FAIL(err)
++
++    /* Set X toggle */
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_VIP_CNTRL_3_W,
++                             E_MASKREG_P00_VIP_CNTRL_3_x_tgl,
++                             toggleX);
++    RETIF_REG_FAIL(err);
++    
++#ifdef TMFL_RGB_DDR_12BITS
++    if (syncSource == HDMITX_SYNCSRC_EXT_VREF) {
++       if (structure3D == HDMITX_3D_FRAME_PACKING) {
++          /* 
++             stereo sync signaling : 
++             -----------------------
++             
++             When there is a positive sync at the input pins, therefore a negative sync
++             at input of the TBG, then 3d_neg_vs signal has to be set at 1 (OR-function)
++             to create the correct VS to preset the line and pixel counters
++             
++             case Vs > 0:
++             -----------
++             Vs     : __/¨¨\__
++             Vs(TBG): ¨¨\__/¨¨ where Vs(TBG)=NOT(Vs)
++             3D     : ¨¨\_____ 
++             Stereo : ¨¨\__/¨¨ where Stereo = Vs(TBG) OR 3D because 3d_neg_vs = 1
++             
++             case Vs < 0:
++             -----------
++             Vs     : ¨¨\__/¨¨
++             Vs(TBG): __/¨¨\__ where Vs(TBG)=NOT(Vs)
++             3D     : ¨¨\_____ 
++             Stereo : __/¨¨\__ where Stereo = Vs(TBG) AND NOT(3D) because 3d_neg_vs = 0
++             
++             
++             It is possible to invert the incoming VS, HS and DE. In case of 3D format
++             the DE input will be the 3D signal. This signal will only be used to remove
++             1 of the VS depending on the polarity of the 3D signal. When there is a need
++             to switch the Left or Right it is possible to invert the 3D signal with an
++             already existing register.
++             
++          */
++          
++          err = setHwRegisterField(pDis,
++                                   E_REG_P00_VIDFORMAT_W,
++                                   E_MASKREG_P00_VIDFORMAT_3d_neg_vs,
++                                   toggleV);
++          RETIF_REG_FAIL(err);
++       }
++       err = setHwRegisterField(pDis,
++                                E_REG_P00_VIDFORMAT_W,
++                                E_MASKREG_P00_VIDFORMAT_3d,
++                                (structure3D == HDMITX_3D_FRAME_PACKING));
++       RETIF_REG_FAIL(err);
++    }
++#endif
++
++
++    if (EXTRA(reg_idx) && (structure3D != HDMITX_3D_FRAME_PACKING)) {
++       /* 2d extra video format */
++       RETIF_REG_FAIL(set_video(pDis,BASE(reg_idx),(tmHdmiTxVidReg_t *)format_param_extra));
++    }
++    else if (EXTRA(reg_idx3D) && (structure3D == HDMITX_3D_FRAME_PACKING)) {
++       /* 3d extra frame packing */
++       RETIF_REG_FAIL(set_video(pDis,BASE(reg_idx3D),(tmHdmiTxVidReg_t *)format_param_extra));
++    }
++    else {
++       /* see video set up using E_REG_P00_VIDFORMAT_W */ 
++    }
++                   
++                   
++#ifdef FORMAT_PC
++                   
++    if (IS_PC(vinFmt))
++    {
++       RETIF_REG_FAIL(set_video(pDis,reg_idx,(tmHdmiTxVidReg_t *)format_param_PC));
++
++       regVal = DEPTH_COLOR_PC;
++       err = setHwRegisterField(pDis,
++                                E_REG_P00_HVF_CNTRL_1_W,
++                                E_MASKREG_P00_HVF_CNTRL_1_pad,
++                                regVal);
++       RETIF_REG_FAIL(err);
++    }
++#endif /* FORMAT_PC */
++
++    /* Set refpix, refline */
++    err = setHwRegisterMsbLsb(pDis, E_REG_P00_REFPIX_MSB_W, uRefPix);
++    RETIF_REG_FAIL(err)
++    err = setHwRegisterMsbLsb(pDis, E_REG_P00_REFLINE_MSB_W, uRefLine);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989VideoInSetSyncManual                                            */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989VideoInSetSyncManual
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxSyncSource_t   syncSource,
++    tmbslHdmiTxVsMeth_t       syncMethod,
++    tmbslHdmiTxPixTogl_t      toggleV,
++    tmbslHdmiTxPixTogl_t      toggleH,
++    tmbslHdmiTxPixTogl_t      toggleX,
++    UInt16                    uRefPix,    
++    UInt16                    uRefLine   
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++    UInt8             embedded;   /* Register value */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(syncSource   >= HDMITX_SYNCSRC_INVALID)
++    RETIF_BADPARAM(syncMethod   >= HDMITX_VSMETH_INVALID)
++    RETIF_BADPARAM(toggleV      >= HDMITX_PIXTOGL_INVALID)
++    RETIF_BADPARAM(toggleH      >= HDMITX_PIXTOGL_INVALID)
++    RETIF_BADPARAM(toggleX      >= HDMITX_PIXTOGL_INVALID)
++    RETIF_BADPARAM(uRefPix  >= HDMITX_VOUT_FINE_PIXEL_INVALID)
++    RETIF_BADPARAM(uRefLine >= HDMITX_VOUT_FINE_LINE_INVALID)
++
++    if (syncSource != HDMITX_SYNCSRC_NO_CHANGE)
++    {
++        if (syncSource == HDMITX_SYNCSRC_EMBEDDED)
++        {
++            embedded = 1;
++        }
++        else
++        {
++            embedded = 0;
++        }
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_3_W,
++                                 E_MASKREG_P00_VIP_CNTRL_3_emb,
++                                 embedded);
++        RETIF_REG_FAIL(err)
++    }
++    if (syncMethod != HDMITX_VSMETH_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_TBG_CNTRL_0_W,
++                                 E_MASKREG_P00_TBG_CNTRL_0_sync_mthd,
++                                 (UInt8)syncMethod);
++        RETIF_REG_FAIL(err)
++    }
++/*     printk("DBG manual toggle X:%d V:%d H:%d\n",toggleX,toggleV,toggleH); */
++    if (toggleV != HDMITX_PIXTOGL_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_3_W,
++                                 E_MASKREG_P00_VIP_CNTRL_3_v_tgl,
++                                 (UInt8)toggleV);
++        RETIF_REG_FAIL(err)
++    }
++    if (toggleH != HDMITX_PIXTOGL_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_3_W,
++                                 E_MASKREG_P00_VIP_CNTRL_3_h_tgl,
++                                 (UInt8)toggleH);
++        RETIF_REG_FAIL(err)
++    }
++    if (toggleX != HDMITX_PIXTOGL_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_3_W,
++                                 E_MASKREG_P00_VIP_CNTRL_3_x_tgl,
++                                 (UInt8)toggleX);
++        RETIF_REG_FAIL(err)
++    }
++    if (uRefPix < HDMITX_VOUT_FINE_PIXEL_NO_CHANGE)
++    {
++        err = setHwRegisterMsbLsb(pDis, E_REG_P00_REFPIX_MSB_W, uRefPix);
++        RETIF_REG_FAIL(err)
++    }
++    if (uRefLine < HDMITX_VOUT_FINE_LINE_NO_CHANGE)
++    {
++        err = setHwRegisterMsbLsb(pDis, E_REG_P00_REFLINE_MSB_W, uRefLine);
++        RETIF_REG_FAIL(err)
++    }
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989VideoOutDisable                                                 */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989VideoOutDisable
++(
++    tmUnitSelect_t  txUnit,
++    Bool            bDisable
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(bDisable > True)
++
++    /* Set or clear frame_dis in the scaler Timebase Control 0 register 
++     * according to bDisable
++     */
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_TBG_CNTRL_0_W,
++                             E_MASKREG_P00_TBG_CNTRL_0_frame_dis,
++                             (UInt8)bDisable);
++    if (bDisable)
++    {
++        setState(pDis, EV_OUTDISABLE);
++    }
++    return err;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989VideoOutSetConfig                                               */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989VideoOutSetConfig
++(
++    tmUnitSelect_t            txUnit,
++    tmbslHdmiTxSinkType_t     sinkType,
++    tmbslHdmiTxVoutMode_t     voutMode,
++    tmbslHdmiTxVoutPrefil_t   preFilter,
++    tmbslHdmiTxVoutYuvBlnk_t  yuvBlank,
++    tmbslHdmiTxVoutQrange_t   quantization 
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++    UInt8             regVal;     /* Register value */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(sinkType     >= HDMITX_SINK_INVALID)
++    RETIF_BADPARAM(voutMode     >= HDMITX_VOUTMODE_INVALID)
++    RETIF_BADPARAM(preFilter    >= HDMITX_VOUT_PREFIL_INVALID)
++    RETIF_BADPARAM(yuvBlank     >= HDMITX_VOUT_YUV_BLNK_INVALID)
++    RETIF_BADPARAM(quantization >= HDMITX_VOUT_QRANGE_INVALID)
++
++    if (sinkType == HDMITX_SINK_EDID)
++    {
++        if (pDis->EdidStatus == HDMITX_EDID_NOT_READ)
++        {
++            /* EDID has not been read so assume simplest sink */
++            pDis->sinkType = HDMITX_SINK_DVI;
++        }
++        else
++        {
++            /* EDID has been read so set sink to the type that was read */
++            pDis->sinkType = pDis->EdidSinkType;
++        }
++    }
++    else
++    {
++        /* Set demanded sink type */
++        pDis->sinkType = sinkType;
++    }
++
++    /* Is DVI sink required? */
++    if (pDis->sinkType == HDMITX_SINK_DVI)
++    {
++        /* Mute the audio FIFO */
++        err = setHwRegisterField(pDis,
++                                 E_REG_P11_AIP_CNTRL_0_RW,
++                                 E_MASKREG_P11_AIP_CNTRL_0_rst_fifo,
++                                 1);
++        RETIF_REG_FAIL(err)
++
++        /* Force RGB mode for DVI sink */
++        voutMode = HDMITX_VOUTMODE_RGB444;
++
++        /* Set HDMI HDCP mode off for DVI */
++        err = setHwRegisterFieldTable(pDis, &kVoutHdcpOff[0]);
++        RETIF_REG_FAIL(err);
++
++        HDCP_F1;
++
++        err = setHwRegisterField(pDis,
++                                 E_REG_P11_ENC_CNTRL_RW,
++                                 E_MASKREG_P11_ENC_CNTRL_ctl_code,
++                                 regVal);
++        RETIF_REG_FAIL(err)
++    }
++    else
++    {
++        /* Unmute the audio FIFO */
++        err = setHwRegisterField(pDis,
++                                 E_REG_P11_AIP_CNTRL_0_RW,
++                                 E_MASKREG_P11_AIP_CNTRL_0_rst_fifo,
++                                 0);
++        RETIF_REG_FAIL(err)
++
++        /* Set HDMI HDCP mode on for HDMI */
++        /* Also sets E_MASKREG_P11_ENC_CNTRL_ctl_code */
++        err = setHwRegisterFieldTable(pDis, &kVoutHdcpOn[0]);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* For each parameter that is not No Change, set its register */
++    if (voutMode != HDMITX_VOUTMODE_NO_CHANGE)
++    {
++        /* Save the output mode for later use by the matrix & downsampler */
++        pDis->voutMode = voutMode;
++    }
++    if (preFilter < HDMITX_VOUT_PREFIL_NO_CHANGE)
++    {
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++       /* 
++          power management :
++          freeze/wakeup SPDIF clock
++       */
++       err = setHwRegisterField(pDis, E_REG_FEAT_POWER_DOWN,            \
++                                E_MASKREG_FEAT_POWER_DOWN_prefilt,      \
++                                (preFilter == HDMITX_VOUT_PREFIL_OFF));
++       RETIF_REG_FAIL(err);
++#endif
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P00_HVF_CNTRL_0_W, 
++                                 E_MASKREG_P00_HVF_CNTRL_0_prefil,
++                                 (UInt8)preFilter);
++        RETIF_REG_FAIL(err)
++    }
++    if (yuvBlank < HDMITX_VOUT_YUV_BLNK_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P00_HVF_CNTRL_1_W, 
++                                 E_MASKREG_P00_HVF_CNTRL_1_yuvblk,
++                                 (UInt8)yuvBlank);
++        RETIF_REG_FAIL(err)
++    }
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989VideoOutSetSync                                                 */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989VideoOutSetSync
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxVsSrc_t      srcH,
++    tmbslHdmiTxVsSrc_t      srcV,
++    tmbslHdmiTxVsSrc_t      srcX,
++    tmbslHdmiTxVsTgl_t      toggle,
++    tmbslHdmiTxVsOnce_t     once
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++    UInt8 reg_idx;
++    struct sync_desc *sync;
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(srcH   >= HDMITX_VSSRC_INVALID)
++    RETIF_BADPARAM(srcV   >= HDMITX_VSSRC_INVALID)
++    RETIF_BADPARAM(srcX   >= HDMITX_VSSRC_INVALID)
++    RETIF_BADPARAM(toggle >= HDMITX_VSTGL_INVALID)
++    RETIF_BADPARAM(once   >= HDMITX_VSONCE_INVALID)
++
++    /* For each parameter that is not No Change, set its register */
++    if (srcH != HDMITX_VSSRC_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_TBG_CNTRL_1_W,
++                                 E_MASKREG_P00_TBG_CNTRL_1_vhx_ext_hs,
++                                 (UInt8)srcH);
++        RETIF_REG_FAIL(err)
++    }
++    if (srcV != HDMITX_VSSRC_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_TBG_CNTRL_1_W,
++                                 E_MASKREG_P00_TBG_CNTRL_1_vhx_ext_vs,
++                                 (UInt8)srcV);
++        RETIF_REG_FAIL(err)
++    }
++    if (srcX != HDMITX_VSSRC_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_TBG_CNTRL_1_W,
++                                 E_MASKREG_P00_TBG_CNTRL_1_vhx_ext_de,
++                                 (UInt8)srcX);
++        RETIF_REG_FAIL(err)
++    }
++    {
++       /* Hs Vs polarity fix */
++       /* set polarity back when VIDFORMAT_TABLE (E_REG_P00_VIDFORMAT_W) is not used */
++       RETIF_BADPARAM(reg_vid_fmt(pDis->vinFmt,0,&reg_idx,0,&sync));
++       if (EXTRA(reg_idx)) {
++          toggle= E_MASKREG_P00_TBG_CNTRL_1_vh_tgl &                    \
++             (0x04 | sync[BASE(reg_idx)].v_toggle | sync[BASE(reg_idx)].h_toggle);
++       }
++    }
++
++
++    if (toggle != HDMITX_VSTGL_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_TBG_CNTRL_1_W,
++                                 E_MASKREG_P00_TBG_CNTRL_1_vh_tgl,
++                                 (UInt8)toggle);
++/*         printk("DBG toogl CNTRL1:%d\n",toggle); */
++        RETIF_REG_FAIL(err)
++    }
++    if (once != HDMITX_VSONCE_NO_CHANGE)
++    {
++        /* Must be last register set */
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_TBG_CNTRL_0_W,
++                                 E_MASKREG_P00_TBG_CNTRL_0_sync_once,
++                                 (UInt8)once);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Toggle TMDS serialiser force flags - stability fix */
++    err = setHwRegisterField(pDis,
++                             E_REG_P02_BUFFER_OUT_RW,
++                             E_MASKREG_P02_BUFFER_OUT_srl_force,
++                             (UInt8)HDMITX_TMDSOUT_FORCED0);
++    RETIF_REG_FAIL(err)
++    err = setHwRegisterField(pDis,
++                             E_REG_P02_BUFFER_OUT_RW,
++                             E_MASKREG_P02_BUFFER_OUT_srl_force,
++                             (UInt8)HDMITX_TMDSOUT_NORMAL);
++    RETIF_REG_FAIL(err)
++
++
++    if (once == HDMITX_VSONCE_ONCE)
++    {
++        /* Toggle output Sync Once flag for settings to take effect */
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_TBG_CNTRL_0_W,
++                                 E_MASKREG_P00_TBG_CNTRL_0_sync_once,
++                                 (UInt8)HDMITX_VSONCE_EACH_FRAME);
++        RETIF_REG_FAIL(err)
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_TBG_CNTRL_0_W,
++                                 E_MASKREG_P00_TBG_CNTRL_0_sync_once,
++                                 (UInt8)HDMITX_VSONCE_ONCE);
++        RETIF_REG_FAIL(err)
++    }
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989VideoSetInOut                                                   */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989VideoSetInOut
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxVidFmt_t     vinFmt,
++    tmbslHdmiTx3DStructure_t structure3D,
++    tmbslHdmiTxScaMode_t    scaModeRequest,
++    tmbslHdmiTxVidFmt_t     voutFmt,
++    UInt8                   uPixelRepeat,
++    tmbslHdmiTxMatMode_t    matMode,
++    tmbslHdmiTxVoutDbits_t  datapathBits,
++    tmbslHdmiTxVQR_t        dviVqr
++)
++{
++    tmHdmiTxobject_t        *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t           err;         /* Error code */
++    tmbslHdmiTxScaMode_t    scaMode;     /* Scaler mode */
++    UInt8                   reg_idx,reg_idx3D;  /* Video o/p format value used for register */
++    UInt8 regVal;
++    
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(!IS_VALID_FMT(vinFmt))
++    RETIF_BADPARAM(!IS_VALID_FMT(voutFmt))
++
++    RETIF_BADPARAM(scaModeRequest >= HDMITX_SCAMODE_INVALID)
++    RETIF_BADPARAM(uPixelRepeat   >= HDMITX_PIXREP_INVALID)
++    RETIF_BADPARAM(matMode        >= HDMITX_MATMODE_INVALID)
++    RETIF_BADPARAM(datapathBits   >= HDMITX_VOUT_DBITS_INVALID)
++
++    scaMode = HDMITX_SCAMODE_OFF;
++    pDis->scaMode = HDMITX_SCAMODE_OFF;
++
++    /* Get current input format if it must not change */
++    if (vinFmt == HDMITX_VFMT_NO_CHANGE)
++    {
++        RETIF(pDis->vinFmt == HDMITX_VFMT_NULL,
++              TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++        vinFmt = pDis->vinFmt;
++    }
++    else
++    {
++        pDis->vinFmt = vinFmt;
++        pDis->h3dFpOn = (structure3D == HDMITX_3D_FRAME_PACKING);
++
++#ifdef TMFL_TDA9989_PIXEL_CLOCK_ON_DDC
++
++        if (IS_TV(pDis->vinFmt)) {
++           
++           err = setHwRegister(pDis, E_REG_P00_TIMER_H_W, 0);
++           RETIF(err != TM_OK, err);
++           
++           err = setHwRegister(pDis, E_REG_P00_NDIV_IM_W, kndiv_im[vinFmt]);
++           RETIF(err != TM_OK, err);
++           
++           err = setHwRegister(pDis, E_REG_P12_TX3_RW, kclk_div[vinFmt]);
++           RETIF(err != TM_OK, err);
++           
++        }
++        else {
++           
++           err = setHwRegister(pDis, E_REG_P00_TIMER_H_W, E_MASKREG_P00_TIMER_H_im_clksel);
++           RETIF(err != TM_OK, err);
++           err = setHwRegister(pDis, E_REG_P12_TX3_RW, 17);
++           RETIF(err != TM_OK, err);
++        }
++#endif /* TMFL_TDA9989_PIXEL_CLOCK_ON_DDC */
++
++
++    }
++
++    /* Get current output format if it must not change */
++    if (voutFmt == HDMITX_VFMT_NO_CHANGE)
++    {
++        RETIF(pDis->voutFmt == HDMITX_VFMT_NULL,
++              TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++        voutFmt = pDis->voutFmt;
++    }
++    else
++    {
++        pDis->voutFmt = voutFmt;
++    }
++    if (pDis->voutMode == HDMITX_VOUTMODE_RGB444)
++    {
++       if ((pDis->voutFmt >= HDMITX_VFMT_02_720x480p_60Hz) && (IS_TV(pDis->voutFmt)))
++        {
++            err = setHwRegisterField(pDis, 
++                                    E_REG_P00_HVF_CNTRL_1_W, 
++                                    E_MASKREG_P00_HVF_CNTRL_1_vqr,
++                                    (UInt8) HDMITX_VOUT_QRANGE_RGB_YUV);
++            RETIF_REG_FAIL(err)
++        }
++        else /*Format PC or VGA*/
++        {
++            err = setHwRegisterField(pDis, 
++                                    E_REG_P00_HVF_CNTRL_1_W, 
++                                    E_MASKREG_P00_HVF_CNTRL_1_vqr,
++                                    (UInt8) HDMITX_VOUT_QRANGE_FS);
++            RETIF_REG_FAIL(err)
++        }
++    }
++    else
++    {
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P00_HVF_CNTRL_1_W, 
++                                 E_MASKREG_P00_HVF_CNTRL_1_vqr,
++                                 (UInt8) HDMITX_VOUT_QRANGE_YUV);
++        RETIF_REG_FAIL(err);
++    }
++
++    /* Set pixel repetition - sets pixelRepeatCount, used by setScalerFormat */
++    err = setPixelRepeat(pDis, voutFmt, uPixelRepeat, structure3D);
++    RETIF(err != TM_OK, err);
++    
++    /* If scaler mode is auto then set mode based on input and output format */
++    if (scaMode != HDMITX_SCAMODE_NO_CHANGE)
++       {
++          /* Set scaler clock */
++          regVal = 0;
++          if ((pDis->pixelRepeatCount > HDMITX_PIXREP_MIN) && 
++              (pDis->pixelRepeatCount <= HDMITX_PIXREP_MAX))
++             {
++                regVal = 2;
++             }
++          else if (pDis->vinMode == HDMITX_VINMODE_CCIR656)
++             {
++                regVal = (UInt8)((pDis->scaMode == HDMITX_SCAMODE_ON) ? 0 : 1);
++                
++                if (pDis->pixRate == HDMITX_PIXRATE_DOUBLE)
++                   {
++                      regVal = 0;
++                   }
++             }
++          
++          err = setHwRegisterField(pDis,
++                                   E_REG_P02_SEL_CLK_RW, 
++                                   E_MASKREG_P02_SEL_CLK_sel_vrf_clk,
++                                   regVal);
++          RETIF_REG_FAIL(err);
++          
++          /* Look up the VIDFORMAT register format from the register format table */
++          RETIF_BADPARAM(reg_vid_fmt(vinFmt,structure3D,&reg_idx,&reg_idx3D,0));
++
++          /* Set format register for the selected output format voutFmt */
++          if (PREFETCH(reg_idx3D) && (structure3D == HDMITX_3D_FRAME_PACKING)) {
++             /* embedded 3D video format */
++             err = setHwRegister(pDis, E_REG_P00_VIDFORMAT_W,reg_idx3D);
++          }
++          else if (PREFETCH(reg_idx) && (structure3D != HDMITX_3D_FRAME_PACKING)) {
++             /* embedded 2D video format */
++/*              printk("DBG %s E_REG_P00_VIDFORMAT_W used\n",__func__); */
++             err = setHwRegister(pDis, E_REG_P00_VIDFORMAT_W,reg_idx);
++          }
++          else {
++             /* see video set up using set_video() */
++          }
++          RETIF_REG_FAIL(err);
++          
++       }
++    
++    /* Set VS and optional DE */
++    err = setDeVs(pDis, voutFmt, structure3D);
++    RETIF(err != TM_OK, err);
++       
++    /* If matrix mode is auto then set mode based on input and output format */
++    if (matMode != HDMITX_MATMODE_NO_CHANGE)
++    {
++        if (matMode == HDMITX_MATMODE_AUTO)
++        {
++            err = tmbslTDA9989MatrixSetConversion(txUnit, vinFmt,
++          pDis->vinMode, voutFmt, pDis->voutMode,pDis->dviVqr);
++        }
++        else
++        {
++            err = tmbslTDA9989MatrixSetMode(txUnit, HDMITX_MCNTRL_OFF, 
++                  HDMITX_MSCALE_NO_CHANGE);
++        }
++        RETIF(err != TM_OK, err)
++    }
++
++    /* Set upsampler and downsampler */
++    err = setSampling(pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Set colour component bit depth */
++    if (datapathBits != HDMITX_VOUT_DBITS_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P00_HVF_CNTRL_1_W, 
++                                 E_MASKREG_P00_HVF_CNTRL_1_pad,
++                                 (UInt8)datapathBits);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Save kBypassColourProc registers before pattern goes on */
++    getHwRegister(pDis, E_REG_P00_MAT_CONTRL_W,  &gMatContrl[txUnit]);
++    getHwRegister(pDis, E_REG_P00_HVF_CNTRL_0_W, &gHvfCntrl0[txUnit]);
++    getHwRegister(pDis, E_REG_P00_HVF_CNTRL_1_W, &gHvfCntrl1[txUnit]);
++
++    setState(pDis, EV_SETINOUT);
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989MatrixSetCoeffs                                                 */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989MatrixSetCoeffs
++(
++    tmUnitSelect_t         txUnit,
++    tmbslHdmiTxMatCoeff_t *pMatCoeff
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    Int                 i;      /* Loop index */
++    UInt8               buf[HDMITX_MAT_COEFF_NUM * 2];     /* Temp buffer */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pMatCoeff == (tmbslHdmiTxMatCoeff_t *)0)
++    for (i = 0; i < HDMITX_MAT_COEFF_NUM; i++)
++    {
++        RETIF_BADPARAM((pMatCoeff->Coeff[i] < HDMITX_MAT_OFFSET_MIN) || 
++              (pMatCoeff->Coeff[i] > HDMITX_MAT_OFFSET_MAX))
++    }
++
++    /* Convert signed 11 bit values from Coeff array to pairs of MSB-LSB
++     * register values, and write to register pairs
++     */
++    for (i = 0; i < HDMITX_MAT_COEFF_NUM; i++)
++    {
++        /* Mask & copy MSB */
++        buf[i*2] = (UInt8)(((UInt16)pMatCoeff->Coeff[i] & 0x0700) >> 8);
++        /* Copy LSB */
++        buf[(i*2)+1] = (UInt8)((UInt16)pMatCoeff->Coeff[i] & 0x00FF);
++    }
++    err = setHwRegisters(pDis,
++                         E_REG_P00_MAT_P11_MSB_W,
++                         &buf[0],
++                         HDMITX_MAT_COEFF_NUM * 2);
++    return err;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989MatrixSetConversion                                             */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989MatrixSetConversion
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxVidFmt_t     vinFmt,
++    tmbslHdmiTxVinMode_t    vinMode,
++    tmbslHdmiTxVidFmt_t     voutFmt,
++    tmbslHdmiTxVoutMode_t   voutMode,
++    tmbslHdmiTxVQR_t        dviVqr
++)
++{
++    tmHdmiTxobject_t            *pDis;  /* Ptr to Device Instance Structure */
++    tmErrorCode_t               err;        /* Error code */
++    tmbslTDA9989Colourspace_t    cspace_in;  /* Input colourspaces */
++    tmbslTDA9989Colourspace_t    cspace_out; /* Output colourspaces */
++    Int                         matrixIndex;/* Index into matrix preset array */
++    UInt8                       buf[MATRIX_PRESET_SIZE]; /* Temp buffer */
++    UInt8                       i; /* Loop index */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(!IS_VALID_FMT(vinFmt))
++    RETIF_BADPARAM(!IS_VALID_FMT(voutFmt))
++    /* NB: NO_CHANGE is not valid for this function, so limit to actual values*/
++    RETIF_BADPARAM(vinMode >= HDMITX_VINMODE_NO_CHANGE)
++    /* NB: NO_CHANGE is not valid for this function, so limit to actual values*/
++    RETIF_BADPARAM(voutMode >= HDMITX_VOUTMODE_NO_CHANGE)
++
++    /* Since vinMode and voutMode are different types, we don't use a local
++       function to do this and use inline code twice */
++     
++
++    /* Calculate input colour space */
++        switch (vinFmt)
++        {       /* Catch the HD modes */
++        case HDMITX_VFMT_04_1280x720p_60Hz:
++        case HDMITX_VFMT_05_1920x1080i_60Hz:
++        case HDMITX_VFMT_16_1920x1080p_60Hz:
++        case HDMITX_VFMT_19_1280x720p_50Hz:
++        case HDMITX_VFMT_20_1920x1080i_50Hz:
++        case HDMITX_VFMT_31_1920x1080p_50Hz:
++        case HDMITX_VFMT_32_1920x1080p_24Hz:
++        case HDMITX_VFMT_33_1920x1080p_25Hz:
++        case HDMITX_VFMT_34_1920x1080p_30Hz:
++        case HDMITX_VFMT_60_1280x720p_24Hz:
++        case HDMITX_VFMT_61_1280x720p_25Hz:
++        case HDMITX_VFMT_62_1280x720p_30Hz:
++    
++            if(vinMode == HDMITX_VINMODE_RGB444)    /* RGB */
++            {
++                cspace_in = HDMITX_CS_RGB_LIMITED;
++            }
++            else                                    /* CCIR656, YUV444, YU422 */
++            {
++                cspace_in = HDMITX_CS_YUV_ITU_BT709;
++            }
++            break;
++        default:    /* Now all the SD modes */
++            if(vinMode == HDMITX_VINMODE_RGB444)    /* we're RGB */
++            {
++                cspace_in = HDMITX_CS_RGB_LIMITED;
++            }
++            else                                    /* CCIR656, YUV444, YU422 */
++            {
++                cspace_in = HDMITX_CS_YUV_ITU_BT601;
++            }
++            break;
++        }
++
++/*     } */
++
++    /* Calculate output colour space */
++#ifdef FORMAT_PC
++    if(IS_PC(voutFmt))
++    {
++        /* Catch the PC formats */
++    	cspace_in = HDMITX_CS_RGB_FULL; /* PR1570 FIXED */
++        cspace_out = HDMITX_CS_RGB_FULL;
++    }
++    else
++    {
++#endif
++        switch (voutFmt)
++        {       /* Catch the HD modes */
++        case HDMITX_VFMT_04_1280x720p_60Hz:
++        case HDMITX_VFMT_05_1920x1080i_60Hz:
++        case HDMITX_VFMT_16_1920x1080p_60Hz:
++        case HDMITX_VFMT_19_1280x720p_50Hz:
++        case HDMITX_VFMT_20_1920x1080i_50Hz:
++        case HDMITX_VFMT_31_1920x1080p_50Hz:
++        case HDMITX_VFMT_32_1920x1080p_24Hz:
++        case HDMITX_VFMT_33_1920x1080p_25Hz:
++        case HDMITX_VFMT_34_1920x1080p_30Hz:
++        case HDMITX_VFMT_60_1280x720p_24Hz:
++        case HDMITX_VFMT_61_1280x720p_25Hz:
++        case HDMITX_VFMT_62_1280x720p_30Hz:
++            
++            if(voutMode == HDMITX_VOUTMODE_RGB444)  /* RGB */
++            {
++                cspace_out = HDMITX_CS_RGB_LIMITED;
++            }
++            else                                    /* YUV444 or YUV422 */
++            {
++                cspace_out = HDMITX_CS_YUV_ITU_BT709;
++            }
++            break;
++        default:    /* Now all the SD modes */
++            if(voutMode == HDMITX_VOUTMODE_RGB444)  /* RGB */
++            {
++                cspace_out = HDMITX_CS_RGB_LIMITED;
++            }
++            else                                    /* YUV444 or YUV422 */
++            {
++                cspace_out = HDMITX_CS_YUV_ITU_BT601;
++            }
++            break;
++        }
++#ifdef FORMAT_PC
++    }
++#endif
++
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++    /* 
++       power management :
++       freeze/wakeup color space conversion clock
++    */
++    err = setHwRegisterField(pDis, E_REG_FEAT_POWER_DOWN,             \
++                             E_MASKREG_FEAT_POWER_DOWN_csc,           \
++                             (cspace_in == cspace_out));
++    RETIF_REG_FAIL(err);
++#endif
++
++    if (cspace_in == cspace_out)
++    {
++        /* Switch off colour matrix by setting bypass flag */
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P00_MAT_CONTRL_W,
++                                 E_MASKREG_P00_MAT_CONTRL_mat_bp,
++                                 1);
++    }
++    else
++    {
++        /* Load appropriate values into matrix  - we have preset blocks of
++         * 31 register vales in a table, just need to work out which set to use
++         */
++        matrixIndex = kMatrixIndex[cspace_in][cspace_out];
++
++        /* Set the first block byte separately, as it is shadowed and can't
++         * be set by setHwRegisters */
++        err = setHwRegister(pDis,
++                             E_REG_P00_MAT_CONTRL_W,
++                             kMatrixPreset[matrixIndex][0]);
++        RETIF_REG_FAIL(err)
++        
++        for (i = 0; i < MATRIX_PRESET_SIZE; i++)
++        {
++            buf[i] = kMatrixPreset[matrixIndex][i];
++        }
++        
++        /* Set the rest of the block */
++        err = setHwRegisters(pDis,
++                             E_REG_P00_MAT_OI1_MSB_W,
++                             &buf[1],
++                             MATRIX_PRESET_SIZE - 1);
++    }
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989MatrixSetInputOffset                                            */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989MatrixSetInputOffset
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxMatOffset_t  *pMatOffset
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    Int                 i;      /* Loop index */
++    UInt8               buf[HDMITX_MAT_OFFSET_NUM * 2];    /* Temp buffer */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pMatOffset == (tmbslHdmiTxMatOffset_t *)0)
++    for (i = 0; i < HDMITX_MAT_OFFSET_NUM; i++)
++    {
++        RETIF_BADPARAM((pMatOffset->Offset[i] < HDMITX_MAT_OFFSET_MIN) || 
++              (pMatOffset->Offset[i] > HDMITX_MAT_OFFSET_MAX))
++    }
++
++    /* Convert signed 11 bit values from Offset array to pairs of MSB-LSB
++     * register values, and write to register pairs
++     */
++    for (i = 0; i < HDMITX_MAT_OFFSET_NUM; i++)
++    {
++        /* Mask & copy MSB */
++        buf[i*2] = (UInt8)(((UInt16)pMatOffset->Offset[i] & 0x0700) >> 8);
++        /* Copy LSB */
++        buf[(i*2)+1] = (UInt8)((UInt16)pMatOffset->Offset[i] & 0x00FF);
++    }
++    err = setHwRegisters(pDis,
++                         E_REG_P00_MAT_OI1_MSB_W,
++                         &buf[0],
++                         HDMITX_MAT_OFFSET_NUM * 2);
++    return err;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989MatrixSetMode                                                   */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989MatrixSetMode
++(
++    tmUnitSelect_t       txUnit,
++    tmbslHdmiTxmCntrl_t mControl,
++    tmbslHdmiTxmScale_t mScale
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM((mControl > HDMITX_MCNTRL_MAX) ||
++          (mScale > HDMITX_MSCALE_MAX))
++
++    /* For each value that is not NoChange, update the appropriate register */
++    if (mControl != HDMITX_MCNTRL_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P00_MAT_CONTRL_W,
++                                 E_MASKREG_P00_MAT_CONTRL_mat_bp,
++                                 (UInt8)mControl);
++        RETIF_REG_FAIL(err)
++    }
++
++    if (mScale != HDMITX_MSCALE_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P00_MAT_CONTRL_W,
++                                 E_MASKREG_P00_MAT_CONTRL_mat_sc,
++                                 (UInt8)mScale);
++        RETIF_REG_FAIL(err)
++    }
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989MatrixSetOutputOffset                                           */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989MatrixSetOutputOffset
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxMatOffset_t  *pMatOffset
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    Int                 i;      /* Loop index */
++    UInt8               buf[HDMITX_MAT_OFFSET_NUM * 2];   /* Temp buffer */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM(pMatOffset == (tmbslHdmiTxMatOffset_t *)0)
++    for (i = 0; i < HDMITX_MAT_OFFSET_NUM; i++)
++    {
++        RETIF_BADPARAM((pMatOffset->Offset[i] < HDMITX_MAT_OFFSET_MIN) || 
++              (pMatOffset->Offset[i] > HDMITX_MAT_OFFSET_MAX))
++    }
++
++    /* Convert signed 11 bit values from Offset array to pairs of MSB-LSB
++     * register values, and write to register pairs
++     */
++    for (i = 0; i < HDMITX_MAT_OFFSET_NUM; i++)
++    {
++        /* Mask & copy MSB */
++        buf[i*2] = (UInt8)(((UInt16)pMatOffset->Offset[i] & 0x0700) >> 8);
++        /* Copy LSB */
++        buf[(i*2)+1] = (UInt8)((UInt16)pMatOffset->Offset[i] & 0x00FF);
++    }
++    err = setHwRegisters(pDis,
++                         E_REG_P00_MAT_OO1_MSB_W,
++                         &buf[0],
++                         HDMITX_MAT_OFFSET_NUM * 2);
++    return err;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetAclkRecovery                                              */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989PktSetAclkRecovery
++(
++    tmUnitSelect_t  txUnit,
++    Bool            bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++    
++    /* Write the ACR packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_FLAGS_RW,
++                             E_MASKREG_P11_DIP_FLAGS_acr,
++                             (UInt8)bEnable);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetAcp                                                       */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PktSetAcp
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPkt_t    *pPkt,
++    UInt                byteCnt,
++    UInt8               uAcpType,
++    Bool                bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    UInt8               buf[3]; /* Temp buffer to hold header bytes */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Only supported for device N4 or later */ 
++
++    /* Check remaining parameter(s) - NULL pointer allowed */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++
++    if(pPkt != Null)
++    {
++        /* Pointer to structure provided so check parameters */
++        RETIF_BADPARAM(byteCnt > HDMITX_PKT_DATA_BYTE_CNT)
++        RETIF(byteCnt == 0, TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++
++        /* Data to change, start by clearing ACP packet insertion flag */
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P11_DIP_FLAGS_RW,
++                                 E_MASKREG_P11_DIP_FLAGS_acp,
++                                 0x00);
++        RETIF_REG_FAIL(err)
++
++        /* Prepare ACP header */
++        buf[0] = 0x04;      /* ACP packet */
++        buf[1] = uAcpType;
++        buf[2] = 0;         /* Reserved [HDMI 1.2] */
++
++
++        /* Write 3 header bytes to registers */
++        err = setHwRegisters(pDis,
++                             E_REG_P11_ACP_HB0_RW,
++                             &buf[0],
++                             3);
++        RETIF_REG_FAIL(err)
++
++        /* Write "byteCnt" bytes of data to registers */
++        err = setHwRegisters(pDis,
++                             E_REG_P11_ACP_PB0_RW,
++                             &pPkt->dataByte[0],
++                             (UInt16)byteCnt);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Write the ACP packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_FLAGS_RW,
++                             E_MASKREG_P11_DIP_FLAGS_acp,
++                             (UInt8)bEnable);
++    return err;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetAudioInfoframe                                            */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PktSetAudioInfoframe
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPktAif_t *pPkt,
++    Bool                bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    UInt8               buf[9]; /* Temp buffer to hold header/packet bytes */
++    UInt16              bufReg; /* Base register used for writing InfoFrame*/
++    UInt16              flagReg;/* Flag register to be used */
++    UInt8               flagMask;/* Mask used for writing flag register */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameter(s) - NULL pointer allowed */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++    if(pPkt != Null)
++    {
++        /* Pointer to structure provided so check parameters */
++        RETIF_BADPARAM(pPkt->CodingType   > 0x0F)
++        RETIF_BADPARAM(pPkt->ChannelCount > 0x07)
++        RETIF_BADPARAM(pPkt->SampleFreq   > 0x07)
++        RETIF_BADPARAM(pPkt->SampleSize   > 0x03)
++        /* No need to check ChannelAlloc - all values are allowed */
++        RETIF_BADPARAM((pPkt->DownMixInhibit != True) &&
++              (pPkt->DownMixInhibit != False))
++        RETIF_BADPARAM(pPkt->LevelShift   > 0x0F)
++    }
++
++    /* Only supported for device N4 or later */ 
++
++    /* We're using n4 or later, use IF4 buffer for Audio InfoFrame */
++    bufReg = E_REG_P10_IF4_HB0_RW; 
++    flagReg = E_REG_P11_DIP_IF_FLAGS_RW;
++    flagMask = E_MASKREG_P11_DIP_IF_FLAGS_if4;
++
++    if(pPkt != Null)
++    {
++        /* Data to change, start by clearing AIF packet insertion flag */
++        err = setHwRegisterField(pDis, 
++                                 flagReg,
++                                 flagMask,
++                                 0x00);
++        RETIF_REG_FAIL(err)
++
++        /* Prepare AIF header */
++        buf[0] = 0x84;     /* Audio InfoFrame */
++        buf[1] = 0x01;     /* Version 1 [HDMI 1.2] */
++        buf[2] = 0x0A;     /* Length [HDMI 1.2] */
++
++        /* Prepare AIF packet (byte numbers offset by 3) */
++        buf[0+3] = 0;     /* Preset checksum to zero so calculation works! */
++        buf[1+3] = ((pPkt->CodingType & 0x0F) << 4) |
++                     (pPkt->ChannelCount & 0x07);        /* CT3-0, CC2-0 */
++        buf[2+3] = ((pPkt->SampleFreq & 0x07) << 2) |
++                     (pPkt->SampleSize & 0x03);          /* SF2-0, SS1-0 */
++        buf[3+3] = 0;                                      /* [HDMI 1.2] */
++        buf[4+3] = pPkt->ChannelAlloc;                  /* CA7-0 */
++        buf[5+3] = ((pPkt->LevelShift & 0x0F) << 3);    /* LS3-0 */
++        if(pPkt->DownMixInhibit == True)
++        {
++            buf[5+3] += 0x80;                              /* DMI bit */
++        }
++
++        /* Calculate checksum - this is worked out on "Length" bytes of the
++         * packet, the checksum (which we've preset to zero), and the three
++         * header bytes.  We exclude bytes PB6 to PB10 (which we
++         * are not writing) since they are zero.
++         */
++        buf[0+3] = calculateChecksum(&buf[0], 0x0A+1+3-5);
++
++        /* Write header and packet bytes in one operation */
++        err = setHwRegisters(pDis,
++                             bufReg,
++                             &buf[0],
++                             9);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Write AIF packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             flagReg,
++                             flagMask,
++                             (UInt8)bEnable);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetGeneralCntrl                                              */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989PktSetGeneralCntrl
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxaMute_t  *paMute,
++    Bool                bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameter(s) - NULL pointer allowed */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++
++    if(paMute != Null)
++    {
++        RETIF_BADPARAM((*paMute != HDMITX_AMUTE_OFF) && (*paMute != HDMITX_AMUTE_ON))
++
++        if (*paMute == HDMITX_AMUTE_ON)
++        {
++            err = setHwRegister(pDis, E_REG_P11_GC_AVMUTE_RW, 0x02);
++            RETIF_REG_FAIL(err)
++        }
++        else
++        {
++            err = setHwRegister(pDis, E_REG_P11_GC_AVMUTE_RW, 0x01);
++            RETIF_REG_FAIL(err)
++        }
++    }
++
++    /* Set or clear GC packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_FLAGS_RW,
++                             E_MASKREG_P11_DIP_FLAGS_gc,
++                             (UInt8)bEnable);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetIsrc1                                                     */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PktSetIsrc1
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPkt_t    *pPkt,
++    UInt                byteCnt,
++    Bool                bIsrcCont,
++    Bool                bIsrcValid,
++    UInt8               uIsrcStatus,
++    Bool                bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    UInt8               buf[3]; /* Temp buffer to hold header bytes */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Only supported for device N4 or later */ 
++
++    /* Check remaining parameter(s) - NULL pointer allowed */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++
++    if(pPkt != Null)
++    {
++        /* Pointer to structure provided so check parameters */
++        RETIF_BADPARAM((bIsrcCont != True) && (bIsrcCont != False))
++        RETIF_BADPARAM((bIsrcValid != True) && (bIsrcValid != False))
++        RETIF_BADPARAM(uIsrcStatus > 7)    /* 3 bits */
++        RETIF_BADPARAM(byteCnt > HDMITX_PKT_DATA_BYTE_CNT)
++        RETIF(byteCnt == 0, TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++
++        /* Data to change, start by clearing ISRC1 packet insertion flag */
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P11_DIP_FLAGS_RW,
++                                 E_MASKREG_P11_DIP_FLAGS_isrc1,
++                                 0x00);
++        RETIF_REG_FAIL(err)
++
++        /* Prepare ISRC1 header */
++        buf[0] = 0x05;      /* ISRC1 packet */
++        buf[1] = (uIsrcStatus & 0x07);
++        if(bIsrcValid == True)
++        {
++            buf[1] += 0x40;
++        }
++        if(bIsrcCont == True)
++        {
++            buf[1] += 0x80;
++        }
++        buf[2] = 0;         /* Reserved [HDMI 1.2] */
++
++        /* Write 3 header bytes to registers */
++        err = setHwRegisters(pDis,
++                             E_REG_P11_ISRC1_HB0_RW,
++                             &buf[0],
++                             3);
++        RETIF_REG_FAIL(err)
++
++        /* Write "byteCnt" bytes of data to registers */
++        err = setHwRegisters(pDis,
++                             E_REG_P11_ISRC1_PB0_RW,
++                             &pPkt->dataByte[0],
++                             (UInt16)byteCnt);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Write the ISRC1 packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_FLAGS_RW,
++                             E_MASKREG_P11_DIP_FLAGS_isrc1,
++                             (UInt8)bEnable);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetIsrc2                                                     */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PktSetIsrc2
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPkt_t    *pPkt,
++    UInt                byteCnt,
++    Bool                bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    UInt8               buf[3]; /* Temp buffer to hold header bytes */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Only supported for device N4 or later */ 
++
++    /* Check remaining parameter(s) - NULL pointer allowed */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++
++    if(pPkt != Null)
++    {
++        /* Pointer to structure provided so check parameters */
++        RETIF_BADPARAM(byteCnt > HDMITX_PKT_DATA_BYTE_CNT)
++        RETIF(byteCnt == 0, TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++
++        /* Data to change, start by clearing ISRC2 packet insertion flag */
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P11_DIP_FLAGS_RW,
++                                 E_MASKREG_P11_DIP_FLAGS_isrc2,
++                                 0x00);
++        RETIF_REG_FAIL(err)
++
++        /* Prepare ISRC2 header */
++        buf[0] = 0x06;      /* ISRC2 packet */
++        buf[1] = 0;         /* Reserved [HDMI 1.2] */
++        buf[2] = 0;         /* Reserved [HDMI 1.2] */
++
++        /* Write 3 header bytes to registers */
++        err = setHwRegisters(pDis,
++                             E_REG_P11_ISRC2_HB0_RW,
++                             &buf[0],
++                             3);
++        RETIF_REG_FAIL(err)
++
++        /* Write "byteCnt" bytes of data to registers */
++        err = setHwRegisters(pDis,
++                             E_REG_P11_ISRC2_PB0_RW,
++                             &pPkt->dataByte[0],
++                             (UInt16)byteCnt);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Write the ISRC2 packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_FLAGS_RW,
++                             E_MASKREG_P11_DIP_FLAGS_isrc2,
++                             (UInt8)bEnable);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetMpegInfoframe                                             */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PktSetMpegInfoframe
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxPktMpeg_t    *pPkt,
++    Bool                    bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    UInt8               buf[9]; /* Temp buffer to hold packet */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Only supported for device N4 or later */ 
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++
++    if(pPkt != Null)
++    {
++        /* Pointer to structure provided so check parameters */
++        RETIF_BADPARAM((pPkt->bFieldRepeat != True) && (pPkt->bFieldRepeat != False))
++        RETIF_BADPARAM(pPkt->frameType >= HDMITX_MPEG_FRAME_INVALID)
++
++        /* Data to change, start by clearing MPEG packet insertion flag */
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P11_DIP_IF_FLAGS_RW,
++                                 E_MASKREG_P11_DIP_IF_FLAGS_if5,
++                                 0x00);
++        RETIF_REG_FAIL(err)
++
++        /* Prepare MPEG header */
++        buf[0] = 0x85;      /* MPEG Source InfoFrame */
++        buf[1] = 0x01;      /* Version 1 [HDMI 1.2] */
++        buf[2] = 0x0A;      /* Length [HDMI 1.2] */
++
++        /* Prepare MPEG packet (byte numbers offset by 3) */
++        buf[0+3] = 0;     /* Preset checksum to zero so calculation works! */
++        buf[1+3] = (UInt8)(pPkt->bitRate & 0x000000FF);
++        buf[2+3] = (UInt8)((pPkt->bitRate & 0x0000FF00) >> 8);
++        buf[3+3] = (UInt8)((pPkt->bitRate & 0x00FF0000) >> 16);
++        buf[4+3] = (UInt8)((pPkt->bitRate & 0xFF000000) >> 24);
++        buf[5+3] = pPkt->frameType;                         /* MF1-0 */
++        if(pPkt->bFieldRepeat == True)
++        {
++            buf[5+3] += 0x10;                               /* FR0 bit */
++        }
++
++        /* Calculate checksum - this is worked out on "Length" bytes of the
++         * packet, the checksum (which we've preset to zero), and the three
++         * header bytes.  We exclude bytes PB6 to PB10 (which we
++         * are not writing) since they are zero.
++         */
++        buf[0+3] = calculateChecksum(&buf[0], 0x0A+1+3-5);
++
++        /* Write header and packet bytes in one operation */
++        err = setHwRegisters(pDis,
++                             E_REG_P10_IF5_HB0_RW,
++                             &buf[0],
++                             9);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Write the MPEG packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_IF_FLAGS_RW,
++                             E_MASKREG_P11_DIP_IF_FLAGS_if5,
++                             (UInt8)bEnable);
++    return err;
++}
++/*============================================================================*/
++/* tmbslTDA9989PktSetNullInsert                                                */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PktSetNullInsert
++(
++    tmUnitSelect_t  txUnit,
++    Bool            bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++
++    /* Set or clear FORCE_NULL packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_FLAGS_RW,
++                             E_MASKREG_P11_DIP_FLAGS_force_null,
++                             (UInt8)bEnable);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetNullSingle                                                */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PktSetNullSingle
++(
++    tmUnitSelect_t  txUnit
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Set NULL packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_FLAGS_RW,
++                             E_MASKREG_P11_DIP_FLAGS_null,
++                             0x01);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetSpdInfoframe                                              */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PktSetSpdInfoframe
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPktSpd_t *pPkt,
++    Bool                bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    UInt8               buf[29];/* Temp buffer to hold packet */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Only supported for device N4 or later */ 
++
++    /* Check remaining parameter(s) */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++
++    if(pPkt != Null)
++    {
++        /* Pointer to structure provided so check parameters */
++        RETIF_BADPARAM(pPkt->SourceDevInfo >= HDMITX_SPD_INFO_INVALID)
++
++        /* Data to change, start by clearing SPD packet insertion flag */
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P11_DIP_IF_FLAGS_RW,
++                                 E_MASKREG_P11_DIP_IF_FLAGS_if3,
++                                 0x00);
++        RETIF_REG_FAIL(err)
++
++        /* Prepare SPD header */
++        buf[0] = 0x83;      /* Source. Product Descriptor InfoFrame */
++        buf[1] = 0x01;      /* Version 1 [CEA 861B] */
++        buf[2] = 0x19;      /* Length [HDMI 1.2] */
++
++        /* Prepare SPD packet (byte numbers offset by 3) */
++        buf[0+3] = 0;     /* Preset checksum to zero so calculation works! */
++        lmemcpy(&buf[1+3], &pPkt->VendorName[0], HDMI_TX_SPD_VENDOR_SIZE);
++        lmemcpy(&buf[1+3+HDMI_TX_SPD_VENDOR_SIZE], &pPkt->ProdDescr[0],
++               HDMI_TX_SPD_DESCR_SIZE);
++
++
++        buf[HDMI_TX_SPD_LENGTH+3] = pPkt->SourceDevInfo;
++
++        /* Calculate checksum - this is worked out on "Length" bytes of the
++         * packet, the checksum (which we've preset to zero), and the three
++         * header bytes.  
++         */
++        buf[0+3] = calculateChecksum(&buf[0], HDMI_TX_SPD_LENGTH+1+3);
++
++        /* Write header and packet bytes in one operation */
++        err = setHwRegisters(pDis,
++                             E_REG_P10_IF3_HB0_RW,
++                             &buf[0],
++                             29);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Write the SPD packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_IF_FLAGS_RW,
++                             E_MASKREG_P11_DIP_IF_FLAGS_if3,
++                             (UInt8)bEnable);
++    return err;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetVideoInfoframe                                            */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PktSetVideoInfoframe
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPktVif_t *pPkt,
++    Bool                bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    UInt8               buf[17];/* Temp buffer to hold header/packet bytes */
++    UInt16              bufReg; /* Base register used for writing InfoFrame*/
++    UInt16              flagReg;/* Flag register to be used */
++    UInt8               flagMask;/* Mask used for writing flag register */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameter(s) - NULL pointer allowed */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++    if(pPkt != Null)
++    {
++        /* Pointer to structure provided so check parameters */
++        RETIF_BADPARAM(pPkt->Colour             > 0x03)
++        RETIF_BADPARAM((pPkt->ActiveInfo != True) && (pPkt->ActiveInfo != False))
++        RETIF_BADPARAM(pPkt->BarInfo            > 0x03)
++        RETIF_BADPARAM(pPkt->ScanInfo           > 0x03)
++        RETIF_BADPARAM(pPkt->Colorimetry        > 0x03)
++        RETIF_BADPARAM(pPkt->PictureAspectRatio > 0x03)
++        RETIF_BADPARAM(pPkt->ActiveFormatRatio  > 0x0F)
++        RETIF_BADPARAM(pPkt->Scaling            > 0x03)
++        RETIF_BADPARAM(pPkt->VidFormat          > 0x7F)
++        RETIF_BADPARAM(pPkt->PixelRepeat        > 0x0F)
++    }
++
++    /* Only supported for device N4 or later */ 
++
++    /* We're using n4 or later, use IF2 buffer for Video InfoFrame */
++    bufReg = E_REG_P10_IF2_HB0_RW; 
++    flagReg = E_REG_P11_DIP_IF_FLAGS_RW;
++    flagMask = E_MASKREG_P11_DIP_IF_FLAGS_if2;
++
++    if(pPkt != Null)
++    {
++        /* Data to change, start by clearing VIF packet insertion flag */
++        err = setHwRegisterField(pDis, 
++                                 flagReg,
++                                 flagMask,
++                                 0x00);
++        RETIF_REG_FAIL(err)
++
++        /* Prepare VIF header */
++        buf[0] = 0x82;     /* Video InfoFrame */
++        buf[1] = 0x02;     /* Version 2 [HDMI 1.2] */
++        buf[2] = 0x0D;     /* Length [HDMI 1.2] */
++
++        /* Prepare VIF packet (byte numbers offset by 3) */
++        buf[0+3] = 0;     /* Preset checksum to zero so calculation works! */
++        buf[1+3] = ((pPkt->Colour & 0x03) << 5) |       /* Y1-0, B1-0,S1-0 */
++                    ((pPkt->BarInfo & 0x03) << 2) |
++                     (pPkt->ScanInfo & 0x03);
++        if(pPkt->ActiveInfo == True)
++        {
++            buf[1+3] += 0x10;                              /* AI bit */
++        }
++        buf[2+3] = ((pPkt->Colorimetry & 0x03) << 6) |  /* C1-0, M1-0, R3-0 */
++                    ((pPkt->PictureAspectRatio & 0x03) << 4) |
++                     (pPkt->ActiveFormatRatio & 0x0F);
++        buf[3+3] = (pPkt->Scaling & 0x03);              /* SC1-0 */                                    /* [HDMI 1.2] */
++        buf[4+3] = (pPkt->VidFormat & 0x7F);            /* VIC6-0 */
++        buf[5+3] = (pPkt->PixelRepeat & 0x0F);          /* PR3-0 */
++        buf[6+3] = (UInt8)(pPkt->EndTopBarLine & 0x00FF);
++        buf[7+3] = (UInt8)((pPkt->EndTopBarLine & 0xFF00) >> 8);
++        buf[8+3] = (UInt8)(pPkt->StartBottomBarLine & 0x00FF);
++        buf[9+3] = (UInt8)((pPkt->StartBottomBarLine & 0xFF00) >> 8);
++        buf[10+3] = (UInt8)(pPkt->EndLeftBarPixel & 0x00FF);
++        buf[11+3] = (UInt8)((pPkt->EndLeftBarPixel & 0xFF00) >> 8);
++        buf[12+3] = (UInt8)(pPkt->StartRightBarPixel & 0x00FF);
++        buf[13+3] = (UInt8)((pPkt->StartRightBarPixel & 0xFF00) >> 8);
++
++        /* Calculate checksum - this is worked out on "Length" bytes of the
++         * packet, the checksum (which we've preset to zero), and the three
++         * header bytes.
++         */
++        buf[0+3] = calculateChecksum(&buf[0], 0x0D+1+3);
++
++        /* Write header and packet bytes in one operation */
++        err = setHwRegisters(pDis,
++                             bufReg,
++                             &buf[0],
++                             17);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Write VIF packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             flagReg,
++                             flagMask,
++                             (UInt8)bEnable);
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetRawVideoInfoframe                                       */
++/*============================================================================*/
++tmErrorCode_t tmbslTDA9989PktSetRawVideoInfoframe
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxPktRawAvi_t *pPkt,
++    Bool                    bEnable
++)
++{
++
++
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Check remaining parameter(s) - NULL pointer allowed */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++    
++    /* use IF2 buffer */
++    if(pPkt != Null)
++    {
++        /* Data to change, start by clearing VIF packet insertion flag */
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P11_DIP_IF_FLAGS_RW,
++                                 E_MASKREG_P11_DIP_IF_FLAGS_if2,
++                                 0x00);
++        RETIF_REG_FAIL(err)
++
++
++        /* Write VIF raw header bytes 0-2 */
++        err = setHwRegisters(pDis,
++                             E_REG_P10_IF2_HB0_RW,
++                             pPkt->HB,
++                             3);
++        RETIF_REG_FAIL(err)
++
++        /* Write VIF raw payload bytes 0-27 */
++        err = setHwRegisters(pDis,
++                             E_REG_P10_IF2_PB0_RW,
++                             pPkt->PB,
++                             28);
++
++        RETIF_REG_FAIL(err)
++
++    }
++
++    /* Write VIF packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_IF_FLAGS_RW,
++                             E_MASKREG_P11_DIP_IF_FLAGS_if2,
++                             (UInt8)bEnable);
++    
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PktSetVsInfoframe                                               */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989PktSetVsInfoframe
++(
++    tmUnitSelect_t      txUnit,
++    tmbslHdmiTxPkt_t    *pPkt,
++    UInt                byteCnt,
++    UInt8               uVersion,
++    Bool                bEnable
++)
++{
++    tmHdmiTxobject_t    *pDis;  /* Pointer to Device Instance Structure */
++    tmErrorCode_t       err;    /* Error code */
++    UInt8               buf[31];/* Temp buffer to hold packet */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED error if the 
++     * sinkType is not HDMI
++     */ 
++    RETIF(pDis->sinkType != HDMITX_SINK_HDMI,
++          TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++
++    /* Only supported for device N4 or later */ 
++
++    /* Check remaining parameter(s) - NULL pointer allowed */
++    RETIF_BADPARAM((bEnable != True) && (bEnable != False))
++
++    if(pPkt != Null)
++    {
++        /* Pointer to structure provided so check parameters */
++        /* InfoFrame needs a checksum, so 1 usable byte less than full pkt */
++        RETIF_BADPARAM(byteCnt > (HDMITX_PKT_DATA_BYTE_CNT-1))
++        RETIF(byteCnt == 0, TMBSL_ERR_HDMI_INCONSISTENT_PARAMS)
++
++        /* Data to change, start by clearing VS_IF packet insertion flag */
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P11_DIP_IF_FLAGS_RW,
++                                 E_MASKREG_P11_DIP_IF_FLAGS_if1,
++                                 0x00);
++        RETIF_REG_FAIL(err)
++
++        /* Prepare VS_IF header */
++        lmemset(&buf[0], 0, 31); /* Clear buffer as user may vary length used */
++        buf[0] = 0x81;          /* Vendor Specific InfoFrame */
++        buf[1] = uVersion;      /* Vendor defined version */
++        buf[2] = (UInt8)byteCnt;       /* Length [HDMI 1.2] */
++
++        /* Prepare VS_IF packet (byte numbers offset by 3) */
++        buf[0+3] = 0;     /* Preset checksum to zero so calculation works! */
++        lmemcpy(&buf[1+3], &pPkt->dataByte[0], byteCnt);
++
++        /* Calculate checksum - this is worked out on "Length" bytes of the
++         * packet, the checksum (which we've preset to zero), and the three
++         * header bytes.  
++         */
++        buf[0+3] = calculateChecksum(&buf[0], byteCnt+1+3);
++
++        /* Write header and packet bytes in one operation  - write entire 
++         * buffer even though we may not be using it all so that zeros
++         * are placed in the unused registers. */
++        err = setHwRegisters(pDis,
++                             E_REG_P10_IF1_HB0_RW,
++                             &buf[0],
++                             31);
++        RETIF_REG_FAIL(err)
++    }
++
++    /* Write the VS_IF packet insertion flag */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P11_DIP_IF_FLAGS_RW,
++                             E_MASKREG_P11_DIP_IF_FLAGS_if1,
++                             (UInt8)bEnable);
++    return err;
++}
++
++/*============================================================================*/
++/*                              STATIC FUNCTIONS                              */
++/*============================================================================*/
++
++/*===============================================================================*/
++/* reg_vid_fmt(): get register index for normal and 3D, plus sync table          */
++/*===============================================================================*/
++static UInt8 reg_vid_fmt(tmbslHdmiTxVidFmt_t fmt,              \
++                         tmbslHdmiTx3DStructure_t structure3D, \
++                         UInt8 *idx,                           \
++                         UInt8 *idx3d,                         \
++                         struct sync_desc **sync)
++{
++   struct vic2reg *hash;
++   int i;
++
++   (*idx)=REGVFMT_INVALID;
++   if (idx3d) (*idx3d)=REGVFMT_INVALID;
++   if (IS_TV(fmt)) {
++      VIC2REG_LOOP(vic2reg_TV,idx);
++      if (idx3d) {
++         if (structure3D == HDMITX_3D_FRAME_PACKING) {
++            /* any 3D FP prefetch ? */
++            VIC2REG_LOOP(vic2reg_TV_FP,idx3d);
++         }
++      }
++   }
++#ifdef FORMAT_PC
++   else {
++      VIC2REG_LOOP(vic2reg_PC,idx);
++   }
++#endif
++   /* PR1570 FIXED */
++   if (sync) {
++	   if PREFETCH(*idx) {
++		   *sync = (struct sync_desc *)ref_sync;
++	   }
++#ifdef FORMAT_PC 	   
++	   else if PCFORMAT(*idx) {
++		   *sync = (struct sync_desc *)ref_sync_PC;
++		   *idx = *idx - E_REGVFMT_MAX_EXTRA;
++	   }
++#endif //FORMAT_PC
++	   else {
++		   *sync = (struct sync_desc *)ref_sync_extra;
++	   }
++   }
++   return ((*idx)==REGVFMT_INVALID);
++}
++
++/*===============================================================================*/
++/* pix_clk(): get pixel clock                                                    */
++/*===============================================================================*/
++UInt8 pix_clk(tmbslHdmiTxVidFmt_t fmt, tmbslHdmiTxVfreq_t freq, UInt8 *pclk)
++{
++
++   (*pclk)=REGVFMT_INVALID;
++#ifdef FORMAT_PC
++   if (IS_PC(fmt)) {
++      (*pclk)=kVfmtToPixClk_PC[fmt - HDMITX_VFMT_PC_MIN];
++   }
++#endif
++   if (IS_TV(fmt)) {
++      (*pclk)=kVfmtToPixClk_TV[fmt - HDMITX_VFMT_TV_MIN][freq];
++   }
++   return ((*pclk)==REGVFMT_INVALID);
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(pix_clk);
++#endif
++
++/*===============================================================================*/
++/* calculateVidFmtIndex(): Calculate table index according to video format value */
++/*===============================================================================*/
++tmbslHdmiTxVidFmt_t calculateVidFmtIndex(tmbslHdmiTxVidFmt_t vidFmt)
++{
++    tmbslHdmiTxVidFmt_t vidFmtIndex = vidFmt;
++    
++    /* Hanlde VIC or table index discontinuity */
++    if((vidFmt >= HDMITX_VFMT_60_1280x720p_24Hz) && (vidFmt <= HDMITX_VFMT_62_1280x720p_30Hz))
++    {
++        vidFmtIndex = (tmbslHdmiTxVidFmt_t)(HDMITX_VFMT_INDEX_60_1280x720p_24Hz + (vidFmt - HDMITX_VFMT_60_1280x720p_24Hz));
++    }
++#ifdef FORMAT_PC
++    else if (IS_PC(vidFmt))
++    {
++        vidFmtIndex = (tmbslHdmiTxVidFmt_t)(HDMITX_VFMT_TV_NUM + (vidFmt - HDMITX_VFMT_PC_MIN));
++    }
++#endif /* FORMAT_PC */
++    return(vidFmtIndex);
++}
++
++/*============================================================================*/
++/* setDeVs                                                                    */
++/*============================================================================*/
++static tmErrorCode_t
++setDeVs
++(
++    tmHdmiTxobject_t    *pDis,
++    tmbslHdmiTxVidFmt_t  voutFmt,
++    tmbslHdmiTx3DStructure_t structure3D
++)
++{
++    tmErrorCode_t   err;        /* Error code */
++    UInt16          vsPixStrt2; /* VS pixel number for start pulse in field 2 */
++    UInt8           reg_idx;    /* Video format value used for register */
++    struct sync_desc *sync;
++
++    /* IF voutFmt = No Change THEN return TM_OK */
++    RETIF(voutFmt == HDMITX_VFMT_NO_CHANGE, TM_OK);
++
++    /* Quit if the output format does not map to the register format */
++    RETIF_BADPARAM(reg_vid_fmt(voutFmt,structure3D,&reg_idx,0,&sync));
++
++    /* DE_START & DE_STOP no longer set because N2 device no longer supported */
++
++    /* Adjust VS_PIX_STRT_2 and VS_PIX_END_2 for interlaced output formats */
++    vsPixStrt2 = sync[BASE(reg_idx)].Vs2;
++    err = setHwRegisterMsbLsb(pDis, E_REG_P00_VS_PIX_STRT_2_MSB_W, vsPixStrt2);
++    RETIF_REG_FAIL(err)
++    err = setHwRegisterMsbLsb(pDis, E_REG_P00_VS_PIX_END_2_MSB_W, vsPixStrt2);
++/*     printk("DBG %s vs2:%d\n",__func__,vsPixStrt2); */
++
++    return err;
++}
++
++/*============================================================================*/
++/* setPixelRepeat                                                             */
++/*============================================================================*/
++static tmErrorCode_t
++setPixelRepeat
++(
++    tmHdmiTxobject_t    *pDis,
++    tmbslHdmiTxVidFmt_t voutFmt,
++    UInt8               uPixelRepeat,
++    tmbslHdmiTx3DStructure_t structure3D
++)
++{
++    tmErrorCode_t err = TM_OK;  /* Error code */
++
++    RETIF(voutFmt == HDMITX_VFMT_NO_CHANGE, TM_OK)
++
++    err = InputConfig(pDis,
++                      HDMITX_VINMODE_NO_CHANGE,
++                      HDMITX_PIXEDGE_NO_CHANGE,
++                      HDMITX_PIXRATE_NO_CHANGE,
++                      HDMITX_UPSAMPLE_NO_CHANGE, 
++                      uPixelRepeat,
++                      voutFmt,
++                      structure3D);
++
++   return err;
++}
++/*============================================================================*/
++/* setSampling                                                                */
++/*============================================================================*/
++static tmErrorCode_t
++setSampling
++(
++ tmHdmiTxobject_t   *pDis
++)
++{
++    tmErrorCode_t err;          /* Error code */
++    UInt8         upSample;     /* 1 if upsampler must be enabled */
++    UInt8         downSample;   /* 1 if downsampler must be enabled */
++    UInt8         matrixBypass; /*>0 if matrix has been bypassed */
++
++    if ((pDis->vinMode == HDMITX_VINMODE_YUV422)
++    ||  (pDis->vinMode == HDMITX_VINMODE_CCIR656))
++    {
++        if (pDis->voutMode == HDMITX_VOUTMODE_YUV422)
++        {
++            /* Input 422/656, output 422 */
++            err = getHwRegister(pDis, E_REG_P00_MAT_CONTRL_W, &matrixBypass);
++            RETIF_REG_FAIL(err)
++            matrixBypass &= E_MASKREG_P00_MAT_CONTRL_mat_bp;
++            /* Has matrix been bypassed? */
++            if (matrixBypass > 0)
++            {
++                upSample = 0;
++                downSample = 0;
++            }
++            else
++            {
++                upSample = 1;
++                downSample = 1;
++            }
++        }
++        else
++        {
++            /* Input 422/656, output not 422 */
++            upSample = 1;
++            downSample = 0;
++        }
++    }
++    else
++    {
++        if (pDis->voutMode == HDMITX_VOUTMODE_YUV422)
++        {
++            /* Input not 422/656, output 422 */
++            upSample = 0;
++            downSample = 1;
++        }
++        else
++        {
++            /* Input not 422/656, output not 422 */
++            upSample = 0;
++            downSample = 0;
++        }
++    }
++
++    /* Check upsample mode saved by tmbslTDA9989VideoInSetConfig */
++    if (pDis->upsampleMode != HDMITX_UPSAMPLE_AUTO)
++    {
++        /* Saved upsample mode overrides local one */
++        upSample = pDis->upsampleMode;
++    }
++
++    /* Set upsampler */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P00_HVF_CNTRL_0_W, 
++                             E_MASKREG_P00_HVF_CNTRL_0_intpol,
++                             upSample);
++    RETIF_REG_FAIL(err)
++
++    /* Set downsampler */
++    err = setHwRegisterField(pDis, 
++                             E_REG_P00_HVF_CNTRL_1_W, 
++                             E_MASKREG_P00_HVF_CNTRL_1_for,
++                             downSample);
++    return err;
++}
++
++
++/*============================================================================*/
++/* calculateChecksum - returns the byte needed to yield a checksum of zero    */
++/*============================================================================*/
++static UInt8
++calculateChecksum
++(   
++    UInt8       *pData,     /* Pointer to checksum data */
++    Int         numBytes    /* Number of bytes over which to calculate */
++    )
++{
++    UInt8       checksum = 0;   /* Working checksum calculation */
++    UInt8       result = 0;     /* Value to be returned */
++    Int         i;
++
++    if((pData != Null) && (numBytes > 0))
++    {
++        for (i = 0; i < numBytes; i++)
++        {
++            checksum = checksum + (*(pData + i));
++        }
++        result = (255 - checksum) + 1;
++    }
++    return result;          /* returns 0 in the case of null ptr or 0 bytes */
++}
++
++/*============================================================================*/
++/* InputConfig                                                                */
++/*============================================================================*/
++static tmErrorCode_t
++InputConfig
++(
++    tmHdmiTxobject_t           *pDis,
++    tmbslHdmiTxVinMode_t       vinMode,
++    tmbslHdmiTxPixEdge_t       sampleEdge,
++    tmbslHdmiTxPixRate_t       pixRate,
++    tmbslHdmiTxUpsampleMode_t  upsampleMode, 
++    UInt8                      uPixelRepeat,
++    tmbslHdmiTxVidFmt_t        voutFmt,
++    tmbslHdmiTx3DStructure_t structure3D
++)
++{
++    tmErrorCode_t err = TM_OK;  /* Error code */
++    UInt8         reg_idx,reg_idx3D;      /* Video format value used for register */
++    UInt8         ssd=0;          /* Packed srl, scg and de */
++    struct sync_desc *sync;
++
++    /****************Check Parameters********************/
++    /* Check parameters */
++    RETIF_BADPARAM(vinMode      >= HDMITX_VINMODE_INVALID);
++    RETIF_BADPARAM(sampleEdge   >= HDMITX_PIXEDGE_INVALID);
++    RETIF_BADPARAM(pixRate      >= HDMITX_PIXRATE_INVALID);
++    RETIF_BADPARAM(upsampleMode >= HDMITX_UPSAMPLE_INVALID);
++
++    RETIF(voutFmt == HDMITX_VFMT_NO_CHANGE, TM_OK);
++    RETIF_BADPARAM(!IS_VALID_FMT(voutFmt));
++
++    /* Quit if the output format does not map to the register format */
++    RETIF_BADPARAM(reg_vid_fmt(voutFmt,structure3D,&reg_idx,&reg_idx3D,&sync));
++
++/****************Set the VinMode************************
++- P00_VIP_CNTRL_4_ccir656
++- P00_HVF_CNTRL_1_semi_planar
++- P02_PLL_SERIAL_3_srl_ccir
++- P02_SEL_CLK_sel_vrf_clk
++*/
++    if (vinMode != HDMITX_VINMODE_NO_CHANGE)
++    {
++        pDis->vinMode = vinMode;
++    }
++/****************Set the sampleEdge***********************
++-P00_VIP_CNTRL_3_edge*/
++
++    if (sampleEdge != HDMITX_PIXEDGE_NO_CHANGE)
++    {
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_VIP_CNTRL_3_W,
++                                 E_MASKREG_P00_VIP_CNTRL_3_edge,
++                                 (UInt8)sampleEdge);
++        RETIF_REG_FAIL(err)
++    }
++
++/****************Set the Pixel Rate***********************
++-P02_CCIR_DIV_refdiv2
++-P02_P02_PLL_SCG2_selpllclkin
++-P02_P02_PLL_DE_bypass_pllde
++-P00_VIP_CNTRL_4_656_alt */
++
++    if (pixRate != HDMITX_PIXRATE_NO_CHANGE)
++       {
++          pDis->pixRate = pixRate;
++       }
++    
++    if ((pixRate != HDMITX_PIXRATE_NO_CHANGE)||(vinMode != HDMITX_VINMODE_NO_CHANGE))
++       {
++          switch (pDis->vinMode)
++             {
++             case HDMITX_VINMODE_RGB444:
++             case HDMITX_VINMODE_YUV444:    
++                
++                if (pDis->pixRate == HDMITX_PIXRATE_SINGLE)
++                   {
++                      err = setHwRegisterFieldTable(pDis, &kVinMode444[0]);
++                      
++                      RETIF_REG_FAIL(err)
++                         
++                         
++                         
++                         err = setHwRegisterField(pDis, 
++                                                  E_REG_P00_VIP_CNTRL_4_W,
++                                                  E_MASKREG_P00_VIP_CNTRL_4_656_alt,
++                                                  0);
++                      RETIF_REG_FAIL(err)
++                         
++                         }
++                else if (pDis->pixRate == HDMITX_PIXRATE_SINGLE_REPEATED)
++                   {
++                      err = setHwRegisterFieldTable(pDis, &kVinMode444[0]);
++                      
++                      RETIF_REG_FAIL(err)
++                         
++                         
++                         
++                         err = setHwRegisterField(pDis, 
++                                                  E_REG_P00_VIP_CNTRL_4_W,
++                                                  E_MASKREG_P00_VIP_CNTRL_4_656_alt,
++                                                  0);
++                      RETIF_REG_FAIL(err)
++                         
++                         }
++                else 
++                   {
++                      /* Not supported*/
++                   }
++                break;
++             case HDMITX_VINMODE_YUV422: 
++                if (pDis->pixRate == HDMITX_PIXRATE_SINGLE)
++                   {
++                      err = setHwRegisterFieldTable(pDis, &kVinModeYUV422[0]);
++                      
++                      RETIF_REG_FAIL(err)
++                         
++                         
++                         
++                         err = setHwRegisterField(pDis, 
++                                                  E_REG_P00_VIP_CNTRL_4_W,
++                                                  E_MASKREG_P00_VIP_CNTRL_4_656_alt,
++                                                  0);
++                      RETIF_REG_FAIL(err)
++                         
++                         }
++                else if (pDis->pixRate == HDMITX_PIXRATE_SINGLE_REPEATED)
++                   {
++                      err = setHwRegisterFieldTable(pDis, &kVinModeYUV422[0]);
++                      
++                      RETIF_REG_FAIL(err)
++                         
++                         
++                         
++                         err = setHwRegisterField(pDis, 
++                                                  E_REG_P00_VIP_CNTRL_4_W,
++                                                  E_MASKREG_P00_VIP_CNTRL_4_656_alt,
++                                                  0);
++                      RETIF_REG_FAIL(err)
++                         
++                         }
++                else 
++                   {
++                      /* Not supported*/
++                      return TMBSL_ERR_HDMI_BAD_PARAMETER;
++                   }
++                break;
++             case HDMITX_VINMODE_CCIR656:
++                if(pDis->pixRate == HDMITX_PIXRATE_SINGLE)
++                   {
++                      
++                      err = setHwRegisterFieldTable(pDis, &kVinModeCCIR656[0]);
++                      
++                      RETIF_REG_FAIL(err)
++                         
++                         
++                         
++                         err = setHwRegisterField(pDis, 
++                                                  E_REG_P00_VIP_CNTRL_4_W,
++                                                  E_MASKREG_P00_VIP_CNTRL_4_656_alt,
++                                                  0);
++                      RETIF_REG_FAIL(err)
++                         
++                         }
++                else if (pDis->pixRate == HDMITX_PIXRATE_SINGLE_REPEATED)
++                   {
++                      err = setHwRegisterFieldTable(pDis, &kVinModeCCIR656[0]);
++                      
++                      RETIF_REG_FAIL(err)
++                         
++                         
++                         
++                         err = setHwRegisterField(pDis, 
++                                                  E_REG_P00_VIP_CNTRL_4_W,
++                                                  E_MASKREG_P00_VIP_CNTRL_4_656_alt,
++                                                  0);
++                      RETIF_REG_FAIL(err)
++                         
++                         }
++                else if (pDis->pixRate == HDMITX_PIXRATE_DOUBLE)
++                   {
++                      err = setHwRegisterFieldTable(pDis, &kVinModeCCIR656_DDR_above720p[0]);
++                      
++                      RETIF_REG_FAIL(err)
++                         
++                         
++                         
++                         
++                         err = setHwRegisterField(pDis, 
++                                                  E_REG_P00_VIP_CNTRL_4_W,
++                                                  E_MASKREG_P00_VIP_CNTRL_4_656_alt,
++                                                  1);
++                      RETIF_REG_FAIL(err)
++                         
++                         }
++                break;
++             default:
++                err = setHwRegisterFieldTable(pDis, &kVinMode444[0]);
++                
++                RETIF_REG_FAIL(err)
++                   break;
++             }
++          
++       }
++    /****************Update the Sample Mode***********************/
++    
++    if (upsampleMode != HDMITX_UPSAMPLE_NO_CHANGE) {
++       pDis->upsampleMode = upsampleMode;
++    }
++
++/****************Set the Pixel repeat PLL Value ***********************
++- P02_PLL_SERIAL_2_srl_nosc
++- P02_PLL_DE_pllde_nosc */
++
++    if ((structure3D == HDMITX_3D_FRAME_PACKING) && \
++        (reg_idx3D != REGVFMT_INVALID)) {
++       /* embedded 3D video format */
++       ssd = pll[reg_idx3D];
++    }
++    else {
++       /* embedded 2D video format */
++       ssd = pll[reg_idx];
++    }
++
++    if ( ssd < SSD_UNUSED_VALUE) {
++        err = setHwRegisterField(pDis, E_REG_P02_PLL_SERIAL_2_RW,
++                             E_MASKREG_P02_PLL_SERIAL_2_srl_nosc,
++                             ssd);
++/*         printk("DBG nosc:%d\n",ssd); */
++    }
++
++/*****************Set the Pixel Repetition***********************
++- P02_PLL_SERIAL_2_srl_pr*/
++
++    /* Set pixel repetition */
++    if (uPixelRepeat != HDMITX_PIXREP_NO_CHANGE)
++    {
++        if (uPixelRepeat == HDMITX_PIXREP_DEFAULT)
++        {
++            /* Look up default pixel repeat value for this output format */
++            uPixelRepeat = sync[BASE(reg_idx)].pix_rep;
++        }
++
++        /* Update current pixel repetition count */
++        pDis->pixelRepeatCount = uPixelRepeat;
++
++        err = setHwRegisterField(pDis, 
++                                 E_REG_P02_PLL_SERIAL_2_RW, 
++                                 E_MASKREG_P02_PLL_SERIAL_2_srl_pr,
++                                 uPixelRepeat);
++        RETIF_REG_FAIL(err)
++        /* Set pixel repetition count for Repetitor module */
++        err = setHwRegister(pDis, E_REG_P00_RPT_CNTRL_W, uPixelRepeat);
++    }
++
++/*******************Fixe other settings*********************
++- P02_PLL_SERIAL_1_srl_man_iz     = 0
++- P02_PLL_SERIAL_3_srl_de         = 0
++- Pol Clk Sel = P02_SERIALIZER_RW = 0
++- P02_BUFFER_OUT_srl_force        = 0 
++- P02_BUFFER_OUT_srl_clk          = 0
++- P02_PLL_DE_pllde_iz             = 0
++*/
++
++    err = setHwRegisterField(pDis, 
++                            E_REG_P02_PLL_SERIAL_1_RW, 
++                            E_MASKREG_P02_PLL_SERIAL_1_srl_man_iz,
++                            0);
++
++
++RETIF_REG_FAIL(err)
++
++   err = setHwRegisterField(pDis, 
++                            E_REG_P02_PLL_SERIAL_3_RW, 
++                            E_MASKREG_P02_PLL_SERIAL_3_srl_de,
++                            0);
++RETIF_REG_FAIL(err)
++
++err = setHwRegister(pDis, E_REG_P02_SERIALIZER_RW, 0);
++RETIF_REG_FAIL(err)
++
++return err;
++}
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_InOut_l.h b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_InOut_l.h
+new file mode 100755
+index 0000000..343e41b
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_InOut_l.h
+@@ -0,0 +1,112 @@
++/**
++ * Copyright (C) 2009 Koninklijke Philips Electronics N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of Koninklijke Philips Electronics N.V. and is confidential in
++ * nature. Under no circumstances is this software to be  exposed to or placed
++ * under an Open Source License of any type without the expressed written
++ * permission of Koninklijke Philips Electronics N.V.
++ *
++ * \file          tmbslTDA9989_InOut_l.h
++ *
++ * \version       $Revision: 2 $
++ *
++ *
++*/
++
++#ifndef TMBSLTDA9989_INOUT_L_H
++#define TMBSLTDA9989_INOUT_L_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       MACRO DEFINITIONS                                    */
++/*============================================================================*/
++
++#define IS_TV(fmt) (fmt >= HDMITX_VFMT_TV_MIN && fmt <= HDMITX_VFMT_TV_MAX)
++#define IS_VALID_FMT(fmt) IS_TV(fmt)
++#ifdef FORMAT_PC
++#define IS_PC(fmt) (fmt >= HDMITX_VFMT_PC_MIN && fmt <= HDMITX_VFMT_PC_MAX)
++#define IS_VALID_FMT(fmt) (IS_TV(fmt)||IS_PC(fmt))
++#endif
++#define VIC2REG_LOOP(array,idx) do {                           \
++   hash=(struct vic2reg *)(array);                         \
++   for (i=0;i<(sizeof(array)/sizeof(struct vic2reg));i++) { \
++      if (hash[i].vic==fmt) {                              \
++         (*idx)=hash[i].reg;                               \
++         break;                                            \
++      }                                                    \
++   }                                                       \
++} while (0);
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++typedef struct 
++{
++    UInt16 Register;
++    UInt8  MaskSwap;
++    UInt8  MaskMirror;
++} tmbslTDA9989RegVip;
++
++/*============================================================================*/
++/*                       EXTERN DATA DEFINITION                               */
++/*============================================================================*/
++
++extern CONST_DAT tmHdmiTxRegMaskVal_t kCommonPllCfg[];
++
++/**
++ * Table of PLL settings registers to configure for 480i and 576i vinFmt
++ */
++extern CONST_DAT tmHdmiTxRegMaskVal_t kVfmt480i576iPllCfg[];
++
++/**
++ * Table of PLL settings registers to configure for single mode pixel rate,
++ * vinFmt 480i or 576i only
++ */
++extern CONST_DAT tmHdmiTxRegMaskVal_t kSinglePrateVfmt480i576iPllCfg[];
++
++/**
++ * Table of PLL settings registers to configure for single repeated mode pixel rate,
++ * vinFmt 480i or 576i only
++ */
++extern CONST_DAT tmHdmiTxRegMaskVal_t kSrepeatedPrateVfmt480i576iPllCfg[];
++
++/**
++ * Table of PLL settings registers to configure for other vinFmt than 480i and 576i
++ */
++extern CONST_DAT tmHdmiTxRegMaskVal_t kVfmtOtherPllCfg[];
++
++/**
++ * Table of PLL settings registers to configure single mode pixel rate,
++ * vinFmt other than 480i or 576i
++ */
++extern CONST_DAT tmHdmiTxRegMaskVal_t kSinglePrateVfmtOtherPllCfg[];
++
++/**
++ * Table of PLL settings registers to configure double mode pixel rate,
++ * vinFmt other than 480i or 576i
++ */
++extern CONST_DAT tmHdmiTxRegMaskVal_t kDoublePrateVfmtOtherPllCfg[];
++
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++extern tmbslHdmiTxVidFmt_t calculateVidFmtIndex(tmbslHdmiTxVidFmt_t vidFmt);
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMBSLTDA9989_INOUT_L_H */
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Misc.c b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Misc.c
+new file mode 100755
+index 0000000..d45cc25
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Misc.c
+@@ -0,0 +1,2512 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_misc.c
++ *
++ * \version        %version: 3 %
++ *
++ *
++*/
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#include <linux/kernel.h>
++#endif
++#include "tmbslHdmiTx_types.h"
++#include "tmbslTDA9989_Functions.h"
++#include "tmbslTDA9989_local.h"
++#include "tmbslTDA9989_HDCP_l.h"
++#include "tmbslTDA9989_State_l.h"
++#include "tmbslTDA9989_InOut_l.h"
++#include "tmbslTDA9989_Edid_l.h"
++#include "tmbslTDA9989_Misc_l.h"
++
++/*============================================================================*/
++/*                     TYPES DECLARATIONS                                     */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS EXPORTED                      */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS                               */
++/*============================================================================*/
++
++/** Preset default values for an object instance */
++static CONST_DAT tmHdmiTxobject_t kHdmiTxInstanceDefault
++=
++{
++    ST_UNINITIALIZED,                   /* state */
++    0,                                  /* nIgnoredEvents */
++    tmUnit0,                            /* txUnit */
++    0,                                  /* uHwAddress */
++    (ptmbslHdmiTxSysFunc_t)0,           /* sysFuncWrite */
++    (ptmbslHdmiTxSysFunc_t)0,           /* sysFuncRead */
++    (ptmbslHdmiTxSysFuncEdid_t)0,       /* sysFuncEdidRead */
++    (ptmbslHdmiTxSysFuncTimer_t)0,      /* sysFuncTimer */
++    {                                   /* funcIntCallbacks[] */
++        (ptmbslHdmiTxCallback_t)0
++    },
++    0,                                  /* InterruptsEnable */      
++    {                                   /* uSupportedVersions[] */
++        E_DEV_VERSION_N2,
++        E_DEV_VERSION_TDA19989,
++        E_DEV_VERSION_TDA19989_N2,
++        E_DEV_VERSION_TDA19988,
++        E_DEV_VERSION_LIST_END
++    },
++    E_DEV_VERSION_LIST_END,             /* uDeviceVersion */
++    E_DEV_VERSION_LIST_END,             /* uDeviceFeatures */
++    (tmbslHdmiTxPowerState_t)tmPowerOff,                         /* ePowerState */
++    False,                              /* EdidAlternateAddr */
++    HDMITX_SINK_DVI,                    /* sinkType */
++    HDMITX_SINK_DVI,                    /* EdidSinkType */
++    False,                              /* EdidSinkAi */
++    0,                                  /* EdidCeaFlags */
++
++    0,                                  /* EdidCeaXVYCCFlags */
++    {
++     False,                              /* latency_available */
++     False,                              /* Ilatency_available */
++     0,                                  /* Edidvideo_latency */
++     0,                                  /* Edidaudio_latency */
++     0,                                  /* EdidIvideo_latency */
++     0},                                 /* EdidIaudio_latency */
++
++    {
++        0,                                          /* maximum supported TMDS clock */
++        0,                                          /* content type Graphics (text) */
++        0,                                          /* content type Photo */
++        0,                                          /* content type Cinema */
++        0,                                          /* content type Game */
++        0,                                          /* additional video format */
++        0,                                          /* 3D support by the HDMI Sink */
++        0,                                          /* 3D multi strctures present */
++        0,                                          /* additional info for the values in the image size area */
++        0,                                          /* total length of 3D video formats */
++        0,                                          /* total length of extended video formats */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} /* max_len-10, ie: 31-10=21 */
++    },
++    
++    HDMITX_EDID_NOT_READ,               /* EdidStatus */
++    0,                                  /* NbDTDStored */
++    {                                   /* EdidDTD: */ /* * NUMBER_DTD_STORED */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},  /*1 */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},  /*2 */  
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},  /*3 */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},  /*4 */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},  /*5 */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},  /*6 */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},  /*7 */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},  /*8 */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},  /*9 */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0,0}  /*10*/
++    },
++    {                               /* EdidMonitorDescriptor */
++        False,                      /* bDescRecord */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0} /* uMonitorName[EDID_MONITOR_DESCRIPTOR_SIZE]       */
++    },  
++    {
++        False,                      /* bDescRecord */
++        0,                          /* uMinVerticalRate                                 */
++        0,                          /* uMaxVerticalRate                                 */
++        0,                          /* uMinHorizontalRate                               */
++        0,                          /* uMaxHorizontalRate                               */
++        0                           /* uMaxSupportedPixelClk                            */
++    },
++    {
++        False,                      /* bDescRecord */
++        {0,0,0,0,0,0,0,0,0,0,0,0,0} /* uOtherDescriptor[EDID_MONITOR_DESCRIPTOR_SIZE]   */
++    },
++    {                                   /* EdidVFmts[] */
++        HDMITX_VFMT_NULL
++    },
++    0,                                  /* EdidSvdCnt */
++    {                                   /* EdidAFmts[]. */
++        {0,0,0}                             /* {ModeChans, Freqs, Byte3} */
++    },
++    0,                                  /* EdidSadCnt */
++    {
++        0                               /* EdidBlock[ ] */
++    },
++    0,                                  /* EdidBlockCnt */
++    0,                                  /* EdidSourceAddress */
++    0,                                  /* EdidBlockRequested */
++    False,                              /* EdidReadStarted */
++    {                                   /* EdidToApp */
++        0,                              /* pRawEdid */
++        0                               /* numBlocks */
++    },
++    {                                   /* EDIDBasicDisplayParam */
++        0,                              /* uVideoInputDef */
++        0,                              /* uMaxHorizontalSize */
++        0,                              /* uMaxVerticalSize */
++        0,                              /* uGamma */
++        0,                              /* uFeatureSupport */
++    },
++#ifdef TMFL_HDCP_SUPPORT
++    False,                              /* HDCPIgnoreEncrypt */
++    0,                                  /* HdcpPortAddress */
++    HDMITX_HDCP_TXMODE_NOT_SET,         /* HdcpTxMode */
++    HDMITX_HDCP_OPTION_DEFAULT,         /* HdcpOptions */
++    0,                                  /* HdcpBcaps */
++    0,                                  /* HdcpBstatus */
++    0,                                  /* HdcpRi */
++    0,                                  /* HdcpFsmState */
++    0,                                  /* HdcpT0FailState */
++    0,                                  /* HdcpSeed */
++    {0, 0, 0, 0, 0},                    /* HdcpAksv */
++    (ptmHdmiTxFunc_t)0,                 /* HdcpFuncScheduled */
++    0,                                  /* HdcpFuncRemainingMs */
++    0,                                  /* HdcpCheckIntervalMs */
++    0,                                  /* HdcpCheckRemainingMs */
++    0,                                  /* HdcpCheckNum */
++    0,                                  /* HdcpChecksToDo */
++#endif /* TMFL_HDCP_SUPPORT */
++    HDMITX_VFMT_NULL,                   /* vinFmt */
++    HDMITX_VFMT_NULL,                   /* voutFmt */
++    HDMITX_PIXRATE_DOUBLE,              /* pixRate */
++    HDMITX_VINMODE_RGB444,              /* vinMode */
++    HDMITX_VOUTMODE_RGB444,             /* voutMode */
++    HDMITX_VFREQ_INVALID,               /* voutFreq */
++    HDMITX_SCAMODE_OFF,                 /* scaMode */
++    HDMITX_UPSAMPLE_AUTO,               /* upsampleMode */
++    HDMITX_PIXREP_MIN,                  /* pixelRepeatCount */
++    HDMITX_HOTPLUG_INVALID,             /* hotPlugStatus */
++    HDMITX_RX_SENSE_INVALID,            /* rxSenseStatus */
++    E_PAGE_INVALID,                     /* curRegPage */
++    {
++        /* These match power-up defaults.  shadowReg[]: */
++        0x00,                           /* E_SP00_INT_FLAGS_0 */
++        0x00,                           /* E_SP00_INT_FLAGS_1 */
++        0x00,                           /* E_SP00_INT_FLAGS_2 */
++        0x01,                           /* E_SP00_VIP_CNTRL_0 */
++        0x24,                           /* E_SP00_VIP_CNTRL_1 */
++        0x56,                           /* E_SP00_VIP_CNTRL_2 */
++        0x17,                           /* E_SP00_VIP_CNTRL_3 */
++        0x01,                           /* E_SP00_VIP_CNTRL_4 */
++        0x00,                           /* E_SP00_VIP_CNTRL_5 */
++        0x05,                           /* E_SP00_MAT_CONTRL  */
++        0x00,                           /* E_SP00_TBG_CNTRL_0 */
++        0x00,                           /* E_SP00_TBG_CNTRL_1 */
++        0x00,                           /* E_SP00_HVF_CNTRL_0 */
++        0x00,                           /* E_SP00_HVF_CNTRL_1 */
++        0x00,                           /* E_SP00_TIMER_H     */
++        0x00,                           /* E_SP00_DEBUG_PROBE */
++        0x00                            /* E_SP00_AIP_CLKSEL  */
++        ,0x00                           /* E_SP01_SC_VIDFORMAT*/
++        ,0x00                           /* E_SP01_SC_CNTRL    */
++        ,0x00                           /* E_SP01_TBG_CNTRL_0 */
++#ifdef TMFL_HDCP_SUPPORT
++        ,0x00                           /* E_SP12_CTRL   */
++        ,0x00                           /* E_SP12_BCAPS  */
++#endif /* TMFL_HDCP_SUPPORT */
++    },
++    False,                              /* Init prevFilterPattern to false */
++    False,                              /* Init prevPattern to false */
++    False,                              /* bInitialized */
++    HDMITX_VQR_DEFAULT
++};
++
++
++/**
++ * Table of shadow registers, as packed Shad/Page/Addr codes.
++ * This allows shadow index values to be searched for using register page
++ * and address values.
++ */
++static CONST_DAT UInt16 kShadowReg[E_SNUM] =
++{/* Shadow Index                  Packed Shad/Page/Addr */
++    E_REG_P00_INT_FLAGS_0_RW,    /* E_SP00_INT_FLAGS_0  */
++    E_REG_P00_INT_FLAGS_1_RW,    /* E_SP00_INT_FLAGS_1  */
++    E_REG_P00_INT_FLAGS_2_RW,    /* E_SP00_INT_FLAGS_2  */
++    E_REG_P00_VIP_CNTRL_0_W ,    /* E_SP00_VIP_CNTRL_0  */
++    E_REG_P00_VIP_CNTRL_1_W ,    /* E_SP00_VIP_CNTRL_1  */
++    E_REG_P00_VIP_CNTRL_2_W ,    /* E_SP00_VIP_CNTRL_2  */
++    E_REG_P00_VIP_CNTRL_3_W ,    /* E_SP00_VIP_CNTRL_3  */
++    E_REG_P00_VIP_CNTRL_4_W ,    /* E_SP00_VIP_CNTRL_4  */
++    E_REG_P00_VIP_CNTRL_5_W ,    /* E_SP00_VIP_CNTRL_5  */
++    E_REG_P00_MAT_CONTRL_W  ,    /* E_SP00_MAT_CONTRL   */
++    E_REG_P00_TBG_CNTRL_0_W ,    /* E_SP00_TBG_CNTRL_0  */
++    E_REG_P00_TBG_CNTRL_1_W ,    /* E_SP00_TBG_CNTRL_1  */
++    E_REG_P00_HVF_CNTRL_0_W ,    /* E_SP00_HVF_CNTRL_0  */
++    E_REG_P00_HVF_CNTRL_1_W ,    /* E_SP00_HVF_CNTRL_1  */
++    E_REG_P00_TIMER_H_W     ,    /* E_SP00_TIMER_H      */
++    E_REG_P00_DEBUG_PROBE_W ,    /* E_SP00_DEBUG_PROBE  */
++    E_REG_P00_AIP_CLKSEL_W,      /* E_SP00_AIP_CLKSEL   */
++    E_REG_P01_SC_VIDFORMAT_W,    /* E_SP01_SC_VIDFORMAT */
++    E_REG_P01_SC_CNTRL_W,        /* E_SP01_SC_CNTRL     */
++    E_REG_P01_TBG_CNTRL_0_W      /* E_SP01_TBG_CNTRL_0  */
++#ifdef TMFL_HDCP_SUPPORT
++    ,E_REG_P12_CTRL_W       /* E_SP12_CTRL    */
++    ,E_REG_P12_BCAPS_W      /* E_SP12_BCAPS   */
++#endif /* TMFL_HDCP_SUPPORT */
++};
++
++
++/**
++ * Table of registers to switch to low power (standby)
++ 
++static CONST_DAT tmHdmiTxRegMaskVal_t kPowerOff[] =
++{
++    {E_REG_P02_TEST2_RW,        E_MASKREG_P02_TEST2_pwd1v8,         1},
++    {E_REG_P02_PLL_SCG1_RW,     E_MASKREG_P02_PLL_SCG1_scg_fdn,     1},
++    {E_REG_P02_PLL_SERIAL_1_RW, E_MASKREG_P02_PLL_SERIAL_1_srl_fdn, 1},
++    {E_REG_P02_PLL_DE_RW,       E_MASKREG_P02_PLL_DE_pllde_fdn,     1},
++    {E_REG_P02_BUFFER_OUT_RW,   E_MASKREG_P02_BUFFER_OUT_srl_force, 2},
++    {E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_ena_sc_clk,   0},
++    {E_REG_P00_CCLK_ON_RW,      E_MASKREG_P00_CCLK_ON_cclk_on,      0},
++    {0,0,0}
++};
++*/
++/**
++ * Table of registers to switch to normal power (resume)
++ 
++static CONST_DAT tmHdmiTxRegMaskVal_t kPowerOn[] =
++{
++    {E_REG_P02_TEST2_RW,        E_MASKREG_P02_TEST2_pwd1v8,         0},
++    {E_REG_P02_PLL_SERIAL_1_RW, E_MASKREG_P02_PLL_SERIAL_1_srl_fdn, 0},
++    {E_REG_P02_PLL_DE_RW,       E_MASKREG_P02_PLL_DE_pllde_fdn,     0},
++    {E_REG_P02_PLL_SCG1_RW,     E_MASKREG_P02_PLL_SCG1_scg_fdn,     0},
++    {E_REG_P02_SEL_CLK_RW,      E_MASKREG_P02_SEL_CLK_ena_sc_clk,   1},
++    {E_REG_P02_BUFFER_OUT_RW,   E_MASKREG_P02_BUFFER_OUT_srl_force, 0},
++    {E_REG_P00_TBG_CNTRL_0_W,   E_MASKREG_P00_TBG_CNTRL_0_sync_once,0},
++    {E_REG_P00_CCLK_ON_RW,      E_MASKREG_P00_CCLK_ON_cclk_on,      1},
++    {0,0,0}
++};
++*/
++
++static CONST_DAT tmbslHdmiTxCallbackInt_t kITCallbackPriority[HDMITX_CALLBACK_INT_NUM] =
++{
++    HDMITX_CALLBACK_INT_R0,             /**< R0 interrupt                     */
++    HDMITX_CALLBACK_INT_ENCRYPT,        /**< HDCP encryption switched off     */
++    HDMITX_CALLBACK_INT_HPD,            /**< Transition on HPD input          */
++    HDMITX_CALLBACK_INT_T0,             /**< HDCP state machine in state T0   */
++    HDMITX_CALLBACK_INT_BCAPS,          /**< BCAPS available                  */
++    HDMITX_CALLBACK_INT_BSTATUS,        /**< BSTATUS available                */
++    HDMITX_CALLBACK_INT_SHA_1,          /**< sha-1(ksv,bstatus,m0)=V'         */
++    HDMITX_CALLBACK_INT_PJ,             /**< pj=pj' check fails               */
++    HDMITX_CALLBACK_INT_SW_INT,         /**< SW DEBUG interrupt               */
++    HDMITX_CALLBACK_INT_RX_SENSE,       /**< RX SENSE interrupt               */
++    HDMITX_CALLBACK_INT_EDID_BLK_READ,  /**< EDID BLK READ interrupt          */
++    HDMITX_CALLBACK_INT_VS_RPT,         /**< VS interrupt                     */
++    HDMITX_CALLBACK_INT_PLL_LOCK        /** PLL LOCK not present on TDA9984   */
++};
++
++
++
++#ifdef TMFL_TDA9989_PIXEL_CLOCK_ON_DDC
++
++ CONST_DAT UInt8 kndiv_im[] =
++{
++    0, /* HDMITX_VFMT_NO_CHANGE */
++    4, /* HDMITX_VFMT_01_640x480p_60Hz */
++    4, /* HDMITX_VFMT_02_720x480p_60Hz */
++    4, /* HDMITX_VFMT_03_720x480p_60Hz */
++    12, /* HDMITX_VFMT_04_1280x720p_60Hz */
++    12, /* HDMITX_VFMT_05_1920x1080i_60Hz */
++    4, /* HDMITX_VFMT_06_720x480i_60Hz */
++    4, /* HDMITX_VFMT_07_720x480i_60Hz */
++    4, /* HDMITX_VFMT_08_720x240p_60Hz */
++    4, /* HDMITX_VFMT_09_720x240p_60Hz */
++    4, /* HDMITX_VFMT_10_720x480i_60Hz */
++    4, /* HDMITX_VFMT_11_720x480i_60Hz */
++    4, /* HDMITX_VFMT_12_720x240p_60Hz */
++    4, /* HDMITX_VFMT_13_720x240p_60Hz */
++    4, /* HDMITX_VFMT_14_1440x480p_60Hz */
++    4, /* HDMITX_VFMT_15_1440x480p_60Hz */
++    12,/* HDMITX_VFMT_16_1920x1080p_60Hz */
++    4, /* HDMITX_VFMT_17_720x576p_50Hz */
++    4, /* HDMITX_VFMT_18_720x576p_50Hz */
++    12, /* HDMITX_VFMT_19_1280x720p_50Hz */
++    12, /* HDMITX_VFMT_20_1920x1080i_50Hz */
++    4, /* HDMITX_VFMT_21_720x576i_50Hz */
++    4, /* HDMITX_VFMT_22_720x576i_50Hz */
++    4, /* HDMITX_VFMT_23_720x288p_50Hz */
++    4, /* HDMITX_VFMT_24_720x288p_50Hz */
++    4, /* HDMITX_VFMT_25_720x576i_50Hz */
++    4, /* HDMITX_VFMT_26_720x576i_50Hz */
++    4, /* HDMITX_VFMT_27_720x288p_50Hz */
++    4, /* HDMITX_VFMT_28_720x288p_50Hz */
++    4, /* HDMITX_VFMT_29_1440x576p_50Hz */
++    4, /* HDMITX_VFMT_30_1440x576p_50Hz */
++    12,/* HDMITX_VFMT_31_1920x1080p_50Hz */
++    12, /* HDMITX_VFMT_32_1920x1080p_24Hz */
++    12, /* HDMITX_VFMT_33_1920x1080p_25Hz */
++    12, /* HDMITX_VFMT_34_1920x1080p_30Hz */
++
++};
++
++ CONST_DAT UInt8 kclk_div[] =
++ {
++    0, /* HDMITX_VFMT_NO_CHANGE */
++    44, /* HDMITX_VFMT_01_640x480p_60Hz */
++    44, /* HDMITX_VFMT_02_720x480p_60Hz */
++    44, /* HDMITX_VFMT_03_720x480p_60Hz */
++    44, /* HDMITX_VFMT_04_1280x720p_60Hz */
++    44, /* HDMITX_VFMT_05_1920x1080i_60Hz */
++    44, /* HDMITX_VFMT_06_720x480i_60Hz */
++    44, /* HDMITX_VFMT_07_720x480i_60Hz */
++    44, /* HDMITX_VFMT_08_720x240p_60Hz */
++    44, /* HDMITX_VFMT_09_720x240p_60Hz */
++    44, /* HDMITX_VFMT_10_720x480i_60Hz */
++    44, /* HDMITX_VFMT_11_720x480i_60Hz */
++    44, /* HDMITX_VFMT_12_720x240p_60Hz */
++    44, /* HDMITX_VFMT_13_720x240p_60Hz */
++    44, /* HDMITX_VFMT_14_1440x480p_60Hz */
++    44, /* HDMITX_VFMT_15_1440x480p_60Hz */
++    44,/* HDMITX_VFMT_16_1920x1080p_60Hz */
++    44, /* HDMITX_VFMT_17_720x576p_50Hz */
++    44, /* HDMITX_VFMT_18_720x576p_50Hz */
++    44, /* HDMITX_VFMT_19_1280x720p_50Hz */
++    44, /* HDMITX_VFMT_20_1920x1080i_50Hz */
++    44, /* HDMITX_VFMT_21_720x576i_50Hz */
++    44, /* HDMITX_VFMT_22_720x576i_50Hz */
++    44, /* HDMITX_VFMT_23_720x288p_50Hz */
++    44, /* HDMITX_VFMT_24_720x288p_50Hz */
++    44, /* HDMITX_VFMT_25_720x576i_50Hz */
++    44, /* HDMITX_VFMT_26_720x576i_50Hz */
++    44, /* HDMITX_VFMT_27_720x288p_50Hz */
++    44, /* HDMITX_VFMT_28_720x288p_50Hz */
++    44, /* HDMITX_VFMT_29_1440x576p_50Hz */
++    44, /* HDMITX_VFMT_30_1440x576p_50Hz */
++    44,/* HDMITX_VFMT_31_1920x1080p_50Hz */
++    44, /* HDMITX_VFMT_32_1920x1080p_24Hz */
++    44, /* HDMITX_VFMT_33_1920x1080p_25Hz */
++    44, /* HDMITX_VFMT_34_1920x1080p_30Hz */
++ };
++
++#endif /* TMFL_TDA9989_PIXEL_CLOCK_ON_DDC */
++
++
++/*============================================================================*/
++/*                       FUNCTIONS DECLARATIONS                               */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                       VARIABLES DECLARATIONS                               */
++/*============================================================================*/
++
++#ifdef TMFL_HDCP_SUPPORT
++static UInt32 sgBcapsCounter = 0;
++#endif /* TMFL_HDCP_SUPPORT */
++
++#define TDA19989_DDC_SPEED_FACTOR 39
++
++static Bool gMiscInterruptHpdRxEnable = False; /* Enable HPD and RX sense IT after */
++                                               /* first call done by init function */
++static UInt8 int_level=0xFF;
++/*============================================================================*/
++/*                       FUNCTION PROTOTYPES                                  */
++/*============================================================================*/
++
++/*============================================================================*/
++/* tmbslTDA9989Deinit                                                          */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989Deinit
++(
++    tmUnitSelect_t txUnit
++)
++{
++    tmHdmiTxobject_t *pDis;     					/* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;      					/* Error code */
++    UInt8             EnableModeMask = 0;          /* Local Variable */    
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++    
++	 /* patch to get successfull soft reset even if powerstate has been set to standby mode */
++    /*Write data in ENAMODS CEC Register */
++    EnableModeMask = 0x40;
++    EnableModeMask |= E_MASKREG_CEC_ENAMODS_ena_hdmi; /*Enable HDMI Mode*/
++    EnableModeMask &= ~E_MASKREG_CEC_ENAMODS_dis_fro; /* Enable FRO  */
++    err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, EnableModeMask);
++    RETIF_REG_FAIL(err)    
++
++    /* Hold the device in reset to disable it */
++    err = setHwRegisterField(pDis, E_REG_P00_MAIN_CNTRL0_RW,
++                             E_MASKREG_P00_MAIN_CNTRL0_sr, 1);
++    RETIF_REG_FAIL(err)                               
++                             
++	 /* patch to get successfull soft reset even if powerstate has been set to standby mode */   
++    EnableModeMask &= ~E_MASKREG_CEC_ENAMODS_ena_hdmi; /* Disable HDMI Mode*/
++    EnableModeMask &= ~E_MASKREG_CEC_ENAMODS_ena_rxs; /* Reset RxSense Mode*/    
++    EnableModeMask |= E_MASKREG_CEC_ENAMODS_dis_fro; /* Disable FRO  */
++    err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, EnableModeMask);
++    RETIF_REG_FAIL(err)
++
++    /* Clear the Initialized flag to destroy the device instance */
++    pDis->bInitialized = False;
++
++    setState(pDis, EV_DEINIT);
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HotPlugGetStatus                                                */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HotPlugGetStatus
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxHotPlug_t *pHotPlugStatus,
++    Bool                  client /* Used to determine whether the request comes from the application */
++)
++{
++    tmHdmiTxobject_t *pDis;     /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;      /* Error code */
++    UInt8             regVal;   /* Register value */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM(pHotPlugStatus == (tmbslHdmiTxHotPlug_t *)0)
++
++    /* Read HPD RXS level */
++    err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&regVal);
++    RETIF(err != TM_OK, err)
++
++    /* Read Hot Plug input status to know the actual level that caused the interrupt */
++    if (client)
++    {
++        *pHotPlugStatus = (regVal & E_MASKREG_CEC_RXSHPDLEV_hpd_level) ?
++                HDMITX_HOTPLUG_ACTIVE : HDMITX_HOTPLUG_INACTIVE;
++    } 
++    else {
++
++    *pHotPlugStatus = pDis->hotPlugStatus;
++
++    }
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989RxSenseGetStatus                                                */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989RxSenseGetStatus
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxRxSense_t *pRxSenseStatus,
++    Bool                  client /* Used to determine whether the request comes from the application */
++)
++{
++    tmHdmiTxobject_t *pDis;     /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;      /* Error code */
++    UInt8             regVal;   /* Register value */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM(pRxSenseStatus == (tmbslHdmiTxRxSense_t *)0)
++
++
++    /* Read HPD RXS level */
++    err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&regVal);
++    RETIF(err != TM_OK, err)
++
++
++    /*Read RXS_FIL status to know the actual level that caused the interrupt */
++    if (client)
++    {
++         *pRxSenseStatus = (regVal & E_MASKREG_CEC_RXSHPDLEV_rxs_level) ?
++                 HDMITX_RX_SENSE_ACTIVE : HDMITX_RX_SENSE_INACTIVE;
++    }
++    else {
++    *pRxSenseStatus = pDis->rxSenseStatus;
++    }
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HwGetRegisters                                                  */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HwGetRegisters
++(
++    tmUnitSelect_t  txUnit,
++    Int             regPage,
++    Int             regAddr,
++    UInt8          *pRegBuf,
++    Int             nRegs
++)
++{
++    tmHdmiTxobject_t *pDis;         /* Pointer to Device Instance Structure */
++    tmErrorCode_t   err;            /* Error code */
++    Int             i;              /* Loop index */
++    UInt8           newRegPage;     /* The register's new page number */
++    UInt8           regShad;        /* Index to the register's shadow copy */
++    UInt16          regShadPageAddr;/* Packed shadowindex/page/address */
++    tmbslHdmiTxSysArgs_t sysArgs;   /* Arguments passed to system function     */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM((regPage < kPageIndexToPage[E_PAGE_00]) 
++      || ((regPage > kPageIndexToPage[E_PAGE_02]) 
++       && (regPage < kPageIndexToPage[E_PAGE_09]))
++      || ((regPage > kPageIndexToPage[E_PAGE_09]) 
++       && (regPage < kPageIndexToPage[E_PAGE_11]))
++      ||  (regPage > kPageIndexToPage[E_PAGE_12]))
++    RETIF_BADPARAM((regAddr < E_REG_MIN_ADR) || (regAddr >= E_REG_CURPAGE_ADR_W))
++    RETIF_BADPARAM(pRegBuf == (pUInt8)0)
++    RETIF_BADPARAM((nRegs < 1) || ((nRegs + regAddr) > E_REG_CURPAGE_ADR_W))
++
++    /* Set page register if required */
++    newRegPage = (UInt8)regPage;
++    if (pDis->curRegPage != newRegPage)
++    {
++        /* All non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = E_REG_CURPAGE_ADR_W;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = &newRegPage;
++        err = pDis->sysFuncWrite(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_WRITE)
++        pDis->curRegPage = newRegPage;
++    }
++
++    /* Read each register in the range. nRegs must start at 1 or more */
++    for ( ; nRegs > 0; pRegBuf++, regAddr++, nRegs--)
++    {
++        /* Find shadow register index.
++         * This loop is not very efficient, but it is assumed that this API
++         * will not be used often. The alternative is to use a huge sparse
++         * array indexed by page and address and containing the shadow index.
++         */
++        regShad = E_SNONE;
++        for (i = 0; i < E_SNUM; i++)
++        {
++            /* Check lookup table for match with page and address */
++            regShadPageAddr = kShadowReg[i];
++            if ((SPA2PAGE(regShadPageAddr) == newRegPage)
++            &&  (SPA2ADDR(regShadPageAddr) == regAddr))
++            {
++                /* Found page and address - look up the shadow index */
++                regShad = SPA2SHAD(regShadPageAddr);
++                break;
++            }
++        }
++        /* Read the shadow register if available, as device registers that
++         * are shadowed cannot be read directly */
++        if (regShad != E_SNONE)
++        {
++            *pRegBuf = pDis->shadowReg[regShad];
++        }
++        else
++        {
++            /* Read the device register - all non-OK results are errors.
++             * Note that some non-shadowed registers are also write-only and
++             * cannot be read. */
++            sysArgs.slaveAddr       = pDis->uHwAddress;
++            sysArgs.firstRegister   = (UInt8)regAddr;
++            sysArgs.lenData         = 1;
++            sysArgs.pData           = pRegBuf;
++            err = pDis->sysFuncRead(&sysArgs);
++            RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_READ)
++        }
++    }
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HwGetVersion                                                    */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989HwGetVersion
++(
++    tmUnitSelect_t  txUnit,
++    pUInt8          pHwVersion
++)
++{
++    tmHdmiTxobject_t *pDis;     /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;      /* Error code */
++    UInt8             regVal;
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM(pHwVersion == (pUInt8)0)
++
++    /* Get MSB version Value*/
++    err = getHwRegister(pDis, E_REG_P00_VERSION_MSB_RW, &regVal);
++    RETIF(err != TM_OK, err)
++
++   switch (regVal) 
++    {
++    case 0x01:
++        *pHwVersion = (UInt8)(BSLHDMITX_TDA9989);
++        break;
++    case 0x02:
++        *pHwVersion = (UInt8)(BSLHDMITX_TDA19989);
++        break;
++    case 0x03:
++        *pHwVersion = (UInt8)(BSLHDMITX_TDA19988);
++        break;
++    default:
++        *pHwVersion = (UInt8)(BSLHDMITX_UNKNOWN);
++        break;
++    }
++
++    return TM_OK;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989HwHandleInterrupt                                               */
++/* RETIF_REG_FAIL NOT USED HERE AS ALL ERRORS SHOULD BE TRAPPED IN ALL BUILDS */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HwHandleInterrupt
++(
++    tmUnitSelect_t      txUnit
++)
++{
++    tmHdmiTxobject_t        *pDis;            /* Pointer to Device Instance Structure */
++    tmErrorCode_t           err;              /* Error code */
++    UInt8                   regVal;           /* Register value */
++    UInt8                   regVal1;           /* Register value */
++    UInt16                  fInterruptStatus; /* Interrupt flags */
++    UInt16                  fInterruptMask;   /* Mask to test each interrupt bit */
++    tmbslHdmiTxRxSense_t    newRxs_fil;       /* Latest copy of rx_sense */
++    Int                     i;                /* Loop counter */
++    tmbslHdmiTxHotPlug_t    newHpdIn;         /* Latest copy of hpd input */
++    Bool                    sendEdidCallback;
++    Bool hpdOrRxsLevelHasChanged = False;
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    fInterruptStatus = 0;
++    sendEdidCallback = False;
++
++
++
++    /* Read HPD RXS int status */ 
++    err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDINT_R,&regVal);
++    RETIF(err != TM_OK, err);
++
++    /* Read HPD RXS level */
++    err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&regVal1);
++    RETIF(err != TM_OK, err);
++
++    if (int_level!=0xFF) { /* init should be done */
++       /* check multi-transition */
++       if ((regVal==0) && (int_level!=regVal1)) {
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++          printk("HDMI Int multi-transition\n");
++#endif
++          err = setCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, 0x00);
++          err += setCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, \
++                                  E_MASKREG_CEC_RXSHPDINTENA_ena_rxs_int | \
++                                  E_MASKREG_CEC_RXSHPDINTENA_ena_hpd_int);
++          err += getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&regVal1);
++          RETIF(err != TM_OK, err)
++       }
++    }
++    int_level=regVal1;
++
++    /* Read Hot Plug input status to know the actual level that caused the interrupt */
++    newHpdIn = (regVal1 & E_MASKREG_CEC_RXSHPDLEV_hpd_level) ?
++                HDMITX_HOTPLUG_ACTIVE : HDMITX_HOTPLUG_INACTIVE;
++
++    /*Read RXS_FIL status to know the actual level that caused the interrupt */
++    newRxs_fil = (regVal1 & E_MASKREG_CEC_RXSHPDLEV_rxs_level) ?
++                 HDMITX_RX_SENSE_ACTIVE : HDMITX_RX_SENSE_INACTIVE;
++
++    /*Fill fInterruptStatus with HPD Interrupt flag*/
++
++    if (newHpdIn != pDis->hotPlugStatus) 
++         {
++              fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_HPD); 
++            /* Yes: save new HPD level */
++            pDis->hotPlugStatus = newHpdIn;
++            hpdOrRxsLevelHasChanged = True;
++         }
++
++    /*Fill fInterruptStatus with RX Sense Interrupt flag*/
++    if (newRxs_fil != pDis->rxSenseStatus)
++         {
++            fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_RX_SENSE); 
++            /* Yes: save new rxSense level */
++            pDis->rxSenseStatus = newRxs_fil;
++            hpdOrRxsLevelHasChanged = True;
++         }
++
++
++
++    /* is it  HDMI interrupt ? */
++    err = getCECHwRegister(pDis, E_REG_CEC_INTERRUPTSTATUS_R,&regVal);
++    RETIF(err != TM_OK, err)
++
++    /* there is no HDMI int to handle, give up */
++    if ((regVal & E_MASKREG_CEC_INTERRUPTSTATUS_hdmi_int) == 0x00) {
++        
++        if (hpdOrRxsLevelHasChanged == True) {
++        }
++        else {
++        return TM_OK;
++        }
++    }
++
++
++
++    /************************************************************************************************/
++    /***********************************End of Temporary code****************************************/
++    /************************************************************************************************/
++
++    /* Do only if HDMI is On*/
++    if(pDis->ePowerState == tmPowerOn)
++    {   
++        /* Read the main interrupt flags register to determine the source(s) 
++        * of the interrupt. (The device resets these register flags after they 
++        * have been read.)
++         */
++        err = getHwRegister(pDis, E_REG_P00_INT_FLAGS_0_RW, &regVal);
++        RETIF(err != TM_OK, err)
++
++#ifdef TMFL_HDCP_SUPPORT
++        /* encrypt */
++        if ((regVal & E_MASKREG_P00_INT_FLAGS_0_encrypt) != 0)
++        {
++          fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_ENCRYPT); 
++        }
++#endif /* TMFL_HDCP_SUPPORT */
++
++        /* get TO interrupt Flag*/
++        if ((regVal & E_MASKREG_P00_INT_FLAGS_0_t0) != 0)
++        {
++            fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_T0); 
++        }
++
++#ifdef TMFL_HDCP_SUPPORT
++        /* bcaps */
++        if ((regVal & E_MASKREG_P00_INT_FLAGS_0_bcaps) != 0)
++        {
++            fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_BCAPS);
++
++            /* TDA19989 N1 only */
++            if (pDis->uDeviceVersion == E_DEV_VERSION_TDA19989) {
++
++            /* WA: HDCP ATC Test 1B_03 */
++
++            sgBcapsCounter++;
++
++            if (sgBcapsCounter == 49) {
++                sgBcapsCounter = 0;
++                /* force a T0 interrupt */
++                fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_T0);
++            }
++
++            } /* TDA19989 N1 only */
++
++        }
++
++        /* bstatus */
++        if ((regVal & E_MASKREG_P00_INT_FLAGS_0_bstatus) != 0)
++        {
++            fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_BSTATUS);
++
++            /* TDA19989 N1 only */
++            if (pDis->uDeviceVersion == E_DEV_VERSION_TDA19989) {
++
++            /* WA: HDCP ATC Test 1B_03 */
++            sgBcapsCounter = 0;
++
++            } /* TDA19989 N1 only */
++
++        }
++
++        /* sha_1 */
++        if ((regVal & E_MASKREG_P00_INT_FLAGS_0_sha_1) != 0)
++        {
++           fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_SHA_1); 
++        }
++
++        /* pj */
++        if ((regVal & E_MASKREG_P00_INT_FLAGS_0_pj) != 0)
++        {
++           fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_PJ); 
++        }
++
++        /* r0 */
++        if ((regVal & E_MASKREG_P00_INT_FLAGS_0_r0) != 0)
++        {
++          fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_R0);
++
++          /* TDA19989 N1 only */
++          if (pDis->uDeviceVersion == E_DEV_VERSION_TDA19989) {
++
++          /* WA: HDCP ATC Test 1B_03 */
++          sgBcapsCounter = 0;
++
++           } /* TDA19989 N1 only */
++
++        }
++#endif /* TMFL_HDCP_SUPPORT */
++
++    
++        err = getHwRegister(pDis, E_REG_P00_INT_FLAGS_1_RW, &regVal);
++        RETIF(err != TM_OK, err)
++
++
++     /* Read the software interrupt flag */
++        if ((regVal & E_MASKREG_P00_INT_FLAGS_1_sw_int) != 0)
++        {
++            fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_SW_INT); 
++        }
++
++        /* Read the VS_rpt interrupt flag */
++	if (((pDis->InterruptsEnable & E_MASKREG_P00_INT_FLAGS_1_vs_rpt) != 0) && 
++	    ((regVal & E_MASKREG_P00_INT_FLAGS_1_vs_rpt) != 0)
++	    )
++	  {
++	    fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_VS_RPT); 
++	  }
++
++         /* Read INT_FLAGS_2 interrupt flag register. 
++         *(The device resets these register flags after they 
++         * have been read.) */
++          err = getHwRegister(pDis, E_REG_P00_INT_FLAGS_2_RW, &regVal);
++          RETIF(err != TM_OK, err)
++
++        /* Has the EDID_blk_rd interrupt occurs */
++        if ((regVal & E_MASKREG_P00_INT_FLAGS_2_edid_blk_rd) != 0)
++        {
++             fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_EDID_BLK_READ);
++        }
++    }
++
++
++    /* Handle the HPD Interrupt */
++        if ((fInterruptStatus & (1 << HDMITX_CALLBACK_INT_HPD))!=0 )
++        {
++           /* Callback disable on first tmbslTDA9989HwHandleInterrupt call */
++           if(gMiscInterruptHpdRxEnable)
++           {
++                /* Reset EDID status */
++                err = ClearEdidRequest(txUnit);
++
++                /* Reset all simultaneous HDCP interrupts on hot plug,
++                * preserving only the high-priority hpd interrupt rx_sense and sw interrupt for debug*/
++                fInterruptStatus &= (1 << HDMITX_CALLBACK_INT_HPD) |
++                                    (1 << HDMITX_CALLBACK_INT_RX_SENSE) |
++                                    (1 << HDMITX_CALLBACK_INT_SW_INT);
++
++                if(pDis->ePowerState == tmPowerOn)
++                {
++                    if ((pDis->hotPlugStatus == HDMITX_HOTPLUG_ACTIVE))
++                    {
++
++                        /* TDA19989 N1 only */
++                        if (pDis->uDeviceVersion == E_DEV_VERSION_TDA19989) {
++
++                        err = tmbslTDA9989Reset(txUnit);
++                        RETIF(err != TM_OK, err)
++
++                        err = hotPlugRestore(txUnit);
++                        RETIF(err != TM_OK, err)
++
++                        } /* TDA19989 N1 only */
++
++                        else { /* TDA19989 N2 */
++
++                           HDCP_F2;
++                        }
++
++                        #ifdef TMFL_TDA9989_PIXEL_CLOCK_ON_DDC
++
++                        err = tmbslTDA9989Reset(txUnit);
++                        RETIF(err != TM_OK, err)
++
++                        err = hotPlugRestore(txUnit);
++                        RETIF(err != TM_OK, err)
++
++                        #endif /* TMFL_TDA9989_PIXEL_CLOCK_ON_DDC */
++
++
++
++                        setState(pDis, EV_PLUGGEDIN);
++                    }
++                    else
++                    {
++                        setState(pDis, EV_UNPLUGGED);
++                    }
++               }
++           }
++       }
++       else
++       {
++            /* Clear HPD status if level has not changed */
++           fInterruptStatus &= ~(1 << HDMITX_CALLBACK_INT_HPD);
++
++           if (fInterruptStatus & (1 << HDMITX_CALLBACK_INT_EDID_BLK_READ))
++           {
++               err = EdidBlockAvailable(txUnit,&sendEdidCallback);
++               RETIF(err != TM_OK, err)
++               if (sendEdidCallback == False)
++               {
++                   /* Read EDID not finished clear callback */
++                   fInterruptStatus &= ~(1 << HDMITX_CALLBACK_INT_EDID_BLK_READ);
++               }
++               else {
++                #ifdef TMFL_TDA9989_PIXEL_CLOCK_ON_DDC
++
++                if ( (pDis->vinFmt == HDMITX_VFMT_16_1920x1080p_60Hz) || (pDis->vinFmt == HDMITX_VFMT_31_1920x1080p_50Hz)) {
++
++                err = setHwRegisterField(pDis, 
++                                 E_REG_P02_PLL_SERIAL_3_RW, 
++                                 E_MASKREG_P02_PLL_SERIAL_3_srl_ccir,
++                                 0x00);
++                RETIF_REG_FAIL(err)
++                }
++
++               #endif /* TMFL_TDA9989_PIXEL_CLOCK_ON_DDC */
++               }
++
++
++           }
++      }
++
++    /*Handle RxSense Interrupt*/
++    if ((fInterruptStatus &( 1 << HDMITX_CALLBACK_INT_RX_SENSE))!= 0)
++    {
++        /* Callback disable on first tmbslTDA9989HwHandleInterrupt call */
++        if(gMiscInterruptHpdRxEnable)
++        {
++
++
++            fInterruptStatus &= (1 << HDMITX_CALLBACK_INT_HPD) |
++                                (1 << HDMITX_CALLBACK_INT_RX_SENSE) |
++                                (1 << HDMITX_CALLBACK_INT_SW_INT);
++
++            if (pDis->rxSenseStatus == HDMITX_RX_SENSE_ACTIVE)
++            {
++                setState(pDis, EV_SINKON);
++            }
++            else
++            {
++                setState(pDis, EV_SINKOFF);
++            }
++        }
++    }
++    else
++    {
++        /* Clear RX_sense IT if level has not changed */
++        fInterruptStatus &= ~(1 << HDMITX_CALLBACK_INT_RX_SENSE);
++    }
++
++    /* Ignore other simultaneous HDCP interrupts if T0 interrupt,
++     * preserving any hpd interrupt */
++
++    if (fInterruptStatus & (1 << HDMITX_CALLBACK_INT_T0))
++    {
++        if (pDis->EdidReadStarted)
++        {
++
++#ifdef TMFL_HDCP_SUPPORT
++	err = getHwRegister(pDis, E_REG_P12_TX0_RW, &regVal);
++	RETIF(err != TM_OK, err)
++			
++        /* EDID read failure */
++	if ((regVal & E_MASKREG_P12_TX0_sr_hdcp) != 0) {
++
++#endif /* TMFL_HDCP_SUPPORT */
++
++
++            /* Reset EDID status */
++            err = ClearEdidRequest(txUnit);
++            RETIF(err != TM_OK, err)
++
++    	    /* enable EDID callback */
++	    fInterruptStatus = (UInt16) (fInterruptStatus & (~(1 << HDMITX_CALLBACK_INT_T0)));
++	    fInterruptStatus = fInterruptStatus | (1 << HDMITX_CALLBACK_INT_EDID_BLK_READ);
++
++#ifdef TMFL_HDCP_SUPPORT
++        }
++#endif /* TMFL_HDCP_SUPPORT */
++
++        }
++        else
++        {
++            fInterruptStatus &= 
++                (
++                 (1 << HDMITX_CALLBACK_INT_HPD)
++                |(1 << HDMITX_CALLBACK_INT_T0)
++                |(1 << HDMITX_CALLBACK_INT_RX_SENSE)
++                |(1 << HDMITX_CALLBACK_INT_SW_INT)
++                );
++        }
++    }
++
++    HDCP_F3;
++
++    /* For each interrupt flag that is set, check the corresponding registered 
++     * callback function pointer in the Device Instance Structure 
++     * funcIntCallbacks array.
++     */
++    fInterruptMask = 1;
++    for (i = 0; i < HDMITX_CALLBACK_INT_NUM; i++)
++    {
++        if ( i != HDMITX_CALLBACK_INT_PLL_LOCK) /* PLL LOCK not present on TDA9989 */
++	    {
++
++            fInterruptMask = 1;
++            fInterruptMask  = fInterruptMask << ((UInt16)kITCallbackPriority[i]);
++    
++            if (fInterruptStatus & fInterruptMask)
++            {
++                /* IF a registered callback pointer is non-null THEN call it. */
++                if (pDis->funcIntCallbacks[kITCallbackPriority[i]] != (ptmbslHdmiTxCallback_t)0)
++                {
++                    pDis->funcIntCallbacks[kITCallbackPriority[i]](txUnit);
++                }
++            }
++
++	    }
++    }
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989FlagSwInt                                                       */
++/* Use only for debug to flag the software debug interrupt                    */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989FlagSwInt
++(
++ tmUnitSelect_t              txUnit,
++ UInt32                      uSwInt
++ )
++{
++    tmHdmiTxobject_t *pDis;     /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;      /* Error code */
++
++    DUMMY_ACCESS(uSwInt);
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    err = setHwRegister(pDis, E_REG_P00_SW_INT_W, 
++                        E_MASKREG_P00_SW_INT_sw_int);
++
++
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989HwSetRegisters                                                  */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989HwSetRegisters 
++(
++    tmUnitSelect_t  txUnit,
++    Int             regPage, 
++    Int             regAddr, 
++    UInt8          *pRegBuf, 
++    Int             nRegs
++)
++{
++    tmHdmiTxobject_t *pDis;         /* Pointer to Device Instance Structure */
++    tmErrorCode_t   err;            /* Error code */
++    Int             i;              /* Loop index */
++    UInt8           newRegPage;     /* The register's new page number */
++    UInt8           regShad;        /* Index to the register's shadow copy */
++    UInt16          regShadPageAddr;/* Packed shadowindex/page/address */
++    tmbslHdmiTxSysArgs_t sysArgs;   /* Arguments passed to system function */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM((regPage < kPageIndexToPage[E_PAGE_00])
++      || ((regPage > kPageIndexToPage[E_PAGE_02])
++       && (regPage < kPageIndexToPage[E_PAGE_11]))
++      ||  (regPage > kPageIndexToPage[E_PAGE_12]))
++    RETIF_BADPARAM((regAddr < E_REG_MIN_ADR) || (regAddr >= E_REG_CURPAGE_ADR_W))
++    RETIF_BADPARAM(pRegBuf == (pUInt8)0)
++    RETIF_BADPARAM((nRegs < 0) || ((nRegs + regAddr) > E_REG_CURPAGE_ADR_W))
++
++    /* Set page register if required */
++    newRegPage = (UInt8)regPage;
++    if (pDis->curRegPage != newRegPage)
++    {
++        /* All non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = E_REG_CURPAGE_ADR_W;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = &newRegPage;
++        err = pDis->sysFuncWrite(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_WRITE)
++        pDis->curRegPage = newRegPage;
++    }
++
++    /* Write each register in the range. nRegs = 0 is ok, to allow only
++     * the page register to be written if required (above)
++     */
++    for ( ; nRegs > 0; pRegBuf++, regAddr++, nRegs--)
++    {
++        /* Find shadow register index.
++         * This loop is not very efficient, but it is assumed that this API
++         * will not be used often. The alternative is to use a huge sparse
++         * array indexed by page and address and containing the shadow index.
++         */
++        for (i = 0; i < E_SNUM; i++)
++        {
++            /* Check lookup table for match with page and address */
++            regShadPageAddr = kShadowReg[i];
++            if ((SPA2PAGE(regShadPageAddr) == newRegPage)
++            &&  (SPA2ADDR(regShadPageAddr) == regAddr))
++            {
++                /* Found index - write the shadow register */
++                regShad = SPA2SHAD(regShadPageAddr);
++                pDis->shadowReg[regShad] = *pRegBuf;
++                break;
++            }
++        }
++        /* Write the device register - all non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = (UInt8)regAddr;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = pRegBuf;
++        err = pDis->sysFuncWrite(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_WRITE)
++    }
++
++    return TM_OK;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989HwStartup                                                       */
++/*============================================================================*/
++void
++tmbslTDA9989HwStartup
++(
++    void
++)
++{
++    /* Reset device instance data for when compiler doesn't do it */
++    lmemset(&gHdmiTxInstance, 0, sizeof(gHdmiTxInstance));
++}
++
++/*============================================================================*/
++/* tmbslTDA9989Init                                                            */
++/* RETIF_REG_FAIL NOT USED HERE AS ALL ERRORS SHOULD BE TRAPPED IN ALL BUILDS */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989Init
++(
++    tmUnitSelect_t             txUnit,
++    UInt8                      uHwAddress,
++    ptmbslHdmiTxSysFunc_t      sysFuncWrite,
++    ptmbslHdmiTxSysFunc_t      sysFuncRead,
++    ptmbslHdmiTxSysFuncEdid_t  sysFuncEdidRead,
++    ptmbslHdmiTxSysFuncTimer_t sysFuncTimer,
++    tmbslHdmiTxCallbackList_t *funcIntCallbacks,
++    Bool                       bEdidAltAddr,
++    tmbslHdmiTxVidFmt_t        vinFmt,
++    tmbslHdmiTxPixRate_t       pixRate
++)
++{
++    tmHdmiTxobject_t *pDis;                /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;                 /* Error code */
++    Int               i;                   /* Loop index */
++    Bool              bFound;              /* T=found, F=not found */
++    UInt8             EnableIntMask = 0;   /* Mask used to enable HPD and RX Sense interrupt*/
++    UInt8             EnableModeMask;      /* Mask used to Set HDMI and RxSense modes*/
++    UInt16            val16Bits;           /* Value on 16 bit */
++    UInt8             regVal;              /* Register value */
++
++    /* Check unit parameter and point to its object */
++    RETIF(txUnit < tmUnit0, TMBSL_ERR_HDMI_BAD_UNIT_NUMBER) 
++    RETIF(txUnit >= HDMITX_UNITS_MAX, TMBSL_ERR_HDMI_BAD_UNIT_NUMBER)
++    pDis = &gHdmiTxInstance[txUnit];
++
++    /* IF the bInitialized flag is set THEN return (only Init does this) */
++    RETIF(pDis->bInitialized, TMBSL_ERR_HDMI_INIT_FAILED)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM(uHwAddress < HDMITX_SLAVE_ADDRESS_MIN)
++    RETIF_BADPARAM(uHwAddress > HDMITX_SLAVE_ADDRESS_MAX)
++    RETIF_BADPARAM(sysFuncWrite == (ptmbslHdmiTxSysFunc_t)0)
++    RETIF_BADPARAM(sysFuncRead == (ptmbslHdmiTxSysFunc_t)0)
++    /*RETIF_BADPARAM(sysFuncEdidRead == (ptmbslHdmiTxSysFuncEdid_t)0)*/ /*Previously on TDA9983*/
++    /*RETIF_BADPARAM(sysFuncTimer == (ptmbslHdmiTxSysFuncTimer_t)0)*/
++    RETIF_BADPARAM((bEdidAltAddr != True) && (bEdidAltAddr != False))
++    RETIF_BADPARAM(!IS_VALID_FMT(vinFmt))
++    RETIF_BADPARAM(pixRate >= HDMITX_PIXRATE_INVALID)
++
++    /* Set all Device Instance Structure members to default values */
++    lmemcpy(pDis, &kHdmiTxInstanceDefault, sizeof(*pDis));
++
++    /* Copy txUnit, uHwAddress, sysFuncWrite and sysFuncRead values to
++     * the defaulted Device Instance Structure BEFORE FIRST DEVICE ACCESS.
++     */
++    pDis->txUnit          = txUnit;
++#ifdef UNIT_TEST
++    /* Unit test build can't support 127 device sets of dummy registers, so use
++     * smaller range instead, indexed by unit number not I2C address */
++    pDis->uHwAddress      = (UInt8)txUnit;
++#else
++    /* Store actual I2C address */
++    pDis->uHwAddress      = uHwAddress;
++#endif
++    pDis->sysFuncWrite    = sysFuncWrite;
++    pDis->sysFuncRead     = sysFuncRead;
++    pDis->sysFuncEdidRead = sysFuncEdidRead;
++    pDis->sysFuncTimer    = sysFuncTimer;
++
++    /* IF the funcIntCallbacks array pointer is defined
++     * THEN for each funcIntCallbacks pointer that is not null:
++     * - Copy the pointer to the Device Instance Structure
++     *   funcIntCallbacks array.
++     */
++
++    for (i = 0; i < HDMITX_CALLBACK_INT_NUM; i++)
++    {
++        if ((funcIntCallbacks != (tmbslHdmiTxCallbackList_t *)0)
++            && (funcIntCallbacks->funcCallback[i] != (ptmbslHdmiTxCallback_t)0))
++        {
++            pDis->funcIntCallbacks[i] = funcIntCallbacks->funcCallback[i];
++        }
++        else
++        {
++            pDis->funcIntCallbacks[i] = (ptmbslHdmiTxCallback_t)0;
++        }
++    }
++
++    /* Set the EDID alternate address flag if needed*/
++    pDis->bEdidAlternateAddr = bEdidAltAddr;
++
++//*****************************************************************************************//
++//*****************************************************************************************//
++//**********************Enable HDMI and RxSense************************///
++
++       /* reset ENAMODS */
++        err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, 0x40);
++        RETIF_REG_FAIL(err)
++
++
++
++
++
++    /*Read data out of ENAMODS CEC Register */
++    err = getCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, &EnableModeMask);
++
++    /*Enable required modes*/
++    EnableModeMask |= E_MASKREG_CEC_ENAMODS_ena_hdmi; /*Enable HDMI Mode*/
++    EnableModeMask |= E_MASKREG_CEC_ENAMODS_ena_rxs;  /*Enable RxSense Mode*/
++    EnableModeMask &= ~E_MASKREG_CEC_ENAMODS_dis_fro; /* Enable FRO  */
++
++    /*Write data in ENAMODS CEC Register */
++     err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, EnableModeMask);
++
++     pDis->ePowerState = (tmbslHdmiTxPowerState_t) tmPowerOn;
++
++    /* Set the bInitialized flag to enable other APIs */
++    pDis->bInitialized = True;
++
++    /* Reset the device */
++    err = tmbslTDA9989Reset(txUnit);
++    RETIF(err != TM_OK, err)
++
++//***************************************************************************************//
++//****************Get Device Version and Capabilities************************************//
++    /* Read the device version register to uDeviceVersion in the
++     * Device Instance Structure
++     */
++    err = getHwRegister(pDis, E_REG_P00_VERSION_R, &regVal);
++    RETIF(err != TM_OK, err)
++
++    /* Copy N4 features bits to DIS */
++    pDis->uDeviceFeatures = regVal & 
++        (E_MASKREG_P00_VERSION_not_h | E_MASKREG_P00_VERSION_not_s);
++
++    pDis->uDeviceVersion = regVal;
++
++    /* Get MSB version Value*/
++    err = getHwRegister(pDis, E_REG_P00_VERSION_MSB_RW, &regVal);
++    RETIF(err != TM_OK, err)
++
++    /* Build Device Version Info */
++    val16Bits = regVal;
++    pDis->uDeviceVersion = pDis->uDeviceVersion | (val16Bits << 8);
++    val16Bits = pDis->uDeviceFeatures;
++    pDis->uDeviceVersion &= ~val16Bits;
++
++    if (pDis->uDeviceVersion != E_DEV_VERSION_LIST_END)
++    {
++        /* Search for the device version in the Supported Version 
++        * List in the Device Instance Structure.
++        */
++        for (i = 0, bFound = False; i < E_DEV_VERSION_LIST_NUM; i++)
++        {
++            if (pDis->uDeviceVersion == pDis->uSupportedVersions[i])
++            {
++                bFound = True;
++            }
++        }
++        if (bFound == False)
++        {
++            /* IF the device version is not found in the Supported Version List THEN 
++             * this driver component is not compatible with the device.*/
++            err = tmbslTDA9989Deinit(txUnit);
++            RETIF(err != TM_OK, err)
++            return TMBSL_ERR_HDMI_COMPATIBILITY;
++        }
++    }
++    else
++    {
++        /* Quit if version reads zero */
++        err = tmbslTDA9989Deinit(txUnit);
++        RETIF(err != TM_OK, err)
++        return TMBSL_ERR_HDMI_COMPATIBILITY;
++    }
++
++/***************************************************************************************/
++/************Set the BIAS_tmds Value (general control for Analogu module)***************/
++    regVal = HDMI_TX_VSWING_VALUE;
++
++    err = setHwRegister(pDis, E_REG_P02_ANA_GENERAL_RW, regVal);
++    RETIF(err != TM_OK, err)
++
++/*****************************************************************************************/
++/*****************************************************************************************/
++
++    /* Set the PLL before resetting the device */    
++    /* PLL registers common configuration */
++    err = setHwRegisterFieldTable(pDis, &kCommonPllCfg[0]);
++    RETIF_REG_FAIL(err)
++    
++    /*Reset 656_Alt bit in VIP_CONTROL_4 Register*/
++    err = setHwRegisterField( pDis, E_REG_P00_VIP_CNTRL_4_W, E_MASKREG_P00_VIP_CNTRL_4_656_alt, 0);
++
++    switch (vinFmt)
++    {
++    /* 480i or 576i video input format */
++    case HDMITX_VFMT_06_720x480i_60Hz:
++    case HDMITX_VFMT_07_720x480i_60Hz:
++    case HDMITX_VFMT_21_720x576i_50Hz:
++    case HDMITX_VFMT_22_720x576i_50Hz:
++        err = setHwRegisterFieldTable(pDis, &kVfmt480i576iPllCfg[0]);
++        RETIF_REG_FAIL(err)
++
++        switch (pixRate)
++        {
++        case HDMITX_PIXRATE_SINGLE:
++            /* Single edge mode, vinFmt 480i or 576i */
++            err = setHwRegisterFieldTable(pDis, &kSinglePrateVfmt480i576iPllCfg[0]);
++            RETIF_REG_FAIL(err)
++
++        break;
++        case HDMITX_PIXRATE_SINGLE_REPEATED:
++            /* Single repeated edge mode, vinFmt 480i or 576i */
++            err = setHwRegisterFieldTable(pDis, &kSrepeatedPrateVfmt480i576iPllCfg[0]);
++            RETIF_REG_FAIL(err)
++
++        break;
++        default:
++            /* Double edge mode doesn't exist for vinFmt 480i or 576i */
++            return(TMBSL_ERR_HDMI_INCONSISTENT_PARAMS);
++        }        
++        
++        break;
++        
++
++    /* Others video input format */
++    default:
++        err = setHwRegisterFieldTable(pDis, &kVfmtOtherPllCfg[0]);
++        RETIF_REG_FAIL(err)
++        
++        switch (pixRate)
++        {
++        case HDMITX_PIXRATE_SINGLE:
++            /* Single edge mode, vinFmt other than 480i or 576i */
++            err = setHwRegisterFieldTable(pDis, &kSinglePrateVfmtOtherPllCfg[0]);
++            RETIF_REG_FAIL(err)
++        break;
++        case HDMITX_PIXRATE_DOUBLE:
++            /* Double edge mode, vinFmt other than 480i or 576i */
++            err = setHwRegisterFieldTable(pDis, &kDoublePrateVfmtOtherPllCfg[0]);
++            RETIF_REG_FAIL(err)
++        break;
++        default:
++            /* Single repeated edge mode doesn't exist for other vinFmt */
++            return(TMBSL_ERR_HDMI_INCONSISTENT_PARAMS);
++        }     
++        break;
++        
++    }
++
++    /* DDC interface is disable for TDA9989 after reset, enable it */
++    err = setHwRegister(pDis, E_REG_P00_DDC_DISABLE_RW, 0x00);
++    RETIF(err != TM_OK, err)
++
++    /* Set clock speed of the DDC channel */ 
++
++    err = setHwRegister(pDis, E_REG_P12_TX3_RW, TDA19989_DDC_SPEED_FACTOR);
++    RETIF(err != TM_OK, err)
++
++    /* TDA19989 N1 only */
++    if (pDis->uDeviceVersion == E_DEV_VERSION_TDA19989) {
++
++      err = setHwRegisterField(pDis,
++                             E_REG_P00_I2C_MASTER_RW,
++                             E_MASKREG_P00_I2C_MASTER_dis_mm,
++                             0); /* 0: enable multi master mode */
++      RETIF_REG_FAIL(err)
++
++    } /* TDA19989 N1 only */
++
++
++    err = setCECHwRegister(pDis, E_REG_CEC_FRO_IM_CLK_CTRL_RW, E_MASKREG_CEC_FRO_IM_CLK_CTRL_ghost_dis | E_MASKREG_CEC_FRO_IM_CLK_CTRL_imclk_sel);
++    RETIF_REG_FAIL(err)
++
++    /* The DIS hotplug status is HDMITX_HOTPLUG_INVALID, so call the main 
++     * interrupt handler to read the current Hot Plug status and run any
++     * registered HPD callback before interrupts are enabled below */
++    //err = tmbslTDA9989HwHandleInterrupt(txUnit);
++    RETIF(err != TM_OK, err)
++
++    /* enable  sw _interrupt and  VS_interrupt for debug */
++    err = setHwRegister(pDis, E_REG_P00_INT_FLAGS_1_RW, 
++                        E_MASKREG_P00_INT_FLAGS_1_sw_int);
++
++    /* enable edid read */
++    err = setHwRegister(pDis, E_REG_P00_INT_FLAGS_2_RW, 
++                        E_MASKREG_P00_INT_FLAGS_2_edid_blk_rd);
++
++
++   /* Read HPD RXS level */
++    err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&regVal);
++    RETIF(err != TM_OK, err)
++
++    /* Read Hot Plug input status to know the actual level that caused the interrupt */
++    pDis->hotPlugStatus = (regVal & E_MASKREG_CEC_RXSHPDLEV_hpd_level) ?
++                HDMITX_HOTPLUG_ACTIVE : HDMITX_HOTPLUG_INACTIVE;
++
++    /*Read RXS_FIL status to know the actual level that caused the interrupt */
++    pDis->rxSenseStatus = (regVal & E_MASKREG_CEC_RXSHPDLEV_rxs_level) ?
++                 HDMITX_RX_SENSE_ACTIVE : HDMITX_RX_SENSE_INACTIVE;
++
++    /*Disable required Interrupts*/
++    err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, &EnableIntMask);
++    EnableIntMask |= E_MASKREG_CEC_RXSHPDINTENA_ena_rxs_int; /* Enable RxSense Interrupt*/
++    EnableIntMask |= E_MASKREG_CEC_RXSHPDINTENA_ena_hpd_int; /* Enable HPD Interrupt*/
++
++    /* Switch BSL State machine into UNINITIALIZED State */
++    setState(pDis, EV_INIT);
++
++    /*Write data in RXSHPD Register*/ 
++    err += setCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, EnableIntMask);
++    err += getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&int_level);
++
++    /* Enable HPD and RX sense IT after first call done by init function */
++    gMiscInterruptHpdRxEnable = True;
++
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989PowerGetState                                                   */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989PowerGetState
++(
++    tmUnitSelect_t            txUnit,
++    tmPowerState_t   *pePowerState
++)
++{
++    tmHdmiTxobject_t *pDis;   /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;    /* Error code */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM(pePowerState == (tmPowerState_t)0)
++
++    /*return parameter*/
++        *pePowerState = (tmPowerState_t) pDis->ePowerState;
++
++    return TM_OK;
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989PowerSetState                                                   */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989PowerSetState
++(
++    tmUnitSelect_t            txUnit,
++    tmPowerState_t            ePowerState
++)
++{
++    tmHdmiTxobject_t *pDis;                /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;                 /* Error code */
++    UInt8             RegVal = 0;          /* Local Variable */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    if (ePowerState == tmPowerOff) {
++        ePowerState = tmPowerStandby;
++    }
++
++
++    /* Check remaining parameters */
++    RETIF_BADPARAM((ePowerState != tmPowerStandby)
++                 &&(ePowerState != tmPowerSuspend)
++                 &&(ePowerState != tmPowerOn)
++                 )
++
++    if ((ePowerState == tmPowerStandby)&&(pDis->ePowerState != tmPowerStandby))
++    {
++        /*Disable HPD and RxSense Interrupts*/
++        err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, &RegVal);
++        RegVal &= ~E_MASKREG_CEC_RXSHPDINTENA_ena_hpd_int;
++        RegVal &= ~E_MASKREG_CEC_RXSHPDINTENA_ena_rxs_int;
++        err += setCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, RegVal);
++        err += getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&int_level);
++        RETIF_REG_FAIL(err)
++    
++        /* Disable if coming from ACTIVE */
++        if (pDis->ePowerState == tmPowerOn)
++        {
++
++            /* Disable audio and video ports */
++            err = setHwRegister(pDis,
++                                E_REG_P00_ENA_AP_RW,
++                                0x00);  /* 0: disable */
++            RETIF_REG_FAIL(err)
++
++
++                err = setHwRegister(pDis,
++                                    E_REG_P00_ENA_VP_0_RW,
++                                    0x00);  /* 0: disable */
++            RETIF_REG_FAIL(err)
++   
++                err = setHwRegister(pDis,
++                                    E_REG_P00_ENA_VP_1_RW,
++                                    0x00);  /* 0: disable */
++            RETIF_REG_FAIL(err)
++   
++                err = setHwRegister(pDis,
++                                    E_REG_P00_ENA_VP_2_RW,
++                                    0x00);  /* 0: disable */
++            RETIF_REG_FAIL(err)
++
++                /* Disable DDC */
++                err = setHwRegisterField(pDis,
++                                         E_REG_P00_DDC_DISABLE_RW,
++                                         E_MASKREG_P00_DDC_DISABLE_ddc_dis,
++                                         1); /* 1: disable */
++            RETIF_REG_FAIL(err);
++
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++            /* power down clocks */
++            tmbslTDA9989HdcpPowerDown(txUnit,True);
++            err = setHwRegisterField(pDis, E_REG_FEAT_POWER_DOWN,     \
++                                     E_MASKREG_FEAT_POWER_DOWN_all,   \
++                                     0x0F);
++#endif
++        }
++
++        /*Disable HDMI and RxSense Modes AND FRO if required*/
++        err = getCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, &RegVal);
++        RegVal &= ~E_MASKREG_CEC_ENAMODS_ena_hdmi; /* Reset HDMI Mode*/
++
++        err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, RegVal);
++        RETIF_REG_FAIL(err)
++
++        err = getCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, &RegVal);
++        RETIF_REG_FAIL(err)
++        RegVal |= E_MASKREG_CEC_ENAMODS_ena_hdmi; /* Set HDMI Mode*/
++        err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, RegVal);
++        RETIF_REG_FAIL(err)
++
++        err = getCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, &RegVal);
++        RegVal &= ~E_MASKREG_CEC_ENAMODS_ena_hdmi; /* Reset HDMI Mode*/
++
++        RegVal &= ~E_MASKREG_CEC_ENAMODS_ena_rxs;  /* Reset RxSense Mode*/
++
++
++        /* disable FRO */
++        RegVal |= E_MASKREG_CEC_ENAMODS_dis_fro;
++        err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, RegVal);
++        RETIF_REG_FAIL(err)
++  
++
++       /*Send STANDBY event to the BSL State Machine */
++       setState(pDis, EV_STANDBY);
++    }
++    else if ((ePowerState == tmPowerSuspend)&&(pDis->ePowerState != tmPowerSuspend))
++    {
++
++       /* Disable if coming from ACTIVE */
++        if (pDis->ePowerState == tmPowerOn)
++        {
++            /* Disable audio and video ports */
++            err = setHwRegister(pDis,
++                                E_REG_P00_ENA_AP_RW,
++                                0x00);  /* 0: disable */
++            RETIF_REG_FAIL(err)
++
++
++                err = setHwRegister(pDis,
++                                    E_REG_P00_ENA_VP_0_RW,
++                                    0x00);  /* 0: disable */
++            RETIF_REG_FAIL(err)
++   
++                err = setHwRegister(pDis,
++                                    E_REG_P00_ENA_VP_1_RW,
++                                    0x00);  /* 0: disable */
++            RETIF_REG_FAIL(err)
++   
++                err = setHwRegister(pDis,
++                                    E_REG_P00_ENA_VP_2_RW,
++                                    0x00);  /* 0: disable */
++            RETIF_REG_FAIL(err);
++
++            /* Disable DDC */
++            err = setHwRegisterField(pDis,
++                                     E_REG_P00_DDC_DISABLE_RW,
++                                     E_MASKREG_P00_DDC_DISABLE_ddc_dis,
++                                     1); /* 1: disable */
++            RETIF_REG_FAIL(err);
++
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++            /* power down clocks */
++            tmbslTDA9989HdcpPowerDown(txUnit,True);
++            err = setHwRegisterField(pDis, E_REG_FEAT_POWER_DOWN,     \
++                                     E_MASKREG_FEAT_POWER_DOWN_all,   \
++                                     0x0F);
++#endif
++          }
++
++        /*Enable RxSense Mode and Disable HDMI Mode*/
++        err = getCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, &RegVal);
++        RegVal &= ~E_MASKREG_CEC_ENAMODS_ena_hdmi; /* Reset HDMI Mode*/
++        RegVal |= E_MASKREG_CEC_ENAMODS_ena_rxs;   /* Set RxSense Mode*/
++        err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, RegVal);
++        RETIF_REG_FAIL(err)
++
++        /*Enable HPD and RxS Interupt in case of the current Device Power States is STANDBY*/
++        /*In other cases, those interrupts have already been enabled*/
++        if(pDis->ePowerState == tmPowerStandby)
++        {
++           /* Enable FRO if coming from STANDBY */
++           err = getCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, &RegVal);
++           RegVal &= ~E_MASKREG_CEC_ENAMODS_dis_fro; /* Enable FRO  */
++           err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, RegVal);
++           RETIF_REG_FAIL(err)
++
++           /*Enable HPD and RxS Interupt*/
++           err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, &RegVal);
++           RegVal |= E_MASKREG_CEC_RXSHPDINTENA_ena_hpd_int; /* Enable HPD Interrupt*/
++           RegVal |= E_MASKREG_CEC_RXSHPDINTENA_ena_rxs_int; /* Enable RxSense Interrupt*/
++           err += setCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, RegVal);
++           err += getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&int_level);
++           RETIF_REG_FAIL(err)
++
++           /* force interrupt HPD and RXS level reading */
++           err = tmbslTDA9989HwHandleInterrupt(txUnit);
++           RETIF(err != TM_OK, err)
++
++
++        }
++
++        /*Send the SLEEP event to the BSL State Machine */
++        setState(pDis, EV_SLEEP);
++
++    }
++
++    else if ((ePowerState == tmPowerOn)&&(pDis->ePowerState != tmPowerOn))
++    {
++
++         /* Enable RxSense HDMI Modes */
++        err = getCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, &RegVal);
++        RegVal |= E_MASKREG_CEC_ENAMODS_ena_hdmi; /* Set HDMI Mode*/
++        RegVal |= E_MASKREG_CEC_ENAMODS_ena_rxs;  /* Set RxSense Mode*/
++        err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, RegVal);
++        RETIF_REG_FAIL(err)
++
++        /*Enable HPD and RxS Interupt in case of the current Device Power States is STANDBY*/
++        /*In other cases, those interrupts have already been enabled*/
++        if(pDis->ePowerState == tmPowerStandby)
++        {
++           /* Enable FRO if coming from STANDBY */
++           err = getCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, &RegVal);
++           RegVal &= ~E_MASKREG_CEC_ENAMODS_dis_fro; /* Enable FRO  */
++           err = setCECHwRegister(pDis, E_REG_CEC_ENAMODS_RW, RegVal);
++           RETIF_REG_FAIL(err)
++   
++   
++           /*Apply the required mode, Reset RxS and HDMI bits*/
++           err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, &RegVal);
++           RegVal |= E_MASKREG_CEC_RXSHPDINTENA_ena_hpd_int; /* Enable HPD Interrupt*/
++           RegVal |= E_MASKREG_CEC_RXSHPDINTENA_ena_rxs_int; /* Enable RxSense Interrupt*/
++           err += setCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, RegVal);
++           err += getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&int_level);
++           RETIF_REG_FAIL(err)
++        }
++
++
++        /* Restore BIAS TMDS */
++        RegVal = HDMI_TX_VSWING_VALUE;
++        err = setHwRegister(pDis, E_REG_P02_ANA_GENERAL_RW, RegVal);
++        RETIF(err != TM_OK, err)
++
++
++    err = tmbslTDA9989Reset(txUnit);
++    RETIF(err != TM_OK, err)
++
++
++    err = setHwRegisterField( pDis, E_REG_P00_VIP_CNTRL_4_W, E_MASKREG_P00_VIP_CNTRL_4_656_alt, 0);
++
++    err = setHwRegister(pDis, E_REG_P12_TX3_RW, TDA19989_DDC_SPEED_FACTOR);
++    RETIF(err != TM_OK, err)
++
++    /* TDA19989 N1 only */
++    if (pDis->uDeviceVersion == E_DEV_VERSION_TDA19989) {
++
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_I2C_MASTER_RW,
++                             E_MASKREG_P00_I2C_MASTER_dis_mm,
++                             0); 
++    RETIF_REG_FAIL(err)
++
++    } /* TDA19989 N1 only */
++
++    err = setCECHwRegister(pDis, E_REG_CEC_FRO_IM_CLK_CTRL_RW, E_MASKREG_CEC_FRO_IM_CLK_CTRL_ghost_dis | E_MASKREG_CEC_FRO_IM_CLK_CTRL_imclk_sel);
++    RETIF_REG_FAIL(err)
++
++#ifdef TMFL_HDCP_SUPPORT
++    if (pDis->HdcpSeed) {
++        err = tmbslTDA9989HdcpDownloadKeys(txUnit, pDis->HdcpSeed, HDMITX_HDCP_DECRYPT_ENABLE);
++    }
++#endif /* TMFL_HDCP_SUPPORT */
++
++
++       /* Enable DDC */
++        err = setHwRegisterField(pDis,
++                                 E_REG_P00_DDC_DISABLE_RW,
++                                 E_MASKREG_P00_DDC_DISABLE_ddc_dis,
++                                 0); /* 0: enable */
++        RETIF_REG_FAIL(err)
++
++       /* Enable audio and video ports */
++        err = setHwRegister(pDis,
++                           E_REG_P00_ENA_AP_RW,
++                           0xFF);  /* 1: enable */
++        RETIF_REG_FAIL(err)
++
++
++        err = setHwRegister(pDis,
++                           E_REG_P00_ENA_VP_0_RW,
++                           0xFF);  /* 1: enable */
++        RETIF_REG_FAIL(err)
++   
++        err = setHwRegister(pDis,
++                           E_REG_P00_ENA_VP_1_RW,
++                           0xFF);  /* 1: enable */
++        RETIF_REG_FAIL(err)
++   
++        err = setHwRegister(pDis,
++                           E_REG_P00_ENA_VP_2_RW,
++                           0xFF);  /* 1: enable */
++        RETIF_REG_FAIL(err)
++
++
++        /*Send the Hot Plug detection status event to the BSL State Machine */
++        if (pDis->hotPlugStatus == HDMITX_HOTPLUG_ACTIVE)
++        {
++            setState(pDis, EV_PLUGGEDIN);
++        }
++        else
++        {
++            setState(pDis, EV_UNPLUGGED);
++        }
++
++    }
++ 
++    /* Set the current Device Power status to the required Power Status */
++    pDis->ePowerState = (tmbslHdmiTxPowerState_t) ePowerState;
++
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989Reset                                                           */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989Reset
++(
++    tmUnitSelect_t      txUnit
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to its object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Reset I2C master and Audio*/
++    (void)setHwRegisterField(pDis, E_REG_P00_SR_REG_W,
++                             E_MASKREG_P00_SR_REG_sr_i2c_ms | 
++                             E_MASKREG_P00_SR_REG_sr_audio, 1);
++
++    pDis->sysFuncTimer(50); /* ms */
++
++   (void)setHwRegisterField(pDis, E_REG_P00_SR_REG_W,
++                             E_MASKREG_P00_SR_REG_sr_i2c_ms | 
++                             E_MASKREG_P00_SR_REG_sr_audio, 0);
++
++    pDis->sysFuncTimer(50); /* ms */
++
++    /* Write to the transmitter to do a soft reset. Don't abort after any
++     * error here, to ensure full reset.
++     */
++    (void)setHwRegisterField(pDis, E_REG_P00_MAIN_CNTRL0_RW,
++                             E_MASKREG_P00_MAIN_CNTRL0_sr, 1);
++    /* pDis->sysFuncTimer(50); */ /* ms */
++    (void)setHwRegisterField(pDis, E_REG_P00_MAIN_CNTRL0_RW,
++                             E_MASKREG_P00_MAIN_CNTRL0_sr, 0);
++    /* pDis->sysFuncTimer(50); */ /* ms */
++    /* Clear any colourbars */
++    (void)setHwRegisterField(pDis, E_REG_P00_HVF_CNTRL_0_W,
++                             E_MASKREG_P00_HVF_CNTRL_0_sm, 0);
++
++#ifdef TMFL_HDCP_SUPPORT
++    /* Disable any scheduled function and HDCP check timer */
++    pDis->HdcpFuncRemainingMs = 0;
++    pDis->HdcpCheckNum = 0;
++#endif /* TMFL_HDCP_SUPPORT */
++
++    /* Switch BSL State machine into UNINITIALIZED State */
++    setState(pDis, EV_DEINIT);
++    /* Switch Power State into STAND_BY State */
++    //pDis->ePowerState = tmPowerStandby;
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989SwGetVersion                                                    */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989SwGetVersion 
++(
++    ptmSWVersion_t      pSWVersion
++)
++{
++    /* Check parameters */
++    RETIF_BADPARAM(pSWVersion == (ptmSWVersion_t)0)
++
++    /* Get the version details of the component. */
++    pSWVersion->compatibilityNr = HDMITX_BSL_COMP_NUM;
++    pSWVersion->majorVersionNr  = HDMITX_BSL_MAJOR_VER;
++    pSWVersion->minorVersionNr  = HDMITX_BSL_MINOR_VER;
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989SysTimerWait                                                    */
++/*============================================================================*/
++tmErrorCode_t   
++tmbslTDA9989SysTimerWait 
++(
++    tmUnitSelect_t      txUnit,
++    UInt16              waitMs
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Return if this device timer is not set up */
++    RETIF(!pDis->sysFuncTimer, TMBSL_ERR_HDMI_NOT_INITIALIZED)
++
++    /* Wait for the requested time */
++    pDis->sysFuncTimer(waitMs);
++
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989TestSetMode                                                     */
++/*============================================================================*/
++
++tmErrorCode_t
++tmbslTDA9989TestSetMode
++(
++    tmUnitSelect_t          txUnit,
++    tmbslHdmiTxTestMode_t   testMode,
++    tmbslHdmiTxTestState_t  testState
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++    /* Register used to activate a test */
++    UInt16            testReg = E_REG_P00_VIP_CNTRL_4_W; 
++    /* Register bitfield mask used */
++    UInt8             testMask = E_MASKREG_P00_VIP_CNTRL_4_tst_pat; 
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM(testMode  >= HDMITX_TESTMODE_INVALID)
++    RETIF_BADPARAM(testState >= HDMITX_TESTSTATE_INVALID)
++
++    /* Set the mode selected by testMode to the state indicated by testState */
++    switch (testMode)
++    {
++    case HDMITX_TESTMODE_PAT:
++        testReg  = E_REG_P00_VIP_CNTRL_4_W;
++        testMask = E_MASKREG_P00_VIP_CNTRL_4_tst_pat;
++        break;
++    case HDMITX_TESTMODE_656:
++        testReg  = E_REG_P00_VIP_CNTRL_4_W;
++        testMask = E_MASKREG_P00_VIP_CNTRL_4_tst_656;
++        break;
++    case HDMITX_TESTMODE_SERPHOE:
++        /*testReg  = E_REG_P02_TEST1_RW;
++        testMask = E_MASKREG_P02_TEST1_tstserphoe;*/
++        break;
++    case HDMITX_TESTMODE_NOSC:
++        testReg  = E_REG_P02_TEST1_RW;
++        testMask = E_MASKREG_P02_TEST1_tst_nosc;
++        break;
++    case HDMITX_TESTMODE_HVP:
++        /*testReg  = E_REG_P02_TEST1_RW;
++        testMask = E_MASKREG_P02_TEST1_tst_hvp;*/
++        break;
++    case HDMITX_TESTMODE_PWD:
++        /*testReg  = E_REG_P02_TEST2_RW;
++        testMask = E_MASKREG_P02_TEST2_pwd1v8;*/
++        break;
++    case HDMITX_TESTMODE_DIVOE:
++        /*testReg  = E_REG_P02_TEST2_RW;
++        testMask = E_MASKREG_P02_TEST2_divtestoe;*/
++        break;
++    case HDMITX_TESTMODE_INVALID:
++        break;
++    }
++    err = setHwRegisterField(pDis, testReg, testMask, (UInt8)testState);
++    return err;
++}
++
++/*============================================================================*/
++/**
++    \brief Fill Gamut metadata packet into one of the gamut HW buffer. this
++           function is not sending any gamut metadata into the HDMI stream,
++           it is only loading data into the HW.
++
++    \param txUnit Transmitter unit number
++    \param pPkt   pointer to the gamut packet structure
++    \param bufSel number of the gamut buffer to fill
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMBSL_ERR_BSLHDMIRX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMBSL_ERR_BSLHDMIRX_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_BSLHDMIRX_I2C_WRITE: failed when writing to the I2C
++              bus
++
++ ******************************************************************************/
++tmErrorCode_t tmbslTDA9989PktFillGamut
++(
++    tmUnitSelect_t         txUnit,
++    tmbslHdmiTxPktGamut_t *pPkt,
++    UInt8                  bufSel
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM((bufSel != 0) && (bufSel != 1))
++
++    /* Fill Gamut registers*/
++    /*Fill buffer 0*/
++    if(bufSel == 0)
++    {
++        /*Write Header*/
++        err = setHwRegisters(pDis, E_REG_P13_GMD_0_HB0_RW, &pPkt->HB[0], 3);
++        RETIF(err != TM_OK, err)
++        /*Write Payload*/
++        err = setHwRegisters(pDis, E_REG_P13_GMD_0_PB0_RW, &pPkt->PB[0], 28);
++        RETIF(err != TM_OK, err)
++    }
++
++    /*Fill buffer 1*/
++    else 
++    {
++        /*Write Header*/
++        err = setHwRegisters(pDis, E_REG_P13_GMD_1_HB0_RW, &pPkt->HB[0], 3);
++        RETIF(err != TM_OK, err)
++         /*Write Payload*/
++        err = setHwRegisters(pDis, E_REG_P13_GMD_1_PB0_RW, &pPkt->PB[0], 28);
++        RETIF(err != TM_OK, err)
++    }
++
++return err;
++}
++
++/*============================================================================*/
++/**
++    \brief Enable transmission of gamut metadata packet. Calling this function
++           tells HW which gamut buffer to send into the HDMI stream. HW will
++           only take into account this command at the next VS, not during the
++           current one.
++
++    \param txUnit Transmitter unit number
++    \param bufSel Number of the gamut buffer to be sent
++    \param enable Enable/disable gamut packet transmission
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMBSL_ERR_BSLHDMIRX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMBSL_ERR_BSLHDMIRX_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_BSLHDMIRX_I2C_WRITE: failed when writing to the I2C
++              bus
++
++ ******************************************************************************/
++tmErrorCode_t tmbslTDA9989PktSendGamut
++(
++    tmUnitSelect_t         txUnit,
++    UInt8                  bufSel,
++    Bool                   bEnable
++)
++{
++    tmHdmiTxobject_t *pDis;           /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;            /* Error code */
++    UInt8             GMD_Ctrl_Val;   /*GMD control Value*/
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM((bufSel != 0) && (bufSel != 1))
++
++    /*Init Value*/
++    GMD_Ctrl_Val = 0x00;
++
++    /*Enable Send of Gamut MetaData*/
++    if(bEnable)
++    {
++        /*Send Buffer 0*/
++        if(bufSel == 0)
++        {
++            GMD_Ctrl_Val |= E_MASKREG_P13_GMD_CONTROL_enable;
++            GMD_Ctrl_Val &= ~E_MASKREG_P13_GMD_CONTROL_buf_sel;
++            err = setHwRegister(pDis, E_REG_P13_GMD_CONTROL_RW, GMD_Ctrl_Val);
++            RETIF(err != TM_OK, err)
++        }
++        /*Send Buffer 1*/
++        else
++        {
++            GMD_Ctrl_Val |= E_MASKREG_P13_GMD_CONTROL_enable;
++            GMD_Ctrl_Val |= E_MASKREG_P13_GMD_CONTROL_buf_sel;
++            err = setHwRegister(pDis, E_REG_P13_GMD_CONTROL_RW, GMD_Ctrl_Val);
++            RETIF(err != TM_OK, err)
++        }
++    }
++    /*Disable Send of Gamut MetaData*/
++    else
++    {
++        GMD_Ctrl_Val &= ~E_MASKREG_P13_GMD_CONTROL_enable;
++        GMD_Ctrl_Val &= ~E_MASKREG_P13_GMD_CONTROL_buf_sel;
++        err = setHwRegister(pDis, E_REG_P13_GMD_CONTROL_RW, GMD_Ctrl_Val);
++        RETIF(err != TM_OK, err)
++    }
++
++    return err;
++}
++
++
++
++
++/*============================================================================*/
++/* tmbslTDA9989EnableCallback                                                 */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989EnableCallback
++(
++    tmUnitSelect_t           txUnit,
++    tmbslHdmiTxCallbackInt_t callbackSource,
++    Bool                     enable
++)
++{
++    tmHdmiTxobject_t *pDis;           /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err = TM_OK;    /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM( callbackSource >= HDMITX_CALLBACK_INT_NUM )
++
++    switch (callbackSource)
++    {
++        case HDMITX_CALLBACK_INT_VS_RPT:
++            /* Enable or disable VS Interrupt */
++            err = setHwRegisterField(pDis, 
++                                     E_REG_P00_INT_FLAGS_1_RW,
++                                     E_MASKREG_P00_INT_FLAGS_1_vs_rpt,
++                                     (UInt8)enable);
++            if (enable)
++            {
++                pDis->InterruptsEnable |= (1 << callbackSource);
++            }
++            else
++            {
++                pDis->InterruptsEnable &= ~(1 << callbackSource);
++            }
++            break;
++        default:                      
++            err = TMBSL_ERR_HDMI_NOT_SUPPORTED;
++            break;
++    }
++    
++    return err;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989SetColorDepth                                                  */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989SetColorDepth
++(
++    tmUnitSelect_t        txUnit,
++    tmbslHdmiTxColorDepth colorDepth,
++    Bool                  termEnable
++)
++{
++    tmHdmiTxobject_t *pDis;           /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err = TM_OK;    /* Error code */
++
++    DUMMY_ACCESS(termEnable);
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Check parameters */
++    RETIF_BADPARAM( colorDepth >= HDMITX_COLORDEPTH_INVALID )
++
++    switch (colorDepth)
++    {
++        case HDMITX_COLORDEPTH_NO_CHANGE:
++            break;
++
++        case HDMITX_COLORDEPTH_24:
++
++            break;
++
++        default:                      
++            err = TMBSL_ERR_HDMI_NOT_SUPPORTED;
++            break;
++    }
++
++    return err;
++
++}
++
++
++/*============================================================================*/
++/* tmbslTDA9989Set5vpower                                                     */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989Set5vpower
++(
++    tmUnitSelect_t txUnit,
++    Bool           pwrEnable
++)
++{
++    tmHdmiTxobject_t *pDis;           /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;            /* Error code */
++
++    DUMMY_ACCESS(pwrEnable);
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++/*============================================================================*/
++/* tmbslTDA9989SetDefaultPhase                                                */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989SetDefaultPhase
++(
++    tmUnitSelect_t        txUnit,
++    Bool                  bEnable,
++    tmbslHdmiTxColorDepth colorDepth,
++    UInt8                 videoFormat
++)
++{
++    tmHdmiTxobject_t *pDis;           /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;            /* Error code */
++
++    DUMMY_ACCESS(bEnable);
++    DUMMY_ACCESS(colorDepth);
++    DUMMY_ACCESS(videoFormat);
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    return TMBSL_ERR_HDMI_NOT_SUPPORTED;
++}
++
++
++
++/*============================================================================*/
++/* tmbslDebugWriteFakeRegPage                                                 */
++/*============================================================================*/
++tmErrorCode_t tmbslDebugWriteFakeRegPage( tmUnitSelect_t txUnit )
++{
++    tmHdmiTxobject_t *pDis;           /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;            /* Error code */
++
++    err = checkUnitSetDis(txUnit, &pDis);
++
++    pDis->curRegPage = 0x20; 
++
++    return err;
++}
++
++
++/*============================================================================*/
++/* hotPlugRestore                                                             */
++/*============================================================================*/
++tmErrorCode_t hotPlugRestore ( tmUnitSelect_t txUnit )
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++    UInt8             regVal;
++    UInt8             EnableIntMask = 0;   /* Mask used to enable HPD and RX Sense interrupt*/
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Set the BIAS_tmds Value */
++    regVal = HDMI_TX_VSWING_VALUE;
++    err = setHwRegister(pDis, E_REG_P02_ANA_GENERAL_RW, regVal);
++    RETIF(err != TM_OK, err)
++
++    /* PLL registers common configuration */
++    err = setHwRegisterFieldTable(pDis, &kCommonPllCfg[0]);
++    RETIF_REG_FAIL(err)
++
++    /*Reset 656_Alt bit in VIP_CONTROL_4 Register*/
++    err = setHwRegisterField( pDis, E_REG_P00_VIP_CNTRL_4_W, E_MASKREG_P00_VIP_CNTRL_4_656_alt, 0);
++
++    /* DDC interface is disable for TDA9989 after reset, enable it */
++    err = setHwRegister(pDis, E_REG_P00_DDC_DISABLE_RW, 0x00);
++    RETIF(err != TM_OK, err)
++
++    err = setHwRegister(pDis, E_REG_P12_TX3_RW, TDA19989_DDC_SPEED_FACTOR);
++    RETIF(err != TM_OK, err)
++
++    /* TDA19989 N1 only */
++    if (pDis->uDeviceVersion == E_DEV_VERSION_TDA19989) {
++
++    err = setHwRegisterField(pDis,
++                             E_REG_P00_I2C_MASTER_RW,
++                             E_MASKREG_P00_I2C_MASTER_dis_mm,
++                             0); /* 0: enable multi master mode */
++    RETIF_REG_FAIL(err)
++
++    } /* TDA19989 N1 only */
++
++
++    err = setCECHwRegister(pDis, E_REG_CEC_FRO_IM_CLK_CTRL_RW, E_MASKREG_CEC_FRO_IM_CLK_CTRL_ghost_dis | E_MASKREG_CEC_FRO_IM_CLK_CTRL_imclk_sel);
++    RETIF_REG_FAIL(err)
++
++
++
++
++   /* enable sw_interrupt for debug */
++    err = setHwRegister(pDis, E_REG_P00_INT_FLAGS_1_RW, 
++                        E_MASKREG_P00_INT_FLAGS_1_sw_int);
++
++    /* enable edid read */
++    err = setHwRegister(pDis, E_REG_P00_INT_FLAGS_2_RW, 
++                        E_MASKREG_P00_INT_FLAGS_2_edid_blk_rd);
++
++    err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, &EnableIntMask);
++    EnableIntMask |= E_MASKREG_CEC_RXSHPDINTENA_ena_rxs_int; /* Enable RxSense Interrupt*/
++    EnableIntMask |= E_MASKREG_CEC_RXSHPDINTENA_ena_hpd_int; /* Enable HPD Interrupt*/
++    err += setCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, EnableIntMask);
++    err += getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&int_level);
++
++#ifdef TMFL_HDCP_SUPPORT
++
++	if (pDis->HdcpSeed)
++	{
++		err = tmbslTDA9989HdcpDownloadKeys(txUnit, pDis->HdcpSeed, HDMITX_HDCP_DECRYPT_ENABLE);
++	}
++
++#endif /* TMFL_HDCP_SUPPORT */
++
++    setState(pDis, EV_INIT);
++
++    return err;
++}
++
++#ifdef TMFL_TDA9989_PIXEL_CLOCK_ON_DDC
++
++tmErrorCode_t hotPlugRestore ( tmUnitSelect_t txUnit )
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++    UInt8             regVal;
++    UInt8             EnableIntMask = 0;   /* Mask used to enable HPD and RX Sense interrupt*/
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err)
++
++    /* Set the BIAS_tmds Value */
++    regVal = HDMI_TX_VSWING_VALUE;
++    err = setHwRegister(pDis, E_REG_P02_ANA_GENERAL_RW, regVal);
++    RETIF(err != TM_OK, err)
++
++    /* PLL registers common configuration */
++    err = setHwRegisterFieldTable(pDis, &kCommonPllCfg[0]);
++    RETIF_REG_FAIL(err)
++
++    /*Reset 656_Alt bit in VIP_CONTROL_4 Register*/
++    err = setHwRegisterField( pDis, E_REG_P00_VIP_CNTRL_4_W, E_MASKREG_P00_VIP_CNTRL_4_656_alt, 0);
++
++    /* DDC interface is disable for TDA9989 after reset, enable it */
++    err = setHwRegister(pDis, E_REG_P00_DDC_DISABLE_RW, 0x00);
++    RETIF(err != TM_OK, err)
++
++
++
++     if ( (pDis->vinFmt != HDMITX_VFMT_NO_CHANGE) && (pDis->vinFmt <= HDMITX_VFMT_TV_MAX ) ) {
++
++         err = setHwRegister(pDis, E_REG_P00_TIMER_H_W, 0);
++         RETIF(err != TM_OK, err)
++
++         err = setHwRegister(pDis, E_REG_P00_NDIV_IM_W, kndiv_im[pDis->vinFmt]);
++         RETIF(err != TM_OK, err)
++
++         err = setHwRegister(pDis, E_REG_P12_TX3_RW, kclk_div[pDis->vinFmt]);
++         RETIF(err != TM_OK, err)
++
++        }
++        else if (pDis->vinFmt > HDMITX_VFMT_TV_MAX) {
++
++            err = setHwRegister(pDis, E_REG_P00_TIMER_H_W, E_MASKREG_P00_TIMER_H_im_clksel);
++            RETIF(err != TM_OK, err)
++            err = setHwRegister(pDis, E_REG_P12_TX3_RW, 17);
++            RETIF(err != TM_OK, err)
++        }
++
++
++
++
++
++   /* enable sw_interrupt for debug */
++    err = setHwRegister(pDis, E_REG_P00_INT_FLAGS_1_RW, 
++                        E_MASKREG_P00_INT_FLAGS_1_sw_int);
++
++    /* enable edid read */
++    err = setHwRegister(pDis, E_REG_P00_INT_FLAGS_2_RW, 
++                        E_MASKREG_P00_INT_FLAGS_2_edid_blk_rd);
++
++    err = getCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, &EnableIntMask);
++    EnableIntMask |= E_MASKREG_CEC_RXSHPDINTENA_ena_rxs_int; /* Enable RxSense Interrupt*/
++    EnableIntMask |= E_MASKREG_CEC_RXSHPDINTENA_ena_hpd_int; /* Enable HPD Interrupt*/
++    err += setCECHwRegister(pDis, E_REG_CEC_RXSHPDINTENA_RW, EnableIntMask);
++    err += getCECHwRegister(pDis, E_REG_CEC_RXSHPDLEV_R,&int_level);
++
++    return err;
++}
++
++#endif /* TMFL_TDA9989_PIXEL_CLOCK_ON_DDC */
++
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++/*============================================================================*/
++/* tmbslTDA9989HdcpPowerDown                                                  */
++/* RETIF_REG_FAIL NOT USED HERE AS ALL ERRORS SHOULD BE TRAPPED IN ALL BUILDS */
++/*============================================================================*/
++tmErrorCode_t
++tmbslTDA9989HdcpPowerDown
++(
++    tmUnitSelect_t      txUnit,
++    Bool                requested
++)
++{
++    tmHdmiTxobject_t *pDis;       /* Pointer to Device Instance Structure */
++    tmErrorCode_t     err;        /* Error code */
++
++    /* Check unit parameter and point to TX unit object */
++    err = checkUnitSetDis(txUnit, &pDis);
++    RETIF(err != TM_OK, err);
++    
++    err = setHwRegisterField(pDis, E_REG_P12_TX4_RW, \
++                             E_MASKREG_P12_TX4_pd_all, \
++                             (requested?0x07:0x00));
++    return err;
++
++}
++#endif
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Misc_l.h b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Misc_l.h
+new file mode 100755
+index 0000000..990ee5c
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_Misc_l.h
+@@ -0,0 +1,62 @@
++/**
++ * Copyright (C) 2009 Koninklijke Philips Electronics N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of Koninklijke Philips Electronics N.V. and is confidential in
++ * nature. Under no circumstances is this software to be  exposed to or placed
++ * under an Open Source License of any type without the expressed written
++ * permission of Koninklijke Philips Electronics N.V.
++ *
++ * \file          tmbslTDA9989_Misc_l.h
++ *
++ * \version       $Revision: 2 $
++ *
++*/
++
++#ifndef TMBSLTDA9989_MISC_L_H
++#define TMBSLTDA9989_MISC_L_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       MACRO DEFINITIONS                                    */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                       EXTERN DATA DEFINITION                               */
++/*============================================================================*/
++
++#ifdef TMFL_TDA9989_PIXEL_CLOCK_ON_DDC
++extern    CONST_DAT UInt8 kndiv_im[];
++extern    CONST_DAT UInt8 kclk_div[];
++#endif /* TMFL_TDA9989_PIXEL_CLOCK_ON_DDC */
++
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++
++tmErrorCode_t hotPlugRestore ( tmUnitSelect_t  txUnit );
++
++#ifdef TMFL_TDA9989_PIXEL_CLOCK_ON_DDC
++tmErrorCode_t hotPlugRestore ( tmUnitSelect_t  txUnit );
++#endif /* TMFL_TDA9989_PIXEL_CLOCK_ON_DDC */
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMBSLTDA9989_MISC_L_H */
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_State.c b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_State.c
+new file mode 100755
+index 0000000..887f8e1
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_State.c
+@@ -0,0 +1,240 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_state.c
++ *
++ * \version       $Revision: 2 $
++ *
++*/
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#include <linux/kernel.h>
++#include <linux/module.h>
++#endif
++
++#include "tmbslTDA9989_Functions.h"
++#include "tmbslTDA9989_local.h"
++#include "tmbslTDA9989_State_l.h"
++
++
++/*============================================================================*/
++/*                     TYPES DECLARATIONS                                     */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS                               */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                       DEFINES DECLARATIONS                               */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                       VARIABLES DECLARATIONS                               */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                       FUNCTION PROTOTYPES                                  */
++/*============================================================================*/
++
++/*============================================================================*/
++/* setState                                                                   */
++/*============================================================================*/
++tmErrorCode_t
++setState
++(
++    tmHdmiTxobject_t   *pDis,
++    tmbslTDA9989Event_t  event
++)
++{
++    tmbslTDA9989State_t state = pDis->state;
++    UInt8 nIgnoredEvents = pDis->nIgnoredEvents;
++
++    switch (state)
++    {
++    case ST_UNINITIALIZED:
++        switch (event)
++        {
++        case EV_INIT:               state = ST_STANDBY;           break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_PLUGGEDIN:          state = ST_AWAIT_EDID;        break;
++        default:                    nIgnoredEvents++;             break;
++        }                                                               
++        break;
++
++    case ST_STANDBY:
++        switch (event)
++        {
++        case EV_UNPLUGGED:          state = ST_DISCONNECTED;      break; /*Only when PowerSetState(ON)*/
++        case EV_PLUGGEDIN:          state = ST_AWAIT_EDID;        break; /*Only when PowerSetState(ON)*/
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_SETINOUT:           state = ST_VIDEO_NO_HDCP;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++
++        default:                    nIgnoredEvents++;             break;
++        }                                                               
++        break; 
++    case ST_SLEEP:
++        switch (event)
++        {
++        case EV_UNPLUGGED:          state = ST_DISCONNECTED;      break; /*Only when PowerSetState(ON)*/
++        case EV_PLUGGEDIN:          state = ST_AWAIT_EDID;        break; /*Only when PowerSetState(ON)*/
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        default:                    nIgnoredEvents++;             break;
++        }                                                               
++        break;
++
++    case ST_DISCONNECTED:                                               
++        switch (event)                                                  
++        {                                                               
++        case EV_PLUGGEDIN:          state = ST_AWAIT_EDID;        break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        default:                    nIgnoredEvents++;             break;
++        }                                                               
++        break;                                                          
++    case ST_AWAIT_EDID:                                                 
++        switch (event)                                                  
++        {                                                               
++		case EV_GETBLOCKDATA:       state = ST_AWAIT_RX_SENSE;	  break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        case EV_UNPLUGGED:          state = ST_SLEEP;             break;
++        default:                    nIgnoredEvents++;             break;
++        }
++        break;
++
++    case ST_AWAIT_RX_SENSE:                                                 
++        switch (event)                                                  
++        {                                                               
++        case EV_SINKON:             state = ST_SINK_CONNECTED;    break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        case EV_UNPLUGGED:          state = ST_SLEEP;             break;
++        default:                    nIgnoredEvents++;             break;
++        }
++        break;
++
++    case ST_SINK_CONNECTED:
++        switch (event)
++        {
++        case EV_SETINOUT:           state = ST_VIDEO_NO_HDCP;     break;
++        case EV_SINKOFF:            state = ST_AWAIT_RX_SENSE;    break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        case EV_UNPLUGGED:          state = ST_SLEEP;             break;
++        default:                    nIgnoredEvents++;             break;
++        }                                                               
++        break;                                                          
++    case ST_VIDEO_NO_HDCP:                                              
++        switch (event)                                                  
++        {                                                               
++        case EV_OUTDISABLE:         state = ST_SINK_CONNECTED;    break;
++        case EV_HDCP_RUN:           state = ST_HDCP_WAIT_RX;      break;
++        case EV_SINKOFF:            state = ST_AWAIT_RX_SENSE;    break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        case EV_UNPLUGGED:          state = ST_SLEEP;             break;
++        default:                    nIgnoredEvents++;             break;
++        }                                                               
++        break;                                                          
++    case ST_HDCP_WAIT_RX:                                               
++        switch (event)                                                  
++        {                                                               
++        case EV_HDCP_BKSV_NREPEAT:  state = ST_HDCP_AUTHENTICATED;break;
++        case EV_HDCP_BKSV_REPEAT:   state = ST_HDCP_WAIT_BSTATUS; break;
++        case EV_HDCP_BKSV_NSECURE:  state = ST_HDCP_WAIT_RX;      break;
++        case EV_HDCP_T0:            state = ST_HDCP_WAIT_RX;      break;
++        case EV_HDCP_STOP:          state = ST_VIDEO_NO_HDCP;     break;
++        case EV_SINKOFF:            state = ST_AWAIT_RX_SENSE;    break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        case EV_UNPLUGGED:          state = ST_SLEEP;             break;
++        default:                    nIgnoredEvents++;             break;
++        }
++        break;
++    case ST_HDCP_WAIT_BSTATUS:
++        switch (event)
++        {
++        case EV_HDCP_BSTATUS_GOOD:  state = ST_HDCP_WAIT_SHA_1;   break;
++        case EV_HDCP_T0:            state = ST_HDCP_WAIT_RX;      break;
++        case EV_HDCP_STOP:          state = ST_VIDEO_NO_HDCP;     break;
++        case EV_SINKOFF:            state = ST_AWAIT_RX_SENSE;    break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        case EV_UNPLUGGED:          state = ST_SLEEP;             break;
++        default:                    nIgnoredEvents++;             break;
++        }
++        break;
++    case ST_HDCP_WAIT_SHA_1:
++        switch (event)
++        {
++        case EV_HDCP_KSV_SECURE:    state = ST_HDCP_AUTHENTICATED;break;
++        case EV_HDCP_T0:            state = ST_HDCP_WAIT_RX;      break;
++        case EV_HDCP_STOP:          state = ST_VIDEO_NO_HDCP;     break;
++        case EV_SINKOFF:            state = ST_AWAIT_RX_SENSE;    break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        case EV_UNPLUGGED:          state = ST_SLEEP;             break;
++        default:                    nIgnoredEvents++;             break;
++        }
++        break;
++    case ST_HDCP_AUTHENTICATED:
++        switch (event)
++        {
++        case EV_HDCP_T0:            state = ST_HDCP_WAIT_RX;      break;
++        case EV_HDCP_STOP:          state = ST_VIDEO_NO_HDCP;     break;
++        case EV_SINKOFF:            state = ST_AWAIT_RX_SENSE;    break;
++        case EV_DEINIT:             state = ST_UNINITIALIZED;     break;
++        case EV_STANDBY:            state = ST_STANDBY;           break;
++        case EV_SLEEP:              state = ST_SLEEP;             break;
++        case EV_UNPLUGGED:          state = ST_SLEEP;             break;
++        default:                    nIgnoredEvents++;             break;
++        }
++        break;
++    
++    case ST_INVALID:
++        nIgnoredEvents++;
++        break;
++
++    default:
++        break;
++    }
++
++    pDis->state = state;
++    pDis->nIgnoredEvents = nIgnoredEvents;
++
++    if (nIgnoredEvents)
++    {
++        /* int cbeDebug = 1; */
++    }
++
++    return TM_OK;
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(setState);
++#endif
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_State_l.h b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_State_l.h
+new file mode 100755
+index 0000000..c0e7857
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_State_l.h
+@@ -0,0 +1,56 @@
++/**
++ * Copyright (C) 2009 Koninklijke Philips Electronics N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of Koninklijke Philips Electronics N.V. and is confidential in
++ * nature. Under no circumstances is this software to be  exposed to or placed
++ * under an Open Source License of any type without the expressed written
++ * permission of Koninklijke Philips Electronics N.V.
++ *
++ * \file          tmbslTDA9989_State.h
++ *
++ * \version       $Revision: 2 $
++ *
++ *
++*/
++
++#ifndef TMBSLTDA9989_STATE_L_H
++#define TMBSLTDA9989_STATE_L_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       MACRO DEFINITIONS                                    */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++
++
++/*============================================================================*/
++/*                       EXTERN DATA DEFINITION                               */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++
++tmErrorCode_t    setState (tmHdmiTxobject_t *pDis, tmbslTDA9989Event_t event);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMBSLTDA9989_STATE_L_H */
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local.c b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local.c
+new file mode 100755
+index 0000000..9030ebc
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local.c
+@@ -0,0 +1,670 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_local.c
++ *
++ * \version       $Revision: 2 $
++ *
++ *
++*/
++
++/*============================================================================*/
++/*                   FILE CONFIGURATION                                       */
++/*============================================================================*/
++
++/* Defining this symbol on the compiler command line excludes some API checks */
++/* #define NO_RETIF_BADPARAM */
++
++/*============================================================================*/
++/*                   STANDARD INCLUDE FILES                                   */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                   PROJECT INCLUDE FILES                                    */
++/*============================================================================*/
++#include "tmbslHdmiTx_types.h"
++#include "tmbslTDA9989_Functions.h"
++#include "tmbslTDA9989_local.h"
++
++/*============================================================================*/
++/*                   MACRO DEFINITIONS                                        */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                   TYPE DEFINITIONS                                         */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                   PUBLIC VARIABLE DEFINITIONS                              */
++/*============================================================================*/
++
++/** The array of object instances for all concurrently supported HDMI 
++ *  Transmitter units
++ */
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#ifdef USE_SHARED_HDMI_INSTANCE
++extern tmHdmiTxobject_t gHdmiTxInstance[HDMITX_UNITS_MAX];
++#else
++#include <linux/kernel.h>
++#include <linux/module.h>
++RAM_DAT tmHdmiTxobject_t gHdmiTxInstance[HDMITX_UNITS_MAX];
++EXPORT_SYMBOL(gHdmiTxInstance);
++#endif
++#else
++RAM_DAT tmHdmiTxobject_t gHdmiTxInstance[HDMITX_UNITS_MAX];
++#endif
++
++/**
++ * Lookup table to map register page index to actual page number
++ */
++CONST_DAT UInt8 kPageIndexToPage[E_PAGE_NUM] =
++{
++    0x00,   /* E_PAGE_00 */
++    0x01,   /* E_PAGE_01 */
++    0x02,   /* E_PAGE_02 */
++    0x09,   /* E_PAGE_09 */
++    0x10,   /* E_PAGE_10 */
++    0x11,   /* E_PAGE_11 */
++    0x12,   /* E_PAGE_12 */
++    0x13    /* E_PAGE_13 */
++};
++
++
++/*============================================================================*/
++/*                   STATIC VARIABLE DECLARATIONS                             */
++/*============================================================================*/
++
++/**
++ * Lookup table to map an 8-bit mask to a number of left shifts
++ * needed to shift a value starting at bit 0 onto the mask.
++ * Indexed by mask 0-255. For example, mask 0x00 and 0x01 need
++ * no shift, mask 0x02 needs one shift, mask 0x03 needs no shift,
++ * mask 0x04 needs 2 shifts, etc.
++ * Rows were formatted by "HDMI Driver - Register List.xls" and pasted here
++ */
++static CONST_DAT UInt8 kMaskToShift[256] =
++{/* Mask index: */
++ /*x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF        */
++    0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 1x */
++    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 2x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 3x */
++    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 4x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 5x */
++    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 6x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 7x */
++    7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 8x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 9x */
++    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Ax */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Bx */
++    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Cx */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Dx */
++    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Ex */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0  /* Fx */
++};
++
++/*============================================================================*/
++/*                   STATIC FUNCTION DECLARATIONS                             */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                   PUBLIC FUNCTION DEFINITIONS                              */
++/*============================================================================*/
++
++/*============================================================================*/
++/* checkUnitSetDis                                                            */
++/*============================================================================*/
++tmErrorCode_t
++checkUnitSetDis
++(
++    tmUnitSelect_t   txUnit,
++    tmHdmiTxobject_t **ppDis
++)
++{
++    /* Return error if unit numbr is out of range */
++    RETIF(txUnit < tmUnit0, TMBSL_ERR_HDMI_BAD_UNIT_NUMBER)
++    RETIF(txUnit >= HDMITX_UNITS_MAX, TMBSL_ERR_HDMI_BAD_UNIT_NUMBER)
++
++    /* Point to unit's Device Instance Structure */
++    *ppDis = &gHdmiTxInstance[txUnit];
++
++    /* Return if this device instance is not initialised */
++    if(!(*ppDis)->bInitialized)
++    {
++        return TMBSL_ERR_HDMI_NOT_INITIALIZED;
++    }
++
++    return TM_OK;
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(checkUnitSetDis);
++#endif
++
++/*============================================================================*/
++/* getHwRegisters                                                             */
++/*============================================================================*/
++tmErrorCode_t
++getHwRegisters
++(
++    tmHdmiTxobject_t *pDis, 
++    UInt16 regShadPageAddr,
++    UInt8 *pData, 
++    UInt16 lenData
++    )
++{
++    tmErrorCode_t   err;        /* Error code */
++    UInt8           regShad;    /* The index to the register's shadow copy */
++    UInt8           regPage;    /* The index to the register's page        */
++    UInt8           regAddr;    /* The register's address on the page      */
++    UInt8           newRegPage; /* The register's new page number          */
++    tmbslHdmiTxSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Unpack 1st register's shadow index, page index and address */
++    regShad = SPA2SHAD(regShadPageAddr);
++    regPage = SPA2PAGE(regShadPageAddr);
++    regAddr = SPA2ADDR(regShadPageAddr);
++    newRegPage = kPageIndexToPage[regPage];
++    
++    /* Check length does not overflow page */
++    RETIF_BADPARAM((regAddr+lenData) > E_REG_CURPAGE_ADR_W)
++
++    /* Check 1st reg does not have a shadow - whole range assumed likewise */
++    RETIF_BADPARAM(regShad != E_SNONE)
++
++    /* Set page register if required */
++    if (pDis->curRegPage != newRegPage)
++    {
++        /* All non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = E_REG_CURPAGE_ADR_W;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = &newRegPage;
++        err = pDis->sysFuncWrite(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_WRITE)
++        pDis->curRegPage = newRegPage;
++    }
++
++    /* Get I2C register range - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->uHwAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = (UInt8)lenData;
++    sysArgs.pData           = pData;
++    err = pDis->sysFuncRead(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMBSL_ERR_HDMI_I2C_READ;
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(getHwRegisters);
++#endif
++
++/*============================================================================*/
++/* getHwRegister                                                              */
++/*============================================================================*/
++tmErrorCode_t
++getHwRegister
++(
++    tmHdmiTxobject_t *pDis, 
++    UInt16  regShadPageAddr, 
++    UInt8   *pRegValue
++)
++{
++    tmErrorCode_t   err;        /* Error code */
++    UInt8           regShad;    /* The index to the register's shadow copy */
++    UInt8           regPage;    /* The index to the register's page        */
++    UInt8           regAddr;    /* The register's address on the page      */
++    UInt8           newRegPage; /* The register's new page number          */
++    tmbslHdmiTxSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Unpack register shadow index, page index and address */
++    regShad = SPA2SHAD(regShadPageAddr);
++    regPage = SPA2PAGE(regShadPageAddr);
++    regAddr = SPA2ADDR(regShadPageAddr);
++    newRegPage = kPageIndexToPage[regPage];
++    
++    /* Set page register if required */
++    if (pDis->curRegPage != newRegPage)
++    {
++        /* All non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = E_REG_CURPAGE_ADR_W;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = &newRegPage;
++        err = pDis->sysFuncWrite(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_WRITE)
++        pDis->curRegPage = newRegPage;
++    }
++
++    if ((regShad != E_SNONE) 
++    && (regShadPageAddr != E_REG_P00_INT_FLAGS_0_RW)
++    && (regShadPageAddr != E_REG_P00_INT_FLAGS_1_RW)
++    && (regShadPageAddr != E_REG_P00_INT_FLAGS_2_RW))
++    {
++        /* Get shadow copy - shadowed registers can't be read */
++        /* Don't read shadow copy of interrupt status flags! */
++        *pRegValue = pDis->shadowReg[regShad];
++        return TM_OK;
++    }    
++    else
++    {
++        /* Get I2C register - all non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = regAddr;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = pRegValue;
++        err = pDis->sysFuncRead(&sysArgs);
++        return (err == TM_OK) ? TM_OK : TMBSL_ERR_HDMI_I2C_READ;
++    }
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(getHwRegister);
++#endif
++
++/*============================================================================*/
++/* setHwRegisters                                                             */
++/*============================================================================*/
++tmErrorCode_t
++setHwRegisters
++(
++    tmHdmiTxobject_t *pDis, 
++    UInt16 regShadPageAddr,
++    UInt8 *pData, 
++    UInt16 lenData
++    )
++{
++    tmErrorCode_t   err;        /* Error code */
++    UInt8           regShad;    /* The index to the register's shadow copy */
++    UInt8           regPage;    /* The index to the register's page        */
++    UInt8           regAddr;    /* The register's address on the page      */
++    UInt8           newRegPage; /* The register's new page number          */
++    tmbslHdmiTxSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Unpack 1st register's shadow index, page index and address */
++    regShad = SPA2SHAD(regShadPageAddr);
++    regPage = SPA2PAGE(regShadPageAddr);
++    regAddr = SPA2ADDR(regShadPageAddr);
++    newRegPage = kPageIndexToPage[regPage];
++    
++    /* Check length does not overflow page */
++    RETIF_BADPARAM((regAddr+lenData) > E_REG_CURPAGE_ADR_W)
++
++    /* Check 1st reg does not have a shadow - whole range assumed likewise */
++    RETIF_BADPARAM(regShad != E_SNONE)
++
++    /* Set page register if required - whole range is on same page */
++    if (pDis->curRegPage != newRegPage)
++    {
++        /* All non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = E_REG_CURPAGE_ADR_W;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = &newRegPage;
++        err = pDis->sysFuncWrite(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_WRITE)
++        pDis->curRegPage = newRegPage;
++    }
++
++    /* Write to I2C register range - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->uHwAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = (UInt8)lenData;
++    sysArgs.pData           = pData;
++    err = pDis->sysFuncWrite(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMBSL_ERR_HDMI_I2C_WRITE;
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(setHwRegisters);
++#endif
++
++
++/*============================================================================*/
++/* setHwRegisterMsbLsb                                                        */
++/*============================================================================*/
++tmErrorCode_t
++setHwRegisterMsbLsb
++(
++    tmHdmiTxobject_t *pDis, 
++    UInt16  regShadPageAddr, 
++    UInt16  regWord
++)
++{
++    tmErrorCode_t   err;        /* Error code */
++    UInt8           regPage;    /* The index to the register's page        */
++    UInt8           regAddr;    /* The register's address on the page      */
++    UInt8           newRegPage; /* The register's new page number          */
++    UInt8           msbLsb[2];  /* The bytes from regWord                  */
++    tmbslHdmiTxSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Unpack register shadow index, page index and address */
++    regPage = SPA2PAGE(regShadPageAddr);
++    regAddr = SPA2ADDR(regShadPageAddr);
++    newRegPage = kPageIndexToPage[regPage];
++
++    /* Unpack regWord bytes, MSB first */
++    msbLsb[0] = (UInt8)(regWord >> 8);
++    msbLsb[1] = (UInt8)(regWord & 0xFF);
++
++    /* Set page register if required */
++    if (pDis->curRegPage != newRegPage)
++    {
++        /* All non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = E_REG_CURPAGE_ADR_W;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = &newRegPage;
++        err = pDis->sysFuncWrite(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_WRITE)
++        pDis->curRegPage = newRegPage;
++    }
++
++    /* No word registers are shadowed */
++    
++    /* Write to I2C - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->uHwAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = 2;
++    sysArgs.pData           = &msbLsb[0];
++    err = pDis->sysFuncWrite(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMBSL_ERR_HDMI_I2C_WRITE;
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(setHwRegisterMsbLsb);
++#endif
++
++/*============================================================================*/
++/* setHwRegister                                                              */
++/*============================================================================*/
++tmErrorCode_t
++setHwRegister_main
++(
++    tmHdmiTxobject_t *pDis, 
++    UInt16  regShadPageAddr, 
++    UInt8   regValue
++)
++{
++    tmErrorCode_t   err;        /* Error code */
++    UInt8           regShad;    /* The index to the register's shadow copy */
++    UInt8           regPage;    /* The index to the register's page        */
++    UInt8           regAddr;    /* The register's address on the page      */
++    UInt8           newRegPage; /* The register's new page number          */
++    tmbslHdmiTxSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Unpack register shadow index, page index and address */
++    regShad = SPA2SHAD(regShadPageAddr);
++    regPage = SPA2PAGE(regShadPageAddr);
++    regAddr = SPA2ADDR(regShadPageAddr);
++    newRegPage = kPageIndexToPage[regPage];
++    
++    /* Set page register if required */
++    if (pDis->curRegPage != newRegPage)
++    {
++        /* All non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = E_REG_CURPAGE_ADR_W;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = &newRegPage;
++        err = pDis->sysFuncWrite(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_WRITE)
++        pDis->curRegPage = newRegPage;
++    }
++
++    /* Set shadow copy */
++    if (regShad != E_SNONE)
++    {
++        pDis->shadowReg[regShad] = regValue;
++    }    
++    
++    /* Write to I2C - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->uHwAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = 1;
++    sysArgs.pData           = &regValue;
++    err = pDis->sysFuncWrite(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMBSL_ERR_HDMI_I2C_WRITE;
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(setHwRegister_main);
++#endif
++
++/*============================================================================*/
++/*  setHwRegisterField                                                        */
++/*============================================================================*/
++tmErrorCode_t
++setHwRegisterField
++(
++    tmHdmiTxobject_t *pDis, 
++    UInt16  regShadPageAddr, 
++    UInt8   fieldMask, 
++    UInt8   fieldValue
++)
++{
++    tmErrorCode_t   err;        /* Error code */
++    UInt8           regShad;    /* The index to the register's shadow copy */
++    UInt8           regPage;    /* The index to the register's page        */
++    UInt8           regAddr;    /* The register's address on the page      */
++    UInt8           newRegPage; /* The register's new page number          */
++    UInt8           regValue;   /* The register's current value            */
++    tmbslHdmiTxSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Unpack register shadow index, page index and address */
++    regShad = SPA2SHAD(regShadPageAddr);
++    regPage = SPA2PAGE(regShadPageAddr);
++    regAddr = SPA2ADDR(regShadPageAddr);
++    newRegPage = kPageIndexToPage[regPage];
++   
++    /* Set page register if required */
++    if (pDis->curRegPage != newRegPage)
++    {
++        /* All non-OK results are errors */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = E_REG_CURPAGE_ADR_W;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = &newRegPage;
++        err = pDis->sysFuncWrite(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_WRITE)
++        pDis->curRegPage = newRegPage;
++    }
++
++    if (regShad != E_SNONE)
++    {
++        /* Get shadow copy */
++        regValue = pDis->shadowReg[regShad];
++    }
++    else
++    {
++        /* Read I2C register value.
++         * All bitfield registers are either shadowed or can be read.
++         */
++        sysArgs.slaveAddr       = pDis->uHwAddress;
++        sysArgs.firstRegister   = regAddr;
++        sysArgs.lenData         = 1;
++        sysArgs.pData           = &regValue;
++        err = pDis->sysFuncRead(&sysArgs);
++        RETIF(err != TM_OK, TMBSL_ERR_HDMI_I2C_READ)
++    }
++
++    /* Reset register bits that are set in the mask */
++    regValue = regValue & (UInt8)(~fieldMask);
++
++    /* Shift the field value left to align its bits with the mask */
++    fieldValue <<= kMaskToShift[fieldMask];
++
++    /* Reset shifted field bits that are not set in the mask */
++    fieldValue &= fieldMask;
++
++    /* Set the shifted bitfield */
++    regValue |= fieldValue;
++
++    /* Set shadow copy */
++    if (regShad != E_SNONE)
++    {
++        pDis->shadowReg[regShad] = regValue;
++    }
++
++    /* Write to I2C - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->uHwAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = 1;
++    sysArgs.pData           = &regValue;
++    err = pDis->sysFuncWrite(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMBSL_ERR_HDMI_I2C_WRITE;
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(setHwRegisterField);
++#endif
++
++/*============================================================================*/
++/* getCECHwRegister                                                              */
++/*============================================================================*/
++tmErrorCode_t
++getCECHwRegister
++(
++    tmHdmiTxobject_t *pDis, 
++    UInt16  regAddr,
++    UInt8   *pRegValue
++)
++{
++    tmErrorCode_t   err;          /* Error code */
++    tmbslHdmiTxSysArgs_t sysArgs; /* Arguments passed to system function   */
++    UInt8           CECAddress;   /* CEC Address deduced from uHwAddress */
++
++    /*Convert HwAddress into CEC Address*/
++    CECAddress = pDis->uHwAddress;
++    CECAddress = CECAddress ^ 0x44; /*Convert address to obtain  the correspondance in CEC*/
++    /*CECAddress = ((~CECAddress & 0x44)||(CECAddress & 0xBB)); */
++    /*Prepare Write operation*/
++    sysArgs.slaveAddr       = CECAddress;
++    sysArgs.firstRegister   = (UInt8)regAddr;
++    sysArgs.lenData         = 1;
++    sysArgs.pData           = pRegValue;
++    
++    /*Read data in Chip*/ 
++    err = pDis->sysFuncRead(&sysArgs);     /* Call IC Read function*/
++
++    return (err == TM_OK) ? TM_OK : TMBSL_ERR_HDMI_I2C_READ;
++
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(getCECHwRegister);
++#endif
++
++/*============================================================================*/
++/* setCECHwRegister                                                           */
++/*============================================================================*/
++tmErrorCode_t
++setCECHwRegister
++(
++    tmHdmiTxobject_t *pDis, 
++    UInt16  regAddr, 
++    UInt8   regValue
++)
++{
++    tmErrorCode_t   err;          /* Error code */
++    tmbslHdmiTxSysArgs_t sysArgs; /* Arguments passed to system function   */
++    UInt8           CECAddress;   /* CEC Address deduced from uHwAddress */
++
++    /*Convert HwAddress into CEC Address*/
++    CECAddress = pDis->uHwAddress;
++    CECAddress = CECAddress ^ 0x44; /*Convert address to obtain  the correspondance in CEC*/
++    
++    /*Prepare Write operation*/
++    sysArgs.slaveAddr       = CECAddress;
++    sysArgs.firstRegister   = (UInt8)regAddr;
++    sysArgs.lenData         = 1;
++    sysArgs.pData           = &regValue;
++    
++    /*Write data in Chip*/ 
++    err = pDis->sysFuncWrite(&sysArgs);    /* Call IC Write function*/
++
++    return (err == TM_OK) ? TM_OK : TMBSL_ERR_HDMI_I2C_WRITE;
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(setCECHwRegister);
++#endif
++
++/*============================================================================*/
++/* setHwRegisterFieldTable                                                    */
++/*============================================================================*/
++tmErrorCode_t
++setHwRegisterFieldTable
++(
++    tmHdmiTxobject_t *pDis,
++    const tmHdmiTxRegMaskVal_t *pTable
++)
++{
++    tmErrorCode_t err; /* Error code */
++    Int           i;   /* Table index */
++
++    /* Set register, mask and value from table until terminator is reached */
++    for (i = 0; pTable[i].Reg > 0; i++)
++    {
++        err = setHwRegisterField(pDis, pTable[i].Reg, pTable[i].Mask, pTable[i].Val);
++        RETIF(err != TM_OK, err)
++    }
++    return TM_OK;
++}
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++EXPORT_SYMBOL(setHwRegisterFieldTable);
++#endif
++
++
++/*============================================================================*/
++/* lmemcpy                                                                     */
++/*============================================================================*/
++tmErrorCode_t
++lmemcpy
++(
++    void *pTable1,
++    const void * pTable2,
++    UInt Size
++)
++{
++    char *ptrSource = (char*) pTable1;
++    char *endSource = (char*)pTable1 + Size;
++    char *ptrDest = (char *)pTable2;
++
++    RETIF_BADPARAM(pTable1 == Null)
++    RETIF_BADPARAM(pTable2 == Null)
++
++    while (endSource > ptrSource)
++    {
++        *(ptrSource++) = *(ptrDest++);
++    }
++    return TM_OK;
++}
++
++/*============================================================================*/
++/* lmemset                                                                     */
++/*============================================================================*/
++tmErrorCode_t
++lmemset
++(
++    void *pTable1,
++    const UInt8 value,
++    UInt Size
++)
++{
++    char *ptrSource = (char*) pTable1;
++    char *endSource = (char*)pTable1 + Size;
++
++    RETIF_BADPARAM(pTable1 == Null)
++
++    while (endSource > ptrSource)
++    {
++        *(ptrSource++) = value;
++    }
++    return TM_OK;
++}
++
++/*============================================================================*/
++/*                   STATIC FUNCTION DEFINTIONS                               */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                     END OF FILE                                            */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local.h b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local.h
+new file mode 100755
+index 0000000..02843e2
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local.h
+@@ -0,0 +1,2056 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_local.h
++ *
++ * \version       %version: 3 %
++ *
++*/
++
++#ifndef TMBSLTDA9989_LOCAL_H
++#define TMBSLTDA9989_LOCAL_H
++#define setHwRegister(pDis, regShadPageAddr, regValue) setHwRegister_main(pDis, regShadPageAddr, regValue); printk("Setting " # regShadPageAddr "\n");
++
++/*
++
++                      INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       MACRO DEFINITIONS                                    */
++/*============================================================================*/
++#ifndef DUMMY_ACCESS
++#ifdef _WINDOWS
++#define DUMMY_ACCESS(x) x
++#else
++#define DUMMY_ACCESS(x)
++#endif
++#endif /* DUMMY_ACCESS */
++
++/** \name Versions
++ *  A group of macros to set the software component number and version
++ */
++/*@{*/
++/** Compatibility number */
++#define HDMITX_BSL_COMP_NUM             1
++
++/** Major software version 1 to 255 */
++#define HDMITX_BSL_MAJOR_VER            5
++
++/** Minor software version 0 to 9 */
++#define HDMITX_BSL_MINOR_VER            4
++/*@}*/
++
++/** \name ErrorChecks
++ *  A group of checks ensuring that public error codes match DVP standard errors
++ */
++/*@{*/
++/** SW interface compatibility error */
++#if TMBSL_ERR_HDMI_COMPATIBILITY != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_COMPATIBILITY)
++#error
++#endif
++
++/** SW major version error */
++#if TMBSL_ERR_HDMI_MAJOR_VERSION != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_MAJOR_VERSION)
++#error
++#endif
++
++/** SW component version error */
++#if TMBSL_ERR_HDMI_COMP_VERSION != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_COMP_VERSION)
++#error
++#endif
++
++/** Invalid device unit number */
++#if TMBSL_ERR_HDMI_BAD_UNIT_NUMBER != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_BAD_UNIT_NUMBER)
++#error
++#endif
++
++/** Invalid input parameter other than unit number */
++#if TMBSL_ERR_HDMI_BAD_PARAMETER != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_BAD_PARAMETER)
++#error
++#endif
++
++/** Inconsistent input parameters */
++#if TMBSL_ERR_HDMI_INCONSISTENT_PARAMS != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_INCONSISTENT_PARAMS)
++#error
++#endif
++
++/** Component is not initialized */
++#if TMBSL_ERR_HDMI_NOT_INITIALIZED != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_NOT_INITIALIZED)
++#error
++#endif
++
++/** Command not supported for current device */
++#if TMBSL_ERR_HDMI_NOT_SUPPORTED != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_NOT_SUPPORTED)
++#error
++#endif
++
++/** Initialization failed */
++#if TMBSL_ERR_HDMI_INIT_FAILED != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_INIT_FAILED)
++#error
++#endif
++
++/** Component is busy and cannot do a new operation */
++#if TMBSL_ERR_HDMI_BUSY != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_BUSY)
++#error
++#endif
++
++/** I2C read error */
++#if TMBSL_ERR_HDMI_I2C_READ != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_READ)
++#error
++#endif
++
++/** I2C write error */
++#if TMBSL_ERR_HDMI_I2C_WRITE != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_WRITE)
++#error
++#endif
++
++/** Assertion failure */
++#if TMBSL_ERR_HDMI_ASSERTION != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_ASSERTION)
++#error
++#endif
++
++/** Bad EDID block checksum */
++#if TMBSL_ERR_HDMI_INVALID_CHECKSUM != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_INVALID_STATE)
++#error
++#endif
++
++/** No connection to HPD pin */
++#if TMBSL_ERR_HDMI_NULL_CONNECTION != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_NULL_CONNECTION)
++#error
++#endif
++
++/** Not allowed in DVI mode */
++#if TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_OPERATION_NOT_PERMITTED)
++#error
++#endif
++
++/** Ressource not available*/
++#if TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE != \
++(TMBSL_ERR_HDMI_BASE + TM_ERR_NO_RESOURCES)
++#error
++#endif
++ 
++
++/*@}*/
++
++/**
++ * A macro to check a condition and if true return a result
++ */
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#include <linux/kernel.h>
++#define RETIF(cond, rslt)       if ((cond)){printk(KERN_INFO "%s %d\n",__func__,__LINE__);return (rslt);}
++#else
++#define RETIF(cond, rslt)       if ((cond)){return (rslt);}
++#endif
++
++/**
++ * A macro to check a condition and if true return 
++ * TMBSL_ERR_HDMI_BAD_PARAMETER.
++ * To save code space, it can be compiled out by defining NO_RETIF_BADPARAM on
++ * the compiler command line.
++ */
++#ifdef NO_RETIF_BADPARAM
++#define RETIF_BADPARAM(cond)
++#else
++#define RETIF_BADPARAM(cond)  if ((cond)){return TMBSL_ERR_HDMI_BAD_PARAMETER;}
++#endif
++
++/**
++ * A macro to check the result of a register API and if not TM_OK to return it.
++ * To save code space, it can be compiled out by defining NO_RETIF_REG_FAIL on
++ * the compiler command line.
++ */
++#ifdef NO_RETIF_REG_FAIL
++#define RETIF_REG_FAIL(result)
++#else
++#define RETIF_REG_FAIL(result)  if ((result) != TM_OK){return (result);}
++#endif
++
++/**
++ * Check the consistancy of BSL structure
++ */
++/* #define BSL_CONSISTANCY(_x_,_y_) do { \ */
++/* #if ((_x_) != (_y_) * (_x_)[0])    \ */
++/* #error "BSL HAS WRONG ARRAY SIZE"  \ */
++/* #endif \ */
++/*    } while (0) */
++
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++/**
++ * Driver events and states used for diagnosis
++ */
++typedef enum _tmbslTDA9989Event
++{
++    EV_DEINIT               = 0,
++    EV_INIT                 = 1,
++    EV_STANDBY              = 2,
++    EV_SLEEP                = 3,
++    EV_ON                   = 4,
++    EV_UNPLUGGED            = 5,
++    EV_PLUGGEDIN            = 6,
++    EV_RESUME_UNPLUGGED     = 7,
++    EV_RESUME_PLUGGEDIN     = 8,
++    EV_GETBLOCKDATA         = 9,
++    EV_SETINOUT             = 10,
++    EV_OUTDISABLE           = 11,
++    EV_HDCP_RUN             = 12,
++    EV_HDCP_BKSV_NREPEAT    = 13,
++    EV_HDCP_BKSV_NSECURE    = 14,
++    EV_HDCP_BKSV_REPEAT     = 15,
++    EV_HDCP_BSTATUS_GOOD    = 16,
++    EV_HDCP_KSV_SECURE      = 17,
++    EV_HDCP_T0              = 18,
++    EV_HDCP_STOP            = 19,
++    EV_SINKON               = 20,
++    EV_SINKOFF              = 21,
++    EV_INVALID              = 22
++} tmbslTDA9989Event_t;
++
++typedef enum _tmbslTDA9989State
++{
++    ST_UNINITIALIZED        = 0,
++    ST_STANDBY              = 1,
++    ST_SLEEP                = 2,
++    ST_DISCONNECTED         = 3,
++    ST_AWAIT_EDID           = 4,
++    ST_SINK_CONNECTED       = 5,
++    ST_VIDEO_NO_HDCP        = 6,
++    ST_HDCP_WAIT_RX         = 7,
++    ST_HDCP_WAIT_BSTATUS    = 8,
++    ST_HDCP_WAIT_SHA_1      = 9,
++    ST_HDCP_AUTHENTICATED   = 10,
++    ST_AWAIT_RX_SENSE       = 11,
++    ST_INVALID              = 12,
++    ST_NUM                  = 13
++} tmbslTDA9989State_t;
++
++/**
++ * An enum to index into the Device Instance Data shadowReg array
++ */
++enum _eShad
++{
++    E_SP00_INT_FLAGS_0  = 0,
++    E_SP00_INT_FLAGS_1  = 1,
++    E_SP00_INT_FLAGS_2  = 2,
++    E_SP00_VIP_CNTRL_0  = 3,
++    E_SP00_VIP_CNTRL_1  = 4,
++    E_SP00_VIP_CNTRL_2  = 5,
++    E_SP00_VIP_CNTRL_3  = 6,
++    E_SP00_VIP_CNTRL_4  = 7,
++    E_SP00_VIP_CNTRL_5  = 8,
++    E_SP00_MAT_CONTRL   = 9,
++    E_SP00_TBG_CNTRL_0  = 10,
++    E_SP00_TBG_CNTRL_1  = 11,
++    E_SP00_HVF_CNTRL_0  = 12,
++    E_SP00_HVF_CNTRL_1  = 13,
++    E_SP00_TIMER_H      = 14,
++    E_SP00_DEBUG_PROBE  = 15,
++    E_SP00_AIP_CLKSEL   = 16,
++    E_SP01_SC_VIDFORMAT = 17,
++    E_SP01_SC_CNTRL     = 18,
++    E_SP01_TBG_CNTRL_0  = 19,
++#ifdef TMFL_HDCP_SUPPORT
++    E_SP12_CTRL    = 20,
++    E_SP12_BCAPS   = 21,
++    E_SNUM              = 22,   /* Number of shadow registers */
++    E_SNONE             = 22    /* Index value indicating no shadow register */
++#else /* TMFL_HDCP_SUPPORT */
++    E_SNUM              = 20,   /* Number of shadow registers */
++    E_SNONE             = 20    /* Index value indicating no shadow register */
++#endif /* TMFL_HDCP_SUPPORT */
++};
++
++/**
++ * Page list
++ * These are indexes to the allowed register page numbers
++ */
++enum _ePage
++{
++    E_PAGE_00      = 0,
++    E_PAGE_01      = 1,
++    E_PAGE_02      = 2,
++    E_PAGE_09      = 3,
++    E_PAGE_10      = 4,
++    E_PAGE_11      = 5,
++    E_PAGE_12      = 6,
++    E_PAGE_13      = 7,
++    E_PAGE_NUM     = 8,         /* Number of pages */
++    E_PAGE_INVALID = 8          /* Index value indicating invalid page */
++};
++
++/**
++ * Macros to initialize and access the following register list enum _eReg
++ */
++/* Pack shadow index s, page index p and register address a into UInt16 */
++#define SPA(s,p,a)       (UInt16)(((s)<<11)|((p)<<8)|(a))
++/* Unpacks shadow index s from UInt16 */
++#define SPA2SHAD(spa)    (UInt8)((spa)>>11)
++/* Unpacks page index p from UInt16 */
++#define SPA2PAGE(spa)    (UInt8)(((spa)>>8)&0x0007)
++/* Unpacks register address a from UInt16 */
++#define SPA2ADDR(spa)    (UInt8)((spa)&0x00FF)
++
++/**
++ * Register list
++ *
++ * Each register symbol has these fields: E_REG_page_register_access
++ *
++ * The symbols have a 16-bit value as follows, including an index to
++ * the Device Instance Data shadowReg[] array:
++ *
++ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
++ * |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
++ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
++ * |  Shadow Index     |Page Index |       Register Address        |
++ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
++ *
++ */
++enum _eReg
++{
++    /*************************************************************************/
++    /** Rows formatted in "HDMI Driver - Register List.xls" and pasted here **/
++    /*************************************************************************/
++    E_REG_MIN_ADR                    = 0x00, /* First register on all pages   */
++    E_REG_CURPAGE_ADR_W              = 0xFF, /* Address register on all pages */
++    /*CEC Registers*/
++
++    E_REG_CEC_INTERRUPTSTATUS_R       = 0xEE,
++    E_REG_CEC_RXSHPDINTENA_RW         = 0xFC,
++    E_REG_CEC_RXSHPDINT_R             = 0xFD,
++    E_REG_CEC_RXSHPDLEV_R             = 0xFE,
++    E_REG_CEC_ENAMODS_RW              = 0xFF,
++    E_REG_CEC_FRO_IM_CLK_CTRL_RW      = 0xFB,
++
++    E_REG_P00_VERSION_R              = SPA(E_SNONE            , E_PAGE_00, 0x00),
++    E_REG_P00_MAIN_CNTRL0_RW         = SPA(E_SNONE            , E_PAGE_00, 0x01),
++    E_REG_P00_VERSION_MSB_RW         = SPA(E_SNONE            , E_PAGE_00, 0x02),
++    E_REG_P00_PACKAGE_TYPE_R         = SPA(E_SNONE            , E_PAGE_00, 0x03),
++    E_REG_P00_SR_REG_W               = SPA(E_SNONE            , E_PAGE_00, 0x0A),
++    E_REG_P00_DDC_DISABLE_RW         = SPA(E_SNONE            , E_PAGE_00, 0x0B),
++    E_REG_P00_CCLK_ON_RW             = SPA(E_SNONE            , E_PAGE_00, 0x0C),
++    E_REG_P00_I2C_MASTER_RW          = SPA(E_SNONE            , E_PAGE_00, 0x0D),
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++    E_REG_FEAT_POWER_DOWN            = SPA(E_SNONE            , E_PAGE_00, 0x0E),
++#endif
++
++    E_REG_P00_INT_FLAGS_0_RW         = SPA(E_SP00_INT_FLAGS_0 , E_PAGE_00, 0x0F),
++    E_REG_P00_INT_FLAGS_1_RW         = SPA(E_SP00_INT_FLAGS_1 , E_PAGE_00, 0x10),
++    E_REG_P00_INT_FLAGS_2_RW         = SPA(E_SP00_INT_FLAGS_2 , E_PAGE_00, 0x11),
++    /*E_REG_P00_INT_FLAGS_3_R          = SPA(E_SNONE            , E_PAGE_00, 0x12),*/
++    E_REG_P00_SW_INT_W               = SPA(E_SNONE            , E_PAGE_00, 0x15),
++    E_REG_P00_ENA_ACLK_RW            = SPA(E_SNONE            , E_PAGE_00, 0x16),
++    E_REG_P00_ENA_VP_0_RW            = SPA(E_SNONE            , E_PAGE_00, 0x18),
++    E_REG_P00_ENA_VP_1_RW            = SPA(E_SNONE            , E_PAGE_00, 0x19),
++    E_REG_P00_ENA_VP_2_RW            = SPA(E_SNONE            , E_PAGE_00, 0x1A),
++    E_REG_P00_ENA_AP_RW              = SPA(E_SNONE            , E_PAGE_00, 0x1E),
++    E_REG_P00_VIP_CNTRL_0_W          = SPA(E_SP00_VIP_CNTRL_0 , E_PAGE_00, 0x20),
++    E_REG_P00_VIP_CNTRL_1_W          = SPA(E_SP00_VIP_CNTRL_1 , E_PAGE_00, 0x21),
++    E_REG_P00_VIP_CNTRL_2_W          = SPA(E_SP00_VIP_CNTRL_2 , E_PAGE_00, 0x22),
++    E_REG_P00_VIP_CNTRL_3_W          = SPA(E_SP00_VIP_CNTRL_3 , E_PAGE_00, 0x23),
++    E_REG_P00_VIP_CNTRL_4_W          = SPA(E_SP00_VIP_CNTRL_4 , E_PAGE_00, 0x24),
++    E_REG_P00_VIP_CNTRL_5_W          = SPA(E_SP00_VIP_CNTRL_5 , E_PAGE_00, 0x25),
++    E_REG_P00_MUX_AP_RW              = SPA(E_SNONE            , E_PAGE_00, 0x26),
++    E_REG_P00_MUX_VP_VIP_OUT_RW      = SPA(E_SNONE            , E_PAGE_00, 0x27),
++    E_REG_P00_MAT_CONTRL_W           = SPA(E_SP00_MAT_CONTRL  , E_PAGE_00, 0x80),
++    E_REG_P00_MAT_OI1_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x81),
++    E_REG_P00_MAT_OI1_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x82),
++    E_REG_P00_MAT_OI2_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x83),
++    E_REG_P00_MAT_OI2_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x84),
++    E_REG_P00_MAT_OI3_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x85),
++    E_REG_P00_MAT_OI3_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x86),
++    E_REG_P00_MAT_P11_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x87),
++    E_REG_P00_MAT_P11_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x88),
++    E_REG_P00_MAT_P12_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x89),
++    E_REG_P00_MAT_P12_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x8A),
++    E_REG_P00_MAT_P13_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x8B),
++    E_REG_P00_MAT_P13_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x8C),
++    E_REG_P00_MAT_P21_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x8D),
++    E_REG_P00_MAT_P21_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x8E),
++    E_REG_P00_MAT_P22_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x8F),
++    E_REG_P00_MAT_P22_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x90),
++    E_REG_P00_MAT_P23_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x91),
++    E_REG_P00_MAT_P23_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x92),
++    E_REG_P00_MAT_P31_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x93),
++    E_REG_P00_MAT_P31_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x94),
++    E_REG_P00_MAT_P32_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x95),
++    E_REG_P00_MAT_P32_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x96),
++    E_REG_P00_MAT_P33_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x97),
++    E_REG_P00_MAT_P33_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x98),
++    E_REG_P00_MAT_OO1_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x99),
++    E_REG_P00_MAT_OO1_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x9A),   
++    E_REG_P00_MAT_OO2_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x9B),
++    E_REG_P00_MAT_OO2_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x9C),
++    E_REG_P00_MAT_OO3_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x9D),
++    E_REG_P00_MAT_OO3_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0x9E),
++    E_REG_P00_VIDFORMAT_W            = SPA(E_SNONE            , E_PAGE_00, 0xA0),
++    E_REG_P00_REFPIX_MSB_W           = SPA(E_SNONE            , E_PAGE_00, 0xA1),
++    E_REG_P00_REFPIX_LSB_W           = SPA(E_SNONE            , E_PAGE_00, 0xA2),
++    E_REG_P00_REFLINE_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0xA3),
++    E_REG_P00_REFLINE_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0xA4),
++    E_REG_P00_NPIX_MSB_W             = SPA(E_SNONE            , E_PAGE_00, 0xA5),
++    E_REG_P00_NPIX_LSB_W             = SPA(E_SNONE            , E_PAGE_00, 0xA6),
++    E_REG_P00_NLINE_MSB_W            = SPA(E_SNONE            , E_PAGE_00, 0xA7),
++    E_REG_P00_NLINE_LSB_W            = SPA(E_SNONE            , E_PAGE_00, 0xA8),
++    E_REG_P00_VS_LINE_STRT_1_MSB_W   = SPA(E_SNONE            , E_PAGE_00, 0xA9),
++    E_REG_P00_VS_LINE_STRT_1_LSB_W   = SPA(E_SNONE            , E_PAGE_00, 0xAA),
++    E_REG_P00_VS_PIX_STRT_1_MSB_W    = SPA(E_SNONE            , E_PAGE_00, 0xAB),
++    E_REG_P00_VS_PIX_STRT_1_LSB_W    = SPA(E_SNONE            , E_PAGE_00, 0xAC),
++    E_REG_P00_VS_LINE_END_1_MSB_W    = SPA(E_SNONE            , E_PAGE_00, 0xAD),
++    E_REG_P00_VS_LINE_END_1_LSB_W    = SPA(E_SNONE            , E_PAGE_00, 0xAE),
++    E_REG_P00_VS_PIX_END_1_MSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xAF),
++    E_REG_P00_VS_PIX_END_1_LSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xB0),
++    E_REG_P00_VS_LINE_STRT_2_MSB_W   = SPA(E_SNONE            , E_PAGE_00, 0xB1),
++    E_REG_P00_VS_LINE_STRT_2_LSB_W   = SPA(E_SNONE            , E_PAGE_00, 0xB2),
++    E_REG_P00_VS_PIX_STRT_2_MSB_W    = SPA(E_SNONE            , E_PAGE_00, 0xB3),
++    E_REG_P00_VS_PIX_STRT_2_LSB_W    = SPA(E_SNONE            , E_PAGE_00, 0xB4),
++    E_REG_P00_VS_LINE_END_2_MSB_W    = SPA(E_SNONE            , E_PAGE_00, 0xB5),
++    E_REG_P00_VS_LINE_END_2_LSB_W    = SPA(E_SNONE            , E_PAGE_00, 0xB6),
++    E_REG_P00_VS_PIX_END_2_MSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xB7),
++    E_REG_P00_VS_PIX_END_2_LSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xB8),
++    E_REG_P00_HS_PIX_START_MSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xB9),
++    E_REG_P00_HS_PIX_START_LSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xBA),
++    E_REG_P00_HS_PIX_STOP_MSB_W      = SPA(E_SNONE            , E_PAGE_00, 0xBB),
++    E_REG_P00_HS_PIX_STOP_LSB_W      = SPA(E_SNONE            , E_PAGE_00, 0xBC),
++    E_REG_P00_VWIN_START_1_MSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xBD),
++    E_REG_P00_VWIN_START_1_LSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xBE),
++    E_REG_P00_VWIN_END_1_MSB_W       = SPA(E_SNONE            , E_PAGE_00, 0xBF),
++    E_REG_P00_VWIN_END_1_LSB_W       = SPA(E_SNONE            , E_PAGE_00, 0xC0),
++    E_REG_P00_VWIN_START_2_MSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xC1),
++    E_REG_P00_VWIN_START_2_LSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xC2),
++    E_REG_P00_VWIN_END_2_MSB_W       = SPA(E_SNONE            , E_PAGE_00, 0xC3),
++    E_REG_P00_VWIN_END_2_LSB_W       = SPA(E_SNONE            , E_PAGE_00, 0xC4),
++    E_REG_P00_DE_START_MSB_W         = SPA(E_SNONE            , E_PAGE_00, 0xC5),
++    E_REG_P00_DE_START_LSB_W         = SPA(E_SNONE            , E_PAGE_00, 0xC6),
++    E_REG_P00_DE_STOP_MSB_W          = SPA(E_SNONE            , E_PAGE_00, 0xC7),
++    E_REG_P00_DE_STOP_LSB_W          = SPA(E_SNONE            , E_PAGE_00, 0xC8),
++    E_REG_P00_COLBAR_WIDTH_W         = SPA(E_SNONE            , E_PAGE_00, 0xC9),
++    E_REG_P00_TBG_CNTRL_0_W          = SPA(E_SP00_TBG_CNTRL_0 , E_PAGE_00, 0xCA),
++    E_REG_P00_TBG_CNTRL_1_W          = SPA(E_SP00_TBG_CNTRL_1 , E_PAGE_00, 0xCB),
++    E_REG_P00_VBL_OFFSET_START_W     = SPA(E_SNONE            , E_PAGE_00, 0xCC),
++    E_REG_P00_VBL_OFFSET_END_W       = SPA(E_SNONE            , E_PAGE_00, 0xCD),
++    E_REG_P00_HBL_OFFSET_START_W     = SPA(E_SNONE            , E_PAGE_00, 0xCE),
++    E_REG_P00_HBL_OFFSET_END_W       = SPA(E_SNONE            , E_PAGE_00, 0xCF),
++    E_REG_P00_DWIN_RE_DE_W           = SPA(E_SNONE            , E_PAGE_00, 0xD0),
++    E_REG_P00_DWIN_FE_DE_W           = SPA(E_SNONE            , E_PAGE_00, 0xD1),
++#ifdef TMFL_RGB_DDR_12BITS
++    E_REG_P00_VSPACE_START_MSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xD2),
++    E_REG_P00_VSPACE_START_LSB_W     = SPA(E_SNONE            , E_PAGE_00, 0xD3),
++    E_REG_P00_VSPACE_END_MSB_W       = SPA(E_SNONE            , E_PAGE_00, 0xD4),
++    E_REG_P00_VSPACE_END_LSB_W       = SPA(E_SNONE            , E_PAGE_00, 0xD5),
++    E_REG_P00_ENABLE_SPACE_W         = SPA(E_SNONE            , E_PAGE_00, 0xD6),
++    E_REG_P00_VSPACE_Y_DATA_W        = SPA(E_SNONE            , E_PAGE_00, 0xD7),
++    E_REG_P00_VSPACE_U_DATA_W        = SPA(E_SNONE            , E_PAGE_00, 0xD8),
++    E_REG_P00_VSPACE_V_DATA_W        = SPA(E_SNONE            , E_PAGE_00, 0xD9),
++#endif
++
++    E_REG_P00_TIMER_RI_PJ_RW         = SPA(E_SNONE            , E_PAGE_00, 0xE1),
++    E_REG_P00_BCAPS_POLL_RW          = SPA(E_SNONE            , E_PAGE_00, 0xE2),
++    E_REG_P00_100us_RW               = SPA(E_SNONE            , E_PAGE_00, 0xE3),
++
++    E_REG_P00_HVF_CNTRL_0_W          = SPA(E_SP00_HVF_CNTRL_0 , E_PAGE_00, 0xE4),
++    E_REG_P00_HVF_CNTRL_1_W          = SPA(E_SP00_HVF_CNTRL_1 , E_PAGE_00, 0xE5),       
++
++    E_REG_P00_TIMER_H_W              = SPA(E_SP00_TIMER_H     , E_PAGE_00, 0xE8),
++    E_REG_P00_TIMER_M_W              = SPA(E_SNONE            , E_PAGE_00, 0xE9),
++    E_REG_P00_TIMER_L_W              = SPA(E_SNONE            , E_PAGE_00, 0xEA),
++    E_REG_P00_TIMER_2SEC_W           = SPA(E_SNONE            , E_PAGE_00, 0xEB),
++    E_REG_P00_TIMER_5SEC_W           = SPA(E_SNONE            , E_PAGE_00, 0xEC),
++    E_REG_P00_NDIV_IM_W              = SPA(E_SNONE            , E_PAGE_00, 0xEE),
++    E_REG_P00_NDIV_PF_W              = SPA(E_SNONE            , E_PAGE_00, 0xEF),   
++    E_REG_P00_RPT_CNTRL_W            = SPA(E_SNONE            , E_PAGE_00, 0xF0),
++    E_REG_P00_LEAD_OFF_W             = SPA(E_SNONE            , E_PAGE_00, 0xF1),
++    E_REG_P00_TRAIL_OFF_W            = SPA(E_SNONE            , E_PAGE_00, 0xF2),
++    E_REG_P00_MISR_EXP_0_RW          = SPA(E_SNONE            , E_PAGE_00, 0xF3),
++    E_REG_P00_MISR_EXP_1_RW          = SPA(E_SNONE            , E_PAGE_00, 0xF4),
++    E_REG_P00_MISR_EXP_2_RW          = SPA(E_SNONE            , E_PAGE_00, 0xF5),
++    E_REG_P00_MISR_0_R               = SPA(E_SNONE            , E_PAGE_00, 0xF6),
++    E_REG_P00_MISR_1_R               = SPA(E_SNONE            , E_PAGE_00, 0xF7),                 
++    E_REG_P00_DEBUG_PROBE_W          = SPA(E_SP00_DEBUG_PROBE , E_PAGE_00, 0xF8),
++    E_REG_P00_GHOST_XADDR_W          = SPA(E_SNONE            , E_PAGE_00, 0xF9),
++    E_REG_P00_MISR_2_R               = SPA(E_SNONE            , E_PAGE_00, 0xFA),
++    E_REG_P00_I2S_FORMAT_RW          = SPA(E_SNONE            , E_PAGE_00, 0xFC),
++    E_REG_P00_AIP_CLKSEL_W           = SPA(E_SP00_AIP_CLKSEL  , E_PAGE_00, 0xFD),
++    E_REG_P00_GHOST_ADDR_W           = SPA(E_SNONE            , E_PAGE_00, 0xFE),
++    E_REG_P01_SC_VIDFORMAT_W         = SPA(E_SP01_SC_VIDFORMAT, E_PAGE_01, 0x00),
++
++    E_REG_P01_SC_CNTRL_W             = SPA(E_SP01_SC_CNTRL    , E_PAGE_01, 0x01),
++    E_REG_P01_SC_DELTA_PHASE_V_W     = SPA(E_SNONE            , E_PAGE_01, 0x02),
++    E_REG_P01_SC_DELTA_PHASE_H_W     = SPA(E_SNONE            , E_PAGE_01, 0x03),
++    E_REG_P01_SC_START_PHASE_H_W     = SPA(E_SNONE            , E_PAGE_01, 0x04),
++    E_REG_P01_SC_NPIX_IN_LSB_W       = SPA(E_SNONE            , E_PAGE_01, 0x05),
++    E_REG_P01_SC_NPIX_IN_MSB_W       = SPA(E_SNONE            , E_PAGE_01, 0x06),
++    E_REG_P01_SC_NPIX_OUT_LSB_W      = SPA(E_SNONE            , E_PAGE_01, 0x07),
++    E_REG_P01_SC_NPIX_OUT_MSB_W      = SPA(E_SNONE            , E_PAGE_01, 0x08),
++    E_REG_P01_SC_NLINE_IN_LSB_W      = SPA(E_SNONE            , E_PAGE_01, 0x09),
++    E_REG_P01_SC_NLINE_IN_MSB_W      = SPA(E_SNONE            , E_PAGE_01, 0x0A),
++    E_REG_P01_SC_NLINE_OUT_LSB_W     = SPA(E_SNONE            , E_PAGE_01, 0x0B),
++    E_REG_P01_SC_NLINE_OUT_MSB_W     = SPA(E_SNONE            , E_PAGE_01, 0x0C),
++    E_REG_P01_SC_NLINE_SKIP_W        = SPA(E_SNONE            , E_PAGE_01, 0x0D),   
++    E_REG_P01_SC_SAMPLE_BUFFILL_R    = SPA(E_SNONE            , E_PAGE_01, 0x0E),
++    E_REG_P01_SC_MAX_BUFFILL_P_0_R   = SPA(E_SNONE            , E_PAGE_01, 0x0F),
++    E_REG_P01_SC_MAX_BUFFILL_P_1_R   = SPA(E_SNONE            , E_PAGE_01, 0x10),
++    E_REG_P01_SC_MAX_BUFFILL_D_0_R   = SPA(E_SNONE            , E_PAGE_01, 0x11),
++    E_REG_P01_SC_MAX_BUFFILL_D_1_R   = SPA(E_SNONE            , E_PAGE_01, 0x12),
++    E_REG_P01_SC_SAMPLE_FIFOFILL_R   = SPA(E_SNONE            , E_PAGE_01, 0x13),
++    E_REG_P01_SC_MAX_FIFOFILL_PI_R   = SPA(E_SNONE            , E_PAGE_01, 0x14),
++    E_REG_P01_SC_MIN_FIFOFILL_PO1_R  = SPA(E_SNONE            , E_PAGE_01, 0x15),
++    E_REG_P01_SC_MIN_FIFOFILL_PO2_R  = SPA(E_SNONE            , E_PAGE_01, 0x16),
++    E_REG_P01_SC_MIN_FIFOFILL_PO3_R  = SPA(E_SNONE            , E_PAGE_01, 0x17),   
++    E_REG_P01_SC_MIN_FIFOFILL_PO4_R  = SPA(E_SNONE            , E_PAGE_01, 0x18),
++    E_REG_P01_SC_MAX_FIFOFILL_DI_R   = SPA(E_SNONE            , E_PAGE_01, 0x19),
++    E_REG_P01_SC_MAX_FIFOFILL_DO_R   = SPA(E_SNONE            , E_PAGE_01, 0x1A),
++    E_REG_P01_SC_VS_LUT_0_W          = SPA(E_SNONE            , E_PAGE_01, 0x1B),
++    E_REG_P01_SC_VS_LUT_1_W          = SPA(E_SNONE            , E_PAGE_01, 0x1C),
++    E_REG_P01_SC_VS_LUT_2_W          = SPA(E_SNONE            , E_PAGE_01, 0x1D),
++    E_REG_P01_SC_VS_LUT_3_W          = SPA(E_SNONE            , E_PAGE_01, 0x1E),
++    E_REG_P01_SC_VS_LUT_4_W          = SPA(E_SNONE            , E_PAGE_01, 0x1F),
++    E_REG_P01_SC_VS_LUT_5_W          = SPA(E_SNONE            , E_PAGE_01, 0x20),
++    E_REG_P01_SC_VS_LUT_6_W          = SPA(E_SNONE            , E_PAGE_01, 0x21),
++    E_REG_P01_SC_VS_LUT_7_W          = SPA(E_SNONE            , E_PAGE_01, 0x22),
++    E_REG_P01_SC_VS_LUT_8_W          = SPA(E_SNONE            , E_PAGE_01, 0x23),
++    E_REG_P01_SC_VS_LUT_9_W          = SPA(E_SNONE            , E_PAGE_01, 0x24),
++    E_REG_P01_SC_VS_LUT_10_W         = SPA(E_SNONE            , E_PAGE_01, 0x25),
++    E_REG_P01_SC_VS_LUT_11_W         = SPA(E_SNONE            , E_PAGE_01, 0x26),
++    E_REG_P01_SC_VS_LUT_12_W         = SPA(E_SNONE            , E_PAGE_01, 0x27),
++    E_REG_P01_SC_VS_LUT_13_W         = SPA(E_SNONE            , E_PAGE_01, 0x28),
++    E_REG_P01_SC_VS_LUT_14_W         = SPA(E_SNONE            , E_PAGE_01, 0x29),
++    E_REG_P01_SC_VS_LUT_15_W         = SPA(E_SNONE            , E_PAGE_01, 0x2A),
++    E_REG_P01_SC_VS_LUT_16_W         = SPA(E_SNONE            , E_PAGE_01, 0x2B),
++    E_REG_P01_SC_VS_LUT_17_W         = SPA(E_SNONE            , E_PAGE_01, 0x2C),
++    E_REG_P01_SC_VS_LUT_18_W         = SPA(E_SNONE            , E_PAGE_01, 0x2D),
++    E_REG_P01_SC_VS_LUT_19_W         = SPA(E_SNONE            , E_PAGE_01, 0x2E),
++    E_REG_P01_SC_VS_LUT_20_W         = SPA(E_SNONE            , E_PAGE_01, 0x2F),
++    E_REG_P01_SC_VS_LUT_21_W         = SPA(E_SNONE            , E_PAGE_01, 0x30),
++    E_REG_P01_SC_VS_LUT_22_W         = SPA(E_SNONE            , E_PAGE_01, 0x31),
++    E_REG_P01_SC_VS_LUT_23_W         = SPA(E_SNONE            , E_PAGE_01, 0x32),
++    E_REG_P01_SC_VS_LUT_24_W         = SPA(E_SNONE            , E_PAGE_01, 0x33),
++    E_REG_P01_SC_VS_LUT_25_W         = SPA(E_SNONE            , E_PAGE_01, 0x34),
++    E_REG_P01_SC_VS_LUT_26_W         = SPA(E_SNONE            , E_PAGE_01, 0x35),
++    E_REG_P01_SC_VS_LUT_27_W         = SPA(E_SNONE            , E_PAGE_01, 0x36),
++    E_REG_P01_SC_VS_LUT_28_W         = SPA(E_SNONE            , E_PAGE_01, 0x37),
++    E_REG_P01_SC_VS_LUT_29_W         = SPA(E_SNONE            , E_PAGE_01, 0x38),
++    E_REG_P01_SC_VS_LUT_30_W         = SPA(E_SNONE            , E_PAGE_01, 0x39),
++    E_REG_P01_SC_VS_LUT_31_W         = SPA(E_SNONE            , E_PAGE_01, 0x3A),
++    E_REG_P01_SC_VS_LUT_32_W         = SPA(E_SNONE            , E_PAGE_01, 0x3B),
++    E_REG_P01_SC_VS_LUT_33_W         = SPA(E_SNONE            , E_PAGE_01, 0x3C),
++    E_REG_P01_SC_VS_LUT_34_W         = SPA(E_SNONE            , E_PAGE_01, 0x3D),
++    E_REG_P01_SC_VS_LUT_35_W         = SPA(E_SNONE            , E_PAGE_01, 0x3E),   
++    E_REG_P01_SC_VS_LUT_36_W         = SPA(E_SNONE            , E_PAGE_01, 0x3F),
++    E_REG_P01_SC_VS_LUT_37_W         = SPA(E_SNONE            , E_PAGE_01, 0x40),
++    E_REG_P01_SC_VS_LUT_38_W         = SPA(E_SNONE            , E_PAGE_01, 0x41),
++    E_REG_P01_SC_VS_LUT_39_W         = SPA(E_SNONE            , E_PAGE_01, 0x42),
++    E_REG_P01_SC_VS_LUT_40_W         = SPA(E_SNONE            , E_PAGE_01, 0x43),
++    E_REG_P01_SC_VS_LUT_41_W         = SPA(E_SNONE            , E_PAGE_01, 0x44),
++    E_REG_P01_SC_VS_LUT_42_W         = SPA(E_SNONE            , E_PAGE_01, 0x45),
++    E_REG_P01_SC_VS_LUT_43_W         = SPA(E_SNONE            , E_PAGE_01, 0x46),
++    E_REG_P01_SC_VS_LUT_44_W         = SPA(E_SNONE            , E_PAGE_01, 0x47),
++    E_REG_P01_SC_LAT_SCO_RW          = SPA(E_SNONE            , E_PAGE_01, 0x48),
++    E_REG_P01_VIDFORMAT_W            = SPA(E_SNONE            , E_PAGE_01, 0xA0),
++    E_REG_P01_REFPIX_MSB_W           = SPA(E_SNONE            , E_PAGE_01, 0xA1),   
++    E_REG_P01_REFPIX_LSB_W           = SPA(E_SNONE            , E_PAGE_01, 0xA2),
++    E_REG_P01_REFLINE_MSB_W          = SPA(E_SNONE            , E_PAGE_01, 0xA3),
++    E_REG_P01_REFLINE_LSB_W          = SPA(E_SNONE            , E_PAGE_01, 0xA4),
++    E_REG_P01_NPIX_MSB_W             = SPA(E_SNONE            , E_PAGE_01, 0xA5),
++    E_REG_P01_NPIX_LSB_W             = SPA(E_SNONE            , E_PAGE_01, 0xA6),
++    E_REG_P01_NLINE_MSB_W            = SPA(E_SNONE            , E_PAGE_01, 0xA7),
++    E_REG_P01_NLINE_LSB_W            = SPA(E_SNONE            , E_PAGE_01, 0xA8),
++    E_REG_P01_VWIN_START_1_MSB_W     = SPA(E_SNONE            , E_PAGE_01, 0xBD),
++    E_REG_P01_VWIN_START_1_LSB_W     = SPA(E_SNONE            , E_PAGE_01, 0xBE),
++    E_REG_P01_VWIN_END_1_MSB_W       = SPA(E_SNONE            , E_PAGE_01, 0xBF),
++    E_REG_P01_VWIN_END_1_LSB_W       = SPA(E_SNONE            , E_PAGE_01, 0xC0),
++    E_REG_P01_VWIN_START_2_MSB_W     = SPA(E_SNONE            , E_PAGE_01, 0xC1),
++    E_REG_P01_VWIN_START_2_LSB_W     = SPA(E_SNONE            , E_PAGE_01, 0xC2),
++    E_REG_P01_VWIN_END_2_MSB_W       = SPA(E_SNONE            , E_PAGE_01, 0xC3),
++    E_REG_P01_VWIN_END_2_LSB_W       = SPA(E_SNONE            , E_PAGE_01, 0xC4),
++    E_REG_P01_DE_START_MSB_W         = SPA(E_SNONE            , E_PAGE_01, 0xC5),
++    E_REG_P01_DE_START_LSB_W         = SPA(E_SNONE            , E_PAGE_01, 0xC6),
++    E_REG_P01_DE_STOP_MSB_W          = SPA(E_SNONE            , E_PAGE_01, 0xC7),
++    E_REG_P01_DE_STOP_LSB_W          = SPA(E_SNONE            , E_PAGE_01, 0xC8),
++    E_REG_P01_TBG_CNTRL_0_W          = SPA(E_SP01_TBG_CNTRL_0 , E_PAGE_01, 0xCA),
++    E_REG_P02_PLL_SERIAL_1_RW        = SPA(E_SNONE            , E_PAGE_02, 0x00),
++    E_REG_P02_PLL_SERIAL_2_RW        = SPA(E_SNONE            , E_PAGE_02, 0x01),
++    E_REG_P02_PLL_SERIAL_3_RW        = SPA(E_SNONE            , E_PAGE_02, 0x02),
++    E_REG_P02_SERIALIZER_RW          = SPA(E_SNONE            , E_PAGE_02, 0x03),
++    E_REG_P02_BUFFER_OUT_RW          = SPA(E_SNONE            , E_PAGE_02, 0x04),
++    E_REG_P02_PLL_SCG1_RW            = SPA(E_SNONE            , E_PAGE_02, 0x05),
++    E_REG_P02_PLL_SCG2_RW            = SPA(E_SNONE            , E_PAGE_02, 0x06),
++    E_REG_P02_PLL_SCGN1_RW           = SPA(E_SNONE            , E_PAGE_02, 0x07),
++    E_REG_P02_PLL_SCGN2_RW           = SPA(E_SNONE            , E_PAGE_02, 0x08),
++    E_REG_P02_PLL_SCGR1_RW           = SPA(E_SNONE            , E_PAGE_02, 0x09),
++    E_REG_P02_PLL_SCGR2_RW           = SPA(E_SNONE            , E_PAGE_02, 0x0A),
++    E_REG_P02_VAI_PLL_R              = SPA(E_SNONE            , E_PAGE_02, 0x0D),
++    E_REG_P02_AUDIO_DIV_RW           = SPA(E_SNONE            , E_PAGE_02, 0x0E),
++    E_REG_P02_TEST1_RW               = SPA(E_SNONE            , E_PAGE_02, 0x0F),
++    /*E_REG_P02_TEST2_RW               = SPA(E_SNONE            , E_PAGE_02, 0x10),*/
++    E_REG_P02_SEL_CLK_RW             = SPA(E_SNONE            , E_PAGE_02, 0x11),
++    E_REG_P02_ANA_GENERAL_RW         = SPA(E_SNONE            , E_PAGE_02, 0x12),
++    E_REG_P02_BUFFER_OUT2_RW         = SPA(E_SNONE            , E_PAGE_02, 0x13),
++    E_REG_P02_SRL_TSTPAT0_RW         = SPA(E_SNONE            , E_PAGE_02, 0x14),
++    E_REG_P02_SRL_TSTPAT1_RW         = SPA(E_SNONE            , E_PAGE_02, 0x15),
++    E_REG_P02_SRL_TSTPAT2_RW         = SPA(E_SNONE            , E_PAGE_02, 0x16),
++    E_REG_P02_SRL_TSTPAT3_RW         = SPA(E_SNONE            , E_PAGE_02, 0x17),
++
++    E_REG_P09_EDID_DATA_0_R          = SPA(E_SNONE            , E_PAGE_09, 0x00),
++    E_REG_P09_EDID_DATA_1_R          = SPA(E_SNONE            , E_PAGE_09, 0x01),
++    E_REG_P09_EDID_DATA_2_R          = SPA(E_SNONE            , E_PAGE_09, 0x02),
++    E_REG_P09_EDID_DATA_3_R          = SPA(E_SNONE            , E_PAGE_09, 0x03),
++    E_REG_P09_EDID_DATA_4_R          = SPA(E_SNONE            , E_PAGE_09, 0x04),
++    E_REG_P09_EDID_DATA_5_R          = SPA(E_SNONE            , E_PAGE_09, 0x05),
++    E_REG_P09_EDID_DATA_6_R          = SPA(E_SNONE            , E_PAGE_09, 0x06),
++    E_REG_P09_EDID_DATA_7_R          = SPA(E_SNONE            , E_PAGE_09, 0x07),
++    E_REG_P09_EDID_DATA_8_R          = SPA(E_SNONE            , E_PAGE_09, 0x08),
++    E_REG_P09_EDID_DATA_9_R          = SPA(E_SNONE            , E_PAGE_09, 0x09),
++    E_REG_P09_EDID_DATA_10_R         = SPA(E_SNONE            , E_PAGE_09, 0x0A),
++    E_REG_P09_EDID_DATA_11_R         = SPA(E_SNONE            , E_PAGE_09, 0x0B),
++    E_REG_P09_EDID_DATA_12_R         = SPA(E_SNONE            , E_PAGE_09, 0x0C),
++    E_REG_P09_EDID_DATA_13_R         = SPA(E_SNONE            , E_PAGE_09, 0x0D),
++    E_REG_P09_EDID_DATA_14_R         = SPA(E_SNONE            , E_PAGE_09, 0x0E),
++    E_REG_P09_EDID_DATA_15_R         = SPA(E_SNONE            , E_PAGE_09, 0x0F),
++    E_REG_P09_EDID_DATA_16_R         = SPA(E_SNONE            , E_PAGE_09, 0x10),
++    E_REG_P09_EDID_DATA_17_R         = SPA(E_SNONE            , E_PAGE_09, 0x11),
++    E_REG_P09_EDID_DATA_18_R         = SPA(E_SNONE            , E_PAGE_09, 0x12),
++    E_REG_P09_EDID_DATA_19_R         = SPA(E_SNONE            , E_PAGE_09, 0x13),
++    E_REG_P09_EDID_DATA_20_R         = SPA(E_SNONE            , E_PAGE_09, 0x14),
++    E_REG_P09_EDID_DATA_21_R         = SPA(E_SNONE            , E_PAGE_09, 0x15),
++    E_REG_P09_EDID_DATA_22_R         = SPA(E_SNONE            , E_PAGE_09, 0x16),
++    E_REG_P09_EDID_DATA_23_R         = SPA(E_SNONE            , E_PAGE_09, 0x17),
++    E_REG_P09_EDID_DATA_24_R         = SPA(E_SNONE            , E_PAGE_09, 0x18),
++    E_REG_P09_EDID_DATA_25_R         = SPA(E_SNONE            , E_PAGE_09, 0x19),
++    E_REG_P09_EDID_DATA_26_R         = SPA(E_SNONE            , E_PAGE_09, 0x1A),
++    E_REG_P09_EDID_DATA_27_R         = SPA(E_SNONE            , E_PAGE_09, 0x1B),
++    E_REG_P09_EDID_DATA_28_R         = SPA(E_SNONE            , E_PAGE_09, 0x1C),
++    E_REG_P09_EDID_DATA_29_R         = SPA(E_SNONE            , E_PAGE_09, 0x1D),
++    E_REG_P09_EDID_DATA_30_R         = SPA(E_SNONE            , E_PAGE_09, 0x1E),
++    E_REG_P09_EDID_DATA_31_R         = SPA(E_SNONE            , E_PAGE_09, 0x1F),
++    E_REG_P09_EDID_DATA_32_R         = SPA(E_SNONE            , E_PAGE_09, 0x20),
++    E_REG_P09_EDID_DATA_33_R         = SPA(E_SNONE            , E_PAGE_09, 0x21),
++    E_REG_P09_EDID_DATA_34_R         = SPA(E_SNONE            , E_PAGE_09, 0x22),
++    E_REG_P09_EDID_DATA_35_R         = SPA(E_SNONE            , E_PAGE_09, 0x23),
++    E_REG_P09_EDID_DATA_36_R         = SPA(E_SNONE            , E_PAGE_09, 0x24),
++    E_REG_P09_EDID_DATA_37_R         = SPA(E_SNONE            , E_PAGE_09, 0x25),
++    E_REG_P09_EDID_DATA_38_R         = SPA(E_SNONE            , E_PAGE_09, 0x26),
++    E_REG_P09_EDID_DATA_39_R         = SPA(E_SNONE            , E_PAGE_09, 0x27),
++    E_REG_P09_EDID_DATA_40_R         = SPA(E_SNONE            , E_PAGE_09, 0x28),
++    E_REG_P09_EDID_DATA_41_R         = SPA(E_SNONE            , E_PAGE_09, 0x29),
++    E_REG_P09_EDID_DATA_42_R         = SPA(E_SNONE            , E_PAGE_09, 0x2A),
++    E_REG_P09_EDID_DATA_43_R         = SPA(E_SNONE            , E_PAGE_09, 0x2B),
++    E_REG_P09_EDID_DATA_44_R         = SPA(E_SNONE            , E_PAGE_09, 0x2C),   
++    E_REG_P09_EDID_DATA_45_R         = SPA(E_SNONE            , E_PAGE_09, 0x2D),
++    E_REG_P09_EDID_DATA_46_R         = SPA(E_SNONE            , E_PAGE_09, 0x2E),
++    E_REG_P09_EDID_DATA_47_R         = SPA(E_SNONE            , E_PAGE_09, 0x2F),
++    E_REG_P09_EDID_DATA_48_R         = SPA(E_SNONE            , E_PAGE_09, 0x30),
++    E_REG_P09_EDID_DATA_49_R         = SPA(E_SNONE            , E_PAGE_09, 0x31),
++    E_REG_P09_EDID_DATA_50_R         = SPA(E_SNONE            , E_PAGE_09, 0x32),
++    E_REG_P09_EDID_DATA_51_R         = SPA(E_SNONE            , E_PAGE_09, 0x33),
++    E_REG_P09_EDID_DATA_52_R         = SPA(E_SNONE            , E_PAGE_09, 0x34),
++    E_REG_P09_EDID_DATA_53_R         = SPA(E_SNONE            , E_PAGE_09, 0x35),
++    E_REG_P09_EDID_DATA_54_R         = SPA(E_SNONE            , E_PAGE_09, 0x36),
++    E_REG_P09_EDID_DATA_55_R         = SPA(E_SNONE            , E_PAGE_09, 0x37),
++    E_REG_P09_EDID_DATA_56_R         = SPA(E_SNONE            , E_PAGE_09, 0x38),
++    E_REG_P09_EDID_DATA_57_R         = SPA(E_SNONE            , E_PAGE_09, 0x39),
++    E_REG_P09_EDID_DATA_58_R         = SPA(E_SNONE            , E_PAGE_09, 0x3A),
++    E_REG_P09_EDID_DATA_59_R         = SPA(E_SNONE            , E_PAGE_09, 0x3B),
++    E_REG_P09_EDID_DATA_60_R         = SPA(E_SNONE            , E_PAGE_09, 0x3C),
++    E_REG_P09_EDID_DATA_61_R         = SPA(E_SNONE            , E_PAGE_09, 0x3D),       
++    E_REG_P09_EDID_DATA_62_R         = SPA(E_SNONE            , E_PAGE_09, 0x3E),
++    E_REG_P09_EDID_DATA_63_R         = SPA(E_SNONE            , E_PAGE_09, 0x3F),
++    E_REG_P09_EDID_DATA_64_R         = SPA(E_SNONE            , E_PAGE_09, 0x40),
++    E_REG_P09_EDID_DATA_65_R         = SPA(E_SNONE            , E_PAGE_09, 0x41),
++    E_REG_P09_EDID_DATA_66_R         = SPA(E_SNONE            , E_PAGE_09, 0x42),
++    E_REG_P09_EDID_DATA_67_R         = SPA(E_SNONE            , E_PAGE_09, 0x43),
++    E_REG_P09_EDID_DATA_68_R         = SPA(E_SNONE            , E_PAGE_09, 0x44),
++    E_REG_P09_EDID_DATA_69_R         = SPA(E_SNONE            , E_PAGE_09, 0x45),
++    E_REG_P09_EDID_DATA_70_R         = SPA(E_SNONE            , E_PAGE_09, 0x46),
++    E_REG_P09_EDID_DATA_71_R         = SPA(E_SNONE            , E_PAGE_09, 0x47),
++    E_REG_P09_EDID_DATA_72_R         = SPA(E_SNONE            , E_PAGE_09, 0x48),
++    E_REG_P09_EDID_DATA_73_R         = SPA(E_SNONE            , E_PAGE_09, 0x49),
++    E_REG_P09_EDID_DATA_74_R         = SPA(E_SNONE            , E_PAGE_09, 0x4A),
++    E_REG_P09_EDID_DATA_75_R         = SPA(E_SNONE            , E_PAGE_09, 0x4B),
++    E_REG_P09_EDID_DATA_76_R         = SPA(E_SNONE            , E_PAGE_09, 0x4C),
++    E_REG_P09_EDID_DATA_77_R         = SPA(E_SNONE            , E_PAGE_09, 0x4D),
++    E_REG_P09_EDID_DATA_78_R         = SPA(E_SNONE            , E_PAGE_09, 0x4E),
++    E_REG_P09_EDID_DATA_79_R         = SPA(E_SNONE            , E_PAGE_09, 0x4F),
++    E_REG_P09_EDID_DATA_80_R         = SPA(E_SNONE            , E_PAGE_09, 0x50),
++    E_REG_P09_EDID_DATA_81_R         = SPA(E_SNONE            , E_PAGE_09, 0x51),
++    E_REG_P09_EDID_DATA_82_R         = SPA(E_SNONE            , E_PAGE_09, 0x52),
++    E_REG_P09_EDID_DATA_83_R         = SPA(E_SNONE            , E_PAGE_09, 0x53),
++    E_REG_P09_EDID_DATA_84_R         = SPA(E_SNONE            , E_PAGE_09, 0x54),
++    E_REG_P09_EDID_DATA_85_R         = SPA(E_SNONE            , E_PAGE_09, 0x55),   
++    E_REG_P09_EDID_DATA_86_R         = SPA(E_SNONE            , E_PAGE_09, 0x56),
++    E_REG_P09_EDID_DATA_87_R         = SPA(E_SNONE            , E_PAGE_09, 0x57),
++    E_REG_P09_EDID_DATA_88_R         = SPA(E_SNONE            , E_PAGE_09, 0x58),
++    E_REG_P09_EDID_DATA_89_R         = SPA(E_SNONE            , E_PAGE_09, 0x59),
++    E_REG_P09_EDID_DATA_90_R         = SPA(E_SNONE            , E_PAGE_09, 0x5A),
++    E_REG_P09_EDID_DATA_91_R         = SPA(E_SNONE            , E_PAGE_09, 0x5B),
++    E_REG_P09_EDID_DATA_92_R         = SPA(E_SNONE            , E_PAGE_09, 0x5C),
++    E_REG_P09_EDID_DATA_93_R         = SPA(E_SNONE            , E_PAGE_09, 0x5D),
++    E_REG_P09_EDID_DATA_94_R         = SPA(E_SNONE            , E_PAGE_09, 0x5E),
++    E_REG_P09_EDID_DATA_95_R         = SPA(E_SNONE            , E_PAGE_09, 0x5F),
++    E_REG_P09_EDID_DATA_96_R         = SPA(E_SNONE            , E_PAGE_09, 0x60),
++    E_REG_P09_EDID_DATA_97_R         = SPA(E_SNONE            , E_PAGE_09, 0x61),
++    E_REG_P09_EDID_DATA_98_R         = SPA(E_SNONE            , E_PAGE_09, 0x62),
++    E_REG_P09_EDID_DATA_99_R         = SPA(E_SNONE            , E_PAGE_09, 0x63),
++    E_REG_P09_EDID_DATA_100_R        = SPA(E_SNONE            , E_PAGE_09, 0x64),
++    E_REG_P09_EDID_DATA_101_R        = SPA(E_SNONE            , E_PAGE_09, 0x65),
++    E_REG_P09_EDID_DATA_102_R        = SPA(E_SNONE            , E_PAGE_09, 0x66),
++    E_REG_P09_EDID_DATA_103_R        = SPA(E_SNONE            , E_PAGE_09, 0x67),
++    E_REG_P09_EDID_DATA_104_R        = SPA(E_SNONE            , E_PAGE_09, 0x68),
++    E_REG_P09_EDID_DATA_105_R        = SPA(E_SNONE            , E_PAGE_09, 0x69),
++    E_REG_P09_EDID_DATA_106_R        = SPA(E_SNONE            , E_PAGE_09, 0x6A),
++    E_REG_P09_EDID_DATA_107_R        = SPA(E_SNONE            , E_PAGE_09, 0x6B),
++    E_REG_P09_EDID_DATA_108_R        = SPA(E_SNONE            , E_PAGE_09, 0x6C),
++    E_REG_P09_EDID_DATA_109_R        = SPA(E_SNONE            , E_PAGE_09, 0x6D),
++    E_REG_P09_EDID_DATA_110_R        = SPA(E_SNONE            , E_PAGE_09, 0x6E),
++    E_REG_P09_EDID_DATA_111_R        = SPA(E_SNONE            , E_PAGE_09, 0x6F),
++    E_REG_P09_EDID_DATA_112_R        = SPA(E_SNONE            , E_PAGE_09, 0x70),
++    E_REG_P09_EDID_DATA_113_R        = SPA(E_SNONE            , E_PAGE_09, 0x71),
++    E_REG_P09_EDID_DATA_114_R        = SPA(E_SNONE            , E_PAGE_09, 0x72),
++    E_REG_P09_EDID_DATA_115_R        = SPA(E_SNONE            , E_PAGE_09, 0x73),
++    E_REG_P09_EDID_DATA_116_R        = SPA(E_SNONE            , E_PAGE_09, 0x74),
++    E_REG_P09_EDID_DATA_117_R        = SPA(E_SNONE            , E_PAGE_09, 0x75),
++    E_REG_P09_EDID_DATA_118_R        = SPA(E_SNONE            , E_PAGE_09, 0x76),
++    E_REG_P09_EDID_DATA_119_R        = SPA(E_SNONE            , E_PAGE_09, 0x77),
++    E_REG_P09_EDID_DATA_120_R        = SPA(E_SNONE            , E_PAGE_09, 0x78),
++    E_REG_P09_EDID_DATA_121_R        = SPA(E_SNONE            , E_PAGE_09, 0x79),
++    E_REG_P09_EDID_DATA_122_R        = SPA(E_SNONE            , E_PAGE_09, 0x7A),
++    E_REG_P09_EDID_DATA_123_R        = SPA(E_SNONE            , E_PAGE_09, 0x7B),
++    E_REG_P09_EDID_DATA_124_R        = SPA(E_SNONE            , E_PAGE_09, 0x7C),
++    E_REG_P09_EDID_DATA_125_R        = SPA(E_SNONE            , E_PAGE_09, 0x7D),
++    E_REG_P09_EDID_DATA_126_R        = SPA(E_SNONE            , E_PAGE_09, 0x7E),
++    E_REG_P09_EDID_DATA_127_R        = SPA(E_SNONE            , E_PAGE_09, 0x7F),
++    E_REG_P09_EDID_CTRL_RW           = SPA(E_SNONE            , E_PAGE_09, 0xFA),
++    E_REG_P09_DDC_ADDR_RW            = SPA(E_SNONE            , E_PAGE_09, 0xFB),
++    E_REG_P09_DDC_OFFS_RW            = SPA(E_SNONE            , E_PAGE_09, 0xFC),
++    E_REG_P09_DDC_SEGM_ADDR_RW       = SPA(E_SNONE            , E_PAGE_09, 0xFD),
++    E_REG_P09_DDC_SEGM_RW            = SPA(E_SNONE            , E_PAGE_09, 0xFE),   
++    
++    E_REG_P10_IF1_HB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0x20),
++    E_REG_P10_IF1_HB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0x21),
++    E_REG_P10_IF1_HB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0x22),
++    E_REG_P10_IF1_PB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0x23),
++    E_REG_P10_IF1_PB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0x24),
++    E_REG_P10_IF1_PB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0x25),
++    E_REG_P10_IF1_PB3_RW             = SPA(E_SNONE            , E_PAGE_10, 0x26),
++    E_REG_P10_IF1_PB4_RW             = SPA(E_SNONE            , E_PAGE_10, 0x27),
++    E_REG_P10_IF1_PB5_RW             = SPA(E_SNONE            , E_PAGE_10, 0x28),
++    E_REG_P10_IF1_PB6_RW             = SPA(E_SNONE            , E_PAGE_10, 0x29),
++    E_REG_P10_IF1_PB7_RW             = SPA(E_SNONE            , E_PAGE_10, 0x2A),
++    E_REG_P10_IF1_PB8_RW             = SPA(E_SNONE            , E_PAGE_10, 0x2B),
++    E_REG_P10_IF1_PB9_RW             = SPA(E_SNONE            , E_PAGE_10, 0x2C),
++    E_REG_P10_IF1_PB10_RW            = SPA(E_SNONE            , E_PAGE_10, 0x2D),
++    E_REG_P10_IF1_PB11_RW            = SPA(E_SNONE            , E_PAGE_10, 0x2E),
++    E_REG_P10_IF1_PB12_RW            = SPA(E_SNONE            , E_PAGE_10, 0x2F),
++    E_REG_P10_IF1_PB13_RW            = SPA(E_SNONE            , E_PAGE_10, 0x30),
++    E_REG_P10_IF1_PB14_RW            = SPA(E_SNONE            , E_PAGE_10, 0x31),
++    E_REG_P10_IF1_PB15_RW            = SPA(E_SNONE            , E_PAGE_10, 0x32),
++    E_REG_P10_IF1_PB16_RW            = SPA(E_SNONE            , E_PAGE_10, 0x33),
++    E_REG_P10_IF1_PB17_RW            = SPA(E_SNONE            , E_PAGE_10, 0x34),
++    E_REG_P10_IF1_PB18_RW            = SPA(E_SNONE            , E_PAGE_10, 0x35),
++    E_REG_P10_IF1_PB19_RW            = SPA(E_SNONE            , E_PAGE_10, 0x36),
++    E_REG_P10_IF1_PB20_RW            = SPA(E_SNONE            , E_PAGE_10, 0x37),
++    E_REG_P10_IF1_PB21_RW            = SPA(E_SNONE            , E_PAGE_10, 0x38),
++    E_REG_P10_IF1_PB22_RW            = SPA(E_SNONE            , E_PAGE_10, 0x39),
++    E_REG_P10_IF1_PB23_RW            = SPA(E_SNONE            , E_PAGE_10, 0x3A),
++    E_REG_P10_IF1_PB24_RW            = SPA(E_SNONE            , E_PAGE_10, 0x3B),
++    E_REG_P10_IF1_PB25_RW            = SPA(E_SNONE            , E_PAGE_10, 0x3C),
++    E_REG_P10_IF1_PB26_RW            = SPA(E_SNONE            , E_PAGE_10, 0x3D),
++    E_REG_P10_IF1_PB27_RW            = SPA(E_SNONE            , E_PAGE_10, 0x3E),
++    E_REG_P10_IF2_HB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0x40),
++    E_REG_P10_IF2_HB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0x41),
++    E_REG_P10_IF2_HB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0x42),
++    E_REG_P10_IF2_PB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0x43),
++    E_REG_P10_IF2_PB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0x44),
++    E_REG_P10_IF2_PB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0x45),
++    E_REG_P10_IF2_PB3_RW             = SPA(E_SNONE            , E_PAGE_10, 0x46),
++    E_REG_P10_IF2_PB4_RW             = SPA(E_SNONE            , E_PAGE_10, 0x47),
++    E_REG_P10_IF2_PB5_RW             = SPA(E_SNONE            , E_PAGE_10, 0x48),
++    E_REG_P10_IF2_PB6_RW             = SPA(E_SNONE            , E_PAGE_10, 0x49),
++    E_REG_P10_IF2_PB7_RW             = SPA(E_SNONE            , E_PAGE_10, 0x4A),
++    E_REG_P10_IF2_PB8_RW             = SPA(E_SNONE            , E_PAGE_10, 0x4B),
++    E_REG_P10_IF2_PB9_RW             = SPA(E_SNONE            , E_PAGE_10, 0x4C),
++    E_REG_P10_IF2_PB10_RW            = SPA(E_SNONE            , E_PAGE_10, 0x4D),
++    E_REG_P10_IF2_PB11_RW            = SPA(E_SNONE            , E_PAGE_10, 0x4E),
++    E_REG_P10_IF2_PB12_RW            = SPA(E_SNONE            , E_PAGE_10, 0x4F),
++    E_REG_P10_IF2_PB13_RW            = SPA(E_SNONE            , E_PAGE_10, 0x50),
++    E_REG_P10_IF2_PB14_RW            = SPA(E_SNONE            , E_PAGE_10, 0x51),
++    E_REG_P10_IF2_PB15_RW            = SPA(E_SNONE            , E_PAGE_10, 0x52),
++    E_REG_P10_IF2_PB16_RW            = SPA(E_SNONE            , E_PAGE_10, 0x53),
++    E_REG_P10_IF2_PB17_RW            = SPA(E_SNONE            , E_PAGE_10, 0x54),
++    E_REG_P10_IF2_PB18_RW            = SPA(E_SNONE            , E_PAGE_10, 0x55),
++    E_REG_P10_IF2_PB19_RW            = SPA(E_SNONE            , E_PAGE_10, 0x56),
++    E_REG_P10_IF2_PB20_RW            = SPA(E_SNONE            , E_PAGE_10, 0x57),
++    E_REG_P10_IF2_PB21_RW            = SPA(E_SNONE            , E_PAGE_10, 0x58),
++    E_REG_P10_IF2_PB22_RW            = SPA(E_SNONE            , E_PAGE_10, 0x59),
++    E_REG_P10_IF2_PB23_RW            = SPA(E_SNONE            , E_PAGE_10, 0x5A),
++    E_REG_P10_IF2_PB24_RW            = SPA(E_SNONE            , E_PAGE_10, 0x5B),
++    E_REG_P10_IF2_PB25_RW            = SPA(E_SNONE            , E_PAGE_10, 0x5C),
++    E_REG_P10_IF2_PB26_RW            = SPA(E_SNONE            , E_PAGE_10, 0x5D),
++    E_REG_P10_IF2_PB27_RW            = SPA(E_SNONE            , E_PAGE_10, 0x5E),
++    E_REG_P10_IF3_HB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0x60),
++    E_REG_P10_IF3_HB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0x61),
++    E_REG_P10_IF3_HB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0x62),
++    E_REG_P10_IF3_PB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0x63),
++    E_REG_P10_IF3_PB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0x64),
++    E_REG_P10_IF3_PB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0x65),
++    E_REG_P10_IF3_PB3_RW             = SPA(E_SNONE            , E_PAGE_10, 0x66),
++    E_REG_P10_IF3_PB4_RW             = SPA(E_SNONE            , E_PAGE_10, 0x67),
++    E_REG_P10_IF3_PB5_RW             = SPA(E_SNONE            , E_PAGE_10, 0x68),
++    E_REG_P10_IF3_PB6_RW             = SPA(E_SNONE            , E_PAGE_10, 0x69),
++    E_REG_P10_IF3_PB7_RW             = SPA(E_SNONE            , E_PAGE_10, 0x6A),
++    E_REG_P10_IF3_PB8_RW             = SPA(E_SNONE            , E_PAGE_10, 0x6B),
++    E_REG_P10_IF3_PB9_RW             = SPA(E_SNONE            , E_PAGE_10, 0x6C),
++    E_REG_P10_IF3_PB10_RW            = SPA(E_SNONE            , E_PAGE_10, 0x6D),
++    E_REG_P10_IF3_PB11_RW            = SPA(E_SNONE            , E_PAGE_10, 0x6E),
++    E_REG_P10_IF3_PB12_RW            = SPA(E_SNONE            , E_PAGE_10, 0x6F),
++    E_REG_P10_IF3_PB13_RW            = SPA(E_SNONE            , E_PAGE_10, 0x70),   
++    E_REG_P10_IF3_PB14_RW            = SPA(E_SNONE            , E_PAGE_10, 0x71),
++    E_REG_P10_IF3_PB15_RW            = SPA(E_SNONE            , E_PAGE_10, 0x72),
++    E_REG_P10_IF3_PB16_RW            = SPA(E_SNONE            , E_PAGE_10, 0x73),
++    E_REG_P10_IF3_PB17_RW            = SPA(E_SNONE            , E_PAGE_10, 0x74),
++    E_REG_P10_IF3_PB18_RW            = SPA(E_SNONE            , E_PAGE_10, 0x75),
++    E_REG_P10_IF3_PB19_RW            = SPA(E_SNONE            , E_PAGE_10, 0x76),
++    E_REG_P10_IF3_PB20_RW            = SPA(E_SNONE            , E_PAGE_10, 0x77),
++    E_REG_P10_IF3_PB21_RW            = SPA(E_SNONE            , E_PAGE_10, 0x78),
++    E_REG_P10_IF3_PB22_RW            = SPA(E_SNONE            , E_PAGE_10, 0x79),
++    E_REG_P10_IF3_PB23_RW            = SPA(E_SNONE            , E_PAGE_10, 0x7A),
++    E_REG_P10_IF3_PB24_RW            = SPA(E_SNONE            , E_PAGE_10, 0x7B),
++    E_REG_P10_IF3_PB25_RW            = SPA(E_SNONE            , E_PAGE_10, 0x7C),
++    E_REG_P10_IF3_PB26_RW            = SPA(E_SNONE            , E_PAGE_10, 0x7D),
++    E_REG_P10_IF3_PB27_RW            = SPA(E_SNONE            , E_PAGE_10, 0x7E),
++    E_REG_P10_IF4_HB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0x80),
++    E_REG_P10_IF4_HB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0x81),
++    E_REG_P10_IF4_HB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0x82),
++    E_REG_P10_IF4_PB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0x83),
++    E_REG_P10_IF4_PB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0x84),
++    E_REG_P10_IF4_PB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0x85),
++    E_REG_P10_IF4_PB3_RW             = SPA(E_SNONE            , E_PAGE_10, 0x86),
++    E_REG_P10_IF4_PB4_RW             = SPA(E_SNONE            , E_PAGE_10, 0x87),
++    E_REG_P10_IF4_PB5_RW             = SPA(E_SNONE            , E_PAGE_10, 0x88),   
++    E_REG_P10_IF4_PB6_RW             = SPA(E_SNONE            , E_PAGE_10, 0x89),
++    E_REG_P10_IF4_PB7_RW             = SPA(E_SNONE            , E_PAGE_10, 0x8A),
++    E_REG_P10_IF4_PB8_RW             = SPA(E_SNONE            , E_PAGE_10, 0x8B),
++    E_REG_P10_IF4_PB9_RW             = SPA(E_SNONE            , E_PAGE_10, 0x8C),
++    E_REG_P10_IF4_PB10_RW            = SPA(E_SNONE            , E_PAGE_10, 0x8D),
++    E_REG_P10_IF4_PB11_RW            = SPA(E_SNONE            , E_PAGE_10, 0x8E),
++    E_REG_P10_IF4_PB12_RW            = SPA(E_SNONE            , E_PAGE_10, 0x8F),
++    E_REG_P10_IF4_PB13_RW            = SPA(E_SNONE            , E_PAGE_10, 0x90),
++    E_REG_P10_IF4_PB14_RW            = SPA(E_SNONE            , E_PAGE_10, 0x91),
++    E_REG_P10_IF4_PB15_RW            = SPA(E_SNONE            , E_PAGE_10, 0x92),
++    E_REG_P10_IF4_PB16_RW            = SPA(E_SNONE            , E_PAGE_10, 0x93),
++    E_REG_P10_IF4_PB17_RW            = SPA(E_SNONE            , E_PAGE_10, 0x94),
++    E_REG_P10_IF4_PB18_RW            = SPA(E_SNONE            , E_PAGE_10, 0x95),
++    E_REG_P10_IF4_PB19_RW            = SPA(E_SNONE            , E_PAGE_10, 0x96),
++    E_REG_P10_IF4_PB20_RW            = SPA(E_SNONE            , E_PAGE_10, 0x97),
++    E_REG_P10_IF4_PB21_RW            = SPA(E_SNONE            , E_PAGE_10, 0x98),
++    E_REG_P10_IF4_PB22_RW            = SPA(E_SNONE            , E_PAGE_10, 0x99),
++    E_REG_P10_IF4_PB23_RW            = SPA(E_SNONE            , E_PAGE_10, 0x9A),
++    E_REG_P10_IF4_PB24_RW            = SPA(E_SNONE            , E_PAGE_10, 0x9B),
++    E_REG_P10_IF4_PB25_RW            = SPA(E_SNONE            , E_PAGE_10, 0x9C),
++    E_REG_P10_IF4_PB26_RW            = SPA(E_SNONE            , E_PAGE_10, 0x9D),
++    E_REG_P10_IF4_PB27_RW            = SPA(E_SNONE            , E_PAGE_10, 0x9E),
++    E_REG_P10_IF5_HB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA0),
++    E_REG_P10_IF5_HB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA1),
++    E_REG_P10_IF5_HB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA2),
++    E_REG_P10_IF5_PB0_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA3),
++    E_REG_P10_IF5_PB1_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA4),
++    E_REG_P10_IF5_PB2_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA5),
++    E_REG_P10_IF5_PB3_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA6),
++    E_REG_P10_IF5_PB4_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA7),
++    E_REG_P10_IF5_PB5_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA8),
++    E_REG_P10_IF5_PB6_RW             = SPA(E_SNONE            , E_PAGE_10, 0xA9),
++    E_REG_P10_IF5_PB7_RW             = SPA(E_SNONE            , E_PAGE_10, 0xAA),
++    E_REG_P10_IF5_PB8_RW             = SPA(E_SNONE            , E_PAGE_10, 0xAB),
++    E_REG_P10_IF5_PB9_RW             = SPA(E_SNONE            , E_PAGE_10, 0xAC),
++    E_REG_P10_IF5_PB10_RW            = SPA(E_SNONE            , E_PAGE_10, 0xAD),
++    E_REG_P10_IF5_PB11_RW            = SPA(E_SNONE            , E_PAGE_10, 0xAE),
++    E_REG_P10_IF5_PB12_RW            = SPA(E_SNONE            , E_PAGE_10, 0xAF),
++    E_REG_P10_IF5_PB13_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB0),
++    E_REG_P10_IF5_PB14_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB1),
++    E_REG_P10_IF5_PB15_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB2),
++    E_REG_P10_IF5_PB16_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB3),
++    E_REG_P10_IF5_PB17_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB4),
++    E_REG_P10_IF5_PB18_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB5),
++    E_REG_P10_IF5_PB19_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB6),
++    E_REG_P10_IF5_PB20_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB7),
++    E_REG_P10_IF5_PB21_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB8),
++    E_REG_P10_IF5_PB22_RW            = SPA(E_SNONE            , E_PAGE_10, 0xB9),
++    E_REG_P10_IF5_PB23_RW            = SPA(E_SNONE            , E_PAGE_10, 0xBA),
++    E_REG_P10_IF5_PB24_RW            = SPA(E_SNONE            , E_PAGE_10, 0xBB),
++    E_REG_P10_IF5_PB25_RW            = SPA(E_SNONE            , E_PAGE_10, 0xBC),
++    E_REG_P10_IF5_PB26_RW            = SPA(E_SNONE            , E_PAGE_10, 0xBD),
++    E_REG_P10_IF5_PB27_RW            = SPA(E_SNONE            , E_PAGE_10, 0xBE),
++    E_REG_P11_AIP_CNTRL_0_RW         = SPA(E_SNONE            , E_PAGE_11, 0x00),
++    E_REG_P11_CA_I2S_RW              = SPA(E_SNONE            , E_PAGE_11, 0x01),
++    E_REG_P11_CA_DSD_RW              = SPA(E_SNONE            , E_PAGE_11, 0x02),
++    E_REG_P11_OBA_PH_RW              = SPA(E_SNONE            , E_PAGE_11, 0x03),
++    E_REG_P11_LATENCY_RD_RW          = SPA(E_SNONE            , E_PAGE_11, 0x04),
++    E_REG_P11_ACR_CTS_0_RW           = SPA(E_SNONE            , E_PAGE_11, 0x05),
++    E_REG_P11_ACR_CTS_1_RW           = SPA(E_SNONE            , E_PAGE_11, 0x06),
++    E_REG_P11_ACR_CTS_2_RW           = SPA(E_SNONE            , E_PAGE_11, 0x07),
++    E_REG_P11_ACR_N_0_RW             = SPA(E_SNONE            , E_PAGE_11, 0x08),
++    E_REG_P11_ACR_N_1_RW             = SPA(E_SNONE            , E_PAGE_11, 0x09),
++    E_REG_P11_ACR_N_2_RW             = SPA(E_SNONE            , E_PAGE_11, 0x0A),
++    E_REG_P11_GC_AVMUTE_RW           = SPA(E_SNONE            , E_PAGE_11, 0x0B),
++    E_REG_P11_CTS_N_RW               = SPA(E_SNONE            , E_PAGE_11, 0x0C),
++    E_REG_P11_ENC_CNTRL_RW           = SPA(E_SNONE            , E_PAGE_11, 0x0D),
++    E_REG_P11_DIP_FLAGS_RW           = SPA(E_SNONE            , E_PAGE_11, 0x0E),   
++    E_REG_P11_DIP_IF_FLAGS_RW        = SPA(E_SNONE            , E_PAGE_11, 0x0F),
++    E_REG_P11_CH_STAT_B_0_RW         = SPA(E_SNONE            , E_PAGE_11, 0x14),
++    E_REG_P11_CH_STAT_B_1_RW         = SPA(E_SNONE            , E_PAGE_11, 0x15),
++    E_REG_P11_CH_STAT_B_3_RW         = SPA(E_SNONE            , E_PAGE_11, 0x16),
++    E_REG_P11_CH_STAT_B_4_RW         = SPA(E_SNONE            , E_PAGE_11, 0x17),
++    E_REG_P11_CH_STAT_B_2_ap0_l_RW   = SPA(E_SNONE            , E_PAGE_11, 0x18),
++    E_REG_P11_CH_STAT_B_2_ap0_r_RW   = SPA(E_SNONE            , E_PAGE_11, 0x19),
++    E_REG_P11_CH_STAT_B_2_ap1_l_RW   = SPA(E_SNONE            , E_PAGE_11, 0x1A),
++    E_REG_P11_CH_STAT_B_2_ap1_r_RW   = SPA(E_SNONE            , E_PAGE_11, 0x1B),
++    E_REG_P11_CH_STAT_B_2_ap2_l_RW   = SPA(E_SNONE            , E_PAGE_11, 0x1C),
++    E_REG_P11_CH_STAT_B_2_ap2_r_RW   = SPA(E_SNONE            , E_PAGE_11, 0x1D),
++    E_REG_P11_CH_STAT_B_2_ap3_l_RW   = SPA(E_SNONE            , E_PAGE_11, 0x1E),
++    E_REG_P11_CH_STAT_B_2_ap3_r_RW   = SPA(E_SNONE            , E_PAGE_11, 0x1F),
++    E_REG_P11_ISRC1_HB0_RW           = SPA(E_SNONE            , E_PAGE_11, 0x20),
++    E_REG_P11_ISRC1_HB1_RW           = SPA(E_SNONE            , E_PAGE_11, 0x21),
++    E_REG_P11_ISRC1_HB2_RW           = SPA(E_SNONE            , E_PAGE_11, 0x22),
++    E_REG_P11_ISRC1_PB0_RW           = SPA(E_SNONE            , E_PAGE_11, 0x23),
++    E_REG_P11_ISRC1_PB1_RW           = SPA(E_SNONE            , E_PAGE_11, 0x24),
++    E_REG_P11_ISRC1_PB2_RW           = SPA(E_SNONE            , E_PAGE_11, 0x25),
++    E_REG_P11_ISRC1_PB3_RW           = SPA(E_SNONE            , E_PAGE_11, 0x26),
++    E_REG_P11_ISRC1_PB4_RW           = SPA(E_SNONE            , E_PAGE_11, 0x27),
++    E_REG_P11_ISRC1_PB5_RW           = SPA(E_SNONE            , E_PAGE_11, 0x28),
++    E_REG_P11_ISRC1_PB6_RW           = SPA(E_SNONE            , E_PAGE_11, 0x29),
++    E_REG_P11_ISRC1_PB7_RW           = SPA(E_SNONE            , E_PAGE_11, 0x2A),
++    E_REG_P11_ISRC1_PB8_RW           = SPA(E_SNONE            , E_PAGE_11, 0x2B),
++    E_REG_P11_ISRC1_PB9_RW           = SPA(E_SNONE            , E_PAGE_11, 0x2C),
++    E_REG_P11_ISRC1_PB10_RW          = SPA(E_SNONE            , E_PAGE_11, 0x2D),
++    E_REG_P11_ISRC1_PB11_RW          = SPA(E_SNONE            , E_PAGE_11, 0x2E),
++    E_REG_P11_ISRC1_PB12_RW          = SPA(E_SNONE            , E_PAGE_11, 0x2F),
++    E_REG_P11_ISRC1_PB13_RW          = SPA(E_SNONE            , E_PAGE_11, 0x30),
++    E_REG_P11_ISRC1_PB14_RW          = SPA(E_SNONE            , E_PAGE_11, 0x31),
++    E_REG_P11_ISRC1_PB15_RW          = SPA(E_SNONE            , E_PAGE_11, 0x32),
++    E_REG_P11_ISRC1_PB16_RW          = SPA(E_SNONE            , E_PAGE_11, 0x33),
++    E_REG_P11_ISRC1_PB17_RW          = SPA(E_SNONE            , E_PAGE_11, 0x34),
++    E_REG_P11_ISRC1_PB18_RW          = SPA(E_SNONE            , E_PAGE_11, 0x35),
++    E_REG_P11_ISRC1_PB19_RW          = SPA(E_SNONE            , E_PAGE_11, 0x36),
++    E_REG_P11_ISRC1_PB20_RW          = SPA(E_SNONE            , E_PAGE_11, 0x37),
++    E_REG_P11_ISRC1_PB21_RW          = SPA(E_SNONE            , E_PAGE_11, 0x38),
++    E_REG_P11_ISRC1_PB22_RW          = SPA(E_SNONE            , E_PAGE_11, 0x39),   
++    E_REG_P11_ISRC1_PB23_RW          = SPA(E_SNONE            , E_PAGE_11, 0x3A)    ,
++    E_REG_P11_ISRC1_PB24_RW          = SPA(E_SNONE            , E_PAGE_11, 0x3B)    ,
++    E_REG_P11_ISRC1_PB25_RW          = SPA(E_SNONE            , E_PAGE_11, 0x3C),
++    E_REG_P11_ISRC1_PB26_RW          = SPA(E_SNONE            , E_PAGE_11, 0x3D),
++    E_REG_P11_ISRC1_PB27_RW          = SPA(E_SNONE            , E_PAGE_11, 0x3E),
++    E_REG_P11_ISRC2_HB0_RW           = SPA(E_SNONE            , E_PAGE_11, 0x40),
++    E_REG_P11_ISRC2_HB1_RW           = SPA(E_SNONE            , E_PAGE_11, 0x41),
++    E_REG_P11_ISRC2_HB2_RW           = SPA(E_SNONE            , E_PAGE_11, 0x42),
++    E_REG_P11_ISRC2_PB0_RW           = SPA(E_SNONE            , E_PAGE_11, 0x43),
++    E_REG_P11_ISRC2_PB1_RW           = SPA(E_SNONE            , E_PAGE_11, 0x44),
++    E_REG_P11_ISRC2_PB2_RW           = SPA(E_SNONE            , E_PAGE_11, 0x45),
++    E_REG_P11_ISRC2_PB3_RW           = SPA(E_SNONE            , E_PAGE_11, 0x46),
++    E_REG_P11_ISRC2_PB4_RW           = SPA(E_SNONE            , E_PAGE_11, 0x47),
++    E_REG_P11_ISRC2_PB5_RW           = SPA(E_SNONE            , E_PAGE_11, 0x48),
++    E_REG_P11_ISRC2_PB6_RW           = SPA(E_SNONE            , E_PAGE_11, 0x49),
++    E_REG_P11_ISRC2_PB7_RW           = SPA(E_SNONE            , E_PAGE_11, 0x4A),
++    E_REG_P11_ISRC2_PB8_RW           = SPA(E_SNONE            , E_PAGE_11, 0x4B),
++    E_REG_P11_ISRC2_PB9_RW           = SPA(E_SNONE            , E_PAGE_11, 0x4C),
++    E_REG_P11_ISRC2_PB10_RW          = SPA(E_SNONE            , E_PAGE_11, 0x4D),
++    E_REG_P11_ISRC2_PB11_RW          = SPA(E_SNONE            , E_PAGE_11, 0x4E),
++    E_REG_P11_ISRC2_PB12_RW          = SPA(E_SNONE            , E_PAGE_11, 0x4F),
++    E_REG_P11_ISRC2_PB13_RW          = SPA(E_SNONE            , E_PAGE_11, 0x50),
++    E_REG_P11_ISRC2_PB14_RW          = SPA(E_SNONE            , E_PAGE_11, 0x51),
++    E_REG_P11_ISRC2_PB15_RW          = SPA(E_SNONE            , E_PAGE_11, 0x52),
++    E_REG_P11_ISRC2_PB16_RW          = SPA(E_SNONE            , E_PAGE_11, 0x53),
++    E_REG_P11_ISRC2_PB17_RW          = SPA(E_SNONE            , E_PAGE_11, 0x54),
++    E_REG_P11_ISRC2_PB18_RW          = SPA(E_SNONE            , E_PAGE_11, 0x55),
++    E_REG_P11_ISRC2_PB19_RW          = SPA(E_SNONE            , E_PAGE_11, 0x56),
++    E_REG_P11_ISRC2_PB20_RW          = SPA(E_SNONE            , E_PAGE_11, 0x57),
++    E_REG_P11_ISRC2_PB21_RW          = SPA(E_SNONE            , E_PAGE_11, 0x58),
++    E_REG_P11_ISRC2_PB22_RW          = SPA(E_SNONE            , E_PAGE_11, 0x59),
++    E_REG_P11_ISRC2_PB23_RW          = SPA(E_SNONE            , E_PAGE_11, 0x5A),
++    E_REG_P11_ISRC2_PB24_RW          = SPA(E_SNONE            , E_PAGE_11, 0x5B),
++    E_REG_P11_ISRC2_PB25_RW          = SPA(E_SNONE            , E_PAGE_11, 0x5C),
++    E_REG_P11_ISRC2_PB26_RW          = SPA(E_SNONE            , E_PAGE_11, 0x5D),
++    E_REG_P11_ISRC2_PB27_RW          = SPA(E_SNONE            , E_PAGE_11, 0x5E),
++    E_REG_P11_ACP_HB0_RW             = SPA(E_SNONE            , E_PAGE_11, 0x60),
++    E_REG_P11_ACP_HB1_RW             = SPA(E_SNONE            , E_PAGE_11, 0x61),
++    E_REG_P11_ACP_HB2_RW             = SPA(E_SNONE            , E_PAGE_11, 0x62),
++    E_REG_P11_ACP_PB0_RW             = SPA(E_SNONE            , E_PAGE_11, 0x63),
++    E_REG_P11_ACP_PB1_RW             = SPA(E_SNONE            , E_PAGE_11, 0x64),
++    E_REG_P11_ACP_PB2_RW             = SPA(E_SNONE            , E_PAGE_11, 0x65),
++    E_REG_P11_ACP_PB3_RW             = SPA(E_SNONE            , E_PAGE_11, 0x66),
++    E_REG_P11_ACP_PB4_RW             = SPA(E_SNONE            , E_PAGE_11, 0x67),
++    E_REG_P11_ACP_PB5_RW             = SPA(E_SNONE            , E_PAGE_11, 0x68),
++    E_REG_P11_ACP_PB6_RW             = SPA(E_SNONE            , E_PAGE_11, 0x69),
++    E_REG_P11_ACP_PB7_RW             = SPA(E_SNONE            , E_PAGE_11, 0x6A),
++    E_REG_P11_ACP_PB8_RW             = SPA(E_SNONE            , E_PAGE_11, 0x6B),
++    E_REG_P11_ACP_PB9_RW             = SPA(E_SNONE            , E_PAGE_11, 0x6C),
++    E_REG_P11_ACP_PB10_RW            = SPA(E_SNONE            , E_PAGE_11, 0x6D),
++    E_REG_P11_ACP_PB11_RW            = SPA(E_SNONE            , E_PAGE_11, 0x6E),
++    E_REG_P11_ACP_PB12_RW            = SPA(E_SNONE            , E_PAGE_11, 0x6F),
++    E_REG_P11_ACP_PB13_RW            = SPA(E_SNONE            , E_PAGE_11, 0x70),
++    E_REG_P11_ACP_PB14_RW            = SPA(E_SNONE            , E_PAGE_11, 0x71),
++    E_REG_P11_ACP_PB15_RW            = SPA(E_SNONE            , E_PAGE_11, 0x72),
++    E_REG_P11_ACP_PB16_RW            = SPA(E_SNONE            , E_PAGE_11, 0x73),
++    E_REG_P11_ACP_PB17_RW            = SPA(E_SNONE            , E_PAGE_11, 0x74),
++    E_REG_P11_ACP_PB18_RW            = SPA(E_SNONE            , E_PAGE_11, 0x75),
++    E_REG_P11_ACP_PB19_RW            = SPA(E_SNONE            , E_PAGE_11, 0x76),
++    E_REG_P11_ACP_PB20_RW            = SPA(E_SNONE            , E_PAGE_11, 0x77),
++    E_REG_P11_ACP_PB21_RW            = SPA(E_SNONE            , E_PAGE_11, 0x78),
++    E_REG_P11_ACP_PB22_RW            = SPA(E_SNONE            , E_PAGE_11, 0x79),
++    E_REG_P11_ACP_PB23_RW            = SPA(E_SNONE            , E_PAGE_11, 0x7A),
++    E_REG_P11_ACP_PB24_RW            = SPA(E_SNONE            , E_PAGE_11, 0x7B),
++    E_REG_P11_ACP_PB25_RW            = SPA(E_SNONE            , E_PAGE_11, 0x7C),
++    E_REG_P11_ACP_PB26_RW            = SPA(E_SNONE            , E_PAGE_11, 0x7D),
++    E_REG_P11_ACP_PB27_RW            = SPA(E_SNONE            , E_PAGE_11, 0x7E),
++    E_REG_P13_GMD_0_HB0_RW           = SPA(E_SNONE            , E_PAGE_13, 0x00),
++    E_REG_P13_GMD_0_HB1_RW           = SPA(E_SNONE            , E_PAGE_13, 0x01),
++    E_REG_P13_GMD_0_HB2_RW           = SPA(E_SNONE            , E_PAGE_13, 0x02),
++    E_REG_P13_GMD_0_PB0_RW           = SPA(E_SNONE            , E_PAGE_13, 0x03),
++    E_REG_P13_GMD_0_PB1_RW           = SPA(E_SNONE            , E_PAGE_13, 0x04),
++    E_REG_P13_GMD_0_PB2_RW           = SPA(E_SNONE            , E_PAGE_13, 0x05),
++    E_REG_P13_GMD_0_PB3_RW           = SPA(E_SNONE            , E_PAGE_13, 0x06),
++    E_REG_P13_GMD_0_PB4_RW           = SPA(E_SNONE            , E_PAGE_13, 0x07),
++    E_REG_P13_GMD_0_PB5_RW           = SPA(E_SNONE            , E_PAGE_13, 0x08),
++    E_REG_P13_GMD_0_PB6_RW           = SPA(E_SNONE            , E_PAGE_13, 0x09),
++    E_REG_P13_GMD_0_PB7_RW           = SPA(E_SNONE            , E_PAGE_13, 0x0A),
++    E_REG_P13_GMD_0_PB8_RW           = SPA(E_SNONE            , E_PAGE_13, 0x0B),
++    E_REG_P13_GMD_0_PB9_RW           = SPA(E_SNONE            , E_PAGE_13, 0x0C),
++    E_REG_P13_GMD_0_PB10_RW          = SPA(E_SNONE            , E_PAGE_13, 0x0D),
++    E_REG_P13_GMD_0_PB11_RW          = SPA(E_SNONE            , E_PAGE_13, 0x0E),
++    E_REG_P13_GMD_0_PB12_RW          = SPA(E_SNONE            , E_PAGE_13, 0x0F),
++    E_REG_P13_GMD_0_PB13_RW          = SPA(E_SNONE            , E_PAGE_13, 0x10),
++    E_REG_P13_GMD_0_PB14_RW          = SPA(E_SNONE            , E_PAGE_13, 0x11),
++    E_REG_P13_GMD_0_PB15_RW          = SPA(E_SNONE            , E_PAGE_13, 0x12),
++    E_REG_P13_GMD_0_PB16_RW          = SPA(E_SNONE            , E_PAGE_13, 0x13),
++    E_REG_P13_GMD_0_PB17_RW          = SPA(E_SNONE            , E_PAGE_13, 0x14),
++    E_REG_P13_GMD_0_PB18_RW          = SPA(E_SNONE            , E_PAGE_13, 0x15),
++    E_REG_P13_GMD_0_PB19_RW          = SPA(E_SNONE            , E_PAGE_13, 0x16),
++    E_REG_P13_GMD_0_PB20_RW          = SPA(E_SNONE            , E_PAGE_13, 0x17),
++    E_REG_P13_GMD_0_PB21_RW          = SPA(E_SNONE            , E_PAGE_13, 0x18),
++    E_REG_P13_GMD_0_PB22_RW          = SPA(E_SNONE            , E_PAGE_13, 0x19),
++    E_REG_P13_GMD_0_PB23_RW          = SPA(E_SNONE            , E_PAGE_13, 0x1A),
++    E_REG_P13_GMD_0_PB24_RW          = SPA(E_SNONE            , E_PAGE_13, 0x1B),
++    E_REG_P13_GMD_0_PB25_RW          = SPA(E_SNONE            , E_PAGE_13, 0x1C),
++    E_REG_P13_GMD_0_PB26_RW          = SPA(E_SNONE            , E_PAGE_13, 0x1D),
++    E_REG_P13_GMD_0_PB27_RW          = SPA(E_SNONE            , E_PAGE_13, 0x1E),
++    E_REG_P13_GMD_CONTROL_RW         = SPA(E_SNONE            , E_PAGE_13, 0x1F),
++    E_REG_P13_GMD_1_HB0_RW           = SPA(E_SNONE            , E_PAGE_13, 0x20),
++    E_REG_P13_GMD_1_HB1_RW           = SPA(E_SNONE            , E_PAGE_13, 0x21),
++    E_REG_P13_GMD_1_HB2_RW           = SPA(E_SNONE            , E_PAGE_13, 0x22),
++    E_REG_P13_GMD_1_PB0_RW           = SPA(E_SNONE            , E_PAGE_13, 0x23),
++    E_REG_P13_GMD_1_PB1_RW           = SPA(E_SNONE            , E_PAGE_13, 0x24),
++    E_REG_P13_GMD_1_PB2_RW           = SPA(E_SNONE            , E_PAGE_13, 0x25),
++    E_REG_P13_GMD_1_PB3_RW           = SPA(E_SNONE            , E_PAGE_13, 0x26),
++    E_REG_P13_GMD_1_PB4_RW           = SPA(E_SNONE            , E_PAGE_13, 0x27),
++    E_REG_P13_GMD_1_PB5_RW           = SPA(E_SNONE            , E_PAGE_13, 0x28),
++    E_REG_P13_GMD_1_PB6_RW           = SPA(E_SNONE            , E_PAGE_13, 0x29),
++    E_REG_P13_GMD_1_PB7_RW           = SPA(E_SNONE            , E_PAGE_13, 0x2A),
++    E_REG_P13_GMD_1_PB8_RW           = SPA(E_SNONE            , E_PAGE_13, 0x2B),
++    E_REG_P13_GMD_1_PB9_RW           = SPA(E_SNONE            , E_PAGE_13, 0x2C),
++    E_REG_P13_GMD_1_PB10_RW          = SPA(E_SNONE            , E_PAGE_13, 0x2D),
++    E_REG_P13_GMD_1_PB11_RW          = SPA(E_SNONE            , E_PAGE_13, 0x2E),
++    E_REG_P13_GMD_1_PB12_RW          = SPA(E_SNONE            , E_PAGE_13, 0x2F),
++    E_REG_P13_GMD_1_PB13_RW          = SPA(E_SNONE            , E_PAGE_13, 0x30),
++    E_REG_P13_GMD_1_PB14_RW          = SPA(E_SNONE            , E_PAGE_13, 0x31),
++    E_REG_P13_GMD_1_PB15_RW          = SPA(E_SNONE            , E_PAGE_13, 0x32),
++    E_REG_P13_GMD_1_PB16_RW          = SPA(E_SNONE            , E_PAGE_13, 0x33),
++    E_REG_P13_GMD_1_PB17_RW          = SPA(E_SNONE            , E_PAGE_13, 0x34),
++    E_REG_P13_GMD_1_PB18_RW          = SPA(E_SNONE            , E_PAGE_13, 0x35),
++    E_REG_P13_GMD_1_PB19_RW          = SPA(E_SNONE            , E_PAGE_13, 0x36),
++    E_REG_P13_GMD_1_PB20_RW          = SPA(E_SNONE            , E_PAGE_13, 0x37),
++    E_REG_P13_GMD_1_PB21_RW          = SPA(E_SNONE            , E_PAGE_13, 0x38),
++    E_REG_P13_GMD_1_PB22_RW          = SPA(E_SNONE            , E_PAGE_13, 0x39),
++    E_REG_P13_GMD_1_PB23_RW          = SPA(E_SNONE            , E_PAGE_13, 0x3A),
++    E_REG_P13_GMD_1_PB24_RW          = SPA(E_SNONE            , E_PAGE_13, 0x3B),
++    E_REG_P13_GMD_1_PB25_RW          = SPA(E_SNONE            , E_PAGE_13, 0x3C),
++    E_REG_P13_GMD_1_PB26_RW          = SPA(E_SNONE            , E_PAGE_13, 0x3D),
++    E_REG_P13_GMD_1_PB27_RW          = SPA(E_SNONE            , E_PAGE_13, 0x3E)
++};
++#undef SPR
++
++/**
++ * Register bitfield masks, with a macro to allow binary initializers.
++ * Enum names are derived directly from TDA998x register and bitfield names.
++ */
++#define BINARY(d7,d6,d5,d4,d3,d2,d1,d0) \
++    (((d7)<<7)|((d6)<<6)|((d5)<<5)|((d4)<<4)|((d3)<<3)|((d2)<<2)|((d1)<<1)|(d0))
++
++enum _eMaskReg
++{
++    E_MASKREG_NONE                          = BINARY(0,0,0,0, 0,0,0,0),
++    E_MASKREG_ALL                           = BINARY(1,1,1,1, 1,1,1,1),
++
++    /* N4 features flags read from version register:
++     * not_h = no HDCP support
++     * not_s = no scaler support
++     *
++     * N5 = a flag that is not a register bit, but is derived by the
++     * driver from the new N5 registers DWIN_RE_DE and DWIN_FE_DE,
++     * because the N5 device still uses the N4 version register value.
++     * This bit position would clash with version register, so is not
++     * present in the driver's copy (uDeviceVersion) of the version 
++     * register, but only in the driver's features byte (uDeviceFeatures).
++     */
++
++     /* CEC Masks*/
++
++    E_MASKREG_CEC_INTERRUPTSTATUS_hdmi_int  = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_CEC_INTERRUPTSTATUS_cec_int   = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_CEC_RXSHPDINTENA_ena_hpd_int  = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_CEC_RXSHPDINTENA_ena_rxs_int  = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_CEC_RXSHPDINT_hpd_int         = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_CEC_RXSHPDINT_rxs_int         = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_CEC_RXSHPDLEV_hpd_level       = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_CEC_RXSHPDLEV_rxs_level       = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_CEC_ENAMODS_dis_fro           = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_CEC_ENAMODS_dis_cclk          = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_CEC_ENAMODS_ena_rxs           = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_CEC_ENAMODS_ena_hdmi          = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_CEC_ENAMODS_ena_cec           = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_CEC_FRO_IM_CLK_CTRL_ghost_dis = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_CEC_FRO_IM_CLK_CTRL_ena_otp   = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_CEC_FRO_IM_CLK_CTRL_imclk_sel = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_CEC_FRO_IM_CLK_CTRL_fro_div   = BINARY(0,0,0,0, 0,0,0,1),
++
++     /* HDMI Masks*/
++    E_MASKREG_P00_VERSION_not_h             = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P00_VERSION_not_s             = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_FEATURE_N5                = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_MAIN_CNTRL0_scaler        = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_MAIN_CNTRL0_cehs          = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_MAIN_CNTRL0_cecs          = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_MAIN_CNTRL0_dehs          = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_MAIN_CNTRL0_decs          = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_MAIN_CNTRL0_sr            = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_SR_REG_sr_i2c_ms          = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_SR_REG_sr_audio           = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_DDC_DISABLE_ddc_dis       = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_CCLK_ON_cclk_ddc_on       = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_I2C_MASTER_app_strt_lat    = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_I2C_MASTER_dis_filt        = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_I2C_MASTER_dis_mm          = BINARY(0,0,0,0, 0,0,0,1),
++
++#ifdef TMFL_TDA19989
++    E_MASKREG_FEAT_POWER_DOWN_spdif          = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_FEAT_POWER_DOWN_otp            = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_FEAT_POWER_DOWN_csc            = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_FEAT_POWER_DOWN_prefilt        = BINARY(0,0,0,0, 0,0,0,1),
++    E_MASKREG_FEAT_POWER_DOWN_all            = BINARY(0,0,0,0, 1,1,1,1),
++#endif
++
++    E_MASKREG_P00_INT_FLAGS_0_r0            = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_INT_FLAGS_0_pj            = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_INT_FLAGS_0_sha_1         = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P00_INT_FLAGS_0_bstatus       = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_INT_FLAGS_0_bcaps         = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_INT_FLAGS_0_t0            = BINARY(0,0,0,0, 0,1,0,0),
++    /*E_MASKREG_P00_INT_FLAGS_0_hpd           = BINARY(0,0,0,0, 0,0,1,0),*/
++    E_MASKREG_P00_INT_FLAGS_0_encrypt       = BINARY(0,0,0,0, 0,0,0,1),
++
++    /*E_MASKREG_P00_INT_FLAGS_1_hpd_in        = BINARY(1,0,0,0, 0,0,0,0),*/
++    E_MASKREG_P00_INT_FLAGS_1_sw_int        = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_INT_FLAGS_1_sc_deil       = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P00_INT_FLAGS_1_sc_vid        = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_INT_FLAGS_1_sc_out        = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_INT_FLAGS_1_sc_in         = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_INT_FLAGS_1_otp           = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_INT_FLAGS_1_vs_rpt        = BINARY(0,0,0,0, 0,0,0,1),
++    /*E_MASKREG_P00_INT_FLAGS_2_rx_sense      = BINARY(0,0,0,0, 0,0,0,1),*/
++    E_MASKREG_P00_INT_FLAGS_2_edid_blk_rd   = BINARY(0,0,0,0, 0,0,1,0),
++
++    /*E_MASKREG_P00_INT_FLAGS_3_rxs_fil       = BINARY(0,0,0,0, 0,0,0,1),*/
++    
++    E_MASKREG_P00_SW_INT_sw_int             = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_ENA_ACLK_ena_aclk         = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_GND_ACLK_gnd_aclk         = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_ENA_VP_0_ena_vp7          = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_0_ena_vp6          = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_0_ena_vp5          = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_0_ena_vp4          = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_0_ena_vp3          = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_ENA_VP_0_ena_vp2          = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_ENA_VP_0_ena_vp1          = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_ENA_VP_0_ena_vp0          = BINARY(0,0,0,0, 0,0,0,1),
++    
++    E_MASKREG_P00_ENA_VP_1_ena_vp15         = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_1_ena_vp14         = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_1_ena_vp13         = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_1_ena_vp12         = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_1_ena_vp11         = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_ENA_VP_1_ena_vp10         = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_ENA_VP_1_ena_vp9          = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_ENA_VP_1_ena_vp8          = BINARY(0,0,0,0, 0,0,0,1),
++    
++    E_MASKREG_P00_ENA_VP_2_ena_vp23         = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_2_ena_vp22         = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_2_ena_vp21         = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_2_ena_vp20         = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_ENA_VP_2_ena_vp19         = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_ENA_VP_2_ena_vp18         = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_ENA_VP_2_ena_vp17         = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_ENA_VP_2_ena_vp16         = BINARY(0,0,0,0, 0,0,0,1),
++    
++    E_MASKREG_P00_ENA_AP_ena_ap7            = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_AP_ena_ap6            = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_AP_ena_ap5            = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P00_ENA_AP_ena_ap4            = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_ENA_AP_ena_ap3            = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_ENA_AP_ena_ap2            = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_ENA_AP_ena_ap1            = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_ENA_AP_ena_ap0            = BINARY(0,0,0,0, 0,0,0,1),
++    
++    E_MASKREG_P00_VIP_CNTRL_0_mirr_a        = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_0_swap_a        = BINARY(0,1,1,1, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_0_mirr_b        = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_0_swap_b        = BINARY(0,0,0,0, 0,1,1,1),
++
++    E_MASKREG_P00_VIP_CNTRL_1_mirr_c        = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_1_swap_c        = BINARY(0,1,1,1, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_1_mirr_d        = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_1_swap_d        = BINARY(0,0,0,0, 0,1,1,1),
++
++    E_MASKREG_P00_VIP_CNTRL_2_mirr_e        = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_2_swap_e        = BINARY(0,1,1,1, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_2_mirr_f        = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_2_swap_f        = BINARY(0,0,0,0, 0,1,1,1),
++
++#ifdef TMFL_TDA19989
++    E_MASKREG_P00_MUX_VP_VIP_OUT_red        = BINARY(0,0,1,1, 0,0,0,0),
++    E_MASKREG_P00_MUX_VP_VIP_OUT_green      = BINARY(0,0,0,0, 1,1,0,0),
++    E_MASKREG_P00_MUX_VP_VIP_OUT_blue       = BINARY(0,0,0,0, 0,0,1,1),
++#endif
++
++    E_MASKREG_P00_VIP_CNTRL_3_edge          = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_3_de_int        = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_3_sp_sync       = BINARY(0,0,1,1, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_3_emb           = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_3_v_tgl         = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_VIP_CNTRL_3_h_tgl         = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_VIP_CNTRL_3_x_tgl         = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_VIP_CNTRL_4_tst_pat       = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_4_tst_656       = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_4_656_alt       = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_4_ccir656       = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_VIP_CNTRL_4_blankit       = BINARY(0,0,0,0, 1,1,0,0),
++    E_MASKREG_P00_VIP_CNTRL_4_blc           = BINARY(0,0,0,0, 0,0,1,1),
++
++    E_MASKREG_P00_VIP_CNTRL_5_sp_cnt        = BINARY(0,0,0,0, 0,1,1,0),
++    E_MASKREG_P00_VIP_CNTRL_5_ckcase        = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_MAT_CONTRL_mat_bp         = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_MAT_CONTRL_mat_sc         = BINARY(0,0,0,0, 0,0,1,1),
++
++#ifdef TMFL_TDA19989
++    E_MASKREG_P00_VIDFORMAT_3d              = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_VIDFORMAT_3d_neg_vs       = BINARY(0,1,0,0, 0,0,0,0),
++#endif
++    E_MASKREG_P00_VIDFORMAT_vidformat       = BINARY(0,0,0,1, 1,1,1,1),
++
++    E_MASKREG_P00_TBG_CNTRL_0_sync_once     = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_TBG_CNTRL_0_sync_mthd     = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_TBG_CNTRL_0_frame_dis     = BINARY(0,0,1,0, 0,0,0,0),
++
++    E_MASKREG_P00_TBG_CNTRL_1_dwin_dis      = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_TBG_CNTRL_1_vhx_ext       = BINARY(0,0,1,1, 1,0,0,0),
++    E_MASKREG_P00_TBG_CNTRL_1_vhx_ext_vs    = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P00_TBG_CNTRL_1_vhx_ext_hs    = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P00_TBG_CNTRL_1_vhx_ext_de    = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_TBG_CNTRL_1_vh_tgl        = BINARY(0,0,0,0, 0,1,1,1),
++    E_MASKREG_P00_TBG_CNTRL_1_vh_tgl_2      = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_TBG_CNTRL_1_vh_tgl_1      = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_TBG_CNTRL_1_vh_tgl_0      = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_I2C_TIMER_RI              = BINARY(0,0,0,0, 1,1,1,1),
++    E_MASKREG_P00_I2C_TIMER_PJ              = BINARY(1,1,1,1, 0,0,0,0),
++
++    E_MASKREG_P00_HVF_CNTRL_0_sm            = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P00_HVF_CNTRL_0_rwb           = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_HVF_CNTRL_0_prefil        = BINARY(0,0,0,0, 1,1,0,0),
++    E_MASKREG_P00_HVF_CNTRL_0_intpol        = BINARY(0,0,0,0, 0,0,1,1),
++
++    E_MASKREG_P00_HVF_CNTRL_1_semi_planar   = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_HVF_CNTRL_1_pad           = BINARY(0,0,1,1, 0,0,0,0),
++    E_MASKREG_P00_HVF_CNTRL_1_vqr           = BINARY(0,0,0,0, 1,1,0,0),
++    E_MASKREG_P00_HVF_CNTRL_1_yuvblk        = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_HVF_CNTRL_1_for           = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_TIMER_H_wd_clksel         = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_TIMER_H_tim_h             = BINARY(0,0,0,0, 0,0,1,1),
++
++    E_MASKREG_P00_DEBUG_PROBE_sel           = BINARY(0,0,1,1, 0,0,0,0),
++    E_MASKREG_P00_DEBUG_PROBE_bypass        = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P00_DEBUG_PROBE_vid_de        = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_DEBUG_PROBE_di_de         = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P00_DEBUG_PROBE_woo_en        = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P00_I2S_FORMAT_i2s_format     = BINARY(0,0,0,0, 0,0,1,1),
++
++    E_MASKREG_P00_I2S_FORMAT_i2s_data_size  = BINARY(0,0,0,0, 1,1,0,0),
++
++    E_MASKREG_P00_AIP_CLKSEL_dst_rate       = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P00_AIP_CLKSEL_sel_aip_SHIFT  = 3,
++    E_MASKREG_P00_AIP_CLKSEL_sel_aip        = BINARY(0,0,1,1, 1,0,0,0),
++    E_MASKREG_P00_AIP_CLKSEL_sel_pol_clk    = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P00_AIP_CLKSEL_sel_fs         = BINARY(0,0,0,0, 0,0,1,1),
++    E_MASKREG_P01_SC_VIDFORMAT_lut_sel      = BINARY(1,1,0,0, 0,0,0,0),
++    E_MASKREG_P01_SC_VIDFORMAT_vid_format_o = BINARY(0,0,1,1, 1,0,0,0),
++    E_MASKREG_P01_SC_VIDFORMAT_vid_format_i = BINARY(0,0,0,0, 0,1,1,1),
++
++    E_MASKREG_P01_SC_CNTRL_phases_h         = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P01_SC_CNTRL_il_out_on        = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P01_SC_CNTRL_phases_v         = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P01_SC_CNTRL_vs_on            = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P01_SC_CNTRL_deil_on          = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P01_VIDFORMAT_vidformat       = BINARY(0,0,0,0, 0,1,1,1),
++
++    E_MASKREG_P01_TBG_CNTRL_0_sync_once     = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P01_TBG_CNTRL_0_sync_mthd     = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P01_TBG_CNTRL_0_frame_dis     = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P01_TBG_CNTRL_0_top_ext       = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P01_TBG_CNTRL_0_de_ext        = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P01_TBG_CNTRL_0_top_sel       = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P01_TBG_CNTRL_0_top_tgl       = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P02_PLL_SERIAL_1_srl_man_iz   = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P02_PLL_SERIAL_1_srl_iz       = BINARY(0,0,0,0, 0,1,1,0),
++    E_MASKREG_P02_PLL_SERIAL_1_srl_fdn      = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P02_PLL_SERIAL_2_srl_pr       = BINARY(1,1,1,1, 0,0,0,0),
++    E_MASKREG_P02_PLL_SERIAL_2_srl_nosc     = BINARY(0,0,0,0, 0,0,1,1),
++
++    E_MASKREG_P02_PLL_SERIAL_3_srl_pxin_sel = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P02_PLL_SERIAL_3_srl_de       = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P02_PLL_SERIAL_3_srl_ccir     = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P02_SERIALIZER_srl_phase3     = BINARY(1,1,1,1, 0,0,0,0),
++    E_MASKREG_P02_SERIALIZER_srl_phase2     = BINARY(0,0,0,0, 1,1,1,1),
++
++    E_MASKREG_P02_BUFFER_OUT_srl_force      = BINARY(0,0,0,0, 1,1,0,0),
++    E_MASKREG_P02_BUFFER_OUT_srl_clk        = BINARY(0,0,0,0, 0,0,1,1),
++
++    E_MASKREG_P02_PLL_SCG1_scg_fdn          = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P02_PLL_SCG2_bypass_scg       = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P02_PLL_SCG2_selpllclkin      = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P02_PLL_SCG2_scg_nosc         = BINARY(0,0,0,0, 0,0,1,1),
++
++    E_MASKREG_P02_VAI_PLL_pllde_hvp         = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P02_VAI_PLL_pllscg_hvp        = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P02_VAI_PLL_pllsrl_hvp        = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P02_VAI_PLL_pllscg_lock       = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P02_VAI_PLL_pllsrl_lock       = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P02_AUDIO_DIV_audio_div       = BINARY(0,0,0,0, 0,1,1,1),
++
++    E_MASKREG_P02_TEST1_srldat              = BINARY(1,1,0,0, 0,0,0,0),
++    E_MASKREG_P02_TEST1_tst_nosc            = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P02_TEST1_tst_enahvp          = BINARY(0,0,0,0, 0,0,0,1),
++
++    //E_MASKREG_P02_TEST2_pwd1v8              = BINARY(0,0,0,0, 0,0,1,0),
++    //E_MASKREG_P02_TEST2_divtestoe           = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P02_SEL_CLK_ena_sc_clk        = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P02_SEL_CLK_sel_vrf_clk       = BINARY(0,0,0,0, 0,1,1,0),
++    E_MASKREG_P02_SEL_CLK_sel_clk1          = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P02_BUFF_OUT2_force_dat2      = BINARY(0,0,1,1, 0,0,0,0),
++    E_MASKREG_P02_BUFF_OUT2_force_dat1      = BINARY(0,0,0,0, 1,1,0,0),
++    E_MASKREG_P02_BUFF_OUT2_force_dat0      = BINARY(0,0,0,0, 0,0,1,1),
++
++    E_MASKREG_P09_EDID_CTRL_edid_rd         = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P11_AIP_CNTRL_0_rst_cts       = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P11_AIP_CNTRL_0_acr_man       = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P11_AIP_CNTRL_0_layout        = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P11_AIP_CNTRL_0_swap          = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P11_AIP_CNTRL_0_rst_fifo      = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P11_CA_I2S_hbr_chstat_4       = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P11_CA_I2S_ca_i2s             = BINARY(0,0,0,1, 1,1,1,1),
++
++    E_MASKREG_P11_GC_AVMUTE_set_mute        = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P11_GC_AVMUTE_clr_mute        = BINARY(0,0,0,0, 0,0,0,1),
++    E_MASKREG_P11_GC_AVMUTE_setclr_mute     = BINARY(0,0,0,0, 0,0,1,1),
++
++    E_MASKREG_P11_CTS_N_m_sel               = BINARY(0,0,1,1, 0,0,0,0),
++    E_MASKREG_P11_CTS_N_k_sel               = BINARY(0,0,0,0, 0,1,1,1),
++
++    E_MASKREG_P11_ENC_CNTRL_ctl_code        = BINARY(0,0,0,0, 1,1,0,0),
++    E_MASKREG_P11_ENC_CNTRL_rst_sel         = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P11_ENC_CNTRL_rst_enc         = BINARY(0,0,0,0, 0,0,0,1),
++    E_MASKREG_P11_DIP_FLAGS_force_null      = BINARY(1,0,0,0, 0,0,0,0),
++    E_MASKREG_P11_DIP_FLAGS_null            = BINARY(0,1,0,0, 0,0,0,0),
++    E_MASKREG_P11_DIP_FLAGS_acp             = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P11_DIP_FLAGS_isrc2           = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P11_DIP_FLAGS_isrc1           = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P11_DIP_FLAGS_gc              = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P11_DIP_FLAGS_acr             = BINARY(0,0,0,0, 0,0,0,1),
++
++    E_MASKREG_P11_DIP_IF_FLAGS_if5          = BINARY(0,0,1,0, 0,0,0,0),
++    E_MASKREG_P11_DIP_IF_FLAGS_if4          = BINARY(0,0,0,1, 0,0,0,0),
++    E_MASKREG_P11_DIP_IF_FLAGS_if3          = BINARY(0,0,0,0, 1,0,0,0),
++    E_MASKREG_P11_DIP_IF_FLAGS_if2          = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P11_DIP_IF_FLAGS_if1          = BINARY(0,0,0,0, 0,0,1,0),
++
++    E_MASKREG_P13_GMD_CONTROL_buf_sel       = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P13_GMD_CONTROL_enable        = BINARY(0,0,0,0, 0,0,0,1)
++};
++#undef BINARY
++
++/**
++ * 3 enum for the video formats :
++ *  - 1 used in the E_REG_P00_VIDFORMAT_W register
++ *  - 1 for new format that are not prefetch
++ *  - 1 for PC
++ */
++#define REGVFMT_INVALID 0xFF
++
++enum _eRegVfmt {
++   E_REGVFMT_640x480p_60Hz     = 0, /* 1 */
++   E_REGVFMT_720x480p_60Hz     ,    /* 2/3 */
++   E_REGVFMT_1280x720p_60Hz    ,    /* 4 */
++   E_REGVFMT_1920x1080i_60Hz   ,    /* 5 */
++   E_REGVFMT_720x480i_60Hz     ,    /* 6/4 */
++   E_REGVFMT_720x240p_60Hz     ,    /*NT 8/9 */
++   E_REGVFMT_1920x1080p_60Hz   ,    /* 16 */
++   E_REGVFMT_720x576p_50Hz     ,    /* 17/18 */
++   E_REGVFMT_1280x720p_50Hz    ,    /* 19 */
++   E_REGVFMT_1920x1080i_50Hz   ,    /* 20 */
++   E_REGVFMT_720x576i_50Hz     ,    /* 21/22 */
++   E_REGVFMT_720x288p_50Hz     ,    /* 23/24 */
++   E_REGVFMT_1920x1080p_50Hz   ,    /* 31 */
++#ifdef TMFL_RGB_DDR_12BITS
++   E_REGVFMT_1920x1080p_24Hz   ,    /* 32 */
++   E_REGVFMT_1440x576p_50Hz    ,    /* 29/30 */
++   E_REGVFMT_1440x480p_60Hz    ,    /* 14/15 */
++   E_REGVFMT_2880x480p_60Hz    ,    /* 35/36 */
++   E_REGVFMT_2880x576p_50Hz    ,    /* 37/38 */
++   E_REGVFMT_2880x480i_60Hz    ,    /* 10/11*/
++   E_REGVFMT_2880x480i_60Hz_PR2,    /* 10/11*/
++   E_REGVFMT_2880x480i_60Hz_PR4,    /* 10/11*/
++   E_REGVFMT_2880x576i_50Hz    ,    /* 25/26 */
++   E_REGVFMT_2880x576i_50Hz_PR2,    /* 25/26 */
++   E_REGVFMT_720x480p_60Hz_FP  ,    /* 2/3 FP */
++   E_REGVFMT_1280x720p_60Hz_FP ,    /* 4 FP */
++   E_REGVFMT_720x576p_50Hz_FP  ,    /* 17/18 FP */
++   E_REGVFMT_1280x720p_50Hz_FP ,    /* 19 FP */
++   E_REGVFMT_1920x1080p_24Hz_FP,    /* 32 FP */
++   E_REGVFMT_1920x1080p_25Hz_FP,    /* 33 FP */
++   E_REGVFMT_1920x1080p_30Hz_FP,    /* 34 FP */
++   E_REGVFMT_1920x1080i_60Hz_FP,    /* 5 FP */
++   E_REGVFMT_1920x1080i_50Hz_FP,    /* 20 FP */
++#endif
++   E_REGVFMT_MAX_PREFETCH      ,
++   E_REGVFMT_NUM_PREFETCH      = E_REGVFMT_MAX_PREFETCH
++};
++
++enum _eRegVfmtExtra {
++#ifndef TMFL_RGB_DDR_12BITS
++   E_REGVFMT_1920x1080p_24Hz   = E_REGVFMT_MAX_PREFETCH, /* 32 */
++   E_REGVFMT_1920x1080p_25Hz   , /* 33 */
++#else
++   E_REGVFMT_1920x1080p_25Hz   = E_REGVFMT_MAX_PREFETCH,
++#endif
++   E_REGVFMT_1920x1080p_30Hz,   /* 34 */
++   E_REGVFMT_1280x720p_24Hz,    /* 60 */
++   E_REGVFMT_1280x720p_25Hz,    /* 61 */
++   E_REGVFMT_1280x720p_30Hz ,   /* 62 */
++#ifndef TMFL_RGB_DDR_12BITS
++   E_REGVFMT_1280x720p_60Hz_FP,
++   E_REGVFMT_1920x1080i_60Hz_FP,
++   E_REGVFMT_1280x720p_50Hz_FP,
++   E_REGVFMT_1920x1080i_50Hz_FP,
++   E_REGVFMT_1920x1080p_24Hz_FP,
++   E_REGVFMT_1920x1080p_25Hz_FP,
++   E_REGVFMT_1920x1080p_30Hz_FP,
++#endif
++   E_REGVFMT_1280x720p_24Hz_FP,
++   E_REGVFMT_1280x720p_25Hz_FP,
++   E_REGVFMT_1280x720p_30Hz_FP,
++   E_REGVFMT_MAX_EXTRA         ,
++   E_REGVFMT_NUM_EXTRA         = E_REGVFMT_MAX_EXTRA - E_REGVFMT_MAX_PREFETCH
++};
++
++#ifdef FORMAT_PC
++enum _eRegVfmtPC {
++    E_REGVFMT_640x480p_72Hz     = E_REGVFMT_MAX_EXTRA,
++    E_REGVFMT_640x480p_75Hz     ,
++    E_REGVFMT_640x480p_85Hz     ,
++    E_REGVFMT_800x600p_60Hz     ,
++    E_REGVFMT_800x600p_72Hz     ,
++    E_REGVFMT_800x600p_75Hz     ,
++    E_REGVFMT_800x600p_85Hz     ,
++    E_REGVFMT_1024x768p_60Hz    ,
++    E_REGVFMT_1024x768p_70Hz    ,
++    E_REGVFMT_1024x768p_75Hz    ,
++    E_REGVFMT_1280x768p_60Hz    ,
++    E_REGVFMT_1280x1024p_60Hz   ,
++    E_REGVFMT_1360x768p_60Hz    ,
++    E_REGVFMT_1400x1050p_60Hz   ,
++    E_REGVFMT_1600x1200p_60Hz   ,
++    E_REGVFMT_1280x1024p_85Hz   ,
++    E_REGVFMT_MAX_PC            ,
++    E_REGVFMT_NUM_PC            = E_REGVFMT_MAX_PC - E_REGVFMT_MAX_EXTRA
++};
++#define E_REGVFMT_MAX E_REGVFMT_MAX_PC
++#else
++#define E_REGVFMT_MAX E_REGVFMT_MAX_EXTRA
++#endif /*FORMAT_PC*/
++
++#define PREFETCH(fmt) ((fmt) < E_REGVFMT_MAX_PREFETCH)
++#define EXTRA(fmt) (!PREFETCH(fmt))
++#define PCFORMAT(fmt) ((fmt) >= E_REGVFMT_MAX_EXTRA)/* PR1570 FIXED */
++#define BASE(fmt) (PREFETCH(fmt)?(fmt):(fmt)-E_REGVFMT_MAX_PREFETCH)
++
++
++/**
++ * An enum for the video input formats used in the E_REG_P01_SC_VIDFORMAT_W
++ * register
++ */
++enum _eRegVfmtScIn
++{
++    E_REGVFMT_SCIN_480i_60Hz        = 0,
++    E_REGVFMT_SCIN_576i_50Hz        = 1,
++    E_REGVFMT_SCIN_480p_60Hz        = 2,
++    E_REGVFMT_SCIN_576p_50Hz        = 3,
++    E_REGVFMT_SCIN_720p_50Hz_60Hz   = 4,
++    E_REGVFMT_SCIN_1080i_50Hz_60Hz  = 5,
++    E_REGVFMT_SCIN_MAX              = 5,
++    E_REGVFMT_SCIN_NUM              = 6,
++    E_REGVFMT_SCIN_INVALID          = 6
++};
++ 
++/**
++ * An enum to list all supported pixel clock frequencies in kHz
++ */
++enum _ePixClk
++{
++    E_PIXCLK_25175      = 0,
++    E_PIXCLK_25200      = 1,
++    E_PIXCLK_27000      = 2,
++    E_PIXCLK_27027      = 3,
++    E_PIXCLK_54000      = 4,
++    E_PIXCLK_54054      = 5,
++    E_PIXCLK_59400      = 6,
++    E_PIXCLK_74175      = 7,
++    E_PIXCLK_74250      = 8,
++    E_PIXCLK_148350     = 9,
++    E_PIXCLK_148500     = 10,
++    E_PIXCLK_108000     = 11,
++    E_PIXCLK_108108     = 12,
++#ifndef FORMAT_PC
++    E_PIXCLK_MAX        = 12,
++    E_PIXCLK_INVALID    = 13,
++    E_PIXCLK_NUM        = 13
++#else /* FORMAT_PC */
++    E_PIXCLK_31500      = 13,
++    E_PIXCLK_36000      = 14,
++    E_PIXCLK_40000      = 15,
++    E_PIXCLK_49500      = 16,
++    E_PIXCLK_50000      = 17,
++    E_PIXCLK_56250      = 18,
++    E_PIXCLK_65000      = 19,
++    E_PIXCLK_75000      = 20,
++    E_PIXCLK_78750      = 21,
++    E_PIXCLK_79500      = 22,
++    E_PIXCLK_85500      = 23,
++    E_PIXCLK_PC_108000  = 24,
++    E_PIXCLK_121750     = 25,
++    E_PIXCLK_162000     = 26,
++    E_PIXCLK_MAX        = 26,
++    E_PIXCLK_INVALID    = 27,
++    E_PIXCLK_NUM        = 27
++#endif /* FORMAT_PC */
++};
++
++/**
++ * An enum to list all device version codes supported by this driver.
++ * The values form a list, with non-zero version codes first in any order.
++ * The E_DEV_VERSION_END_LIST must be the last value in the list.
++ */
++enum _eDevVersion
++{
++    E_DEV_VERSION_N2            = 0x101,    /**< TDA9989 n2  */
++    E_DEV_VERSION_TDA19989      = 0x201,    /**< TDA19989    */
++    E_DEV_VERSION_TDA19989_N2   = 0x202,    /**< TDA19989 N2 */
++    E_DEV_VERSION_TDA19988      = 0x301,    /**< TDA19988    */
++    E_DEV_VERSION_LIST_END      = 0x00,
++    E_DEV_VERSION_LIST_NUM      = 5         /**< Number of items in list */
++};
++
++/**
++ * An enum to list all CEA Data Block Tag Codes we may find in EDID.
++ */
++enum _eCeaBlockTags
++{
++    E_CEA_RESERVED_0     = 0x00,
++    E_CEA_AUDIO_BLOCK    = 0x01,
++    E_CEA_VIDEO_BLOCK    = 0x02,
++    E_CEA_VSDB           = 0x03,
++    E_CEA_SPEAKER_ALLOC  = 0x04,
++    E_CEA_VESA_DTC       = 0x05,
++    E_CEA_RESERVED_6     = 0x06,
++    E_CEA_EXTENDED       = 0x07
++};
++
++/**
++ * An enum to list all CEA Data Block Extended Tag Codes we may find in EDID.
++ */
++enum _eCeaExtendedBlockTags
++{
++    EXT_CEA_MISC_VIDEO_FIELDS        = 0x00,
++    EXT_CEA_VS_VIDEO_DB              = 0x01,
++    EXT_CEA_COLORIMETRY_DB           = 0x05,
++    EXT_CEA_MISC_AUDIO_FIELDS        = 0x10,
++    EXT_CEA_VS_AUDIO_DB              = 0x11
++};
++
++/** A typedef for colourspace values */
++typedef enum
++{
++    HDMITX_CS_RGB_FULL              = 0,    /**< RGB Full (PC) */
++    HDMITX_CS_RGB_LIMITED           = 1,    /**< RGB Limited (TV) */
++    HDMITX_CS_YUV_ITU_BT601         = 2,    /**< YUV ITUBT601 (SDTV) */
++    HDMITX_CS_YUV_ITU_BT709         = 3,    /**< YUV ITUBT709 (HDTV) */
++    HDMITX_CS_NUM                   = 4     /**< Number Cspaces we support */
++} tmbslTDA9989Colourspace_t;
++
++/** Matrix register block size */
++#define MATRIX_PRESET_SIZE          31
++
++/** Matrix register block size */
++#define MATRIX_PRESET_QTY           12
++
++/** The enum that vectors us into the MatrixPreset table */
++enum _eMatrixPresetIndex
++{
++    E_MATRIX_RGBF_2_RGBL    = 0,
++    E_MATRIX_RGBF_2_BT601   = 1,
++    E_MATRIX_RGBF_2_BT709   = 2,
++    E_MATRIX_RGBL_2_RGBF    = 3,
++    E_MATRIX_RGBL_2_BT601   = 4,
++    E_MATRIX_RGBL_2_BT709   = 5,
++    E_MATRIX_BT601_2_RGBF   = 6,
++    E_MATRIX_BT601_2_RGBL   = 7,
++    E_MATRIX_BT601_2_BT709  = 8,
++    E_MATRIX_BT709_2_RGBF   = 9,
++    E_MATRIX_BT709_2_RGBL   = 10,
++    E_MATRIX_BT709_2_BT601  = 11
++};   
++
++/** EDID i2c address */
++#define DDC_EDID_ADDRESS        0xA0
++
++/** EDID alternate i2c address */
++#define DDC_EDID_ADDRESS_ALT    0xA2
++
++/** EDID Segment Pointer address */
++#define DDC_SGMT_PTR_ADDRESS    0x60
++
++/** EDID DTD block descriptor size */
++#define EDID_DTD_BLK_SIZE       0x12
++
++/** number of detailed timing descriptor stored in pDis */
++#define NUMBER_DTD_STORED       10
++
++/** MUX_AP audio selection values */
++#define MUX_AP_SELECT_I2S     0xE4
++#define MUX_AP_SELECT_SPDIF   0x27
++
++#define TDA19989_MUX_AP_SELECT_I2S     0x64
++#define TDA19989_MUX_AP_SELECT_SPDIF   0x24
++
++/** VSWING default value */
++#define HDMI_TX_VSWING_VALUE 0x09
++
++
++/**
++ * \brief A structure type to form arrays that hold a series of registers and
++ * values
++ */
++typedef struct _tmHdmiTxRegVal_t
++{
++    UInt16 Reg;
++    UInt8  Val;
++} tmHdmiTxRegVal_t;
++
++/**
++ * \brief A structure type to form arrays that hold a series of registers,
++ * bitfield masks and bitfield values
++ */
++typedef struct _tmHdmiTxRegMaskVal_t
++{
++    UInt16 Reg;
++    UInt8  Mask;
++    UInt8  Val;
++} tmHdmiTxRegMaskVal_t;
++
++/**
++ * \brief A function pointer type to call a function and return a result
++ */
++typedef tmErrorCode_t (FUNC_PTR * ptmHdmiTxFunc_t) (tmUnitSelect_t txUnit);
++
++/**
++ * \brief The structure of a TM998x object, one per device unit
++ ****************************************************************************
++ ** Copy changes to kTestDisNames tab in "HDMI Driver - Register List.xls" **
++ ****************************************************************************
++ */
++
++typedef struct _tmHdmiTxobject_t
++{
++    /** Component State */
++    tmbslTDA9989State_t state;
++
++    /** Count of events ignored by setState() */
++    UInt8 nIgnoredEvents;
++
++    /** Device unit number */
++    tmUnitSelect_t txUnit;
++
++    /** Device I2C slave address */
++    UInt8 uHwAddress;
++
++    /** System function to write to the I2C driver */
++    ptmbslHdmiTxSysFunc_t sysFuncWrite;
++
++    /** System function to read from the I2C driver */
++    ptmbslHdmiTxSysFunc_t sysFuncRead;
++
++    /** System function to read EDID blocks via the I2C driver */
++    ptmbslHdmiTxSysFuncEdid_t sysFuncEdidRead;
++
++    /** System function to run a timer */
++    ptmbslHdmiTxSysFuncTimer_t sysFuncTimer;
++
++    /** Array of registered interrupt handler callback functions */
++    ptmbslHdmiTxCallback_t funcIntCallbacks[HDMITX_CALLBACK_INT_NUM];
++
++    /** Flags to store disable or enable of interrupts */
++    UInt16 InterruptsEnable; /* At moment used only for VS Interrupt */
++
++    /** Device version(s) supported by this component */
++    UInt16 uSupportedVersions[E_DEV_VERSION_LIST_NUM];
++
++    /** Device version read from register, with features flags masked out */
++    UInt16 uDeviceVersion;
++
++    /** Device features flags read from version register */
++    UInt8 uDeviceFeatures;
++
++    /** The device's power state */
++    tmbslHdmiTxPowerState_t ePowerState;
++
++    /*=== E D I D ===*/
++
++    /** EDID Use alternative i2c address flag */
++    Bool bEdidAlternateAddr;
++
++    /** The sink type set by the user (may or may not match EdidSinkType) */
++    tmbslHdmiTxSinkType_t sinkType;
++
++    /** EDID Sink Type for receiver */
++    tmbslHdmiTxSinkType_t EdidSinkType;
++
++    /** EDID AI_Support from HDMI VSDB */
++    Bool EdidSinkAi;
++
++    /** EDID CEA flags from extension block */
++    UInt8 EdidCeaFlags;
++
++    /** EDID CEA flags from colorimetry block */
++    UInt8 EdidCeaXVYCCFlags;
++
++    /** EDID latency information */
++    tmbslHdmiTxEdidLatency_t EdidLatency;
++
++    /** EDID 3D data structure */
++    tmbslHdmiTxEdidExtraVsdbData_t EdidExtraVsdbData;
++
++    /** EDID Read Status */
++    UInt8 EdidStatus;
++
++    /** NB DTD stored in EdidDTD */
++    UInt8 NbDTDStored;
++
++    /** EDID Detailed Timing Descriptor */
++    tmbslHdmiTxEdidDtd_t EdidDTD[NUMBER_DTD_STORED];
++
++    /** EDID First Moniteur descriptor */
++    tmbslHdmiTxEdidFirstMD_t EdidFirstMonitorDescriptor;
++
++    /** EDID Second Moniteur descriptor */
++    tmbslHdmiTxEdidSecondMD_t EdidSecondMonitorDescriptor;
++
++    /** EDID Other Moniteur descriptor */
++    tmbslHdmiTxEdidOtherMD_t EdidOtherMonitorDescriptor;
++
++    /** EDID supported Short Video Descriptors */
++    UInt8 EdidVFmts[HDMI_TX_SVD_MAX_CNT];
++
++    /** Counter for supported short video descriptors */
++    UInt8 EdidSvdCnt;
++
++    /** EDID supported Short Audio Descriptors */
++    tmbslHdmiTxEdidSad_t EdidAFmts[HDMI_TX_SAD_MAX_CNT];
++
++    /** Counter for supported short audio descriptors */
++    UInt8 EdidSadCnt;
++
++    /** EDID block workspace */
++    UInt8 EdidBlock[EDID_BLOCK_SIZE];
++
++    /** EDID Block Count */
++    UInt8 EdidBlockCnt;
++
++    /** CEC Source Address read from EDID as "A.B.C.D" nibbles */
++    UInt16 EdidSourceAddress;
++
++    /** EDID block number which is reading */
++    UInt8 EdidBlockRequested;
++
++    /** EDID read on going*/
++    Bool EdidReadStarted;
++
++    /** Parameter for return edid block requested by application */
++    tmbslHdmiTxEdidToApp_t EdidToApp;
++
++    /** EDID Basic Display Parameters */
++    tmbslHdmiTxEdidBDParam_t EDIDBasicDisplayParam;
++    
++#ifdef TMFL_HDCP_SUPPORT
++    /*=== H D C P === */
++
++    Bool HDCPIgnoreEncrypt;
++
++    /** Configured DDC I2C slave address */
++    UInt8 HdcpSlaveAddress;
++
++    /** Configured mode of our transmitter device */
++    tmbslHdmiTxHdcpTxMode_t HdcpTxMode;
++
++    /** Configured HDCP options */
++    tmbslHdmiTxHdcpOptions_t HdcpOptions;
++
++    /** BCAPS read from sink */
++    UInt8 HdcpBcaps;
++
++    /** BSTATUS read from sink */
++    UInt16 HdcpBstatus;
++
++    /** Device value generated for Ri=Ri' comparison */
++    UInt16 HdcpRi;
++
++    /** Device HDCP FSM state */
++    UInt8 HdcpFsmState;
++
++    /** Device failure state that caused T0 interrupt */
++    UInt8 HdcpT0FailState;
++
++    /** Otp Seed key from user*/
++    UInt16 HdcpSeed;
++
++    /* Key Selection Vector for transmitter */
++    UInt8 HdcpAksv[HDMITX_KSV_BYTES_PER_DEVICE];
++
++    /** Local callback scheduled to be called after HdcpFuncRemainingMs */
++    ptmHdmiTxFunc_t HdcpFuncScheduled;
++
++    /** Period in ms after which to call HdcpFuncScheduled; 0=disabled */
++    UInt16 HdcpFuncRemainingMs;
++
++    /** Configured period in ms after which to do HDCP check */
++    UInt16 HdcpCheckIntervalMs;
++
++    /** Period in ms until next HDCP check */
++    UInt16 HdcpCheckRemainingMs;
++
++    /** Number of the HDCP check since HDCP was started; 0=disabled */
++    UInt8 HdcpCheckNum;
++
++    /** Configured number of HDCP checks to do after HDCP is started */
++    UInt8 HdcpChecksToDo;
++#endif /* TMFL_HDCP_SUPPORT */
++
++    /*=== V I D E O ===*/
++
++    /** Current EIA/CEA video input format */
++    tmbslHdmiTxVidFmt_t vinFmt;
++
++    /** Current EIA/CEA video output format */
++    tmbslHdmiTxVidFmt_t voutFmt;
++    
++    /** Current pix Rate*/
++    tmbslHdmiTxPixRate_t pixRate;
++
++    /** Video input mode */
++    tmbslHdmiTxVinMode_t vinMode;
++
++    /** Video output mode */
++    tmbslHdmiTxVoutMode_t voutMode;
++
++    /** Vertical output frequency */
++    tmbslHdmiTxVfreq_t voutFreq;
++
++    /** Current scaler mode */
++    tmbslHdmiTxScaMode_t scaMode;
++
++    /** Current upsampler mode */
++    tmbslHdmiTxUpsampleMode_t upsampleMode;
++
++    /** Current pixel repetition count */
++    UInt8 pixelRepeatCount;
++
++    /** Status of hot plug detect pin last read at interrupt */
++    tmbslHdmiTxHotPlug_t hotPlugStatus;
++
++    /** Status of rx sense detect pin last read at interrupt */
++    tmbslHdmiTxRxSense_t rxSenseStatus;
++
++    /** Current register page */
++    UInt8 curRegPage;
++
++    /** Shadow copies of write-only registers with bitfields */
++    UInt8 shadowReg[E_SNUM];
++
++    /** TRUE: Blue screen is the previous test pattern ; FALSE: is not */
++    Bool prevFilterPattern;
++
++    /** TRUE: last screen is test pattern ; FALSE: is not */
++    Bool prevPattern;
++
++    /** TRUE: Unit has been initialized; FALSE: not initialized */
++    Bool bInitialized;
++
++    tmbslHdmiTxVQR_t        dviVqr;
++
++    /** TRUE: 3D Frame Packing video is ongoing */
++    Bool h3dFpOn;
++
++} tmHdmiTxobject_t;
++
++/**
++ * \The structure of registers for video format , 
++ *  used by PC_formats and chip_unknown formats
++ */
++
++typedef struct _tmHdmiTxVidReg_t
++{
++    UInt16  nPix;
++    UInt16  nLine;
++    UInt8   VsLineStart;
++    UInt16  VsPixStart;
++    UInt8   VsLineEnd;
++    UInt16  VsPixEnd;
++    UInt16  HsStart;
++    UInt16  HsEnd;
++    UInt8   ActiveVideoStart;
++    UInt16  ActiveVideoEnd;
++    UInt16  DeStart;
++    UInt16  DeEnd;
++    UInt16  ActiveSpaceStart;
++    UInt16  ActiveSpaceEnd;
++} tmHdmiTxVidReg_t;
++
++
++/*============================================================================*/
++/*                       EXTERN DATA DEFINITION                               */
++/*============================================================================*/
++
++#include "tmbslTDA9989_local_otp.h"
++
++extern RAM_DAT  tmHdmiTxobject_t gHdmiTxInstance[HDMITX_UNITS_MAX];
++extern CONST_DAT UInt8 kPageIndexToPage[E_PAGE_NUM];
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++
++tmErrorCode_t    checkUnitSetDis (tmUnitSelect_t txUnit,
++                                  tmHdmiTxobject_t **ppDis);
++tmErrorCode_t    getHwRegisters (tmHdmiTxobject_t *pDis, 
++                                 UInt16 regShadPageAddr,
++                                 UInt8 *pData, UInt16 lenData);
++tmErrorCode_t    getHwRegister (tmHdmiTxobject_t *pDis, 
++                                UInt16 regShadPageAddr,
++                                UInt8 *pRegValue);
++tmErrorCode_t    setHwRegisters (tmHdmiTxobject_t *pDis, 
++                                 UInt16 regShadPageAddr,
++                                 UInt8 *pData, UInt16 lenData);
++tmErrorCode_t    setHwRegisterMsbLsb (tmHdmiTxobject_t *pDis, 
++                                      UInt16 regShadPageAddr, 
++                                      UInt16 regWord);
++
++tmErrorCode_t    setHwRegister_main (tmHdmiTxobject_t *pDis, 
++                                UInt16 regShadPageAddr,
++                                UInt8 regValue);
++tmErrorCode_t    setHwRegisterField (tmHdmiTxobject_t *pDis,
++                                     UInt16 regShadPageAddr,
++                                     UInt8 fieldMask, UInt8 fieldValue);
++tmErrorCode_t    setHwRegisterFieldTable(tmHdmiTxobject_t *pDis,
++                                     const tmHdmiTxRegMaskVal_t *pTable);
++tmErrorCode_t    getCECHwRegister(tmHdmiTxobject_t *pDis, 
++                                    UInt16  regAddr,
++                                    UInt8   *pRegValue);
++tmErrorCode_t    setCECHwRegister(tmHdmiTxobject_t *pDis, 
++                                    UInt16  regAddr, 
++                                    UInt8   regValue);
++
++tmErrorCode_t    lmemcpy (void *pTable1,
++                        const void *pTable2,
++                        UInt Size);
++tmErrorCode_t    lmemset (void *pTable1,
++                        const UInt8 value,
++                        UInt Size);
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMBSLTDA9989_LOCAL_H */
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local_otp.h b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local_otp.h
+new file mode 100755
+index 0000000..43cb78d
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmbslTDA9989/src/tmbslTDA9989_local_otp.h
+@@ -0,0 +1,54 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmbslTDA9989_local_otp.h
++ *
++ * \version       %version: 1 %
++ *
++*/
++
++#ifndef TMBSLTDA9989_LOCAL_OTP_H
++#define TMBSLTDA9989_LOCAL_OTP_H
++
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++#define BINARY(d7,d6,d5,d4,d3,d2,d1,d0) \
++    (((d7)<<7)|((d6)<<6)|((d5)<<5)|((d4)<<4)|((d3)<<3)|((d2)<<2)|((d1)<<1)|(d0))
++
++enum _eRegOtp {
++#ifdef TMFL_HDCP_SUPPORT
++    E_REG_P12_CTRL_W                 = SPA(E_SP12_CTRL        , E_PAGE_12, 0x40),
++#ifdef BCAPS_REPEATER
++    E_REG_P12_BCAPS_W                = SPA(E_SP12_BCAPS       , E_PAGE_12, 0x49),
++#else
++    E_REG_P12_BCAPS_W                = SPA(E_SNONE            , E_PAGE_12, 0x49),
++#endif /* BCAPS_REPEATER */
++#endif
++    E_REG_P12_TX0_RW                 = SPA(E_SNONE            , E_PAGE_12, 0x97),
++    E_REG_P12_TX3_RW                 = SPA(E_SNONE            , E_PAGE_12, 0x9A),
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++    E_REG_P12_TX4_RW                 = SPA(E_SNONE            , E_PAGE_12, 0x9B),
++#endif
++    E_REG_P12_TX33_RW                = SPA(E_SNONE            , E_PAGE_12, 0xB8),
++};
++
++enum _eMaskRegOtp
++{
++    E_MASKREG_P12_TX33_hdmi                 = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P12_TX0_sr_hdcp               = BINARY(0,0,0,0, 0,0,0,1),
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++    E_MASKREG_P12_TX4_pd_rg                 = BINARY(0,0,0,0, 0,1,0,0),
++    E_MASKREG_P12_TX4_pd_ram                = BINARY(0,0,0,0, 0,0,1,0),
++    E_MASKREG_P12_TX4_pd_hdcp               = BINARY(0,0,0,0, 0,0,0,1),
++    E_MASKREG_P12_TX4_pd_all                = BINARY(0,0,0,0, 0,1,1,1),
++#endif
++};
++
++#endif /* TMBSLTDA9989_LOCAL_OTP_H */
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_IW.h b/drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_IW.h
+new file mode 100755
+index 0000000..fac6b7d
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_IW.h
+@@ -0,0 +1,305 @@
++/**
++ * Copyright (C) 2007 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiCEC_IW.h
++ *
++ * \version       $Revision: 1 $
++ *
++ * \date          $Date:  $
++ *
++ * \brief         devlib driver component API for the CEC messages
++ *
++ * \section refs  Reference Documents
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   $History: tmdlHdmiCEC_IW.h $
++ *
++   \endverbatim
++ *
++*/
++
++#ifndef TMDLHDMICEC_IW_H
++#define TMDLHDMICEC_IW_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#include <linux/kernel.h>
++#else
++#ifdef TMFL_OS_WINDOWS
++#define _WIN32_WINNT 0x0500
++#include "windows.h"
++#else
++#include "RTL.h"
++#endif
++#endif
++
++#include "tmNxTypes.h"
++#include "tmdlHdmiCEC_Types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++/*============================================================================*/
++/*                       TYPE DEFINITIONS                                     */
++/*============================================================================*/
++typedef void (*tmdlHdmiTxIWFuncPtr_t) (void);
++typedef UInt8 tmdlHdmiTxIWTaskHandle_t;
++typedef UInt8 tmdlHdmiTxIWQueueHandle_t;
++#ifdef TMFL_OS_WINDOWS
++typedef HANDLE tmdlHdmiTxIWSemHandle_t;
++#else
++typedef UInt8 tmdlHdmiTxIWSemHandle_t;
++#endif
++
++/**
++ * \brief Enum listing all available devices for enable/disable interrupts
++ */
++typedef enum
++{
++    TMDL_HDMI_IW_RX_1,
++    TMDL_HDMI_IW_RX_2,
++    TMDL_HDMI_IW_TX_1,
++    TMDL_HDMI_IW_TX_2,
++    TMDL_HDMI_IW_CEC_1,
++    TMDL_HDMI_IW_CEC_2
++} tmdlHdmiIWDeviceInterrupt_t;
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++
++/**
++    \brief This function creates a task and allocates all the necessary
++           resources. Note that creating a task do not start it automatically,
++           an explicit call to IWTaskStart must be made.
++
++    \param pFunc      Pointer to the function that will be executed in the task context.
++    \param Priority   Priority of the task. The minimum priority is 0, the maximum is 255.
++    \param StackSize  Size of the stack to allocate for this task.
++    \param pHandle    Pointer to the handle buffer.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_NO_RESOURCES: the resource is not available
++            - TMDL_ERR_DLHDMIRX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWTaskCreate(tmdlHdmiTxIWFuncPtr_t pFunc,UInt8 priority, UInt16 stackSize, tmdlHdmiTxIWTaskHandle_t *pHandle);
++
++/*============================================================================*/
++
++/**
++    \brief    This function destroys an existing task and frees resources used by it.
++
++    \param Handle        Handle of the task to be destroyed, as returned by IWTaskCreate.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_RESOURCE_NOT_OWNED: the caller does not own 
++              the resource
++            - TMDL_ERR_DLHDMIRX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWTaskDestroy(tmdlHdmiTxIWTaskHandle_t handle);
++
++/*============================================================================*/
++
++/**
++    \brief This function start an existing task.
++
++    \param Handle        Handle of the task to be started.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_ALREADY_STARTED: the function is already started
++            - TMDL_ERR_DLHDMIRX_NOT_STARTED: the function is not started
++            - TMDL_ERR_DLHDMIRX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWTaskStart(tmdlHdmiTxIWTaskHandle_t handle);
++
++/*============================================================================*/
++
++/**
++    \brief This function blocks the current task for the specified amount time. This is a passive wait.
++
++    \param Duration    Duration of the task blocking in milliseconds.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_NO_RESOURCES: the resource is not available
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWWait(UInt16 duration);
++
++/*============================================================================*/
++
++/**
++    \brief This function creates a message queue.
++
++    \param QueueSize    Maximum number of messages in the message queue.
++    \param pHandle        Pointer to the handle buffer.
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMIRX_NO_RESOURCES: the resource is not available
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWQueueCreate(UInt8 queueSize, tmdlHdmiTxIWQueueHandle_t *pHandle);
++
++/*============================================================================*/
++
++/**
++    \brief This function destroys an existing message queue.
++
++    \param    Handle        Handle of the queue to be destroyed.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMIRX_RESOURCE_NOT_OWNED: the caller does not own 
++              the resource
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWQueueDestroy(tmdlHdmiTxIWQueueHandle_t handle);
++
++/*============================================================================*/
++
++/**
++    \brief This function sends a message into the specified message queue.
++
++    \param Handle    Handle of the queue that will receive the message.
++    \param Message   Message to be sent.
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMIRX_RESOURCE_NOT_OWNED: the caller does not own 
++              the resource
++            - TMDL_ERR_DLHDMIRX_FULL: the queue is full
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWQueueSend(tmdlHdmiTxIWQueueHandle_t handle, UInt8 message);
++
++/*============================================================================*/
++
++/**
++    \brief This function reads a message from the specified message queue.
++
++    \param    Handle        Handle of the queue from which to read the message.
++    \param    pMessage      Pointer to the message buffer.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMIRX_RESOURCE_NOT_OWNED: the caller does not own 
++              the resource
++            - TMDL_ERR_DLHDMIRX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWQueueReceive(tmdlHdmiTxIWQueueHandle_t handle, UInt8 *pMessage);
++
++/*============================================================================*/
++
++/**
++    \brief This function creates a semaphore.
++
++    \param     pHandle    Pointer to the handle buffer.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_NO_RESOURCES: the resource is not available
++            - TMDL_ERR_DLHDMIRX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreCreate(tmdlHdmiTxIWSemHandle_t *pHandle);
++
++/*============================================================================*/
++
++/**
++    \brief This function destroys an existing semaphore.
++
++    \param    Handle        Handle of the semaphore to be destroyed.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreDestroy(tmdlHdmiTxIWSemHandle_t handle);
++
++/*============================================================================*/
++
++/**
++    \brief This function acquires the specified semaphore.
++
++    \param Handle        Handle of the semaphore to be acquired.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreP(tmdlHdmiTxIWSemHandle_t handle);
++
++/*============================================================================*/
++
++/**
++    \brief This function releases the specified semaphore.
++
++    \param    Handle        Handle of the semaphore to be released.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMIRX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreV(tmdlHdmiTxIWSemHandle_t handle);
++
++/******************************************************************************
++    \brief  This function disables the interrupts for a specific device.
++
++    \param
++
++    \return The call result:
++            - TM_OK: the call was successful
++
++******************************************************************************/
++void tmdlHdmiTxIWDisableInterrupts(tmdlHdmiIWDeviceInterrupt_t device);
++
++/******************************************************************************
++    \brief  This function enables the interrupts for a specific device.
++
++    \param
++
++    \return The call result:
++            - TM_OK: the call was successful
++
++******************************************************************************/
++void tmdlHdmiTxIWEnableInterrupts(tmdlHdmiIWDeviceInterrupt_t device);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMICEC_IW_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_Linux.c b/drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_Linux.c
+new file mode 100755
+index 0000000..a775288
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_Linux.c
+@@ -0,0 +1,436 @@
++/*============================================================================*/
++/*                             INCLUDE FILES                                  */
++/*============================================================================*/
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/types.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++
++#include "tmdlHdmiCEC_IW.h"
++#include "tmNxTypes.h"
++#include "tmdlHdmiCEC.h"
++#include "tmdlHdmiCEC_cfg.h"
++
++struct i2c_client *GetThisI2cClient(void);
++unsigned char  my_i2c_data[255];
++
++/*============================================================================*/
++/*                          MACROS                                            */
++/*============================================================================*/
++#define RETIF(cond, rslt) if ((cond)){return (rslt);}
++#define I2C_M_WR 0
++
++/*============================================================================*/
++/*                          FUNCTIONS DECLARATIONS                            */
++/*============================================================================*/
++
++
++tmErrorCode_t           I2cReadFunction(tmdlHdmiCecSysArgs_t *pSysArgs);
++tmErrorCode_t           I2cWriteFunction(tmdlHdmiCecSysArgs_t *pSysArgs);
++
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS                               */
++/*============================================================================*/
++
++
++#define COMMAND_TASK_PRIORITY_0  250
++#define COMMAND_TASK_STACKSIZE_0 128
++#define COMMAND_TASK_QUEUESIZE_0 8
++
++/* I2C adress of the unit */
++#ifdef TMFL_TDA9996
++	#define UNIT_I2C_ADDRESS_0 0x60 /* I2C Address of TDA9950 */
++#else
++	#define UNIT_I2C_ADDRESS_0 0x34 /* I2C Address of TDA9950 */
++#endif
++
++
++
++/*============================================================================*/
++/*                       VARIABLES DECLARATIONS                               */
++/*============================================================================*/
++
++
++tmdlHdmiCecCapabilities_t CeccapabilitiesList = {TMDL_HDMICEC_DEVICE_UNKNOWN, CEC_VERSION_1_3a};
++
++tmdlHdmiCecDriverConfigTable_t CecdriverConfigTable[MAX_UNITS] = {
++    {
++    COMMAND_TASK_PRIORITY_0,
++    COMMAND_TASK_STACKSIZE_0,
++    COMMAND_TASK_QUEUESIZE_0,
++    UNIT_I2C_ADDRESS_0,
++    I2cReadFunction,
++    I2cWriteFunction,
++    &CeccapabilitiesList
++    }
++};
++
++
++int blockwrite_reg(struct i2c_client *client,
++		   u8 reg, u16 alength, u8 *val, u16 *out_len)
++{
++   int err = 0,i,initiator,receiver;
++   struct i2c_msg msg[1];
++    
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++   
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = alength+1;
++   msg->buf = my_i2c_data;
++   
++   msg->buf[0] = reg;   
++   for (i=0; i<alength; i++) {
++      msg->buf[i+1] = val[i];
++/*       printk(KERN_INFO "buf[%d]=%d val[%d]=%d\n",i+1,msg->buf[i+1],i,val[i]); */
++   }
++   
++   err = i2c_transfer(client->adapter, msg, 1);
++   udelay(50);
++
++   if (reg==7) {
++      /* CEC message */
++      extern char *cec_opcode(int op);
++      initiator = (msg->buf[3] >> 4) & 0x0f;
++      receiver = msg->buf[3] & 0x0f;
++/*       printk(KERN_INFO "reg:%d alength:%d \n",reg, alength); */
++      if (alength==3) {
++         printk(KERN_INFO "hdmicec:polling:[%x--->%x] \n", initiator,receiver);
++      }
++      else {
++         printk(KERN_INFO "hdmicec:Tx:[%x--->%x] %s %02x%02x%02x%02x\n", \
++                initiator,receiver,cec_opcode(msg->buf[4]),msg->buf[4],msg->buf[5],msg->buf[6],msg->buf[7]);
++      }
++   }
++/*    dev_dbg(&client->dev, "<%s> i2c Block write at 0x%x, " */
++/*            "*val=%d flags=%d byte[%d] err=%d\n", */
++/*            __func__, data[0], data[1], msg->flags, i, err); */
++   return (err < 0?err:0);
++
++#if 0
++   int err = 0, i;
++   struct i2c_msg msg[1];
++   u8 data[2];
++
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = 2;
++   msg->buf = data;
++
++   /* high byte goes out first */
++   data[0] = reg >> 8;
++
++   for (i = 0; i < alength - 1; i++) {
++      data[1] = val[i];
++      err = i2c_transfer(client->adapter, msg, 1);
++      udelay(50);
++      dev_dbg(&client->dev, "<%s> i2c Block write at 0x%x, "
++	      "*val=%d flags=%d byte[%d] err=%d\n",
++	      __func__, data[0], data[1], msg->flags, i, err);
++      if (err < 0)
++	 break;
++   }
++   /* set the number of bytes written*/
++   *out_len = i;
++
++   if (err < 0) {
++      dev_err(&client->dev, "<%s> ERROR:  i2c Block Write at 0x%x, "
++	      "*val=%d flags=%d bytes written=%d "
++	      "err=%d\n",
++	      __func__, data[0], data[1], msg->flags, i, err);
++      return err;
++   }
++   return 0;
++#endif
++}
++
++int blockread_reg(struct i2c_client *client, u16 data_length,
++		  u8 reg, u16 alength, u8 *val, u16 *out_len)
++{
++   int err = 0;
++   struct i2c_msg msg[1];
++   u8 data[2];
++
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = 1;
++   msg->buf = data;
++   data[0] = reg; /* High byte goes out first */
++   err = i2c_transfer(client->adapter, msg, 1);
++   if (err<0) goto BLOCK_READ_OUPS;
++
++   msg->flags = I2C_M_RD;
++   msg->len = alength; 
++   msg->buf = val;
++   err = i2c_transfer(client->adapter, msg, 1);
++   if (err<0) goto BLOCK_READ_OUPS;
++
++/*    printk(KERN_INFO "DBG blockread_reg addr:%x len:%d buf:%02x%02x%02x%02x\n",msg->addr,msg->len,\ */
++/*           msg->buf[0],msg->buf[1],msg->buf[2],msg->buf[3]); */
++
++   return 0;
++   
++ BLOCK_READ_OUPS:
++/*    printk(KERN_INFO "DBG blockread_reg addr:%x len:%d ERROR\n",msg->addr,msg->len); */
++   dev_err(&client->dev, "<%s> ERROR:  i2c Read at 0x%x, "
++           "*val=%d flags=%d bytes err=%d\n",
++           __func__, reg, *val, msg->flags, err);
++   return err;
++
++#if 0
++   int err = 0, i;
++   struct i2c_msg msg[1];
++   u8 data[2];
++
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = 1;
++   msg->buf = data;
++
++   /* High byte goes out first */
++   data[0] = reg;
++
++   for (i = 0; i < alength; i++) {
++      err = i2c_transfer(client->adapter, msg, 1);
++      dev_dbg(&client->dev, "<%s> i2c Block Read1 at 0x%x, "
++	      "*val=%d flags=%d err=%d\n",
++	      __func__, data[0], data[1], msg->flags, err);
++      if (err >= 0) {
++	 mdelay(3);
++	 msg->flags = I2C_M_RD;
++	 msg->len = data_length;
++	 err = i2c_transfer(client->adapter, msg, 1);
++      } else
++	 break;
++      if (err >= 0) {
++	 val[i] = 0;
++	 /* High byte comes first */
++	 if (data_length == 1)
++	    val[i] = data[0];
++	 else if (data_length == 2)
++	    val[i] = data[1] + (data[0] << 8);
++	 dev_dbg(&client->dev, "<%s> i2c Block Read2 at 0x%x, "
++		 "*val=%d flags=%d byte=%d "
++		 "err=%d\n",
++		 __func__, reg, val[i], msg->flags, i, err);
++      } else
++	 break;
++   }
++   *out_len = i;
++   dev_info(&client->dev, "<%s> i2c Block Read at 0x%x, bytes read = %d\n",
++	    __func__, reg, *out_len);
++
++   if (err < 0) {
++      dev_err(&client->dev, "<%s> ERROR:  i2c Read at 0x%x, "
++	      "*val=%d flags=%d bytes read=%d err=%d\n",
++	      __func__, reg, *val, msg->flags, i, err);
++      return err;
++   }
++   return 0;
++#endif
++}
++
++
++int write_reg(struct i2c_client *client, u8 reg, u8 val)
++{
++   int err = 0;
++   struct i2c_msg msg[1];
++   u8 data[2];
++   int retries = 0;
++
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++
++ retry:
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = 2;
++   msg->buf = data;
++
++   data[0] = reg;
++   data[1] = val;
++
++   err = i2c_transfer(client->adapter, msg, 1);
++   dev_dbg(&client->dev, "<%s> i2c write at=%x "
++	   "val=%x flags=%d err=%d\n",
++	   __func__, data[0], data[1], msg->flags, err);
++   udelay(50);
++
++/*    printk(KERN_INFO "DBG write_reg addr:%x reg:%d data:%x %s\n",msg->addr,reg,val,(err<0?"ERROR":"")); */
++   if (err >= 0)
++      return 0;
++
++   dev_err(&client->dev, "<%s> ERROR: i2c write at=%x "
++	   "val=%x flags=%d err=%d\n",
++	   __func__, data[0], data[1], msg->flags, err);
++   if (retries <= 5) {
++      dev_info(&client->dev, "Retrying I2C... %d\n", retries);
++      retries++;
++      set_current_state(TASK_UNINTERRUPTIBLE);
++      schedule_timeout(msecs_to_jiffies(20));
++      goto retry;
++   }
++
++   return err;
++}
++
++int read_reg(struct i2c_client *client, u16 data_length, u8 reg, u8 *val)
++{
++   int err = 0;
++   struct i2c_msg msg[1];
++   u8 data[2];
++
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = 1;
++   msg->buf = data;
++
++   data[0] = reg;
++   err = i2c_transfer(client->adapter, msg, 1);
++   dev_dbg(&client->dev, "<%s> i2c Read1 reg=%x val=%d "
++	   "flags=%d err=%d\n",
++	   __func__, reg, data[1], msg->flags, err);
++
++   if (err >= 0) {
++      mdelay(3);
++      msg->flags = I2C_M_RD;
++      msg->len = data_length;
++      err = i2c_transfer(client->adapter, msg, 1);
++   }
++
++   if (err >= 0) {
++      *val = 0;
++      if (data_length == 1)
++	 *val = data[0];
++      else if (data_length == 2)
++	 *val = data[1] + (data[0] << 8);
++      dev_dbg(&client->dev, "<%s> i2c Read2 at 0x%x, *val=%d "
++	      "flags=%d err=%d\n",
++	      __func__, reg, *val, msg->flags, err);
++      return 0;
++   }
++
++   dev_err(&client->dev, "<%s> ERROR: i2c Read at 0x%x, "
++	   "*val=%d flags=%d err=%d\n",
++	   __func__, reg, *val, msg->flags, err);
++   return err;
++}
++
++
++tmErrorCode_t I2cReadFunction (tmdlHdmiCecSysArgs_t *pSysArgs)
++{
++   tmErrorCode_t errCode = TM_OK;
++   u16 outLenght=0;
++   struct i2c_client *client=GetThisI2cClient();
++   u32 client_main_addr=client->addr;
++
++   /* DevLib needs address control, so let it be */ 
++   client->addr=pSysArgs->slaveAddr;
++
++   if (pSysArgs->lenData == 1) {
++      /* single byte */
++      errCode = read_reg(GetThisI2cClient(),1,pSysArgs->firstRegister,pSysArgs->pData);
++   }
++   else {
++      /* block */
++      errCode = blockread_reg(GetThisI2cClient(),1, \
++			      pSysArgs->firstRegister, \
++			      pSysArgs->lenData, \
++			      pSysArgs->pData, &outLenght);
++   }
++   
++   /* restore default client address */
++   client->addr=client_main_addr;
++
++   return errCode;
++}
++
++
++tmErrorCode_t I2cWriteFunction(tmdlHdmiCecSysArgs_t *pSysArgs)
++{
++
++   tmErrorCode_t errCode = TM_OK;
++   u16 outLenght=0;
++   struct i2c_client *client=GetThisI2cClient();
++   u32 client_main_addr=client->addr;
++
++   /* DevLib needs address control, so let it be */ 
++   client->addr=pSysArgs->slaveAddr;
++   
++   if (pSysArgs->lenData == 1) {
++      /* single byte */
++      errCode = write_reg(GetThisI2cClient(),pSysArgs->firstRegister,*pSysArgs->pData);
++   }
++   else {
++      /* block */
++      errCode = blockwrite_reg(GetThisI2cClient(),  \
++                               pSysArgs->firstRegister, \
++                               pSysArgs->lenData,       \
++                               pSysArgs->pData,&outLenght);
++   }
++   
++   /* restore default client address */
++   client->addr=client_main_addr;
++
++   return errCode;
++
++}
++
++tmErrorCode_t tmdlHdmiTxIWWait
++(
++    UInt16 duration
++)
++{
++
++    mdelay((unsigned long)duration);
++
++    return(TM_OK);
++}
++
++tmErrorCode_t tmdlHdmiCecCfgGetConfig
++(
++    tmUnitSelect_t                 unit,
++    tmdlHdmiCecDriverConfigTable_t *pConfig
++)
++{
++    /* check if unit number is in range */
++    RETIF((unit < 0) || (unit >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER)
++
++    /* check if pointer is Null */
++    RETIF(pConfig == Null, TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS)
++
++    *pConfig = CecdriverConfigTable[unit];
++
++    return(TM_OK);
++};
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_cfg.h b/drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_cfg.h
+new file mode 100755
+index 0000000..ecf98d7
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiCEC/cfg/tmdlHdmiCEC_cfg.h
+@@ -0,0 +1,107 @@
++/**
++ * Copyright (C) 2006 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiCEC_cfg.h
++ *
++ * \version       $Revision: 1 $
++ *
++ * \date          $Date:  $
++ *
++ * \brief         devlib driver component API for the CEC messages
++ *
++ * \section refs  Reference Documents
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++ *
++   $History:  tmdlHdmiCEC_cfg.h
++ *
++ *
++   \endverbatim
++ *
++*/
++/******************************************************************************
++******************************************************************************
++*                THIS FILE MUST NOT BE MODIFIED BY CUSTOMER                  *
++******************************************************************************
++*****************************************************************************/
++
++#ifndef TMDLHDMICEC_CFG_H
++#define TMDLHDMICEC_CFG_H
++
++#include "tmNxTypes.h"
++#include "tmdlHdmiCEC_Types.h"
++#include "tmdlHdmiCEC_Functions.h"
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Number of HW units supported by SW driver */
++#define MAX_UNITS 1
++
++
++#ifndef TMFL_CEC_AVAILABLE
++typedef struct _tmbslHdmiTxSysArgs_t
++{
++    UInt8 slaveAddr;
++    UInt8 firstRegister;
++    UInt8 lenData;
++    UInt8 *pData;
++} tmbslHdmiTxSysArgs_t;
++#endif
++
++
++
++/*============================================================================*/
++/*                          TYPES DECLARATIONS                                */
++/*============================================================================*/
++typedef struct
++{
++    UInt8                         commandTaskPriority;
++    UInt8                         commandTaskStackSize;
++    UInt8                         commandTaskQueueSize;
++    UInt8                         i2cAddress;
++    ptmdlHdmiCecSysFunc_t         i2cReadFunction;
++    ptmdlHdmiCecSysFunc_t         i2cWriteFunction;
++    tmdlHdmiCecCapabilities_t     *pCapabilitiesList;
++} tmdlHdmiCecDriverConfigTable_t;
++
++/*============================================================================*/
++/*                       FUNCTIONS DECLARATIONS                               */
++/*============================================================================*/
++
++/**
++    \brief This function allows to the main driver to retrieve its
++           configuration parameters.
++
++    \param pConfig Pointer to the config structure
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiCecCfgGetConfig
++(
++    tmUnitSelect_t                 unit,
++    tmdlHdmiCecDriverConfigTable_t *pConfig
++);
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMICEC_CFG_H */
++
++/*============================================================================*/
++/*                               END OF FILE                                  */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/docs/02_sw_req_an/tmdlHdmiCEC_API.zip b/drivers/video/nxp/comps/tmdlHdmiCEC/docs/02_sw_req_an/tmdlHdmiCEC_API.zip
+new file mode 100755
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+
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC.h b/drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC.h
+new file mode 100755
+index 0000000..f89d8d3
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC.h
+@@ -0,0 +1,46 @@
++//=============================================================================
++// Copyright (C) 2007 NXP N.V., All Rights Reserved.
++// This source code and any compilation or derivative thereof is the proprietary
++// information of NXP N.V. and is confidential in nature. Under no circumstances
++// is this software to be  exposed to or placed under an Open Source License of
++// any type without the expressed written permission of NXP N.V.
++//=============================================================================
++/*!
++    \file    tmdlHdmiCEC.h
++
++	\version 1.0
++
++	\date    04/07/2007
++
++ 	\brief   This provides interfaces description of CEC messages.
++
++    \section refs  Reference Documents
++             TDA998X Driver - tmdlHdmiTx - SCS.doc
++    \note    None.
++ 
++    HISTORY :
++    \verbatim
++     Date          Modified by CRPRNr  TASKNr  Maintenance description
++     -------------|-----------|-------|-------|-----------------------------------
++     04/07/2007   |  F.G      |       |       | Creation.
++     -------------|-----------|-------|-------|-----------------------------------
++    \endverbatim
++*/
++//==========================================================================
++
++#ifndef TMDLHDMICEC_H
++#define TMDLHDMICEC_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++#include "tmNxCompId.h"
++#include "tmdlHdmiCEC_Types.h"
++#include "tmdlHdmiCEC_Functions.h"
++
++#endif /* TMDLHDMICEC_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Functions.h b/drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Functions.h
+new file mode 100755
+index 0000000..fa33118
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Functions.h
+@@ -0,0 +1,3166 @@
++//=============================================================================
++// Copyright (C) 2007 NXP N.V., All Rights Reserved.
++// This source code and any compilation or derivative thereof is the proprietary
++// information of NXP N.V. and is confidential in nature. Under no circumstances
++// is this software to be  exposed to or placed under an Open Source License of
++// any type without the expressed written permission of NXP N.V.
++//=============================================================================
++/*!
++    \file    tmdlHdmiCEC_Functions.h
++
++	\version 1.0
++
++	\date    04/07/2007
++
++ 	\brief   This provides interfaces description of CEC messages.
++
++    \section refs  Reference Documents
++             TDA998X Driver - tmdlHdmiCec - SCS.doc
++    \note    None.
++ 
++    HISTORY :
++    \verbatim
++     Date          Modified by CRPRNr  TASKNr  Maintenance description
++     -------------|-----------|-------|-------|-----------------------------------
++     04/07/2007   |  F.G      |       |       | Creation.
++     -------------|-----------|-------|-------|-----------------------------------
++    \endverbatim
++*/
++//==========================================================================
++
++#ifndef TMDLHDMICEC_FUNCTIONS_H
++#define TMDLHDMICEC_FUNCTIONS_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#include "tmNxTypes.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++/*============================================================================*/
++/*                       PUBLIC FUNCTION DECLARATION                          */
++/*============================================================================*/
++
++//==========================================================================
++/*!
++    \brief This message is reserved for testing purposes
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++	\param UInt8 ReceiverLogicalAddress\n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecAbortMessage
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by a new source to indicate that it has started
++           to transmit a stream OR used in reponse to a <Request Active Source>
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt16 PhysicalAddress \n
++           Physical address of the device.\n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecActiveSource
++(
++   tmInstance_t   Instance,
++   UInt16         PhysicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to indicate the supported CEC version in response
++           to a <Get CEC Version>
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++		 
++	\param UInt8 ReceiverLogicalAddress\n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECVersion_t CECVersion \n
++           Supported CEC Version.\n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVersion
++(
++   tmInstance_t         Instance,
++   UInt8                ReceiverLogicalAddress,
++   tmdlHdmiCECVersion_t CECVersion
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to clear an Analogue timer block of a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++           
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++    
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++           
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++           
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++    
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++    
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n 
++           
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++    
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClearAnalogueTimer
++(
++   tmInstance_t                        Instance,
++   UInt8                               ReceiverLogicalAddress,
++   UInt8                               DayOfMonth,
++   UInt8                               MonthOfYear,
++   UInt16                              StartTime,
++   tmdlHdmiCECDuration_t              *pDuration,
++   UInt8                               RecordingSequence,
++   tmdlHdmiCECAnalogueBroadcastType_t  AnalogueBroadcastType,
++   UInt16                              AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t        BroadcastSystem
++);
++
++
++//==========================================================================
++/*!
++    \brief This message is used to clear a digital timer block of a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++           
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++    
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++           
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++           
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++    
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++    
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClearDigitalTimer
++(
++   tmInstance_t                               Instance,
++   UInt8                                      ReceiverLogicalAddress,
++   UInt8                                      DayOfMonth,
++   UInt8                                      MonthOfYear,
++   UInt16                                     StartTime,
++   tmdlHdmiCECDuration_t                     *pDuration,
++   UInt8                                      RecordingSequence,
++   tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to clear a digital timer block of a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++           
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++    
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++           
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++           
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++    
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++    
++    \param tmdlHdmiCECExternalPlug_t  ExternalPlug \n
++           indicates external plug number (1 to 255 )on the recording device.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClearExternalTimerWithExternalPlug
++(
++   tmInstance_t                Instance,
++   UInt8                       ReceiverLogicalAddress,
++   UInt8                       DayOfMonth,
++   UInt8                       MonthOfYear,
++   UInt16                      StartTime,
++   tmdlHdmiCECDuration_t      *pDuration,
++   UInt8                       RecordingSequence,
++   tmdlHdmiCECExternalPlug_t  ExternalPlug
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to clear a digital timer block of a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++           
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++    
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++           
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++           
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++    
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++    
++    \param tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress \n
++           Defines the path between the TV an a device-thus giving it a physical
++           address within the cluster.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClearExternalTimerWithPhysicalAddress
++(
++   tmInstance_t                           Instance,
++   UInt8                                  ReceiverLogicalAddress,
++   UInt8                                  DayOfMonth,
++   UInt8                                  MonthOfYear,
++   UInt16                                 StartTime,
++   tmdlHdmiCECDuration_t                 *pDuration,
++   UInt8                                  RecordingSequence,
++   tmdlHdmiCECExternalPhysicalAddress_t  ExternalPhysicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to conrol a device's media functions
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECDecControlMode_t DeckControlMode \n
++           Used in message <Deck Control>\n
++    
++    \note  The "Skip Forward / Wind" and "Skip Reverse / Rewind" values are
++           used for example in a DVD as next xhapter and previous chapter and
++           in a VCR as wind and rewind. \n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecDeckControl
++(
++   tmInstance_t                Instance,
++   UInt8                       ReceiverLogicalAddress,
++   tmdlHdmiCECDecControlMode_t DeckControlMode
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to provide a deck's status to the initiator
++           of the <Give Deck Status> message 
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECDecInfo_t DeckInfo \n
++           Information on the device's current status \n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecDeckStatus
++(
++   tmInstance_t         Instance,
++   UInt8                ReceiverLogicalAddress,
++   tmdlHdmiCECDecInfo_t DeckInfo
++);
++
++//==========================================================================
++/*!
++    \brief This message report the vendor ID of this device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt32 VendorID \n
++           Indentifier for a specific Vendor \n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecDeviceVendorID
++(
++   tmInstance_t Instance,
++   UInt32       VendorID
++);
++
++//==========================================================================
++/*!
++    \brief This message is used as a reponse to indicate that the device does
++           not support the requested message type, or that it cannot execute it
++           at the present time.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECFeatureOpcode_t FeatureOpcode \n
++           Opcode of the aborted message. \n
++    
++    \param tmdlHdmiCECAbortReason_t   AbortReason \n
++           The reason why message cannot respond. \n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecFeatureAbort
++(
++   tmInstance_t               Instance,
++   UInt8                      ReceiverLogicalAddress,
++   tmdlHdmiCECFeatureOpcode_t FeatureOpcode,
++   tmdlHdmiCECAbortReason_t   AbortReason
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by a device to enquire which version of CEC
++           the target supports
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetCecVersion
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is sent by a device capable of character generation
++           (for OSD and Menus) to a TV in order to discover the currently selected
++           Menu Language. Also used by a TV during installation to dicover the
++           currently set menu language of other devices.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetMenuLanguage
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is requests an amplifier to send its volume and mute status
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveAudioStatus
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to request the status of a device regardless
++           of whether or not it is the current active source.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECStatusRequest_t StatusRequest \n
++           Allows the initiator to request the status once or on all future state
++           change. Or to cancel a previous <Give Deck Status > ["On"] request. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveDeckStatus
++(
++   tmInstance_t               Instance,
++   UInt8                      ReceiverLogicalAddress,
++   tmdlHdmiCECStatusRequest_t StatusRequest
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to determine the current power status of a 
++           target device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveDevicePowerStatus
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is request the vendor ID from a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveDeviceVendorID
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to request preferred OSD name of a device
++           for use in menus associated with that device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveOsdName
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is a request to a device to return its physical Address
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGivePhysicalAddress
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message request the status of the system audio mode
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveSystemAudioModeStatus
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to request the status of a tuner device
++    
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECStatusRequest_t StatusRequest \n
++           Allows the initiator to request the status once or on all future state
++           change. Or to cancel a previous <Give Tuner Device Status > ["On"] request. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveTunerDeviceStatus
++(
++   tmInstance_t               Instance,
++   UInt8                      ReceiverLogicalAddress,
++   tmdlHdmiCECStatusRequest_t StatusRequest
++);
++
++//==========================================================================
++/*!
++    \brief This message sent by a source device to the TV whenever it enters
++           the active state
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receivers. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecImageViewOn
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by the currently active source to inform the
++           TV that it has no video to be presented to the user, or is going
++           into standby as the result of a lcoal user command on the device.
++    
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8 ReceiverLogicalAddress, \n
++           Address of message receiver. \n
++           
++    \param tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress \n
++           Physical Address of the device. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecInactiveSource
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message request from the TV for a device to show/remove a
++           menu or to query if a device is currently showing a menu
++    
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECMenuRequestType_t  MenuRequestType \n
++           Indicates if the menu request is to activate or deactivate the 
++           devices menu or simply query the devices menu status. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecMenuRequest
++(
++   tmInstance_t                  Instance,
++   UInt8                         ReceiverLogicalAddress,
++   tmdlHdmiCECMenuRequestType_t  MenuRequestType
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to indicate to the TV that the device is 
++           showing/has removed a menu and requets the remote control keys to
++           be passed though
++    
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECMenuState_t  MenuState \n
++           Indicates if the device is in the 'Device Menu Active' state or
++           'Device Menu Inactive' state. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecMenuStatus
++(
++   tmInstance_t            Instance,
++   UInt8                   ReceiverLogicalAddress,
++   tmdlHdmiCECMenuState_t  MenuState
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to control the playback behaviour of a source
++           device
++    
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECPlayMode_t  PlayMode \n
++           In which mode to play media. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecPlay
++(
++   tmInstance_t           Instance,
++   UInt8                  ReceiverLogicalAddress,
++   tmdlHdmiCECPlayMode_t  PlayMode
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by any device for device discovery - similar to
++           ping in other protocols
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecPollingMessage
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message request a device to stop a recording
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOff
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message attempt to record analogue source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n 
++           
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++    
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n       
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnAnalogueService
++(
++   tmInstance_t                        Instance,
++   UInt8                               ReceiverLogicalAddress,
++   tmdlHdmiCECAnalogueBroadcastType_t  AnalogueBroadcastType,
++   UInt16                              AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t        BroadcastSystem
++);
++
++//==========================================================================
++/*!
++    \brief This message attempt to record digital source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnDigitalService
++(
++   tmInstance_t                              Instance,
++   UInt8                                     ReceiverLogicalAddress,
++   tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification
++);
++
++//==========================================================================
++/*!
++    \brief This message attempt to record an external physical address source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress \n
++           Defines the path between the TV an a device-thus giving it a physical
++           address within the cluster.\n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnExternalPhysicalAddress
++(
++   tmInstance_t                         Instance,
++   UInt8                                ReceiverLogicalAddress,
++   tmdlHdmiCECExternalPhysicalAddress_t ExternalPhysicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message attempt to record an external plug source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECExternalPlug_t  ExternalPlug \n
++           indicates external plug number (1 to 255 )on the recording device.\n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnExternalPlug
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress,
++   tmdlHdmiCECExternalPlug_t      ExternalPlug
++);
++
++//==========================================================================
++/*!
++    \brief This message attempt to record an external plug source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnOwnSource
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by a recording device to inform the initiator
++           of the message <Record On> about its status.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECRecordStatusInfo_t  RecordStatusInfo \n
++           The recording status of the device.\n        
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordStatus
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress,
++   tmdlHdmiCECRecordStatusInfo_t  RecordStatusInfo
++);
++
++//==========================================================================
++/*!
++    \brief This message request by the recording device to record the presently
++           displayed source.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordTvScreen
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message report an amplifier's volume and mute.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECAudioStatus_t AudioStatus \n
++           Volume and mute status. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportAudioStatus
++(
++   tmInstance_t              Instance,
++   UInt8                     ReceiverLogicalAddress,
++   ptmdlHdmiCECAudioStatus_t pAudioStatus
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecReportShortAudioDescriptor( )
++    \brief This message Report Audio Capability.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt32 ShortAudioDecriptor \n
++           Audio Descriptor. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportShortAudioDescriptor
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress,
++   UInt32         ShortAudioDecriptor
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRequestShortAudioDescriptor( )
++    \brief This message Request Audio Capability.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt8 AudioFormatID \n
++	   
++    \param UInt8 AudioFormatCode \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRequestShortAudioDescriptor
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress,
++   UInt8          AudioFormatID,
++   UInt8          AudioFormatCode
++   
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecIniateARC( )
++    \brief This message Used by an ARC RX device to activate the
++           ARC functionality in an ARC TX device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecIniateARC
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecReportArcInitiated( )
++    \brief This message Used by an ARC TX device to indicate that
++           its ARC functionality has been activated
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportArcInitiated
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecReportArcTerminated( )
++    \brief This message Used by an ARC TX device to indicate that its ARC functionality
++           has been deactivated.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportArcTerminated
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRequestArcInitiation( )
++    \brief This message Used by an ARC TX device to request an ARC RX device to
++           activate the ARC functionality in the ARC TX device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRequestArcInitiation
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRequestArcTerminiation( )
++    \brief Used by an ARC TX device to request an ARC RX device to deactivate 
++           the ARC functionality in the ARC TX device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRequestArcTerminiation
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecTerminateARC( )
++    \brief Used by an ARC TX device to request an ARC RX device to deactivate 
++           the ARC functionality in the ARC TX device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTerminateARC
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to inform all other devices of the mapping
++           between physical and logical address of the initiator.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt16 PhysicalAddress \n
++           Device physical address within the cluster. \n
++           
++    \param tmdlHdmiCECDeviceType_t DeviceType \n
++           Type of the device (TV, Playback, tuner,...). \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportPhysicalAddress
++(
++   tmInstance_t             Instance,
++   UInt16                   PhysicalAddress,
++   tmdlHdmiCECDeviceType_t  DeviceType
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to inform a requesting device of the current
++           power status.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECPowerStatus_t PowerStatus \n
++           Current power status. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportPowerStatus
++(
++   tmInstance_t             Instance,
++   UInt8                    ReceiverLogicalAddress,
++   tmdlHdmiCECPowerStatus_t PowerStatus
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by a new device to discover the status of
++           the system.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRequestActiveSource
++(
++   tmInstance_t  Instance
++);
++
++//==========================================================================
++/*!
++    \brief This message is sent by a CEC switch when it is manually switched to 
++           inform all other devices on the network that the active route below
++           the switch has changed.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt16 OriginalAddress \n
++           Previous address that the switch was switched to. \n
++           
++    \param UInt16 NewAddress \n
++           The new address it has been moved to. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRoutingChange
++(
++   tmInstance_t  Instance,
++   UInt16        OriginalAddress,
++   UInt16        NewAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is sent by a CEC switch to indicate the active route
++           below the switch.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt16 PhysicalAddress \n
++           The current active route to the sink in the CEC switch. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRoutingInformation
++(
++   tmInstance_t  Instance,
++   UInt16        PhysicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message select directly an analogue TV Service.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n 
++           
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++    
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSelectAnalogueService
++(
++   tmInstance_t                       Instance,
++   UInt8                              ReceiverLogicalAddress,
++   tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType,
++   UInt16                             AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t       BroadcastSystem
++);
++
++//==========================================================================
++/*!
++    \brief This message select directly a digital TV, Radio or Data Broadcast
++           Service.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSelectDigitalService
++(
++   tmInstance_t                                Instance,
++   UInt8                                       ReceiverLogicalAddress,
++   ptmdlHdmiCECDigitalServiceIdentification_t  pServiceIdentification
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to set asingle timer block on an analogue 
++           recording device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++           
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++    
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++           
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++           
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++    
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++    
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n 
++           
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++    
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetAnalogueTimer
++(
++   tmInstance_t                        Instance,
++   UInt8                               ReceiverLogicalAddress,
++   UInt8                               DayOfMonth,
++   UInt8                               MonthOfYear,
++   UInt16                              StartTime,
++   tmdlHdmiCECDuration_t              *pDuration,
++   UInt8                               RecordingSequence,
++   tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType,
++   UInt16                              AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t       BroadcastSystem
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to control audio rate from Source device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param tmdlHdmiCECAudioRate_t AudioRate \n
++           The audio rate requested. \n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetAudioRate
++(
++   tmInstance_t           Instance,
++   UInt8                  ReceiverLogicalAddress,
++   tmdlHdmiCECAudioRate_t AudioRate
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to set a digital timer block on a digital
++           recording device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++           
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++    
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++           
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++           
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++    
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++    
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetDigitalTimer
++(
++   tmInstance_t                               Instance,
++    UInt8                                     ReceiverLogicalAddress,
++   UInt8                                      DayOfMonth,
++   UInt8                                      MonthOfYear,
++   UInt16                                     StartTime,
++   tmdlHdmiCECDuration_t                     *pDuration,
++   UInt8                                      RecordingSequence,
++   tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to set a single timer block to record from an
++           external device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++    
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++           
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++           
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++    
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++    
++    \param tmdlHdmiCECExternalPlug_t  ExternalPlug \n
++           indicates external plug number (1 to 255 )on the recording device.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetExternalTimerWithExternalPlug
++(
++   tmInstance_t                Instance,
++   UInt8                       ReceiverLogicalAddress,
++   UInt8                       DayOfMonth,
++   UInt8                       MonthOfYear,
++   UInt16                      StartTime,
++   tmdlHdmiCECDuration_t      *pDuration,
++   UInt8                       RecordingSequence,
++   tmdlHdmiCECExternalPlug_t  ExternalPlug
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to set a single timer block to record from an
++           external device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++    
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++           
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++           
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++    
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++    
++    \param tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress \n
++           Defines the path between the TV an a device-thus giving it a physical
++           address within the cluster.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetExternalTimerWithPhysicalAddress
++(
++   tmInstance_t                           Instance,
++   UInt8                                  ReceiverLogicalAddress,
++   UInt8                                  DayOfMonth,
++   UInt8                                  MonthOfYear,
++   UInt16                                 StartTime,
++   tmdlHdmiCECDuration_t                 *pDuration,
++   UInt8                                  RecordingSequence,
++   tmdlHdmiCECExternalPhysicalAddress_t  ExternalPhysicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by a TV or another device to indicate the menu
++           Language.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param const char *pLanguage \n
++           Pointer on the user's menu language choice. \n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetMenuLanguage
++(
++   tmInstance_t Instance,
++   const char   *pLanguage
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to set the preferred OSD name of a device 
++           for use in manus associated with that device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param const char *pOsdName \n
++           Pointer on the preferred name of the device. \n
++           
++    \param UInt8    OsdNameLength \n
++           Length of Osd Name String. \n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetOsdName
++(
++   tmInstance_t Instance,
++   UInt8        ReceiverLogicalAddress,
++   const char   *pOsdName,
++   UInt8        OsdNameLength
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to send a test message to output on a TV.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECDisplayControl_t DisplayControl \n
++           Display timing. \n
++    
++    \param const char *pOsdString \n
++           Pointer on the Text to display. \n
++     
++    \param UInt8    OsdStringLength \n
++           Length of Osd String. \n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetOsdString
++(
++   tmInstance_t                 Instance,
++   UInt8                        ReceiverLogicalAddress,
++   tmdlHdmiCECDisplayControl_t  DisplayControl,
++   const char                   *pOsdString,
++   UInt8                        OsdStringLength
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by a TV to request a streaming path from
++           the specified physical address.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt16 PhysicalAddress \n
++           Physical address of the device.\n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetStreamPath
++(
++   tmInstance_t  Instance,
++   UInt16        PhysicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message turn the system audio Mode ON or OFF.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECSystemAudioStatus_t SystemAudioStatus \n
++           Specifies if the system audio mode is ON or OFF.\n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetSystemAudioMode
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress,
++   tmdlHdmiCECSystemAudioStatus_t SystemAudioStatus
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to set the name of a program associated
++           with a timer block.Sent directly after sending a 
++           <Set analogue Timer> or <Set Digital Timer> message. The name
++           is then associated with that timer block.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++    
++    \param const char *pProgramTitleString \n
++           Pointer on the program title. \n
++           
++    \param UInt8    ProgramTitleLength \n
++           Length of Program Title String. \n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetTimerProgramTitle
++(
++   tmInstance_t Instance,
++   UInt8        ReceiverLogicalAddress,
++   const char   *pProgramTitleString,
++   UInt8        ProgramTitleLength
++);
++
++//==========================================================================
++/*!
++    \brief This message switches one or all devices into standby mode.Can be
++           be used as a broadcast message o be addressed to a specific device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecStandby
++(
++   tmInstance_t Instance,
++   UInt8        ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief A device implementing System Audio Control and which has volume
++           control RC button(eg TV or STB) request to use System Audio Mode
++           to the amplifier.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt16 PhysicalAddress \n
++           Physical address of the device.\n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSystemAudioModeRequest
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress,
++   UInt16        PhysicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief Reports the current status of the System Audio Mode.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECSystemAudioStatus_t SystemAudioStatus \n
++           Current system audio mode.\n
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSystemAudioModeStatus
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress,
++   tmdlHdmiCECSystemAudioStatus_t SystemAudioStatus
++);
++
++//==========================================================================
++/*!
++    \brief This message as <Image View On>, but should also remove any text,
++           menus and PIP windows from the TV's display
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTextViewOn
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to give the status of a <Cleared Analogue Timer>,
++           <Clear Digital Timer> or <Clear External Timer> message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECTimerClearedStatusData_t TimerClearedStatusData \n
++           Indicates if the timer was cleared successfully. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTimerClearedStatus
++(
++   tmInstance_t                        Instance,
++   UInt8                               ReceiverLogicalAddress,
++   tmdlHdmiCECTimerClearedStatusData_t TimerClearedStatusData
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to send timer status to the initiator of a
++           <Set Timer> message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECTimerStatusData_t *pTimerStatusData \n
++           Pointer on the Timer status. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTimerStatus
++(
++   tmInstance_t                 Instance,
++   UInt8                        ReceiverLogicalAddress,
++   tmdlHdmiCECTimerStatusData_t *pTimerStatusData
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by a tuner device to provide its status to the
++           initiator of the <Give Tuner Device Status> message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param tmdlHdmiCECRecordingFlag_t RecordingFlag \n
++           Indicates if the tuner is being used as a source of a recording. \n
++           
++    \param tmdlHdmiCECTunerDisplayInfo_t TunerDisplayInfo \n
++           Indicates if the the device is currently deplaying its tuner or not. \n
++           
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n 
++           
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++    
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTunerDeviceStatusAnalogue
++(
++   tmInstance_t                       Instance,
++   UInt8                              ReceiverLogicalAddress,
++   tmdlHdmiCECRecordingFlag_t         RecordingFlag,
++   tmdlHdmiCECTunerDisplayInfo_t      TunerDisplayInfo,
++   tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType,
++   UInt16                             AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t       BroadcastSystem
++);
++
++//==========================================================================
++/*!
++    \brief This message is used by a tuner device to provide its status to the
++           initiator of the <Give Tuner Device Status> message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param tmdlHdmiCECRecordingFlag_t RecordingFlag \n
++           Indicates if the tuner is being used as a source of a recording. \n
++           
++    \param tmdlHdmiCECTunerDisplayInfo_t TunerDisplayInfo \n
++           Indicates if the the device is currently deplaying its tuner or not. \n
++           
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTunerDeviceStatusDigital
++(
++   tmInstance_t                               Instance,
++   UInt8                                      ReceiverLogicalAddress,
++   tmdlHdmiCECRecordingFlag_t                 RecordingFlag,
++   tmdlHdmiCECTunerDisplayInfo_t              TunerDisplayInfo,
++   ptmdlHdmiCECDigitalServiceIdentification_t pServiceIdentification
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to tune to next lowest service in a tuner's
++           service list.Can be used for PIP.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTunerStepDecrement
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to tune to next highest service in a tuner's
++           service list.Can be used for PIP.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTunerStepIncrement
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECUserRemoteControlCommand_t UICommand \n
++           Relevant UI command issued by user. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressed
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   tmdlHdmiCECUserRemoteControlCommand_t UICommand
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECPlayMode_t PlayMode \n
++           In which mode to play media. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedPlay
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   tmdlHdmiCECPlayMode_t                 PlayMode
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8 SelectAudioInput \n
++           Number of the Audio Input (Audio input number between 1 and 255). \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedSelectAudioInput
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   UInt8                                 SelectAudioInput
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8 SelectAVInput \n
++           Number of the A/V Input (A/V input number between 1 and 255). \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedSelectAVInput
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   UInt8                                 SelectAVInput
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8 SelectMedia \n
++           Number of Media (Media number between 1 and 255). \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedSelectMedia
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   UInt8                                 SelectMedia
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param tmdlHdmiCECChannelIdentifier_t  *pChannelIdentifier \n
++           Pointer to the structure of Major and Minor Channel number
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedTune
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   tmdlHdmiCECChannelIdentifier_t        *pChannelIdentifier
++);
++
++//==========================================================================
++/*!
++    \brief This message is used to indicate that the user released a remote button
++           The last one indicated by the <User Control Pressed> Message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlReleased
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief This message is allows vendor specific commands to be sent between 
++           two devices.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++    
++    \param UInt8  *pVendorSpecificData \n
++           Pointer to the Vendor Specific datas
++           
++    \param UInt8    VendorSpecificDataLength \n
++           Length of VendorSpecificData. \n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVendorCommand
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress,
++   UInt8         *pVendorSpecificData,
++   UInt8         VendorSpecificDataLength
++);
++
++//==========================================================================
++/*!
++    \brief This message is allows vendor specific commands to be sent between 
++           two devices or broadcast.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt32 VendorID \n
++           Indentifier for a specific Vendor \n
++    
++    \param UInt8  *pVendorSpecificData \n
++           Pointer to the Vendor Specific datas
++           
++    \param UInt8    VendorSpecificDataLength \n
++           Length of VendorSpecificData. \n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVendorCommandWithID
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress,
++   UInt32        VendorID,
++   UInt8         *pVendorSpecificData,
++   UInt8         VendorSpecificDataLength
++);
++
++//==========================================================================
++/*!
++    \brief This message indicates that a remote control button has been depressed.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \param UInt8  *pVendorSpecificRcCode \n
++           Pointer to the Vendor Specific remote control code.
++           its recommended t keep this to a minimum size.
++           The maximum length shall not exceed 14 data blocks to avoid saturating bus
++           
++    \param UInt8    VendorSpecificRcCodeLength \n
++           Length of VendorSpecificRcCode. \n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVendorRemoteButtonDown
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress,
++   UInt8         *pVendorSpecificRcCode,
++   UInt8         VendorSpecificRcCodeLength
++);
++
++//==========================================================================
++/*!
++    \brief This message indicates that a remote control button (the last button
++           pressed indicated by the <Vendor remote button down > message) has 
++           been released.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++           
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVendorRemoteButtonUp
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress
++);
++
++//==========================================================================
++/*!
++    \brief Get the software version of the driver.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param pSWVersion Pointer to the version structure
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetSWVersion
++(
++    tmSWVersion_t  *pSWVersion
++);
++
++//==========================================================================
++/*!
++    \brief Get the number of available CEC devices in the system.
++           A unit directly represents a physical device.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param pUnitCount Pointer to the number of available units.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetNumberOfUnits
++(
++    UInt32  *pUnitCount
++);
++
++//==========================================================================
++/*!
++    \brief Get the capabilities of unit 0. Capabilities are stored into a
++           dedicated structure.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param pCapabilities Pointer to the capabilities structure.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetCapabilities
++(
++    tmdlHdmiCecCapabilities_t *pCapabilities
++);
++
++//==========================================================================
++/*!
++    \brief Get the capabilities of a specific unit. Capabilities are stored
++           into a dedicated structure 
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param unit          Unit to be probed.
++    \param pCapabilities Pointer to the capabilities structure.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetCapabilitiesM
++(
++    tmUnitSelect_t            unit,
++    tmdlHdmiCecCapabilities_t *pCapabilities
++);
++
++//==========================================================================
++/*!
++    \brief Open unit 0 of CEC driver and provides the instance number to
++           the caller. Note that one unit of CEC represents one physical
++           CEC device and that only one instance per unit can be opened.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param pInstance Pointer to the variable that will receive the instance
++                     identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_OWNED: the resource is already in use
++            - TMDL_ERR_DLHDMICEC_INIT_FAILED: the unit instance is already
++              initialised or something wrong happened at lower level.
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_NO_RESOURCES: the resource is not available
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecOpen
++(
++    tmInstance_t   *pInstance
++);
++
++//==========================================================================
++/*!
++    \brief Open a specific unit of CEC driver and provides the instance
++           number to the caller. Note that one unit of CEC represents one
++           physical CEC device and that only one instance per unit can be
++           opened.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param pInstance Pointer to the structure that will receive the instance
++                     identifier.
++    \param unit      Unit number to be opened.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_OWNED: the resource is already in use
++            - TMDL_ERR_DLHDMICEC_INIT_FAILED: the unit instance is already
++              initialised or something wrong happened at lower level.
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_NO_RESOURCES: the resource is not available
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecOpenM
++(
++    tmInstance_t   *pInstance,
++    tmUnitSelect_t  unit
++);
++
++//==========================================================================
++/*!
++    \brief Close an instance of CEC driver.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClose
++(
++    tmInstance_t   instance
++);
++
++//==========================================================================
++/*!
++    \brief Set the power state of an instance of the CEC device. ON
++           state corresponds to a fully supplied, up and running device. Other
++           modes correspond to the powerdown state of the device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++
++    \param instance   Instance identifier.
++    \param powerState Power state to set.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetPowerState
++(
++    tmInstance_t   instance,
++    tmPowerState_t powerState
++);
++
++//==========================================================================
++/*!
++    \brief Get the power state of an instance of the CEC device. ON
++           state corresponds to a fully supplied, up and running device. Other
++           modes correspond to the powerdown state of the device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance    Instance identifier.
++    \param pPowerState Pointer to the power state.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetPowerState
++(
++    tmInstance_t    instance,
++    tmPowerState_t *pPowerState
++);
++
++//==========================================================================
++/*!
++    \brief Set the configuration of instance attributes. This function is
++           required by DVP architecture rules but actually does nothing in this
++           driver
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance    Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecInstanceConfig
++(
++    tmInstance_t    instance
++);
++
++//==========================================================================
++/*!
++    \brief Setup the instance with its configuration parameters. This function
++           allows basic instance configuration like Logical Address or device
++           state.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure containing all setup parameters
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecInstanceSetup
++(
++    tmInstance_t                instance,
++    ptmdlHdmiCecInstanceSetup_t pSetupInfo
++);
++
++//==========================================================================
++/*!
++    \brief Get instance setup parameters.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure that will receive setup
++                      parameters
++                      This function is synchronous.
++                      This function is not ISR friendly.
++
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetInstanceSetup
++(
++    tmInstance_t                instance,
++    ptmdlHdmiCecInstanceSetup_t pSetupInfo
++);
++
++//==========================================================================
++/*!
++    \brief Make device library handle an incoming interrupt. This function is
++           used by application to tell the device library that the hardware
++           sent an interrupt. It can also be used to poll the interrupt status
++           of the device if the interrupt line is not physically connected to
++           the CPU.
++           This function is synchronous.
++           This function is ISR friendly.
++
++
++    \param instance   Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_FULL: the queue is full
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecHandleInterrupt
++(
++    tmInstance_t    instance
++);
++
++//==========================================================================
++/*!
++    \brief Register event callbacks. Only one callback is registered through
++           this API. This callback will received the type of event that
++           occured throug a dedicated parameter and will be called as many
++           times as there is pending events.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance   Instance identifier.
++    \param pCallback  Pointer to the callback function that will handle events
++                      from the devlib.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_INVALID_STATE: the state is invalid for
++              the function
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRegisterCallbacks
++(
++    tmInstance_t                instance,
++    ptmdlHdmiCecCallbackFunc_t  pkCallback
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetLogicalAddress( )
++    \brief Set Device Logical Address
++
++    \param instance Instance identifier.
++    \param LogicalAddress Logical Address value.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetLogicalAddress
++(
++    tmInstance_t   instance,
++	tmdlHdmiCECLogicalAddress_t   LogicalAddress
++);
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetRetry( )
++    \brief Change the number of retransmission
++
++    \param instance Instance identifier.
++    \param NbRetry Number of retry.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetRetry
++(
++    tmInstance_t   instance,
++	UInt8   NbRetry
++);
++
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t getCecLastMessage( )
++    \brief Return the Addresses and the Opcode of the last CEC
++	       transmitted message
++
++    \param pSaveMessage   Pointer to the CEC Save Message
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t getCecLastMessage
++(
++    tmdlHdmiCecSaveMessage_t  *pSaveMessage
++);
++
++
++//==========================================================================
++/*!
++    \brief This function allows enabling a specific event of devlib.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance Instance identifier.
++    \param event    Event to enable
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecEnableEvent
++(
++    tmInstance_t      instance,
++    tmdlHdmiCecEvent_t event
++);
++
++//==========================================================================
++/*!
++    \brief This function allows disabling a specific event of devlib.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance Instance identifier.
++    \param event    Event to disable
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecDisableEvent
++(
++    tmInstance_t      instance,
++    tmdlHdmiCecEvent_t event
++);
++
++
++//==========================================================================
++/*!
++    \brief This function enables calibration depending on CEC clock source
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance          Instance identifier.
++    \param cecClockSource    CEC clock source
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecEnableCalibration
++(
++   tmInstance_t instance,
++   tmdlHdmiCecClockSource_t cecClockSource
++);
++
++
++//==========================================================================
++/*!
++    \brief This function disable calibration depending on CEC clock source
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance          Instance identifier.
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecDisableCalibration(
++   tmInstance_t instance
++);
++
++//==========================================================================
++/*!
++    \brief This function allow to send a generic CEC message
++           This function has to be used when CEC messages are construct in 
++	   the middleware
++
++    \param instance  Instance identifier.
++    
++    \param *pData    Pointer to the CEC data buffer 
++    
++    \param lenData   Lenght of I2C data buffer
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSendMessage(
++
++   tmInstance_t instance,
++   UInt8        *pData,
++   UInt16       lenData
++);
++
++unsigned char tmdlHdmiCecGetRegister(tmInstance_t   instance, UInt32 offset);
++tmErrorCode_t tmdlHdmiCecSetRegister(tmInstance_t  instance,UInt32 offset,UInt32 value);
++
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMICEC_FUNCTIONS_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Types.h b/drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Types.h
+new file mode 100755
+index 0000000..d0bd632
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiCEC/inc/tmdlHdmiCEC_Types.h
+@@ -0,0 +1,1083 @@
++//=============================================================================
++// Copyright (C) 2007 NXP N.V., All Rights Reserved.
++// This source code and any compilation or derivative thereof is the proprietary
++// information of NXP N.V. and is confidential in nature. Under no circumstances
++// is this software to be  exposed to or placed under an Open Source License of
++// any type without the expressed written permission of NXP N.V.
++//=============================================================================
++/*!
++    \file    tmdlHdmiCEC_Types.h
++
++	\version 1.0
++
++	\date    04/07/2007
++
++ 	\brief   This provides interfaces description of CEC messages.
++
++    \section refs  Reference Documents
++             TDA998X Driver - tmdlHdmiTx - SCS.doc
++    \note    None.
++ 
++    HISTORY :
++    \verbatim
++     Date          Modified by CRPRNr  TASKNr  Maintenance description
++     -------------|-----------|-------|-------|-----------------------------------
++     04/07/2007   |  F.G      |       |       | Creation.
++     -------------|-----------|-------|-------|-----------------------------------
++    \endverbatim
++*/
++//==========================================================================
++
++#ifndef TMDLHDMICEC_TYPES_H
++#define TMDLHDMICEC_TYPES_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#include "tmNxTypes.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       MACRO DEFINITIONS                                    */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                                DEFINES                                     */
++/*============================================================================*/
++
++/**< Error Codes */
++#define TMDL_ERR_DLHDMICEC_BASE                      CID_DL_HDMICEC
++#define TMDL_ERR_DLHDMICEC_COMPATIBILITY             (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_COMPATIBILITY)             /**< SW Interface compatibility   */
++#define TMDL_ERR_DLHDMICEC_MAJOR_VERSION             (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_MAJOR_VERSION)             /**< SW Major Version error       */
++#define TMDL_ERR_DLHDMICEC_COMP_VERSION              (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_COMP_VERSION)              /**< SW component version error   */
++#define TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER           (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_BAD_UNIT_NUMBER)           /**< Invalid device unit number   */
++#define TMDL_ERR_DLHDMICEC_BAD_INSTANCE              (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_BAD_INSTANCE)              /**< Bad input instance value     */
++#define TMDL_ERR_DLHDMICEC_BAD_HANDLE                (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_BAD_HANDLE)                /**< Bad input handle             */
++#define TMDL_ERR_DLHDMICEC_BAD_PARAMETER             (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_BAD_PARAMETER)             /**< Invalid input parameter      */
++#define TMDL_ERR_DLHDMICEC_NO_RESOURCES              (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_NO_RESOURCES)              /**< Resource is not available    */
++#define TMDL_ERR_DLHDMICEC_RESOURCE_OWNED            (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_RESOURCE_OWNED)            /**< Resource is already in use   */
++#define TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED        (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_RESOURCE_NOT_OWNED)        /**< Caller does not own resource */
++#define TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS       (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_INCONSISTENT_PARAMS)       /**< Inconsistent input params    */
++#define TMDL_ERR_DLHDMICEC_NOT_INITIALIZED           (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_NOT_INITIALIZED)           /**< Component is not initialized */
++#define TMDL_ERR_DLHDMICEC_NOT_SUPPORTED             (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_NOT_SUPPORTED)             /**< Function is not supported    */
++#define TMDL_ERR_DLHDMICEC_INIT_FAILED               (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_INIT_FAILED)               /**< Initialization failed        */
++#define TMDL_ERR_DLHDMICEC_BUSY                      (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_BUSY)                      /**< Component is busy            */
++#define TMDL_ERR_DLHDMICEC_I2C_READ                  (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_READ)                      /**< Read error                   */
++#define TMDL_ERR_DLHDMICEC_I2C_WRITE                 (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_WRITE)                     /**< Write error                  */
++#define TMDL_ERR_DLHDMICEC_FULL                      (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_FULL)                      /**< Queue is full                */
++#define TMDL_ERR_DLHDMICEC_NOT_STARTED               (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_NOT_STARTED)               /**< Function is not started      */
++#define TMDL_ERR_DLHDMICEC_ALREADY_STARTED           (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_ALREADY_STARTED)           /**< Function is already started  */
++#define TMDL_ERR_DLHDMICEC_ASSERTION                 (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_ASSERTION)                 /**< Assertion failure            */
++#define TMDL_ERR_DLHDMICEC_INVALID_STATE             (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_INVALID_STATE)             /**< Invalid state for function   */
++#define TMDL_ERR_DLHDMICEC_OPERATION_NOT_PERMITTED   (TMDL_ERR_DLHDMICEC_BASE + TM_ERR_OPERATION_NOT_PERMITTED)   /**< corresponds to posix EPERM   */
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++/*!
++	\enum  tmdlHdmiCECAbortReason_t
++    \brief This enum indicates the reason for a <Feature Abort> response
++*/
++typedef enum
++{
++   CEC_ABORT_UNKNOWN_OPCODE      = 0, /*!< Unrecognized opcode */
++   CEC_ABORT_INCORRECT_MODE      = 1, /*!< Not in correct mode to respond */
++   CEC_ABORT_NO_SOURCE           = 2, /*!< cannot provide source */
++   CEC_ABORT_INVALID_OPERAND     = 3, /*!< Invalid operand  */
++   CEC_ABORT_REFUSED             = 4, /*!< Refused */
++   CEC_ABORT_UNABLE_TO_DETERMINE = 5  /*!< Unable to Determine */
++} tmdlHdmiCECAbortReason_t;
++
++/*!
++	\enum  tmdlHdmiCECAnalogueBroadcastType_t
++    \brief This enum indicates the analogue broadcast type
++*/
++typedef enum
++{
++   CEC_BROADCAST_TYPE_CABLE       = 0x00, /*!< Cable */
++   CEC_BROADCAST_TYPE_SATELLITE   = 0x01, /*!< Satellite*/
++   CEC_BROADCAST_TYPE_TERRESTRIAL = 0x02 /*!< Terrestrial */
++} tmdlHdmiCECAnalogueBroadcastType_t;
++
++/*!
++	\enum  _tmdlHdmiCECAnalogueFrequency
++    \brief This enum specify the min and max frequency used by an analogue tuner
++*/
++enum _tmdlHdmiCECAnalogueFrequency
++{
++    CEC_ANALOG_FREQ_MIN = 0x0000, /*!< Min frequency used by analogue tuner */
++    CEC_ANALOG_FREQ_MAX = 0xFFFF  /*!< Max frequency used by analogue tuner */
++};
++
++/*!
++	\enum  _tmdlHdmiCECAsciiDigit
++    \brief This enum represent the min and max of a printable digit character
++*/
++enum _tmdlHdmiCECAsciiDigit
++{
++    CEC_ASCII_DIGIT_MIN = 0x30, /*!< Min of a printable digit character */
++    CEC_ASCII_DIGIT_MAX = 0x39  /*!< Max of a printable digit character */
++};
++
++/*!
++	\enum  _tmdlHdmiCECAscii
++    \brief This enum represent the min and max of a printable character
++*/
++enum _tmbsHdmiCECAscii
++{
++    CEC_ASCII_CHARACTER_MIN  = 0x20, /*!< Min of a printable character */
++    CEC_ASCII_CHARACTER_MAX  = 0x7E  /*!< Max of a printable character */
++};
++
++/*!
++    \enum  _tmdlHdmiCECAudioFormatCode
++    \brief This enum represent the min and max of a Audio Format Code is defined
++           in CEA-861-D for CEA Short Audio Descriptor
++*/
++enum _tmdlHdmiCECAudioFormatCode
++{
++    CEC_AUDIO_FORMAT_CODE_MIN = 0x01, /*!< Min of a Audio Format Code */
++    CEC_AUDIO_FORMAT_CODE_MAX = 0x0F  /*!< Max of a Audio Format Code */
++};
++
++/*!
++	\enum  tmdlHdmiCECAudioRate_t
++    \brief This enum indicates the audio range control
++*/
++typedef enum
++{
++   CEC_AUDIO_RATE_OFF                        = 0, /*!< Rate Control off */
++   CEC_AUDIO_RATE_WIDE_RANGE_STANDARD_RATE   = 1, /*!< Standard rate : 100% rate */
++   CEC_AUDIO_RATE_WIDE_RANGE_FAST_RATE       = 2, /*!< Fast rate : Max 101% rate */
++   CEC_AUDIO_RATE_WIDE_RANGE_SLOW_RATE       = 3, /*!< Sloaw rate : 99% rate */
++   CEC_AUDIO_RATE_NARROW_RANGE_STANDARD_RATE = 4, /*!< Standard rate : 100% rate */
++   CEC_AUDIO_RATE_NARROW_RANGE_FAST_RATE     = 5, /*!< Fast rate : Max 101% rate */
++   CEC_AUDIO_RATE_NARROW_RANGE_SLOW_RATE     = 6  /*!< Sloaw rate : 99% rate */                                          
++} tmdlHdmiCECAudioRate_t;
++
++/*!
++	\enum  tmdlHdmiCECAudioMute_t
++    \brief This enum indicates the audio current audio mute status
++*/
++typedef enum
++{
++   CEC_AUDIO_MUTE_OFF  = 0, /*!< Audio Mute off */
++   CEC_AUDIO_MUTE_ON   = 1 /*!< Audio Mute on */
++} tmdlHdmiCECAudioMute_t;
++
++
++/*!
++	\struct tmdlHdmiCECAudioStatus_t
++    \brief  This union indicates the current audio status of a device
++*/
++typedef struct _tmdlHdmiCECAudioStatus_t
++{
++     tmdlHdmiCECAudioMute_t audioMuteStatus   ; /*!< Audio Mute Status */
++     UInt8                  audioVolumeStatus ; /*!< Audio Volume Status  */
++} tmdlHdmiCECAudioStatus_t, *ptmdlHdmiCECAudioStatus_t;
++
++
++/*!
++	\enum  tmdlHdmiCECBoolean_t
++    \brief This enum indicates a Flag
++*/
++typedef enum
++{
++   CEC_FALSE  = 0, /*!< False */
++   CEC_TRUE   = 1, /*!< True */
++} tmdlHdmiCECBoolean_t;
++
++
++/*!
++	\enum  tmdlHdmiCECBroadcastSystem_t
++    \brief This enum indicates information about the color system, the sound carrier and IF-frequency
++*/
++typedef enum
++{                                         /*!< Sound  / Sound Modulation / Video Modulation / Vertical Frequency / Color sub-carier         */
++   CEC_BROADCAST_SYSTEM_PAL_BG       = 0, /*!< 5.5MHZ / FM                 NEG                50HZ                 4.43 MHZ                 */
++   CEC_BROADCAST_SYSTEM_PAL_SECAM_L  = 1, /*!< 6.5MHZ / AM                 POS                50HZ                 Fob 4.25MHz,For 4.406Mhz */
++   CEC_BROADCAST_SYSTEM_PAL_M        = 2, /*!< 4.5MHZ / FM                 NEG                60HZ                 3.5756 MHZ               */
++   CEC_BROADCAST_SYSTEM_NTSC_M       = 3, /*!< 4.5MHZ / FM                 NEG                60HZ                 3.5795 MHZ               */
++   CEC_BROADCAST_SYSTEM_PAL_I        = 4, /*!< 6.0MHZ / FM                 NEG                50HZ                 4.43 MHZ                 */
++   CEC_BROADCAST_SYSTEM_SECAM_DK     = 5, /*!< 6.5MHZ / FM                 NEG                50HZ                 Fob 4.25MHz,For 4.406Mhz */
++   CEC_BROADCAST_SYSTEM_SECAM_BG     = 6, /*!< 5.5MHZ / FM                 NEG                50HZ                 Fob 4.25MHz,For 4.406Mhz */
++   CEC_BROADCAST_SYSTEM_SECAM_L      = 7, /*!< 6.5MHZ / AM                 POS                50HZ                 Fob 4.25MHz,For 4.406Mhz */
++   CEC_BROADCAST_SYSTEM_PAL_DK       = 8, /*!< 5.5MHZ / FM                 NEG                50HZ                 4.43MHZ                  */
++   CEC_BROADCAST_SYSTEM_FUTURE_USE   = 9, /*!< Future Use   */
++   CEC_BROADCAST_SYSTEM_OTHER_SYSTEM = 31 /*!< Other System */
++} tmdlHdmiCECBroadcastSystem_t;
++
++/*!
++	\enum  tmdlHdmiCECVersion_t
++    \brief This enum indicates the supported CEC version
++*/
++typedef enum
++{
++   CEC_VERSION_Reserved = 0x00, /*!< CEC Reserved */
++   CEC_VERSION_Reserved1 = 0x01, /*!< CEC Reserved */
++   CEC_VERSION_Reserved2 = 0x02, /*!< CEC Reserved */
++   CEC_VERSION_Reserved3 = 0x03, /*!< CEC Reserved */
++   CEC_VERSION_1_3a     = 0x04, /*!< CEC Version 1.3a */
++   CEC_VERSION_1_4      = 0x05  /*!< CEC Version 1.4  */
++} tmdlHdmiCECVersion_t;
++
++/*!
++	\enum  tmdlHdmiCECChanNumFormat_t
++    \brief This enum indicates the Channel Format
++*/
++typedef enum
++{
++   CEC_FIRST_CHAN_NUMBER  = 0x01, /*!< 1-part channel number */
++   CEC_SECOND_CHAN_NUMBER = 0x02  /*!< 2-part channel number */
++} tmdlHdmiCECChanNumFormat_t;
++
++/*!
++	\struct tmdlHdmiCECChannelIdentifier_t
++    \brief  This struct indicates a 1-part Logical or Virtual Channel Number or
++            a 2-part Major and Minor channel combination
++*/
++typedef struct
++{
++     tmdlHdmiCECChanNumFormat_t ChanNumFormat   ; /*!< Channel Format */
++     UInt16                      MajorChanNumber ; /*!< Major Channel Number (if channel is 2-part) */
++     UInt16                      MinorChanNumber ; /*!< 1-part Channel Number ,or a Minor Channel Number (if channel is 2-part) */
++} tmdlHdmiCECChannelIdentifier_t ;
++
++/*!
++	\enum  tmdlHdmiCECDayOfMonth_t
++    \brief This enum indicates the day of the month
++*/
++typedef enum
++{
++   CEC_FIRST_DAY_OF_MONTH  = 1, /*!< First day of the month */
++   CEC_LAST_DAY_OF_MONTH   = 31 /*!< Last day of the month */
++} tmdlHdmiCECDayOfMonth_t;
++
++/*!
++	\enum  tmdlHdmiCECDecControlMode_t
++    \brief This enum indicates command used for opcode <Deck Control>
++*/
++typedef enum
++{
++   CEC_DECK_CONTROL_WIND   = 1, /*!< Skip Forward / Wind   */
++   CEC_DECK_CONTROL_REWIND = 2, /*!< Skip Reverse / Rewind */
++   CEC_DECK_CONTROL_STOP   = 3, /*!< Stop                  */
++   CEC_DECK_CONTROL_EJECT  = 4  /*!< Eject                 */
++} tmdlHdmiCECDecControlMode_t;
++
++/*!
++	\enum  tmdlHdmiCECDecInfo_t
++    \brief This enum indicates the current status of a tape or disk deck
++*/
++typedef enum
++{
++   CEC_DECK_INFO_PLAY              = 0x11, /*!< Play                  */
++   CEC_DECK_INFO_RECORD            = 0x12, /*!< Record                */
++   CEC_DECK_INFO_PLAY_REVERSE      = 0x13, /*!< Play Reverse          */
++   CEC_DECK_INFO_STILL             = 0x14, /*!< Still                 */
++   CEC_DECK_INFO_SLOW              = 0x15, /*!< Slow                  */
++   CEC_DECK_INFO_SLOW_REVERSE      = 0x16, /*!< Slow Reverse          */
++   CEC_DECK_INFO_FAST_FORWARD      = 0x17, /*!< Fast Forward          */
++   CEC_DECK_INFO_FAST_REVERSE      = 0x18, /*!< Fast Reverse          */
++   CEC_DECK_INFO_NO_MEDIA          = 0x19, /*!< No Media              */
++   CEC_DECK_INFO_STOP              = 0x1A, /*!< Stop                  */
++   CEC_DECK_INFO_WIND              = 0x1B, /*!< Skip Forward / Wind   */
++   CEC_DECK_INFO_REWIND            = 0x1C, /*!< Skip Reverse / Rewind */
++   CEC_DECK_INFO_ID_SEARCH_FORWARD = 0x1D, /*!< Index Search Forward  */
++   CEC_DECK_INFO_ID_SEARCH_REVERSE = 0x1E, /*!< Index Search Forward  */
++   CEC_DECK_INFO_OTHER_STATUS      = 0x1F  /*!< Other Status          */
++} tmdlHdmiCECDecInfo_t;
++
++
++/*!
++	\enum  tmdlHdmiCECDeviceType_t
++    \brief This enum indicates the device type
++*/
++typedef enum
++{
++   CEC_DEVICE_TYPE_TV               = 0, /*!< TV               */
++   CEC_DEVICE_TYPE_REC_DEVICE       = 1, /*!< Recording Device */
++   CEC_DEVICE_TYPE_RESERVED         = 2, /*!< Reserved         */
++   CEC_DEVICE_TYPE_TUNER            = 3, /*!< Tuner            */
++   CEC_DEVICE_TYPE_PLAYBACK_DEVICE  = 4, /*!< PlayBack Device  */
++   CEC_DEVICE_TYPE_AUDIO_DEVICE     = 5, /*!< Audio System     */
++   CEC_DEVICE_TYPE_PURE_CEC_SWITCTH = 6,  /*!< Pure CEC Switch  */
++   CEC_DEVICE_TYPE_VIDEO_PROCESSOR  = 7  /*!< Video Processor  */
++} tmdlHdmiCECDeviceType_t;
++
++/*!
++	\enum  tmdlHdmiCECServiceIdentMethod_t
++    \brief This enum indicates a Service Indentification Method
++*/
++typedef enum
++{
++   CEC_SERVICE_DIGITAL  = 0, /*!< Service identified by digital IDs  */
++   CEC_SERVICE_CHANNEL  = 1  /*!< Service identified by channel      */
++} tmdlHdmiCECServiceIdentMethod_t;
++
++/*!
++	\enum  tmdlHdmiCECDigitalBroadcastSystem_t
++    \brief This enum indicates the Digital Broadcast System of required service
++*/
++typedef enum
++{
++   CEC_DIGITAL_BROADCAST_SYSTEM_ARIB_GENERIC = 0x01, /*!< ARIB generic */
++   CEC_DIGITAL_BROADCAST_SYSTEM_ATSC_GENERIC = 0x02, /*!< ATSC generic */
++   CEC_DIGITAL_BROADCAST_SYSTEM_DVB_GENERIC  = 0x03, /*!< DVB generic  */
++   CEC_DIGITAL_BROADCAST_SYSTEM_ARIB_BS      = 0x08, /*!< ARIB-BS      */
++   CEC_DIGITAL_BROADCAST_SYSTEM_ARIB_CS      = 0x09, /*!< ARIB-CS      */
++   CEC_DIGITAL_BROADCAST_SYSTEM_ARIB_T       = 0x0A, /*!< ARIB-T       */
++   CEC_DIGITAL_BROADCAST_SYSTEM_CABLE        = 0x10, /*!< Cable        */
++   CEC_DIGITAL_BROADCAST_SYSTEM_SATELLITE    = 0x11, /*!< Satellite    */
++   CEC_DIGITAL_BROADCAST_SYSTEM_TERRESTRIAL  = 0x12, /*!< Terrestrial  */
++   CEC_DIGITAL_BROADCAST_SYSTEM_DVB_C        = 0x18, /*!< DVB-C        */
++   CEC_DIGITAL_BROADCAST_SYSTEM_DVB_S        = 0x19, /*!< DVB-S        */
++   CEC_DIGITAL_BROADCAST_SYSTEM_DVB_S2       = 0x1A, /*!< DVB-S2       */
++   CEC_DIGITAL_BROADCAST_SYSTEM_DVB_T        = 0x1B  /*!< DVB-T        */
++} tmdlHdmiCECDigitalBroadcastSystem_t;
++
++/*!
++	\struct tmdlHdmiCECAribData_t
++    \brief  This struct indicates the ARIB Data
++*/
++typedef struct
++{
++     UInt16 TransportStreamID ; /*!< Tansport_stream_id of the transport stream carrying the required service                  */
++     UInt16 ServiceID         ; /*!< Service_ID of the required service                                                        */
++     UInt16 OriginalNetworkID ; /*!< Original_network_ID of the network carrying the transport stream for the required service */
++} tmdlHdmiCECAribData_t ;
++
++/*!
++	\struct tmdlHdmiCECAtscData_t
++    \brief  This struct indicates the ATSC Data
++*/
++typedef struct
++{
++     UInt16 TransportStreamID ; /*!< Tansport_stream_id of the transport stream carrying the required service */
++     UInt16 ProgramNumber     ; /*!< Program Number of the required service                                   */
++     UInt16 Reserved          ; /*!< Reserved                                                                 */
++} tmdlHdmiCECAtscData_t ; 
++
++/*!
++	\struct tmdlHdmiCECDvbData_t
++    \brief  This struct indicates the DVB Data
++*/
++typedef struct
++{
++     UInt16 TransportStreamID ; /*!< Tansport_stream_id of the transport stream carrying the required service                  */
++     UInt16 ServiceID         ; /*!< Service_ID of the required service                                                        */
++     UInt16 OriginalNetworkID ; /*!< Original_network_ID of the network carrying the transport stream for the required service */
++} tmdlHdmiCECDvbData_t ;
++
++/*!
++	\struct tmdlHdmiCECChannelData_t
++    \brief  This struct indicates the Channel Data
++*/
++typedef struct
++{
++     tmdlHdmiCECChannelIdentifier_t ChannelIdentifier ; /*!< Logical or virtual channel number of a service */
++     UInt16 Reserved                                  ; /*!< Reserved                                       */
++} tmdlHdmiCECChannelData_t ;
++
++/*!
++	\struct tmdlHdmiCECDigitalServiceIdentification_t
++    \brief  This struct indicates the Digital Broadcast System 
++            and the parameters to identify a specific service
++*/
++typedef struct _tmdlHdmiCECDigitalServiceIdentification_t
++{
++     tmdlHdmiCECServiceIdentMethod_t     ServiceIdentificationMethod ; /*!< See tmdlHdmiCECServiceIdentMethod_t                                                                   */
++     tmdlHdmiCECDigitalBroadcastSystem_t DigitalBroadcastSystem      ; /*!< See tmdlHdmiCECDigitalBroadcastSystem_t                                                               */
++     void                                *pServiceIdentification     ; /*!< tmdlHdmiCECAribData_t or tmdlHdmiCECAtscData_t or tmdlHdmiCECDvbData_t or tmdlHdmiCECChannelData_t */
++}tmdlHdmiCECDigitalServiceIdentification_t, *ptmdlHdmiCECDigitalServiceIdentification_t;
++
++/*!
++	\enum  tmdlHdmiCECDisplayControl_t
++    \brief This enum indicates the display mode for an on screen display message
++*/
++typedef enum
++{
++   CEC_DISPLAY_CONTROL_DEFAULT_TIME           = 0  , /*!< Display for default time */
++   CEC_DISPLAY_CONTROL_UNTIL_CLEARED          = 64 , /*!< Display until cleared     */
++   CEC_DISPLAY_CONTROL_CLEAR_PREVIOUS_MESSAGE = 128, /*!< Clear previous message    */
++   CEC_DISPLAY_CONTROL_RESERVED               = 192  /*!< Clear previous message    */
++} tmdlHdmiCECDisplayControl_t;
++
++/*!
++	\struct tmdlHdmiCECDuration_t
++    \brief  This struct indicates a duration in BCD format
++*/
++typedef struct
++{
++     UInt8 Hours  ; /*!< Duration hours in bcd format between 0 and 99 */
++     UInt8 Minute ; /*!< Duration minute in bcd format between 0 and 59 */
++} tmdlHdmiCECDuration_t ;
++
++/*!
++    \brief  This typedef indicates physical adress of device that is to be used as the source of a recording
++*/
++typedef UInt16 tmdlHdmiCECExternalPhysicalAddress_t ;
++
++/*!
++    \brief  This typedef indicates external plug number (1 to 255 )on the recording device
++*/
++typedef UInt8 tmdlHdmiCECExternalPlug_t;
++
++/*!
++	\enum  tmdlHdmiCECExternalSourceSpecifier_t
++    \brief This enum indicates External source specifier 
++*/
++typedef enum
++{
++   CEC_EXTERNAL_PLUG             = 4  , /*!< Display for default time */
++   CEC_EXTERNAL_PHYSICAL_ADDRESS = 5    /*!< Display until cleared     */
++} tmdlHdmiCECExternalSourceSpecifier_t;
++
++/*!
++    \brief  This typedef indicates External Source is specified bey exeternal plug number on the recording device
++            or by the External physical Adress of the required source
++*/
++typedef UInt8 ExternalSourceSpecifier;
++
++
++/*!
++	\enum  tmdlHdmiCECFeatureOpcode_t
++    \brief This enum defines command to be performed
++*/
++typedef enum
++{
++   CEC_OPCODE_FEATURE_ABORT                 = 0x00, /*!< */
++   CEC_OPCODE_IMAGE_VIEW_ON                 = 0x04, /*!< */
++   CEC_OPCODE_TUNER_STEP_INCREMENT          = 0x05, /*!< */
++   CEC_OPCODE_TUNER_STEP_DECREMENT          = 0x06, /*!< */
++   CEC_OPCODE_TUNER_DEVICE_STATUS           = 0x07, /*!< */
++   CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS      = 0x08, /*!< */
++   CEC_OPCODE_RECORD_ON                     = 0x09, /*!< */
++   CEC_OPCODE_RECORD_STATUS                 = 0x0A, /*!< */
++   CEC_OPCODE_RECORD_OFF                    = 0x0B, /*!< */
++   CEC_OPCODE_TEXT_VIEW_ON                  = 0x0D, /*!< */
++   CEC_OPCODE_RECORD_TV_SCREEN              = 0x0F, /*!< */
++   CEC_OPCODE_GIVE_DECK_STATUS              = 0x1A, /*!< */
++   CEC_OPCODE_DECK_STATUS                   = 0x1B, /*!< */
++   CEC_OPCODE_SET_MENU_LANGUAGE             = 0x32, /*!< */
++   CEC_OPCODE_CLEAR_ANALOGUE_TIMER          = 0x33, /*!< */
++   CEC_OPCODE_SET_ANALOGUE_TIMER            = 0x34, /*!< */
++   CEC_OPCODE_TIMER_STATUS                  = 0x35, /*!< */
++   CEC_OPCODE_STANDBY                       = 0x36, /*!< */
++   CEC_OPCODE_PLAY                          = 0x41, /*!< */
++   CEC_OPCODE_DESCK_CONTROL                 = 0x42, /*!< */
++   CEC_OPCODE_TIMER_CLEARED_STATUS          = 0x43, /*!< */
++   CEC_OPCODE_USER_CONTROL_PRESSED          = 0x44, /*!< */
++   CEC_OPCODE_USER_CONTROL_RELEASED         = 0x45, /*!< */
++   CEC_OPCODE_GIVE_OSD_NAME                 = 0x46, /*!< */
++   CEC_OPCODE_SET_OSD_NAME                  = 0x47, /*!< */
++   CEC_OPCODE_SET_OSD_STRING                = 0x64, /*!< */
++   CEC_OPCODE_SET_TIMER_PROGRAM_TITLE       = 0x67, /*!< */
++   CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST     = 0x70, /*!< */
++   CEC_OPCODE_GIVE_AUDIO_STATUS             = 0x71, /*!< */
++   CEC_OPCODE_SET_SYSTEM_AUDIO_MODE         = 0x72, /*!< */
++   CEC_OPCODE_REPORT_AUDIO_STATUS           = 0x7A, /*!< */
++   CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS = 0x7D, /*!< */
++   CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS      = 0x7E, /*!< */
++   CEC_OPCODE_ROUTING_CHANGE                = 0x80, /*!< */
++   CEC_OPCODE_ROUTING_INFORMATION           = 0x81, /*!< */
++   CEC_OPCODE_ACTIVE_SOURCE                 = 0x82, /*!< */
++   CEC_OPCODE_GIVE_PHYSICAL_ADDRESS         = 0x83, /*!< */
++   CEC_OPCODE_REPORT_PHYSICAL_ADDRESS       = 0x84, /*!< */
++   CEC_OPCODE_REQUEST_ACTIVE_SOURCE         = 0x85, /*!< */
++   CEC_OPCODE_SET_STREAM_PATH               = 0x86, /*!< */
++   CEC_OPCODE_DEVICE_VENDOR_ID		    = 0x87, /*!< */
++   CEC_OPCODE_VENDOR_COMMAND                = 0x89, /*!< */
++   CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN     = 0x8A, /*!< */
++   CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP       = 0x8B, /*!< */
++   CEC_OPCODE_GIVE_DEVICE_VENDOR_ID         = 0x8C, /*!< */
++   CEC_OPCODE_MENU_REQUEST                  = 0x8D, /*!< */
++   CEC_OPCODE_MENU_STATUS                   = 0x8E, /*!< */
++   CEC_OPCODE_GIVE_DEVICE_POWER_STATUS      = 0x8F, /*!< */
++   CEC_OPCODE_REPORT_POWER_STATUS           = 0x90, /*!< */
++   CEC_OPCODE_GET_MENU_LANGUAGE             = 0x91, /*!< */
++   CEC_OPCODE_SET_ANALOGUE_SERVICE          = 0x92, /*!< */
++   CEC_OPCODE_SET_DIGITAL_SERVICE           = 0x93, /*!< */
++   CEC_OPCODE_SET_DIGITAL_TIMER             = 0x97, /*!< */
++   CEC_OPCODE_CLEAR_DIGITAL_TIMER           = 0x99, /*!< */
++   CEC_OPCODE_SET_AUDIO_RATE                = 0x9A, /*!< */
++   CEC_OPCODE_INACTIVE_SOURCE               = 0x9D, /*!< */
++   CEC_OPCODE_CEC_VERSION                   = 0x9E, /*!< */
++   CEC_OPCODE_GET_CEC_VERSION               = 0x9F, /*!< */
++   CEC_OPCODE_VENDOR_COMMAND_WITH_ID        = 0xA0, /*!< */
++   CEC_OPCODE_CLEAR_EXTERNAL_TIMER          = 0xA1, /*!< */
++   CEC_OPCODE_SET_EXTERNAL_TIMER            = 0xA2, /*!< */
++   CEC_OPCODE_REPORT_SHORT_AUDIO_DESCRIPTOR = 0xA3, /*!< */
++   CEC_OPCODE_REQUEST_SHORT_AUDIO_DESCRIPTOR = 0xA4, /*!< */
++   CEC_OPCODE_INITATE_ARC                   = 0xC0, /*!< */
++   CEC_OPCODE_REPORT_ARC_INITIATED          = 0xC1, /*!< */
++   CEC_OPCODE_REPORT_ARC_TERMINATED         = 0xC2, /*!< */
++   CEC_OPCODE_REPORT_ARC_INITIATION         = 0xC3, /*!< */
++   CEC_OPCODE_REPORT_ARC_TERMINATION        = 0xC4, /*!< */
++   CEC_OPCODE_TERMINATE_ARC                 = 0xC5, /*!< */
++   CEC_OPCODE_ABORT_MESSAGE                 = 0xFF  /*!< This message is reserved for testing*/
++} tmdlHdmiCECFeatureOpcode_t;
++
++
++/*!
++	\enum  tmdlHdmiCECMenuRequestType_t
++    \brief This enum specifies wether to activate or desactivate a devices menu or
++           simply query its current menu status
++*/
++typedef enum
++{
++   CEC_MENU_TYPE_ACTIVATE        = 0 , /*!< Activate   */
++   CEC_MENU_TYPE_DEACTIVATE      = 1 , /*!< Deactivate */
++   CEC_MENU_TYPE_QUERY           = 2   /*!< Query      */
++} tmdlHdmiCECMenuRequestType_t;
++
++/*!
++	\enum  tmdlHdmiCECMenuState_t
++    \brief This enum pecifies state of the device menu
++*/
++typedef enum
++{
++   CEC_MENU_STATE_ACTIVATE        = 0 , /*!< Activate   */
++   CEC_MENU_STATE_DEACTIVATE      = 1   /*!< Deactivate */
++} tmdlHdmiCECMenuState_t;
++
++/*!
++	\enum  tmdlHdmiCECPlayMode_t
++    \brief This enum indicates in which mode to play media
++*/
++typedef enum
++{
++   CEC_MODE_PLAY_FORWARD              = 0x24 ,
++   CEC_MODE_PLAY_REVERSE              = 0x20 ,
++   CEC_MODE_FAST_FORWARD_MIN_SPEED    = 0x05 ,
++   CEC_MODE_FAST_FORWARD_MEDIUM_SPEED = 0x06 ,
++   CEC_MODE_FAST_FORWARD_MAX_SPEED    = 0x07 ,
++   CEC_MODE_FAST_REVERSE_MIN_SPEED    = 0x09 ,
++   CEC_MODE_FAST_REVERSE_MEDIUM_SPEED = 0x0A ,
++   CEC_MODE_FAST_REVERSE_MAX_SPEED    = 0x0B ,
++   CEC_MODE_SLOW_FORWARD_MIN_SPEED    = 0x15 ,
++   CEC_MODE_SLOW_FORWARD_MEDIUM_SPEED = 0x16 ,
++   CEC_MODE_SLOW_FORWARD_MAX_SPEED    = 0x17 ,
++   CEC_MODE_SLOW_REVERSE_MIN_SPEED    = 0x19 ,
++   CEC_MODE_SLOW_REVERSE_MEDIUM_SPEED = 0x1A ,
++   CEC_MODE_SLOW_REVERSE_MAX_SPEED    = 0x1B  
++} tmdlHdmiCECPlayMode_t;
++
++/*!
++	\enum  tmdlHdmiCECPowerStatus_t
++    \brief This enum indicates the current power status of a device
++*/
++typedef enum
++{
++   CEC_POWER_STATUS_ON                       = 0x00 , /*!< On                          */
++   CEC_POWER_STATUS_STANDBY                  = 0x01 , /*!< Standby                     */
++   CEC_POWER_STATUS_TRANSITION_STANDBY_TO_ON = 0x02 , /*!< In Transition Standby to On */
++   CEC_POWER_STATUS_TRANSITION_ON_TO_STANDBY = 0x03   /*!< In Transition On to StandBy */
++} tmdlHdmiCECPowerStatus_t;
++
++/*!
++	\enum  tmdlHdmiCECRecordSourceType_t
++    \brief This enum allows the record source to be specified for a recording
++*/
++typedef enum
++{
++   CEC_RECORD_SOURCE_OWN_SOURCE                = 1 , /*!< Own Source                */
++   CEC_RECORD_SOURCE_DIGITAL_SERVICE           = 2 , /*!< Digital Service           */
++   CEC_RECORD_SOURCE_ANALOGUE_SERVICE          = 3 , /*!< Analogue Service          */
++   CEC_RECORD_SOURCE_EXTERNAL_PLUG             = 4 , /*!< External Plug             */
++   CEC_RECORD_SOURCE_EXTERNAL_PHYSICAL_ADDRESS = 5   /*!< External Physical Address */
++} tmdlHdmiCECRecordSourceType_t;
++
++/*!
++	\enum  tmdlHdmiCECRecordStatusInfo_t
++    \brief This enum indicates the status of a recording
++*/
++typedef enum
++{
++   CEC_RECORD_STATUS_INFO_RECORDING_CURRENTLY_SELECTED_SOURCE       = 1 , /*!< */
++   CEC_RECORD_STATUS_INFO_RECORDING_DIGITAL_SERVICE                 = 2 , /*!< */
++   CEC_RECORD_STATUS_INFO_RECORDING_ANALOGUE_SERVCICE               = 3 , /*!< */
++   CEC_RECORD_STATUS_INFO_RECORDING_EXTERNAL_INPUT                  = 4 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_UNABLE_TO_RECORD_DIGITAL_SERVICE   = 5 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_UNABLE_TO_RECORD_ANALOGUE_SERVICE  = 6 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_UNABLE_TO_SELECT_REQUIRED_SERVICE  = 7 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_INVALID_EXTERNAL_PLUG_NUMBER       = 9 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_INVALID_EXTERNAL_PHYSICAL_ADDRESS  = 10 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_CA_SYSTEM_NOT_SUPPORTED            = 11 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_NO_OR_INSUFFICIENT_CA_ENTITLEMENTS = 12 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_NOT_ALLOWED_TO_COPY_SOURCE         = 13 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_NO_FURTHER_COPY_ALLOWED            = 14 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_NO_MEDIA                           = 16 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_PLAYING                            = 17 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_ALREADY_RECORDING                  = 18 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_MEDIA_PROTECTED                    = 19 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_NO_SOURCE_SIGNAL                   = 20 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_MEDIA_PROBLEM                      = 21 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_NOT_ENOUGH_SPACE_AVAILABLE         = 22 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_REC_PARENTAL_LOCK_ON                   = 23 , /*!< */
++   CEC_RECORD_STATUS_INFO_RECORDING_TERMINATED_NORMALLY             = 26 , /*!< */
++   CEC_RECORD_STATUS_INFO_RECORDING_HAS_ALREADY_TERMINATED          = 27 , /*!< */
++   CEC_RECORD_STATUS_INFO_NO_RECORDING_OTHER_REASON                 = 31 /*!< */
++} tmdlHdmiCECRecordStatusInfo_t;
++
++
++/*!
++	\enum  tmdlHdmiCECRecordingSequence_t
++    \brief This enum indicates the status of a recording
++*/
++typedef enum
++{
++   CEC_RECORDING_SEQUENCE_ONCE_ONLY = 0 , /*!< */
++   CEC_RECORDING_SEQUENCE_SYNDAY    = 1 , /*!< */
++   CEC_RECORDING_SEQUENCE_MONDAY    = 2 , /*!< */
++   CEC_RECORDING_SEQUENCE_TUESDAY   = 4 , /*!< */
++   CEC_RECORDING_SEQUENCE_WEDNESDAY = 8 , /*!< */
++   CEC_RECORDING_SEQUENCE_THURSDAY  = 16, /*!< */
++   CEC_RECORDING_SEQUENCE_FRIDAY    = 32, /*!< */
++   CEC_RECORDING_SEQUENCE_SATURDAY  = 64  /*!< */
++} tmdlHdmiCECRecordingSequence_t;
++
++/*!
++	\enum  tmdlHdmiCECStatusRequest_t
++    \brief This enum contains the status request mode which can be report once or
++           on all future state changes or reporting off.
++*/
++typedef enum
++{
++   CEC_STATUS_REQUEST_ON   = 1 , /*!< Status Request ON   */
++   CEC_STATUS_REQUEST_OFF  = 2 , /*!< Status Request OFF  */
++   CEC_STATUS_REQUEST_ONCE = 3   /*!< Status Request ONCE */
++} tmdlHdmiCECStatusRequest_t;
++
++/*!
++	\enum  tmdlHdmiCECSystemAudioStatus_t
++    \brief This enum indicates if the system audio Mode is On or Off
++*/
++typedef enum
++{
++   CEC_SYSTEM_AUDIO_STATUS_OFF  = 0 ,   /*!< Status Request OFF  */   
++   CEC_SYSTEM_AUDIO_STATUS_ON   = 1  /*!< Status Request ON   */
++} tmdlHdmiCECSystemAudioStatus_t;
++
++/*!
++	\enum  tmdlHdmiCECTimerClearedStatusData_t
++    \brief This enum indicates status in <Timer Cleared Status> message
++*/
++typedef enum
++{
++   CEC_TIMER_STATUS_TIMER_NOT_CLEARED_RECORDING          = 0,  /*!< */
++   CEC_TIMER_STATUS_TIMER_NOT_CLEARED_NO_MATCHING        = 1,  /*!< */
++   CEC_TIMER_STATUS_TIMER_NOT_CLEARED_NO_INFO_AVAILABLE  = 2,  /*!< */
++   CEC_TIMER_STATUS_TIMER_NOT_TIMER_CLEARED              = 128 /*!< */
++} tmdlHdmiCECTimerClearedStatusData_t;
++
++
++/*!
++	\enum  tmdlHdmiCECTimerOverlapWarning_t
++    \brief This enum indicates if there is another timer block already set which
++           overlaps with this new recording request
++*/
++typedef enum
++{
++   CEC_TIMER_OVERLAP_WARNING_NO_OVERLAP            = 0, /*!< No Overlap   */
++   CEC_TIMER_OVERLAP_WARNING_TIMER_BLOCKS_OVERLAP  = 1  /*!< Timer blocks overlap  */
++} tmdlHdmiCECTimerOverlapWarning_t;
++
++/*!
++	\enum  tmdlHdmiCECMediaInfo_t
++    \brief This enum indicates if removable media is present and its write protect state
++*/
++typedef enum
++{
++   CEC_MEDIA_INFO_MEDIA_PRESENT_AND_NOT_PROTECTED   = 0, /*!< Media present and not protected */
++   CEC_MEDIA_INFO_MEDIA_PRESENT_BUT_PROTECTED       = 1, /*!< Media present but protected     */
++   CEC_MEDIA_INFO_MEDIA_NOT_PRESENT                 = 2, /*!< Media not present               */
++   CEC_MEDIA_INFO_FUTURE_USE                        = 3  /*!< Future use                      */
++} tmdlHdmiCECMediaInfo_t;
++
++
++/*!
++	\enum  tmdlHdmiCECProgrammedIndicator_t
++    \brief This enum indicates a selector for [Timer Programmed Info]
++*/
++typedef enum
++{
++   CEC_PROGRAM_INDICATOR_NOT_PROGRAMMED = 0, /*!< */
++   CEC_PROGRAM_INDICATOR_PROGRAMMED     = 1  /*!< */
++} tmdlHdmiCECProgrammedIndicator_t;
++
++/*!
++	\enum  tmdlHdmiCECProgrammedInfo_t
++    \brief This enum indicates any non-fatal issues with the programming request
++*/
++typedef enum
++{
++   CEC_PROGRAM_INFO_ENOUGHT_SPACE_AVAILABLE_FOR_RECORDING     = 8, /*!< */
++   CEC_PROGRAM_INFO_NOT_ENOUGHT_SPACE_AVAILABLE_FOR_RECORDING = 9, /*!< */
++   CEC_PROGRAM_INFO_NO_MEDIA_INFO_AVAILABLE                   = 10,/*!< */
++   CEC_PROGRAM_INFO_MAY_NOT_BE_ENOUGH_SPACE_AVAILABLE         = 11 /*!< */
++} tmdlHdmiCECProgrammedInfo_t;
++
++
++/*!
++	\enum  tmdlHdmiCECNotProgrammedErrorInfo_t
++    \brief This enum indicates reason for programming failure
++*/
++typedef enum
++{
++   CEC_PROGRAM_ERROR_INFO_FUTURE_USE                        = 0,  /*!< */
++   CEC_PROGRAM_ERROR_INFO_NO_FREE_TIMER_AVAILABLE           = 1,  /*!< */
++   CEC_PROGRAM_ERROR_INFO_DATE_OUT_OF_RANGE                 = 2,  /*!< */
++   CEC_PROGRAM_ERROR_INFO_RECORDING_SEQUENCE_ERROR          = 3,  /*!< */
++   CEC_PROGRAM_ERROR_INFO_INVALID_EXTERNAL_PLUG_NUMBER      = 4,  /*!< */
++   CEC_PROGRAM_ERROR_INFO_INVALID_EXTERNAL_PHYSICAL_ADDRESS = 5,  /*!< */
++   CEC_PROGRAM_ERROR_INFO_CA_SYSTEM_NOT_SUPPORTED           = 6,  /*!< */
++   CEC_PROGRAM_ERROR_INFO_NO_OR_INSUFFICIENT_CA_ENTITLMENTS = 7,  /*!< */
++   CEC_PROGRAM_ERROR_INFO_DOES_NOT_SUPPORT_RESOLUTION       = 8,  /*!< Tuner or recorder does not support HD */
++   CEC_PROGRAM_ERROR_INFO_PARENTAL_LOCK_ON                  = 9,  /*!< */
++   CEC_PROGRAM_ERROR_INFO_CLOCK_FAILURE                     = 10, /*!< */
++   CEC_PROGRAM_ERROR_INFO_DUPLICATE_ALREADY_PROGRAMMED      = 14  /*!< A timer block with identical details has already been programmed*/
++} tmdlHdmiCECNotProgrammedErrorInfo_t;
++
++/*!
++	\struct tmdlHdmiCECTimerProgrammedInfo_t
++    \brief  This struct 
++*/
++typedef struct
++{
++  tmdlHdmiCECProgrammedIndicator_t SelectProgramInfo ; /*!< tmdlHdmiCECProgrammedIndicator_t */
++  UInt8                             ProgramInfo;        /*!< tmdlHdmiCECProgrammedInfo_t or tmdlHdmiCECNotProgrammedErrorInfo_t*/
++  UInt16                            DurationAvailable ; /*!< Optional paramter : If [Programmed Info] is "Not enough space available" */
++} tmdlHdmiCECTimerProgrammedInfo_t ;                   /*!<  If [Not Programmed Info] is "Duplicate : already programmed" */
++
++/*!
++	\struct tmdlHdmiCECTimerStatusData_t
++    \brief  This struct is used by recording device to respond to the initiator
++            of a <Set Timer> message
++*/
++typedef struct
++{
++  tmdlHdmiCECTimerOverlapWarning_t TimerOverlapWarning ; /*!< Indicates if there is another timer block already set which overlaps with this bew recording request*/
++  tmdlHdmiCECMediaInfo_t           MediaInfo           ; /*!< Indicate if removable media is present and its write protect state */
++  tmdlHdmiCECTimerProgrammedInfo_t TimerProgrammedInfo ; /*!< Give information about how and if the programming request has been done */
++} tmdlHdmiCECTimerStatusData_t ;
++
++
++/*!
++	\enum  tmdlHdmiCECRecordingFlag_t
++    \brief This enum indicates if the tuner is being used as a source of a recording
++*/
++typedef enum
++{
++   CEC_RECORDING_FLAG_NOT_BEING_USED_FOR_RECORDING = 0, /*!< Not Being used for recording  */
++   CEC_RECORDING_FLAG_BEING_USED_FOR_RECORDING     = 1  /*!< Being used for recording      */
++} tmdlHdmiCECRecordingFlag_t;
++
++/*!
++	\enum  tmdlHdmiCECTunerDisplayInfo_t
++    \brief This enum indicates if the device is currently displaying its tuner or not.
++           (it may for example be displaying an external source or media)
++*/
++typedef enum
++{
++   CEC_TUNER_DISPLAY_MEDIA_DISPLAYING_DIGITAL_TUNER  = 0, /*!< Displaying Digital Tuner */
++   CEC_TUNER_DISPLAY_MEDIA_NOT_DISPLAYING_TUNER      = 1, /*!< Not Displaying Tuner */
++   CEC_TUNER_DISPLAY_MEDIA_DISPLAYING_ANALOGUE_TUNER = 2  /*!< Not Displaying Tuner */
++} tmdlHdmiCECTunerDisplayInfo_t;
++
++/*!
++    \enum  tmdlHdmiCECUiBroadcastType_t
++    \brief This enum indicates type of broadcast
++*/
++typedef enum
++{
++   CEC_UI_BROADCAST_TYPE_ALL_AVAILABLE           = 0x00 , /*!< */
++   CEC_UI_BROADCAST_TYPE_DIGITAL_ANALOGUE_TOGGLE = 0x01 , /*!< */
++   CEC_UI_BROADCAST_TYPE_ANALOGUE                = 0x10 , /*!< */
++   CEC_UI_BROADCAST_TYPE_ANALOGUE_TERRESTRIAL    = 0x20 , /*!< */
++   CEC_UI_BROADCAST_TYPE_ANALOGUE_CABLE          = 0x30 , /*!< */
++   CEC_UI_BROADCAST_TYPE_ANALOGUE_SATELLITE      = 0x40 , /*!< */
++   CEC_UI_BROADCAST_TYPE_DIGITAL                 = 0x50 , /*!< */
++   CEC_UI_BROADCAST_TYPE_DIGITAL_TERRESTRIAL     = 0x60 , /*!< */
++   CEC_UI_BROADCAST_TYPE_DIGITAL_CABLE           = 0x70 , /*!< */
++   CEC_UI_BROADCAST_TYPE_DIGITAL_SATELLITE       = 0x80 , /*!< */
++   CEC_UI_BROADCAST_TYPE_DIGITAL_COM_SATELLITE   = 0x90 , /*!< */
++   CEC_UI_BROADCAST_TYPE_DIGITAL_COM_SATELLITE_2 = 0x91 , /*!< */
++   CEC_UI_BROADCAST_TYPE_IP                      = 0xA0   /*!< */
++} tmdlHdmiCECUiBroadcastType_t;
++
++/*!
++    \enum  tmdlHdmiCECUiSoundPresentationControl_t
++    \brief This enum indicates the selected command
++*/
++typedef enum
++{
++   CEC_UI_PRESENTATION_CONTROL_SOUND_MIX_DUAL_MONO        = 0x20 , /*!< "Sound Mixing Mode (Dual Mono)" */
++   CEC_UI_PRESENTATION_CONTROL_SOUND_MIX_KARAOKE          = 0x30 , /*!< "Sound Mixing Mode (Karaoke)" */
++   CEC_UI_PRESENTATION_CONTROL_SELECT_AUDIO_DOWNMIX       = 0x80 , /*!< "Select Audio Downmix Mode" */
++   CEC_UI_PRESENTATION_CONTROL_SELECT_AUDIO_REVERBERATION = 0x90 , /*!< "Select Audio Reverberation Processing Mode" */
++   CEC_UI_PRESENTATION_CONTROL_SELECT_AUDIO_EQUALIZER     = 0xA0 , /*!< "Select Audio Equalizer Mode" */
++   CEC_UI_PRESENTATION_CONTROL_BASS_STEP_PLUS             = 0xB1 , /*!< "bass step + " */
++   CEC_UI_PRESENTATION_CONTROL_BASS_NEUTRAL_POSITION      = 0xB2 , /*!< "bass neutral position" */
++   CEC_UI_PRESENTATION_CONTROL_BASS_STEP_MINUS            = 0xB3 , /*!< "bass step - " */
++   CEC_UI_PRESENTATION_CONTROL_TREBLE_STEP_PLUS           = 0xC1 , /*!< "Treble step + " */
++   CEC_UI_PRESENTATION_CONTROL_TREBLE_NEUTRAL_POSITION    = 0xC2 , /*!< "Treble neutral position" */
++   CEC_UI_PRESENTATION_CONTROL_TREBLE_STEP_MINUS          = 0xC3  /*!< "Treble step - " */
++ 
++} tmdlHdmiCECUiSoundPresentationControl_t;
++
++/*!
++	\enum  tmdlHdmiCECUserRemoteControlCommand_t
++    \brief This enum indicates the remote control button pressed
++*/
++typedef enum
++{
++   CEC_REMOTE_BUTTON_SELECT                       = 0, 
++   CEC_REMOTE_BUTTON_UP                           = 1, 
++   CEC_REMOTE_BUTTON_DOWN                         = 2,
++   CEC_REMOTE_BUTTON_LEFT                         = 3,
++   CEC_REMOTE_BUTTON_RIGHT                        = 4,
++   CEC_REMOTE_BUTTON_RIGHT_UP                     = 5,
++   CEC_REMOTE_BUTTON_RIGHT_DOWN                   = 6,
++   CEC_REMOTE_BUTTON_LEFT_UP                      = 7,
++   CEC_REMOTE_BUTTON_LEFT_DOWN                    = 8,
++   CEC_REMOTE_BUTTON_ROOT_MENU                    = 9,
++   CEC_REMOTE_BUTTON_SETUP_MENU                   = 10,
++   CEC_REMOTE_BUTTON_CONTENTS_MENU                = 11,
++   CEC_REMOTE_BUTTON_FAVORITE_MENU                = 12,
++   CEC_REMOTE_BUTTON_EXIT                         = 13,
++   CEC_REMOTE_BUTTON_MEDIA_TOP_MENU               = 16,
++   CEC_REMOTE_BUTTON_MEDIA_CONTEXT                = 17,
++   CEC_REMOTE_BUTTON_NUMBER_ENTRY_MODE            = 29,
++   CEC_REMOTE_BUTTON_NUMBER_11                    = 30,
++   CEC_REMOTE_BUTTON_NUMBER_12                    = 31,
++   CEC_REMOTE_BUTTON_NUMBER_0_OR_NUMBER_10        = 32,
++   CEC_REMOTE_BUTTON_NUMBER_1                     = 33,
++   CEC_REMOTE_BUTTON_NUMBER_2                     = 34,
++   CEC_REMOTE_BUTTON_NUMBER_3                     = 35,
++   CEC_REMOTE_BUTTON_NUMBER_4                     = 36,
++   CEC_REMOTE_BUTTON_NUMBER_5                     = 37,
++   CEC_REMOTE_BUTTON_NUMBER_6                     = 38,
++   CEC_REMOTE_BUTTON_NUMBER_7                     = 39,
++   CEC_REMOTE_BUTTON_NUMBER_8                     = 40,
++   CEC_REMOTE_BUTTON_NUMBER_9                     = 41,
++   CEC_REMOTE_BUTTON_DOT                          = 42,
++   CEC_REMOTE_BUTTON_ENTER                        = 43,
++   CEC_REMOTE_BUTTON_CLEAR                        = 44,
++   CEC_REMOTE_BUTTON_NEXT_FAVORITE                = 47,
++   CEC_REMOTE_BUTTON_CHANNEL_UP                   = 48,
++   CEC_REMOTE_BUTTON_CHANNEL_DOWN                 = 49,
++   CEC_REMOTE_BUTTON_PREVIOUS_CHANNEL             = 50,
++   CEC_REMOTE_BUTTON_SOUND_SELECT                 = 51,
++   CEC_REMOTE_BUTTON_INPUT_SELECT                 = 52,
++   CEC_REMOTE_BUTTON_DISPLAY_INFORMATION          = 53,
++   CEC_REMOTE_BUTTON_HELP                         = 54,
++   CEC_REMOTE_BUTTON_PAGE_UP                      = 55,
++   CEC_REMOTE_BUTTON_PAGE_DOWN                    = 56,
++   CEC_REMOTE_BUTTON_POWER                        = 64,
++   CEC_REMOTE_BUTTON_VOLUME_UP                    = 65,
++   CEC_REMOTE_BUTTON_VOLUME_DOWN                  = 66,
++   CEC_REMOTE_BUTTON_MUTE                         = 67,
++   CEC_REMOTE_BUTTON_PLAY                         = 68,
++   CEC_REMOTE_BUTTON_STOP                         = 69,
++   CEC_REMOTE_BUTTON_PAUSE                        = 70,
++   CEC_REMOTE_BUTTON_RECORD                       = 71,
++   CEC_REMOTE_BUTTON_REWIND                       = 72,
++   CEC_REMOTE_BUTTON_FAST_FORWARD                 = 73,
++   CEC_REMOTE_BUTTON_EJECT                        = 74,
++   CEC_REMOTE_BUTTON_FORWARD                      = 75,
++   CEC_REMOTE_BUTTON_BACKWARD                     = 76,
++   CEC_REMOTE_BUTTON_STOP_RECORD                  = 77,
++   CEC_REMOTE_BUTTON_PAUSE_RECORD                 = 78,
++   CEC_REMOTE_BUTTON_ANGLE                        = 80,
++   CEC_REMOTE_BUTTON_SUB_PICTURE                  = 81,
++   CEC_REMOTE_BUTTON_VIDEO_ON_DEMAND              = 82,
++   CEC_REMOTE_BUTTON_ELECTRONIC_PROGRAM_GUIDE     = 83,
++   CEC_REMOTE_BUTTON_TIMER_PROGRAMMING            = 84,
++   CEC_REMOTE_BUTTON_INITIAL_CONFIGURATION        = 85,
++   CEC_REMOTE_BUTTON_SELECT_BROADCAST_TYPE        = 86,
++   CEC_REMOTE_BUTTON_SELECT_SOUND_PRESENTATION    = 87,
++   CEC_REMOTE_BUTTON_PLAY_FUNCTION                = 96,
++   CEC_REMOTE_BUTTON_PAUSE_PLAY_FUNCTION          = 97,
++   CEC_REMOTE_BUTTON_RECORD_FUNCTION              = 98,
++   CEC_REMOTE_BUTTON_PAUSE_RECORD_FUNCTION        = 99,
++   CEC_REMOTE_BUTTON_STOP_FUNCTION                = 100,
++   CEC_REMOTE_BUTTON_MUTE_FUNCTION                = 101,
++   CEC_REMOTE_BUTTON_RESTORE_VOLUME_FUNCTION      = 102,
++   CEC_REMOTE_BUTTON_TUNE_FUNCTION                = 103,
++   CEC_REMOTE_BUTTON_SELECT_MEDIA_FUNCTION        = 104,
++   CEC_REMOTE_BUTTON_SELECT_AV_INPUT_FUNCTION     = 105,
++   CEC_REMOTE_BUTTON_SELECT_AUDIO_INPUT_FUNCTION  = 106,
++   CEC_REMOTE_BUTTON_POWER_TOGGLE_FUNCTION        = 107,
++   CEC_REMOTE_BUTTON_POWER_OFF_FUNCTION           = 108,
++   CEC_REMOTE_BUTTON_POWER_ON_FUNCTION            = 109,
++   CEC_REMOTE_BUTTON_F1_BLUE                      = 113,
++   CEC_REMOTE_BUTTON_F2_RED                       = 114,
++   CEC_REMOTE_BUTTON_F3_GREEN                     = 115,
++   CEC_REMOTE_BUTTON_F4_YELLOW                    = 116,
++   CEC_REMOTE_BUTTON_F5                           = 117,
++   CEC_REMOTE_BUTTON_DATA                         = 118
++} tmdlHdmiCECUserRemoteControlCommand_t;
++
++/*!
++	\enum  tmdlHdmiCECLogicalAddress_t
++    \brief This enum indicates the logical address of the a device
++*/
++typedef enum
++{
++   CEC_LOGICAL_ADDRESS_TV                     = 0,  /*!< TV                    */
++   CEC_LOGICAL_ADDRESS_RECORDING_DEVICE_1     = 1,  /*!< Recording Device 1    */
++   CEC_LOGICAL_ADDRESS_RECORDING_DEVICE_2     = 2,  /*!< Recording Device 1    */
++   CEC_LOGICAL_ADDRESS_TUNER_1                = 3,  /*!< Tuner 1               */
++   CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_1      = 4,  /*!< Playback Device 1     */
++   CEC_LOGICAL_ADDRESS_AUDIO_SYSTEM           = 5,  /*!< Audio System          */
++   CEC_LOGICAL_ADDRESS_TUNER_2                = 6,  /*!< Tuner 2               */
++   CEC_LOGICAL_ADDRESS_TUNER_3                = 7,  /*!< Tuner 3               */
++   CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_2      = 8,  /*!< Playback Device 2     */
++   CEC_LOGICAL_ADDRESS_RECORDING_DEVICE_3     = 9,  /*!< Recording Device 3    */
++   CEC_LOGICAL_ADDRESS_TUNER_4                = 10, /*!< Tuner 4               */
++   CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_3      = 11, /*!< Playback Device 3     */
++   CEC_LOGICAL_ADDRESS_RESERVED1              = 12, /*!< Reserved              */
++   CEC_LOGICAL_ADDRESS_RESERVED2              = 13, /*!< Reserved              */
++   CEC_LOGICAL_ADDRESS_SPECIFIC_USE           = 14, /*!< Specific Use          */
++   CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST  = 15  /*!< Unregistred/Broadcast */
++} tmdlHdmiCECLogicalAddress_t;
++
++
++/*!
++   \enum  tmdlHdmiCecEvent_t
++   \brief Enum listing all events that can be signalled to application
++ */
++typedef enum
++{
++    TMDL_HDMICEC_CALLBACK_MESSAGE_AVAILABLE = 0,  /**< A message is available on CEC line */
++    TMDL_HDMICEC_CALLBACK_STATUS = 1,             /**< Status of CEC line */
++} tmdlHdmiCecEvent_t;
++
++/*!
++   \enum  tmdlHdmiCecEventStatus_t
++   \brief Enum listing all available event status
++ */
++typedef enum
++{
++    TMDL_HDMICEC_EVENT_ENABLED,      /*!< Event is enabled  */
++    TMDL_HDMICEC_EVENT_DISABLED      /*!< Event is disabled */
++} tmdlHdmiCecEventStatus_t;
++
++/**
++ * \brief System function pointer type, to call user I2C read/write functions
++ * \param slaveAddr     The I2C slave address
++ * \param firstRegister The first device register address to read or write 
++ * \param lenData       Length of data to read or write (i.e. no. of registers)
++ * \param pData         Pointer to data to write, or to buffer to receive data
++ * \return              The call result:
++ *                      - TM_OK: the call was successful
++ *                      - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing
++ *                      - TMBSL_ERR_HDMI_I2C_READ:  failed when reading
++ */
++typedef struct
++{
++    UInt8 slaveAddr;
++    UInt8 firstRegister;
++    UInt8 lenData;
++    UInt8 *pData;
++} tmdlHdmiCecSysArgs_t;
++typedef tmErrorCode_t (*ptmdlHdmiCecSysFunc_t) (tmdlHdmiCecSysArgs_t *pSysArgs);
++
++
++/*!
++   \brief Timer function pointer type, to call an application timer
++   \param Parameter ms: Delay in milliseconds required
++ */
++typedef Void (*ptmbslHdmiCecSysFuncTimer_t) (UInt16 ms);
++
++/*!
++   \brief Callback function pointer type, used to allow driver to callback
++          application when activity status is changing at input.
++   \param Event Identifier of the source event.
++ */
++typedef void (*ptmdlHdmiCecCallbackFunc_t) (tmdlHdmiCecEvent_t event,
++                                               UInt8           *pdata,
++                                               UInt8           size);
++
++/*!
++   \brief Enum listing all supported device versions
++ */
++ typedef enum
++ {
++     TMDL_HDMICEC_DEVICE_UNKNOWN, /*!< HW device is unknown   */
++     TMDL_HDMICEC_DEVICE_TDA9950, /*!< HW device is a TDA9950 */
++     TMDL_HDMICEC_DEVICE_TDA9989, /*!< HW device is a TDA9989 */
++ } tmdlHdmiCecDeviceVersion_t;
++
++
++/*!
++   \brief Enum listing possible CEC clock source
++ */
++ typedef enum
++ {
++     TMDL_HDMICEC_CLOCK_XTAL,
++     TMDL_HDMICEC_CLOCK_FRO,
++     TMDL_HDMICEC_CLOCK_PCLK
++ } tmdlHdmiCecClockSource_t;
++
++
++/**
++ * \brief Structure describing unit capabilities
++ */
++typedef struct
++{
++    tmdlHdmiCecDeviceVersion_t DeviceVersion;  /*!< HW device version                        */
++    tmdlHdmiCECVersion_t       HdmiCecVersion; /*!< Supported HDMI CEC standard version      */
++} tmdlHdmiCecCapabilities_t;
++
++ 
++/*!
++	\struct tmdlHdmiCECInstanceSetup_t
++    \brief  This struct is used to setup CEC driver by application
++            Application setup the device and state of the device.
++*/
++
++typedef struct _tmdlHdmiCecInstanceSetup_t
++{
++    tmdlHdmiCECLogicalAddress_t DeviceLogicalAddress;
++    tmdlHdmiCecClockSource_t    cecClockSource;
++//  tmdlHdmiCECDeviceState_t    DeviceState;
++} tmdlHdmiCecInstanceSetup_t, *ptmdlHdmiCecInstanceSetup_t; 
++ 
++ 
++/**
++ * \brief The structure of a CEC Data Register Protocol
++*/
++typedef struct
++{
++  UInt8 AddressByte;
++  Bool  MessageTypePolling;       /* Indicate if it's a poolling message "1" or a normal CEC message "0" */
++  UInt8 Opcode;
++}tmdlHdmiCecSaveMessage_t;
++
++typedef struct
++{
++  UInt8 FrameByteCount;  
++  UInt8 AddressByte;
++  UInt8 DataBytes[15];
++}tmdlHdmiCecFrameFormat_t;
++
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMICEC_TYPES_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC.c b/drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC.c
+new file mode 100755
+index 0000000..26df9b3
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC.c
+@@ -0,0 +1,7575 @@
++//=============================================================================
++// Copyright (C) 2007 NXP N.V., All Rights Reserved.
++// This source code and any compilation or derivative thereof is the proprietary
++// information of NXP N.V. and is confidential in nature. Under no circumstances
++// is this software to be  exposed to or placed under an Open Source License of
++// any type without the expressed written permission of NXP N.V.
++//=============================================================================
++/*!
++    \file    tmdlHdmiCEC.c
++
++    \version 1.0
++
++    \date    24/07/2007
++
++    \brief   devlib driver component API for the CEC features.
++
++    \section refs  Reference Documents
++             TDA998X Driver - tmdlHdmiTx - SCS.doc
++    \note    None.
++
++    HISTORY :
++    \verbatim
++     Date          Modified by CRPRNr  TASKNr  Maintenance description
++     -------------|-----------|-------|-------|-----------------------------------
++     24/07/2007   |  F.G      |       |       | Creation.
++     -------------|-----------|-------|-------|-----------------------------------
++    \endverbatim
++*/
++//==========================================================================
++
++/*============================================================================*/
++/*                   FILE CONFIGURATION                                       */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                   STANDARD INCLUDE FILES                                   */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                   PROJECT INCLUDE FILES                                    */
++/*============================================================================*/
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#include <linux/kernel.h>
++#else
++#include <string.h>
++#include <stdio.h>
++#endif
++#include "tmdlHdmiCEC_IW.h"
++#include "tmdlHdmiCEC_cfg.h"
++#include "tmdlHdmiCEC.h"
++#include "tmdlHdmiCEC_local.h"
++
++/*============================================================================*/
++/*                   MACRO DEFINITIONS                                        */
++/*============================================================================*/
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#define DV_DBG_PRINT printk
++#else
++#define DV_DBG_PRINT printf
++#endif
++
++/*============================================================================*/
++/*                   TYPE DEFINITIONS                                         */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                   PUBLIC VARIABLE DEFINITIONS                              */
++/*============================================================================*/
++tmdlHdmiCecUnitConfig_t UnitTable[MAX_UNITS] = {
++    {0,CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST,False, TMDL_HDMICEC_DEVICE_TDA9950, CEC_STATE_NOT_INITIALIZED, 0}
++};
++
++tmdlHdmiCecDriverConfigTable_t gtmdlHdmiCecDriverConfigTable[MAX_UNITS];
++
++tmdlHdmiCecSaveMessage_t gtmdlHdmiCecDriverSaveMessage;
++
++
++/*============================================================================*/
++/*                   STATIC CONSTANT DECLARATIONS                             */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                   STATIC VARIABLE DECLARATIONS                             */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                   STATIC FUNCTION DECLARATIONS                             */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                              FUNCTIONS                                     */
++/*============================================================================*/
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGetSWVersion( )
++    \brief Get the software version of the driver.
++
++    \param pSWVersion Pointer to the version structure
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetSWVersion
++(
++    tmSWVersion_t  *pSWVersion
++)
++{
++    /* check that input pointer is not NULL */
++    RETIF(pSWVersion == Null, TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS)
++
++    /* copy SW version */
++    pSWVersion->compatibilityNr = VERSION_COMPATIBILITY;
++    pSWVersion->majorVersionNr  = VERSION_MAJOR;
++    pSWVersion->minorVersionNr  = VERSION_MINOR;
++
++    return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGetNumberOfUnits( )
++    \brief Get the number of available CEC devices in the system.
++           A unit directly represents a physical device.
++
++    \param pUnitCount Pointer to the number of available units.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetNumberOfUnits
++(
++    UInt32  *pUnitCount
++)
++{
++    /* check that input pointer is not NULL */
++    RETIF(pUnitCount == Null, TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS)
++
++    /* copy the maximum number of units */
++    *pUnitCount = MAX_UNITS;
++
++    return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGetInstanceSetup( )
++    \brief Get instance setup parameters.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure that will receive setup
++                      parameters
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetInstanceSetup
++(
++    tmInstance_t                instance,
++    ptmdlHdmiCecInstanceSetup_t pSetupInfo
++)
++{
++    /* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++    /* check that input pointer is not NULL */
++    RETIF(pSetupInfo == Null, TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS)
++
++    /* check if unit corresponding to instance is opened */
++    RETIF(UnitTable[instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++    pSetupInfo->DeviceLogicalAddress  = UnitTable[instance].DeviceLogicalAddress;
++    
++
++    return(TM_OK);
++}
++
++//=========================	=================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecHandleInterrupt( )
++    \brief Make device library handle an incoming interrupt. This function is
++           used by application to tell the device library that the hardware
++           sent an interrupt. It can also be used to poll the interrupt status
++           of the device if the interrupt line is not physically connected to
++           the CPU.
++           This function is synchronous.
++           This function is ISR friendly.
++
++
++    \param instance   Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_FULL: the queue is full
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecHandleInterrupt
++(
++    tmInstance_t    instance
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_ReadBuffer[19] ;   /* I2C Read data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  tmdlHdmiCecUnitConfig_t        *pCecObject; /* Pointer to Cec Object */
++  tmdlHdmiCecFrameFormat_t  ReadFrame;
++  tmdlHdmiCecSaveMessage_t  LastSendMessage;
++  int i;
++
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++  pCecObject = &UnitTable[instance];
++
++#ifdef TMFL_TDA9989
++  //Check if pending CEC interruption
++  errCode = getCecHwRegisters(pDis, E_REG_CEC_INT, I2c_ReadBuffer,1);
++  RETIF(errCode != TM_OK, errCode)
++
++  if ((I2c_ReadBuffer[0] & CEC_INT_MASK) == 0x00)
++  {
++  		//No CEC interruption pending.
++		return TM_OK;
++  }  	
++#endif
++
++  errCode = getCecHwRegisters(pDis, E_REG_CDR0,I2c_ReadBuffer,19);
++  RETIF(errCode != TM_OK, errCode)
++     
++  /*Fill Frame structure with read data*/
++
++  /* Case of Receiving CECData.cnf*/
++  /*Inform Success or reason of failure of CEC message sending*/
++  if (I2c_ReadBuffer[1]== 0x01)
++  {
++    /* Get Infos of last message send */ 
++    getCecLastMessage(&LastSendMessage);
++	
++    if (LastSendMessage.MessageTypePolling)
++    {
++     ReadFrame.FrameByteCount = I2c_ReadBuffer[0];
++     ReadFrame.AddressByte = LastSendMessage.AddressByte;
++     ReadFrame.DataBytes[0]= I2c_ReadBuffer[2];
++    }
++    else
++    {
++     ReadFrame.FrameByteCount = I2c_ReadBuffer[0]+1;
++     ReadFrame.AddressByte = LastSendMessage.AddressByte;
++     ReadFrame.DataBytes[0]= I2c_ReadBuffer[2];
++     ReadFrame.DataBytes[1]= LastSendMessage.Opcode;
++    }
++    
++    pCecObject->MessageCallback(TMDL_HDMICEC_CALLBACK_STATUS
++                               , (Void *) &ReadFrame, ReadFrame.FrameByteCount);
++  }
++
++  /* Case of Receiving CECData.ind*/
++  /*Give receive data from CEC bus*/
++  if (I2c_ReadBuffer[1]== 0x81)
++  {
++    ReadFrame.FrameByteCount = I2c_ReadBuffer[0];
++    ReadFrame.AddressByte = I2c_ReadBuffer[2];
++    for (i=0; i<15; i++)
++    {
++    ReadFrame.DataBytes[i] = I2c_ReadBuffer[i+3];
++    }
++
++    pCecObject->MessageCallback(TMDL_HDMICEC_CALLBACK_MESSAGE_AVAILABLE
++                               , (Void *) &ReadFrame, ReadFrame.FrameByteCount);
++  }
++
++  return(TM_OK);
++
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecOpen( )
++    \brief Open unit 0 of CEC and provides the instance number to
++           the caller. Note that one unit of CEC represents one physical
++           CEC device and that only one instance per unit can be opened.
++
++    \param pInstance Pointer to the variable that will receive the instance
++                     identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_OWNED: the resource is already in use
++            - TMDL_ERR_DLHDMICEC_INIT_FAILED: the unit instance is already
++              initialised or something wrong happened at lower level.
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_NO_RESOURCES: the resource is not available
++            - TMDL_ERR_DLHDMICEC_INVALID_STATE: the state is invalid for
++              the function
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecOpen
++(
++    tmInstance_t   *pInstance
++)
++{
++    /* directly call OpenM function for unit 0 and return the result */
++    return(tmdlHdmiCecOpenM(pInstance, (tmUnitSelect_t)0));
++}
++
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecOpenM( )
++    \brief Open a specific unit of CEC driver and provides the instance
++           number to the caller. Note that one unit of CEC represents one
++           physical CEC device and that only one instance per unit can be
++           opened. This function switches driver's state machine to
++           "initialized" state.
++
++    \param pInstance Pointer to the structure that will receive the instance
++                     identifier.
++    \param unit      Unit number to be opened.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_OWNED: the resource is already in use
++            - TMDL_ERR_DLHDMICEC_INIT_FAILED: the unit instance is already
++              initialised or something wrong happened at lower level.
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_NO_RESOURCES: the resource is not available
++            - TMDL_ERR_DLHDMICEC_INVALID_STATE: the state is invalid for
++              the function
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecOpenM
++(
++    tmInstance_t   *pInstance,
++    tmUnitSelect_t  unit
++)
++{
++
++    /* check if unit number is in range */
++    RETIF((unit < 0) || (unit >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER)
++
++    /* check if Instance pointer is Null */
++    RETIF(pInstance == Null, TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS)
++
++    /* check if unit is already instanciated */
++    RETIF(UnitTable[unit].opened == True, TMDL_ERR_DLHDMICEC_RESOURCE_OWNED)
++
++    /* Ckeck the state */
++    RETIF(UnitTable[unit].state != CEC_STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++    /* instanciate unit and return corresponding instance number */
++    /* Since HW unit are only instanciable once, instance = unit */
++    UnitTable[unit].opened           = True;    
++    UnitTable[unit].MessageCallback = Null;
++    /* Give a logical Address to Device */
++    UnitTable[unit].DeviceLogicalAddress = CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST;
++
++    /* Recover the configuration of the device library */
++    RETIF(tmdlHdmiCecCfgGetConfig(unit, &gtmdlHdmiCecDriverConfigTable[unit])!= TM_OK, TMDL_ERR_DLHDMICEC_INIT_FAILED)
++
++    *pInstance = (tmInstance_t)unit;
++
++    return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecClose( )
++    \brief Close an instance of CEC driver.
++
++    \param instance Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClose
++(
++    tmInstance_t   instance
++)
++{
++    /* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++    /* check if unit corresponding to instance is opened */
++    RETIF(UnitTable[instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++    /* close instance */
++    UnitTable[instance].opened = False;
++    UnitTable[instance].state = CEC_STATE_NOT_INITIALIZED;
++
++    return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecInstanceConfig( )
++    \brief Set the configuration of instance attributes. This function is
++           required by DVP architecture rules but actually does nothing in this
++           driver
++
++    \param instance    Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecInstanceConfig
++(
++    tmInstance_t    instance
++)
++{
++    if (instance);
++
++    return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecInstanceSetup( )
++    \brief Setup the instance with its configuration parameters. This function
++           allows basic instance configuration for CEC Stack Processor.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure containing all setup parameters
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecInstanceSetup
++(
++    tmInstance_t               instance,
++    tmdlHdmiCecInstanceSetup_t *pSetupInfo
++)
++{
++    tmErrorCode_t                  errCode;
++    tmdlHdmiCecDriverConfigTable_t *pDis;     /* Pointer to Device Instance Structure */
++#ifdef TMFL_TDA9989
++    unsigned char               I2c_ReadBuffer[1];
++#endif
++
++
++    /* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++    /* check that input pointer is not NULL */
++    RETIF(pSetupInfo == Null, TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS)
++
++    /* check if unit corresponding to instance is opened */
++    RETIF(UnitTable[instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++    /* Ckeck the state */
++    RETIF(UnitTable[instance].state != CEC_STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++    pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++
++    /* Wait for 250 ms */
++    RETIF( (errCode = tmdlHdmiTxIWWait(500) ) != TM_OK, errCode)
++
++#ifdef TMFL_TDA9989
++    /* Enable CEC Stack Processor */
++	errCode = getCecHwRegisters(pDis, E_REG_CDR0,I2c_ReadBuffer,1);	
++	RETIF(errCode != TM_OK, errCode)
++
++	errCode = getCecHwRegisters(pDis, E_REG_ENAMODS,I2c_ReadBuffer,1);	
++	RETIF(errCode != TM_OK, errCode)
++
++	I2c_ReadBuffer[0] |= DEFAULT_ENAMODS; 
++
++    errCode = setCecHwRegister(pDis, E_REG_ENAMODS, I2c_ReadBuffer[0]);
++    if (errCode != TM_OK)
++    {   
++		//TODO WA still needed?
++		errCode = setCecHwRegister(pDis, E_REG_ENAMODS, I2c_ReadBuffer[0]);
++        RETIF(errCode != TM_OK, errCode)
++    }
++
++    RETIF( (errCode = tmdlHdmiTxIWWait(TDA9950_RESET_DELAY_MS) ) != TM_OK, errCode)
++
++	/* Select CEC clock source and divider value */
++
++    if (pSetupInfo->cecClockSource == TMDL_HDMICEC_CLOCK_XTAL)
++	{
++	   errCode = getCecHwRegisters(pDis, E_REG_CEC_CLK,I2c_ReadBuffer,1);	
++	   RETIF(errCode != TM_OK, errCode)
++
++	   I2c_ReadBuffer[0] &= CEC_CLK_SEL; 
++       errCode = setCecHwRegister(pDis, E_REG_CEC_CLK, I2c_ReadBuffer[0]);
++    }
++
++	RETIF( (errCode = tmdlHdmiTxIWWait(TDA9950_RESET_DELAY_MS) ) != TM_OK, errCode)
++
++    //TODO WA to avoid spurious interrupts
++	errCode = getCecHwRegisters(pDis, E_REG_CDR0,I2c_ReadBuffer,1);
++    RETIF(errCode != TM_OK, errCode)
++#endif
++
++
++    /* Reset CEC Stack Processor */
++    errCode = setCecHwRegister(pDis, E_REG_CCR, 0x80);
++    RETIF(errCode != TM_OK, errCode)
++
++
++    /* Wait for 250 ms */
++    RETIF( (errCode = tmdlHdmiTxIWWait(TDA9950_RESET_DELAY_MS) ) != TM_OK, errCode)
++
++    /* Configure Stack Processor (Retry = 5)*/
++    errCode = setCecHwRegister(pDis, E_REG_CCONR, 0x05);
++    RETIF(errCode != TM_OK, errCode)
++
++
++    UnitTable[instance].DeviceLogicalAddress = pSetupInfo->DeviceLogicalAddress;
++
++
++    /* CEC Control register */
++    errCode = setCecHwRegisterMsbLsb(pDis, E_REG_ACKH, 0x1 << (UnitTable[instance].DeviceLogicalAddress));
++    RETIF(errCode != TM_OK, errCode)
++
++
++    /* CEC Stack Processor enable*/
++    errCode = setCecHwRegister(pDis, E_REG_CCR, 0x40);
++    RETIF(errCode != TM_OK, errCode)
++
++
++    /* switch instance to its new state */
++    UnitTable[instance].state = CEC_STATE_CONFIGURED;
++
++    return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRegisterCallback( )
++    \brief Register event callbacks. Three types of callbacks can be
++           registered : input activity related callback, data related
++           callback (infoframes, packets, etc.) and general information
++           callback. A null pointer means that no callback are registered.
++
++    \param instance                 Instance identifier.
++    \param MessageCallback         Pointer to the callback function that will
++                                    handle message related events.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_INVALID_STATE: the state is invalid for
++              the function
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRegisterCallbacks
++(
++    tmInstance_t               instance,
++    ptmdlHdmiCecCallbackFunc_t MessageCallback
++)
++{
++    /* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++    /* check if unit corresponding to instance is opened */
++    RETIF(UnitTable[instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++    /* check if instance state is correct */
++    //RETIF(UnitTable[instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++    /* store callback pointers */
++    UnitTable[instance].MessageCallback  = MessageCallback;
++
++    return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetLogicalAddress( )
++    \brief Set Device Logical Address
++
++    \param instance      Instance identifier.
++    \param LogicalAddress Logical address value.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetLogicalAddress
++(
++    tmInstance_t   instance,
++	tmdlHdmiCECLogicalAddress_t   LogicalAddress
++)
++{
++    tmErrorCode_t                  errCode;
++    tmdlHdmiCecDriverConfigTable_t *pDis;     /* Pointer to Device Instance Structure */
++	
++    /* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++    /* check if unit corresponding to instance is opened */
++    RETIF(UnitTable[instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++    /* Ckeck the state */
++    RETIF(UnitTable[instance].state != CEC_STATE_CONFIGURED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++    pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++    
++    UnitTable[instance].DeviceLogicalAddress = LogicalAddress;
++    
++    errCode = setCecHwRegisterMsbLsb(pDis, E_REG_ACKH, 0x1 << (UnitTable[instance].DeviceLogicalAddress));
++    RETIF(errCode != TM_OK, errCode)
++
++    return(TM_OK);
++}
++
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetRetry( )
++    \brief Change the number of retransmission
++
++    \param instance Instance identifier.
++    \param NbRetry Number of retry.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetRetry
++(
++    tmInstance_t   instance,
++	UInt8   NbRetry
++)
++{
++    tmErrorCode_t                  errCode;
++	tmdlHdmiCecDriverConfigTable_t *pDis;     /* Pointer to Device Instance Structure */
++	
++	/* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++    /* check if unit corresponding to instance is opened */
++    RETIF(UnitTable[instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++	/* Ckeck the state */
++    RETIF(UnitTable[instance].state != CEC_STATE_CONFIGURED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++	pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++
++    /* Configure Retry register */
++    errCode = setCecHwRegister(pDis, E_REG_CCONR, NbRetry);
++    RETIF(errCode != TM_OK, errCode)
++
++	return(TM_OK);
++}
++
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t getCecLastMessage( )
++    \brief Return the Addresses and the Opcode of the last CEC
++	       transmitted message
++
++    \param pSaveMessage   Pointer to the CEC Save Message
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t getCecLastMessage
++(
++    tmdlHdmiCecSaveMessage_t  *pSaveMessage
++)
++{
++    /* copy Last CEC message datas */
++    pSaveMessage->AddressByte  = gtmdlHdmiCecDriverSaveMessage.AddressByte;
++    pSaveMessage->MessageTypePolling = gtmdlHdmiCecDriverSaveMessage.MessageTypePolling;
++    pSaveMessage->Opcode  = gtmdlHdmiCecDriverSaveMessage.Opcode;
++
++    return(TM_OK);
++}
++
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecImageViewOn( )
++    \brief This message sent by a source device to the TV whenever it enters
++           the active state
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receivers. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecImageViewOn
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C Write data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  //RETIF(UnitTable[instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Image View On command */
++	
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_IMAGE_VIEW_ON ;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecInactiveSource( )
++    \brief This message is used by the currently active source to inform the
++           TV that it has no video to be presented to the user, or is going
++           into standby as the result of a lcoal user command on the device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 ReceiverLogicalAddress, \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress \n
++           Physical Address of the device. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecInactiveSource
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */  	
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++  //======To do : make a prepare message function with parameter
++  /* Inactive source command */  
++  I2c_Buffer[0] = 0x06;  
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_INACTIVE_SOURCE ;  /* Inactive Source*/
++  I2c_Buffer[4] = (unsigned char)(PhysicalAddress >> 8);    /* MsByte of Physical Address */
++  I2c_Buffer[5] = (unsigned char)PhysicalAddress;           /* LsByte of Physical Address */
++
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecActiveSource()
++    \brief This message is used by a new source to indicate that it has started
++           to transmit a stream OR used in reponse to a <Request Active Source>
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt16 PhysicalAddress \n
++           Physical address of the device.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecActiveSource
++(
++   tmInstance_t   Instance,
++   UInt16         PhysicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Active Source command */	
++  I2c_Buffer[0] = 0x06;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= 0x0F;                                                            /* Broadcast*/
++
++  I2c_Buffer[3] = CEC_OPCODE_ACTIVE_SOURCE ;        /* Active source */
++  I2c_Buffer[4] = (unsigned char)(PhysicalAddress >> 8);    /* MsByte of Physical Address */
++  I2c_Buffer[5] = (unsigned char)PhysicalAddress;           /* LsByte of Physical Address */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecVersion()
++    \brief This message is used to indicate the supported CEC version in response
++           to a <Get CEC Version>
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 ReceiverLogicalAddress\n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECVersion_t CECVersion \n
++           Supported CEC Version.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVersion
++(
++   tmInstance_t         Instance,
++   UInt8                ReceiverLogicalAddress,
++   tmdlHdmiCECVersion_t CECVersion
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* CEC Version command */
++  I2c_Buffer[0] = 0x05;     /* Param number */  
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_CEC_VERSION ;  /* CECVersion*/
++  I2c_Buffer[4] = CECVersion;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecClearAnalogueTimer( )
++    \brief This message is used to clear an Analogue timer block of a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n
++
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClearAnalogueTimer
++(
++   tmInstance_t                        Instance,
++   UInt8                               ReceiverLogicalAddress,
++   UInt8                               DayOfMonth,
++   UInt8                               MonthOfYear,
++   UInt16                              StartTime,
++   tmdlHdmiCECDuration_t              *pDuration,
++   UInt8                               RecordingSequence,
++   tmdlHdmiCECAnalogueBroadcastType_t  AnalogueBroadcastType,
++   UInt16                              AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t        BroadcastSystem
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[15] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Clear Analogue Timer command */
++  I2c_Buffer[0] = 0x0f;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_CLEAR_ANALOGUE_TIMER ;
++  I2c_Buffer[4] = DayOfMonth;                       /*Day of Month*/
++  I2c_Buffer[5] = MonthOfYear;                      /*Month of Year*/
++  I2c_Buffer[6] = (unsigned char)(StartTime >> 8);  /*Start Time*/
++  I2c_Buffer[7] = (UInt8)StartTime;
++  I2c_Buffer[8] = pDuration -> Hours;               /*Duration Hours*/
++  I2c_Buffer[9] = pDuration -> Minute;              /*Duration minute*/
++  I2c_Buffer[10] = RecordingSequence;               /*Recording Sequence*/
++  I2c_Buffer[11] = AnalogueBroadcastType;           /*Analogue Broadcast Type*/
++  I2c_Buffer[12] = (unsigned char)(AnalogueFrequency >> 8); /*Analogue Frequency*/
++  I2c_Buffer[13] = (unsigned char)AnalogueFrequency;
++  I2c_Buffer[14] = BroadcastSystem;                 /*BroadcastSystem*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,15); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecClearDigitalTimer( )
++    \brief This message is used to clear a digital timer block of a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClearDigitalTimer
++(
++   tmInstance_t                               Instance,
++   UInt8                                      ReceiverLogicalAddress,
++   UInt8                                      DayOfMonth,
++   UInt8                                      MonthOfYear,
++   UInt16                                     StartTime,
++   tmdlHdmiCECDuration_t                     *pDuration,
++   UInt8                                      RecordingSequence,
++   tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[18] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  tmdlHdmiCECAribData_t *pARIB_Pointer;
++  tmdlHdmiCECAtscData_t *pATSC_Pointer;
++  tmdlHdmiCECDvbData_t  *pDVB_Pointer;
++
++  unsigned char Regval;                 /* Local variable*/
++
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++
++  //======To do : make a prepare message function with parameter
++  /* Clear Digital Timer command */
++  I2c_Buffer[0] = 0x12;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++	/*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_CLEAR_DIGITAL_TIMER ;
++  I2c_Buffer[4] = DayOfMonth;                       /*Day of Month*/
++  I2c_Buffer[5] = MonthOfYear;                      /*Month of Year*/
++  I2c_Buffer[6] = (unsigned char)(StartTime >> 8);  /*Start Time*/
++  I2c_Buffer[7] = (UInt8)StartTime;
++  I2c_Buffer[8] = pDuration -> Hours;               /*Duration Hours*/
++  I2c_Buffer[9] = pDuration -> Minute;              /*Durantion Minute*/
++  I2c_Buffer[10] = RecordingSequence;               /*Recording Sequence*/
++
++  /* Digital service Identification*/
++  /*Merge Service Method and Digital Broadcast System in the same Byte*/
++  Regval = (unsigned char)(pServiceIdentification->ServiceIdentificationMethod & 0x01); /*bit 7 is Service Method*/
++  Regval = Regval << 7;
++  Regval |= (unsigned char)(pServiceIdentification->DigitalBroadcastSystem & 0x7F);     /*bits 6 to 0 are Digital Broadcast*/
++  I2c_Buffer[11] = Regval;
++
++
++  /*Case of a ARIB Generic*/
++  if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ARIB_GENERIC)
++    {
++        pARIB_Pointer = pServiceIdentification->pServiceIdentification;
++
++		I2c_Buffer[12] = (unsigned char)(pARIB_Pointer->TransportStreamID >> 8);
++		I2c_Buffer[13] = (unsigned char)pARIB_Pointer->TransportStreamID;
++		I2c_Buffer[14] = (unsigned char)(pARIB_Pointer->ServiceID >> 8);
++		I2c_Buffer[15] = (unsigned char)pARIB_Pointer->ServiceID;
++		I2c_Buffer[16] = (unsigned char)(pARIB_Pointer->OriginalNetworkID >> 8);
++		I2c_Buffer[17] = (unsigned char)pARIB_Pointer->OriginalNetworkID;
++
++    }
++    /*Case of a ATSC Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ATSC_GENERIC)
++    {
++        pATSC_Pointer = pServiceIdentification->pServiceIdentification;
++
++		I2c_Buffer[12] = (unsigned char)(pATSC_Pointer->TransportStreamID >> 8);
++		I2c_Buffer[13] = (unsigned char)pATSC_Pointer->TransportStreamID;
++		I2c_Buffer[14] = (unsigned char)(pATSC_Pointer->ProgramNumber >> 8);
++		I2c_Buffer[15] = (unsigned char)pATSC_Pointer->ProgramNumber;
++		I2c_Buffer[16] = (unsigned char)(pATSC_Pointer->Reserved >> 8);
++		I2c_Buffer[17] = (unsigned char)pATSC_Pointer->Reserved;
++    }
++    /*Case of a DVB Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_DVB_GENERIC)
++    {
++        pDVB_Pointer = pServiceIdentification->pServiceIdentification;
++
++		I2c_Buffer[12] = (unsigned char)(pDVB_Pointer->TransportStreamID >> 8);
++		I2c_Buffer[13] = (unsigned char)pDVB_Pointer->TransportStreamID;
++		I2c_Buffer[14] = (unsigned char)(pDVB_Pointer->ServiceID >> 8);
++		I2c_Buffer[15] = (unsigned char)pDVB_Pointer->ServiceID;
++		I2c_Buffer[16] = (unsigned char)(pDVB_Pointer->OriginalNetworkID >> 8);
++		I2c_Buffer[17] = (unsigned char)pDVB_Pointer->OriginalNetworkID;
++    }
++    /*other cases, Buffer are empty*/
++  else
++    {
++		I2c_Buffer[12] = 0xFF;
++		I2c_Buffer[13] = 0xFF;
++		I2c_Buffer[14] = 0xFF;
++		I2c_Buffer[15] = 0xFF;
++		I2c_Buffer[16] = 0xFF;
++		I2c_Buffer[17] = 0xFF;
++    }
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,18); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecClearExternalTimerWithExternalPlug( )
++    \brief This message is used to clear a digital timer block of a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++
++    \param tmdlHdmiCECExternalPlug_t  ExternalPlug \n
++           indicates external plug number (1 to 255 )on the recording device.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClearExternalTimerWithExternalPlug
++(
++   tmInstance_t                Instance,
++   UInt8                       ReceiverLogicalAddress,
++   UInt8                       DayOfMonth,
++   UInt8                       MonthOfYear,
++   UInt16                      StartTime,
++   tmdlHdmiCECDuration_t      *pDuration,
++   UInt8                       RecordingSequence,
++   tmdlHdmiCECExternalPlug_t   ExternalPlug
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[13] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  // RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Clear External Timer with External Plug Command*/
++  I2c_Buffer[0] = 0x0D;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_CLEAR_EXTERNAL_TIMER ;
++  I2c_Buffer[4] = DayOfMonth;                       /*Day of Month*/
++  I2c_Buffer[5] = MonthOfYear;                      /*Month of Year*/
++  I2c_Buffer[6] = (unsigned char)(StartTime >> 8);  /*Start Time*/
++  I2c_Buffer[7] = (unsigned char)StartTime;
++  I2c_Buffer[8] = pDuration -> Hours;               /*Duration Hours*/
++  I2c_Buffer[9] = pDuration -> Minute;              /*Duration minute*/	
++  I2c_Buffer[10] = RecordingSequence;               /*Recording Sequence*/
++  I2c_Buffer[11] = CEC_EXTERNAL_PLUG;               /*External Source Specifier = External Plug */
++  I2c_Buffer[12] = ExternalPlug;                    /*External Plug*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,13); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecClearExternalTimerWithPhysicalAddress( )
++    \brief This message is used to clear a digital timer block of a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++
++    \param tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress \n
++           Defines the path between the TV an a device-thus giving it a physical
++           address within the cluster.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecClearExternalTimerWithPhysicalAddress
++(
++   tmInstance_t                           Instance,
++   UInt8                                  ReceiverLogicalAddress,
++   UInt8                                  DayOfMonth,
++   UInt8                                  MonthOfYear,
++   UInt16                                 StartTime,
++   tmdlHdmiCECDuration_t                 *pDuration,
++   UInt8                                  RecordingSequence,
++   tmdlHdmiCECExternalPhysicalAddress_t   ExternalPhysicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[14] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Clear External Timer with Physical Address Command */
++  I2c_Buffer[0] = 0x0E;     /* Param number */  
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++ /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_CLEAR_EXTERNAL_TIMER ;             /*Clear External Timer*/
++  I2c_Buffer[4] = DayOfMonth;                                   /*Day of Month*/
++  I2c_Buffer[5] = MonthOfYear;                                  /*Month of Year*/
++  I2c_Buffer[6] = (unsigned char)(StartTime >> 8);              /*Start Time*/
++  I2c_Buffer[7] = (unsigned char)StartTime;
++  I2c_Buffer[8] = pDuration -> Hours;                           /*Duration Hours*/
++  I2c_Buffer[9] = pDuration -> Minute;                          /*Duration Minute*/
++  I2c_Buffer[10] = RecordingSequence;                           /*Recording Sequence*/
++  I2c_Buffer[11] = CEC_EXTERNAL_PHYSICAL_ADDRESS;               /*External Source Specifier = External Address*/
++  I2c_Buffer[12] = (unsigned char)(ExternalPhysicalAddress >> 8);   /*External Address*/
++  I2c_Buffer[13] = (unsigned char)ExternalPhysicalAddress;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,14); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecTextViewOn( )
++    \brief This message as <Image View On>, but should also remove any text,
++           menus and PIP windows from the TV's display
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTextViewOn
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to Instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if Instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Text View On command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_TEXT_VIEW_ON ;     /* Text View On */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecTimerClearedStatus( )
++    \brief This message is used to give the status of a <Cleared Analogue Timer>,
++           <Clear Digital Timer> or <Clear External Timer> message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECTimerClearedStatusData_t TimerClearedStatusData \n
++           Indicates if the timer was cleared successfully. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTimerClearedStatus
++(
++   tmInstance_t                        Instance,
++   UInt8                               ReceiverLogicalAddress,
++   tmdlHdmiCECTimerClearedStatusData_t TimerClearedStatusData
++)
++{
++
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Timer Clear Status command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_TIMER_CLEARED_STATUS;  /* System Audio Status*/
++  I2c_Buffer[4] = TimerClearedStatusData;           /* Timer Cleared Status*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecTimerStatus( )
++    \brief This message is used to send timer status to the initiator of a
++           <Set Timer> message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECTimerStatusData_t *pTimerStatusData \n
++           Pointer on the Timer status. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTimerStatus
++(
++   tmInstance_t                 Instance,
++   UInt8                        ReceiverLogicalAddress,
++   tmdlHdmiCECTimerStatusData_t *pTimerStatusData
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[7] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  tmdlHdmiCECTimerProgrammedInfo_t *pTimerProgInfo;
++  unsigned char Regval;
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Timer Status command */
++  I2c_Buffer[0] = 0x07;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++ /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_TIMER_CLEARED_STATUS;  /* System Audio Status*/
++  /* First Byte Building */
++  Regval = ((unsigned char)(pTimerStatusData->TimerOverlapWarning)& 0x01) << 7 ; // bit 7 for Timer Overlap Warning
++  Regval |= ((unsigned char)(pTimerStatusData->MediaInfo)& 0x03) << 5;           // bit 6 to 5 for Media Info
++
++  pTimerProgInfo = &(pTimerStatusData->TimerProgrammedInfo);
++  Regval |= ((unsigned char)(pTimerProgInfo->SelectProgramInfo)& 0x01)<< 4;      // bit 4 for Timer Programed Indicator
++  Regval |= (unsigned char)(pTimerProgInfo->ProgramInfo)& 0x0F;                  // bit 3 to 0 for Program Information
++  I2c_Buffer[4] = Regval;
++
++  /* 2 Duration Available Bytes Building */
++  /* Duration Available is only filled in the the both following conditions*/
++  if((pTimerProgInfo->SelectProgramInfo == CEC_PROGRAM_INDICATOR_NOT_PROGRAMMED)&&(pTimerProgInfo->ProgramInfo == CEC_PROGRAM_ERROR_INFO_DUPLICATE_ALREADY_PROGRAMMED))
++  {
++  I2c_Buffer[5] = (unsigned char)(pTimerProgInfo->DurationAvailable >> 8);
++  I2c_Buffer[6] = (unsigned char)pTimerProgInfo->DurationAvailable;
++  }
++  else if((pTimerProgInfo->SelectProgramInfo == CEC_PROGRAM_INDICATOR_PROGRAMMED)&&(pTimerProgInfo->ProgramInfo == CEC_PROGRAM_INFO_NOT_ENOUGHT_SPACE_AVAILABLE_FOR_RECORDING))
++  {
++  I2c_Buffer[5] = (unsigned char)(pTimerProgInfo->DurationAvailable >> 8);
++  I2c_Buffer[6] = (unsigned char)pTimerProgInfo->DurationAvailable;
++  }
++  /*Else, 2 bytes of Duration Available are filled with 0xFF*/
++  else
++  {
++  I2c_Buffer[5] = 0xFF;
++  I2c_Buffer[6] = 0xFF;
++  }
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,7); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecTunerDeviceStatusAnalogue( )
++    \brief This message is used by a tuner device to provide its status to the
++           initiator of the <Give Tuner Device Status> message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECRecordingFlag_t RecordingFlag \n
++           Indicates if the tuner is being used as a source of a recording. \n
++
++    \param tmdlHdmiCECTunerDisplayInfo_t TunerDisplayInfo \n
++           Indicates if the the device is currently deplaying its tuner or not. \n
++
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n
++
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTunerDeviceStatusAnalogue
++(
++   tmInstance_t                       Instance,
++   UInt8                              ReceiverLogicalAddress,
++   tmdlHdmiCECRecordingFlag_t         RecordingFlag,
++   tmdlHdmiCECTunerDisplayInfo_t      TunerDisplayInfo,
++   tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType,
++   UInt16                             AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t       BroadcastSystem
++   )
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[9] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  unsigned char Regval;                 /*Local Variable*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Select Aanalogue Service command */
++  I2c_Buffer[0] = 0x09;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_TUNER_DEVICE_STATUS ;          /* Tuner Device Status*/
++  /* Build First Byte*/
++  Regval = ((unsigned char)RecordingFlag & 0X01)<< 7;       /*bit 7 is Recording Flag */
++  Regval |= (unsigned char)TunerDisplayInfo & 0X7F;         /*bit 6 to 0 are Tuner display Info*/
++  I2c_Buffer[4] = Regval;
++
++  I2c_Buffer[5] = AnalogueBroadcastType;                    /*Analogue Broadcast System type*/
++  I2c_Buffer[6] = (unsigned char)(AnalogueFrequency >> 8);  /*Analogue Frequency*/
++  I2c_Buffer[7] = (unsigned char)AnalogueFrequency;
++  I2c_Buffer[8] = BroadcastSystem;                          /*Broadcast System*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,9); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecTunerDeviceStatusDigital( )
++    \brief This message is used by a tuner device to provide its status to the
++           initiator of the <Give Tuner Device Status> message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECRecordingFlag_t RecordingFlag \n
++           Indicates if the tuner is being used as a source of a recording. \n
++
++    \param tmdlHdmiCECTunerDisplayInfo_t TunerDisplayInfo \n
++           Indicates if the the device is currently deplaying its tuner or not. \n
++
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTunerDeviceStatusDigital
++(
++   tmInstance_t                               Instance,
++   UInt8                                      ReceiverLogicalAddress,
++   tmdlHdmiCECRecordingFlag_t                 RecordingFlag,
++   tmdlHdmiCECTunerDisplayInfo_t              TunerDisplayInfo,
++   ptmdlHdmiCECDigitalServiceIdentification_t pServiceIdentification
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[12] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  tmdlHdmiCECAribData_t *pARIB_Pointer;
++  tmdlHdmiCECAtscData_t *pATSC_Pointer;
++  tmdlHdmiCECDvbData_t  *pDVB_Pointer;
++
++  unsigned char Regval;                 /* Local variable*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Record On Digital Service command */
++  I2c_Buffer[0] = 0x0C;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_TUNER_DEVICE_STATUS ;      /* Tuner Device Status*/
++
++  /* Merge Recording Flag With Tuner Display Info*/
++  Regval = ((unsigned char)RecordingFlag & 0X01)<< 7; /* bit 7 is Recording Flag*/
++  Regval |= (unsigned char)TunerDisplayInfo & 0X7F;   /* bit 6 to 0 are Tuner display Info*/
++  I2c_Buffer[4] = Regval;
++
++  /* Digital service Identification*/
++  /*Merge Service Method and Digital Broadcast System in the same Byte*/
++  Regval = (unsigned char)(pServiceIdentification->ServiceIdentificationMethod & 0x01) << 7; /* bit 7 is Service Method*/
++  Regval |= (unsigned char)(pServiceIdentification->DigitalBroadcastSystem & 0x7F);          /* bits 6 to 0 are Digital Broadcast*/
++  I2c_Buffer[5] = Regval;
++
++  /*Case of a ARIB Generic*/
++  if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ARIB_GENERIC)
++    {
++        pARIB_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[6] = (unsigned char)(pARIB_Pointer->TransportStreamID >> 8);
++        I2c_Buffer[7] = (unsigned char)pARIB_Pointer->TransportStreamID;
++        I2c_Buffer[8] = (unsigned char)(pARIB_Pointer->ServiceID >> 8);
++        I2c_Buffer[9] = (unsigned char)pARIB_Pointer->ServiceID;
++        I2c_Buffer[10] = (unsigned char)(pARIB_Pointer->OriginalNetworkID >> 8);
++        I2c_Buffer[11] = (unsigned char)pARIB_Pointer->OriginalNetworkID;
++    }
++    /*Case of a ATSC Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ATSC_GENERIC)
++    {
++        pATSC_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[6] = (unsigned char)(pATSC_Pointer->TransportStreamID >> 8);
++        I2c_Buffer[7] = (unsigned char)pATSC_Pointer->TransportStreamID;
++        I2c_Buffer[8] = (unsigned char)(pATSC_Pointer->ProgramNumber >> 8);
++        I2c_Buffer[9] = (unsigned char)pATSC_Pointer->ProgramNumber;
++        I2c_Buffer[10] = (unsigned char)(pATSC_Pointer->Reserved >> 8);
++        I2c_Buffer[11] = (unsigned char)pATSC_Pointer->Reserved;
++    }
++    /*Case of a DVB Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_DVB_GENERIC)
++    {
++        pDVB_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[6] = (unsigned char)(pDVB_Pointer->TransportStreamID >> 8);
++        I2c_Buffer[7] = (unsigned char)pDVB_Pointer->TransportStreamID;
++        I2c_Buffer[8] = (unsigned char)(pDVB_Pointer->ServiceID >> 8);
++        I2c_Buffer[9] = (unsigned char)pDVB_Pointer->ServiceID;
++        I2c_Buffer[10] = (unsigned char)(pDVB_Pointer->OriginalNetworkID >> 8);
++        I2c_Buffer[11] = (unsigned char)pDVB_Pointer->OriginalNetworkID;
++    }
++    /*other cases, Buffer are empty*/
++  else
++    {
++        I2c_Buffer[6] = 0xFF;
++        I2c_Buffer[7] = 0xFF;
++        I2c_Buffer[8] = 0xFF;
++        I2c_Buffer[9] = 0xFF;
++        I2c_Buffer[10] = 0xFF;
++        I2c_Buffer[11] = 0xFF;
++    }
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,12); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRequestActiveSource( )
++    \brief This message is used by a new device to discover the status of
++           the system.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_Instance: the Instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRequestActiveSource
++(
++   tmInstance_t  Instance
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* IRequest Active Source command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= 0x0F;                                                            /* Broadcast*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REQUEST_ACTIVE_SOURCE ;        /* Request Active Source */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRoutingChange( )
++    \brief This message is sent by a CEC switch when it is manually switched to
++           inform all other devices on the network that the active route below
++           the switch has changed.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt16 OriginalAddress \n
++           Previous address that the switch was switched to. \n
++
++    \param UInt16 NewAddress \n
++           The new address it has been moved to. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRoutingChange
++(
++   tmInstance_t  Instance,
++   UInt16        OriginalAddress,
++   UInt16        NewAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[8] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Routing Change command */
++  I2c_Buffer[0] = 0x08;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= 0x0F;                                                            /* Broadcast*/
++
++  I2c_Buffer[3] = CEC_OPCODE_ROUTING_CHANGE ;            /* Routing Change */
++  I2c_Buffer[4] = (unsigned char)(OriginalAddress >> 8); /* MsByte of Original Address*/
++  I2c_Buffer[5] = (unsigned char)OriginalAddress;        /* LsByte of Original Address */
++  I2c_Buffer[6] = (unsigned char)(NewAddress >> 8);      /* MsByte of New Address */
++  I2c_Buffer[7] = (unsigned char)NewAddress;             /* LsByte of New Address */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,8); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRoutingInformation( )
++    \brief This message is sent by a CEC switch to indicate the active route
++           below the switch.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt16 PhysicalAddress \n
++           The current active route to the sink in the CEC switch. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRoutingInformation
++(
++   tmInstance_t  Instance,
++   UInt16        PhysicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Routing Information command */
++  I2c_Buffer[0] = 0x06;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= 0x0F;                                                            /* Broadcast*/
++
++  I2c_Buffer[3] = CEC_OPCODE_ROUTING_INFORMATION ;       /* Routing Information */
++  I2c_Buffer[4] = (unsigned char)(PhysicalAddress >> 8); /* MsByte of Physical Address*/
++  I2c_Buffer[5] = (unsigned char)PhysicalAddress;        /* LsByte of Physical Address */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSelectAnalogueService( )
++    \brief This message select directly an analogue TV Service.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n
++
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSelectAnalogueService
++(
++   tmInstance_t                       Instance,
++   UInt8                              ReceiverLogicalAddress,
++   tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType,
++   UInt16                             AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t       BroadcastSystem
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[8] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Select Aanalogue Service command */
++  I2c_Buffer[0] = 0x08;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_ANALOGUE_SERVICE ; /* Select Analogue Service*/
++  I2c_Buffer[4] = AnalogueBroadcastType;
++  I2c_Buffer[5] = (unsigned char)(AnalogueFrequency >> 8);
++  I2c_Buffer[6] = (unsigned char)AnalogueFrequency;
++  I2c_Buffer[7] = BroadcastSystem;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,8); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetStreamPath( )
++    \brief This message is used by a TV to request a streaming path from
++           the specified physical address.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt16 PhysicalAddress \n
++           Physical address of the device.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetStreamPath
++(
++   tmInstance_t  Instance,
++   UInt16        PhysicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set Stream Path command */
++  I2c_Buffer[0] = 0x06;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= 0x0F;                                                            /* Broadcast*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_STREAM_PATH ;              /* Set Stream Path */
++  I2c_Buffer[4] = (unsigned char)(PhysicalAddress >> 8);    /* MsByte of Physical Address*/
++  I2c_Buffer[5] = (unsigned char)PhysicalAddress;           /* LsByte of Physical Address */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++ //==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetSystemAudioMode( )
++    \brief This message turn the system audio Mode ON or OFF.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECSystemAudioStatus_t SystemAudioStatus \n
++           Specifies if the system audio mode is ON or OFF.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetSystemAudioMode
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress,
++   tmdlHdmiCECSystemAudioStatus_t SystemAudioStatus
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set System Audio Mode Command */
++  I2c_Buffer[0] = 0x05;    /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_SYSTEM_AUDIO_MODE ;    /* Set System Audio Mode*/
++  I2c_Buffer[4] = SystemAudioStatus;                    /*System Audio Status*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetTimerProgramTitle( )
++    \brief This message is used to set the name of a program associated
++           with a timer block.Sent directly after sending a
++           <Set analogue Timer> or <Set Digital Timer> message. The name
++           is then associated with that timer block.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param const char *pProgramTitleString \n
++           Pointer on the program title. \n
++
++    \param UInt8    ProgramTitleLength \n
++           Length of Program Title String. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetTimerProgramTitle
++(
++   tmInstance_t Instance,
++   UInt8        ReceiverLogicalAddress,
++   const char   *pProgramTitleString,
++   UInt8        ProgramTitleLength
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[19] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  unsigned char loci;                   /* Local increment variable*/
++  unsigned char MessLength;             /* Local Message length*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Set Timer Program Title */
++  MessLength = ProgramTitleLength+4;                         /* Calculate Message length*/
++
++  I2c_Buffer[0] = (unsigned char)MessLength;
++
++  I2c_Buffer[1] = 0x00;                                      /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_TIMER_PROGRAM_TITLE ;      /* Set Timer Program Title*/
++
++  for(loci = 0; loci <= ProgramTitleLength ; loci++)
++    {
++        I2c_Buffer[(loci+4)] = pProgramTitleString[loci];     /* Fill Table with Program Title characters*/
++    }
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,(MessLength)); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecStandby( )
++    \brief This message switches one or all devices into standby mode.Can be
++           be used as a broadcast message o be addressed to a specific device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecStandby
++(
++   tmInstance_t Instance,
++   UInt8        ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Standby command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_STANDBY ;      /* Standby */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSystemAudioModeRequest( )
++    \brief A device implementing System Audio Control and which has volume
++           control RC button(eg TV or STB) request to use System Audio Mode
++           to the amplifier.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt16 PhysicalAddress \n
++           Physical address of the device.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSystemAudioModeRequest
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress,
++   UInt16        PhysicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* System Audio Mode Request command */
++  I2c_Buffer[0] = 0x06;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST ;    /* System Audio Mode Request*/
++  I2c_Buffer[4] = (unsigned char)(PhysicalAddress >> 8);    /* MsByte of Physical Address */
++  I2c_Buffer[5] = (unsigned char)PhysicalAddress;           /* LsByte of Physical Address */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSystemAudioModeStatus( )
++    \brief Reports the current status of the System Audio Mode.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECSystemAudioStatus_t SystemAudioStatus \n
++           Current system audio mode.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSystemAudioModeStatus
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress,
++   tmdlHdmiCECSystemAudioStatus_t SystemAudioStatus
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* System Audio Mode Status command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS ; /* System Audio Mode Status*/
++  I2c_Buffer[4] = SystemAudioStatus;                    /* System Audio Status*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGiveTunerDeviceStatus( )
++    \brief This message is used to request the status of a tuner device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECStatusRequest_t StatusRequest \n
++           Allows the initiator to request the status once or on all future state
++           change. Or to cancel a previous <Give Tuner Device Status > ["On"] request. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveTunerDeviceStatus
++(
++   tmInstance_t               Instance,
++   UInt8                      ReceiverLogicalAddress,
++   tmdlHdmiCECStatusRequest_t StatusRequest
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* System Audio Mode Request command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS ; /* Give Tuner Device Status*/
++  I2c_Buffer[4] = (unsigned char)StatusRequest; /* Status Request */
++
++  errCode = setCecHwRegisters(pDis,E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRecordTvScreen( )
++    \brief This message request by the recording device to record the presently
++           displayed source.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordTvScreen
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress
++)
++{ tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Record TV Sreen command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++ /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_RECORD_TV_SCREEN ;     /* Record TV screen */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecReportAudioStatus( )
++    \brief This message report an amplifier's volume and mute.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECAudioStatus_t AudioStatus \n
++           Volume and mute status. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportAudioStatus
++(
++   tmInstance_t              Instance,
++   UInt8                     ReceiverLogicalAddress,
++   ptmdlHdmiCECAudioStatus_t pAudioStatus
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  unsigned char Regval;                 /*Local Variable*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Report Audio Status command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REPORT_AUDIO_STATUS ;  /* Report Audio Statust*/
++  Regval = (((unsigned char)pAudioStatus -> audioMuteStatus) & 0x01 )<< 7; /* bit 7 Mute Status*/
++  Regval |= ((unsigned char)pAudioStatus -> audioVolumeStatus) & 0x7F; /* bit 6 to 0 Volum Status*/
++  I2c_Buffer[4] = Regval;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecReportShortAudioDescriptor( )
++    \brief This message Report Audio Capability.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt32 ShortAudioDecriptor \n
++           Audio Descriptor. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportShortAudioDescriptor
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress,
++   UInt32         ShortAudioDecriptor
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[7] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Report Short Audio Decriptor */
++  I2c_Buffer[0] = 0x07;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REPORT_SHORT_AUDIO_DESCRIPTOR ;  /* Report Audio Capability*/
++  I2c_Buffer[4] = (unsigned char)(ShortAudioDecriptor >> 16);  /* MSByte of ShortAudioDecriptor*/
++  I2c_Buffer[5] = (unsigned char)(ShortAudioDecriptor >> 8);
++  I2c_Buffer[6] = (unsigned char)ShortAudioDecriptor;          /* LSByte of ShortAudioDecriptor*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,7); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRequestShortAudioDescriptor( )
++    \brief This message Request Audio Capability.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt8 AudioFormatID \n
++	   
++    \param UInt8 AudioFormatCode \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRequestShortAudioDescriptor
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress,
++   UInt8          AudioFormatID,
++   UInt8          AudioFormatCode
++   
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  unsigned char Regval;                 /*Local Variable*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Report Short Audio Decriptor */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REQUEST_SHORT_AUDIO_DESCRIPTOR ;  /* Request Audio Capability*/
++  Regval = (((unsigned char)AudioFormatCode) & 0x3F )<< 2; /* bit 3 to 7  AudioFormatCode*/
++  Regval |= ((unsigned char)AudioFormatID) & 0x03; /* bit 1 to 0 AudioFormatID*/
++  I2c_Buffer[4] = Regval;
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,7); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecIniateARC( )
++    \brief This message Used by an ARC RX device to activate the
++           ARC functionality in an ARC TX device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecIniateARC
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Report Short Audio Decriptor */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_INITATE_ARC ; 
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecReportArcInitiated( )
++    \brief This message Used by an ARC TX device to indicate that
++           its ARC functionality has been activated
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportArcInitiated
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Report Short Audio Decriptor */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REPORT_ARC_INITIATED ; 
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecReportArcTerminated( )
++    \brief This message Used by an ARC TX device to indicate that its ARC functionality
++           has been deactivated.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportArcTerminated
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Report Short Audio Decriptor */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REPORT_ARC_TERMINATED ; 
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRequestArcInitiation( )
++    \brief This message Used by an ARC TX device to request an ARC RX device to
++           activate the ARC functionality in the ARC TX device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRequestArcInitiation
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Report Short Audio Decriptor */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REPORT_ARC_INITIATION ; 
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRequestArcTerminiation( )
++    \brief Used by an ARC TX device to request an ARC RX device to deactivate 
++           the ARC functionality in the ARC TX device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRequestArcTerminiation
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Report Short Audio Decriptor */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REPORT_ARC_TERMINATION ; 
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecTerminateARC( )
++    \brief Used by an ARC TX device to request an ARC RX device to deactivate 
++           the ARC functionality in the ARC TX device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++	   
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTerminateARC
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Report Short Audio Decriptor */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_TERMINATE_ARC ; 
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGivePhysicalAddress( )
++    \brief This message is a request to a device to return its physical Address
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGivePhysicalAddress
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Give physical Address command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GIVE_PHYSICAL_ADDRESS ;        /* Give Physical Address */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGiveSystemAudioModeStatus( )
++    \brief This message request the status of the system audio mode
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveSystemAudioModeStatus
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Give System Audio Mode Status command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS ;    /* Give System Audio Mode Status*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGetMenuLanguage( )
++    \brief This message is sent by a device capable of character generation
++           (for OSD and Menus) to a TV in order to discover the currently selected
++           Menu Language. Also used by a TV during installation to dicover the
++           currently set menu language of other devices.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetMenuLanguage
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Get Menu Language command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GET_MENU_LANGUAGE ;        /* Get Menu Address */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGiveAudioStatus( )
++    \brief This message is requests an amplifier to send its volume and mute status
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveAudioStatus
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Give Audio Mode Status command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GIVE_AUDIO_STATUS ;    /* Message Abort*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecPollingMessage( )
++    \brief This message is used by any device for device discovery - similar to
++           ping in other protocols
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecPollingMessage
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[3] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Polling Message command */
++  I2c_Buffer[0] = 0x03;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,3); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 1;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = 0;
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRecordStatus( )
++    \brief This message is used by a recording device to inform the initiator
++           of the message <Record On> about its status.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECRecordStatusInfo_t  RecordStatusInfo \n
++           The recording status of the device.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordStatus
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress,
++   tmdlHdmiCECRecordStatusInfo_t  RecordStatusInfo
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Record Status command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++ /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_RECORD_STATUS ;    /* Record Status */
++  I2c_Buffer[4] = RecordStatusInfo; /* Record Status */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRecordOff( )
++    \brief This message request a device to stop a recording
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOff
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Record Off command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_RECORD_OFF ;   /* Record Off */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRecordOnAnalogueService( )
++    \brief This message attempt to record analogue source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n
++
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnAnalogueService
++(
++   tmInstance_t                        Instance,
++   UInt8                               ReceiverLogicalAddress,
++   tmdlHdmiCECAnalogueBroadcastType_t  AnalogueBroadcastType,
++   UInt16                              AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t        BroadcastSystem
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[9] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Record On Analogue Device command */
++  I2c_Buffer[0] = 0x09;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_RECORD_ON ;                     /*Record On*/
++
++  I2c_Buffer[4] = CEC_RECORD_SOURCE_ANALOGUE_SERVICE;        /*RecordSourceType = CEC_RECORD_SOURCE_ANALOGUE_SERVICE*/
++  I2c_Buffer[5] = AnalogueBroadcastType;                     /*Analogue Brodcast Type*/
++  I2c_Buffer[6] = (unsigned char)(AnalogueFrequency >> 8);   /*Analogue Frequency*/
++  I2c_Buffer[7] = (unsigned char)AnalogueFrequency;
++  I2c_Buffer[8] = BroadcastSystem;                           /*Brodcast System*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,9); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRecordOnDigitalService( )
++    \brief This message attempt to record digital source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnDigitalService
++(
++   tmInstance_t                              Instance,
++   UInt8                                     ReceiverLogicalAddress,
++   tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[12] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  tmdlHdmiCECAribData_t *pARIB_Pointer;
++  tmdlHdmiCECAtscData_t *pATSC_Pointer;
++  tmdlHdmiCECDvbData_t  *pDVB_Pointer;
++
++  unsigned char Regval;                 /* Local variable*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Record On Digital Service command */
++  I2c_Buffer[0] = 0x0C;     /* Param number = 10*/
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_RECORD_ON ;                  /* Record On Digital Service*/
++
++  I2c_Buffer[4] = CEC_RECORD_SOURCE_DIGITAL_SERVICE;     /* RecordSourceType = CEC_RECORD_SOURCE_DIGITAL_SERVICE */
++
++  /* Digital Service Identification*/
++  /*Merge Service Method and Digital Broadcast System in the same Byte*/
++  Regval = (unsigned char)(pServiceIdentification->ServiceIdentificationMethod & 0x01); /*bit 7 is Service Method*/
++  Regval = Regval << 7;
++  Regval |= (unsigned char)(pServiceIdentification->DigitalBroadcastSystem & 0x7F);     /*bits 6 to 0 are Digital Broadcast*/
++  I2c_Buffer[5] = Regval;
++
++  /*Case of a ARIB Generic*/
++  if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ARIB_GENERIC)
++    {
++        pARIB_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[6] = (unsigned char)(pARIB_Pointer->TransportStreamID >> 8);
++        I2c_Buffer[7] = (unsigned char)pARIB_Pointer->TransportStreamID;
++        I2c_Buffer[8] = (unsigned char)(pARIB_Pointer->ServiceID >> 8);
++        I2c_Buffer[9] = (unsigned char)pARIB_Pointer->ServiceID;
++        I2c_Buffer[10] = (unsigned char)(pARIB_Pointer->OriginalNetworkID >> 8);
++        I2c_Buffer[11] = (unsigned char)pARIB_Pointer->OriginalNetworkID;
++    }
++    /*Case of a ATSC Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ATSC_GENERIC)
++    {
++        pATSC_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[6] = (unsigned char)(pATSC_Pointer->TransportStreamID >> 8);
++        I2c_Buffer[7] = (unsigned char)pATSC_Pointer->TransportStreamID;
++        I2c_Buffer[8] = (unsigned char)(pATSC_Pointer->ProgramNumber >> 8);
++        I2c_Buffer[9] = (unsigned char)pATSC_Pointer->ProgramNumber;
++        I2c_Buffer[10] = (unsigned char)(pATSC_Pointer->Reserved >> 8);
++        I2c_Buffer[11] = (unsigned char)pATSC_Pointer->Reserved;
++    }
++    /*Case of a DVB Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_DVB_GENERIC)
++    {
++        pDVB_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[6] = (unsigned char)(pDVB_Pointer->TransportStreamID >> 8);
++        I2c_Buffer[7] = (unsigned char)pDVB_Pointer->TransportStreamID;
++        I2c_Buffer[8] = (unsigned char)(pDVB_Pointer->ServiceID >> 8);
++        I2c_Buffer[9] = (unsigned char)pDVB_Pointer->ServiceID;
++        I2c_Buffer[10] = (unsigned char)(pDVB_Pointer->OriginalNetworkID >> 8);
++        I2c_Buffer[11] = (unsigned char)pDVB_Pointer->OriginalNetworkID;
++    }
++    /*other cases, Buffer are empty*/
++  else
++    {
++        I2c_Buffer[6] = 0xFF;
++        I2c_Buffer[7] = 0xFF;
++        I2c_Buffer[8] = 0xFF;
++        I2c_Buffer[9] = 0xFF;
++        I2c_Buffer[10] = 0xFF;
++        I2c_Buffer[11] = 0xFF;
++    }
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,12); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRecordOnExternalPhysicalAddress( )
++    \brief This message attempt to record an external physical address source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress \n
++           Defines the path between the TV an a device-thus giving it a physical
++           address within the cluster.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnExternalPhysicalAddress
++(
++   tmInstance_t                         Instance,
++   UInt8                                ReceiverLogicalAddress,
++   tmdlHdmiCECExternalPhysicalAddress_t ExternalPhysicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[7] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Record On External Physial Address command */
++  I2c_Buffer[0] = 0x07;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_RECORD_ON ;                          /*Record On*/
++  I2c_Buffer[4] = CEC_RECORD_SOURCE_EXTERNAL_PHYSICAL_ADDRESS;    /*RecordSourceType = CEC_RECORD_SOURCE_EXTERNAL_PHYSICAL_ADDRESS*/
++  I2c_Buffer[5] = (unsigned char)(ExternalPhysicalAddress >> 8);  /*External Physical Address*/
++  I2c_Buffer[6] = (unsigned char)ExternalPhysicalAddress;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,7);       /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRecordOnExternalPlug( )
++    \brief This message attempt to record an external plug source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param tmdlHdmiCECExternalPlug_t  ExternalPlug \n
++           indicates external plug number (1 to 255 )on the recording device.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnExternalPlug
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress,
++   tmdlHdmiCECExternalPlug_t      ExternalPlug
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Record On External Plug command */
++  I2c_Buffer[0] = 0x06;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_RECORD_ON ;                   /* Record On*/
++
++  I2c_Buffer[4] = CEC_RECORD_SOURCE_EXTERNAL_PLUG;         /* RecordSourceType = CEC_RECORD_SOURCE_EXTERNAL_PLUG*/
++  I2c_Buffer[5] = ExternalPlug;                            /*External Plug*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecRecordOnOwnSource( )
++    \brief This message attempt to record an external plug source
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8    ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecRecordOnOwnSource
++(
++   tmInstance_t                   Instance,
++   UInt8                          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Record On Own Source command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_RECORD_ON ;                /* Record On*/
++
++  I2c_Buffer[4] = CEC_RECORD_SOURCE_OWN_SOURCE;         /* RecordSourceType = CEC_RECORD_SOURCE_OWN_SOURCE*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecReportPhysicalAddress( )
++    \brief This message is used to inform all other devices of the mapping
++           between physical and logical address of the initiator.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt16 PhysicalAddress \n
++           Device physical address within the cluster. \n
++
++    \param tmdlHdmiCECDeviceType_t DeviceType \n
++           Type of the device (TV, Playback, tuner,...). \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportPhysicalAddress
++(
++   tmInstance_t             Instance,
++   UInt16                   PhysicalAddress,
++   tmdlHdmiCECDeviceType_t  DeviceType
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[7] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Report Physical Address command */
++  I2c_Buffer[0] = 0x07;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= 0x0F;                                                            /* Broadcast*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REPORT_PHYSICAL_ADDRESS ;      /* Report Physical Address */
++  I2c_Buffer[4] = (unsigned char)(PhysicalAddress >> 8);    /* MsByte of Physical Address*/
++  I2c_Buffer[5] = (unsigned char)PhysicalAddress;           /* LsByte of Physical Address */
++
++  I2c_Buffer[6] = DeviceType ;                              /* Device Type*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,7); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetMenuLanguage( )
++    \brief This message is used by a TV or another device to indicate the menu
++           Language.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param const char *pLanguage \n
++           Pointer on the user's menu language choice. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetMenuLanguage
++(
++   tmInstance_t Instance,
++   const char   *pLanguage
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[7] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++ // RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set Menu Language command */
++  I2c_Buffer[0] = 0x07;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= 0x0F;                                                            /* Broadcast*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_MENU_LANGUAGE ;        /* Set Menu Language*/
++  I2c_Buffer[4] = pLanguage[0];     /* First Tocken*/
++  I2c_Buffer[5] = pLanguage[1];
++  I2c_Buffer[6] = pLanguage[2];     /* Last Tocken*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,7); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecDeckControl()
++    \brief This message is used to conrol a device's media functions
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECDecControlMode_t DeckControlMode \n
++           Used in message <Deck Control>\n
++
++    \note  The "Skip Forward / Wind" and "Skip Reverse / Rewind" values are
++           used for example in a DVD as next xhapter and previous chapter and
++           in a VCR as wind and rewind. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecDeckControl
++(
++   tmInstance_t                Instance,
++   UInt8                       ReceiverLogicalAddress,
++   tmdlHdmiCECDecControlMode_t DeckControlMode
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if Instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to Instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if Instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Deck Control command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_DESCK_CONTROL;     /* Deck Control Mode*/
++  I2c_Buffer[4] = DeckControlMode;      /* Deck Control Value*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecDeckStatus()
++    \brief This message is used to provide a deck's status to the initiator
++           of the <Give Deck Status> message
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECDecInfo_t DeckInfo \n
++           Information on the device's current status \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecDeckStatus
++(
++   tmInstance_t         Instance,
++   UInt8                ReceiverLogicalAddress,
++   tmdlHdmiCECDecInfo_t DeckInfo
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Deck Status command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_DECK_STATUS;       /* Deck Status*/
++  I2c_Buffer[4] = DeckInfo;     /* Deck Status Mode Information*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGiveDeckStatus( )
++    \brief This message is used to request the status of a device regardless
++           of whether or not it is the current active source.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECStatusRequest_t StatusRequest \n
++           Allows the initiator to request the status once or on all future state
++           change. Or to cancel a previous <Give Deck Status > ["On"] request. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveDeckStatus
++(
++   tmInstance_t               Instance,
++   UInt8                      ReceiverLogicalAddress,
++   tmdlHdmiCECStatusRequest_t StatusRequest
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if Instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Give Deck Status command */
++  I2c_Buffer[0] = 0x05;    /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GIVE_DECK_STATUS;      /* Give Deck Status*/
++  I2c_Buffer[4] = StatusRequest;        /* Deck Status Request Information*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecPlay( )
++    \brief This message is used to control the playback behaviour of a source
++           device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECPlayMode_t  PlayMode \n
++           In which mode to play media. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecPlay
++(
++   tmInstance_t           Instance,
++   UInt8                  ReceiverLogicalAddress,
++   tmdlHdmiCECPlayMode_t  PlayMode
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Play command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_PLAY;  /* Play*/
++  I2c_Buffer[4] = (unsigned char)PlayMode;          /* Play Mode Information Information*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSelectDigitalService( )
++    \brief This message select directly a digital TV, Radio or Data Broadcast
++           Service.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSelectDigitalService
++(
++   tmInstance_t                                Instance,
++   UInt8                                       ReceiverLogicalAddress,
++   ptmdlHdmiCECDigitalServiceIdentification_t  pServiceIdentification
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[11] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  tmdlHdmiCECAribData_t *pARIB_Pointer;
++  tmdlHdmiCECAtscData_t *pATSC_Pointer;
++  tmdlHdmiCECDvbData_t  *pDVB_Pointer;
++
++  unsigned char Regval;                 /*Local Variable*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Select Digital Service command */
++  I2c_Buffer[0] = 0x0B;     /* Param number = 10*/
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_DIGITAL_SERVICE ;      /* Select Digital Service*/
++
++  /*Merge Service Method and Digital Broadcast System in the same Byte*/
++  Regval = (unsigned char)(pServiceIdentification->ServiceIdentificationMethod & 0x01); /* Load the 1 bit of Service Method*/
++  Regval = Regval << 7;
++  Regval |= (unsigned char)(pServiceIdentification->DigitalBroadcastSystem & 0x7F);     /*Merge with the 7 bits of Digital Broadcast*/
++  I2c_Buffer[4] = Regval;
++
++  /*Case of a ARIB Generic*/
++  if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ARIB_GENERIC)
++    {
++        pARIB_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[5] = (unsigned char)(pARIB_Pointer->TransportStreamID >> 8);     /* Service Identification */
++        I2c_Buffer[6] = (unsigned char)pARIB_Pointer->TransportStreamID;
++        I2c_Buffer[7] = (unsigned char)(pARIB_Pointer->ServiceID >> 8);
++        I2c_Buffer[8] = (unsigned char)pARIB_Pointer->ServiceID;
++        I2c_Buffer[9] = (unsigned char)(pARIB_Pointer->OriginalNetworkID >> 8);
++        I2c_Buffer[10] = (unsigned char)pARIB_Pointer->OriginalNetworkID;
++    }
++    /*Case of a ATSC Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ATSC_GENERIC)
++    {
++        pATSC_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[5] = (unsigned char)(pATSC_Pointer->TransportStreamID >> 8);     /* Service Identification */
++        I2c_Buffer[6] = (unsigned char)pATSC_Pointer->TransportStreamID;
++        I2c_Buffer[7] = (unsigned char)(pATSC_Pointer->ProgramNumber >> 8);
++        I2c_Buffer[8] = (unsigned char)pATSC_Pointer->ProgramNumber;
++        I2c_Buffer[9] = (unsigned char)(pATSC_Pointer->Reserved >> 8);
++        I2c_Buffer[10] = (unsigned char)pATSC_Pointer->Reserved;
++    }
++    /*Case of a DVB Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_DVB_GENERIC)
++    {
++        pDVB_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[5] = (unsigned char)(pDVB_Pointer->TransportStreamID >> 8);      /* Service Identification */
++        I2c_Buffer[6] = (unsigned char)pDVB_Pointer->TransportStreamID;
++        I2c_Buffer[7] = (unsigned char)(pDVB_Pointer->ServiceID >> 8);
++        I2c_Buffer[8] = (unsigned char)pDVB_Pointer->ServiceID;
++        I2c_Buffer[9] = (unsigned char)(pDVB_Pointer->OriginalNetworkID >> 8);
++        I2c_Buffer[10] = (unsigned char)pDVB_Pointer->OriginalNetworkID;
++    }
++    /*other cases, Buffer are empty*/
++  else
++    {
++        I2c_Buffer[5] = 0xFF;       /* Service Identification */
++        I2c_Buffer[6] = 0xFF;
++        I2c_Buffer[7] = 0xFF;
++        I2c_Buffer[8] = 0xFF;
++        I2c_Buffer[9] = 0xFF;
++        I2c_Buffer[10] = 0xFF;
++    }
++	errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,11); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetAnalogueTimer( )
++    \brief This message is used to set asingle timer block on an analogue
++           recording device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++
++    \param tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType \n
++           "Cable,Sattellite,Terrestrial".\n
++
++    \param UInt16 AnalogueFrequency \n
++           Specify frequency used by analogue tuner (0x0000<=N<=0xFFFF).\n
++
++    \param tmdlHdmiCECBroadcastSystem_t BroadcastSystem \n
++           Specify information about the colour system, the sound carrier and
++           the IF-frequency.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetAnalogueTimer
++(
++   tmInstance_t                        Instance,
++   UInt8                               ReceiverLogicalAddress,
++   UInt8                               DayOfMonth,
++   UInt8                               MonthOfYear,
++   UInt16                              StartTime,
++   tmdlHdmiCECDuration_t              *pDuration,
++   UInt8                               RecordingSequence,
++   tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType,
++   UInt16                              AnalogueFrequency,
++   tmdlHdmiCECBroadcastSystem_t       BroadcastSystem
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[15] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set Analogue Timer command */
++  I2c_Buffer[0] = 0x0F;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_ANALOGUE_TIMER ;   /* Message Abort*/
++  I2c_Buffer[4] = DayOfMonth;
++  I2c_Buffer[5] = MonthOfYear;
++  I2c_Buffer[6] = (unsigned char)(StartTime >> 8);
++  I2c_Buffer[7] = (unsigned char)StartTime;
++  I2c_Buffer[8] = pDuration -> Hours;
++  I2c_Buffer[9] = pDuration -> Minute;
++  I2c_Buffer[10] = RecordingSequence;
++  I2c_Buffer[11] = AnalogueBroadcastType;
++  I2c_Buffer[12] = (unsigned char)(AnalogueFrequency >> 8);
++  I2c_Buffer[13] = (unsigned char)AnalogueFrequency;
++  I2c_Buffer[14] = BroadcastSystem;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,15); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetAudioRate( )
++    \brief This message is used to control audio rate from Source device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECAudioRate_t AudioRate \n
++           The audio rate requested. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetAudioRate
++(
++   tmInstance_t           Instance,
++   UInt8                  ReceiverLogicalAddress,
++   tmdlHdmiCECAudioRate_t AudioRate
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set Audio Rate command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_AUDIO_RATE ;   /* Set Audio Rate */
++  I2c_Buffer[4] = AudioRate;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetDigitalTimer( )
++    \brief This message is used to set a digital timer block on a digital
++           recording device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 ReceiverLogicalAddress \n
++           Address of message receiver. \n
++
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++
++    \param tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification \n
++           Pointer to the structure Digital Service Identification
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetDigitalTimer
++(
++   tmInstance_t                               Instance,
++    UInt8                                     ReceiverLogicalAddress,
++   UInt8                                      DayOfMonth,
++   UInt8                                      MonthOfYear,
++   UInt16                                     StartTime,
++   tmdlHdmiCECDuration_t                     *pDuration,
++   UInt8                                      RecordingSequence,
++   tmdlHdmiCECDigitalServiceIdentification_t *pServiceIdentification
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[18] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  tmdlHdmiCECAribData_t *pARIB_Pointer;
++  tmdlHdmiCECAtscData_t *pATSC_Pointer;
++  tmdlHdmiCECDvbData_t  *pDVB_Pointer;
++
++  unsigned char Regval;                 /* Local variable*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set Digital Timer command */
++  I2c_Buffer[0] = 0x12;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_DIGITAL_TIMER ;        /* Set Digital Timer*/
++  I2c_Buffer[4] = DayOfMonth;                           /* Day of Month*/
++  I2c_Buffer[5] = MonthOfYear;                          /* Month of Year*/
++  I2c_Buffer[6] = (unsigned char)(StartTime >> 8);      /* Start Time*/
++  I2c_Buffer[7] = (unsigned char)StartTime;
++  I2c_Buffer[8] = pDuration -> Hours;                   /* Duration Hours*/
++  I2c_Buffer[9] = pDuration -> Minute;                  /* Duration Minute*/
++  I2c_Buffer[10] = RecordingSequence;                   /*Recording Sequence*/
++
++  /* Digital service Identification*/
++  /*Merge Service Method and Digital Broadcast System in the same Byte*/
++  Regval = (unsigned char)(pServiceIdentification->ServiceIdentificationMethod & 0x01); /*bit 7 is Service Method*/
++  Regval = Regval << 7;
++  Regval |= (unsigned char)(pServiceIdentification->DigitalBroadcastSystem & 0x7F);     /*bits 6 to 0 are Digital Broadcast*/
++  I2c_Buffer[11] = Regval;
++
++  /*Case of a ARIB Generic*/
++  if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ARIB_GENERIC)
++    {
++        pARIB_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[12] = (unsigned char)(pARIB_Pointer->TransportStreamID >> 8);
++        I2c_Buffer[13] = (unsigned char)pARIB_Pointer->TransportStreamID;
++        I2c_Buffer[14] = (unsigned char)(pARIB_Pointer->ServiceID >> 8);
++        I2c_Buffer[15] = (unsigned char)pARIB_Pointer->ServiceID;
++        I2c_Buffer[16] = (unsigned char)(pARIB_Pointer->OriginalNetworkID >> 8);
++        I2c_Buffer[17] = (unsigned char)pARIB_Pointer->OriginalNetworkID;
++    }
++    /*Case of a ATSC Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_ATSC_GENERIC)
++    {
++        pATSC_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[12] = (unsigned char)(pATSC_Pointer->TransportStreamID >> 8);
++        I2c_Buffer[13] = (unsigned char)pATSC_Pointer->TransportStreamID;
++        I2c_Buffer[14] = (unsigned char)(pATSC_Pointer->ProgramNumber >> 8);
++        I2c_Buffer[15] = (unsigned char)pATSC_Pointer->ProgramNumber;
++        I2c_Buffer[16] = (unsigned char)(pATSC_Pointer->Reserved >> 8);
++        I2c_Buffer[17] = (unsigned char)pATSC_Pointer->Reserved;
++    }
++    /*Case of a DVB Generic*/
++  else if(pServiceIdentification->DigitalBroadcastSystem == CEC_DIGITAL_BROADCAST_SYSTEM_DVB_GENERIC)
++    {
++        pDVB_Pointer = pServiceIdentification->pServiceIdentification;
++
++        I2c_Buffer[12] = (unsigned char)(pDVB_Pointer->TransportStreamID >> 8);
++        I2c_Buffer[13] = (unsigned char)pDVB_Pointer->TransportStreamID;
++        I2c_Buffer[14] = (unsigned char)(pDVB_Pointer->ServiceID >> 8);
++        I2c_Buffer[15] = (unsigned char)pDVB_Pointer->ServiceID;
++        I2c_Buffer[16] = (unsigned char)(pDVB_Pointer->OriginalNetworkID >> 8);
++        I2c_Buffer[17] = (unsigned char)pDVB_Pointer->OriginalNetworkID;
++    }
++    /*other cases, Buffer are empty*/
++  else
++    {
++        I2c_Buffer[12] = 0xFF;
++        I2c_Buffer[13] = 0xFF;
++        I2c_Buffer[14] = 0xFF;
++        I2c_Buffer[15] = 0xFF;
++        I2c_Buffer[16] = 0xFF;
++        I2c_Buffer[17] = 0xFF;
++    }
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,18); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetExternalTimerWithExternalPlug( )
++    \brief This message is used to set a single timer block to record from an
++           external device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++
++    \param tmdlHdmiCECExternalPlug_t  ExternalPlug \n
++           indicates external plug number (1 to 255 )on the recording device.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetExternalTimerWithExternalPlug
++(
++   tmInstance_t                Instance,
++   UInt8                       ReceiverLogicalAddress,
++   UInt8                       DayOfMonth,
++   UInt8                       MonthOfYear,
++   UInt16                      StartTime,
++   tmdlHdmiCECDuration_t      *pDuration,
++   UInt8                       RecordingSequence,
++   tmdlHdmiCECExternalPlug_t  ExternalPlug
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[13] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set External Timer With External Plug command */
++  I2c_Buffer[0] = 0x0D;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_EXTERNAL_TIMER ;   /*SetDigital Timer*/
++
++  I2c_Buffer[4] = DayOfMonth;                       /*Day of Month*/
++  I2c_Buffer[5] = MonthOfYear;                      /*Month of Year*/
++  I2c_Buffer[6] = (unsigned char)(StartTime >> 8);  /*Start Time*/
++  I2c_Buffer[7] = (unsigned char)StartTime;
++  I2c_Buffer[8] = pDuration -> Hours;               /*Duration Hours*/
++  I2c_Buffer[9] = pDuration -> Minute;              /*Duration Minute*/
++  I2c_Buffer[10] = RecordingSequence;               /*Recording Sequence*/
++  I2c_Buffer[11] = CEC_EXTERNAL_PLUG;               /*External Source Specifier = External Plug */
++  I2c_Buffer[12] = ExternalPlug;                    /*External Plug*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,13); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetExternalTimerWithPhysicalAddress( )
++    \brief This message is used to set a single timer block to record from an
++           external device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8  DayOfMonth \n
++           Day of the month.\n
++
++    \param UInt8  MonthOfYear \n
++           Month of the year.\n
++
++    \param UInt16 StartTime \n
++           Start time for a timer based recording.\n
++
++    \param UInt16 Duration \n
++           Pointer to the structure tmdlHdmiCECDuration_t in BCD format.\n
++
++    \param UInt8 Recording Sequence \n
++           Indicates if recording is repeated and, if so, on which day
++           For repeated recording the recording sequence value is the
++           bitwise OR of the days when recordings are required
++           Shall be set to 0x00 when recording is not repeated.\n
++
++    \param tmdlHdmiCECExternalPhysicalAddress_t  PhysicalAddress \n
++           Defines the path between the TV an a device-thus giving it a physical
++           address within the cluster.\n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetExternalTimerWithPhysicalAddress
++(
++   tmInstance_t                           Instance,
++   UInt8                                  ReceiverLogicalAddress,
++   UInt8                                  DayOfMonth,
++   UInt8                                  MonthOfYear,
++   UInt16                                 StartTime,
++   tmdlHdmiCECDuration_t                 *pDuration,
++   UInt8                                  RecordingSequence,
++   tmdlHdmiCECExternalPhysicalAddress_t  ExternalPhysicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[14] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set external Timer With External Physical Address command */
++  I2c_Buffer[0] = 0x0E;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_EXTERNAL_TIMER ;   /* SetDigital Timer*/
++
++  I2c_Buffer[4] = DayOfMonth;                       /* Day of Month*/
++  I2c_Buffer[5] = MonthOfYear;                      /* Month of Year*/
++  I2c_Buffer[6] = (unsigned char)(StartTime >> 8);  /* Start Time*/
++  I2c_Buffer[7] = (unsigned char)StartTime;
++  I2c_Buffer[8] = pDuration -> Hours;               /* Duration Hours*/
++  I2c_Buffer[9] = pDuration -> Minute;              /* Duration Minute*/
++  I2c_Buffer[10] = RecordingSequence;               /* Recording Sequence*/
++  I2c_Buffer[11] = CEC_EXTERNAL_PHYSICAL_ADDRESS;   /*External Source Specifier = External Address*/
++  I2c_Buffer[12] = (unsigned char)(ExternalPhysicalAddress >> 8);  /*External Address*/
++  I2c_Buffer[13] = (unsigned char) ExternalPhysicalAddress;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,14); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecTunerStepDecrement( )
++    \brief This message is used to tune to next lowest service in a tuner's
++           service list.Can be used for PIP.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTunerStepDecrement
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Tuner Step Decrement command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_TUNER_STEP_DECREMENT ;         /* Tuner Step Decrement*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecTunerStepIncrement( )
++    \brief This message is used to tune to next highest service in a tuner's
++           service list.Can be used for PIP.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecTunerStepIncrement
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Tuner Step Increment command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_TUNER_STEP_INCREMENT ;     /* Tuner Step Increment*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecDeviceVendorID()
++    \brief This message report the vendor ID of this device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt32 VendorID \n
++           Indentifier for a specific Vendor \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecDeviceVendorID
++(
++   tmInstance_t Instance,
++   UInt32       VendorID
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[7] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Device Vendor ID command */
++  I2c_Buffer[0] = 0x07;     /* Param number in case of Vendor ID is 32 Bytes*/
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= 0x0F;                                                            /* Broadcast*/
++
++  I2c_Buffer[3] = CEC_OPCODE_DEVICE_VENDOR_ID ;     /* Device Vendor ID opcode = 0x87*/
++  I2c_Buffer[4] = (unsigned char)(VendorID >> 16);  /* MSByte of Vendor ID*/
++  I2c_Buffer[5] = (unsigned char)(VendorID >> 8);
++  I2c_Buffer[6] = (unsigned char)VendorID;          /* LSByte of Vendor ID*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,7); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGiveDeviceVendorID( )
++    \brief This message is request the vendor ID from a device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveDeviceVendorID
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Give Device Vendor ID command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GIVE_DEVICE_VENDOR_ID ;        /* Give Device Vendor*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecVendorCommand( )
++    \brief This message is allows vendor specific commands to be sent between
++           two devices.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8  *pVendorSpecificData \n
++           Pointer to the Vendor Specific datas
++
++    \param UInt8    VendorSpecificDataLength \n
++           Length of VendorSpecificData. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVendorCommand
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress,
++   UInt8         *pVendorSpecificData,
++   UInt8         VendorSpecificDataLength
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[19] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  unsigned char loci;                   /* Local increment variable*/
++  unsigned char MessLength;             /* Local Message length*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Vendor Command command */
++  MessLength = VendorSpecificDataLength + 4;       /* Calculate Message length*/
++
++  I2c_Buffer[0] = MessLength;                    /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_VENDOR_COMMAND ;       /* Vendor Command*/
++
++  for(loci = 0; loci <= VendorSpecificDataLength ; loci++)
++    {
++        I2c_Buffer[(loci+7)] = pVendorSpecificData[loci];    /* Fill Table with vendorSpecific Data characters*/
++    }
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,MessLength); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecVendorCommandWithID( )
++    \brief This message is allows vendor specific commands to be sent between
++           two devices or broadcast.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt32 VendorID \n
++           Indentifier for a specific Vendor \n
++
++    \param UInt8  *pVendorSpecificData \n
++           Pointer to the Vendor Specific datas
++
++    \param UInt8    VendorSpecificDataLength \n
++           Length of VendorSpecificData. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVendorCommandWithID
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress,
++   UInt32        VendorID,
++   UInt8         *pVendorSpecificData,
++   UInt8         VendorSpecificDataLength
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[19] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  unsigned char loci;                   /* Local increment variable*/
++  unsigned char MessLength;             /* Local Message length*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Vendor Command With ID command */
++   MessLength = VendorSpecificDataLength + 7;       /* Calculate Message length*/
++
++  I2c_Buffer[0] = MessLength;                      /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_VENDOR_COMMAND_WITH_ID ;       /* Vendor Command*/
++  I2c_Buffer[4] = (unsigned char)(VendorID >> 16);  /* MSByte of Vendor ID*/
++  I2c_Buffer[5] = (unsigned char)(VendorID >> 8);
++  I2c_Buffer[6] = (unsigned char)VendorID;          /* LSByte of Vendor ID*/
++
++  for(loci = 0; loci <= VendorSpecificDataLength ; loci++)
++  {
++     I2c_Buffer[(loci+7)] = pVendorSpecificData[loci];    /* Fill Table with vendorSpecific Data characters*/
++  }
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,MessLength); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecVendorRemoteButtonDown( )
++    \brief This message indicates that a remote control button has been depressed.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8  *pVendorSpecificRcCode \n
++           Pointer to the Vendor Specific remote control code.
++           its recommended t keep this to a minimum size.
++           The maximum length shall not exceed 14 data blocks to avoid saturating bus
++
++    \param UInt8    VendorSpecificRcCodeLength \n
++           Length of VendorSpecificRcCode. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVendorRemoteButtonDown
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress,
++   UInt8         *pVendorSpecificRcCode,
++   UInt8         VendorSpecificRcCodeLength
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[19] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  unsigned char loci;                   /* Local increment variable*/
++  unsigned char MessLength;             /* Local Message length*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  /* Vendor Remote Button Down command */
++  MessLength = VendorSpecificRcCodeLength + 4;         /* Calculate Message length*/
++
++  I2c_Buffer[0] = MessLength;                       /* Message Length */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN ;    /* Vendor Remote Button Down Opcode*/
++  /*Vendor Specific RC code Parameter*/
++  for(loci = 0; loci <= VendorSpecificRcCodeLength ; loci++)
++    {
++        I2c_Buffer[(loci+4)] = pVendorSpecificRcCode[loci];   /* Fill Table with Vendor Specific RC Code data*/
++    }
++  /*Send message Via I2C*/
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,MessLength);
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecVendorRemoteButtonUp( )
++    \brief This message indicates that a remote control button (the last button
++           pressed indicated by the <Vendor remote button down > message) has
++           been released.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecVendorRemoteButtonUp
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Vendor Remote Button Up command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP ;      /* Vendor Remote Button Up*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetOsdString( )
++    \brief This message is used to send a test message to output on a TV.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECDisplayControl_t DisplayControl \n
++           Display timing. \n
++
++    \param const char *pOsdString \n
++           Pointer on the Text to display. \n
++
++    \param UInt8    OsdStringLength \n
++           Length of Osd String. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetOsdString
++(
++   tmInstance_t                 Instance,
++   UInt8                        ReceiverLogicalAddress,
++   tmdlHdmiCECDisplayControl_t  DisplayControl,
++   const char                   *pOsdString,
++   UInt8                        OsdStringLength
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[19] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  unsigned char loci;                   /* Local increment variable*/
++  unsigned char MessLength;             /* Local Message length*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set OSD String command */
++
++  MessLength = OsdStringLength+5;                   /* Calculate Message length*/
++
++  I2c_Buffer[0] = (unsigned char)MessLength;
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_OSD_STRING ;       /* Set Osd String*/
++  I2c_Buffer[4] = DisplayControl;                   /*Display Control*/
++   for(loci = 0; loci <= OsdStringLength ; loci++)
++    {
++        I2c_Buffer[(loci+5)] = pOsdString[loci];         /* Fill Table with OSD Name characters*/
++    }
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,(MessLength)); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGiveOsdName( )
++    \brief This message is used to request preferred OSD name of a device
++           for use in menus associated with that device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveOsdName
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Give OSD Name command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GIVE_OSD_NAME ;    /* Give OSD Name*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetOsdName( )
++    \brief This message is used to set the preferred OSD name of a device
++           for use in manus associated with that device.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param const char *pOsdName \n
++           Pointer on the preferred name of the device. \n
++
++    \param UInt8    OsdNameLength \n
++           Length of Osd Name String. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetOsdName
++(
++   tmInstance_t Instance,
++   UInt8        ReceiverLogicalAddress,
++   const char   *pOsdName,
++   UInt8        OsdNameLength
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[19] ;       /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++  unsigned char loci;                   /* Local increment variable*/
++  unsigned char MessLength;             /* Local Message length*/
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Set OSD Name command */
++
++  MessLength = OsdNameLength+4;                         /* Calculate Message length*/
++
++  I2c_Buffer[0] = (unsigned char)MessLength;
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_SET_OSD_NAME ;     /* Set Osd Name*/
++    for(loci = 0; loci <= OsdNameLength ; loci++)
++    {
++        I2c_Buffer[(loci+4)] = pOsdName[loci];       /* Fill Table with OSD Name characters*/
++    }
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,(MessLength)); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecMenuRequest( )
++    \brief This message request from the TV for a device to show/remove a
++           menu or to query if a device is currently showing a menu
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECMenuRequestType_t  MenuRequestType \n
++           Indicates if the menu request is to activate or deactivate the
++           devices menu or simply query the devices menu status. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecMenuRequest
++(
++   tmInstance_t                  Instance,
++   UInt8                         ReceiverLogicalAddress,
++   tmdlHdmiCECMenuRequestType_t  MenuRequestType
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Menu Request command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_MENU_REQUEST ;     /* Menu Request*/
++  I2c_Buffer[4] = MenuRequestType;              /*Menu Request Type */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecMenuStatus( )
++    \brief This message is used to indicate to the TV that the device is
++           showing/has removed a menu and requets the remote control keys to
++           be passed though
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECMenuState_t  MenuState \n
++           Indicates if the device is in the 'Device Menu Active' state or
++           'Device Menu Inactive' state. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecMenuStatus
++(
++   tmInstance_t            Instance,
++   UInt8                   ReceiverLogicalAddress,
++   tmdlHdmiCECMenuState_t  MenuState
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Menu Status command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_MENU_STATUS;       /* Menu Status*/
++  I2c_Buffer[4] = MenuState;                    /* Menu State*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecUserControlPressed( )
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECUserRemoteControlCommand_t UICommand \n
++           Relevant UI command issued by user. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressed
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   tmdlHdmiCECUserRemoteControlCommand_t UICommand
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* User Control Pressed command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++  
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++ /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_USER_CONTROL_PRESSED;      /* User Control pressed*/
++  I2c_Buffer[4] = UICommand;                            /* UI Command*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecUserControlPressedPlay( )
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECPlayMode_t PlayMode \n
++           In which mode to play media. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedPlay
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   tmdlHdmiCECPlayMode_t                 PlayMode
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* User Control Presses Play command */
++  I2c_Buffer[0] = 0x06;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_USER_CONTROL_PRESSED;      /* User Control Pressed*/
++
++  I2c_Buffer[4] = CEC_REMOTE_BUTTON_PLAY_FUNCTION;      /* UI Command = CEC_REMOTE_BUTTON_PLAY_FUNCTION */
++  I2c_Buffer[5] = PlayMode;                             /* Play Mode*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecUserControlPressedSelectAudioInput( )
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 SelectAudioInput \n
++           Number of the Audio Input (Audio input number between 1 and 255). \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedSelectAudioInput
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   UInt8                                 SelectAudioInput
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* User Control Pressed Select Audio Input command */
++  I2c_Buffer[0] = 0x06;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_USER_CONTROL_PRESSED;                /* User Control Pressed*/
++
++  I2c_Buffer[4] = CEC_REMOTE_BUTTON_SELECT_AUDIO_INPUT_FUNCTION;  /* UI Command = CEC_REMOTE_BUTTON_SELECT_AUDIO_INPUT_FUNCTION*/
++  I2c_Buffer[5] = SelectAudioInput;                               /* UI Function Select Audio mode*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6);       /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecUserControlPressedSelectAVInput( )
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 SelectAVInput \n
++           Number of the A/V Input (A/V input number between 1 and 255). \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedSelectAVInput
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   UInt8                                 SelectAVInput
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* User Control Pressed Select AV Input command */
++  I2c_Buffer[0] = 0x06;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_USER_CONTROL_PRESSED;             /* User Control Pressed*/
++
++  I2c_Buffer[4] = CEC_REMOTE_BUTTON_SELECT_AV_INPUT_FUNCTION;  /* UI Command = CEC_REMOTE_BUTTON_SELECT_AV_INPUT_FUNCTION */
++  I2c_Buffer[5] = SelectAVInput;                               /* UI Function Select A/V Input*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecUserControlPressedSelectMedia( )
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 SelectMedia \n
++           Number of Media (Media number between 1 and 255). \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedSelectMedia
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   UInt8                                 SelectMedia
++)
++{ 
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* User Control Pressed Select Media command */
++  I2c_Buffer[0] = 0x06;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_USER_CONTROL_PRESSED;          /* User Control Pressed*/
++
++  I2c_Buffer[4] = CEC_REMOTE_BUTTON_SELECT_MEDIA_FUNCTION;  /* UI Command = CEC_REMOTE_BUTTON_SELECT_MEDIA_FUNCTION*/
++  I2c_Buffer[5] = SelectMedia;                              /* UI Function Media*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecUserControlPressedTune( )
++    \brief This message is used to indicate that the user pressed a remote button
++           or switched from one remote control button to another.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECChannelIdentifier_t  *pChannelIdentifier \n
++           Pointer to the structure of Major and Minor Channel number
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlPressedTune
++(
++   tmInstance_t                          Instance,
++   UInt8                                 ReceiverLogicalAddress,
++   tmdlHdmiCECChannelIdentifier_t        *pChannelIdentifier
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[10] ;       /* I2C data buffer */
++  UInt16 Regval16 ;                      /* Local variable used for conversion*/
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* User Control Pressed Tune command */
++  I2c_Buffer[0] = 0x0A;   /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_USER_CONTROL_PRESSED;      /* User Control Pressed Opcode*/
++
++  I2c_Buffer[4] = CEC_REMOTE_BUTTON_TUNE_FUNCTION;      /* UI Command = CEC_REMOTE_BUTTON_TUNE_FUNCTION*/
++
++  /* Merge 6 bits of ChanNum with 10 bits of Major channel*/
++  Regval16 = (UInt16)(pChannelIdentifier->ChanNumFormat & 0x003F); // Save the 6 lsbits
++  Regval16 = Regval16 << 10;
++  Regval16 |= (UInt16)(pChannelIdentifier->MajorChanNumber & 0x03FF);
++
++  /* Load the 4 information bytes of Channel ID*/
++  I2c_Buffer[5] = (unsigned char)(Regval16 >> 8);
++  I2c_Buffer[6] = (unsigned char)Regval16;
++  I2c_Buffer[7] = (unsigned char)(pChannelIdentifier->MinorChanNumber >> 8);
++  I2c_Buffer[8] = (unsigned char)pChannelIdentifier->MinorChanNumber;
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,9); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecUserControlReleased( )
++    \brief This message is used to indicate that the user released a remote button
++           The last one indicated by the <User Control Pressed> Message.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecUserControlReleased
++(
++   tmInstance_t  Instance,
++   UInt8         ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* User Control Released command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++ /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_USER_CONTROL_RELEASED ;        /* User Control Released */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGiveDevicePowerStatus( )
++    \brief This message is used to determine the current power status of a
++           target device
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGiveDevicePowerStatus
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Give Device power Status Power Status command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GIVE_DEVICE_POWER_STATUS ;     /* Give Device Power Status */
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecReportPowerStatus( )
++    \brief This message is used to inform a requesting device of the current
++           power status.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECPowerStatus_t PowerStatus \n
++           Current power status. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecReportPowerStatus
++(
++   tmInstance_t             Instance,
++   UInt8                    ReceiverLogicalAddress,
++   tmdlHdmiCECPowerStatus_t PowerStatus
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[5] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Report Power Status command */
++  I2c_Buffer[0] = 0x05;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++ /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_REPORT_POWER_STATUS ;      /* Report Power Status*/
++  I2c_Buffer[4] = PowerStatus;                          /* Power Status*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,5); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecFeatureAbort()
++    \brief This message is used as a reponse to indicate that the device does
++           not support the requested message type, or that it cannot execute it
++           at the present time.
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param tmdlHdmiCECFeatureOpcode_t FeatureOpcode \n
++           Opcode of the aborted message. \n
++
++    \param tmdlHdmiCECAbortReason_t   AbortReason \n
++           The reason why message cannot respond. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecFeatureAbort
++(
++   tmInstance_t               Instance,
++   UInt8                      ReceiverLogicalAddress,
++   tmdlHdmiCECFeatureOpcode_t FeatureOpcode,
++   tmdlHdmiCECAbortReason_t   AbortReason
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[6] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Feature Abort command */
++  I2c_Buffer[0] = 0x06;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_FEATURE_ABORT ;    /* Feature Abort*/
++  I2c_Buffer[4] = FeatureOpcode;    /* Feature Opcode*/
++  I2c_Buffer[5] = AbortReason;      /* Abort Reason*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,6); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGetCecVersion( )
++    \brief This message is used by a device to enquire which version of CEC
++           the target supports
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetCecVersion
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* Get CEC Version command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_GET_CEC_VERSION ;  /* Get CEC Version*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecAbortMessage( )
++    \brief This message is reserved for testing purposes
++
++    \param tmInstance_t Instance \n
++           Instance identifier. \n
++
++    \param UInt8 ReceiverLogicalAddress\n
++           Address of message receiver. \n
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecAbortMessage
++(
++   tmInstance_t   Instance,
++   UInt8          ReceiverLogicalAddress
++)
++{
++  tmErrorCode_t  errCode;
++  unsigned char  I2c_Buffer[4] ;        /* I2C data buffer */
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((Instance < 0) || (Instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[Instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++  /* check if instance state is correct */
++  //RETIF(UnitTable[Instance].state != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[Instance];
++
++  //======To do : make a prepare message function with parameter
++  /* CEC Abort Message command */
++  I2c_Buffer[0] = 0x04;     /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[Instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= ReceiverLogicalAddress & 0x0F;                                   /* Receiver logical Address*/
++
++  I2c_Buffer[3] = CEC_OPCODE_ABORT_MESSAGE ;    /* Message Abort*/
++
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,4); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = I2c_Buffer[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = I2c_Buffer[3];
++
++  return(TM_OK);
++}
++
++//Non Functional function used to provide easy way to access register 
++
++//==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecGetRegister( )
++    \brief Setup the instance with its configuration parameters. This function
++           allows basic instance configuration for CEC Stack Processor.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure containing all setup parameters
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++unsigned char tmdlHdmiCecGetRegister
++(
++    tmInstance_t               instance,
++    UInt32                     offset
++)
++{
++    tmErrorCode_t                  errCode;
++	tmdlHdmiCecDriverConfigTable_t *pDis;     /* Pointer to Device Instance Structure */
++    unsigned char               I2c_ReadBuffer[1];
++
++
++    /* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), 0xFF)
++
++    /* check if unit corresponding to instance is opened */
++    RETIF(UnitTable[instance].opened == False, 0xFF)
++
++    /* Ckeck the state */
++    //RETIF(UnitTable[instance].state != CEC_STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++    pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++
++    errCode = getCecHwRegisters(pDis, (UInt8) offset,I2c_ReadBuffer,1);
++    RETIF(errCode != TM_OK, 0xff)
++
++    return(I2c_ReadBuffer[0]);
++}
++
++//QB 10 Jan ==========================================================================
++/*!
++    \fn tmErrorCode_t tmdlHdmiCecSetRegister( )
++    \brief Setup the instance with its configuration parameters. This function
++           allows basic instance configuration for CEC Stack Processor.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure containing all setup parameters
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetRegister
++(
++    tmInstance_t                instance,
++    UInt32                      offset,
++    UInt32                      value
++)
++{
++    tmErrorCode_t                  errCode;
++    tmdlHdmiCecDriverConfigTable_t *pDis;     /* Pointer to Device Instance Structure */
++
++
++    /* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++    /* check if unit corresponding to instance is opened */
++    RETIF(UnitTable[instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++
++    /* Ckeck the state */
++    //RETIF(UnitTable[instance].state != CEC_STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMICEC_INVALID_STATE)
++
++        pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++
++    errCode = setCecHwRegister(pDis, (UInt8) offset,(UInt8)value);
++    RETIF(errCode != TM_OK, errCode)
++
++    return(TM_OK);
++}
++
++
++
++//==========================================================================
++/*!
++    \brief Set the power state of an instance of the CEC device. ON
++           state corresponds to a fully supplied, up and running device. Other
++           modes correspond to the powerdown state of the device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++
++    \param instance   Instance identifier.
++    \param powerState Power state to set.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSetPowerState
++(
++    tmInstance_t   instance,
++    tmPowerState_t powerState
++)
++{
++    tmErrorCode_t errCode = TM_OK;
++
++#ifdef TMFL_TDA9989
++    unsigned char I2c_ReadBuffer[1];
++
++    tmdlHdmiCecDriverConfigTable_t *pDis;
++
++    pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++
++    /* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++    if (powerState == tmPowerOn) {
++  
++	errCode = getCecHwRegisters(pDis, E_REG_ENAMODS,I2c_ReadBuffer,1);
++        RETIF(errCode != TM_OK, errCode)
++
++	I2c_ReadBuffer[0] |= DEFAULT_ENAMODS;
++
++        errCode = setCecHwRegister(pDis, E_REG_ENAMODS, I2c_ReadBuffer[0]);
++	RETIF(errCode != TM_OK, errCode)
++
++
++    }
++    else if (powerState == tmPowerStandby) {
++
++	errCode = getCecHwRegisters(pDis, E_REG_ENAMODS,I2c_ReadBuffer,1);
++        RETIF(errCode != TM_OK, errCode)
++
++        I2c_ReadBuffer[0] &=  ~(DEFAULT_ENAMODS);
++
++        errCode = setCecHwRegister(pDis, E_REG_ENAMODS, I2c_ReadBuffer[0]);
++	RETIF(errCode != TM_OK, errCode)
++
++        UnitTable[instance].state = CEC_STATE_NOT_INITIALIZED;
++
++    }
++    else {
++        return TMDL_ERR_DLHDMICEC_BAD_PARAMETER;
++    }
++
++#endif  /*  TMFL_TDA9989 */
++
++    return errCode;
++}
++
++
++//==========================================================================
++/*!
++    \brief Get the power state of an instance of the CEC device. ON
++           state corresponds to a fully supplied, up and running device. Other
++           modes correspond to the powerdown state of the device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance    Instance identifier.
++    \param pPowerState Pointer to the power state.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecGetPowerState
++(
++    tmInstance_t    instance,
++    tmPowerState_t *pPowerState
++)
++{
++   tmErrorCode_t errCode = TM_OK;
++
++#ifdef TMFL_TDA9989
++
++    unsigned char I2c_ReadBuffer[1];
++
++    tmdlHdmiCecDriverConfigTable_t *pDis;
++
++    pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++
++
++    /* check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++    if (pPowerState == NULL) return TMDL_ERR_DLHDMICEC_BAD_PARAMETER;
++
++
++    errCode = getCecHwRegisters(pDis, E_REG_ENAMODS,I2c_ReadBuffer,1);
++    RETIF(errCode != TM_OK, errCode)
++
++    if ((I2c_ReadBuffer[0] & DEFAULT_ENAMODS) == DEFAULT_ENAMODS) {
++        *pPowerState = tmPowerOn;
++    }
++    else {
++        *pPowerState = tmPowerStandby;
++    }
++
++
++#endif  /*  TMFL_TDA9989 */
++
++    return errCode;
++
++}
++
++//==========================================================================
++/*!
++    \brief This function allow to send a generic CEC message
++           This function has to be used when CEC messages are construct in 
++	   the middleware
++
++    \param instance  Instance identifier.
++    
++    \param *pData    Pointer to the CEC data buffer 
++    
++    \param lenData   Lenght of I2C data buffer
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++	    - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++*/
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecSendMessage(
++
++   tmInstance_t instance,
++   UInt8        *pData,
++   UInt16       lenData
++)
++{
++
++  tmErrorCode_t  errCode = TM_OK;
++
++#ifdef TMFL_TDA9989
++
++  unsigned char  I2c_Buffer[19] ;        /* I2C data buffer */
++  unsigned char  Loci;                   /* Local increment variable*/
++  unsigned char  MessLength;             /* Local Message length*/
++  
++  tmdlHdmiCecDriverConfigTable_t *pDis; /* Pointer to Device Instance Structure */
++
++  /* check if instance number is in range */
++  RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++  /* check if unit corresponding to instance is opened */
++  RETIF(UnitTable[instance].opened == False, TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED)
++  
++  /* check if CEC message is not too long */
++  RETIF((lenData > 16), TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS)
++
++  pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++
++  /* Calculate Internal Message length*/
++  MessLength = (lenData-1)+3; /* real data is less ReceiverLogical address */
++  
++  I2c_Buffer[0] = MessLength;  /* Param number */
++
++  I2c_Buffer[1] = 0x00;     /* Request CEC data */
++
++  /*Build Initiator and Reciever Logical Address Byte*/
++  I2c_Buffer[2] = (unsigned char)(UnitTable[instance].DeviceLogicalAddress) & 0x0F; /*Initiator logical Address*/
++  I2c_Buffer[2] = I2c_Buffer[2] << 4;
++  I2c_Buffer[2] |= pData[0] & 0x0F;
++
++  for(Loci = 0; Loci <= lenData ; Loci++)
++  {
++     I2c_Buffer[(Loci+3)] = pData[(Loci+1)];     /* Fill Table with Data from middleware, Data begin at position 1*/
++  }
++  
++  errCode = setCecHwRegisters(pDis, E_REG_CDR0, I2c_Buffer,MessLength); /* CEC Data register */
++  RETIF(errCode != TM_OK, errCode)
++  
++  /* Save Datas of the CEC message send */
++  gtmdlHdmiCecDriverSaveMessage.AddressByte = pData[2];
++  gtmdlHdmiCecDriverSaveMessage.MessageTypePolling = 0;
++  gtmdlHdmiCecDriverSaveMessage.Opcode = pData[3];
++
++#endif  /*  TMFL_TDA9989 */
++
++  return errCode;
++
++}
++
++
++
++//==========================================================================
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecEnableCalibration(tmInstance_t instance,tmdlHdmiCecClockSource_t cecClockSource)
++{
++    tmErrorCode_t errCode = TM_OK;
++
++#ifdef TMFL_TDA9989
++
++    unsigned char                   I2c_ReadBuffer[1];
++    tmdlHdmiCecDriverConfigTable_t *pDis;
++
++    pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++
++   /* check if instance number is in range */
++   RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++   /* CLOCK SOURCE is FRO */
++   if (cecClockSource == TMDL_HDMICEC_CLOCK_FRO) {
++
++
++
++   	   /* cf PR1795 set desired frequency to 12 Mhz*/
++
++	   tmdlHdmiCecSetRegister(instance, 0xF3, 0xC0);
++
++	   RETIF(errCode != TM_OK, errCode)
++
++	   tmdlHdmiCecSetRegister(instance, 0xF4, 0xD4);
++
++	   RETIF(errCode != TM_OK, errCode)
++
++       /* set calibration in automatic mode */
++       errCode = getCecHwRegisters(pDis, E_REG_CEC_DES_FREQ2,I2c_ReadBuffer,1);
++       RETIF(errCode != TM_OK, errCode)
++       I2c_ReadBuffer[0] &= CEC_AUTOMATIC_CALIBRATION_MSK;
++       errCode = setCecHwRegister(pDis, E_REG_CEC_DES_FREQ2, I2c_ReadBuffer[0]);
++       RETIF(errCode != TM_OK, errCode)
++
++
++       /* select FRO clock mode, osc_freq shall be also set to one */
++       I2c_ReadBuffer[0] = CEC_SELECT_FRO_CLOCK_SOURCE;
++       errCode = setCecHwRegister(pDis, E_REG_CEC_CLK, I2c_ReadBuffer[0]);
++       RETIF(errCode != TM_OK, errCode)
++
++
++       /* Enable cec_clk AND FRO */
++       errCode = getCecHwRegisters(pDis, E_REG_ENAMODS,I2c_ReadBuffer,1);	
++       RETIF(errCode != TM_OK, errCode)
++       I2c_ReadBuffer[0] |= CEC_ENABLE_CEC_CLK_MSK;
++       I2c_ReadBuffer[0] &= CEC_ENABLE_FRO_MSK;
++       errCode = setCecHwRegister(pDis, E_REG_ENAMODS, I2c_ReadBuffer[0]);
++       RETIF(errCode != TM_OK, errCode)
++
++       /* Enable calibration */
++       I2c_ReadBuffer[0] = CEC_ENABLE_CALIBRATION;
++       errCode = setCecHwRegister(pDis, E_REG_CEC_CAL_XOSC_CTRL1, I2c_ReadBuffer[0]);
++       RETIF(errCode != TM_OK, errCode)
++
++   } /* CLOCK SOURCE is FRO */
++
++#endif  /*  TMFL_TDA9989 */
++
++    return errCode;
++}
++
++
++//==========================================================================
++//==========================================================================
++tmErrorCode_t tmdlHdmiCecDisableCalibration(tmInstance_t instance)
++{
++    tmErrorCode_t errCode = TM_OK;
++
++#ifdef TMFL_TDA9989
++
++    unsigned char                   I2c_ReadBuffer[1];
++    tmdlHdmiCecDriverConfigTable_t *pDis;
++
++    pDis = &gtmdlHdmiCecDriverConfigTable[instance];
++
++   /* check if instance number is in range */
++   RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMICEC_BAD_INSTANCE)
++
++   /* Disable calibration */
++   I2c_ReadBuffer[0] = CEC_DISABLE_CALIBRATION;
++   errCode = setCecHwRegister(pDis, E_REG_CEC_CAL_XOSC_CTRL1, I2c_ReadBuffer[0]);
++   RETIF(errCode != TM_OK, errCode)
++
++#endif  /*  TMFL_TDA9989 */
++
++    return errCode;
++}
++
++/*============================================================================*/
++/*                     END OF FILE                                            */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.c b/drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.c
+new file mode 100755
+index 0000000..ed422d7
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.c
+@@ -0,0 +1,280 @@
++/**
++ * Copyright (C) 2006 Koninklijke Philips Electronics N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of Koninklijke Philips Electronics N.V. and is confidential in
++ * nature. Under no circumstances is this software to be  exposed to or placed
++ * under an Open Source License of any type without the expressed written
++ * permission of Koninklijke Philips Electronics N.V.
++ *
++ * \file          tmdlHdmiCEC_local.c
++ *
++ * \version       $Revision:  $
++ *
++ * \date          $Date: $
++ *
++ * \brief         dev lib driver component for the CEC messages
++ *
++ * \section refs  Reference Documents
++ * \section info  Change Information
++ *
++ * \verbatim
++   $History: tmdlHdmiCEC_local.c $
++ * 
++   \endverbatim
++ *
++*/
++
++/*============================================================================*/
++/*                   FILE CONFIGURATION                                       */
++/*============================================================================*/
++
++/* Defining this symbol on the compiler command line excludes some API checks */
++/* #define NO_RETIF_BADPARAM */
++
++/*============================================================================*/
++/*                   STANDARD INCLUDE FILES                                   */
++/*============================================================================*/
++
++
++/*============================================================================*/
++/*                   PROJECT INCLUDE FILES                                    */
++/*============================================================================*/
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#include <linux/kernel.h>
++#else
++#include <string.h>
++#endif
++#include "tmdlHdmiCEC.h"
++#include "tmdlHdmiCEC_local.h"
++
++/*============================================================================*/
++/*                   MACRO DEFINITIONS                                        */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                   TYPE DEFINITIONS                                         */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                   PUBLIC VARIABLE DEFINITIONS                              */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                   STATIC VARIABLE DECLARATIONS                             */
++/*============================================================================*/
++
++/**
++ * Lookup table to map an 8-bit mask to a number of left shifts
++ * needed to shift a value starting at bit 0 onto the mask.
++ * Indexed by mask 0-255. For example, mask 0x00 and 0x01 need
++ * no shift, mask 0x02 needs one shift, mask 0x03 needs no shift,
++ * mask 0x04 needs 2 shifts, etc.
++ * Rows were formatted by "HDMI Driver - Register List.xls" and pasted here
++ */
++static CONST_DAT UInt8 kMaskToShift[256] =
++{/* Mask index: */
++ /*x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF        */
++    0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 1x */
++    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 2x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 3x */
++    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 4x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 5x */
++    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 6x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 7x */
++    7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 8x */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 9x */
++    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Ax */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Bx */
++    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Cx */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Dx */
++    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* Ex */
++    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0  /* Fx */
++};
++
++/*============================================================================*/
++/*                   STATIC FUNCTION DECLARATIONS                             */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                   PUBLIC FUNCTION DEFINITIONS                              */
++/*============================================================================*/
++
++/*============================================================================*/
++/* getCecHwRegisters                                                             */
++/*============================================================================*/
++tmErrorCode_t
++getCecHwRegisters
++(
++    tmdlHdmiCecDriverConfigTable_t *pDis, 
++    UInt8  regAddr,
++    UInt8  *pData, 
++    UInt16 lenData
++    )
++{
++    tmErrorCode_t        err;     /* Error code */
++    tmdlHdmiCecSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Get I2C register range - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->i2cAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = (UInt8)lenData;
++    sysArgs.pData           = pData;
++    err = pDis->i2cReadFunction(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMDL_ERR_DLHDMICEC_I2C_READ;
++}
++
++/*============================================================================*/
++/* getCecHwRegister                                                              */
++/*============================================================================*/
++tmErrorCode_t
++getCecHwRegister
++(
++    tmdlHdmiCecDriverConfigTable_t *pDis, 
++    UInt8 regAddr, 
++    UInt8 *pRegValue
++)
++{
++    tmErrorCode_t        err;     /* Error code */
++    tmdlHdmiCecSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Get I2C register - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->i2cAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = 1;
++    sysArgs.pData           = pRegValue;
++    err = pDis->i2cReadFunction(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMDL_ERR_DLHDMICEC_I2C_READ;
++
++}
++
++/*============================================================================*/
++/* setCecHwRegisters                                                             */
++/*============================================================================*/
++tmErrorCode_t
++setCecHwRegisters
++(
++    tmdlHdmiCecDriverConfigTable_t *pDis, 
++    UInt8  regAddr,
++    UInt8  *pData, 
++    UInt16 lenData
++    )
++{
++    tmErrorCode_t        err;     /* Error code */
++    tmdlHdmiCecSysArgs_t sysArgs; /* Arguments passed to system function   */
++    
++    /* Write to I2C register range - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->i2cAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = (UInt8)lenData;
++    sysArgs.pData           = pData;
++    err = pDis->i2cWriteFunction(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMDL_ERR_DLHDMICEC_I2C_WRITE;
++}
++
++/*============================================================================*/
++/* setCecHwRegisterMsbLsb                                                        */
++/*============================================================================*/
++tmErrorCode_t
++setCecHwRegisterMsbLsb
++(
++    tmdlHdmiCecDriverConfigTable_t *pDis, 
++    UInt8  regAddr, 
++    UInt16 regWord
++)
++{
++    tmErrorCode_t        err;        /* Error code */
++    UInt8                msbLsb[2];  /* The bytes from regWord                  */
++    tmdlHdmiCecSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Unpack regWord bytes, MSB first */
++    msbLsb[0] = (UInt8)(regWord >> 8);
++    msbLsb[1] = (UInt8)(regWord & 0xFF);
++
++    /* Write to I2C - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->i2cAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = 2;
++    sysArgs.pData           = &msbLsb[0];
++    err = pDis->i2cWriteFunction(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMDL_ERR_DLHDMICEC_I2C_WRITE;
++}
++
++/*============================================================================*/
++/* setCecHwRegister                                                              */
++/*============================================================================*/
++tmErrorCode_t
++setCecHwRegister
++(
++    tmdlHdmiCecDriverConfigTable_t *pDis, 
++    UInt8 regAddr, 
++    UInt8 regValue
++)
++{
++    tmErrorCode_t        err;     /* Error code */
++    tmdlHdmiCecSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Write to I2C - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->i2cAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = 1;
++    sysArgs.pData           = &regValue;
++    err = pDis->i2cWriteFunction(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMDL_ERR_DLHDMICEC_I2C_WRITE;
++}
++
++/*============================================================================*/
++/*  setCecHwRegisterField                                                        */
++/*============================================================================*/
++tmErrorCode_t
++setCecHwRegisterField
++(
++    tmdlHdmiCecDriverConfigTable_t *pDis, 
++    UInt8 regAddr, 
++    UInt8 fieldMask, 
++    UInt8 fieldValue
++)
++{
++    tmErrorCode_t        err;        /* Error code */
++    UInt8                regValue;   /* The register's current value            */
++    tmdlHdmiCecSysArgs_t sysArgs; /* Arguments passed to system function   */
++
++    /* Read I2C register value.
++     * All bitfield registers are either shadowed or can be read.
++     */
++    sysArgs.slaveAddr       = pDis->i2cAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = 1;
++    sysArgs.pData           = &regValue;
++    err = pDis->i2cReadFunction(&sysArgs);
++    RETIF(err != TM_OK, TMDL_ERR_DLHDMICEC_I2C_READ)
++
++    /* Reset register bits that are set in the mask */
++    regValue = regValue & (UInt8)(~fieldMask);
++
++    /* Shift the field value left to align its bits with the mask */
++    fieldValue <<= kMaskToShift[fieldMask];
++
++    /* Reset shifted field bits that are not set in the mask */
++    fieldValue &= fieldMask;
++
++    /* Set the shifted bitfield */
++    regValue |= fieldValue;
++
++    /* Write to I2C - all non-OK results are errors */
++    sysArgs.slaveAddr       = pDis->i2cAddress;
++    sysArgs.firstRegister   = regAddr;
++    sysArgs.lenData         = 1;
++    sysArgs.pData           = &regValue;
++    err = pDis->i2cWriteFunction(&sysArgs);
++    return (err == TM_OK) ? TM_OK : TMDL_ERR_DLHDMICEC_I2C_WRITE;
++}
++
++
++/*============================================================================*/
++/*                   STATIC FUNCTION DEFINTIONS                               */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                     END OF FILE                                            */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.h b/drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.h
+new file mode 100755
+index 0000000..c0baa18
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiCEC/src/tmdlHdmiCEC_local.h
+@@ -0,0 +1,221 @@
++//=============================================================================
++// Copyright (C) 2007 NXP N.V., All Rights Reserved.
++// This source code and any compilation or derivative thereof is the proprietary
++// information of NXP N.V. and is confidential in nature. Under no circumstances
++// is this software to be  exposed to or placed under an Open Source License of
++// any type without the expressed written permission of NXP N.V.
++//=============================================================================
++/*!
++    \file    tmdlHdmiCEC_local.h
++
++	\version 1.0
++
++	\date    24/07/2007
++
++ 	\brief   devlib driver component API for the CEC messages.
++
++    \section refs  Reference Documents
++             TDA998X Driver - tmdlHdmiTx - SCS.doc
++    \note    None.
++ 
++    HISTORY :
++    \verbatim
++     Date          Modified by CRPRNr  TASKNr  Maintenance description
++     -------------|-----------|-------|-------|-----------------------------------
++     24/07/2007   |  F.G      |       |       | Creation.
++     -------------|-----------|-------|-------|-----------------------------------
++    \endverbatim
++*/
++//==========================================================================
++
++#ifndef TMDLHDMICEC_LOCAL_H
++#define TMDLHDMICEC_LOCAL_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++//#include "tmdlHdmiCEC_IW.h"
++#include "tmdlHdmiCEC_cfg.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       MACRO DEFINITIONS                                    */
++/*============================================================================*/
++
++/* Version of the SW driver */
++#define VERSION_COMPATIBILITY 0
++#define VERSION_MAJOR         1
++#define VERSION_MINOR         4
++
++/**
++ * A macro to check a condition and if true return a result
++ */
++#define RETIF(cond, rslt)       if ((cond)){return (rslt);}
++
++/**
++ * A macro to check a condition and if true return 
++ * TMBSL_ERR_HDMI_BAD_PARAMETER.
++ * To save code space, it can be compiled out by defining NO_RETIF_BADPARAM on
++ * the compiler command line.
++ */
++#ifdef NO_RETIF_BADPARAM
++#define RETIF_BADPARAM(cond)
++#else
++#define RETIF_BADPARAM(cond)  if ((cond)){return TMBSL_ERR_HDMI_BAD_PARAMETER;}
++#endif
++
++/**
++ * A macro to check the result of a register API and if not TM_OK to return it.
++ * To save code space, it can be compiled out by defining NO_RETIF_REG_FAIL on
++ * the compiler command line.
++ */
++#ifdef NO_RETIF_REG_FAIL
++#define RETIF_REG_FAIL(result)
++#else
++#define RETIF_REG_FAIL(result)  if ((result) != TM_OK){return (result);}
++#endif
++
++#define TDA9950_RESET_DELAY_MS 250
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++#ifdef TMFL_TDA9989
++
++#define E_REG_ENAMODS	0xFF
++#define E_REG_CEC_CLK	0xF6
++#define E_REG_CEC_INT	0xEE
++#define E_REG_COMBI_INT	0xEC
++#define DEFAULT_ENAMODS 0x81
++#define CEC_CLK_SEL	0xE6
++#define CEC_INT_MASK	0x01
++
++#define E_REG_CEC_CAL_XOSC_CTRL1 0xF2
++#define E_REG_CEC_DES_FREQ2      0xF5
++
++
++#define CEC_AUTOMATIC_CALIBRATION_MSK    0x7F
++#define CEC_SELECT_FRO_CLOCK_SOURCE      0x11
++#define CEC_ENABLE_CEC_CLK_MSK           0x80
++#define CEC_ENABLE_FRO_MSK               0xBF
++#define CEC_ENABLE_CALIBRATION           0x01
++#define CEC_DISABLE_CALIBRATION          0x00
++
++
++#endif  /* TMFL_TDA9989 */
++
++/*!
++   \enum  CEC Stack Processor Regsiters 
++   \brief The CSP is controlled via a series of registers
++*/
++
++enum _eReg
++{
++  E_REG_APR   = 0x00, /*!< Address Pointer Regsiter (Write)           */
++  E_REG_CSR   = 0x00, /*!< CSP Status Register (Read)                 */
++  E_REG_CER   = 0x01, /*!< CSP Error Register  (Read)                 */
++  E_REG_CVR   = 0x02, /*!< CSP Version Register(Read)                 */
++  E_REG_CCR   = 0x03, /*!< CSP Control Register (Read/Write)          */
++  E_REG_ACKH  = 0x04, /*!< CEC Address ACK High Register (Read/Write) */
++  E_REG_ACKL  = 0x05, /*!< CEC Address ACK Low Register (Read/Write)  */
++  E_REG_CCONR = 0x06, /*!< CEC Config Register (Read/Write)           */
++  E_REG_CDR0  = 0x07, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR1  = 0x08, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR2  = 0x09, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR3  = 0x0A, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR4  = 0x0B, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR5  = 0x0C, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR6  = 0x0D, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR7  = 0x0E, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR8  = 0x0F, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR9  = 0x10, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR10 = 0x11, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR11 = 0x12, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR12 = 0x13, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR13 = 0x14, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR14 = 0x15, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR15 = 0x16, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR16 = 0x17, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR17 = 0x18, /*!< CEC Data Register (Read/Write)             */
++  E_REG_CDR18 = 0x19 /*!< CEC Data Register (Read/Write)             */
++};
++
++
++/* possible states of the state driver */
++typedef enum
++{
++    CEC_STATE_NOT_INITIALIZED, /**< Driver is not initialized */
++    CEC_STATE_UNLOCKED ,       /**< Driver is not locked */
++    CEC_STATE_LOCKED,          /**< Driver is locked */
++    CEC_STATE_CONFIGURED       /**< Driver is configured */
++} tmdlHdmiCecDriverState_t;
++
++/**
++ * \brief The structure of a CEC object, one per device unit
++*/
++typedef struct
++{
++    tmInstance_t                  instance;
++    tmdlHdmiCECLogicalAddress_t   DeviceLogicalAddress;
++	Bool                          opened;                   /**< is unit instanciated ? */
++    tmdlHdmiCecDeviceVersion_t    deviceVersion;            /**< Version of the HW device */
++    tmdlHdmiCecDriverState_t      state;                    /**< Current state of the driver */
++    ptmdlHdmiCecCallbackFunc_t    MessageCallback;         /**< Message callback */
++}tmdlHdmiCecUnitConfig_t;
++
++
++/**
++ * \brief States of CEC Status
++*/
++#define CEC_MSG_SUCCESS	    			0x00	/*Message transmisson Succeed*/
++#define CEC_CSP_OFF_STATE   			0x80	/*CSP in Off State*/
++#define CEC_BAD_REQ_SERVICE 			0x81	/*Bad .req service*/
++#define CEC_MSG_FAIL_UNABLE_TO_ACCESS	0x82	/*Message transmisson failed: Unable to access CEC line*/
++#define CEC_MSG_FAIL_ARBITRATION_ERROR	0x83	/*Message transmisson failed: Arbitration error*/
++#define CEC_MSG_FAIL_BIT_TIMMING_ERROR	0x84	/*Message transmisson failed: Bit timming error*/
++#define CEC_MSG_FAIL_DEST_NOT_ACK		0x85	/*Message transmisson failed: Destination Address not aknowledged*/
++#define CEC_MSG_FAIL_DATA_NOT_ACK		0x86	/*Message transmisson failed: Databyte not acknowledged*/
++
++
++/*============================================================================*/
++/*                       EXTERN DATA DEFINITION                               */
++/*============================================================================*/
++
++extern tmdlHdmiCecDriverConfigTable_t gtmdlHdmiCecDriverConfigTable[MAX_UNITS];
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++
++tmErrorCode_t    getCecHwRegisters (tmdlHdmiCecDriverConfigTable_t *pDis, 
++                                 UInt8  regAddr,
++                                 UInt8 *pData, UInt16 lenData);
++tmErrorCode_t    getCecHwRegister (tmdlHdmiCecDriverConfigTable_t *pDis, 
++                                UInt8  regAddr,
++                                UInt8 *pRegValue);
++tmErrorCode_t    setCecHwRegisters (tmdlHdmiCecDriverConfigTable_t *pDis, 
++                                 UInt8  regAddr,
++                                 UInt8 *pData, UInt16 lenData);
++tmErrorCode_t    setCecHwRegisterMsbLsb (tmdlHdmiCecDriverConfigTable_t *pDis, 
++                                      UInt8  regAddr, 
++                                      UInt16 regWord);
++tmErrorCode_t    setCecHwRegister (tmdlHdmiCecDriverConfigTable_t *pDis, 
++                                UInt8  regAddr,
++                                UInt8 regValue);
++tmErrorCode_t    setCecHwRegisterField (tmdlHdmiCecDriverConfigTable_t *pDis,
++                                     UInt8  regAddr,
++                                     UInt8 fieldMask, UInt8 fieldValue);
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMI_CEC_LOCAL_H */
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c b/drivers/video/nxp/comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c
+new file mode 100755
+index 0000000..aae2c10
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c
+@@ -0,0 +1,570 @@
++/**
++ * Copyright (C) 2009 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx_LinuxCfg.c
++ *
++ * \version       Revision: 1
++ *
++ * \date          Date: 25/03/11 11:00
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * HDMI Tx Driver - FRS.doc,
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   History:       tmdlHdmiTx_LinuxCfg.c
++ *
++ * *****************  Version 2  ***************** 
++ * User: V. Vrignaud Date: March 25th, 2011
++ *
++ * *****************  Version 1  *****************
++ * User: A. Lepine Date: October 1st, 2009
++ * initial version
++ *
++
++   \endverbatim
++ *
++*/
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                                MACRO                                       */
++/*============================================================================*/
++/* macro for quick error handling */
++#define RETIF(cond, rslt) if ((cond)){return (rslt);}
++#define I2C_M_WR 0
++
++/*============================================================================*/
++/*                   STATIC FUNCTION DECLARATIONS                             */
++/*============================================================================*/
++tmErrorCode_t TxI2cReadFunction(tmbslHdmiTxSysArgs_t *pSysArgs);
++tmErrorCode_t TxI2cWriteFunction(tmbslHdmiTxSysArgs_t *pSysArgs);
++
++/******************************************************************************
++ ******************************************************************************
++ *                 THIS PART CAN BE MODIFIED BY CUSTOMER                      *
++ ******************************************************************************
++ *****************************************************************************/
++struct i2c_client *GetThisI2cClient(void);
++unsigned char  my_i2c_data[255];
++
++/* The following includes are used by I2C access function. If    */
++/* you need to rewrite these functions for your own SW infrastructure, then   */
++/* it can be removed                                                          */
++#	include <linux/kernel.h>
++#	include <linux/errno.h>
++#	include <linux/string.h>
++#	include <linux/types.h>
++#	include <linux/i2c.h>
++#	include <linux/delay.h>
++
++#include <linux/gfp.h>
++
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/vt_kern.h>
++#include <asm/types.h>
++
++/* I2C adress of the unit                                                     */
++/* Put there the I2C slave adress of the Tx transmitter IC                    */
++#define UNIT_I2C_ADDRESS_0 0x70
++
++/* Intel CE 4100 I2C bus number                                               */
++/* Put there the number of I2C bus handling the Rx transmitter IC             */
++#define I2C_BUS_NUMBER_0 0 // initial:0
++
++/* I2C Number of bytes in the data buffer.                                    */
++#define SUB_ADDR_BYTE_COUNT_0 1
++
++/* Priority of the command task                                               */
++/* Command task is an internal task that handles incoming event from the IC   */
++/* put there a value that will ensure a response time of ~20ms in your system */
++#define COMMAND_TASK_PRIORITY_0  250
++#define COMMAND_TASK_PRIORITY_1  250
++
++/* Priority of the hdcp check tasks */
++/* HDCP task is an internal task that handles periodical HDCP processing      */
++/* put there a value that will ensure a response time of ~20ms in your system */
++#define HDCP_CHECK_TASK_PRIORITY_0  250
++
++/* Stack size of the command tasks */
++/* This value depends of the type of CPU used, and also from the length of    */
++/* the customer callbacks. Increase this value if you are making a lot of     */
++/* processing (function calls & local variables) and that you experience      */
++/* stack overflows                                                            */
++#define COMMAND_TASK_STACKSIZE_0 128
++#define COMMAND_TASK_STACKSIZE_1 128
++
++/* stack size of the hdcp check tasks */
++/* This value depends of the type of CPU used, default value should be enough */
++/* for all configuration                                                      */
++#define HDCP_CHECK_TASK_STACKSIZE_0 128
++
++/* Size of the message queues for command tasks                               */
++/* This value defines the size of the message queue used to link the          */
++/* the tmdlHdmiTxHandleInterrupt function and the command task. The default   */
++/* value below should fit any configuration                                   */
++#define COMMAND_TASK_QUEUESIZE_0 128
++#define COMMAND_TASK_QUEUESIZE_1 128
++
++/* HDCP key seed                                                              */
++/* HDCP key are stored encrypted into the IC, this value allows the IC to     */
++/* decrypt them. This value is provided to the customer by NXP customer       */
++/* support team.                                                              */
++#define KEY_SEED 0x1234
++
++/* Video port configuration for YUV444 input                                  */
++/* You can specify in this table how are connected video ports in case of     */
++/* YUV444 input signal. Each line of the array corresponds to a quartet of    */
++/* pins of one video port (see comment on the left to identify them). Just    */
++/* change the enum to specify which signal you connected to it. See file      */
++/* tmdlHdmiTx_cfg.h to get the list of possible values                        */
++const tmdlHdmiTxCfgVideoSignal444 videoPortMapping_YUV444[MAX_UNITS][6] = {
++    {
++        TMDL_HDMITX_VID444_BU_0_TO_3,   /* Signals connected to VPA[0..3] */
++        TMDL_HDMITX_VID444_BU_4_TO_7,   /* Signals connected to VPA[4..7] */
++        TMDL_HDMITX_VID444_GY_0_TO_3,   /* Signals connected to VPB[0..3] */
++        TMDL_HDMITX_VID444_GY_4_TO_7,   /* Signals connected to VPB[4..7] */
++        TMDL_HDMITX_VID444_VR_0_TO_3,   /* Signals connected to VPC[0..3] */
++        TMDL_HDMITX_VID444_VR_4_TO_7    /* Signals connected to VPC[4..7] */
++    }
++};
++
++/* Video port configuration for RGB444 input                                  */
++/* You can specify in this table how are connected video ports in case of     */
++/* RGB444 input signal. Each line of the array corresponds to a quartet of    */
++/* pins of one video port (see comment on the left to identify them). Just    */
++/* change the enum to specify which signal you connected to it. See file      */
++/* tmdlHdmiTx_cfg.h to get the list of possible values                        */
++const tmdlHdmiTxCfgVideoSignal444 videoPortMapping_RGB444[MAX_UNITS][6] = {
++    {
++        TMDL_HDMITX_VID444_GY_0_TO_3,   /* Signals connected to VPA[0..3] */
++        TMDL_HDMITX_VID444_GY_4_TO_7,   /* Signals connected to VPA[4..7] */
++        TMDL_HDMITX_VID444_BU_0_TO_3,   /* Signals connected to VPC[0..3] */
++        TMDL_HDMITX_VID444_BU_4_TO_7,   /* Signals connected to VPC[4..7] */
++        TMDL_HDMITX_VID444_VR_0_TO_3,   /* Signals connected to VPB[0..3] */
++        TMDL_HDMITX_VID444_VR_4_TO_7    /* Signals connected to VPB[4..7] */
++    }
++};
++
++/* Video port configuration for YUV422 input                                  */
++/* You can specify in this table how are connected video ports in case of     */
++/* YUV422 input signal. Each line of the array corresponds to a quartet of    */
++/* pins of one video port (see comment on the left to identify them). Just    */
++/* change the enum to specify which signal you connected to it. See file      */
++/* tmdlHdmiTx_cfg.h to get the list of possible values                        */
++const tmdlHdmiTxCfgVideoSignal422 videoPortMapping_YUV422[MAX_UNITS][6] = {
++    {
++        TMDL_HDMITX_VID422_Y_4_TO_7,           /* Signals connected to VPA[0..3] */    
++        TMDL_HDMITX_VID422_Y_8_TO_11,          /* Signals connected to VPA[4..7] */    
++        TMDL_HDMITX_VID422_UV_4_TO_7,          /* Signals connected to VPB[0..3] */
++        TMDL_HDMITX_VID422_UV_8_TO_11,         /* Signals connected to VPB[4..7] */
++        TMDL_HDMITX_VID422_NOT_CONNECTED,      /* Signals connected to VPC[0..3] */
++        TMDL_HDMITX_VID422_NOT_CONNECTED       /* Signals connected to VPC[4..7] */
++    }
++};
++
++/* Video port configuration for CCIR656 input                                 */
++/* You can specify in this table how are connected video ports in case of     */
++/* CCIR656 input signal. Each line of the array corresponds to a quartet of   */
++/* pins of one video port (see comment on the left to identify them). Just    */
++/* change the enum to specify which signal you connected to it. See file      */
++/* tmdlHdmiTx_cfg.h to get the list of possible values                        */
++const tmdlHdmiTxCfgVideoSignalCCIR656 videoPortMapping_CCIR656[MAX_UNITS][6] = {
++    {
++        TMDL_HDMITX_VIDCCIR_4_TO_7,         /* Signals connected to VPA[0..3] */
++        TMDL_HDMITX_VIDCCIR_8_TO_11,        /* Signals connected to VPA[4..7] */
++        TMDL_HDMITX_VIDCCIR_NOT_CONNECTED,  /* Signals connected to VPB[0..3] */
++        TMDL_HDMITX_VIDCCIR_NOT_CONNECTED,  /* Signals connected to VPB[4..7] */
++        TMDL_HDMITX_VIDCCIR_NOT_CONNECTED,  /* Signals connected to VPC[0..3] */
++        TMDL_HDMITX_VIDCCIR_NOT_CONNECTED   /* Signals connected to VPC[4..7] */
++    }
++}; 
++
++/*
++ *
++ * Linux wrapping starts here...............................
++ *
++ */ 
++/* 
++ *  Write a bloc to a register in Tx device.
++ */
++int blockwrite_reg(struct i2c_client *client, u8 reg, u16 alength, u8 *val)
++{
++   int err = 0;   
++   int i;
++   struct i2c_msg msg[1];
++    
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++   
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = alength+1;
++   msg->buf = my_i2c_data;
++   
++   msg->buf[0] = reg;   
++   for (i=1; i<=alength; i++) msg->buf[i] = (*val++);
++   
++   err = i2c_transfer(client->adapter, msg, 1);
++   udelay(50);
++
++
++/*    printk(KERN_INFO "DBG blockwrite_reg addr:%x reg:%d data:%x %s\n",msg->addr,reg,val,(err<0?"ERROR":"")); */
++
++/*    dev_dbg(&client->dev, "<%s> i2c Block write at 0x%x, " */
++/*            "*val=%d flags=%d byte[%d] err=%d\n", */
++/*            __func__, data[0], data[1], msg->flags, i, err); */
++
++   return (err < 0?err:0);
++}
++
++/* 
++ *  Read a bloc to a register in Tx device.
++ */
++int blockread_reg(struct i2c_client *client, u8 reg, u16 alength, u8 *val)
++{
++   int err = 0;
++   struct i2c_msg msg[1];
++   u8 data[2];
++
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = 1;
++   msg->buf = data;
++   data[0] = reg; /* High byte goes out first */
++   err = i2c_transfer(client->adapter, msg, 1);
++/*    printk(KERN_INFO "DBG blockread_reg #1 addr:%x len:%d buf:%02x%02x%02x%02x %s\n",msg->addr,msg->len,\ */
++/*           msg->buf[0],msg->buf[1],msg->buf[2],msg->buf[3],(err<0?"ERROR":"")); */
++   if (err<0) goto BLOCK_READ_OUPS;
++
++   msg->flags = I2C_M_RD;
++   msg->len = alength; 
++   msg->buf = val;
++   err = i2c_transfer(client->adapter, msg, 1);
++/*    printk(KERN_INFO "DBG blockread_reg #2 addr:%x len:%d buf:%02x%02x%02x%02x %s\n",msg->addr,msg->len,\ */
++/*           msg->buf[0],msg->buf[1],msg->buf[2],msg->buf[3],(err<0?"ERROR":"")); */
++
++   if (err<0) goto BLOCK_READ_OUPS;
++
++   return 0;
++   
++ BLOCK_READ_OUPS:
++   dev_err(&client->dev, "<%s> ERROR:  i2c Read at 0x%x, "
++           "*val=%d flags=%d bytes err=%d\n",
++           __func__, reg, *val, msg->flags, err);
++		   
++   return err;
++}
++
++/* 
++ *  Write a byte to a register in Tx device.
++ */
++int write_reg(struct i2c_client *client, u8 reg, u8 val)
++{
++   int err = 0;
++   struct i2c_msg msg[1];
++   u8 data[2];
++   int retries = 0;   
++
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++
++ retry:
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = 2;
++   msg->buf = data;
++
++   data[0] = reg;
++   data[1] = val;
++
++   err = i2c_transfer(client->adapter, msg, 1);
++   dev_dbg(&client->dev, "<%s> i2c write at=%x "
++	   "val=%x flags=%d err=%d\n",
++	   __func__, data[0], data[1], msg->flags, err);
++   udelay(50);
++
++/*    printk(KERN_INFO "DBG write_reg addr:%x reg:%d data:%x %s\n",msg->addr,reg,val,(err<0?"ERROR":"")); */
++
++   if (err >= 0)
++      return 0;
++
++   dev_err(&client->dev, "<%s> ERROR: i2c write at=%x "
++	   "val=%x flags=%d err=%d\n",
++	   __func__, data[0], data[1], msg->flags, err);
++   if (retries <= 5) {
++      dev_info(&client->dev, "Retrying I2C... %d\n", retries);
++      retries++;
++      set_current_state(TASK_UNINTERRUPTIBLE);
++      schedule_timeout(msecs_to_jiffies(20));
++      goto retry;
++   }
++   
++   return err;
++}
++
++/*
++ *  Read a byte from a register in Tx device.
++ */
++int read_reg(struct i2c_client *client, u16 data_length, u8 reg, u8 *val)
++{
++   int err = 0;  
++   struct i2c_msg msg[1];
++   u8 data[2];
++
++   if (!client->adapter) {
++      dev_err(&client->dev, "<%s> ERROR: No HDMI Device\n", __func__);
++      return -ENODEV;
++   }
++
++   msg->addr = client->addr;
++   msg->flags = I2C_M_WR;
++   msg->len = 1;
++   msg->buf = data;
++
++   data[0] = reg;
++   err = i2c_transfer(client->adapter, msg, 1);
++   dev_dbg(&client->dev, "<%s> i2c Read1 reg=%x val=%d "
++	   "flags=%d err=%d\n",
++	   __func__, reg, data[1], msg->flags, err);
++
++   if (err >= 0) {
++      mdelay(3);
++      msg->flags = I2C_M_RD;
++      msg->len = data_length;
++      err = i2c_transfer(client->adapter, msg, 1);
++   }
++
++   if (err >= 0) {
++      *val = 0;
++      if (data_length == 1)
++	 *val = data[0];
++      else if (data_length == 2)
++	 *val = data[1] + (data[0] << 8);
++      dev_dbg(&client->dev, "<%s> i2c Read2 at 0x%x, *val=%d "
++	      "flags=%d err=%d\n",
++	      __func__, reg, *val, msg->flags, err);
++      return 0;
++   }
++
++   dev_err(&client->dev, "<%s> ERROR: i2c Read at 0x%x, "
++	   "*val=%d flags=%d err=%d\n",
++	   __func__, reg, *val, msg->flags, err);
++
++   return err;   
++}
++/*
++ *
++ * Linux wrapping end...............................
++ *
++ */
++
++/* The following function must be rewritten by the customer to fit its own    */
++/* SW infrastructure. This function allows reading through I2C bus.           */
++/* tmbslHdmiTxSysArgs_t definition is located into tmbslHdmiTx_type.h file.   */
++tmErrorCode_t TxI2cReadFunction(tmbslHdmiTxSysArgs_t *pSysArgs)
++{
++   tmErrorCode_t errCode = TM_OK;
++   struct i2c_client *client=GetThisI2cClient();
++   u32 client_main_addr=client->addr;
++
++   /* DevLib needs address control, so let it be */ 
++   client->addr=pSysArgs->slaveAddr;
++
++   if (pSysArgs->lenData == 1) {
++      /* single byte */
++      errCode = read_reg(GetThisI2cClient(),1,pSysArgs->firstRegister,pSysArgs->pData);
++   }
++   else {
++      /* block */
++      errCode = blockread_reg(GetThisI2cClient(), \
++			      pSysArgs->firstRegister, \
++			      pSysArgs->lenData, \
++			      pSysArgs->pData);
++   }
++   
++   /* restore default client address */
++   client->addr=client_main_addr;
++
++    return errCode;
++}
++
++/* The following function must be rewritten by the customer to fit its own    */
++/* SW infrastructure. This function allows writing through I2C bus.           */
++/* tmbslHdmiTxSysArgs_t definition is located into tmbslHdmiTx_type.h file.   */
++tmErrorCode_t TxI2cWriteFunction(tmbslHdmiTxSysArgs_t *pSysArgs)
++{
++   tmErrorCode_t  errCode = TM_OK;
++   struct i2c_client *client=GetThisI2cClient();
++   u32 client_main_addr=client->addr;
++
++   /* DevLib needs address control, so let it be */ 
++   client->addr=pSysArgs->slaveAddr;
++   
++   if (pSysArgs->lenData == 1) {
++      /* single byte */
++      errCode = write_reg(GetThisI2cClient(),pSysArgs->firstRegister,*pSysArgs->pData);
++   }
++   else {
++      /* block */
++      errCode = blockwrite_reg(GetThisI2cClient(),  \
++                               pSysArgs->firstRegister, \
++                               pSysArgs->lenData,       \
++                               pSysArgs->pData);
++   }
++   
++   /* restore default client address */
++   client->addr=client_main_addr;
++
++    return errCode;
++}
++
++
++/******************************************************************************
++    \brief  This function blocks the current task for the specified amount time. 
++            This is a passive wait.
++
++    \param  Duration    Duration of the task blocking in milliseconds.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWWait
++(
++    UInt16 duration
++)
++{
++	mdelay((unsigned long)duration);
++
++    return(TM_OK);
++}
++
++/******************************************************************************
++    \brief  This function creates a semaphore.
++
++    \param  pHandle Pointer to the handle buffer.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreCreate
++(
++    tmdlHdmiTxIWSemHandle_t *pHandle
++)
++{
++    struct semaphore * mutex;
++    
++    /* check that input pointer is not NULL */
++    RETIF(pHandle == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    mutex = (struct semaphore *)kmalloc(sizeof(struct semaphore),GFP_KERNEL);
++    if (!mutex) {
++       printk(KERN_ERR "malloc failed in %s\n",__func__);
++       return TMDL_ERR_DLHDMITX_NO_RESOURCES;
++    }
++    
++    sema_init(mutex, 1);
++    *pHandle = (tmdlHdmiTxIWSemHandle_t)mutex;
++
++    RETIF(pHandle == NULL, TMDL_ERR_DLHDMITX_NO_RESOURCES)
++
++    return(TM_OK);
++}
++
++/******************************************************************************
++    \brief  This function destroys an existing semaphore.
++
++    \param  Handle  Handle of the semaphore to be destroyed.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreDestroy
++(
++    tmdlHdmiTxIWSemHandle_t handle
++)
++{
++   RETIF(handle == False, TMDL_ERR_DLHDMITX_BAD_HANDLE);
++   
++   if (atomic_read((atomic_t*)&((struct semaphore *)handle)->count) < 1) {
++      printk(KERN_ERR "release catched semaphore");
++   }
++   
++   kfree((void*)handle);
++   
++   return(TM_OK);
++}
++
++/******************************************************************************
++    \brief  This function acquires the specified semaphore.
++
++    \param  Handle  Handle of the semaphore to be acquired.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreP
++(
++    tmdlHdmiTxIWSemHandle_t handle
++)
++{
++    down((struct semaphore *)handle);
++
++    return(TM_OK);
++}
++
++/******************************************************************************
++    \brief  This function releases the specified semaphore.
++
++    \param  Handle  Handle of the semaphore to be released.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreV
++(
++    tmdlHdmiTxIWSemHandle_t handle
++)
++{
++    up((struct semaphore *)handle);
++
++    return(TM_OK);
++}
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_cfg.c b/drivers/video/nxp/comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_cfg.c
+new file mode 100755
+index 0000000..23c5437
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_cfg.c
+@@ -0,0 +1,624 @@
++/**
++ * Copyright (C) 2006 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx_cfg.c
++ *
++ * \version       Revision: 1
++ *
++ * \date          Date: 25/03/11 11:00
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * HDMI Tx Driver - FRS.doc,
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   History:       tmdlHdmiTx_cfg.c
++ *
++ * *****************  Version 2  *****************
++ * User: V. Vrignaud Date: March 25th, 2011
++ *
++ * *****************  Version 1  *****************
++ * User: J. Lamotte Date: 08/08/07  Time: 11:00
++ * initial version
++ *
++
++   \endverbatim
++ *
++*/
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#include "tmdlHdmiTx_IW.h"
++#include "tmdlHdmiTx.h"
++#include "tmdlHdmiTx_cfg.h"
++
++#ifdef TMFL_CEC_AVAILABLE
++#include "tmdlHdmiCEC_functions.h"
++#define CEC_UNIT_I2C_ADDRESS_0 0x34
++#define CEC_UNIT_I2C_ADDRESS_1 0x34
++#endif
++
++//#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#ifdef TMFL_CFG_ZOOMII // OMAP Zoom II
++#	include "tmdlHdmiTx_Linux_cfg.c"
++#elif TMFL_CFG_INTELCE4100 // Intel CE 4100
++#	include "tmdlHdmiTx_IntelCE4100_cfg.c"
++#elif TMFL_OS_WINDOWS // Windows demo application
++#	include "tmdlHdmiTx_Win_cfg.c"
++#else // Section to be modified by customer - Default configuration for NXP evalkit
++
++/*============================================================================*/
++/*                                MACRO                                       */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                   STATIC FUNCTION DECLARATIONS                             */
++/*============================================================================*/
++tmErrorCode_t TxI2cReadFunction(tmbslHdmiTxSysArgs_t *pSysArgs);
++tmErrorCode_t TxI2cWriteFunction(tmbslHdmiTxSysArgs_t *pSysArgs);
++
++/******************************************************************************
++ ******************************************************************************
++ *                 THIS PART CAN BE MODIFIED BY CUSTOMER                      *
++ ******************************************************************************
++ *****************************************************************************/
++/* The following includes are used by I2C access function for ARM7. If    */
++/* you need to rewrite these functions for your own SW infrastructure, then   */
++/* it can be removed                                                          */
++#include "I2C.h"
++#include <LPC21xx.H>
++
++/* I2C adress of the unit                                                     */
++/* Put there the I2C slave adress of the Tx transmitter IC                    */
++#define UNIT_I2C_ADDRESS_0 0x70
++
++/* Priority of the command task                                               */
++/* Command task is an internal task that handles incoming event from the IC   */
++/* put there a value that will ensure a response time of ~20ms in your system */
++#define COMMAND_TASK_PRIORITY_0  250
++#define COMMAND_TASK_PRIORITY_1  250
++
++/* Priority of the hdcp check tasks */
++/* HDCP task is an internal task that handles periodical HDCP processing      */
++/* put there a value that will ensure a response time of ~20ms in your system */
++#define HDCP_CHECK_TASK_PRIORITY_0  250
++
++/* Stack size of the command tasks */
++/* This value depends of the type of CPU used, and also from the length of    */
++/* the customer callbacks. Increase this value if you are making a lot of     */
++/* processing (function calls & local variables) and that you experience      */
++/* stack overflows                                                            */
++#define COMMAND_TASK_STACKSIZE_0 128
++#define COMMAND_TASK_STACKSIZE_1 128
++
++/* stack size of the hdcp check tasks */
++/* This value depends of the type of CPU used, default value should be enough */
++/* for all configuration                                                      */
++#define HDCP_CHECK_TASK_STACKSIZE_0 128
++
++/* Size of the message queues for command tasks                               */
++/* This value defines the size of the message queue used to link the          */
++/* the tmdlHdmiTxHandleInterrupt function and the command task. The default   */
++/* value below should fit any configuration                                   */
++#define COMMAND_TASK_QUEUESIZE_0 128
++#define COMMAND_TASK_QUEUESIZE_1 128
++
++/* HDCP key seed                                                              */
++/* HDCP key are stored encrypted into the IC, this value allows the IC to     */
++/* decrypt them. This value is provided to the customer by NXP customer       */
++/* support team.                                                              */
++#define KEY_SEED 0x1234
++
++/* Video port configuration for YUV444 input                                  */
++/* You can specify in this table how are connected video ports in case of     */
++/* YUV444 input signal. Each line of the array corresponds to a quartet of    */
++/* pins of one video port (see comment on the left to identify them). Just    */
++/* change the enum to specify which signal you connected to it. See file      */
++/* tmdlHdmiTx_cfg.h to get the list of possible values                        */
++const tmdlHdmiTxCfgVideoSignal444 videoPortMapping_YUV444[MAX_UNITS][6] = {
++    {
++        TMDL_HDMITX_VID444_GY_0_TO_3,   /* Signals connected to VPB[0..3] */
++        TMDL_HDMITX_VID444_GY_4_TO_7,   /* Signals connected to VPB[4..7] */
++        TMDL_HDMITX_VID444_BU_0_TO_3,   /* Signals connected to VPA[0..3] */
++        TMDL_HDMITX_VID444_BU_4_TO_7,   /* Signals connected to VPA[4..7] */
++        TMDL_HDMITX_VID444_VR_0_TO_3,   /* Signals connected to VPC[0..3] */
++        TMDL_HDMITX_VID444_VR_4_TO_7    /* Signals connected to VPC[4..7] */
++    }
++};
++
++/* Video port configuration for RGB444 input                                  */
++/* You can specify in this table how are connected video ports in case of     */
++/* RGB444 input signal. Each line of the array corresponds to a quartet of    */
++/* pins of one video port (see comment on the left to identify them). Just    */
++/* change the enum to specify which signal you connected to it. See file      */
++/* tmdlHdmiTx_cfg.h to get the list of possible values                        */
++const tmdlHdmiTxCfgVideoSignal444 videoPortMapping_RGB444[MAX_UNITS][6] = {
++    {
++        TMDL_HDMITX_VID444_GY_0_TO_3,   /* Signals connected to VPB[0..3] */
++        TMDL_HDMITX_VID444_GY_4_TO_7,   /* Signals connected to VPB[4..7] */
++        TMDL_HDMITX_VID444_BU_0_TO_3,   /* Signals connected to VPA[0..3] */
++        TMDL_HDMITX_VID444_BU_4_TO_7,   /* Signals connected to VPA[4..7] */
++        TMDL_HDMITX_VID444_VR_0_TO_3,   /* Signals connected to VPC[0..3] */
++        TMDL_HDMITX_VID444_VR_4_TO_7    /* Signals connected to VPC[4..7] */
++    }
++};
++
++/* Video port configuration for YUV422 input                                  */
++/* You can specify in this table how are connected video ports in case of     */
++/* YUV422 input signal. Each line of the array corresponds to a quartet of    */
++/* pins of one video port (see comment on the left to identify them). Just    */
++/* change the enum to specify which signal you connected to it. See file      */
++/* tmdlHdmiTx_cfg.h to get the list of possible values                        */
++const tmdlHdmiTxCfgVideoSignal422 videoPortMapping_YUV422[MAX_UNITS][6] = {
++    {
++        TMDL_HDMITX_VID422_NOT_CONNECTED,   /* Signals connected to VPC[0..3] */
++        TMDL_HDMITX_VID422_NOT_CONNECTED,   /* Signals connected to VPB[4..7] */
++        TMDL_HDMITX_VID422_UV_4_TO_7,       /* Signals connected to VPC[4..7] */
++        TMDL_HDMITX_VID422_UV_8_TO_11,      /* Signals connected to VPB[0..3] */
++        TMDL_HDMITX_VID422_Y_4_TO_7,      	/* Signals connected to VPA[0..3] */
++        TMDL_HDMITX_VID422_Y_8_TO_11	    /* Signals connected to VPA[4..7] */
++    }
++};
++
++/* Video port configuration for CCIR656 input                                 */
++/* You can specify in this table how are connected video ports in case of     */
++/* CCIR656 input signal. Each line of the array corresponds to a quartet of   */
++/* pins of one video port (see comment on the left to identify them). Just    */
++/* change the enum to specify which signal you connected to it. See file      */
++/* tmdlHdmiTx_cfg.h to get the list of possible values                        */
++const tmdlHdmiTxCfgVideoSignalCCIR656 videoPortMapping_CCIR656[MAX_UNITS][6] = {
++    {
++        TMDL_HDMITX_VIDCCIR_NOT_CONNECTED,  /* Signals connected to VPB[0..3] */
++        TMDL_HDMITX_VIDCCIR_NOT_CONNECTED,  /* Signals connected to VPB[4..7] */
++        TMDL_HDMITX_VIDCCIR_NOT_CONNECTED,  /* Signals connected to VPC[0..3] */
++        TMDL_HDMITX_VIDCCIR_NOT_CONNECTED,  /* Signals connected to VPC[4..7] */
++        TMDL_HDMITX_VIDCCIR_4_TO_7,        	/* Signals connected to VPA[4..7] */
++        TMDL_HDMITX_VIDCCIR_8_TO_11         /* Signals connected to VPA[0..3] */
++    }
++};
++
++/* The following function must be rewritten by the customer to fit its own    */
++/* SW infrastructure. This function allows reading through I2C bus.           */
++/* tmbslHdmiTxSysArgs_t definition is located into tmbslHdmiTx_type.h file.   */
++tmErrorCode_t TxI2cReadFunction(tmbslHdmiTxSysArgs_t *pSysArgs)
++{
++    tmErrorCode_t errCode = TM_OK;
++
++    if (pSysArgs->slaveAddr == 0x70)
++    {
++        errCode = i2cRead(reg_TDA998X, (tmbslHdmiSysArgs_t *) pSysArgs);
++    }
++    else if (pSysArgs->slaveAddr == 0x34)
++    {
++       errCode = i2cRead(reg_TDA9989_CEC, (tmbslHdmiSysArgs_t *) pSysArgs); 
++    }
++    else
++    {
++        errCode = ~TM_OK;
++    }
++    
++    return errCode;
++}
++
++/* The following function must be rewritten by the customer to fit its own    */
++/* SW infrastructure. This function allows writing through I2C bus.           */
++/* tmbslHdmiTxSysArgs_t definition is located into tmbslHdmiTx_type.h file.   */
++tmErrorCode_t TxI2cWriteFunction(tmbslHdmiTxSysArgs_t *pSysArgs)
++{
++    tmErrorCode_t  errCode = TM_OK;
++
++    if (pSysArgs->slaveAddr == 0x70)
++    {
++        errCode = i2cWrite(reg_TDA998X, (tmbslHdmiSysArgs_t *) pSysArgs);
++      
++    }
++    else if (pSysArgs->slaveAddr == 0x34)
++    {
++       errCode = i2cWrite(reg_TDA9989_CEC, (tmbslHdmiSysArgs_t *) pSysArgs);
++    }
++    else
++    {
++        errCode = ~TM_OK;
++    }
++    
++    return errCode;
++}
++
++#endif
++
++#ifdef TMFL_RGB_DDR_12BITS
++
++/* Video port configuration for RGB 24 bits input received with only 12 bits  */
++/* using the double data rate                                                 */
++/*
++  The main difference between RGB12 bits and CCIR 656 formats is that for the new format
++  RGB888 the“Green� data is separated on rising and on falling edge. This is in principle
++  no problem only the result is that the colors RGB will be swabbed.
++  After the Video Input Processing (VIP) module there will be a multiplexer structure
++  implemented which can swab all colors and combinations.
++  
++  Extra information on request
++  
++  P:\Partages\BCT_TV_FE\Product_Development\Project folders\TDA19988    \
++  14_Design\Video_pipe_Schematic_RGB888.pdf
++
++  but ok, let's give it a try...
++
++  In DDR, VIP input latches on failing and raising clock edge,
++  so VIP internal input is doubled from 24 to 48 bits
++
++  VIP input ------>[ T ]---[ T ]--------------------> VIP internal input
++     /24   |         |       °      /24   |                /48
++           |         |       |            |
++           |  pclk-----------             |
++           |         |                    |
++           |         °                    |
++            ------>[ T ]------------------
++                                    /24
++
++  But in the 24 VIP input, only 12 bits are used :
++
++  -------------------------------------------------------------------
++  |          |          |          |          |          |          |
++  | Vpc[7:4] | Vpc[3:0] | Vpb[7:4] | Vpb[3:0] | Vpa[7:4] | Vpa[3:0] |
++  |          |          | ........ |          | ........ | ........ |
++  -------------------------------------------------------------------
++                             ^                      ^         ^
++                             |                      |         |
++                             |                      |         |
++  location of valid data -------------------------------------
++
++  So we get first RGB 12 bits on bits 24 to 47 of VIP internal input
++  and second RGB 12 bits on bits 0 to 23 of VIP internal input
++
++  1)first edge (failing)   R[7:4]                 R[3:0]     G[7:4]
++                             |                      |         |
++                             |                      |         |
++                             V                      V         V
++  --------------------------------------------------------------------..
++  |          |          |          |          |          |          |
++  | 47...44  | 43...40  | 39...36  | 35...32  | 31...28  | 27...24  |
++  |          |          |          |          |          |          |
++  --------------------------------------------------------------------..
++
++  2)2nd edge (raising)     G[3:0]                 B[7:3]     B[3:0]
++                             |                      |         |
++                             |                      |         |
++                             V                      V         V
++..-------------------------------------------------------------------
++  |          |          |          |          |          |          |
++  | 23...20  | 19...16  | 15...12  | 11...8   |  7...4   |  3...0   |
++  |          |          |          |          |          |          |
++..-------------------------------------------------------------------
++
++
++
++
++
++
++  After port swaping, internal video bus goes back from 48 to 24 bits
++
++  VIP internal ------------>[ swap ]-------[ T ]---------->
++                     /48       |             |    /24
++                               |             |
++            i2c_swap_a/f ------      pclk ---
++
++  -------------------------------------------------------------------
++  |          |          |          |          |          |          |
++  | 23...20  | 19...16  | 15...12  | 11...8   |  7...4   |  3...0   |
++  |          |          |          |          |          |          |
++  -------------------------------------------------------------------
++    R[7:4]     R[3:0]     G[7:4]     G[3:0]     B[7:3]     B[3:0]
++
++   Here is the swapping code :
++
++IF    i2c_swap_a = "000" THEN vp_alt_d2(11 downto 8) <= vp_alt_i_r(23 downto 20); vp_alt_d2(23 downto 20) <= vp_alt_i_r(47 downto 44);
++ELSIF i2c_swap_a = "001" THEN vp_alt_d2(11 downto 8) <= vp_alt_i_r(19 downto 16); vp_alt_d2(23 downto 20) <= vp_alt_i_r(43 downto 40);
++ELSIF i2c_swap_a = "010" THEN vp_alt_d2(11 downto 8) <= vp_alt_i_r(15 downto 12); vp_alt_d2(23 downto 20) <= vp_alt_i_r(39 downto 36);
++ELSIF i2c_swap_a = "011" THEN vp_alt_d2(11 downto 8) <= vp_alt_i_r(11 downto 8 ); vp_alt_d2(23 downto 20) <= vp_alt_i_r(35 downto 32);
++ELSIF i2c_swap_a = "100" THEN vp_alt_d2(11 downto 8) <= vp_alt_i_r( 7 downto 4 ); vp_alt_d2(23 downto 20) <= vp_alt_i_r(31 downto 28);
++ELSE                          vp_alt_d2(11 downto 8) <= vp_alt_i_r( 3 downto 0 ); vp_alt_d2(23 downto 20) <= vp_alt_i_r(27 downto 24); END IF;
++
++IF    i2c_swap_b = "000" THEN vp_alt_d2( 7 downto 4) <= vp_alt_i_r(23 downto 20); vp_alt_d2(19 downto 16) <= vp_alt_i_r(47 downto 44);
++ELSIF i2c_swap_b = "001" THEN vp_alt_d2( 7 downto 4) <= vp_alt_i_r(19 downto 16); vp_alt_d2(19 downto 16) <= vp_alt_i_r(43 downto 40);
++ELSIF i2c_swap_b = "010" THEN vp_alt_d2( 7 downto 4) <= vp_alt_i_r(15 downto 12); vp_alt_d2(19 downto 16) <= vp_alt_i_r(39 downto 36);
++ELSIF i2c_swap_b = "011" THEN vp_alt_d2( 7 downto 4) <= vp_alt_i_r(11 downto 8 ); vp_alt_d2(19 downto 16) <= vp_alt_i_r(35 downto 32);
++ELSIF i2c_swap_b = "100" THEN vp_alt_d2( 7 downto 4) <= vp_alt_i_r( 7 downto 4 ); vp_alt_d2(19 downto 16) <= vp_alt_i_r(31 downto 28);
++ELSE                          vp_alt_d2( 7 downto 4) <= vp_alt_i_r( 3 downto 0 ); vp_alt_d2(19 downto 16) <= vp_alt_i_r(27 downto 24); END IF;
++
++IF    i2c_swap_c = "000" THEN vp_alt_d2( 3 downto 0) <= vp_alt_i_r(23 downto 20); vp_alt_d2(15 downto 12) <= vp_alt_i_r(47 downto 44);
++ELSIF i2c_swap_c = "001" THEN vp_alt_d2( 3 downto 0) <= vp_alt_i_r(19 downto 16); vp_alt_d2(15 downto 12) <= vp_alt_i_r(43 downto 40);
++ELSIF i2c_swap_c = "010" THEN vp_alt_d2( 3 downto 0) <= vp_alt_i_r(15 downto 12); vp_alt_d2(15 downto 12) <= vp_alt_i_r(39 downto 36);
++ELSIF i2c_swap_c = "011" THEN vp_alt_d2( 3 downto 0) <= vp_alt_i_r(11 downto 8 ); vp_alt_d2(15 downto 12) <= vp_alt_i_r(35 downto 32);
++ELSIF i2c_swap_c = "100" THEN vp_alt_d2( 3 downto 0) <= vp_alt_i_r( 7 downto 4 ); vp_alt_d2(15 downto 12) <= vp_alt_i_r(31 downto 28);
++ELSE                          vp_alt_d2( 3 downto 0) <= vp_alt_i_r( 3 downto 0 ); vp_alt_d2(15 downto 12) <= vp_alt_i_r(27 downto 24); END IF;
++
++  in case of RGB DDR 12 bits, we get :
++    . i2c_swap_a = "010"
++    . i2c_swap_b = "011"
++    . i2c_swap_c > "100"
++
++ ;)
++
++*/
++
++const tmdlHdmiTxCfgVideoSignal_RGB_DDR_12bits VideoPortMapping_RGB_DDR_12bits[MAX_UNITS][6] = {
++    {
++        TMDL_HDMITX_VID_B_0_3_G_4_7,        /* Signals connected to VPA[0..3] */
++        TMDL_HDMITX_VID_DDR_NOT_CONNECTED,  /* Signals connected to VPA[4..7] */
++        TMDL_HDMITX_VID_B_4_7_R_0_3,        /* Signals connected to VPB[0..3] */
++        TMDL_HDMITX_VID_G_0_3_R_4_7,        /* Signals connected to VPB[4..7] */
++        TMDL_HDMITX_VID_DDR_NOT_CONNECTED,  /* Signals connected to VPC[0..3] */
++        TMDL_HDMITX_VID_DDR_NOT_CONNECTED   /* Signals connected to VPC[4..7] */
++    }
++};
++
++/*
++
++  Then VIP targeted order is not RGB but BGR
++  so we use a new register for TDA19988 MUX_VP_VIP_OUT
++  with VIP_OUTPUT_RGB_GBR as defined in cfg.h file
++
++  -------------------------------------------------------------------
++  |          |          |          |          |          |          |
++  | 23...20  | 19...16  | 15...12  | 11...8   |  7...4   |  3...0   |
++  |          |          |          |          |          |          |
++  -------------------------------------------------------------------
++    R[7:4]     R[3:0]     G[7:4]     G[3:0]     B[7:3]     B[3:0]
++       -                    .                     .                      
++           -             .                     .                        
++               -       .                     .                          
++                   - .                     .                            
++                   .   -                 .                              
++                 .         -           .                        
++               .               -     .                          
++             .                     -                            
++           .                     .     -                  
++         .                     .           -              
++       .                     .                 -          
++
++    G[7:4]     G[3:0]     B[7:4]     B[3:0]     R[7:3]     R[3:0]
++
++*/
++
++const UInt8 VideoPortMux_RGB_DDR_12bits[MAX_UNITS] = {
++   VIP_MUX_R_R | VIP_MUX_G_G | VIP_MUX_B_B
++};
++
++const UInt8 VideoPortNoMux[MAX_UNITS] = {
++   VIP_MUX_G_B | VIP_MUX_B_R | VIP_MUX_R_G
++};
++
++#endif /* TMFL_RGB_DDR_12BITS */
++
++/* Audio port configuration for SPDIF                                         */
++/* Here you can specify the audio port routing configuration for SPDIF input. */
++/* enableAudioPortSPDIF and groundAudioPortSPDIF should be filled with a      */
++/* value build as follows : each bit represent an audio port, LSB is port 0.  */
++/* enableAudioClockPortSPDIF and groundAudioClockPortSPDIF can be configured  */
++/* with the corresponding enums (See file tmdlHdmiTx_cfg.h for more details). */
++UInt8 enableAudioPortSPDIF[MAX_UNITS]      = {0x02};
++UInt8 enableAudioClockPortSPDIF[MAX_UNITS] = {DISABLE_AUDIO_CLOCK_PORT};
++UInt8 groundAudioPortSPDIF[MAX_UNITS]      = {0xFD};
++UInt8 groundAudioClockPortSPDIF[MAX_UNITS] = {ENABLE_AUDIO_CLOCK_PORT_PULLDOWN};
++
++/* Audio port configuration for I2S                                           */
++/* Here you can specify the audio port routing configuration for SPDIF input. */
++/* enableAudioPortI2S and groundAudioPortI2S should be filled with a          */
++/* value build as follows : each bit represent an audio port, LSB is port 0.  */
++/* enableAudioClockPortI2S and groundAudioClockPortI2S can be configured      */
++/* with the corresponding enums (See file tmdlHdmiTx_cfg.h for more details). */
++UInt8 enableAudioPortI2S[MAX_UNITS]        = {0x03};
++UInt8 enableAudioPortI2S8C[MAX_UNITS]      = {0x1f};
++UInt8 enableAudioClockPortI2S[MAX_UNITS]   = {ENABLE_AUDIO_CLOCK_PORT};
++UInt8 groundAudioPortI2S[MAX_UNITS]        = {0xfc};
++UInt8 groundAudioPortI2S8C[MAX_UNITS]      = {0xe0};
++UInt8 groundAudioClockPortI2S[MAX_UNITS]   = {DISABLE_AUDIO_CLOCK_PORT_PULLDOWN};
++
++/* Audio port configuration for OBA                                           */
++/* Here you can specify the audio port routing configuration for SPDIF input. */
++/* enableAudioPortOBA and groundAudioPortOBA should be filled with a          */
++/* value build as follows : each bit represent an audio port, LSB is port 0.  */
++/* enableAudioClockPortOBA and groundAudioClockPortOBA can be configured      */
++/* with the corresponding enums (See file tmdlHdmiTx_cfg.h for more details). */
++UInt8 enableAudioPortOBA[MAX_UNITS]        = {0xFF};
++UInt8 enableAudioClockPortOBA[MAX_UNITS]   = {ENABLE_AUDIO_CLOCK_PORT};
++UInt8 groundAudioPortOBA[MAX_UNITS]        = {0x00};
++UInt8 groundAudioClockPortOBA[MAX_UNITS]   = {DISABLE_AUDIO_CLOCK_PORT_PULLDOWN};
++
++/* Audio port configuration for DST                                           */
++/* Here you can specify the audio port routing configuration for SPDIF input. */
++/* enableAudioPortDST and groundAudioPortDST should be filled with a          */
++/* value build as follows : each bit represent an audio port, LSB is port 0.  */
++/* enableAudioClockPortDST and groundAudioClockPortDST can be configured      */
++/* with the corresponding enums (See file tmdlHdmiTx_cfg.h for more details). */
++UInt8 enableAudioPortDST[MAX_UNITS]        = {0xFF};
++UInt8 enableAudioClockPortDST[MAX_UNITS]   = {ENABLE_AUDIO_CLOCK_PORT};
++UInt8 groundAudioPortDST[MAX_UNITS]        = {0x00};
++UInt8 groundAudioClockPortDST[MAX_UNITS]   = {DISABLE_AUDIO_CLOCK_PORT_PULLDOWN};
++
++/* Audio port configuration for HBR                                           */
++/* Here you can specify the audio port routing configuration for SPDIF input. */
++/* enableAudioPortHBR and groundAudioPortHBR should be filled with a          */
++/* value build as follows : each bit represent an audio port, LSB is port 0.  */
++/* enableAudioClockPortHBR and groundAudioClockPortHBR can be configured      */
++/* with the corresponding enums (See file tmdlHdmiTx_cfg.h for more details). */
++UInt8 enableAudioPortHBR[MAX_UNITS]        = {0x1f};
++UInt8 enableAudioClockPortHBR[MAX_UNITS]   = {ENABLE_AUDIO_CLOCK_PORT};
++UInt8 groundAudioPortHBR[MAX_UNITS]        = {0xe0};
++UInt8 groundAudioClockPortHBR[MAX_UNITS]   = {DISABLE_AUDIO_CLOCK_PORT_PULLDOWN};
++
++/*****************************************************************************
++******************************************************************************
++*                THIS PART MUST NOT BE MODIFIED BY CUSTOMER                  *
++******************************************************************************
++*****************************************************************************/
++
++/* DO NOT MODIFY, those tables are filled dynamically by                      */
++/* dlHdmiTxGenerateCfgVideoPortTables API                                     */
++UInt8 mirrorTableCCIR656[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 swapTableCCIR656[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 enableVideoPortCCIR656[MAX_UNITS][3] = {{0x00, 0x00, 0x00}};
++UInt8 groundVideoPortCCIR656[MAX_UNITS][3] = {{0xFF, 0xFF, 0xFF}};
++UInt8 mirrorTableYUV422[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 swapTableYUV422[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 enableVideoPortYUV422[MAX_UNITS][3] = {{0x00, 0x00, 0x00}};
++UInt8 groundVideoPortYUV422[MAX_UNITS][3] = {{0xFF, 0xFF, 0xFF}};
++UInt8 mirrorTableYUV444[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 swapTableYUV444[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 enableVideoPortYUV444[MAX_UNITS][3] = {{0x00, 0x00, 0x00}};
++UInt8 groundVideoPortYUV444[MAX_UNITS][3] = {{0xFF, 0xFF, 0xFF}};
++UInt8 mirrorTableRGB444[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 swapTableRGB444[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 enableVideoPortRGB444[MAX_UNITS][3] = {{0x00, 0x00, 0x00}};
++UInt8 groundVideoPortRGB444[MAX_UNITS][3] = {{0xFF, 0xFF, 0xFF}};
++#ifdef TMFL_RGB_DDR_12BITS
++UInt8 mirrorTableRGB_DDR_12bits[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 swapTableRGB_DDR_12bits[MAX_UNITS][6] = {{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}};
++UInt8 enableVideoPortRGB_DDR_12bits[MAX_UNITS][3] = {{0x00, 0x00, 0x00}};
++UInt8 groundVideoPortRGB_DDR_12bits[MAX_UNITS][3] = {{0xFF, 0xFF, 0xFF}};
++UInt8 NoMux[MAX_UNITS] = {0x00};
++UInt8 Mux_RGB_DDR_12bits[MAX_UNITS] = {0x00};
++#endif
++
++/* DO NOT MODIFY, this table is used for transmission of the configuration to */
++/* the core driver                                                            */
++tmdlHdmiTxDriverConfigTable_t driverConfigTableTx[MAX_UNITS] = {
++    {
++        COMMAND_TASK_PRIORITY_0,
++        COMMAND_TASK_STACKSIZE_0,
++        COMMAND_TASK_QUEUESIZE_0,
++        HDCP_CHECK_TASK_PRIORITY_0,
++        HDCP_CHECK_TASK_STACKSIZE_0,
++        UNIT_I2C_ADDRESS_0,
++        TxI2cReadFunction,
++        TxI2cWriteFunction,
++        Null,                           /* filled dynamically, do not modify */
++        &mirrorTableCCIR656[0][0],      /* filled dynamically, do not modify */
++        &swapTableCCIR656[0][0],        /* filled dynamically, do not modify */
++        &enableVideoPortCCIR656[0][0],  /* filled dynamically, do not modify */
++        &groundVideoPortCCIR656[0][0],  /* filled dynamically, do not modify */
++        &mirrorTableYUV422[0][0],       /* filled dynamically, do not modify */
++        &swapTableYUV422[0][0],         /* filled dynamically, do not modify */
++        &enableVideoPortYUV422[0][0],   /* filled dynamically, do not modify */
++        &groundVideoPortYUV422[0][0],   /* filled dynamically, do not modify */
++        &mirrorTableYUV444[0][0],       /* filled dynamically, do not modify */
++        &swapTableYUV444[0][0],         /* filled dynamically, do not modify */
++        &enableVideoPortYUV444[0][0],   /* filled dynamically, do not modify */
++        &groundVideoPortYUV444[0][0],   /* filled dynamically, do not modify */
++        &mirrorTableRGB444[0][0],       /* filled dynamically, do not modify */
++        &swapTableRGB444[0][0],         /* filled dynamically, do not modify */
++        &enableVideoPortRGB444[0][0],   /* filled dynamically, do not modify */
++        &groundVideoPortRGB444[0][0],   /* filled dynamically, do not modify */
++#ifdef TMFL_RGB_DDR_12BITS
++        &mirrorTableRGB_DDR_12bits[0][0],
++        &swapTableRGB_DDR_12bits[0][0],
++        &NoMux[0],
++        &Mux_RGB_DDR_12bits[0],
++        &enableVideoPortRGB_DDR_12bits[0][0],
++        &groundVideoPortRGB_DDR_12bits[0][0],
++#endif
++        &enableAudioPortSPDIF[0],
++        &groundAudioPortSPDIF[0],
++        &enableAudioClockPortSPDIF[0],
++        &groundAudioClockPortSPDIF[0],
++        &enableAudioPortI2S[0],
++        &groundAudioPortI2S[0],
++        &enableAudioPortI2S8C[0],
++        &groundAudioPortI2S8C[0],
++        &enableAudioClockPortI2S[0],
++        &groundAudioClockPortI2S[0],
++        &enableAudioPortOBA[0],
++        &groundAudioPortOBA[0],
++        &enableAudioClockPortOBA[0],
++        &groundAudioClockPortOBA[0],
++        &enableAudioPortDST[0],
++        &groundAudioPortDST[0],
++        &enableAudioClockPortDST[0],
++        &groundAudioClockPortDST[0],
++        &enableAudioPortHBR[0],
++        &groundAudioPortHBR[0],
++        &enableAudioClockPortHBR[0],
++        &groundAudioClockPortHBR[0],
++        KEY_SEED,
++        TMDL_HDMITX_PATTERN_BLUE,
++        1                               /* DE signal is available */
++    }
++ };
++
++#ifdef TMFL_CEC_AVAILABLE
++
++tmdlHdmiCecCapabilities_t CeccapabilitiesList = {TMDL_HDMICEC_DEVICE_UNKNOWN, CEC_VERSION_1_3a};
++
++/**
++ * \brief Configuration Tables. This table can be modified by the customer 
++            to choose its prefered configuration
++ */
++
++tmdlHdmiCecDriverConfigTable_t CecdriverConfigTable[MAX_UNITS] = {
++    {
++    COMMAND_TASK_PRIORITY_0,
++    COMMAND_TASK_STACKSIZE_0,
++    COMMAND_TASK_QUEUESIZE_0,
++    CEC_UNIT_I2C_ADDRESS_0,
++    TxI2cReadFunction,
++    TxI2cWriteFunction,
++    &CeccapabilitiesList
++    }
++};
++
++
++/******************************************************************************
++******************************************************************************
++*                THIS PART MUST NOT BE MODIFIED BY CUSTOMER                  *
++******************************************************************************
++*****************************************************************************/
++
++/**
++    \brief This function allows to the main driver to retrieve its
++           configuration parameters.
++
++    \param pConfig Pointer to the config structure
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiCecCfgGetConfig
++(
++    tmUnitSelect_t                 unit,
++    tmdlHdmiCecDriverConfigTable_t *pConfig
++)
++{
++    /* check if unit number is in range */
++    if((unit < 0) || (unit >= MAX_UNITS))
++	  	return TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER;
++
++    /* check if pointer is Null */
++    if(pConfig == Null)
++	 	return TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS;
++
++    *pConfig = CecdriverConfigTable[unit];
++
++    return TM_OK;
++}
++
++#endif
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_IW.h b/drivers/video/nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_IW.h
+new file mode 100755
+index 0000000..1b8cd29
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_IW.h
+@@ -0,0 +1,290 @@
++/**
++ * Copyright (C) 2007 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx_IW.h
++ *
++ * \version       $Revision: 1 $
++ *
++ * \date          $Date: 07/08/07 16:00 $
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * TDA998x Driver - FRS.doc,
++ * TDA998x Driver - tmdlHdmiTx - SCS.doc
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   $History: tmdlHdmiTx_IW.h $
++ *
++ * *****************  Version 1  *****************
++ * User: J. Lamotte Date: 07/08/07   Time: 16:00
++ * Updated in $/Source/tmdlHdmiTx/inc
++ * initial version
++ *
++
++   \endverbatim
++ *
++*/
++
++#ifndef TMDLHDMITX_IW_H
++#define TMDLHDMITX_IW_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#ifdef TMFL_OS_WINDOWS
++#define _WIN32_WINNT 0x0500
++#include "windows.h"
++#endif
++
++#include "tmNxTypes.h"
++#include "tmdlHdmiTx_Types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       TYPE DEFINITIONS                                     */
++/*============================================================================*/
++typedef void (*tmdlHdmiTxIWFuncPtr_t) (void);
++typedef UInt8 tmdlHdmiTxIWTaskHandle_t;
++typedef UInt8 tmdlHdmiTxIWQueueHandle_t;
++#ifdef TMFL_OS_WINDOWS
++typedef HANDLE tmdlHdmiTxIWSemHandle_t;
++#else
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++typedef unsigned long tmdlHdmiTxIWSemHandle_t;
++#else
++typedef UInt8 tmdlHdmiTxIWSemHandle_t;
++#endif
++#endif
++
++/**
++ * \brief Enum listing all available devices for enable/disable interrupts
++ */
++typedef enum
++{
++    TMDL_HDMI_IW_RX_1,
++    TMDL_HDMI_IW_RX_2,
++    TMDL_HDMI_IW_TX_1,
++    TMDL_HDMI_IW_TX_2,
++    TMDL_HDMI_IW_CEC_1,
++    TMDL_HDMI_IW_CEC_2
++} tmdlHdmiIWDeviceInterrupt_t;
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++
++/******************************************************************************
++    \brief  This function creates a task and allocates all the necessary
++            resources. Note that creating a task do not start it automatically,
++            an explicit call to tmdlHdmiTxIWTaskStart must be made.
++
++    \param  pFunc       Pointer to the function that will be executed in the task context.
++    \param  Priority    Priority of the task. The minimum priority is 0, the maximum is 255.
++    \param  StackSize   Size of the stack to allocate for this task.
++    \param  pHandle     Pointer to the handle buffer.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWTaskCreate(tmdlHdmiTxIWFuncPtr_t pFunc,UInt8 priority, UInt16 stackSize, tmdlHdmiTxIWTaskHandle_t *pHandle);
++
++/******************************************************************************
++    \brief  This function destroys an existing task and frees resources used by it.
++
++    \param  Handle  Handle of the task to be destroyed, as returned by tmdlHdmiTxIWTaskCreate.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWTaskDestroy(tmdlHdmiTxIWTaskHandle_t handle);
++
++/******************************************************************************
++    \brief  This function start an existing task.
++
++    \param  Handle  Handle of the task to be started.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_ALREADY_STARTED: the function is already started
++            - TMDL_ERR_DLHDMITX_NOT_STARTED: the function is not started
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWTaskStart(tmdlHdmiTxIWTaskHandle_t handle);
++
++/******************************************************************************
++    \brief  This function blocks the current task for the specified amount time. This is a passive wait.
++
++    \param  Duration    Duration of the task blocking in milliseconds.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWWait(UInt16 duration);
++
++/******************************************************************************
++    \brief  This function creates a message queue.
++
++    \param  QueueSize   Maximum number of messages in the message queue.
++    \param  pHandle     Pointer to the handle buffer.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWQueueCreate(UInt8 queueSize, tmdlHdmiTxIWQueueHandle_t *pHandle);
++
++/******************************************************************************
++    \brief  This function destroys an existing message queue.
++
++    \param  Handle  Handle of the queue to be destroyed.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWQueueDestroy(tmdlHdmiTxIWQueueHandle_t handle);
++
++/******************************************************************************
++    \brief  This function sends a message into the specified message queue.
++
++    \param  Handle  Handle of the queue that will receive the message.
++    \param  Message Message to be sent.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMITX_FULL: the queue is full
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWQueueSend(tmdlHdmiTxIWQueueHandle_t handle, UInt8 message);
++
++/******************************************************************************
++    \brief  This function reads a message from the specified message queue.
++
++    \param  Handle      Handle of the queue from which to read the message.
++    \param  pMessage    Pointer to the message buffer.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWQueueReceive(tmdlHdmiTxIWQueueHandle_t handle, UInt8 *pMessage);
++
++/******************************************************************************
++    \brief  This function creates a semaphore.
++
++    \param  pHandle Pointer to the handle buffer.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreCreate(tmdlHdmiTxIWSemHandle_t *pHandle);
++
++/******************************************************************************
++    \brief  This function destroys an existing semaphore.
++
++    \param  Handle  Handle of the semaphore to be destroyed.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreDestroy(tmdlHdmiTxIWSemHandle_t handle);
++
++/******************************************************************************
++    \brief  This function acquires the specified semaphore.
++
++    \param  Handle  Handle of the semaphore to be acquired.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreP(tmdlHdmiTxIWSemHandle_t handle);
++
++/******************************************************************************
++    \brief  This function releases the specified semaphore.
++
++    \param  Handle  Handle of the semaphore to be released.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxIWSemaphoreV(tmdlHdmiTxIWSemHandle_t handle);
++
++/******************************************************************************
++    \brief  This function disables the interrupts for a specific device.
++
++    \param
++
++    \return The call result:
++            - TM_OK: the call was successful
++
++******************************************************************************/
++void tmdlHdmiTxIWDisableInterrupts(tmdlHdmiIWDeviceInterrupt_t device);
++
++/******************************************************************************
++    \brief  This function enables the interrupts for a specific device.
++
++    \param
++
++    \return The call result:
++            - TM_OK: the call was successful
++
++******************************************************************************/
++void tmdlHdmiTxIWEnableInterrupts(tmdlHdmiIWDeviceInterrupt_t device);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMITX_IW_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_cfg.h b/drivers/video/nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_cfg.h
+new file mode 100755
+index 0000000..1a672aa
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/cfg/tmdlHdmiTx_cfg.h
+@@ -0,0 +1,298 @@
++/**
++ * Copyright (C) 2006 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx_cfg.h
++ *
++ * \version       $Revision: 1 $
++ *
++ * \date          $Date: 08/08/07 11:00 $
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * HDMI Tx Driver - FRS.doc,
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   $History: tmbslHdmiTx_cfg.h $
++ *
++ * *****************  Version 1  *****************
++ * User: J. Lamotte Date: 08/08/07  Time: 11:00
++ * initial version
++ *
++
++   \endverbatim
++ *
++*/
++
++/*****************************************************************************/
++/*****************************************************************************/
++/*                THIS FILE MUST NOT BE MODIFIED BY CUSTOMER                 */
++/*      Customer specific configuration is set in tmdlHdmiTx_cfg.c file      */
++/*****************************************************************************/
++/*****************************************************************************/
++
++#ifndef TMDLHDMITX_CFG_H
++#define TMDLHDMITX_CFG_H
++
++#include "tmNxTypes.h"
++#include "tmbslHdmiTx_types.h"
++#include "tmdlHdmiTx_Types.h"
++
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                          TYPES DECLARATIONS                                */
++/*============================================================================*/
++
++/**
++ * \brief Video signals that can be input to video ports in RGB/YUV 4:4:4 mode
++ */
++typedef enum
++{
++    TMDL_HDMITX_VID444_GY_4_TO_7 = 0x00,        /**< Video signal G/Y, bits 4 to 7 */
++    TMDL_HDMITX_VID444_GY_0_TO_3 = 0x01,        /**< Video signal G/Y, bits 0 to 3 */
++    TMDL_HDMITX_VID444_BU_4_TO_7 = 0x02,        /**< Video signal B/U, bits 4 to 7 */
++    TMDL_HDMITX_VID444_BU_0_TO_3 = 0x03,        /**< Video signal B/U, bits 0 to 3 */
++    TMDL_HDMITX_VID444_VR_4_TO_7 = 0x04,        /**< Video signal V/R, bits 4 to 7 */
++    TMDL_HDMITX_VID444_VR_0_TO_3 = 0x05,        /**< Video signal V/R, bits 0 to 3 */
++    TMDL_HDMITX_VID444_GY_7_TO_4 = 0x80,        /**< Video signal G/Y, bits 7 to 4 (mirrored) */
++    TMDL_HDMITX_VID444_GY_3_TO_0 = 0x81,        /**< Video signal G/Y, bits 3 to 0 (mirrored) */
++    TMDL_HDMITX_VID444_BU_7_TO_4 = 0x82,        /**< Video signal B/U, bits 7 to 4 (mirrored) */
++    TMDL_HDMITX_VID444_BU_3_TO_0 = 0x83,        /**< Video signal B/U, bits 3 to 0 (mirrored) */
++    TMDL_HDMITX_VID444_VR_7_TO_4 = 0x84,        /**< Video signal V/R, bits 7 to 4 (mirrored) */
++    TMDL_HDMITX_VID444_VR_3_TO_0 = 0x85,        /**< Video signal V/R, bits 3 to 0 (mirrored) */
++    TMDL_HDMITX_VID444_NOT_CONNECTED = 0x100    /**< No signal connected */
++} tmdlHdmiTxCfgVideoSignal444;
++
++/**
++ * \brief Video signals that can be input to video ports in semi-planar YUV 4:2:2 mode
++ */
++typedef enum
++{
++    TMDL_HDMITX_VID422_Y_8_TO_11     = 0x00,    /**< Video signal G/Y, bits 8 to 11 */
++    TMDL_HDMITX_VID422_Y_4_TO_7      = 0x01,    /**< Video signal G/Y, bits 4 to 7 */
++    TMDL_HDMITX_VID422_Y_0_TO_3      = 0x02,    /**< Video signal G/Y, bits 0 to 3 */
++    TMDL_HDMITX_VID422_UV_8_TO_11    = 0x03,    /**< Video signal B/U, bits 8 to 11 */
++    TMDL_HDMITX_VID422_UV_4_TO_7     = 0x04,    /**< Video signal B/U, bits 4 to 7 */
++    TMDL_HDMITX_VID422_UV_0_TO_3     = 0x05,    /**< Video signal B/U, bits 0 to 3 */
++    TMDL_HDMITX_VID422_Y_11_TO_8     = 0x80,    /**< Video signal G/Y, bits 11 to 8 (mirrored) */
++    TMDL_HDMITX_VID422_Y_7_TO_4      = 0x81,    /**< Video signal G/Y, bits 7 to 4 (mirrored) */
++    TMDL_HDMITX_VID422_Y_3_TO_0      = 0x82,    /**< Video signal G/Y, bits 3 to 0 (mirrored) */
++    TMDL_HDMITX_VID422_UV_11_TO_8    = 0x83,    /**< Video signal B/U, bits 11 to 8 (mirrored) */
++    TMDL_HDMITX_VID422_UV_7_TO_4     = 0x84,    /**< Video signal B/U, bits 7 to 4 (mirrored) */
++    TMDL_HDMITX_VID422_UV_3_TO_0     = 0x85,    /**< Video signal B/U, bits 3 to 0 (mirrored) */
++    TMDL_HDMITX_VID422_NOT_CONNECTED = 0x100    /**< No signal connected */
++} tmdlHdmiTxCfgVideoSignal422;
++
++/**
++ * \brief Video signals that can be input to video ports in semi-planar CCIR 656 mode
++ */
++typedef enum
++{
++    TMDL_HDMITX_VIDCCIR_8_TO_11       = 0x00,   /**< Video signal CCIR, bits 8 to 11 */
++    TMDL_HDMITX_VIDCCIR_4_TO_7        = 0x01,   /**< Video signal CCIR, bits 4 to 7 */
++    TMDL_HDMITX_VIDCCIR_0_TO_3        = 0x02,   /**< Video signal CCIR, bits 0 to 3 */
++    TMDL_HDMITX_VIDCCIR_11_TO_8       = 0x80,   /**< Video signal CCIR, bits 11 to 8 (mirrored) */
++    TMDL_HDMITX_VIDCCIR_7_TO_4        = 0x81,   /**< Video signal CCIR, bits 7 to 4 (mirrored) */
++    TMDL_HDMITX_VIDCCIR_3_TO_0        = 0x82,   /**< Video signal CCIR, bits 3 to 0 (mirrored) */
++    TMDL_HDMITX_VIDCCIR_NOT_CONNECTED = 0x100   /**< No signal connected */
++} tmdlHdmiTxCfgVideoSignalCCIR656;
++
++#ifdef TMFL_RGB_DDR_12BITS
++/**
++ * \brief Video signals that can be input to video ports in semi-planar CCIR 656 mode
++ */
++typedef enum
++{
++    TMDL_HDMITX_VID_B_0_3_G_4_7        = 0x00,   /**< Video signal blue 0 to 3 then green 4 to 7 */
++    TMDL_HDMITX_VID_B_4_7_R_0_3        = 0x01,   /**< Video signal blue 4 to 7 then red 0 to 3 */
++    TMDL_HDMITX_VID_G_0_3_R_4_7        = 0x02,   /**< Video signal green 0 to 3 then red 4 to 7 */
++    TMDL_HDMITX_VID_DDR_NOT_CONNECTED  = 0x100   /**< No signal connected */
++} tmdlHdmiTxCfgVideoSignal_RGB_DDR_12bits;
++
++/**
++ * \brief Video signals can be mux each others using register 0x27 (MUX_VP_MIX_OUT)
++ * Whatch out that VIP output shall be GBR: green on [23:16], blue on [15:8] and red in [7:0]
++ * this is done by default for all video mode but RGB_DDR_12bits where some extra mux is needed
++ */
++typedef enum
++{
++    VIP_MUX_R_B                        = 0x00,   /**< internal vp_r = vp blue */
++    VIP_MUX_R_G                        = 0x10,   /**< internal vp_r = vp green */
++    VIP_MUX_R_R                        = 0x20,   /**< internal vp_r = vp red */
++    VIP_MUX_G_B                        = 0x00,   /**< internal vp_g = vp blue */
++    VIP_MUX_G_G                        = 0x04,   /**< internal vp_g = vp green */
++    VIP_MUX_G_R                        = 0x08,   /**< internal vp_g = vp red */
++    VIP_MUX_B_B                        = 0x00,   /**< internal vp_b = vp blue */
++    VIP_MUX_B_G                        = 0x01,   /**< internal vp_b = vp green */
++    VIP_MUX_B_R                        = 0x02,   /**< internal vp_b = vp red */
++} tmdlHdmiTxCfgVideoSignal_VIP_OUTPUT_MUX;
++#endif
++
++/* Audio port configuration, bitn = 1 to enable port n, = 0 to disable port n */
++#define ENABLE_ALL_AUDIO_PORT       0xFF
++/* Audio clock port configuration */
++#define ENABLE_AUDIO_CLOCK_PORT     1
++#define DISABLE_AUDIO_CLOCK_PORT    0
++/* Audio port configuration, bitn = 1 to pulldown port n*/
++#define DISABLE_ALL_AUDIO_PORT_PULLDOWN 0x00
++/* Audio clock port pulldown configuration */
++#define ENABLE_AUDIO_CLOCK_PORT_PULLDOWN    1
++#define DISABLE_AUDIO_CLOCK_PORT_PULLDOWN   0
++
++/**
++ * \brief Structure defining a video mode
++ */
++typedef struct _tmdlHdmiTxCfgResolution_t {
++    tmdlHdmiTxVidFmt_t          resolutionID;
++    UInt16                      width;
++    UInt16                      height;
++    Bool                        interlaced;
++    tmdlHdmiTxVfreq_t           vfrequency;
++    tmdlHdmiTxPictAspectRatio_t aspectRatio;
++} tmdlHdmiTxCfgResolution_t, *ptmdlHdmiTxCfgResolution_t;
++
++/**
++ * \brief Structure gathering all configuration parameters
++ */
++typedef struct
++{
++    UInt8                       commandTaskPriority;
++    UInt8                       commandTaskStackSize;
++    UInt8                       commandTaskQueueSize;
++    UInt8                       hdcpTaskPriority;
++    UInt8                       hdcpTaskStackSize;
++    UInt8                       i2cAddress;
++    ptmbslHdmiTxSysFunc_t       i2cReadFunction;
++    ptmbslHdmiTxSysFunc_t       i2cWriteFunction;
++    ptmdlHdmiTxCfgResolution_t  pResolutionInfo;
++    UInt8                       *pMirrorTableCCIR656;
++    UInt8                       *pSwapTableCCIR656;
++    UInt8                       *pEnableVideoPortCCIR656;
++    UInt8                       *pGroundVideoPortCCIR656;
++    UInt8                       *pMirrorTableYUV422;
++    UInt8                       *pSwapTableYUV422;
++    UInt8                       *pEnableVideoPortYUV422;
++    UInt8                       *pGroundVideoPortYUV422;
++    UInt8                       *pMirrorTableYUV444;
++    UInt8                       *pSwapTableYUV444;
++    UInt8                       *pEnableVideoPortYUV444;
++    UInt8                       *pGroundVideoPortYUV444;
++    UInt8                       *pMirrorTableRGB444;
++    UInt8                       *pSwapTableRGB444;
++    UInt8                       *pEnableVideoPortRGB444;
++    UInt8                       *pGroundVideoPortRGB444;
++#ifdef TMFL_RGB_DDR_12BITS
++    UInt8                       *pMirrorTableRGB_DDR_12bits;
++    UInt8                       *pSwapTableRGB_DDR_12bits;
++    UInt8                       *pNoMux;
++    UInt8                       *pMux_RGB_DDR_12bits;
++    UInt8                       *pEnableVideoPortRGB_DDR_12bits;
++    UInt8                       *pGroundVideoPortRGB_DDR_12bits;
++#endif
++    UInt8                       *pEnableAudioPortSPDIF;
++    UInt8                       *pGroundAudioPortSPDIF;
++    UInt8                       *pEnableAudioClockPortSPDIF;
++    UInt8                       *pGroundAudioClockPortSPDIF;
++    UInt8                       *pEnableAudioPortI2S;
++    UInt8                       *pGroundAudioPortI2S;
++    UInt8                       *pEnableAudioPortI2S8C;
++    UInt8                       *pGroundAudioPortI2S8C;
++    UInt8                       *pEnableAudioClockPortI2S;
++    UInt8                       *pGroundAudioClockPortI2S;
++    UInt8                       *pEnableAudioPortOBA;
++    UInt8                       *pGroundAudioPortOBA;
++    UInt8                       *pEnableAudioClockPortOBA;
++    UInt8                       *pGroundAudioClockPortOBA;
++    UInt8                       *pEnableAudioPortDST;
++    UInt8                       *pGroundAudioPortDST;
++    UInt8                       *pEnableAudioClockPortDST;
++    UInt8                       *pGroundAudioClockPortDST;
++    UInt8                       *pEnableAudioPortHBR;
++    UInt8                       *pGroundAudioPortHBR;
++    UInt8                       *pEnableAudioClockPortHBR;
++    UInt8                       *pGroundAudioClockPortHBR;
++    UInt16                      keySeed;
++    tmdlHdmiTxTestPattern_t     pattern;
++    UInt8                       dataEnableSignalAvailable; /* 0 DE is NOT available, 1 DE is there */
++} tmdlHdmiTxDriverConfigTable_t;
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS                               */
++/*============================================================================*/
++
++/* Number of HW units supported by SW driver */
++#define MAX_UNITS 1
++
++#ifdef TMFL_OS_WINDOWS          /* OS Windows */
++extern tmdlHdmiTxCfgVideoSignalCCIR656 videoPortMapping_CCIR656[MAX_UNITS][6];
++extern tmdlHdmiTxCfgVideoSignal422 videoPortMapping_YUV422[MAX_UNITS][6];
++extern tmdlHdmiTxCfgVideoSignal444 videoPortMapping_YUV444[MAX_UNITS][6];
++extern tmdlHdmiTxCfgVideoSignal444 videoPortMapping_RGB444[MAX_UNITS][6];
++#ifdef TMFL_RGB_DDR_12BITS
++extern tmdlHdmiTxCfgVideoSignal_RGB_DDR_12bits VideoPortMapping_RGB_DDR_12bits[MAX_UNITS][6];
++extern UInt8 VideoPortMux_RGB_DDR_12bits[MAX_UNITS];
++extern UInt8 VideoPortNoMux[MAX_UNITS];
++#endif
++#else /* TMFL_OS_WINDOWS */
++extern const tmdlHdmiTxCfgVideoSignalCCIR656 videoPortMapping_CCIR656[MAX_UNITS][6];
++extern const tmdlHdmiTxCfgVideoSignal422 videoPortMapping_YUV422[MAX_UNITS][6];
++extern const tmdlHdmiTxCfgVideoSignal444 videoPortMapping_YUV444[MAX_UNITS][6];
++extern const tmdlHdmiTxCfgVideoSignal444 videoPortMapping_RGB444[MAX_UNITS][6];
++#ifdef TMFL_RGB_DDR_12BITS
++extern const tmdlHdmiTxCfgVideoSignal_RGB_DDR_12bits VideoPortMapping_RGB_DDR_12bits[MAX_UNITS][6];
++extern const UInt8 VideoPortMux_RGB_DDR_12bits[MAX_UNITS];
++extern const UInt8 VideoPortNoMux[MAX_UNITS];
++#endif
++#endif /* TMFL_OS_WINDOWS */
++
++/*============================================================================*/
++/*                          VARIABLES DECLARATIONS                            */
++/*============================================================================*/
++extern tmdlHdmiTxDriverConfigTable_t driverConfigTableTx[MAX_UNITS];
++
++
++/*============================================================================*/
++/*                       FUNCTIONS DECLARATIONS                               */
++/*============================================================================*/
++#ifdef TMFL_CEC_AVAILABLE
++
++#include "tmdlHdmiCEC_Types.h"
++
++typedef struct
++{
++    UInt8                         commandTaskPriority;
++    UInt8                         commandTaskStackSize;
++    UInt8                         commandTaskQueueSize;
++    UInt8                         i2cAddress;
++    ptmdlHdmiCecSysFunc_t         i2cReadFunction;
++    ptmdlHdmiCecSysFunc_t         i2cWriteFunction;
++    tmdlHdmiCecCapabilities_t     *pCapabilitiesList;
++} tmdlHdmiCecDriverConfigTable_t;
++
++tmErrorCode_t tmdlHdmiCecCfgGetConfig
++(
++    tmUnitSelect_t                 unit,
++    tmdlHdmiCecDriverConfigTable_t *pConfig
++);
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMITX_CFG_H */
++
++/*============================================================================*/
++/*                               END OF FILE                                  */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/docs/02_sw_req_an/tmdlHdmiTx_API.zip b/drivers/video/nxp/comps/tmdlHdmiTx/docs/02_sw_req_an/tmdlHdmiTx_API.zip
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+
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx.h b/drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx.h
+new file mode 100755
+index 0000000..d5d34ca
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx.h
+@@ -0,0 +1,52 @@
++/**
++ * Copyright (C) 2007 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx.h
++ *
++ * \version       $Revision: 1 $
++ *
++ * \date          $Date: 02/08/07 08:32 $
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * HDMI Tx Driver - FRS.doc,
++ * HDMI Tx Driver - tmdlHdmiTx - SCS.doc
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   $History: tmdlHdmiTx.h $
++ *
++ * *****************  Version 13  *****************
++ * User: Demoment     Date: 02/08/07   Time: 08:32
++ * Updated in $/Source/tmdlHdmiTx/inc
++ * initial version
++ *
++
++   \endverbatim
++ *
++*/
++
++#ifndef TMDLHDMITX_H
++#define TMDLHDMITX_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++#include "tmNxCompId.h"
++#include "tmdlHdmiTx_Types.h"
++#include "tmdlHdmiTx_Functions.h"
++
++
++#endif /* TMDLHDMITX_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Functions.h b/drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Functions.h
+new file mode 100755
+index 0000000..050645d
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Functions.h
+@@ -0,0 +1,1806 @@
++/**
++ * Copyright (C) 2007 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx_Functions.h
++ *
++ * \version       $Revision: 1 $
++ *
++ * \date          $Date: 02/08/07 8:32 $
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * HDMI Tx Driver - FRS.doc,
++ * HDMI Tx Driver - tmdlHdmiTx - SCS.doc
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   $History: tmdlHdmiTx_Functions.h $
++ *
++ * *****************  Version 1  *****************
++ * User: Demoment     Date: 02/08/07   Time: 8:32
++ * Updated in $/Source/tmdlHdmiTx/inc
++ * initial version
++ *
++
++   \endverbatim
++ *
++*/
++
++#ifndef TMDLHDMITX_FUNCTIONS_H
++#define TMDLHDMITX_FUNCTIONS_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#include "tmNxTypes.h"
++#include "tmdlHdmiTx_Types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       EXTERN FUNCTION PROTOTYPES                           */
++/*============================================================================*/
++
++/*****************************************************************************/
++/**
++    \brief Get the software version of the driver.
++
++    \param pSWVersion Pointer to the version structure.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetSWVersion
++(
++    tmSWVersion_t  *pSWVersion
++);
++
++/*****************************************************************************/
++/**
++    \brief Get the number of available HDMI transmitters devices in the system.
++           A unit directly represents a physical device.
++
++    \param pUnitCount Pointer to the number of available units.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetNumberOfUnits
++(
++    UInt32  *pUnitCount
++);
++
++/*****************************************************************************/
++/**
++    \brief Get the capabilities of unit 0. Capabilities are stored into a
++           dedicated structure and are directly read from the HW device.
++
++    \param pCapabilities Pointer to the capabilities structure.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetCapabilities
++(
++    tmdlHdmiTxCapabilities_t *pCapabilities
++);
++
++/*****************************************************************************/
++/**
++    \brief Get the capabilities of a specific unit. Capabilities are stored
++           into a dedicated structure and are directly read from the HW
++           device.
++
++    \param unit          Unit to be probed.
++    \param pCapabilities Pointer to the capabilities structure.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetCapabilitiesM
++(
++   tmUnitSelect_t            unit,
++   tmdlHdmiTxCapabilities_t *pCapabilities
++);
++
++/*****************************************************************************/
++/**
++    \brief Open unit 0 of HdmiTx driver and provides the instance number to
++           the caller. Note that one unit of HdmiTx represents one physical
++           HDMI transmitter and that only one instance per unit can be opened.
++
++    \param pInstance Pointer to the variable that will receive the instance
++                     identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the transmitter instance is not initialised
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOURCE_OWNED: the resource is already in use
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_INIT_FAILED: the unit instance is already
++              initialised or something wrong happened at lower level.
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: the unit is not initialized
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_HDMI_INIT_FAILED: the unit instance is already
++              initialised
++            - TMBSL_ERR_HDMI_COMPATIBILITY: the driver is not compatiable
++              with the internal device version code
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxOpen
++(
++    tmInstance_t   *pInstance
++);
++
++/*****************************************************************************/
++/**
++    \brief Open a specific unit of HdmiTx driver and provides the instance
++           number to the caller. Note that one unit of HdmiTx represents one
++           physical HDMI transmitter and that only one instance per unit can be
++           opened. This function switches driver's state machine to
++           "initialized" state.
++
++    \param pInstance Pointer to the structure that will receive the instance
++                     identifier.
++    \param unit      Unit number to be opened.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the transmitter instance is not initialised
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOURCE_OWNED: the resource is already in use
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_INIT_FAILED: the unit instance is already
++              initialised or something wrong happened at lower level.
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: the unit is not initialized
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_HDMI_INIT_FAILED: the unit instance is already
++              initialised
++            - TMBSL_ERR_HDMI_COMPATIBILITY: the driver is not compatiable
++              with the internal device version code
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxOpenM
++(
++    tmInstance_t   *pInstance,
++    tmUnitSelect_t  unit
++);
++
++/*****************************************************************************/
++/**
++    \brief Close an instance of HdmiTx driver.
++
++    \param instance Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxClose
++(
++    tmInstance_t   instance
++);
++
++/*****************************************************************************/
++/**
++    \brief Set the power state of an instance of the HDMI transmitter.
++
++    \param instance   Instance identifier.
++    \param powerState Power state to set.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetPowerState
++(
++    tmInstance_t    instance,
++    tmPowerState_t  powerState
++);
++
++/*****************************************************************************/
++/**
++    \brief Get the power state of an instance of the HDMI transmitter.
++
++    \param instance    Instance identifier.
++    \param pPowerState Pointer to the power state.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetPowerState
++(
++    tmInstance_t    instance,
++    tmPowerState_t  *pPowerState
++);
++
++/*****************************************************************************/
++/**
++    \brief Set the configuration of instance attributes. This function is
++           required by DVP architecture rules but actually does nothing in this
++           driver
++
++    \param instance    Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxInstanceConfig
++(
++    tmInstance_t    instance
++);
++
++/*****************************************************************************/
++/**
++    \brief Setup the instance with its configuration parameters. This function
++           allows basic instance configuration like enabling HDCP, choosing
++           HDCP encryption mode or enabling HDCP repeater mode.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure containing all setup parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxInstanceSetup
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxInstanceSetupInfo_t   *pSetupInfo
++);
++
++/*****************************************************************************/
++/**
++    \brief Get instance setup parameters.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure that will receive setup
++                      parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetInstanceSetup
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxInstanceSetupInfo_t   *pSetupInfo
++);
++
++/*****************************************************************************/
++/**
++    \brief Make device library handle an incoming interrupt. This function is
++           used by application to tell the device library that the hardware
++           sent an interrupt.
++
++    \param instance   Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMITX_FULL: the queue is full
++
++ ******************************************************************************/
++tmErrorCode_t tmdlHdmiTxHandleInterrupt
++(
++    tmInstance_t    instance
++);
++
++/*****************************************************************************/
++/**
++    \brief Register event callbacks. Only one callback is registered through
++           this API. This callback will received the type of event that
++           occured throug a dedicated parameter and will be called as many
++           times as there is pending events.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance   Instance identifier.
++    \param pCallback  Pointer to the callback function that will handle events
++                      from the devlib.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxRegisterCallbacks
++(
++    tmInstance_t            instance,
++    ptmdlHdmiTxCallback_t   pCallback
++);
++
++/*****************************************************************************/
++/**
++    \brief This function allows enabling a specific event. By default, all
++           events are disabled, except input lock.
++
++    \param instance Instance identifier.
++    \param event    Event to enable.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxEnableEvent
++(
++    tmInstance_t      instance,
++    tmdlHdmiTxEvent_t event
++);
++
++/*****************************************************************************/
++/**
++    \brief This function allows disabling a specific event. By default, all
++           events are disabled, except input lock.
++
++    \param instance Instance identifier.
++    \param event    Event to disable.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxDisableEvent
++(
++    tmInstance_t      instance,
++    tmdlHdmiTxEvent_t event
++);
++
++/*****************************************************************************/
++/**
++    \brief Get specifications of a given video format. Application can use
++           this function to retreives all specifications (frequencies,
++           resolution, etc.) of a given IA/CEA 861-D video format.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance         Instance identifier.
++    \param resolutionID     ID of the resolution to retrieve specs from.
++    \param pResolutionSpecs Pointer to the structure receiving specs.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOLUTION_UNKNOWN: the resolution is unknown
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetVideoFormatSpecs
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxVidFmt_t      resolutionID,
++    tmdlHdmiTxVidFmtSpecs_t *pResolutionSpecs
++);
++
++/*****************************************************************************/
++/**
++    \brief Configures all input and output parameters : format, modes, rates,
++           etc. This is the main configuration function of the driver. Here
++           are transmitted all crucial input and output parameters of the
++           device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance          Instance identifier.
++    \param videoInputConfig  Configuration of the input video.
++    \param videoOutputConfig Configuration of the output video.
++    \param audioInputConfig  Configuration of the input audio.
++    \param sinkType          Type of sink connected to the output of the Tx.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetInputOutput
++(
++    tmInstance_t               instance,
++    tmdlHdmiTxVideoInConfig_t  videoInputConfig,
++    tmdlHdmiTxVideoOutConfig_t videoOutputConfig,
++    tmdlHdmiTxAudioInConfig_t  audioInputConfig,
++    tmdlHdmiTxSinkType_t       sinkType
++);
++
++/*****************************************************************************/
++/**
++    \brief Configures audio input parameters : format, rate, etc.
++           This function is similar to tmdlHdmiTxSetInputOutput except that
++           video is not reconfigured.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance          Instance identifier.
++    \param audioInputConfig  Configuration of the input audio.
++    \param sinkType          Type of sink connected to the output of the Tx.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetAudioInput
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxAudioInConfig_t   audioInputConfig,
++    tmdlHdmiTxSinkType_t        sinkType
++);
++
++/*****************************************************************************/
++/**
++    \brief Defines the content of AVI infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pAviIfData   Pointer to the structure containing AVI infoframe
++                        parameters. 
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetVideoInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxAviIfData_t   *pAviIfData
++);
++
++/*****************************************************************************/
++/**
++    \brief Defines the content of AUD infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pAudIfData   Pointer to the structure containing AUD infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetAudioInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxAudIfData_t   *pAudIfData
++);
++
++/*****************************************************************************/
++/**
++    \brief Defines the content of the audio content protection packet to be
++           sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pAcpPktData  Pointer to the structure containing ACP infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetACPPacket
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxAcpPktData_t  *pAcpPktData
++);
++
++/*****************************************************************************/
++/**
++    \brief Defines the content of the General Control packet to be sent by Tx
++           device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pGcpPktData  Pointer to the structure containing GCP packet parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetGeneralControlPacket
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxGcpPktData_t  *pGcpPktData
++);
++
++/*****************************************************************************/
++/**
++    \brief Defines the content of ISRC1 packet to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param enable           Enable/disable infoframe insertion.
++    \param pIsrc1PktData    Pointer to the structure containing GCP packet parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetISRC1Packet
++(
++    tmInstance_t                instance,
++    Bool                        enable,
++    tmdlHdmiTxIsrc1PktData_t    *pIsrc1PktData
++);
++
++/*****************************************************************************/
++/**
++    \brief Defines the content of ISRC2 packet to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param enable           Enable/disable infoframe insertion.
++    \param pIsrc2PktData    Pointer to the structure containing GCP packet parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetISRC2Packet
++(
++    tmInstance_t                instance,
++    Bool                        enable,
++    tmdlHdmiTxIsrc2PktData_t    *pIsrc2PktData
++);
++
++/*****************************************************************************/
++/**
++    \brief Defines the content of MPS infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pMpsIfData   Pointer to the structure containing MPS infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetMPSInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxMpsIfData_t   *pMpsIfData
++);
++
++/*****************************************************************************/
++/**
++    \brief Defines the content of SPD infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pSpdIfData   Pointer to the structure containing SPD infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetSpdInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxSpdIfData_t   *pSpdIfData
++);
++
++/*****************************************************************************/
++/**
++    \brief Defines the content of VS infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pVsIfData    Pointer to the structure containing VS infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetVsInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxVsPktData_t   *pVsIfData
++);
++
++/*****************************************************************************/
++/**
++    \brief Enables/disables NULL packet sending (only used for debug purpose).
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance  Instance identifier.
++    \param enable    Enable/disable packet insertion.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxDebugSetNullPacket
++(
++    tmInstance_t    instance,
++    Bool            enable
++);
++
++/*****************************************************************************/
++/**
++    \brief Send one single NULL packet (only used for debug purpose).
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance  Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxDebugSetSingleNullPacket
++(
++    tmInstance_t    instance
++);
++
++/*****************************************************************************/
++/**
++    \brief Set the audio output mute status. This function can be used to mute
++           audio output, without muting video. This can be typically used when
++           reconfiguring the audio HW after a sample rate change.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance   Instance identifier.
++    \param muteStatus Mute status (True/False).
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetAudioMute
++(
++    tmInstance_t instance,
++    Bool         audioMute
++);
++
++/*****************************************************************************/
++/**
++    \brief Reset audio CTS.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance   Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxResetAudioCts
++(
++    tmInstance_t instance
++);
++
++/*****************************************************************************/
++/**
++    \brief Retrieve EDID Status from driver.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pEdidStatus      Pointer to the array that will receive the EDID Status.
++    \param pEdidBlkCount    Pointer to the integer that will receive the number of
++                            read EDID block.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidStatus
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxEdidStatus_t  *pEdidStatus,
++    UInt8                   *pEdidBlkCount
++);
++
++/*****************************************************************************/
++/**
++    \brief Retrieves audio descriptors from receiver's EDID. This function
++           parses the EDID of Tx device to get the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++
++    \param instance             Instance identifier.
++    \param pAudioDescs          Pointer to the array that will receive audio
++                                descriptors.
++    \param maxAudioDescs        Size of the array.
++    \param pWrittenAudioDescs   Pointer to the integer that will receive the actual
++                                number of written descriptors.
++    \param pAudioFlags          Pointer to the byte to receive Audio Capabilities Flags.
++                                This byte is filled as such:
++                                b7    is the Basic audio bit from CEA Extension Version 3.    
++                                If this bit is set to 1 this means that the sink handles "Basic audio" i.e.
++                                two channel L-PCM audio at sample rates of 32kHz, 44.1kHz, and 48kHz.
++                                b6    is the Supports_AI bit from the VSDB
++                                This bit set to 1 if the sink supports at least one function that uses
++                                information carried by the ACP, ISRC1, or ISRC2 packets.
++                                b5-b0    0
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidAudioCaps
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxEdidAudioDesc_t   *pAudioDescs,
++    UInt                        maxAudioDescs,
++    UInt                        *pWrittenAudioDescs,
++    UInt8                       *pAudioFlags
++);
++
++/*****************************************************************************/
++/**
++    \brief Retrieves supported video formats (short descriptors) from
++           receiver's EDID. This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance             Instance identifier.
++    \param pVideoDesc           Pointer to the structure that will receive short
++                                video descriptors.
++    \param maxVideoFormats      Size of the array.
++    \param pWrittenVideoFormats Pointer to the integer that will receive the actual
++                                number of written descriptors.
++    \param pVideoFlags          Pointer to the byte to receive Video Capability Flags.
++                                b7: underscan supported
++                                b6: YCbCr 4:4:4 supported
++                                b5: YCbCr 4:2:2 supported
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidVideoCaps
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxShortVidDesc_t    *pVideoDesc,
++    UInt                        maxVideoFormats,
++    UInt                        *pWrittenVideoFormats,
++    UInt8                       *pVideoFlags
++);
++
++/*****************************************************************************/
++/**
++    \brief Retrieves supported video formats (short descriptors) from
++           receiver's EDID. This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance                 Instance identifier.
++    \param pNativeVideoFormat    Pointer to the array that will receive video
++                                    timing descriptor.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidVideoPreferred
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxEdidVideoTimings_t    *pNativeVideoFormat
++);
++
++/*****************************************************************************/
++/**
++    \brief Retrieves the sink type from receiver's EDID (HDMI or DVI). This
++           function parses the EDID of Rx device to get the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance  Instance identifier.
++    \param pSinkType Pointer to the array that will receive sink type.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMDL_ERR_DLHDMITX_NOT_INITIALIZED: the transmitter is not initialized
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidSinkType
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxSinkType_t    *pSinkType
++);
++
++/*****************************************************************************/
++/**
++    \brief Retrieves source address from receivers's EDID. This
++           function parses the EDID of Rx device to get the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pSourceAddress   Pointer to the integer that will receive the EDID source
++                            address.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidSourceAddress
++(
++    tmInstance_t    instance,
++    UInt16          *pSourceAddress
++);
++
++
++
++/*****************************************************************************/
++/**
++    \brief Retreives KSV list received by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param pKsv         Pointer to the array that will receive the KSV list.
++    \param maxKsv       Maximum number of KSV that the array can store.
++    \param pWrittenKsv  Actual number of KSV written into the array.
++    \param pDepth       Connection tree depth.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetKsvList
++(
++    tmInstance_t    instance,
++    UInt8           *pKsv,
++    UInt8           maxKsv,
++    UInt8           *pWrittenKsv,
++    UInt8           *pDepth,
++    Bool            *pMaxCascExd,
++    Bool            *pMaxDevsExd
++);
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++/******************************************************************************
++    \brief Retreives HDCP depth received by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param pDepth       Connection tree depth returned with KSV list.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetDepth(
++    tmInstance_t    instance,
++    UInt8           *pDepth
++);
++
++/******************************************************************************
++    \brief Generate SHA_1 interrupt if not occured.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGeneSHA_1_IT
++(
++    tmInstance_t    instance
++);
++#endif /* HDMI_TX_REPEATER_ISR_MODE */
++/*****************************************************************************/
++/**
++    \brief Enable/Disable HDCP encryption.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance   Instance identifier.
++    \param hdcpEnable HDCP On/Off (true = On, False = Off).
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_RESOLUTION_UNKNOWN: the resolution is unknown
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetHdcp
++(
++    tmInstance_t instance,
++    Bool         hdcpEnable
++);
++
++/*****************************************************************************/
++/**
++    \brief Get the driver HDCP state.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance          Instance identifier.
++    \param pHdcpCheckState   Pointer to the integer that will receive the HDCP check state.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetHdcpState
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxHdcpCheck_t   *pHdcpCheckState
++);
++
++/*****************************************************************************/
++/**
++    \brief Check the result of an HDCP encryption attempt, called at
++           intervals (set by timeSinceLastCall) after tmdlHdmiTxSetHdcp(true).
++           This API must be used only in case of No Operating System. if OS, 
++           this is manage internally of this device library.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance             Instance identifier.
++    \param timeSinceLastCall    Time passed in milliseconds since last call,
++                                must be shorter than 600 ms.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++            - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxHdcpCheck
++(
++    tmInstance_t    instance,
++    UInt16          timeSinceLastCall
++);
++
++/*****************************************************************************/
++/**
++    \brief This function loads a gamut metadata packet into the HW. HW will
++           actually send it at the beginning of next VS, during the vertical
++           blanking.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable gamut metadata packet insertion.
++    \param pGamutData   Pointer to the structure containing gamut metadata
++                        parameters. 
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetGamutPacket
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxGamutData_t   *pGamutData
++);
++
++/*****************************************************************************/
++/**
++    \brief This function set the extended colorimetry with one of the following 
++           extended colorimetries(bits EC2-0): xvYCC601, xvYCC709, sYCC601, 
++           AdobeYCC601, AdobeRGB. When the parameter extendedColorimetry is 
++           xvYCC601 or xvYCC70, this function calls the API tmdlHdmiTxSetGamutPacket
++           to send Gamut Packet Data that does not exist for all other types of
++           extended colorimetries for which pointer pGamutData can be set to NULL.
++           This function also allows to set YCC Quantization Range (YQ1-0)
++           
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance              Instance identifier.
++    \param enable                Enable/Disable extended colorimetry.
++    \param extendedColorimetry   value of the extended colorimetry (bits EC2 EC1 EC0). 
++    \param yccQR                 YCC quantisation range
++    \param pGamutData            Pointer to the structure containing gamut metadata
++                                 parameters. 
++
++    \return The call result:
++           - TM_OK: the call was successful
++           - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong
++           - TMDL_ERR_DLHDMITX_BAD_PARAMETER: a parameter was out of range
++           - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for the function
++           - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++           - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++           - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++           - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++           - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++           - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetExtendedColorimetry
++(
++    tmInstance_t                 instance,
++    Bool                         enable,
++    tmdlHdmiTxExtColorimetry_t   extendedColorimetry,
++    tmdlHdmiTxYCCQR_t            yccQR,
++    tmdlHdmiTxGamutData_t        *pGamutData
++);
++
++/*****************************************************************************/
++/**
++    \brief Retrieves supported detailled video descriptors from
++           receiver's EDID. This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pDTDescriptors   Pointer to the array that will receive detailled 
++                            timing descriptors.
++    \param maxDTDesc        Size of the array.
++    \param pWrittenDesc     Pointer to the integer that will receive the actual
++                            number of written descriptors.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidDetailledTimingDescriptors
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    UInt8                           maxDTDesc,
++    UInt8                           *pWrittenDTDesc
++);
++
++/*****************************************************************************/
++/**
++    \brief Retrieves supported monitor descriptor from receiver's EDID.
++           This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pEdidFirstMD     Pointer to the array that will receive the first monitor
++                            descriptors.
++    \param pEdidSecondMD    Pointer to the array that will receive the second monitor
++                            descriptors.
++    \param pEdidOtherMD     Pointer to the array that will receive the other monitor
++                            descriptors.
++    \param maxOtherMD       Size of the array.
++    \param pWrittenOtherMD  Pointer to the integer that will receive the actual
++                            number of written descriptors.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidMonitorDescriptors
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxEdidFirstMD_t     *pEdidFirstMD,
++    tmdlHdmiTxEdidSecondMD_t    *pEdidSecondMD,
++    tmdlHdmiTxEdidOtherMD_t     *pEdidOtherMD,
++    UInt8                       maxOtherMD,
++    UInt8                       *pWrittenOtherMD
++);
++
++/*****************************************************************************/
++/**
++    \brief Retrieves TV picture ratio from receiver's EDID. 
++           This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance             Instance identifier.
++    \param pEdidTvPictureRatio  Pointer to the variable that will receive TV picture ratio
++                                value.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidTVPictureRatio
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxPictAspectRatio_t     *pEdidTvPictureRatio
++);
++
++/******************************************************************************
++    \brief This function set the revocation list use for HDCP
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param listPtr      Pointer on revocation list provide by application.
++    \param length       length of revocation list. 
++
++    \return The call result:
++            - TM_OK: the call was successful, however RX keys have
++                     not been checked with provided revocation list
++                     because they are not available.
++            - TMDL_DLHDMITX_HDCP_SECURE: the call was successful, RX keys are secure
++            - TMDL_DLHDMITX_HDCP_NOT_SECURE: the call was successful, RX keys are NOT secure
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: we are a repeater                             
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++
++******************************************************************************/
++
++tmErrorCode_t tmdlHdmiTxSetHDCPRevocationList(
++    tmInstance_t    instance,
++    void            *listPtr, 
++    UInt32          length
++);
++
++
++/*****************************************************************************/
++/**
++    \brief Retreives current HDCP link status. This function is typically used
++           when an "HDCP INACTIVE" event is received to know why HDCP 
++           is INACTIVE.
++
++    \param instance    Instance identifier.
++    \param pHdcpStatus Pointer to the enum describing the status.
++    \param pRawStatus  Pointer to the byte with the raw error code from HW.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMITX_NOT_INITIALIZED: the transmitter is not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetHdcpFailStatus
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxHdcpStatus_t *pHdcpStatus,
++    UInt8                  *pRawStatus
++);
++
++
++/*****************************************************************************/
++/**
++    \brief Retrieves latency information from receiver's EDID.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++
++    \param instance             Instance identifier.
++    \param pLatency             Pointer to the data structure that receive latency
++                                information.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidLatencyInfo
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxEdidLatency_t    *pLatency
++);
++
++
++/******************************************************************************
++    \brief Retrieves additional data from receiver's EDID VSDB. This function 
++           parses the EDID of Rx device to get the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance             Instance identifier.
++    \param pExtraVsdbData       Pointer to the structure of additional VSDB data 
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidExtraVsdbData
++(
++    tmInstance_t                     instance,
++    tmdlHdmiTxEdidExtraVsdbData_t    **pExtraVsdbData
++);
++
++
++/******************************************************************************
++    \brief This function set the B... screen
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful, however RX keys have
++                     not been checked with provided revocation list
++                     because they are not available.
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++
++
++******************************************************************************/
++
++tmErrorCode_t tmdlHdmiTxSetBScreen(
++    tmInstance_t            instance,
++    tmdlHdmiTxTestPattern_t pattern
++);
++
++/******************************************************************************
++    \brief This function set the Remove B.... screen
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier. 
++
++    \return The call result:
++            - TM_OK: the call was successful, however RX keys have
++                     not been checked with provided revocation list
++                     because they are not available.
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++
++
++******************************************************************************/
++
++tmErrorCode_t tmdlHdmiTxRemoveBScreen(
++    tmInstance_t    instance
++);
++
++/******************************************************************************
++    \brief This function Convert DTD to CEA
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier. 
++    \param pDTDescriptors   Pointer on one DTD 
++    \return The call result:
++            - CEA code
++
++
++******************************************************************************/
++tmdlHdmiTxVidFmt_t tmdlHdmiTxConvertDTDtoCEA
++(
++    tmInstance_t    instance,
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors
++);
++
++
++/*****************************************************************************/
++/**
++    \brief Retrieve HPD status from driver.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pHPDStatus       Pointer to the variable that will receive the HPD Status.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetHPDStatus
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxHotPlug_t *   pHPDStatus
++);
++
++
++/*****************************************************************************/
++/**
++    \brief Retrieve RXSense status from driver.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pRXSenseStatus   Pointer to the variable that will receive the RXSense Status.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetRXSenseStatus
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxRxSense_t *   pRXSenseStatus
++);
++
++
++/******************************************************************************
++    \brief Mute or unmute the TMDS outputs.
++
++    \param instance         Instance identifier.
++    \param muteTmdsOut      Mute or unmute indication.
++
++    \return NA.
++    
++******************************************************************************/   
++tmErrorCode_t tmdlHdmiTxTmdsSetOutputsMute
++(
++    tmInstance_t            instance,
++    Bool                    muteTmdsOut
++);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMITX_FUNCTIONS_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Types.h b/drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Types.h
+new file mode 100755
+index 0000000..f090ce2
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Types.h
+@@ -0,0 +1,1066 @@
++/**
++ * Copyright (C) 2007 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx_Types.h
++ *
++ * \version       $Revision: 1 $
++ *
++ * \date          $Date: 02/08/07 08:32 $
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * HDMI Tx Driver - FRS.doc,
++ * HDMI Tx Driver - tmdlHdmiTx - SCS.doc
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   $History: tmdlHdmiTx_Types.h $
++ *
++ * *****************  Version 1  *****************
++ * User: Demoment     Date: 02/08/07   Time: 08:32
++ * Updated in $/Source/tmdlHdmiTx/inc
++ * initial version
++
++   \endverbatim
++ *
++*/
++
++#ifndef TMDLHDMITX_TYPES_H
++#define TMDLHDMITX_TYPES_H
++
++/*============================================================================*/
++/*                       INCLUDE FILES                                        */
++/*============================================================================*/
++
++#include "tmNxTypes.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                       MACRO DEFINITIONS                                    */
++/*============================================================================*/
++
++/*============================================================================*/
++/*                                DEFINES                                     */
++/*============================================================================*/
++
++/**< Error Codes */
++#define TMDL_ERR_DLHDMITX_BASE                      CID_DL_HDMITX
++#define TMDL_ERR_DLHDMITX_COMP                      (TMDL_ERR_DLHDMITX_BASE | TM_ERR_COMP_UNIQUE_START)
++
++#define TMDL_ERR_DLHDMITX_COMPATIBILITY             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_COMPATIBILITY)             /**< SW Interface compatibility   */
++#define TMDL_ERR_DLHDMITX_MAJOR_VERSION             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_MAJOR_VERSION)             /**< SW Major Version error       */
++#define TMDL_ERR_DLHDMITX_COMP_VERSION              (TMDL_ERR_DLHDMITX_BASE + TM_ERR_COMP_VERSION)              /**< SW component version error   */
++#define TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER           (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_UNIT_NUMBER)           /**< Invalid device unit number   */
++#define TMDL_ERR_DLHDMITX_BAD_INSTANCE              (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_INSTANCE)              /**< Bad input instance value     */
++#define TMDL_ERR_DLHDMITX_BAD_HANDLE                (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_HANDLE)                /**< Bad input handle             */
++#define TMDL_ERR_DLHDMITX_BAD_PARAMETER             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_PARAMETER)             /**< Invalid input parameter      */
++#define TMDL_ERR_DLHDMITX_NO_RESOURCES              (TMDL_ERR_DLHDMITX_BASE + TM_ERR_NO_RESOURCES)              /**< Resource is not available    */
++#define TMDL_ERR_DLHDMITX_RESOURCE_OWNED            (TMDL_ERR_DLHDMITX_BASE + TM_ERR_RESOURCE_OWNED)            /**< Resource is already in use   */
++#define TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED        (TMDL_ERR_DLHDMITX_BASE + TM_ERR_RESOURCE_NOT_OWNED)        /**< Caller does not own resource */
++#define TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS       (TMDL_ERR_DLHDMITX_BASE + TM_ERR_INCONSISTENT_PARAMS)       /**< Inconsistent input params    */
++#define TMDL_ERR_DLHDMITX_NOT_INITIALIZED           (TMDL_ERR_DLHDMITX_BASE + TM_ERR_NOT_INITIALIZED)           /**< Component is not initialized */
++#define TMDL_ERR_DLHDMITX_NOT_SUPPORTED             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_NOT_SUPPORTED)             /**< Function is not supported    */
++#define TMDL_ERR_DLHDMITX_INIT_FAILED               (TMDL_ERR_DLHDMITX_BASE + TM_ERR_INIT_FAILED)               /**< Initialization failed        */
++#define TMDL_ERR_DLHDMITX_BUSY                      (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BUSY)                      /**< Component is busy            */
++#define TMDL_ERR_DLHDMITX_I2C_READ                  (TMDL_ERR_DLHDMITX_BASE + TM_ERR_READ)                      /**< Read error                   */
++#define TMDL_ERR_DLHDMITX_I2C_WRITE                 (TMDL_ERR_DLHDMITX_BASE + TM_ERR_WRITE)                     /**< Write error                  */
++#define TMDL_ERR_DLHDMITX_FULL                      (TMDL_ERR_DLHDMITX_BASE + TM_ERR_FULL)                      /**< Queue is full                */
++#define TMDL_ERR_DLHDMITX_NOT_STARTED               (TMDL_ERR_DLHDMITX_BASE + TM_ERR_NOT_STARTED)               /**< Function is not started      */
++#define TMDL_ERR_DLHDMITX_ALREADY_STARTED           (TMDL_ERR_DLHDMITX_BASE + TM_ERR_ALREADY_STARTED)           /**< Function is already started  */
++#define TMDL_ERR_DLHDMITX_ASSERTION                 (TMDL_ERR_DLHDMITX_BASE + TM_ERR_ASSERTION)                 /**< Assertion failure            */
++#define TMDL_ERR_DLHDMITX_INVALID_STATE             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_INVALID_STATE)             /**< Invalid state for function   */
++#define TMDL_ERR_DLHDMITX_OPERATION_NOT_PERMITTED   (TMDL_ERR_DLHDMITX_BASE + TM_ERR_OPERATION_NOT_PERMITTED)   /**< Corresponds to posix EPERM   */
++#define TMDL_ERR_DLHDMITX_RESOLUTION_UNKNOWN        (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_FORMAT)                /**< Bad format                   */
++
++#define TMDL_DLHDMITX_HDCP_SECURE               (TMDL_ERR_DLHDMITX_COMP + 0x0001) /**< Revocation list is secure */
++#define TMDL_DLHDMITX_HDCP_NOT_SECURE           (TMDL_ERR_DLHDMITX_COMP + 0x0002) /**< Revocation list is NOT secure */
++
++
++/*============================================================================*/
++/*                       ENUM OR TYPE DEFINITIONS                             */
++/*============================================================================*/
++
++/**
++ * \brief Enum listing all events that can be signalled to application
++ */
++typedef enum
++{
++    TMDL_HDMITX_HDCP_ACTIVE         = 0,    /**< HDCP encryption status switched to active */
++    TMDL_HDMITX_HDCP_INACTIVE       = 1,    /**< HDCP encryption status switched to inactive */
++    TMDL_HDMITX_HPD_ACTIVE          = 2,    /**< Hotplug status switched to active */
++    TMDL_HDMITX_HPD_INACTIVE        = 3,    /**< Hotplug status switched to inactive */
++    TMDL_HDMITX_RX_KEYS_RECEIVED    = 4,    /**< Receiver(s) key(s) received */
++    TMDL_HDMITX_RX_DEVICE_ACTIVE    = 5,    /**< Rx device is connected and active */
++    TMDL_HDMITX_RX_DEVICE_INACTIVE  = 6,    /**< Rx device is connected but inactive (standby) */
++    TMDL_HDMITX_EDID_RECEIVED       = 7,    /**< EDID has been received */
++    TMDL_HDMITX_VS_RPT_RECEIVED     = 8,    /**< VS interrupt has been received */              
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++    TMDL_HDMITX_B_STATUS            = 9,    /**< TX received BStatus */
++#endif /* HDMI_TX_REPEATER_ISR_MODE */
++    TMDL_HDMITX_DEBUG_EVENT_1       = 10     /**< This is a debug event */
++} tmdlHdmiTxEvent_t;
++
++/**
++ * \brief Enum listing all available event status
++ */
++typedef enum
++{
++    TMDL_HDMITX_EVENT_ENABLED,  /**< Event is enabled */
++    TMDL_HDMITX_EVENT_DISABLED  /**< Event is disabled */
++} tmdlHdmiTxEventStatus_t;
++
++/**
++ * \brief Callback function pointer type, used to allow driver to callback
++          application when activity status is changing at input.
++ * \param Event Identifier of the source event.
++ */
++typedef void (*ptmdlHdmiTxCallback_t) (tmdlHdmiTxEvent_t event);
++
++/**
++ * \brief Enum listing all supported device versions
++ */
++ typedef enum
++ {
++     TMDL_HDMITX_DEVICE_UNKNOWN,   /**< HW device is unknown */
++     TMDL_HDMITX_DEVICE_TDA9984,   /**< HW device is IC TDA9984 */
++     TMDL_HDMITX_DEVICE_TDA9989,   /**< HW device is IC TDA9989 */
++     TMDL_HDMITX_DEVICE_TDA9981,   /**< HW device is IC TDA9981 */
++     TMDL_HDMITX_DEVICE_TDA9983,   /**< HW device is IC TDA9983 */
++     TMDL_HDMITX_DEVICE_TDA19989,  /**< HW device is IC TDA19989 */
++     TMDL_HDMITX_DEVICE_TDA19988   /**< ok, u got it, it's a TDA19988 */
++ } tmdlHdmiTxDeviceVersion_t;
++
++/**
++ * \brief Enum defining the supported HDMI standard version
++ */
++typedef enum
++{
++   TMDL_HDMITX_HDMI_VERSION_UNKNOWN, /**< Unknown   */
++   TMDL_HDMITX_HDMI_VERSION_1_1,     /**< HDMI 1.1  */
++   TMDL_HDMITX_HDMI_VERSION_1_2a,    /**< HDMI 1.2a */
++   TMDL_HDMITX_HDMI_VERSION_1_3a     /**< HDMI 1.3  */
++} tmdlHdmiTxHdmiVersion_t;
++
++/**
++ * \brief Enum listing all color depth (8 bits/color, 10 bits/color, etc.)
++ */
++typedef enum
++{
++    TMDL_HDMITX_COLORDEPTH_24   = 0,    /**< 8 bits per color */
++    TMDL_HDMITX_COLORDEPTH_30   = 1,    /**< 10 bits per color */
++    TMDL_HDMITX_COLORDEPTH_36   = 2,    /**< 12 bits per color */
++    TMDL_HDMITX_COLORDEPTH_48   = 3     /**< 16 bits per color */
++} tmdlHdmiTxColorDepth_t;
++
++/**
++ * \brief Enum defining the EDID Status
++ */
++typedef enum
++{
++    TMDL_HDMITX_EDID_READ                = 0,   /**< All blocks read OK */
++    TMDL_HDMITX_EDID_READ_INCOMPLETE     = 1,   /**< All blocks read OK but buffer too small to return all of them */
++    TMDL_HDMITX_EDID_ERROR_CHK_BLOCK_0   = 2,   /**< Block 0 checksum error */
++    TMDL_HDMITX_EDID_ERROR_CHK           = 3,   /**< Block 0 OK, checksum error in one or more other blocks */
++    TMDL_HDMITX_EDID_NOT_READ            = 4,   /**< EDID not read */
++    TMDL_HDMITX_EDID_STATUS_INVALID      = 5    /**< Invalid   */
++} tmdlHdmiTxEdidStatus_t;
++
++/**
++ * \brief Structure defining the supported audio packets
++ */
++typedef struct
++{
++   Bool HBR;              /**< High Bitrate Audio packet */
++   Bool DST;              /**< Direct Stream Transport audio packet */
++   Bool oneBitAudio;      /**< One Bit Audio sample packet */
++} tmdlHdmiTxAudioPacket_t;
++
++/**
++ * \brief Enum listing all possible audio input formats
++ */
++typedef enum
++{
++    TMDL_HDMITX_AFMT_SPDIF      = 0, /**< SPDIF */
++    TMDL_HDMITX_AFMT_I2S        = 1, /**< I2S */
++    TMDL_HDMITX_AFMT_OBA        = 2, /**< One bit audio / DSD */
++    TMDL_HDMITX_AFMT_DST        = 3, /**< DST */
++    TMDL_HDMITX_AFMT_HBR        = 4  /**< HBR */
++} tmdlHdmiTxAudioFormat_t;
++
++/**
++ * \brief Enum listing all possible audio input sample rates
++ */
++typedef enum
++{
++    TMDL_HDMITX_AFS_32K           = 0, /**< 32kHz    */
++    TMDL_HDMITX_AFS_44K           = 1, /**< 44.1kHz  */
++    TMDL_HDMITX_AFS_48K           = 2, /**< 48kHz    */
++    TMDL_HDMITX_AFS_88K           = 3, /**< 88.2kHz  */
++    TMDL_HDMITX_AFS_96K           = 4, /**< 96kHz    */
++    TMDL_HDMITX_AFS_176K          = 5, /**< 176.4kHz */
++    TMDL_HDMITX_AFS_192K          = 6  /**< 192kHz   */
++} tmdlHdmiTxAudioRate_t;
++
++/**
++ * \brief Enum listing all possible audio input sample rates
++ */
++typedef enum
++{
++    TMDL_HDMITX_I2SQ_16BITS       = 16, /**< 16 bits */
++    TMDL_HDMITX_I2SQ_32BITS       = 32, /**< 32 bits */
++    TMDL_HDMITX_I2SQ_OTHERS       = 0   /**< for SPDIF and DSD */
++} tmdlHdmiTxAudioI2SQualifier_t;
++
++/**
++ * \brief Enum listing all possible audio I2S formats
++ */
++typedef enum
++{
++    TMDL_HDMITX_I2SFOR_PHILIPS_L   = 0,	/**< Philips like format */
++    TMDL_HDMITX_I2SFOR_OTH_L       = 2,	/**< Other non Philips left justified */
++    TMDL_HDMITX_I2SFOR_OTH_R	   = 3,	/**< Other non Philips right justified */
++    TMDL_HDMITX_I2SFOR_INVALID     = 4	/**< Invalid format */
++} tmdlHdmiTxAudioI2SFormat_t;
++
++/**
++ * \brief Enum listing all possible DST data transfer rates 
++ */
++typedef enum
++{
++    TMDL_HDMITX_DSTRATE_SINGLE  = 0,    /**< Single transfer rate */
++    TMDL_HDMITX_DSTRATE_DOUBLE  = 1     /**< Double data rate */
++} tmdlHdmiTxDstRate_t;
++
++/**
++ * \brief Structure describing unit capabilities
++ */
++typedef struct
++{
++    tmdlHdmiTxDeviceVersion_t   deviceVersion;  /**< HW device version */
++    tmdlHdmiTxHdmiVersion_t     hdmiVersion;    /**< Supported HDMI standard version  */
++    tmdlHdmiTxAudioPacket_t     audioPacket;    /**< Supported audio packets */
++    tmdlHdmiTxColorDepth_t      colorDepth;     /**< Supported color depth */
++    Bool                        hdcp;           /**< Supported Hdcp encryption (True/False) */
++	Bool                        scaler;         /**< Supported scaler (True/False) */
++} tmdlHdmiTxCapabilities_t;
++
++/**
++ * \brief Structure gathering all instance setup parameters
++ */
++typedef struct
++{
++    Bool    simplayHd;          /**< Enable simplayHD support */
++    Bool    repeaterEnable;     /**< Enable repeater mode */
++    UInt8   *pEdidBuffer;       /**< Pointer to raw EDID data */
++    UInt32  edidBufferSize;     /**< Size of buffer for raw EDID data */
++} tmdlHdmiTxInstanceSetupInfo_t;
++
++/**
++ * \brief Enum listing all IA/CEA 861-D video formats
++ */
++typedef enum
++{
++    TMDL_HDMITX_VFMT_NULL               = 0,    /**< Not a valid format...        */
++    TMDL_HDMITX_VFMT_NO_CHANGE          = 0,    /**< ...or no change required     */
++    TMDL_HDMITX_VFMT_MIN                = 1,    /**< Lowest valid format          */
++    TMDL_HDMITX_VFMT_TV_MIN             = 1,    /**< Lowest valid TV format       */
++    TMDL_HDMITX_VFMT_01_640x480p_60Hz   = 1,    /**< Format 01 640  x 480p  60Hz  */
++    TMDL_HDMITX_VFMT_02_720x480p_60Hz   = 2,    /**< Format 02 720  x 480p  60Hz  */
++    TMDL_HDMITX_VFMT_03_720x480p_60Hz   = 3,    /**< Format 03 720  x 480p  60Hz  */
++    TMDL_HDMITX_VFMT_04_1280x720p_60Hz  = 4,    /**< Format 04 1280 x 720p  60Hz  */
++    TMDL_HDMITX_VFMT_05_1920x1080i_60Hz = 5,    /**< Format 05 1920 x 1080i 60Hz  */
++    TMDL_HDMITX_VFMT_06_720x480i_60Hz   = 6,    /**< Format 06 720  x 480i  60Hz  */
++    TMDL_HDMITX_VFMT_07_720x480i_60Hz   = 7,    /**< Format 07 720  x 480i  60Hz  */
++    TMDL_HDMITX_VFMT_08_720x240p_60Hz   = 8,    /**< Format 08 720  x 240p  60Hz  */
++    TMDL_HDMITX_VFMT_09_720x240p_60Hz   = 9,    /**< Format 09 720  x 240p  60Hz  */
++    TMDL_HDMITX_VFMT_10_720x480i_60Hz   = 10,   /**< Format 10 720  x 480i  60Hz  */
++    TMDL_HDMITX_VFMT_11_720x480i_60Hz   = 11,   /**< Format 11 720  x 480i  60Hz  */
++    TMDL_HDMITX_VFMT_12_720x240p_60Hz   = 12,   /**< Format 12 720  x 240p  60Hz  */
++    TMDL_HDMITX_VFMT_13_720x240p_60Hz   = 13,   /**< Format 13 720  x 240p  60Hz  */
++    TMDL_HDMITX_VFMT_14_1440x480p_60Hz  = 14,   /**< Format 14 1440 x 480p  60Hz  */
++    TMDL_HDMITX_VFMT_15_1440x480p_60Hz  = 15,   /**< Format 15 1440 x 480p  60Hz  */
++    TMDL_HDMITX_VFMT_16_1920x1080p_60Hz = 16,   /**< Format 16 1920 x 1080p 60Hz  */
++    TMDL_HDMITX_VFMT_17_720x576p_50Hz   = 17,   /**< Format 17 720  x 576p  50Hz  */
++    TMDL_HDMITX_VFMT_18_720x576p_50Hz   = 18,   /**< Format 18 720  x 576p  50Hz  */
++    TMDL_HDMITX_VFMT_19_1280x720p_50Hz  = 19,   /**< Format 19 1280 x 720p  50Hz  */
++    TMDL_HDMITX_VFMT_20_1920x1080i_50Hz = 20,   /**< Format 20 1920 x 1080i 50Hz  */
++    TMDL_HDMITX_VFMT_21_720x576i_50Hz   = 21,   /**< Format 21 720  x 576i  50Hz  */
++    TMDL_HDMITX_VFMT_22_720x576i_50Hz   = 22,   /**< Format 22 720  x 576i  50Hz  */
++    TMDL_HDMITX_VFMT_23_720x288p_50Hz   = 23,   /**< Format 23 720  x 288p  50Hz  */
++    TMDL_HDMITX_VFMT_24_720x288p_50Hz   = 24,   /**< Format 24 720  x 288p  50Hz  */
++    TMDL_HDMITX_VFMT_25_720x576i_50Hz   = 25,   /**< Format 25 720  x 576i  50Hz  */
++    TMDL_HDMITX_VFMT_26_720x576i_50Hz   = 26,   /**< Format 26 720  x 576i  50Hz  */
++    TMDL_HDMITX_VFMT_27_720x288p_50Hz   = 27,   /**< Format 27 720  x 288p  50Hz  */
++    TMDL_HDMITX_VFMT_28_720x288p_50Hz   = 28,   /**< Format 28 720  x 288p  50Hz  */
++    TMDL_HDMITX_VFMT_29_1440x576p_50Hz  = 29,   /**< Format 29 1440 x 576p  50Hz  */
++    TMDL_HDMITX_VFMT_30_1440x576p_50Hz  = 30,   /**< Format 30 1440 x 576p  50Hz  */
++    TMDL_HDMITX_VFMT_31_1920x1080p_50Hz = 31,   /**< Format 31 1920 x 1080p 50Hz  */
++    TMDL_HDMITX_VFMT_32_1920x1080p_24Hz = 32,   /**< Format 32 1920 x 1080p 24Hz  */
++    TMDL_HDMITX_VFMT_33_1920x1080p_25Hz = 33,   /**< Format 33 1920 x 1080p 25Hz  */
++    TMDL_HDMITX_VFMT_34_1920x1080p_30Hz = 34,   /**< Format 34 1920 x 1080p 30Hz  */
++    TMDL_HDMITX_VFMT_35_2880x480p_60Hz  = 35,   /**< Format 35 2880 x 480p  60Hz 4:3  */
++    TMDL_HDMITX_VFMT_36_2880x480p_60Hz  = 36,   /**< Format 36 2880 x 480p  60Hz 16:9 */
++    TMDL_HDMITX_VFMT_37_2880x576p_50Hz  = 37,   /**< Format 37 2880 x 576p  50Hz 4:3  */
++    TMDL_HDMITX_VFMT_38_2880x576p_50Hz  = 38,   /**< Format 38 2880 x 576p  50Hz 16:9 */
++
++    TMDL_HDMITX_VFMT_INDEX_60_1280x720p_24Hz = 39,/**< Index of HDMITX_VFMT_60_1280x720p_24Hz */
++    TMDL_HDMITX_VFMT_60_1280x720p_24Hz  = 60,   /**< Format 60 1280 x 720p  23.97/24Hz 16:9 */
++    TMDL_HDMITX_VFMT_61_1280x720p_25Hz  = 61,   /**< Format 61 1280 x 720p  25Hz 16:9 */
++    TMDL_HDMITX_VFMT_62_1280x720p_30Hz  = 62,   /**< Format 60 1280 x 720p  29.97/30Hz 16:9 */
++
++    TMDL_HDMITX_VFMT_TV_MAX             = 62,   /**< Highest valid TV format      */
++    TMDL_HDMITX_VFMT_TV_NO_REG_MIN      = 32,   /**< Lowest TV format without prefetched table */
++    TMDL_HDMITX_VFMT_TV_NUM             = 42,   /**< Number of TV formats & null  */
++
++    TMDL_HDMITX_VFMT_PC_MIN             = 128,  /**< Lowest valid PC format       */
++    TMDL_HDMITX_VFMT_PC_640x480p_60Hz   = 128,  /**< PC format 128                */
++    TMDL_HDMITX_VFMT_PC_800x600p_60Hz   = 129,  /**< PC format 129                */
++    TMDL_HDMITX_VFMT_PC_1152x960p_60Hz  = 130,  /**< PC format 130                */
++    TMDL_HDMITX_VFMT_PC_1024x768p_60Hz  = 131,  /**< PC format 131                */
++    TMDL_HDMITX_VFMT_PC_1280x768p_60Hz  = 132,  /**< PC format 132                */
++    TMDL_HDMITX_VFMT_PC_1280x1024p_60Hz = 133,  /**< PC format 133                */
++    TMDL_HDMITX_VFMT_PC_1360x768p_60Hz  = 134,  /**< PC format 134                */
++    TMDL_HDMITX_VFMT_PC_1400x1050p_60Hz = 135,  /**< PC format 135                */
++    TMDL_HDMITX_VFMT_PC_1600x1200p_60Hz = 136,  /**< PC format 136                */
++    TMDL_HDMITX_VFMT_PC_1024x768p_70Hz  = 137,  /**< PC format 137                */
++    TMDL_HDMITX_VFMT_PC_640x480p_72Hz   = 138,  /**< PC format 138                */
++    TMDL_HDMITX_VFMT_PC_800x600p_72Hz   = 139,  /**< PC format 139                */
++    TMDL_HDMITX_VFMT_PC_640x480p_75Hz   = 140,  /**< PC format 140                */
++    TMDL_HDMITX_VFMT_PC_1024x768p_75Hz  = 141,  /**< PC format 141                */
++    TMDL_HDMITX_VFMT_PC_800x600p_75Hz   = 142,  /**< PC format 142                */
++    TMDL_HDMITX_VFMT_PC_1024x864p_75Hz  = 143,  /**< PC format 143                */
++    TMDL_HDMITX_VFMT_PC_1280x1024p_75Hz = 144,  /**< PC format 144                */
++    TMDL_HDMITX_VFMT_PC_640x350p_85Hz   = 145,  /**< PC format 145                */
++    TMDL_HDMITX_VFMT_PC_640x400p_85Hz   = 146,  /**< PC format 146                */
++    TMDL_HDMITX_VFMT_PC_720x400p_85Hz   = 147,  /**< PC format 147                */
++    TMDL_HDMITX_VFMT_PC_640x480p_85Hz   = 148,  /**< PC format 148                */
++    TMDL_HDMITX_VFMT_PC_800x600p_85Hz   = 149,  /**< PC format 149                */
++    TMDL_HDMITX_VFMT_PC_1024x768p_85Hz  = 150,  /**< PC format 150                */
++    TMDL_HDMITX_VFMT_PC_1152x864p_85Hz  = 151,  /**< PC format 151                */
++    TMDL_HDMITX_VFMT_PC_1280x960p_85Hz  = 152,  /**< PC format 152                */
++    TMDL_HDMITX_VFMT_PC_1280x1024p_85Hz = 153,  /**< PC format 153                */
++    TMDL_HDMITX_VFMT_PC_1024x768i_87Hz  = 154,  /**< PC format 154                */
++    TMDL_HDMITX_VFMT_PC_MAX             = 154,  /**< Highest valid PC format      */
++    TMDL_HDMITX_VFMT_PC_NUM             = (TMDL_HDMITX_VFMT_PC_MAX-TMDL_HDMITX_VFMT_PC_MIN+1)   /**< Number of PC formats         */
++} tmdlHdmiTxVidFmt_t;
++
++/**
++ * \brief Structure defining the EDID short video descriptor
++ */
++typedef struct
++{
++    tmdlHdmiTxVidFmt_t  videoFormat;            /**< Video format as defined by EIA/CEA 861-D */
++    Bool                nativeVideoFormat;   /**< True if format is the preferred video format */
++} tmdlHdmiTxShortVidDesc_t;
++
++/**
++ * \brief Enum listing all picture aspect ratio (H:V) (4:3, 16:9)
++ */
++typedef enum
++{
++    TMDL_HDMITX_P_ASPECT_RATIO_UNDEFINED    = 0,    /**< Undefined picture aspect ratio */
++    TMDL_HDMITX_P_ASPECT_RATIO_6_5          = 1,    /**< 6:5 picture aspect ratio (PAR) */
++    TMDL_HDMITX_P_ASPECT_RATIO_5_4          = 2,    /**< 5:4 PAR */
++    TMDL_HDMITX_P_ASPECT_RATIO_4_3          = 3,    /**< 4:3 PAR */
++    TMDL_HDMITX_P_ASPECT_RATIO_16_10        = 4,    /**< 16:10 PAR */
++    TMDL_HDMITX_P_ASPECT_RATIO_5_3          = 5,    /**< 5:3 PAR */
++    TMDL_HDMITX_P_ASPECT_RATIO_16_9         = 6,    /**< 16:9 PAR */
++    TMDL_HDMITX_P_ASPECT_RATIO_9_5          = 7     /**< 9:5 PAR */
++} tmdlHdmiTxPictAspectRatio_t;
++
++/**
++ * \brief Enum listing all vertical frequency
++ */
++typedef enum
++{
++    TMDL_HDMITX_VFREQ_24Hz      = 0,    /**< 24Hz          */
++    TMDL_HDMITX_VFREQ_25Hz      = 1,    /**< 25Hz          */
++    TMDL_HDMITX_VFREQ_30Hz      = 2,    /**< 30Hz          */
++    TMDL_HDMITX_VFREQ_50Hz      = 3,    /**< 50Hz          */
++    TMDL_HDMITX_VFREQ_59Hz      = 4,    /**< 59.94Hz       */
++    TMDL_HDMITX_VFREQ_60Hz      = 5,    /**< 60Hz          */
++#ifndef FORMAT_PC
++    TMDL_HDMITX_VFREQ_INVALID   = 6,    /**< Invalid       */
++    TMDL_HDMITX_VFREQ_NUM       = 6     /**< No. of values */
++#else /* FORMAT_PC */
++    TMDL_HDMITX_VFREQ_70Hz      = 6,    /**< 70Hz          */
++    TMDL_HDMITX_VFREQ_72Hz      = 7,    /**< 72Hz          */
++    TMDL_HDMITX_VFREQ_75Hz      = 8,    /**< 75Hz          */
++    TMDL_HDMITX_VFREQ_85Hz      = 9,    /**< 85Hz          */
++    TMDL_HDMITX_VFREQ_87Hz      = 10,   /**< 87Hz          */
++    TMDL_HDMITX_VFREQ_INVALID   = 11,   /**< Invalid       */
++    TMDL_HDMITX_VFREQ_NUM       = 11    /**< No. of values */
++#endif /* FORMAT_PC */
++} tmdlHdmiTxVfreq_t;
++
++/**
++ * \brief Structure storing specifications of a video resolution
++ */
++typedef struct
++{
++    UInt16                      width;         /**< Width of the frame in pixels */
++    UInt16                      height;        /**< Height of the frame in pixels */
++    Bool                        interlaced;    /**< Interlaced mode (True/False) */
++    tmdlHdmiTxVfreq_t           vfrequency;    /**< Vertical frequency in Hz */
++    tmdlHdmiTxPictAspectRatio_t aspectRatio;   /**< Picture aspect ratio (H:V) */
++} tmdlHdmiTxVidFmtSpecs_t;
++
++/**
++ * \brief Enum listing all video input modes (CCIR, RGB, etc.)
++ */
++typedef enum
++{
++    TMDL_HDMITX_VINMODE_CCIR656 = 0,    /**< CCIR656 */
++    TMDL_HDMITX_VINMODE_RGB444,         /**< RGB444  */
++    TMDL_HDMITX_VINMODE_YUV444,         /**< YUV444  */
++    TMDL_HDMITX_VINMODE_YUV422,         /**< YUV422  */
++#ifdef TMFL_RGB_DDR_12BITS
++    TMDL_HDMITX_VINMODE_RGB_DDR_12BITS, /**< RGB24 bits on a 12 bits bus using double data rate clocking */
++#endif
++    TMDL_HDMITX_VINMODE_NO_CHANGE ,     /**< No change */
++    TMDL_HDMITX_VINMODE_INVALID         /**< Invalid */
++} tmdlHdmiTxVinMode_t;
++
++/**
++ * \brief Enum listing all possible sync sources
++ */
++typedef enum
++{
++    TMDL_HDMITX_SYNCSRC_EMBEDDED = 0, /**< Embedded sync */
++    TMDL_HDMITX_SYNCSRC_EXT_VREF = 1, /**< External sync Vref, Href, Fref */
++    TMDL_HDMITX_SYNCSRC_EXT_VS   = 2  /**< External sync Vs, Hs */
++} tmdlHdmiTxSyncSource_t;
++
++/**
++ * \brief Enum listing all output pixel rate (Single, Double, etc.)
++ */
++typedef enum
++{
++    TMDL_HDMITX_PIXRATE_DOUBLE          = 0,        /**< Double pixel rate */
++    TMDL_HDMITX_PIXRATE_SINGLE          = 1,        /**< Single pixel rate */
++    TMDL_HDMITX_PIXRATE_SINGLE_REPEATED = 2         /**< Single pixel repeated */
++} tmdlHdmiTxPixRate_t;
++
++/**
++ * \brief Enum listing the supported transmission formats of 3D video data
++ */
++typedef enum
++{
++    TMDL_HDMITX_3D_NONE                 = 0,        /**< 3D video data not present */
++    TMDL_HDMITX_3D_FRAME_PACKING        = 1,        /**< 3D video data Frame Packing structure */
++    TMDL_HDMITX_3D_TOP_AND_BOTTOM       = 2,        /**< 3D video data Top and Bottom structure */
++    TMDL_HDMITX_3D_SIDE_BY_SIDE_HALF    = 3,        /**< 3D video data Side by Side Half structure */
++    TMDL_HDMITX_3D_INVALID              = 4         /**< Invalid */
++} tmdlHdmiTx3DStructure_t;
++
++/**
++ * \brief Structure defining the video input configuration
++ */
++typedef struct
++{
++   tmdlHdmiTxVidFmt_t       format;       /**< Video format as defined by EIA/CEA 861-D */
++   tmdlHdmiTxVinMode_t      mode;         /**< Video mode (CCIR, RGB, YUV, etc.) */
++   tmdlHdmiTxSyncSource_t   syncSource;   /**< Sync source type */
++   tmdlHdmiTxPixRate_t      pixelRate;    /**< Pixel rate */
++   tmdlHdmiTx3DStructure_t  structure3D;  /**< 3D structure as defined in HDMI1.4a */
++} tmdlHdmiTxVideoInConfig_t;
++
++/**
++ * \brief Enum listing all video output modes (YUV, RGB, etc.)
++ */
++typedef enum
++{
++    TMDL_HDMITX_VOUTMODE_RGB444     = 0,    /**< RGB444    */
++    TMDL_HDMITX_VOUTMODE_YUV422     = 1,    /**< YUV422    */
++    TMDL_HDMITX_VOUTMODE_YUV444     = 2     /**< YUV444    */
++} tmdlHdmiTxVoutMode_t;
++
++/**
++ * \brief Enum defining possible quantization range
++ */
++typedef enum
++{
++    TMDL_HDMITX_VQR_DEFAULT = 0, /* Follow HDMI spec. */
++    TMDL_HDMITX_RGB_FULL    = 1, /* Force RGB FULL , DVI only */
++    TMDL_HDMITX_RGB_LIMITED = 2  /* Force RGB LIMITED , DVI only */
++} tmdlHdmiTxVQR_t;
++
++
++/**
++ * \brief Enum defining possible YCC Quantization Range
++ */
++typedef enum
++{
++    TMDL_HDMITX_YQR_LIMITED = 0, /* LIMITED range */
++    TMDL_HDMITX_YQR_FULL    = 1, /* FULL range */
++    TMDL_HDMITX_YQR_INVALID = 2  /* Invalid range */
++} tmdlHdmiTxYCCQR_t;
++
++
++/**
++ * \brief Structure defining the video output configuration
++ */
++typedef struct
++{
++   tmdlHdmiTxVidFmt_t       format;     /**< Video format as defined by EIA/CEA 861-D */
++   tmdlHdmiTxVoutMode_t     mode;       /**< Video mode (CCIR, RGB, YUV, etc.) */
++   tmdlHdmiTxColorDepth_t   colorDepth; /**< Color depth */
++   tmdlHdmiTxVQR_t          dviVqr;     /**< VQR applied in DVI mode */ 
++} tmdlHdmiTxVideoOutConfig_t;
++
++
++typedef enum
++{
++  TMDL_HDMITX_AUDIO_DATA_PCM     = 0,  /**< Main data field represents linear PCM samples.    */
++  TMDL_HDMITX_AUDIO_DATA_OTHER   = 1,  /**< Main data field used for purposes other purposes. */
++  TMDL_HDMITX_AUDIO_DATA_INVALID = 2   /**< Invalid value */  
++} tmdlHdmiTxAudioData_t;
++
++
++typedef enum
++{
++    TMDL_HDMITX_CSCOPYRIGHT_PROTECTED   = 0,  /**< Copyright protected     */
++    TMDL_HDMITX_CSCOPYRIGHT_UNPROTECTED = 1,  /**< Not copyright protected */
++    TMDL_HDMITX_CSCOPYRIGHT_INVALID     = 2   /**< Invalid value           */
++} tmdlHdmiTxCScopyright_t;
++
++typedef enum
++{
++    TMDL_HDMITX_CSFI_PCM_2CHAN_NO_PRE    = 0,  /**< PCM 2 channels without pre-emphasis or NON Linear PCM */
++    TMDL_HDMITX_CSFI_PCM_2CHAN_PRE       = 1,  /**< PCM 2 channels with 50us/15us pre-emphasis    */
++    TMDL_HDMITX_CSFI_PCM_2CHAN_PRE_RSVD1 = 2,  /**< PCM Reserved for 2 channels with pre-emphasis */
++    TMDL_HDMITX_CSFI_PCM_2CHAN_PRE_RSVD2 = 3,  /**< PCM Reserved for 2 channels with pre-emphasis */
++    TMDL_HDMITX_CSFI_INVALID             = 4   /**< Invalid value                                 */
++} tmdlHdmiTxCSformatInfo_t;
++
++
++typedef enum
++{
++    TMDL_HDMITX_CSCLK_LEVEL_II    = 0,     /**< Level II                     */
++    TMDL_HDMITX_CSCLK_LEVEL_I     = 1,     /**< Level I                      */
++    TMDL_HDMITX_CSCLK_LEVEL_III   = 2,     /**< Level III                    */
++    TMDL_HDMITX_CSCLK_NOT_MATCHED = 3,     /**< Not matched to sample freq.  */
++    TMDL_HDMITX_CSCLK_INVALID     = 4      /**< Invalid                      */
++} tmdlHdmiTxCSclkAcc_t;
++
++
++typedef enum
++{
++    TMDL_HDMITX_CSMAX_LENGTH_20   = 0,  /**< Max word length is 20 bits   */
++    TMDL_HDMITX_CSMAX_LENGTH_24   = 1,  /**< Max word length is 24 bits   */
++    TMDL_HDMITX_CSMAX_INVALID     = 2   /**< Invalid value                */
++} tmdlHdmiTxCSmaxWordLength_t;
++
++
++
++typedef enum
++{
++    TMDL_HDMITX_CSWORD_DEFAULT          = 0,     /**< Word length is not indicated                    */
++    TMDL_HDMITX_CSWORD_20_OF_24         = 1,     /**< Sample length is 20 bits out of max 24 possible */
++    TMDL_HDMITX_CSWORD_16_OF_20         = 1,     /**< Sample length is 16 bits out of max 20 possible */
++    TMDL_HDMITX_CSWORD_22_OF_24         = 2,     /**< Sample length is 22 bits out of max 24 possible */
++    TMDL_HDMITX_CSWORD_18_OF_20         = 2,     /**< Sample length is 18 bits out of max 20 possible */
++    TMDL_HDMITX_CSWORD_RESVD            = 3,     /**< Reserved - shall not be used */
++    TMDL_HDMITX_CSWORD_23_OF_24         = 4,     /**< Sample length is 23 bits out of max 24 possible */
++    TMDL_HDMITX_CSWORD_19_OF_20         = 4,     /**< Sample length is 19 bits out of max 20 possible */
++    TMDL_HDMITX_CSWORD_24_OF_24         = 5,     /**< Sample length is 24 bits out of max 24 possible */
++    TMDL_HDMITX_CSWORD_20_OF_20         = 5,     /**< Sample length is 20 bits out of max 20 possible */
++    TMDL_HDMITX_CSWORD_21_OF_24         = 6,     /**< Sample length is 21 bits out of max 24 possible */
++    TMDL_HDMITX_CSWORD_17_OF_20         = 6,     /**< Sample length is 17 bits out of max 20 possible */
++    TMDL_HDMITX_CSWORD_INVALID          = 7      /**< Invalid */
++} tmdlHdmiTxCSwordLength_t;
++
++
++typedef enum
++{
++    TMDL_HDMITX_CSOFREQ_NOT_INDICATED = 0,   /**< Not Indicated */
++    TMDL_HDMITX_CSOFREQ_192k          = 1,   /**< 192kHz        */
++    TMDL_HDMITX_CSOFREQ_12k           = 2,   /**< 12kHz         */
++    TMDL_HDMITX_CSOFREQ_176_4k        = 3,   /**< 176.4kHz      */
++    TMDL_HDMITX_CSOFREQ_RSVD1         = 4,   /**< Reserved      */
++    TMDL_HDMITX_CSOFREQ_96k           = 5,   /**< 96kHz         */
++    TMDL_HDMITX_CSOFREQ_8k            = 6,   /**< 8kHz          */
++    TMDL_HDMITX_CSOFREQ_88_2k         = 7,   /**< 88.2kHz       */
++    TMDL_HDMITX_CSOFREQ_16k           = 8,   /**< 16kHz         */
++    TMDL_HDMITX_CSOFREQ_24k           = 9,   /**< 24kHz         */
++    TMDL_HDMITX_CSOFREQ_11_025k       = 10,  /**< 11.025kHz     */
++    TMDL_HDMITX_CSOFREQ_22_05k        = 11,  /**< 22.05kHz      */
++    TMDL_HDMITX_CSOFREQ_32k           = 12,  /**< 32kHz         */
++    TMDL_HDMITX_CSOFREQ_48k           = 13,  /**< 48kHz         */
++    TMDL_HDMITX_CSOFREQ_RSVD2         = 14,  /**< Reserved      */
++    TMDL_HDMITX_CSOFREQ_44_1k         = 15,  /**< 44.1kHz       */
++    TMDL_HDMITX_CSAFS_INVALID         = 16   /**< Invalid value */
++} tmdlHdmiTxCSorigAfs_t;
++
++
++
++typedef struct
++{
++    tmdlHdmiTxAudioData_t          PcmIdentification;
++    tmdlHdmiTxCScopyright_t        CopyrightInfo;
++    tmdlHdmiTxCSformatInfo_t       FormatInfo;
++    UInt8                          categoryCode;
++    tmdlHdmiTxCSclkAcc_t           clockAccuracy;
++    tmdlHdmiTxCSmaxWordLength_t    maxWordLength;
++    tmdlHdmiTxCSwordLength_t       wordLength;
++    tmdlHdmiTxCSorigAfs_t          origSampleFreq;
++} tmdlHdmiTxAudioInChannelStatus;
++
++
++/**
++ * \brief Structure defining the audio input configuration
++ */
++typedef struct
++{
++   tmdlHdmiTxAudioFormat_t          format;             /**< Audio format (I2S, SPDIF, etc.) */
++   tmdlHdmiTxAudioRate_t            rate;               /**< Audio sampling rate */
++   tmdlHdmiTxAudioI2SFormat_t       i2sFormat;          /**< I2S format of the audio input */
++   tmdlHdmiTxAudioI2SQualifier_t    i2sQualifier;       /**< I2S qualifier of the audio input (8,16,32 bits) */
++   tmdlHdmiTxDstRate_t              dstRate;            /**< DST data transfer rate */
++   UInt8                            channelAllocation;  /**< Ref to CEA-861D p85 */
++   tmdlHdmiTxAudioInChannelStatus   channelStatus;      /**< Ref to IEC 60958-3 */
++} tmdlHdmiTxAudioInConfig_t;
++
++/**
++ * \brief Enum listing all the type of sunk
++ */
++typedef enum
++{
++    TMDL_HDMITX_SINK_DVI  = 0, /**< DVI  */
++    TMDL_HDMITX_SINK_HDMI = 1, /**< HDMI */
++    TMDL_HDMITX_SINK_EDID = 2  /**< As currently defined in EDID */
++} tmdlHdmiTxSinkType_t;
++
++/**
++ * \brief Structure defining the content of a gamut packet
++ */
++typedef struct
++{
++    Bool   nextField;           /**< Gamut relevant for field following packet insertion */
++    UInt8  GBD_Profile;         /**< Profile of the gamut packet : 0 = P0, 1 = P1 */
++    UInt8  affectedGamutSeqNum; /**< Gamut sequence number of the field that have to be affected by this gamut packet */
++    Bool   noCurrentGBD;        /**< Current field not using specific gamut */
++    UInt8  currentGamutSeqNum;  /**< Gamut sequence number of the current field */
++    UInt8  packetSequence;      /**< Sequence of the packet inside a multiple packet gamut */
++    UInt8  payload[28];         /**< Payload of the gamut packet */
++} tmdlHdmiTxGamutData_t;
++
++/**
++ * \brief Type defining the content of a generic packet
++ */
++typedef UInt8 tmdlHdmiTxGenericPacket[28];
++
++/**
++ * \brief Structure defining the content of an ACP packet
++ */
++typedef struct
++{
++    UInt8 acpType;
++    UInt8 acpData[28];
++} tmdlHdmiTxAcpPktData_t;
++
++/**
++ * \brief Structure defining the content of an AVI infoframe
++ */
++typedef struct
++{
++    UInt8  colorIndicator;                /**< RGB or YCbCr indicator. See CEA-861-B table 8 for details */
++    UInt8  activeInfoPresent;             /**< Active information present. Indicates if activeFormatAspectRatio field is valid */
++    UInt8  barInformationDataValid;       /**< Bar information data valid */
++    UInt8  scanInformation;               /**< Scan information. See CEA-861-B table 8 for details */
++    UInt8  colorimetry;                   /**< Colorimetry. See CEA-861-B table 9 for details */
++    UInt8  pictureAspectRatio;            /**< Picture aspect ratio. See CEA-861-B table 9 for details */
++    UInt8  activeFormatAspectRatio;       /**< Active Format aspect ratio. See CEA-861-B table 10 and Annex H for details */
++    UInt8  nonUniformPictureScaling;      /**< Non-uniform picture scaling. See CEA-861-B table 11 for details */
++    UInt8  videoFormatIdentificationCode; /**< Video format indentification code. See CEA-861-B section 6.3 for details */
++    UInt8  pixelRepetitionFactor;         /**< Pixel repetition factor. See CEA-861-B table 11 for details */
++    UInt16 lineNumberEndTopBar;
++    UInt16 lineNumberStartBottomBar;
++    UInt16 lineNumberEndLeftBar;
++    UInt16 lineNumberStartRightBar;
++} tmdlHdmiTxAviIfData_t;
++
++/**
++ * \brief Structure defining the content of an ACP packet
++ */
++typedef struct
++{
++    Bool avMute;
++} tmdlHdmiTxGcpPktData_t;
++
++/**
++ * \brief Structure defining the content of an AUD infoframe
++ */
++typedef struct
++{
++    UInt8 codingType;        /**< Coding type (always set to zero) */
++    UInt8 channelCount;      /**< Channel count. See CEA-861-B table 17 for details */
++    UInt8 samplefrequency;   /**< Sample frequency. See CEA-861-B table 18 for details */
++    UInt8 sampleSize;        /**< Sample frequency. See CEA-861-B table 18 for details */
++    UInt8 channelAllocation; /**< Channel allocation. See CEA-861-B section 6.3.2 for details */
++    Bool  downmixInhibit;    /**< Downmix inhibit. See CEA-861-B section 6.3.2 for details */
++    UInt8 levelShiftValue;   /**< level shift value for downmixing. See CEA-861-B section 6.3.2 and table 23 for details */
++} tmdlHdmiTxAudIfData_t;
++
++/**
++ * \brief Structure defining the content of an ISRC1 packet
++ */
++typedef struct
++{
++    Bool  isrcCont;         /**< ISRC packet continued in next packet */
++    Bool  isrcValid;        /**< Set to one when ISRCStatus and UPC_EAN_ISRC_xx are valid */
++    UInt8 isrcStatus;       /**< ISRC status */
++    UInt8 UPC_EAN_ISRC[16]; /**< ISRC packet data */
++} tmdlHdmiTxIsrc1PktData_t;
++
++/**
++ * \brief Structure defining the content of an ISRC2 packet
++ */
++typedef struct
++{
++    UInt8 UPC_EAN_ISRC[16];  /**< ISRC packet data */
++} tmdlHdmiTxIsrc2PktData_t;
++
++/**
++ * \brief Structure defining the content of an MPS infoframe
++ */
++typedef struct
++{
++    UInt32 bitRate;         /**< MPEG bit rate in Hz */
++    UInt32 frameType;       /**< MPEG frame type */
++    Bool   fieldRepeat;     /**< 0: new field, 1:repeated field */
++} tmdlHdmiTxMpsIfData_t;
++
++/**
++ * \brief Structure defining the content of an SPD infoframe
++ */
++typedef struct
++{
++    UInt8   vendorName[8];   /**< Vendor name */
++    UInt8   productDesc[16]; /**< Product Description */
++    UInt32  sourceDevInfo;   /**< Source Device Info */
++} tmdlHdmiTxSpdIfData_t;
++
++
++/**
++ * \brief Structure defining the content of a VS infoframe packet according to HDMI 1.4a standard
++ */
++
++/* HDMI version */
++#define TMDL_HDMITX_VERSION            0x01
++
++/* HDMI video format [3bits] */
++#define TMDL_HDMITX_VIDEO_FORMAT_SHIFT 5
++#define TMDL_HDMITX_FORMAT_EXTENDED    (0x01 << TMDL_HDMITX_VIDEO_FORMAT_SHIFT)
++#define TMDL_HDMITX_3D                 (0x02 << TMDL_HDMITX_VIDEO_FORMAT_SHIFT)
++
++/* IEEE registration identifier (0x000C03) with least significant byte first */
++#define TMDL_HDMITX_HDMI_IEEE_BYTE0    0x03
++#define TMDL_HDMITX_HDMI_IEEE_BYTE1    0x0C
++#define TMDL_HDMITX_HDMI_IEEE_BYTE2    0x00
++
++/* 3D structure [4bits] */
++#define TMDL_HDMITX_3D_STRUCTURE_SHIFT 4
++#define TMDL_HDMITX_FRAME_PACKING      (0x00 << TMDL_HDMITX_3D_STRUCTURE_SHIFT)
++#define TMDL_HDMITX_FIELD_ALTERNATIVE  (0x01 << TMDL_HDMITX_3D_STRUCTURE_SHIFT)
++#define TMDL_HDMITX_LINE_ALTERNATIVE   (0x02 << TMDL_HDMITX_3D_STRUCTURE_SHIFT)
++#define TMDL_HDMITX_SIDE_BY_SIDE_FULL  (0x03 << TMDL_HDMITX_3D_STRUCTURE_SHIFT)
++#define TMDL_HDMITX_L_DEPTH            (0x04 << TMDL_HDMITX_3D_STRUCTURE_SHIFT)
++#define TMDL_HDMITX_L_DEPTH_GFX        (0x05 << TMDL_HDMITX_3D_STRUCTURE_SHIFT)
++#define TMDL_HDMITX_TOP_AND_BOTTOM     (0x06 << TMDL_HDMITX_3D_STRUCTURE_SHIFT)
++#define TMDL_HDMITX_SIDE_BY_SIDE_HALF  (0x08 << TMDL_HDMITX_3D_STRUCTURE_SHIFT)
++
++/* 3D EXT Data [4bits] */
++#define TMDL_HDMITX_3D_EXT_DATA_SHIFT  4
++#define TMDL_HDMITX_HORIZONTAL_SUB     (0x00 << TMDL_HDMITX_3D_EXT_DATA_SHIFT)  /* Horizontal sub-sampling */
++#define TMDL_HDMITX_QUINCUNX_OLOR      (0x04 << TMDL_HDMITX_3D_EXT_DATA_SHIFT)  /* Odd/Left picture, Odd/Right picture */
++#define TMDL_HDMITX_QUINCUNX_OLER      (0x05 << TMDL_HDMITX_3D_EXT_DATA_SHIFT)  /* Odd/Left picture, Even/Right picture */
++#define TMDL_HDMITX_QUINCUNX_ELOR      (0x06 << TMDL_HDMITX_3D_EXT_DATA_SHIFT)  /* Even/Left picture, Odd/Right picture */
++#define TMDL_HDMITX_QUINCUNX_ELER      (0x07 << TMDL_HDMITX_3D_EXT_DATA_SHIFT)  /* Even/Left picture, Even/Right picture */
++
++/* 3D Meta field */
++#define TMDL_HDMITX_3D_META_TYPE_SHIFT 5 
++#define TMDL_HDMITX_3D_META_PRESENT    (0x01 << 3)
++#define TMDL_HDMITX_3D_META_PARALLAX   (0x00 << TMDL_HDMITX_3D_META_TYPE_SHIFT)
++
++#define TMDL_HDMITX_VS_PKT_DATA_LEN    27
++typedef struct
++{
++   UInt8 version;
++   /*
++   Packet Byte #        7     6     5     4     3     2     1     0
++
++      PB1          24bit IEEE Registration Identifier (0x000C03)
++      PB2                 ( least significant byte first )
++      PB3
++      PB4          (HDMI_Video_Format  ) (0)   (0)   (0)   (0)   (0)
++      PB5          (3D_Structure             ) +Meta (0)   (0)   (0)
++      PB6          (3D_Ext_Data              ) (0)   (0)   (0)   (0)
++      PB7          (3D_Metadata_type   )  (3D_Metadata_Length (= N))
++      PB8          (3D_Metadata_1                                  )
++       ...                                              ...
++      PB [7+N]     (3D_Metadata_N                                  )
++      PB[8+N]~[Nv] (Reserved (0)                                   )
++   */
++   UInt8 vsData[TMDL_HDMITX_VS_PKT_DATA_LEN];
++
++} tmdlHdmiTxVsPktData_t;
++
++/**
++ * \brief Structure defining the additional Edid VSDB data according to HDMI 1.4a standard
++ */
++typedef struct
++{
++    UInt8 maxTmdsClock;      /* maximum supported TMDS clock */
++    UInt8 cnc0;              /* content type Graphics (text) */
++    UInt8 cnc1;              /* content type Photo */
++    UInt8 cnc2;              /* content type Cinema */
++    UInt8 cnc3;              /* content type Game */
++    UInt8 hdmiVideoPresent;  /* additional video format */
++    UInt8 h3DPresent;        /* 3D support by the HDMI Sink */
++    UInt8 h3DMultiPresent;   /* 3D multi strctures present */
++    UInt8 imageSize;         /* additional info for the values in the image size area */
++    UInt8 hdmi3DLen;         /* total length of 3D video formats */
++    UInt8 hdmiVicLen;        /* total length of extended video formats */
++    UInt8 ext3DData[21];     /* max_len-10, ie: 31-10=21 */
++} tmdlHdmiTxEdidExtraVsdbData_t;
++
++/**
++ * \brief Structure defining the Edid audio descriptor
++ */
++typedef struct
++{
++    UInt8 format;         /* EIA/CEA861 mode */
++    UInt8 channels;       /* number of channels */
++    UInt8 supportedFreqs; /* bitmask of supported frequencies */
++    UInt8 supportedRes;   /* bitmask of supported resolutions (LPCM only) */
++    UInt8 maxBitrate;     /* Maximum bitrate divided by 8KHz (compressed formats only) */
++} tmdlHdmiTxEdidAudioDesc_t;
++
++/**
++ * \brief Structure defining detailed timings of a video format
++ */
++typedef struct
++{
++    UInt16  pixelClock;        /**< Pixel Clock/10 000         */
++    UInt16  hActivePixels;     /**< Horizontal Active Pixels   */
++    UInt16  hBlankPixels;      /**< Horizontal Blanking Pixels */
++    UInt16  vActiveLines;      /**< Vertical Active Lines      */
++    UInt16  vBlankLines;       /**< Vertical Blanking Lines    */
++    UInt16  hSyncOffset;       /**< Horizontal Sync Offset     */
++    UInt16  hSyncWidth;        /**< Horiz. Sync Pulse Width    */
++    UInt16  vSyncOffset;       /**< Vertical Sync Offset       */
++    UInt16  vSyncWidth;        /**< Vertical Sync Pulse Width  */
++    UInt16  hImageSize;        /**< Horizontal Image Size      */
++    UInt16  vImageSize;        /**< Vertical Image Size        */
++    UInt16  hBorderPixels;     /**< Horizontal Border          */
++    UInt16  vBorderPixels;     /**< Vertical Border            */
++    UInt8   flags;             /**< Interlace/sync info        */
++} tmdlHdmiTxEdidVideoTimings_t;
++
++/** size descriptor block of monitor descriptor */
++#define EDID_MONITOR_DESCRIPTOR_SIZE   13
++
++/**
++ * \brief Structure defining the first monitor descriptor
++ */
++typedef struct
++{   
++    Bool    descRecord;                                 /**< True when parameters of struct are available   */
++    UInt8   monitorName[EDID_MONITOR_DESCRIPTOR_SIZE];  /**< Monitor Name                                   */
++} tmdlHdmiTxEdidFirstMD_t;
++
++/**
++ * \brief Structure defining the second monitor descriptor
++ */
++typedef struct
++{
++    Bool    descRecord;             /**< True when parameters of struct are available   */
++    UInt8   minVerticalRate;        /**< Min vertical rate in Hz                        */
++    UInt8   maxVerticalRate;        /**< Max vertical rate in Hz                        */
++    UInt8   minHorizontalRate;      /**< Min horizontal rate in Hz                      */
++    UInt8   maxHorizontalRate;      /**< Max horizontal rate in Hz                      */
++    UInt8   maxSupportedPixelClk;   /**< Max suuported pixel clock rate in MHz          */
++} tmdlHdmiTxEdidSecondMD_t;
++
++/**
++ * \brief Structure defining the other monitor descriptor
++ */
++typedef struct
++{
++    Bool    descRecord;                                     /**< True when parameters of struct are available   */
++    UInt8   otherDescriptor[EDID_MONITOR_DESCRIPTOR_SIZE];  /**< Other monitor Descriptor                       */
++} tmdlHdmiTxEdidOtherMD_t;
++
++/**
++ * \brief Test pattern types
++ */
++typedef enum
++{
++    TMDL_HDMITX_PATTERN_OFF     = 0, /**< Insert test pattern       */
++    TMDL_HDMITX_PATTERN_CBAR4   = 1, /**< Insert 4-bar colour bar   */
++    TMDL_HDMITX_PATTERN_CBAR8   = 2, /**< Insert 8-bar colour bar   */
++    TMDL_HDMITX_PATTERN_BLUE	= 3, /**< Insert Blue screen        */
++    TMDL_HDMITX_PATTERN_BLACK   = 4, /**< Insert Black screen       */
++    TMDL_HDMITX_PATTERN_INVALID = 5  /**< Invalid pattern		    */
++} tmdlHdmiTxTestPattern_t;
++
++/**
++ * \brief Enum listing all hdcp state
++ */
++typedef enum
++{
++    TMDL_HDMITX_HDCP_CHECK_NOT_STARTED       = 0,    /**< Check not started */
++    TMDL_HDMITX_HDCP_CHECK_IN_PROGRESS       = 1,    /**< No failures, more to do */
++    TMDL_HDMITX_HDCP_CHECK_PASS              = 2,    /**< Final check has passed */
++    TMDL_HDMITX_HDCP_CHECK_FAIL_FIRST        = 3,    /**< First check failure code */
++    TMDL_HDMITX_HDCP_CHECK_FAIL_DRIVER_STATE = 3,    /**< Driver not AUTHENTICATED */
++    TMDL_HDMITX_HDCP_CHECK_FAIL_DEVICE_T0    = 4,    /**< A T0 interrupt occurred */
++    TMDL_HDMITX_HDCP_CHECK_FAIL_DEVICE_RI    = 5,    /**< Device RI changed */
++    TMDL_HDMITX_HDCP_CHECK_FAIL_DEVICE_FSM   = 6,    /**< Device FSM not 10h */
++    TMDL_HDMITX_HDCP_CHECK_NUM               = 7     /**< Number of check results */
++}tmdlHdmiTxHdcpCheck_t;
++
++/**
++ * \brief Enum listing all hdcp option flags
++ */
++typedef enum
++{
++    TMDL_HDMITX_HDCP_OPTION_FORCE_PJ_IGNORED    = 0x01, /* Not set: obey PJ result     */
++    TMDL_HDMITX_HDCP_OPTION_FORCE_SLOW_DDC      = 0x02, /* Not set: obey BCAPS setting */
++    TMDL_HDMITX_HDCP_OPTION_FORCE_NO_1_1        = 0x04, /* Not set: obey BCAPS setting */
++    TMDL_HDMITX_HDCP_OPTION_FORCE_REPEATER      = 0x08, /* Not set: obey BCAPS setting */
++    TMDL_HDMITX_HDCP_OPTION_FORCE_NO_REPEATER   = 0x10, /* Not set: obey BCAPS setting */
++    TMDL_HDMITX_HDCP_OPTION_FORCE_V_EQU_VBAR    = 0x20, /* Not set: obey V=V' result   */
++    TMDL_HDMITX_HDCP_OPTION_FORCE_VSLOW_DDC     = 0x40, /* Set: 50kHz DDC */
++    TMDL_HDMITX_HDCP_OPTION_DEFAULT             = 0x00, /* All the above Not Set vals */
++    TMDL_HDMITX_HDCP_OPTION_MASK                = 0x7F, /* Only these bits are allowed */
++    TMDL_HDMITX_HDCP_OPTION_MASK_BAD            = 0x80  /* These bits are not allowed  */
++}tmdlHdmiTxHdcpOptions_t;
++
++#ifndef NO_HDCP
++/** KSV list sizes */
++typedef enum
++{
++    TMDL_HDMITX_KSV_LIST_MAX_DEVICES = 128,
++    TMDL_HDMITX_KSV_BYTES_PER_DEVICE = 5
++} tmdlHdmiTxHdcpHandleSHA_1;
++
++/**
++ * \brief Structure defining information about hdcp
++ */
++typedef struct
++{
++    tmdlHdmiTxHdcpCheck_t   hdcpCheckState;                                 /* Hdcp check state */
++    UInt8                   hdcpErrorState;                                 /* Error State when T0 occured */
++    Bool                    bKsvSecure;                                     /* BKSV is secured */
++    UInt8                   hdcpBksv[TMDL_HDMITX_KSV_BYTES_PER_DEVICE];     /* BKSV read from B sink */
++    UInt8                   hdcpKsvList[TMDL_HDMITX_KSV_BYTES_PER_DEVICE *
++                                        TMDL_HDMITX_KSV_LIST_MAX_DEVICES];  /* KSV list read from B sink during
++                                                                            SHA-1 interrupt */
++    UInt8                   hdcpKsvDevices;                                 /* Number of devices read from
++                                                                            B sink during SHA-1 interrupt */
++    UInt8                   hdcpDeviceDepth;                               /* Connection tree depth */
++    Bool                    hdcpMaxCascExceeded;
++    Bool                    hdcpMaxDevsExceeded;
++} tmdlHdmiTxHdcpInfo_t;
++#endif /* NO_HDCP */
++
++/**
++ * \brief Enum defining possible HDCP
++ */
++typedef enum
++{
++    TMDL_HDMITX_HDCP_OK = 0,
++    TMDL_HDMITX_HDCP_BKSV_RCV_FAIL,                   /* Source does not receive Sink BKsv  */
++    TMDL_HDMITX_HDCP_BKSV_CHECK_FAIL,                 /* BKsv does not contain 20 zeros and 20 ones */
++    TMDL_HDMITX_HDCP_BCAPS_RCV_FAIL,                  /* Source does not receive Sink Bcaps */
++    TMDL_HDMITX_HDCP_AKSV_SEND_FAIL,                  /* Source does not send AKsv */
++    TMDL_HDMITX_HDCP_R0_RCV_FAIL,                     /* Source does not receive R'0 */
++    TMDL_HDMITX_HDCP_R0_CHECK_FAIL,                   /* R0 = R'0 check fail */
++    TMDL_HDMITX_HDCP_BKSV_NOT_SECURE,
++    TMDL_HDMITX_HDCP_RI_RCV_FAIL,                     /* Source does not receive R'i */
++    TMDL_HDMITX_HDCP_RPT_RI_RCV_FAIL,                 /* Source does not receive R'i repeater mode */
++    TMDL_HDMITX_HDCP_RI_CHECK_FAIL,                   /* RI = R'I check fail */
++    TMDL_HDMITX_HDCP_RPT_RI_CHECK_FAIL,               /* RI = R'I check fail repeater mode */
++    TMDL_HDMITX_HDCP_RPT_BCAPS_RCV_FAIL,              /* Source does not receive Sink Bcaps repeater mode */
++    TMDL_HDMITX_HDCP_RPT_BCAPS_READY_TIMEOUT,
++    TMDL_HDMITX_HDCP_RPT_V_RCV_FAIL,                  /* Source does not receive V'*/
++    TMDL_HDMITX_HDCP_RPT_BSTATUS_RCV_FAIL,            /* Source does not receive BSTATUS repeater mode */
++    TMDL_HDMITX_HDCP_RPT_KSVLIST_RCV_FAIL,            /* Source does not receive Ksv list in repeater mode */
++    TMDL_HDMITX_HDCP_RPT_KSVLIST_NOT_SECURE,
++    TMDL_HDMITX_HDCP_UNKNOWN_STATUS
++
++}tmdlHdmiTxHdcpStatus_t;
++
++
++/**
++ * \brief EDID information about sink latency
++ */
++typedef struct
++{
++    Bool   latency_available;
++    Bool   Ilatency_available;
++    UInt8  Edidvideo_latency;
++    UInt8  Edidaudio_latency;
++    UInt8  EdidIvideo_latency;
++    UInt8  EdidIaudio_latency;
++
++} tmdlHdmiTxEdidLatency_t;
++
++
++/**
++ * \brief Enum defining possible HotPlug status
++ */
++typedef enum
++{
++    TMDL_HDMITX_HOTPLUG_INACTIVE    = 0,    /**< Hotplug inactive */
++    TMDL_HDMITX_HOTPLUG_ACTIVE      = 1,    /**< Hotplug active   */
++    TMDL_HDMITX_HOTPLUG_INVALID     = 2     /**< Invalid Hotplug  */
++} tmdlHdmiTxHotPlug_t;
++
++
++/**
++ * \brief Enum defining possible RxSense status
++ */
++typedef enum
++{
++    TMDL_HDMITX_RX_SENSE_INACTIVE    = 0,    /**< RxSense inactive */
++    TMDL_HDMITX_RX_SENSE_ACTIVE      = 1,    /**< RxSense active   */
++    TMDL_HDMITX_RX_SENSE_INVALID     = 2     /**< Invalid RxSense  */
++} tmdlHdmiTxRxSense_t;
++
++
++/**
++ * \brief  Enum listing all the types of extented colorimetries
++ */
++typedef enum
++{
++    TMDL_HDMITX_EXT_COLORIMETRY_XVYCC601      = 0,
++    TMDL_HDMITX_EXT_COLORIMETRY_XVYCC709      = 1,
++    TMDL_HDMITX_EXT_COLORIMETRY_SYCC601       = 2,
++    TMDL_HDMITX_EXT_COLORIMETRY_ADOBEYCC601   = 3,
++    TMDL_HDMITX_EXT_COLORIMETRY_ADOBERGB      = 4,
++    TMDL_HDMITX_EXT_COLORIMETRY_INVALID       = 5
++} tmdlHdmiTxExtColorimetry_t;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMITX_TYPES_H */
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
++
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx.c b/drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx.c
+new file mode 100755
+index 0000000..b80b9f2
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx.c
+@@ -0,0 +1,7166 @@
++/**
++ * Copyright (C) 2006 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx.c
++ *
++ * \version       Revision: 1
++ *
++ * \date          Date: 10/08/07 10:00
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * HDMI Tx Driver - FRS.doc,
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   History:       tmdlHdmiTx.c
++ *
++ * *****************  Version 1  *****************
++ * User: J. Lamotte Date: 10/08/07   Time: 10:00
++ * Updated in $/Source/tmdlHdmiTx/inc
++ * initial version
++ 
++   \endverbatim
++ *
++*/
++
++/*============================================================================*/
++/*                             INCLUDE FILES                                  */
++/*============================================================================*/
++#include "tmdlHdmiTx_IW.h"
++#include "tmdlHdmiTx.h"
++#include "tmdlHdmiTx_local.h"
++#include "tmdlHdmiTx_cfg.h"
++#include "tmbslHdmiTx_funcMapping.h"
++
++/*============================================================================*/
++/*                          TYPES DECLARATIONS                                */
++/*============================================================================*/
++
++/* Macro to avoid compilation warnings */
++#ifdef TMFL_OS_WINDOWS
++#define DUMMY_ACCESS(x) x
++#else
++#define DUMMY_ACCESS(x)
++#endif
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS                               */
++/*============================================================================*/
++
++
++
++/*============================================================================*/
++/*                         FUNCTION PROTOTYPES                                */
++/*============================================================================*/
++
++/* Prototypes of internal functions */
++/* Task functions */
++#ifndef TMFL_NO_RTOS
++static void CommandTaskUnit0(void);
++static void HdcpTaskUnit0(void);
++#endif /* TMFL_NO_RTOS */
++
++/* Interrupt callback functions */
++static void dlHdmiTxHandleENCRYPT(tmInstance_t instance);
++static void dlHdmiTxHandleHPD(tmInstance_t instance);
++static void dlHdmiTxHandleT0(tmInstance_t instance);
++static void dlHdmiTxHandleBCAPS(tmInstance_t instance);
++static void dlHdmiTxHandleBSTATUS(tmInstance_t instance);
++static void dlHdmiTxHandleSHA_1(tmInstance_t instance);
++static void dlHdmiTxHandlePJ(tmInstance_t instance);
++static void dlHdmiTxHandleR0(tmInstance_t instance);
++static void dlHdmiTxHandleSW_INT(tmInstance_t instance);
++static void dlHdmiTxHandleRX_SENSE(tmInstance_t instance);
++static void dlHdmiTxHandleEDID_READ(tmInstance_t instance);
++static void dlHdmiTxHandleVS_RPT(tmInstance_t instance);
++
++/* Devlib internal color bar management functions */ 
++#ifndef NO_HDCP
++static void dlHdmiTxCheckColorBar(tmInstance_t instance);
++static void dlHdmiTxCheckHdcpColorBar(tmInstance_t instance);
++#endif
++
++#ifndef NO_HDCP
++static void dlHdmiTxFindHdcpSeed(tmInstance_t instance);
++#endif /* NO_HDCP */
++
++/* Set the state machine of device library */
++static void dlHdmiTxSetState
++(
++    tmInstance_t instance, 
++    tmdlHdmiTxDriverState_t state
++);
++
++/* Get the event status (enable or disable) in order to known
++   if event should be signaled */
++static tmdlHdmiTxEventStatus_t dlHdmiTxGetEventStatus
++(
++    tmInstance_t        instance,
++    tmdlHdmiTxEvent_t   event
++);
++
++/* Use by tmdlHdmiTxSetInputOutput in scaler mode */
++static Bool dlHdmiTxGetReflineRefpix
++(
++    tmdlHdmiTxVidFmt_t      vinFmt,    
++    tmdlHdmiTxVinMode_t     vinMode,   
++    tmdlHdmiTxVidFmt_t      voutFmt,   
++    UInt8                   syncIn,
++    tmdlHdmiTxPixRate_t     pixRate,
++    UInt16                  *pRefPix,  
++    UInt16                  *pRefLine, 
++    UInt16                  *pScRefPix,
++    UInt16                  *pScRefLine,
++    Bool                    *pbVerified
++);
++
++/* Use by tmdlHdmiTxSetInputOutput to set AVI infoframe */
++static tmErrorCode_t dlHdmiTxSetVideoInfoframe
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxVidFmt_t      voutFmt,
++    tmdlHdmiTxVoutMode_t    voutMode
++);
++
++/* Use to set AVI infoframe with raw data */
++static tmErrorCode_t dlHdmiTxSetRawVideoInfoframe 
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxAviIfData_t   *pContentVif,
++    Bool                    enable
++);
++
++/* Calculate Checksum for info frame */
++static UInt8
++dlHdmiTxcalculateCheksumIF
++(   
++    tmbslHdmiTxPktRawAvi_t   *pData     /* Pointer to checksum data */
++);
++
++/* IMPORTANT: The 3 functions define below should not be declared in static
++   in order to allow applicative API to call them. Those functions are not
++   in tmdlHdmiTx_Functions.h but are in tmdlHdmiTxCore.def */
++
++/* Get the device library state */
++tmdlHdmiTxDriverState_t dlHdmiTxGetState(tmInstance_t instance);
++
++/* Set pattern ON (Blue screen or color bar) */
++tmErrorCode_t dlHdmiTxSetTestPatternOn
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxVidFmt_t		voutFmt,
++    tmdlHdmiTxVoutMode_t    voutMode,
++    tmdlHdmiTxTestPattern_t pattern
++);
++
++/* Set pattern OFF */
++tmErrorCode_t dlHdmiTxSetTestPatternOff
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxVidFmt_t      voutFmt,
++    tmdlHdmiTxVoutMode_t    voutMode
++);
++
++/* Get DTD from BSL */
++static tmErrorCode_t dlHdmiTxEdidGetDTD
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    UInt8                           maxDTDesc,
++    UInt8                           *pWrittenDTDesc
++);
++
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_640HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors
++);
++
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_720HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    tmdlHdmiTxPictAspectRatio_t     pictureAspectRatio
++);
++
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_1280HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors
++);
++
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_1920HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    Bool                            formatInterlaced
++);
++
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_1440HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    tmdlHdmiTxPictAspectRatio_t     pictureAspectRatio,
++    Bool                            formatInterlaced
++);
++
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_2880HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    tmdlHdmiTxPictAspectRatio_t     pictureAspectRatio,
++    Bool                            formatInterlaced
++);
++
++static tmdlHdmiTxPictAspectRatio_t dlHdmiTxCalcAspectRatio (
++    UInt16    HImageSize,
++    UInt16    VImageSize
++);
++
++#ifndef NO_HDCP
++static void dlHdmiTxCheckHdcpBksv
++(
++    tmInstance_t    instance,
++    UInt8 *         pHdcpBksvTested,
++    Bool  *         pbBksvSecure,
++    Bool            bBigEndian
++);
++#endif
++
++/* Calculate table index according to video format value */
++static tmdlHdmiTxVidFmt_t dlHdmiTxCalcVidFmtIndex(tmdlHdmiTxVidFmt_t vidFmt);
++
++extern tmErrorCode_t tmbslDebugWriteFakeRegPage( tmUnitSelect_t txUnit );
++
++/*============================================================================*/
++/*                       VARIABLES DECLARATIONS                               */
++/*============================================================================*/
++
++tmdlHdmiTxIWSemHandle_t dlHdmiTxItSemaphore[MAX_UNITS];
++
++/* Unit configuration structure (device library system configuration) */
++unitConfig_t unitTableTx[MAX_UNITS] =
++{ 
++  { 
++    False,
++    False,
++    (tmdlHdmiTxHdcpOptions_t) HDCP_OPT_DEFAULT,
++    False,
++    False,
++    TMDL_HDMITX_DEVICE_UNKNOWN,
++    0,
++    0,
++    (tmdlHdmiTxIWTaskHandle_t) 0,
++    (tmdlHdmiTxIWQueueHandle_t) 0,
++    (tmdlHdmiTxIWTaskHandle_t) 0,
++    STATE_NOT_INITIALIZED,
++    (ptmdlHdmiTxCallback_t) 0,
++    {Null, 0,},
++  }
++};
++
++#ifndef TMFL_NO_RTOS
++
++tmdlHdmiTxIWFuncPtr_t commandTaskTableTx[MAX_UNITS] = {
++    CommandTaskUnit0
++    };
++
++tmdlHdmiTxIWFuncPtr_t hdcpTaskTableTx[MAX_UNITS] = {
++    HdcpTaskUnit0
++    };
++
++#endif /* TMFL_NO_RTOS */
++
++tmbslHdmiTxCallbackList_t callbackFuncTableTx;
++
++/* Device library configuration structure completed by dlHdmiTxGetConfig with
++   informations contained in config file */
++tmdlHdmiTxDriverConfigTable_t gtmdlHdmiTxDriverConfigTable[MAX_UNITS] = {
++    {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ,0, 0, 0, 0, 0, 0, 0, TMDL_HDMITX_PATTERN_OFF,0},
++};
++
++/* Video info (see instanceStatusInfoTx) */
++tmdlHdmiTxVideoInfo_t videoInfoListTx = {
++    False,
++    {TMDL_HDMITX_VFMT_03_720x480p_60Hz, TMDL_HDMITX_VINMODE_YUV422, TMDL_HDMITX_SYNCSRC_EXT_VS, TMDL_HDMITX_PIXRATE_SINGLE, TMDL_HDMITX_3D_NONE},
++    {TMDL_HDMITX_VFMT_03_720x480p_60Hz, TMDL_HDMITX_VOUTMODE_YUV422, TMDL_HDMITX_COLORDEPTH_24,TMDL_HDMITX_VQR_DEFAULT}
++};
++
++/* Audio info (see instanceStatusInfoTx) */
++tmdlHdmiTxAudioInfo_t audioInfoListTx = {
++    False,
++    {TMDL_HDMITX_AFMT_SPDIF, TMDL_HDMITX_AFS_48K,TMDL_HDMITX_I2SFOR_PHILIPS_L,TMDL_HDMITX_I2SQ_16BITS,TMDL_HDMITX_DSTRATE_SINGLE,0x00} 
++};
++
++/* Event state (see instanceStatusInfoTx) */
++tmdlHdmiTxEventState_t eventStateListTx[EVENT_NB] = {
++    {TMDL_HDMITX_HDCP_ACTIVE,           TMDL_HDMITX_EVENT_DISABLED},
++    {TMDL_HDMITX_HDCP_INACTIVE,         TMDL_HDMITX_EVENT_DISABLED},
++    {TMDL_HDMITX_HPD_ACTIVE,            TMDL_HDMITX_EVENT_DISABLED},
++    {TMDL_HDMITX_HPD_INACTIVE,          TMDL_HDMITX_EVENT_DISABLED},
++    {TMDL_HDMITX_RX_KEYS_RECEIVED,      TMDL_HDMITX_EVENT_DISABLED},
++    {TMDL_HDMITX_RX_DEVICE_ACTIVE,      TMDL_HDMITX_EVENT_DISABLED},
++    {TMDL_HDMITX_RX_DEVICE_INACTIVE,    TMDL_HDMITX_EVENT_DISABLED},
++    {TMDL_HDMITX_EDID_RECEIVED,         TMDL_HDMITX_EVENT_DISABLED},
++    {TMDL_HDMITX_VS_RPT_RECEIVED,       TMDL_HDMITX_EVENT_DISABLED}
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++    ,{TMDL_HDMITX_B_STATUS,              TMDL_HDMITX_EVENT_DISABLED}
++#endif /* HDMI_TX_REPEATER_ISR_MODE */
++};
++
++/* Color bars state (see instanceStatusInfoTx) */
++tmdlHdmiTxColBarState_t colorBarStateTx = {
++    False,
++    True,
++    True,
++    False,
++    False,
++    True,
++    False
++};
++
++tmdlHdmiTxGamutState_t gamutStateTx = {
++    False,
++    0,
++    TMDL_HDMITX_EXT_COLORIMETRY_XVYCC601,
++    False,
++    TMDL_HDMITX_YQR_LIMITED
++};
++
++
++/* Instance status (save the actual configuration) */
++instanceStatus_t instanceStatusInfoTx[MAX_UNITS] = { 
++    {(ptmdlHdmiTxVideoInfo_t)  &videoInfoListTx,
++     (ptmdlHdmiTxAudioInfo_t)  &audioInfoListTx,
++     (ptmdlHdmiTxEventState_t) eventStateListTx,
++     (ptmdlHdmiTxColBarState_t) &colorBarStateTx,
++     (ptmdlHdmiTxGamutState_t) &gamutStateTx }
++};
++
++/* HDCP seed table, arranged as pairs of 16-bit integers: lookup value, seed value.
++ * If no table is programmed and if KEY_SEED in config file is null, HDCP will be disabled */
++#define SEED_TABLE_LEN 10
++static const UInt16 kSeedTable[SEED_TABLE_LEN][2] = { 
++	{0, 0},
++	{0, 0},
++	{0, 0},
++	{0, 0},
++	{0, 0},
++	{0, 0},
++	{0, 0},
++	{0, 0},
++	{0, 0},
++	{0, 0}
++};
++
++#ifndef NO_HDCP
++tmdlHdmiTxHdcpInfo_t hdcpInfoListTx[MAX_UNITS];
++#endif /* NO_HDCP */
++
++
++static Bool gI2CDebugAccessesEnabled = True; /* For debug purpose only, used to manage underlying I2C accessed */
++
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++static Bool gIgnoreNextSha1 = False;
++#endif /*HDMI_TX_REPEATER_ISR_MODE*/
++
++/*============================================================================*/
++/*                              FUNCTIONS                                     */
++/*============================================================================*/
++
++/******************************************************************************
++    \brief Get the software version of the driver.
++
++    \param pSWVersion Pointer to the version structure.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetSWVersion
++(
++    tmSWVersion_t   *pSWVersion
++)
++{
++    /* Check if SWVersion pointer is Null */
++    RETIF(pSWVersion == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Copy SW version */
++    pSWVersion->compatibilityNr = VERSION_COMPATIBILITY;
++    pSWVersion->majorVersionNr = VERSION_MAJOR;
++    pSWVersion->minorVersionNr = VERSION_MINOR;
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Get the number of available HDMI transmitters devices in the system.
++           A unit directly represents a physical device.
++
++    \param pUnitCount Pointer to the number of available units.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetNumberOfUnits
++(
++    UInt32  *pUnitCount
++)
++{
++    /* Check if UnitCount pointer is Null */
++    RETIF(pUnitCount == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Copy the maximum number of units */
++    *pUnitCount = MAX_UNITS;
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Get the capabilities of unit 0. Capabilities are stored into a
++           dedicated structure and are directly read from the HW device.
++
++    \param pCapabilities Pointer to the capabilities structure.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetCapabilities
++(
++    tmdlHdmiTxCapabilities_t    *pCapabilities
++)
++{
++    /* Directly call GetCapabilitiesM function for unit 0 and return the result */
++    return(tmdlHdmiTxGetCapabilitiesM((tmUnitSelect_t)0, pCapabilities));
++}
++
++/******************************************************************************
++    \brief Get the capabilities of a specific unit. Capabilities are stored
++           into a dedicated structure and are directly read from the HW
++           device.
++
++    \param unit          Unit to be probed.
++    \param pCapabilities Pointer to the capabilities structure.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetCapabilitiesM
++(
++   tmUnitSelect_t           unit,
++   tmdlHdmiTxCapabilities_t *pCapabilities
++)
++{
++    tmErrorCode_t   errCode = TM_OK;
++    Bool            featureSupported;    
++
++    /* Check if unit number is in range */
++    RETIF((unit < 0) || (unit >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER)
++
++    /* Check if Capalities pointer is Null */
++    RETIF(pCapabilities == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Device version */
++    pCapabilities->deviceVersion = unitTableTx[unit].deviceVersion ;
++
++    /* Retrieve the capabilities from the BSL layer */   
++
++    /* HDCP support */
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_HDCP, &featureSupported) ) != TM_OK, errCode)
++
++    pCapabilities->hdcp = featureSupported;
++
++    /* Scaler support */
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_SCALER, &featureSupported) ) != TM_OK, errCode)
++
++    pCapabilities->scaler = featureSupported;
++    
++    /* Audio HBR support */
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_AUDIO_HBR, &featureSupported) ) != TM_OK, errCode)
++
++    pCapabilities->audioPacket.HBR = featureSupported;
++    
++    /* Audio OBA support */
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_AUDIO_OBA, &featureSupported) ) != TM_OK, errCode)
++
++    pCapabilities->audioPacket.oneBitAudio = featureSupported;
++
++    /* Audio DST support */
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_AUDIO_DST, &featureSupported) ) != TM_OK, errCode)
++
++    pCapabilities->audioPacket.DST = featureSupported;
++
++    /* HDMI version 1.1 support */
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_HDMI_1_1, &featureSupported) ) != TM_OK, errCode)
++
++    if (featureSupported)
++    {
++        pCapabilities->hdmiVersion = TMDL_HDMITX_HDMI_VERSION_1_1;
++    }
++
++    /* HDMI version 1.2A support */
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_HDMI_1_2A, &featureSupported) ) != TM_OK, errCode)
++
++    if (featureSupported)
++    {
++        pCapabilities->hdmiVersion = TMDL_HDMITX_HDMI_VERSION_1_2a;
++    }
++
++    /* HDMI version 1.3 support */
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_HDMI_1_3A, &featureSupported) ) != TM_OK, errCode)
++
++    if (featureSupported)
++    {
++        pCapabilities->hdmiVersion = TMDL_HDMITX_HDMI_VERSION_1_3a;
++    }
++
++    /* Deep Color support */
++    /* By default */
++    pCapabilities->colorDepth = TMDL_HDMITX_COLORDEPTH_24; 
++    
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_DEEP_COLOR_30, &featureSupported) ) != TM_OK, errCode)
++
++    if (featureSupported)
++    {
++        pCapabilities->colorDepth = TMDL_HDMITX_COLORDEPTH_30;
++    }
++
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_DEEP_COLOR_36, &featureSupported) ) != TM_OK, errCode)
++
++    if (featureSupported)
++    {
++        pCapabilities->colorDepth = TMDL_HDMITX_COLORDEPTH_36;
++    }
++
++    RETIF( (errCode = tmbslHdmiTxHwGetCapabilities(unit, 
++        HDMITX_FEATURE_HW_DEEP_COLOR_48, &featureSupported) ) != TM_OK, errCode)
++
++    if (featureSupported)
++    {
++        pCapabilities->colorDepth = TMDL_HDMITX_COLORDEPTH_48;
++    }
++
++    return errCode;
++}
++
++/******************************************************************************
++    \brief Open unit 0 of HdmiTx driver and provides the instance number to
++           the caller. Note that one unit of HdmiTx represents one physical
++           HDMI transmitter and that only one instance per unit can be opened.
++
++    \param pInstance Pointer to the variable that will receive the instance
++                     identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the transmitter instance is not initialised
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOURCE_OWNED: the resource is already in use
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_INIT_FAILED: the unit instance is already
++              initialised or something wrong happened at lower level.
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number 
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: the unit is not initialized
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter is invalid or out 
++              of range
++            - TMBSL_ERR_HDMI_INIT_FAILED: the unit instance is already 
++              initialised
++            - TMBSL_ERR_HDMI_COMPATIBILITY: the driver is not compatiable 
++              with the internal device version code
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxOpen
++(
++    tmInstance_t   *pInstance
++)
++{
++    /* Directly call OpenM function for unit 0 and return the result */
++    return(tmdlHdmiTxOpenM(pInstance, (tmUnitSelect_t)0));
++}
++
++/******************************************************************************
++    \brief Open a specific unit of HdmiTx driver and provides the instance
++           number to the caller. Note that one unit of HdmiTx represents one
++           physical HDMI transmitter and that only one instance per unit can be
++           opened. This function switches driver's state machine to
++           "initialized" state.
++
++    \param pInstance Pointer to the structure that will receive the instance
++                     identifier.
++    \param unit      Unit number to be opened.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the transmitter instance is not initialised
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOURCE_OWNED: the resource is already in use
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_INIT_FAILED: the unit instance is already
++              initialised or something wrong happened at lower level.
++            - TMDL_ERR_DLHDMITX_NO_RESOURCES: the resource is not available
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number 
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: the unit is not initialized
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter is invalid or out 
++              of range
++            - TMBSL_ERR_HDMI_INIT_FAILED: the unit instance is already 
++              initialised
++            - TMBSL_ERR_HDMI_COMPATIBILITY: the driver is not compatiable 
++              with the internal device version code
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxOpenM
++(
++    tmInstance_t   *pInstance,
++    tmUnitSelect_t  unit
++)
++{
++    tmErrorCode_t           errCode;
++    tmErrorCode_t           errCodeSem;
++    UInt16                  i;
++    UInt8                   deviceVersion;
++    Bool                    featureSupported;
++
++    /* Check if unit number is in range */
++    RETIF((unit < 0) || (unit >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER)
++
++    /* Check if Instance pointer is Null */
++    RETIF(pInstance == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    
++    /* Create the semaphore to protect variables modified under interruption */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreCreate(&dlHdmiTxItSemaphore[unit]) ) != TM_OK, errCode)
++
++    /* Take the sempahore */
++    RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[unit]) ) != TM_OK, errCodeSem)
++
++    /* Check if unit is already instanciated */
++    RETIF_SEM(dlHdmiTxItSemaphore[unit],
++        unitTableTx[unit].opened == True, TMDL_ERR_DLHDMITX_RESOURCE_OWNED)
++
++    /* Check the state */
++    RETIF_SEM(dlHdmiTxItSemaphore[unit], 
++        dlHdmiTxGetState(unit) != STATE_NOT_INITIALIZED, TMDL_ERR_DLHDMITX_INVALID_STATE) 
++
++	/* Instanciate unit and return corresponding instance number */
++    /* Since HW unit are only instanciable once, instance = unit */
++    unitTableTx[unit].opened                = True;
++    unitTableTx[unit].hdcpEnable            = False;
++    unitTableTx[unit].repeaterEnable        = False;
++    unitTableTx[unit].deviceVersion         = TMDL_HDMITX_DEVICE_UNKNOWN;
++    unitTableTx[unit].simplayHd             = False;
++    unitTableTx[unit].pCallback             = Null;
++    unitTableTx[unit].revocationList.pList  = Null;
++    unitTableTx[unit].revocationList.length = 0;
++    
++    /* Recover the configuration of the device library */
++    RETIF_SEM(dlHdmiTxItSemaphore[unit],
++        dlHdmiTxGetConfig(unit, &gtmdlHdmiTxDriverConfigTable[unit])!= TM_OK, TMDL_ERR_DLHDMITX_INIT_FAILED)
++
++#ifndef TMFL_NO_RTOS
++    
++    /* Create message queue associated to this instance/unit */
++    RETIF_SEM(dlHdmiTxItSemaphore[unit],
++        tmdlHdmiTxIWQueueCreate(gtmdlHdmiTxDriverConfigTable[unit].commandTaskQueueSize,
++        &(unitTableTx[unit].queueHandle)) != TM_OK, TMDL_ERR_DLHDMITX_NO_RESOURCES)
++
++    /* Create the command task associated to this instance/unit */
++    RETIF_SEM(dlHdmiTxItSemaphore[unit],
++        tmdlHdmiTxIWTaskCreate(commandTaskTableTx[unit],
++        gtmdlHdmiTxDriverConfigTable[unit].commandTaskPriority,
++        gtmdlHdmiTxDriverConfigTable[unit].commandTaskStackSize,
++        &(unitTableTx[unit].commandTaskHandle)) != TM_OK, TMDL_ERR_DLHDMITX_NO_RESOURCES)
++
++    RETIF_SEM(dlHdmiTxItSemaphore[unit],
++        tmdlHdmiTxIWTaskStart(unitTableTx[unit].commandTaskHandle) != TM_OK, TMDL_ERR_DLHDMITX_NO_RESOURCES)
++
++	/* Create the hdcp check task associated to this instance/unit */
++#ifndef NO_HDCP
++    RETIF_SEM(dlHdmiTxItSemaphore[unit],
++        tmdlHdmiTxIWTaskCreate(hdcpTaskTableTx[unit],
++        gtmdlHdmiTxDriverConfigTable[unit].hdcpTaskPriority,
++        gtmdlHdmiTxDriverConfigTable[unit].hdcpTaskStackSize,
++        &(unitTableTx[unit].hdcpTaskHandle)) != TM_OK, TMDL_ERR_DLHDMITX_NO_RESOURCES)
++#endif /* NO_HDCP */
++
++#endif /* TMFL_NO_RTOS */
++
++    *pInstance = (tmInstance_t)unit;
++
++#ifndef NO_HDCP
++    hdcpInfoListTx[unit].bKsvSecure = False;
++    hdcpInfoListTx[unit].hdcpKsvDevices = 0;
++    for(i=0; i<TMDL_HDMITX_KSV_BYTES_PER_DEVICE; i++) { hdcpInfoListTx[unit].hdcpBksv[i] = 0; }
++    hdcpInfoListTx[unit].hdcpDeviceDepth = 0;
++#endif /* NO_HDCP */
++
++    /* Init the BSL */
++	/* Make sure all events are disabled */
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_HDCP_ACTIVE].status = TMDL_HDMITX_EVENT_DISABLED;
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_HDCP_INACTIVE].status = TMDL_HDMITX_EVENT_DISABLED;
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_HPD_ACTIVE].status = TMDL_HDMITX_EVENT_DISABLED;
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_HPD_INACTIVE].status = TMDL_HDMITX_EVENT_DISABLED;
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_RX_KEYS_RECEIVED].status = TMDL_HDMITX_EVENT_DISABLED;
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_RX_DEVICE_ACTIVE].status = TMDL_HDMITX_EVENT_DISABLED;
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_RX_DEVICE_INACTIVE].status = TMDL_HDMITX_EVENT_DISABLED;
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_EDID_RECEIVED].status = TMDL_HDMITX_EVENT_DISABLED;
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_VS_RPT_RECEIVED].status = TMDL_HDMITX_EVENT_DISABLED;
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++    instanceStatusInfoTx[unit].pEventState[TMDL_HDMITX_B_STATUS].status = TMDL_HDMITX_EVENT_DISABLED;
++#endif /* HDMI_TX_REPEATER_ISR_MODE */
++    instanceStatusInfoTx[unit].pColBarState->disableColorBarOnR0 = False;
++    instanceStatusInfoTx[unit].pColBarState->hdcpColbarChange = False;
++    instanceStatusInfoTx[unit].pColBarState->hdcpEncryptOrT0 = True;
++    instanceStatusInfoTx[unit].pColBarState->hdcpSecureOrT0 = False;
++    instanceStatusInfoTx[unit].pColBarState->inOutFirstSetDone = False;
++    instanceStatusInfoTx[unit].pColBarState->colorBarOn = False;
++    instanceStatusInfoTx[unit].pColBarState->changeColorBarNow = False;
++
++    instanceStatusInfoTx[unit].pGamutState->gamutOn = False;
++    instanceStatusInfoTx[unit].pGamutState->gamutBufNum = 0; /* use buffer 0 by default */
++    instanceStatusInfoTx[unit].pGamutState->wideGamutColorSpace = TMDL_HDMITX_EXT_COLORIMETRY_XVYCC601;
++    instanceStatusInfoTx[unit].pGamutState->extColOn = False;
++    instanceStatusInfoTx[unit].pGamutState->yccQR = TMDL_HDMITX_YQR_LIMITED;
++
++
++    instanceStatusInfoTx[unit].pAudioInfo->audioMuteState = False; /* Initially audio is not muted */
++
++
++
++    /* The funcCallback is not the same between BSL, so fill it dynamically */
++    for(i=0; i<HDMITX_CALLBACK_INT_NUM; i++)
++    {
++        callbackFuncTableTx.funcCallback[i] = Null;
++    }
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_ENCRYPT] = dlHdmiTxHandleENCRYPT;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_HPD] = dlHdmiTxHandleHPD;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_T0] = dlHdmiTxHandleT0;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_BCAPS] = dlHdmiTxHandleBCAPS;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_BSTATUS] = dlHdmiTxHandleBSTATUS;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_SHA_1] = dlHdmiTxHandleSHA_1;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_PJ] = dlHdmiTxHandlePJ;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_R0] = dlHdmiTxHandleR0;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_SW_INT] = dlHdmiTxHandleSW_INT;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_RX_SENSE] = dlHdmiTxHandleRX_SENSE;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_EDID_BLK_READ] = dlHdmiTxHandleEDID_READ;
++    callbackFuncTableTx.funcCallback[HDMITX_CALLBACK_INT_VS_RPT] = dlHdmiTxHandleVS_RPT;
++
++    /* Prepare static TDA9984 driver data as the compiler doesn't seem to */
++
++    tmbslHdmiTxHwStartup();
++    errCode = tmbslHdmiTxInit(*pInstance, 
++                gtmdlHdmiTxDriverConfigTable[unit].i2cAddress,
++                gtmdlHdmiTxDriverConfigTable[unit].i2cWriteFunction,
++                gtmdlHdmiTxDriverConfigTable[unit].i2cReadFunction,
++                (ptmbslHdmiTxSysFuncEdid_t)0, /* Not used for TDA9984 */
++                (ptmbslHdmiTxSysFuncTimer_t)tmdlHdmiTxIWWait,
++                &callbackFuncTableTx,
++                False, /* Alternate EDID address not used */
++                (tmbslHdmiTxVidFmt_t)instanceStatusInfoTx[unit].pVideoInfo->videoInConfig.format,
++                (tmbslHdmiTxPixRate_t)instanceStatusInfoTx[unit].pVideoInfo->videoInConfig.pixelRate);
++    if (errCode != TM_OK)
++    {
++        /* Init failed */
++        tmbslHdmiTxDeinit(unit);
++
++        /* Release the sempahore */
++        RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[unit]) ) != TM_OK, errCodeSem)
++
++        return errCode;
++    }
++    else
++    {
++        /* Init passed, continue */
++
++        /* Start by forcing the TMDS ouputs off */
++        errCode = tmbslHdmiTxTmdsSetOutputs(unit,
++            HDMITX_TMDSOUT_FORCED0);
++        RETIF_SEM(dlHdmiTxItSemaphore[unit], (errCode != TM_OK) && (errCode != TMBSL_ERR_HDMI_NOT_SUPPORTED), errCode)
++
++        RETIF_SEM(dlHdmiTxItSemaphore[unit],
++            (errCode = tmbslHdmiTxHwGetCapabilities(unit,
++            HDMITX_FEATURE_HW_HDCP, &featureSupported) ) != TM_OK, errCode)
++
++#ifndef NO_HDCP
++        if (featureSupported == True)
++        {
++			dlHdmiTxFindHdcpSeed(unit);
++        }
++#endif /* NO_HDCP */
++
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++        tmbslHdmiTxHdcpPowerDown(unit,True);
++#endif
++        /* Retrieve the hardware device version from the BSL layer */
++        RETIF_SEM(dlHdmiTxItSemaphore[unit],
++                  (errCode = tmbslHdmiTxHwGetVersion(unit,&deviceVersion) ) \
++                  != TM_OK, errCode);
++
++        /* Store the hardware device version in the global variable */
++        switch (deviceVersion)
++           {
++           case BSLHDMITX_TDA9984:
++              unitTableTx[unit].deviceVersion = TMDL_HDMITX_DEVICE_TDA9984;
++              break;
++              
++           case BSLHDMITX_TDA9989:
++              unitTableTx[unit].deviceVersion = TMDL_HDMITX_DEVICE_TDA9989;
++              break;
++              
++	       case BSLHDMITX_TDA9981:
++              unitTableTx[unit].deviceVersion = TMDL_HDMITX_DEVICE_TDA9981;
++              break;
++              
++           case BSLHDMITX_TDA9983:
++              unitTableTx[unit].deviceVersion = TMDL_HDMITX_DEVICE_TDA9983;
++              break;
++              
++           case BSLHDMITX_TDA19989:
++              unitTableTx[unit].deviceVersion = TMDL_HDMITX_DEVICE_TDA19989;
++              break;
++              
++           case BSLHDMITX_TDA19988:
++              unitTableTx[unit].deviceVersion = TMDL_HDMITX_DEVICE_TDA19988;
++              break;
++              
++	       default:
++              unitTableTx[unit].deviceVersion = TMDL_HDMITX_DEVICE_UNKNOWN;
++              break;
++           }
++    }
++
++
++#ifndef TMFL_NO_RTOS
++	/* Start HDCP check task */
++
++#ifndef NO_HDCP
++    RETIF_SEM(dlHdmiTxItSemaphore[unit],
++        tmdlHdmiTxIWTaskStart(unitTableTx[unit].hdcpTaskHandle) != TM_OK, TMDL_ERR_DLHDMITX_NO_RESOURCES)
++#endif /* NO_HDCP */
++
++#endif /* TMFL_NO_RTOS */
++
++
++	/* Set the state machine to initialized */
++    dlHdmiTxSetState(unit, STATE_INITIALIZED);
++
++    /* Release the sempahore */
++    RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[unit]) ) != TM_OK, errCodeSem)
++    
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Close an instance of HdmiTx driver.
++
++    \param instance Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own 
++              the resource
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxClose
++(
++    tmInstance_t    instance
++)
++{
++    tmErrorCode_t   errCode = TM_OK;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check if unit corresponding to instance is opened */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        unitTableTx[instance].opened == False, TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED)
++
++    /* Close instance */
++    unitTableTx[instance].opened = False;
++    
++    /* Set the state machine */
++    dlHdmiTxSetState(instance, STATE_NOT_INITIALIZED);
++    
++    /* Destroy resources allocated for this instance/unit */
++
++#ifndef TMFL_NO_RTOS
++
++#ifndef NO_HDCP
++    tmdlHdmiTxIWTaskDestroy(unitTableTx[instance].hdcpTaskHandle);
++#endif /* NO_HDCP */
++
++    tmdlHdmiTxIWTaskDestroy(unitTableTx[instance].commandTaskHandle);
++    tmdlHdmiTxIWQueueDestroy(unitTableTx[instance].queueHandle);
++
++#endif /* TMFL_NO_RTOS */
++
++    /* Reset an instance of an HDMI transmitter */
++	tmbslHdmiTxDeinit(instance);
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Close the handle to the semaphore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreDestroy(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Set the power state of an instance of the HDMI transmitter.
++
++    \param instance   Instance identifier.
++    \param powerState Power state to set.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number 
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetPowerState
++(
++    tmInstance_t    instance,
++    tmPowerState_t  powerState
++)
++{
++    tmErrorCode_t           errCode;
++    tmbslHdmiTxHotPlug_t    hpdStatus;  /* HPD status */
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    if  (unitTableTx[instance].deviceVersion == TMDL_HDMITX_DEVICE_TDA9984)
++    {
++	    if (powerState == tmPowerSuspend)
++	    {
++	        return TMDL_ERR_DLHDMITX_NOT_SUPPORTED;
++	    }
++    }
++
++
++
++
++    /* Switch off HDCP */
++    if ( ((powerState == tmPowerOff) && (unitTableTx[instance].hdcpEnable == True)) 
++         || ((powerState == tmPowerStandby) && (unitTableTx[instance].hdcpEnable == True))
++         || ((powerState == tmPowerSuspend) && (unitTableTx[instance].hdcpEnable == True))
++       )
++    {
++        /* Release the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++        /* Switch off HDCP */
++        RETIF( (errCode = tmdlHdmiTxSetHdcp(instance, False) ) != TM_OK, errCode)
++        /* Take the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++    }
++
++
++    /* TDA9989, TDA19989 and TDA19988 only */
++    if  ( (unitTableTx[instance].deviceVersion == TMDL_HDMITX_DEVICE_TDA9989)
++          ||
++          (unitTableTx[instance].deviceVersion == TMDL_HDMITX_DEVICE_TDA19989)
++          ||
++          (unitTableTx[instance].deviceVersion == TMDL_HDMITX_DEVICE_TDA19988))
++
++    {
++        if ((powerState != tmPowerOn) && (powerState != tmPowerSuspend)) {
++            dlHdmiTxSetState(instance, STATE_INITIALIZED);
++        }
++
++        if ((powerState == tmPowerOn) && (unitTableTx[instance].simplayHd == True)) {
++
++    instanceStatusInfoTx[0].pColBarState->disableColorBarOnR0 = False;
++    instanceStatusInfoTx[0].pColBarState->hdcpColbarChange = False;
++    instanceStatusInfoTx[0].pColBarState->hdcpEncryptOrT0 = True;
++    instanceStatusInfoTx[0].pColBarState->hdcpSecureOrT0 = False;
++    instanceStatusInfoTx[0].pColBarState->inOutFirstSetDone = False;
++    instanceStatusInfoTx[0].pColBarState->colorBarOn = True;
++    instanceStatusInfoTx[0].pColBarState->changeColorBarNow = True;
++    
++        }
++
++    }
++
++    /* Set the power state of the transmitter */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxPowerSetState(instance, 
++        powerState) ) != TM_OK, errCode)
++
++    /* Get Hot Plug status */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxHotPlugGetStatus(instance,
++                                               &hpdStatus,False) ) != TM_OK, errCode)
++
++    if (powerState == tmPowerOn)
++    {
++        if ((hpdStatus == HDMITX_HOTPLUG_ACTIVE) && (dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE))
++        {
++            /* Yes: Wait for DDC line to settle before reading EDID */
++            tmbslHdmiTxSysTimerWait(instance,
++                    500); /* ms */
++
++            /* Request EDID read */
++            RETIF_SEM(dlHdmiTxItSemaphore[instance],
++                (errCode = tmbslHdmiTxEdidRequestBlockData(instance,
++                unitTableTx[instance].pEdidBuffer, (Int)((unitTableTx[instance].edidBufferSize) >> 7),
++                (Int)(unitTableTx[instance].edidBufferSize)) ) != TM_OK, errCode)
++        }
++    }
++        
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Get the power state of an instance of the HDMI transmitter.
++
++    \param instance    Instance identifier.
++    \param pPowerState Pointer to the power state.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetPowerState
++(
++    tmInstance_t    instance,
++    tmPowerState_t  *pPowerState
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if PowerState pointer is Null */
++    RETIF(pPowerState == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Get the power state of the transmitter */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxPowerGetState(instance,
++        pPowerState) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Set the configuration of instance attributes. This function is
++           required by DVP architecture rules but actually does nothing in this
++           driver.
++
++    \param instance    Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxInstanceConfig
++(
++    tmInstance_t    instance
++)
++{
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Setup the instance with its configuration parameters. This function
++           allows basic instance configuration like enabling HDCP, choosing
++           HDCP encryption mode or enabling HDCP repeater mode.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure containing all setup parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own 
++              the resource
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxInstanceSetup
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxInstanceSetupInfo_t   *pSetupInfo
++)
++{
++    tmErrorCode_t   errCode;
++#ifndef NO_HDCP
++    UInt16          i;
++#endif
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if SetupInfo pointer is NULL */
++    RETIF(pSetupInfo == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check if unit corresponding to instance is opened */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        unitTableTx[instance].opened == False, TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED)
++
++    /* Check the state */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        dlHdmiTxGetState(instance) != STATE_INITIALIZED, TMDL_ERR_DLHDMITX_INVALID_STATE) 
++
++    unitTableTx[instance].repeaterEnable = pSetupInfo->repeaterEnable;
++    unitTableTx[instance].simplayHd = pSetupInfo->simplayHd;
++    unitTableTx[instance].pEdidBuffer = pSetupInfo->pEdidBuffer;
++    unitTableTx[instance].edidBufferSize = pSetupInfo->edidBufferSize;
++    
++#ifndef NO_HDCP
++    /* Reset HDCP DevLib data */
++    hdcpInfoListTx[instance].hdcpCheckState = TMDL_HDMITX_HDCP_CHECK_NOT_STARTED;
++    hdcpInfoListTx[instance].hdcpErrorState = 0;
++    hdcpInfoListTx[instance].hdcpKsvDevices = 0;
++    hdcpInfoListTx[instance].bKsvSecure = False;
++    for(i=0; i<TMDL_HDMITX_KSV_BYTES_PER_DEVICE; i++) { hdcpInfoListTx[instance].hdcpBksv[i] = 0; }
++    hdcpInfoListTx[instance].hdcpDeviceDepth = 0;
++
++    hdcpInfoListTx[instance].hdcpMaxCascExceeded = False;
++    hdcpInfoListTx[instance].hdcpMaxDevsExceeded = False;
++#endif /* NO_HDCP */
++
++    /* Set state machine to Unplugged */
++    dlHdmiTxSetState(instance, STATE_UNPLUGGED);
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Get instance setup parameters.
++
++    \param instance   Instance identifier.
++    \param pSetupInfo Pointer to the structure that will receive setup
++                      parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own 
++              the resource
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetInstanceSetup
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxInstanceSetupInfo_t   *pSetupInfo
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if SetupInfo pointer is NULL */
++    RETIF(pSetupInfo == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check if unit corresponding to instance is opened */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        unitTableTx[instance].opened == False, TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED)
++
++    pSetupInfo->simplayHd          = unitTableTx[instance].simplayHd;
++    pSetupInfo->repeaterEnable     = unitTableTx[instance].repeaterEnable;
++    /* JL, TODO */
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Make device library handle an incoming interrupt. This function is
++           used by application to tell the device library that the hardware
++           sent an interrupt.
++
++    \param instance   Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own 
++              the resource
++            - TMDL_ERR_DLHDMITX_FULL: the queue is full
++
++ ******************************************************************************/
++tmErrorCode_t tmdlHdmiTxHandleInterrupt
++(
++    tmInstance_t    instance
++)
++{
++#ifndef TMFL_NO_RTOS
++    tmErrorCode_t errCode;
++    UInt8         message = 0;
++#else
++    tmErrorCode_t err = TM_OK;
++#endif /* TMFL_NO_RTOS */
++
++   /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++ 
++#ifndef TMFL_NO_RTOS   
++    RETIF( (errCode = tmdlHdmiTxIWQueueSend(unitTableTx[instance].queueHandle, message)) != TM_OK, errCode)
++
++    /* Disable interrupts for Tx until the callbacks have been done by the command task */
++    switch(instance)
++    {
++        case INSTANCE_0:
++            tmdlHdmiTxIWDisableInterrupts(TMDL_HDMI_IW_TX_1);
++            break;
++        case INSTANCE_1:
++            tmdlHdmiTxIWDisableInterrupts(TMDL_HDMI_IW_TX_2);
++            break;
++        default:
++            return TMDL_ERR_DLHDMITX_BAD_INSTANCE;
++    }
++#else
++
++        /* Clear T0 flag before polling for interrupts */
++        instanceStatusInfoTx[0].pColBarState->hdcpSecureOrT0 = False;
++
++        if (gI2CDebugAccessesEnabled == True)
++        {
++
++            err = tmbslHdmiTxHwHandleInterrupt(0);
++        
++            if ((err == TMBSL_ERR_HDMI_I2C_WRITE) || (err == TMBSL_ERR_HDMI_I2C_READ))
++            {
++
++                unitTableTx[0].pCallback(TMDL_HDMITX_DEBUG_EVENT_1);
++            }
++
++        }/* (gI2CDebugAccessesEnabled == True) */
++
++
++#endif /* TMFL_NO_RTOS */
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Register event callbacks. Only one callback is registered through
++           this API. This callback will received the type of event that
++           occured throug a dedicated parameter and will be called as many
++           times as there is pending events.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance   Instance identifier.
++    \param pCallback  Pointer to the callback function that will handle events
++                      from the devlib.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED: the caller does not own
++              the resource
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxRegisterCallbacks
++(
++    tmInstance_t            instance,
++    ptmdlHdmiTxCallback_t   pCallback
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check if unit corresponding to instance is opened */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        unitTableTx[instance].opened == False, TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED)
++    
++    /* Check if instance state is correct */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        dlHdmiTxGetState(instance) != STATE_INITIALIZED, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Store callback pointers */
++    unitTableTx[instance].pCallback = pCallback;
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief This function allows enabling a specific event. By default, all
++           events are disabled, except input lock.
++
++    \param instance Instance identifier.
++    \param event    Event to enable.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxEnableEvent
++(
++    tmInstance_t        instance,
++    tmdlHdmiTxEvent_t   event
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if the event exists */
++    RETIF_BADPARAM(event >= EVENT_NB)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Protect the access to this ressource */
++    instanceStatusInfoTx[instance].pEventState[event].status = TMDL_HDMITX_EVENT_ENABLED;
++  
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief This function allows disabling a specific event. By default, all
++           events are disabled, except input lock.
++
++    \param instance Instance identifier.
++    \param event    Event to disable.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxDisableEvent
++(
++    tmInstance_t        instance,
++    tmdlHdmiTxEvent_t   event
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if the event exists */
++    RETIF_BADPARAM(event >= EVENT_NB)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Protect the access to this ressource */
++    instanceStatusInfoTx[instance].pEventState[event].status = TMDL_HDMITX_EVENT_DISABLED;
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Get specifications of a given video format. Application can use
++           this function to retreives all specifications (frequencies,
++           resolution, etc.) of a given IA/CEA 861-D video format.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance         Instance identifier.
++    \param resolutionID     ID of the resolution to retrieve specs from.
++    \param pResolutionSpecs Pointer to the structure receiving specs.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_RESOLUTION_UNKNOWN: the resolution is unknown
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetVideoFormatSpecs
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxVidFmt_t      resolutionID,
++    tmdlHdmiTxVidFmtSpecs_t *pResolutionSpecs
++)
++{
++    UInt8	i;
++    Bool    find = False;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if ResolutionSpecs pointer is Null */
++    RETIF(pResolutionSpecs == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    for (i = 0; i < RESOLUTION_NB; i++)
++    {
++        if(resolutionID == gtmdlHdmiTxDriverConfigTable[instance].pResolutionInfo[i].resolutionID)
++        {
++            find = True;
++            pResolutionSpecs->height      = gtmdlHdmiTxDriverConfigTable[instance].pResolutionInfo[i].height;
++            pResolutionSpecs->width       = gtmdlHdmiTxDriverConfigTable[instance].pResolutionInfo[i].width;
++            pResolutionSpecs->interlaced  = gtmdlHdmiTxDriverConfigTable[instance].pResolutionInfo[i].interlaced;
++            pResolutionSpecs->vfrequency  = gtmdlHdmiTxDriverConfigTable[instance].pResolutionInfo[i].vfrequency;
++            pResolutionSpecs->aspectRatio = gtmdlHdmiTxDriverConfigTable[instance].pResolutionInfo[i].aspectRatio;
++            
++            /* Transformation of 2D-interlaced formats into 3DFP-progressif formats */
++            if((instanceStatusInfoTx[instance].pVideoInfo->videoInConfig.structure3D == TMDL_HDMITX_3D_FRAME_PACKING)
++               && pResolutionSpecs->interlaced && ((resolutionID == TMDL_HDMITX_VFMT_20_1920x1080i_50Hz)
++                                                   || (resolutionID == TMDL_HDMITX_VFMT_05_1920x1080i_60Hz)))
++            {
++                pResolutionSpecs->interlaced = False;
++                if(pResolutionSpecs->vfrequency == TMDL_HDMITX_VFREQ_50Hz)
++                {
++                   pResolutionSpecs->vfrequency = TMDL_HDMITX_VFREQ_25Hz;
++                }
++                else if((pResolutionSpecs->vfrequency == TMDL_HDMITX_VFREQ_60Hz) || (pResolutionSpecs->vfrequency == TMDL_HDMITX_VFREQ_59Hz))
++                {
++                   pResolutionSpecs->vfrequency = TMDL_HDMITX_VFREQ_30Hz;
++                }
++            }
++            
++            break;
++        }
++    }
++
++    /* Resolution not found in table */
++    RETIF(find == False, TMDL_ERR_DLHDMITX_RESOLUTION_UNKNOWN)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Configures all input and output parameters : format, modes, rates,
++           etc. This is the main configuration function of the driver. Here
++           are transmitted all crucial input and output parameters of the
++           device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance          Instance identifier.
++    \param videoInputConfig  Configuration of the input video.
++    \param videoOutputConfig Configuration of the output video.
++    \param audioInputConfig  Configuration of the input audio.
++    \param sinkType          Type of sink connected to the output of the Tx.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetInputOutput
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxVideoInConfig_t   videoInputConfig,
++    tmdlHdmiTxVideoOutConfig_t  videoOutputConfig,
++    tmdlHdmiTxAudioInConfig_t   audioInputConfig,
++    tmdlHdmiTxSinkType_t        sinkType
++)
++{
++    tmErrorCode_t           errCode;
++    UInt8                   pixRepeat;                  /* Pixel repetition */
++    tmbslHdmiTxVoutDbits_t  pathBits;                   /* Data path bit width */
++    tmbslHdmiTxPixEdge_t    pixelEdge;                  /* Pixel sampling edge */
++    tmbslHdmiTxVsMeth_t     syncMethod;                 /* Sync method */
++    tmbslHdmiTxPixTogl_t    toggle;                     /* Toggling */
++    UInt8                   syncIn;                     /* Embedded or external */
++    tmbslHdmiTxPixSubpkt_t  spSync;                     /* Subpacket sync */
++    tmbslHdmiTxBlnkSrc_t    blankit;                    /* Blanking */
++    tmbslHdmiTxPixRate_t    pixRateSingleDouble;        /* HDMITX_PIXRATE_SINGLE */
++    UInt16                  uRefPix;                    /* REFPIX for output */
++    UInt16                  uRefLine;                   /* REFLINE for output */
++    UInt16                  uScRefPix=0;                /* REFPIX for scaler */
++    UInt16                  uScRefLine=0;               /* REFLINE for scaler */
++    Bool                    bVerified;                  /* Scaler setting verified */
++    tmbslHdmiTxTopSel_t     topSel;                     /* Adjustment for interlaced output */
++    tmbslHdmiTxHPhases_t    phasesH;                    /* Horizontal phase */
++    tmbslHdmiTxVsOnce_t     once;                       /* Line/pixel counters sync */
++    tmbslHdmiTxScaMode_t    scalerMode;                 /* Current scaler mode */
++    Bool                    OBASupported;               /* OBA supported or not */
++    Bool                    DSTSupported;               /* DST supported or not */
++    Bool                    HBRSupported;               /* HBR supporeted or not */
++
++    UInt8                   *pSwapTable = Null;         /* Initialized after (depend on video mode used) */
++    UInt8                   *pMirrorTable = Null;       /* Initialized after (depend on video mode used) */
++#ifdef TMFL_RGB_DDR_12BITS
++    UInt8                   *pMux = Null;                 /* Initialized after (depend on video mode used) */
++#endif
++    UInt8                   *pEnaVideoPortTable = Null; /* Initialized after (depend on video mode used) */
++    UInt8                   *pGndVideoPortTable = Null; /* Initialized after (depend on video mode used) */
++    tmdlHdmiTxVidFmt_t      vinFmtIndex;                /* index in table kVfmtToShortFmt_TV */
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Update the instance status information */
++    instanceStatusInfoTx[instance].pVideoInfo->videoInConfig.format       = videoInputConfig.format;
++    instanceStatusInfoTx[instance].pVideoInfo->videoInConfig.mode         = videoInputConfig.mode;
++    instanceStatusInfoTx[instance].pVideoInfo->videoInConfig.syncSource   = videoInputConfig.syncSource;
++    instanceStatusInfoTx[instance].pVideoInfo->videoInConfig.pixelRate    = videoInputConfig.pixelRate;
++    instanceStatusInfoTx[instance].pVideoInfo->videoInConfig.structure3D  = videoInputConfig.structure3D;
++
++    instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format      = videoOutputConfig.format;
++    instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.mode        = videoOutputConfig.mode;
++    instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.colorDepth  = videoOutputConfig.colorDepth;
++
++    /* TODO */
++    /*instanceStatusInfoTx[instance].pVideoInfo->videoMuteState            = */
++
++    /* Audio OBA support */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxHwGetCapabilities(instance, 
++        HDMITX_FEATURE_HW_AUDIO_OBA, &OBASupported) ) != TM_OK, errCode)
++
++    /* Audio DST support */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxHwGetCapabilities(instance, 
++        HDMITX_FEATURE_HW_AUDIO_DST, &DSTSupported) ) != TM_OK, errCode)
++
++    /* Audio HBR support */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxHwGetCapabilities(instance, 
++        HDMITX_FEATURE_HW_AUDIO_HBR, &HBRSupported) ) != TM_OK, errCode)
++
++    /* Test if audio input format is supported */
++    if ( ((audioInputConfig.format == TMDL_HDMITX_AFMT_OBA) && (OBASupported == False)) ||
++	         ((audioInputConfig.format == TMDL_HDMITX_AFMT_DST) && (DSTSupported == False)) ||
++             ((audioInputConfig.format == TMDL_HDMITX_AFMT_HBR) && (HBRSupported == False)) )
++    {
++        /* Release the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++        return TMDL_ERR_DLHDMITX_NOT_SUPPORTED;
++    }
++
++    instanceStatusInfoTx[instance].pAudioInfo->audioInCfg.format            = audioInputConfig.format;
++    instanceStatusInfoTx[instance].pAudioInfo->audioInCfg.i2sFormat         = audioInputConfig.i2sFormat;
++    instanceStatusInfoTx[instance].pAudioInfo->audioInCfg.i2sQualifier      = audioInputConfig.i2sQualifier;
++    instanceStatusInfoTx[instance].pAudioInfo->audioInCfg.rate              = audioInputConfig.rate;
++    instanceStatusInfoTx[instance].pAudioInfo->audioInCfg.channelAllocation = audioInputConfig.channelAllocation;
++
++
++    if (sinkType == TMDL_HDMITX_SINK_EDID)
++    {
++        /* Change sink type with the currently defined in EDID */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxEdidGetSinkType(instance, 
++            (tmbslHdmiTxSinkType_t *)&sinkType) ) != TM_OK, errCode)
++    }
++
++    /* forbid format with pixel repetition in DVI */
++    if (sinkType == TMDL_HDMITX_SINK_DVI)
++    {
++        if(((videoOutputConfig.format >= TMDL_HDMITX_VFMT_06_720x480i_60Hz) && (videoOutputConfig.format <= TMDL_HDMITX_VFMT_15_1440x480p_60Hz)) 
++        || ((videoOutputConfig.format >= TMDL_HDMITX_VFMT_21_720x576i_50Hz) && (videoOutputConfig.format <= TMDL_HDMITX_VFMT_30_1440x576p_50Hz)) 
++        || ((videoOutputConfig.format >= TMDL_HDMITX_VFMT_35_2880x480p_60Hz)&& (videoOutputConfig.format <= TMDL_HDMITX_VFMT_38_2880x576p_50Hz))
++          )
++        {
++            /* Release the sempahore */
++            RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++            return TMDL_ERR_DLHDMITX_BAD_PARAMETER;
++        }
++    }
++    
++    /* Set color depth according to output config, transmitter termination is disable */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxSetColorDepth(instance, 
++        (tmbslHdmiTxColorDepth)(videoOutputConfig.colorDepth), False) ) != TM_OK, errCode)
++
++    /* Set the TMDS outputs to a forced state */
++    errCode = tmbslHdmiTxTmdsSetOutputs(instance, 
++        HDMITX_TMDSOUT_FORCED0);
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], (errCode != TM_OK) && (errCode != TMBSL_ERR_HDMI_NOT_SUPPORTED), errCode)
++
++    /* Fine-tune the TMDS serializer */
++    errCode = tmbslHdmiTxTmdsSetSerializer(instance, 
++        4, 8);
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], (errCode != TM_OK) && (errCode != TMBSL_ERR_HDMI_NOT_SUPPORTED), errCode)
++
++    /* Set video output configuration */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxVideoOutSetConfig(instance, 
++        (tmbslHdmiTxSinkType_t)sinkType, (tmbslHdmiTxVoutMode_t)videoOutputConfig.mode, HDMITX_VOUT_PREFIL_OFF,
++		HDMITX_VOUT_YUV_BLNK_16, HDMITX_VOUT_QRANGE_FS) ) != TM_OK, errCode)
++
++    /* Set default config */
++    pixRepeat   = HDMITX_PIXREP_DEFAULT;
++    pathBits    = HDMITX_VOUT_DBITS_12;
++    pixelEdge   = HDMITX_PIXEDGE_CLK_POS;
++    syncMethod  = HDMITX_VSMETH_V_H;
++    toggle      = HDMITX_PIXTOGL_ENABLE;
++    
++    /* Set sync details */
++    if (videoInputConfig.syncSource == TMDL_HDMITX_SYNCSRC_EMBEDDED)
++    {
++        /* Embedded sync */
++        syncIn      = EMB;
++        spSync      = HDMITX_PIXSUBPKT_SYNC_HEMB;
++        blankit     = HDMITX_BLNKSRC_VS_HEMB_VEMB;
++        syncMethod  = HDMITX_VSMETH_V_XDE;
++    }
++    else
++    {
++        /* External sync */
++        syncIn  = EXT;
++
++
++        if (gtmdlHdmiTxDriverConfigTable[instance].dataEnableSignalAvailable == 1)
++        {
++        /* DE is available */
++        spSync  = HDMITX_PIXSUBPKT_SYNC_DE;
++        }
++        else
++        {
++        /* DE is NOT available */
++        spSync  = HDMITX_PIXSUBPKT_SYNC_HS;
++        }
++
++
++
++        blankit = HDMITX_BLNKSRC_NOT_DE;
++    }
++
++
++#ifdef TMFL_RGB_DDR_12BITS
++    /* by default, mux is not used */
++    pMux = &gtmdlHdmiTxDriverConfigTable[instance].pNoMux[0];
++#endif
++
++    /* Port swap table */
++    switch(videoInputConfig.mode)
++    {
++        case TMDL_HDMITX_VINMODE_CCIR656:
++            pathBits = HDMITX_VOUT_DBITS_8;
++            pixelEdge = HDMITX_PIXEDGE_CLK_NEG;
++            pSwapTable = gtmdlHdmiTxDriverConfigTable[instance].pSwapTableCCIR656;
++            pMirrorTable = gtmdlHdmiTxDriverConfigTable[instance].pMirrorTableCCIR656;
++#ifdef TMFL_RGB_DDR_12BITS
++            pMux = &gtmdlHdmiTxDriverConfigTable[instance].pMux_RGB_DDR_12bits[0];
++#endif
++            pEnaVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pEnableVideoPortCCIR656;
++            pGndVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pGroundVideoPortCCIR656;
++            break;
++
++        case TMDL_HDMITX_VINMODE_RGB444:
++            pSwapTable = gtmdlHdmiTxDriverConfigTable[instance].pSwapTableRGB444;
++            pMirrorTable = gtmdlHdmiTxDriverConfigTable[instance].pMirrorTableRGB444;
++            pEnaVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pEnableVideoPortRGB444;
++            pGndVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pGroundVideoPortRGB444;
++            break;
++
++        case TMDL_HDMITX_VINMODE_YUV444:
++            pSwapTable = gtmdlHdmiTxDriverConfigTable[instance].pSwapTableYUV444;
++            pMirrorTable = gtmdlHdmiTxDriverConfigTable[instance].pMirrorTableYUV444;
++            pEnaVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pEnableVideoPortYUV444;
++            pGndVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pGroundVideoPortYUV444;
++            break;
++
++        case TMDL_HDMITX_VINMODE_YUV422:
++            pSwapTable = gtmdlHdmiTxDriverConfigTable[instance].pSwapTableYUV422;
++            pMirrorTable = gtmdlHdmiTxDriverConfigTable[instance].pMirrorTableYUV422;
++#ifdef TMFL_RGB_DDR_12BITS
++            pMux = &gtmdlHdmiTxDriverConfigTable[instance].pMux_RGB_DDR_12bits[0];
++#endif
++            pEnaVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pEnableVideoPortYUV422;
++            pGndVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pGroundVideoPortYUV422;
++            break;
++
++#ifdef TMFL_RGB_DDR_12BITS
++        case TMDL_HDMITX_VINMODE_RGB_DDR_12BITS:
++            pSwapTable = gtmdlHdmiTxDriverConfigTable[instance].pSwapTableRGB_DDR_12bits;
++            pMirrorTable = gtmdlHdmiTxDriverConfigTable[instance].pMirrorTableRGB_DDR_12bits;
++            pMux = &gtmdlHdmiTxDriverConfigTable[instance].pMux_RGB_DDR_12bits[0];
++            pEnaVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pEnableVideoPortRGB_DDR_12bits;
++            pGndVideoPortTable = gtmdlHdmiTxDriverConfigTable[instance].pGroundVideoPortRGB_DDR_12bits;
++            break;
++#endif
++         default:
++         break;
++    }
++
++    /* Set the audio and video input port configuration */
++    errCode = tmbslHdmiTxSetVideoPortConfig(instance, pEnaVideoPortTable, pGndVideoPortTable);
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], (errCode != TM_OK) && (errCode != TMBSL_ERR_HDMI_NOT_SUPPORTED), errCode);
++
++#ifdef TMFL_RGB_DDR_12BITS
++    errCode = tmbslHdmiTxVideoInSetMapping(instance, pSwapTable, pMirrorTable, pMux);
++#else
++    errCode = tmbslHdmiTxVideoInSetMapping(instance, pSwapTable, pMirrorTable);
++#endif
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], (errCode != TM_OK) && (errCode != TMBSL_ERR_HDMI_NOT_SUPPORTED), errCode);
++    
++    /* Set fine image position */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++              (errCode = tmbslHdmiTxVideoInSetFine(instance, spSync, HDMITX_PIXTOGL_NO_ACTION) ) != TM_OK, errCode);
++
++    /* Set input blanking */
++    errCode = tmbslHdmiTxVideoInSetBlanking(instance, blankit, HDMITX_BLNKCODE_ALL_0);
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], (errCode != TM_OK) && (errCode != TMBSL_ERR_HDMI_NOT_SUPPORTED), errCode);
++
++    /* Configure video input options and control the upsampler */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++              (errCode = tmbslHdmiTxVideoInSetConfig(instance, 
++                                                     (tmbslHdmiTxVinMode_t)videoInputConfig.mode, (tmbslHdmiTxVidFmt_t)videoOutputConfig.format, 
++                                                     (tmbslHdmiTx3DStructure_t)videoInputConfig.structure3D, pixelEdge, 
++                                                     (tmbslHdmiTxPixRate_t)videoInputConfig.pixelRate, HDMITX_UPSAMPLE_AUTO) ) != TM_OK, errCode);
++
++
++    /* Set input ouput - may give NOT_SUPPORTED error */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++              (errCode = tmbslHdmiTxVideoSetInOut(instance, (tmbslHdmiTxVidFmt_t)videoInputConfig.format, 
++                                                  (tmbslHdmiTx3DStructure_t)videoInputConfig.structure3D, 
++                                                  HDMITX_SCAMODE_AUTO, (tmbslHdmiTxVidFmt_t)videoOutputConfig.format,
++                                                  pixRepeat, HDMITX_MATMODE_AUTO, pathBits, (tmbslHdmiTxVQR_t) videoOutputConfig.dviVqr) ) != TM_OK, errCode);
++
++
++    /* Only set audio for HDMI, not DVI */
++    if (sinkType == TMDL_HDMITX_SINK_HDMI)
++    {
++        /* Release the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++        /* Set audio parameters */
++        RETIF( (errCode = tmdlHdmiTxSetAudioInput(instance, audioInputConfig, sinkType) ) != TM_OK, errCode)
++        /* Take the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++    }
++
++    /* Output fine adjustment */
++    pixRateSingleDouble = (tmbslHdmiTxPixRate_t)videoInputConfig.pixelRate;
++    if (videoInputConfig.pixelRate == HDMITX_PIXRATE_SINGLE_REPEATED)
++    {
++	    pixRateSingleDouble = HDMITX_PIXRATE_SINGLE;
++    }
++    
++
++    if ((videoInputConfig.structure3D != HDMITX_3D_FRAME_PACKING) && 
++        dlHdmiTxGetReflineRefpix(videoInputConfig.format, videoInputConfig.mode, videoOutputConfig.format, 
++                                    syncIn, (tmdlHdmiTxPixRate_t)pixRateSingleDouble, &uRefPix, &uRefLine, 
++									&uScRefPix, &uScRefLine, &bVerified) > 0)
++    {
++        /* From 720p50/60 or 1080i50/60 up-scaling to 1080p50/60, when external sync,
++           toggleV, toggleH and toggleX need to be set to 0 */
++        if (syncIn == EXT)
++        {
++            switch (videoInputConfig.format)
++            {
++                case TMDL_HDMITX_VFMT_04_1280x720p_60Hz:
++                case TMDL_HDMITX_VFMT_19_1280x720p_50Hz:
++                case TMDL_HDMITX_VFMT_05_1920x1080i_60Hz:
++                case TMDL_HDMITX_VFMT_20_1920x1080i_50Hz:
++                    if ( (videoOutputConfig.format == TMDL_HDMITX_VFMT_16_1920x1080p_60Hz) 
++                        || (videoOutputConfig.format == TMDL_HDMITX_VFMT_31_1920x1080p_50Hz) )
++                    {
++                        toggle = HDMITX_PIXTOGL_NO_ACTION;
++                    }
++                    break;
++                default:
++                    toggle = HDMITX_PIXTOGL_ENABLE;
++                    break;
++            }
++        }
++
++        /* Combination found in table for scaler: configure input manually */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxVideoInSetSyncManual(instance, 
++            (tmbslHdmiTxSyncSource_t)videoInputConfig.syncSource, syncMethod, toggle, toggle, toggle, uRefPix, uRefLine) ) != TM_OK, errCode)
++    }
++    else
++    {
++        /* Not found so assume non-scaler and auto-configure input */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxVideoInSetSyncAuto(instance, 
++            (tmbslHdmiTxSyncSource_t)videoInputConfig.syncSource, (tmbslHdmiTxVidFmt_t)videoInputConfig.format,
++			(tmbslHdmiTxVinMode_t)videoInputConfig.mode, (tmbslHdmiTx3DStructure_t)videoInputConfig.structure3D)) != TM_OK, errCode)
++    }
++
++    /* Only set infoframes for HDMI, not DVI */
++    if (sinkType == TMDL_HDMITX_SINK_HDMI)
++    {
++	    /* Set avi infoframe */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = dlHdmiTxSetVideoInfoframe(instance, videoOutputConfig.format, videoOutputConfig.mode) ) != TM_OK, 
++            errCode)
++    }
++
++    errCode = tmbslHdmiTxScalerGetMode(instance, 
++                &scalerMode);
++
++    /* Ignore scaler TMBSL_ERR_HDMI_NOT_SUPPORTED error */
++    if ((errCode == TM_OK) && (scalerMode == HDMITX_SCAMODE_ON))
++    {
++        /* Enable scaler mode */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxScalerInDisable(instance, 
++            False) ) != TM_OK, errCode) 
++
++        /* Correction to interlace */
++        topSel = HDMITX_TOPSEL_INTERNAL;
++        if ((videoOutputConfig.format == TMDL_HDMITX_VFMT_05_1920x1080i_60Hz)
++                || (videoOutputConfig.format == TMDL_HDMITX_VFMT_20_1920x1080i_50Hz))
++        {
++            /* video input format is range-checked by tmbslHdmiTxVideoSetInOut above */
++            vinFmtIndex = dlHdmiTxCalcVidFmtIndex(videoInputConfig.format);
++            if ((kVfmtToShortFmt_TV[vinFmtIndex] == TV_480p_60Hz)
++            ||  (kVfmtToShortFmt_TV[vinFmtIndex] == TV_576p_50Hz))
++            {
++                /* Correct for 1080i output for p->i conversion only */
++                topSel = HDMITX_TOPSEL_VRF;
++            }
++        }
++
++        /* Set scaler field positions */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxScalerSetFieldOrder(instance, 
++            HDMITX_INTEXT_NO_CHANGE, HDMITX_INTEXT_NO_CHANGE, topSel, HDMITX_TOPTGL_NO_CHANGE) ) != TM_OK, errCode) 
++
++        /* Scaler fine adjustment */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxScalerSetFine(instance, 
++            uScRefPix, uScRefLine) ) != TM_OK, errCode) 
++
++        if ((videoOutputConfig.format == TMDL_HDMITX_VFMT_16_1920x1080p_60Hz) 
++            || (videoOutputConfig.format == TMDL_HDMITX_VFMT_31_1920x1080p_50Hz))
++        {
++            phasesH = HDMITX_H_PHASES_16;
++        }
++        else
++        {
++            phasesH = HDMITX_H_PHASES_15;
++        }
++
++        /* Set scaler phase */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxScalerSetPhase(instance, 
++            phasesH) ) != TM_OK, errCode) 
++
++        /* Set scaler latency */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxScalerSetLatency(instance, 
++            0x22) ) != TM_OK, errCode) 
++
++        /* Set scaler synchronisation option */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxScalerSetSync(instance, 
++            syncMethod, HDMITX_VSONCE_EACH_FRAME) ) != TM_OK, errCode) 
++
++        /* With scaler, use Only Once setting for tmbslHdmiTxVideoOutSetSync */
++        once = HDMITX_VSONCE_ONCE;
++    }
++    else
++    {
++        once = HDMITX_VSONCE_EACH_FRAME;
++    }
++
++    /* Set video synchronisation */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxVideoOutSetSync(instance, 
++        HDMITX_VSSRC_INTERNAL, HDMITX_VSSRC_INTERNAL, HDMITX_VSSRC_INTERNAL, 
++        HDMITX_VSTGL_TABLE, once) ) != TM_OK, errCode) 
++	
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    instanceStatusInfoTx[instance].pColBarState->inOutFirstSetDone = True;
++    
++    /* Test if pattern is already on */
++    if (instanceStatusInfoTx[instance].pColBarState->colorBarOn == True)
++    {
++        /* If pattern is On, apply new settings */
++        instanceStatusInfoTx[instance].pColBarState->changeColorBarNow = True;
++    }
++
++    return TM_OK;
++}
++
++/*****************************************************************************/
++/**
++    \brief Configures audio input parameters : format, rate, etc.
++           This function is similar to tmdlHdmiTxSetInputOutput except that
++           video is not reconfigured.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance          Instance identifier.
++    \param audioInputConfig  Configuration of the input audio.
++    \param sinkType          Type of sink connected to the output of the Tx.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetAudioInput
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxAudioInConfig_t   audioInputConfig,
++    tmdlHdmiTxSinkType_t        sinkType
++)
++{
++    tmErrorCode_t           errCode;
++    tmdlHdmiTxVidFmtSpecs_t resolutionSpecs;            /* Used to convert video format to video frequency */
++    UInt8                   layout;                     /* 0 or 1 */
++    UInt8                   aifChannelCountCode = 0;    /* audio info frame channels */
++    tmbslHdmiTxVfreq_t      vOutFreq;                   /* Vertical output frequency */
++    tmbslHdmiTxctsRef_t     ctsRef;                     /* CTS ref source */
++    UInt16                  uCtsX;                      /* CtsX value */
++    tmbslHdmiTxPktAif_t     pktAif;                     /* Audio infoframe packet */
++    Bool                    OBASupported;               /* OBA supported or not */
++    Bool                    DSTSupported;               /* DST supported or not */
++    Bool                    HBRSupported;               /* HBR supporeted or not */
++    UInt8                   *pEnaAudioPortCfg;
++    UInt8                   *pGndAudioPortCfg;
++    UInt8                   *pEnaAudioClockPortCfg;
++    UInt8                   *pGndAudioClockPortCfg;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the semaphore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Audio OBA support */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxHwGetCapabilities(instance, 
++        HDMITX_FEATURE_HW_AUDIO_OBA, &OBASupported) ) != TM_OK, errCode)
++
++    /* Audio DST support */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxHwGetCapabilities(instance, 
++        HDMITX_FEATURE_HW_AUDIO_DST, &DSTSupported) ) != TM_OK, errCode)
++
++    /* Audio HBR support */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxHwGetCapabilities(instance, 
++        HDMITX_FEATURE_HW_AUDIO_HBR, &HBRSupported) ) != TM_OK, errCode)
++
++    /* Test if audio input format is supported */
++    if ( ((audioInputConfig.format == TMDL_HDMITX_AFMT_OBA) && (OBASupported == False)) ||
++	         ((audioInputConfig.format == TMDL_HDMITX_AFMT_DST) && (DSTSupported == False)) ||
++             ((audioInputConfig.format == TMDL_HDMITX_AFMT_HBR) && (HBRSupported == False)) )
++    {
++        /* Release the semaphore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++        return TMDL_ERR_DLHDMITX_NOT_SUPPORTED;
++    }
++    
++    if (sinkType == TMDL_HDMITX_SINK_EDID)
++    {
++        /* Change sink type with the currently defined in EDID */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxEdidGetSinkType(instance, 
++            (tmbslHdmiTxSinkType_t *)&sinkType) ) != TM_OK, errCode)
++    }
++
++    if (sinkType == TMDL_HDMITX_SINK_HDMI)
++    {
++		/* Set audio layout */
++		layout = 1;
++		if (audioInputConfig.channelAllocation == 0x00) {
++		  layout = 0;
++	}
++	aifChannelCountCode = kChanAllocChanNum[audioInputConfig.channelAllocation] - 1;
++
++        /* Port audio configuration */
++        switch(audioInputConfig.format)
++        {
++            case TMDL_HDMITX_AFMT_SPDIF:
++                pEnaAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioPortSPDIF;
++                pGndAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioPortSPDIF;
++                pEnaAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioClockPortSPDIF;
++                pGndAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioClockPortSPDIF;
++                break;
++
++            case TMDL_HDMITX_AFMT_I2S:
++                pEnaAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioClockPortI2S;
++                pGndAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioClockPortI2S;
++
++                if(audioInputConfig.channelAllocation >= 1 ) /* For Multi channels */
++                {
++                    pEnaAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioPortI2S8C;
++                    pGndAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioPortI2S8C;
++                }
++                else
++                {
++                    pEnaAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioPortI2S;
++                    pGndAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioPortI2S;
++                }
++                break;
++
++            case TMDL_HDMITX_AFMT_OBA:
++                pEnaAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioPortOBA;
++                pGndAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioPortOBA;
++                pEnaAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioClockPortOBA;
++                pGndAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioClockPortOBA;
++                break;
++
++            case TMDL_HDMITX_AFMT_DST:
++                pEnaAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioPortDST;
++                pGndAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioPortDST;
++                pEnaAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioClockPortDST;
++                pGndAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioClockPortDST;
++                break;
++
++            case TMDL_HDMITX_AFMT_HBR:
++                pEnaAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioPortHBR;
++                pGndAudioPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioPortHBR;
++                pEnaAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pEnableAudioClockPortHBR;
++                pGndAudioClockPortCfg = gtmdlHdmiTxDriverConfigTable[instance].pGroundAudioClockPortHBR;
++                break;
++
++            default:
++                /* Release the sempahore */
++                RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++                return TMDL_ERR_DLHDMITX_BAD_PARAMETER;
++        }
++
++        errCode = tmbslHdmiTxSetAudioPortConfig(instance,
++            pEnaAudioPortCfg, pGndAudioPortCfg);
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], (errCode != TM_OK) && (errCode != TMBSL_ERR_HDMI_NOT_SUPPORTED), errCode)
++
++        errCode = tmbslHdmiTxSetAudioClockPortConfig(instance,
++            pEnaAudioClockPortCfg, pGndAudioClockPortCfg);
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], (errCode != TM_OK) && (errCode != TMBSL_ERR_HDMI_NOT_SUPPORTED), errCode)
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxAudioInSetConfig(instance, 
++		    (tmbslHdmiTxaFmt_t)audioInputConfig.format, (tmbslHdmiTxI2sFor_t)audioInputConfig.i2sFormat, 
++			audioInputConfig.channelAllocation, HDMITX_CHAN_NO_CHANGE, HDMITX_CLKPOLDSD_NO_CHANGE, HDMITX_SWAPDSD_NO_CHANGE,
++			layout, HDMITX_LATENCY_CURRENT, (tmbslHdmiTxDstRate_t)audioInputConfig.dstRate) ) != TM_OK, errCode) 
++
++        /* Find output vertical frequency from output format */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmdlHdmiTxGetVideoFormatSpecs(instance, instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format,
++            &resolutionSpecs) ) != TM_OK, errCode)
++            vOutFreq = (tmbslHdmiTxVfreq_t)resolutionSpecs.vfrequency;
++
++        if ((audioInputConfig.format == TMDL_HDMITX_AFMT_SPDIF)  
++                || (audioInputConfig.format == TMDL_HDMITX_AFMT_OBA))
++        {
++            ctsRef = HDMITX_CTSREF_FS64SPDIF;
++            uCtsX = HDMITX_CTSX_64;
++        }
++        else /* I2S */
++        {
++            ctsRef = HDMITX_CTSREF_ACLK;
++            if (audioInputConfig.i2sQualifier == TMDL_HDMITX_I2SQ_32BITS)
++            {
++                uCtsX = HDMITX_CTSX_64;
++            }
++            else
++            {
++                uCtsX = HDMITX_CTSX_32;
++            }
++        }
++
++        /* Set the Clock Time Stamp generator in HDMI mode only */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxAudioInSetCts(instance, 
++            ctsRef, (tmbslHdmiTxafs_t)audioInputConfig.rate, (tmbslHdmiTxVidFmt_t)instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format, 
++			vOutFreq, HDMITX_CTS_AUTO, uCtsX, HDMITX_CTSK_USE_CTSX, HDMITX_CTSMTS_USE_CTSX,
++			(tmbslHdmiTxDstRate_t)audioInputConfig.dstRate) ) != TM_OK, errCode)
++
++        /* Set Channel Status registers
++            No need to call tmbslTDA9984AudioOutSetChanStatusMapping, since default Byte 2
++            values of "Do not take into account" are adequate */
++
++
++        if (audioInputConfig.format != TMDL_HDMITX_AFMT_SPDIF) /* channel status automatically copied from SPDIF*/
++        {
++
++        if (audioInputConfig.format != TMDL_HDMITX_AFMT_HBR) {
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxAudioOutSetChanStatus(instance,
++                                                        (tmbslHdmiTxAudioData_t)audioInputConfig.channelStatus.PcmIdentification,
++                                                        (tmbslHdmiTxCSformatInfo_t)audioInputConfig.channelStatus.FormatInfo,
++                                                        (tmbslHdmiTxCScopyright_t)audioInputConfig.channelStatus.CopyrightInfo,
++                                                        audioInputConfig.channelStatus.categoryCode,
++                                                        (tmbslHdmiTxafs_t)audioInputConfig.rate,
++                                                        (tmbslHdmiTxCSclkAcc_t)audioInputConfig.channelStatus.clockAccuracy,
++                                                        (tmbslHdmiTxCSmaxWordLength_t)audioInputConfig.channelStatus.maxWordLength,
++                                                        (tmbslHdmiTxCSwordLength_t)audioInputConfig.channelStatus.wordLength,
++                                                        (tmbslHdmiTxCSorigAfs_t)audioInputConfig.channelStatus.origSampleFreq))!= TM_OK, errCode)
++            }
++        else {
++
++
++         RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxAudioOutSetChanStatus(instance,
++                                                        (tmbslHdmiTxAudioData_t)audioInputConfig.channelStatus.PcmIdentification,
++                                                        (tmbslHdmiTxCSformatInfo_t)audioInputConfig.channelStatus.FormatInfo,
++                                                        (tmbslHdmiTxCScopyright_t)audioInputConfig.channelStatus.CopyrightInfo,
++                                                        audioInputConfig.channelStatus.categoryCode,
++                                                        HDMITX_AFS_768K,
++                                                        (tmbslHdmiTxCSclkAcc_t)audioInputConfig.channelStatus.clockAccuracy,
++                                                        (tmbslHdmiTxCSmaxWordLength_t)audioInputConfig.channelStatus.maxWordLength,
++                                                        (tmbslHdmiTxCSwordLength_t)audioInputConfig.channelStatus.wordLength,
++                                                        (tmbslHdmiTxCSorigAfs_t)audioInputConfig.channelStatus.origSampleFreq))!= TM_OK, errCode)
++
++
++            }
++
++        }
++
++ 
++        /* Set reset_fifo to 1 */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxAudioOutSetMute(instance, 
++            HDMITX_AMUTE_ON) ) != TM_OK, errCode)
++
++        /* UN Mute audio only if previously not muted */
++        if (instanceStatusInfoTx[instance].pAudioInfo->audioMuteState == False) {
++
++               /* Wait for 20 ms */
++               RETIF_SEM(dlHdmiTxItSemaphore[instance],(errCode = tmdlHdmiTxIWWait(20) ) != TM_OK, errCode)
++               /* Set reset_fifo to 0 */
++               RETIF_SEM(dlHdmiTxItSemaphore[instance],
++                         (errCode = tmbslHdmiTxAudioOutSetMute(instance, 
++                         HDMITX_AMUTE_OFF) ) != TM_OK, errCode)
++
++         }
++
++
++        /* Set audio infoframe */
++        pktAif.ChannelCount     = aifChannelCountCode;
++        pktAif.CodingType       = 0; /* refer to stream header */
++        pktAif.SampleSize       = 0; /* refer to stream header */
++        pktAif.ChannelAlloc     = audioInputConfig.channelAllocation;
++        pktAif.LevelShift       = 0; /* 0dB level shift */
++        pktAif.DownMixInhibit   = 0; /* down-mix stereo permitted */
++        pktAif.SampleFreq       = AIF_SF_REFER_TO_STREAM_HEADER; /* refer to stream header */
++
++        /* SampleFreq parameter need to be set for OBA and DST audio stream */
++        if ( (audioInputConfig.format == TMDL_HDMITX_AFMT_OBA) ||
++                (audioInputConfig.format == TMDL_HDMITX_AFMT_DST) )
++        {
++            switch (audioInputConfig.rate)
++            {
++                case TMDL_HDMITX_AFS_32K:
++                    pktAif.SampleFreq = AIF_SF_32K; /* see table 18 of CEA-861 */
++                    break;
++                case TMDL_HDMITX_AFS_44K:
++                    pktAif.SampleFreq = AIF_SF_44K; 
++                    break;
++                case TMDL_HDMITX_AFS_48K:
++                    pktAif.SampleFreq = AIF_SF_48K; 
++                    break;
++                case TMDL_HDMITX_AFS_88K:
++                    pktAif.SampleFreq = AIF_SF_88K; 
++                    break;
++                case TMDL_HDMITX_AFS_96K:
++                    pktAif.SampleFreq = AIF_SF_96K; 
++                    break;
++                case TMDL_HDMITX_AFS_176K:
++                    pktAif.SampleFreq = AIF_SF_176K; 
++                    break;
++                case TMDL_HDMITX_AFS_192K:
++                    pktAif.SampleFreq = AIF_SF_192K; 
++                    break;
++                default:
++                    pktAif.SampleFreq = AIF_SF_REFER_TO_STREAM_HEADER; /* refer to stream header */
++                    break;
++            }
++        }
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxPktSetAudioInfoframe(instance, 
++            &pktAif, True) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Defines the content of AVI infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pAviIfData   Pointer to the structure containing AVI infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetVideoInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxAviIfData_t   *pAviIfData
++)
++{
++    tmErrorCode_t       errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    if (enable == True)
++    {
++        /* Check if AviIfData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pAviIfData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++        errCode = dlHdmiTxSetRawVideoInfoframe(instance, pAviIfData, enable);
++    }
++    else
++    {
++        errCode = dlHdmiTxSetRawVideoInfoframe(instance, Null, enable);
++    }
++
++    /* Ignore infoframe interlock in DVI mode */
++    if (errCode == TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++    {
++        errCode = TM_OK;
++    }
++
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], errCode != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Defines the content of AUD infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pAudIfData   Pointer to the structure containing AUD infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetAudioInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxAudIfData_t   *pAudIfData
++)
++{
++    tmErrorCode_t       errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    if (enable == True)
++    {
++        /* Check if AudIfData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pAudIfData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetAudioInfoframe(instance,
++            (tmbslHdmiTxPktAif_t *)pAudIfData, enable) ) != TM_OK, errCode)
++    }
++    else
++    {
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetAudioInfoframe(instance,
++            Null, enable) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Defines the content of the audio content protection packet to be
++           sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pAcpPktData  Pointer to the structure containing ACP infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetACPPacket
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxAcpPktData_t  *pAcpPktData
++)
++{
++    tmErrorCode_t       errCode;
++    tmbslHdmiTxPkt_t    pkt;
++    UInt8               i;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    if (enable == True)
++    {
++        /* Check if AcpPktData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pAcpPktData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++        switch (pAcpPktData->acpType)
++        {
++            /* Make sure bytes reserved are 0 */
++            case 0 : /* Generic audio */
++                for (i=0; i<28; i++) { pkt.dataByte[i] = 0; }
++                break;
++
++            case 1 : /* IEC 60958 identified audio */
++                for (i=0; i<28; i++) { pkt.dataByte[i] = 0; }
++                break;
++
++            case 2 : /* DVD Audio */
++                for (i=0; i<2; i++) { pkt.dataByte[i] = pAcpPktData->acpData[i]; }
++                for (i=2; i<28; i++) { pkt.dataByte[i] = 0; }
++                break;
++
++            case 3 : /* SuperAudio CD */
++                for (i=0; i<17; i++) { pkt.dataByte[i] = pAcpPktData->acpData[i]; }
++                for (i=17; i<28; i++) { pkt.dataByte[i] = 0; }
++                break;
++
++            default :
++                /* Release the sempahore */
++                RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++                return TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS;
++        }
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetAcp(instance,
++            &pkt, 28, pAcpPktData->acpType, enable) ) != TM_OK, errCode)
++    }
++    else
++    {
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetAcp(instance,
++            Null, 0, 0, enable) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Defines the content of the General Control packet to be sent by Tx
++           device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pGcpPktData  Pointer to the structure containing GCP packet parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetGeneralControlPacket
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxGcpPktData_t  *pGcpPktData
++)
++{
++    tmErrorCode_t       errCode;
++    tmbslHdmiTxaMute_t  aMute;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++    
++    if (enable == True)
++    {
++        /* Check if GcpPktData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pGcpPktData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++        if(pGcpPktData->avMute == False)
++        {
++            aMute = HDMITX_AMUTE_OFF;
++        }
++        else
++        {
++            aMute = HDMITX_AMUTE_ON;
++        }
++
++        /* Set contents of general control packet & enable/disable packet insertion */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetGeneralCntrl(instance,
++            &aMute, enable) ) != TM_OK, errCode)
++    }
++    else
++    {
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetGeneralCntrl(instance,
++            Null, enable) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Defines the content of ISRC1 packet to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param enable           Enable/disable infoframe insertion.
++    \param pIsrc1PktData    Pointer to the structure containing GCP packet parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetISRC1Packet
++(
++    tmInstance_t                instance,
++    Bool                        enable,
++    tmdlHdmiTxIsrc1PktData_t    *pIsrc1PktData
++)
++{
++    tmErrorCode_t       errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++    
++    if (enable == True)
++    {
++        /* Check if Isrc1PktData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pIsrc1PktData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetIsrc1(instance,
++            (tmbslHdmiTxPkt_t *)pIsrc1PktData->UPC_EAN_ISRC, 16, pIsrc1PktData->isrcCont, 
++            pIsrc1PktData->isrcValid, pIsrc1PktData->isrcStatus, enable) ) != TM_OK, errCode)
++    }
++    else
++    {
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetIsrc1(instance,
++            Null, 0, 0, 0, 0, enable) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Defines the content of ISRC2 packet to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param enable           Enable/disable infoframe insertion.
++    \param pIsrc2PktData    Pointer to the structure containing GCP packet parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetISRC2Packet
++(
++    tmInstance_t                instance,
++    Bool                        enable,
++    tmdlHdmiTxIsrc2PktData_t    *pIsrc2PktData
++)
++{
++    tmErrorCode_t       errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    if (enable == True)
++    {
++        /* Check if Isrc1PktData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pIsrc2PktData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetIsrc2(instance,
++            (tmbslHdmiTxPkt_t *)pIsrc2PktData->UPC_EAN_ISRC, 16, enable) ) != TM_OK, errCode)
++    }
++    else
++    {
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetIsrc2(instance,
++            Null, 0, enable) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Defines the content of MPS infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pMpsIfData   Pointer to the structure containing MPS infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetMPSInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxMpsIfData_t   *pMpsIfData
++)
++{
++    tmErrorCode_t           errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    if (enable == True)
++    {
++        /* Check if MpsIfData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pMpsIfData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetMpegInfoframe(instance,
++            (tmbslHdmiTxPktMpeg_t *)pMpsIfData, enable) ) != TM_OK, errCode)
++    }
++    else
++    {
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetMpegInfoframe(instance,
++            Null, enable) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Defines the content of SPD infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pSpdIfData   Pointer to the structure containing SPD infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetSpdInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxSpdIfData_t   *pSpdIfData
++)
++{
++    tmErrorCode_t       errCode;
++    
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    if (enable == True)
++    {
++        /* Check if SpdIfData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pSpdIfData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxPktSetSpdInfoframe(instance,
++            (tmbslHdmiTxPktSpd_t *)pSpdIfData, enable) ) != TM_OK, errCode)
++    }
++    else
++    {
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxPktSetSpdInfoframe(instance,
++            Null, enable) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Defines the content of VS infoframe to be sent by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable infoframe insertion.
++    \param pVsIfData    Pointer to the structure containing VS infoframe
++                        parameters.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetVsInfoframe
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxVsPktData_t   *pVsIfData
++)
++{
++    tmErrorCode_t       errCode;
++    
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    if (enable == True)
++    {
++        /* Check if VsIfData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pVsIfData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxPktSetVsInfoframe(instance,
++            (tmbslHdmiTxPkt_t *)pVsIfData->vsData, HDMITX_PKT_DATA_BYTE_CNT-1, pVsIfData->version, enable) ) != TM_OK, errCode)
++    }
++    else
++    {
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxPktSetVsInfoframe(instance,
++            Null, 0, pVsIfData->version, enable) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Enables/disables NULL packet sending (only used for debug purpose).
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance  Instance identifier.
++    \param enable    Enable/disable packet insertion.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxDebugSetNullPacket
++(
++    tmInstance_t    instance,
++    Bool            enable
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxPktSetNullInsert(instance,
++        enable) ) != TM_OK, errCode)
++
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Send one single NULL packet (only used for debug purpose).
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance  Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxDebugSetSingleNullPacket
++(
++    tmInstance_t    instance
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxPktSetNullSingle(instance) )
++        != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Set the audio output mute status. This function can be used to mute
++           audio output, without muting video. This can be typically used when
++           reconfiguring the audio HW after a sample rate change.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance   Instance identifier.
++    \param muteStatus Mute status (True/False).
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetAudioMute
++(
++    tmInstance_t    instance,
++    Bool            audioMute
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Mute or Un-mute the audio output */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxAudioOutSetMute(instance, 
++        (tmbslHdmiTxaMute_t)audioMute) ) != TM_OK, errCode)
++
++    /* Store current audio mute status */
++    instanceStatusInfoTx[instance].pAudioInfo->audioMuteState = audioMute;
++
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Reset audio CTS.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance   Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxResetAudioCts
++(
++    tmInstance_t    instance
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Reset the audio Clock Time Stamp generator */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxAudioInResetCts(instance)
++        ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Retrieve EDID Status from driver.
++           This function is synchronous.
++           This function is ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pEdidStatus      Pointer to the array that will receive the EDID Status.
++    \param pEdidBlkCount    Pointer to the integer that will receive the number of 
++                            read EDID block.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidStatus
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxEdidStatus_t  *pEdidStatus,
++    UInt8                   *pEdidBlkCount
++)
++{
++    tmErrorCode_t   errCode;
++    UInt8           edidStatus;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if EdidStatus and pReadBytesNumber pointers are Null */
++    RETIF(pEdidStatus == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pEdidBlkCount == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Get the EDID status from BSL driver */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetStatus(instance, 
++        (UInt8 *)&edidStatus) ) != TM_OK, errCode)
++
++    if (edidStatus >= TMDL_HDMITX_EDID_STATUS_INVALID)
++    {
++        *pEdidStatus = TMDL_HDMITX_EDID_STATUS_INVALID;
++    }
++    else
++    {
++        *pEdidStatus = (tmdlHdmiTxEdidStatus_t)edidStatus;
++    }
++
++    if ((*pEdidStatus == TMDL_HDMITX_EDID_READ) ||
++        (*pEdidStatus == TMDL_HDMITX_EDID_ERROR_CHK))
++    {
++        /* Get the read EDID block number from BSL driver */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxEdidGetBlockCount(instance, 
++            pEdidBlkCount) ) != TM_OK, errCode)
++    }
++    
++    if (errCode != TM_OK)
++    {
++        /* Error during read EDID, number of read block is 0 */
++        *pEdidBlkCount = 0;
++    
++        /* Release the sempahore */
++        (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++
++        return errCode;
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Retrieves audio descriptors from receiver's EDID. This function
++           parses the EDID of Tx device to get the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++
++    \param instance             Instance identifier.
++    \param pAudioDescs          Pointer to the array that will receive audio
++                                descriptors.
++    \param maxAudioDescs        Size of the array.
++    \param pWrittenAudioDescs   Pointer to the integer that will receive the actual
++                                number of written descriptors.
++    \param pAudioFlags          Pointer to the byte to receive Audio Capabilities Flags.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidAudioCaps
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxEdidAudioDesc_t   *pAudioDescs,
++    UInt                        maxAudioDescs,
++    UInt                        *pWrittenAudioDescs,
++    UInt8                       *pAudioFlags
++)
++{
++    tmErrorCode_t           errCode;
++    tmbslHdmiTxEdidSad_t    edidSad[HDMI_TX_SAD_MAX_CNT];
++    UInt                    i;
++    
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if AudioDescs, WrittenAudioDescs and AudioFlags pointers are Null */
++    RETIF(pAudioDescs == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pWrittenAudioDescs == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pAudioFlags == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Get video capabilities from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetAudioCapabilities(instance, 
++        edidSad, maxAudioDescs, pWrittenAudioDescs, pAudioFlags) ) != TM_OK, errCode)
++
++    for (i=0; i<*pWrittenAudioDescs; i++)
++    {
++        pAudioDescs[i].format            = (edidSad[i].ModeChans & 0x78) >> 3; /* Bits[6:3]: EIA/CEA861 mode */
++        pAudioDescs[i].channels          = edidSad[i].ModeChans & 0x07;        /* Bits[2:0]: channels */
++        pAudioDescs[i].supportedFreqs    = edidSad[i].Freqs;                   /* Supported frequencies */
++
++        if (pAudioDescs[i].format == 1)             /* LPCM format */
++        {
++            pAudioDescs[i].supportedRes = edidSad[i].Byte3 & 0x07;
++            pAudioDescs[i].maxBitrate   = 0x00;
++        }
++        else if ( (pAudioDescs[i].format >= 2) &&   /* Compressed format */
++                    (pAudioDescs[i].format <= 8) )
++        {
++            pAudioDescs[i].supportedRes = 0x00;
++            pAudioDescs[i].maxBitrate   = edidSad[i].Byte3;
++        }
++        else
++        {
++            pAudioDescs[i].supportedRes = 0x00;
++            pAudioDescs[i].maxBitrate   = 0x00;
++        }
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Retrieves supported video formats (short descriptors) from
++           receiver's EDID. This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance             Instance identifier.
++    \param pVideoDesc           Pointer to the structure that will receive short
++                                video descriptors.
++    \param maxVideoFormats      Size of the array.
++    \param pWrittenVideoFormats Pointer to the integer that will receive the actual
++                                number of written descriptors.
++    \param pVideoFlags          Pointer to the byte to receive Video Capability Flags.
++                                b7: underscan supported
++                                b6: YCbCr 4:4:4 supported
++                                b5: YCbCr 4:2:2 supported
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidVideoCaps
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxShortVidDesc_t    *pVideoDesc,
++    UInt                        maxVideoFormats,
++    UInt                        *pWrittenVideoFormats,
++    UInt8                       *pVideoFlags
++)
++{
++    tmErrorCode_t                   errCode;
++    UInt8                           edidVFmtsBuffer[HDMI_TX_SVD_MAX_CNT];
++    tmdlHdmiTxEdidVideoTimings_t    edidDTDBuffer[NUMBER_DTD_STORED];
++    UInt8                           i;
++    UInt8                           writtenDTD = 0;
++    UInt8                           dtdCounter = 0;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if Videoformats, WrittenVideoFormats and VideoFlags pointers are Null */
++    RETIF(pVideoDesc == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pWrittenVideoFormats == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pVideoFlags == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(maxVideoFormats == 0, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Get video capabilities from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetVideoCapabilities(instance, 
++        edidVFmtsBuffer, HDMI_TX_SVD_MAX_CNT, pWrittenVideoFormats, pVideoFlags) ) != TM_OK, errCode)
++
++    /* Get detailled descriptors from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = dlHdmiTxEdidGetDTD(instance, edidDTDBuffer, NUMBER_DTD_STORED, &writtenDTD) ) != TM_OK, errCode)
++
++    dtdCounter = 0;
++    if (writtenDTD > 0)
++    {
++        /* Release the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++        /* Write first DTD in first position of table video desc  */
++        pVideoDesc[0].videoFormat = tmdlHdmiTxConvertDTDtoCEA(instance, &(edidDTDBuffer[dtdCounter]));
++
++        /* Take the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++        dtdCounter++;
++
++        pVideoDesc[0].nativeVideoFormat = False;
++    }
++
++    /* Start with i = 1 keep the first position for the first DTD */
++    for (i = dtdCounter; i< maxVideoFormats ; i++)
++    {
++        if ((i < (HDMI_TX_SVD_MAX_CNT + dtdCounter)) && (i < ((*pWrittenVideoFormats) + dtdCounter)))
++        {
++            /* Store SVD */
++            pVideoDesc[i].videoFormat = (tmdlHdmiTxVidFmt_t)((Int)edidVFmtsBuffer[i - dtdCounter] & 0x7F); 
++            /* if bit 7 is true, it means that is a preferred video format */
++            if ((edidVFmtsBuffer[i - dtdCounter] & 0x80) == 0x80)
++            {
++                pVideoDesc[i].nativeVideoFormat = True;
++            }
++            else
++            {
++                pVideoDesc[i].nativeVideoFormat = False;
++            }
++        }
++        else
++        {
++            if ((dtdCounter < NUMBER_DTD_STORED) && (dtdCounter < writtenDTD))
++            {
++                /* Release the sempahore */
++                RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++                /* Store DTD except first DTD */
++                pVideoDesc[i].videoFormat = tmdlHdmiTxConvertDTDtoCEA(instance, &(edidDTDBuffer[dtdCounter]));
++                /* Take the sempahore */
++                RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++                dtdCounter++;
++
++                pVideoDesc[i].nativeVideoFormat = False;
++            }
++            else
++            {
++                /* VGA is always supported */
++                pVideoDesc[i].videoFormat = TMDL_HDMITX_VFMT_01_640x480p_60Hz;
++                pVideoDesc[i].nativeVideoFormat = False;
++                /* Last format supported exit from loop for */
++                break;
++            }
++        }
++    }
++
++    *pWrittenVideoFormats = *pWrittenVideoFormats + dtdCounter + 1;     /* + 1 for VGA format */
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Retrieves supported video formats (short descriptors) from
++           receiver's EDID. This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance                 Instance identifier.
++    \param pNativeVideoFormat    Pointer to the array that will receive video
++                                    timing descriptor.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidVideoPreferred
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxEdidVideoTimings_t    *pNativeVideoFormat
++)
++{
++    tmErrorCode_t   errCode;
++    
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if NativeVideoFormat pointer is Null */
++    RETIF(pNativeVideoFormat == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Get preferred video format from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetVideoPreferred(instance,
++        (tmbslHdmiTxEdidDtd_t *)pNativeVideoFormat) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/*****************************************************************************/
++/**
++    \brief Retrieves supported detailled video descriptors from
++           receiver's EDID. This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pDTDescriptors   Pointer to the array that will receive detailled 
++                            timing descriptors.
++    \param maxDTDesc        Size of the array.
++    \param pWrittenDesc     Pointer to the integer that will receive the actual
++                            number of written descriptors.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidDetailledTimingDescriptors
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    UInt8                           maxDTDesc,
++    UInt8                           *pWrittenDTDesc
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if DTDescriptors, WrittenDTDesc pointers are Null */
++    RETIF(pDTDescriptors == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pWrittenDTDesc == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Get detailled descriptors from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = dlHdmiTxEdidGetDTD(instance, pDTDescriptors, maxDTDesc, pWrittenDTDesc) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/*****************************************************************************/
++/**
++    \brief Retrieves supported monitor descriptor from receiver's EDID.
++           This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pEdidFirstMD     Pointer to the array that will receive the first monitor
++                            descriptors.
++    \param pEdidSecondMD    Pointer to the array that will receive the second monitor
++                            descriptors.
++    \param pEdidOtherMD     Pointer to the array that will receive the other monitor
++                            descriptors.
++    \param maxOtherMD       Size of the array.
++    \param pWrittenOtherMD  Pointer to the integer that will receive the actual
++                            number of written descriptors.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidMonitorDescriptors
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxEdidFirstMD_t     *pEdidFirstMD,
++    tmdlHdmiTxEdidSecondMD_t    *pEdidSecondMD,
++    tmdlHdmiTxEdidOtherMD_t     *pEdidOtherMD,
++    UInt8                       maxOtherMD,
++    UInt8                       *pWrittenOtherMD
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if DTDescriptors, WrittenDTDesc pointers are Null */
++    RETIF(pEdidFirstMD == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pEdidSecondMD == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pEdidOtherMD == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Get monitor descriptors from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetMonitorDescriptors(instance, 
++        (tmbslHdmiTxEdidFirstMD_t *)pEdidFirstMD, (tmbslHdmiTxEdidSecondMD_t *)pEdidSecondMD, 
++        (tmbslHdmiTxEdidOtherMD_t *)pEdidOtherMD, maxOtherMD, pWrittenOtherMD) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/*****************************************************************************/
++/**
++    \brief Retrieves TV picture ratio from receiver's EDID. 
++           This function parses the EDID of Rx device to get
++           the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance             Instance identifier.
++    \param pEdidTvPictureRatio  Pointer to the array that will receive the TV picture 
++                                ratio.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidTVPictureRatio
++(
++    tmInstance_t                 instance,
++    tmdlHdmiTxPictAspectRatio_t  *pEdidTvPictureRatio
++)
++{
++    tmErrorCode_t               errCode;
++    tmbslHdmiTxEdidBDParam_t    edidBDParam;
++    UInt16                      horizontalSize;
++    UInt16                      verticalSize;
++    tmbslHdmiTxEdidDtd_t        edidDTDBuffer;
++    UInt8                       writtenDTD = 0;
++    Bool                        bDataAvailable = False; /* Data available in EDID for calcul TV picture ratio */
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if DTDescriptors, WrittenDTDesc pointers are Null */
++    RETIF(pEdidTvPictureRatio == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Get Basic Display Parameter from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetBasicDisplayParam(instance, 
++        &edidBDParam) ) != TM_OK, errCode)
++
++    horizontalSize  = (UInt16)edidBDParam.uMaxHorizontalSize;
++    verticalSize    = (UInt16)edidBDParam.uMaxVerticalSize;
++
++    if ((horizontalSize == 0) && (verticalSize == 0))
++    {
++        /* Get Basic Display Parameter from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxEdidGetDetailedTimingDescriptors            
++                      (instance, &edidDTDBuffer, 1, &writtenDTD) ) != TM_OK, errCode);
++
++        if (writtenDTD == 1)
++        {
++            horizontalSize  = edidDTDBuffer.uHImageSize;
++            verticalSize    = edidDTDBuffer.uVImageSize;
++            bDataAvailable = True;
++        }
++        else
++        {
++            *pEdidTvPictureRatio = TMDL_HDMITX_P_ASPECT_RATIO_UNDEFINED;
++        }
++    }
++    else
++    {
++        bDataAvailable = True;
++    }
++
++    if (bDataAvailable == True)
++    {
++        *pEdidTvPictureRatio = dlHdmiTxCalcAspectRatio(horizontalSize, verticalSize);
++    }
++        
++        /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++
++
++}
++
++/******************************************************************************
++    \brief Retrieves the sink type from receiver's EDID (HDMI or DVI). This
++           function parses the EDID of Rx device to get the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance  Instance identifier.
++    \param pSinkType Pointer to the array that will receive sink type.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidSinkType
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxSinkType_t    *pSinkType
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if SinkType pointer is Null */
++    RETIF(pSinkType == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Read the source address from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetSinkType(instance,
++        (tmbslHdmiTxSinkType_t *)pSinkType) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Retrieves source address from receivers's EDID. This
++           function parses the EDID of Rx device to get the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance         Instance identifier.
++    \param pSourceAddress   Pointer to the integer that will receive the EDID source 
++                            address.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidSourceAddress
++(
++    tmInstance_t    instance,
++    UInt16          *pSourceAddress
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if SourceAddress pointer is Null */
++    RETIF(pSourceAddress == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Read the source address from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetSourceAddress(instance, 
++        pSourceAddress) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Retreives KSV list received by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param pKsv         Pointer to the array that will receive the KSV list.
++    \param maxKsv       Maximum number of KSV that the array can store.
++    \param pWrittenKsv  Actual number of KSV written into the array.
++    \param pDepth       Connection tree depth returned with KSV list.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetKsvList
++(
++    tmInstance_t    instance,
++    UInt8           *pKsv,
++    UInt8           maxKsv,
++    UInt8           *pWrittenKsv,
++    UInt8           *pDepth,
++    Bool            *pMaxCascExd,
++    Bool            *pMaxDevsExd
++)
++{
++    tmErrorCode_t   errCode;
++#ifndef NO_HDCP
++    UInt16          i,j;
++#endif
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if pDepth, Ksv and WrittenKsv pointers are Null */
++    RETIF(pKsv == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pWrittenKsv == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pDepth == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pMaxCascExd == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pMaxDevsExd == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Maximum Ksv is HDMITX_KSV_LIST_MAX_DEVICES, 128 devices */
++    RETIF_BADPARAM(maxKsv > HDMITX_KSV_LIST_MAX_DEVICES)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Make sure that *pWrittenKsv is 0 */
++    *pWrittenKsv = 0;
++
++    /* Make sure that *pDepth is 0 */
++    *pDepth = 0;
++
++#ifndef NO_HDCP
++
++    *pMaxCascExd = hdcpInfoListTx[instance].hdcpMaxCascExceeded;
++    *pMaxDevsExd = hdcpInfoListTx[instance].hdcpMaxDevsExceeded;
++
++
++    /* Copy the bKsv */
++    if (maxKsv) {
++
++        for (j=0; j<5 ;j++) {
++            pKsv[j] = hdcpInfoListTx[instance].hdcpBksv[4-j];
++        }
++        *pWrittenKsv = *pWrittenKsv + 1;
++
++    } /* maxKsv */
++
++
++    /* Copy the Ksv list */
++    for (i=1; i <= hdcpInfoListTx[instance].hdcpKsvDevices; i++)
++    {
++        if (i < maxKsv)
++        {
++            for (j=0; j<5 ;j++)
++            {
++                pKsv[(5*i)+j] = hdcpInfoListTx[instance].hdcpKsvList[(5*(i-1))+j];
++            }
++            *pWrittenKsv = *pWrittenKsv + 1;
++        }
++    }
++
++    *pDepth = hdcpInfoListTx[instance].hdcpDeviceDepth;
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++#else
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TMDL_ERR_DLHDMITX_NOT_SUPPORTED;
++#endif /* NO_HDCP */
++}
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++/******************************************************************************
++    \brief Retreives HDCP depth received by Tx device.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param pDepth       Connection tree depth returned with KSV list.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetDepth
++(
++    tmInstance_t    instance,
++    UInt8           *pDepth
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if pDepth, is Null */
++    RETIF(pDepth == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Make sure that *pDepth is 0 */
++    *pDepth = 0;
++
++#ifndef NO_HDCP
++
++
++    *pDepth = hdcpInfoListTx[instance].hdcpDeviceDepth;
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++#else
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TMDL_ERR_DLHDMITX_NOT_SUPPORTED;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief Generate SHA_1 interrupt if not occured.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGeneSHA_1_IT
++(
++    tmInstance_t    instance
++)
++{
++    tmErrorCode_t   errCode;
++
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    dlHdmiTxHandleSHA_1(instance);
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++    
++    return TM_OK;
++}
++#endif /* HDMI_TX_REPEATER_ISR_MODE */
++/******************************************************************************
++    \brief Enable/Disable HDCP encryption.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance   Instance identifier.
++    \param hdcpEnable HDCP On/Off (true = On, False = Off).
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_RESOLUTION_UNKNOWN: the resolution is unknown
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetHdcp
++(
++    tmInstance_t    instance,
++    Bool            hdcpEnable
++)
++{
++    tmErrorCode_t               errCode;
++#ifndef NO_HDCP
++   tmdlHdmiTxVidFmtSpecs_t     resolutionSpecs;
++    tmbslHdmiTxVfreq_t          voutFreq;
++    tmbslHdmiTxVidFmt_t         voutFmt;
++    tmbslHdmiTxHdcpTxMode_t     txMode; 
++    tmbslHdmiTxHdcpOptions_t    options;
++    UInt8                       slaveAddress;
++    UInt16                      i;
++#endif
++    tmbslHdmiTxRxSense_t        rxSenseStatus;  /* Rx Sense status */
++    tmbslHdmiTxHotPlug_t        hpdStatus;      /* HPD status */
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Hdcp is not supported if keySeed is null */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        gtmdlHdmiTxDriverConfigTable[instance].keySeed == HDCP_SEED_NULL, TMDL_ERR_DLHDMITX_NOT_SUPPORTED)
++
++    /* Read rxSenseStatus and hpdStatus to authorize HDCP only if active */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxRxSenseGetStatus(instance,
++                                               &rxSenseStatus,False) ) != TM_OK, errCode)
++
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxHotPlugGetStatus(instance,
++                                               &hpdStatus,False) ) != TM_OK, errCode)
++
++#ifndef NO_HDCP
++    if (hdcpEnable == True) /* HDCP ON */
++    {
++        if ( (rxSenseStatus == HDMITX_RX_SENSE_ACTIVE) && (hpdStatus == HDMITX_HOTPLUG_ACTIVE) )
++        {
++
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++           tmbslHdmiTxHdcpPowerDown(instance,False);
++#endif
++            /* Reset HDCP DevLib data to ensure that new values are used */
++            hdcpInfoListTx[instance].hdcpCheckState = TMDL_HDMITX_HDCP_CHECK_IN_PROGRESS;
++            hdcpInfoListTx[instance].hdcpErrorState = 0;
++            hdcpInfoListTx[instance].hdcpKsvDevices = 0;
++            hdcpInfoListTx[instance].bKsvSecure = True;
++            for(i=0; i<TMDL_HDMITX_KSV_BYTES_PER_DEVICE; i++) { hdcpInfoListTx[instance].hdcpBksv[i] = 0; }
++            hdcpInfoListTx[instance].hdcpDeviceDepth = 0;
++
++            hdcpInfoListTx[instance].hdcpMaxCascExceeded = False;
++            hdcpInfoListTx[instance].hdcpMaxDevsExceeded = False;
++
++            /* Current used video output format */
++            voutFmt = (tmbslHdmiTxVidFmt_t)instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format;
++
++            /* Find output vertical frequency from output format */
++            RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++                (errCode = tmdlHdmiTxGetVideoFormatSpecs(instance, (tmdlHdmiTxVidFmt_t)voutFmt, &resolutionSpecs) ) != TM_OK, errCode)
++                voutFreq = (tmbslHdmiTxVfreq_t)resolutionSpecs.vfrequency;
++
++            /* Configure HDCP */
++
++            /* HDCP DDC Slave address */
++            slaveAddress = HDMITX_HDCP_SLAVE_PRIMARY;
++
++            /* Top level or repeater HDCP mode */
++            if (unitTableTx[instance].repeaterEnable == True)
++            {
++                txMode = HDMITX_HDCP_TXMODE_REPEATER;
++            }
++            else
++            {
++                txMode = HDMITX_HDCP_TXMODE_TOP_LEVEL;
++            }
++
++		    instanceStatusInfoTx[instance].pColBarState->changeColorBarNow = True; 
++            instanceStatusInfoTx[instance].pColBarState->colorBarOn = True;
++            dlHdmiTxCheckColorBar(instance);
++
++            /* HDCP options */
++            options = (tmbslHdmiTxHdcpOptions_t)unitTableTx[instance].hdcpOptions;
++
++            RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++                (errCode = tmbslHdmiTxHdcpConfigure(instance, 
++                slaveAddress, txMode, options, HDCP_CHECK_INTERVAL_MS, HDCP_NUM_CHECKS) ) != TM_OK, errCode)
++
++            /* Start HDCP */
++            RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++                (errCode = tmbslHdmiTxHdcpInit(instance, 
++                voutFmt, voutFreq) ) != TM_OK, errCode)
++
++            RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++                (errCode = tmbslHdmiTxHdcpRun(instance)
++                ) != TM_OK, errCode)
++
++            unitTableTx[instance].hdcpEnable = True;
++
++            /* Release the sempahore */
++            RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++            return errCode;
++        }
++
++        /* Release the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++        return TMDL_ERR_DLHDMITX_INVALID_STATE;
++    }
++    else    /* HDCP OFF */
++    {
++		RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++            (errCode = tmbslHdmiTxHdcpStop(instance)
++            ) != TM_OK, errCode)
++
++        unitTableTx[instance].hdcpEnable = False;
++
++        if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_HDCP_INACTIVE) == TMDL_HDMITX_EVENT_ENABLED)
++        {
++            /* Release the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++            unitTableTx[instance].pCallback(TMDL_HDMITX_HDCP_INACTIVE);
++            /* Take the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++        }   
++
++        /* Release the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode);
++        
++#ifdef TMFL_HDCP_OPTIMIZED_POWER
++        tmbslHdmiTxHdcpPowerDown(instance,True);
++#endif
++        return TM_OK;
++    }
++#else
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TMDL_ERR_DLHDMITX_NOT_SUPPORTED;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief Get the driver HDCP state.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance          Instance identifier.
++    \param pHdcpCheckState   Pointer to the integer that will receive the HDCP check state.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetHdcpState
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxHdcpCheck_t   *pHdcpCheckState
++)
++{
++    tmErrorCode_t               errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++   
++    /* Check if HdcpCheckState pointer is Null */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], pHdcpCheckState == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++#ifndef NO_HDCP
++    /* Result of tmbslHdmiTxHdcpCheck */
++    *pHdcpCheckState = hdcpInfoListTx[instance].hdcpCheckState;
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++   
++    return TM_OK;
++#else   
++    *pHdcpCheckState = TMDL_HDMITX_HDCP_CHECK_NOT_STARTED;
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TMDL_ERR_DLHDMITX_NOT_SUPPORTED;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief Check the result of an HDCP encryption attempt, called at
++           intervals (set by timeSinceLastCall) after tmdlHdmiTxSetHdcp(true).
++           This API must be used only in case of No Operating System. if OS, 
++           this is manage internally of this device library.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance             Instance identifier.
++    \param timeSinceLastCall    Time passed in milliseconds since last call,
++                                must be shorter than 600 ms.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_NOT_SUPPORTED: device does not support HDCP
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading the I2C bus
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing the I2C bus
++            - TMBSL_ERR_HDMI_NOT_SUPPORTED: device does not support HDCP
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxHdcpCheck
++(
++    tmInstance_t    instance,
++    UInt16          timeSinceLastCall
++)
++{
++    tmErrorCode_t           errCode;
++    Bool                    featureSupported;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = tmbslHdmiTxHwGetCapabilities(instance, 
++        HDMITX_FEATURE_HW_HDCP, &featureSupported) ) != TM_OK, errCode)
++
++#ifndef NO_HDCP
++    dlHdmiTxCheckColorBar(instance);
++    dlHdmiTxCheckHdcpColorBar(instance);
++
++    if (featureSupported == True)
++    {
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxHdcpCheck(instance,
++            timeSinceLastCall, (tmbslHdmiTxHdcpCheck_t *)&(hdcpInfoListTx[instance].hdcpCheckState)) ) != TM_OK, errCode)
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++#else
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TMDL_ERR_DLHDMITX_NOT_SUPPORTED;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief This function loads a gamut metadata packet into the HW. HW will
++           actually send it at the beginning of next VS, during the vertical
++           blanking.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param enable       Enable/disable gamut metadata packet insertion.
++    \param pGamutData   Pointer to the structure containing gamut metadata
++                        parameters. 
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetGamutPacket
++(
++    tmInstance_t            instance,
++    Bool                    enable,
++    tmdlHdmiTxGamutData_t   *pGamutData
++)
++{
++    tmErrorCode_t           errCode;
++    tmbslHdmiTxPktGamut_t   pkt;
++    UInt8                   i;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    if (enable == True)
++    {
++        /* Check if GamutData pointer is Null */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], pGamutData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    
++        /* Fill data */
++        pkt.HB[0] = 0x0A;
++
++        pkt.HB[1] = 0x00;
++        pkt.HB[1] = (UInt8)(pkt.HB[1] | ((pGamutData->nextField & 0x01) << 7));
++        pkt.HB[1] |= (pGamutData->GBD_Profile & 0x07) << 4;
++        pkt.HB[1] |= (pGamutData->affectedGamutSeqNum & 0x0F);
++
++        pkt.HB[2] = 0x00;
++        pkt.HB[2] = (UInt8)(pkt.HB[2] | ((pGamutData->noCurrentGBD & 0x01) << 7));
++        pkt.HB[2] |= (pGamutData->packetSequence & 0x03) << 4;
++        pkt.HB[2] |= (pGamutData->currentGamutSeqNum & 0x0F);
++
++        for(i=0; i<28; i++)
++        {
++            pkt.PB[i] = pGamutData->payload[i];
++        }
++
++        /* Store GBD color space */
++        if ( ((pGamutData->payload[0]) & 0x03) == 2 )
++        {
++            instanceStatusInfoTx[instance].pGamutState->wideGamutColorSpace = TMDL_HDMITX_EXT_COLORIMETRY_XVYCC709;
++        }
++        else
++        {
++            instanceStatusInfoTx[instance].pGamutState->wideGamutColorSpace = TMDL_HDMITX_EXT_COLORIMETRY_XVYCC601;
++        }
++
++        /* Fill Gamut metadata packet */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxPktFillGamut(instance,
++            &pkt, instanceStatusInfoTx[instance].pGamutState->gamutBufNum) ) != TM_OK, errCode)
++
++        /* Enable Gamut metadata transmission */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxPktSendGamut(instance,
++            instanceStatusInfoTx[instance].pGamutState->gamutBufNum, enable) ) != TM_OK, errCode)
++
++        /* Use next buffer for next time */
++        if (instanceStatusInfoTx[instance].pGamutState->gamutBufNum == 0)
++        {
++            instanceStatusInfoTx[instance].pGamutState->gamutBufNum = 1;
++        }
++        else
++        {
++            instanceStatusInfoTx[instance].pGamutState->gamutBufNum = 0;
++        }
++    }
++    else
++    {
++        /* Disable Gamut metadata transmission */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance],
++            (errCode = tmbslHdmiTxPktSendGamut(instance,
++            0, enable) ) != TM_OK, errCode)
++    }
++
++    /* Store gamut status */
++    instanceStatusInfoTx[instance].pGamutState->gamutOn = enable;
++    if(enable) instanceStatusInfoTx[instance].pGamutState->extColOn = False;
++
++	/* Set avi infoframe */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = dlHdmiTxSetVideoInfoframe(instance, 
++        instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format, 
++        instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.mode) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief This function set the extended colorimetry with one of the following 
++           extended colorimetries(bits EC2-0): xvYCC601, xvYCC709, sYCC601, 
++           AdobeYCC601, AdobeRGB. When the parameter extendedColorimetry is 
++           xvYCC601 or xvYCC70, this function calls the API tmdlHdmiTxSetGamutPacket
++           to send Gamut Packet Data that does not exist for all other types of
++           extended colorimetries for which pointer pGamutData can be set to NULL.
++           This function also allows to set YCC Quantization Range (YQ1-0)
++           
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance              Instance identifier.
++    \param enable                Enable/Disable extended colorimetry.
++    \param extendedColorimetry   value of the extended colorimetry (bits EC2 EC1 EC0). 
++    \param yccQR                 YCC quantisation range
++    \param pGamutData            Pointer to the structure containing gamut metadata
++                                 parameters. 
++
++    \return The call result:
++           - TM_OK: the call was successful
++           - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong
++           - TMDL_ERR_DLHDMITX_BAD_PARAMETER: a parameter was out of range
++           - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for the function
++           - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++           - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++           - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++           - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++           - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++           - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxSetExtendedColorimetry
++(
++    tmInstance_t                 instance,
++    Bool                         enable,
++    tmdlHdmiTxExtColorimetry_t   extendedColorimetry,
++    tmdlHdmiTxYCCQR_t            yccQR,
++    tmdlHdmiTxGamutData_t        *pGamutData
++)
++{
++    tmErrorCode_t errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check if extendedColorimetry & yccQR values are in the correct range */
++    if(enable)  // no need to check them for disable handling
++    {
++        RETIF(extendedColorimetry >= TMDL_HDMITX_EXT_COLORIMETRY_INVALID, TMDL_ERR_DLHDMITX_BAD_PARAMETER)
++        RETIF(yccQR >= TMDL_HDMITX_YQR_INVALID, TMDL_ERR_DLHDMITX_BAD_PARAMETER)
++    }
++    
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Store YCC quantisation range value for later AVI InfoFrame insertion */
++    if(enable) instanceStatusInfoTx[instance].pGamutState->yccQR = yccQR;
++
++    /* Extended colorimetries that need to send Gamut Packet Data */
++    if( ( (enable == True) && ( (extendedColorimetry == TMDL_HDMITX_EXT_COLORIMETRY_XVYCC601) || 
++          (extendedColorimetry == TMDL_HDMITX_EXT_COLORIMETRY_XVYCC709) ) ) 
++                         || 
++        ( (enable == False) && (instanceStatusInfoTx[instance].pGamutState->gamutOn == True) ) )
++    {   
++        /* can not have two different types of extended colorimeties enabled in the same time */
++        if(enable) instanceStatusInfoTx[instance].pGamutState->extColOn = False;
++
++        /* Release the sempahore */
++        RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++        /* Call the API that handles Gamut MetaData */
++        RETIF( (errCode = tmdlHdmiTxSetGamutPacket(instance, enable, pGamutData) ) != TM_OK, errCode)
++
++        return TM_OK;
++    }
++
++    /* Extended colorimetries that do not need to send Gamut Packet Data */
++    if (instanceStatusInfoTx[instance].pGamutState->gamutOn == True)
++    {
++        /* Disable Gamut metadata transmission */
++        RETIF_SEM(dlHdmiTxItSemaphore[instance], (errCode = tmbslHdmiTxPktSendGamut(instance, 0, False) ) != TM_OK, errCode)
++
++        instanceStatusInfoTx[instance].pGamutState->gamutOn = False;
++    }
++
++    /* Store the extended colorimetry that does not need sending Gamut Packet Data */
++    if(enable) instanceStatusInfoTx[instance].pGamutState->wideGamutColorSpace = extendedColorimetry;
++    instanceStatusInfoTx[instance].pGamutState->extColOn = enable;
++    
++	/* Set avi infoframe */
++    RETIF_SEM(dlHdmiTxItSemaphore[instance],
++        (errCode = dlHdmiTxSetVideoInfoframe(instance, 
++        instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format, 
++        instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.mode) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief This function set the revocation list use for HDCP
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++    \param listPtr      Pointer on revocation list provide by application.
++    \param length       length of revocation list. 
++
++    \return The call result:
++            - TM_OK: the call was successful, however RX keys have
++                     not been checked with provided revocation list
++                     because they are not available.
++            - TMDL_DLHDMITX_HDCP_SECURE: the call was successful, RX keys are secure
++            - TMDL_DLHDMITX_HDCP_NOT_SECURE: the call was successful, RX keys are NOT secure
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: we are a repeater                             
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++
++tmErrorCode_t tmdlHdmiTxSetHDCPRevocationList(
++    tmInstance_t    instance,
++    void            *listPtr, 
++    UInt32          length
++)
++{
++  tmErrorCode_t errCode       = TM_OK;
++#ifndef NO_HDCP
++  tmErrorCode_t errCodeSem    = TM_OK;
++  UInt8         aCounter     = 0;
++  UInt8         indexKSVList = 0;
++  UInt8         i;
++  Bool 		bIsSecure = True;
++#endif
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check parameters */
++    RETIF((listPtr == Null) || (length == 0), TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++#ifndef NO_HDCP
++  /* --------------------- */
++  /* Take the semaphore    */
++  /* --------------------- */
++  RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCodeSem)
++
++  /* Register revocation list */
++    unitTableTx[instance].revocationList.pList  = (UInt8 *)listPtr;
++    unitTableTx[instance].revocationList.length = length;
++
++  /* Look if hdcpBksv is filled in */
++  for (i=0; i<TMDL_HDMITX_KSV_BYTES_PER_DEVICE; i++) {
++    if ( hdcpInfoListTx[instance].hdcpBksv[i] == 0) aCounter++;
++  }
++
++  /* If it the case ,check bksv */
++  if (aCounter != TMDL_HDMITX_KSV_BYTES_PER_DEVICE) {
++
++    dlHdmiTxCheckHdcpBksv (instance, hdcpInfoListTx[instance].hdcpBksv,&bIsSecure, True);
++
++    /* bksv is secure */
++    if (bIsSecure == True) {
++
++      /* if HDMI TX is at top level */
++      if (unitTableTx[instance].repeaterEnable == False) {
++
++	/* if present, check ksv list */
++	if (hdcpInfoListTx[instance].hdcpKsvDevices) {
++
++	  while (( indexKSVList <  TMDL_HDMITX_KSV_LIST_MAX_DEVICES ) &&
++		 ( indexKSVList <  hdcpInfoListTx[instance].hdcpKsvDevices ) && 
++		 ( bIsSecure == True)) {
++
++	    dlHdmiTxCheckHdcpBksv (instance,
++				   &(hdcpInfoListTx[instance].hdcpKsvList[indexKSVList * TMDL_HDMITX_KSV_BYTES_PER_DEVICE]),
++				   &bIsSecure,
++				   False);
++	    indexKSVList++;
++	  }
++
++	  if (bIsSecure == True) {
++	    errCode = TMDL_DLHDMITX_HDCP_SECURE;
++	  }
++	  else {
++	    errCode = TMDL_DLHDMITX_HDCP_NOT_SECURE;
++	  }
++	}
++	else { /* ksv list does NOT exist */
++
++	  /* we suppose that application calls the API after RX_KEYS_RECEIVED */
++	  errCode = TMDL_DLHDMITX_HDCP_SECURE;
++	}
++
++      }
++      else { /* we are a repeater */
++	errCode = TMDL_ERR_DLHDMITX_INVALID_STATE;
++      }
++
++    }
++    else { /* bksv NOT secure */
++
++      errCode = TMDL_DLHDMITX_HDCP_NOT_SECURE;
++    }
++
++  } 
++  else {
++    /* bksv is not read, could not be tested */
++    errCode = TM_OK;
++  }
++
++  /* --------------------------- */
++    /* Release the sempahore */
++  /* --------------------------- */
++  RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCodeSem)
++#else
++     (void)instance; /* Remove compiler warning */
++#endif /* NO_HDCP */
++  return errCode;
++}
++
++/******************************************************************************
++    \brief This function set the B... screen
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier.
++
++    \return The call result:
++            - TM_OK: the call was successful, however RX keys have
++                     not been checked with provided revocation list
++                     because they are not available.
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++
++
++******************************************************************************/
++
++tmErrorCode_t tmdlHdmiTxSetBScreen(
++    tmInstance_t            instance,
++    tmdlHdmiTxTestPattern_t pattern
++)
++{
++
++    tmErrorCode_t errCodeSem    = TM_OK;
++    tmErrorCode_t errCode       = TM_OK;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* --------------------- */
++    /* Take the semaphore    */
++    /* --------------------- */
++    RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCodeSem)
++
++    gtmdlHdmiTxDriverConfigTable[instance].pattern = pattern;
++
++    /* Set service mode colour bar on/off (also used as HDCP logo pattern) */
++    (void)dlHdmiTxSetTestPatternOn(instance, instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format,
++        instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.mode, 
++        gtmdlHdmiTxDriverConfigTable[instance].pattern);
++
++    /* --------------------------- */
++    /* Release the sempahore */
++    /* --------------------------- */
++    RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCodeSem)
++
++    return errCode;
++
++}
++
++/******************************************************************************
++    \brief This function set the Remove B.... screen
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance     Instance identifier. 
++
++    \return The call result:
++            - TM_OK: the call was successful, however RX keys have
++                     not been checked with provided revocation list
++                     because they are not available.
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++
++
++******************************************************************************/
++
++tmErrorCode_t tmdlHdmiTxRemoveBScreen(
++    tmInstance_t    instance
++)
++{
++
++    tmErrorCode_t errCodeSem    = TM_OK;
++    tmErrorCode_t errCode       = TM_OK;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* --------------------- */
++    /* Take the semaphore    */
++    /* --------------------- */
++    RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCodeSem)
++
++    /* Restore last output format and mode */
++    (void)dlHdmiTxSetTestPatternOff(instance, 
++            instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format,
++            instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.mode);
++
++    /* --------------------------- */
++    /* Release the sempahore */
++    /* --------------------------- */
++    RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCodeSem)
++
++    return errCode;
++
++}
++
++/******************************************************************************
++    \brief tmdlHdmiTxConvertDTDtoCEA .
++
++    \param DTDescriptors     DTD to convert.
++
++    \return NA.
++
++******************************************************************************/
++tmdlHdmiTxVidFmt_t tmdlHdmiTxConvertDTDtoCEA
++(
++    tmInstance_t    instance,
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors
++)
++{
++
++    tmdlHdmiTxVidFmt_t          codeCEA;
++    tmdlHdmiTxPictAspectRatio_t pictureAspectRatio;
++    Bool                        formatInterlaced;
++
++    /* --------------------- */
++    /* Take the semaphore    */
++    /* --------------------- */
++    tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++
++    formatInterlaced = False;
++
++    if ((pDTDescriptors->flags) & 0x80)
++    {
++        formatInterlaced = True;
++    }
++
++    pictureAspectRatio = dlHdmiTxCalcAspectRatio (pDTDescriptors->hImageSize, pDTDescriptors->vImageSize);
++
++    switch (pDTDescriptors->hActivePixels)
++    {
++        case 640:
++            codeCEA = dlHdmiTxConvertDTDtoCEA_640HAP(pDTDescriptors);
++        break;
++
++        case 720:
++            codeCEA = dlHdmiTxConvertDTDtoCEA_720HAP(pDTDescriptors, pictureAspectRatio);
++        break;
++
++        case 1280:
++            codeCEA = dlHdmiTxConvertDTDtoCEA_1280HAP(pDTDescriptors);
++        break;
++
++        case 1920:
++            codeCEA = dlHdmiTxConvertDTDtoCEA_1920HAP(pDTDescriptors, formatInterlaced);
++        break;
++
++        case 1440:
++            codeCEA = dlHdmiTxConvertDTDtoCEA_1440HAP(pDTDescriptors, pictureAspectRatio, formatInterlaced);
++        break;
++
++        case 2880:
++            codeCEA = dlHdmiTxConvertDTDtoCEA_2880HAP(pDTDescriptors, pictureAspectRatio, formatInterlaced);
++        break;
++
++        default:
++            /* Not a valid format */
++            codeCEA = TMDL_HDMITX_VFMT_NULL;
++        break;
++    }
++
++    /* --------------------------- */
++    /* Release the sempahore */
++    /* --------------------------- */
++    tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++
++    return codeCEA;
++
++}
++
++/*============================================================================*/
++/*                           INTERNAL FUNCTION                                */
++/*============================================================================*/
++
++/******************************************************************************
++    \brief Get the REFPIX and REFLINE for output and scaler 
++            for the current settings.
++
++    \param vinFmt       Video input format.
++    \param vinMode      Video input mode.
++    \param voutFmt      Video output format.
++    \param syncIn       Type of synchro (ext or emb).
++    \param pixRate      Video pixel rate.
++    \param pRefPix      RefPix for output.
++    \param pRefLine     RefLine for output.
++    \param pScRefPix    RefPix for scaler.
++    \param pScRefLine   RefLine for scaler.
++    \param pbVerified   Pointer to the boolean that will receive the fact that
++                        this scaler setting was verified.
++
++    \return True (Found) or False (Not found).
++
++******************************************************************************/
++static Bool dlHdmiTxGetReflineRefpix
++(
++    tmdlHdmiTxVidFmt_t      vinFmt,    
++    tmdlHdmiTxVinMode_t     vinMode,   
++    tmdlHdmiTxVidFmt_t      voutFmt,   
++    UInt8                   syncIn,
++    tmdlHdmiTxPixRate_t     pixRate,
++    UInt16                  *pRefPix,  
++    UInt16                  *pRefLine, 
++    UInt16                  *pScRefPix,
++    UInt16                  *pScRefLine,
++    Bool                    *pbVerified
++)
++{
++    UInt8 shortVinFmt;
++    UInt8 shortVoutFmt;
++    int i;
++    Bool bFound;
++    tmdlHdmiTxVidFmt_t      vinFmtIndex, voutFmtIndex;
++    
++    /* Search for all values to match in table, until table end is reached
++     * when both refPix values are zero */
++    *pRefPix    = 0;
++    *pRefLine   = 0;
++    *pScRefPix  = 0;
++    *pScRefLine = 0;
++    
++    /* If match is not found in table, we can assume a verified non-scaler 
++     * combination */
++    *pbVerified = 1;
++    bFound = False;
++
++    if ((voutFmt  <  TMDL_HDMITX_VFMT_TV_NO_REG_MIN) 
++        || ((voutFmt >= HDMITX_VFMT_35_2880x480p_60Hz) && (voutFmt <= HDMITX_VFMT_38_2880x576p_50Hz)))    
++    {
++        vinFmtIndex  = dlHdmiTxCalcVidFmtIndex(vinFmt);
++        voutFmtIndex = dlHdmiTxCalcVidFmtIndex(voutFmt);
++        shortVinFmt  = kVfmtToShortFmt_TV[vinFmtIndex];
++        shortVoutFmt = kVfmtToShortFmt_TV[voutFmtIndex];
++
++        for (i = 0; kRefpixRefline[i].shortVinFmt != TV_INVALID; i++)
++        {
++            if ((kRefpixRefline[i].shortVinFmt == shortVinFmt)
++                &&  (UNPKMODE(kRefpixRefline[i].modeRateSyncVerf) == vinMode)
++                &&  (kRefpixRefline[i].shortVoutFmt == shortVoutFmt)
++                &&  (UNPKRATE(kRefpixRefline[i].modeRateSyncVerf) == pixRate)
++                &&  (UNPKSYNC(kRefpixRefline[i].modeRateSyncVerf) == syncIn))
++            {
++                *pRefPix    = kRefpixRefline[i].refPix;
++                *pRefLine   = kRefpixRefline[i].refLine;
++                *pScRefPix  = kRefpixRefline[i].scRefPix;
++                *pScRefLine = kRefpixRefline[i].scRefLine;
++                *pbVerified = UNPKVERF(kRefpixRefline[i].modeRateSyncVerf);
++                bFound = True;
++                break;
++            }
++        }
++    }
++
++    return bFound;
++}
++
++/******************************************************************************
++    \brief Set the video infoframe.
++
++    \param instance     Instance identifier.
++    \param voutFmt      Video output format.
++    \param voutMode     Video output mode.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++static tmErrorCode_t dlHdmiTxSetVideoInfoframe 
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxVidFmt_t      voutFmt,
++    tmdlHdmiTxVoutMode_t    voutMode
++)
++{
++    tmErrorCode_t         errCode;        
++    tmdlHdmiTxAviIfData_t contentVif;
++    tmdlHdmiTxVidFmt_t    voutFmtIndex;
++
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    contentVif.colorIndicator           = voutMode; /* 3rd api_set_avi_infoframe param */
++    contentVif.activeInfoPresent        = 0;
++    contentVif.barInformationDataValid  = 0;
++    contentVif.scanInformation          = 0;
++
++    voutFmtIndex = dlHdmiTxCalcVidFmtIndex(voutFmt);
++    contentVif.pictureAspectRatio = kVfmtToAspect_TV[voutFmtIndex];
++
++    contentVif.activeFormatAspectRatio = 8;
++    contentVif.nonUniformPictureScaling = 0;
++
++#ifdef FORMAT_PC
++    if (voutFmt >= TMDL_HDMITX_VFMT_PC_MIN)
++    {
++        if (voutFmt == TMDL_HDMITX_VFMT_PC_640x480p_60Hz)
++        {
++            contentVif.videoFormatIdentificationCode = (tmbslHdmiTxVidFmt_t)TMDL_HDMITX_VFMT_01_640x480p_60Hz;
++        }
++        else
++        {
++            /* Format PC not Valid in EIA861b */
++            contentVif.videoFormatIdentificationCode = (tmbslHdmiTxVidFmt_t)TMDL_HDMITX_VFMT_NULL; 
++        }
++    }
++    else
++    {
++#endif /* FORMAT_PC */
++
++        contentVif.videoFormatIdentificationCode = (tmbslHdmiTxVidFmt_t)voutFmt;
++        
++#ifdef FORMAT_PC
++    }
++#endif /* FORMAT_PC */
++
++
++    if (((voutFmt >= TMDL_HDMITX_VFMT_06_720x480i_60Hz) && (voutFmt <= TMDL_HDMITX_VFMT_09_720x240p_60Hz))
++        || ((voutFmt >= TMDL_HDMITX_VFMT_21_720x576i_50Hz) && (voutFmt <= TMDL_HDMITX_VFMT_24_720x288p_50Hz)))
++    {
++        /* Force pixel repeat for formats where it's mandatory (Pixel Frequency < 20 Mpix/s)*/
++        contentVif.pixelRepetitionFactor = 1; 
++    }
++    else if((voutFmt == TMDL_HDMITX_VFMT_10_720x480i_60Hz)  || (voutFmt == TMDL_HDMITX_VFMT_11_720x480i_60Hz)  ||
++            (voutFmt == TMDL_HDMITX_VFMT_25_720x576i_50Hz)  || (voutFmt == TMDL_HDMITX_VFMT_26_720x576i_50Hz) )
++    {
++        contentVif.pixelRepetitionFactor = HDMITX_PIXREP_3;    // pixel sent 1 or 10 times, here 4 times
++    }
++    else if((voutFmt == TMDL_HDMITX_VFMT_14_1440x480p_60Hz) || (voutFmt == TMDL_HDMITX_VFMT_15_1440x480p_60Hz) ||
++            (voutFmt == TMDL_HDMITX_VFMT_29_1440x576p_50Hz) || (voutFmt == TMDL_HDMITX_VFMT_30_1440x576p_50Hz))
++    {
++        contentVif.pixelRepetitionFactor = HDMITX_PIXREP_1;    // pixel sent 1 or 2 times, here 2 times
++    }
++    else if((voutFmt >= TMDL_HDMITX_VFMT_35_2880x480p_60Hz) && (voutFmt <= TMDL_HDMITX_VFMT_38_2880x576p_50Hz))
++    {
++            contentVif.pixelRepetitionFactor = HDMITX_PIXREP_3;
++    }
++    else /* Default to no repeat for all other formats */
++    {
++        contentVif.pixelRepetitionFactor = HDMITX_PIXREP_NONE; 
++    }
++
++    if ((instanceStatusInfoTx[instance].pGamutState->gamutOn  == True) ||
++        (instanceStatusInfoTx[instance].pGamutState->extColOn == True))
++    {
++        contentVif.colorimetry = (UInt8)TMDL_HDMITX_COLORIMETRY_EXTENDED;
++    }
++    else
++    {
++        switch (voutFmt)
++        {
++            case TMDL_HDMITX_VFMT_04_1280x720p_60Hz:
++            case TMDL_HDMITX_VFMT_05_1920x1080i_60Hz:
++            case TMDL_HDMITX_VFMT_16_1920x1080p_60Hz:
++            case TMDL_HDMITX_VFMT_19_1280x720p_50Hz:
++            case TMDL_HDMITX_VFMT_20_1920x1080i_50Hz:
++            case TMDL_HDMITX_VFMT_31_1920x1080p_50Hz:
++                contentVif.colorimetry = (UInt8)TMDL_HDMITX_COLORIMETRY_ITU709;    
++                break;
++
++	        default:
++                contentVif.colorimetry = (UInt8)TMDL_HDMITX_COLORIMETRY_ITU601;
++                break;
++        }
++    }
++
++    contentVif.lineNumberEndTopBar      = 0;
++    contentVif.lineNumberStartBottomBar = 0;
++    contentVif.lineNumberEndLeftBar     = 0;
++    contentVif.lineNumberStartRightBar  = 0;
++
++    errCode = dlHdmiTxSetRawVideoInfoframe(instance, &contentVif, True);
++
++    /* Ignore infoframe interlock in DVI mode */
++    if (errCode == TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED)
++    {
++        errCode = TM_OK;
++    }
++    
++    return errCode;
++}
++
++/******************************************************************************
++    \brief Set the video infoframe.
++
++    \param instance     Instance identifier.
++    \param voutFmt      Video output format.
++    \param voutMode     Video output mode.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++            - TMBSL_ERR_HDMI_I2C_READ: failed when reading to the I2C bus
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_OPERATION_NOT_PERMITTED: not allowed in DVI mode
++
++******************************************************************************/
++static tmErrorCode_t dlHdmiTxSetRawVideoInfoframe 
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxAviIfData_t   *pContentVif,
++    Bool                    enable
++)
++{
++
++    tmErrorCode_t           errCode;
++    tmbslHdmiTxPktRawAvi_t  PktInfoFrame;
++    UInt8         i;
++
++    if(pContentVif != Null)
++    {
++
++        for(i=0; i<sizeof(PktInfoFrame.PB); i++) { PktInfoFrame.PB[i] = 0; }
++
++        /* Prepare VIF header */
++        PktInfoFrame.HB[0] = 0x82;     /* Video InfoFrame */
++        PktInfoFrame.HB[1] = 0x02;     /* Version 2 [HDMI 1.2] */
++        PktInfoFrame.HB[2] = 0x0D;     /* Length [HDMI 1.2] */
++
++        /* Prepare VIF packet (byte numbers offset by 3) */
++        PktInfoFrame.PB[0] = 0;     /* Preset checksum to zero so calculation works! */
++        PktInfoFrame.PB[1] = ((pContentVif->colorIndicator& 0x03) << 5) |       /* Y1-0, B1-0,S1-0 */
++                    ((pContentVif->barInformationDataValid& 0x03) << 2) |
++                        (pContentVif->scanInformation & 0x03);
++        if(pContentVif->activeInfoPresent == True)
++        {
++            PktInfoFrame.PB[1] += 0x10;                              /* A0 bit */
++        }
++
++        PktInfoFrame.PB[2] = ((pContentVif->colorimetry & 0x03) << 6) |  /* C1-0, M1-0, R3-0 */
++                    ((pContentVif->pictureAspectRatio & 0x03) << 4) |
++                        (pContentVif->activeFormatAspectRatio  & 0x0F);
++
++        PktInfoFrame.PB[3] = (pContentVif->nonUniformPictureScaling & 0x03);              /* SC1-0 */ /* [HDMI 1.2] */
++
++            /* Q1-0 = 00 => RGB Quantization Range depends on video format (CEA-861) */
++            /* Limited Range for all video formats except PC formats which requires Full Range */
++
++        if (pContentVif->colorimetry == TMDL_HDMITX_COLORIMETRY_EXTENDED)
++        {
++            PktInfoFrame.PB[3] = (( ((UInt8)instanceStatusInfoTx[instance].pGamutState->wideGamutColorSpace) & 0x07) <<4)
++                                | PktInfoFrame.PB[3];
++        }
++
++            /* Bit ITC = 0 => No Content Type ; Bit ITC = 1 => Content Type (see CN1-0) */
++            /* Today ITC = 0 => No Content Type */
++
++        PktInfoFrame.PB[4] = (pContentVif->videoFormatIdentificationCode & 0x7F);            /* VIC6-0 */
++
++        PktInfoFrame.PB[5] = (pContentVif->pixelRepetitionFactor & 0x0F);          /* PR3-0 */
++
++            /* CN1-0 => Content Type */
++            /* Today CN1-0 = 00 => No Data */
++
++        /* YQ1-0 => YCC Quantization Range, only managed for those extended colorimetries */
++        if (pContentVif->colorimetry == TMDL_HDMITX_COLORIMETRY_EXTENDED)
++        {
++            PktInfoFrame.PB[5] |= ( ((UInt8)instanceStatusInfoTx[instance].pGamutState->yccQR) & 0x03) << 6;
++        }
++        PktInfoFrame.PB[6] = (UInt8)(pContentVif->lineNumberEndTopBar & 0x00FF);
++        PktInfoFrame.PB[7] = (UInt8)((pContentVif->lineNumberEndTopBar & 0xFF00) >> 8);
++        PktInfoFrame.PB[8] = (UInt8)(pContentVif->lineNumberStartBottomBar & 0x00FF);
++        PktInfoFrame.PB[9] = (UInt8)((pContentVif->lineNumberStartBottomBar & 0xFF00) >> 8);
++        PktInfoFrame.PB[10] = (UInt8)(pContentVif->lineNumberEndLeftBar & 0x00FF);
++        PktInfoFrame.PB[11] = (UInt8)((pContentVif->lineNumberEndLeftBar & 0xFF00) >> 8);
++        PktInfoFrame.PB[12] = (UInt8)(pContentVif->lineNumberStartRightBar & 0x00FF);
++        PktInfoFrame.PB[13] = (UInt8)((pContentVif->lineNumberStartRightBar & 0xFF00) >> 8);
++
++        /* Calculate checksum - this is worked out on "Length" bytes of the
++            * packet, the checksum (which we've preset to zero), and the three
++            * header bytes.
++            */
++        PktInfoFrame.PB[0] = dlHdmiTxcalculateCheksumIF(&PktInfoFrame);
++
++        errCode = tmbslHdmiTxPktSetRawVideoInfoframe(instance,
++                    &PktInfoFrame, enable);
++    }
++    else
++    {
++        errCode = tmbslHdmiTxPktSetVideoInfoframe(instance,
++                                                                                        Null, enable);
++    }
++
++    return errCode;
++
++}
++
++/*============================================================================*/
++/* calculateChecksum - returns the byte needed to yield a checksum of zero    */
++/*============================================================================*/
++static UInt8
++dlHdmiTxcalculateCheksumIF
++(   
++    tmbslHdmiTxPktRawAvi_t       *pData     /* Pointer to checksum data */
++)
++{
++    UInt8       checksum = 0;   /* Working checksum calculation */
++    UInt8       result = 0;     /* Value to be returned */
++    UInt8       numBytes = 0;
++    Int         i;
++
++    if(pData != Null)
++    {
++
++        numBytes = sizeof(pData->HB);
++
++        for (i = 0; i < numBytes; i++)
++        {
++            checksum = checksum + pData->HB[i];
++        }
++
++        numBytes = sizeof(pData->PB);
++
++        for (i = 0; i < numBytes; i++)
++        {
++            checksum = checksum + pData->PB[i];
++        }
++
++        result = (UInt8)((255 - checksum) + 1);
++    }
++    return result;          /* returns 0 in the case of null ptr or 0 bytes */
++}
++
++/******************************************************************************
++    \brief Set colourbar test pattern on with RGB infoframe
++
++    \param instance     Instance identifier.
++    \param voutFmt      Video output format.
++    \param voutMode     Video output mode.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++******************************************************************************/
++tmErrorCode_t dlHdmiTxSetTestPatternOn
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxVidFmt_t		voutFmt,
++    tmdlHdmiTxVoutMode_t    voutMode,
++    tmdlHdmiTxTestPattern_t pattern
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    RETIF( (errCode = tmbslHdmiTxTestSetPattern(instance, 
++                        (tmbslHdmiTxTestPattern_t)pattern) ) != TM_OK, errCode)
++
++    if (pattern > TMDL_HDMITX_PATTERN_CBAR8)
++    {
++        RETIF( (errCode = dlHdmiTxSetVideoInfoframe(instance, voutFmt, voutMode) ) != TM_OK, errCode)
++    }
++    else
++    {
++        /* For TMDL_HDMITX_PATTERN_CBAR8 and TMDL_HDMITX_PATTERN_CBAR4, video mode in infoframe should be RGB */
++        RETIF( (errCode = dlHdmiTxSetVideoInfoframe(instance, voutFmt, TMDL_HDMITX_VOUTMODE_RGB444) ) != TM_OK, errCode)
++    }
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief Set colourbar test pattern off with previous infoframe
++
++    \param instance     Instance identifier.
++    \param voutFmt      Video output format.
++    \param voutMode     Video output mode.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or 
++              out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++            - TMBSL_ERR_HDMI_I2C_WRITE: failed when writing to the I2C bus
++
++******************************************************************************/
++tmErrorCode_t dlHdmiTxSetTestPatternOff
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxVidFmt_t      voutFmt,
++    tmdlHdmiTxVoutMode_t    voutMode
++)
++{
++    tmErrorCode_t errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    RETIF( (errCode = tmbslHdmiTxTestSetPattern(instance, 
++                        (tmbslHdmiTxTestPattern_t)TMDL_HDMITX_PATTERN_OFF) ) != TM_OK, errCode)
++
++    /* Restore video infoframe */
++    RETIF( (errCode = dlHdmiTxSetVideoInfoframe(instance, voutFmt, voutMode) ) != TM_OK, errCode)
++
++    return TM_OK;
++}
++
++/******************************************************************************
++    \brief HDCP ENCRYPT interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleENCRYPT
++(
++    tmInstance_t    instance
++)
++{
++#ifndef NO_HDCP
++
++    tmbslHdmiTxHdcpHandleENCRYPT(instance);
++
++    if (instanceStatusInfoTx[instance].pColBarState->disableColorBarOnR0 == False)
++    {
++        instanceStatusInfoTx[instance].pColBarState->hdcpColbarChange = False;
++        instanceStatusInfoTx[instance].pColBarState->hdcpEncryptOrT0 = True;
++    }
++    instanceStatusInfoTx[instance].pColBarState->disableColorBarOnR0 = False;
++#else
++    (void)instance; /* Remove compiler warning */
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief HPD interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleHPD
++(
++    tmInstance_t    instance
++)
++{
++    tmErrorCode_t           errCode;
++    tmbslHdmiTxHotPlug_t    hpdStatus;  /* HPD status */
++    tmPowerState_t          powerState; /* Power state of transmitter */
++
++    hpdStatus = HDMITX_HOTPLUG_INVALID;
++
++    /* Get Hot Plug status */
++    errCode = tmbslHdmiTxHotPlugGetStatus(instance,
++                                          &hpdStatus,False);
++
++    if (errCode != TM_OK) return;
++
++    /* Get the power state of the transmitter */
++    errCode = tmbslHdmiTxPowerGetState(instance,
++                &powerState);
++
++    if (errCode != TM_OK) return;
++
++    /* Has hot plug changed to Active? */
++    if (hpdStatus == HDMITX_HOTPLUG_ACTIVE)
++    {
++        /* Set state machine to Plugged */
++        dlHdmiTxSetState(instance, STATE_PLUGGED);
++
++        if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_HPD_ACTIVE) == TMDL_HDMITX_EVENT_ENABLED)
++        {
++            /* Release the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++            unitTableTx[instance].pCallback(TMDL_HDMITX_HPD_ACTIVE);
++            /* Take the sempahore */
++           (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++        }        
++
++        if (powerState == tmPowerOn)
++        {
++            /* Yes: Wait for DDC line to settle before reading EDID */
++            tmbslHdmiTxSysTimerWait(instance,
++                    500); /* ms */
++
++            /* Request EDID read */
++            errCode = tmbslHdmiTxEdidRequestBlockData(instance,
++                unitTableTx[instance].pEdidBuffer, (Int)((unitTableTx[instance].edidBufferSize) >> 7),
++                (Int)(unitTableTx[instance].edidBufferSize));
++
++            if (errCode != TM_OK) return;
++        }
++    }
++    else
++    {
++#ifndef NO_HDCP
++        if (unitTableTx[instance].hdcpEnable == True)
++        {
++            /* Release the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++            /* Switch off HDCP */
++            (void)tmdlHdmiTxSetHdcp(instance, False);
++            /* Take the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++        }
++#endif /* NO_HDCP */
++
++        /* Set state machine to Unplugged */
++        dlHdmiTxSetState(instance, STATE_UNPLUGGED);
++
++        if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_HPD_INACTIVE) == TMDL_HDMITX_EVENT_ENABLED)
++        {
++            /* Release the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++            unitTableTx[instance].pCallback(TMDL_HDMITX_HPD_INACTIVE);
++            /* Take the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++        }        
++    }
++}
++
++/******************************************************************************
++    \brief T0 interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleT0
++(
++    tmInstance_t    instance
++)
++{
++#ifndef NO_HDCP
++    tmErrorCode_t errCode;
++
++    errCode = tmbslHdmiTxHdcpHandleT0(instance);
++    
++    if (errCode != TM_OK) return;
++
++    tmbslHdmiTxHdcpGetT0FailState(instance,
++            &(hdcpInfoListTx[instance].hdcpErrorState));
++
++    if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_HDCP_INACTIVE) == TMDL_HDMITX_EVENT_ENABLED)
++    {
++        /* Release the sempahore */
++        (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++        unitTableTx[instance].pCallback(TMDL_HDMITX_HDCP_INACTIVE);
++        /* Take the sempahore */
++        (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++    }        
++
++    instanceStatusInfoTx[instance].pColBarState->hdcpColbarChange = False;
++    instanceStatusInfoTx[instance].pColBarState->hdcpEncryptOrT0 = True;
++    instanceStatusInfoTx[instance].pColBarState->hdcpSecureOrT0 = True;
++#else
++    (void)instance;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief BCAPS interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleBCAPS
++(
++    tmInstance_t    instance
++)
++{
++#ifndef NO_HDCP
++    Bool  bCheckRequired;
++    tmErrorCode_t  errCode;
++
++    /* Handle BCAPS interrupt immediately */
++    errCode = tmbslHdmiTxHdcpHandleBCAPS(instance);
++
++    if (errCode != TM_OK) return;
++
++    /* Wait for TDA9984 to read BKSV from B device */
++    tmbslHdmiTxSysTimerWait(instance, 10); 
++
++    /* Handle BKSV read */
++    errCode = tmbslHdmiTxHdcpHandleBKSV(instance,
++                hdcpInfoListTx[instance].hdcpBksv, &bCheckRequired);
++
++    if (errCode != TM_OK) return;
++
++    if (bCheckRequired)
++    {
++         /* check HdcpBksv against a revocation list */
++        dlHdmiTxCheckHdcpBksv (instance, hdcpInfoListTx[instance].hdcpBksv,&(hdcpInfoListTx[instance].bKsvSecure), True);
++    }
++    else
++    {
++        /* Result is always secure if no check required */
++        hdcpInfoListTx[instance].bKsvSecure = True;
++    }
++
++    /* Handle BKSV result */
++    errCode = tmbslHdmiTxHdcpHandleBKSVResult(instance,
++               hdcpInfoListTx[instance].bKsvSecure);
++
++    if (errCode != TM_OK) return;
++
++    
++#else
++    (void)instance;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief BSTATUS interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleBSTATUS
++(
++    tmInstance_t    instance
++)
++{
++#ifndef NO_HDCP
++    UInt16 bstatus = 0;
++
++	tmbslHdmiTxHdcpHandleBSTATUS(instance,
++            &bstatus);
++
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++    gIgnoreNextSha1 = False;
++#endif /*HDMI_TX_REPEATER_ISR_MODE*/
++
++    if (((bstatus & HDMITX_HDCP_BSTATUS_MAX_CASCADE_EXCEEDED) > 0)
++    ||  ((bstatus & HDMITX_HDCP_BSTATUS_MAX_DEVS_EXCEEDED) > 0))
++    {
++
++        hdcpInfoListTx[instance].hdcpDeviceDepth = (UInt8)((bstatus & HDMITX_HDCP_BSTATUS_CASCADE_DEPTH)>>8);
++
++        /* The KsvList length is limited by the smaller of the list array
++        * length and the number of devices returned in BSTATUS */
++        hdcpInfoListTx[instance].hdcpKsvDevices = 
++            (UInt8)(bstatus & HDMITX_HDCP_BSTATUS_DEVICE_COUNT);
++
++        if (HDMITX_KSV_LIST_MAX_DEVICES < hdcpInfoListTx[instance].hdcpKsvDevices)
++        {
++            hdcpInfoListTx[instance].hdcpKsvDevices = HDMITX_KSV_LIST_MAX_DEVICES;
++        }
++
++        if ((bstatus & HDMITX_HDCP_BSTATUS_MAX_CASCADE_EXCEEDED) > 0)
++        {
++            hdcpInfoListTx[instance].hdcpMaxCascExceeded = True;
++        }
++
++        if ((bstatus & HDMITX_HDCP_BSTATUS_MAX_DEVS_EXCEEDED) > 0)
++        {
++            hdcpInfoListTx[instance].hdcpMaxDevsExceeded = True;
++        }
++
++        if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_RX_KEYS_RECEIVED) == TMDL_HDMITX_EVENT_ENABLED)
++        {
++            /* Release the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++            unitTableTx[instance].pCallback(TMDL_HDMITX_RX_KEYS_RECEIVED);
++            /* Take the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++        }
++    }
++    else
++    {
++
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++        /* Call SHA_1 otherwise this ISR is missed */
++        hdcpInfoListTx[instance].hdcpDeviceDepth = (UInt8)((bstatus & HDMITX_HDCP_BSTATUS_CASCADE_DEPTH)>>8);
++
++        if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_B_STATUS) == TMDL_HDMITX_EVENT_ENABLED)
++        {
++            /* Release the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++            unitTableTx[instance].pCallback(TMDL_HDMITX_B_STATUS);
++            /* Take the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++        }
++
++
++#endif /* HDMI_TX_REPEATER_ISR_MODE */
++    }
++
++
++#else
++    (void)instance;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief SHA_1 interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleSHA_1
++(
++    tmInstance_t    instance
++)
++{
++#ifndef NO_HDCP
++    tmErrorCode_t               errCode;
++    UInt8                       indexKSVList;
++
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++    if (gIgnoreNextSha1 == False)
++    {
++       gIgnoreNextSha1 = True;
++#endif /*HDMI_TX_REPEATER_ISR_MODE*/
++    
++        errCode = tmbslHdmiTxHdcpHandleSHA_1(instance,
++                    HDMITX_KSV_LIST_MAX_DEVICES, hdcpInfoListTx[instance].hdcpKsvList,
++                    &(hdcpInfoListTx[instance].hdcpKsvDevices),&(hdcpInfoListTx[instance].hdcpDeviceDepth));
++        if (errCode != TM_OK) return;
++    
++        /* Top level or repeater HDCP mode */
++        if (unitTableTx[instance].repeaterEnable == False)
++        {
++            /* check HdcpKsvList against revocation list */
++            
++            indexKSVList = 0;
++            while (( indexKSVList <  TMDL_HDMITX_KSV_LIST_MAX_DEVICES ) &&
++                   ( indexKSVList <  hdcpInfoListTx[instance].hdcpKsvDevices ) && 
++                    (hdcpInfoListTx[instance].bKsvSecure == True)
++                  )
++            {
++                dlHdmiTxCheckHdcpBksv (instance,
++                                       &(hdcpInfoListTx[instance].hdcpKsvList[indexKSVList * TMDL_HDMITX_KSV_BYTES_PER_DEVICE]),
++                                       &(hdcpInfoListTx[instance].bKsvSecure),
++                                       False);
++                indexKSVList++;
++            }
++        }
++        else
++        {
++            hdcpInfoListTx[instance].bKsvSecure = True;
++        }
++    
++        /* Handle SHA_1 result */
++        errCode = tmbslHdmiTxHdcpHandleSHA_1Result(instance,
++                    hdcpInfoListTx[instance].bKsvSecure);
++    
++        if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_RX_KEYS_RECEIVED) == TMDL_HDMITX_EVENT_ENABLED)
++        {
++            /* Release the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++            unitTableTx[instance].pCallback(TMDL_HDMITX_RX_KEYS_RECEIVED);
++            /* Take the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++        }
++    
++        if (!hdcpInfoListTx[instance].bKsvSecure) 
++        {
++           instanceStatusInfoTx[instance].pColBarState->changeColorBarNow = True; 
++           instanceStatusInfoTx[instance].pColBarState->colorBarOn = True;
++           dlHdmiTxCheckColorBar(instance);
++        }
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++    }
++#endif /*HDMI_TX_REPEATER_ISR_MODE*/
++        
++
++#else
++    (void)instance;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief PJ interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandlePJ
++(
++    tmInstance_t    instance
++)
++{
++#ifndef NO_HDCP
++    tmbslHdmiTxHdcpHandlePJ(instance);
++#else
++    (void)instance;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief R0 interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleR0
++(
++    tmInstance_t    instance
++)
++{
++#ifndef NO_HDCP
++    tmErrorCode_t             errCode;
++    tmbslHdmiTxSinkCategory_t category;
++
++
++
++  if (hdcpInfoListTx[instance].bKsvSecure == True)
++    {
++
++        if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_HDCP_ACTIVE) == TMDL_HDMITX_EVENT_ENABLED)
++        {
++            /* Release the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++            unitTableTx[instance].pCallback(TMDL_HDMITX_HDCP_ACTIVE);
++            /* Take the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++        }
++
++        instanceStatusInfoTx[instance].pColBarState->hdcpSecureOrT0 = False;
++    }
++
++
++    errCode = tmbslHdmiTxHdcpGetSinkCategory(instance,
++                                             &category);
++    if (errCode != TM_OK) return;
++
++    if (category == HDMITX_SINK_CAT_NOT_REPEATER)
++    {
++        if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_RX_KEYS_RECEIVED) == TMDL_HDMITX_EVENT_ENABLED)
++        {
++            /* Release the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++            unitTableTx[instance].pCallback(TMDL_HDMITX_RX_KEYS_RECEIVED);
++            /* Take the sempahore */
++            (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++        }
++    }
++
++    instanceStatusInfoTx[instance].pColBarState->disableColorBarOnR0 = True;
++    instanceStatusInfoTx[instance].pColBarState->hdcpColbarChange = True;
++#else
++    (void)instance;
++#endif /* NO_HDCP */
++}
++
++/******************************************************************************
++    \brief SW_INT interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleSW_INT
++(
++    tmInstance_t    instance
++)
++{
++    DUMMY_ACCESS(instance);
++}
++
++/******************************************************************************
++    \brief RX_SENSE interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleRX_SENSE
++(
++    tmInstance_t    instance
++)
++{
++    tmErrorCode_t           errCode;
++    tmbslHdmiTxRxSense_t    rxSenseStatus;  /* Rx Sense status */
++    tmbslHdmiTxHotPlug_t    hpdStatus;      /* HPD status */
++
++    errCode = tmbslHdmiTxRxSenseGetStatus(instance,
++                                          &rxSenseStatus,False);
++
++    if (errCode != TM_OK) return;
++
++    errCode = tmbslHdmiTxHotPlugGetStatus(instance,
++                                          &hpdStatus,False);
++
++    if (errCode != TM_OK) return;
++
++//    if (hpdStatus == HDMITX_HOTPLUG_ACTIVE) 
++//    {
++        if (rxSenseStatus == HDMITX_RX_SENSE_ACTIVE)
++        {
++            if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_RX_DEVICE_ACTIVE) == TMDL_HDMITX_EVENT_ENABLED)
++            {
++                /* Release the sempahore */
++                (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++                unitTableTx[instance].pCallback(TMDL_HDMITX_RX_DEVICE_ACTIVE);
++                /* Take the sempahore */
++				(void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++            }
++        }
++        else if (rxSenseStatus == HDMITX_RX_SENSE_INACTIVE)
++        {
++
++            if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_RX_DEVICE_INACTIVE) == TMDL_HDMITX_EVENT_ENABLED)
++            {
++                /* Release the sempahore */
++                (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++                unitTableTx[instance].pCallback(TMDL_HDMITX_RX_DEVICE_INACTIVE);
++                /* Take the sempahore */
++                (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++            }
++
++#ifndef NO_HDCP
++            if (unitTableTx[instance].hdcpEnable == True)
++            {
++                /* Release the sempahore */
++                (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++                /* Switch off HDCP */
++                (void)tmdlHdmiTxSetHdcp(instance, False);
++                /* Take the sempahore */
++                (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++            }
++#endif /* NO_HDCP */
++        }
++//    }
++}
++
++/******************************************************************************
++    \brief EDID_READ interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleEDID_READ
++(
++    tmInstance_t    instance
++)
++{
++    tmErrorCode_t           errCode;
++    UInt8                   edidStatus = TMDL_HDMITX_EDID_NOT_READ;
++
++    /* Get the edid status and read the connected device's EDID */
++
++    /* Get Edid status */
++    errCode = tmbslHdmiTxEdidGetStatus(instance,
++                &edidStatus);
++
++    if (errCode != TM_OK)
++    {
++        /* Set state machine to Plugged */
++        dlHdmiTxSetState(instance, STATE_PLUGGED);
++        return;
++    }
++
++    /* Has hot plug changed to Active? */
++    if ((edidStatus == TMDL_HDMITX_EDID_READ) ||
++        (edidStatus == TMDL_HDMITX_EDID_ERROR_CHK))
++    {
++        /* Set state machine to EDID available */
++       dlHdmiTxSetState(instance, STATE_EDID_AVAILABLE);
++    }
++    else
++    {
++        /* Set state machine to Plugged */
++        dlHdmiTxSetState(instance, STATE_PLUGGED);
++    }
++    
++
++    if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_EDID_RECEIVED) == TMDL_HDMITX_EVENT_ENABLED)
++    {
++       /* Release the sempahore */
++       (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++       unitTableTx[instance].pCallback(TMDL_HDMITX_EDID_RECEIVED);
++       /* Take the sempahore */
++       (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++    }
++
++    
++}
++
++/******************************************************************************
++    \brief VS_RPT interrupt callback.
++
++    \param instance     Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxHandleVS_RPT
++(
++    tmInstance_t    instance
++)
++{
++    if (dlHdmiTxGetEventStatus(instance, TMDL_HDMITX_VS_RPT_RECEIVED) == TMDL_HDMITX_EVENT_ENABLED)
++    {
++        /* Release the sempahore */
++        (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]);
++        unitTableTx[instance].pCallback(TMDL_HDMITX_VS_RPT_RECEIVED);
++        /* Take the sempahore */
++        (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]);
++    }        
++}
++
++/******************************************************************************
++    \brief dlHdmiTxConvertDTDtoCEA_640HAP .
++
++    \param  pDTDescriptors      DTD to convert.
++            pictureAspectRatio  aspect ratio of DTD
++            formatInterlaced    DTD Interlaced or progressif
++
++    \return NA.
++
++******************************************************************************/
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_640HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors
++)
++{
++    tmdlHdmiTxVidFmt_t          codeCEA;
++
++    switch (pDTDescriptors->vActiveLines)
++    {
++        case 480:
++            codeCEA = TMDL_HDMITX_VFMT_01_640x480p_60Hz;
++        break;
++
++        default:
++            /* Not a valid format */
++            codeCEA = TMDL_HDMITX_VFMT_NULL;
++        break;
++    }
++
++    return codeCEA;
++
++}
++
++/******************************************************************************
++    \brief dlHdmiTxConvertDTDtoCEA_720HAP .
++
++    \param  pDTDescriptors      DTD to convert.
++            pictureAspectRatio  aspect ratio of DTD
++            formatInterlaced    DTD Interlaced or progressif
++
++    \return NA.
++
++******************************************************************************/
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_720HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    tmdlHdmiTxPictAspectRatio_t     pictureAspectRatio
++)
++{
++    tmdlHdmiTxVidFmt_t          codeCEA;
++
++    switch (pDTDescriptors->vActiveLines)
++    {
++        case 480:
++            if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++            {
++                codeCEA = TMDL_HDMITX_VFMT_02_720x480p_60Hz;
++            }
++            else
++            {
++                codeCEA = TMDL_HDMITX_VFMT_03_720x480p_60Hz;
++            }
++        break;
++
++        case 576:
++            if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++            {
++                codeCEA = TMDL_HDMITX_VFMT_17_720x576p_50Hz;
++            }
++            else
++            {
++                codeCEA = TMDL_HDMITX_VFMT_18_720x576p_50Hz;
++            }
++        break;
++
++        default:
++            /* Not a valid format */
++            codeCEA = TMDL_HDMITX_VFMT_NULL;
++        break;
++    }
++
++    return codeCEA;
++
++}
++/******************************************************************************
++    \brief dlHdmiTxConvertDTDtoCEA_1280HAP .
++
++    \param  pDTDescriptors      DTD to convert.
++            pictureAspectRatio  aspect ratio of DTD
++            formatInterlaced    DTD Interlaced or progressif
++
++    \return NA.
++
++******************************************************************************/
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_1280HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors
++)
++{
++    tmdlHdmiTxVidFmt_t          codeCEA;
++
++    switch (pDTDescriptors->vActiveLines)
++    {
++        case 720:
++            switch (pDTDescriptors->hBlankPixels)
++            {
++                case 370: 
++                    codeCEA = TMDL_HDMITX_VFMT_04_1280x720p_60Hz;
++                break;
++
++                case 700: 
++                    codeCEA = TMDL_HDMITX_VFMT_19_1280x720p_50Hz;
++                break;
++
++                default:
++                    /* Not a valid format */
++                    codeCEA = TMDL_HDMITX_VFMT_NULL;
++                break;
++            }
++        break;
++
++        default:
++            /* Not a valid format */
++            codeCEA = TMDL_HDMITX_VFMT_NULL;
++        break;
++    }
++
++
++    return codeCEA;
++}
++
++/******************************************************************************
++    \brief dlHdmiTxConvertDTDtoCEA_1920HAP .
++
++    \param  pDTDescriptors      DTD to convert.
++            pictureAspectRatio  aspect ratio of DTD
++            formatInterlaced    DTD Interlaced or progressif
++
++    \return NA.
++
++******************************************************************************/
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_1920HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    Bool                            formatInterlaced
++
++)
++{
++    tmdlHdmiTxVidFmt_t          codeCEA;
++
++    switch (pDTDescriptors->hBlankPixels)
++    {
++        case 280:
++            if (formatInterlaced)
++            {
++                codeCEA = TMDL_HDMITX_VFMT_05_1920x1080i_60Hz;
++            }
++            else
++            {
++                if ( pDTDescriptors->pixelClock == 14850 )
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_16_1920x1080p_60Hz;
++                }
++                else
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_34_1920x1080p_30Hz;
++                }
++            }
++        break;
++
++        case 720: 
++            if (formatInterlaced)
++            {
++                codeCEA = TMDL_HDMITX_VFMT_20_1920x1080i_50Hz;
++            }
++            else
++            {
++                switch (pDTDescriptors->pixelClock)
++                {
++                    case 14850:
++                        codeCEA = TMDL_HDMITX_VFMT_31_1920x1080p_50Hz;
++                    break;
++
++                    case 7425:
++                        codeCEA = TMDL_HDMITX_VFMT_33_1920x1080p_25Hz;
++                    break;
++                    default:
++                        /* Not a valid format */
++                        codeCEA = TMDL_HDMITX_VFMT_NULL;
++                    break;
++                }
++            }
++        break;
++
++        case 830: 
++            codeCEA = TMDL_HDMITX_VFMT_32_1920x1080p_24Hz;
++        break;
++
++        default:
++            /* Not a valid format */
++            codeCEA = TMDL_HDMITX_VFMT_NULL;
++        break;
++    }
++           
++
++    return codeCEA;
++}
++
++/******************************************************************************
++    \brief dlHdmiTxConvertDTDtoCEA_1440HAP .
++
++    \param  pDTDescriptors      DTD to convert.
++            pictureAspectRatio  aspect ratio of DTD
++            formatInterlaced    DTD Interlaced or progressif
++
++    \return NA.
++
++******************************************************************************/
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_1440HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    tmdlHdmiTxPictAspectRatio_t     pictureAspectRatio,
++    Bool                            formatInterlaced
++
++)
++{
++    tmdlHdmiTxVidFmt_t          codeCEA;
++
++    switch (pDTDescriptors->vActiveLines)
++    {
++        case 240:
++            if (formatInterlaced)
++            {
++                if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_06_720x480i_60Hz;
++                }
++                else
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_07_720x480i_60Hz;
++                }
++            }
++            else
++            {
++                if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_08_720x240p_60Hz;
++                }
++                else
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_09_720x240p_60Hz;
++                }
++            }
++        break;
++
++        case 288:
++            if (formatInterlaced)
++            {
++                if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_21_720x576i_50Hz;
++                }
++                else
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_22_720x576i_50Hz;
++                }
++            }
++            else
++            {
++                if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_23_720x288p_50Hz;
++                }
++                else
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_24_720x288p_50Hz;
++                }
++            }
++        break;
++
++        case 480:
++            if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++            {
++                codeCEA = TMDL_HDMITX_VFMT_14_1440x480p_60Hz;
++            }
++            else
++            {
++                codeCEA = TMDL_HDMITX_VFMT_15_1440x480p_60Hz;
++            }
++        break;
++
++        case 576:
++            if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++            {
++                codeCEA = TMDL_HDMITX_VFMT_29_1440x576p_50Hz;
++            }
++            else
++            {
++                codeCEA = TMDL_HDMITX_VFMT_30_1440x576p_50Hz;
++            }
++        break;
++
++        default:
++            /* Not a valid format */
++            codeCEA = TMDL_HDMITX_VFMT_NULL;
++        break;
++    }
++
++    return codeCEA;
++}
++
++/******************************************************************************
++    \brief dlHdmiTxConvertDTDtoCEA_2880HAP .
++
++    \param  pDTDescriptors      DTD to convert.
++            pictureAspectRatio  aspect ratio of DTD
++            formatInterlaced    DTD Interlaced or progressif
++
++    \return NA.
++
++******************************************************************************/
++static tmdlHdmiTxVidFmt_t dlHdmiTxConvertDTDtoCEA_2880HAP
++(
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    tmdlHdmiTxPictAspectRatio_t     pictureAspectRatio,
++    Bool                            formatInterlaced
++)
++{
++    tmdlHdmiTxVidFmt_t          codeCEA;
++
++    switch (pDTDescriptors->vActiveLines)
++    {
++        case 240:
++            if (formatInterlaced)
++            {
++                if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_10_720x480i_60Hz;
++                }
++                else
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_11_720x480i_60Hz;
++                }
++            }
++            else
++            {
++                if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_12_720x240p_60Hz;
++                }
++                else
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_13_720x240p_60Hz;
++                }
++            }
++        break;
++
++        case 288:
++            if (formatInterlaced)
++            {
++                if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_25_720x576i_50Hz;
++                }
++                else
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_26_720x576i_50Hz;
++                }
++            }
++            else
++            {
++                if (pictureAspectRatio == TMDL_HDMITX_P_ASPECT_RATIO_4_3)
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_27_720x288p_50Hz;
++                }
++                else
++                {
++                    codeCEA = TMDL_HDMITX_VFMT_28_720x288p_50Hz;
++                }
++            }
++        break;
++
++        default:
++            /* Not a valid format */
++            codeCEA = TMDL_HDMITX_VFMT_NULL;
++        break;
++    }
++
++    return codeCEA;
++}
++
++/******************************************************************************
++    \brief EdidGetDTD .
++
++    \param .
++
++    \return NA.
++
++******************************************************************************/
++tmErrorCode_t dlHdmiTxEdidGetDTD
++(
++    tmInstance_t                    instance,
++    tmdlHdmiTxEdidVideoTimings_t    *pDTDescriptors,
++    UInt8                           maxDTDesc,
++    UInt8                           *pWrittenDTDesc
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check the current state */   
++    RETIF( dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    /* Get detailled descriptors from EDID, return TMDL_ERR_DLHDMITX_NO_RESOURCES if EDID are not read */
++    RETIF((errCode = tmbslHdmiTxEdidGetDetailedTimingDescriptors(
++                        instance, (tmbslHdmiTxEdidDtd_t *)pDTDescriptors, maxDTDesc, pWrittenDTDesc) ) != TM_OK, errCode);
++
++    return TM_OK;
++}
++
++
++/******************************************************************************
++    \brief Command processing task, dedicated to unit/instance 0.
++
++    \param NA.
++
++    \return NA.
++
++******************************************************************************/
++
++#ifndef TMFL_NO_RTOS
++static void CommandTaskUnit0()
++{
++    UInt8                   command;
++    Bool                    loop = True;    /* Just to avoid compiler warning */
++    tmErrorCode_t           err = TM_OK;
++
++    while(loop)
++    {
++        tmdlHdmiTxIWQueueReceive(unitTableTx[0].queueHandle, &command);
++
++        /* Take the sempahore */
++        (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[0]);
++
++        /* Clear T0 flag before polling for interrupts */
++        instanceStatusInfoTx[0].pColBarState->hdcpSecureOrT0 = False;
++
++        if (gI2CDebugAccessesEnabled == True)
++        {
++
++            err = tmbslHdmiTxHwHandleInterrupt(0);
++        
++            if ((err == TMBSL_ERR_HDMI_I2C_WRITE) || (err == TMBSL_ERR_HDMI_I2C_READ))
++            {
++
++                unitTableTx[0].pCallback(TMDL_HDMITX_DEBUG_EVENT_1);
++            }
++
++        }/* (gI2CDebugAccessesEnabled == True) */
++
++        /* Enable interrupts for Tx (interrupts are disabled in the HandleInterrupt function) */
++        tmdlHdmiTxIWEnableInterrupts(TMDL_HDMI_IW_TX_1);
++
++        /* Release the sempahore */
++        (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[0]);
++    };
++}
++#endif /* TMFL_NO_RTOS */
++
++/******************************************************************************
++    \brief Hdcp check task, dedicated to unit/instance 0.
++
++    \param NA.
++
++    \return NA.
++
++******************************************************************************/
++#ifndef TMFL_NO_RTOS
++static void HdcpTaskUnit0()
++{
++    Bool loop = True;    /* Just to avoid compiler warning */
++    Bool featureSupported;
++
++    tmbslHdmiTxHwGetCapabilities(0, 
++            HDMITX_FEATURE_HW_HDCP, &featureSupported);
++
++#ifndef NO_HDCP
++    while(loop)
++    {
++        (void)tmdlHdmiTxIWWait(35);
++		
++		/* Take the sempahore */
++        (void)tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[0]);
++
++        if (gI2CDebugAccessesEnabled == True)
++        {
++
++            dlHdmiTxCheckColorBar(0);
++            dlHdmiTxCheckHdcpColorBar(0);
++
++            if (featureSupported == True)
++            {
++                tmbslHdmiTxHdcpCheck(0,35, (tmbslHdmiTxHdcpCheck_t *)&(hdcpInfoListTx[0].hdcpCheckState));
++            }
++
++        } /*  gI2CDebugAccessesEnabled == True*/
++
++        /* Release the sempahore */
++        (void)tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[0]);
++    };
++#else
++    (void)loop;
++#endif /* NO_HDCP */
++}
++#endif /* TMFL_NO_RTOS */
++
++#ifndef NO_HDCP
++/******************************************************************************
++    \brief Check hdcp state to manage color bar.
++
++    \param instance Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxCheckHdcpColorBar
++(
++    tmInstance_t instance
++)
++{
++    /* Use HDCP check result to control HDCP colour bars */
++    if ( (instanceStatusInfoTx[instance].pColBarState->disableColorBarOnR0 == True)
++        && (instanceStatusInfoTx[instance].pColBarState->hdcpColbarChange == True)
++        && (instanceStatusInfoTx[instance].pColBarState->hdcpSecureOrT0 == False) )
++    {
++        /* Remove test pattern once if Authenticated with no error interrupts */ 
++        if (instanceStatusInfoTx[instance].pColBarState->colorBarOn != False)
++        {
++            instanceStatusInfoTx[instance].pColBarState->colorBarOn = False;
++            instanceStatusInfoTx[instance].pColBarState->changeColorBarNow = True;
++
++            if (unitTableTx[instance].simplayHd == True) {
++
++           /* Mute or Un-mute the audio output */
++           tmbslHdmiTxAudioOutSetMute(instance,(tmbslHdmiTxaMute_t)HDMITX_AMUTE_OFF);
++
++           /* Store current audio mute status */
++           instanceStatusInfoTx[instance].pAudioInfo->audioMuteState = False;
++            }
++
++
++        }
++        /* Reset state flags */
++        instanceStatusInfoTx[instance].pColBarState->hdcpColbarChange = False;
++        instanceStatusInfoTx[instance].pColBarState->hdcpSecureOrT0 = True;
++
++#ifdef TMFL_TDA19989
++        instanceStatusInfoTx[instance].pColBarState->disableColorBarOnR0 = False;
++#endif /* TMFL_TDA19989 */
++
++
++
++    }
++    
++    if ( (instanceStatusInfoTx[instance].pColBarState->hdcpEncryptOrT0 == True)
++        && (instanceStatusInfoTx[instance].pColBarState->inOutFirstSetDone == True))
++    {
++        /* Set test pattern once if not Authenticated, to mask HDCP failure */ 
++        if (instanceStatusInfoTx[instance].pColBarState->colorBarOn != True)
++        {
++            instanceStatusInfoTx[instance].pColBarState->colorBarOn = True;
++            instanceStatusInfoTx[instance].pColBarState->changeColorBarNow = True;
++
++            if (unitTableTx[instance].simplayHd == True) {
++
++           /* Mute or Un-mute the audio output */
++           tmbslHdmiTxAudioOutSetMute(instance,(tmbslHdmiTxaMute_t)HDMITX_AMUTE_ON);
++
++           /* Store current audio mute status */
++           instanceStatusInfoTx[instance].pAudioInfo->audioMuteState = True;
++            }
++
++        }
++        /* Reset state flag */
++        instanceStatusInfoTx[instance].pColBarState->hdcpEncryptOrT0 = False;
++    }
++}
++#endif
++
++#ifndef NO_HDCP
++/******************************************************************************
++    \brief Show color bars or restore the last video format.
++
++    \param instance Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxCheckColorBar
++(
++    tmInstance_t instance
++)
++{
++    if ( (instanceStatusInfoTx[instance].pColBarState->inOutFirstSetDone == True)
++			&& (instanceStatusInfoTx[instance].pColBarState->changeColorBarNow == True) )
++    {
++        instanceStatusInfoTx[instance].pColBarState->changeColorBarNow = False;
++
++        if (unitTableTx[instance].simplayHd == True)
++        {
++            if (instanceStatusInfoTx[instance].pColBarState->colorBarOn == True)
++            {
++                /* Set service mode colour bar on/off (also used as HDCP logo pattern) */
++                (void)dlHdmiTxSetTestPatternOn(instance, instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format,
++                    instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.mode, 
++                    gtmdlHdmiTxDriverConfigTable[instance].pattern);
++            }
++            else
++            {
++                /* Restore last output format and mode */
++                (void)dlHdmiTxSetTestPatternOff(instance, 
++                        instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.format,
++                        instanceStatusInfoTx[instance].pVideoInfo->videoOutConfig.mode);
++            }
++        }
++    }
++}
++#endif
++
++#ifndef NO_HDCP
++/******************************************************************************
++    \brief Get hdcp seed.
++
++    \param instance Instance identifier.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxFindHdcpSeed
++(
++    tmInstance_t instance
++)
++{
++#if HDCP_SEED_DEFAULT == HDCP_SEED_NULL
++    UInt8 otp[3];
++#endif
++
++    /* If no seed is coded in this file then find it somewhere else */
++#if HDCP_SEED_DEFAULT == HDCP_SEED_NULL
++    /* See if a seed table has been programmed in flash */
++    if (kSeedTable[0][0] != 0xFFFF)
++    {
++        /* Read OTP LSB at address 0x00 and try to match in flash table */
++        if ( (tmbslHdmiTxHdcpGetOtp(instance,
++				0x00, otp)) == TM_OK)
++        {
++            int i;
++            for (i = 0; i < SEED_TABLE_LEN; i++)
++            {
++                if (kSeedTable[i][0] == otp[2]) /* OTP_DATA_LSB */
++                {
++                    /* Found seed! */
++                    gtmdlHdmiTxDriverConfigTable[instance].keySeed = kSeedTable[i][1];
++                    break;
++                }
++            }
++        }
++    }
++#endif  /* HDCP_SEED_DEFAULT != HDCP_SEED_NULL */
++
++    /* Initialise the TDA9984 HDCP keys */
++    if (gtmdlHdmiTxDriverConfigTable[instance].keySeed != HDCP_SEED_NULL)
++    {
++		/* Initialise the HDMI Transmitter HDCP keys */
++        tmbslHdmiTxHdcpDownloadKeys(instance,
++				gtmdlHdmiTxDriverConfigTable[instance].keySeed, HDMITX_HDCP_DECRYPT_ENABLE);
++    }
++}
++#endif /* NO_HDCP */
++
++/******************************************************************************
++    \brief Set the state of the state machine.
++
++    \param instance Instance identifier.
++    \param state    State of the state machine.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxSetState
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxDriverState_t state
++)
++{
++    /* Set the state */
++    unitTableTx[instance].state = state;
++}
++
++/******************************************************************************
++    \brief Get the state of the state machine.
++
++    \param instance Instance identifier.
++
++    \return tmdlHdmiTxDriverState_t Current State of the state machine.
++
++******************************************************************************/
++tmdlHdmiTxDriverState_t dlHdmiTxGetState
++(
++    tmInstance_t instance
++)
++{
++    tmdlHdmiTxDriverState_t state;
++   
++    /* Get the state */
++    state = unitTableTx[instance].state;
++
++    return (state);   
++}
++
++/******************************************************************************
++    \brief Get the state of the event (enabled or disabled).
++
++    \param instance Instance identifier.
++    \param event    Event to give the state.
++
++    \return NA.
++
++******************************************************************************/
++static tmdlHdmiTxEventStatus_t dlHdmiTxGetEventStatus
++(
++    tmInstance_t        instance,
++    tmdlHdmiTxEvent_t   event
++)
++{
++    tmdlHdmiTxEventStatus_t   eventStatus;
++   
++    /* Get the event status */
++    eventStatus = instanceStatusInfoTx[instance].pEventState[event].status;
++
++    return (eventStatus);
++}
++
++/******************************************************************************
++    \brief Caculation of aspect ratio.
++
++    \param HImageSize Horizontal image size.
++    \param VImageSize Vertical image size.
++
++    \return NA.
++
++******************************************************************************/
++static tmdlHdmiTxPictAspectRatio_t dlHdmiTxCalcAspectRatio (
++    UInt16    HImageSize,
++    UInt16    VImageSize
++)
++{
++    tmdlHdmiTxPictAspectRatio_t    pictureAspectRatio;
++    UInt16                         calcPictureAspectRatio;
++
++    /* Define picture Aspect Ratio                                          */
++    /* 16/9 = 1.77777 so the result approach is 2                           */
++    /* 4/3 = 1.33333 so the result approach is 1                            */
++    /*  operation :                                                         */
++    /* ImageSize + (vImageSize/2)                                           */
++    /* -------------------------- > vImageSize     ->True 16/9 False 4/3    */
++    /*           2                                                          */
++
++    calcPictureAspectRatio = ((UInt16)(HImageSize + ((VImageSize)>>1)))>>1;
++
++    if(calcPictureAspectRatio > VImageSize)
++    {
++        pictureAspectRatio = TMDL_HDMITX_P_ASPECT_RATIO_16_9;
++    }
++    else
++    {
++        pictureAspectRatio = TMDL_HDMITX_P_ASPECT_RATIO_4_3;
++    }
++
++    return pictureAspectRatio;
++
++}
++
++#ifndef NO_HDCP
++/******************************************************************************
++    \brief dlHdmiTxCheckHdcpBksv .
++
++    \param pHdcpBksvTested  ksv To test.
++    \param pbBksvSecure     Test result.
++    \param bBigEndian       ksv provide by hardware are in little or big endian.
++
++    \return NA.
++
++******************************************************************************/
++static void dlHdmiTxCheckHdcpBksv
++(
++    tmInstance_t    instance,
++    UInt8 *         pHdcpBksvTested,
++    Bool  *         pbBksvSecure,
++    Bool            bBigEndian
++)
++{
++
++    UInt32 NbInRevocationList;
++
++    NbInRevocationList = 0;
++
++    /* CBE: force secure, otherwise we will not look at anything */
++    *pbBksvSecure = True;
++
++    if ((unitTableTx[instance].revocationList.pList != Null) && (unitTableTx[instance].revocationList.length > 0))
++    {
++        while ((*pbBksvSecure == True) && (NbInRevocationList < unitTableTx[instance].revocationList.length))
++        {
++            if (bBigEndian)
++            {
++                if ((pHdcpBksvTested[0] == unitTableTx[instance].revocationList.pList[NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE])
++                    &&
++                    (pHdcpBksvTested[1] == unitTableTx[instance].revocationList.pList[1 + (NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE)])
++                    &&
++                    (pHdcpBksvTested[2] == unitTableTx[instance].revocationList.pList[2 + (NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE)])
++                    &&
++                    (pHdcpBksvTested[3] == unitTableTx[instance].revocationList.pList[3 + (NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE)])
++                    &&
++                    (pHdcpBksvTested[4] == unitTableTx[instance].revocationList.pList[4 + (NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE)])
++                    )
++                {
++                    *pbBksvSecure = False;
++                }
++            }
++            else
++            {
++                if ((pHdcpBksvTested[4] == unitTableTx[instance].revocationList.pList[NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE])
++                    &&
++                    (pHdcpBksvTested[3] == unitTableTx[instance].revocationList.pList[1 + (NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE)])
++                    &&
++                    (pHdcpBksvTested[2] == unitTableTx[instance].revocationList.pList[2 + (NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE)])
++                    &&
++                    (pHdcpBksvTested[1] == unitTableTx[instance].revocationList.pList[3 + (NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE)])
++                    &&
++                    (pHdcpBksvTested[0] == unitTableTx[instance].revocationList.pList[4 + (NbInRevocationList * HDMITX_KSV_BYTES_PER_DEVICE)])
++                    )
++                {
++                    *pbBksvSecure = False;
++                }
++            }
++            NbInRevocationList++;
++        }
++
++    }
++
++
++}
++#endif
++
++/******************************************************************************
++    \brief dlHdmiTxCalcVidFmtIndex.
++
++    \param vidFmt  video format.
++
++    \return table index.
++
++******************************************************************************/
++static tmdlHdmiTxVidFmt_t dlHdmiTxCalcVidFmtIndex(tmdlHdmiTxVidFmt_t vidFmt)
++{
++    tmdlHdmiTxVidFmt_t vidFmtIndex = vidFmt;
++    
++    /* Hanlde VIC or table index discontinuity */
++    if((vidFmt >= TMDL_HDMITX_VFMT_60_1280x720p_24Hz) && (vidFmt <= TMDL_HDMITX_VFMT_62_1280x720p_30Hz))
++    {
++        vidFmtIndex = (tmdlHdmiTxVidFmt_t)(TMDL_HDMITX_VFMT_INDEX_60_1280x720p_24Hz + (vidFmt - TMDL_HDMITX_VFMT_60_1280x720p_24Hz));
++    }
++#ifdef FORMAT_PC
++    else if (vidFmt >= TMDL_HDMITX_VFMT_PC_MIN)
++    {
++        vidFmtIndex = (tmdlHdmiTxVidFmt_t)(TMDL_HDMITX_VFMT_TV_NUM + (vidFmt - TMDL_HDMITX_VFMT_PC_MIN));
++    }
++#endif /* FORMAT_PC */
++    return(vidFmtIndex);
++}
++
++
++tmErrorCode_t tmdlHdmiTxDebugEnableI2CAccesses ( tmInstance_t instance,
++                                                 Bool         enableI2C)
++{
++    tmErrorCode_t   errCode = TM_OK;
++
++    /* Check if instance number is in range */
++    if( (instance < 0) || (instance >= MAX_UNITS) ) 
++    {
++        errCode = TMDL_ERR_DLHDMITX_BAD_INSTANCE;
++        return errCode;
++    }
++
++    if (enableI2C == True)
++    {
++        errCode = tmbslDebugWriteFakeRegPage(instance);
++        gI2CDebugAccessesEnabled = True;
++    } 
++    else
++    {
++        gI2CDebugAccessesEnabled = False;
++    }
++
++
++    return errCode;
++
++} /* tmdlHdmiTxDebugManageI2CAccesses */
++
++/*****************************************************************************/
++/**
++    \brief Retreives current HDCP link status. This function is typically used
++           when an "HDCP INACTIVE" event is received to know why HDCP 
++           is INACTIVE.
++
++    \param instance    Instance identifier.
++    \param pHdcpStatus Pointer to the enum describing the status.
++    \param pRawStatus  Pointer to the byte with the raw error code from HW.
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_BAD_HANDLE: the handle number is wrong
++            - TMDL_ERR_DLHDMITX_BAD_PARAMETER: a parameter is invalid or out
++              of range
++            - TMDL_ERR_DLHDMITX_NOT_INITIALIZED: the transmitter is not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetHdcpFailStatus
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxHdcpStatus_t *pHdcpStatus,
++    UInt8                  *pRawStatus
++)
++{
++    tmErrorCode_t   errCode = TM_OK;
++
++#ifndef NO_HDCP
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++    RETIF(pHdcpStatus == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++    RETIF(pRawStatus == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    *pRawStatus  = hdcpInfoListTx[instance].hdcpErrorState;
++
++    switch (hdcpInfoListTx[instance].hdcpErrorState) 
++    {
++
++    case 0:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_OK;
++        break;
++
++    case 0x02:
++    case 0x03:
++    case 0x04:
++    case 0x05:
++    case 0x06:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_BKSV_RCV_FAIL;
++        break;
++
++    case 0x08:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_BKSV_CHECK_FAIL;
++        break;
++
++    case 0x0C:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_BCAPS_RCV_FAIL;
++        break;
++
++    case 0x0F:
++    case 0x10:
++    case 0x11:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_AKSV_SEND_FAIL;
++        break;
++
++    case 0x23:
++    case 0x24:
++    case 0x25:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_R0_RCV_FAIL;
++        break;
++
++    case 0x26:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_R0_CHECK_FAIL;
++        break;
++
++    case 0x27:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_BKSV_NOT_SECURE;
++        break;
++
++    case 0x2B:
++    case 0x2C:
++    case 0x2D:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RI_RCV_FAIL;
++        break;
++
++    case 0x77:
++    case 0x78:
++    case 0x79:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RPT_RI_RCV_FAIL;
++        break;
++
++    case 0x2E:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RI_CHECK_FAIL;
++    break;
++
++    case 0x7A:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RPT_RI_CHECK_FAIL;
++        break;
++
++    case 0x66:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RPT_BCAPS_RCV_FAIL;
++        break;
++
++    case 0x67:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RPT_BCAPS_READY_TIMEOUT;
++        break;
++
++    case 0x6A:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RPT_V_RCV_FAIL;
++        break;
++
++    case 0x6C:
++    case 0x6D:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RPT_BSTATUS_RCV_FAIL;
++        break;
++
++    case 0x6F:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RPT_KSVLIST_RCV_FAIL;
++        break;
++
++    case 0x74:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_RPT_KSVLIST_NOT_SECURE;
++        break;
++
++    default:
++        *pHdcpStatus = TMDL_HDMITX_HDCP_UNKNOWN_STATUS;
++        break;
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++#else
++       (void)instance; /* Remove compiler warning */
++#endif /* NO_HDCP */
++
++    return errCode;
++}
++
++
++tmErrorCode_t tmdlHdmiTxGetEdidLatencyInfo
++(
++    tmInstance_t                instance,
++    tmdlHdmiTxEdidLatency_t    *pLatency
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check pointer is Null */
++    RETIF( pLatency == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetLatencyInfo(instance, (tmbslHdmiTxEdidLatency_t *) pLatency) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++} /* tmdlHdmiTxGetEdidLatencyInfo */
++
++/******************************************************************************
++    \brief Retrieves additional data from receiver's EDID VSDB. This function 
++           parses the EDID of Rx device to get the relevant data.
++           This function is synchronous.
++           This function is not ISR friendly.
++
++    \param instance             Instance identifier.
++    \param pExtraVsdbData       Pointer to the structure of additional VSDB data 
++    
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_INSTANCE: the instance number is wrong or
++              out of range
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++            - TMDL_ERR_DLHDMITX_INVALID_STATE: the state is invalid for
++              the function
++            - TMBSL_ERR_HDMI_BAD_PARAMETER: a parameter was out of range
++            - TMBSL_ERR_HDMI_BAD_UNIT_NUMBER: bad transmitter unit number
++            - TMBSL_ERR_HDMI_RESOURCE_NOT_AVAILABLE : EDID not read
++            - TMBSL_ERR_HDMI_NOT_INITIALIZED: transmitter not initialized
++
++******************************************************************************/
++tmErrorCode_t tmdlHdmiTxGetEdidExtraVsdbData
++(
++    tmInstance_t                     instance,
++    tmdlHdmiTxEdidExtraVsdbData_t    **pExtraVsdbData
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    /* Check pointer is Null */
++    RETIF(pExtraVsdbData == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Check the current state */   
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        dlHdmiTxGetState(instance) != STATE_EDID_AVAILABLE, TMDL_ERR_DLHDMITX_INVALID_STATE)
++
++    RETIF_SEM(dlHdmiTxItSemaphore[instance], 
++        (errCode = tmbslHdmiTxEdidGetExtraVsdbData(instance, (tmbslHdmiTxEdidExtraVsdbData_t **)pExtraVsdbData) ) != TM_OK, errCode)
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++} /* tmdlHdmiTxGetEdidExtraVsdbData */
++
++
++tmErrorCode_t tmdlHdmiTxGetHPDStatus
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxHotPlug_t *   pHPDStatus
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    RETIF( pHPDStatus== Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Get the HPD status from BSL driver */
++        errCode = tmbslHdmiTxHotPlugGetStatus(instance,(tmbslHdmiTxHotPlug_t *)pHPDStatus,True);
++
++    if (errCode == TM_OK) {
++        /* do nothing */
++    }
++    else {
++        *pHPDStatus = TMDL_HDMITX_HOTPLUG_INVALID;
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++
++} /* tmdlHdmiTxGetHPDStatus */
++
++
++
++tmErrorCode_t tmdlHdmiTxGetRXSenseStatus
++(
++    tmInstance_t            instance,
++    tmdlHdmiTxRxSense_t *   pRXSenseStatus
++)
++{
++    tmErrorCode_t   errCode;
++
++    /* Check if instance number is in range */
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    RETIF( pRXSenseStatus== Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++
++    /* Take the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    /* Get the RXS sense status from BSL driver */
++        errCode = tmbslHdmiTxRxSenseGetStatus(instance,( tmbslHdmiTxRxSense_t*)pRXSenseStatus,True);
++
++    if (errCode == TM_OK) {
++        /* do nothing */
++    }
++    else {
++        *pRXSenseStatus = TMDL_HDMITX_RX_SENSE_INVALID;
++    }
++
++    /* Release the sempahore */
++    RETIF( (errCode = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCode)
++
++    return TM_OK;
++
++} /* tmdlHdmiTxGetRXSenseStatus */
++
++
++/******************************************************************************
++    \brief Mute or unmute the TMDS outputs.
++
++    \param instance         Instance identifier.
++    \param muteTmdsOut      Mute or unmute indication.
++
++    \return NA.
++    
++******************************************************************************/   
++tmErrorCode_t tmdlHdmiTxTmdsSetOutputsMute
++(
++    tmInstance_t            instance,
++    Bool                    muteTmdsOut
++)
++{
++    tmErrorCode_t           errCode;
++    tmErrorCode_t           errCodeSem;
++    tmbslHdmiTxTmdsOut_t    tmdsOut;
++    
++    RETIF((instance < 0) || (instance >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_INSTANCE)
++
++    if (muteTmdsOut)
++        tmdsOut = HDMITX_TMDSOUT_FORCED0;       // forced 0 outputs
++    else
++        tmdsOut = HDMITX_TMDSOUT_NORMAL;        // normal outputs
++
++    /* Take the sempahore */
++    RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreP(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCodeSem)
++
++    errCode = tmbslHdmiTxTmdsSetOutputs (instance, tmdsOut);
++
++    /* Release the sempahore */
++    RETIF( (errCodeSem = tmdlHdmiTxIWSemaphoreV(dlHdmiTxItSemaphore[instance]) ) != TM_OK, errCodeSem)
++
++
++    return errCode;
++}
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.c b/drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.c
+new file mode 100755
+index 0000000..fc6886d
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.c
+@@ -0,0 +1,342 @@
++/**
++ * Copyright (C) 2006 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx_local.c
++ *
++ * \version       Revision: 1
++ *
++ * \date          Date: 21/02/08
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * HDMI Tx Driver - FRS.doc,
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   History:       tmdlHdmiTx_local.c
++ *
++ * *****************  Version 1  *****************
++ * User: G. Burnouf Date: 21/02/08
++ * Updated in $/Source/tmdlHdmiTx/src
++ * initial version
++ 
++   \endverbatim
++ *
++*/
++
++/*============================================================================*/
++/*                             INCLUDE FILES                                  */
++/*============================================================================*/
++#include "tmdlHdmiTx_local.h"
++#include "tmdlHdmiTx_cfg.h"
++#include "tmdlHdmiTx.h"
++
++/*============================================================================*/
++/*                          TYPES DECLARATIONS                                */
++/*============================================================================*/
++
++typedef struct _dlHdmiTxResolution_t {
++    tmdlHdmiTxVidFmt_t          resolutionID;
++    UInt16                      width;         
++    UInt16                      height;        
++    Bool                        interlaced;    
++    tmdlHdmiTxVfreq_t           vfrequency;    
++    tmdlHdmiTxPictAspectRatio_t aspectRatio;   
++} dlHdmiTxResolution_t, *pdlHdmiTxResolution_t;
++
++
++/*============================================================================*/
++/*                       CONSTANTS DECLARATIONS                               */
++/*============================================================================*/
++/* macro for quick error handling */
++#ifndef RETIF
++#define RETIF(cond, rslt) if ((cond)){return (rslt);}
++#endif
++
++/*============================================================================*/
++/*                         FUNCTION PROTOTYPES                                */
++/*============================================================================*/
++
++/******************************************************************************/
++/* DO NOT MODIFY                                                              */
++/******************************************************************************/
++
++static void dlHdmiTxGenerateVideoPortTables
++(
++    tmUnitSelect_t                  unit,
++    tmdlHdmiTxDriverConfigTable_t   *pConfig
++);
++
++
++/*============================================================================*/
++/*                       VARIABLES DECLARATIONS                               */
++/*============================================================================*/
++
++/**
++ * \brief List of the resolution to be detected by the device library
++ */
++
++#ifdef TMFL_OS_WINDOWS          /* OS Windows */
++dlHdmiTxResolution_t resolutionInfoTx[RESOLUTION_NB] = {
++#else                           /* OS ARM7 */
++const dlHdmiTxResolution_t resolutionInfoTx[RESOLUTION_NB] = {
++#endif                          /* endif TMFL_OS_WINDOWS */
++    /* TV Formats */
++    /* 60 HZ */
++    {TMDL_HDMITX_VFMT_01_640x480p_60Hz,     640,   480,    False,  TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_02_720x480p_60Hz,     720,   480,    False,  TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_03_720x480p_60Hz,     720,   480,    False,  TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_04_1280x720p_60Hz,    1280,  720,    False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_05_1920x1080i_60Hz,   1920,  1080,   True,   TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_06_720x480i_60Hz,     720,   480,    True,   TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_07_720x480i_60Hz,     720,   480,    True,   TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_08_720x240p_60Hz,     720,   240,    False,  TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_09_720x240p_60Hz,     720,   240,    False,  TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_10_720x480i_60Hz,     720,   480,    True,   TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_11_720x480i_60Hz,     720,   480,    True,   TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_12_720x240p_60Hz,     720,   240,    False,  TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_13_720x240p_60Hz,     720,   240,    False,  TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_14_1440x480p_60Hz,    1440,  480,    False,  TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_15_1440x480p_60Hz,    1440,  480,    False,  TMDL_HDMITX_VFREQ_59Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_16_1920x1080p_60Hz,   1920,  1080,   False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_35_2880x480p_60Hz,    2880, 480,     False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_36_2880x480p_60Hz,    2880, 480,     False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++
++    /* 50 HZ */
++    {TMDL_HDMITX_VFMT_17_720x576p_50Hz,     720,   576,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_18_720x576p_50Hz,     720,   576,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_19_1280x720p_50Hz,    1280,  720,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_20_1920x1080i_50Hz,   1920,  1080,   True,   TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_21_720x576i_50Hz,     720,   576,    True,   TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_22_720x576i_50Hz,     720,   576,    True,   TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_23_720x288p_50Hz,     720,   288,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_24_720x288p_50Hz,     720,   288,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_25_720x576i_50Hz,     720,   576,    True,   TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_26_720x576i_50Hz,     720,   576,    True,   TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_27_720x288p_50Hz,     720,   288,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_28_720x288p_50Hz,     720,   288,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_29_1440x576p_50Hz,    1440,  576,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_30_1440x576p_50Hz,    1440,  576,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_31_1920x1080p_50Hz,   1920,  1080,   False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_37_2880x576p_50Hz,    2880,  576,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_38_2880x576p_50Hz,    2880,  576,    False,  TMDL_HDMITX_VFREQ_50Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++
++    /* Low Tv */
++    {TMDL_HDMITX_VFMT_32_1920x1080p_24Hz,   1920,  1080,   False,  TMDL_HDMITX_VFREQ_24Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_33_1920x1080p_25Hz,   1920,  1080,   False,  TMDL_HDMITX_VFREQ_25Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_34_1920x1080p_30Hz,   1920,  1080,   False,  TMDL_HDMITX_VFREQ_30Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_60_1280x720p_24Hz,    1280,  720,    False,  TMDL_HDMITX_VFREQ_24Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_61_1280x720p_25Hz,    1280,  720,    False,  TMDL_HDMITX_VFREQ_25Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_62_1280x720p_30Hz,    1280,  720,    False,  TMDL_HDMITX_VFREQ_30Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9}
++
++#ifdef FORMAT_PC
++    /* PC Formats */
++    /* 60 HZ */
++    ,{TMDL_HDMITX_VFMT_PC_640x480p_60Hz,     640,   480,    False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_800x600p_60Hz,     800,   600,    False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_1152x960p_60Hz,    1152,  960,    False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_6_5},
++    {TMDL_HDMITX_VFMT_PC_1024x768p_60Hz,    1024,  768,    False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_1280x768p_60Hz,    1280,  768,    False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_5_3},
++    {TMDL_HDMITX_VFMT_PC_1280x1024p_60Hz,   1280,  1024,   False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_5_4},
++    {TMDL_HDMITX_VFMT_PC_1360x768p_60Hz,    1360,  768,    False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_9},
++    {TMDL_HDMITX_VFMT_PC_1400x1050p_60Hz,   1400,  1050,   False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_1600x1200p_60Hz,   1600,  1200,   False,  TMDL_HDMITX_VFREQ_60Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    /* 70 HZ */
++    {TMDL_HDMITX_VFMT_PC_1024x768p_70Hz,    1024,  768,    False,  TMDL_HDMITX_VFREQ_70Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    /* 72 HZ */
++    {TMDL_HDMITX_VFMT_PC_640x480p_72Hz,     640,   480,    False,  TMDL_HDMITX_VFREQ_72Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_800x600p_72Hz,     800,   600,    False,  TMDL_HDMITX_VFREQ_72Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    /* 75 HZ */
++    {TMDL_HDMITX_VFMT_PC_640x480p_75Hz,     640,   480,    False,  TMDL_HDMITX_VFREQ_75Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_1024x768p_75Hz,    1024,  768,    False,  TMDL_HDMITX_VFREQ_75Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_800x600p_75Hz,     800,   600,    False,  TMDL_HDMITX_VFREQ_75Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_1024x864p_75Hz,    1024,  864,    False,  TMDL_HDMITX_VFREQ_75Hz, TMDL_HDMITX_P_ASPECT_RATIO_UNDEFINED},
++    {TMDL_HDMITX_VFMT_PC_1280x1024p_75Hz,   1280,  1024,   False,  TMDL_HDMITX_VFREQ_75Hz, TMDL_HDMITX_P_ASPECT_RATIO_5_4},
++    /* 85 HZ */
++    {TMDL_HDMITX_VFMT_PC_640x350p_85Hz,     640,   350,    False,  TMDL_HDMITX_VFREQ_85Hz, TMDL_HDMITX_P_ASPECT_RATIO_UNDEFINED},
++    {TMDL_HDMITX_VFMT_PC_640x400p_85Hz,     640,   400,    False,  TMDL_HDMITX_VFREQ_85Hz, TMDL_HDMITX_P_ASPECT_RATIO_16_10},
++    {TMDL_HDMITX_VFMT_PC_720x400p_85Hz,     720,   400,    False,  TMDL_HDMITX_VFREQ_85Hz, TMDL_HDMITX_P_ASPECT_RATIO_9_5},
++    {TMDL_HDMITX_VFMT_PC_640x480p_85Hz,     640,   480,    False,  TMDL_HDMITX_VFREQ_85Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_800x600p_85Hz,     800,   600,    False,  TMDL_HDMITX_VFREQ_85Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_1024x768p_85Hz,    1024,  768,    False,  TMDL_HDMITX_VFREQ_85Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_1152x864p_85Hz,    1152,  864,    False,  TMDL_HDMITX_VFREQ_85Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_1280x960p_85Hz,    1280,  960,    False,  TMDL_HDMITX_VFREQ_85Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3},
++    {TMDL_HDMITX_VFMT_PC_1280x1024p_85Hz,   1280,  1024,   False,  TMDL_HDMITX_VFREQ_85Hz, TMDL_HDMITX_P_ASPECT_RATIO_5_4},
++    /* 87 HZ */
++    {TMDL_HDMITX_VFMT_PC_1024x768i_87Hz,    1024,  768,    True,   TMDL_HDMITX_VFREQ_87Hz, TMDL_HDMITX_P_ASPECT_RATIO_4_3}
++#endif /* FORMAT_PC */
++};
++
++
++/*============================================================================*/
++/*                         FUNCTION                                           */
++/*============================================================================*/
++
++/******************************************************************************/
++/* DO NOT MODIFY                                                              */
++/******************************************************************************
++    \brief This function allows to the main driver to retrieve its
++           configuration parameters.
++
++    \param pConfig Pointer to the config structure
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t dlHdmiTxGetConfig
++(
++    tmUnitSelect_t                  unit,
++    tmdlHdmiTxDriverConfigTable_t   *pConfig
++)
++{
++    /* Check if unit number is in range */
++    RETIF((unit < 0) || (unit >= MAX_UNITS), TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER)
++
++    /* Check if pointer is Null */
++    RETIF(pConfig == Null, TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS)
++
++    *pConfig = driverConfigTableTx[unit];
++
++    /* Done here because of const declaration of tables in ARM7 case */
++    pConfig->pResolutionInfo = (ptmdlHdmiTxCfgResolution_t)resolutionInfoTx;
++
++    /* Generate swap and mirror tables in function of video port mapping tables */
++    dlHdmiTxGenerateVideoPortTables(unit, pConfig);
++
++    return TM_OK;
++}
++
++
++/*============================================================================*/
++/*                           INTERNAL FUNCTION                                */
++/*============================================================================*/
++/******************************************************************************/
++/* DO NOT MODIFY                                                              */
++/******************************************************************************/
++static void dlHdmiTxGenerateVideoPortTables
++(
++    tmUnitSelect_t                  unit,
++    tmdlHdmiTxDriverConfigTable_t   *pConfig
++)
++{
++    UInt8   i;
++
++    for (i=0; i<6; i++)
++    {
++        /* CCIR656 */
++        if (videoPortMapping_CCIR656[unit][i] != TMDL_HDMITX_VIDCCIR_NOT_CONNECTED)
++        {
++            pConfig->pSwapTableCCIR656[videoPortMapping_CCIR656[unit][i] & 0x07F] = 5-i;
++            pConfig->pMirrorTableCCIR656[videoPortMapping_CCIR656[unit][i] & 0x07F] = (UInt8)(videoPortMapping_CCIR656[unit][i] >> 7);
++            /* Enable port and disable ground port */
++            if (((5-i) % 2) == 0)
++            {
++                pConfig->pEnableVideoPortCCIR656[i/2] |= 0x0F;
++                pConfig->pGroundVideoPortCCIR656[i/2] = (UInt8)(pConfig->pGroundVideoPortCCIR656[i/2] & 0xF0);
++            }
++            else
++            {
++                pConfig->pEnableVideoPortCCIR656[i/2] = (UInt8)(pConfig->pEnableVideoPortCCIR656[i/2] | 0xF0);
++                pConfig->pGroundVideoPortCCIR656[i/2] &= 0x0F;
++            }
++        }
++
++        /* YUV422 */
++        if (videoPortMapping_YUV422[unit][i] != TMDL_HDMITX_VID422_NOT_CONNECTED)
++        {
++            pConfig->pSwapTableYUV422[videoPortMapping_YUV422[unit][i] & 0x07F] = 5-i;
++            pConfig->pMirrorTableYUV422[videoPortMapping_YUV422[unit][i] & 0x07F] = (UInt8)(videoPortMapping_YUV422[unit][i] >> 7);
++            /* Enable port and disable ground port */
++            if (((5-i) % 2) == 0)
++            {
++                pConfig->pEnableVideoPortYUV422[i/2] |= 0x0F;
++                pConfig->pGroundVideoPortYUV422[i/2] = (UInt8)(pConfig->pGroundVideoPortYUV422[i/2] & 0xF0);
++            }
++            else
++            {
++                pConfig->pEnableVideoPortYUV422[i/2] = (UInt8)(pConfig->pEnableVideoPortYUV422[i/2] | 0xF0);
++                pConfig->pGroundVideoPortYUV422[i/2] &= 0x0F;
++            }
++        }
++
++        /* YUV444 */
++        if (videoPortMapping_YUV444[unit][i] != TMDL_HDMITX_VID444_NOT_CONNECTED)
++        {
++            pConfig->pSwapTableYUV444[videoPortMapping_YUV444[unit][i] & 0x07F] = 5-i;
++            pConfig->pMirrorTableYUV444[videoPortMapping_YUV444[unit][i] & 0x07F] = (UInt8)(videoPortMapping_YUV444[unit][i] >> 7);
++            /* Enable port and disable ground port */
++            if (((5-i) % 2) == 0)
++            {
++                pConfig->pEnableVideoPortYUV444[i/2] |= 0x0F;
++                pConfig->pGroundVideoPortYUV444[i/2] = (UInt8)(pConfig->pGroundVideoPortYUV444[i/2] & 0xF0);
++            }
++            else
++            {
++                pConfig->pEnableVideoPortYUV444[i/2] = (UInt8)(pConfig->pEnableVideoPortYUV444[i/2] | 0xF0);
++                pConfig->pGroundVideoPortYUV444[i/2] &= 0x0F;
++            }
++        }
++
++        /* RGB444 */
++        if (videoPortMapping_RGB444[unit][i] != TMDL_HDMITX_VID444_NOT_CONNECTED)
++        {
++            pConfig->pSwapTableRGB444[videoPortMapping_RGB444[unit][i] & 0x07F] = 5-i;
++            pConfig->pMirrorTableRGB444[videoPortMapping_RGB444[unit][i] & 0x07F] = (UInt8)(videoPortMapping_RGB444[unit][i] >> 7);
++            /* Enable port and disable ground port */
++            if (((5-i) % 2) == 0)
++            {
++                pConfig->pEnableVideoPortRGB444[i/2] |= 0x0F;
++                pConfig->pGroundVideoPortRGB444[i/2] = (UInt8)(pConfig->pGroundVideoPortRGB444[i/2] & 0xF0);
++            }
++            else
++            {
++                pConfig->pEnableVideoPortRGB444[i/2] = (UInt8)(pConfig->pEnableVideoPortRGB444[i/2] | 0xF0);
++                pConfig->pGroundVideoPortRGB444[i/2] &= 0x0F;
++            }
++        }
++
++
++#ifdef TMFL_RGB_DDR_12BITS
++        /* RGB DDR 12bits */
++        if (VideoPortMapping_RGB_DDR_12bits[unit][i] != TMDL_HDMITX_VID_DDR_NOT_CONNECTED)
++        {
++            pConfig->pSwapTableRGB_DDR_12bits[VideoPortMapping_RGB_DDR_12bits[unit][i] & 0x07F] = 5-i;
++            pConfig->pMirrorTableRGB_DDR_12bits[VideoPortMapping_RGB_DDR_12bits[unit][i] & 0x07F] = (UInt8)(VideoPortMapping_RGB_DDR_12bits[unit][i] >> 7);
++            /* Enable port and disable ground port */
++            if (((5-i) % 2) == 0)
++            {
++                pConfig->pEnableVideoPortRGB_DDR_12bits[i/2] |= 0x0F;
++                pConfig->pGroundVideoPortRGB_DDR_12bits[i/2] = (UInt8)(pConfig->pGroundVideoPortRGB_DDR_12bits[i/2] & 0xF0);
++            }
++            else
++            {
++                pConfig->pEnableVideoPortRGB_DDR_12bits[i/2] = (UInt8)(pConfig->pEnableVideoPortRGB_DDR_12bits[i/2] | 0xF0);
++                pConfig->pGroundVideoPortRGB_DDR_12bits[i/2] &= 0x0F;
++            }
++        }
++#endif
++    }
++
++#ifdef TMFL_RGB_DDR_12BITS
++    /* VIP internal mux for RGB DDR  */
++    pConfig->pNoMux = (UInt8*)&VideoPortNoMux[unit];
++    pConfig->pMux_RGB_DDR_12bits = (UInt8*)&VideoPortMux_RGB_DDR_12bits[unit];
++#endif
++
++}
++
++/*============================================================================*/
++/*                            END OF FILE                                     */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.h b/drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.h
+new file mode 100755
+index 0000000..ccda7bf
+--- /dev/null
++++ b/drivers/video/nxp/comps/tmdlHdmiTx/src/tmdlHdmiTx_local.h
+@@ -0,0 +1,702 @@
++/**
++ * Copyright (C) 2006 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * \file          tmdlHdmiTx_local.h
++ *
++ * \version       $Revision: 1 $
++ *
++ * \date          $Date: 02/08/07 08:32 $
++ *
++ * \brief         devlib driver component API for the TDA998x HDMI Transmitters
++ *
++ * \section refs  Reference Documents
++ * HDMI Tx Driver - FRS.doc,
++ *
++ * \section info  Change Information
++ *
++ * \verbatim
++
++   $History: tmdlHdmiTx_local.h $
++ *
++  * *****************  Version 13  *****************
++ * User: J. Lamotte Date: 02/08/07   Time: 08:32
++ * Updated in $/Source/tmdlHdmiTx/inc
++ * initial version
++ *
++
++   \endverbatim
++ *
++*/
++
++#ifndef TMDLHDMITX_LOCAL_H
++#define TMDLHDMITX_LOCAL_H
++
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#include <linux/kernel.h>
++#endif
++
++#include "tmdlHdmiTx_IW.h"
++#include "tmNxTypes.h"
++#include "tmdlHdmiTx_Types.h"
++#include "tmdlHdmiTx_cfg.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*============================================================================*/
++/*                            MACRO DEFINITIONS                               */
++/*============================================================================*/
++
++/* Version of the SW driver */
++#define VERSION_COMPATIBILITY 0
++#define VERSION_MAJOR         5
++#define VERSION_MINOR         3
++
++/* Invalid HDCP seed */
++#define HDCP_SEED_NULL      0
++
++/* A default seed value may be defined here, or set to HDCP_SEED_NULL.
++ * If HDCP_SEED_NULL, a table of seeds may instead be programmed separately
++ * into flash at the location of kSeedTable, below */
++#define HDCP_SEED_DEFAULT   HDCP_SEED_NULL
++
++/* Default SHA-1 test handling */
++#define HDCP_OPT_DEFAULT    ( TMDL_HDMITX_HDCP_OPTION_FORCE_PJ_IGNORED \
++                                | TMDL_HDMITX_HDCP_OPTION_FORCE_VSLOW_DDC \
++                                | TMDL_HDMITX_HDCP_OPTION_FORCE_NO_1_1 )
++
++/**
++ * A macro to check a condition and if true return a result
++ */
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#define RETIF(cond, rslt)       if ((cond)){ \
++      printk(KERN_INFO "%s %d\n",__func__,__LINE__); \
++      return (rslt);}
++#else
++#define RETIF(cond, rslt)       if ((cond)){return (rslt);}
++#endif
++
++/**
++ * A macro to check a condition and if true return 
++ * TMDL_ERR_DLHDMITX_BAD_PARAMETER.
++ * To save code space, it can be compiled out by defining NO_RETIF_BADPARAM on
++ * the compiler command line.
++ */
++#ifdef NO_RETIF_BADPARAM
++#define RETIF_BADPARAM(cond)
++#else
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#define RETIF_BADPARAM(cond)  if ((cond)){ \
++      printk(KERN_INFO "%s %d\n",__func__,__LINE__);    \
++      return TMDL_ERR_DLHDMITX_BAD_PARAMETER;}
++#else
++#define RETIF_BADPARAM(cond)  if ((cond)){return TMDL_ERR_DLHDMITX_BAD_PARAMETER;}
++#endif
++#endif
++
++/**
++ * A macro to check a condition and if true, release the semaphore describe by handle and return a result
++ */
++#ifdef TMFL_LINUX_OS_KERNEL_DRIVER
++#define RETIF_SEM(handle, cond, rslt)       if ((cond)){ \
++      tmdlHdmiTxIWSemaphoreV(handle);                    \
++      printk(KERN_INFO "%s %d\n",__func__,__LINE__);     \
++      return (rslt);}
++#else
++#define RETIF_SEM(handle, cond, rslt)       if ((cond)){tmdlHdmiTxIWSemaphoreV(handle); return (rslt);}
++#endif
++
++ /* Resolution supported */
++#ifndef FORMAT_PC
++#define RESOLUTION_NB   41
++#else
++#define RESOLUTION_NB   68
++#endif /* FORMAT_PC */
++
++/* Instance number */
++#define INSTANCE_0  0
++#define INSTANCE_1  1
++
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++/* Number of event */
++#define EVENT_NB    10
++#else /* HDMI_TX_REPEATER_ISR_MODE */
++/* Number of event */
++#define EVENT_NB    9
++#endif /* HDMI_TX_REPEATER_ISR_MODE */
++
++/* Size of a KSV is five bytes */
++#define KSV_SIZE  5
++
++/* Arbitrary short TV format values */
++#define TV_INVALID      0
++#define TV_VGA_60Hz     1
++#define TV_240p_60Hz    2
++#define TV_480p_60Hz    3
++#define TV_480i_60Hz    4
++#define TV_720p_60Hz    5
++#define TV_1080p_60Hz   6
++#define TV_1080i_60Hz   7
++#define TV_288p_50Hz    8
++#define TV_576p_50Hz    9
++#define TV_576i_50Hz    10
++#define TV_720p_50Hz    11
++#define TV_1080p_50Hz   12
++#define TV_1080i_50Hz   13
++
++/* Shorthands for vinMode values in tmbslTDA9984.h */
++#define iINVALID TMDL_HDMITX_VINMODE_INVALID
++#define iCCIR656 TMDL_HDMITX_VINMODE_CCIR656
++#define iRGB444  TMDL_HDMITX_VINMODE_RGB444 
++#define iYUV444  TMDL_HDMITX_VINMODE_YUV444 
++#define iYUV422  TMDL_HDMITX_VINMODE_YUV422 
++
++/* Shorthands for input sync */
++#define EMB      1
++#define EXT      0
++
++/* Shorthands for single/double pixel rate in tmbslTDA9984.h */
++#define SINGLE   TMDL_HDMITX_PIXRATE_SINGLE
++#define DOUBLE   TMDL_HDMITX_PIXRATE_DOUBLE
++
++/* Shorthands for sampling frequency in tmdlHdmiTxSetAudioInput API */
++#define AIF_SF_REFER_TO_STREAM_HEADER   0
++#define AIF_SF_32K                      1
++#define AIF_SF_44K                      2
++#define AIF_SF_48K                      3
++#define AIF_SF_88K                      4
++#define AIF_SF_96K                      5
++#define AIF_SF_176K                     6
++#define AIF_SF_192K                     7
++
++/* HDCP check interval in milliseconds */
++#define HDCP_CHECK_INTERVAL_MS  2500
++
++/* Number of HDCP checks to carry out after HDCP is started */
++#define HDCP_NUM_CHECKS         5
++
++#define TMDL_HDMITX_CHANNELALLOC_LUT_SIZE 32
++
++
++static CONST_DAT UInt8 kChanAllocChanNum[TMDL_HDMITX_CHANNELALLOC_LUT_SIZE] = \
++{2,3,3,4,3,4,4,5,4,5,5,6,5,6,6,7,6,7,7,8,4,5,5,6,5,6,6,7,6,7,7,8 };
++
++
++/**
++ * Lookup table to convert from EIA/CEA TV video format to
++ * aspect ratio used in video infoframe:
++ * Aspect ratio 1=4:3, 2=16:9
++ */
++#ifndef FORMAT_PC
++static CONST_DAT UInt8 kVfmtToAspect_TV[TMDL_HDMITX_VFMT_TV_NUM] =
++#else /* FORMAT_PC */
++static CONST_DAT UInt8 kVfmtToAspect_TV[TMDL_HDMITX_VFMT_TV_NUM + TMDL_HDMITX_VFMT_PC_NUM] =
++#endif /* FORMAT_PC */
++{
++    0,  /* HDMITX_VFMT_NULL                */
++    1,  /* HDMITX_VFMT_01_640x480p_60Hz    */
++    1,  /* HDMITX_VFMT_02_720x480p_60Hz    */
++    2,  /* HDMITX_VFMT_03_720x480p_60Hz    */
++    2,  /* HDMITX_VFMT_04_1280x720p_60Hz   */
++    2,  /* HDMITX_VFMT_05_1920x1080i_60Hz  */
++    1,  /* HDMITX_VFMT_06_720x480i_60Hz    */
++    2,  /* HDMITX_VFMT_07_720x480i_60Hz    */
++    1,  /* HDMITX_VFMT_08_720x240p_60Hz    */
++    2,  /* HDMITX_VFMT_09_720x240p_60Hz    */
++    1,  /* HDMITX_VFMT_10_720x480i_60Hz    */
++    2,  /* HDMITX_VFMT_11_720x480i_60Hz    */
++    1,  /* HDMITX_VFMT_12_720x240p_60Hz    */
++    2,  /* HDMITX_VFMT_13_720x240p_60Hz    */
++    1,  /* HDMITX_VFMT_14_1440x480p_60Hz   */
++    2,  /* HDMITX_VFMT_15_1440x480p_60Hz   */
++    2,  /* HDMITX_VFMT_16_1920x1080p_60Hz  */
++    1,  /* HDMITX_VFMT_17_720x576p_50Hz    */
++    2,  /* HDMITX_VFMT_18_720x576p_50Hz    */
++    2,  /* HDMITX_VFMT_19_1280x720p_50Hz   */
++    2,  /* HDMITX_VFMT_20_1920x1080i_50Hz  */
++    1,  /* HDMITX_VFMT_21_720x576i_50Hz    */
++    2,  /* HDMITX_VFMT_22_720x576i_50Hz    */
++    1,  /* HDMITX_VFMT_23_720x288p_50Hz    */
++    2,  /* HDMITX_VFMT_24_720x288p_50Hz    */
++    1,  /* HDMITX_VFMT_25_720x576i_50Hz    */
++    2,  /* HDMITX_VFMT_26_720x576i_50Hz    */
++    1,  /* HDMITX_VFMT_27_720x288p_50Hz    */
++    2,  /* HDMITX_VFMT_28_720x288p_50Hz    */
++    1,  /* HDMITX_VFMT_29_1440x576p_50Hz   */
++    2,  /* HDMITX_VFMT_30_1440x576p_50Hz   */
++    2,  /* HDMITX_VFMT_31_1920x1080p_50Hz  */
++    2,  /* HDMITX_VFMT_32_1920x1080p_24Hz  */
++    2,  /* HDMITX_VFMT_33_1920x1080p_25Hz  */
++    2,  /* HDMITX_VFMT_34_1920x1080p_30Hz  */
++
++    1,  /* TMDL_HDMITX_VFMT_35_2880x480p_60Hz */
++    2,  /* TMDL_HDMITX_VFMT_36_2880x480p_60Hz */
++    1,  /* TMDL_HDMITX_VFMT_37_2880x576p_50Hz */
++    2,  /* TMDL_HDMITX_VFMT_38_2880x576p_50Hz */
++
++    2,  /* TMDL_HDMITX_VFMT_60_1280x720p_24HZ */
++    2,  /* TMDL_HDMITX_VFMT_61_1280_720p_25HZ */
++    2   /* TMDL_HDMITX_VFMT_62_1280_720p_30HZ */
++    
++#ifdef FORMAT_PC
++   ,1,  /* HDMITX_VFMT_PC_640x480p_60Hz    */
++    1,  /* HDMITX_VFMT_PC_800x600p_60Hz    */
++    1,  /* HDMITX_VFMT_PC_1152x960p_60Hz   */
++    1,  /* HDMITX_VFMT_PC_1024x768p_60Hz   */
++    1,  /* HDMITX_VFMT_PC_1280x768p_60Hz   */
++    1,  /* HDMITX_VFMT_PC_1280x1024p_60Hz  */
++    1,  /* HDMITX_VFMT_PC_1360x768p_60Hz   */
++    1,  /* HDMITX_VFMT_PC_1400x1050p_60Hz  */
++    1,  /* HDMITX_VFMT_PC_1600x1200p_60Hz  */
++    1,  /* HDMITX_VFMT_PC_1024x768p_70Hz   */
++    1,  /* HDMITX_VFMT_PC_640x480p_72Hz    */
++    1,  /* HDMITX_VFMT_PC_800x600p_72Hz    */
++    1,  /* HDMITX_VFMT_PC_640x480p_75Hz    */
++    1,  /* HDMITX_VFMT_PC_1024x768p_75Hz   */
++    1,  /* HDMITX_VFMT_PC_800x600p_75Hz    */
++    1,  /* HDMITX_VFMT_PC_1024x864p_75Hz   */
++    1,  /* HDMITX_VFMT_PC_1280x1024p_75Hz  */
++    1,  /* HDMITX_VFMT_PC_640x350p_85Hz    */
++    1,  /* HDMITX_VFMT_PC_640x400p_85Hz    */
++    1,  /* HDMITX_VFMT_PC_720x400p_85Hz    */
++    1,  /* HDMITX_VFMT_PC_640x480p_85Hz    */
++    1,  /* HDMITX_VFMT_PC_800x600p_85Hz    */
++    1,  /* HDMITX_VFMT_PC_1024x768p_85Hz   */
++    1,  /* HDMITX_VFMT_PC_1152x864p_85Hz   */
++    1,  /* HDMITX_VFMT_PC_1280x960p_85Hz   */
++    1,  /* HDMITX_VFMT_PC_1280x1024p_85Hz  */
++    1   /* HDMITX_VFMT_PC_1024x768i_87Hz   */
++#endif /* FORMAT_PC */
++};
++
++/**
++ * Lookup table to convert from EIA/CEA TV video format to
++ * the short format of resolution/interlace/frequency
++ */
++static CONST_DAT UInt8 kVfmtToShortFmt_TV[TMDL_HDMITX_VFMT_TV_NUM] =
++{
++    TV_INVALID,         /* HDMITX_VFMT_NULL               */
++    TV_VGA_60Hz,        /* HDMITX_VFMT_01_640x480p_60Hz   */
++    TV_480p_60Hz,       /* HDMITX_VFMT_02_720x480p_60Hz   */
++    TV_480p_60Hz,       /* HDMITX_VFMT_03_720x480p_60Hz   */
++    TV_720p_60Hz,       /* HDMITX_VFMT_04_1280x720p_60Hz  */
++    TV_1080i_60Hz,      /* HDMITX_VFMT_05_1920x1080i_60Hz */
++    TV_480i_60Hz,       /* HDMITX_VFMT_06_720x480i_60Hz   */
++    TV_480i_60Hz,       /* HDMITX_VFMT_07_720x480i_60Hz   */
++    TV_240p_60Hz,       /* HDMITX_VFMT_08_720x240p_60Hz   */
++    TV_240p_60Hz,       /* HDMITX_VFMT_09_720x240p_60Hz   */
++    TV_480i_60Hz,       /* HDMITX_VFMT_10_720x480i_60Hz   */
++    TV_480i_60Hz,       /* HDMITX_VFMT_11_720x480i_60Hz   */
++    TV_240p_60Hz,       /* HDMITX_VFMT_12_720x240p_60Hz   */
++    TV_240p_60Hz,       /* HDMITX_VFMT_13_720x240p_60Hz   */
++    TV_480p_60Hz,       /* HDMITX_VFMT_14_1440x480p_60Hz  */
++    TV_480p_60Hz,       /* HDMITX_VFMT_15_1440x480p_60Hz  */
++    TV_1080p_60Hz,      /* HDMITX_VFMT_16_1920x1080p_60Hz */
++    TV_576p_50Hz,       /* HDMITX_VFMT_17_720x576p_50Hz   */
++    TV_576p_50Hz,       /* HDMITX_VFMT_18_720x576p_50Hz   */
++    TV_720p_50Hz,       /* HDMITX_VFMT_19_1280x720p_50Hz  */
++    TV_1080i_50Hz,      /* HDMITX_VFMT_20_1920x1080i_50Hz */
++    TV_576i_50Hz,       /* HDMITX_VFMT_21_720x576i_50Hz   */
++    TV_576i_50Hz,       /* HDMITX_VFMT_22_720x576i_50Hz   */
++    TV_288p_50Hz,       /* HDMITX_VFMT_23_720x288p_50Hz   */
++    TV_288p_50Hz,       /* HDMITX_VFMT_24_720x288p_50Hz   */
++    TV_576i_50Hz,       /* HDMITX_VFMT_25_720x576i_50Hz   */
++    TV_576i_50Hz,       /* HDMITX_VFMT_26_720x576i_50Hz   */
++    TV_288p_50Hz,       /* HDMITX_VFMT_27_720x288p_50Hz   */
++    TV_288p_50Hz,       /* HDMITX_VFMT_28_720x288p_50Hz   */
++    TV_576p_50Hz,       /* HDMITX_VFMT_29_1440x576p_50Hz  */
++    TV_576p_50Hz,       /* HDMITX_VFMT_30_1440x576p_50Hz  */
++    TV_1080p_50Hz,      /* HDMITX_VFMT_31_1920x1080p_50Hz */
++    TV_INVALID,         /* HDMITX_VFMT_NULL               */
++    TV_INVALID,         /* HDMITX_VFMT_NULL               */
++    TV_INVALID,         /* HDMITX_VFMT_NULL               */
++    TV_480p_60Hz,       /* HDMITX_VFMT_35_2880x480p_60Hz  */
++    TV_480p_60Hz,       /* HDMITX_VFMT_36_2880x480p_60Hz  */
++    TV_576p_50Hz,       /* HDMITX_VFMT_37_2880x576p_50Hz  */
++    TV_576p_50Hz,       /* HDMITX_VFMT_38_2880x576p_50Hz  */
++    TV_INVALID,         /* HDMITX_VFMT_NULL               */
++    TV_INVALID,         /* HDMITX_VFMT_NULL               */
++    TV_INVALID          /* HDMITX_VFMT_NULL               */
++};
++
++/**
++ * Macro to pack vinMode(0-5), pixRate(0-1), syncIn(0-1) and bVerified(0-1)
++ * into a byte
++ */
++#define PKBYTE(mode,rate,sync,verf) (((rate)<<7)|((sync)<<6)|((verf)<<5)|((mode)&0x1F))
++
++/**
++ * Macros to unpack vinMode(0-5), pixRate(0-1), syncIn(0-1) and bVerified(0-1)
++ * from a byte
++ */
++#define UNPKRATE(byte) (((byte)>>7)&1)
++#define UNPKSYNC(byte) (((byte)>>6)&1)
++#define UNPKVERF(byte) (((byte)>>5)&1)
++#define UNPKMODE(byte) ((byte)&0x1F)
++
++/**
++ * Lookup table to match main video settings and look up sets of
++ * Refpix and Refline values
++ */
++static CONST_DAT struct
++{
++    /* Values to match */
++    UInt8   modeRateSyncVerf;   /* Packed vinMode, pixRate, syncIn, bVerified */
++    UInt8   shortVinFmt;
++    UInt8   shortVoutFmt;
++    /* Values to look up */
++    UInt16  refPix;             /* Output values */
++    UInt16  refLine;
++    UInt16  scRefPix;           /* Scaler values */
++    UInt16  scRefLine;
++} kRefpixRefline [] =
++{
++  /*************************************************************/
++  /** Rows formatted in "Refpix_Refline.xls" and pasted here  **/
++  /** DO NOT DELETE ANY ROWS, to keep all scaler combinations **/
++  /*************************************************************/
++  /*        mode_____Rate___Sync_Verf  shortVinFmt     shortVoutFmt    refPix  refLine  scRefPix  scRefLine  Test ID  */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_480i_60Hz,   TV_480p_60Hz,   0x08b,  0x024,   0x078,    0x017}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_480i_60Hz,   TV_720p_60Hz,   0x08b,  0x012,   0x078,    0x017}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_480i_60Hz,   TV_1080i_60Hz,  0x08b,  0x00e,   0x078,    0x017}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_480i_60Hz,   TV_1080p_60Hz,  0x08b,  0x021,   0x078,    0x017}, /*  */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_480p_60Hz,   TV_720p_60Hz,   0x08b,  0x017,   0x078,    0x02c}, /* VID_F_01 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_480p_60Hz,   TV_1080i_60Hz,  0x08b,  0x013,   0x078,    0x02c}, /* VID_F_01 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_480p_60Hz,   TV_1080p_60Hz,  0x08b,  0x027,   0x07A,    0x02c}, /*  */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_576i_50Hz,   TV_576p_50Hz,   0x091,  0x026,   0x085,    0x018}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_576i_50Hz,   TV_720p_50Hz,   0x091,  0x013,   0x085,    0x018}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_576i_50Hz,   TV_1080i_50Hz,  0x091,  0x00f,   0x085,    0x018}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_576i_50Hz,   TV_1080p_50Hz,  0x091,  0x022,   0x085,    0x018}, /*  */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_576p_50Hz,   TV_720p_50Hz,   0x091,  0x019,   0x085,    0x02e}, /* VID_F_06 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_576p_50Hz,   TV_1080i_50Hz,  0x091,  0x014,   0x085,    0x02e}, /* VID_F_06 */
++    {PKBYTE(iCCIR656,SINGLE,EMB, 1),   TV_576p_50Hz,   TV_1080p_50Hz,  0x091,  0x028,   0x087,    0x02e}, /*  */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_480i_60Hz,   TV_480p_60Hz,   0x014,  0x20d,   0x359,    0x004}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_480i_60Hz,   TV_720p_60Hz,   0x014,  0x2cb,   0x359,    0x004}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_480i_60Hz,   TV_1080i_60Hz,  0x014,  0x44c,   0x359,    0x004}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_480i_60Hz,   TV_1080p_60Hz,  0x014,  0x436,   0x359,    0x004}, /*  */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_480p_60Hz,   TV_720p_60Hz,   0x011,  0x2d3,   0x358,    0x007}, /* VID_F_01 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_480p_60Hz,   TV_1080i_60Hz,  0x011,  0x452,   0x358,    0x007}, /* VID_F_01 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_480p_60Hz,   TV_1080p_60Hz,  0x011,  0x43e,   0x358,    0x007}, /*  */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_576i_50Hz,   TV_576p_50Hz,   0x00d,  0x26b,   0x35f,    0x001}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_576i_50Hz,   TV_720p_50Hz,   0x00d,  0x2cb,   0x35f,    0x001}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_576i_50Hz,   TV_1080i_50Hz,  0x00d,  0x44b,   0x35f,    0x001}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_576i_50Hz,   TV_1080p_50Hz,  0x00d,  0x435,   0x35f,    0x001}, /*  */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_576p_50Hz,   TV_720p_50Hz,   0x00d,  0x2d1,   0x35f,    0x001}, /* VID_F_06 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_576p_50Hz,   TV_1080i_50Hz,  0x00d,  0x451,   0x35f,    0x001}, /* VID_F_06 */
++    {PKBYTE(iCCIR656,SINGLE,EXT, 1),   TV_576p_50Hz,   TV_1080p_50Hz,  0x00d,  0x43d,   0x35f,    0x001}, /*  */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_480i_60Hz,   TV_480p_60Hz,   0x08b,  0x024,   0x078,    0x017}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_480i_60Hz,   TV_720p_60Hz,   0x08b,  0x012,   0x078,    0x017}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_480i_60Hz,   TV_1080i_60Hz,  0x08b,  0x00e,   0x078,    0x017}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_480i_60Hz,   TV_1080p_60Hz,  0x08b,  0x021,   0x078,    0x017}, /*  */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_480p_60Hz,   TV_720p_60Hz,   0x08b,  0x017,   0x078,    0x02c}, /* VID_F_01 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_480p_60Hz,   TV_1080i_60Hz,  0x08b,  0x013,   0x078,    0x02c}, /* VID_F_01 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_480p_60Hz,   TV_1080p_60Hz,  0x08b,  0x027,   0x07A,    0x02c}, /*  */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_576i_50Hz,   TV_576p_50Hz,   0x091,  0x026,   0x085,    0x018}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_576i_50Hz,   TV_720p_50Hz,   0x091,  0x013,   0x085,    0x018}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_576i_50Hz,   TV_1080i_50Hz,  0x091,  0x00f,   0x085,    0x018}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_576i_50Hz,   TV_1080p_50Hz,  0x091,  0x022,   0x085,    0x018}, /*  */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_576p_50Hz,   TV_720p_50Hz,   0x091,  0x019,   0x085,    0x02e}, /* VID_F_06 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_576p_50Hz,   TV_1080i_50Hz,  0x091,  0x014,   0x085,    0x02e}, /* VID_F_06 */
++    {PKBYTE(iCCIR656,DOUBLE,EMB, 1),   TV_576p_50Hz,   TV_1080p_50Hz,  0x091,  0x028,   0x087,    0x02e}, /*  */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_480i_60Hz,   TV_480p_60Hz,   0x014,  0x20d,   0x359,    0x004}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_480i_60Hz,   TV_720p_60Hz,   0x014,  0x2cb,   0x359,    0x004}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_480i_60Hz,   TV_1080i_60Hz,  0x014,  0x44c,   0x359,    0x004}, /* VID_F_04 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_480i_60Hz,   TV_1080p_60Hz,  0x014,  0x436,   0x359,    0x004}, /*  */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_480p_60Hz,   TV_720p_60Hz,   0x011,  0x2d3,   0x358,    0x007}, /* VID_F_01 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_480p_60Hz,   TV_1080i_60Hz,  0x011,  0x452,   0x358,    0x007}, /* VID_F_01 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_480p_60Hz,   TV_1080p_60Hz,  0x011,  0x43e,   0x358,    0x007}, /*  */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_576i_50Hz,   TV_576p_50Hz,   0x00d,  0x26b,   0x35f,    0x001}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_576i_50Hz,   TV_720p_50Hz,   0x00d,  0x2cb,   0x35f,    0x001}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_576i_50Hz,   TV_1080i_50Hz,  0x00d,  0x44b,   0x35f,    0x001}, /* VID_F_09 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_576i_50Hz,   TV_1080p_50Hz,  0x00d,  0x435,   0x35f,    0x001}, /*  */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_576p_50Hz,   TV_720p_50Hz,   0x00d,  0x2d1,   0x35f,    0x001}, /* VID_F_06 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_576p_50Hz,   TV_1080i_50Hz,  0x00d,  0x451,   0x35f,    0x001}, /* VID_F_06 */
++    {PKBYTE(iCCIR656,DOUBLE,EXT, 1),   TV_576p_50Hz,   TV_1080p_50Hz,  0x00d,  0x43d,   0x35f,    0x001}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_480i_60Hz,   TV_480p_60Hz,   0x08d,  0x028,   0x078,    0x017}, /* VID_F_04 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_480i_60Hz,   TV_720p_60Hz,   0x08d,  0x014,   0x078,    0x017}, /* VID_F_04 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_480i_60Hz,   TV_1080i_60Hz,  0x08d,  0x010,   0x078,    0x017}, /* VID_F_04 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_480i_60Hz,   TV_1080p_60Hz,  0x08d,  0x021,   0x078,    0x017}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_480p_60Hz,   TV_720p_60Hz,   0x08d,  0x017,   0x078,    0x02c}, /* VID_F_01 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_480p_60Hz,   TV_1080i_60Hz,  0x08d,  0x014,   0x078,    0x02c}, /* VID_F_01 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_480p_60Hz,   TV_1080p_60Hz,  0x08d,  0x027,   0x07C,    0x02c}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_576i_50Hz,   TV_576p_50Hz,   0x093,  0x02a,   0x085,    0x018}, /* VID_F_09 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_576i_50Hz,   TV_720p_50Hz,   0x093,  0x013,   0x085,    0x018}, /* VID_F_09 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_576i_50Hz,   TV_1080i_50Hz,  0x093,  0x00e,   0x085,    0x018}, /* VID_F_09 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_576i_50Hz,   TV_1080p_50Hz,  0x093,  0x022,   0x085,    0x018}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_576p_50Hz,   TV_720p_50Hz,   0x093,  0x019,   0x085,    0x02e}, /* VID_F_06 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_576p_50Hz,   TV_1080i_50Hz,  0x093,  0x014,   0x085,    0x02e}, /* VID_F_06 */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_576p_50Hz,   TV_1080p_50Hz,  0x093,  0x028,   0x089,    0x02e}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_720p_50Hz,   TV_1080p_50Hz,  0x2bf,  0x024,   0x105,    0x019}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_720p_60Hz,   TV_1080p_60Hz,  0x175,  0x024,   0x105,    0x019}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_1080i_50Hz,  TV_1080p_50Hz,  0x2d3,  0x023,   0x0c3,    0x014}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EMB, 1),   TV_1080i_60Hz,  TV_1080p_60Hz,  0x11b,  0x023,   0x0c3,    0x014}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_480i_60Hz,   TV_480p_60Hz,   0x016,  0x20d,   0x359,    0x004}, /* VID_F_04 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_480i_60Hz,   TV_720p_60Hz,   0x016,  0x2cb,   0x359,    0x004}, /* VID_F_04 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_480i_60Hz,   TV_1080i_60Hz,  0x016,  0x44c,   0x359,    0x004}, /* VID_F_04 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_480i_60Hz,   TV_1080p_60Hz,  0x016,  0x436,   0x359,    0x004}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_480p_60Hz,   TV_720p_60Hz,   0x013,  0x2d3,   0x358,    0x007}, /* VID_F_01 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_480p_60Hz,   TV_1080i_60Hz,  0x013,  0x452,   0x358,    0x007}, /* VID_F_01 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_480p_60Hz,   TV_1080p_60Hz,  0x013,  0x43e,   0x358,    0x007}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_576i_50Hz,   TV_576p_50Hz,   0x00f,  0x26b,   0x35f,    0x001}, /* VID_F_09 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_576i_50Hz,   TV_720p_50Hz,   0x00f,  0x2cb,   0x35f,    0x001}, /* VID_F_09 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_576i_50Hz,   TV_1080i_50Hz,  0x00f,  0x44b,   0x35f,    0x001}, /* VID_F_09 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_576i_50Hz,   TV_1080p_50Hz,  0x00f,  0x435,   0x35f,    0x001}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_576p_50Hz,   TV_720p_50Hz,   0x00f,  0x2d1,   0x35f,    0x001}, /* VID_F_06 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_576p_50Hz,   TV_1080i_50Hz,  0x00f,  0x451,   0x35f,    0x001}, /* VID_F_06 */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_576p_50Hz,   TV_1080p_50Hz,  0x00f,  0x43d,   0x35f,    0x001}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_720p_50Hz,   TV_1080p_50Hz,  0x1bb,  0x463,   0x7bb,    0x000}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_720p_60Hz,   TV_1080p_60Hz,  0x071,  0x463,   0x671,    0x000}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_1080i_50Hz,  TV_1080p_50Hz,  0x213,  0x460,   0xa4f,    0x000}, /*  */
++    {PKBYTE(iYUV422, SINGLE,EXT, 1),   TV_1080i_60Hz,  TV_1080p_60Hz,  0x05b,  0x460,   0x897,    0x000}, /*  */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV422, DOUBLE,EMB, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV422, DOUBLE,EXT, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV444, SINGLE,EMB, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV444, SINGLE,EXT, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV444, DOUBLE,EMB, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iYUV444, DOUBLE,EXT, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iRGB444, SINGLE,EMB, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_480p_60Hz,   TV_VGA_60Hz,    0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iRGB444, SINGLE,EXT, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iRGB444, DOUBLE,EMB, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_480i_60Hz,   TV_480p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_480i_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_480i_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_04 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_480p_60Hz,   TV_720p_60Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_480p_60Hz,   TV_1080i_60Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_01 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_576i_50Hz,   TV_576p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_576i_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_576i_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_09 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_576p_50Hz,   TV_720p_50Hz,   0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iRGB444, DOUBLE,EXT, 0),   TV_576p_50Hz,   TV_1080i_50Hz,  0x000,  0x000,   0x000,    0x000}, /* VID_F_06 */
++    {PKBYTE(iINVALID,DOUBLE,EMB, 0),   TV_INVALID,     TV_INVALID,     0x000,  0x000,   0x000,    0x000}  /* EndTable */
++};
++
++
++/*============================================================================*/
++/*                         ENUM OR TYPE DEFINITIONS                           */
++/*============================================================================*/
++/* Enum listing all the type of colorimetry */
++typedef enum
++{
++    TMDL_HDMITX_COLORIMETRY_NO_DATA  = 0,
++    TMDL_HDMITX_COLORIMETRY_ITU601   = 1,
++    TMDL_HDMITX_COLORIMETRY_ITU709   = 2,
++    TMDL_HDMITX_COLORIMETRY_EXTENDED = 3
++} tmdlHdmiTxColorimetry_t;
++
++/* Possible states of the state machine */
++typedef enum
++{
++    STATE_NOT_INITIALIZED,  /**< Driver is not initialized */
++    STATE_INITIALIZED,      /**< Driver is initialized */
++    STATE_UNPLUGGED,        /**< Receiver device not connected */
++    STATE_PLUGGED,          /**< Receiver device connected, clock lock */
++    STATE_EDID_AVAILABLE    /**< Managed to read receiver's EDID */
++} tmdlHdmiTxDriverState_t;
++
++/* revocation list structure */
++typedef struct
++{
++    UInt8*                      pList;
++    UInt32                      length;
++} revocationList_t;
++
++
++/* unit configuration structure */
++typedef struct
++{
++    Bool                        opened;					/**< Is unit instanciated ? */
++    Bool                        hdcpEnable;				/**< Is HDCP enabled ? */
++    tmdlHdmiTxHdcpOptions_t     hdcpOptions;			/**< HDCP options */
++    Bool                        repeaterEnable;			/**< Is repeater enabled ? */
++    Bool                        simplayHd;				/**< Enable simplayHD support */
++    tmdlHdmiTxDeviceVersion_t   deviceVersion;			/**< Version of the HW device */
++    UInt8                       *pEdidBuffer;			/**< Pointer to raw EDID data */
++    UInt32                      edidBufferSize; 		/**< Size of buffer for raw EDID data */
++    tmdlHdmiTxIWTaskHandle_t    commandTaskHandle;		/**< Handle of the command task associated to this unit */
++    tmdlHdmiTxIWQueueHandle_t   queueHandle;			/**< Handle of the message queue associated to this unit */
++	tmdlHdmiTxIWTaskHandle_t	hdcpTaskHandle;			/**< Handle of the hdcp check task associated to this unit */
++    tmdlHdmiTxDriverState_t     state;					/**< Current state of the driver */
++    ptmdlHdmiTxCallback_t       pCallback;				/**< Data callback */
++    revocationList_t            revocationList;         /**< Revolation List */
++} unitConfig_t;
++
++
++/* Instance status */
++
++/* Video information structure */
++typedef struct _tmdlHdmiTxVideoInfo_t
++{
++    Bool                        videoMuteState; /* Video mute state: on/off */
++    tmdlHdmiTxVideoInConfig_t   videoInConfig;  /* Video input configuration */
++    tmdlHdmiTxVideoOutConfig_t  videoOutConfig; /* Video output configuration */
++} tmdlHdmiTxVideoInfo_t, *ptmdlHdmiTxVideoInfo_t;
++
++/* Audio information structure */
++typedef struct _tmdlHdmiTxAudioInfo_t
++{
++    Bool                        audioMuteState; /* Audio mute state: on/off */
++    tmdlHdmiTxAudioInConfig_t   audioInCfg;     /* Audio input configuration */
++} tmdlHdmiTxAudioInfo_t, *ptmdlHdmiTxAudioInfo_t;
++
++/* Event state structure */
++typedef struct _tmdlHdmiTxEventState_t
++{
++    tmdlHdmiTxEvent_t       event;  /* Event */
++    tmdlHdmiTxEventStatus_t status; /* Event status: enabled or disabled */
++} tmdlHdmiTxEventState_t, *ptmdlHdmiTxEventState_t;
++
++/* Color bars state structure */
++typedef struct _tmdlHdmiTxColBarState_t
++{
++    Bool disableColorBarOnR0;               /* To be able to disable colorBar on R0*/
++    Bool hdcpColbarChange;                  /* Used to auto-reset colour bars */
++    Bool hdcpEncryptOrT0;                   /* True when ENCRYPT or T0 interrupt */
++    Bool hdcpSecureOrT0;                    /* True when BKSV secure or T0 */
++    Bool inOutFirstSetDone;                 /* API tmdlHdmiTxSetInputOutput call at least one time*/
++    Bool colorBarOn;                        
++    Bool changeColorBarNow;
++} tmdlHdmiTxColBarState_t, *ptmdlHdmiTxColBarState_t;
++
++/* Gamut state structure */
++typedef struct _tmdlHdmiTxGamutState_t
++{
++    Bool  gamutOn;                                      /* Gamut status : able or disable */
++    UInt8 gamutBufNum;                                  /* Numero of the buffer used for Gamut metadata (0 or 1) */
++    tmdlHdmiTxExtColorimetry_t wideGamutColorSpace;     /* Store extended colorimetry */
++    Bool  extColOn;                                     /* extended colorimetry status : enabled or disabled */
++    tmdlHdmiTxYCCQR_t          yccQR;                   /* Store YCC quantisation range */
++} tmdlHdmiTxGamutState_t, *ptmdlHdmiTxGamutState_t;
++
++
++/* instance status structure */
++typedef struct
++{
++    ptmdlHdmiTxVideoInfo_t      pVideoInfo;     /* Video information: current mode and format... */
++    ptmdlHdmiTxAudioInfo_t      pAudioInfo;     /* Audio information: current mode and format... */
++    ptmdlHdmiTxEventState_t     pEventState;    /* Event state: enabled or disabled */
++    ptmdlHdmiTxColBarState_t    pColBarState;   /* Color bars state */
++    ptmdlHdmiTxGamutState_t     pGamutState;    /* Gamut state */
++} instanceStatus_t;
++
++/*============================================================================*/
++/*                         FUNCTION PROTOTYPES                                */
++/*============================================================================*/
++
++
++/******************************************************************************
++    \brief This function allows to the main driver to retrieve its
++           configuration parameters.
++
++    \param pConfig Pointer to the config structure
++
++    \return The call result:
++            - TM_OK: the call was successful
++            - TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER: the unit number is wrong or
++              the receiver instance is not initialised
++            - TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS: an input parameter is
++              inconsistent
++
++******************************************************************************/
++tmErrorCode_t dlHdmiTxGetConfig
++(
++    tmUnitSelect_t                  unit,
++    tmdlHdmiTxDriverConfigTable_t   *pConfig
++);
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMDLHDMITX_LOCAL_H */
++
++/*============================================================================*/
++/*                               END OF FILE                                  */
++/*============================================================================*/
+diff --git a/drivers/video/nxp/inc/tmFlags.h b/drivers/video/nxp/inc/tmFlags.h
+new file mode 100755
+index 0000000..deabca6
+--- /dev/null
++++ b/drivers/video/nxp/inc/tmFlags.h
+@@ -0,0 +1,237 @@
++/*  MoReUse 2002-09-13 Continuus Version 2                                      */
++/*                                                                              */
++/* Changes: made ansi compliant                                                 */
++/*--------------------------------------------------------------------------    */
++ /* (C) Copyright 2002 Koninklijke Philips Electronics N.V., All Rights Reserved*/
++ /*                                                                             */
++ /* This source code and any compilation or derivative thereof is the sole      */
++ /* property of Philips Corporation and is provided pursuant to a Software      */
++ /* License Agreement.  This code is the proprietary information of             */
++ /* Philips Corporation and is confidential in nature.  Its use and             */
++ /* dissemination by any party other than Philips Corporation is strictly       */
++ /* limited by the confidential information provisions of the Agreement         */
++ /* referenced above.                                                           */
++ /*-------------------------------------------------------------------------    */
++ /* FILENAME:     tmFlags.h                                                     */
++ /*                                                                             */
++ /* DESCRIPTION:  Platform dependent build flags (typically generated by the    */
++ /*               SDE build process if it doesn't already exist).               */
++ /*                                                                             */
++ /* DOCUMENT REF: DVP Build Process Specification                               */
++ /*                                                                             */
++ /* NOTES:        This file defines the TMFL_xxx build flags configuration.     */
++ /*               It does not include specific component diversity flags that   */
++ /*               are defined in the component makefiles (e.g., TMFL_SCOPE      */
++ /*               defined in BSL board files)                                   */
++ /*                                                                             */
++ /*               This file is based on SDE Version 1.2 generated output.       */
++ /*-------------------------------------------------------------------------    */
++ /*                                                                             */
++ #ifndef TM_FLAGS_H
++ #define TM_FLAGS_H
++
++/* Configurable build flags                                                     */
++/* NOTE: The following flags are configurable (typically generated by SDE       */
++/*          based on _TMXXX build environment variables).  See individual flags */
++/*         for comments about the settings and consistency requirements.        */
++
++/* TMFL_BUILD_VERSION: <Major>.<Minor>.<BuildNumber> as decimal digits. This    */
++/*   number is product/release dependent and not standardized as of now.        */
++/*#define TMFL_BUILD_VERSION            00.01.00*/
++
++/* RIDE tool does not support . in define value */
++/* TMFL_BUILD_VERSION is not used to specify neither TDA9975_SW version not TDA9983_SW version */ 
++#define TMFL_BUILD_VERSION            00
++
++/* TMFL_CPU: CPU type/model numbers: (TMFL_CPU_TYPE_XXX | TMFL_CPU_MODEL_XXX).  */
++/*   Example: (TMFL_CPU_TYPE_X86 | TMFL_CPU_MODEL_I486) or (TMFL_CPU_I486) for  */
++/*   an x86 i486 CPU.                                                           */
++ #define TMFL_CPU                      (TMFL_CPU_TYPE_X86 | TMFL_CPU_MODEL_I486)
++
++/* TMFL_ENDIAN: CPU endianness: <TMFL_ENDIAN_BIG | TMFL_ENDIAN_LITTLE>          */
++ #define TMFL_ENDIAN                   (TMFL_ENDIAN_LITTLE)
++
++/* TMFL_OS: Operating system type/version where the version number should be    */
++/*   included if defined: (TMFL_OS_<TTT>[VVV]).  Example: TMFL_OS_PSOS250       */
++/*   indicates that the target OS is pSOS Version 2.50.                         */ 
++ #define TMFL_OS                       (TMFL_OS_NULLOS)
++
++/* TMFL_CPU_IS_XXX: These are boolean flags that reflects the CPU type and      */
++/*   must be consistent with the TMFL_CPU setting (i.e., if TMFL_CPU =          */
++/*   TMFL_CPU_I486, then TMFL_CPU_IS_X86 = 1) and all other TMFL_CPU_IS_XXX     */
++/*	 flags are 0.                                                               */
++ #define TMFL_CPU_IS_X86               1
++ #define TMFL_CPU_IS_MIPS              0
++ #define TMFL_CPU_IS_HP                0
++ #define TMFL_CPU_IS_TM                0
++ #define TMFL_CPU_IS_ARM               0
++ #define TMFL_CPU_IS_REAL              0
++
++/* TMFL_OS_IS_XXX: These are boolean flags that reflects the OS type and        */
++/*   must be consistent with the TMFL_OS setting (i.e., if TMFL_OS =            */
++/*   TMFL_OS_PSOS250, then TMFL_OS_IS_PSOS = 1) and all other TMFL_OS_IS_XXX    */
++/*   flags are 0.                                                               */
++ #define TMFL_OS_IS_BTM                0
++ #define TMFL_OS_IS_CE                 0
++ #define TMFL_OS_IS_NT                 0
++ #define TMFL_OS_IS_PSOS               0
++ #define TMFL_OS_IS_NULLOS             1
++ #define TMFL_OS_IS_ECOS               0
++ #define TMFL_OS_IS_VXWORKS            0
++ #define TMFL_OS_IS_MTOS               0
++
++
++/* Non-configurable constants                                                   */
++/* NOTE: These values do not change and should not be modified !                */
++ #define TMFL_CPU_TYPE_MASK            0xffff0000
++ #define TMFL_CPU_TYPE_X86             0x00010000
++ #define TMFL_CPU_TYPE_MIPS            0x00020000
++ #define TMFL_CPU_TYPE_TM              0x00030000
++ #define TMFL_CPU_TYPE_HP              0x00040000
++ #define TMFL_CPU_TYPE_ARM             0x00050000
++ #define TMFL_CPU_TYPE_REAL            0x00060000
++ #define TMFL_CPU_MODEL_MASK           0x0000ffff
++ #define TMFL_CPU_MODEL_I486           0x00000001
++ #define TMFL_CPU_MODEL_R3940          0x00000002
++ #define TMFL_CPU_MODEL_R4300          0x00000003
++ #define TMFL_CPU_MODEL_TM1100         0x00000004
++ #define TMFL_CPU_MODEL_TM1300         0x00000005
++ #define TMFL_CPU_MODEL_TM32           0x00000006
++ #define TMFL_CPU_MODEL_HP             0x00000007
++ #define TMFL_CPU_MODEL_R4640          0x00000008
++ #define TMFL_CPU_MODEL_ARM7           0x00000009
++ #define TMFL_CPU_MODEL_ARM920T        0x0000000a
++ #define TMFL_CPU_MODEL_ARM940T        0x0000000b
++ #define TMFL_CPU_MODEL_ARM10          0x0000000c
++ #define TMFL_CPU_MODEL_STRONGARM      0x0000000d
++ #define TMFL_CPU_MODEL_RD24120        0x0000000e
++ #define TMFL_CPU_MODEL_ARM926EJS      0x0000000f
++ #define TMFL_CPU_MODEL_ARM946         0x00000010
++ #define TMFL_CPU_MODEL_R1910          0x00000011
++ #define TMFL_CPU_MODEL_R4450          0x00000012
++ #define TMFL_CPU_MODEL_TM3260         0x00000013
++ #define TMFL_ENDIAN_BIG               1
++ #define TMFL_ENDIAN_LITTLE            0
++ #define TMFL_OS_MASK                  0xff000000
++ #define TMFL_OS_VERSION_MASK          0x00ffffff
++ #define TMFL_OS_BTM                   0x00000000
++ #define TMFL_OS_CE                    0x01000000
++ #define TMFL_OS_CE212                 0x01020102
++ #define TMFL_OS_CE300                 0x01030000
++ #define TMFL_OS_NT                    0x02000000
++ #define TMFL_OS_NT4                   0x02040000
++ #define TMFL_OS_PSOS                  0x03000000
++ #define TMFL_OS_PSOS250               0x03020500
++ #define TMFL_OS_PSOS200               0x03020000
++ #define TMFL_OS_NULLOS                0x04000000
++ #define TMFL_OS_ECOS                  0x05000000
++ #define TMFL_OS_VXWORKS               0x06000000
++ #define TMFL_OS_MTOS                  0x07000000
++ #define TMFL_SCOPE_SP                 0
++ #define TMFL_SCOPE_MP                 1
++ #define TMFL_REL_ASSERT               0x00000002
++ #define TMFL_REL_DEBUG                0x00000001
++ #define TMFL_REL_RETAIL               0x00000000
++ #define TMFL_CPU_I486                 0x00010001
++ #define TMFL_CPU_R3940                0x00020002
++ #define TMFL_CPU_R4300                0x00020003
++ #define TMFL_CPU_TM1100               0x00030004
++ #define TMFL_CPU_TM1300               0x00030005
++ #define TMFL_CPU_TM32                 0x00030006
++ #define TMFL_CPU_HP                   0x00040007
++ #define TMFL_CPU_R4640                0x00020008
++ #define TMFL_CPU_ARM7                 0x00050009
++ #define TMFL_CPU_ARM920T              0x0005000a
++ #define TMFL_CPU_ARM940T              0x0005000b
++ #define TMFL_CPU_ARM10                0x0005000c
++ #define TMFL_CPU_STRONGARM            0x0005000d
++ #define TMFL_CPU_RD24120              0x0006000e
++ #define TMFL_CPU_ARM926EJS            0x0005000f
++ #define TMFL_CPU_ARM946               0x00050010
++ #define TMFL_CPU_R1910                0x00020011
++ #define TMFL_CPU_R4450                0x00020012
++ #define TMFL_CPU_TM3260               0x00030013
++ #define TMFL_MODE_KERNEL              1
++ #define TMFL_MODE_USER                0
++
++/******************************************************************************/
++/*	Components features defines                                               */
++/******************************************************************************/
++#ifdef TMFL_TDA19988
++#	ifndef TMFL_TDA19989
++#		define TMFL_TDA19989
++#	endif /* TMFL_TDA19989 */
++#	define TMFL_RGB_DDR_12BITS
++#	define TMFL_HDCP_OPTIMIZED_POWER
++#endif /* TMFL_TDA19988 */
++
++#ifdef TMFL_TDA19989
++#	ifndef TMFL_TDA9989
++#		define TMFL_TDA9989
++#		define SUPPORT_3D_FP
++#	endif /* TMFL_TDA9989 */
++#endif /* TMFL_TDA19989 */
++/******************************************************************************/
++/* Preprocessor checks for invalid settings (if file is manually modified)    */
++/******************************************************************************/
++/*                                                                            */
++
++/* Check if TMFL_CPU flag changed from its default setting.                   */
++#if     (TMFL_CPU == (TMFL_CPU_TYPE_MASK | TMFL_CPU_MODEL_MASK))
++#error  ERROR: TMFL_CPU must be set (TMFL_CPU_TYPE_XXX | TMFL_CPU_MODEL_XXX) !
++#endif
++
++/* Check if TMFL_ENDIAN flag setting is valid.                                */
++#if     ((TMFL_ENDIAN != TMFL_ENDIAN_BIG) && (TMFL_ENDIAN != TMFL_ENDIAN_LITTLE))
++#error  ERROR: TMFL_ENDIAN must be set to a valid TMFL_ENDIAN_XXX value !
++#endif
++
++/* Check if TMFL_OS flag changed from its default setting.                    */
++#if     (TMFL_OS == (TMFL_OS_MASK | TMFL_OS_VERSION_MASK))
++#error  ERROR: TMFL_OS must be set to a valid value (TMFL_OS_<TYPE>[<VERSION>]) !
++#endif
++
++/* The TMFL_CPU_IS_XXX is a Boolean; one and only one flag can be true (=1).  */
++#if     ((TMFL_CPU_IS_X86 + TMFL_CPU_IS_MIPS + TMFL_CPU_IS_TM + TMFL_CPU_IS_HP + TMFL_CPU_IS_ARM + TMFL_CPU_IS_REAL) != 1)
++#error  ERROR: One or more TMFL_CPU_IS_XXX values are incorrect or missing !
++#endif
++
++/* TMFL_CPU and TMFL_CPU_IS_XXX must be consistent                            */
++#if     (((TMFL_CPU & TMFL_CPU_TYPE_MASK) == TMFL_CPU_TYPE_X86)  && (TMFL_CPU_IS_X86 != 1))
++#error  ERROR: Inconsistent TMFL_CPU and TMFL_CPU_IS_X86 settings !
++#elif   (((TMFL_CPU & TMFL_CPU_TYPE_MASK) == TMFL_CPU_TYPE_MIPS) && (TMFL_CPU_IS_MIPS != 1))
++#error  ERROR: Inconsistent TMFL_CPU and TMFL_CPU_IS_MIPS settings !
++#elif   (((TMFL_CPU & TMFL_CPU_TYPE_MASK) == TMFL_CPU_TYPE_TM)   && (TMFL_CPU_IS_TM != 1))
++#error  ERROR: Inconsistent TMFL_CPU and TMFL_CPU_IS_TM settings !
++#elif   (((TMFL_CPU & TMFL_CPU_TYPE_MASK) == TMFL_CPU_TYPE_HP)   && (TMFL_CPU_IS_HP != 1))
++#error  ERROR: Inconsistent TMFL_CPU and TMFL_CPU_IS_HP settings !
++#elif   (((TMFL_CPU & TMFL_CPU_TYPE_MASK) == TMFL_CPU_TYPE_ARM)  && (TMFL_CPU_IS_ARM != 1))
++#error  ERROR: Inconsistent TMFL_CPU and TMFL_CPU_IS_ARM settings !
++#elif   (((TMFL_CPU & TMFL_CPU_TYPE_MASK) == TMFL_CPU_TYPE_REAL) && (TMFL_CPU_IS_REAL != 1))
++#error  ERROR: Inconsistent TMFL_CPU and TMFL_CPU_IS_REAL settings !
++#endif /* (((TMFL_CPU & TMFL_CPU_TYPE_MASK) == TMFL_CPU_TYPE_X86) && ...      */
++
++/* The TMFL_OS_IS_XXX is a Boolean; one and only one flag can be true (=1).   */
++#if     ((TMFL_OS_IS_BTM + TMFL_OS_IS_CE + TMFL_OS_IS_NT + TMFL_OS_IS_PSOS + TMFL_OS_IS_NULLOS + TMFL_OS_IS_ECOS + TMFL_OS_IS_VXWORKS + TMFL_OS_IS_MTOS) != 1)
++#error  ERROR: One or more TMFL_OS_IS_XXX values are incorrect or missing !
++#endif
++
++#if     (((TMFL_OS & TMFL_OS_MASK) == TMFL_OS_BTM)     && (TMFL_OS_IS_BTM != 1))
++#error  ERROR: Inconsistent TMFL_OS and TMFL_OS_IS_BTM settings !
++#elif   (((TMFL_OS & TMFL_OS_MASK) == TMFL_OS_CE)      && (TMFL_OS_IS_CE != 1))
++#error  ERROR: Inconsistent TMFL_OS and TMFL_OS_IS_CE settings !
++#elif   (((TMFL_OS & TMFL_OS_MASK) == TMFL_OS_NT)      && (TMFL_OS_IS_NT != 1))
++#error  ERROR: Inconsistent TMFL_OS and TMFL_OS_IS_NT settings !
++#elif   (((TMFL_OS & TMFL_OS_MASK) == TMFL_OS_PSOS)    && (TMFL_OS_IS_PSOS != 1))
++#error  ERROR: Inconsistent TMFL_OS and TMFL_OS_IS_PSOS settings !
++#elif   (((TMFL_OS & TMFL_OS_MASK) == TMFL_OS_NULLOS)  && (TMFL_OS_IS_NULLOS != 1))
++#error  ERROR: Inconsistent TMFL_OS and TMFL_OS_IS_NULLOS settings !
++#elif   (((TMFL_OS & TMFL_OS_MASK) == TMFL_OS_ECOS)    && (TMFL_OS_IS_ECOS != 1))
++#error  ERROR: Inconsistent TMFL_OS and TMFL_OS_IS_ECOS settings !
++#elif   (((TMFL_OS & TMFL_OS_MASK) == TMFL_OS_VXWORKS) && (TMFL_OS_IS_VXWORKS != 1))
++#error  ERROR: Inconsistent TMFL_OS and TMFL_OS_IS_VXWORKS settings !
++#elif   (((TMFL_OS & TMFL_OS_MASK) == TMFL_OS_MTOS)    &&  (TMFL_OS_IS_MTOS != 1))
++#error  ERROR: Inconsistent TMFL_OS and TMFL_OS_IS_MTOS settings !
++#endif /* (((TMFL_OS & TMFL_OS_MASK) == TMFL_OS_XX) && (TMFL_OS_IS_XX != 1))  */
++
++#endif   /* TM_FLAGS_H                                        */
+diff --git a/drivers/video/nxp/inc/tmNxCompId.h b/drivers/video/nxp/inc/tmNxCompId.h
+new file mode 100755
+index 0000000..2302901
+--- /dev/null
++++ b/drivers/video/nxp/inc/tmNxCompId.h
+@@ -0,0 +1,1743 @@
++/* -------------------------------------------------------------------------- */
++/* (C) Copyright 2000-2005              Koninklijke Philips Electronics N.V., */
++/*     All rights reserved                                                    */
++/*                                                                            */
++/* This source code and any compilation or derivative thereof is the          */
++/* proprietary information of Konlinklijke Philips Electronics N.V. and is    */
++/* Confidential in nature.                                                    */
++/* Under no circumstances is this software to be exposed to or placed under an*/
++/* Open Source License of any type without the expressed written permission of*/
++/* Koninklijke Philips Electronics N.V.                                       */
++/* -------------------------------------------------------------------------- */
++/*                                                                            */
++/* MoReUse - 2005-10-24   Version 118                                         */
++/*                                                                            */
++/* Added:                                                                     */
++/*    CID_AACPENC                                                             */
++/*                                                                            */
++/*                                                                            */
++/* Changed:                                                                   */
++/*                                                                            */
++/*                                                                            */
++/*                                                                            */
++/* Removed:                                                                   */
++/*                                                                            */
++/*                                                                            */
++/*                                                                            */
++/* General Error Codes Added                                                  */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++/* FILE NAME:    tmNxCompId.h                                                 */
++/*                                                                            */
++/* DESCRIPTION:  This header file identifies the standard component           */
++/*               identifiers (CIDs) and interface identifiers (IID) for       */
++/*               Nexperia platforms.                                          */
++/*               The objective of these identifiers is to enable unique       */
++/*               identification of software components and interfaces.        */
++/*               In addition, standard status values are also defined to make */
++/*               determination of typical error cases much easier.            */
++/*                                                                            */
++/*               Functional errors are not real errors in the sense of        */
++/*               unexpected behaviour but are part of the normal communication*/
++/*               between a client an a server component. They are linked to   */
++/*               an interface, rather than to a component. All implementations*/
++/*               of an interface must have the same behaviour with respect to */
++/*               functional errors. Functional erros are all positive         */
++/*               One global functional error is defined:  TM_OK 0x00000000    */
++/*                                                                            */
++/*               Non-functional errors (all negative numbers) indicate        */
++/*               unexpected behaviour. They are linked to concrete component  */
++/*               implementations                                              */
++/*                                                                            */
++/*               NOTE: The current implementation is different from the prev. */
++/*                     component identifier implementation, based on classes, */
++/*                     types and layers. However, the new system is backward  */
++/*                     compatitible with the old implementation.              */
++/*                                                                            */
++/*               tmNxCompId.h defines a number of general error codes that can*/
++/*               be used by all components. These error codes are concatenated*/
++/*               to the CID or IID value in the local component headerfile of */
++/*               the component that wants to (re-)use this general error code */
++/*               General error codes can be used for both functional and      */
++/*               non-functional errors. They should only be used if they      */
++/*               semantically fully match (if not, defined a new component or */
++/*               interface specific error code.                               */
++/*                                                                            */
++/* General Rules:                                                             */
++/*               A return value has a length of 32 bits. At the binary level, */
++/*               1 bit indicates the component or interface flag; 16 bits are */
++/*               used for the actual component id (CID) or interface id (IID) */
++/*               and 12 bits for the return status.                           */
++/*                     The component/interface flag is bit 31.                */
++/*                     Bits 30--28 are all 0.                                 */
++/*                     The component/interface id occupies bits 27--12.       */
++/*                     The return status occupies bits 11--0.                 */
++/*                                                                            */
++/*                     +--------+-----+-------+-----------+                   */
++/*                     | flag:1 | 0:3 | id:16 | status:12 |                   */
++/*                     +--------+-----+-------+-----------+                   */
++/*                                                                            */
++/*                     Format of interface ids:                               */
++/*                                                                            */
++/*                     +-----+-----+--------+-----------+                     */
++/*                     | 0:1 | 0:3 | iid:16 | status:12 |                     */
++/*                     +-----+-----+--------+-----------+                     */
++/*                                                                            */
++/*                     Format of component ids:                               */
++/*                                                                            */
++/*                     +-----+-----+--------+-----------+                     */
++/*                     | 1:1 | 0:3 | cid:16 | status:12 |                     */
++/*                     +-----+-----+--------+-----------+                     */
++/*                                                                            */
++/*               At the macro level, we use the prefix "CID_" for component   */
++/*               ids (previous version "CID_COMP_") and "IID_" for interface  */
++/*               ids.                                                         */
++/*                                                                            */
++/*               Each component id will be used by only one component; each   */
++/*               component will have its own component id.                    */
++/*               Each interface id will be used by only one interface; each   */
++/*               interface will have its own interface id.                    */
++/*                                                                            */
++/*               In order to avoid problems when promoting a UNIQUE interface */
++/*               to a SEPARATE interface, the ranges for CIDs and IIDS must   */
++/*               not overlap.                                                 */
++/*                                                                            */
++/*               Component names and component ids have to be registered      */
++/*               together; the same applies for interface names and ids.      */
++/*                                                                            */
++/*           NOTE about Compatibility                                         */
++/*               In the previous implementation the first four bits were      */
++/*               reserved for class, and there were separate fields for       */
++/*               type and tag, like this:                                     */
++/*                                                                            */
++/*                     +---------+--------+-------+---------+-----------+     */
++/*                     | class:4 | type:4 | tag:8 | layer:4 | status:12 |     */
++/*                     +---------+--------+-------+---------+-----------+     */
++/*                                                                            */
++/*               The values 0 or 8 are not valid classes, and this fact       */
++/*               can be used to distinguish a new-style IID (class == 0),     */
++/*               a new-style CID (class == 8), and an old-style CID           */
++/*               (otherwise).                                                 */
++/*                                                                            */
++/*           NOTE about error codes                                           */
++/*               The general error codes use the range 0x001 to 0x7FF.        */
++/*               The component specific error codes are defined in the        */
++/*               local component header file and can use 0x800 to 0xFFF.      */
++/*               TM_OK has the value 0x00000000.                              */
++/*               The proposed error code ranges (general and specific) are    */
++/*               the same for functional and non-functional errors.           */
++/*                                                                            */
++/*               The previously defined ranges for external customers,        */
++/*               assert errors and fatal errors have been dropped.            */
++/*               The previously defined range for general errors started      */
++/*               at 0x000 instead of 0x001                                    */
++/*                                                                            */
++/* DOCUMENT REF: Nexperia/MoReUse Naming Conventions                          */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++
++#ifndef TMNXCOMPID_H
++#define TMNXCOMPID_H
++
++/* -------------------------------------------------------------------------- */
++/*                                                                            */
++/*   Standard include files:                                                  */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++#include "tmNxTypes.h"
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++/* -------------------------------------------------------------------------- */
++/*                                                                            */
++/*    Types and defines:                                                      */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++
++/* -------------------------------------------------------------------------- */
++/*                                                                            */
++/*   TM_OK is the 32 bit global status value used by all Nexperia components  */
++/*   to indicate successful function/operation status.  If a non-zero value is*/
++/*   returned as status, it should use the component ID formats defined.      */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++#define TM_OK                     0U         /* Global success return status   */
++
++/* -------------------------------------------------------------------------- */
++/*                                                                            */
++/*     General Defines                                                        */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++#define CID_IID_FLAG_BITSHIFT    31
++#define CID_ID_BITSHIFT          12
++#define IID_ID_BITSHIFT          12
++
++#define CID_FLAG                 (0x1U << CID_IID_FLAG_BITSHIFT)
++#define IID_FLAG                 (0x0U << CID_IID_FLAG_BITSHIFT)
++
++#define CID_ID(number)           ((number) << CID_ID_BITSHIFT)
++#define CID_ID_BITMASK           (0x7FFFFU  << CID_ID_BITSHIFT)
++
++#define IID_ID(number)           ((number) << IID_ID_BITSHIFT)
++#define IID_ID_BITMASK           (0x7FFFFU  << IID_ID_BITSHIFT)
++
++/* -------------------------------------------------------------------------- */
++/*                                                                            */
++/*     Definition of the interface IDs                                        */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++#define IID_IENUMUNKNOWN            (IID_ID(0x001U) | IID_FLAG)
++#define IID_IBIND                   (IID_ID(0x002U) | IID_FLAG)
++#define IID_IBINDINFO               (IID_ID(0x003U) | IID_FLAG)
++#define IID_IMEM                    (IID_ID(0x004U) | IID_FLAG)
++#define IID_IUNKNOWN                (IID_ID(0x005U) | IID_FLAG)
++#define IID_IIC                     (IID_ID(0x006U) | IID_FLAG)
++#define IID_ACHAN                   (IID_ID(0x007U) | IID_FLAG)
++#define IID_AFEAT                   (IID_ID(0x008U) | IID_FLAG)
++#define IID_AMIX                    (IID_ID(0x009U) | IID_FLAG)
++#define IID_ANAADEC                 (IID_ID(0x00aU) | IID_FLAG)
++#define IID_ANAVENC                 (IID_ID(0x00bU) | IID_FLAG)
++#define IID_ANAVENCRYPT             (IID_ID(0x00cU) | IID_FLAG)
++#define IID_ANAVDEC                 (IID_ID(0x00dU) | IID_FLAG)
++#define IID_BBARDETEXT              (IID_ID(0x00eU) | IID_FLAG)
++#define IID_BLEVELDETEXT            (IID_ID(0x00fU) | IID_FLAG)
++#define IID_BLEVELMODEXT            (IID_ID(0x010U) | IID_FLAG)
++#define IID_BSLSPDI                 (IID_ID(0x011U) | IID_FLAG)
++#define IID_BSLSPDO                 (IID_ID(0x012U) | IID_FLAG)
++#define IID_BSL_AI                  (IID_ID(0x013U) | IID_FLAG)
++#define IID_BSL_AO                  (IID_ID(0x014U) | IID_FLAG)
++#define IID_BSL_AVI                 (IID_ID(0X015U) | IID_FLAG)
++#define IID_BSL_AVO                 (IID_ID(0x016U) | IID_FLAG)
++#define IID_BSL_EEPROM              (IID_ID(0X017U) | IID_FLAG)
++#define IID_BSL_IDE                 (IID_ID(0X018U) | IID_FLAG)
++#define IID_BSL_NANDFLASH           (IID_ID(0X019U) | IID_FLAG)
++#define IID_BSL_NORFLASH            (IID_ID(0X01aU) | IID_FLAG)
++#define IID_BSL_PARPORT             (IID_ID(0X01bU) | IID_FLAG)
++#define IID_BSL_RTC                 (IID_ID(0X01cU) | IID_FLAG)
++#define IID_COLENH                  (IID_ID(0x01dU) | IID_FLAG)
++#define IID_COLENHEXT               (IID_ID(0x01eU) | IID_FLAG)
++#define IID_CONNMGR                 (IID_ID(0x01fU) | IID_FLAG)
++#define IID_CRT                     (IID_ID(0x020U) | IID_FLAG)
++#define IID_CTI                     (IID_ID(0X021U) | IID_FLAG)
++#define IID_CTIEXT                  (IID_ID(0X022U) | IID_FLAG)
++#define IID_DIGADEC                 (IID_ID(0X023U) | IID_FLAG)
++#define IID_DIGVDEC                 (IID_ID(0X024U) | IID_FLAG)
++#define IID_DMX                     (IID_ID(0X025U) | IID_FLAG)
++#define IID_DNR                     (IID_ID(0X026U) | IID_FLAG)
++#define IID_DNREXT                  (IID_ID(0X027U) | IID_FLAG)
++#define IID_DVBSUBTDEC              (IID_ID(0X028U) | IID_FLAG)
++#define IID_FATERR                  (IID_ID(0X029U) | IID_FLAG)
++#define IID_FREND                   (IID_ID(0X02aU) | IID_FLAG)
++#define IID_GAMMAEXT                (IID_ID(0X02bU) | IID_FLAG)
++#define IID_HISTOMEASEXT            (IID_ID(0X02cU) | IID_FLAG)
++#define IID_HISTOMODEXT             (IID_ID(0X02dU) | IID_FLAG)
++#define IID_MML                     (IID_ID(0X02eU) | IID_FLAG)
++#define IID_NOISEESTEXT             (IID_ID(0X02fU) | IID_FLAG)
++#define IID_OSAL                    (IID_ID(0X030U) | IID_FLAG)
++#define IID_PIPSTORE                (IID_ID(0X031U) | IID_FLAG)
++#define IID_SCANRATECONV            (IID_ID(0X032U) | IID_FLAG)
++#define IID_SCANRATECONVEXT         (IID_ID(0X033U) | IID_FLAG)
++#define IID_SHARPENH                (IID_ID(0X034U) | IID_FLAG)
++#define IID_SHARPENHEXT             (IID_ID(0X035U) | IID_FLAG)
++#define IID_SHARPMEASEXT            (IID_ID(0X036U) | IID_FLAG)
++#define IID_SPDIFIN                 (IID_ID(0X037U) | IID_FLAG)
++#define IID_SPDIFOUT                (IID_ID(0X038U) | IID_FLAG)
++#define IID_SPEAKER                 (IID_ID(0X039U) | IID_FLAG)
++#define IID_STCDEC                  (IID_ID(0X03aU) | IID_FLAG)
++#define IID_STREAMINJ               (IID_ID(0X03bU) | IID_FLAG)
++#define IID_SYNCTAG                 (IID_ID(0X03cU) | IID_FLAG)
++#define IID_TSSACOM                 (IID_ID(0X03dU) | IID_FLAG)
++#define IID_TXTDEC                  (IID_ID(0X03eU) | IID_FLAG)
++#define IID_UTILCRYPT               (IID_ID(0X03fU) | IID_FLAG)
++#define IID_UVBWDETEXT              (IID_ID(0X040U) | IID_FLAG)
++#define IID_VBIINSERT               (IID_ID(0X041U) | IID_FLAG)
++#define IID_VBISLICE                (IID_ID(0X042U) | IID_FLAG)
++#define IID_VDCC                    (IID_ID(0X043U) | IID_FLAG)
++#define IID_VDSTSCAN                (IID_ID(0X044U) | IID_FLAG)
++#define IID_VFEAT                   (IID_ID(0X045U) | IID_FLAG)
++#define IID_VMIX                    (IID_ID(0X046U) | IID_FLAG)
++#define IID_VSCALEEXT               (IID_ID(0X047U) | IID_FLAG)
++#define IID_VSRCPROP                (IID_ID(0X048U) | IID_FLAG)
++#define IID_VSRCSCANPROP            (IID_ID(0X049U) | IID_FLAG)
++#define IID_GENI2C                  (IID_ID(0X04aU) | IID_FLAG)
++#define IID_PLFINSTVIN              (IID_ID(0X04bU) | IID_FLAG)
++#define IID_PLFINSTAIN              (IID_ID(0X04cU) | IID_FLAG)
++#define IID_PLFINSTAOUT             (IID_ID(0X04dU) | IID_FLAG)
++#define IID_PLFINSTGFX              (IID_ID(0X04eU) | IID_FLAG)
++#define IID_CONNMGRATV              (IID_ID(0X04fU) | IID_FLAG)
++#define IID_IAMALIVE                (IID_ID(0X050U) | IID_FLAG)
++#define IID_BBARDET                 (IID_ID(0X051U) | IID_FLAG)
++#define IID_CONTRRESEXT             (IID_ID(0X052U) | IID_FLAG)
++#define IID_NOISEMEAS               (IID_ID(0X053U) | IID_FLAG)
++#define IID_SHARPMEAS               (IID_ID(0X054U) | IID_FLAG)
++#define IID_HISTOMOD                (IID_ID(0X055U) | IID_FLAG)
++#define IID_ANTIAGING               (IID_ID(0X056U) | IID_FLAG)
++#define IID_AMBIENTLEVEL            (IID_ID(0X057U) | IID_FLAG)
++#define IID_HAD_DRV_IIC             (IID_ID(0X058U) | IID_FLAG)
++#define IID_HAD_DRV_GPIO            (IID_ID(0X059U) | IID_FLAG)
++#define IID_HAD_DRV_CSM             (IID_ID(0X05aU) | IID_FLAG)
++#define IID_DRIVERHAL               (IID_ID(0X05bU) | IID_FLAG)
++#define IID_MUTISTR                 (IID_ID(0X05cU) | IID_FLAG)
++#define IID_MUTIVEC                 (IID_ID(0X05dU) | IID_FLAG)
++#define IID_MUTISTRX                (IID_ID(0X05eU) | IID_FLAG)
++#define IID_MUTICMD                 (IID_ID(0X05fU) | IID_FLAG)
++#define IID_TASK_CONDITION          (IID_ID(0X060U) | IID_FLAG)
++#define IID_PACKET_POOL             (IID_ID(0X061U) | IID_FLAG)
++#define IID_PACKET_QUEUE            (IID_ID(0X062U) | IID_FLAG)
++#define IID_UDSDCD                  (IID_ID(0X063U) | IID_FLAG)
++#define IID_DCSS_RL                 (IID_ID(0X064U) | IID_FLAG)
++#define IID_DCSS_DD                 (IID_ID(0X065U) | IID_FLAG)
++#define IID_DCSS_GD                 (IID_ID(0X066U) | IID_FLAG)
++#define IID_DCSS_RSC                (IID_ID(0X067U) | IID_FLAG)
++#define IID_DCSS_P                  (IID_ID(0X068U) | IID_FLAG)
++#define IID_DCSS                    (IID_ID(0X069U) | IID_FLAG)
++#define IID_CC_BURST_CUTTING_AREA   (IID_ID(0X06aU) | IID_FLAG)
++#define IID_CC_CONFIGURATION        (IID_ID(0X06bU) | IID_FLAG)
++#define IID_CC_CONTROL              (IID_ID(0X06cU) | IID_FLAG)
++#define IID_CC_DEBUG                (IID_ID(0X06dU) | IID_FLAG)
++#define IID_CC_DECODER              (IID_ID(0X06eU) | IID_FLAG)
++#define IID_CC_ENCODER              (IID_ID(0X06fU) | IID_FLAG)
++#define IID_CC_HF_PROCESSING        (IID_ID(0X070U) | IID_FLAG)
++#define IID_CC_INTERFACE            (IID_ID(0X071U) | IID_FLAG)
++#define IID_CC_NATLAB               (IID_ID(0X072U) | IID_FLAG)
++#define IID_CC_PIC                  (IID_ID(0X073U) | IID_FLAG)
++#define IID_CC_WOBBLE               (IID_ID(0X074U) | IID_FLAG)
++#define IID_CC_REGISTERMAP          (IID_ID(0X075U) | IID_FLAG)
++#define IID_CC_WOBBLE_REG           (IID_ID(0X076U) | IID_FLAG)
++#define IID_CC_PIC_REG              (IID_ID(0X077U) | IID_FLAG)
++#define IID_CC_NATLAB_REG           (IID_ID(0X078U) | IID_FLAG)
++#define IID_CC_INTERFACE_REG        (IID_ID(0X079U) | IID_FLAG)
++#define IID_CC_HF_PROCESSING_REG    (IID_ID(0X07aU) | IID_FLAG)
++#define IID_CC_ENCODER_REG          (IID_ID(0X07bU) | IID_FLAG)
++#define IID_CC_DECODER_REG          (IID_ID(0X07cU) | IID_FLAG)
++#define IID_CC_DEBUG_REG            (IID_ID(0X07dU) | IID_FLAG)
++#define IID_CC_CONTROL_REG          (IID_ID(0X07eU) | IID_FLAG)
++#define IID_CC_CONFIGURATION_REG    (IID_ID(0X07fU) | IID_FLAG)
++#define IID_CC_BURST_CUTTING_AREA_REG (IID_ID(0X080U) | IID_FLAG)
++#define IID_CC_PHYSICAL_VALUES      (IID_ID(0X081U) | IID_FLAG)
++#define IID_CC_GENERAL_SETTINGS     (IID_ID(0X082U) | IID_FLAG)
++#define IID_CC_COEFFICIENTS         (IID_ID(0X083U) | IID_FLAG)
++#define IID_REMOTE_CONTROL          (IID_ID(0X084U) | IID_FLAG)
++#define IID_TUNER                   (IID_ID(0X085U) | IID_FLAG)
++#define IID_MUTITST                 (IID_ID(0X086U) | IID_FLAG)
++#define IID_CHIP_CONTEXT            (IID_ID(0X087U) | IID_FLAG)
++#define IID_API                     (IID_ID(0X088U) | IID_FLAG)
++#define IID_CHANDEC                 (IID_ID(0X089U) | IID_FLAG)
++#define IID_TUNING                  (IID_ID(0X08aU) | IID_FLAG)
++#define IID_TUNINGAFC               (IID_ID(0X08bU) | IID_FLAG)
++#define IID_TUNINGAFCNTF            (IID_ID(0X08cU) | IID_FLAG)
++#define IID_TUNINGCHAN              (IID_ID(0X08dU) | IID_FLAG)
++#define IID_TUNINGSEARCHNTF         (IID_ID(0X08eU) | IID_FLAG)
++#define IID_ID3EXTR                 (IID_ID(0X08fU) | IID_FLAG)
++#define IID_ANAAVDEM                (IID_ID(0X090U) | IID_FLAG)
++#define IID_ANAAVDEMNTF             (IID_ID(0X091U) | IID_FLAG)
++#define IID_CCEXTR                  (IID_ID(0X092U) | IID_FLAG)
++#define IID_CHANDECDVBC             (IID_ID(0X093U) | IID_FLAG)
++#define IID_CHANDECDVBS             (IID_ID(0X094U) | IID_FLAG)
++#define IID_CHANDECDVBT             (IID_ID(0X095U) | IID_FLAG)
++#define IID_CHANDECNTF              (IID_ID(0X096U) | IID_FLAG)
++#define IID_OOB                     (IID_ID(0X097U) | IID_FLAG)
++#define IID_RFAMP                   (IID_ID(0X098U) | IID_FLAG)
++#define IID_SIGSTRENGTH             (IID_ID(0X099U) | IID_FLAG)
++#define IID_SIGSTRENGTHNTF          (IID_ID(0X09aU) | IID_FLAG)
++#define IID_IMAGEDEC                (IID_ID(0X09bU) | IID_FLAG)
++#define IID_TUNINGSEARCH            (IID_ID(0X09cU) | IID_FLAG)
++#define IID_PINOBJECTS              (IID_ID(0X09dU) | IID_FLAG)
++#define IID_URLSRC                  (IID_ID(0X09eU) | IID_FLAG)
++#define IID_OSDKERNELAPP            (IID_ID(0X09fU) | IID_FLAG)         
++#define IID_OSDKERNELMEM            (IID_ID(0X0a0U) | IID_FLAG)
++#define IID_OSDKERNELOSD            (IID_ID(0X0a1U) | IID_FLAG)
++#define IID_OSDKERNELOSDCONTROL     (IID_ID(0X0a2U) | IID_FLAG)
++#define IID_RTC                     (IID_ID(0X0a3U) | IID_FLAG)
++#define IID_FS                      (IID_ID(0X0a4U) | IID_FLAG)
++#define IID_BE                      (IID_ID(0X0a5U) | IID_FLAG)
++#define IID_CD_LIB                  (IID_ID(0X0a6U) | IID_FLAG)
++#define IID_DB                      (IID_ID(0X0a7U) | IID_FLAG)
++#define IID_AVIN                    (IID_ID(0X0a8U) | IID_FLAG)
++#define IID_AVOUT                   (IID_ID(0X0a9U) | IID_FLAG)
++#define IID_INT                     (IID_ID(0X0aaU) | IID_FLAG)
++#define IID_EVT                     (IID_ID(0X0abU) | IID_FLAG)
++#define IID_DMA                     (IID_ID(0X0acU) | IID_FLAG)
++#define IID_CLK                     (IID_ID(0X0adU) | IID_FLAG)
++#define IID_VMIXBORDERPAINTER       (IID_ID(0X0aeU) | IID_FLAG)
++#define IID_CPROCTVFLOW             (IID_ID(0X0afU) | IID_FLAG)
++#define IID_VTRANTIAGING            (IID_ID(0X0b0U) | IID_FLAG)
++#define IID_VTRFADE                 (IID_ID(0X0b1U) | IID_FLAG)
++#define IID_VTRSCALE                (IID_ID(0X0b2U) | IID_FLAG)
++#define IID_VTRSTROBE               (IID_ID(0X0b3U) | IID_FLAG)
++#define IID_HDMIIN                  (IID_ID(0X0b4U) | IID_FLAG)
++#define IID_ACHANSEL                (IID_ID(0X0b5U) | IID_FLAG)
++#define IID_SSP                     (IID_ID(0X0b6U) | IID_FLAG)
++#define IID_CONNMGR_STILL           (IID_ID(0X0b7U) | IID_FLAG)
++#define IID_CONNMGR_AUDIO           (IID_ID(0X0b8U) | IID_FLAG)
++#define IID_CONNMGR_MPEG2PS         (IID_ID(0X0b9U) | IID_FLAG)
++#define IID_SPI_SD                  (IID_ID(0X0baU) | IID_FLAG)
++#define IID_DECODERHALCST           (IID_ID(0X0bbU) | IID_FLAG)
++#define IID_SOD                     (IID_ID(0X0bcU) | IID_FLAG)
++#define IID_DCSS_AA                 (IID_ID(0X0bdU) | IID_FLAG)
++#define IID_DCSS_AVI                (IID_ID(0X0beU) | IID_FLAG)
++#define IID_DCSS_BC                 (IID_ID(0X0bfU) | IID_FLAG)
++#define IID_DCSS_CLUT               (IID_ID(0X0c0U) | IID_FLAG)
++#define IID_DCSS_COL                (IID_ID(0X0c1U) | IID_FLAG)
++#define IID_DCSS_DFC                (IID_ID(0X0c2U) | IID_FLAG)
++#define IID_DCSS_DOC                (IID_ID(0X0c3U) | IID_FLAG)
++#define IID_DCSS_GIO                (IID_ID(0X0c4U) | IID_FLAG)
++#define IID_DCSS_ISD                (IID_ID(0X0c5U) | IID_FLAG)
++#define IID_DCSS_KBI                (IID_ID(0X0c6U) | IID_FLAG)
++#define IID_DCSS_OSD                (IID_ID(0X0c7U) | IID_FLAG)
++#define IID_DCSS_PIF                (IID_ID(0X0c8U) | IID_FLAG)
++#define IID_DCSS_PVI                (IID_ID(0X0c9U) | IID_FLAG)
++#define IID_DCSS_SIS                (IID_ID(0X0caU) | IID_FLAG)
++#define IID_DCSS_TIG                (IID_ID(0X0cbU) | IID_FLAG)
++#define IID_DCSS_USC                (IID_ID(0X0ccU) | IID_FLAG)
++#define IID_DCSS_VCR                (IID_ID(0X0cdU) | IID_FLAG)
++#define IID_CONNMGR_MP4RTP_PLAYER   (IID_ID(0X0ceU) | IID_FLAG)
++#define IID_CONNMGR_AVIMP4_PLAYER   (IID_ID(0X0cfU) | IID_FLAG)
++#define IID_VDECANAEXT2             (IID_ID(0X0d0U) | IID_FLAG)
++#define IID_STBCOMMON               (IID_ID(0X0d1U) | IID_FLAG)
++#define IID_AVSYNCCTRL              (IID_ID(0X0d2U) | IID_FLAG)
++#define IID_PRIVNETSCHEMECONFIG     (IID_ID(0X0d3U) | IID_FLAG)
++#define IID_SHAREDVARIABLE          (IID_ID(0X0d4U) | IID_FLAG)
++#define IID_NETSCHEMECONFIG         (IID_ID(0X0d5U) | IID_FLAG)
++#define IID_AVSYNCTRICK             (IID_ID(0X0d6U) | IID_FLAG)
++#define IID_SETINTF                 (IID_ID(0X0d7U) | IID_FLAG)
++#define IID_URLDMXMONITOR           (IID_ID(0X0d8U) | IID_FLAG)
++#define IID_VDECMONITOR             (IID_ID(0X0d9U) | IID_FLAG)
++#define IID_STBVIDEOTYPES           (IID_ID(0X0daU) | IID_FLAG)
++
++#define IID_RESERVED                (CID_ID(0x7fffU) | CID_FLAG)
++/* ************************************************************************** */
++/* Interface Id's reserved for external organizations                         */
++/*                                                                            */
++/*  None                                                                      */
++/*                                                                            */
++/* ************************************************************************** */
++
++/* -------------------------------------------------------------------------- */
++/*                                                                            */
++/*     Definition of the component IDs                                        */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++#define CID_MPMP1_GRINDER           (CID_ID(0x8001U) | CID_FLAG)
++#define CID_MUSB_GRINDER            (CID_ID(0x8002U) | CID_FLAG)
++#define CID_UOTGPFL                 (CID_ID(0x8003U) | CID_FLAG)
++#define CID_CHIPBUILDER_GRINDER     (CID_ID(0x8004U) | CID_FLAG)
++
++#define CID_AANALYZER               (CID_ID(0x8009U) | CID_FLAG)
++#define CID_ADEC_AAC4               (CID_ID(0x800aU) | CID_FLAG)
++#define CID_ADEC_ATV                (CID_ID(0x800bU) | CID_FLAG)
++#define CID_ADEC_CELP4              (CID_ID(0x800cU) | CID_FLAG)
++#define CID_ADEC_CORE               (CID_ID(0x800dU) | CID_FLAG)
++#define CID_ADEC_MP3PRO             (CID_ID(0x800eU) | CID_FLAG)
++#define CID_ADEC_PL2                (CID_ID(0x800fU) | CID_FLAG)
++#define CID_ADEC_STB                (CID_ID(0x8010U) | CID_FLAG)
++#define CID_ADEEMPH                 (CID_ID(0x8011U) | CID_FLAG)
++#define CID_AENCAAC4                (CID_ID(0x8012U) | CID_FLAG)
++#define CID_AREND_AO_MUX            (CID_ID(0x8013U) | CID_FLAG)
++#define CID_ASP_IIRZ2               (CID_ID(0x8014U) | CID_FLAG)
++#define CID_ASRC                    (CID_ID(0x8015U) | CID_FLAG)
++#define CID_ASYS_CORE               (CID_ID(0x8016U) | CID_FLAG)
++#define CID_ATV_PLF_BASIC           (CID_ID(0x8017U) | CID_FLAG)
++#define CID_ATV_STUBS               (CID_ID(0x8018U) | CID_FLAG)
++#define CID_AVI_READ_DIVX           (CID_ID(0x8019U) | CID_FLAG)
++#define CID_BOOTINFO                (CID_ID(0x801aU) | CID_FLAG)
++#define CID_BROWSE_EIS              (CID_ID(0x801bU) | CID_FLAG)
++#define CID_BSL_7113                (CID_ID(0x801cU) | CID_FLAG)
++#define CID_BSL_7113QT              (CID_ID(0x801dU) | CID_FLAG)
++#define CID_BSL_7114                (CID_ID(0x801eU) | CID_FLAG)
++#define CID_BSL_7118                (CID_ID(0x801fU) | CID_FLAG)
++#define CID_BSL_ANABEL              (CID_ID(0x8020U) | CID_FLAG)
++#define CID_BSL_ANABELQT            (CID_ID(0x8021U) | CID_FLAG)
++#define CID_BSL_AVIP                (CID_ID(0x8022U) | CID_FLAG)
++#define CID_BSL_BOARDS              (CID_ID(0x8023U) | CID_FLAG)
++#define CID_BSL_CORE                (CID_ID(0x8024U) | CID_FLAG)
++#define CID_BSL_DENC                (CID_ID(0x8025U) | CID_FLAG)
++#define CID_BSL_EEPROM_ATMEL        (CID_ID(0x8026U) | CID_FLAG)
++#define CID_BSL_IDEXIO              (CID_ID(0x8027U) | CID_FLAG)
++#define CID_BSL_NANDSAMSUNG         (CID_ID(0x8028U) | CID_FLAG)
++#define CID_BSL_NORINTEL            (CID_ID(0x8029U) | CID_FLAG)
++#define CID_BSL_RTCPCF8563          (CID_ID(0x802aU) | CID_FLAG)
++#define CID_BSL_UART_HWAPI          (CID_ID(0x802bU) | CID_FLAG)
++#define CID_BSL_UDA1344             (CID_ID(0x802cU) | CID_FLAG)
++#define CID_BT_1500                 (CID_ID(0x802dU) | CID_FLAG)
++#define CID_BT_API                  (CID_ID(0x802eU) | CID_FLAG)
++#define CID_BT_CORE                 (CID_ID(0x802fU) | CID_FLAG)
++#define CID_BT_CPU                  (CID_ID(0x8030U) | CID_FLAG)
++#define CID_BT_MIPS                 (CID_ID(0x8031U) | CID_FLAG)
++#define CID_BT_TRIMEDIA             (CID_ID(0x8032U) | CID_FLAG)
++#define CID_BT_V2PCI                (CID_ID(0x8033U) | CID_FLAG)
++#define CID_BT_VPCI                 (CID_ID(0x8034U) | CID_FLAG)
++#define CID_BT_VSTB                 (CID_ID(0x8035U) | CID_FLAG)
++#define CID_BUFFEREDREAD            (CID_ID(0x8036U) | CID_FLAG)
++#define CID_CONN_MGRAUDSYSSTB       (CID_ID(0x8037U) | CID_FLAG)
++#define CID_DEMUXMPEGTS_SW          (CID_ID(0x8038U) | CID_FLAG)
++#define CID_DIG_ADEC_AUDSYS_STB     (CID_ID(0x8039U) | CID_FLAG)
++#define CID_DL_AI                   (CID_ID(0x803aU) | CID_FLAG)
++#define CID_DL_AICP                 (CID_ID(0x803bU) | CID_FLAG)
++#define CID_DL_AO                   (CID_ID(0x803cU) | CID_FLAG)
++#define CID_DL_AVFS                 (CID_ID(0x803dU) | CID_FLAG)
++#define CID_DL_CLOCK                (CID_ID(0x803eU) | CID_FLAG)
++#define CID_DL_DFS                  (CID_ID(0x803fU) | CID_FLAG)
++#define CID_DL_DISKSCHED            (CID_ID(0x8040U) | CID_FLAG)
++#define CID_DL_DMA                  (CID_ID(0x8041U) | CID_FLAG)
++#define CID_DL_ETH_IP3902           (CID_ID(0x8042U) | CID_FLAG)
++#define CID_DL_GPIO                 (CID_ID(0x8043U) | CID_FLAG)
++#define CID_DL_I2C                  (CID_ID(0x8044U) | CID_FLAG)
++#define CID_DL_IDE                  (CID_ID(0x8045U) | CID_FLAG)
++#define CID_DL_IDESTUB              (CID_ID(0x8046U) | CID_FLAG)
++#define CID_DL_IIC                  (CID_ID(0x8047U) | CID_FLAG)
++#define CID_DL_IR                   (CID_ID(0x8048U) | CID_FLAG)
++#define CID_DL_MBS                  (CID_ID(0x8049U) | CID_FLAG)
++#define CID_DL_MBS2                 (CID_ID(0x804aU) | CID_FLAG)
++#define CID_DL_NANDFLASH            (CID_ID(0x804bU) | CID_FLAG)
++#define CID_DL_NORFLASH             (CID_ID(0x804cU) | CID_FLAG)
++#define CID_DL_PCI                  (CID_ID(0x804dU) | CID_FLAG)
++#define CID_DL_PROCESSOR            (CID_ID(0x804eU) | CID_FLAG)
++#define CID_DL_QTNR                 (CID_ID(0x804fU) | CID_FLAG)
++#define CID_DL_QVCP                 (CID_ID(0x8050U) | CID_FLAG)
++#define CID_DL_SEM                  (CID_ID(0x8051U) | CID_FLAG)
++#define CID_DL_SPDI                 (CID_ID(0x8052U) | CID_FLAG)
++#define CID_DL_SPDO                 (CID_ID(0x8053U) | CID_FLAG)
++#define CID_DL_TIMER                (CID_ID(0x8054U) | CID_FLAG)
++#define CID_DL_TSDMA                (CID_ID(0x8055U) | CID_FLAG)
++#define CID_DL_TSIO                 (CID_ID(0x8056U) | CID_FLAG)
++#define CID_DL_UDMA                 (CID_ID(0x8057U) | CID_FLAG)
++#define CID_DL_VID_MEAS             (CID_ID(0x8058U) | CID_FLAG)
++#define CID_DL_VIP                  (CID_ID(0x8059U) | CID_FLAG)
++#define CID_DL_VMPG                 (CID_ID(0x805aU) | CID_FLAG)
++#define CID_DL_XIO                  (CID_ID(0x805bU) | CID_FLAG)
++#define CID_DRAWTEXT                (CID_ID(0x805cU) | CID_FLAG)
++#define CID_DVPDEBUG                (CID_ID(0x805dU) | CID_FLAG)
++#define CID_FATALERROR              (CID_ID(0x805eU) | CID_FLAG)
++#define CID_FATALERROR_VT           (CID_ID(0x805fU) | CID_FLAG)
++#define CID_FREADAVPROP             (CID_ID(0x8060U) | CID_FLAG)
++#define CID_FWRITEAVPROP            (CID_ID(0x8061U) | CID_FLAG)
++#define CID_HELP                    (CID_ID(0x8062U) | CID_FLAG)
++#define CID_HTTP_IO_DRIVER          (CID_ID(0x8063U) | CID_FLAG)
++#define CID_HW_AICP                 (CID_ID(0x8064U) | CID_FLAG)
++#define CID_HW_CLOCK                (CID_ID(0x8065U) | CID_FLAG)
++#define CID_HW_DMA                  (CID_ID(0x8066U) | CID_FLAG)
++#define CID_HW_DRAW                 (CID_ID(0x8067U) | CID_FLAG)
++#define CID_HW_DRAWCOMMON           (CID_ID(0x8068U) | CID_FLAG)
++#define CID_HW_DRAWDE               (CID_ID(0x8069U) | CID_FLAG)
++#define CID_HW_DRAWREF              (CID_ID(0x806aU) | CID_FLAG)
++#define CID_HW_DRAWSHARED           (CID_ID(0x806bU) | CID_FLAG)
++#define CID_HW_DRAWTMH              (CID_ID(0x806cU) | CID_FLAG)
++#define CID_HW_DRAWTMT              (CID_ID(0x806dU) | CID_FLAG)
++#define CID_HW_DRAWTMTH             (CID_ID(0x806eU) | CID_FLAG)
++#define CID_HW_DSP                  (CID_ID(0x806fU) | CID_FLAG)
++#define CID_HW_ETH_IP3902           (CID_ID(0x8070U) | CID_FLAG)
++#define CID_HW_GIC                  (CID_ID(0x8071U) | CID_FLAG)
++#define CID_HW_GPIO                 (CID_ID(0x8072U) | CID_FLAG)
++#define CID_HW_I2C                  (CID_ID(0x8073U) | CID_FLAG)
++#define CID_HW_IIC                  (CID_ID(0x8074U) | CID_FLAG)
++#define CID_HW_MBS                  (CID_ID(0x8075U) | CID_FLAG)
++#define CID_HW_MMIARB               (CID_ID(0x8076U) | CID_FLAG)
++#define CID_HW_MMIARB1010           (CID_ID(0x8077U) | CID_FLAG)
++#define CID_HW_PCI                  (CID_ID(0x8078U) | CID_FLAG)
++#define CID_HW_PIC                  (CID_ID(0x8079U) | CID_FLAG)
++#define CID_HW_SMC                  (CID_ID(0x807aU) | CID_FLAG)
++#define CID_HW_TSDMA                (CID_ID(0x807bU) | CID_FLAG)
++#define CID_HW_UART                 (CID_ID(0x807cU) | CID_FLAG)
++#define CID_HW_UDMA                 (CID_ID(0x807dU) | CID_FLAG)
++#define CID_HW_VIP                  (CID_ID(0x807eU) | CID_FLAG)
++#define CID_HW_VMSP                 (CID_ID(0x807fU) | CID_FLAG)
++#define CID_HW_XIO                  (CID_ID(0x8080U) | CID_FLAG)
++#define CID_INFRA_MISC              (CID_ID(0x8081U) | CID_FLAG)
++#define CID_INTERRUPT               (CID_ID(0x8082U) | CID_FLAG)
++#define CID_IPC_DT                  (CID_ID(0x8083U) | CID_FLAG)
++#define CID_IPC_READ                (CID_ID(0x8084U) | CID_FLAG)
++#define CID_IPC_RPC                 (CID_ID(0x8085U) | CID_FLAG)
++#define CID_IPC_WRITE               (CID_ID(0x8086U) | CID_FLAG)
++#define CID_LIBLOAD_TM              (CID_ID(0x8087U) | CID_FLAG)
++#define CID_MEMDBG                  (CID_ID(0x8088U) | CID_FLAG)
++#define CID_MENU                    (CID_ID(0x8089U) | CID_FLAG)
++#define CID_MP4READ                 (CID_ID(0x808aU) | CID_FLAG)
++#define CID_MPEGCOLORBAR            (CID_ID(0x808bU) | CID_FLAG)
++#define CID_NETSTACK_FUSION         (CID_ID(0x808cU) | CID_FLAG)
++#define CID_NETSTACK_TARGET_TCP     (CID_ID(0x808dU) | CID_FLAG)
++#define CID_NETSTACK_UPNP_ALLEGRO   (CID_ID(0x808dU) | CID_FLAG)
++#define CID_NETSTACK_UPNP_INTEL     (CID_ID(0x808eU) | CID_FLAG)
++#define CID_NETWORKREAD             (CID_ID(0x8090U) | CID_FLAG)
++#define CID_NM_COMMON               (CID_ID(0x8091U) | CID_FLAG)
++#define CID_NM_DEI                  (CID_ID(0x8092U) | CID_FLAG)
++#define CID_NM_EST                  (CID_ID(0x8093U) | CID_FLAG)
++#define CID_NM_QFD                  (CID_ID(0x8094U) | CID_FLAG)
++#define CID_NM_UPC                  (CID_ID(0x8095U) | CID_FLAG)
++#define CID_NM_UPC_SPIDER           (CID_ID(0x8096U) | CID_FLAG)
++#define CID_OS                      (CID_ID(0x8097U) | CID_FLAG)
++#define CID_PROBE                   (CID_ID(0x8098U) | CID_FLAG)
++#define CID_PSIUTIL                 (CID_ID(0x8099U) | CID_FLAG)
++#define CID_REALNETWORKS_ENGINE     (CID_ID(0x809aU) | CID_FLAG)
++#define CID_SCAN_RATE_CONV_VSYS_TV  (CID_ID(0x809bU) | CID_FLAG)
++#define CID_SPOSAL                  (CID_ID(0x809cU) | CID_FLAG)
++#define CID_TIMEDOCTOR              (CID_ID(0x809dU) | CID_FLAG)
++#define CID_TSA_CLOCK               (CID_ID(0x809eU) | CID_FLAG)
++
++#define CID_TST_AVETC_SINK          (CID_ID(0x80a0U) | CID_FLAG)
++#define CID_TST_DEMUX               (CID_ID(0x80a1U) | CID_FLAG)
++#define CID_TST_DEMUX_FOR_MUX       (CID_ID(0x80a2U) | CID_FLAG)
++#define CID_TST_SPTS_SINK           (CID_ID(0x80a3U) | CID_FLAG)
++#define CID_TTI_UTIL                (CID_ID(0x80a4U) | CID_FLAG)
++#define CID_UART                    (CID_ID(0x80a5U) | CID_FLAG)
++#define CID_UPCONV100MC             (CID_ID(0x80a6U) | CID_FLAG)
++#define CID_UTILCPIREC              (CID_ID(0x80a7U) | CID_FLAG)
++#define CID_UTILCRYPTRIJNDAEL       (CID_ID(0x80a8U) | CID_FLAG)
++#define CID_VATV                    (CID_ID(0x80a9U) | CID_FLAG)
++#define CID_VATV_TR                 (CID_ID(0x80aaU) | CID_FLAG)
++#define CID_VBI_INSERT_VSYS_TV      (CID_ID(0x80abU) | CID_FLAG)
++#define CID_VCAP_VIP2               (CID_ID(0x80acU) | CID_FLAG)
++#define CID_VDEC_BMP                (CID_ID(0x80adU) | CID_FLAG)
++#define CID_VDEC_DIVX               (CID_ID(0x80aeU) | CID_FLAG)
++#define CID_VDEC_GIF                (CID_ID(0x80afU) | CID_FLAG)
++#define CID_VDEC_JPEG               (CID_ID(0x80b0U) | CID_FLAG)
++#define CID_VDEC_JPEG2K             (CID_ID(0x80b1U) | CID_FLAG)
++#define CID_VDEC_MP                 (CID_ID(0x80b2U) | CID_FLAG)
++#define CID_VDECMPEG4               (CID_ID(0x80b3U) | CID_FLAG)
++#define CID_VENC_MPEG4              (CID_ID(0x80b4U) | CID_FLAG)
++#define CID_VENCMJPEG               (CID_ID(0x80b5U) | CID_FLAG)
++#define CID_VENCMPEG2               (CID_ID(0x80b6U) | CID_FLAG)
++#define CID_VIDEOUTIL               (CID_ID(0x80b7U) | CID_FLAG)
++#define CID_VPACK                   (CID_ID(0x80b8U) | CID_FLAG)
++#define CID_VPIP_REC_PLAY           (CID_ID(0x80b9U) | CID_FLAG)
++#define CID_VPOST_ICP               (CID_ID(0x80baU) | CID_FLAG)
++#define CID_VREND_VCP               (CID_ID(0x80bbU) | CID_FLAG)
++#define CID_VRENDVO                 (CID_ID(0x80bcU) | CID_FLAG)
++#define CID_VSCHED                  (CID_ID(0x80bdU) | CID_FLAG)
++#define CID_VTBLBASE                (CID_ID(0x80beU) | CID_FLAG)
++#define CID_VTRANS_MBS2             (CID_ID(0x80bfU) | CID_FLAG)
++#define CID_VTRANS_QTNR             (CID_ID(0x80c0U) | CID_FLAG)
++#define CID_VXWORKS_BSP             (CID_ID(0x80c1U) | CID_FLAG)
++#define CID_WREAD                   (CID_ID(0x80c2U) | CID_FLAG)
++#define CID_CONNMGR_ATV             (CID_ID(0x80c3U) | CID_FLAG)
++#define CID_DL_VPK                  (CID_ID(0x80c4U) | CID_FLAG)
++#define CID_VTRANS_VPK              (CID_ID(0x80c5U) | CID_FLAG)
++#define CID_DL_VIP2                 (CID_ID(0x80c6U) | CID_FLAG)
++#define CID_VX_GEN_UART             (CID_ID(0x80c7U) | CID_FLAG)
++#define CID_VX_GPIO                 (CID_ID(0x80c8U) | CID_FLAG)
++#define CID_VX_GEN_TIMER            (CID_ID(0x80c9U) | CID_FLAG)
++#define CID_M4VENC_DIS              (CID_ID(0x80caU) | CID_FLAG)
++#define CID_VENC_ANA                (CID_ID(0x80cbU) | CID_FLAG)
++#define CID_BSL_VENC_ANA            (CID_ID(0x80ccU) | CID_FLAG)
++#define CID_BSL_VENC_ANA_EXT        (CID_ID(0x80cdU) | CID_FLAG)
++#define CID_BSL_VENC_ANAVBI_EXT     (CID_ID(0x80ceU) | CID_FLAG)
++#define CID_CMDX                    (CID_ID(0x80cfU) | CID_FLAG)
++#define CID_LL_GPIO                 (CID_ID(0x80d0U) | CID_FLAG)
++#define CID_LL_KEYPAD               (CID_ID(0x80d1U) | CID_FLAG)
++#define CID_LL_TIMER                (CID_ID(0x80d2U) | CID_FLAG)
++#define CID_LL_SPI                  (CID_ID(0x80d3U) | CID_FLAG)
++#define CID_LL_UART                 (CID_ID(0x80d4U) | CID_FLAG)
++#define CID_LL_I2C                  (CID_ID(0x80d5U) | CID_FLAG)
++#define CID_LL_TR                   (CID_ID(0x80d6U) | CID_FLAG)
++#define CID_HW_KEYPAD               (CID_ID(0x80d7U) | CID_FLAG)
++#define CID_HW_TIMER                (CID_ID(0x80d8U) | CID_FLAG)
++#define CID_HW_SPI                  (CID_ID(0x80d9U) | CID_FLAG)
++#define CID_HW_VATV_IOSYNC          (CID_ID(0x80daU) | CID_FLAG)
++#define CID_DL_VO                   (CID_ID(0x80dbU) | CID_FLAG)
++#define CID_DL_LVDS                 (CID_ID(0x80dcU) | CID_FLAG)
++#define CID_HW_DDR2031              (CID_ID(0x80ddU) | CID_FLAG)
++#define CID_BSL_PHY                 (CID_ID(0x80deU) | CID_FLAG)
++#define CID_ETH_TTCP                (CID_ID(0x80dfU) | CID_FLAG)
++#define CID_CDIGADEC_MP3PRO         (CID_ID(0x80e0U) | CID_FLAG)
++#define CID_CID3EXTR                (CID_ID(0x80e1U) | CID_FLAG)
++#define CID_IMAGEDEC_JPEG           (CID_ID(0x80e2U) | CID_FLAG)
++#define CID_CURLSRC_MP3PRO          (CID_ID(0x80e3U) | CID_FLAG)
++#define CID_CURLSRC_IMAGEDEC        (CID_ID(0x80e4U) | CID_FLAG)
++#define CID_DVP_MAIN                (CID_ID(0x80e5U) | CID_FLAG)
++#define CID_TMMAN32                 (CID_ID(0x80e6U) | CID_FLAG)
++#define CID_TMMAN_CRT               (CID_ID(0x80e7U) | CID_FLAG)
++#define CID_UHS_HAL_PCI             (CID_ID(0x80e8U) | CID_FLAG)
++#define CID_UHS_OSAL_VXWORKS        (CID_ID(0x80e9U) | CID_FLAG)
++#define CID_UHS_OSAL_PSOS           (CID_ID(0x80eaU) | CID_FLAG)
++#define CID_UHS_USBD                (CID_ID(0x80ebU) | CID_FLAG)
++#define CID_UHS_RBC                 (CID_ID(0x80ecU) | CID_FLAG)
++#define CID_UHS_UFI                 (CID_ID(0x80edU) | CID_FLAG)
++#define CID_UHS_SCSI                (CID_ID(0x80eeU) | CID_FLAG)
++#define CID_UHS_PRINTER             (CID_ID(0x80efU) | CID_FLAG)
++#define CID_UHS_MOUSE               (CID_ID(0x80f0U) | CID_FLAG)
++#define CID_UHS_KEYBOARD            (CID_ID(0x80f1U) | CID_FLAG)
++#define CID_UHS_HUB                 (CID_ID(0x80f2U) | CID_FLAG)
++#define CID_UHS_HCD_1561            (CID_ID(0x80f3U) | CID_FLAG)
++#define CID_CLEANUP                 (CID_ID(0x80f4U) | CID_FLAG)
++#define CID_ALLOCATOR               (CID_ID(0x80f5U) | CID_FLAG)
++#define CID_TCS_CORE_LIBDEV         (CID_ID(0x80f6U) | CID_FLAG)
++#define CID_VDI_VDO_ROUTER          (CID_ID(0x80f7U) | CID_FLAG)
++#define CID_CONNMGR_ATSC            (CID_ID(0x80f8U) | CID_FLAG)
++#define CID_ASPDIF                  (CID_ID(0x80f9U) | CID_FLAG)
++#define CID_APLL                    (CID_ID(0x80faU) | CID_FLAG)
++#define CID_ATVPLFINSTVIN           (CID_ID(0x80fbU) | CID_FLAG)
++#define CID_ATV_PLF                 (CID_ID(0x80fcU) | CID_FLAG)
++#define CID_DL_WATCHDOG             (CID_ID(0x80fdU) | CID_FLAG)
++#define CID_WMT_NET_READER          (CID_ID(0x80feU) | CID_FLAG)
++#define CID_DL_FGPO                 (CID_ID(0x80ffU) | CID_FLAG)
++#define CID_DL_FGPI                 (CID_ID(0x8100U) | CID_FLAG)
++#define CID_WMT_DECODER             (CID_ID(0x8101U) | CID_FLAG)
++#define CID_HAD_DRV_IIC             (CID_ID(0x8102U) | CID_FLAG)
++#define CID_HAD_DRV_GPIO            (CID_ID(0x8103U) | CID_FLAG)
++#define CID_HAD_GLOBAL              (CID_ID(0x8104U) | CID_FLAG)
++#define CID_HAD_SMM                 (CID_ID(0x8105U) | CID_FLAG)
++#define CID_HAD_DRV_CSM             (CID_ID(0x8106U) | CID_FLAG)
++#define CID_CARACASWDOG             (CID_ID(0x8107U) | CID_FLAG)
++#define CID_CARACASADC              (CID_ID(0x8108U) | CID_FLAG)
++#define CID_CARACASDMA              (CID_ID(0x8109U) | CID_FLAG)
++#define CID_CARACASFLASHCTRL        (CID_ID(0x810aU) | CID_FLAG)
++#define CID_CARACASGPTIMER          (CID_ID(0x810bU) | CID_FLAG)
++#define CID_CARACASGPIO             (CID_ID(0x810cU) | CID_FLAG)
++#define CID_CARACASI2CMO            (CID_ID(0x810dU) | CID_FLAG)
++#define CID_CARACASI2CMS            (CID_ID(0x810eU) | CID_FLAG)
++#define CID_CARACASRTC              (CID_ID(0x810fU) | CID_FLAG)
++#define CID_CARACASSPI              (CID_ID(0x8110U) | CID_FLAG)
++#define CID_CARACASTIMER            (CID_ID(0x8111U) | CID_FLAG)
++#define CID_CARACASUART             (CID_ID(0x8112U) | CID_FLAG)
++#define CID_TSSA40                  (CID_ID(0x8113U) | CID_FLAG)
++#define CID_PACKET_POOL             (CID_ID(0x8114U) | CID_FLAG)
++#define CID_TSSA15_WRAPPER          (CID_ID(0x8115U) | CID_FLAG)
++#define CID_TASK_SYNC               (CID_ID(0x8116U) | CID_FLAG)
++#define CID_TASK_CONDITION          (CID_ID(0x8117U) | CID_FLAG)
++#define CID_PACKET_QUEUE            (CID_ID(0x8118U) | CID_FLAG)
++#define CID_CONNECTION_TOOLKIT      (CID_ID(0x8119U) | CID_FLAG)
++#define CID_TSSA16                  (CID_ID(0x811aU) | CID_FLAG)
++#define CID_UDSDFU                  (CID_ID(0x811bU) | CID_FLAG)
++#define CID_BTH                     (CID_ID(0x811cU) | CID_FLAG)
++#define CID_DCDIP9021               (CID_ID(0x811dU) | CID_FLAG)
++#define CID_DCDIP3501V1X            (CID_ID(0x811eU) | CID_FLAG)
++#define CID_ISP1581                 (CID_ID(0x811fU) | CID_FLAG)
++#define CID_DCSS_TV                 (CID_ID(0x8120U) | CID_FLAG)
++#define CID_DCSS_MON                (CID_ID(0x8121U) | CID_FLAG)
++#define CID_DCSS_RSC_PC             (CID_ID(0x8122U) | CID_FLAG)
++#define CID_DCSS_RSC_INT            (CID_ID(0x8123U) | CID_FLAG)
++#define CID_DCSS_RSC_EXT            (CID_ID(0x8124U) | CID_FLAG)
++#define CID_DCSS_LIT                (CID_ID(0x8125U) | CID_FLAG)
++#define CID_DCSS_LIT_C              (CID_ID(0x8126U) | CID_FLAG)
++#define CID_DCSS_45A                (CID_ID(0x8127U) | CID_FLAG)
++#define CID_UDSCORE                 (CID_ID(0x8128U) | CID_FLAG)
++#define CID_HW_AUDIO7135            (CID_ID(0x8129U) | CID_FLAG)
++#define CID_DL_AUDIO3X              (CID_ID(0x812aU) | CID_FLAG)
++#define CID_REGACC                  (CID_ID(0x812bU) | CID_FLAG)
++#define CID_HW_MJPEG                (CID_ID(0x812cU) | CID_FLAG)
++#define CID_ISP1582                 (CID_ID(0x812dU) | CID_FLAG)
++#define CID_MUTI                    (CID_ID(0x812eU) | CID_FLAG)
++#define CID_CHANNEL_DECODER_ENCODER (CID_ID(0x812fU) | CID_FLAG)
++#define CID_RESMGR                  (CID_ID(0x8130U) | CID_FLAG)
++#define CID_WIDGET                  (CID_ID(0x8131U) | CID_FLAG)
++#define CID_FB                      (CID_ID(0x8132U) | CID_FLAG)
++#define CID_GFX                     (CID_ID(0x8133U) | CID_FLAG)
++#define CID_HPS_DISPATCHER          (CID_ID(0x8134U) | CID_FLAG)
++#define CID_DL_PLXGPIO              (CID_ID(0x8135U) | CID_FLAG)
++#define CID_HW_PLXGPIO              (CID_ID(0x8136U) | CID_FLAG)
++#define CID_DL_PLXPHI               (CID_ID(0x8137U) | CID_FLAG)
++#define CID_HW_PLXPHI_EVALUATOR     (CID_ID(0x8138U) | CID_FLAG)
++#define CID_DL_SCALER               (CID_ID(0x8139U) | CID_FLAG)
++#define CID_EFM                     (CID_ID(0x813aU) | CID_FLAG)
++#define CID_HW_TUNER_FM1236MK3      (CID_ID(0x813bU) | CID_FLAG)
++#define CID_HW_TUNER_FM1216MK3      (CID_ID(0x813cU) | CID_FLAG)
++#define CID_HW_TUNER_FM1216MK2      (CID_ID(0x813dU) | CID_FLAG)
++#define CID_ANALOG_CHANNEL_TABLE    (CID_ID(0x813eU) | CID_FLAG)
++#define CID_TUNER_CONTROL           (CID_ID(0x813fU) | CID_FLAG)
++#define CID_DL_UIMS                 (CID_ID(0x8140U) | CID_FLAG)
++#define CID_DL_RCTRANSMITTER        (CID_ID(0x8141U) | CID_FLAG)
++#define CID_HW_CST_RCRECEIVER       (CID_ID(0x8142U) | CID_FLAG)
++#define CID_HW_CST_RCTRANSMITTER    (CID_ID(0x8143U) | CID_FLAG)
++#define CID_DCDIP3506               (CID_ID(0x8144U) | CID_FLAG)
++#define CID_DCDIP3501V2X            (CID_ID(0x8145U) | CID_FLAG)
++#define CID_MTV_COORD               (CID_ID(0x8146U) | CID_FLAG)
++#define CID_MTV_IMG_ROT_CTRL        (CID_ID(0x8147U) | CID_FLAG)
++#define CID_TFE_TRACE               (CID_ID(0x8148U) | CID_FLAG)
++#define CID_TMCAL_SERVER            (CID_ID(0x8149U) | CID_FLAG)
++#define CID_BOOT_LOADER             (CID_ID(0x814aU) | CID_FLAG)
++#define CID_TD_SAVE_DATA            (CID_ID(0x814bU) | CID_FLAG)
++#define CID_TFE_TRACE_PROCESS_DATA  (CID_ID(0x814cU) | CID_FLAG)
++#define CID_VIDEOCTRL               (CID_ID(0x814dU) | CID_FLAG)
++#define CID_BOOT                    (CID_ID(0x814eU) | CID_FLAG)
++#define CID_EVENT                   (CID_ID(0x814fU) | CID_FLAG)
++#define CID_USERINPUT               (CID_ID(0x8150U) | CID_FLAG)
++#define CID_BSL_TUNER               (CID_ID(0x8151U) | CID_FLAG)
++#define CID_P5KIIC                  (CID_ID(0x8152U) | CID_FLAG)
++#define CID_HW_PMANSECURITY         (CID_ID(0x8153U) | CID_FLAG)
++#define CID_DRM_DIVX                (CID_ID(0x8154U) | CID_FLAG)
++#define CID_TMHWVIDEODEC7136        (CID_ID(0x8155U) | CID_FLAG)
++#define CID_TMDLVIDEODEC            (CID_ID(0x8156U) | CID_FLAG)
++#define CID_OSD_KERNEL              (CID_ID(0x8157U) | CID_FLAG)
++#define CID_HW_DCSNETWORK           (CID_ID(0x8158U) | CID_FLAG)
++#define CID_DL_RCRECEIVER           (CID_ID(0x8159U) | CID_FLAG)
++#define CID_INT                     (CID_ID(0x815aU) | CID_FLAG)
++#define CID_RTC                     (CID_ID(0x815bU) | CID_FLAG)
++#define CID_TIMER                   (CID_ID(0x815cU) | CID_FLAG)
++#define CID_IPC                     (CID_ID(0x815dU) | CID_FLAG)
++#define CID_P5KTELETEXT             (CID_ID(0x815eU) | CID_FLAG)
++#define CID_P5KAUDIOVIDEO           (CID_ID(0x815fU) | CID_FLAG)
++#define CID_P5KCONFIG               (CID_ID(0x8160U) | CID_FLAG)
++#define CID_HW_CST_TRANSPSTREAMIN   (CID_ID(0x8161U) | CID_FLAG)
++#define CID_HOMER_KERNEL            (CID_ID(0x8162U) | CID_FLAG)
++#define CID_HOMER_DRIVER            (CID_ID(0x8163U) | CID_FLAG)
++#define CID_CD_FILE_SYSTEM          (CID_ID(0x8164U) | CID_FLAG)
++#define CID_COBALT_APP              (CID_ID(0x8165U) | CID_FLAG)
++#define CID_COBALT_UI               (CID_ID(0x8166U) | CID_FLAG)
++#define CID_CD_SERVO                (CID_ID(0x8167U) | CID_FLAG)
++#define CID_CD_UTILS                (CID_ID(0x8168U) | CID_FLAG)
++#define CID_COBALT_SYSTEM           (CID_ID(0x8169U) | CID_FLAG)
++#define CID_CDSLIM                  (CID_ID(0x816aU) | CID_FLAG)
++#define CID_CD_DATABASE             (CID_ID(0x816bU) | CID_FLAG)
++#define CID_CANAVENC                (CID_ID(0x816cU) | CID_FLAG)
++#define CID_CANTIAGING              (CID_ID(0x816dU) | CID_FLAG)
++#define CID_CAUTOPICTCTRL           (CID_ID(0x816eU) | CID_FLAG)
++#define CID_CBBARCTRL               (CID_ID(0x816fU) | CID_FLAG)
++#define CID_CBBARDET                (CID_ID(0x8170U) | CID_FLAG)
++#define CID_CBBARDETEXT             (CID_ID(0x8171U) | CID_FLAG)
++#define CID_CBLEVELDETEXT           (CID_ID(0x8172U) | CID_FLAG)
++#define CID_CCOLENH                 (CID_ID(0x8173U) | CID_FLAG)
++#define CID_CCOLENHEXT              (CID_ID(0x8174U) | CID_FLAG)
++#define CID_CCONTRESEXT             (CID_ID(0x8175U) | CID_FLAG)
++#define CID_CCTI                    (CID_ID(0x8176U) | CID_FLAG)
++#define CID_CCTIEXT                 (CID_ID(0x8177U) | CID_FLAG)
++#define CID_CDNR                    (CID_ID(0x8178U) | CID_FLAG)
++#define CID_CDNREXT                 (CID_ID(0x8179U) | CID_FLAG)
++#define CID_CGAMMAEXT               (CID_ID(0x817aU) | CID_FLAG)
++#define CID_CHISTOMEASEXT           (CID_ID(0x817bU) | CID_FLAG)
++#define CID_CHISTOMOD               (CID_ID(0x817cU) | CID_FLAG)
++#define CID_CHISTOMODEXT            (CID_ID(0x817dU) | CID_FLAG)
++#define CID_CMBSXRAY                (CID_ID(0x817eU) | CID_FLAG)
++#define CID_CNOISE                  (CID_ID(0x817fU) | CID_FLAG)
++#define CID_CNOISEESTEXT            (CID_ID(0x8180U) | CID_FLAG)
++#define CID_CPFSPD                  (CID_ID(0x8181U) | CID_FLAG)
++#define CID_CQVCPXRAY               (CID_ID(0x8182U) | CID_FLAG)
++#define CID_CSCANRATECONV           (CID_ID(0x8183U) | CID_FLAG)
++#define CID_CSCANRATECONVEXT        (CID_ID(0x8184U) | CID_FLAG)
++#define CID_CSHARPENH               (CID_ID(0x8185U) | CID_FLAG)
++#define CID_CSHARPENHEXT            (CID_ID(0x8186U) | CID_FLAG)
++#define CID_CSHARPMEAS              (CID_ID(0x8187U) | CID_FLAG)
++#define CID_CSHARPMEASEXT           (CID_ID(0x8188U) | CID_FLAG)
++#define CID_CSYNCTAG                (CID_ID(0x8189U) | CID_FLAG)
++#define CID_CUVBWDETEXT             (CID_ID(0x818aU) | CID_FLAG)
++#define CID_CVBISLICE               (CID_ID(0x818bU) | CID_FLAG)
++#define CID_CVFEAT                  (CID_ID(0x818cU) | CID_FLAG)
++#define CID_CVFEAT2                 (CID_ID(0x818dU) | CID_FLAG)
++#define CID_CVIPXRAY                (CID_ID(0x818eU) | CID_FLAG)
++#define CID_CVIPXRAYDITHER          (CID_ID(0x818fU) | CID_FLAG)
++#define CID_CVMIX                   (CID_ID(0x8190U) | CID_FLAG)
++#define CID_CVTRSCALEEXT            (CID_ID(0x8191U) | CID_FLAG)
++#define CID_CVTRANTIAGING           (CID_ID(0x8192U) | CID_FLAG)
++#define CID_CVTRFADEVCP             (CID_ID(0x8193U) | CID_FLAG)
++#define CID_CVTRSCALEMBSVCP         (CID_ID(0x8194U) | CID_FLAG)
++#define CID_CVTRSTROBEMBS           (CID_ID(0x8195U) | CID_FLAG)
++#define CID_NM_UTILS                (CID_ID(0x8196U) | CID_FLAG)
++#define CID_VSEQSCHEDENGINE         (CID_ID(0x8197U) | CID_FLAG)
++#define CID_VCPSCHEDENGINE          (CID_ID(0x8198U) | CID_FLAG)
++#define CID_VGENTEST                (CID_ID(0x8199U) | CID_FLAG)
++#define CID_VMENU                   (CID_ID(0x819aU) | CID_FLAG)
++#define CID_VPROCCOMMON             (CID_ID(0x819bU) | CID_FLAG)
++#define CID_VPROCTV                 (CID_ID(0x819cU) | CID_FLAG)
++#define CID_VPROCTV505E             (CID_ID(0x819dU) | CID_FLAG)
++#define CID_SCHEDENGINE             (CID_ID(0x819eU) | CID_FLAG)
++#define CID_VSLNMCOMMON             (CID_ID(0x819fU) | CID_FLAG)
++#define CID_VSLVCAPVIP              (CID_ID(0x81a0U) | CID_FLAG)
++#define CID_VSLVCAPVIPVBI           (CID_ID(0x81a1U) | CID_FLAG)
++#define CID_VSLVINCONVERT           (CID_ID(0x81a2U) | CID_FLAG)
++#define CID_VSLIOSYNC               (CID_ID(0x81a3U) | CID_FLAG)
++#define CID_VSLVRENDVCP             (CID_ID(0x81a4U) | CID_FLAG)
++#define CID_VSLVRENDVCPVBI          (CID_ID(0x81a5U) | CID_FLAG)
++#define CID_VSLSYNCTAG              (CID_ID(0x81a6U) | CID_FLAG)
++#define CID_VSLVTRANSMBS            (CID_ID(0x81a7U) | CID_FLAG)
++#define CID_VSLVTRANSNM             (CID_ID(0x81a8U) | CID_FLAG)
++#define CID_VSLVTRANSQTNR           (CID_ID(0x81a9U) | CID_FLAG)
++#define CID_VSLVTRANSSWTNR          (CID_ID(0x81aaU) | CID_FLAG)
++#define CID_VTRANSSWTNR             (CID_ID(0x81abU) | CID_FLAG)
++#define CID_LL_DMA                  (CID_ID(0x81acU) | CID_FLAG)
++#define CID_BSL_PNX8550             (CID_ID(0x81adU) | CID_FLAG)
++#define CID_BSL_PNX1500             (CID_ID(0x81aeU) | CID_FLAG)
++#define CID_BSL_NULL                (CID_ID(0x81afU) | CID_FLAG)
++#define CID_BSL_PNX2015             (CID_ID(0x81b0U) | CID_FLAG)
++#define CID_HW_SCALER7136           (CID_ID(0x81b1U) | CID_FLAG)
++#define CID_SPI_IP3409              (CID_ID(0x81b2U) | CID_FLAG)
++#define CID_SPI_3409                (CID_ID(0x81b3U) | CID_FLAG)
++#define CID_SPISD_3409              (CID_ID(0x81b4U) | CID_FLAG)
++#define CID_CONNMGRMP4RTPPLAYER     (CID_ID(0x81b5U) | CID_FLAG)
++#define CID_DL_NANDFLASH2           (CID_ID(0x81b6U) | CID_FLAG)
++#define CID_HW_HOSTIF               (CID_ID(0x81b7U) | CID_FLAG)
++#define CID_LL_HOSTIF               (CID_ID(0x81b8U) | CID_FLAG)
++#define CID_LL_MJPEG                (CID_ID(0x81b9U) | CID_FLAG)
++#define CID_HW_SENSORIF             (CID_ID(0x81baU) | CID_FLAG)
++#define CID_LL_SENSORIF             (CID_ID(0x81bbU) | CID_FLAG)
++#define CID_HW_ECSP                 (CID_ID(0x81bcU) | CID_FLAG)
++#define CID_LL_ECSP                 (CID_ID(0x81bdU) | CID_FLAG)
++#define CID_HW_DOWNSCALER           (CID_ID(0x81beU) | CID_FLAG)
++#define CID_LL_DOWNSCALER           (CID_ID(0x81bfU) | CID_FLAG)
++#define CID_HW_UPSCALER             (CID_ID(0x81c0U) | CID_FLAG)
++#define CID_LL_UPSCALER             (CID_ID(0x81c1U) | CID_FLAG)
++#define CID_HW_JITTEREX             (CID_ID(0x81c2U) | CID_FLAG)
++#define CID_LL_JITTEREX             (CID_ID(0x81c3U) | CID_FLAG)
++#define CID_HW_NOISERED             (CID_ID(0x81c4U) | CID_FLAG)
++#define CID_LL_NOISERED             (CID_ID(0x81c5U) | CID_FLAG)
++#define CID_HW_JPEGENCODER          (CID_ID(0x81c6U) | CID_FLAG)
++#define CID_LL_JPEGENCODER          (CID_ID(0x81c7U) | CID_FLAG)
++#define CID_HW_FLASHLIGHT           (CID_ID(0x81c8U) | CID_FLAG)
++#define CID_LL_FLASHLIGHT           (CID_ID(0x81c9U) | CID_FLAG)
++#define CID_HW_TVCONVERTER          (CID_ID(0x81caU) | CID_FLAG)
++#define CID_LL_TVCONVERTER          (CID_ID(0x81cbU) | CID_FLAG)
++#define CID_HW_DVDOMATRIX           (CID_ID(0x81ccU) | CID_FLAG)
++#define CID_LL_DVDOMATRIX           (CID_ID(0x81cdU) | CID_FLAG)
++#define CID_HW_CLCD                 (CID_ID(0x81ceU) | CID_FLAG)
++#define CID_LL_CLCD                 (CID_ID(0x81cfU) | CID_FLAG)
++#define CID_HW_VDE                  (CID_ID(0x81d0U) | CID_FLAG)
++#define CID_LL_VDE                  (CID_ID(0x81d1U) | CID_FLAG)
++#define CID_HW_MCSPI                (CID_ID(0x81d2U) | CID_FLAG)
++#define CID_LL_MCSPI                (CID_ID(0x81d3U) | CID_FLAG)
++#define CID_HW_PWM                  (CID_ID(0x81d4U) | CID_FLAG)
++#define CID_LL_PWM                  (CID_ID(0x81d5U) | CID_FLAG)
++#define CID_OSAL_NXM                (CID_ID(0x81d6U) | CID_FLAG)
++#define CID_MEMPROF                 (CID_ID(0x81d7U) | CID_FLAG)
++#define CID_ALCONSTRETCH            (CID_ID(0x81d8U) | CID_FLAG)
++#define CID_AUTOFOCUS               (CID_ID(0x81d9U) | CID_FLAG)
++#define CID_LL_DVDO2DTL             (CID_ID(0x81daU) | CID_FLAG)
++#define CID_HW_DVDO2DTL             (CID_ID(0x81dbU) | CID_FLAG)
++#define CID_LL_DTL2DVDO             (CID_ID(0x81dcU) | CID_FLAG)
++#define CID_HW_DTL2DVDO             (CID_ID(0x81ddU) | CID_FLAG)
++#define CID_LL_COLORMATRIX          (CID_ID(0x81deU) | CID_FLAG)
++#define CID_HW_COLORMATRIX          (CID_ID(0x81dfU) | CID_FLAG)
++#define CID_UHSPDIFOUT_ASYSATV      (CID_ID(0x81e0U) | CID_FLAG)
++#define CID_DL_NANDFLASH1           (CID_ID(0x81e1U) | CID_FLAG)
++#define CID_NANDBOOTFFS             (CID_ID(0x81e2U) | CID_FLAG)
++#define CID_CONNMGR_APROCTV         (CID_ID(0x81e3U) | CID_FLAG)
++#define CID_CONNMGRSTILLPLAYER      (CID_ID(0x81e4U) | CID_FLAG)
++#define CID_CONNMGRAUDIOPLAYER      (CID_ID(0x81e5U) | CID_FLAG)
++#define CID_DCDIP9028               (CID_ID(0x81e6U) | CID_FLAG)
++#define CID_CURLSRC_AUDIO           (CID_ID(0x81e7U) | CID_FLAG)
++#define CID_CONNMGRAVIMP4PLAYER     (CID_ID(0x81e8U) | CID_FLAG)
++#define CID_AUDIOVIDEOSYNC          (CID_ID(0x81e9U) | CID_FLAG)
++#define CID_PACKETLIST              (CID_ID(0x81eaU) | CID_FLAG)
++#define CID_ASYNCSINK               (CID_ID(0x81ebU) | CID_FLAG)
++#define CID_VSYNCSINK               (CID_ID(0x81ecU) | CID_FLAG)
++#define CID_XSYNCSINK               (CID_ID(0x81edU) | CID_FLAG)
++#define CID_PCIEXP                  (CID_ID(0x81eeU) | CID_FLAG)
++#define CID_SOD_KERNEL              (CID_ID(0x81efU) | CID_FLAG)
++#define CID_SOD_EMULATE             (CID_ID(0x81f0U) | CID_FLAG)
++#define CID_SOD_MGR                 (CID_ID(0x81f1U) | CID_FLAG)
++#define CID_NANDPARTTABLE           (CID_ID(0x81f2U) | CID_FLAG)
++#define CID_HW_AUDIO7136            (CID_ID(0x81f3U) | CID_FLAG)
++#define CID_SPI3409                 (CID_ID(0x81f4U) | CID_FLAG)
++#define CID_DCSS_MATH               (CID_ID(0x81f5U) | CID_FLAG)
++#define CID_DCSS_LIT_CSD            (CID_ID(0x81f6U) | CID_FLAG)
++#define CID_DCSS_LIT_M              (CID_ID(0x81f7U) | CID_FLAG)
++#define CID_ADT                     (CID_ID(0x81f8U) | CID_FLAG)
++#define CID_ACS                     (CID_ID(0x81f9U) | CID_FLAG)
++#define CID_ACB                     (CID_ID(0x81faU) | CID_FLAG)
++#define CID_ACL                     (CID_ID(0x81fbU) | CID_FLAG)
++#define CID_AVEPP                   (CID_ID(0x81fcU) | CID_FLAG)
++#define CID_UDSSIC                  (CID_ID(0x81fdU) | CID_FLAG)
++#define CID_PROXYI2C                (CID_ID(0x81feU) | CID_FLAG)
++#define CID_PL081DMA                (CID_ID(0x81feU) | CID_FLAG)
++#define CID_DD_CPIPE                (CID_ID(0x81ffU) | CID_FLAG)
++#define CID_DD_MBVP                 (CID_ID(0x8200U) | CID_FLAG)
++#define CID_CARENDAOUT              (CID_ID(0x8201U) | CID_FLAG)
++#define CID_CADIGAIN                (CID_ID(0x8202U) | CID_FLAG)
++#define CID_CONNMGR_TV506E          (CID_ID(0x8203U) | CID_FLAG)
++#define CID_ASYNCHANDLER            (CID_ID(0x8204U) | CID_FLAG)
++#define CID_COMP_M4VENCPSC          (CID_ID(0x8205U) | CID_FLAG)
++#define CID_CONNMGRNETSCHEMECONFIG  (CID_ID(0x8206U) | CID_FLAG)
++#define CID_CARACASSPIAHB           (CID_ID(0x8207U) | CID_FLAG)
++#define CID_COMP_ADECLPCM           (CID_ID(0x8208U) | CID_FLAG)
++#define CID_CDIGADEC_MULTISTD       (CID_ID(0x8209U) | CID_FLAG)
++#define CID_ADB                     (CID_ID(0x820aU) | CID_FLAG)
++#define CID_ADR                     (CID_ID(0x820bU) | CID_FLAG)
++#define CID_AGN                     (CID_ID(0x820cU) | CID_FLAG)
++#define CID_ANT                     (CID_ID(0x820dU) | CID_FLAG)
++#define CID_APP                     (CID_ID(0x820eU) | CID_FLAG)
++#define CID_ASC                     (CID_ID(0x820fU) | CID_FLAG)
++#define CID_ASM                     (CID_ID(0x8210U) | CID_FLAG)
++#define CID_ASS                     (CID_ID(0x8211U) | CID_FLAG)
++#define CID_ATP                     (CID_ID(0x8212U) | CID_FLAG)
++#define CID_VDEC_MJPEG              (CID_ID(0x8213U) | CID_FLAG)
++#define CID_MOV_READ                (CID_ID(0x8214U) | CID_FLAG)
++#define CID_EWIFI                   (CID_ID(0x8215U) | CID_FLAG)
++#define CID_SCR                     (CID_ID(0x8216U) | CID_FLAG)
++#define CID_AEPP                    (CID_ID(0x8217U) | CID_FLAG)
++#define CID_VEPP                    (CID_ID(0x8218U) | CID_FLAG)
++#define CID_MP3ENC                  (CID_ID(0x8219U) | CID_FLAG)
++#define CID_TDFLOADER               (CID_ID(0x821aU) | CID_FLAG)
++#define CID_VIOSYNC                 (CID_ID(0x821bU) | CID_FLAG)
++#define CID_STBDP                   (CID_ID(0x821cU) | CID_FLAG)
++#define CID_STBEVENT                (CID_ID(0x821dU) | CID_FLAG)
++#define CID_STBFB                   (CID_ID(0x821eU) | CID_FLAG)
++#define CID_STBDEMUX                (CID_ID(0x821fU) | CID_FLAG)
++#define CID_STBFILE                 (CID_ID(0x8220U) | CID_FLAG)
++#define CID_STBGPIO                 (CID_ID(0x8221U) | CID_FLAG)
++#define CID_STBI2C                  (CID_ID(0x8222U) | CID_FLAG)
++#define CID_STBMMIOBUS              (CID_ID(0x8223U) | CID_FLAG)
++#define CID_STBPROC                 (CID_ID(0x8224U) | CID_FLAG)
++#define CID_STBROOT                 (CID_ID(0x8225U) | CID_FLAG)
++#define CID_STBRPC                  (CID_ID(0x8226U) | CID_FLAG)
++#define CID_STBRTC                  (CID_ID(0x8227U) | CID_FLAG)
++#define CID_STBTMLOAD               (CID_ID(0x8228U) | CID_FLAG)
++#define CID_STBSTREAMINGSYSTEM      (CID_ID(0x8229U) | CID_FLAG)
++#define CID_STBVIDEOSCALER          (CID_ID(0x822aU) | CID_FLAG)
++#define CID_STBANALOGBACKEND        (CID_ID(0x822bU) | CID_FLAG)
++#define CID_STBVIDEORENDERER        (CID_ID(0x822cU) | CID_FLAG)
++#define CID_DRV_MMU                 (CID_ID(0x822dU) | CID_FLAG)
++#define CID_COMP_AINJECTOR          (CID_ID(0x822eU) | CID_FLAG)
++#define CID_VDEC_ANA                (CID_ID(0x822fU) | CID_FLAG)
++#define CID_STBAC3AUD               (CID_ID(0x8230U) | CID_FLAG)
++#define CID_STBAUDIO                (CID_ID(0x8231U) | CID_FLAG)
++#define CID_PHMODARM11WRAPPER       (CID_ID(0x8232U) | CID_FLAG)
++#define CID_GPIO_IP4004             (CID_ID(0x8233U) | CID_FLAG)
++#define CID_TMCADIGSPDIFIN          (CID_ID(0x8234U) | CID_FLAG)
++#define CID_TMCARENDSPDIFOUT        (CID_ID(0x8235U) | CID_FLAG)
++#define CID_TMCPLFINSTAIN           (CID_ID(0x8236U) | CID_FLAG)
++#define CID_TMCPLFINSTAOUT          (CID_ID(0x8237U) | CID_FLAG)
++#define CID_TMCSPDIFIN              (CID_ID(0x8238U) | CID_FLAG)
++#define CID_TMCSPDIFOUT             (CID_ID(0x8239U) | CID_FLAG)
++#define CID_BSL_HDMIRX              (CID_ID(0x823aU) | CID_FLAG)
++#define CID_AACPENC                 (CID_ID(0x823bU) | CID_FLAG)
++#define CID_DL_HDMIRX               (CID_ID(0x823cU) | CID_FLAG)
++#define CID_APP_HDMIRX              (CID_ID(0x823dU) | CID_FLAG)
++#define CID_INFRA_HDMI              (CID_ID(0x823eU) | CID_FLAG)
++#define CID_DL_HDMICEC              (CID_ID(0x823fU) | CID_FLAG)
++#define CID_BSL_HDMITX              (CID_ID(0x8240U) | CID_FLAG)
++#define CID_DL_HDMITX               (CID_ID(0x8241U) | CID_FLAG)
++#define CID_APP_HDMITX              (CID_ID(0x8242U) | CID_FLAG)
++
++/*define CID_UART                   (CID_ID(0x80a5U) | CID_FLAG) already defined*/
++#define CID_CHIP                    (CID_ID(0x815bU) | CID_FLAG)
++
++#define CID_RESERVED                (CID_ID(0xff80U) | CID_FLAG)
++/* ************************************************************************** */
++/* Component Id's reserved for external organizations                         */
++/*                                                                            */
++/*                            0xff80 thru 0xffbf                              */
++/* Range of component ID's is reserved for the use of parties outside of      */
++/*  Philips that wish to use component ID's privately.                        */
++/*  If a component is going to be exchanged in the 'PS Ecosystem', then a     */
++/*  public component ID should be registered with MoReUse.                    */
++/*                                                                            */
++/* Range to be used by CE Television Systems                                  */
++/*                            0xffc0 thru 0xffff                              */
++/*                                                                            */
++/* ************************************************************************** */
++
++/* -------------------------------------------------------------------------- */
++/*                                                                            */
++/* Component ID types are defined as unsigned 32 bit integers (UInt32)        */
++/* Interface ID types are defined as unsigned 32 bit integers (UInt32)        */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++
++/* -------------------------------------------------------------------------- */
++/*                                                                            */
++/*  Obsolete Component ID values                                              */
++/*                                                                            */
++/* -------------------------------------------------------------------------- */
++
++/* -------------------------------------------------------------------------- */
++/* Component Class definitions (bits 31:28, 4 bits)                           */
++/* NOTE: A class of 0x0 must not be defined to ensure that the overall 32 bit */
++/*       component ID/status combination is always non-0 (no TM_OK conflict). */
++/* -------------------------------------------------------------------------- */
++#define CID_CLASS_BITSHIFT  28
++#define CID_CLASS_BITMASK   (0xFU << CID_CLASS_BITSHIFT)
++#define CID_GET_CLASS(compId) ((compId & CID_CLASS_BITMASK) >> CID_CLASS_BITSHIFT)
++
++#define CID_CLASS_NONE      (0x1U << CID_CLASS_BITSHIFT)
++#define CID_CLASS_VIDEO     (0x2U << CID_CLASS_BITSHIFT)
++#define CID_CLASS_AUDIO     (0x3U << CID_CLASS_BITSHIFT)
++#define CID_CLASS_GRAPHICS  (0x4U << CID_CLASS_BITSHIFT)
++#define CID_CLASS_BUS       (0x5U << CID_CLASS_BITSHIFT)
++#define CID_CLASS_INFRASTR  (0x6U << CID_CLASS_BITSHIFT)
++
++#define CID_CLASS_CUSTOMER  (0xFU << CID_CLASS_BITSHIFT)
++
++/* -------------------------------------------------------------------------- */
++/* Component Type definitions (bits 27:24, 4 bits)                            */
++/* -------------------------------------------------------------------------- */
++#define CID_TYPE_BITSHIFT   24
++#define CID_TYPE_BITMASK    (0xFU << CID_TYPE_BITSHIFT)
++#define CID_GET_TYPE(compId)  ((compId & CID_TYPE_BITMASK) >> CID_TYPE_BITSHIFT)
++
++#define CID_TYPE_NONE       (0x0U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_SOURCE     (0x1U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_SINK       (0x2U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_ENCODER    (0x3U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_DECODER    (0x4U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_MUX        (0x5U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_DEMUX      (0x6U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_DIGITIZER  (0x7U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_RENDERER   (0x8U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_FILTER     (0x9U << CID_TYPE_BITSHIFT)
++#define CID_TYPE_CONTROL    (0xAU << CID_TYPE_BITSHIFT)
++#define CID_TYPE_DATABASE   (0xBU << CID_TYPE_BITSHIFT)
++#define CID_TYPE_SUBSYSTEM  (0xCU << CID_TYPE_BITSHIFT)
++#define CID_TYPE_CUSTOMER   (0xFU << CID_TYPE_BITSHIFT)
++
++/* -------------------------------------------------------------------------- */
++/* Component Tag definitions (bits 23:16, 8 bits)                             */
++/* NOTE: Component tags are defined in groups, dependent on the class and     */
++/* type.                                                                      */
++/* -------------------------------------------------------------------------- */
++#define CID_TAG_BITSHIFT    16
++#define CID_TAG_BITMASK     (0xFFU << CID_TAG_BITSHIFT)
++
++#define CID_TAG_NONE        (0x00U << CID_TAG_BITSHIFT)
++
++#define CID_TAG_CUSTOMER    (0xE0U << CID_TAG_BITSHIFT)
++
++#define TAG(number)         ((number) << CID_TAG_BITSHIFT)
++
++/* -------------------------------------------------------------------------- */
++/* General Component Layer definitions (bits 15:12, 4 bits)                   */
++/* -------------------------------------------------------------------------- */
++#define CID_LAYER_BITSHIFT  12
++#define CID_LAYER_BITMASK   (0xF << CID_LAYER_BITSHIFT)
++#define CID_GET_LAYER(compId) ((compId & CID_LAYER_BITMASK) >> CID_LAYER_BITSHIFT)
++
++#define CID_LAYER_NONE      (0x0U << CID_LAYER_BITSHIFT)
++#define CID_LAYER_BTM       (0x1U << CID_LAYER_BITSHIFT)
++#define CID_LAYER_HWAPI     (0x2U << CID_LAYER_BITSHIFT)
++#define CID_LAYER_BSL       (0x3U << CID_LAYER_BITSHIFT)
++#define CID_LAYER_DEVLIB    (0x4U << CID_LAYER_BITSHIFT)
++#define CID_LAYER_TMAL      (0x5U << CID_LAYER_BITSHIFT)
++#define CID_LAYER_TMOL      (0x6U << CID_LAYER_BITSHIFT)
++#define CID_LAYER_TMNL      (0xEU << CID_LAYER_BITSHIFT)
++
++/* -------------------------------------------------------------------------- */
++/*   "new" i.e. after 2002-01-31 layer definitions                            */
++/* "New" Component Layers depend on the component type and class              */
++/* So we can have an identical layer value for each type/class combination    */
++/* In order not to break existing code that assumes that layers are unique,   */
++/* we start new layers at 0x7                                                 */
++/* -------------------------------------------------------------------------- */
++
++/*------------------ CTYP_BUS_NOTYPE dependent layer definitions -------------*/
++#define CID_LAYER_UDS      (0x7U << CID_LAYER_BITSHIFT)  /* USB Device Stack   */
++#define CID_LAYER_UHS      (0x8U << CID_LAYER_BITSHIFT)  /* USB Host stack     */
++#define CID_LAYER_UOTG     (0x9U << CID_LAYER_BITSHIFT)  /* USB OTG stack      */
++
++#define CID_LAYER_CUSTOMER  (0xFU << CID_LAYER_BITSHIFT) /* Customer Defined   */
++
++/* -------------------------------------------------------------------------- */
++/* Component Identifier definitions (bits 31:12, 20 bits)                     */
++/* NOTE: These DVP platform component identifiers are designed to be unique   */
++/*       within the system.  The component identifier encompasses the class   */
++/*       (CID_CLASS_XXX), type (CID_TYPE_XXX), tag, and layer (CID_LAYER_XXX) */
++/*       fields to form the unique component identifier.  This allows any     */
++/*       error/progress status value to be identified as to its original      */
++/*       source, whether or not the source component s header file is present.*/
++/*       The standard error/progress status definitions should be used        */
++/*       whenever possible to ease status interpretation.  No layer           */
++/*       information is defined at this point; it should be ORed into the API */
++/*       status values defined in the APIs header file.                       */
++/* -------------------------------------------------------------------------- */
++#if     (CID_LAYER_NONE != 0)
++#error  ERROR: DVP component identifiers require the layer type 'NONE' = 0 !
++#endif
++
++/* -------------------------------------------------------------------------- */
++/* Classless Types/Components (don t fit into other class categories)         */
++/* -------------------------------------------------------------------------- */
++#define CTYP_NOCLASS_NOTYPE       (CID_CLASS_NONE | CID_TYPE_NONE)
++#define CTYP_NOCLASS_SOURCE       (CID_CLASS_NONE | CID_TYPE_SOURCE)
++#define CTYP_NOCLASS_SINK         (CID_CLASS_NONE | CID_TYPE_SINK)
++#define CTYP_NOCLASS_MUX          (CID_CLASS_NONE | CID_TYPE_MUX)
++#define CTYP_NOCLASS_DEMUX        (CID_CLASS_NONE | CID_TYPE_DEMUX)
++#define CTYP_NOCLASS_FILTER       (CID_CLASS_NONE | CID_TYPE_FILTER)
++#define CTYP_NOCLASS_CONTROL      (CID_CLASS_NONE | CID_TYPE_CONTROL)
++#define CTYP_NOCLASS_DATABASE     (CID_CLASS_NONE | CID_TYPE_DATABASE)
++#define CTYP_NOCLASS_SUBSYS       (CID_CLASS_NONE | CID_TYPE_SUBSYSTEM)
++
++#define CID_COMP_CLOCK            (TAG(0x01U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_DMA              (TAG(0x02U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_PIC              (TAG(0x03U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_NORFLASH         (TAG(0x04U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_NANDFLASH        (TAG(0x05U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_GPIO             (TAG(0x06U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_SMARTCARD        (TAG(0x07U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_UDMA             (TAG(0x08U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_DSP              (TAG(0x09U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_TIMER            (TAG(0x0AU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_TSDMA            (TAG(0x0BU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_MMIARB           (TAG(0x0CU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_EEPROM           (TAG(0x0DU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_PARPORT          (TAG(0x0EU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_VSS              (TAG(0x0FU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_TSIO             (TAG(0x10U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_DBG              (TAG(0x11U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_TTE              (TAG(0x12U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_AVPROP           (TAG(0x13U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_SERIAL_RAM       (TAG(0x14U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_SMARTMEDIA       (TAG(0x15U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_COMPACT_FLASH    (TAG(0x16U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_CI               (TAG(0x17U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_INT_ALARM        (TAG(0x18U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_TASK_ALARM       (TAG(0x19U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_XDMA             (TAG(0x1AU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_ICC              (TAG(0x1BU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_CONNMGR          (TAG(0x1CU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_CONNMGRVSYSTV    (TAG(0x1DU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_VBISLICERVSYSTV  (TAG(0x1EU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_VMIXVSYSTV       (TAG(0x1FU) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_NTF              (TAG(0x20U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_NTY              CID_COMP_NTF  /* legacy */
++#define CID_COMP_FATERR           (TAG(0x21U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_DVBTDEMOD        (TAG(0x22U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_HYBRIDTUNER      (TAG(0x23U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_VLD              (TAG(0x24U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_GIC              (TAG(0x25U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_WEB              (TAG(0x26U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_ANAEPGDB         (TAG(0x27U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_HWSEM            (TAG(0x28U) | CTYP_NOCLASS_NOTYPE)
++#define CID_COMP_MMON             (TAG(0x29U) | CTYP_NOCLASS_NOTYPE)
++
++#define CID_COMP_FREAD            (TAG(0x01U) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_CDRREAD          (TAG(0x02U) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_VSB              (TAG(0x03U) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_ANALOGTVTUNER    (TAG(0x04U) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_TPINMPEG2        (TAG(0x05U) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_DREAD            (TAG(0x06U) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_TREAD            (TAG(0x07U) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_RTC              (TAG(0x08U) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_TOUCHC           (TAG(0x09U) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_KEYPAD           (TAG(0x0AU) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_ADC              (TAG(0x0BU) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_READLIST         (TAG(0x0CU) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_FROMDISK         (TAG(0x0DU) | CTYP_NOCLASS_SOURCE)
++#define CID_COMP_SOURCE           (TAG(0x0EU) | CTYP_NOCLASS_SOURCE)
++
++#define CID_COMP_FWRITE           (TAG(0x01U) | CTYP_NOCLASS_SINK)
++#define CID_COMP_CDWRITE          (TAG(0x02U) | CTYP_NOCLASS_SINK)
++#define CID_COMP_CHARLCD          (TAG(0x03U) | CTYP_NOCLASS_SINK)
++#define CID_COMP_PWM              (TAG(0x04U) | CTYP_NOCLASS_SINK)
++#define CID_COMP_DAC              (TAG(0x05U) | CTYP_NOCLASS_SINK)
++#define CID_COMP_TSDMAINJECTOR    (TAG(0x06U) | CTYP_NOCLASS_SINK)
++#define CID_COMP_TODISK           (TAG(0x07U) | CTYP_NOCLASS_SINK)
++
++#define CID_COMP_MUXMPEGPS        (TAG(0x01U) | CTYP_NOCLASS_MUX)
++#define CID_COMP_MUXMPEG          (TAG(0x02U) | CTYP_NOCLASS_MUX)
++
++#define CID_COMP_DEMUXMPEGTS      (TAG(0x01U) | CTYP_NOCLASS_DEMUX)
++#define CID_COMP_DEMUXMPEGPS      (TAG(0x02U) | CTYP_NOCLASS_DEMUX)
++#define CID_COMP_DEMUXDV          (TAG(0x03U) | CTYP_NOCLASS_DEMUX)
++
++#define CID_COMP_COPYIO           (TAG(0x01U) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_COPYINPLACE      (TAG(0x02U) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_UART             (TAG(0x03U) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_SSI              (TAG(0x04U) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_MODEMV34         (TAG(0x05U) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_MODEMV42         (TAG(0x06U) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_HTMLPARSER       (TAG(0x07U) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_VMSP             (TAG(0x08U) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_X                (TAG(0x09U) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_TXTSUBTDECEBU    (TAG(0x0AU) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_CPI              (TAG(0x0BU) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_TRICK            (TAG(0x0CU) | CTYP_NOCLASS_FILTER)
++#define CID_COMP_FWRITEFREAD      (TAG(0x0DU) | CTYP_NOCLASS_FILTER)
++
++#define CID_COMP_REMCTL5          (TAG(0x01U) | CTYP_NOCLASS_CONTROL)
++#define CID_COMP_INFRARED         (TAG(0x02U) | CTYP_NOCLASS_CONTROL)
++
++#define CID_COMP_PSIP             (TAG(0x01U) | CTYP_NOCLASS_DATABASE)
++#define CID_COMP_IDE              (TAG(0x02U) | CTYP_NOCLASS_DATABASE)
++#define CID_COMP_DISKSCHED        (TAG(0x03U) | CTYP_NOCLASS_DATABASE)
++#define CID_COMP_AVFS             (TAG(0x04U) | CTYP_NOCLASS_DATABASE)
++#define CID_COMP_MDB              (TAG(0x05U) | CTYP_NOCLASS_DATABASE)
++#define CID_COMP_ATAPI_CMDS       (TAG(0x06U) | CTYP_NOCLASS_DATABASE)
++
++#define CID_COMP_IRDMMPEG         (TAG(0x01U) | CTYP_NOCLASS_SUBSYS)
++#define CID_COMP_STORSYS          (TAG(0x02U) | CTYP_NOCLASS_SUBSYS)
++#define CID_COMP_PMU              (TAG(0x03U) | CTYP_NOCLASS_SUBSYS)
++
++/* -------------------------------------------------------------------------- */
++/* Video Class Types/Components (video types handle video/graphics data)      */
++/* -------------------------------------------------------------------------- */
++#define CTYP_VIDEO_SINK            (CID_CLASS_VIDEO | CID_TYPE_SINK)
++#define CTYP_VIDEO_SOURCE          (CID_CLASS_VIDEO | CID_TYPE_SOURCE)
++#define CTYP_VIDEO_ENCODER         (CID_CLASS_VIDEO | CID_TYPE_ENCODER)
++#define CTYP_VIDEO_DECODER         (CID_CLASS_VIDEO | CID_TYPE_DECODER)
++#define CTYP_VIDEO_DIGITIZER       (CID_CLASS_VIDEO | CID_TYPE_DIGITIZER)
++#define CTYP_VIDEO_RENDERER        (CID_CLASS_VIDEO | CID_TYPE_RENDERER)
++#define CTYP_VIDEO_FILTER          (CID_CLASS_VIDEO | CID_TYPE_FILTER)
++#define CTYP_VIDEO_SUBSYS          (CID_CLASS_VIDEO | CID_TYPE_SUBSYSTEM)
++
++#define CID_COMP_LCD               (TAG(0x01U) | CTYP_VIDEO_SINK)
++
++#define CID_COMP_VCAPVI            (TAG(0x01U) | CTYP_VIDEO_SOURCE)
++#define CID_COMP_VIP               (TAG(0x02U) | CTYP_VIDEO_SOURCE)
++#define CID_COMP_VI                (TAG(0x03U) | CTYP_VIDEO_SOURCE)
++#define CID_COMP_VSLICER           (TAG(0x04U) | CTYP_VIDEO_SOURCE)
++#define CID_COMP_FBREAD            (TAG(0x05U) | CTYP_VIDEO_SOURCE)
++#define CID_COMP_QVI               (TAG(0x06U) | CTYP_VIDEO_SOURCE)
++#define CID_COMP_CAMERA            (TAG(0x07U) | CTYP_VIDEO_SOURCE)
++#define CID_COMP_CAM_SENSOR        (TAG(0x08U) | CTYP_VIDEO_SOURCE)
++
++#define CID_COMP_VENCM1            (TAG(0x01U) | CTYP_VIDEO_ENCODER)
++#define CID_COMP_VENCM2            (TAG(0x02U) | CTYP_VIDEO_ENCODER)
++#define CID_COMP_VENCMJ            (TAG(0x03U) | CTYP_VIDEO_ENCODER)
++#define CID_COMP_VENCH263          (TAG(0x04U) | CTYP_VIDEO_ENCODER)
++#define CID_COMP_VENCH261          (TAG(0x05U) | CTYP_VIDEO_ENCODER)
++#define CID_COMP_M4VENC            (TAG(0x06U) | CTYP_VIDEO_ENCODER)
++#define CID_COMP_M4VENCME          (TAG(0x07U) | CTYP_VIDEO_ENCODER)
++#define CID_COMP_M4VENCTC          (TAG(0x08U) | CTYP_VIDEO_ENCODER)
++#define CID_COMP_M4VENCBSG         (TAG(0x09U) | CTYP_VIDEO_ENCODER)
++#define CID_COMP_M4VENCJPEG        (TAG(0x0AU) | CTYP_VIDEO_ENCODER)
++
++#define CID_COMP_VDECM1            (TAG(0x01U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECM2            (TAG(0x02U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECMPEG          (TAG(0x03U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECMJ            (TAG(0x04U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECSUBPICSVCD    (TAG(0x05U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECH263          (TAG(0x06U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECH261          (TAG(0x07U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDEC              (TAG(0x08U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECSUBPICDVD     (TAG(0x09U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECSUBPICBMPDVD  (TAG(0x0AU) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECSUBPICRENDDVD (TAG(0x0BU) | CTYP_VIDEO_DECODER)
++#define CID_COMP_M4PP              (TAG(0x0CU) | CTYP_VIDEO_DECODER)
++#define CID_COMP_M4MC              (TAG(0x0DU) | CTYP_VIDEO_DECODER)
++#define CID_COMP_M4CSC             (TAG(0x0EU) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECTXT           (TAG(0x0FU) | CTYP_VIDEO_DECODER)
++#define CID_COMP_VDECDV            (TAG(0x10U) | CTYP_VIDEO_DECODER)
++#define CID_COMP_BACKANIM          (TAG(0x11U) | CTYP_VIDEO_DECODER)
++
++#define CID_COMP_VDIG              (TAG(0x01U) | CTYP_VIDEO_DIGITIZER)
++#define CID_COMP_VDIGVIRAW         (TAG(0x02U) | CTYP_VIDEO_DIGITIZER)
++#define CID_COMP_VDIG_EXT          (TAG(0x03U) | CTYP_VIDEO_DIGITIZER)
++#define CID_COMP_VDIG_VBI          (TAG(0x04U) | CTYP_VIDEO_DIGITIZER)
++#define CID_COMP_VDIG_EXT_VBI      (TAG(0x05U) | CTYP_VIDEO_DIGITIZER)
++
++#define CID_COMP_VREND             (TAG(0x01U) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_HDVO              (TAG(0x02U) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_VRENDGFXVO        (TAG(0x03U) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_AICP              (TAG(0x04U) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_VRENDVORAW        (TAG(0x05U) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_VO                (TAG(0x06U) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_VRENDVOICP        (TAG(0x07U) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_VMIX              (TAG(0x08U) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_QVCP              (TAG(0x09U) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_VREND_EXT         (TAG(0x0AU) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_VENCANA           (TAG(0x0BU) | CTYP_VIDEO_RENDERER)
++#define CID_COMP_QVO               (TAG(0x0CU) | CTYP_VIDEO_RENDERER)
++
++#define CID_COMP_MBS               (TAG(0x01U) | CTYP_VIDEO_FILTER)
++#define CID_COMP_VTRANS            (TAG(0x02U) | CTYP_VIDEO_FILTER)
++#define CID_COMP_QNM               (TAG(0x03U) | CTYP_VIDEO_FILTER)
++#define CID_COMP_ICP               (TAG(0x04U) | CTYP_VIDEO_FILTER)
++#define CID_COMP_VTRANSNM          (TAG(0x05U) | CTYP_VIDEO_FILTER)
++#define CID_COMP_QFD               (TAG(0x06U) | CTYP_VIDEO_FILTER)
++#define CID_COMP_VTRANSDVD         (TAG(0x07U) | CTYP_VIDEO_FILTER)
++#define CID_COMP_VTRANSCRYSTAL     (TAG(0x08U) | CTYP_VIDEO_FILTER)
++#define CID_COMP_VTRANSUD          (TAG(0x09U) | CTYP_VIDEO_FILTER)
++/*#define CID_COMP_QTNR           (TAG(0x0AU) | CTYP_VIDEO_FILTER) Removed v17:  Replaced with CID_VTRANS_QTNR */
++
++#define CID_COMP_VSYSMT3           (TAG(0x01U) | CTYP_VIDEO_SUBSYS)
++#define CID_COMP_VSYSSTB           (TAG(0x01U) | CTYP_VIDEO_SUBSYS)
++#define CID_COMP_DVDVIDSYS         (TAG(0x02U) | CTYP_VIDEO_SUBSYS)
++#define CID_COMP_VDECUD            (TAG(0x03U) | CTYP_VIDEO_SUBSYS)
++#define CID_COMP_VIDSYS            (TAG(0x04U) | CTYP_VIDEO_SUBSYS)
++#define CID_COMP_VSYSTV            (TAG(0x05U) | CTYP_VIDEO_SUBSYS)
++
++/* -------------------------------------------------------------------------- */
++/* Audio Class Types/Components (audio types primarily handle audio data)     */
++/* -------------------------------------------------------------------------- */
++#define CTYP_AUDIO_NOTYPE       (CID_CLASS_AUDIO | CID_TYPE_NONE)
++#define CTYP_AUDIO_SINK         (CID_CLASS_AUDIO | CID_TYPE_SINK)
++#define CTYP_AUDIO_SOURCE       (CID_CLASS_AUDIO | CID_TYPE_SOURCE)
++#define CTYP_AUDIO_ENCODER      (CID_CLASS_AUDIO | CID_TYPE_ENCODER)
++#define CTYP_AUDIO_DECODER      (CID_CLASS_AUDIO | CID_TYPE_DECODER)
++#define CTYP_AUDIO_DIGITIZER    (CID_CLASS_AUDIO | CID_TYPE_DIGITIZER)
++#define CTYP_AUDIO_RENDERER     (CID_CLASS_AUDIO | CID_TYPE_RENDERER)
++#define CTYP_AUDIO_FILTER       (CID_CLASS_AUDIO | CID_TYPE_FILTER)
++#define CTYP_AUDIO_SUBSYS       (CID_CLASS_AUDIO | CID_TYPE_SUBSYSTEM)
++
++#define CID_COMP_CODEC          (TAG(0x01U) | CTYP_AUDIO_NOTYPE)
++
++#define CID_COMP_SDAC           (TAG(0x01U) | CTYP_AUDIO_SINK)
++
++#define CID_COMP_ADIGAI         (TAG(0x01U) | CTYP_AUDIO_DIGITIZER)
++#define CID_COMP_ADIGSPDIF      (TAG(0x02U) | CTYP_AUDIO_DIGITIZER)
++
++#define CID_COMP_ARENDAO        (TAG(0x01U) | CTYP_AUDIO_RENDERER)
++#define CID_COMP_ARENDSPDIF     (TAG(0x02U) | CTYP_AUDIO_RENDERER)
++
++#define CID_COMP_NOISESEQ       (TAG(0x03U) | CTYP_AUDIO_SOURCE)
++
++#define CID_COMP_AENCAC3        (TAG(0x01U) | CTYP_AUDIO_ENCODER)
++#define CID_COMP_AENCMPEG1      (TAG(0x02U) | CTYP_AUDIO_ENCODER)
++#define CID_COMP_AENCAAC        (TAG(0x03U) | CTYP_AUDIO_ENCODER)
++#define CID_COMP_AENCG723       (TAG(0x04U) | CTYP_AUDIO_ENCODER)
++#define CID_COMP_AENCG728       (TAG(0x05U) | CTYP_AUDIO_ENCODER)
++#define CID_COMP_AENCWMA        (TAG(0x06U) | CTYP_AUDIO_ENCODER)
++#define CID_COMP_AVENCMPEG      (TAG(0x07U) | CTYP_AUDIO_ENCODER)
++#define CID_COMP_AENCMP3        (TAG(0x08U) | CTYP_AUDIO_ENCODER)
++
++#define CID_COMP_ADECPROLOGIC   (TAG(0x01U) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECAC3        (TAG(0x02U) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECMPEG1      (TAG(0x03U) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECMP3        (TAG(0x04U) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECAAC        (TAG(0x05U) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECG723       (TAG(0x06U) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECG728       (TAG(0x07U) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECWMA        (TAG(0x08U) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECTHRU       (TAG(0x09U) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADEC           (TAG(0x0AU) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECPCM        (TAG(0x0BU) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECDV         (TAG(0x0CU) | CTYP_AUDIO_DECODER)
++#define CID_COMP_ADECDTS        (TAG(0x0DU) | CTYP_AUDIO_DECODER)
++
++#define CID_COMP_ASPLIB         (TAG(0x01U) | CTYP_AUDIO_FILTER)
++#define CID_COMP_IIR            (TAG(0x02U) | CTYP_AUDIO_FILTER)
++#define CID_COMP_ASPEQ2         (TAG(0x03U) | CTYP_AUDIO_FILTER)
++#define CID_COMP_ASPEQ5         (TAG(0x04U) | CTYP_AUDIO_FILTER)
++#define CID_COMP_ASPBASSREDIR   (TAG(0x05U) | CTYP_AUDIO_FILTER)
++#define CID_COMP_ASPLAT2        (TAG(0x06U) | CTYP_AUDIO_FILTER)
++#define CID_COMP_ASPPLUGIN      (TAG(0x07U) | CTYP_AUDIO_FILTER)
++#define CID_COMP_AMIXDTV        (TAG(0x08U) | CTYP_AUDIO_FILTER)
++#define CID_COMP_AMIXSIMPLE     (TAG(0x09U) | CTYP_AUDIO_FILTER)
++#define CID_COMP_AMIXSTB        (TAG(0x0AU) | CTYP_AUDIO_FILTER)
++#define CID_COMP_ASPEQ          (TAG(0x0BU) | CTYP_AUDIO_FILTER)
++#define CID_COMP_ATESTSIG       (TAG(0x0CU) | CTYP_AUDIO_FILTER)
++#define CID_COMP_APROC          (TAG(0x0DU) | CTYP_AUDIO_FILTER)
++
++#define CID_COMP_AUDSUBSYS      (TAG(0x01U) | CTYP_AUDIO_SUBSYS)
++#define CID_COMP_AUDSYSSTB      (TAG(0x02U) | CTYP_AUDIO_SUBSYS)
++#define CID_COMP_AUDSYSDVD      (TAG(0x03U) | CTYP_AUDIO_SUBSYS)
++#define CID_COMP_MMC            (TAG(0x04U) | CTYP_AUDIO_SUBSYS)
++#define CID_COMP_COMP_MMC       CID_COMP_MMC  /* legacy */
++#define CID_COMP_ASYSATV        (TAG(0x05U) | CTYP_AUDIO_SUBSYS)
++
++/* -------------------------------------------------------------------------- */
++/* Graphics Class Types/Components                                            */
++/* -------------------------------------------------------------------------- */
++#define CTYP_GRAPHICS_RENDERER  (CID_CLASS_GRAPHICS | CID_TYPE_SINK)
++
++#define CID_COMP_WM             (TAG(0x01U) | CTYP_GRAPHICS_RENDERER)
++#define CID_COMP_WIDGET         (TAG(0x02U) | CTYP_GRAPHICS_RENDERER)
++#define CID_COMP_OM             (TAG(0x03U) | CTYP_GRAPHICS_RENDERER)
++#define CID_COMP_HTMLRENDER     (TAG(0x04U) | CTYP_GRAPHICS_RENDERER)
++#define CID_COMP_VRENDEIA708    (TAG(0x05U) | CTYP_GRAPHICS_RENDERER)
++#define CID_COMP_VRENDEIA608    (TAG(0x06U) | CTYP_GRAPHICS_RENDERER)
++
++#define CTYP_GRAPHICS_DRAW      (CID_CLASS_GRAPHICS | CID_TYPE_NONE)
++
++#define CID_COMP_DRAW           (TAG(0x10U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_DRAW_UT        (TAG(0x11U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_DRAW_DE        (TAG(0x12U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_DRAW_REF       (TAG(0x13U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_DRAW_TMH       (TAG(0x14U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_DRAW_TMT       (TAG(0x15U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_DRAW_TMTH      (TAG(0x16U) | CTYP_GRAPHICS_DRAW)
++
++#define CID_COMP_3D             (TAG(0x30U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_JAWT           (TAG(0x31U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_JINPUT         (TAG(0x32U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_LWM            (TAG(0x33U) | CTYP_GRAPHICS_DRAW)
++#define CID_COMP_2D             (TAG(0x34U) | CTYP_GRAPHICS_DRAW)
++
++/* -------------------------------------------------------------------------- */
++/* Bus Class Types/Components (busses connect hardware components together)   */
++/* -------------------------------------------------------------------------- */
++#define CTYP_BUS_NOTYPE         (CID_CLASS_BUS | CID_TYPE_NONE)
++
++#define CID_COMP_XIO            (TAG(0x01U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_IIC            (TAG(0x02U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_PCI            (TAG(0x03U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_P1394          (TAG(0x04U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_ENET           (TAG(0x05U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_ATA            (TAG(0x06U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_CAN            (TAG(0x07U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UCGDMA         (TAG(0x08U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_I2S            (TAG(0x09U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_SPI            (TAG(0x0AU) | CTYP_BUS_NOTYPE)
++#define CID_COMP_PCM            (TAG(0x0BU) | CTYP_BUS_NOTYPE)
++#define CID_COMP_L3             (TAG(0x0CU) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSPFL         (TAG(0x0DU) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSRSL         (TAG(0x0EU) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSMSBOT       (TAG(0x0FU) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSMSCBI       (TAG(0x10U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSAUDIO       (TAG(0x11U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSHID         (TAG(0x12U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSCDC         (TAG(0x13U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSPRINTER     (TAG(0x14U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSSCSI        (TAG(0x15U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSMODEM       (TAG(0x16U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UDSETHERNET    (TAG(0x17U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UHSPFL         (TAG(0x18U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UHSMS          (TAG(0x19U) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UHSAUDIO       (TAG(0x1AU) | CTYP_BUS_NOTYPE)
++#define CID_COMP_UHSSCSI        (TAG(0x1BU) | CTYP_BUS_NOTYPE)
++
++/* -------------------------------------------------------------------------- */
++/* Infrastructure Class Types/Components                                      */
++/* -------------------------------------------------------------------------- */
++#define CTYP_INFRASTR_NOTYPE    (CID_CLASS_INFRASTR | CID_TYPE_NONE)
++#define CTYP_INFRASTR_DATABASE  (CID_CLASS_INFRASTR | CID_TYPE_DATABASE)
++
++#define CID_COMP_OSAL           (TAG(0x01U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_MML            (TAG(0x02U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_TSSA_DEFAULTS  (TAG(0x03U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_RPC            (TAG(0x04U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_THI            (TAG(0x05U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_REGISTRY       (TAG(0x06U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_TMMAN          (TAG(0x07U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_LDT            (TAG(0x08U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_CPUCONN        (TAG(0x09U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_COMMQUE        (TAG(0x0AU) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_BSLMGR         (TAG(0x0BU) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_CR             (TAG(0x0CU) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_NODE           (TAG(0x0DU) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_COM            (TAG(0x0EU) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_UTIL           (TAG(0x0FU) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_SGLIST         (TAG(0x10U) | CTYP_INFRASTR_NOTYPE)
++#define CID_COMP_ARITH          (TAG(0x11U) | CTYP_INFRASTR_NOTYPE)
++
++#define CID_COMP_MULTIFS        (TAG(0x01U) | CTYP_INFRASTR_DATABASE)
++#define CID_COMP_SFS            (TAG(0x02U) | CTYP_INFRASTR_DATABASE)
++
++/* -------------------------------------------------------------------------- */
++/* Component Standard Error/Progress Status definitions (bits 11:0, 12 bits)  */
++/* NOTE: These status codes are ORed with the component identifier to create  */
++/*       component unique 32 bit status values.  The component status values  */
++/*       should be defined in the header files where the APIs are defined.    */
++/* -------------------------------------------------------------------------- */
++#define CID_ERR_BITMASK                 0xFFFU
++#define CID_ERR_BITSHIFT                0
++#define CID_GET_ERROR(compId)   ((compId & CID_ERR_BITMASK) >> CID_ERR_BITSHIFT)
++
++#define TM_ERR_COMPATIBILITY            0x001U /* SW Interface compatibility   */
++#define TM_ERR_MAJOR_VERSION            0x002U /* SW Major Version error       */
++#define TM_ERR_COMP_VERSION             0x003U /* SW component version error   */
++#define TM_ERR_BAD_MODULE_ID            0x004U /* SW - HW module ID error      */
++#define TM_ERR_BAD_UNIT_NUMBER          0x005U /* Invalid device unit number   */
++#define TM_ERR_BAD_INSTANCE             0x006U /* Bad input instance value     */
++#define TM_ERR_BAD_HANDLE               0x007U /* Bad input handle             */
++#define TM_ERR_BAD_INDEX                0x008U /* Bad input index              */
++#define TM_ERR_BAD_PARAMETER            0x009U /* Invalid input parameter      */
++#define TM_ERR_NO_INSTANCES             0x00AU /* No instances available       */
++#define TM_ERR_NO_COMPONENT             0x00BU /* Component is not present     */
++#define TM_ERR_NO_RESOURCES             0x00CU /* Resource is not available    */
++#define TM_ERR_INSTANCE_IN_USE          0x00DU /* Instance is already in use   */
++#define TM_ERR_RESOURCE_OWNED           0x00EU /* Resource is already in use   */
++#define TM_ERR_RESOURCE_NOT_OWNED       0x00FU /* Caller does not own resource */
++#define TM_ERR_INCONSISTENT_PARAMS      0x010U /* Inconsistent input params    */
++#define TM_ERR_NOT_INITIALIZED          0x011U /* Component is not initialized */
++#define TM_ERR_NOT_ENABLED              0x012U /* Component is not enabled     */
++#define TM_ERR_NOT_SUPPORTED            0x013U /* Function is not supported    */
++#define TM_ERR_INIT_FAILED              0x014U /* Initialization failed        */
++#define TM_ERR_BUSY                     0x015U /* Component is busy            */
++#define TM_ERR_NOT_BUSY                 0x016U /* Component is not busy        */
++#define TM_ERR_READ                     0x017U /* Read error                   */
++#define TM_ERR_WRITE                    0x018U /* Write error                  */
++#define TM_ERR_ERASE                    0x019U /* Erase error                  */
++#define TM_ERR_LOCK                     0x01AU /* Lock error                   */
++#define TM_ERR_UNLOCK                   0x01BU /* Unlock error                 */
++#define TM_ERR_OUT_OF_MEMORY            0x01CU /* Memory allocation failed     */
++#define TM_ERR_BAD_VIRT_ADDRESS         0x01DU /* Bad virtual address          */
++#define TM_ERR_BAD_PHYS_ADDRESS         0x01EU /* Bad physical address         */
++#define TM_ERR_TIMEOUT                  0x01FU /* Timeout error                */
++#define TM_ERR_OVERFLOW                 0x020U /* Data overflow/overrun error  */
++#define TM_ERR_FULL                     0x021U /* Queue (etc.) is full         */
++#define TM_ERR_EMPTY                    0x022U /* Queue (etc.) is empty        */
++#define TM_ERR_NOT_STARTED              0x023U /* Streaming function failed    */
++#define TM_ERR_ALREADY_STARTED          0x024U /* Start function failed        */
++#define TM_ERR_NOT_STOPPED              0x025U /* Non-streaming function failed*/
++#define TM_ERR_ALREADY_STOPPED          0x026U /* Stop function failed         */
++#define TM_ERR_ALREADY_SETUP            0x027U /* Setup function failed        */
++#define TM_ERR_NULL_PARAMETER           0x028U /* Null input parameter         */
++#define TM_ERR_NULL_DATAINFUNC          0x029U /* Null data input function     */
++#define TM_ERR_NULL_DATAOUTFUNC         0x02AU /* Null data output function    */
++#define TM_ERR_NULL_CONTROLFUNC         0x02BU /* Null control function        */
++#define TM_ERR_NULL_COMPLETIONFUNC      0x02CU /* Null completion function     */
++#define TM_ERR_NULL_PROGRESSFUNC        0x02DU /* Null progress function       */
++#define TM_ERR_NULL_ERRORFUNC           0x02EU /* Null error handler function  */
++#define TM_ERR_NULL_MEMALLOCFUNC        0x02FU /* Null memory alloc function   */
++#define TM_ERR_NULL_MEMFREEFUNC         0x030U /* Null memory free  function   */
++#define TM_ERR_NULL_CONFIGFUNC          0x031U /* Null configuration function  */
++#define TM_ERR_NULL_PARENT              0x032U /* Null parent data             */
++#define TM_ERR_NULL_IODESC              0x033U /* Null in/out descriptor       */
++#define TM_ERR_NULL_CTRLDESC            0x034U /* Null control descriptor      */
++#define TM_ERR_UNSUPPORTED_DATACLASS    0x035U /* Unsupported data class       */
++#define TM_ERR_UNSUPPORTED_DATATYPE     0x036U /* Unsupported data type        */
++#define TM_ERR_UNSUPPORTED_DATASUBTYPE  0x037U /* Unsupported data subtype     */
++#define TM_ERR_FORMAT                   0x038U /* Invalid/unsupported format   */
++#define TM_ERR_INPUT_DESC_FLAGS         0x039U /* Bad input  descriptor flags  */
++#define TM_ERR_OUTPUT_DESC_FLAGS        0x03AU /* Bad output descriptor flags  */
++#define TM_ERR_CAP_REQUIRED             0x03BU /* Capabilities required ???    */
++#define TM_ERR_BAD_TMALFUNC_TABLE       0x03CU /* Bad TMAL function table      */
++#define TM_ERR_INVALID_CHANNEL_ID       0x03DU /* Invalid channel identifier   */
++#define TM_ERR_INVALID_COMMAND          0x03EU /* Invalid command/request      */
++#define TM_ERR_STREAM_MODE_CONFUSION    0x03FU /* Stream mode config conflict  */
++#define TM_ERR_UNDERRUN                 0x040U /* Data underflow/underrun      */
++#define TM_ERR_EMPTY_PACKET_RECVD       0x041U /* Empty data packet received   */
++#define TM_ERR_OTHER_DATAINOUT_ERR      0x042U /* Other data input/output err  */
++#define TM_ERR_STOP_REQUESTED           0x043U /* Stop in progress             */
++#define TM_ERR_ASSERTION                0x049U /* Assertion failure            */
++#define TM_ERR_HIGHWAY_BANDWIDTH        0x04AU /* Highway bandwidth bus error  */
++#define TM_ERR_HW_RESET_FAILED          0x04BU /* Hardware reset failed        */
++#define TM_ERR_BAD_FLAGS                0x04DU /* Bad flags                    */
++#define TM_ERR_BAD_PRIORITY             0x04EU /* Bad priority                 */
++#define TM_ERR_BAD_REFERENCE_COUNT      0x04FU /* Bad reference count          */
++#define TM_ERR_BAD_SETUP                0x050U /* Bad setup                    */
++#define TM_ERR_BAD_STACK_SIZE           0x051U /* Bad stack size               */
++#define TM_ERR_BAD_TEE                  0x052U /* Bad tee                      */
++#define TM_ERR_IN_PLACE                 0x053U /* In place                     */
++#define TM_ERR_NOT_CACHE_ALIGNED        0x054U /* Not cache aligned            */
++#define TM_ERR_NO_ROOT_TEE              0x055U /* No root tee                  */
++#define TM_ERR_NO_TEE_ALLOWED           0x056U /* No tee allowed               */
++#define TM_ERR_NO_TEE_EMPTY_PACKET      0x057U /* No tee empty packet          */
++#define TM_ERR_NULL_PACKET              0x059U /* Null packet                  */
++#define TM_ERR_FORMAT_FREED             0x05AU /* Format freed                 */
++#define TM_ERR_FORMAT_INTERNAL          0x05BU /* Format internal              */
++#define TM_ERR_BAD_FORMAT               0x05CU /* Bad format                   */
++#define TM_ERR_FORMAT_NEGOTIATE_DATACLASS 0x05DU /* Format negotiate class     */
++#define TM_ERR_FORMAT_NEGOTIATE_DATATYPE 0x05EU /* Format negotiate type       */
++#define TM_ERR_FORMAT_NEGOTIATE_DATASUBTYPE 0x05FU /* Format negotiate subtype */
++#define TM_ERR_FORMAT_NEGOTIATE_DESCRIPTION 0x060U /* Format negotiate desc    */
++#define TM_ERR_NULL_FORMAT              0x061U /* Null format                  */
++#define TM_ERR_FORMAT_REFERENCE_COUNT   0x062U /* Format reference count       */
++#define TM_ERR_FORMAT_NOT_UNIQUE        0x063U /* Format not unique            */
++#define TM_NEW_FORMAT                   0x064U /* New format (not an error)    */
++#define TM_ERR_FORMAT_NEGOTIATE_EXTENSION 0x065U /* Format negotiate extension */
++#define TM_ERR_INVALID_STATE            0x066U /* Invalid state for function   */
++#define TM_ERR_NULL_CONNECTION          0x067U /* No connection to this pin    */
++#define TM_ERR_OPERATION_NOT_PERMITTED  0x068U /* corresponds to posix EPERM   */
++#define TM_ERR_NOT_CLOCKED              0x069U /* Power down - clocked off     */
++
++
++#define PH_ERR_COMPATIBILITY            0x001U /* SW Interface compatibility   */
++#define PH_ERR_MAJOR_VERSION            0x002U /* SW Major Version error       */
++#define PH_ERR_COMP_VERSION             0x003U /* SW component version error   */
++#define PH_ERR_BAD_MODULE_ID            0x004U /* SW - HW module ID error      */
++#define PH_ERR_BAD_UNIT_NUMBER          0x005U /* Invalid device unit number   */
++#define PH_ERR_BAD_INSTANCE             0x006U /* Bad input instance value     */
++#define PH_ERR_BAD_HANDLE               0x007U /* Bad input handle             */
++#define PH_ERR_BAD_INDEX                0x008U /* Bad input index              */
++#define PH_ERR_BAD_PARAMETER            0x009U /* Invalid input parameter      */
++#define PH_ERR_NO_INSTANCES             0x00AU /* No instances available       */
++#define PH_ERR_NO_COMPONENT             0x00BU /* Component is not present     */
++#define PH_ERR_NO_RESOURCES             0x00CU /* Resource is not available    */
++#define PH_ERR_INSTANCE_IN_USE          0x00DU /* Instance is already in use   */
++#define PH_ERR_RESOURCE_OWNED           0x00EU /* Resource is already in use   */
++#define PH_ERR_RESOURCE_NOT_OWNED       0x00FU /* Caller does not own resource */
++#define PH_ERR_INCONSISTENT_PARAMS      0x010U /* Inconsistent input params    */
++#define PH_ERR_NOT_INITIALIZED          0x011U /* Component is not initialized */
++#define PH_ERR_NOT_ENABLED              0x012U /* Component is not enabled     */
++#define PH_ERR_NOT_SUPPORTED            0x013U /* Function is not supported    */
++#define PH_ERR_INIT_FAILED              0x014U /* Initialization failed        */
++#define PH_ERR_BUSY                     0x015U /* Component is busy            */
++#define PH_ERR_NOT_BUSY                 0x016U /* Component is not busy        */
++#define PH_ERR_READ                     0x017U /* Read error                   */
++#define PH_ERR_WRITE                    0x018U /* Write error                  */
++#define PH_ERR_ERASE                    0x019U /* Erase error                  */
++#define PH_ERR_LOCK                     0x01AU /* Lock error                   */
++#define PH_ERR_UNLOCK                   0x01BU /* Unlock error                 */
++#define PH_ERR_OUT_OF_MEMORY            0x01CU /* Memory allocation failed     */
++#define PH_ERR_BAD_VIRT_ADDRESS         0x01DU /* Bad virtual address          */
++#define PH_ERR_BAD_PHYS_ADDRESS         0x01EU /* Bad physical address         */
++#define PH_ERR_TIMEOUT                  0x01FU /* Timeout error                */
++#define PH_ERR_OVERFLOW                 0x020U /* Data overflow/overrun error  */
++#define PH_ERR_FULL                     0x021U /* Queue (etc.) is full         */
++#define PH_ERR_EMPTY                    0x022U /* Queue (etc.) is empty        */
++#define PH_ERR_NOT_STARTED              0x023U /* Streaming function failed    */
++#define PH_ERR_ALREADY_STARTED          0x024U /* Start function failed        */
++#define PH_ERR_NOT_STOPPED              0x025U /* Non-streaming function failed*/
++#define PH_ERR_ALREADY_STOPPED          0x026U /* Stop function failed         */
++#define PH_ERR_ALREADY_SETUP            0x027U /* Setup function failed        */
++#define PH_ERR_NULL_PARAMETER           0x028U /* Null input parameter         */
++#define PH_ERR_NULL_DATAINFUNC          0x029U /* Null data input function     */
++#define PH_ERR_NULL_DATAOUTFUNC         0x02AU /* Null data output function    */
++#define PH_ERR_NULL_CONTROLFUNC         0x02BU /* Null control function        */
++#define PH_ERR_NULL_COMPLETIONFUNC      0x02CU /* Null completion function     */
++#define PH_ERR_NULL_PROGRESSFUNC        0x02DU /* Null progress function       */
++#define PH_ERR_NULL_ERRORFUNC           0x02EU /* Null error handler function  */
++#define PH_ERR_NULL_MEMALLOCFUNC        0x02FU /* Null memory alloc function   */
++#define PH_ERR_NULL_MEMFREEFUNC         0x030U /* Null memory free  function   */
++#define PH_ERR_NULL_CONFIGFUNC          0x031U /* Null configuration function  */
++#define PH_ERR_NULL_PARENT              0x032U /* Null parent data             */
++#define PH_ERR_NULL_IODESC              0x033U /* Null in/out descriptor       */
++#define PH_ERR_NULL_CTRLDESC            0x034U /* Null control descriptor      */
++#define PH_ERR_UNSUPPORTED_DATACLASS    0x035U /* Unsupported data class       */
++#define PH_ERR_UNSUPPORTED_DATATYPE     0x036U /* Unsupported data type        */
++#define PH_ERR_UNSUPPORTED_DATASUBTYPE  0x037U /* Unsupported data subtype     */
++#define PH_ERR_FORMAT                   0x038U /* Invalid/unsupported format   */
++#define PH_ERR_INPUT_DESC_FLAGS         0x039U /* Bad input  descriptor flags  */
++#define PH_ERR_OUTPUT_DESC_FLAGS        0x03AU /* Bad output descriptor flags  */
++#define PH_ERR_CAP_REQUIRED             0x03BU /* Capabilities required ???    */
++#define PH_ERR_BAD_TMALFUNC_TABLE       0x03CU /* Bad TMAL function table      */
++#define PH_ERR_INVALID_CHANNEL_ID       0x03DU /* Invalid channel identifier   */
++#define PH_ERR_INVALID_COMMAND          0x03EU /* Invalid command/request      */
++#define PH_ERR_STREAM_MODE_CONFUSION    0x03FU /* Stream mode config conflict  */
++#define PH_ERR_UNDERRUN                 0x040U /* Data underflow/underrun      */
++#define PH_ERR_EMPTY_PACKET_RECVD       0x041U /* Empty data packet received   */
++#define PH_ERR_OTHER_DATAINOUT_ERR      0x042U /* Other data input/output err  */
++#define PH_ERR_STOP_REQUESTED           0x043U /* Stop in progress             */
++#define PH_ERR_ASSERTION                0x049U /* Assertion failure            */
++#define PH_ERR_HIGHWAY_BANDWIDTH        0x04AU /* Highway bandwidth bus error  */
++#define PH_ERR_HW_RESET_FAILED          0x04BU /* Hardware reset failed        */
++#define PH_ERR_BAD_FLAGS                0x04DU /* Bad flags                    */
++#define PH_ERR_BAD_PRIORITY             0x04EU /* Bad priority                 */
++#define PH_ERR_BAD_REFERENCE_COUNT      0x04FU /* Bad reference count          */
++#define PH_ERR_BAD_SETUP                0x050U /* Bad setup                    */
++#define PH_ERR_BAD_STACK_SIZE           0x051U /* Bad stack size               */
++#define PH_ERR_BAD_TEE                  0x052U /* Bad tee                      */
++#define PH_ERR_IN_PLACE                 0x053U /* In place                     */
++#define PH_ERR_NOT_CACHE_ALIGNED        0x054U /* Not cache aligned            */
++#define PH_ERR_NO_ROOT_TEE              0x055U /* No root tee                  */
++#define PH_ERR_NO_TEE_ALLOWED           0x056U /* No tee allowed               */
++#define PH_ERR_NO_TEE_EMPTY_PACKET      0x057U /* No tee empty packet          */
++#define PH_ERR_NULL_PACKET              0x059U /* Null packet                  */
++#define PH_ERR_FORMAT_FREED             0x05AU /* Format freed                 */
++#define PH_ERR_FORMAT_INTERNAL          0x05BU /* Format internal              */
++#define PH_ERR_BAD_FORMAT               0x05CU /* Bad format                   */
++#define PH_ERR_FORMAT_NEGOTIATE_DATACLASS 0x05DU /* Format negotiate class     */
++#define PH_ERR_FORMAT_NEGOTIATE_DATATYPE 0x05EU /* Format negotiate type       */
++#define PH_ERR_FORMAT_NEGOTIATE_DATASUBTYPE 0x05FU /* Format negotiate subtype */
++#define PH_ERR_FORMAT_NEGOTIATE_DESCRIPTION 0x060U /* Format negotiate desc    */
++#define PH_ERR_NULL_FORMAT              0x061U /* Null format                  */
++#define PH_ERR_FORMAT_REFERENCE_COUNT   0x062U /* Format reference count       */
++#define PH_ERR_FORMAT_NOT_UNIQUE        0x063U /* Format not unique            */
++#define PH_NEW_FORMAT                   0x064U /* New format (not an error)    */
++#define PH_ERR_FORMAT_NEGOTIATE_EXTENSION 0x065U /* Format negotiate extension */
++#define PH_ERR_INVALID_STATE            0x066U /* Invalid state for function   */
++#define PH_ERR_NULL_CONNECTION          0x067U /* No connection to this pin    */
++#define PH_ERR_OPERATION_NOT_PERMITTED  0x068U /* corresponds to posix EPERM   */
++#define PH_ERR_NOT_CLOCKED              0x069U /* Power down - clocked off     */
++
++/* Add new standard error/progress status codes here                          */
++
++#define TM_ERR_COMP_UNIQUE_START    0x800U /* 0x800-0xBFF: Component unique    */
++#define PH_ERR_COMP_UNIQUE_START    0x800U /* 0x800-0xBFF: Component unique    */
++#define TM_ERR_CUSTOMER_START       0xC00U /* 0xC00-0xDFF: Customer defined    */
++#define PH_ERR_CUSTOMER_START       0xC00U /* 0xC00-0xDFF: Customer defined    */
++
++/* Legacy and withdrawn error codes */
++#define TM_ERR_FORMAT_NEGOTIATE_SUBCLASS TM_ERR_FORMAT_NEGOTIATE_DATACLASS
++#define TM_ERR_NEW_FORMAT                TM_NEW_FORMAT
++#define TM_ERR_PAUSE_PIN_REQUESTED       TM_ERR_STOP_REQUESTED
++#define TM_ERR_PIN_ALREADY_STARTED       TM_ERR_ALREADY_STARTED
++#define TM_ERR_PIN_ALREADY_STOPPED       TM_ERR_ALREADY_STOPPED
++#define TM_ERR_PIN_NOT_STARTED           TM_ERR_NOT_STARTED
++#define TM_ERR_PIN_NOT_STOPPED           TM_ERR_NOT_STOPPED
++#define TM_ERR_PIN_PAUSED                TM_ERR_NOT_STARTED
++
++/* -------------------------------------------------------------------------- */
++/* Standard assert error code start offset                                    */
++/* NOTE: These ranges are FOR LEGACY CODE ONLY and must not be used in new    */
++/*  components                                                                */
++/* -------------------------------------------------------------------------- */
++#define TM_ERR_ASSERT_START         0xE00U /* 0xE00-0xEFF: Assert failures     */
++#define TM_ERR_ASSERT_LAST          0xEFFU /* Last assert error range value    */
++#define CID_IS_ASSERT_ERROR(compId) ((CID_GET_ERROR(compId) >= TM_ERR_ASSERT_START) && (CID_GET_ERROR(compId) <= TM_ERR_ASSERT_LAST))
++
++/* -------------------------------------------------------------------------- */
++/* Standard fatal error code start offset                                     */
++/* NOTE: These ranges are FOR LEGACY CODE ONLY and must not be used in new    */
++/*  components                                                                */
++/* -------------------------------------------------------------------------- */
++
++#define TM_ERR_FATAL_START          0xF00U /* 0xF00-0xFFF: Fatal failures      */
++#define TM_ERR_FATAL_LAST           0xFFFU /* Last fatal error range value     */
++#define CID_IS_FATAL_ERROR(compId)  ((CID_GET_ERROR(compId) >= TM_ERR_FATAL_START) && (CID_GET_ERROR(compId) <= TM_ERR_FATAL_LAST))
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* TMNXCOMPID_H ----------------- */
+diff --git a/drivers/video/nxp/inc/tmNxTypes.h b/drivers/video/nxp/inc/tmNxTypes.h
+new file mode 100755
+index 0000000..af67f61
+--- /dev/null
++++ b/drivers/video/nxp/inc/tmNxTypes.h
+@@ -0,0 +1,366 @@
++/*==========================================================================*/
++/*     (Copyright (C) 2003 Koninklijke Philips Electronics N.V.             */
++/*     All rights reserved.                                                 */
++/*     This source code and any compilation or derivative thereof is the    */
++/*     proprietary information of Koninklijke Philips Electronics N.V.      */
++/*     and is confidential in nature.                                       */
++/*     Under no circumstances is this software to be exposed to or placed   */
++/*     under an Open Source License of any type without the expressed       */
++/*     written permission of Koninklijke Philips Electronics N.V.           */
++/*==========================================================================*/
++/*
++ * Copyright (C) 2000,2001
++ *               Koninklijke Philips Electronics N.V.
++ *               All Rights Reserved.
++ *
++ * Copyright (C) 2000,2001 TriMedia Technologies, Inc.
++ *               All Rights Reserved.
++ *
++ *############################################################
++ *
++ * Module name  : tmNxTypes.h  %version: 7 %
++ *
++ * Last Update  : %date_modified: Tue Jul  8 18:08:00 2003 %
++ *
++ * Description: TriMedia/MIPS global type definitions.
++ *
++ * Document Ref: DVP Software Coding Guidelines Specification
++ * DVP/MoReUse Naming Conventions specification
++ * DVP Software Versioning Specification
++ * DVP Device Library Architecture Specification
++ * DVP Board Support Library Architecture Specification
++ * DVP Hardware API Architecture Specification
++ *
++ *
++ *############################################################
++ */
++
++#ifndef TMNXTYPES_H
++#define TMNXTYPES_H
++
++//-----------------------------------------------------------------------------
++// Standard include files:
++//-----------------------------------------------------------------------------
++//
++
++//-----------------------------------------------------------------------------
++// Project include files:
++//-----------------------------------------------------------------------------
++//
++#include "tmFlags.h"                    // DVP common build control flags
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++//-----------------------------------------------------------------------------
++// Types and defines:
++//-----------------------------------------------------------------------------
++//
++
++/*Under the TCS, <tmlib/tmtypes.h> may have been included by our client. In
++    order to avoid errors, we take account of this possibility, but in order to
++    support environments where the TCS is not available, we do not include the
++    file by name.*/
++
++#ifndef _TMtypes_h
++#define _TMtypes_h
++
++#define False           0
++#define True            1
++
++#ifdef __cplusplus
++#define Null            0
++#else
++#define Null            ((Void *) 0)
++#endif
++
++//
++//      Standard Types
++//
++typedef signed   char   Int8;   //  8 bit   signed integer
++typedef signed   short  Int16;  // 16 bit   signed integer
++typedef signed   long   Int32;  // 32 bit   signed integer
++typedef unsigned char   UInt8;  //  8 bit unsigned integer
++typedef unsigned short  UInt16; // 16 bit unsigned integer
++typedef unsigned long   UInt32; // 32 bit unsigned integer
++typedef float           Float;  // 32 bit floating point
++typedef unsigned int    Bool;   // Boolean (True/False)
++typedef char            Char;   // character, character array ptr
++typedef int             Int;    // machine-natural integer
++typedef unsigned int    UInt;   // machine-natural unsigned integer
++typedef char           *String; // Null terminated 8 bit char str
++
++//-----------------------------------------------------------------------------
++// Legacy TM Types/Structures (Not necessarily DVP Coding Guideline compliant)
++// NOTE: For DVP Coding Gudeline compliant code, do not use these types.
++//
++typedef char          *Address;        // Ready for address-arithmetic
++typedef char const    *ConstAddress;
++typedef unsigned char  Byte;           // Raw byte
++typedef float          Float32;        // Single-precision float
++typedef double         Float64;        // Double-precision float
++typedef void          *Pointer;        // Pointer to anonymous object
++typedef void const    *ConstPointer;
++typedef char const    *ConstString;
++
++typedef Int             Endian;
++#define BigEndian       0
++#define LittleEndian    1
++
++typedef struct tmVersion
++{
++    UInt8   majorVersion;
++    UInt8   minorVersion;
++    UInt16  buildVersion;
++}   tmVersion_t, *ptmVersion_t;
++#endif /*ndef _TMtypes_h*/
++
++/*Define DVP types that are not TCS types.*/
++/*
++** ===== Updated from SDE2/2.3_Beta/sde_template/inc/tmNxTypes.h =====
++**
++** NOTE: IBits32/UBits32 types are defined for use with 32 bit bitfields.  
++**       This is done because ANSI/ISO compliant compilers require bitfields
++**       to be of type "int" else a large number of compiler warnings will 
++**       result.  To avoid the risks associated with redefining Int32/UInt32
++**       to type "int" instead of type "long" (which are the same size on 32
++**       bit CPUs) separate 32bit signed/unsigned bitfield types are defined.
++*/
++typedef signed   int    IBits32;    /* 32 bit   signed integer bitfields */
++typedef unsigned int    UBits32;    /* 32 bit unsigned integer bitfields */
++typedef IBits32 *pIBits32;          /* 32 bit   signed integer bitfield ptr */
++typedef UBits32 *pUBits32;          /* 32 bit unsigned integer bitfield ptr */
++
++typedef Int8   *pInt8;            //  8 bit   signed integer
++typedef Int16  *pInt16;           // 16 bit   signed integer
++typedef Int32  *pInt32;           // 32 bit   signed integer
++typedef UInt8  *pUInt8;           //  8 bit unsigned integer
++typedef UInt16 *pUInt16;          // 16 bit unsigned integer
++typedef UInt32 *pUInt32;          // 32 bit unsigned integer
++typedef void    Void, *pVoid;     // Void (typeless)
++typedef Float  *pFloat;           // 32 bit floating point
++typedef double  Double, *pDouble; // 32/64 bit floating point
++typedef Bool   *pBool;            // Boolean (True/False)
++typedef Char   *pChar;            // character, character array ptr
++typedef Int    *pInt;             // machine-natural integer
++typedef UInt   *pUInt;            // machine-natural unsigned integer
++typedef String *pString;          // Null terminated 8 bit char str,
++
++/*Assume that 64-bit integers are supported natively by C99 compilers and Visual
++    C version 6.00 and higher. More discrimination in this area may be added
++    here as necessary.*/
++#if defined __STDC_VERSION__ && __STDC_VERSION__ > 199409L
++/*This can be enabled only when all explicit references to the hi and lo
++    structure members are eliminated from client code.*/
++#define TMFL_NATIVE_INT64 1
++typedef signed   long long int Int64,  *pInt64;  // 64-bit integer
++typedef unsigned long long int UInt64, *pUInt64; // 64-bit bitmask
++// #elif defined _MSC_VER && _MSC_VER >= 1200
++// /*This can be enabled only when all explicit references to the hi and lo
++//     structure members are eliminated from client code.*/
++// #define TMFL_NATIVE_INT64 1
++// typedef signed   __int64 Int64,  *pInt64;  // 64-bit integer
++// typedef unsigned __int64 UInt64, *pUInt64; // 64-bit bitmask
++#else /*!(defined __STDC_VERSION__ && __STDC_VERSION__ > 199409L)*/
++#define TMFL_NATIVE_INT64 0
++typedef
++    struct
++    {
++        /*Get the correct endianness (this has no impact on any other part of
++            the system, but may make memory dumps easier to understand).*/
++#if TMFL_ENDIAN == TMFL_ENDIAN_BIG
++        Int32 hi; UInt32 lo;
++#else
++        UInt32 lo; Int32 hi;
++#endif
++    }
++    Int64, *pInt64; // 64-bit integer
++typedef
++    struct
++    {
++#if TMFL_ENDIAN == TMFL_ENDIAN_BIG
++        UInt32 hi; UInt32 lo;
++#else
++        UInt32 lo; UInt32 hi;
++#endif
++    }
++    UInt64, *pUInt64; // 64-bit bitmask
++#endif /*defined __STDC_VERSION__ && __STDC_VERSION__ > 199409L*/
++
++// Maximum length of device name in all BSP and capability structures
++#define HAL_DEVICE_NAME_LENGTH 16
++
++typedef UInt32 tmErrorCode_t;
++typedef UInt32 tmProgressCode_t;
++
++/* timestamp definition */
++typedef UInt64 tmTimeStamp_t, *ptmTimeStamp_t;
++
++//for backwards compatibility with the older tmTimeStamp_t definition
++#define ticks   lo
++#define hiTicks hi
++
++typedef union tmColor3                 // 3 byte color structure
++{
++    UBits32 u32;
++#if (TMFL_ENDIAN == TMFL_ENDIAN_BIG)
++    struct {
++        UBits32       : 8;
++        UBits32 red   : 8;
++        UBits32 green : 8;
++        UBits32 blue  : 8;
++    } rgb;
++    struct {
++        UBits32   : 8;
++        UBits32 y : 8;
++        UBits32 u : 8;
++        UBits32 v : 8;
++    } yuv;
++    struct {
++        UBits32   : 8;
++        UBits32 u : 8;
++        UBits32 m : 8;
++        UBits32 l : 8;
++    } uml;
++#else
++    struct {
++        UBits32 blue  : 8;
++        UBits32 green : 8;
++        UBits32 red   : 8;
++        UBits32       : 8;
++    } rgb;
++    struct {
++        UBits32 v : 8;
++        UBits32 u : 8;
++        UBits32 y : 8;
++        UBits32   : 8;
++    } yuv;
++    struct {
++        UBits32 l : 8;
++        UBits32 m : 8;
++        UBits32 u : 8;
++        UBits32   : 8;
++    } uml;
++#endif
++}   tmColor3_t, *ptmColor3_t;
++
++typedef union tmColor4                 // 4 byte color structure
++{
++    UBits32 u32;
++#if (TMFL_ENDIAN == TMFL_ENDIAN_BIG)
++    struct {
++        UBits32 alpha    : 8;
++        UBits32 red      : 8;
++        UBits32 green    : 8;
++        UBits32 blue     : 8;
++    } argb;
++    struct {
++        UBits32 alpha    : 8;
++        UBits32 y        : 8;
++        UBits32 u        : 8;
++        UBits32 v        : 8;
++    } ayuv;
++    struct {
++        UBits32 alpha    : 8;
++        UBits32 u        : 8;
++        UBits32 m        : 8;
++        UBits32 l        : 8;
++    } auml;
++#else
++    struct {
++        UBits32 blue     : 8;
++        UBits32 green    : 8;
++        UBits32 red      : 8;
++        UBits32 alpha    : 8;
++    } argb;
++    struct {
++        UBits32 v        : 8;
++        UBits32 u        : 8;
++        UBits32 y        : 8;
++        UBits32 alpha    : 8;
++    } ayuv;
++    struct {
++        UBits32 l        : 8;
++        UBits32 m        : 8;
++        UBits32 u        : 8;
++        UBits32 alpha    : 8;
++    } auml;
++#endif
++}   tmColor4_t, *ptmColor4_t;
++
++//-----------------------------------------------------------------------------
++// Hardware device power states
++//
++typedef enum tmPowerState
++{
++    tmPowerOn,                          // Device powered on      (D0 state)
++    tmPowerStandby,                     // Device power standby   (D1 state)
++    tmPowerSuspend,                     // Device power suspended (D2 state)
++    tmPowerOff                          // Device powered off     (D3 state)
++
++}   tmPowerState_t, *ptmPowerState_t;
++
++//-----------------------------------------------------------------------------
++// Software Version Structure
++//
++typedef struct tmSWVersion
++{
++    UInt32      compatibilityNr;        // Interface compatibility number
++    UInt32      majorVersionNr;         // Interface major version number
++    UInt32      minorVersionNr;         // Interface minor version number
++
++}   tmSWVersion_t, *ptmSWVersion_t;
++
++/*Under the TCS, <tm1/tmBoardDef.h> may have been included by our client. In
++    order to avoid errors, we take account of this possibility, but in order to
++    support environments where the TCS is not available, we do not include the
++    file by name.*/
++#ifndef _TMBOARDDEF_H_
++#define _TMBOARDDEF_H_
++
++//-----------------------------------------------------------------------------
++// HW Unit Selection
++//
++typedef Int tmUnitSelect_t, *ptmUnitSelect_t;
++
++#define tmUnitNone (-1)
++#define tmUnit0    0
++#define tmUnit1    1
++#define tmUnit2    2
++#define tmUnit3    3
++#define tmUnit4    4
++
++/*+compatibility*/
++#define unitSelect_t       tmUnitSelect_t
++#define unit0              tmUnit0
++#define unit1              tmUnit1
++#define unit2              tmUnit2
++#define unit3              tmUnit3
++#define unit4              tmUnit4
++#define DEVICE_NAME_LENGTH HAL_DEVICE_NAME_LENGTH
++/*-compatibility*/
++
++#endif /*ndef _TMBOARDDEF_H_ */
++
++//-----------------------------------------------------------------------------
++// Instance handle
++//
++typedef Int tmInstance_t, *ptmInstance_t;
++
++// Callback function declaration
++typedef Void (*ptmCallback_t) (UInt32 events, Void *pData, UInt32 userData);
++#define tmCallback_t ptmCallback_t /*compatibility*/
++
++// Kernel debugging function declaration
++#ifdef TMFL_CFG_INTELCE4100
++#define KERN_INFO void
++#define printk(fmt, args...) printf(fmt, ## args)
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif //ndef TMNXTYPES_H
+diff --git a/drivers/video/nxp/linux_hdmi_release_note.txt b/drivers/video/nxp/linux_hdmi_release_note.txt
+new file mode 100755
+index 0000000..d06be0d
+--- /dev/null
++++ b/drivers/video/nxp/linux_hdmi_release_note.txt
+@@ -0,0 +1,417 @@
++Release note:
++
++-------------------------------
++   HDMI Tx modules for TDA998x
++             by
++    NXP Semiconductors BV
++-------------------------------
++
++---------------------------------
++		/!\ WARNING /!\
++If you want to use the HDMI driver from the user space (easier for non-Linux-expert, but needs to have an I2C driver available 
++from the user space), PLEASE DON'T USE THE LINUX DELIVERY. USE THE BASIC DELIVERY INSTEAD, and refer to the install_DL.txt note.
++An exemple of application is available in HdmiTx\sde2\comps\tmdlHdmiTx\tst\tmdlHdmiTx_ExampleApplication\src folder.
++---------------------------------
++
++The release note gives all necessary detail for installation in Linux
++kernel and application tunning. Installation is Linux typical and does
++not require any HDMI background. A default video and audio setting is
++defined in hdmi_tx_init function. It can be changed at will.
++There is no porting to do, it is already provided in module. And the
++classical HDMI DevLib is embedded in it. But the UserManual is still
++usefull for customers who like to optimise the module according to
++their needs. If so, feedback is welcome. ;)
++Customers who like to drive the module from userland can do it using
++IOCTL. IOCTL maps the classical HDMI API. Using the WAIT_FRAME IOCTL,
++userland can catch HDMI events like Hot Plug Detect, RxSens or EDID.
++
++So the two main functions the customer needs to take care are :
++- hdmi_tx_init : to setup the default HDMI settings. These settings can be
++  overwritten using the TDA_SET_INPUT_OUTPUT_CMD IOCTL
++- eventCallbackTx : to fetch HDMI events from userland OR add more
++  automatic behavior in the module itself. For example basic EDID check
++  after reading EDID from the sink.
++
++For customers who like to understand how the HDMI stack works, please
++read the TRANSMITTER_TDA998X_SW_UM_Devlib.pdf user manuel. You learn that:
++1- this module is a 3 levels stack
++2- HDMI core driver API in defined in comps/tmdlHdmiTx/inc
++
++HDCP is delivered in a proprietary module to avoid GPL license constraints.
++For customer that uses HDCP, don't forget to get additional stuff from NXP
++
++For OMAP architecture, a DSS plugin is provided. So to activate
++HDMI (switch DSS to HDMI output) just prompt on target:
++echo "3" > /sys/power/vdd2_lock
++echo "1" > /sys/devices/platform/omapdss/display2/enabled
++And desactivate : 
++echo "0" > /sys/devices/platform/omapdss/display2/enabled
++
++-------------------------------
++ ^           ^
++/!\ CAUTION /!\
++---         ---
++
++This release note and it's FAQ below covers every known questions from customers
++up to now. Thank you for reading it carefully. If you modify the driver, we would
++appreciate to gain from your update. So any feedback is welcome.
++
++-------------------------------
++
++- Contains : 
++  . HdmiTx Linux module
++  . HdmiCec linux module
++  . HDCP linux module (on request only)
++  . test_hdmi/demo_tda test application
++  . TRANSMITTER_TDA998X_SW_UM_Devlib.pdf for HDMI TX API
++  . HDMI_CEC_User_Manual.pdf for HDMI CEC API
++  . this release note
++
++- Features :
++  . HDMI transmiter
++  . Hot Plug Detection
++  . HDCP (on request only)
++  . Customer Electronics Control (v1.4)
++  . 3D video format, including frame packing
++
++- Target :
++  . OMAP3430-ZOOMII (http://omappedia.org/wiki/Android_Getting_Started)
++
++- OS :
++  . Linux Kernel 2.6.29, Android RLS25.12
++
++- Directory :
++  . driver/video/hdmi
++  . driver/video/hdcp (only if hdcp is delivered)
++
++- Compilation tool :
++  . arm-2007q3-51-arm-none-linux-gnueabi-i686-pc-linux-gnu
++
++-------------------------------
++
++- Release :
++ * V1.3.0: 2011, 4th May by Vincent Vrignaud
++  . HDMI1565 improved HDCP robustness in show_video function
++ * V1.2: 2010, 22th Oct by Andre Lepine
++  . TDA19988 support
++ * V1.1: 2010, 15th Oct by Andre Lepine
++  . TDA9983 version (only) has been produced in pure Linux style
++ * V1.03: 2010, 26th Augut by Andre Lepine
++  . USER_SET_INPUT_OUPUT
++  . use suspend mode for event catching when DSS HDMI panel is off (hdmi_disable(1))
++  . prevent IOCTL from updating power mode when used by DSS HDMI panel
++ * V1.02: 2010, 22th Jully by Andre Lepine
++  . SetHdcp with IOCTL
++ * V1.01: 2010, 15th Jully by Andre Lepine
++  . copy_from_user EDID IOCTL
++  . hdcp_onoff rework
++  . SimplayHD feature
++  . kernel i2c_client
++  . start implementing sysfs_attrs : first is resolution
++ * V1.0: 2010, 1st Jully by Andre Lepine
++  . ATC compliancy
++  . BCaps polling during 5s when CCLK is not devided by 2
++  . It HPD+RxSens rebound (several changes before SW polling)
++  . EDID used for video mode switch (HDMI, DVI)
++  . blue screen before the HDCP authentification is passed
++  . TDA reset when removing Linux module
++  . hdcp_fail_status not used in TDA9981
++ * V0.964: 2010, 25th may by Andre Lepine
++  . Check incoming REQUEST_ACTIVE_SOURCE is a broadcast
++ * V0.963: 2010, 21th may by Andre Lepine
++  . External HDCP module validation 
++ * V0.963: 2010, 18th may by Andre Lepine
++  . External HDCP module validation 
++ * V0.962: 2010, 11th may by Andre Lepine
++  . Clean up
++ * V0.961: 2010, 4th may by Andre Lepine
++  . Put image_view_on under compilation flag because it is not suitable for
++    "only hdmi with videoplay" usecase
++  . DEVICE_VENDOR_ID boradcast after logical address retrival
++  . Allow CEC_OPCODE_VENDOR_COMMAND and CEC_OPCODE_DEVICE_VENDOR_ID (not send FEATURE ABORTED)
++ * V0.96: 2010, 16th april by Andre Lepine
++  . Accept HDCP support using the proprietary module nwolc.ko
++ * V0.95: 2010, 23th march by Andre Lepine
++  . Add TDA9981 driver
++ * V0.94: 2010, 19th march by Andre Lepine
++  . Merge TDA19989, TDA9984 and TDA9983 drivers
++ * V0.92: 2010, 11th march by Andre Lepine
++  . Clean-up
++  . DSS pixclock inversion
++ * V0.91: 2010, 18th february by Andre Lepine
++  . porting for TDA9983
++ * V0.9: 2010, 2nd february by Andre Lepine
++  . Change directory structure
++  . Update NXP DevLib
++  . CEC & HDP event handeling fix
++ * V0.8: 2010, 18 january by Andre Lepine
++  . Pure IRQ (remove IRQ flag for polling with timer)
++  . Merge with last HdmiTx and HdmiCec version
++  . Cec initialization and power state
++  . Check argument of IOCTL and use -EFAULT when inconsistant
++ * V0.7: 2010, 11 january by Andre Lepine
++  . Automatic CEC answering for following opcodes :
++     > GIVE_PHYSICAL_ADDRESS
++     > GET_CEC_VERSION
++     > GIVE_OSD_NAME
++     > GIVE_DEVICE_VENDOR_ID
++     > REQUEST_ACTIVE_SOURCE
++     > GIVE_DEVICE_POWER_STATUS
++     > STANDBY
++     > SET_STREAM_PATH
++     > ROUTING_CHANGE
++     > ABORT_MESSAGE
++  . Automatic logical address negociation
++  . HdmiCec gets EDID physical address and HDMI status from HdmiTx
++
++-------------------------------
++
++- Installation :
++
++ * On host:
++  . mkdir $KERNEL_MODULES
++  . cp nxp-TDA1998X-linux-hdmi-cec-(hdcp)-L###-DL##-BSL##.tar.cvfj $KERNEL_MODULES/.
++  . cd $KERNEL_MODULES
++  . tar xvfj nxp-TDA1998X-linux-hdmi-cec-(hdcp)-L###-DL##-BSL##.tar.cvfj
++  . update LINUX_DIR in hdmi/MakeModules with your kernel directory path
++  . select your TDA target in Makefile :  for example TDA_TX := TDA19988  !!! CAUTION, don't forget this !!!
++  . select your platform in Makefile :  for example TDA_PLATFORM := ZOOMII
++  . cd hdmi
++  . make -f MakeModules clean (optional for the first time)
++  . make -f MakeModules (then you get hdmitx.ko and hdmicecc.ko modules)
++  . make -f MakeModules uptx (or any download mean that does not use adb)
++  . make -f MakeModules upcec (or any download mean that does not use adb) (19988/89 only)
++  . cd hdcp (for 19988/89 and 9984 only)
++  . update the KEY_SEED value in comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c
++  . make -f MakeModules (then you get nwolc.ko module)
++  . make -f MakeModules up (or any download mean that does not use adb)
++ * Application (optional), better use your own, this one is just a sample
++  . cd test
++  . make clean (optional for the first time)
++  . make
++  . make upload (or any download mean that does not use adb)
++ * On target:
++  . insmod hdmitx.ko verbose=1 (remove verbose to make the module silent)
++  . insmod hdmicec.ko verbose=1 device=4 (remove verbose to make the module silent)
++  . insmod nwolc.ko (only for HDCP)
++ * On TV
++  . connect TV to target
++
++- Usage :
++
++  . hdmitx module parameters used with insmod :
++    > verbose: Make the driver verbose
++    > major: The major number of the device mapper
++  . hdmicec module parameters used with insmod :
++    > verbose: Make the driver verbose
++    > major: The major number of the device mapper
++    > device: Device type can be 0:tv, 1:rec 3:tuner 4:mediaplayer, 5:audio
++    > addr: Physical address (until EDID received)
++  . modules handles automaticaly HPD, EDID and following CEC messaging :
++    device connectivity and addressing, routing, standby, OSD name,
++    vendor name features.
++  . tda_demo test application show how to take control of the two modules
++    from userland and catch CEC messages
++    BUT HDMI MODULES CAN RUN WITHOUT IT
++  . HDCP feature is only supported if nwolc module is installed, you can
++    add it or remove it dynamically using insmod nwolc.ko and rmmod nwolk.
++
++- FAQ :
++
++  . "Can I modify file tda998x.c ?"
++    YES ! It's only a kind of "application" sample of the core driver below.
++    Feel free to customize it at will !
++
++  . "Can I modify files in comps directoty ?"
++    NO ! Core driver bug shall be discussed with NXP otherwise you may break down
++    some patches and introduce regressions
++
++  . "this->driver.i2c_client not allocated" :
++    1) Declare your I2C bus usage in arch/arm/mach-omap2/board-zoom2.c as follow :
++    | static struct i2c_board_info __initdata zoom2_i2c_bus3_info[] = {
++	|        {I2C_BOARD_INFO(TX_NAME,  TDA998X_I2C_SLAVEADDRESS),},
++	|        {I2C_BOARD_INFO(CEC_NAME,  TDA99XCEC_I2C_SLAVEADDRESS),},
++    | };
++    2) Check the TDA target in Makefile :  for example TDA_TX := TDA9984
++
++  . "Video format and plan are strange..." :
++    Check tda.setio.videoout/in in hdmi_tx_init() function of tda998x.c
++
++  . "The resolution is not the one I want" :
++    Update or create your own omap_video_timings structure and change
++    the video resolution of this->tda.setio.video_out.format in hdmi_tx_init()
++
++  . "I want 720p@60Hz" :
++    1- Line 860: Uncomment> /*    this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_04_1280x720p_60Hz; */
++    2- Line 862: Comment> this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_02_720x480p_60Hz;
++    3- Line 1051: Replace> video_720x480at60Hz_panel_timings with video_1280x720at60Hz_panel_timings
++
++  . "RGB colors are swapped, for example I see RBG instead of RGB" : (for TDA9984 and TDA19989 only)
++    Modify the videoPortMapping_RGB444 video port mapping in comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c. 
++
++  . "YUV signals are swapped, for example I see UVY instead of YUV" : (for TDA9984 and TDA19989 only)
++    Modify the videoPortMapping_YUV444/YUV422 video port mapping in comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c. 
++
++  . "I2C or SPDIF audio does not work, signals are swapped" : (for TDA9984 and TDA19989 only)
++    Modify the enableAudioPortI2S/SPDIF audio port mapping in comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c. 
++
++  . "Where can I find all video format definition ?":
++    in hdmi/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Types.h
++
++  . "Where can I find all audio format definition ?":
++    in hdmi/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Types.h
++
++  . "Where can I find all HDMI types definition ?":
++    in hdmi/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Types.h
++
++  . "Where can I find all power management types definition ?":
++    in hdmi/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Types.h
++
++  . "Where can I find all HDMI Tx API definition ?":
++    in hdmi/comps/tmdlHdmiTx/inc/tmdlHdmiTx_Functions.h
++
++  . "Where can I find all HDMI CEC types definition ?":
++    in hdmi/comps/tmdlHdmiCec/inc/tmdlHdmiCec_Types.h
++
++  . "Where can I find all HDMI CEC API definition ?":
++    in hdmi/comps/tmdlHdmiCec/inc/tmdlHdmiCec_Functions.h
++
++  . "I would like to get debug message":
++    Install the module with debug messages > insmod hdmitx.ko verbose=1 
++
++  . "I would like to see the EDID of the TV":
++    Install the module with debug messages > insmod hdmitx.ko verbose=1 
++
++  . "On the TV display some pixel are flickering":
++    Check the OMAP DSS setup and update the dssdev->panel.config parameters
++
++  . "CEC send Samsung vendor ID":
++    Yes, otherwise you cannot use Samsung devices... replace is by your own
++
++  . "I don't use OMAP":
++    This module contains an OMAP Display SubSystem plugin that automatically
++    drives video output of OMAP (video input of TDA). If you don't have OMAP
++    remove the ANDROID_DSS (or add your PLATFORM flag in Makefile) and do
++    the video bus configuration at your convience. Anyhow, any other usefull 
++    plugin is welcome... So please feedback ;)
++
++  . "How to install HDMI module ?":
++    See installation chapter above.
++
++  . "HDCP is not supported":
++    Ask NXP to deliver you the proprietary HDCP module
++
++  . "HDCP module does not work":
++    Ask NXP to provide you your customer seed number...
++
++  . "How can I control the HDMI with my apps ?":
++    Use open("/dev/hdmitx") to get access to HdmiTx module.
++    Then use ioctl as described in tda998x_ioctl.h.
++
++  . "How can I control CEC with my apps ?":
++    Use open("/dev/hdmicec") to get access to HdmiCec module.
++    Then use ioctl as described in tda998x_ioctl.h.
++
++  . "How can my application get the HDMI event ?":
++    Create a dedicated incoming event thread in your apps and use ioctl WAIT_EVENT
++
++  . "Is is mandatory to create an incoming event thread in my apps ?":
++    No if you don't care.
++
++  . "Did I need to create some apps to make HDMI running ?":
++    No, you can modify hdmi_tx_init according to your needs and install the
++    modules in your init.rc. Hdmi will run automatically.
++
++  . "HDCP device is not authenticated":
++    Check your personnal customer ROMCODE and update accordingly your KEY_SEED value
++    in comps/tmdlHdmiTx/cfg/TDA9989/tmdlHdmiTx_Linux_cfg.c
++
++  . "Where can I get the the KEY_SEED value for HDCP":
++    Ask direcly NXP technical software support
++
++  . "How can I get PC video format like 600x480"
++    Watch out the "features on demand" part of Makefile
++
++  . "I don't get any interrupt wired nor IRQ on my board"
++    Remove the IRQ flag for timer based polling of interrupt
++
++  . "I want to use HDCP"
++    1) Add the nwolc.ko module (or ask it to NXP)
++    2) Add TDA_HDCP := TMFL_HDCP_SUPPORT flag
++    3) set your KEY_SEED number in tmdlHdmiTx_Linux_cfg.c file
++
++  . "HDCP does not work"
++    Ask you key seed to NXP
++
++  . "got unexpected TMDS activity between EDID reading and SetInputOuput"
++    use USER_SET_INPUT_OUTPUT flag
++
++  . "I don't want the module to automatically setup TMDS but from userland instead"
++    use USER_SET_INPUT_OUTPUT flag
++
++  . "I2S audio does not work, N value is not good"
++    Check the audio frequence in hdmi_tx_init or using IOCTL TDA_SET_AUDIO_INPUT_CMD
++    For example, N=6144 at 48KHz, but N=6272 at 44.1Khz
++
++  . "I2S audio does not work, CTS value is not good"
++    Check the audio I2S format in hdmi_tx_init or using IOCTL TDA_SET_AUDIO_INPUT_CMD
++    CTS is automatically computed by the TDA accordingly to the audio input
++    so accordingly to the upstream settings (like an OMAP ;)
++    For example, I2S 16 bits or 32 bits do not produce the same CTS value
++
++  . "How can I change the audio settings ?"
++    Put your own settings in setio.audio_in structure. For example : 
++     this->tda.setio.audio_in.format = TMDL_HDMITX_AFMT_I2S;
++     this->tda.setio.audio_in.rate = TMDL_HDMITX_AFS_44K;
++     this->tda.setio.audio_in.i2sFormat = TMDL_HDMITX_I2SFOR_PHILIPS_L;
++     this->tda.setio.audio_in.i2sQualifier = TMDL_HDMITX_I2SQ_16BITS;
++     this->tda.setio.audio_in.dstRate = TMDL_HDMITX_DSTRATE_SINGLE; /* not relevant here */
++     this->tda.setio.audio_in.channelAllocation = 0; /* audio channel allocation L+R (Ref to CEA-861D p85) */
++
++  . "When shall I set audio  ?"
++    Default (at module startup) is in hdmi_tx_init
++    At will using IOCTL TDA_SET_AUDIO_INPUT_CMD
++
++- Restriction :
++
++  . Remove IRQ flag in Makefile for timer based polling
++  . Add ZOOMII_PATCH to reverse clock edge in ZOOMII
++  . add TWL4030_HACK to get keypad handle and inject CEC::USER_CONTROL events
++  . omap_dss_driver might not be supported by kernel, then hdmi_enable
++    and hdmi_disable should be triggered by any other kernel means or
++    replaced by direct call from application using:
++    -->  ioctl(my_fd,TDA_IOCTL_SET_POWER,[tmPowerOn|tmPowerStandby]);
++  . HDCP can be switch off dynamically with TDA_IOCTL_SET_HDCP but not hw engine,
++    stop it by removing nwolc.ko module
++
++- License :
++
++  . hdmitx and hdmicec modules are free software; you can redistribute
++    it and/or modify it under the terms of the GNU General Public License
++    as published by the Free Software Foundation, using version 2 of the License.
++    These modules are distributed in the hope that it will be useful, but
++    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++    or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++    for more details.
++  . nwolc module source code and any compilation or derivative thereof is
++    the proprietary information of NXP N.V. and is confidential in nature.
++    Under no circumstances is this software to be exposed to or placed under
++    an Open Source License of any type without the expressed written permission
++    of NXP N.V.
++
++- DV :
++
++  . How to create a DV :
++    -> update tda998xversion.h and set PATCH_LEVEL to 0
++    -> update linux_hdmi_release_note.txt
++    $>cd driver/video/hdmi
++    $>make -f MakeModules clean
++    $>cd ..
++    $>tar cvfj $DV_FOLDER/linux-hdmi-nxp-modules.vXYZ.tar.cvfj hdmi
++
++-----------------------------------
++
++- Feedback : vincent.vrignaud@nxp.com -
++
++-----------------------------------
++
+diff --git a/drivers/video/nxp/tda998x.c b/drivers/video/nxp/tda998x.c
+new file mode 100755
+index 0000000..4b45e41
+--- /dev/null
++++ b/drivers/video/nxp/tda998x.c
+@@ -0,0 +1,2307 @@
++/*****************************************************************************/
++/* Copyright (c) 2009 NXP Semiconductors BV                                  */
++/*                                                                           */
++/* This program is free software; you can redistribute it and/or modify      */
++/* it under the terms of the GNU General Public License as published by      */
++/* the Free Software Foundation, using version 2 of the License.             */
++/*                                                                           */
++/* This program is distributed in the hope that it will be useful,           */
++/* but WITHOUT ANY WARRANTY; without even the implied warranty of            */
++/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the              */
++/* GNU General Public License for more details.                              */
++/*                                                                           */
++/* You should have received a copy of the GNU General Public License         */
++/* along with this program; if not, write to the Free Software               */
++/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307       */
++/* USA.                                                                      */
++/*                                                                           */
++/*****************************************************************************/
++
++#define _tx_c_
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/cdev.h>  
++#include <linux/fs.h>
++#include <linux/ioctl.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/workqueue.h>
++#include <linux/interrupt.h>
++#include <asm/uaccess.h>
++#include <mach/gpio.h>
++// #include <mach/display.h>
++
++/* HDMI DevLib */
++#include "tmNxCompId.h"
++#include "tmdlHdmiTx_Types.h"
++#include "tmdlHdmiTx_Functions.h"
++
++/* local */
++#include "tda998x_version.h"
++#include "tda998x.h"
++#include "tda998x_ioctl.h"
++
++#ifdef I2C_DBG
++#include "tmbslHdmiTx_types.h"
++#include "tmbslTDA9989_local.h"
++#endif
++
++#ifdef ANDROID_DSS
++/* DSS hack */
++#endif
++
++/*
++ *
++ * DEFINITION
++ * ----------
++ * LEVEL 0
++ *
++ */
++
++#define FRAME_PACKING 200
++#define NO_FP(x) ((x) % FRAME_PACKING)
++#define IS_FP(x) ((x) > FRAME_PACKING)
++#define WITH_FP(x) ((x) + FRAME_PACKING * (this->tda.setio.video_in.structure3D == TMDL_HDMITX_3D_FRAME_PACKING))
++/*
++ *  Global
++ */
++
++tda_instance our_instance;
++static struct cdev our_cdev, *this_cdev=&our_cdev;
++#ifdef ANDROID_DSS
++static struct omap_video_timings video_640x480at60Hz_panel_timings = {
++   .x_res          = 640,
++   .y_res          = 480,
++   .pixel_clock    = 25175,
++   .hfp            = 16,
++   .hsw            = 96,
++   .hbp            = 48,
++   .vfp            = 10,
++   .vsw            = 2,
++   .vbp            = 33,
++};
++static struct omap_video_timings video_640x480at72Hz_panel_timings = {
++   .x_res          = 640,
++   .y_res          = 480,
++   .pixel_clock    = 31500,
++   .hfp            = 24,
++   .hsw            = 40,
++   .hbp            = 128,
++   .vfp            = 9,
++   .vsw            = 3,
++   .vbp            = 28,
++};
++static struct omap_video_timings video_720x480at60Hz_panel_timings = {
++   .x_res          = 720,
++   .y_res          = 480,
++   .pixel_clock    = 27027,
++   .hfp            = 16,
++   .hbp            = 60,
++   .hsw            = 62,
++   .vfp            = 9,
++   .vbp            = 30,
++   .vsw            = 6,
++};
++static struct omap_video_timings video_1280x720at50Hz_panel_timings = {
++   .x_res          = 1280,
++   .y_res          = 720,
++   .pixel_clock    = 74250,
++#ifdef ZOOMII_PATCH
++   .hfp            = 400,
++   .hbp            = 260,
++#else
++   .hfp            = 440,
++   .hbp            = 220,
++#endif
++   .hsw            = 40,
++   .vfp            = 5,
++   .vbp            = 20,
++   .vsw            = 5,
++};
++static struct omap_video_timings video_1280x720at60Hz_panel_timings = {
++   .x_res          = 1280,
++   .y_res          = 720,
++   .pixel_clock    = 74250,
++#ifdef ZOOMII_PATCH
++   .hfp            = 70,
++   .hbp            = 260,
++#else
++   .hfp            = 110,
++   .hbp            = 220,
++#endif
++   .hsw            = 40,
++   .vfp            = 5,
++   .vbp            = 20,
++   .vsw            = 5,
++};
++static struct omap_video_timings video_1920x1080at50Hz_panel_timings = {
++   .x_res          = 1920,
++   .y_res          = 1080,
++   .pixel_clock    = 148500, /* 2640 x 1125 x 50 /2 */
++#ifdef ZOOMII_PATCH
++   .hfp            = 488,
++   .hbp            = 188,
++#else
++   .hfp            = 528,
++   .hbp            = 148,
++#endif
++   .hsw            = 44,
++   .vfp            = 4,
++   .vbp            = 36,
++   .vsw            = 5,
++};
++static struct omap_video_timings video_800x480at60Hz_panel_timings = {
++   /*    .x_res = 800 /\* 1280 *\/, */
++   /*    .y_res = 480 /\* 720 *\/, */
++   /*    .pixel_clock = 21800 /\* 21800 23800 25700 *\/, */
++   .x_res = 800,
++   .y_res = 480,
++   .pixel_clock = 21800,
++   .hfp = 6,
++   .hsw = 1,
++   .hbp = 4,
++   .vfp = 3,
++   .vsw = 1,
++   .vbp = 4,
++};
++
++#endif
++
++/* #define HDCP_TEST 1 */
++#ifdef HDCP_TEST
++/* TEST */
++int test = 0;
++#endif
++
++/*
++ *  Module params
++ */
++
++static int param_verbose=0,param_major=0,param_minor=0;
++module_param_named(verbose,param_verbose,int,S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(verbose, "Make the driver verbose");
++module_param_named(major, param_major, int, S_IRUGO);
++MODULE_PARM_DESC(major, "The major number of the device mapper");
++
++/*
++ *
++ * TOOLBOX
++ * -------
++ * LEVEL 1
++ *
++ * - i2c read/write
++ * - chip Id check
++ * - i2c client info
++ * 
++ */
++
++/* 
++ *  Get main and unique I2C Client driver handle
++ */
++struct i2c_client *GetThisI2cClient(void)
++{
++   tda_instance *this=&our_instance;
++   return this->driver.i2c_client;
++}
++
++/*
++ * error handling
++ */
++char *hdmi_tx_err_string(int err)
++{
++   switch (err & 0x0FFF)
++      {
++      case TM_ERR_COMPATIBILITY: {return "SW Interface compatibility";break;}
++      case TM_ERR_MAJOR_VERSION: {return "SW Major Version error";break;}
++      case TM_ERR_COMP_VERSION: {return "SW component version error";break;}
++      case TM_ERR_BAD_UNIT_NUMBER: {return "Invalid device unit number";break;}
++      case TM_ERR_BAD_INSTANCE: {return "Bad input instance value  ";break;}
++      case TM_ERR_BAD_HANDLE: {return "Bad input handle";break;}
++      case TM_ERR_BAD_PARAMETER: {return "Invalid input parameter";break;}
++      case TM_ERR_NO_RESOURCES: {return "Resource is not available ";break;}
++      case TM_ERR_RESOURCE_OWNED: {return "Resource is already in use";break;}
++      case TM_ERR_RESOURCE_NOT_OWNED: {return "Caller does not own resource";break;}
++      case TM_ERR_INCONSISTENT_PARAMS: {return "Inconsistent input params";break;}
++      case TM_ERR_NOT_INITIALIZED: {return "Component is not initialised";break;}
++      case TM_ERR_NOT_SUPPORTED: {return "Function is not supported";break;}
++      case TM_ERR_INIT_FAILED: {return "Initialization failed";break;}
++      case TM_ERR_BUSY: {return "Component is busy";break;}
++      case TMDL_ERR_DLHDMITX_I2C_READ: {return "Read error";break;}
++      case TMDL_ERR_DLHDMITX_I2C_WRITE: {return "Write error";break;}
++      case TM_ERR_FULL: {return "Queue is full";break;}
++      case TM_ERR_NOT_STARTED: {return "Function is not started";break;}
++      case TM_ERR_ALREADY_STARTED: {return "Function is already starte";break;}
++      case TM_ERR_ASSERTION: {return "Assertion failure";break;}
++      case TM_ERR_INVALID_STATE: {return "Invalid state for function";break;}
++      case TM_ERR_OPERATION_NOT_PERMITTED: {return "Corresponds to posix EPERM";break;}
++      case TMDL_ERR_DLHDMITX_RESOLUTION_UNKNOWN: {return "Bad format";break;}
++      case TM_OK: {return "OK";break;}
++      default : {printk(KERN_INFO "(err:%x) ",err);return "unknown";break;}
++      }
++}
++
++static char *tda_spy_event(int event)
++{
++   switch (event)
++      {
++      case TMDL_HDMITX_HDCP_ACTIVE: {return "HDCP active";break;}
++      case TMDL_HDMITX_HDCP_INACTIVE: {return "HDCP inactive";break;}
++      case TMDL_HDMITX_HPD_ACTIVE: {return "HPD active";break;}
++      case TMDL_HDMITX_HPD_INACTIVE: {return "HPD inactive";break;}
++      case TMDL_HDMITX_RX_KEYS_RECEIVED: {return "Rx keys received";break;}
++      case TMDL_HDMITX_RX_DEVICE_ACTIVE: {return "Rx device active";break;}
++      case TMDL_HDMITX_RX_DEVICE_INACTIVE: {return "Rx device inactive";break;}
++      case TMDL_HDMITX_EDID_RECEIVED: {return "EDID received";break;}
++      case TMDL_HDMITX_VS_RPT_RECEIVED: {return "VS interrupt has been received";break;}
++         /*       case TMDL_HDMITX_B_STATUS: {return "TX received BStatus";break;} */ 
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++      case TMDL_HDMITX_DEBUG_EVENT_1: {return "DEBUG_EVENT_1";break;}
++#endif
++      default : {return "Unkonwn event";break;}
++      }
++}
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++static char *tda_spy_hsdc_fail_status(int fail)
++{
++   switch (fail)
++      {
++      case TMDL_HDMITX_HDCP_OK: {return "ok";break;}
++      case  TMDL_HDMITX_HDCP_BKSV_RCV_FAIL: {return "Source does not receive Sink BKsv ";break;}
++      case TMDL_HDMITX_HDCP_BKSV_CHECK_FAIL: {return "BKsv does not contain 20 zeros and 20 ones";break;}
++      case TMDL_HDMITX_HDCP_BCAPS_RCV_FAIL: {return "Source does not receive Sink Bcaps";break;}
++      case TMDL_HDMITX_HDCP_AKSV_SEND_FAIL: {return "Source does not send AKsv";break;}
++      case TMDL_HDMITX_HDCP_R0_RCV_FAIL: {return "Source does not receive R'0";break;}
++      case TMDL_HDMITX_HDCP_R0_CHECK_FAIL: {return "R0 = R'0 check fail";break;}
++      case TMDL_HDMITX_HDCP_BKSV_NOT_SECURE: {return "bksv not secure";break;}
++      case TMDL_HDMITX_HDCP_RI_RCV_FAIL: {return "Source does not receive R'i";break;}
++      case TMDL_HDMITX_HDCP_RPT_RI_RCV_FAIL: {return "Source does not receive R'i repeater mode";break;}
++      case TMDL_HDMITX_HDCP_RI_CHECK_FAIL: {return "RI = R'I check fail";break;}
++      case TMDL_HDMITX_HDCP_RPT_RI_CHECK_FAIL: {return "RI = R'I check fail repeater mode";break;}
++      case TMDL_HDMITX_HDCP_RPT_BCAPS_RCV_FAIL: {return "Source does not receive Sink Bcaps repeater mode";break;}
++      case TMDL_HDMITX_HDCP_RPT_BCAPS_READY_TIMEOUT: {return "bcaps ready timeout";break;}
++      case TMDL_HDMITX_HDCP_RPT_V_RCV_FAIL: {return "Source does not receive V";break;}
++      case TMDL_HDMITX_HDCP_RPT_BSTATUS_RCV_FAIL: {return "Source does not receive BSTATUS repeater mode";break;}
++      case TMDL_HDMITX_HDCP_RPT_KSVLIST_RCV_FAIL: {return "Source does not receive Ksv list in repeater mode";break;}
++      case TMDL_HDMITX_HDCP_RPT_KSVLIST_NOT_SECURE: {return "ksvlist not secure";break;}
++      default: {return "";break;}
++      }
++}
++
++static char *tda_spy_hdcp_status(int status)
++{
++   switch (status)
++      {
++      case TMDL_HDMITX_HDCP_CHECK_NOT_STARTED: {return "Check not started";break;}
++      case TMDL_HDMITX_HDCP_CHECK_IN_PROGRESS: {return "No failures, more to do";break;}
++      case TMDL_HDMITX_HDCP_CHECK_PASS: {return "Final check has passed";break;}
++      case TMDL_HDMITX_HDCP_CHECK_FAIL_FIRST: {return "First check failure code\nDriver not AUTHENTICATED";break;}
++      case TMDL_HDMITX_HDCP_CHECK_FAIL_DEVICE_T0: {return "A T0 interrupt occurred";break;}
++      case TMDL_HDMITX_HDCP_CHECK_FAIL_DEVICE_RI: {return "Device RI changed";break;}
++      case TMDL_HDMITX_HDCP_CHECK_FAIL_DEVICE_FSM: {return "Device FSM not 10h";break;}
++      default : {return "Unknown hdcp status";break;}
++      }
++
++}
++#endif
++
++static char *tda_spy_sink(int sink)
++{
++   switch (sink)
++      {
++      case TMDL_HDMITX_SINK_DVI: {return "DVI";break;}
++      case TMDL_HDMITX_SINK_HDMI: {return "HDMI";break;}
++      case TMDL_HDMITX_SINK_EDID: {return "As currently defined in EDID";break;}
++      default : {return "Unkonwn sink";break;}
++      }
++}
++
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++static char *tda_spy_aspect_ratio(int ar)
++{
++   switch (ar)
++      {
++      case TMDL_HDMITX_P_ASPECT_RATIO_UNDEFINED: {return "Undefined picture aspect rati";break;}
++      case TMDL_HDMITX_P_ASPECT_RATIO_6_5: {return "6:5 picture aspect ratio (PAR";break;}
++      case TMDL_HDMITX_P_ASPECT_RATIO_5_4: {return "5:4 PA";break;}
++      case TMDL_HDMITX_P_ASPECT_RATIO_4_3: {return "4:3 PA";break;}
++      case TMDL_HDMITX_P_ASPECT_RATIO_16_10: {return "16:10 PA";break;}
++      case TMDL_HDMITX_P_ASPECT_RATIO_5_3: {return "5:3 PA";break;}
++      case TMDL_HDMITX_P_ASPECT_RATIO_16_9: {return "16:9 PA";break;}
++      case TMDL_HDMITX_P_ASPECT_RATIO_9_5: {return "9:5 PA";break;}
++      default : {return "Unknown aspect ratio";break;}
++      }
++}
++
++#if 0 /* no more used */
++static char *tda_spy_edid_status(int status)
++{
++   switch (status)
++      {
++      case TMDL_HDMITX_EDID_READ: {return "All blocks read";break;}
++      case TMDL_HDMITX_EDID_READ_INCOMPLETE: {return "All blocks read OK but buffer too small to return all of the";break;}
++      case TMDL_HDMITX_EDID_ERROR_CHK_BLOCK_0: {return "Block 0 checksum erro";break;}
++      case TMDL_HDMITX_EDID_ERROR_CHK: {return "Block 0 OK, checksum error in one or more other block";break;}
++      case TMDL_HDMITX_EDID_NOT_READ: {return "EDID not read";break;}
++      case TMDL_HDMITX_EDID_STATUS_INVALID: {return "Invalid ";break;}
++      default : {return "Unknown edid status";break;}
++      }
++}
++#endif
++
++static char *tda_spy_vfmt(int fmt)
++{
++   switch (fmt)
++      {
++      case TMDL_HDMITX_VFMT_NULL: {return "NOT a valid format...";break;}
++      case TMDL_HDMITX_VFMT_01_640x480p_60Hz: {return "vic 01: 640x480p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_02_720x480p_60Hz: {return "vic 02: 720x480p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_03_720x480p_60Hz: {return "vic 03: 720x480p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_04_1280x720p_60Hz: {return "vic 04: 1280x720p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_05_1920x1080i_60Hz: {return "vic 05: 1920x1080i 60Hz";break;}
++      case TMDL_HDMITX_VFMT_06_720x480i_60Hz: {return "vic 06: 720x480i 60Hz";break;}
++      case TMDL_HDMITX_VFMT_07_720x480i_60Hz: {return "vic 07: 720x480i 60Hz";break;}
++      case TMDL_HDMITX_VFMT_08_720x240p_60Hz: {return "vic 08: 720x240p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_09_720x240p_60Hz: {return "vic 09: 720x240p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_10_720x480i_60Hz: {return "vic 10: 720x480i 60Hz";break;}
++      case TMDL_HDMITX_VFMT_11_720x480i_60Hz: {return "vic 11: 720x480i 60Hz";break;}
++      case TMDL_HDMITX_VFMT_12_720x240p_60Hz: {return "vic 12: 720x240p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_13_720x240p_60Hz: {return "vic 13: 720x240p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_14_1440x480p_60Hz: {return "vic 14: 1440x480p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_15_1440x480p_60Hz: {return "vic 15: 1440x480p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_16_1920x1080p_60Hz: {return "vic 16: 1920x1080p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_17_720x576p_50Hz: {return "vic 17: 720x576p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_18_720x576p_50Hz: {return "vic 18: 720x576p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_19_1280x720p_50Hz: {return "vic 19: 1280x720p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_20_1920x1080i_50Hz: {return "vic 20: 1920x1080i 50Hz";break;}
++      case TMDL_HDMITX_VFMT_21_720x576i_50Hz: {return "vic 21: 720x576i 50Hz";break;}
++      case TMDL_HDMITX_VFMT_22_720x576i_50Hz: {return "vic 22: 720x576i 50Hz";break;}
++      case TMDL_HDMITX_VFMT_23_720x288p_50Hz: {return "vic 23: 720x288p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_24_720x288p_50Hz: {return "vic 24: 720x288p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_25_720x576i_50Hz: {return "vic 25: 720x576i 50Hz";break;}
++      case TMDL_HDMITX_VFMT_26_720x576i_50Hz: {return "vic 26: 720x576i 50Hz";break;}
++      case TMDL_HDMITX_VFMT_27_720x288p_50Hz: {return "vic 27: 720x288p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_28_720x288p_50Hz: {return "vic 28: 720x288p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_29_1440x576p_50Hz: {return "vic 29: 1440x576p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_30_1440x576p_50Hz: {return "vic 30: 1440x576p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_31_1920x1080p_50Hz: {return "vic 31: 1920x1080p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_32_1920x1080p_24Hz: {return "vic 32: 1920x1080p 24Hz";break;}
++      case TMDL_HDMITX_VFMT_33_1920x1080p_25Hz: {return "vic 33: 1920x1080p 25Hz";break;}
++      case TMDL_HDMITX_VFMT_34_1920x1080p_30Hz: {return "vic 34: 1920x1080p 30Hz";break;}
++      case TMDL_HDMITX_VFMT_35_2880x480p_60Hz: {return "vic 3: 2880x480p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_36_2880x480p_60Hz: {return "vic 3: 2880x480p 60Hz";break;}
++      case TMDL_HDMITX_VFMT_37_2880x576p_50Hz: {return "vic 3: 2880x576p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_38_2880x576p_50Hz: {return "vic 3: 2880x576p 50Hz";break;}
++      case TMDL_HDMITX_VFMT_60_1280x720p_24Hz: {return "vic 60: 1280x720p 24Hz";break;}
++      case TMDL_HDMITX_VFMT_61_1280x720p_25Hz: {return "vic 61: 1280x720p 25Hz";break;}
++      case TMDL_HDMITX_VFMT_62_1280x720p_30Hz: {return "vic 62: 1280x720p 30Hz";break;}
++      case TMDL_HDMITX_VFMT_PC_800x600p_60Hz: {return "PC 129";break;}
++      case TMDL_HDMITX_VFMT_PC_1152x960p_60Hz: {return "PC 130";break;}
++      case TMDL_HDMITX_VFMT_PC_1024x768p_60Hz: {return "PC 131";break;}
++      case TMDL_HDMITX_VFMT_PC_1280x768p_60Hz: {return "PC 132";break;}
++      case TMDL_HDMITX_VFMT_PC_1280x1024p_60Hz: {return "PC 133";break;}
++      case TMDL_HDMITX_VFMT_PC_1360x768p_60Hz: {return "PC 134";break;}
++      case TMDL_HDMITX_VFMT_PC_1400x1050p_60Hz: {return "PC 135";break;}
++      case TMDL_HDMITX_VFMT_PC_1600x1200p_60Hz: {return "PC 136";break;}
++      case TMDL_HDMITX_VFMT_PC_1024x768p_70Hz: {return "PC 137";break;}
++      case TMDL_HDMITX_VFMT_PC_640x480p_72Hz: {return "PC 138";break;}
++      case TMDL_HDMITX_VFMT_PC_800x600p_72Hz: {return "PC 139";break;}
++      case TMDL_HDMITX_VFMT_PC_640x480p_75Hz: {return "PC 140";break;}
++      case TMDL_HDMITX_VFMT_PC_1024x768p_75Hz: {return "PC 141";break;}
++      case TMDL_HDMITX_VFMT_PC_800x600p_75Hz: {return "PC 142";break;}
++      case TMDL_HDMITX_VFMT_PC_1024x864p_75Hz: {return "PC 143";break;}
++      case TMDL_HDMITX_VFMT_PC_1280x1024p_75Hz: {return "PC 144";break;}
++      case TMDL_HDMITX_VFMT_PC_640x350p_85Hz: {return "PC 145";break;}
++      case TMDL_HDMITX_VFMT_PC_640x400p_85Hz: {return "PC 146";break;}
++      case TMDL_HDMITX_VFMT_PC_720x400p_85Hz: {return "PC 147";break;}
++      case TMDL_HDMITX_VFMT_PC_640x480p_85Hz: {return "PC 148";break;}
++      case TMDL_HDMITX_VFMT_PC_800x600p_85Hz: {return "PC 149";break;}
++      case TMDL_HDMITX_VFMT_PC_1024x768p_85Hz: {return "PC 150";break;}
++      case TMDL_HDMITX_VFMT_PC_1152x864p_85Hz: {return "PC 151";break;}
++      case TMDL_HDMITX_VFMT_PC_1280x960p_85Hz: {return "PC 152";break;}
++      case TMDL_HDMITX_VFMT_PC_1280x1024p_85Hz: {return "PC 153";break;}
++      case TMDL_HDMITX_VFMT_PC_1024x768i_87Hz: {return "PC 154";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_02_720x480p_60Hz: {return "vic 02: 720x480p 60Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_17_720x576p_50Hz: {return "vic 17: 720x576p 50Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_60_1280x720p_24Hz: {return "vic 60: 1280x720p 24Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_61_1280x720p_25Hz: {return "vic 61: 1280x720p 25Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_62_1280x720p_30Hz: {return "vic 62: 1280x720p 30Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_19_1280x720p_50Hz: {return "vic 19: 1280x720p 50Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_04_1280x720p_60Hz: {return "vic 04: 1280x720p 60Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_32_1920x1080p_24Hz: {return "vic 32: 1920x1080p 24Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_33_1920x1080p_25Hz: {return "vic 33: 1920x1080p 25Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_34_1920x1080p_30Hz: {return "vic 34: 1920x1080p 30Hz frame packing";break;}     
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_31_1920x1080p_50Hz: {return "vic 31: 1920x1080p 50Hz frame packing";break;}
++      case FRAME_PACKING + TMDL_HDMITX_VFMT_16_1920x1080p_60Hz: {return "vic 16: 1920x1080p 60Hz frame packing";break;}
++      default : {return "unknown video format";break;}
++      }
++}
++#endif
++
++static char *tda_spy_audio_fmt(int fmt)
++{
++   switch (fmt)
++      {
++      case TMDL_HDMITX_AFMT_SPDIF: {return "SPDIF";break;}
++      case TMDL_HDMITX_AFMT_I2S: {return "I2S";break;}
++      case TMDL_HDMITX_AFMT_OBA: {return "OBA";break;}
++      case TMDL_HDMITX_AFMT_DST: {return "DST";break;}
++      case TMDL_HDMITX_AFMT_HBR: {return "HBR";break;}
++      default : {return "Unknown audio format";break;}
++      }
++}
++
++static char *tda_spy_audio_freq(int freq)
++{
++   switch (freq)
++      {
++      case TMDL_HDMITX_AFS_32K: {return "32k";break;}
++      case TMDL_HDMITX_AFS_44K: {return "44k";break;}
++      case TMDL_HDMITX_AFS_48K: {return "48k";break;}
++      case TMDL_HDMITX_AFS_88K: {return "88k";break;}
++      case TMDL_HDMITX_AFS_96K: {return "96k";break;}
++      case TMDL_HDMITX_AFS_176K: {return "176k";break;}
++      case TMDL_HDMITX_AFS_192K: {return "192k";break;}
++      default : {return "Unknown audio freq";break;}
++      }
++}
++
++static char *tda_spy_audio_i2c(int bits)
++{
++   switch (bits)
++      {
++      case TMDL_HDMITX_I2SQ_16BITS: {return "16 bits";break;}
++      case TMDL_HDMITX_I2SQ_32BITS: {return "32 bits";break;}
++      default : {return "Unknown audio i2c sampling";break;}
++      }
++}
++
++static char *tda_spy_audio_i2c4(int align)
++{
++   switch (align)
++      {
++      case TMDL_HDMITX_I2SFOR_PHILIPS_L: {return "Philips Left";break;}
++      case TMDL_HDMITX_I2SFOR_OTH_L: {return "other left";break;}
++      case TMDL_HDMITX_I2SFOR_OTH_R: {return "other right";break;}
++      default : {return "Unknown audio I2C alignement";break;}
++      }
++}
++
++static void tda_spy_audio(tmdlHdmiTxAudioInConfig_t *audio)
++{
++   printk(KERN_INFO "hdmitx audio input\n format:%d(%s) rate:%d(%s) i2c_format:%d(%s) i2c_qualif:%d(%s) dst_rate:%d channel:%d\n", \
++          audio->format,                                                \
++          tda_spy_audio_fmt(audio->format),                             \
++          audio->rate,                                                  \
++          tda_spy_audio_freq(audio->rate),                              \
++          audio->i2sFormat,                                             \
++          tda_spy_audio_i2c4(audio->i2sFormat),                         \
++          audio->i2sQualifier,                                          \
++          tda_spy_audio_i2c(audio->i2sQualifier),                       \
++          audio->dstRate,                                               \
++          audio->channelAllocation);
++ }
++
++
++static char *tda_ioctl(int io)
++{
++   switch (io)
++      {
++      case TDA_VERBOSE_ON_CMD: {return "TDA_VERBOSE_ON_CMD";break;}
++      case TDA_VERBOSE_OFF_CMD: {return "TDA_VERBOSE_OFF_CMD";break;}
++      case TDA_BYEBYE_CMD: {return "TDA_BYEBYE_CMD";break;}
++      case TDA_GET_SW_VERSION_CMD: {return "TDA_GET_SW_VERSION_CMD";break;}
++      case TDA_SET_POWER_CMD: {return "TDA_SET_POWER_CMD";break;}
++      case TDA_GET_POWER_CMD: {return "TDA_GET_POWER_CMD";break;}
++      case TDA_SETUP_CMD: {return "TDA_SETUP_CMD";break;}
++      case TDA_GET_SETUP_CMD: {return "TDA_GET_SETUP_CMD";break;}
++      case TDA_WAIT_EVENT_CMD: {return "TDA_WAIT_EVENT_CMD";break;}
++      case TDA_ENABLE_EVENT_CMD: {return "TDA_ENABLE_EVENT_CMD";break;}
++      case TDA_DISABLE_EVENT_CMD: {return "TDA_DISABLE_EVENT_CMD";break;}
++      case TDA_GET_VIDEO_SPEC_CMD: {return "TDA_GET_VIDEO_SPEC_CMD";break;}
++      case TDA_SET_INPUT_OUTPUT_CMD: {return "TDA_SET_INPUT_OUTPUT_CMD";break;}
++      case TDA_SET_AUDIO_INPUT_CMD: {return "TDA_SET_AUDIO_INPUT_CMD";break;}
++      case TDA_SET_VIDEO_INFOFRAME_CMD: {return "TDA_SET_VIDEO_INFOFRAME_CMD";break;}
++      case TDA_SET_AUDIO_INFOFRAME_CMD: {return "TDA_SET_AUDIO_INFOFRAME_CMD";break;}
++      case TDA_SET_ACP_CMD: {return "TDA_SET_ACP_CMD";break;}
++      case TDA_SET_GCP_CMD: {return "TDA_SET_GCP_CMD";break;}
++      case TDA_SET_ISRC1_CMD: {return "TDA_SET_ISRC1_CMD";break;}
++      case TDA_SET_ISRC2_CMD: {return "TDA_SET_ISRC2_CMD";break;}
++      case TDA_SET_MPS_INFOFRAME_CMD: {return "TDA_SET_MPS_INFOFRAME_CMD";break;}
++      case TDA_SET_SPD_INFOFRAME_CMD: {return "TDA_SET_SPD_INFOFRAME_CMD";break;}
++      case TDA_SET_VS_INFOFRAME_CMD: {return "TDA_SET_VS_INFOFRAME_CMD";break;}
++      case TDA_SET_AUDIO_MUTE_CMD: {return "TDA_SET_AUDIO_MUTE_CMD";break;}
++      case TDA_RESET_AUDIO_CTS_CMD: {return "TDA_RESET_AUDIO_CTS_CMD";break;}
++      case TDA_GET_EDID_STATUS_CMD: {return "TDA_GET_EDID_STATUS_CMD";break;}
++      case TDA_GET_EDID_AUDIO_CAPS_CMD: {return "TDA_GET_EDID_AUDIO_CAPS_CMD";break;}
++      case TDA_GET_EDID_VIDEO_CAPS_CMD: {return "TDA_GET_EDID_VIDEO_CAPS_CMD";break;}
++      case TDA_GET_EDID_VIDEO_PREF_CMD: {return "TDA_GET_EDID_VIDEO_PREF_CMD";break;}
++      case TDA_GET_EDID_SINK_TYPE_CMD: {return "TDA_GET_EDID_SINK_TYPE_CMD";break;}
++      case TDA_GET_EDID_SOURCE_ADDRESS_CMD: {return "TDA_GET_EDID_SOURCE_ADDRESS_CMD";break;}
++      case TDA_SET_GAMMUT_CMD: {return "TDA_SET_GAMMUT_CMD";break;}
++      case TDA_GET_EDID_DTD_CMD: {return "TDA_GET_EDID_DTD_CMD";break;}
++      case TDA_GET_EDID_MD_CMD: {return "TDA_GET_EDID_MD_CMD";break;}
++      case TDA_GET_EDID_TV_ASPECT_RATIO_CMD: {return "TDA_GET_EDID_TV_ASPECT_RATIO_CMD";break;}
++      case TDA_GET_EDID_LATENCY_CMD: {return "TDA_GET_EDID_LATENCY_CMD";break;}
++      case TDA_GET_HPD_STATUS_CMD: {return "TDA_GET_HPD_STATUS_CMD";break;}
++      default : {return "unknown";break;}
++      }
++
++
++}
++
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++/*
++ *  
++ */
++static int tda_spy(int verbose)
++{
++   tda_instance *this=&our_instance;
++   int i,err=0;
++
++   if (!verbose) {
++      return err;
++   }
++
++   printk(KERN_INFO "\n<edid video caps>\n");
++   this->tda.edid_video_caps.max=EXAMPLE_MAX_SVD;
++   TRY(tmdlHdmiTxGetEdidVideoCaps(this->tda.instance,              \
++                                  this->tda.edid_video_caps.desc, \
++                                  this->tda.edid_video_caps.max,      \
++                                  &this->tda.edid_video_caps.written, \
++                                  &this->tda.edid_video_caps.flags));
++   printk(KERN_INFO "written:%d\n",this->tda.edid_video_caps.written);
++   printk(KERN_INFO "flags:0X%x\n",this->tda.edid_video_caps.flags);
++   if (this->tda.edid_video_caps.written > this->tda.edid_video_caps.max) {
++      printk(KERN_ERR "get %d video caps but was waiting for %d\n", \
++             this->tda.edid_video_caps.written,                     \
++             this->tda.edid_video_caps.max); 
++      this->tda.edid_video_caps.written = this->tda.edid_video_caps.max;
++   }
++   for(i=0; i<this->tda.edid_video_caps.written;i++) {
++      printk(KERN_INFO "videoFormat: %s\n",tda_spy_vfmt(this->tda.edid_video_caps.desc[i].videoFormat));
++      printk(KERN_INFO "nativeVideoFormat:%s\n",(this->tda.edid_video_caps.desc[i].nativeVideoFormat?"yes":"no"));
++   }
++
++   printk(KERN_INFO "\n<edid video timings>\n");
++   TRY(tmdlHdmiTxGetEdidVideoPreferred(this->tda.instance, \
++                                       &this->tda.edid_video_timings));
++   printk(KERN_INFO "Pixel Clock/10 000:%d\n",this->tda.edid_video_timings.pixelClock);
++   printk(KERN_INFO "Horizontal Active Pixels:%d\n",this->tda.edid_video_timings.hActivePixels);
++   printk(KERN_INFO "Horizontal Blanking Pixels:%d\n",this->tda.edid_video_timings.hBlankPixels);
++   printk(KERN_INFO "Vertical Active Lines:%d\n",this->tda.edid_video_timings.vActiveLines);
++   printk(KERN_INFO "Vertical Blanking Lines:%d\n",this->tda.edid_video_timings.vBlankLines);
++   printk(KERN_INFO "Horizontal Sync Offset:%d\n",this->tda.edid_video_timings.hSyncOffset);
++   printk(KERN_INFO "Horiz. Sync Pulse Width:%d\n",this->tda.edid_video_timings.hSyncWidth);
++   printk(KERN_INFO "Vertical Sync Offset:%d\n",this->tda.edid_video_timings.vSyncOffset);
++   printk(KERN_INFO "Vertical Sync Pulse Width:%d\n",this->tda.edid_video_timings.vSyncWidth);
++   printk(KERN_INFO "Horizontal Image Size:%d\n",this->tda.edid_video_timings.hImageSize);
++   printk(KERN_INFO "Vertical Image Size:%d\n",this->tda.edid_video_timings.vImageSize);
++   printk(KERN_INFO "Horizontal Border:%d\n",this->tda.edid_video_timings.hBorderPixels);
++   printk(KERN_INFO "Vertical Border:%d\n",this->tda.edid_video_timings.vBorderPixels);
++   printk(KERN_INFO "Interlace/sync info:%x\n",this->tda.edid_video_timings.flags);
++
++   printk(KERN_INFO "\n<sink type>\n");
++   TRY(tmdlHdmiTxGetEdidSinkType(this->tda.instance,    \
++                                 &this->tda.setio.sink));
++   printk(KERN_INFO "%s\n",tda_spy_sink(this->tda.setio.sink));
++   printk(KERN_INFO "\n<source address>\n");
++   TRY(tmdlHdmiTxGetEdidSourceAddress(this->tda.instance,   \
++                                      &this->tda.src_address));
++   printk(KERN_INFO "%x\n",this->tda.src_address);
++   printk(KERN_INFO "\n<detailled timing descriptors>\n");
++   this->tda.edid_dtd.max=EXAMPLE_MAX_SVD;
++   TRY(tmdlHdmiTxGetEdidDetailledTimingDescriptors(this->tda.instance,  \
++                                                   this->tda.edid_dtd.desc, \
++                                                   this->tda.edid_dtd.max, \
++                                                   &this->tda.edid_dtd.written));
++   printk(KERN_INFO "Interlace/sync info:%x\n",this->tda.edid_dtd.desc[i].flags);
++   printk(KERN_INFO "written:%d\n",this->tda.edid_dtd.written);
++   if (this->tda.edid_dtd.written > this->tda.edid_dtd.max) {
++      printk(KERN_ERR "get %d video caps but was waiting for %d\n", \
++             this->tda.edid_dtd.written,                     \
++             this->tda.edid_dtd.max); 
++      this->tda.edid_dtd.written = this->tda.edid_dtd.max;
++   }
++   for(i=0; i<this->tda.edid_dtd.written;i++) {
++      printk(KERN_INFO "Pixel Clock/10 000:%d\n",this->tda.edid_dtd.desc[i].pixelClock);
++      printk(KERN_INFO "Horizontal Active Pixels:%d\n",this->tda.edid_dtd.desc[i].hActivePixels);
++      printk(KERN_INFO "Horizontal Blanking Pixels:%d\n",this->tda.edid_dtd.desc[i].hBlankPixels);
++      printk(KERN_INFO "Vertical Active Lines:%d\n",this->tda.edid_dtd.desc[i].vActiveLines);
++      printk(KERN_INFO "Vertical Blanking Lines:%d\n",this->tda.edid_dtd.desc[i].vBlankLines);
++      printk(KERN_INFO "Horizontal Sync Offset:%d\n",this->tda.edid_dtd.desc[i].hSyncOffset);
++      printk(KERN_INFO "Horiz. Sync Pulse Width:%d\n",this->tda.edid_dtd.desc[i].hSyncWidth);
++      printk(KERN_INFO "Vertical Sync Offset:%d\n",this->tda.edid_dtd.desc[i].vSyncOffset);
++      printk(KERN_INFO "Vertical Sync Pulse Width:%d\n",this->tda.edid_dtd.desc[i].vSyncWidth);
++      printk(KERN_INFO "Horizontal Image Size:%d\n",this->tda.edid_dtd.desc[i].hImageSize);
++      printk(KERN_INFO "Vertical Image Size:%d\n",this->tda.edid_dtd.desc[i].vImageSize);
++      printk(KERN_INFO "Horizontal Border:%d\n",this->tda.edid_dtd.desc[i].hBorderPixels);
++      printk(KERN_INFO "Vertical Border:%d\n",this->tda.edid_dtd.desc[i].vBorderPixels);
++   }
++
++   printk(KERN_INFO "\n<monitor descriptors>\n");
++   this->tda.edid_md.max=EXAMPLE_MAX_SVD;
++   TRY(tmdlHdmiTxGetEdidMonitorDescriptors(this->tda.instance,  \
++                                           this->tda.edid_md.desc1,    \
++                                           this->tda.edid_md.desc2,    \
++                                           this->tda.edid_md.other,    \
++                                           this->tda.edid_md.max,       \
++                                           &this->tda.edid_md.written));
++   printk(KERN_INFO "written:%d\n",this->tda.edid_md.written);
++   if (this->tda.edid_md.written > this->tda.edid_md.max) {
++      printk(KERN_ERR "get %d video caps but was waiting for %d\n", \
++             this->tda.edid_md.written,                     \
++             this->tda.edid_md.max); 
++      this->tda.edid_md.written = this->tda.edid_md.max;
++   }
++   for(i=0; i<this->tda.edid_md.written;i++) {
++      if (this->tda.edid_md.desc1[i].descRecord) {
++         this->tda.edid_md.desc1[i].monitorName[EDID_MONITOR_DESCRIPTOR_SIZE-1]=0;
++         printk(KERN_INFO "Monitor name:%s\n",this->tda.edid_md.desc1[i].monitorName);
++      }
++      if (this->tda.edid_md.desc1[i].descRecord) {
++         printk(KERN_INFO "Min vertical rate in Hz:%d\n",this->tda.edid_md.desc2[i].minVerticalRate);
++         printk(KERN_INFO "Max vertical rate in Hz:%d\n",this->tda.edid_md.desc2[i].maxVerticalRate);
++         printk(KERN_INFO "Min horizontal rate in Hz:%d\n",this->tda.edid_md.desc2[i].minHorizontalRate);
++         printk(KERN_INFO "Max horizontal rate in Hz:%d\n",this->tda.edid_md.desc2[i].maxHorizontalRate);
++         printk(KERN_INFO "Max supported pixel clock rate in MHz:%d\n",this->tda.edid_md.desc2[i].maxSupportedPixelClk);
++      }
++   }
++
++   printk(KERN_INFO "\n<TV picture ratio>\n");
++   TRY(tmdlHdmiTxGetEdidTVPictureRatio(this->tda.instance,  \
++                                       &this->tda.edid_tv_aspect_ratio));
++   printk(KERN_INFO "%s\n",tda_spy_aspect_ratio(this->tda.edid_tv_aspect_ratio));
++
++   printk(KERN_INFO "\n<latency info>\n");
++   TRY(tmdlHdmiTxGetEdidLatencyInfo(this->tda.instance, \
++                                    &this->tda.edid_latency));
++   if (this->tda.edid_latency.latency_available) {
++      printk(KERN_INFO "Edid video:%d\n",this->tda.edid_latency.Edidvideo_latency);
++      printk(KERN_INFO "Edid audio:%d\n",this->tda.edid_latency.Edidaudio_latency);
++   }
++   if (this->tda.edid_latency.Ilatency_available) {
++      printk(KERN_INFO "Edid Ivideo:%d\n",this->tda.edid_latency.EdidIvideo_latency);
++      printk(KERN_INFO "Edid Iaudio:%d\n",this->tda.edid_latency.EdidIaudio_latency);
++   }
++ TRY_DONE:
++   return err;
++}
++#endif
++
++/*
++ *
++ * PROCESSING
++ * ----------
++ * LEVEL 2
++ *
++ * - 
++ *
++ */
++
++/*
++ * On HDCP
++ */
++void hdcp_on(tda_instance *this) {
++
++   int err=0;
++
++   if (this->tda.hdcp_status != HDCP_IS_NOT_INSTALLED) { /* check HDCP is installed ... */
++         if (this->tda.hdcp_enable) { /* ... but requested ! */ 
++            TRY(tmdlHdmiTxSetHdcp(this->tda.instance,True)); /* switch if on */
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++            /* hide video content until HDCP authentification is finished */
++            if (!this->tda.setup.simplayHd) {
++               TRY(tmdlHdmiTxSetBScreen(this->tda.instance,TMDL_HDMITX_PATTERN_BLUE));
++            }
++#endif
++         }
++   }
++ TRY_DONE:
++   (void)0;
++}
++
++/*
++ * Off HDCP
++ */
++void hdcp_off(tda_instance *this) {
++
++   int err=0;
++
++   if (this->tda.hdcp_status != HDCP_IS_NOT_INSTALLED) { /* check HDCP is installed ... */
++
++         if (this->tda.hdcp_enable) { /* but no more requested */
++            TRY(tmdlHdmiTxSetHdcp(this->tda.instance,False)); /* switch if off */
++         }
++   }
++ TRY_DONE:
++   (void)0;
++}
++
++/*
++ * Run video
++ */
++void show_video(tda_instance *this) {
++
++   int err=0;
++
++   if (this->tda.rx_device_active) { /* check RxSens */
++      if (this->tda.hot_plug_detect == TMDL_HDMITX_HOTPLUG_ACTIVE) { /* should be useless, but legacy... */
++         if (this->tda.power == tmPowerOn) { /* check CEC or DSS didn't switch it off */
++            if (this->tda.src_address != 0xFFFF) { /* check EDID has been received */
++				hdcp_off(this);
++               TRY(tmdlHdmiTxSetInputOutput(this->tda.instance,         \
++                                            this->tda.setio.video_in,   \
++                                            this->tda.setio.video_out,  \
++                                            this->tda.setio.audio_in,   \
++                                            this->tda.setio.sink));
++               hdcp_on(this);
++               /*
++                 Mind that SetInputOutput disable the blue color matrix settings of tmdlHdmiTxSetBScreen ...
++                 so put tmdlHdmiTxSetBScreen (or hdcp_on) always after
++               */
++            }
++         }
++      }
++   }
++
++ TRY_DONE:
++   (void)0;
++}
++
++/*
++ *  TDA interrupt polling
++ */
++static void interrupt_polling(struct work_struct *dummy)
++{
++   tda_instance *this=&our_instance;
++   int err=0;
++
++   /* Tx part */
++   TRY(tmdlHdmiTxHandleInterrupt(this->tda.instance));
++
++   /* CEC part */
++   if (this->driver.cec_callback) this->driver.cec_callback(dummy);
++
++   /* FIX : IT anti debounce */
++   TRY(tmdlHdmiTxHandleInterrupt(this->tda.instance));
++
++ TRY_DONE:
++
++   /* setup next polling */
++#ifndef IRQ
++   mod_timer(&this->driver.no_irq_timer,jiffies + ( CHECK_EVERY_XX_MS * HZ / 1000 ));
++#endif
++
++   (void)0;
++}
++
++/*
++ *  TDA interrupt polling
++ */
++static void hdcp_check(struct work_struct *dummy)
++{
++   int err=0;
++   tda_instance *this=&our_instance;
++   tmdlHdmiTxHdcpCheck_t hdcp_status;
++
++   down(&this->driver.sem);
++
++   if (this->tda.hdcp_status == HDCP_IS_NOT_INSTALLED) goto TRY_DONE;
++
++   TRY(tmdlHdmiTxHdcpCheck(this->tda.instance,HDCP_CHECK_EVERY_MS));
++   TRY(tmdlHdmiTxGetHdcpState(this->tda.instance, &hdcp_status));
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++   if (this->tda.hdcp_status != hdcp_status) {
++      LOG(KERN_INFO,"HDCP status:%s\n",tda_spy_hdcp_status(hdcp_status));
++      this->tda.hdcp_status = hdcp_status;
++   }
++#endif
++#ifdef HDCP_TEST
++   /* TEST */
++   if (test++>500) {
++      test=0;
++      this->tda.hdcp_enable=1-this->tda.hdcp_enable;
++      printk("TEST hdcp:%d\n",this->tda.hdcp_enable);
++      if (this->tda.rx_device_active) { /* check RxSens */
++         if (this->tda.hot_plug_detect == TMDL_HDMITX_HOTPLUG_ACTIVE) { /* should be useless, but legacy... */
++            if (this->tda.power == tmPowerOn) { /* check CEC didn't switch it off */
++               if (this->tda.src_address != 0xFFFF) { /* check EDID has been received */
++                  hdcp_off(this);
++                  hdcp_on(this);				  
++               }
++            }
++         }
++      }
++   }
++#endif
++
++ TRY_DONE:
++
++   /* setup next polling */
++   mod_timer(&this->driver.hdcp_check,jiffies + ( HDCP_CHECK_EVERY_MS * HZ / 1000 ));
++
++   up(&this->driver.sem);
++}
++
++void register_cec_interrupt(cec_callback_t fct)
++{
++   tda_instance *this=&our_instance;
++
++   this->driver.cec_callback = fct;
++}
++EXPORT_SYMBOL(register_cec_interrupt);
++
++void unregister_cec_interrupt(void)
++{
++   tda_instance *this=&our_instance;
++
++   this->driver.cec_callback = NULL;
++}
++EXPORT_SYMBOL(unregister_cec_interrupt);
++
++static DECLARE_WORK(wq_irq, interrupt_polling);
++void polling_timeout(unsigned long arg)
++{
++   /* derefered because ATOMIC context of timer does not support I2C_transfert */
++   schedule_work(&wq_irq);
++}
++
++static DECLARE_WORK(wq_hdcp, hdcp_check);
++void hdcp_check_timeout(unsigned long arg)
++{
++   /* derefered because ATOMIC context of timer does not support I2C_transfert */
++   schedule_work(&wq_hdcp);
++}
++
++#ifdef IRQ
++/*
++ *  TDA irq
++ */
++static irqreturn_t tda_irq(int irq, void *_udc)
++{
++
++   /* do it now */
++   schedule_work(&wq_irq);
++
++   return IRQ_HANDLED;
++}
++#endif
++
++/*
++ *  TDA callback
++ */
++static void eventCallbackTx(tmdlHdmiTxEvent_t event)
++{
++   tda_instance *this=&our_instance;
++   int err=0;
++   unsigned short new_addr;
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++   tda_hdcp_fail hdcp_fail;
++#endif
++
++   this->tda.event=event;
++   if (TMDL_HDMITX_HDCP_INACTIVE != event) {
++      printk(KERN_INFO "hdmi %s\n",tda_spy_event(event));
++   }
++
++   switch (event) {
++   case TMDL_HDMITX_EDID_RECEIVED:
++      TRY(tmdlHdmiTxGetEdidSourceAddress(this->tda.instance,        \
++                                         &new_addr));
++      LOG(KERN_INFO,"phy.@:%x\n",new_addr);
++      /*       if (this->tda.src_address == new_addr) { */
++      /*          break; */
++      /*       } */
++      this->tda.src_address = new_addr;
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++      tda_spy(this->param.verbose>1);
++#endif
++      /* 
++         Customer may add stuff to analyse EDID (see tda_spy())
++         and select automatically some video/audio settings.
++         By default, let go on with next case and activate
++         default video/audio settings with tmdlHdmiTxSetInputOutput()
++      */
++
++      TRY(tmdlHdmiTxGetEdidSinkType(this->tda.instance,     \
++                                    &this->tda.setio.sink));
++      if (TMDL_HDMITX_SINK_HDMI != this->tda.setio.sink) {
++         printk(KERN_INFO "/!\\ CAUTION /!\\ sink is not HDMI but %s\n",tda_spy_sink(this->tda.setio.sink));
++      }
++      
++      msleep(100);
++      /*
++        /!\ WARNING /!                                              \
++        the core driver does not send any HPD nor RXSENS when HDMI was plugged after at boot time
++        and only EDID_RECEIVED is send, so rx_device_active shall be forced now.
++        Do not skip the next case nor add any break here please
++      */
++   case TMDL_HDMITX_RX_DEVICE_ACTIVE: /* TV is ready to receive */
++      this->tda.rx_device_active = 1;
++      show_video(this);
++      break;
++   case TMDL_HDMITX_RX_DEVICE_INACTIVE: /* TV is ignoring the source */
++      this->tda.rx_device_active = 0;
++      break;
++   case TMDL_HDMITX_HPD_ACTIVE: /* HDMI is so funny u can get RxSens without being plugged !!! */
++      this->tda.hot_plug_detect = TMDL_HDMITX_HOTPLUG_ACTIVE;
++      show_video(this);
++      break;
++   case TMDL_HDMITX_HPD_INACTIVE: /* unplug */
++      this->tda.hot_plug_detect = TMDL_HDMITX_HOTPLUG_INACTIVE;
++      this->tda.src_address = 0xFFFF;
++      break;
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++   case TMDL_HDMITX_HDCP_INACTIVE: /* HDCP drops off */
++      tmdlHdmiTxGetHdcpFailStatus(this->tda.instance, \
++                                  &hdcp_fail, \
++                                  &this->tda.hdcp_raw_status);
++      if (this->tda.hdcp_fail != hdcp_fail) {
++         if (this->tda.hdcp_fail) {
++            LOG(KERN_INFO,"%s (%d)\n",tda_spy_hsdc_fail_status(this->tda.hdcp_fail),this->tda.hdcp_raw_status);
++         }
++         this->tda.hdcp_fail = hdcp_fail;
++         tmdlHdmiTxSetBScreen(this->tda.instance,TMDL_HDMITX_PATTERN_BLUE);
++      }
++      break;
++   case TMDL_HDMITX_RX_KEYS_RECEIVED: /* end of HDCP authentification */
++      if (!this->tda.setup.simplayHd) {
++         tmdlHdmiTxRemoveBScreen(this->tda.instance);
++      }
++      break;
++#endif
++   default:
++      break;
++   }
++
++   this->driver.poll_done=true;
++   wake_up_interruptible(&this->driver.wait);
++   
++ TRY_DONE:
++   (void)0;
++}
++
++/*
++ *  hdmi Tx init
++ */
++static int hdmi_tx_init(tda_instance *this)
++{
++   int err=0;
++
++   LOG(KERN_INFO,"called\n");
++
++
++   /*Initialize HDMI Transmiter*/
++   TRY(tmdlHdmiTxOpen(&this->tda.instance));
++   /* Register the HDMI TX events callbacks */
++   TRY(tmdlHdmiTxRegisterCallbacks(this->tda.instance,(ptmdlHdmiTxCallback_t)eventCallbackTx));
++   /* EnableEvent, all by default */
++   TRY(tmdlHdmiTxEnableEvent(this->tda.instance,TMDL_HDMITX_HDCP_ACTIVE));
++   TRY(tmdlHdmiTxEnableEvent(this->tda.instance,TMDL_HDMITX_HDCP_INACTIVE));
++   TRY(tmdlHdmiTxEnableEvent(this->tda.instance,TMDL_HDMITX_HPD_ACTIVE));
++   TRY(tmdlHdmiTxEnableEvent(this->tda.instance,TMDL_HDMITX_HPD_INACTIVE));
++   TRY(tmdlHdmiTxEnableEvent(this->tda.instance,TMDL_HDMITX_RX_KEYS_RECEIVED));
++   TRY(tmdlHdmiTxEnableEvent(this->tda.instance,TMDL_HDMITX_RX_DEVICE_ACTIVE));
++   TRY(tmdlHdmiTxEnableEvent(this->tda.instance,TMDL_HDMITX_RX_DEVICE_INACTIVE));
++   TRY(tmdlHdmiTxEnableEvent(this->tda.instance,TMDL_HDMITX_EDID_RECEIVED));
++
++   /* Size of the application EDID buffer */
++   this->tda.setup.edidBufferSize=EDID_BLOCK_COUNT * EDID_BLOCK_SIZE;
++   /* Buffer to store the application EDID data */
++   this->tda.setup.pEdidBuffer=this->tda.raw_edid;
++   /* To Enable/disable repeater feature, nor relevant here */
++   this->tda.setup.repeaterEnable=false;
++   /* To enable/disable simplayHD feature: blue screen when not authenticated */
++#ifdef SIMPLAYHD
++   this->tda.setup.simplayHd=(this->tda.hdcp_enable?true:false);
++#else
++   this->tda.setup.simplayHd=false;
++#endif
++
++   /* Provides HDMI TX instance configuration */
++   TRY(tmdlHdmiTxInstanceSetup(this->tda.instance,&this->tda.setup));
++   /* Get IC version */
++   TRY(tmdlHdmiTxGetCapabilities(&this->tda.capabilities));
++
++   /* Main settings */
++   this->tda.setio.video_out.mode = TMDL_HDMITX_VOUTMODE_RGB444;
++   this->tda.setio.video_out.colorDepth = TMDL_HDMITX_COLORDEPTH_24;
++#ifdef TMFL_TDA19989
++   this->tda.setio.video_out.dviVqr = TMDL_HDMITX_VQR_DEFAULT; /* Use HDMI rules for DVI output */
++#endif
++   /*    this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_31_1920x1080p_50Hz; */
++   /*    this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_PC_640x480p_60Hz; */
++   /*    this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_PC_640x480p_72Hz; */
++   // this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_04_1280x720p_60Hz; 
++   /*    this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_19_1280x720p_50Hz; */
++   this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_02_720x480p_60Hz;
++
++   this->tda.setio.video_in.mode = TMDL_HDMITX_VINMODE_RGB444;
++   /*    this->tda.setio.video_in.mode = TMDL_HDMITX_VINMODE_CCIR656; */
++   /*    this->tda.setio.video_in.mode = TMDL_HDMITX_VINMODE_YUV422; */
++   this->tda.setio.video_in.format = this->tda.setio.video_out.format;
++   this->tda.setio.video_in.pixelRate = TMDL_HDMITX_PIXRATE_SINGLE;
++   this->tda.setio.video_in.syncSource = TMDL_HDMITX_SYNCSRC_EXT_VS; /* we use HS,VS as synchronisation source */
++
++    this->tda.setio.audio_in.format            = TMDL_HDMITX_AFMT_I2S;         /* audio I2S is coming in */
++    this->tda.setio.audio_in.rate              = TMDL_HDMITX_AFS_48K;          /* audio sampling rate */
++    this->tda.setio.audio_in.i2sFormat         = TMDL_HDMITX_I2SFOR_PHILIPS_L; /* I2S format of the audio input */
++    this->tda.setio.audio_in.i2sQualifier      = TMDL_HDMITX_I2SQ_32BITS;      /* we use a 32 bits bus */
++    this->tda.setio.audio_in.dstRate           = TMDL_HDMITX_DSTRATE_SINGLE;   /* not relevant here */
++    this->tda.setio.audio_in.channelAllocation = 0;                            /* audio channel allocation (Ref to CEA-861D p85) */
++    /* set default channel status */
++    this->tda.setio.audio_in.channelStatus.PcmIdentification = TMDL_HDMITX_AUDIO_DATA_PCM;
++    this->tda.setio.audio_in.channelStatus.CopyrightInfo =     TMDL_HDMITX_CSCOPYRIGHT_PROTECTED;
++    this->tda.setio.audio_in.channelStatus.FormatInfo =        TMDL_HDMITX_CSFI_PCM_2CHAN_NO_PRE;
++    this->tda.setio.audio_in.channelStatus.categoryCode =      0x00;
++    this->tda.setio.audio_in.channelStatus.clockAccuracy =     TMDL_HDMITX_CSCLK_LEVEL_II;
++    this->tda.setio.audio_in.channelStatus.maxWordLength =     TMDL_HDMITX_CSMAX_LENGTH_20;
++    this->tda.setio.audio_in.channelStatus.wordLength =        TMDL_HDMITX_CSWORD_DEFAULT;
++    this->tda.setio.audio_in.channelStatus.origSampleFreq =    TMDL_HDMITX_CSOFREQ_NOT_INDICATED;
++
++
++   this->tda.setio.sink = TMDL_HDMITX_SINK_HDMI; /* skip edid reading */
++   /*    this->tda.src_address = 0x1000; /\* debug *\/ */
++   this->tda.src_address = NO_PHY_ADDR; /* it's unref */
++
++ TRY_DONE:
++   return err;
++}
++
++void reset_hdmi(int hdcp_module)
++{
++   tda_instance *this=&our_instance;
++   int err=0;
++
++   down(&this->driver.sem);
++
++   /* PATCH because of SetPowerState that calls SetHdcp that has just been removed by nwolc :( */
++   if (hdcp_module==2) {
++      tmdlHdmiTxSetHdcp(this->tda.instance,0);
++      goto TRY_DONE;
++   }
++
++   TRY(tmdlHdmiTxSetPowerState(this->tda.instance,tmPowerStandby));
++   tmdlHdmiTxClose(this->tda.instance);
++
++   /* reset */
++   this->tda.hdcp_enable = (hdcp_module?1:0);
++   hdmi_tx_init(this);
++   /* recover previous power state */
++   TRY(tmdlHdmiTxSetPowerState(this->tda.instance,this->tda.power));
++   tmdlHdmiTxGetHPDStatus(this->tda.instance,&this->tda.hot_plug_detect); /* check if activ for timer */
++#ifndef USER_SET_INPUT_OUTPUT
++   show_video(this);
++#endif
++
++   /* wake up or shut down hdcp checking */
++   if (hdcp_module) {
++      this->driver.hdcp_check.expires = jiffies +  ( HDCP_CHECK_EVERY_MS * HZ / 1000 );
++      add_timer(&this->driver.hdcp_check);
++      this->tda.hdcp_status = TMDL_HDMITX_HDCP_CHECK_NOT_STARTED;
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++      tmdlHdmiTxSetBScreen(this->tda.instance,TMDL_HDMITX_PATTERN_BLUE);
++#endif
++   }
++   else {
++      del_timer(&this->driver.hdcp_check);
++      this->tda.hdcp_status = HDCP_IS_NOT_INSTALLED; 
++   }
++
++ TRY_DONE:
++   up(&this->driver.sem);
++}
++EXPORT_SYMBOL(reset_hdmi);
++
++/*
++ *  
++ */
++short edid_phy_addr(void)
++{
++   tda_instance *this=&our_instance;
++
++   return this->tda.src_address;
++}
++EXPORT_SYMBOL(edid_phy_addr);
++
++/*
++ *  
++ */
++tda_power get_hdmi_status(void)
++{ 
++   tda_instance *this=&our_instance;
++   
++   return this->tda.power;
++}
++EXPORT_SYMBOL(get_hdmi_status);
++
++/*
++ *  
++ */
++tda_power get_hpd_status(void)
++{ 
++   tda_instance *this=&our_instance;
++   
++   return (this->tda.hot_plug_detect == TMDL_HDMITX_HOTPLUG_ACTIVE);
++}
++EXPORT_SYMBOL(get_hpd_status);
++
++/*
++ *  
++ */
++int edid_received(void)
++{ 
++   tda_instance *this=&our_instance;
++   
++   return (this->tda.event == TMDL_HDMITX_EDID_RECEIVED);
++}
++EXPORT_SYMBOL(edid_received);
++
++/*
++ *  
++ */
++int hdmi_enable(void)
++{
++   tda_instance *this=&our_instance;
++   int err=0;
++
++   LOG(KERN_INFO,"called\n");
++
++   down(&this->driver.sem);
++
++   this->driver.omap_dss_hdmi_panel = true;
++
++   this->tda.power = tmPowerOn;
++   TRY(tmdlHdmiTxSetPowerState(this->tda.instance,this->tda.power));
++   if (err==TM_ERR_NO_RESOURCES) {
++      LOG(KERN_INFO,"Busy...\n");
++      TRY(tmdlHdmiTxHandleInterrupt(this->tda.instance));
++      TRY(tmdlHdmiTxHandleInterrupt(this->tda.instance));
++      TRY(tmdlHdmiTxHandleInterrupt(this->tda.instance));
++   }
++   tmdlHdmiTxGetHPDStatus(this->tda.instance,&this->tda.hot_plug_detect);
++   show_video(this);
++   
++ TRY_DONE:
++   up(&this->driver.sem);
++   return err;
++}
++EXPORT_SYMBOL(hdmi_enable);
++
++/*
++ *  
++ */
++int hdmi_disable(int event_tracking)
++{ 
++   tda_instance *this=&our_instance;
++   int err=0;
++   
++   LOG(KERN_INFO,"called\n");
++
++   down(&this->driver.sem);
++   this->tda.power = (event_tracking?tmPowerSuspend:tmPowerStandby);
++   TRY(tmdlHdmiTxSetPowerState(this->tda.instance,this->tda.power));
++
++ TRY_DONE:
++   this->driver.omap_dss_hdmi_panel = false;
++   up(&this->driver.sem);
++   return err;
++}
++EXPORT_SYMBOL(hdmi_disable);
++
++/*
++ *
++ * ENTRY POINTS
++ * ------------
++ * LEVEL 3
++ *
++ * - 
++ *
++ */
++
++#ifdef ANDROID_DSS
++/*
++ *  DSS driver :: probe
++ */
++static int hdmi_panel_probe(struct omap_dss_device *dssdev)
++{
++   tda_instance *this=&our_instance;
++
++   LOG(KERN_INFO," called\n");
++
++   /* 	OMAP_DSS_LCD_IVS		= 1<<0, */
++   /* 	OMAP_DSS_LCD_IHS		= 1<<1, */
++   /* 	OMAP_DSS_LCD_IPC		= 1<<2, */
++   /* 	OMAP_DSS_LCD_IEO		= 1<<3, */
++   /* 	OMAP_DSS_LCD_RF			= 1<<4, */
++   /* 	OMAP_DSS_LCD_ONOFF		= 1<<5, */
++   /* 	OMAP_DSS_LCD_TFT		= 1<<20, */
++
++   dssdev->panel.config = OMAP_DSS_LCD_ONOFF | OMAP_DSS_LCD_IPC |  \
++      OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS;
++   dssdev->panel.timings = video_1280x720at50Hz_panel_timings;
++   (void)video_1280x720at60Hz_panel_timings;
++   (void)video_720x480at60Hz_panel_timings;
++   (void)video_1280x720at50Hz_panel_timings;
++   (void)video_800x480at60Hz_panel_timings;
++   (void)video_1280x720at50Hz_panel_timings;
++   (void)video_1920x1080at50Hz_panel_timings;
++   (void)video_640x480at72Hz_panel_timings;
++   (void)video_640x480at60Hz_panel_timings;
++
++   return 0;
++}
++
++/*
++ *  DSS driver :: enable
++ */
++static void hdmi_panel_remove(struct omap_dss_device *dssdev)
++{
++}
++
++/*
++ *  DSS driver :: enable
++ */
++static int hdmi_panel_enable(struct omap_dss_device *dssdev)
++{
++   int r = 0;
++
++   if (dssdev->platform_enable)
++      r = dssdev->platform_enable(dssdev);
++   
++   if (r)
++      goto ERROR0;
++
++   r = hdmi_enable();
++   if (r)
++      goto ERROR0;
++   /* wait couple of vsyncs until enabling the LCD */
++   msleep(50);
++
++   return 0;
++ ERROR0:
++   return r;
++}
++
++/*
++ *  DSS driver :: disable
++ */
++static void hdmi_panel_disable(struct omap_dss_device *dssdev)
++{
++   hdmi_disable(1); /* keep HPD int actif */
++
++   /* wait couple of vsyncs until enabling the hdmi */
++   msleep(50);
++
++   if (dssdev->platform_disable)
++      dssdev->platform_disable(dssdev);
++}
++
++/*
++ *  DSS driver :: suspend
++ */
++static int hdmi_panel_suspend(struct omap_dss_device *dssdev)
++{
++   hdmi_panel_disable(dssdev);
++   return 0;
++}
++
++/*
++ *  DSS driver :: resume
++ */
++static int hdmi_panel_resume(struct omap_dss_device *dssdev)
++{
++   return hdmi_panel_enable(dssdev);
++}
++
++/*
++ *  DSS driver (frontend with omapzoom)
++ *  -----------------------------------
++ */
++static struct omap_dss_driver hdmi_driver = {
++   .probe = hdmi_panel_probe,
++   .remove = hdmi_panel_remove,
++   .enable = hdmi_panel_enable,
++   .disable = hdmi_panel_disable,
++   .suspend = hdmi_panel_suspend,
++   .resume = hdmi_panel_resume,
++   .driver = {
++      .name = "hdmi_panel",
++      .owner = THIS_MODULE,
++   }
++};
++#endif
++
++/*
++ *  ioctl driver :: opening
++ */
++
++static int this_cdev_open(struct inode *pInode, struct file *pFile)
++{
++   tda_instance *this;
++   int minor=iminor(pInode);
++
++   if(minor >= MAX_MINOR) {
++      printk(KERN_ERR "hdmitx:%s:only one tda can be open\n",__func__);
++      return -EINVAL;
++   }
++
++   if ((pFile->private_data != NULL) && (pFile->private_data != &our_instance)) {
++      printk(KERN_ERR "hdmitx:%s:pFile missmatch\n",__func__);
++   }
++   this = pFile->private_data = &our_instance;
++   down(&this->driver.sem);
++
++   LOG(KERN_INFO,"major:%d minor:%d user:%d\n", imajor(pInode), iminor(pInode), this->driver.user_counter);
++
++   if ((this->driver.user_counter++) && (this->driver.minor == minor)) {
++      /* init already done */
++      up(&this->driver.sem);
++      return 0;
++   }
++   this->driver.minor = minor;
++
++
++   up(&this->driver.sem);
++   return 0;
++}
++
++/*
++ *  ioctl driver :: ioctl
++ */
++static int this_cdev_ioctl(struct inode *pInode, struct file *pFile, unsigned int cmd, unsigned long arg)
++{
++   tda_instance* this = pFile->private_data;
++   int err=0;
++
++   LOG(KERN_INFO,":%s\n",tda_ioctl(_IOC_NR(cmd)));
++
++   BUG_ON(this->driver.minor!=iminor(pInode));
++   if (_IOC_TYPE(cmd) != TDA_IOCTL_BASE) {
++      printk(KERN_INFO "hdmitx:%s:unknown ioctl type: %x\n",__func__,_IOC_TYPE(cmd));
++      return -ENOIOCTLCMD;
++   }
++
++   if (_IOC_DIR(cmd) & _IOC_READ) 
++      err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd)) || !arg;
++   else if (_IOC_DIR(cmd) & _IOC_WRITE)
++      err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)) || !arg;
++   if (err) {
++      printk(KERN_ERR "hdmitx:%s:argument access denied (check address vs value)\n",__func__);
++      printk(KERN_ERR "_IOC_DIR:%d arg:%lx\n",_IOC_DIR(cmd),arg);
++      return -EFAULT;
++   }
++   
++   down(&this->driver.sem);
++
++   /* Check DevLib consistancy here */
++
++   switch ( _IOC_NR(cmd) )
++      {
++      case TDA_VERBOSE_ON_CMD:
++         {
++            this->param.verbose=1;
++            printk(KERN_INFO "hdmitx:verbose on\n");
++            break;
++         }
++
++      case TDA_VERBOSE_OFF_CMD:
++         {
++            printk(KERN_INFO "hdmitx:verbose off\n");
++            this->param.verbose=0;
++            break;
++         }
++
++      case TDA_BYEBYE_CMD:
++         {
++            LOG(KERN_INFO,"release event handeling request\n");
++            this->tda.event=RELEASE;
++            this->driver.poll_done = true;
++            wake_up_interruptible(&this->driver.wait);
++            break;
++         }
++
++      case TDA_GET_SW_VERSION_CMD:
++         {
++            TRY(tmdlHdmiTxGetSWVersion(&this->tda.version));
++            BUG_ON(copy_to_user((tda_version*)arg,&this->tda.version,sizeof(tda_version)) != 0);
++            break;
++         }
++
++      case TDA_SET_POWER_CMD:
++         {
++            if (this->driver.omap_dss_hdmi_panel) {
++               /* DSS uses HDMI panel => do not switch the power through the ioctl, this will be done be DSS */
++            }
++            else {
++               BUG_ON(copy_from_user(&this->tda.power,(tda_power*)arg,sizeof(tda_power)) != 0);
++               TRY(tmdlHdmiTxSetPowerState(this->tda.instance,this->tda.power));
++            }
++            break;
++         }
++
++      case TDA_GET_POWER_CMD:
++         {
++            TRY(tmdlHdmiTxGetPowerState(this->tda.instance, \
++                                        &this->tda.power));
++            BUG_ON(copy_to_user((tda_power*)arg,&this->tda.power,sizeof(tda_power)) != 0);
++            break;
++         }
++
++      case TDA_SETUP_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.setup,(tda_setup_info*)arg,sizeof(tda_setup_info)) != 0);
++            TRY(tmdlHdmiTxInstanceSetup(this->tda.instance, \
++                                        &this->tda.setup));
++            break;
++         }
++
++      case TDA_GET_SETUP_CMD:
++         {
++            TRY(tmdlHdmiTxGetInstanceSetup(this->tda.instance, \
++                                           &this->tda.setup));
++            BUG_ON(copy_to_user((tda_setup*)arg,&this->tda.setup,sizeof(tda_setup)) != 0);
++            break;
++         }
++
++      case TDA_WAIT_EVENT_CMD:
++         {
++            this->driver.poll_done = false;
++            up(&this->driver.sem);
++            if (wait_event_interruptible(this->driver.wait,this->driver.poll_done)) return -ERESTARTSYS;
++            down(&this->driver.sem);
++            BUG_ON(copy_to_user((tda_event*)arg,&this->tda.event,sizeof(tda_event)) != 0);
++            break;
++         }
++
++      case TDA_ENABLE_EVENT_CMD:
++         {
++            tmdlHdmiTxEvent_t event;
++            BUG_ON(copy_from_user(&event,(tmdlHdmiTxEvent_t*)arg,sizeof(tmdlHdmiTxEvent_t)) != 0);
++            TRY(tmdlHdmiTxEnableEvent(this->tda.instance,event));
++            break;
++         }
++
++      case TDA_DISABLE_EVENT_CMD:
++         {
++            tmdlHdmiTxEvent_t event;
++            BUG_ON(copy_from_user(&event,(tmdlHdmiTxEvent_t*)arg,sizeof(tmdlHdmiTxEvent_t)) != 0);
++            TRY(tmdlHdmiTxDisableEvent(this->tda.instance,event));
++            break;
++         }
++
++      case TDA_GET_VIDEO_SPEC_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.video_fmt,(tda_video_format*)arg,sizeof(tda_video_format)) != 0);
++            TRY(tmdlHdmiTxGetVideoFormatSpecs(this->tda.instance, \
++                                              this->tda.video_fmt.id, \
++                                              &this->tda.video_fmt.spec));
++            BUG_ON(copy_to_user((tda_video_format*)arg,&this->tda.video_fmt,sizeof(tda_video_format)) != 0);
++            break;
++         }
++
++      case TDA_SET_INPUT_OUTPUT_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.setio,(tda_set_in_out*)arg,sizeof(tda_set_in_out)) != 0);
++
++            /*             TRY(tmdlHdmiTxSetInputOutput(this->tda.instance, \ */
++            /*                                          this->tda.setio.video_in, \ */
++            /*                                          this->tda.setio.video_out, \ */
++            /*                                          this->tda.setio.audio_in, \ */
++            /*                                          this->tda.setio.sink)); */
++            break;
++         }
++
++      case TDA_SET_AUDIO_INPUT_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.setio.audio_in,(tda_set_audio_in*)arg,sizeof(tda_set_audio_in)) != 0);
++            TRY(tmdlHdmiTxSetAudioInput(this->tda.instance, \
++                                        this->tda.setio.audio_in, \
++                                        this->tda.setio.sink));
++            break;
++         }
++
++      case TDA_SET_VIDEO_INFOFRAME_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.video_infoframe,(tda_video_infoframe*)arg,sizeof(tda_video_infoframe)) != 0);
++            TRY(tmdlHdmiTxSetVideoInfoframe(this->tda.instance, \
++                                            this->tda.video_infoframe.enable, \
++                                            &this->tda.video_infoframe.data));
++            break;
++         }
++
++      case TDA_SET_AUDIO_INFOFRAME_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.audio_infoframe,(tda_audio_infoframe*)arg,sizeof(tda_audio_infoframe)) != 0);
++            TRY(tmdlHdmiTxSetAudioInfoframe(this->tda.instance, \
++                                            this->tda.audio_infoframe.enable, \
++                                            &this->tda.audio_infoframe.data));
++            break;
++         }
++
++      case TDA_SET_ACP_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.acp,(tda_acp*)arg,sizeof(tda_acp)) != 0);
++            TRY(tmdlHdmiTxSetACPPacket(this->tda.instance, \
++                                       this->tda.acp.enable, \
++                                       &this->tda.acp.data));
++            break;
++         }
++
++      case TDA_SET_GCP_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.gcp,(tda_gcp*)arg,sizeof(tda_gcp)) != 0);
++            TRY(tmdlHdmiTxSetGeneralControlPacket(this->tda.instance, \
++                                                  this->tda.gcp.enable, \
++                                                  &this->tda.gcp.data));
++            break;
++         }
++
++      case TDA_SET_ISRC1_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.isrc1,(tda_isrc1*)arg,sizeof(tda_isrc1)) != 0);
++            TRY(tmdlHdmiTxSetISRC1Packet(this->tda.instance, \
++                                         this->tda.isrc1.enable, \
++                                         &this->tda.isrc1.data));
++            break;
++         }
++
++      case TDA_SET_MPS_INFOFRAME_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.mps_infoframe,(tda_mps_infoframe*)arg,sizeof(tda_mps_infoframe)) != 0);
++            TRY(tmdlHdmiTxSetMPSInfoframe(this->tda.instance, \
++                                          this->tda.mps_infoframe.enable, \
++                                          &this->tda.mps_infoframe.data));
++            break;
++         }
++
++      case TDA_SET_SPD_INFOFRAME_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.spd_infoframe,(tda_spd_infoframe*)arg,sizeof(tda_spd_infoframe)) != 0);
++            TRY(tmdlHdmiTxSetSpdInfoframe(this->tda.instance, \
++                                          this->tda.spd_infoframe.enable, \
++                                          &this->tda.spd_infoframe.data));
++            break;
++         }
++
++      case TDA_SET_VS_INFOFRAME_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.vs_infoframe,(tda_vs_infoframe*)arg,sizeof(tda_vs_infoframe)) != 0);
++            TRY(tmdlHdmiTxSetVsInfoframe(this->tda.instance, \
++                                         this->tda.vs_infoframe.enable, \
++                                         &this->tda.vs_infoframe.data));
++            break;
++         }
++
++      case TDA_SET_AUDIO_MUTE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.audio_mute,(bool*)arg,sizeof(bool)) != 0);
++            TRY(tmdlHdmiTxSetAudioMute(this->tda.instance,			\
++                                       this->tda.audio_mute));
++            break;
++         }
++
++      case TDA_RESET_AUDIO_CTS_CMD:
++         {
++            TRY(tmdlHdmiTxResetAudioCts(this->tda.instance));
++            break;
++         }
++
++      case TDA_GET_EDID_STATUS_CMD:
++         {
++            TRY(tmdlHdmiTxGetEdidStatus(this->tda.instance, \
++                                        &this->tda.edid.status, \
++                                        &this->tda.edid.block_count));
++            BUG_ON(copy_to_user((tda_edid*)arg,&this->tda.edid,sizeof(tda_edid)) != 0);
++            break;
++         }
++
++      case TDA_GET_EDID_AUDIO_CAPS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.edid_audio_caps,(tda_edid_audio_caps*)arg,sizeof(tda_edid_audio_caps)) != 0);
++            TRY(tmdlHdmiTxGetEdidAudioCaps(this->tda.instance, \
++                                           this->tda.edid_audio_caps.desc, \
++                                           this->tda.edid_audio_caps.max, \
++                                           &this->tda.edid_audio_caps.written, \
++                                           &this->tda.edid_audio_caps.flags));
++            BUG_ON(copy_to_user((tda_edid_audio_caps*)arg,&this->tda.edid_audio_caps,sizeof(tda_edid_audio_caps)) != 0);
++            break;
++         }
++
++      case TDA_GET_EDID_VIDEO_CAPS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.edid_video_caps,(tda_edid_video_caps*)arg,sizeof(tda_edid_video_caps)) != 0);
++            TRY(tmdlHdmiTxGetEdidVideoCaps(this->tda.instance, \
++                                           this->tda.edid_video_caps.desc, \
++                                           this->tda.edid_video_caps.max, \
++                                           &this->tda.edid_video_caps.written, \
++                                           &this->tda.edid_video_caps.flags));
++            BUG_ON(copy_to_user((tda_edid_video_caps*)arg,&this->tda.edid_video_caps,sizeof(tda_edid_video_caps)) != 0);
++            break;
++         }
++
++      case TDA_GET_EDID_VIDEO_PREF_CMD:
++         {
++            TRY(tmdlHdmiTxGetEdidVideoPreferred(this->tda.instance, \
++                                                &this->tda.edid_video_timings));
++            BUG_ON(copy_to_user((tda_edid_video_timings*)arg,&this->tda.edid_video_timings,sizeof(tda_edid_video_timings)) != 0);
++            break;
++         }
++
++      case TDA_GET_EDID_SINK_TYPE_CMD:
++         {
++            TRY(tmdlHdmiTxGetEdidSinkType(this->tda.instance, \
++                                          &this->tda.setio.sink));
++            BUG_ON(copy_to_user((tda_sink*)arg,&this->tda.setio.sink,sizeof(tda_sink)) != 0);
++            break;
++         }
++
++      case TDA_GET_EDID_SOURCE_ADDRESS_CMD:
++         {
++            TRY(tmdlHdmiTxGetEdidSourceAddress(this->tda.instance, \
++                                               &this->tda.src_address));
++            BUG_ON(copy_to_user((unsigned short*)arg,&this->tda.src_address,sizeof(unsigned short)) != 0);
++            break;
++         }
++
++      case TDA_SET_GAMMUT_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.gammut,(tda_gammut*)arg,sizeof(tda_gammut)) != 0);
++            TRY(tmdlHdmiTxSetGamutPacket(this->tda.instance, \
++                                         this->tda.gammut.enable, \
++                                         &this->tda.gammut.data));
++            break;
++         }
++	 
++      case TDA_GET_EDID_DTD_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.edid_dtd,(tda_edid_dtd*)arg,sizeof(tda_edid_dtd)) != 0);
++            TRY(tmdlHdmiTxGetEdidDetailledTimingDescriptors(this->tda.instance, \
++                                                            this->tda.edid_dtd.desc, \
++                                                            this->tda.edid_dtd.max, \
++                                                            &this->tda.edid_dtd.written));
++            BUG_ON(copy_to_user((tda_edid_dtd*)arg,&this->tda.edid_dtd,sizeof(tda_edid_dtd)) != 0);
++            break;
++         }
++     
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++      case TDA_GET_EDID_MD_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.edid_md,(tda_edid_md*)arg,sizeof(tda_edid_md)) != 0);
++            TRY(tmdlHdmiTxGetEdidMonitorDescriptors(this->tda.instance, \
++                                                    this->tda.edid_md.desc1, \
++                                                    this->tda.edid_md.desc2, \
++                                                    this->tda.edid_md.other, \
++                                                    this->tda.edid_md.max, \
++                                                    &this->tda.edid_md.written));
++            BUG_ON(copy_to_user((tda_edid_md*)arg,&this->tda.edid_md,sizeof(tda_edid_md)) != 0);
++            break;
++         }
++
++      case TDA_GET_EDID_TV_ASPECT_RATIO_CMD:
++         {
++            TRY(tmdlHdmiTxGetEdidTVPictureRatio(this->tda.instance, \
++                                                &this->tda.edid_tv_aspect_ratio));
++            BUG_ON(copy_to_user((tda_edid_tv_aspect_ratio*)arg,&this->tda.edid_tv_aspect_ratio,sizeof(tda_edid_tv_aspect_ratio)) != 0);
++            break;
++         }
++
++      case TDA_GET_EDID_LATENCY_CMD:
++         {
++            TRY(tmdlHdmiTxGetEdidLatencyInfo(this->tda.instance, \
++                                             &this->tda.edid_latency));
++            BUG_ON(copy_to_user((tda_edid_latency*)arg,&this->tda.edid_latency,sizeof(tda_edid_latency)) != 0);
++            break;
++         }
++
++      case TDA_SET_HDCP_CMD:
++         {
++            BUG_ON(copy_from_user(&this->tda.hdcp_enable,(bool*)arg,sizeof(bool)) != 0);
++            break;
++         }
++
++      case TDA_GET_HPD_STATUS_CMD:
++         {
++            tmdlHdmiTxGetHPDStatus(this->tda.instance,&this->tda.hot_plug_detect); 
++            BUG_ON(copy_to_user((tmdlHdmiTxHotPlug_t*)arg,&this->tda.hot_plug_detect,sizeof(tmdlHdmiTxHotPlug_t)) != 0);
++            break;
++         }
++      case TDA_GET_HDCP_STATUS_CMD:
++         {
++            BUG_ON(copy_to_user((tda_edid_latency*)arg,&this->tda.hdcp_status,sizeof(tda_hdcp_status)) != 0);
++            break;
++         }
++#endif
++
++      default:
++         {
++            /* unrecognized ioctl */	
++            printk(KERN_INFO "hdmitx:%s:unknown ioctl number: %x\n",__func__,cmd);
++            up(&this->driver.sem);
++            return -ENOIOCTLCMD;
++         }
++      }
++
++ TRY_DONE:
++   up(&this->driver.sem);
++   return err;
++}
++
++/*
++ *  ioctl driver :: releasing
++ */
++static int this_cdev_release(struct inode *pInode, struct file *pFile)
++{
++   tda_instance* this = pFile->private_data;
++   int minor = iminor(pInode);
++
++   LOG(KERN_INFO,"called\n");
++
++   if(minor >= MAX_MINOR) {
++      LOG(KERN_ERR,"minor too big!\n");
++      return -EINVAL;
++   }
++
++   BUG_ON(this->driver.minor!=iminor(pInode));
++   down(&this->driver.sem);
++
++   this->driver.user_counter--;
++   if(this->driver.user_counter == 0) {
++      pFile->private_data = NULL;
++   }
++   else {
++      LOG(KERN_INFO,"Still %d users pending\n",this->driver.user_counter);
++   }
++
++   up(&this->driver.sem);
++   return 0;
++}
++
++/*
++ *  I2C client :: creation
++ */
++static int this_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++   tda_instance *this=&our_instance;
++   int err=0;
++
++  printk(KERN_ERR "i2c probe called.....\n");
++
++   LOG(KERN_INFO,"called\n");
++
++   /*
++     I2C setup
++   */
++   if (this->driver.i2c_client) {
++      dev_err(&this->driver.i2c_client->dev, "<%s> HDMI Device already created \n",
++              __func__);
++      return -ENODEV;
++   }
++
++   this->driver.i2c_client = client;
++   i2c_set_clientdata(client, this);
++
++   /* I2C ok, then let's startup TDA */
++   err = hdmi_tx_init(this);
++   if (err) goto i2c_out;
++   this->tda.hdcp_enable = 0;
++   /* Standby the HDMI TX instance : this is mandatory for TDA boot up sequence, do not change it */
++   this->tda.power = tmPowerStandby;  /* power start sequence phase 1, see phase 2 */
++   tmdlHdmiTxSetPowerState(this->tda.instance,this->tda.power);
++   /* update HPD */
++   tmdlHdmiTxGetHPDStatus(this->tda.instance,&this->tda.hot_plug_detect);
++
++#ifdef ANDROID_DSS
++   /* probe DSS */
++   err = omap_dss_register_driver(&hdmi_driver);
++#endif
++   if (err) goto i2c_tx_out;
++
++   /* prepare event */
++   this->driver.poll_done = true; /* currently idle */
++   init_waitqueue_head(&this->driver.wait);
++
++#ifdef IRQ
++   if (client->irq > 0) {
++      this->driver.gpio = irq_to_gpio(client->irq);
++   }  else {
++      this->driver.gpio = TDA_IRQ_CALIB;
++   }
++
++   /* FRO calibration */
++   err=gpio_request(this->driver.gpio, "tda998x calibration");
++   if (err < 0) {
++      printk(KERN_ERR "hdmitx:%s:cannot use GPIO %d, err:%d\n",__func__, this->driver.gpio,err);
++      goto i2c_out;
++   }
++   /* turn GPIO into IRQ */
++   gpio_direction_input(this->driver.gpio);
++   msleep(1);
++   
++   err=request_irq(gpio_to_irq(this->driver.gpio), tda_irq, 
++                   IRQF_TRIGGER_FALLING|IRQF_DISABLED, "TDA IRQ", this);
++   if (err <0) {
++      printk(KERN_ERR "hdmitx:%s:Cannot request irq, err:%d\n",__func__,err);
++      gpio_free(this->driver.gpio);
++      goto i2c_out;
++   }
++#else
++   init_timer(&this->driver.no_irq_timer);
++   this->driver.no_irq_timer.function=polling_timeout;
++   this->driver.no_irq_timer.data=0;
++   this->driver.no_irq_timer.expires = jiffies + HZ; /* start polling in one sec */
++   add_timer(&this->driver.no_irq_timer);
++#endif
++
++   /* setup hdcp check timer */
++   init_timer(&this->driver.hdcp_check);
++   this->driver.hdcp_check.function=hdcp_check_timeout;
++   this->driver.hdcp_check.data=0;
++
++   tmdlHdmiTxGetSWVersion(&this->tda.version);
++   printk(KERN_INFO "HDMI TX SW Version:%lu.%lu compatibility:%lu\n",   \
++          this->tda.version.majorVersionNr,\
++          this->tda.version.minorVersionNr,\
++          this->tda.version.compatibilityNr);
++   return 0;
++
++ i2c_tx_out:
++   LOG(KERN_INFO,"tmdlHdmiTx closed\n");
++   /* close DevLib */
++   err=tmdlHdmiTxClose(this->tda.instance);
++
++ i2c_out:
++   LOG(KERN_INFO,"this->driver.i2c_client removed\n");
++   this->driver.i2c_client = NULL;
++
++   return err;
++}
++
++/*
++ *  I2C client :: destroy
++ */
++static int this_i2c_remove(struct i2c_client *client)
++{
++   tda_instance *this=&our_instance;
++   int err=0;
++
++   LOG(KERN_INFO,"called\n");
++
++#ifdef ANDROID_DSS
++   /* unplug DSS */
++   omap_dss_unregister_driver(&hdmi_driver);
++#endif
++
++   /* close DevLib */
++   err=tmdlHdmiTxClose(this->tda.instance);
++
++   if (!client->adapter) {
++      dev_err(&this->driver.i2c_client->dev, "<%s> No HDMI Device \n",
++              __func__);
++      return -ENODEV;
++   }
++   this->driver.i2c_client = NULL;
++
++   return err;
++}
++
++/*
++ *  I2C client driver (backend)
++ *  -----------------
++ */
++static const struct i2c_device_id this_i2c_id[] = {
++   { TX_NAME, 0 },
++   { },
++};
++
++MODULE_DEVICE_TABLE(i2c, this_i2c_id);
++
++static struct i2c_driver this_i2c_driver = {
++   .driver = {
++      .owner = THIS_MODULE,
++      .name = TX_NAME,
++   },
++   .probe = this_i2c_probe,
++   .remove = this_i2c_remove,
++   .id_table = this_i2c_id,
++};
++
++/*
++ *  ioctl driver (userland frontend)
++ *  ------------
++ */
++static struct file_operations this_cdev_fops = {
++ owner:    THIS_MODULE,
++ open:     this_cdev_open,
++ release:  this_cdev_release,
++// ioctl:    this_cdev_ioctl,
++};
++
++/*
++ *  sysfs_attrs
++ *  -----------
++ */
++
++static ssize_t reso_show(struct device *dev,struct device_attribute *attr, char *buf)
++{
++   tda_instance *this=&our_instance;
++
++   return sprintf(buf,"format video %d ( %s )\n", \
++                  this->tda.setio.video_in.format,                  \
++                  tda_spy_vfmt(this->tda.setio.video_in.format));
++}
++
++static ssize_t reso_store(struct device *dev,
++                          struct device_attribute *attr, const char *buf, size_t size)
++{
++   tda_instance *this=&our_instance;
++   int resolution=0;
++
++   sscanf(buf,"%d",&resolution);
++   if (resolution != WITH_FP(this->tda.setio.video_in.format)) {
++      LOG(KERN_INFO,"sys_attr new video format\n from %d:( %s )\n to %d:( %s )\n", \
++          this->tda.setio.video_in.format,                              \
++          tda_spy_vfmt(this->tda.setio.video_in.format),                \
++          resolution,                                                   \
++          tda_spy_vfmt(resolution));
++      this->tda.setio.video_out.format = NO_FP(resolution);
++      this->tda.setio.video_in.format = this->tda.setio.video_out.format;
++      this->tda.setio.video_in.structure3D = (IS_FP(resolution)?TMDL_HDMITX_3D_FRAME_PACKING:TMDL_HDMITX_3D_NONE);
++      
++      if (resolution == 0) {
++         this->tda.power = tmPowerStandby;
++         tmdlHdmiTxSetPowerState(this->tda.instance,this->tda.power);
++      } else {
++         this->tda.power = tmPowerOn;
++         tmdlHdmiTxSetPowerState(this->tda.instance,this->tda.power);
++         show_video(this);
++      }
++   }
++   return 0;
++}
++
++
++static ssize_t audio_show(struct device *dev,struct device_attribute *attr, char *buf)
++{
++   tda_instance *this=&our_instance;
++   printk("Audio Show\n");
++
++   tda_spy_audio(&this->tda.setio.audio_in);
++   return sprintf(buf,"audio format %d - %d - %d - %d - %d - %d\n", \
++                  this->tda.setio.audio_in.format,                  \
++                  this->tda.setio.audio_in.rate,                    \
++                  this->tda.setio.audio_in.i2sFormat,               \
++                  this->tda.setio.audio_in.i2sQualifier,            \
++                  this->tda.setio.audio_in.dstRate,                 \
++                  this->tda.setio.audio_in.channelAllocation);
++}
++
++static ssize_t audio_store(struct device *dev,
++                           struct device_attribute *attr, const char *buf, size_t size)
++{
++   tda_instance *this=&our_instance;
++   char desc_format[]="%d - %d - %d - %d - %d - %d\n";
++   tda_audio_in audio;
++   
++   /*
++     Example:
++
++     adb shell "echo '1 - 1 - 0 - 32 - 0 -' >/sys/hdmitx/audio"
++
++     with :
++     
++     TMDL_HDMITX_AFMT_I2S, 
++     TMDL_HDMITX_AFS_44K, 
++     TMDL_HDMITX_I2SFOR_PHILIPS_L, 
++     TMDL_HDMITX_I2SQ_32BITS,
++     TMDL_HDMITX_DSTRATE_SINGLE, 
++     channel:0
++   */
++
++   memcpy(&audio,&this->tda.setio.audio_in,sizeof(audio));
++   sscanf(buf,desc_format,           \
++          &audio.format,             \
++          &audio.rate,               \
++          &audio.i2sFormat,          \
++          &audio.i2sQualifier,       \
++          &audio.dstRate,            \
++          &audio.channelAllocation);
++
++   if (memcmp(&this->tda.setio.audio_in,&audio,sizeof(audio))) {
++      tda_spy_audio(&this->tda.setio.audio_in);
++      memcpy(&this->tda.setio.audio_in,&audio,sizeof(audio));
++      tmdlHdmiTxSetAudioInput(this->tda.instance,           \
++                              this->tda.setio.audio_in,     \
++                              this->tda.setio.sink);
++   }
++   return 0;
++}
++
++#ifdef I2C_DBG
++static ssize_t i2cR_store(struct device *dev,
++                          struct device_attribute *attr, const char *buf, size_t size)
++{
++   /* 
++      adb shell "echo '2 1' >/sys/hdmitx/i2cR"
++      ... read page 0x02 address 0x01
++   */
++   tda_instance *this=&our_instance;
++   tmHdmiTxobject_t *p;
++   tmErrorCode_t err;
++   unsigned int address;
++   unsigned int value,page;
++   char desc_format[]="%x %x\n";
++   
++   err = checkUnitSetDis(this->tda.instance, &p);
++   sscanf(buf,desc_format,&page,&address);
++   err = getHwRegister(p, SPA(E_SNONE,page,address), (unsigned char *)&value);
++   printk("i2c read %x @ page:%x address:%x\n",value,page,address);
++   return 0;
++}
++
++static ssize_t i2cW_store(struct device *dev,
++                          struct device_attribute *attr, const char *buf, size_t size)
++{
++   /*
++     adb shell "echo '2 1 0x03 2' >/sys/hdmitx/i2cW"
++     ... write 0x02 page 0x02 address 0x01 using mask 0x03
++   */
++
++   tda_instance *this=&our_instance;
++   tmHdmiTxobject_t *p;
++   tmErrorCode_t err;
++   unsigned int page,address,mask,value;
++   char desc_format[]="%x %x %x %x\n";
++   
++   err = checkUnitSetDis(this->tda.instance, &p);
++   sscanf(buf,desc_format,&page,&address,&mask,&value);
++   err = setHwRegisterField(p,SPA(E_SNONE,page,address),mask,value); 
++   printk("i2c write %x @ page:%x address:%x mask:%x\n",value,page,address,mask);
++   return 0;
++}
++#endif
++
++static DEVICE_ATTR(resolution, S_IRUGO|S_IWUSR, reso_show, reso_store);
++static DEVICE_ATTR(audio, S_IRUGO|S_IWUSR, audio_show, audio_store);
++#ifdef I2C_DBG
++static DEVICE_ATTR(i2cW, S_IRUGO|S_IWUSR, NULL, i2cW_store);
++static DEVICE_ATTR(i2cR, S_IRUGO|S_IWUSR, NULL, i2cR_store);
++#endif
++static struct device_attribute *display_sysfs_attrs[] = {
++   &dev_attr_resolution,
++   &dev_attr_audio,
++#ifdef I2C_DBG
++   &dev_attr_i2cW,
++   &dev_attr_i2cR,
++#endif
++   NULL
++};
++
++static int comm_init(void)
++{
++   tda_instance *this=&our_instance;
++   int retval=0;
++   int i=0;	
++   struct device_attribute *attr;
++
++   while ((attr = display_sysfs_attrs[i++]) != NULL) {
++      retval=device_create_file (this->driver.dev,attr);
++      if (retval != 0) {
++         goto out_create_file;
++      }
++   }
++   /* create display sysfs links */
++   retval = sysfs_create_link(NULL,&(this->driver.dev->kobj),HDMITX_NAME);
++   if (retval != 0)
++      goto out_create_link;
++   return retval;
++
++ out_create_link:
++   sysfs_remove_link(NULL, HDMITX_NAME);
++ out_create_file:
++   while ((attr = display_sysfs_attrs[i++]) != NULL) {
++      device_remove_file (this->driver.dev,attr);
++   }
++   return retval;
++}
++
++static void comm_exit(void)
++{
++   tda_instance *this=&our_instance;
++   int i=0;	
++   struct device_attribute *attr;
++   while ((attr = display_sysfs_attrs[i++]) != NULL) {
++      device_remove_file (this->driver.dev,attr);
++   }
++   sysfs_remove_link(NULL, HDMITX_NAME);
++}
++
++/*
++ *  Module :: start up
++ */
++static int __init tx_init(void)
++{
++   tda_instance *this=&our_instance;
++   dev_t dev=0;
++   int err=0;
++
++   /* 
++      general device context
++   */
++   memset(this,0,sizeof(tda_instance)); 
++   this->param.verbose = param_verbose;
++   this->param.major = param_major;
++   this->param.minor = param_minor;
++
++   /* Hello word */
++   printk(KERN_INFO "%s(%s) %d.%d.%d compiled: %s %s %s\n", HDMITX_NAME, TDA_NAME, 
++          TDA_VERSION_MAJOR,
++          TDA_VERSION_MINOR,
++          TDA_VERSION_PATCHLEVEL, 
++          __DATE__, __TIME__, TDA_VERSION_EXTRA);
++   if (this->param.verbose) LOG(KERN_INFO,".verbose mode\n");
++
++   /*
++     plug I2C (backend : Hw interfacing)
++   */
++   err = i2c_add_driver(&this_i2c_driver);
++   if (err < 0) {
++      printk(KERN_ERR "Driver registration failed\n");
++      return -ENODEV;
++   }
++
++   if (this->driver.i2c_client == NULL) {
++      printk(KERN_ERR "this->driver.i2c_client not allocated\n");
++      /* unregister i2c */
++      err = -ENODEV;
++      goto init_out;
++   }
++
++   /*
++     cdev init (userland frontend)
++   */
++
++   /* arbitray range of device numbers */
++   if (this->param.major) {
++      /* user force major number @ insmod */
++      dev = MKDEV(this->param.major, this->param.minor);
++      err = register_chrdev_region(dev,MAX_MINOR,HDMITX_NAME);
++      if (err) {
++         printk(KERN_ERR "unable to register %s, dev=%d %s\n",HDMITX_NAME,dev,ERR_TO_STR(err));
++         goto init_out;
++      }
++   } else {
++      /* fully dynamic major number */
++      err = alloc_chrdev_region(&dev, this->param.minor, MAX_MINOR,HDMITX_NAME);
++      if (err) {
++         printk(KERN_ERR "unable to alloc chrdev region for %s, dev=%d %s\n",HDMITX_NAME,dev,ERR_TO_STR(err));
++         goto init_out;
++      }
++      this->param.major = MAJOR(dev);
++      this->param.minor = MINOR(dev);
++      /*       create_dev("/dev/hdmitx",dev); */
++      LOG(KERN_INFO,"/dev/hdmitx created major:%d minor:%d\n",this->param.major, this->param.minor);
++   }
++
++   cdev_init(this_cdev, &this_cdev_fops);
++   this_cdev->owner = THIS_MODULE;
++
++   this->driver.class = class_create(THIS_MODULE, HDMITX_NAME);
++   if (IS_ERR(this->driver.class)) {
++      printk(KERN_INFO "Error creating mmap device class.\n");
++      err =-EIO;
++      goto init_out;
++   }
++   this->driver.dev=device_create(this->driver.class, NULL /* parent */, dev, NULL, HDMITX_NAME);
++
++   this->driver.devno = dev;
++   err = cdev_add(this_cdev, this->driver.devno, MAX_MINOR);
++   if (err){
++      printk(KERN_INFO "unable to add device for %s, ipp_driver.devno=%d %s\n",HDMITX_NAME,this->driver.devno,ERR_TO_STR(err));
++      device_destroy(this->driver.class,this->driver.devno);
++      class_destroy(this->driver.class);
++      unregister_chrdev_region(this->driver.devno, MAX_MINOR);
++      goto init_out;
++   }   
++
++   /* 
++      general device context
++   */
++   sema_init(&this->driver.sem, 1);
++   
++   /*
++     /!\ WARNING /!                                                     \
++     the startup power sequence SHALL BE standby AND THEN suspend (core driver legacy...)
++     this is the only way to get the TDA idle but with active HDP and RxSens interrupt listening
++   */
++   hdmi_disable(1); /* power start sequence phase 2 */
++
++   /*
++     /!\ WARNING /!                                                     \
++     if HDMI is plugged, the core driver will send HDP nor RXSENS event when beeing powered on !
++     So the Android HDMI service shall start by asking the HDP status using the IOCTL GET_HPD_STATUS 
++   */
++   tmdlHdmiTxGetHPDStatus(this->tda.instance,
++                          &this->tda.hot_plug_detect); /* power start sequence phase 3 */
++   
++   /* sysfs_attrs */
++   comm_init();
++   hdmi_enable();
++   return 0;
++
++ init_out:
++   i2c_del_driver(&this_i2c_driver);
++   return err;
++}
++
++/*
++ *  Module :: shut down
++ */
++static void __exit tx_exit(void)
++{
++   tda_instance *this=&our_instance;
++
++   LOG(KERN_INFO,"called\n");
++
++#ifdef IRQ
++   free_irq(gpio_to_irq(this->driver.gpio), this);
++   gpio_free(this->driver.gpio);
++#else
++   del_timer(&this->driver.no_irq_timer);
++#endif
++
++   del_timer(&this->driver.hdcp_check);
++
++   /* sysfs_attrs */
++   comm_exit();
++
++   /* unregister cdevice */
++   cdev_del(this_cdev); 
++   unregister_chrdev_region(this->driver.devno, MAX_MINOR);
++   
++   /* unregister device */
++   device_destroy(this->driver.class,this->driver.devno);
++   class_destroy(this->driver.class);
++
++   /* unregister i2c */
++   i2c_del_driver(&this_i2c_driver);
++}
++
++
++/*
++ *  Module
++ *  ------
++ */
++late_initcall(tx_init);
++// module_init(tx_init);
++module_exit(tx_exit);
++
++/*
++ *  Disclamer
++ *  ---------
++ */
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Andre Lepine <andre.lepine@nxp.com>");
++MODULE_DESCRIPTION(HDMITX_NAME " driver");
+diff --git a/drivers/video/nxp/tda998x.h b/drivers/video/nxp/tda998x.h
+new file mode 100755
+index 0000000..3759474
+--- /dev/null
++++ b/drivers/video/nxp/tda998x.h
+@@ -0,0 +1,143 @@
++/*****************************************************************************/
++/* Copyright (c) 2009 NXP Semiconductors BV                                  */
++/*                                                                           */
++/* This program is free software; you can redistribute it and/or modify      */
++/* it under the terms of the GNU General Public License as published by      */
++/* the Free Software Foundation, using version 2 of the License.             */
++/*                                                                           */
++/* This program is distributed in the hope that it will be useful,           */
++/* but WITHOUT ANY WARRANTY; without even the implied warranty of            */
++/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the              */
++/* GNU General Public License for more details.                              */
++/*                                                                           */
++/* You should have received a copy of the GNU General Public License         */
++/* along with this program; if not, write to the Free Software               */
++/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307       */
++/* USA.                                                                      */
++/*                                                                           */
++/*****************************************************************************/
++
++#ifndef __tx_h__
++#define __tx_h__
++
++#include "tda998x_ioctl.h"
++
++#define HDMITX_NAME "hdmitx"
++
++#define POLLING_WQ_NAME "TDA_POLLING"
++#define HDCP_CHECK_EVERY_MS 35
++#define CHECK_EVERY_XX_MS 200
++#define OMAP_LCD_GPIO 8
++
++#define TDA_MAJOR 234 /* old-style interval of device numbers */
++#define MAX_MINOR 1 /* 1 minor but 2 access : 1 more for pooling */
++
++
++/* common I2C define with kernel */
++/* should be the same as arch/arm/mach-omap2/board-zoom2.c */
++#define TX_NAME "tda998X"
++#define TDA998X_I2C_SLAVEADDRESS 0x70
++
++#define TDA_IRQ_CALIB 107
++
++#define EDID_BLOCK_COUNT 4
++#define EDID_BLOCK_SIZE 128
++#define MAX_EDID_TRIAL 5
++#define NO_PHY_ADDR 0xFFFF
++
++#define HDCP_IS_NOT_INSTALLED TMDL_HDMITX_HDCP_CHECK_NUM /* ugly is bad ! */ 
++
++#define LOG(type,fmt,args...) {if (this->param.verbose) {printk(type HDMITX_NAME":%s:" fmt, __func__, ## args);}}
++/* not found the kernel "strerror" one! If someone knows, please replace it */
++#define ERR_TO_STR(e)((e == -ENODATA)?"ENODATA, no data available":\
++                      (e == -ENOMEM)? "ENOMEM, no memory available":\
++                      (e == -EINVAL)? "EINVAL, invalid argument":\
++                      (e == -EIO)? "EIO, input/output error":\
++                      (e == -ETIMEDOUT)? "ETIMEOUT, timeout has expired":\
++                      (e == -EBUSY)? "EBUSY, device or resource busy":\
++                      (e == -ENOENT)? "ENOENT, no such file or directory":\
++                      (e == -EACCES)? "EACCES, permission denied":\
++                      (e == 0)?       "":\
++                      "!UNKNOWN!")
++
++#define TRY(fct) { \
++      err=(fct);                                                        \
++      if (err) {                                                        \
++         printk(KERN_ERR "%s returned in %s line %d\n",hdmi_tx_err_string(err),__func__,__LINE__); \
++         goto TRY_DONE;                                                 \
++      }                                                                 \
++   }
++
++typedef void (*cec_callback_t)(struct work_struct *dummy);
++
++typedef struct {
++   /* module params */
++   struct { 
++      int verbose;
++      int major;
++      int minor;
++   } param;
++   /* driver */
++   struct {
++      struct class *class;
++      struct device *dev;
++      int devno;
++      struct i2c_client *i2c_client;
++      struct semaphore sem;
++      int user_counter;
++      int minor;
++      wait_queue_head_t wait;
++      bool poll_done;
++#ifndef IRQ
++      struct timer_list no_irq_timer;
++#endif
++      struct timer_list hdcp_check;
++      cec_callback_t cec_callback;
++      bool omap_dss_hdmi_panel;
++      int gpio;
++   } driver;
++   /* HDMI */
++   struct {
++      int instance;
++      tda_version version;
++      tda_setup setup;
++      tda_power power;
++      tmdlHdmiTxHotPlug_t hot_plug_detect;
++      bool rx_device_active;
++      tda_video_format video_fmt;
++      tda_set_in_out setio;
++      bool audio_mute;
++      tda_video_infoframe video_infoframe;
++      tda_audio_infoframe audio_infoframe;
++      tda_acp acp;
++      tda_gcp gcp;
++      tda_isrc1 isrc1;
++      tda_isrc2 isrc2;
++      tda_gammut gammut;
++      tda_mps_infoframe mps_infoframe;
++      tda_spd_infoframe spd_infoframe;
++      tda_vs_infoframe vs_infoframe;
++      tda_edid edid;
++      tda_edid_dtd edid_dtd;
++      tda_edid_md edid_md;
++      tda_edid_audio_caps edid_audio_caps;
++      tda_edid_video_caps edid_video_caps;
++      tda_edid_video_timings edid_video_timings;
++      tda_edid_tv_aspect_ratio edid_tv_aspect_ratio;
++#ifdef TMFL_TDA19989
++      tda_edid_latency edid_latency;
++#endif
++      unsigned short src_address;
++      unsigned char raw_edid[EDID_BLOCK_COUNT*EDID_BLOCK_SIZE];
++      tda_capabilities capabilities;
++      tda_event event;
++      tda_hdcp_status hdcp_status;
++      bool hdcp_enable;
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++      tda_hdcp_fail hdcp_fail;
++#endif
++      unsigned char hdcp_raw_status;
++   } tda;
++} tda_instance;
++
++#endif /* __tx_h__ */
+diff --git a/drivers/video/nxp/tda998x_cec.c b/drivers/video/nxp/tda998x_cec.c
+new file mode 100755
+index 0000000..90f3536
+--- /dev/null
++++ b/drivers/video/nxp/tda998x_cec.c
+@@ -0,0 +1,2157 @@
++/*****************************************************************************/
++/* Copyright (c) 2009 NXP Semiconductors BV                                  */
++/*                                                                           */
++/* This program is free software; you can redistribute it and/or modify      */
++/* it under the terms of the GNU General Public License as published by      */
++/* the Free Software Foundation, using version 2 of the License.             */
++/*                                                                           */
++/* This program is distributed in the hope that it will be useful,           */
++/* but WITHOUT ANY WARRANTY; without even the implied warranty of            */
++/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the              */
++/* GNU General Public License for more details.                              */
++/*                                                                           */
++/* You should have received a copy of the GNU General Public License         */
++/* along with this program; if not, write to the Free Software               */
++/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307       */
++/* USA.                                                                      */
++/*                                                                           */
++/*****************************************************************************/
++
++#define _cec_c_
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/cdev.h>  
++#include <linux/fs.h>
++#include <linux/ioctl.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/input.h>
++#include <asm/uaccess.h>
++#include <mach/gpio.h>
++
++/* HDMI DevLib */
++#include "tmNxCompId.h"
++#include "tmdlHdmiCEC.h"
++#include "tmdlHdmiCEC_local.h"
++
++/* local */
++#include "tda998x_version.h"
++#include "tda998x_cec.h"
++#include "tda998x_ioctl.h"
++
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/vt_kern.h>
++#include <asm/types.h>
++
++
++/*
++ *
++ * DEFINITION
++ * ----------
++ * LEVEL 0
++ *
++ */
++
++/*
++ *  Global
++ */
++
++MODULE_DEVICE_TABLE(i2c, this_i2c_id);
++static const struct i2c_device_id this_i2c_id[] = {
++   { CEC_NAME, 0 },
++   { },
++};
++cec_instance our_instance;
++static struct cdev our_cdev, *this_cdev=&our_cdev;
++
++#ifdef TWL4030_HACK
++/* AL : hack to bypass keypad */
++struct input_dev *gkp_input;
++extern struct input_dev *get_twm4030_input(void);
++#endif
++
++/*
++ * Dependancies to HdmiTx module
++ */
++
++extern void register_cec_interrupt(cec_callback_t fct); 
++extern void unregister_cec_interrupt(void); 
++extern short edid_phy_addr(void); 
++extern int hdmi_enable(void);
++extern int hdmi_disable(int event_tracking);
++extern cec_power get_hdmi_status(void);
++extern cec_power get_hpd_status(void);
++extern int edid_received(void);
++
++/*
++ *  Module params
++ */
++
++static int param_verbose=0,param_major=0,param_minor=0,param_device=4,param_addr=0xFFFF;
++module_param_named(verbose,param_verbose,int,S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(verbose, "Make the driver verbose");
++module_param_named(major, param_major, int, S_IRUGO);
++MODULE_PARM_DESC(major, "The major number of the device mapper");
++module_param_named(device, param_device, int, S_IRUGO);
++MODULE_PARM_DESC(device, "Device type can be 0:tv, 1:rec 3:tuner 4:mediaplayer, 5:audio");
++module_param_named(addr, param_addr, int, S_IRUGO);
++MODULE_PARM_DESC(addr, "Physical address (until EDID received)");
++
++/*
++ *
++ * TOOLBOX
++ * -------
++ * LEVEL 1
++ *
++ * - i2c read/write
++ * - chip Id check
++ * - i2c client info
++ * 
++ */
++
++
++/* 
++ *  Get main and unique I2C Client driver handle
++ */
++struct i2c_client *GetThisI2cClient(void)
++{
++   cec_instance *this=&our_instance;
++   return this->driver.i2c_client;
++}
++
++/*
++ * error handling
++ */
++static char *hdmi_cec_err_string(int err)
++{
++   switch (err)
++      {
++      case TMDL_ERR_DLHDMICEC_COMPATIBILITY: {return "SW Interface compatibility";break;}
++      case TMDL_ERR_DLHDMICEC_MAJOR_VERSION: {return "SW Major Version error";break;}
++      case TMDL_ERR_DLHDMICEC_COMP_VERSION: {return "SW component version error";break;}
++      case TMDL_ERR_DLHDMICEC_BAD_UNIT_NUMBER: {return "Invalid device unit number";break;}
++      case TMDL_ERR_DLHDMICEC_BAD_INSTANCE: {return "Bad input instance value  ";break;}
++      case TMDL_ERR_DLHDMICEC_BAD_HANDLE: {return "Bad input handle";break;}
++      case TMDL_ERR_DLHDMICEC_BAD_PARAMETER: {return "Invalid input parameter";break;}
++      case TMDL_ERR_DLHDMICEC_NO_RESOURCES: {return "Resource is not available ";break;}
++      case TMDL_ERR_DLHDMICEC_RESOURCE_OWNED: {return "Resource is already in use";break;}
++      case TMDL_ERR_DLHDMICEC_RESOURCE_NOT_OWNED: {return "Caller does not own resource";break;}
++      case TMDL_ERR_DLHDMICEC_INCONSISTENT_PARAMS: {return "Inconsistent input params";break;}
++      case TMDL_ERR_DLHDMICEC_NOT_INITIALIZED: {return "Component is not initializ";break;}
++      case TMDL_ERR_DLHDMICEC_NOT_SUPPORTED: {return "Function is not supported";break;}
++      case TMDL_ERR_DLHDMICEC_INIT_FAILED: {return "Initialization failed";break;}
++      case TMDL_ERR_DLHDMICEC_BUSY: {return "Component is busy";break;}
++      case TMDL_ERR_DLHDMICEC_I2C_READ: {return "Read error";break;}
++      case TMDL_ERR_DLHDMICEC_I2C_WRITE: {return "Write error";break;}
++      case TMDL_ERR_DLHDMICEC_FULL: {return "Queue is full";break;}
++      case TMDL_ERR_DLHDMICEC_NOT_STARTED: {return "Function is not started";break;}
++      case TMDL_ERR_DLHDMICEC_ALREADY_STARTED: {return "Function is already starte";break;}
++      case TMDL_ERR_DLHDMICEC_ASSERTION: {return "Assertion failure";break;}
++      case TMDL_ERR_DLHDMICEC_INVALID_STATE: {return "Invalid state for function";break;}
++      case TMDL_ERR_DLHDMICEC_OPERATION_NOT_PERMITTED: {return "Corresponds to posix EPERM";break;}
++      default : {return "Unexpected error";break;}
++      }
++}
++
++char *cec_opcode(int op)
++{
++   switch (op)
++      {
++      case CEC_OPCODE_FEATURE_ABORT: {return "CEC_OPCODE_FEATURE_ABORT";break;}
++      case CEC_OPCODE_IMAGE_VIEW_ON: {return "CEC_OPCODE_IMAGE_VIEW_ON";break;}
++      case CEC_OPCODE_TUNER_STEP_INCREMENT: {return "CEC_OPCODE_TUNER_STEP_INCREMENT";break;}
++      case CEC_OPCODE_TUNER_STEP_DECREMENT: {return "CEC_OPCODE_TUNER_STEP_DECREMENT";break;}
++      case CEC_OPCODE_TUNER_DEVICE_STATUS: {return "CEC_OPCODE_TUNER_DEVICE_STATUS";break;}
++      case CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS: {return "CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS";break;}
++      case CEC_OPCODE_RECORD_ON: {return "CEC_OPCODE_RECORD_ON";break;}
++      case CEC_OPCODE_RECORD_STATUS: {return "CEC_OPCODE_RECORD_STATUS";break;}
++      case CEC_OPCODE_RECORD_OFF: {return "CEC_OPCODE_RECORD_OFF";break;}
++      case CEC_OPCODE_TEXT_VIEW_ON: {return "CEC_OPCODE_TEXT_VIEW_ON";break;}
++      case CEC_OPCODE_RECORD_TV_SCREEN: {return "CEC_OPCODE_RECORD_TV_SCREEN";break;}
++      case CEC_OPCODE_GIVE_DECK_STATUS: {return "CEC_OPCODE_GIVE_DECK_STATUS";break;}
++      case CEC_OPCODE_DECK_STATUS: {return "CEC_OPCODE_DECK_STATUS";break;}
++      case CEC_OPCODE_SET_MENU_LANGUAGE: {return "CEC_OPCODE_SET_MENU_LANGUAGE";break;}
++      case CEC_OPCODE_CLEAR_ANALOGUE_TIMER: {return "CEC_OPCODE_CLEAR_ANALOGUE_TIMER";break;}
++      case CEC_OPCODE_SET_ANALOGUE_TIMER: {return "CEC_OPCODE_SET_ANALOGUE_TIMER";break;}
++      case CEC_OPCODE_TIMER_STATUS: {return "CEC_OPCODE_TIMER_STATUS";break;}
++      case CEC_OPCODE_STANDBY: {return "CEC_OPCODE_STANDBY";break;}
++      case CEC_OPCODE_PLAY: {return "CEC_OPCODE_PLAY";break;}
++/*       case CEC_OPCODE_DECK_CONTROL: {return "CEC_OPCODE_DECK_CONTROL";break;} */
++      case CEC_OPCODE_TIMER_CLEARED_STATUS: {return "CEC_OPCODE_TIMER_CLEARED_STATUS";break;}
++      case CEC_OPCODE_USER_CONTROL_PRESSED: {return "CEC_OPCODE_USER_CONTROL_PRESSED";break;}
++      case CEC_OPCODE_USER_CONTROL_RELEASED: {return "CEC_OPCODE_USER_CONTROL_RELEASED";break;}
++      case CEC_OPCODE_GIVE_OSD_NAME: {return "CEC_OPCODE_GIVE_OSD_NAME";break;}
++      case CEC_OPCODE_SET_OSD_NAME: {return "CEC_OPCODE_SET_OSD_NAME";break;}
++      case CEC_OPCODE_SET_OSD_STRING: {return "CEC_OPCODE_SET_OSD_STRING";break;}
++      case CEC_OPCODE_SET_TIMER_PROGRAM_TITLE: {return "CEC_OPCODE_SET_TIMER_PROGRAM_TITLE";break;}
++      case CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST: {return "CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST";break;}
++      case CEC_OPCODE_GIVE_AUDIO_STATUS: {return "CEC_OPCODE_GIVE_AUDIO_STATUS";break;}
++      case CEC_OPCODE_SET_SYSTEM_AUDIO_MODE: {return "CEC_OPCODE_SET_SYSTEM_AUDIO_MODE";break;}
++      case CEC_OPCODE_REPORT_AUDIO_STATUS: {return "CEC_OPCODE_REPORT_AUDIO_STATUS";break;}
++      case CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS: {return "CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS";break;}
++      case CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS: {return "CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS";break;}
++      case CEC_OPCODE_ROUTING_CHANGE: {return "CEC_OPCODE_ROUTING_CHANGE";break;}
++      case CEC_OPCODE_ROUTING_INFORMATION: {return "CEC_OPCODE_ROUTING_INFORMATION";break;}
++      case CEC_OPCODE_ACTIVE_SOURCE: {return "CEC_OPCODE_ACTIVE_SOURCE";break;}
++      case CEC_OPCODE_GIVE_PHYSICAL_ADDRESS: {return "CEC_OPCODE_GIVE_PHYSICAL_ADDRESS";break;}
++      case CEC_OPCODE_REPORT_PHYSICAL_ADDRESS: {return "CEC_OPCODE_REPORT_PHYSICAL_ADDRESS";break;}
++      case CEC_OPCODE_REQUEST_ACTIVE_SOURCE: {return "CEC_OPCODE_REQUEST_ACTIVE_SOURCE";break;}
++      case CEC_OPCODE_SET_STREAM_PATH: {return "CEC_OPCODE_SET_STREAM_PATH";break;}
++      case CEC_OPCODE_DEVICE_VENDOR_ID: {return "CEC_OPCODE_DEVICE_VENDOR_ID";break;}
++      case CEC_OPCODE_VENDOR_COMMAND: {return "CEC_OPCODE_VENDOR_COMMAND";break;}
++      case CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN: {return "CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN";break;}
++      case CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP: {return "CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP";break;}
++      case CEC_OPCODE_GIVE_DEVICE_VENDOR_ID: {return "CEC_OPCODE_GIVE_DEVICE_VENDOR_ID";break;}
++      case CEC_OPCODE_MENU_REQUEST: {return "CEC_OPCODE_MENU_REQUEST";break;}
++      case CEC_OPCODE_MENU_STATUS: {return "CEC_OPCODE_MENU_STATUS";break;}
++      case CEC_OPCODE_GIVE_DEVICE_POWER_STATUS: {return "CEC_OPCODE_GIVE_DEVICE_POWER_STATUS";break;}
++      case CEC_OPCODE_REPORT_POWER_STATUS: {return "CEC_OPCODE_REPORT_POWER_STATUS";break;}
++      case CEC_OPCODE_GET_MENU_LANGUAGE: {return "CEC_OPCODE_GET_MENU_LANGUAGE";break;}
++      case CEC_OPCODE_SET_ANALOGUE_SERVICE: {return "CEC_OPCODE_SET_ANALOGUE_SERVICE";break;}
++      case CEC_OPCODE_SET_DIGITAL_SERVICE: {return "CEC_OPCODE_SET_DIGITAL_SERVICE";break;}
++      case CEC_OPCODE_SET_DIGITAL_TIMER: {return "CEC_OPCODE_SET_DIGITAL_TIMER";break;}
++      case CEC_OPCODE_CLEAR_DIGITAL_TIMER: {return "CEC_OPCODE_CLEAR_DIGITAL_TIMER";break;}
++      case CEC_OPCODE_SET_AUDIO_RATE: {return "CEC_OPCODE_SET_AUDIO_RATE";break;}
++      case CEC_OPCODE_INACTIVE_SOURCE: {return "CEC_OPCODE_INACTIVE_SOURCE";break;}
++      case CEC_OPCODE_CEC_VERSION: {return "CEC_OPCODE_CEC_VERSION";break;}
++      case CEC_OPCODE_GET_CEC_VERSION: {return "CEC_OPCODE_GET_CEC_VERSION";break;}
++      case CEC_OPCODE_VENDOR_COMMAND_WITH_ID: {return "CEC_OPCODE_VENDOR_COMMAND_WITH_ID";break;}
++      case CEC_OPCODE_CLEAR_EXTERNAL_TIMER: {return "CEC_OPCODE_CLEAR_EXTERNAL_TIMER";break;}
++      case CEC_OPCODE_SET_EXTERNAL_TIMER: {return "CEC_OPCODE_SET_EXTERNAL_TIMER";break;}
++      case CEC_OPCODE_ABORT_MESSAGE: {return "CEC_OPCODE_ABORT_MESSAGE";break;}
++      default : {return "unknown";break;}
++      }
++}
++
++
++static char *cec_ioctl(int io)
++{
++   switch (io)
++      {
++      case CEC_VERBOSE_ON_CMD: {return "CEC_VERBOSE_ON_CMD";break;}
++      case CEC_VERBOSE_OFF_CMD: {return "CEC_VERBOSE_OFF_CMD";break;}
++      case CEC_BYEBYE_CMD: {return "CEC_BYEBYE_CMD";break;}
++      case CEC_IOCTL_RX_ADDR_CMD: {return "CEC_IOCTL_RX_ADDR_CMD";break;}
++      case CEC_IOCTL_PHY_ADDR_CMD: {return "CEC_IOCTL_PHY_ADDR_CMD";break;}
++      case CEC_IOCTL_WAIT_FRAME_CMD: {return "CEC_IOCTL_WAIT_FRAME_CMD";break;}
++      case CEC_IOCTL_ABORT_MSG_CMD: {return "CEC_IOCTL_ABORT_MSG_CMD";break;}
++      case CEC_IOCTL_ACTIVE_SRC_CMD: {return "CEC_IOCTL_ACTIVE_SRC_CMD";break;}
++      case CEC_IOCTL_VERSION_CMD: {return "CEC_IOCTL_VERSION_CMD";break;}
++      case CEC_IOCTL_CLEAR_ANALOGUE_TIMER_CMD: {return "CEC_IOCTL_CLEAR_ANALOGUE_TIMER_CMD";break;}
++      case CEC_IOCTL_CLEAR_DIGITAL_TIMER_CMD: {return "CEC_IOCTL_CLEAR_DIGITAL_TIMER_CMD";break;}
++      case CEC_IOCTL_CLEAR_EXT_TIMER_WITH_EXT_PLUG_CMD: {return "CEC_IOCTL_CLEAR_EXT_TIMER_WITH_EXT_PLUG_CMD";break;}
++      case CEC_IOCTL_CLEAR_EXT_TIMER_WITH_PHY_ADDR_CMD: {return "CEC_IOCTL_CLEAR_EXT_TIMER_WITH_PHY_ADDR_CMD";break;}
++      case CEC_IOCTL_DECK_CTRL_CMD: {return "CEC_IOCTL_DECK_CTRL_CMD";break;}
++      case CEC_IOCTL_DECK_STATUS_CMD: {return "CEC_IOCTL_DECK_STATUS_CMD";break;}
++      case CEC_IOCTL_DEVICE_VENDOR_ID_CMD: {return "CEC_IOCTL_DEVICE_VENDOR_ID_CMD";break;}
++      case CEC_IOCTL_FEATURE_ABORT_CMD: {return "CEC_IOCTL_FEATURE_ABORT_CMD";break;}
++      case CEC_IOCTL_GET_CEC_VERSION_CMD: {return "CEC_IOCTL_GET_CEC_VERSION_CMD";break;}
++      case CEC_IOCTL_GET_MENU_LANGUAGE_CMD: {return "CEC_IOCTL_GET_MENU_LANGUAGE_CMD";break;}
++      case CEC_IOCTL_GIVE_AUDIO_STATUS_CMD: {return "CEC_IOCTL_GIVE_AUDIO_STATUS_CMD";break;}
++      case CEC_IOCTL_GIVE_DECK_STATUS_CMD: {return "CEC_IOCTL_GIVE_DECK_STATUS_CMD";break;}
++      case CEC_IOCTL_GIVE_DEVICE_POWER_STATUS_CMD: {return "CEC_IOCTL_GIVE_DEVICE_POWER_STATUS_CMD";break;}
++      case CEC_IOCTL_GIVE_DEVICE_VENDOR_ID_CMD: {return "CEC_IOCTL_GIVE_DEVICE_VENDOR_ID_CMD";break;}
++      case CEC_IOCTL_GIVE_OSD_NAME_CMD: {return "CEC_IOCTL_GIVE_OSD_NAME_CMD";break;}
++      case CEC_IOCTL_GIVE_PHY_ADDR_CMD: {return "CEC_IOCTL_GIVE_PHY_ADDR_CMD";break;}
++      case CEC_IOCTL_GIVE_SYS_AUDIO_MODE_STATUS_CMD: {return "CEC_IOCTL_GIVE_SYS_AUDIO_MODE_STATUS_CMD";break;}
++      case CEC_IOCTL_GIVE_TUNER_DEVICE_STATUS_CMD: {return "CEC_IOCTL_GIVE_TUNER_DEVICE_STATUS_CMD";break;}
++      case CEC_IOCTL_IMAGE_VIEW_ON_CMD: {return "CEC_IOCTL_IMAGE_VIEW_ON_CMD";break;}
++      case CEC_IOCTL_INACTIVE_SRC_CMD: {return "CEC_IOCTL_INACTIVE_SRC_CMD";break;}
++      case CEC_IOCTL_MENU_REQUEST_CMD: {return "CEC_IOCTL_MENU_REQUEST_CMD";break;}
++      case CEC_IOCTL_MENU_STATUS_CMD: {return "CEC_IOCTL_MENU_STATUS_CMD";break;}
++      case CEC_IOCTL_PLAY_CMD: {return "CEC_IOCTL_PLAY_CMD";break;}
++      case CEC_IOCTL_POLLING_MSG_CMD: {return "CEC_IOCTL_POLLING_MSG_CMD";break;}
++      case CEC_IOCTL_REC_OFF_CMD: {return "CEC_IOCTL_REC_OFF_CMD";break;}
++      case CEC_IOCTL_REC_ON_ANALOGUE_SERVICE_CMD: {return "CEC_IOCTL_REC_ON_ANALOGUE_SERVICE_CMD";break;}
++      case CEC_IOCTL_REC_ON_DIGITAL_SERVICE_CMD: {return "CEC_IOCTL_REC_ON_DIGITAL_SERVICE_CMD";break;}
++      case CEC_IOCTL_REC_ON_EXT_PHY_ADDR_CMD: {return "CEC_IOCTL_REC_ON_EXT_PHY_ADDR_CMD";break;}
++      case CEC_IOCTL_REC_ON_EXT_PLUG_CMD: {return "CEC_IOCTL_REC_ON_EXT_PLUG_CMD";break;}
++      case CEC_IOCTL_REC_ON_OWN_SRC_CMD: {return "CEC_IOCTL_REC_ON_OWN_SRC_CMD";break;}
++      case CEC_IOCTL_REC_STATUS_CMD: {return "CEC_IOCTL_REC_STATUS_CMD";break;}
++      case CEC_IOCTL_REC_TV_SCREEN_CMD: {return "CEC_IOCTL_REC_TV_SCREEN_CMD";break;}
++      case CEC_IOCTL_REPORT_AUDIO_STATUS_CMD: {return "CEC_IOCTL_REPORT_AUDIO_STATUS_CMD";break;}
++      case CEC_IOCTL_REPORT_PHY_ADDR_CMD: {return "CEC_IOCTL_REPORT_PHY_ADDR_CMD";break;}
++      case CEC_IOCTL_REPORT_POWER_STATUS_CMD: {return "CEC_IOCTL_REPORT_POWER_STATUS_CMD";break;}
++      case CEC_IOCTL_REQUEST_ACTIVE_SRC_CMD: {return "CEC_IOCTL_REQUEST_ACTIVE_SRC_CMD";break;}
++      case CEC_IOCTL_ROUTING_CHANGE_CMD: {return "CEC_IOCTL_ROUTING_CHANGE_CMD";break;}
++      case CEC_IOCTL_ROUTING_INFORMATION_CMD: {return "CEC_IOCTL_ROUTING_INFORMATION_CMD";break;}
++      case CEC_IOCTL_SELECT_ANALOGUE_SERVICE_CMD: {return "CEC_IOCTL_SELECT_ANALOGUE_SERVICE_CMD";break;}
++      case CEC_IOCTL_SELECT_DIGITAL_SERVICE_CMD: {return "CEC_IOCTL_SELECT_DIGITAL_SERVICE_CMD";break;}
++      case CEC_IOCTL_SET_ANALOGUE_TIMER_CMD: {return "CEC_IOCTL_SET_ANALOGUE_TIMER_CMD";break;}
++      case CEC_IOCTL_SET_AUDIO_RATE_CMD: {return "CEC_IOCTL_SET_AUDIO_RATE_CMD";break;}
++      case CEC_IOCTL_SET_DIGITAL_TIMER_CMD: {return "CEC_IOCTL_SET_DIGITAL_TIMER_CMD";break;}
++      case CEC_IOCTL_SET_EXT_TIMER_WITH_EXT_PLUG_CMD: {return "CEC_IOCTL_SET_EXT_TIMER_WITH_EXT_PLUG_CMD";break;}
++      case CEC_IOCTL_SET_EXT_TIMER_WITH_PHY_ADDR_CMD: {return "CEC_IOCTL_SET_EXT_TIMER_WITH_PHY_ADDR_CMD";break;}
++      case CEC_IOCTL_SET_MENU_LANGUAGE_CMD: {return "CEC_IOCTL_SET_MENU_LANGUAGE_CMD";break;}
++      case CEC_IOCTL_SET_OSD_NAME_CMD: {return "CEC_IOCTL_SET_OSD_NAME_CMD";break;}
++      case CEC_IOCTL_SET_OSD_STRING_CMD: {return "CEC_IOCTL_SET_OSD_STRING_CMD";break;}
++      case CEC_IOCTL_SET_STREAM_PATH_CMD: {return "CEC_IOCTL_SET_STREAM_PATH_CMD";break;}
++      case CEC_IOCTL_SET_SYS_AUDIO_MODE_CMD: {return "CEC_IOCTL_SET_SYS_AUDIO_MODE_CMD";break;}
++      case CEC_IOCTL_SET_TIMER_PROGRAM_TITLE_CMD: {return "CEC_IOCTL_SET_TIMER_PROGRAM_TITLE_CMD";break;}
++      case CEC_IOCTL_STANDBY_CMD: {return "CEC_IOCTL_STANDBY_CMD";break;}
++      case CEC_IOCTL_SYS_AUDIO_MODE_REQUEST_CMD: {return "CEC_IOCTL_SYS_AUDIO_MODE_REQUEST_CMD";break;}
++      case CEC_IOCTL_SYS_AUDIO_MODE_STATUS_CMD: {return "CEC_IOCTL_SYS_AUDIO_MODE_STATUS_CMD";break;}
++      case CEC_IOCTL_TEXT_VIEW_ON_CMD: {return "CEC_IOCTL_TEXT_VIEW_ON_CMD";break;}
++      case CEC_IOCTL_TIMER_CLEARED_STATUS_CMD: {return "CEC_IOCTL_TIMER_CLEARED_STATUS_CMD";break;}
++      case CEC_IOCTL_TIMER_STATUS_CMD: {return "CEC_IOCTL_TIMER_STATUS_CMD";break;}
++      case CEC_IOCTL_TUNER_DEVICE_STATUS_ANALOGUE_CMD: {return "CEC_IOCTL_TUNER_DEVICE_STATUS_ANALOGUE_CMD";break;}
++      case CEC_IOCTL_TUNER_DEVICE_STATUS_DIGITAL_CMD: {return "CEC_IOCTL_TUNER_DEVICE_STATUS_DIGITAL_CMD";break;}
++      case CEC_IOCTL_TUNER_STEP_DECREMENT_CMD: {return "CEC_IOCTL_TUNER_STEP_DECREMENT_CMD";break;}
++      case CEC_IOCTL_TUNER_STEP_INCREMENT_CMD: {return "CEC_IOCTL_TUNER_STEP_INCREMENT_CMD";break;}
++      case CEC_IOCTL_USER_CTRL_CMD: {return "CEC_IOCTL_USER_CTRL_CMD";break;}
++      case CEC_IOCTL_USER_CTRL_PLAY_CMD: {return "CEC_IOCTL_USER_CTRL_PLAY_CMD";break;}
++      case CEC_IOCTL_USER_CTRL_SELECT_AUDIOINPUT_CMD: {return "CEC_IOCTL_USER_CTRL_SELECT_AUDIOINPUT_CMD";break;}
++      case CEC_IOCTL_USER_CTRL_SELECT_AVINPUT_CMD: {return "CEC_IOCTL_USER_CTRL_SELECT_AVINPUT_CMD";break;}
++      case CEC_IOCTL_USER_CTRL_SELECT_MEDIA_CMD: {return "CEC_IOCTL_USER_CTRL_SELECT_MEDIA_CMD";break;}
++      case CEC_IOCTL_USER_CTRL_TUNE_CMD: {return "CEC_IOCTL_USER_CTRL_TUNE_CMD";break;}
++      case CEC_IOCTL_USER_CTRL_RELEASED_CMD: {return "CEC_IOCTL_USER_CTRL_RELEASED_CMD";break;}
++      case CEC_IOCTL_VENDOR_COMMAND_CMD: {return "CEC_IOCTL_VENDOR_COMMAND_CMD";break;}
++      case CEC_IOCTL_VENDOR_COMMAND_WITH_ID_CMD: {return "CEC_IOCTL_VENDOR_COMMAND_WITH_ID_CMD";break;}
++      case CEC_IOCTL_VENDOR_REMOTE_BUTTON_DOWN_CMD: {return "CEC_IOCTL_VENDOR_REMOTE_BUTTON_DOWN_CMD";break;}
++      case CEC_IOCTL_VENDOR_REMOTE_BUTTON_UP_CMD: {return "CEC_IOCTL_VENDOR_REMOTE_BUTTON_UP_CMD";break;}
++      case CEC_IOCTL_GET_SW_VERSION_CMD: {return "CEC_IOCTL_GET_SW_VERSION_CMD";break;}
++      case CEC_IOCTL_SET_POWER_STATE_CMD: {return "CEC_IOCTL_SET_POWER_STATE_CMD";break;}
++      case CEC_IOCTL_GET_POWER_STATE_CMD: {return "CEC_IOCTL_GET_POWER_STATE_CMD";break;}
++      case CEC_IOCTL_INSTANCE_CONFIG_CMD: {return "CEC_IOCTL_INSTANCE_CONFIG_CMD";break;}
++      case CEC_IOCTL_INSTANCE_SETUP_CMD: {return "CEC_IOCTL_INSTANCE_SETUP_CMD";break;}
++      case CEC_IOCTL_GET_INSTANCE_SETUP_CMD: {return "CEC_IOCTL_GET_INSTANCE_SETUP_CMD";break;}
++      case CEC_IOCTL_ENABLE_EVENT_CMD: {return "CEC_IOCTL_ENABLE_EVENT_CMD";break;}
++      case CEC_IOCTL_DISABLE_EVENT_CMD: {return "CEC_IOCTL_DISABLE_EVENT_CMD";break;}
++      case CEC_IOCTL_ENABLE_CALIBRATION_CMD: {return "CEC_IOCTL_ENABLE_CALIBRATION_CMD";break;}
++      case CEC_IOCTL_DISABLE_CALIBRATION_CMD: {return "CEC_IOCTL_DISABLE_CALIBRATION_CMD";break;}
++      case CEC_IOCTL_SEND_MSG_CMD: {return "CEC_IOCTL_SEND_MSG_CMD";break;}
++      case CEC_IOCTL_SET_REGISTER_CMD: {return "CEC_IOCTL_SET_REGISTER_CMD";break;}
++      default : {return "unknown";break;}
++      }
++}
++
++
++static char *cec_rxstatus(int s)
++{
++   switch (s)
++      {
++      case CEC_MSG_SUCCESS :{return "success";break;}
++      case CEC_MSG_FAIL_DATA_NOT_ACK :{return "data not ack";break;}
++      case CEC_CSP_OFF_STATE :{return "CSP off";break;}
++      case CEC_BAD_REQ_SERVICE :{return "bad Req";break;}
++      case CEC_MSG_FAIL_UNABLE_TO_ACCESS :{return "CEC line error";break;}
++      case CEC_MSG_FAIL_ARBITRATION_ERROR :{return "arb error";break;}
++      case CEC_MSG_FAIL_BIT_TIMMING_ERROR :{return "bit error";break;}
++      case CEC_MSG_FAIL_DEST_NOT_ACK :{return "destination not ack";break;}
++      default : {return "unknown";break;}
++      }
++}
++
++
++static unsigned char get_next_logical_addr(cec_device_type device,unsigned char la)
++{
++   switch (device) {
++   case CEC_DEVICE_TYPE_TV:
++      switch (la) {
++      case CEC_LOGICAL_ADDRESS_TV:
++         return CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST;
++      default:
++         return CEC_LOGICAL_ADDRESS_TV;
++      }
++   case CEC_DEVICE_TYPE_REC_DEVICE:
++      switch (la) {
++      case CEC_LOGICAL_ADDRESS_RECORDING_DEVICE_1:
++         return CEC_LOGICAL_ADDRESS_RECORDING_DEVICE_2;
++      case CEC_LOGICAL_ADDRESS_RECORDING_DEVICE_2:
++         return CEC_LOGICAL_ADDRESS_RECORDING_DEVICE_3;
++      case CEC_LOGICAL_ADDRESS_RECORDING_DEVICE_3:
++         return CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST;
++      default:
++         return CEC_LOGICAL_ADDRESS_RECORDING_DEVICE_1;
++      }
++   case CEC_DEVICE_TYPE_TUNER:
++      switch (la) {
++      case CEC_LOGICAL_ADDRESS_TUNER_1:
++         return CEC_LOGICAL_ADDRESS_TUNER_2;
++      case CEC_LOGICAL_ADDRESS_TUNER_2:
++         return CEC_LOGICAL_ADDRESS_TUNER_3;
++      case CEC_LOGICAL_ADDRESS_TUNER_3:
++         return CEC_LOGICAL_ADDRESS_TUNER_4;
++      case CEC_LOGICAL_ADDRESS_TUNER_4:
++         return CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST;
++      default:
++         return CEC_LOGICAL_ADDRESS_TUNER_1;
++      }
++   case CEC_DEVICE_TYPE_PLAYBACK_DEVICE:
++      switch (la) {
++      case CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_1:
++         return CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_2;
++      case CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_2:
++         return CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_3;
++      case CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_3:
++         return CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST;
++      default:
++         return CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_1;
++      }
++   case CEC_DEVICE_TYPE_AUDIO_DEVICE: 
++      switch (la) {
++      case CEC_LOGICAL_ADDRESS_AUDIO_SYSTEM:
++         return CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST;
++      default:
++         return CEC_LOGICAL_ADDRESS_AUDIO_SYSTEM;
++      }
++   default:
++      return CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST;
++   }
++}
++
++static int device_type(int type)
++{
++   printk(KERN_INFO "hdmicec declared as a ");
++   switch (type) {
++   case CEC_DEVICE_TYPE_TV: 
++      printk("TV");
++      break;
++   case CEC_DEVICE_TYPE_REC_DEVICE: 
++      printk("record");
++      break;
++   case CEC_DEVICE_TYPE_TUNER: 
++      printk("tuner");
++      break;
++   case CEC_DEVICE_TYPE_PLAYBACK_DEVICE: 
++      printk("playback");
++      break;
++   case CEC_DEVICE_TYPE_AUDIO_DEVICE: 
++      printk("audio");
++      break;
++   default: 
++      printk("default (playback)");
++      type = CEC_DEVICE_TYPE_PLAYBACK_DEVICE;
++      break;
++   }
++   printk(" device type\n");
++   return type;
++}
++
++
++/*
++ *
++ * PROCESSING
++ * ----------
++ * LEVEL 2
++ *
++ */
++
++
++/*
++ *  CEC Power On
++ */
++static void cec_on(cec_instance *this)
++{
++   int err;
++   struct task_struct *tsk = current;
++
++   // disable_irq(gpio_to_irq(TDA_IRQ_CALIB));
++
++   this->cec.power = tmPowerOn;
++   TRY(tmdlHdmiCecSetPowerState(this->cec.inst,this->cec.power));
++
++   /* turn GPIO into calib pulse generator */
++   gpio_direction_output(TDA_IRQ_CALIB,0); /* output (1 means try-state or high) */
++   __gpio_set_value(TDA_IRQ_CALIB,1);
++   this->cec.clock = TMDL_HDMICEC_CLOCK_FRO;
++   TRY(tmdlHdmiCecEnableCalibration(this->cec.inst,this->cec.clock));
++   msleep(10);
++   set_current_state(TASK_UNINTERRUPTIBLE);
++
++   /* CAUTION : TDA needs a real 10ms pulse */
++   cpu_relax();
++   spin_lock_irq(&tsk->sighand->siglock);
++   __gpio_set_value(TDA_IRQ_CALIB,0);
++   __udelay(10000);
++   __gpio_set_value(TDA_IRQ_CALIB,1);
++   spin_unlock_irq(&tsk->sighand->siglock);
++
++   msleep(10);
++   TRY(tmdlHdmiCecDisableCalibration(this->cec.inst));
++
++   /* setup */ 
++   TRY(tmdlHdmiCecGetInstanceSetup(this->cec.inst,&this->cec.setup));
++   this->cec.setup.DeviceLogicalAddress = this->cec.rx_addr;
++   this->cec.clock = TMDL_HDMICEC_CLOCK_FRO;
++   this->cec.setup.cecClockSource = this->cec.clock;
++   TRY(tmdlHdmiCecInstanceSetup(this->cec.inst,&this->cec.setup));
++
++   /* turn GPIO into IRQ */
++   gpio_direction_input(TDA_IRQ_CALIB);
++   // enable_irq(gpio_to_irq(TDA_IRQ_CALIB));
++
++   LOG(KERN_INFO,"standby --> on\n");
++
++ TRY_DONE:
++   (void)0;
++}
++
++/*
++ *  CEC Power Off
++ */
++static void cec_standby(cec_instance *this)
++{
++   int err;
++
++   this->cec.power = tmPowerStandby;
++   TRY(tmdlHdmiCecSetPowerState(this->cec.inst,this->cec.power));
++   
++   LOG(KERN_INFO,"on --> standby\n");
++
++ TRY_DONE:
++   (void)0;
++}
++
++/*
++ *  CEC interrupt polling
++ */
++static void cec_interrupt(struct work_struct *dummy)
++{
++   cec_instance *this=&our_instance;
++   unsigned short new_phy_addr=edid_phy_addr();
++   int err=0;
++   
++   LOG(KERN_INFO,"%s called\n",__func__);
++
++   /* switch on/off CEC */
++   if (!get_hpd_status() &&                     \
++       (this->cec.power == tmPowerOn)) {
++      this->cec.source_status = CEC_POWER_STATUS_STANDBY;
++/*       TRY(tmdlHdmiCecInactiveSource(this->cec.inst,             \ */
++/*                                        this->cec.initiator,     \ */
++/*                                        this->cec.phy_addr)); */
++      cec_standby(this);
++   }
++   else if (get_hpd_status() &&                         \
++            (this->cec.power == tmPowerStandby)) {
++      /* send active msg when hdmi has been abled */
++      cec_on(this);
++   }
++   /* new phy addr means new EDID, mean HPD ! */
++   else if ((this->cec.phy_addr != new_phy_addr) &&        \
++       (this->cec.source_status == CEC_POWER_STATUS_ON)) {
++      LOG(KERN_INFO,"New physical address %02x\n",new_phy_addr);
++      this->cec.phy_addr = new_phy_addr;
++      if (this->cec.phy_addr != 0xFFFF) {
++         this->cec.rx_addr = get_next_logical_addr(this->cec.device_type,CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST);
++         TRY(tmdlHdmiCecPollingMessage(this->cec.inst,this->cec.rx_addr));
++      }
++      else {
++         this->cec.rx_addr = CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST;
++      }
++   }
++#ifdef GUI_OVER_HDMI
++   else if (edid_received()) { /* Check me */
++      if (this->cec.source_status == CEC_POWER_STATUS_STANDBY) {
++         /* only for GFX on HDMI, do not use if only video playback on HDMI */
++         TRY(tmdlHdmiCecImageViewOn(this->cec.inst,this->cec.initiator));
++         TRY(tmdlHdmiCecHandleInterrupt(this->cec.inst));
++         msleep(200);
++         TRY(tmdlHdmiCecActiveSource(this->cec.inst,this->cec.phy_addr));
++         this->cec.source_status = CEC_POWER_STATUS_ON;
++      }
++   }
++#endif
++   
++#if 0
++   if (this->cec.phy_addr != 0xFFFF) {
++
++      /* claim source status */
++      if ((get_hdmi_status() ==  tmPowerStandby) &&             \
++          (this->cec.source_status == CEC_POWER_STATUS_ON)) {
++         /* send inactive msg when hdmi has been disabled */
++         this->cec.source_status = CEC_POWER_STATUS_STANDBY;
++         TRY(tmdlHdmiCecInactiveSource(this->cec.inst,          \
++                                       this->cec.initiator,     \
++                                       this->cec.phy_addr));
++      }
++      else if ((get_hdmi_status() ==  tmPowerOn) &&                     \
++               (this->cec.source_status == CEC_POWER_STATUS_STANDBY)) {
++         /* send active msg when hdmi has been abled */
++         this->cec.source_status = CEC_POWER_STATUS_ON;
++         TRY(tmdlHdmiCecActiveSource(this->cec.inst,        \
++                                     this->cec.phy_addr));
++      }
++/*       printk(KERN_INFO "DBG phd_status:%s cec.power:%s\n", \ */
++/*              get_hpd_status()?"Active":"Inactive",                                      \ */
++/*              (this->cec.power==tmPowerOn)?"On":"Standby"); */
++   }
++#endif
++
++   /* internal handeling */
++   TRY(tmdlHdmiCecHandleInterrupt(this->cec.inst));
++    
++ TRY_DONE:
++
++   /* setup next tick */
++   if (!this->driver.deinit_req) {
++      /* setup next polling */
++#ifndef IRQ
++/*       this->driver.timer.expires = jiffies + ( CHECK_EVERY_XX_MS * HZ / 1000 ); */
++/*       add_timer(&this->driver.timer); */
++      mod_timer(&this->driver.timer,jiffies + ( CHECK_EVERY_XX_MS * HZ / 1000 ));
++#endif
++   }
++   else {
++      this->driver.deinit_req++;
++      wake_up_interruptible(&this->driver.wait);
++   }
++}
++
++#ifndef IRQ
++static DECLARE_WORK(wq_name, cec_interrupt);
++
++void polling_timeout(unsigned long arg)
++{
++
++#if 0
++   /* fake frame for equipement-less testing */
++
++      cec_instance *this=&our_instance;
++
++      if (this->driver.timer.data++>1000) {
++         printk(KERN_INFO "Fake Rx message\n");
++         this->driver.timer.data=0;
++
++         this->cec.frame.count = 4;
++         this->cec.frame.addr = 4; /* 0-->4 (TV-->MediaPlayer1) */
++         this->cec.frame.data[0]=0x46; /* opcode: "GiveOsd" */
++         this->cec.frame.service = CEC_RX_DONE;
++         
++         this->driver.poll_done = true;
++         wake_up_interruptible(&this->driver.wait);
++      }
++#endif
++
++   /* derefered because ATOMIC context of timer does not support I2C_transfert */
++   schedule_work(&wq_name);
++
++}
++#endif
++
++#ifndef IRQ
++/*
++ *  TDA irq
++ */
++static irqreturn_t tda_irq(int irq, void *_udc)
++{
++   cec_instance *this=&our_instance;
++   /*    printk(KERN_INFO "DBG caught irq:%d\n",irq); */
++ 
++   /* do it now */
++   mod_timer(&this->driver.timer,jiffies);
++
++   return IRQ_HANDLED;
++}
++#endif
++
++#ifdef TWL4030_HACK
++/*
++ *  User Control
++ */
++static void user_control(int key, int press)
++{
++   input_report_key(gkp_input, key, press);
++   input_sync(gkp_input);
++   msleep(20);
++   input_report_key(gkp_input, key, 0);
++   input_sync(gkp_input);
++}
++#endif
++
++/*
++ *  CEC callback
++ */
++static void eventCallbackCEC(tmdlHdmiCecEvent_t event, unsigned char *data, unsigned char length)
++{
++   int err=0;
++   cec_instance *this=&our_instance;
++   int opcode;
++   int initiator,receiver;
++
++   if (event == TMDL_HDMICEC_CALLBACK_MESSAGE_AVAILABLE) {
++
++      this->cec.frame.count = length;
++      this->cec.frame.addr = data[1]; /* .AddressByte */
++      initiator = (this->cec.frame.addr >> 4) & 0x0F;
++      this->cec.initiator = initiator;
++      receiver = this->cec.frame.addr & 0x0F;
++      memcpy(&this->cec.frame.data,&data[2],length-2); /* .DataBytes[], length - siezof(length,addr,ack) */
++      opcode=this->cec.frame.data[0];
++      printk(KERN_INFO "hdmicec:Rx:[%x--->%x] %s length:%d addr:%d %02x%02x%02x%02x\n",initiator,receiver,cec_opcode(opcode), \
++          length,data[1],
++          this->cec.frame.data[0],                                      \
++          this->cec.frame.data[1],                                      \
++          this->cec.frame.data[2],                                      \
++          this->cec.frame.data[3]);
++      this->cec.frame.service = CEC_RX_DONE;
++
++      msleep(20);
++
++      /* automatic answering */
++      switch (opcode) {
++      case CEC_OPCODE_GIVE_PHYSICAL_ADDRESS:
++         TRY(tmdlHdmiCecReportPhysicalAddress(this->cec.inst,           \
++                                              this->cec.phy_addr,       \
++                                              this->cec.device_type));
++         break;
++      case CEC_OPCODE_GET_CEC_VERSION:
++         TRY(tmdlHdmiCecVersion(this->cec.inst,                         \
++                                this->cec.initiator,                    \
++                                this->cec.version));
++         break;   
++      case CEC_OPCODE_GIVE_OSD_NAME:
++         TRY(tmdlHdmiCecSetOsdName(this->cec.inst,         \
++                                   this->cec.initiator,        \
++                                   this->cec.osd_name.data,         \
++                                   this->cec.osd_name.length));
++         break;
++      case CEC_OPCODE_GIVE_DEVICE_VENDOR_ID:
++         TRY(tmdlHdmiCecDeviceVendorID(this->cec.inst,              \
++                                       this->cec.vendor_id));
++         break;
++      case CEC_OPCODE_REQUEST_ACTIVE_SOURCE:
++         if (this->cec.source_status == CEC_POWER_STATUS_ON) {
++            if (this->cec.initiator != 0x0F) {
++               if (receiver == 0x0F) {
++                  TRY(tmdlHdmiCecActiveSource(this->cec.inst,this->cec.phy_addr));
++               }
++            }
++         }
++         break;
++      case CEC_OPCODE_ACTIVE_SOURCE:
++         if (this->cec.source_status == CEC_POWER_STATUS_ON) {
++            this->cec.source_status = CEC_POWER_STATUS_STANDBY;
++            hdmi_disable(1);
++            this->cec.power = tmPowerOn;
++            TRY(tmdlHdmiCecSetPowerState(this->cec.inst,this->cec.power)); /* keeps CEC alive */
++         }
++         break;
++      case CEC_OPCODE_GIVE_DEVICE_POWER_STATUS:
++         TRY(tmdlHdmiCecReportPowerStatus(this->cec.inst,               \
++                                          this->cec.initiator,          \
++                                          this->cec.source_status));
++         break;
++      case CEC_OPCODE_STANDBY:
++         /* mind recording device can only be stopped by appli */ 
++         if (this->cec.device_type != CEC_DEVICE_TYPE_REC_DEVICE) {
++            this->cec.source_status = CEC_POWER_STATUS_STANDBY;
++            hdmi_disable(1);
++            this->cec.power = tmPowerOn;
++            TRY(tmdlHdmiCecSetPowerState(this->cec.inst,this->cec.power));  /* keeps CEC alive */
++         }
++         break;
++      case CEC_OPCODE_ROUTING_INFORMATION:
++      case CEC_OPCODE_SET_STREAM_PATH:
++         /* wake-up if called */
++         if (this->cec.phy_addr == (((int)this->cec.frame.data[1] << 8) + this->cec.frame.data[2])) {
++            if (this->cec.source_status != CEC_POWER_STATUS_ON) {
++               this->cec.source_status = CEC_POWER_STATUS_ON;
++               hdmi_enable();
++            }
++            TRY(tmdlHdmiCecActiveSource(this->cec.inst,this->cec.phy_addr));
++         }
++         break;
++/*       case /\* NEW DECK ??? *\/ */
++      case CEC_OPCODE_ROUTING_CHANGE:
++         /* wake-up if called */
++         if (this->cec.phy_addr == (((int)this->cec.frame.data[3] << 8) + this->cec.frame.data[4])) {
++            if (this->cec.source_status != CEC_POWER_STATUS_ON) {
++               this->cec.source_status = CEC_POWER_STATUS_ON;
++               hdmi_enable();
++            }
++            TRY(tmdlHdmiCecActiveSource(this->cec.inst,this->cec.phy_addr));
++         }
++         break;
++      case CEC_OPCODE_ABORT_MESSAGE:
++         if (this->cec.phy_addr == (((int)this->cec.frame.data[3] << 8) + this->cec.frame.data[4])) {
++            TRY(tmdlHdmiCecFeatureAbort(this->cec.inst, \
++                                        this->cec.initiator, \
++                                        this->cec.feature_abort.FeatureOpcode, \
++                                        this->cec.feature_abort.AbortReason));
++         }
++         break;
++      case CEC_OPCODE_MENU_REQUEST:
++#ifdef TWL4030_HACK
++         this->cec.menu_status = CEC_MENU_STATE_ACTIVATE;
++         TRY(tmdlHdmiCecMenuStatus(this->cec.inst, \
++                                   this->cec.initiator, \
++                                   this->cec.menu_status));
++         break;
++#endif
++      case CEC_OPCODE_USER_CONTROL_PRESSED:
++         switch (this->cec.frame.data[1]) {
++#ifdef TWL4030_HACK /* AL : hack to bypass keypad */
++         case CEC_REMOTE_BUTTON_SELECT:
++            user_control(353,64);
++            break;
++         case CEC_REMOTE_BUTTON_UP:
++            user_control(103,128);
++            break;
++         case CEC_REMOTE_BUTTON_DOWN:
++            user_control(108,128);
++            break;
++         case CEC_REMOTE_BUTTON_LEFT:
++            user_control(105,128);
++            break;
++         case CEC_REMOTE_BUTTON_RIGHT:
++            user_control(106,128);
++            break;
++         case CEC_REMOTE_BUTTON_EXIT:
++            user_control(14,8);
++            break;
++#endif
++         case CEC_REMOTE_BUTTON_POWER:
++            this->cec.source_status = CEC_POWER_STATUS_ON;
++            hdmi_enable();
++            break;
++         default:
++            this->cec.feature_abort.FeatureOpcode=opcode;
++            this->cec.feature_abort.AbortReason=CEC_ABORT_INVALID_OPERAND;
++            TRY(tmdlHdmiCecFeatureAbort(this->cec.inst, \
++                                        this->cec.initiator, \
++                                        this->cec.feature_abort.FeatureOpcode, \
++                                        this->cec.feature_abort.AbortReason));
++            break;
++         }
++         break;
++#ifdef TWL4030_HACK
++      case CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN:
++         user_control(59,8);
++#endif
++         break;
++      case CEC_OPCODE_FEATURE_ABORT:
++         /* stop any state machine transition */
++         break;
++      case CEC_OPCODE_VENDOR_COMMAND:
++      case CEC_OPCODE_DEVICE_VENDOR_ID:
++         /* hopefully will be handle in userspace */
++         break;
++      default:
++         if (receiver != 0x0F) {
++            this->cec.feature_abort.FeatureOpcode=opcode;
++            this->cec.feature_abort.AbortReason=CEC_ABORT_UNKNOWN_OPCODE;
++            TRY(tmdlHdmiCecFeatureAbort(this->cec.inst,                 \
++                                        this->cec.initiator,            \
++                                        this->cec.feature_abort.FeatureOpcode, \
++                                        this->cec.feature_abort.AbortReason));
++         }
++         break;
++      }
++      this->driver.poll_done = true;
++      wake_up_interruptible(&this->driver.wait);
++   }
++   else if (event == TMDL_HDMICEC_CALLBACK_STATUS) {
++
++      this->cec.frame.count = length;
++      this->cec.frame.addr = data[1]; /* .AddressByte */
++      initiator = (this->cec.frame.addr >> 4) & 0x0F;
++      receiver = this->cec.frame.addr & 0x0F;
++      memcpy(&this->cec.frame.data,&data[2],length-2); /* .DataBytes[], length - siezof(length,addr)  */
++      opcode=this->cec.frame.data[0];
++      this->cec.frame.service = CEC_TX_DONE;
++
++      if (length==POLLING_LENGTH) {
++         if (opcode == CEC_MSG_FAIL_DEST_NOT_ACK) {
++            /* no echo means it's mine ! */
++            TRY(tmdlHdmiCecSetLogicalAddress(this->cec.inst,this->cec.rx_addr));
++            TRY(tmdlHdmiCecReportPhysicalAddress(this->cec.inst,        \
++                                                 this->cec.phy_addr,    \
++                                                 this->cec.device_type));
++            /* DEVICE VENDOR ID sending after logicial address allocation according to spec 1.4 */
++            TRY(tmdlHdmiCecDeviceVendorID(this->cec.inst, this->cec.vendor_id));
++         }
++         else if (opcode == CEC_MSG_SUCCESS) {
++            /* try next one */
++            this->cec.rx_addr=get_next_logical_addr(this->cec.device_type,this->cec.rx_addr);
++            if (this->cec.rx_addr != CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST) {
++               TRY(tmdlHdmiCecPollingMessage(this->cec.inst,this->cec.rx_addr));
++            }
++            else {
++               /* no more room, keep and claim unregistred */
++               TRY(tmdlHdmiCecSetLogicalAddress(this->cec.inst,this->cec.rx_addr));
++               TRY(tmdlHdmiCecReportPhysicalAddress(this->cec.inst,     \
++                                                    this->cec.phy_addr, \
++                                                    this->cec.device_type));
++            }
++         }
++         else {
++            printk(KERN_INFO "ACK [%x--->%x] %s\n",initiator,receiver,cec_rxstatus(opcode));
++         }
++      }
++      else {
++         if (CEC_MSG_SUCCESS != opcode) {
++            printk(KERN_INFO "ACK [%x--->%x] %s\n",initiator,receiver,cec_rxstatus(opcode));
++         }
++      }
++
++      this->driver.poll_done = true;
++      wake_up_interruptible(&this->driver.wait);
++
++   }
++   else {
++      LOG(KERN_ERR,"Oups ! Callback got invalid event %d !\n",event);
++   }
++
++ TRY_DONE:
++   (void)err;
++}
++
++/*
++ *  DevLib CEC opening
++ */
++static int hdmi_cec_init(cec_instance *this)
++{
++   int err=0;
++
++   /* Real opening */
++   TRY(tmdlHdmiCecOpen(&this->cec.inst));
++
++/*    this->cec.vendor_id = 0x006037;   /\* NXP (IEEE OUI) *\/ */
++/*    this->cec.vendor_id = 0x0000f0;   /\* Samsung *\/ */
++   this->cec.vendor_id = 0x00e091;   /* LGE */
++
++/*    this->cec.version = CEC_VERSION_1_4; */
++   this->cec.version = CEC_VERSION_1_3a;
++   this->cec.osd_name.data[0]=0x54; /* TDA19989 by default */
++   this->cec.osd_name.data[1]=0x44;
++   this->cec.osd_name.data[2]=0x41;
++   this->cec.osd_name.data[3]=0x31;
++   this->cec.osd_name.data[4]=0x39;
++   this->cec.osd_name.data[5]=0x39;
++   this->cec.osd_name.data[6]=0x38;
++   this->cec.osd_name.data[7]=0x39;
++   this->cec.osd_name.length=8;
++   
++   TRY(tmdlHdmiCecRegisterCallbacks(this->cec.inst,eventCallbackCEC));
++       
++   this->cec.phy_addr = param_addr;
++   this->cec.device_type = device_type(param_device);
++
++ TRY_DONE:
++   return err;
++}
++
++
++/*
++ *
++ * ENTRY POINTS
++ * ------------
++ * LEVEL 3
++ *
++ * - 
++ *
++ */
++
++
++
++/*
++ *  ioctl driver :: opening
++ */
++
++static int this_cdev_open(struct inode *pInode, struct file *pFile)
++{
++   cec_instance *this;
++   int minor=iminor(pInode);
++
++   if(minor >= MAX_MINOR) {
++      printk(KERN_ERR "hdmicec:%s:only one cec opening please\n",__func__);
++      return -EINVAL;
++   }
++
++   if ((pFile->private_data != NULL) && (pFile->private_data != &our_instance)) {
++      printk(KERN_ERR "hdmicec:%s:pFile missmatch\n",__func__);
++   }
++   this = pFile->private_data = &our_instance;
++   down(&this->driver.sem);
++
++   LOG(KERN_INFO,"major:%d minor:%d user:%d\n", imajor(pInode), iminor(pInode), this->driver.user_counter);
++
++   if ((this->driver.user_counter++) && (this->driver.minor == minor)) {
++      /* init already done */
++      up(&this->driver.sem);
++      return 0;
++   }
++   this->driver.minor = minor;
++
++
++   up(&this->driver.sem);
++   return 0;
++}
++
++/*
++ *  ioctl driver :: ioctl
++ */
++static int this_cdev_ioctl(struct inode *pInode, struct file *pFile, unsigned int cmd, unsigned long arg)
++{
++   cec_instance* this = pFile->private_data;
++   int err=0;
++
++   LOG(KERN_INFO,":%s\n",cec_ioctl(_IOC_NR(cmd)));
++
++   BUG_ON(this->driver.minor!=iminor(pInode));
++   if (_IOC_TYPE(cmd) != CEC_IOCTL_BASE) {
++      printk(KERN_INFO "hdmicec:%s:unknown ioctl type: %x\n",__func__,_IOC_TYPE(cmd));
++      return -ENOIOCTLCMD;
++   }
++
++   if (_IOC_DIR(cmd) & _IOC_READ) 
++      err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd)) || !arg;
++   else if (_IOC_DIR(cmd) & _IOC_WRITE)
++      err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)) || !arg;
++   if (err) {
++      printk(KERN_ERR "hdmicec:%s:argument access denied (check address vs value)\n",__func__);
++      printk(KERN_ERR "_IOC_DIR:%d arg:%lx\n",_IOC_DIR(cmd),arg);
++      return -EFAULT;
++   }
++   
++   down(&this->driver.sem);
++
++   /* Check DevLib consistancy here */
++
++   switch ( _IOC_NR(cmd) )
++      {
++      case CEC_VERBOSE_ON_CMD:
++         {
++            printk(KERN_INFO "verbose on\n");
++            this->param.verbose=1;
++            break;
++         }
++
++      case CEC_VERBOSE_OFF_CMD:
++         {
++            printk(KERN_INFO "verbose off\n");
++            this->param.verbose=0;
++            break;
++         }
++
++      case CEC_BYEBYE_CMD:
++         {
++            LOG(KERN_INFO,"callback release request\n");
++            this->cec.frame.service=CEC_RELEASE;
++            this->driver.poll_done = true;
++            wake_up_interruptible(&this->driver.wait);
++            break;
++         }
++
++         /*
++           no param
++         */
++
++      case CEC_IOCTL_DISABLE_CALIBRATION_CMD:
++         {
++            TRY(tmdlHdmiCecDisableCalibration(this->cec.inst));
++            break;
++         }
++
++      case CEC_IOCTL_INSTANCE_CONFIG_CMD:
++         {
++            TRY(tmdlHdmiCecInstanceConfig(this->cec.inst));
++            break;
++         }
++
++      case CEC_IOCTL_REQUEST_ACTIVE_SRC_CMD:
++         {
++            TRY(tmdlHdmiCecRequestActiveSource(this->cec.inst));
++            break;
++         }
++
++      case CEC_IOCTL_ABORT_MSG_CMD:
++         {
++            TRY(tmdlHdmiCecAbortMessage(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_GET_MENU_LANGUAGE_CMD:
++         {
++            TRY(tmdlHdmiCecGetMenuLanguage(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_GIVE_AUDIO_STATUS_CMD:
++         {
++            TRY(tmdlHdmiCecGiveAudioStatus(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_GIVE_DEVICE_POWER_STATUS_CMD:
++         {
++            TRY(tmdlHdmiCecGiveDevicePowerStatus(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_GIVE_DEVICE_VENDOR_ID_CMD:
++         {
++            TRY(tmdlHdmiCecGiveDeviceVendorID(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_GIVE_OSD_NAME_CMD:
++         {
++            TRY(tmdlHdmiCecGiveOsdName(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_GIVE_PHY_ADDR_CMD:
++         {
++            TRY(tmdlHdmiCecGivePhysicalAddress(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_GIVE_SYS_AUDIO_MODE_STATUS_CMD:
++         {
++            TRY(tmdlHdmiCecGiveSystemAudioModeStatus(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_IMAGE_VIEW_ON_CMD:
++         {
++            TRY(tmdlHdmiCecImageViewOn(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_POLLING_MSG_CMD:
++         {
++            TRY(tmdlHdmiCecPollingMessage(this->cec.inst,this->cec.rx_addr));
++            break;
++         }
++
++      case CEC_IOCTL_REC_OFF_CMD:
++         {
++            TRY(tmdlHdmiCecRecordOff(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_REC_ON_OWN_SRC_CMD:
++         {
++            TRY(tmdlHdmiCecRecordOnOwnSource(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_REC_TV_SCREEN_CMD:
++         {
++            TRY(tmdlHdmiCecRecordTvScreen(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_STANDBY_CMD:
++         {
++            TRY(tmdlHdmiCecStandby(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_TEXT_VIEW_ON_CMD:
++         {
++            TRY(tmdlHdmiCecTextViewOn(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_TUNER_STEP_DECREMENT_CMD:
++         {
++            TRY(tmdlHdmiCecTunerStepDecrement(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_TUNER_STEP_INCREMENT_CMD:
++         {
++            TRY(tmdlHdmiCecTunerStepIncrement(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_USER_CTRL_RELEASED_CMD:
++         {
++            TRY(tmdlHdmiCecUserControlReleased(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_VENDOR_REMOTE_BUTTON_UP_CMD:
++         {
++            TRY(tmdlHdmiCecVendorRemoteButtonUp(this->cec.inst,this->cec.initiator));
++            break;
++         }
++
++      case CEC_IOCTL_ROUTING_INFORMATION_CMD:
++         {
++            TRY(tmdlHdmiCecRoutingInformation(this->cec.inst,this->cec.phy_addr));
++            break;
++         }
++
++      case CEC_IOCTL_SET_STREAM_PATH_CMD:
++         {
++            TRY(tmdlHdmiCecSetStreamPath(this->cec.inst,this->cec.phy_addr));
++            break;
++         }
++
++      case CEC_IOCTL_ACTIVE_SRC_CMD:
++         {
++            /* NEW first do a <image view on> */
++            /* NEW when switch by DSS and was inactive */
++            TRY(tmdlHdmiCecActiveSource(this->cec.inst,this->cec.phy_addr));
++            break;
++         }
++
++      case CEC_IOCTL_SYS_AUDIO_MODE_REQUEST_CMD:
++         {
++            TRY(tmdlHdmiCecSystemAudioModeRequest(this->cec.inst, \
++                                                  this->cec.initiator, \
++                                                  this->cec.phy_addr));
++            break;
++         }
++
++         /*
++           1 param
++         */
++
++      case CEC_IOCTL_RX_ADDR_CMD:
++         {
++            /* 	    BUG_ON(copy_from_user(&this->cec.rx_addr,(unsigned char*)arg,sizeof(unsigned char)) != 0); */
++            this->cec.rx_addr=arg;
++            TRY(tmdlHdmiCecSetLogicalAddress(this->cec.inst,this->cec.rx_addr));
++            break;
++         }
++
++      case CEC_IOCTL_PHY_ADDR_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.phy_addr,(unsigned short*)arg,sizeof(unsigned short)) != 0);
++            break;
++         }
++
++      case CEC_IOCTL_GET_CEC_VERSION_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.version,(cec_version*)arg,sizeof(cec_version)) != 0);
++            TRY(tmdlHdmiCecGetCecVersion(this->cec.inst,this->cec.version));
++            break;
++         }
++
++      case CEC_IOCTL_GET_SW_VERSION_CMD:
++         {
++            TRY(tmdlHdmiCecGetSWVersion(&this->cec.sw_version));
++            BUG_ON(copy_to_user((cec_sw_version*)arg,&this->cec.sw_version,sizeof(cec_sw_version)) != 0);
++            break;
++         }
++
++      case CEC_IOCTL_SET_POWER_STATE_CMD:
++         {
++            /* NEW : log : please use DSS */
++            BUG_ON(copy_from_user(&this->cec.power,(cec_power*)arg,sizeof(cec_power)) != 0);
++            TRY(tmdlHdmiCecSetPowerState(this->cec.inst,this->cec.power));
++            break;
++         }
++
++      case CEC_IOCTL_GET_POWER_STATE_CMD:
++         {
++            TRY(tmdlHdmiCecGetPowerState(this->cec.inst,&this->cec.power));
++            BUG_ON(copy_to_user((cec_power*)arg,&this->cec.power,sizeof(cec_power)) != 0);
++            break;
++         }
++
++      case CEC_IOCTL_INSTANCE_SETUP_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.setup,(cec_setup*)arg,sizeof(cec_setup)) != 0);
++            TRY(tmdlHdmiCecInstanceSetup(this->cec.inst,&this->cec.setup));
++            break;
++         }
++
++      case CEC_IOCTL_GET_INSTANCE_SETUP_CMD:
++         {
++            TRY(tmdlHdmiCecGetInstanceSetup(this->cec.inst,&this->cec.setup));
++            BUG_ON(copy_to_user((cec_setup*)arg,&this->cec.setup,sizeof(cec_setup)) != 0);
++            break;
++         }
++
++         /*
++           case CEC_IOCTL_ENABLE_EVENT_CMD:
++           {
++           BUG_ON(copy_from_user(&this->cec.an_event,(cec_event*)arg,sizeof(cec_event)) != 0);
++           TRY(tmdlHdmiCecEnableEvent(this->cec.inst,this->cec.an_event));
++           break;
++           }
++
++           case CEC_IOCTL_DISABLE_EVENT_CMD:
++           {
++           BUG_ON(copy_from_user(&this->cec.an_event,(cec_event*)arg,sizeof(cec_event)) != 0);
++           TRY(tmdlHdmiCecDisableEvent(this->cec.inst,this->cec.an_event));
++           break;
++           }
++         */
++
++      case CEC_IOCTL_SET_MENU_LANGUAGE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.clock,(cec_string*)arg,sizeof(cec_string)) != 0);
++            TRY(tmdlHdmiCecSetMenuLanguage(this->cec.inst,this->cec.string.data));
++            break;
++         }
++
++      case CEC_IOCTL_ENABLE_CALIBRATION_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.clock,(cec_clock*)arg,sizeof(cec_clock)) != 0);
++            TRY(tmdlHdmiCecEnableCalibration(this->cec.inst,this->cec.clock));
++            break;
++         }
++
++         /*
++           >1 param
++         */
++
++      case CEC_IOCTL_WAIT_FRAME_CMD:
++         {
++            this->cec.frame.service = CEC_WAITING;
++            this->driver.poll_done = false;
++            up(&this->driver.sem);
++            if (wait_event_interruptible(this->driver.wait,this->driver.poll_done)) return -ERESTARTSYS;
++            down(&this->driver.sem);
++            BUG_ON(copy_to_user((cec_frame*)arg,&this->cec.frame,sizeof(cec_frame)) != 0);
++            break;
++         }
++
++      case CEC_IOCTL_VERSION_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.version,(cec_version*)arg,sizeof(cec_version)) != 0);
++            TRY(tmdlHdmiCecVersion(this->cec.inst, \
++                                   this->cec.initiator, \
++                                   this->cec.version));
++            break;
++         }
++
++      case CEC_IOCTL_CLEAR_ANALOGUE_TIMER_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.analog_timer,(cec_analogue_timer*)arg,sizeof(cec_analogue_timer)) != 0);
++            TRY(tmdlHdmiCecClearAnalogueTimer(this->cec.inst, \
++                                              this->cec.initiator, \
++                                              this->cec.analog_timer.DayOfMonth, \
++                                              this->cec.analog_timer.MonthOfYear, \
++                                              this->cec.analog_timer.StartTime, \
++                                              &this->cec.analog_timer.Duration, \
++                                              this->cec.analog_timer.RecordingSequence, \
++                                              this->cec.analog_timer.AnalogueBroadcastType, \
++                                              this->cec.analog_timer.AnalogueFrequency, \
++                                              this->cec.analog_timer.BroadcastSystem));
++            break;
++         }
++
++      case CEC_IOCTL_CLEAR_DIGITAL_TIMER_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.digital_timer,(cec_digital_timer*)arg,sizeof(cec_digital_timer)) != 0);
++            TRY(tmdlHdmiCecClearDigitalTimer(this->cec.inst, \
++                                             this->cec.initiator, \
++                                             this->cec.digital_timer.DayOfMonth, \
++                                             this->cec.digital_timer.MonthOfYear, \
++                                             this->cec.digital_timer.StartTime, \
++                                             &this->cec.digital_timer.Duration, \
++                                             this->cec.digital_timer.RecordingSequence, \
++                                             &this->cec.digital_timer.ServiceIdentification));
++            break;
++         }
++
++      case CEC_IOCTL_CLEAR_EXT_TIMER_WITH_EXT_PLUG_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.etwep,(cec_ext_timer_with_ext_plug*)arg,sizeof(cec_ext_timer_with_ext_plug)) != 0);
++            TRY(tmdlHdmiCecClearExternalTimerWithExternalPlug(this->cec.inst, \
++                                                              this->cec.initiator, \
++                                                              this->cec.etwep.DayOfMonth, \
++                                                              this->cec.etwep.MonthOfYear, \
++                                                              this->cec.etwep.StartTime, \
++                                                              &this->cec.etwep.Duration, \
++                                                              this->cec.etwep.RecordingSequence, \
++                                                              this->cec.etwep.ExternalPlug));
++            break;
++         }
++
++      case CEC_IOCTL_CLEAR_EXT_TIMER_WITH_PHY_ADDR_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.etwpa,(cec_ext_timer_with_phy_addr*)arg,sizeof(cec_ext_timer_with_phy_addr)) != 0);
++            TRY(tmdlHdmiCecClearExternalTimerWithPhysicalAddress(this->cec.inst, \
++                                                                 this->cec.initiator, \
++                                                                 this->cec.etwpa.DayOfMonth, \
++                                                                 this->cec.etwpa.MonthOfYear, \
++                                                                 this->cec.etwpa.StartTime, \
++                                                                 &this->cec.etwpa.Duration, \
++                                                                 this->cec.etwpa.RecordingSequence, \
++                                                                 this->cec.etwpa.ExternalPhysicalAddress));
++            break;
++         }
++
++      case CEC_IOCTL_DECK_CTRL_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.deck_ctrl,(cec_deck_ctrl*)arg,sizeof(cec_deck_ctrl)) != 0);
++            TRY(tmdlHdmiCecDeckControl(this->cec.inst, \
++                                       this->cec.initiator, \
++                                       this->cec.deck_ctrl));
++            break;
++         }
++
++      case CEC_IOCTL_DECK_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.deck_status,(cec_deck_status*)arg,sizeof(cec_deck_status)) != 0);
++            TRY(tmdlHdmiCecDeckStatus(this->cec.inst, \
++                                      this->cec.initiator, \
++                                      this->cec.deck_status));
++            break;
++         }
++
++      case CEC_IOCTL_DEVICE_VENDOR_ID_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.vendor_id,(unsigned long*)arg,sizeof(unsigned long)) != 0);
++            TRY(tmdlHdmiCecDeviceVendorID(this->cec.inst, \
++                                          this->cec.vendor_id));
++            break;
++         }
++
++      case CEC_IOCTL_FEATURE_ABORT_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.feature_abort,(cec_feature_abort*)arg,sizeof(cec_feature_abort)) != 0);
++            TRY(tmdlHdmiCecFeatureAbort(this->cec.inst, \
++                                        this->cec.initiator, \
++                                        this->cec.feature_abort.FeatureOpcode, \
++                                        this->cec.feature_abort.AbortReason));
++            break;
++         }
++
++      case CEC_IOCTL_GIVE_DECK_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.satus_request,(cec_status_request*)arg,sizeof(cec_status_request)) != 0);
++            TRY(tmdlHdmiCecGiveDeckStatus(this->cec.inst, \
++                                          this->cec.initiator, \
++                                          this->cec.satus_request));
++            break;
++         }
++
++      case CEC_IOCTL_GIVE_TUNER_DEVICE_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.satus_request,(cec_status_request*)arg,sizeof(cec_status_request*)) != 0);
++            TRY(tmdlHdmiCecGiveTunerDeviceStatus(this->cec.inst, \
++                                                 this->cec.initiator, \
++                                                 this->cec.satus_request));
++            break;
++         }
++
++      case CEC_IOCTL_INACTIVE_SRC_CMD:
++         {
++            /* NEW first stand by video */
++            /* NEW when hdmi_disable and was active */
++            TRY(tmdlHdmiCecInactiveSource(this->cec.inst, \
++                                          this->cec.initiator, \
++                                          this->cec.phy_addr));
++            break;
++         }
++
++      case CEC_IOCTL_MENU_REQUEST_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.menu_request,(cec_menu_request*)arg,sizeof(cec_menu_request)) != 0);
++            TRY(tmdlHdmiCecMenuRequest(this->cec.inst, \
++                                       this->cec.initiator, \
++                                       this->cec.menu_request));
++            break;
++         }
++
++      case CEC_IOCTL_MENU_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.menu_status,(cec_menu_status*)arg,sizeof(cec_menu_status)) != 0);
++            TRY(tmdlHdmiCecMenuStatus(this->cec.inst, \
++                                      this->cec.initiator, \
++                                      this->cec.menu_status));
++            break;
++         }
++
++      case CEC_IOCTL_PLAY_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.play,(cec_play*)arg,sizeof(cec_play)) != 0);
++            TRY(tmdlHdmiCecPlay(this->cec.inst, \
++                                this->cec.initiator, \
++                                this->cec.play));
++            break;
++         }
++
++      case CEC_IOCTL_REC_ON_ANALOGUE_SERVICE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.analog_service,(cec_analogue_service*)arg,sizeof(cec_analogue_service)) != 0);
++            TRY(tmdlHdmiCecRecordOnAnalogueService(this->cec.inst, \
++                                                   this->cec.initiator, \
++                                                   this->cec.analog_service.AnalogueBroadcastType, \
++                                                   this->cec.analog_service.AnalogueFrequency, \
++                                                   this->cec.analog_service.BroadcastSystem));
++            break;
++         }
++
++      case CEC_IOCTL_REC_ON_DIGITAL_SERVICE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.digital_service,(cec_digital_service*)arg,sizeof(cec_digital_service)) != 0);
++            TRY(tmdlHdmiCecRecordOnDigitalService(this->cec.inst, \
++                                                  this->cec.initiator, \
++                                                  &this->cec.digital_service));
++            break;
++         }
++
++      case CEC_IOCTL_REC_ON_EXT_PHY_ADDR_CMD:
++         {
++            TRY(tmdlHdmiCecRecordOnExternalPhysicalAddress(this->cec.inst, \
++                                                           this->cec.initiator, \
++                                                           this->cec.phy_addr));
++            break;
++         }
++
++      case CEC_IOCTL_REC_ON_EXT_PLUG_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.ext_plug,(cec_ext_plug*)arg,sizeof(cec_ext_plug)) != 0);
++            TRY(tmdlHdmiCecRecordOnExternalPlug(this->cec.inst, \
++                                                this->cec.initiator, \
++                                                this->cec.ext_plug));
++            break;
++         }
++
++      case CEC_IOCTL_REC_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.rec_status,(cec_rec_status*)arg,sizeof(cec_rec_status)) != 0);
++            TRY(tmdlHdmiCecRecordStatus(this->cec.inst, \
++                                        this->cec.initiator, \
++                                        this->cec.rec_status));
++            break;
++         }
++
++      case CEC_IOCTL_REPORT_AUDIO_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.audio_status,(cec_audio_status*)arg,sizeof(cec_audio_status)) != 0);
++            TRY(tmdlHdmiCecReportAudioStatus(this->cec.inst, \
++                                             this->cec.initiator, \
++                                             &this->cec.audio_status));
++            break;
++         }
++
++      case CEC_IOCTL_REPORT_PHY_ADDR_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.device_type,(cec_device_type*)arg,sizeof(cec_device_type)) != 0);
++            TRY(tmdlHdmiCecReportPhysicalAddress(this->cec.inst, \
++                                                 this->cec.phy_addr, \
++                                                 this->cec.device_type));
++            break;
++         }
++
++      case CEC_IOCTL_REPORT_POWER_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.source_status,(cec_power_status*)arg,sizeof(cec_power_status)) != 0);
++            TRY(tmdlHdmiCecReportPowerStatus(this->cec.inst, \
++                                             this->cec.initiator, \
++                                             this->cec.source_status));
++            break;
++         }
++
++      case CEC_IOCTL_SELECT_ANALOGUE_SERVICE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.analog_service,(cec_analogue_service*)arg,sizeof(cec_analogue_service)) != 0);
++            TRY(tmdlHdmiCecSelectAnalogueService(this->cec.inst, \
++                                                 this->cec.initiator, \
++                                                 this->cec.analog_service.AnalogueBroadcastType, \
++                                                 this->cec.analog_service.AnalogueFrequency, \
++                                                 this->cec.analog_service.BroadcastSystem));
++            break;
++         }
++
++      case CEC_IOCTL_SELECT_DIGITAL_SERVICE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.digital_service,(cec_digital_service*)arg,sizeof(cec_digital_service)) != 0);
++            TRY(tmdlHdmiCecSelectDigitalService(this->cec.inst, \
++                                                this->cec.initiator, \
++                                                &this->cec.digital_service));
++            break;
++         }
++
++      case CEC_IOCTL_SET_ANALOGUE_TIMER_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.analog_timer,(cec_analogue_timer*)arg,sizeof(cec_analogue_timer)) != 0);
++            TRY(tmdlHdmiCecSetAnalogueTimer(this->cec.inst, \
++                                            this->cec.initiator, \
++                                            this->cec.analog_timer.DayOfMonth, \
++                                            this->cec.analog_timer.MonthOfYear, \
++                                            this->cec.analog_timer.StartTime, \
++                                            &this->cec.analog_timer.Duration, \
++                                            this->cec.analog_timer.RecordingSequence, \
++                                            this->cec.analog_timer.AnalogueBroadcastType, \
++                                            this->cec.analog_timer.AnalogueFrequency, \
++                                            this->cec.analog_timer.BroadcastSystem));
++            break;
++         }
++
++      case CEC_IOCTL_SET_AUDIO_RATE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.audio_rate,(cec_audio_rate*)arg,sizeof(cec_audio_rate)) != 0);
++            TRY(tmdlHdmiCecSetAudioRate(this->cec.inst, \
++                                        this->cec.initiator, \
++                                        this->cec.audio_rate));
++            break;
++         }
++
++      case CEC_IOCTL_SET_DIGITAL_TIMER_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.digital_timer,(cec_digital_timer*)arg,sizeof(cec_digital_timer)) != 0);
++            TRY(tmdlHdmiCecSetDigitalTimer(this->cec.inst, \
++                                           this->cec.initiator, \
++                                           this->cec.digital_timer.DayOfMonth, \
++                                           this->cec.digital_timer.MonthOfYear, \
++                                           this->cec.digital_timer.StartTime, \
++                                           &this->cec.digital_timer.Duration, \
++                                           this->cec.digital_timer.RecordingSequence, \
++                                           &this->cec.digital_timer.ServiceIdentification));
++            break;
++         }
++
++      case CEC_IOCTL_SET_EXT_TIMER_WITH_EXT_PLUG_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.etwep,(cec_ext_timer_with_ext_plug*)arg,sizeof(cec_ext_timer_with_ext_plug)) != 0);
++            TRY(tmdlHdmiCecSetExternalTimerWithExternalPlug(this->cec.inst, \
++                                                            this->cec.initiator, \
++                                                            this->cec.etwep.DayOfMonth, \
++                                                            this->cec.etwep.MonthOfYear, \
++                                                            this->cec.etwep.StartTime, \
++                                                            &this->cec.etwep.Duration, \
++                                                            this->cec.etwep.RecordingSequence, \
++                                                            this->cec.etwep.ExternalPlug));
++            break;
++         }
++
++      case CEC_IOCTL_SET_EXT_TIMER_WITH_PHY_ADDR_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.etwpa,(cec_ext_timer_with_phy_addr*)arg,sizeof(cec_ext_timer_with_phy_addr)) != 0);
++            TRY(tmdlHdmiCecSetExternalTimerWithPhysicalAddress(this->cec.inst, \
++                                                               this->cec.initiator, \
++                                                               this->cec.etwpa.DayOfMonth, \
++                                                               this->cec.etwpa.MonthOfYear, \
++                                                               this->cec.etwpa.StartTime, \
++                                                               &this->cec.etwpa.Duration, \
++                                                               this->cec.etwpa.RecordingSequence, \
++                                                               this->cec.etwpa.ExternalPhysicalAddress));
++            break;
++         }
++
++      case CEC_IOCTL_SET_SYS_AUDIO_MODE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.sys_audio_status,(cec_sys_audio_status*)arg,sizeof(cec_sys_audio_status)) != 0);
++            TRY(tmdlHdmiCecSetSystemAudioMode(this->cec.inst, \
++                                              this->cec.initiator, \
++                                              this->cec.sys_audio_status));
++            break;
++         }
++
++      case CEC_IOCTL_SYS_AUDIO_MODE_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.sys_audio_status,(cec_sys_audio_status*)arg,sizeof(cec_sys_audio_status)) != 0);
++            TRY(tmdlHdmiCecSystemAudioModeStatus(this->cec.inst, \
++                                                 this->cec.initiator, \
++                                                 this->cec.sys_audio_status));
++            break;
++         }
++
++      case CEC_IOCTL_TIMER_CLEARED_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.timer_cleared_status,(cec_timer_cleared_status*)arg,sizeof(cec_timer_cleared_status)) != 0);
++            TRY(tmdlHdmiCecTimerClearedStatus(this->cec.inst, \
++                                              this->cec.initiator, \
++                                              this->cec.timer_cleared_status));
++            break;
++         }
++
++      case CEC_IOCTL_TIMER_STATUS_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.timer_status,(cec_timer_status*)arg,sizeof(cec_timer_status)) != 0);
++            TRY(tmdlHdmiCecTimerStatus(this->cec.inst, \
++                                       this->cec.initiator, \
++                                       &this->cec.timer_status));
++            break;
++         }
++
++      case CEC_IOCTL_TUNER_DEVICE_STATUS_ANALOGUE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.tdsa,(cec_tuner_device_status_analogue*)arg,sizeof(cec_tuner_device_status_analogue)) != 0);
++            TRY(tmdlHdmiCecTunerDeviceStatusAnalogue(this->cec.inst, \
++                                                     this->cec.initiator, \
++                                                     this->cec.tdsa.RecordingFlag, \
++                                                     this->cec.tdsa.TunerDisplayInfo, \
++                                                     this->cec.tdsa.AnalogueBroadcastType, \
++                                                     this->cec.tdsa.AnalogueFrequency, \
++                                                     this->cec.tdsa.BroadcastSystem));
++            break;
++         }
++
++      case CEC_IOCTL_TUNER_DEVICE_STATUS_DIGITAL_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.tdsd,(cec_tuner_device_status_digital*)arg,sizeof(cec_tuner_device_status_digital)) != 0);
++            TRY(tmdlHdmiCecTunerDeviceStatusDigital(this->cec.inst, \
++                                                    this->cec.initiator, \
++                                                    this->cec.tdsd.RecordingFlag, \
++                                                    this->cec.tdsd.TunerDisplayInfo, \
++                                                    &this->cec.tdsd.ServiceIdentification));
++            break;
++         }
++
++      case CEC_IOCTL_USER_CTRL_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.user_ctrl,(cec_user_ctrl*)arg,sizeof(cec_user_ctrl)) != 0);
++            TRY(tmdlHdmiCecUserControlPressed(this->cec.inst, \
++                                              this->cec.initiator, \
++                                              this->cec.user_ctrl));
++            break;
++         }
++
++      case CEC_IOCTL_USER_CTRL_PLAY_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.play,(cec_play*)arg,sizeof(cec_play)) != 0);
++            TRY(tmdlHdmiCecUserControlPressedPlay(this->cec.inst, \
++                                                  this->cec.initiator, \
++                                                  this->cec.play));
++            break;
++         }
++
++      case CEC_IOCTL_USER_CTRL_SELECT_AUDIOINPUT_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.select,(unsigned char*)arg,sizeof(unsigned char)) != 0);
++            TRY(tmdlHdmiCecUserControlPressedSelectAudioInput(this->cec.inst, \
++                                                              this->cec.initiator, \
++                                                              this->cec.select));
++            break;
++         }
++
++      case CEC_IOCTL_USER_CTRL_SELECT_AVINPUT_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.select,(unsigned char*)arg,sizeof(unsigned char)) != 0);
++            TRY(tmdlHdmiCecUserControlPressedSelectAVInput(this->cec.inst, \
++                                                           this->cec.initiator, \
++                                                           this->cec.select));
++            break;
++         }
++
++      case CEC_IOCTL_USER_CTRL_SELECT_MEDIA_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.select,(unsigned char*)arg,sizeof(unsigned char)) != 0);
++            TRY(tmdlHdmiCecUserControlPressedSelectMedia(this->cec.inst, \
++                                                         this->cec.initiator, \
++                                                         this->cec.select));
++            break;
++         }
++
++      case CEC_IOCTL_USER_CTRL_TUNE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.user_ctrl_tune,(cec_user_ctrl_tune*)arg,sizeof(cec_user_ctrl_tune)) != 0);
++            TRY(tmdlHdmiCecUserControlPressedTune(this->cec.inst, \
++                                                  this->cec.initiator, \
++                                                  &this->cec.user_ctrl_tune));
++            break;
++         }
++
++      case CEC_IOCTL_SET_OSD_NAME_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.osd_name,(cec_string*)arg,sizeof(cec_string)) != 0);
++            TRY(tmdlHdmiCecSetOsdName(this->cec.inst,      \
++                                      this->cec.initiator, \
++                                      this->cec.osd_name.data, \
++                                      this->cec.osd_name.length));
++            break;
++         }
++
++      case CEC_IOCTL_SET_OSD_STRING_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.osd_string,(cec_osd_string*)arg,sizeof(cec_osd_string)) != 0);
++            TRY(tmdlHdmiCecSetOsdString(this->cec.inst, \
++                                        this->cec.initiator, \
++                                        this->cec.osd_string.DisplayControl, \
++                                        this->cec.osd_string.data, \
++                                        this->cec.osd_string.length));
++            break;
++         }
++
++      case CEC_IOCTL_SET_TIMER_PROGRAM_TITLE_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.string,(cec_string*)arg,sizeof(cec_string)) != 0);
++            TRY(tmdlHdmiCecSetTimerProgramTitle(this->cec.inst, \
++                                                this->cec.initiator, \
++                                                this->cec.string.data, \
++                                                this->cec.string.length));
++            break;
++         }
++
++      case CEC_IOCTL_VENDOR_COMMAND_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.string,(cec_string*)arg,sizeof(cec_string)) != 0);
++            TRY(tmdlHdmiCecVendorCommand(this->cec.inst, \
++                                         this->cec.initiator, \
++                                         this->cec.string.data, \
++                                         this->cec.string.length));
++            break;
++         }
++
++      case CEC_IOCTL_VENDOR_REMOTE_BUTTON_DOWN_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.string,(cec_string*)arg,sizeof(cec_string)) != 0);
++            TRY(tmdlHdmiCecVendorRemoteButtonDown(this->cec.inst, \
++                                                  this->cec.initiator, \
++                                                  this->cec.string.data, \
++                                                  this->cec.string.length));
++            break;
++         }
++
++      case CEC_IOCTL_VENDOR_COMMAND_WITH_ID_CMD:
++         {
++            BUG_ON(copy_from_user(&this->cec.vcwi,(cec_vendor_command_with_id*)arg,sizeof(cec_vendor_command_with_id)) != 0);
++            TRY(tmdlHdmiCecVendorCommandWithID(this->cec.inst,	\
++                                               this->cec.initiator,	\
++                                               this->cec.vcwi.VendorID, \
++                                               this->cec.vcwi.cmd.data, \
++                                               this->cec.vcwi.cmd.length));
++            break;
++         }
++
++         /*       case : */
++         /* 	 { */
++         /* 	    BUG_ON(copy_from_user(&this->cec.,(*)arg,sizeof()) != 0); */
++         /* 	    TRY((this->cec.inst, \ */
++         /* 		 this->cec.,	 \ */
++         /* 		 &this->cec.)); */
++         /* 	    break; */
++         /* 	 } */
++
++      default:
++         {
++            /* unrecognized ioctl */	
++            printk(KERN_INFO " unknown ioctl %x\n",cmd);
++            up(&this->driver.sem);
++            return -ENOIOCTLCMD;
++         }
++      }
++
++ TRY_DONE:
++   up(&this->driver.sem);
++   return err;
++}
++
++/*
++ *  ioctl driver :: releasing
++ */
++static int this_cdev_release(struct inode *pInode, struct file *pFile)
++{
++   cec_instance* this = pFile->private_data;
++   int minor = iminor(pInode);
++
++   LOG(KERN_INFO,"called\n");
++
++   if(minor >= MAX_MINOR) {
++      return -EINVAL;
++   }
++
++   BUG_ON(this->driver.minor!=iminor(pInode));
++   down(&this->driver.sem);
++
++   this->driver.user_counter--;
++   if(this->driver.user_counter == 0) {
++      pFile->private_data = NULL;
++   }
++   else {
++      LOG(KERN_INFO,"Still %d user pending\n",this->driver.user_counter);
++   }
++
++   up(&this->driver.sem);
++   return 0;
++}
++
++/*
++ *  I2C client :: creation
++ */
++static int __devinit this_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++   cec_instance *this=&our_instance;
++   int err=0;
++
++   LOG(KERN_INFO,"called\n");
++
++   /*
++     I2C setup
++   */
++   if (this->driver.i2c_client) {
++      dev_err(&this->driver.i2c_client->dev, "<%s> CEC Device already created \n",
++              __func__);
++      return -ENODEV;
++   }
++
++   this->driver.i2c_client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
++   if (!this->driver.i2c_client) {
++      return -ENOMEM;
++   }
++   memset(this->driver.i2c_client, 0, sizeof(struct i2c_client));
++
++   strncpy(this->driver.i2c_client->name, CEC_NAME, I2C_NAME_SIZE);
++   this->driver.i2c_client->addr = TDA99XCEC_I2C_SLAVEADDRESS;
++   this->driver.i2c_client->adapter = client->adapter;
++
++   i2c_set_clientdata(client, this->driver.i2c_client);
++
++   tmdlHdmiCecGetSWVersion(&this->cec.sw_version);
++   LOG(KERN_INFO,"HDMI CEC SW Version:%lu.%lu compatibility:%lu\n", \
++       this->cec.sw_version.majorVersionNr,\
++       this->cec.sw_version.minorVersionNr,\
++       this->cec.sw_version.compatibilityNr);
++
++   /* I2C ok, then let's startup CEC */
++
++   /* prepare event */
++   this->driver.poll_done = true; /* currently idle */
++   init_waitqueue_head(&this->driver.wait);
++#ifndef IRQ
++   init_timer(&this->driver.timer); /* do it before request_irq */
++   this->driver.timer.function=polling_timeout;
++   this->driver.timer.data=0;
++   this->driver.timer.expires = jiffies + HZ; /* start polling in one sec */
++   add_timer(&this->driver.timer);
++#else
++   register_cec_interrupt((cec_callback_t)cec_interrupt);
++#endif
++
++#ifndef IRQ
++   /* FRO calibration */
++   err=gpio_request(TDA_IRQ_CALIB,"tda19989 calibration");
++   if (err < 0) {
++      printk(KERN_ERR "hdmicec:%s:cannot use GPIO 107\n",__func__);
++      goto i2c_out;
++   }
++   /* turn GPIO into IRQ
++   gpio_direction_input(TDA_IRQ_CALIB);
++   msleep(1);
++   if (request_irq(gpio_to_irq(TDA_IRQ_CALIB), \
++                   tda_irq, IRQF_TRIGGER_FALLING|IRQF_DISABLED, "TDA IRQ", NULL)) {
++      printk(KERN_ERR "hdmicec:%s:Cannot request irq, err:%d\n",__func__,err);
++      gpio_free(TDA_IRQ_CALIB);
++      goto i2c_out;
++   }
++   */
++#endif
++
++   err = hdmi_cec_init(this);
++   if (err) goto i2c_out;
++   this->cec.rx_addr=CEC_LOGICAL_ADDRESS_UNREGISTRED_BROADCAST;
++
++   if (get_hpd_status()) {
++      cec_on(this);
++      // disable_irq(gpio_to_irq(TDA_IRQ_CALIB));
++      cec_interrupt(NULL); /* initiate polling */
++      // enable_irq(gpio_to_irq(TDA_IRQ_CALIB));
++   }
++   else {
++      cec_standby(this);
++   }
++
++   return 0;
++
++ i2c_out:
++   LOG(KERN_INFO,"HDMICEC eject: this->driver.i2c_client removed\n");
++   tmdlHdmiCecClose(this->cec.inst);
++   kfree(this->driver.i2c_client);
++   this->driver.i2c_client = NULL;
++
++   return err;
++}
++
++/*
++ *  I2C client :: destroy
++ */
++static int this_i2c_remove(struct i2c_client *client)
++{
++   cec_instance *this=&our_instance;
++   int err=0;
++
++   LOG(KERN_INFO,"called\n");
++
++   err=tmdlHdmiCecClose(this->cec.inst);
++
++   if (!client->adapter) {
++      dev_err(&this->driver.i2c_client->dev, "<%s> No CEC Device \n",
++              __func__);
++      return -ENODEV;
++   }
++   kfree(this->driver.i2c_client);
++   this->driver.i2c_client = NULL;
++
++   return err;
++}
++
++/*
++ *  I2C client driver (backend)
++ *  -----------------
++ */
++static struct i2c_driver this_i2c_driver = {
++   .driver = {
++      .owner = THIS_MODULE,
++      .name = CEC_NAME,
++   },
++   .probe = this_i2c_probe,
++   .remove = this_i2c_remove,
++   .id_table = this_i2c_id,
++};
++
++/*
++ *  ioctl driver (userland frontend)
++ *  ------------
++ */
++static struct file_operations this_cdev_fops = {
++ owner:    THIS_MODULE,
++ open:     this_cdev_open,
++ release:  this_cdev_release,
++// ioctl:    this_cdev_ioctl,
++};
++
++/*
++ *  Module :: start up
++ */
++static int __init cec_init(void)
++{
++   cec_instance *this=&our_instance;
++   dev_t dev=0;
++   int err=0;
++
++   /* 
++      general device context
++   */
++   memset(this,0,sizeof(cec_instance));
++   this->param.verbose = param_verbose;
++   this->param.major = param_major;
++   this->param.minor = param_minor;
++
++   /* Hello word */
++   printk(KERN_INFO "%s(%s) %d.%d.%d compiled: %s %s %s\n", HDMICEC_NAME, TDA_NAME, TDA_VERSION_MAJOR,
++          TDA_VERSION_MINOR, TDA_VERSION_PATCHLEVEL, __DATE__, __TIME__, TDA_VERSION_EXTRA);
++   if (this->param.verbose) LOG(KERN_INFO,".verbose mode\n");
++
++   /*
++     plug I2C (backend : Hw interfacing)
++   */
++   err = i2c_add_driver(&this_i2c_driver);
++   if (err < 0) {
++      printk(KERN_ERR "Driver registration failed\n");
++      return -ENODEV;
++   }
++
++   if (this->driver.i2c_client == NULL) {
++      printk(KERN_ERR "this->driver.i2c_client not allocated\n");
++      err = -ENODEV;
++      goto init_out;
++   }
++
++   /*
++     cdev init (userland frontend)
++   */
++
++   /* arbitray range of device numbers */
++   if (this->param.major) {
++      /* user force major number @ insmod */
++      dev = MKDEV(this->param.major, this->param.minor);
++      err = register_chrdev_region(dev,MAX_MINOR,HDMICEC_NAME);
++      if (err) {
++         printk(KERN_ERR "unable to register %s, dev=%d %s\n",HDMICEC_NAME,dev,ERR_TO_STR(err));
++         goto init_out;
++      }
++   } else {
++      /* fully dynamic major number */
++      err = alloc_chrdev_region(&dev, this->param.minor, MAX_MINOR,HDMICEC_NAME);
++      if (err) {
++         printk(KERN_ERR "unable to alloc chrdev region for %s, dev=%d %s\n",HDMICEC_NAME,dev,ERR_TO_STR(err));
++         goto init_out;
++      }
++      this->param.major = MAJOR(dev);
++   }
++
++   cdev_init(this_cdev, &this_cdev_fops);
++   this_cdev->owner = THIS_MODULE;
++
++   this->driver.class = class_create(THIS_MODULE, HDMICEC_NAME);
++   if (IS_ERR(this->driver.class)) {
++      printk(KERN_INFO "Error creating mmap device class.\n");
++      err =-EIO;
++      goto init_out;
++   }
++   this->driver.dev = device_create(this->driver.class, NULL, dev, NULL, HDMICEC_NAME);
++
++   this->driver.devno = dev;
++   err = cdev_add(this_cdev, this->driver.devno, MAX_MINOR);
++   if (err){
++      printk(KERN_INFO "unable to add device for %s, ipp_driver.devno=%d %s\n",HDMICEC_NAME,this->driver.devno,ERR_TO_STR(err));
++      device_destroy(this->driver.class,this->driver.devno);
++      class_destroy(this->driver.class);
++      unregister_chrdev_region(this->driver.devno, MAX_MINOR);
++      goto init_out;
++   }   
++
++#ifdef TWL4030_HACK
++   /* AL : hack to bypass keypad */
++   gkp_input = get_twm4030_input();
++#endif
++
++   /* 
++      general device context
++   */
++   sema_init(&this->driver.sem, 1);
++   this->driver.deinit_req=0;
++   
++   return 0;
++
++ init_out:
++   i2c_del_driver(&this_i2c_driver);
++   return err;
++}
++
++/*
++ *  Module :: shut down
++ */
++static void __exit cec_exit(void)
++{
++   cec_instance *this=&our_instance;
++   
++   LOG(KERN_INFO,"called\n");
++   
++#ifndef IRQ
++   // free_irq(gpio_to_irq(TDA_IRQ_CALIB), NULL);
++#endif
++   
++   unregister_cec_interrupt();
++   this->driver.deinit_req=1;
++#ifndef IRQ
++   if (wait_event_interruptible(this->driver.wait,this->driver.deinit_req>1)) {
++      /* oups... just wait... */
++      msleep(CHECK_EVERY_XX_MS*20);
++   }
++#endif
++   
++#ifndef IRQ
++   /* release GPIO */ 
++   gpio_free(TDA_IRQ_CALIB);
++#endif
++
++   /* unregister cdevice */
++   cdev_del(this_cdev);
++   unregister_chrdev_region(this->driver.devno, MAX_MINOR);
++
++   /* unregister device */
++   device_destroy(this->driver.class,this->driver.devno);
++   class_destroy(this->driver.class);
++
++   /* unregister i2c */
++   i2c_del_driver(&this_i2c_driver);
++
++}
++
++
++/*
++ *  Module
++ *  ------
++ */
++/* late_initcall(cec_init); */
++module_init(cec_init);
++module_exit(cec_exit);
++
++/*
++ *  Disclamer
++ *  ---------
++ */
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Andre Lepine <andre.lepine@nxp.com>");
++MODULE_DESCRIPTION(HDMICEC_NAME " driver");
++
+diff --git a/drivers/video/nxp/tda998x_cec.h b/drivers/video/nxp/tda998x_cec.h
+new file mode 100755
+index 0000000..fcc3cfa
+--- /dev/null
++++ b/drivers/video/nxp/tda998x_cec.h
+@@ -0,0 +1,140 @@
++/*****************************************************************************/
++/* Copyright (c) 2009 NXP Semiconductors BV                                  */
++/*                                                                           */
++/* This program is free software; you can redistribute it and/or modify      */
++/* it under the terms of the GNU General Public License as published by      */
++/* the Free Software Foundation, using version 2 of the License.             */
++/*                                                                           */
++/* This program is distributed in the hope that it will be useful,           */
++/* but WITHOUT ANY WARRANTY; without even the implied warranty of            */
++/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the              */
++/* GNU General Public License for more details.                              */
++/*                                                                           */
++/* You should have received a copy of the GNU General Public License         */
++/* along with this program; if not, write to the Free Software               */
++/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307       */
++/* USA.                                                                      */
++/*                                                                           */
++/*****************************************************************************/
++
++#ifndef __cec_h__
++#define __cec_h__
++
++#include "tda998x_ioctl.h"
++
++#define HDMICEC_NAME "hdmicec"
++
++#define CEC_MAJOR 234 /* old-style interval of device numbers */
++#define MAX_MINOR 1 /* 1 minor but 2 access : 1 more for pooling */
++
++/* common I2C define with kernel */
++/* should be the same as arch/arm/mach-omap2/board-zoom2.c */
++#define CEC_NAME "tda99Xcec"
++#define TDA99XCEC_I2C_SLAVEADDRESS 0x34
++
++#define TDA_IRQ_CALIB 107
++#define POLLING_LENGTH 3
++
++#define EDID_BLOCK_COUNT    4
++#define EDID_BLOCK_SIZE     128
++
++#ifdef GPL
++#define CHECK_EVERY_XX_MS 500 /* ms */
++#else
++#define CHECK_EVERY_XX_MS 10 /* ms */
++#endif
++
++#define LOG(type,fmt,args...) {if (this->param.verbose) {printk(type HDMICEC_NAME":%s:" fmt, __func__, ## args);}}
++/* not found the kernel "strerror" one! If someone knows, please replace it */
++#define ERR_TO_STR(e)((e == -ENODATA)?"ENODATA, no data available":\
++                      (e == -ENOMEM)? "ENOMEM, no memory available":\
++                      (e == -EINVAL)? "EINVAL, invalid argument":\
++                      (e == -EIO)? "EIO, input/output error":\
++                      (e == -ETIMEDOUT)? "ETIMEOUT, timeout has expired":\
++                      (e == -EBUSY)? "EBUSY, device or resource busy":\
++                      (e == -ENOENT)? "ENOENT, no such file or directory":\
++                      (e == -EACCES)? "EACCES, permission denied":\
++                      (e == 0)?       "":\
++                      "!UNKNOWN!")
++
++#define TRY(fct) { \
++      err=(fct); \
++      if (err) { \
++	 printk(KERN_ERR "%s? in %s line %d\n",hdmi_cec_err_string(err),__func__,__LINE__); \
++	 goto TRY_DONE; \
++      } \
++   }
++
++typedef void (*cec_callback_t) (struct work_struct *dummy);
++
++typedef struct {
++   /* module params */
++   struct { 
++      int verbose;
++      int major;
++      int minor;
++   } param;
++   /* driver */
++   struct {
++      struct class *class;
++      struct device *dev;
++      int devno;
++      struct i2c_client *i2c_client;
++      struct semaphore sem;
++      int user_counter;
++      int minor;
++      wait_queue_head_t wait;
++      bool poll_done;
++      int deinit_req;
++      struct timer_list timer;
++   } driver;
++   /* cec */
++   struct {
++      int inst;
++      unsigned char rx_addr;
++      unsigned short phy_addr;
++      unsigned char initiator;
++      cec_version version;
++      cec_sw_version sw_version;
++      cec_power power;
++      cec_setup setup;
++      cec_clock clock;
++      cec_analogue_timer analog_timer;
++      cec_digital_timer digital_timer;
++      cec_ext_timer_with_ext_plug etwep;
++      cec_ext_timer_with_phy_addr etwpa;
++      cec_deck_ctrl deck_ctrl;
++      cec_deck_status deck_status;
++      unsigned long vendor_id;
++      cec_feature_abort feature_abort;
++      cec_status_request satus_request;
++      cec_menu_request menu_request;
++      cec_menu_status menu_status;
++      cec_play play;
++      cec_analogue_service analog_service;
++      cec_digital_service digital_service;
++      cec_ext_plug ext_plug;
++      cec_rec_status rec_status;
++      cec_audio_status audio_status;
++      cec_device_type device_type;
++      cec_power_status source_status;
++      cec_audio_rate audio_rate;
++      cec_sys_audio_status sys_audio_status;
++      cec_timer_cleared_status timer_cleared_status;
++      cec_timer_status timer_status;
++      cec_tuner_device_status_analogue tdsa;
++      cec_tuner_device_status_digital tdsd;
++      cec_user_ctrl user_ctrl;
++      unsigned char select;
++      cec_user_ctrl_tune user_ctrl_tune;
++      cec_frame frame;
++      bool byebye;
++      cec_string string;
++      cec_string osd_name;
++      cec_osd_string osd_string;
++      cec_vendor_command_with_id vcwi;
++   } cec;
++} cec_instance;
++
++#endif /* __cec_h__ */
++
+diff --git a/drivers/video/nxp/tda998x_ioctl.h b/drivers/video/nxp/tda998x_ioctl.h
+new file mode 100755
+index 0000000..cd5b0cd
+--- /dev/null
++++ b/drivers/video/nxp/tda998x_ioctl.h
+@@ -0,0 +1,1123 @@
++/**
++ * Copyright (C) 2006 NXP N.V., All Rights Reserved.
++ * This source code and any compilation or derivative thereof is the proprietary
++ * information of NXP N.V. and is confidential in nature. Under no circumstances
++ * is this software to be  exposed to or placed under an Open Source License of
++ * any type without the expressed written permission of NXP N.V.
++ *
++ * Version       Revision: 1.0
++ *
++ * Date          Date: 27/10/09
++ *
++ * Brief         API for the TDA1998x HDMI Transmitters
++ *
++ **/
++
++#include <linux/types.h>
++
++#ifndef __tx_ioctl__
++#define __tx_ioctl__
++
++#ifdef __tx_h__
++
++#define TRANS_TYPE 1
++
++#if TRANS_TYPE
++
++#define EXAMPLE_MAX_SVD 30
++
++/*
++  trans-type
++*/
++typedef tmSWVersion_t tda_version;
++typedef tmPowerState_t tda_power;
++typedef tmdlHdmiTxInstanceSetupInfo_t tda_setup;
++typedef tmdlHdmiTxCapabilities_t tda_capabilities;
++typedef tmdlHdmiTxVideoOutConfig_t tda_video_out;
++typedef tmdlHdmiTxVideoInConfig_t tda_video_in;
++typedef tmdlHdmiTxSinkType_t tda_sink;
++typedef tmdlHdmiTxAudioInConfig_t tda_audio_in;
++typedef tmdlHdmiTxEdidAudioDesc_t tda_edid_audio_desc;
++typedef tmdlHdmiTxShortVidDesc_t tda_edid_video_desc;
++typedef tmdlHdmiTxEvent_t tda_event;
++typedef tmdlHdmiTxInstanceSetupInfo_t tda_setup_info;
++typedef tmdlHdmiTxEdidVideoTimings_t tda_edid_video_timings;
++typedef tmdlHdmiTxPictAspectRatio_t tda_edid_tv_aspect_ratio;
++typedef tmdlHdmiTxHdcpCheck_t tda_hdcp_status;
++#if defined (TMFL_TDA19989) || defined (TMFL_TDA9984) 
++typedef tmdlHdmiTxHdcpStatus_t tda_hdcp_fail;
++#endif
++#ifdef TMFL_TDA19989
++typedef tmdlHdmiTxEdidLatency_t tda_edid_latency;
++#endif
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxGamutData_t data;
++} tda_gammut;
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxVsPktData_t data;
++} tda_vs_infoframe;
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxSpdIfData_t data;
++} tda_spd_infoframe;
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxMpsIfData_t data;
++} tda_mps_infoframe;
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxIsrc1PktData_t data;
++} tda_isrc1;
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxIsrc2PktData_t data;
++} tda_isrc2;
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxAcpPktData_t data;
++} tda_acp;
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxGcpPktData_t data;
++} tda_gcp;
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxAviIfData_t data;
++} tda_video_infoframe;
++
++typedef struct {
++   Bool enable;
++   tmdlHdmiTxAudIfData_t data;
++} tda_audio_infoframe;
++
++typedef struct {
++   tmdlHdmiTxVidFmt_t id;
++   tmdlHdmiTxVidFmtSpecs_t spec;
++} tda_video_format;
++
++typedef struct {
++   tda_video_in video_in;
++   tda_video_out video_out;
++   tda_audio_in audio_in; /* Mind tda_set_audio_in if you change this */
++   tda_sink sink; /* Mind tda_set_audio_in if you change this */
++} tda_set_in_out;
++
++typedef struct {
++   tda_audio_in audio_in;
++   tda_sink sink;
++} tda_set_audio_in;
++
++typedef struct {
++   tda_edid_audio_desc desc[EXAMPLE_MAX_SVD];
++   unsigned int max;
++   unsigned int written;
++   unsigned char flags;
++} tda_edid_audio_caps;
++
++typedef struct {
++   tda_edid_video_desc desc[EXAMPLE_MAX_SVD];
++   unsigned int max;
++   unsigned int written;
++   unsigned char flags;
++} tda_edid_video_caps;
++
++typedef struct {
++   tmdlHdmiTxEdidStatus_t status;
++   unsigned char block_count;
++} tda_edid;
++
++typedef struct {
++   tmdlHdmiTxEdidVideoTimings_t desc[EXAMPLE_MAX_SVD];
++   unsigned char max;
++   unsigned char written;
++} tda_edid_dtd;
++
++typedef struct {
++   tmdlHdmiTxEdidFirstMD_t desc1[EXAMPLE_MAX_SVD];
++   tmdlHdmiTxEdidSecondMD_t desc2[EXAMPLE_MAX_SVD];
++   tmdlHdmiTxEdidOtherMD_t other[EXAMPLE_MAX_SVD];
++   unsigned char max;
++   unsigned char written;
++} tda_edid_md;
++
++#else 
++
++#error do not compiled this !
++
++typedef enum
++{
++    TDA_HDCP_ACTIVE         = 0,    /**< HDCP encryption status switched to active */
++    TDA_HDCP_INACTIVE       = 1,    /**< HDCP encryption status switched to inactive */
++    TDA_HPD_ACTIVE          = 2,    /**< Hotplug status switched to active */
++    TDA_HPD_INACTIVE        = 3,    /**< Hotplug status switched to inactive */
++    TDA_RX_KEYS_RECEIVED    = 4,    /**< Receiver(s) key(s) received */
++    TDA_RX_DEVICE_ACTIVE    = 5,    /**< Rx device is connected and active */
++    TDA_RX_DEVICE_INACTIVE  = 6,    /**< Rx device is connected but inactive (standby) */
++    TDA_EDID_RECEIVED       = 7,    /**< EDID has been received */
++    TDA_VS_RPT_RECEIVED     = 8,    /**< VS interrupt has been received */              
++#ifdef HDMI_TX_REPEATER_ISR_MODE
++    TDA_B_STATUS            = 9,    /**< TX received BStatus */
++#endif /* HDMI_TX_REPEATER_ISR_MODE */
++    TDA_DEBUG_EVENT_1       = 10     /**< This is a debug event */
++} tda_event;
++
++typedef struct {
++    unsigned char format;         /* EIA/CEA861 mode */
++    unsigned char channels;       /* number of channels */
++    unsigned char supportedFreqs; /* bitmask of supported frequencies */
++    unsigned char supportedRes;   /* bitmask of supported resolutions (LPCM only) */
++    unsigned char maxBitrate;     /* Maximum bitrate divided by 8KHz (compressed formats only) */
++} tda_edid_audio_desc;
++
++typedef enum {
++    TDA_EDID_READ                = 0,   /**< All blocks read OK */
++    TDA_EDID_READ_INCOMPLETE     = 1,   /**< All blocks read OK but buffer too small to return all of them */
++    TDA_EDID_ERROR_CHK_BLOCK_0   = 2,   /**< Block 0 checksum error */
++    TDA_EDID_ERROR_CHK           = 3,   /**< Block 0 OK, checksum error in one or more other blocks */
++    TDA_EDID_NOT_READ            = 4,   /**< EDID not read */
++    TDA_EDID_STATUS_INVALID      = 5    /**< Invalid   */
++} tda_edid_status;
++
++typedef struct {
++   int HBR;              /**< High Bitrate Audio packet */
++   int DST;              /**< Direct Stream Transport audio packet */
++   int oneBitAudio;      /**< One Bit Audio sample packet */
++} tda_audio_packet;
++
++typedef enum {
++    TDA_AFMT_SPDIF      = 0, /**< SPDIF */
++    TDA_AFMT_I2S        = 1, /**< I2S */
++    TDA_AFMT_OBA        = 2, /**< One bit audio / DSD */
++    TDA_AFMT_DST        = 3, /**< DST */
++    TDA_AFMT_HBR        = 4  /**< HBR */
++} tda_audio_format;
++
++typedef enum {
++    TDA_AFS_32K           = 0, /**< 32kHz    */
++    TDA_AFS_44K           = 1, /**< 44.1kHz  */
++    TDA_AFS_48K           = 2, /**< 48kHz    */
++    TDA_AFS_88K           = 3, /**< 88.2kHz  */
++    TDA_AFS_96K           = 4, /**< 96kHz    */
++    TDA_AFS_176K          = 5, /**< 176.4kHz */
++    TDA_AFS_192K          = 6  /**< 192kHz   */
++} tda_audio_rate;
++
++typedef enum {
++    TDA_I2SQ_16BITS       = 16, /**< 16 bits */
++    TDA_I2SQ_32BITS       = 32, /**< 32 bits */
++    TDA_I2SQ_OTHERS       = 0   /**< for SPDIF and DSD */
++} tda_audio_I2S_qualifier;
++
++typedef enum {
++    TDA_I2SFOR_PHILIPS_L   = 0,	/**< Philips like format */
++    TDA_I2SFOR_OTH_L       = 2,	/**< Other non Philips left justified */
++    TDA_I2SFOR_OTH_R	   = 3,	/**< Other non Philips right justified */
++    TDA_I2SFOR_INVALID     = 4	/**< Invalid format */
++} tda_audio_I2S_format;
++
++typedef enum {
++    TDA_DSTRATE_SINGLE  = 0,    /**< Single transfer rate */
++    TDA_DSTRATE_DOUBLE  = 1     /**< Double data rate */
++} tda_dst_rate;
++
++typedef struct {
++    int    simplayHd;          /**< Enable simplayHD support */
++    int    repeaterEnable;     /**< Enable repeater mode */
++    unsigned char   *pEdidBuffer;       /**< Pointer to raw EDID data */
++    unsigned long  edidBufferSize;     /**< Size of buffer for raw EDID data */
++} tda_instance_setup_info;
++
++typedef enum {
++    TDA_VFMT_NULL               = 0,    /**< Not a valid format...        */
++    TDA_VFMT_NO_CHANGE          = 0,    /**< ...or no change required     */
++    TDA_VFMT_MIN                = 1,    /**< Lowest valid format          */
++    TDA_VFMT_TV_MIN             = 1,    /**< Lowest valid TV format       */
++    TDA_VFMT_01_640x480p_60Hz   = 1,    /**< Format 01 640  x 480p  60Hz  */
++    TDA_VFMT_02_720x480p_60Hz   = 2,    /**< Format 02 720  x 480p  60Hz  */
++    TDA_VFMT_03_720x480p_60Hz   = 3,    /**< Format 03 720  x 480p  60Hz  */
++    TDA_VFMT_04_1280x720p_60Hz  = 4,    /**< Format 04 1280 x 720p  60Hz  */
++    TDA_VFMT_05_1920x1080i_60Hz = 5,    /**< Format 05 1920 x 1080i 60Hz  */
++    TDA_VFMT_06_720x480i_60Hz   = 6,    /**< Format 06 720  x 480i  60Hz  */
++    TDA_VFMT_07_720x480i_60Hz   = 7,    /**< Format 07 720  x 480i  60Hz  */
++    TDA_VFMT_08_720x240p_60Hz   = 8,    /**< Format 08 720  x 240p  60Hz  */
++    TDA_VFMT_09_720x240p_60Hz   = 9,    /**< Format 09 720  x 240p  60Hz  */
++    TDA_VFMT_10_720x480i_60Hz   = 10,   /**< Format 10 720  x 480i  60Hz  */
++    TDA_VFMT_11_720x480i_60Hz   = 11,   /**< Format 11 720  x 480i  60Hz  */
++    TDA_VFMT_12_720x240p_60Hz   = 12,   /**< Format 12 720  x 240p  60Hz  */
++    TDA_VFMT_13_720x240p_60Hz   = 13,   /**< Format 13 720  x 240p  60Hz  */
++    TDA_VFMT_14_1440x480p_60Hz  = 14,   /**< Format 14 1440 x 480p  60Hz  */
++    TDA_VFMT_15_1440x480p_60Hz  = 15,   /**< Format 15 1440 x 480p  60Hz  */
++    TDA_VFMT_16_1920x1080p_60Hz = 16,   /**< Format 16 1920 x 1080p 60Hz  */
++    TDA_VFMT_17_720x576p_50Hz   = 17,   /**< Format 17 720  x 576p  50Hz  */
++    TDA_VFMT_18_720x576p_50Hz   = 18,   /**< Format 18 720  x 576p  50Hz  */
++    TDA_VFMT_19_1280x720p_50Hz  = 19,   /**< Format 19 1280 x 720p  50Hz  */
++    TDA_VFMT_20_1920x1080i_50Hz = 20,   /**< Format 20 1920 x 1080i 50Hz  */
++    TDA_VFMT_21_720x576i_50Hz   = 21,   /**< Format 21 720  x 576i  50Hz  */
++    TDA_VFMT_22_720x576i_50Hz   = 22,   /**< Format 22 720  x 576i  50Hz  */
++    TDA_VFMT_23_720x288p_50Hz   = 23,   /**< Format 23 720  x 288p  50Hz  */
++    TDA_VFMT_24_720x288p_50Hz   = 24,   /**< Format 24 720  x 288p  50Hz  */
++    TDA_VFMT_25_720x576i_50Hz   = 25,   /**< Format 25 720  x 576i  50Hz  */
++    TDA_VFMT_26_720x576i_50Hz   = 26,   /**< Format 26 720  x 576i  50Hz  */
++    TDA_VFMT_27_720x288p_50Hz   = 27,   /**< Format 27 720  x 288p  50Hz  */
++    TDA_VFMT_28_720x288p_50Hz   = 28,   /**< Format 28 720  x 288p  50Hz  */
++    TDA_VFMT_29_1440x576p_50Hz  = 29,   /**< Format 29 1440 x 576p  50Hz  */
++    TDA_VFMT_30_1440x576p_50Hz  = 30,   /**< Format 30 1440 x 576p  50Hz  */
++    TDA_VFMT_31_1920x1080p_50Hz = 31,   /**< Format 31 1920 x 1080p 50Hz  */
++    TDA_VFMT_32_1920x1080p_24Hz = 32,   /**< Format 32 1920 x 1080p 24Hz  */
++    TDA_VFMT_33_1920x1080p_25Hz = 33,   /**< Format 33 1920 x 1080p 25Hz  */
++    TDA_VFMT_34_1920x1080p_30Hz = 34,   /**< Format 34 1920 x 1080p 30Hz  */
++    TDA_VFMT_TV_MAX             = 34,   /**< Highest valid TV format      */
++    TDA_VFMT_TV_NO_REG_MIN      = 32,   /**< Lowest TV format without prefetched table */
++    TDA_VFMT_TV_NUM             = 35,   /**< Number of TV formats & null  */
++    TDA_VFMT_PC_MIN             = 128,  /**< Lowest valid PC format       */
++    TDA_VFMT_PC_640x480p_60Hz   = 128,  /**< PC format 128                */
++    TDA_VFMT_PC_800x600p_60Hz   = 129,  /**< PC format 129                */
++    TDA_VFMT_PC_1152x960p_60Hz  = 130,  /**< PC format 130                */
++    TDA_VFMT_PC_1024x768p_60Hz  = 131,  /**< PC format 131                */
++    TDA_VFMT_PC_1280x768p_60Hz  = 132,  /**< PC format 132                */
++    TDA_VFMT_PC_1280x1024p_60Hz = 133,  /**< PC format 133                */
++    TDA_VFMT_PC_1360x768p_60Hz  = 134,  /**< PC format 134                */
++    TDA_VFMT_PC_1400x1050p_60Hz = 135,  /**< PC format 135                */
++    TDA_VFMT_PC_1600x1200p_60Hz = 136,  /**< PC format 136                */
++    TDA_VFMT_PC_1024x768p_70Hz  = 137,  /**< PC format 137                */
++    TDA_VFMT_PC_640x480p_72Hz   = 138,  /**< PC format 138                */
++    TDA_VFMT_PC_800x600p_72Hz   = 139,  /**< PC format 139                */
++    TDA_VFMT_PC_640x480p_75Hz   = 140,  /**< PC format 140                */
++    TDA_VFMT_PC_1024x768p_75Hz  = 141,  /**< PC format 141                */
++    TDA_VFMT_PC_800x600p_75Hz   = 142,  /**< PC format 142                */
++    TDA_VFMT_PC_1024x864p_75Hz  = 143,  /**< PC format 143                */
++    TDA_VFMT_PC_1280x1024p_75Hz = 144,  /**< PC format 144                */
++    TDA_VFMT_PC_640x350p_85Hz   = 145,  /**< PC format 145                */
++    TDA_VFMT_PC_640x400p_85Hz   = 146,  /**< PC format 146                */
++    TDA_VFMT_PC_720x400p_85Hz   = 147,  /**< PC format 147                */
++    TDA_VFMT_PC_640x480p_85Hz   = 148,  /**< PC format 148                */
++    TDA_VFMT_PC_800x600p_85Hz   = 149,  /**< PC format 149                */
++    TDA_VFMT_PC_1024x768p_85Hz  = 150,  /**< PC format 150                */
++    TDA_VFMT_PC_1152x864p_85Hz  = 151,  /**< PC format 151                */
++    TDA_VFMT_PC_1280x960p_85Hz  = 152,  /**< PC format 152                */
++    TDA_VFMT_PC_1280x1024p_85Hz = 153,  /**< PC format 153                */
++    TDA_VFMT_PC_1024x768i_87Hz  = 154,  /**< PC format 154                */
++    TDA_VFMT_PC_MAX             = 154,  /**< Highest valid PC format      */
++    TDA_VFMT_PC_NUM             = (1+154-128)   /**< Number of PC formats         */
++} tda_video_fmt_id;
++
++typedef struct {
++    tda_video_fmt_id videoFormat;            /**< Video format as defined by EIA/CEA 861-D */
++    int              nativeVideoFormat;   /**< True if format is the preferred video format */
++} tda_edid_video_desc;
++
++typedef struct {
++    tda_video_fmt_id videoFormat;            /**< Video format as defined by EIA/CEA 861-D */
++    int              nativeVideoFormat;   /**< True if format is the preferred video format */
++} tda_short_video_desc;
++
++typedef enum {
++    TDA_P_ASPECT_RATIO_UNDEFINED    = 0,    /**< Undefined picture aspect ratio */
++    TDA_P_ASPECT_RATIO_6_5          = 1,    /**< 6:5 picture aspect ratio (PAR) */
++    TDA_P_ASPECT_RATIO_5_4          = 2,    /**< 5:4 PAR */
++    TDA_P_ASPECT_RATIO_4_3          = 3,    /**< 4:3 PAR */
++    TDA_P_ASPECT_RATIO_16_10        = 4,    /**< 16:10 PAR */
++    TDA_P_ASPECT_RATIO_5_3          = 5,    /**< 5:3 PAR */
++    TDA_P_ASPECT_RATIO_16_9         = 6,    /**< 16:9 PAR */
++    TDA_P_ASPECT_RATIO_9_5          = 7     /**< 9:5 PAR */
++} tda_pict_aspect_ratio;
++
++typedef enum {
++    TDA_VFREQ_24Hz      = 0,    /**< 24Hz          */
++    TDA_VFREQ_25Hz      = 1,    /**< 25Hz          */
++    TDA_VFREQ_30Hz      = 2,    /**< 30Hz          */
++    TDA_VFREQ_50Hz      = 3,    /**< 50Hz          */
++    TDA_VFREQ_59Hz      = 4,    /**< 59.94Hz       */
++    TDA_VFREQ_60Hz      = 5,    /**< 60Hz          */
++    TDA_VFREQ_70Hz      = 6,    /**< 70Hz          */
++    TDA_VFREQ_72Hz      = 7,    /**< 72Hz          */
++    TDA_VFREQ_75Hz      = 8,    /**< 75Hz          */
++    TDA_VFREQ_85Hz      = 9,    /**< 85Hz          */
++    TDA_VFREQ_87Hz      = 10,   /**< 87Hz          */
++    TDA_VFREQ_INVALID   = 11,   /**< Invalid       */
++    TDA_VFREQ_NUM       = 11    /**< No. of values */
++} tda_vfreq;
++
++typedef struct {
++    unsigned short                      width;         /**< Width of the frame in pixels */
++    unsigned short                      height;        /**< Height of the frame in pixels */
++    int                        interlaced;    /**< Interlaced mode (True/False) */
++    tda_vfreq           vfrequency;    /**< Vertical frequency in Hz */
++    tda_pict_aspect_ratio aspectRatio;   /**< Picture aspect ratio (H:V) */
++} tda_video_fmt_specs;
++
++typedef enum {
++    TDA_VINMODE_CCIR656     = 0,    /**< CCIR656 */
++    TDA_VINMODE_RGB444      = 1,    /**< RGB444  */
++    TDA_VINMODE_YUV444      = 2,    /**< YUV444  */
++    TDA_VINMODE_YUV422      = 3,    /**< YUV422  */
++    TDA_VINMODE_NO_CHANGE   = 4,    /**< No change */
++    TDA_VINMODE_INVALID     = 5     /**< Invalid */
++} tda_vinmode;
++
++typedef enum {
++    TDA_SYNCSRC_EMBEDDED = 0, /**< Embedded sync */
++    TDA_SYNCSRC_EXT_VREF = 1, /**< External sync Vref, Href, Fref */
++    TDA_SYNCSRC_EXT_VS   = 2  /**< External sync Vs, Hs */
++} tda_sync_source;
++
++typedef enum {
++    TDA_PIXRATE_DOUBLE          = 0,        /**< Double pixel rate */
++    TDA_PIXRATE_SINGLE          = 1,        /**< Single pixel rate */
++    TDA_PIXRATE_SINGLE_REPEATED = 2         /**< Single pixel repeated */
++} tda_pix_rate;
++
++typedef struct {
++   tda_video_fmt_id       format;     /**< Video format as defined by EIA/CEA 861-D */
++   tda_vinmode      mode;       /**< Video mode (CCIR, RGB, YUV, etc.) */
++   tda_sync_source   syncSource; /**< Sync source type */
++   tda_pix_rate      pixelRate;  /**< Pixel rate */
++} tda_video_in;
++
++typedef enum {
++    TDA_VOUTMODE_RGB444     = 0,    /**< RGB444    */
++    TDA_VOUTMODE_YUV422     = 1,    /**< YUV422    */
++    TDA_VOUTMODE_YUV444     = 2     /**< YUV444    */
++} tda_vout_mode;
++
++typedef enum {
++    TDA_VQR_DEFAULT = 0, /* Follow HDMI spec. */
++    TDA_RGB_FULL    = 1, /* Force RGB FULL , DVI only */
++    TDA_RGB_LIMITED = 2  /* Force RGB LIMITED , DVI only */
++} tda_vqr;
++
++typedef enum {
++    TDA_COLORDEPTH_24   = 0,    /**< 8 bits per color */
++    TDA_COLORDEPTH_30   = 1,    /**< 10 bits per color */
++    TDA_COLORDEPTH_36   = 2,    /**< 12 bits per color */
++    TDA_COLORDEPTH_48   = 3     /**< 16 bits per color */
++} tda_color_depth;
++
++typedef struct {
++   tda_video_fmt_id       format;     /**< Video format as defined by EIA/CEA 861-D */
++   tda_vout_mode     mode;       /**< Video mode (CCIR, RGB, YUV, etc.) */
++   tda_color_depth  colorDepth; /**< Color depth */
++   tda_vqr          dviVqr;     /**< VQR applied in DVI mode */ 
++} tda_video_out;
++
++typedef struct {
++   tda_audio_format          format;             /**< Audio format (I2S, SPDIF, etc.) */
++   tda_audio_rate            rate;               /**< Audio sampling rate */
++   tda_audio_I2S_format       i2sFormat;          /**< I2S format of the audio input */
++   tda_audio_I2S_qualifier    i2sQualifier;       /**< I2S qualifier of the audio input (8,16,32 bits) */
++   tda_dst_rate              dstRate;            /**< DST data transfer rate */
++   unsigned char                            channelAllocation;  /**< Ref to CEA-861D p85 */
++} tda_audio_in;
++
++typedef enum {
++    TDA_SINK_DVI  = 0, /**< DVI  */
++    TDA_SINK_HDMI = 1, /**< HDMI */
++    TDA_SINK_EDID = 2  /**< As currently defined in EDID */
++} tda_sink;
++
++ typedef enum {
++     TDA_DEVICE_UNKNOWN,   /**< HW device is unknown */
++     TDA_DEVICE_TDA9984,   /**< HW device is IC TDA9984 */
++     TDA_DEVICE_TDA9989,   /**< HW device is IC TDA9989 */
++     TDA_DEVICE_TDA9981,   /**< HW device is IC TDA9981 */
++     TDA_DEVICE_TDA9983,   /**< HW device is IC TDA9983 */
++     TDA_DEVICE_TDA19989   /**< HW device is IC TDA19989 */
++ } tda_device_version;
++
++typedef enum {
++   TDA_HDMI_VERSION_UNKNOWN, /**< Unknown   */
++   TDA_HDMI_VERSION_1_1,     /**< HDMI 1.1  */
++   TDA_HDMI_VERSION_1_2a,    /**< HDMI 1.2a */
++   TDA_HDMI_VERSION_1_3a     /**< HDMI 1.3  */
++} tda_hdmi_version;
++ 
++typedef struct {
++   int HBR;              /**< High Bitrate Audio packet */
++   int DST;              /**< Direct Stream Transport audio packet */
++   int oneBitAudio;      /**< One Bit Audio sample packet */
++} tda_audio_packet;
++
++typedef enum {
++    TDA_COLORDEPTH_24   = 0,    /**< 8 bits per color */
++    TDA_COLORDEPTH_30   = 1,    /**< 10 bits per color */
++    TDA_COLORDEPTH_36   = 2,    /**< 12 bits per color */
++    TDA_COLORDEPTH_48   = 3     /**< 16 bits per color */
++} tda_color_depth;
++
++typedef struct {
++    tda_device_version deviceVersion;  /**< HW device version */
++    tda_hdmi_version hdmiVersion;    /**< Supported HDMI standard version  */
++    tda_audio_packet audioPacket;    /**< Supported audio packets */
++    tda_color_depth colorDepth;     /**< Supported color depth */
++    int hdcp;           /**< Supported Hdcp encryption (True/False) */
++   int scaler;         /**< Supported scaler (True/False) */
++} tda_capabilities;
++
++typedef struct {
++    unsigned long compatibilityNr;        // Interface compatibility number
++    unsigned long majorVersionNr;         // Interface major version number
++    unsigned long minorVersionNr;         // Interface minor version number
++} tda_version;
++
++typedef enum
++{
++    PowerOn,                          // Device powered on      (D0 state)
++    PowerStandby,                     // Device power standby   (D1 state)
++    PowerSuspend,                     // Device power suspended (D2 state)
++    PowerOff                          // Device powered off     (D3 state)
++} tda_powerXXX;
++
++typedef struct {
++    unsigned int simplayHd;          /**< Enable simplayHD support */
++    unsigned int repeaterEnable;     /**< Enable repeater mode */
++    unsigned char *pEdidBuffer;       /**< Pointer to raw EDID data */
++    unsigned long edidBufferSize;     /**< Size of buffer for raw EDID data */
++} tda_setup;
++
++typedef struct {
++   tda_video_fmt_id id;
++   tda_video_fmt_specs spec;
++} tda_video_format;
++
++typedef struct {
++   tda_video_in video_in;
++   tda_video_out video_out;
++   tda_audio_in audio_in;
++} tda_set_in_out;
++
++typedef struct {
++   tda_edid_audio_desc desc;
++   unsigned int max;
++   unsigned int written;
++   unsigned char flags;
++} tda_edid_audio_caps;
++
++typedef struct {
++   tda_edid_video_desc desc;
++   unsigned int max;
++   unsigned int written;
++   unsigned char flags;
++} tda_edid_video_caps;
++
++typedef struct {
++   tda_edid_status status;
++   unsigned char block_count;
++} tda_edid;
++
++#endif
++
++#define TDA_IOCTL_BASE 0x40
++#define RELEASE 0xFF
++
++enum {
++   /* driver specific */
++   TDA_VERBOSE_ON_CMD = 0,
++   TDA_VERBOSE_OFF_CMD,
++   TDA_BYEBYE_CMD,
++   /* HDMI Tx */
++   TDA_GET_SW_VERSION_CMD,
++   TDA_SET_POWER_CMD,
++   TDA_GET_POWER_CMD,
++   TDA_SETUP_CMD,
++   TDA_GET_SETUP_CMD,
++   TDA_WAIT_EVENT_CMD,
++   TDA_ENABLE_EVENT_CMD,
++   TDA_DISABLE_EVENT_CMD,
++   TDA_GET_VIDEO_SPEC_CMD,
++   TDA_SET_INPUT_OUTPUT_CMD,
++   TDA_SET_AUDIO_INPUT_CMD,
++   TDA_SET_VIDEO_INFOFRAME_CMD,
++   TDA_SET_AUDIO_INFOFRAME_CMD,
++   TDA_SET_ACP_CMD,
++   TDA_SET_GCP_CMD,
++   TDA_SET_ISRC1_CMD,
++   TDA_SET_ISRC2_CMD,
++   TDA_SET_MPS_INFOFRAME_CMD,
++   TDA_SET_SPD_INFOFRAME_CMD,
++   TDA_SET_VS_INFOFRAME_CMD,
++   TDA_SET_AUDIO_MUTE_CMD,
++   TDA_RESET_AUDIO_CTS_CMD,
++   TDA_GET_EDID_STATUS_CMD,
++   TDA_GET_EDID_AUDIO_CAPS_CMD,
++   TDA_GET_EDID_VIDEO_CAPS_CMD,
++   TDA_GET_EDID_VIDEO_PREF_CMD,
++   TDA_GET_EDID_SINK_TYPE_CMD,
++   TDA_GET_EDID_SOURCE_ADDRESS_CMD,
++   TDA_SET_GAMMUT_CMD,
++   TDA_GET_EDID_DTD_CMD,
++   TDA_GET_EDID_MD_CMD,
++   TDA_GET_EDID_TV_ASPECT_RATIO_CMD,
++   TDA_GET_EDID_LATENCY_CMD,
++   TDA_SET_HDCP_CMD,
++   TDA_GET_HDCP_STATUS_CMD,
++   TDA_GET_HPD_STATUS_CMD,
++};
++
++
++/* driver specific */
++#define TDA_IOCTL_VERBOSE_ON     _IO(TDA_IOCTL_BASE, TDA_VERBOSE_ON_CMD)
++#define TDA_IOCTL_VERBOSE_OFF     _IO(TDA_IOCTL_BASE, TDA_VERBOSE_OFF_CMD)
++#define TDA_IOCTL_BYEBYE     _IO(TDA_IOCTL_BASE, TDA_BYEBYE_CMD)
++/* HDMI Tx */
++#define TDA_IOCTL_GET_SW_VERSION     _IOWR(TDA_IOCTL_BASE, TDA_GET_SW_VERSION_CMD,tda_version)
++#define TDA_IOCTL_SET_POWER     _IOWR(TDA_IOCTL_BASE, TDA_SET_POWER_CMD,tda_power)
++#define TDA_IOCTL_GET_POWER     _IOWR(TDA_IOCTL_BASE, TDA_GET_POWER_CMD,tda_power)
++#define TDA_IOCTL_SETUP     _IOWR(TDA_IOCTL_BASE, TDA_SETUP_CMD,tda_setup_info)
++#define TDA_IOCTL_GET_SETUP     _IOWR(TDA_IOCTL_BASE, TDA_GET_SETUP_CMD,tda_setup_info)
++#define TDA_IOCTL_WAIT_EVENT     _IOWR(TDA_IOCTL_BASE, TDA_WAIT_EVENT_CMD,tda_event)
++#define TDA_IOCTL_ENABLE_EVENT     _IOWR(TDA_IOCTL_BASE, TDA_ENABLE_EVENT_CMD,tda_event)
++#define TDA_IOCTL_DISABLE_EVENT     _IOWR(TDA_IOCTL_BASE, TDA_DISABLE_EVENT_CMD,tda_event)
++#define TDA_IOCTL_GET_VIDEO_SPEC     _IOWR(TDA_IOCTL_BASE, TDA_GET_VIDEO_SPEC_CMD,tda_video_format)
++#define TDA_IOCTL_SET_INPUT_OUTPUT     _IOWR(TDA_IOCTL_BASE, TDA_SET_INPUT_OUTPUT_CMD,tda_set_in_out)
++#define TDA_IOCTL_SET_AUDIO_INPUT     _IOWR(TDA_IOCTL_BASE, TDA_SET_AUDIO_INPUT_CMD,tda_audio_in)
++#define TDA_IOCTL_SET_VIDEO_INFOFRAME     _IOWR(TDA_IOCTL_BASE, TDA_SET_VIDEO_INFOFRAME_CMD,tda_video_infoframe)
++#define TDA_IOCTL_SET_AUDIO_INFOFRAME     _IOWR(TDA_IOCTL_BASE, TDA_SET_AUDIO_INFOFRAME_CMD,tda_audio_infoframe)
++#define TDA_IOCTL_SET_ACP     _IOWR(TDA_IOCTL_BASE, TDA_SET_ACP_CMD,tda_acp)
++#define TDA_IOCTL_SET_GCP     _IOWR(TDA_IOCTL_BASE, TDA_SET_GCP_CMD,tda_gcp)
++#define TDA_IOCTL_SET_ISRC1     _IOWR(TDA_IOCTL_BASE, TDA_SET_ISRC1_CMD,tda_isrc1)
++#define TDA_IOCTL_SET_ISRC2     _IOWR(TDA_IOCTL_BASE, TDA_SET_ISRC2_CMD,tda_isrc2)
++#define TDA_IOCTL_SET_MPS_INFOFRAME     _IOWR(TDA_IOCTL_BASE, TDA_SET_MPS_INFOFRAME_CMD,tda_mps_infoframe)
++#define TDA_IOCTL_SET_SPD_INFOFRAME     _IOWR(TDA_IOCTL_BASE, TDA_SET_SPD_INFOFRAME_CMD,tda_spd_infoframe)
++#define TDA_IOCTL_SET_VS_INFOFRAME     _IOWR(TDA_IOCTL_BASE, TDA_SET_VS_INFOFRAME_CMD,tda_vs_infoframe)
++#define TDA_IOCTL_SET_AUDIO_MUTE     _IOWR(TDA_IOCTL_BASE, TDA_SET_AUDIO_MUTE_CMD,bool)
++#define TDA_IOCTL_RESET_AUDIO_CTS     _IO(TDA_IOCTL_BASE, TDA_RESET_AUDIO_CTS_CMD)
++#define TDA_IOCTL_GET_EDID_STATUS     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_STATUS_CMD,tda_edid)
++#define TDA_IOCTL_GET_EDID_AUDIO_CAPS     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_AUDIO_CAPS_CMD,tda_edid_audio_caps)
++#define TDA_IOCTL_GET_EDID_VIDEO_CAPS     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_VIDEO_CAPS_CMD,tda_edid_video_caps)
++#define TDA_IOCTL_GET_EDID_VIDEO_PREF     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_VIDEO_PREF_CMD,tda_edid_video_timings)
++#define TDA_IOCTL_GET_EDID_SINK_TYPE     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_SINK_TYPE_CMD,tda_sink)
++#define TDA_IOCTL_GET_EDID_SOURCE_ADDRESS     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_SOURCE_ADDRESS_CMD,unsigned short)
++#define TDA_IOCTL_SET_GAMMUT     _IOWR(TDA_IOCTL_BASE, TDA_SET_GAMMUT_CMD,tda_gammut)
++#define TDA_IOCTL_GET_EDID_DTD     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_DTD_CMD,tda_edid_dtd)
++#define TDA_IOCTL_GET_EDID_MD     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_MD_CMD,tda_edid_md)
++#define TDA_IOCTL_GET_EDID_TV_ASPECT_RATIO     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_TV_ASPECT_RATIO_CMD,tda_edid_tv_aspect_ratio)
++#define TDA_IOCTL_GET_HPD_STATUS    _IOWR(TDA_IOCTL_BASE, TDA_GET_HPD_STATUS_CMD, tmdlHdmiTxHotPlug_t)
++#ifdef TMFL_TDA19989
++#define TDA_IOCTL_GET_EDID_LATENCY     _IOWR(TDA_IOCTL_BASE, TDA_GET_EDID_LATENCY_CMD,tda_edid_latency)
++#define TDA_IOCTL_SET_HDCP     _IOWR(TDA_IOCTL_BASE, TDA_SET_HDCP_CMD,bool)
++#define TDA_IOCTL_GET_HDCP_STATUS     _IOWR(TDA_IOCTL_BASE, TDA_GET_HDCP_STATUS_CMD,tda_hdcp_status)
++#endif
++
++
++/* --- Full list --- */
++
++/* legend: */
++/* ------- */
++/* [ ] : not supported */
++/* [x] : IOCTL */
++/* [i] : open, init... */
++
++/* [x] tmdlHdmiTxGetSWVersion */
++/* [ ] tmdlHdmiTxGetNumberOfUnits */
++/* [i] tmdlHdmiTxGetCapabilities */
++/* [ ] tmdlHdmiTxGetCapabilitiesM */
++/* [i] tmdlHdmiTxOpen */
++/* [ ] tmdlHdmiTxOpenM */
++/* [i] tmdlHdmiTxClose */
++/* [x] tmdlHdmiTxSetPowerState */
++/* [x] tmdlHdmiTxGetPowerState */
++/* [ ] tmdlHdmiTxInstanceConfig */
++/* [xi] tmdlHdmiTxInstanceSetup */
++/* [x] tmdlHdmiTxGetInstanceSetup */
++/* [x] tmdlHdmiTxHandleInterrupt see IOCTL_WAIT_EVENT */
++/* [i] tmdlHdmiTxRegisterCallbacks */
++/* [x] tmdlHdmiTxEnableEvent */
++/* [x] tmdlHdmiTxDisableEvent */
++/* [x] tmdlHdmiTxGetVideoFormatSpecs */
++/* [x] tmdlHdmiTxSetInputOutput */
++/* [x] tmdlHdmiTxSetAudioInput */
++/* [x] tmdlHdmiTxSetVideoInfoframe */
++/* [x] tmdlHdmiTxSetAudioInfoframe */
++/* [x] tmdlHdmiTxSetACPPacket */
++/* [x] tmdlHdmiTxSetGeneralControlPacket */
++/* [x] tmdlHdmiTxSetISRC1Packet */
++/* [x] tmdlHdmiTxSetISRC2Packet */
++/* [x] tmdlHdmiTxSetMPSInfoframe */
++/* [x] tmdlHdmiTxSetSpdInfoframe */
++/* [x] tmdlHdmiTxSetVsInfoframe */
++/* [ ] tmdlHdmiTxDebugSetNullPacket */
++/* [ ] tmdlHdmiTxDebugSetSingleNullPacket */
++/* [x] tmdlHdmiTxSetAudioMute */
++/* [x] tmdlHdmiTxResetAudioCts */
++/* [x] tmdlHdmiTxGetEdidStatus */
++/* [x] tmdlHdmiTxGetEdidAudioCaps */
++/* [x] tmdlHdmiTxGetEdidVideoCaps */
++/* [x] tmdlHdmiTxGetEdidVideoPreferred */
++/* [x] tmdlHdmiTxGetEdidSinkType */
++/* [x] tmdlHdmiTxGetEdidSourceAddress */
++/* [ ] tmdlHdmiTxGetKsvList */
++/* [ ] tmdlHdmiTxGetDepth */
++/* [ ] tmdlHdmiTxGeneSHA_1_IT */
++/* [ ] tmdlHdmiTxSetHdcp */
++/* [ ] tmdlHdmiTxGetHdcpState */
++/* [ ] tmdlHdmiTxHdcpCheck */
++/* [x] tmdlHdmiTxSetGamutPacket */
++/* [x] tmdlHdmiTxGetEdidDetailledTimingDescriptors */
++/* [x] tmdlHdmiTxGetEdidMonitorDescriptors */
++/* [x] tmdlHdmiTxGetEdidTVPictureRatio */
++/* [ ] tmdlHdmiTxSetHDCPRevocationList */
++/* [ ] tmdlHdmiTxGetHdcpFailStatus */
++/* [x] tmdlHdmiTxGetEdidLatencyInfo */
++/* [ ] tmdlHdmiTxSetBScreen */
++/* [ ] tmdlHdmiTxRemoveBScreen */
++
++
++#endif /* __tx_h__ */
++#endif /* __tx_ioctl__ */
++
++#ifndef __cec_ioctl__
++#define __cec_ioctl__
++
++#ifdef __cec_h__
++
++typedef struct {
++   UInt8 DayOfMonth;
++   UInt8 MonthOfYear;
++   UInt16 StartTime;
++   tmdlHdmiCECDuration_t Duration;
++   UInt8 RecordingSequence;
++   tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType;
++   UInt16 AnalogueFrequency;
++   tmdlHdmiCECBroadcastSystem_t BroadcastSystem;
++} cec_analogue_timer;
++
++typedef struct {
++   UInt8 DayOfMonth;
++   UInt8 MonthOfYear;
++   UInt16 StartTime;
++   tmdlHdmiCECDuration_t Duration;
++   UInt8 RecordingSequence;
++   tmdlHdmiCECDigitalServiceIdentification_t ServiceIdentification;
++} cec_digital_timer;
++
++typedef struct {
++   UInt8 DayOfMonth;
++   UInt8 MonthOfYear;
++   UInt16 StartTime;
++   tmdlHdmiCECDuration_t Duration;
++   UInt8 RecordingSequence;
++   tmdlHdmiCECExternalPlug_t ExternalPlug;
++} cec_ext_timer_with_ext_plug;
++
++typedef struct {
++   UInt8 DayOfMonth;
++   UInt8 MonthOfYear;
++   UInt16 StartTime;
++   tmdlHdmiCECDuration_t Duration;
++   UInt8 RecordingSequence;
++   tmdlHdmiCECExternalPhysicalAddress_t ExternalPhysicalAddress;
++} cec_ext_timer_with_phy_addr;
++
++typedef struct {
++   tmdlHdmiCECFeatureOpcode_t FeatureOpcode;
++   tmdlHdmiCECAbortReason_t AbortReason;
++} cec_feature_abort;
++
++typedef struct {
++   tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType;
++   UInt16 AnalogueFrequency;
++   tmdlHdmiCECBroadcastSystem_t BroadcastSystem;
++} cec_analogue_service;
++
++typedef struct {
++   UInt16 OriginalAddress;
++   UInt16 NewAddress;
++} cec_routing_change;
++
++typedef struct {
++   char data[15];
++   unsigned char length;
++} cec_string;
++
++typedef struct {
++   tmdlHdmiCECDisplayControl_t DisplayControl;
++   char data[15];
++   unsigned char length;
++} cec_osd_string;
++
++typedef struct {
++   tmdlHdmiCECRecordingFlag_t RecordingFlag;
++   tmdlHdmiCECTunerDisplayInfo_t TunerDisplayInfo;
++   tmdlHdmiCECAnalogueBroadcastType_t AnalogueBroadcastType;
++   UInt16 AnalogueFrequency;
++   tmdlHdmiCECBroadcastSystem_t BroadcastSystem;
++} cec_tuner_device_status_analogue;
++
++typedef struct {
++   tmdlHdmiCECRecordingFlag_t RecordingFlag;
++   tmdlHdmiCECTunerDisplayInfo_t TunerDisplayInfo;
++   tmdlHdmiCECDigitalServiceIdentification_t ServiceIdentification;
++} cec_tuner_device_status_digital;
++
++typedef struct {
++   unsigned long VendorID;
++   cec_string cmd;
++} cec_vendor_command_with_id;
++
++/*
++  typedef struct {
++  UInt8 *pData;
++  UInt16 lenData;
++  } cec_send_msg;
++*/
++
++typedef struct
++{
++   unsigned char count;
++   unsigned char service;
++   unsigned char addr;
++   unsigned char data[15];
++} cec_frame;
++/* typedef tmdlHdmiCecFrameFormat_t cec_frame; */
++
++typedef tmSWVersion_t cec_sw_version;
++typedef tmPowerState_t cec_power;
++typedef tmdlHdmiCecInstanceSetup_t cec_setup;
++typedef tmdlHdmiCecEvent_t cec_event;
++typedef tmdlHdmiCecClockSource_t cec_clock;
++typedef tmdlHdmiCECSystemAudioStatus_t cec_sys_audio_status;
++typedef tmdlHdmiCECAudioRate_t cec_audio_rate;
++typedef tmdlHdmiCECDigitalServiceIdentification_t cec_digital_service;
++typedef tmdlHdmiCECVersion_t cec_version;
++typedef tmdlHdmiCECDecControlMode_t cec_deck_ctrl;
++typedef tmdlHdmiCECDecInfo_t cec_deck_status;
++typedef tmdlHdmiCECStatusRequest_t cec_status_request;
++typedef tmdlHdmiCECMenuRequestType_t cec_menu_request;
++typedef tmdlHdmiCECMenuState_t cec_menu_status;
++typedef tmdlHdmiCECPlayMode_t cec_play;
++typedef tmdlHdmiCECExternalPlug_t cec_ext_plug;
++typedef tmdlHdmiCECRecordStatusInfo_t cec_rec_status;
++typedef tmdlHdmiCECAudioStatus_t cec_audio_status;
++typedef tmdlHdmiCECPowerStatus_t cec_power_status;
++typedef tmdlHdmiCECTimerClearedStatusData_t cec_timer_cleared_status;
++typedef tmdlHdmiCECTimerStatusData_t cec_timer_status;
++typedef tmdlHdmiCECUserRemoteControlCommand_t cec_user_ctrl;
++typedef tmdlHdmiCECChannelIdentifier_t cec_user_ctrl_tune;
++typedef tmdlHdmiCECDeviceType_t cec_device_type;
++
++#define CEC_IOCTL_BASE 0x40
++
++/* service */
++enum {
++   CEC_WAITING = 0x80,
++   CEC_RELEASE,
++   CEC_RX_DONE,
++   CEC_TX_DONE
++};
++
++enum {
++   /* driver specific */
++   CEC_VERBOSE_ON_CMD = 0,
++   CEC_VERBOSE_OFF_CMD,
++   CEC_BYEBYE_CMD,
++
++   /* CEC */
++   CEC_IOCTL_RX_ADDR_CMD, /* receiver logical address selector */
++   CEC_IOCTL_PHY_ADDR_CMD, /* physical address selector */
++   CEC_IOCTL_WAIT_FRAME_CMD,
++   CEC_IOCTL_ABORT_MSG_CMD,
++   CEC_IOCTL_ACTIVE_SRC_CMD,
++   CEC_IOCTL_VERSION_CMD,
++   CEC_IOCTL_CLEAR_ANALOGUE_TIMER_CMD,
++   CEC_IOCTL_CLEAR_DIGITAL_TIMER_CMD,
++   CEC_IOCTL_CLEAR_EXT_TIMER_WITH_EXT_PLUG_CMD,
++   CEC_IOCTL_CLEAR_EXT_TIMER_WITH_PHY_ADDR_CMD,
++   CEC_IOCTL_DECK_CTRL_CMD,
++   CEC_IOCTL_DECK_STATUS_CMD,
++   CEC_IOCTL_DEVICE_VENDOR_ID_CMD,
++   CEC_IOCTL_FEATURE_ABORT_CMD,
++   CEC_IOCTL_GET_CEC_VERSION_CMD,
++   CEC_IOCTL_GET_MENU_LANGUAGE_CMD,
++   CEC_IOCTL_GIVE_AUDIO_STATUS_CMD,
++   CEC_IOCTL_GIVE_DECK_STATUS_CMD,
++   CEC_IOCTL_GIVE_DEVICE_POWER_STATUS_CMD,
++   CEC_IOCTL_GIVE_DEVICE_VENDOR_ID_CMD,
++   CEC_IOCTL_GIVE_OSD_NAME_CMD,
++   CEC_IOCTL_GIVE_PHY_ADDR_CMD,
++   CEC_IOCTL_GIVE_SYS_AUDIO_MODE_STATUS_CMD,
++   CEC_IOCTL_GIVE_TUNER_DEVICE_STATUS_CMD,
++   CEC_IOCTL_IMAGE_VIEW_ON_CMD,
++   CEC_IOCTL_INACTIVE_SRC_CMD,
++   CEC_IOCTL_MENU_REQUEST_CMD,
++   CEC_IOCTL_MENU_STATUS_CMD,
++   CEC_IOCTL_PLAY_CMD,
++   CEC_IOCTL_POLLING_MSG_CMD,
++   CEC_IOCTL_REC_OFF_CMD,
++   CEC_IOCTL_REC_ON_ANALOGUE_SERVICE_CMD,
++   CEC_IOCTL_REC_ON_DIGITAL_SERVICE_CMD,
++   CEC_IOCTL_REC_ON_EXT_PHY_ADDR_CMD,
++   CEC_IOCTL_REC_ON_EXT_PLUG_CMD,
++   CEC_IOCTL_REC_ON_OWN_SRC_CMD,
++   CEC_IOCTL_REC_STATUS_CMD,
++   CEC_IOCTL_REC_TV_SCREEN_CMD,
++   CEC_IOCTL_REPORT_AUDIO_STATUS_CMD,
++   CEC_IOCTL_REPORT_PHY_ADDR_CMD,
++   CEC_IOCTL_REPORT_POWER_STATUS_CMD,
++   CEC_IOCTL_REQUEST_ACTIVE_SRC_CMD,
++   CEC_IOCTL_ROUTING_CHANGE_CMD,
++   CEC_IOCTL_ROUTING_INFORMATION_CMD,
++   CEC_IOCTL_SELECT_ANALOGUE_SERVICE_CMD,
++   CEC_IOCTL_SELECT_DIGITAL_SERVICE_CMD,
++   CEC_IOCTL_SET_ANALOGUE_TIMER_CMD,
++   CEC_IOCTL_SET_AUDIO_RATE_CMD,
++   CEC_IOCTL_SET_DIGITAL_TIMER_CMD,
++   CEC_IOCTL_SET_EXT_TIMER_WITH_EXT_PLUG_CMD,
++   CEC_IOCTL_SET_EXT_TIMER_WITH_PHY_ADDR_CMD,
++   CEC_IOCTL_SET_MENU_LANGUAGE_CMD,
++   CEC_IOCTL_SET_OSD_NAME_CMD,
++   CEC_IOCTL_SET_OSD_STRING_CMD,
++   CEC_IOCTL_SET_STREAM_PATH_CMD,
++   CEC_IOCTL_SET_SYS_AUDIO_MODE_CMD,
++   CEC_IOCTL_SET_TIMER_PROGRAM_TITLE_CMD,
++   CEC_IOCTL_STANDBY_CMD,
++   CEC_IOCTL_SYS_AUDIO_MODE_REQUEST_CMD,
++   CEC_IOCTL_SYS_AUDIO_MODE_STATUS_CMD,
++   CEC_IOCTL_TEXT_VIEW_ON_CMD,
++   CEC_IOCTL_TIMER_CLEARED_STATUS_CMD,
++   CEC_IOCTL_TIMER_STATUS_CMD,
++   CEC_IOCTL_TUNER_DEVICE_STATUS_ANALOGUE_CMD,
++   CEC_IOCTL_TUNER_DEVICE_STATUS_DIGITAL_CMD,
++   CEC_IOCTL_TUNER_STEP_DECREMENT_CMD,
++   CEC_IOCTL_TUNER_STEP_INCREMENT_CMD,
++   CEC_IOCTL_USER_CTRL_CMD,
++   CEC_IOCTL_USER_CTRL_PLAY_CMD,
++   CEC_IOCTL_USER_CTRL_SELECT_AUDIOINPUT_CMD,
++   CEC_IOCTL_USER_CTRL_SELECT_AVINPUT_CMD,
++   CEC_IOCTL_USER_CTRL_SELECT_MEDIA_CMD,
++   CEC_IOCTL_USER_CTRL_TUNE_CMD,
++   CEC_IOCTL_USER_CTRL_RELEASED_CMD,
++   CEC_IOCTL_VENDOR_COMMAND_CMD,
++   CEC_IOCTL_VENDOR_COMMAND_WITH_ID_CMD,
++   CEC_IOCTL_VENDOR_REMOTE_BUTTON_DOWN_CMD,
++   CEC_IOCTL_VENDOR_REMOTE_BUTTON_UP_CMD,
++   CEC_IOCTL_GET_SW_VERSION_CMD,
++   CEC_IOCTL_SET_POWER_STATE_CMD,
++   CEC_IOCTL_GET_POWER_STATE_CMD,
++   CEC_IOCTL_INSTANCE_CONFIG_CMD,
++   CEC_IOCTL_INSTANCE_SETUP_CMD,
++   CEC_IOCTL_GET_INSTANCE_SETUP_CMD,
++   CEC_IOCTL_ENABLE_EVENT_CMD,
++   CEC_IOCTL_DISABLE_EVENT_CMD,
++   CEC_IOCTL_ENABLE_CALIBRATION_CMD,
++   CEC_IOCTL_DISABLE_CALIBRATION_CMD,
++   CEC_IOCTL_SEND_MSG_CMD,
++   CEC_IOCTL_SET_REGISTER_CMD
++};
++
++
++/* driver specific */
++#define CEC_IOCTL_VERBOSE_ON       _IO(CEC_IOCTL_BASE, CEC_VERBOSE_ON_CMD)
++#define CEC_IOCTL_VERBOSE_OFF      _IO(CEC_IOCTL_BASE, CEC_VERBOSE_OFF_CMD)
++#define CEC_IOCTL_BYEBYE      _IO(CEC_IOCTL_BASE, CEC_BYEBYE_CMD)
++
++/* CEC */
++#define CEC_IOCTL_RX_ADDR      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_RX_ADDR_CMD,unsigned char)
++#define CEC_IOCTL_PHY_ADDR      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_PHY_ADDR_CMD,unsigned short)
++#define CEC_IOCTL_WAIT_FRAME      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_WAIT_FRAME_CMD,cec_frame)
++#define CEC_IOCTL_ABORT_MSG      _IO(CEC_IOCTL_BASE,CEC_IOCTL_ABORT_MSG_CMD)
++#define CEC_IOCTL_ACTIVE_SRC      _IO(CEC_IOCTL_BASE,CEC_IOCTL_ACTIVE_SRC_CMD)
++#define CEC_IOCTL_VERSION      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_VERSION_CMD,cec_version)
++#define CEC_IOCTL_CLEAR_ANALOGUE_TIMER      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_CLEAR_ANALOGUE_TIMER_CMD,cec_analogue_timer)
++#define CEC_IOCTL_CLEAR_DIGITAL_TIMER      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_CLEAR_DIGITAL_TIMER_CMD,cec_digital_timer)
++#define CEC_IOCTL_CLEAR_EXT_TIMER_WITH_EXT_PLUG      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_CLEAR_EXT_TIMER_WITH_EXT_PLUG_CMD,cec_ext_timer_with_ext_plug)
++#define CEC_IOCTL_CLEAR_EXT_TIMER_WITH_PHY_ADDR      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_CLEAR_EXT_TIMER_WITH_PHY_ADDR_CMD,cec_ext_timer_with_phy_addr)
++#define CEC_IOCTL_DECK_CTRL      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_DECK_CTRL_CMD,cec_deck_ctrl)
++#define CEC_IOCTL_DECK_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_DECK_STATUS_CMD,cec_deck_status)
++#define CEC_IOCTL_DEVICE_VENDOR_ID      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_DEVICE_VENDOR_ID_CMD,unsigned long)
++#define CEC_IOCTL_FEATURE_ABORT      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_FEATURE_ABORT_CMD,cec_feature_abort)
++#define CEC_IOCTL_GET_CEC_VERSION      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_GET_CEC_VERSION_CMD,unsigned char)
++#define CEC_IOCTL_GET_MENU_LANGUAGE      _IO(CEC_IOCTL_BASE,CEC_IOCTL_GET_MENU_LANGUAGE_CMD)
++#define CEC_IOCTL_GIVE_AUDIO_STATUS      _IO(CEC_IOCTL_BASE,CEC_IOCTL_GIVE_AUDIO_STATUS_CMD)
++#define CEC_IOCTL_GIVE_DECK_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_GIVE_DECK_STATUS_CMD,cec_status_request)
++#define CEC_IOCTL_GIVE_DEVICE_POWER_STATUS      _IO(CEC_IOCTL_BASE,CEC_IOCTL_GIVE_DEVICE_POWER_STATUS_CMD)
++#define CEC_IOCTL_GIVE_DEVICE_VENDOR_ID      _IO(CEC_IOCTL_BASE,CEC_IOCTL_GIVE_DEVICE_VENDOR_ID_CMD)
++#define CEC_IOCTL_GIVE_OSD_NAME      _IO(CEC_IOCTL_BASE,CEC_IOCTL_GIVE_OSD_NAME_CMD)
++#define CEC_IOCTL_GIVE_PHY_ADDR      _IO(CEC_IOCTL_BASE,CEC_IOCTL_GIVE_PHY_ADDR_CMD)
++#define CEC_IOCTL_GIVE_SYS_AUDIO_MODE_STATUS      _IO(CEC_IOCTL_BASE,CEC_IOCTL_GIVE_SYS_AUDIO_MODE_STATUS_CMD)
++#define CEC_IOCTL_GIVE_TUNER_DEVICE_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_GIVE_TUNER_DEVICE_STATUS_CMD,cec_status_request)
++#define CEC_IOCTL_IMAGE_VIEW_ON      _IO(CEC_IOCTL_BASE,CEC_IOCTL_IMAGE_VIEW_ON_CMD)
++#define CEC_IOCTL_INACTIVE_SRC      _IO(CEC_IOCTL_BASE,CEC_IOCTL_INACTIVE_SRC_CMD)
++#define CEC_IOCTL_MENU_REQUEST      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_MENU_REQUEST_CMD,cec_menu_request)
++#define CEC_IOCTL_MENU_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_MENU_STATUS_CMD,cec_menu_status)
++#define CEC_IOCTL_PLAY      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_PLAY_CMD,cec_play)
++#define CEC_IOCTL_POLLING_MSG      _IO(CEC_IOCTL_BASE,CEC_IOCTL_POLLING_MSG_CMD)
++#define CEC_IOCTL_REC_OFF      _IO(CEC_IOCTL_BASE,CEC_IOCTL_REC_OFF_CMD)
++#define CEC_IOCTL_REC_ON_ANALOGUE_SERVICE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_REC_ON_ANALOGUE_SERVICE_CMD,cec_analogue_service)
++#define CEC_IOCTL_REC_ON_DIGITAL_SERVICE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_REC_ON_DIGITAL_SERVICE_CMD,cec_digital_service)
++#define CEC_IOCTL_REC_ON_EXT_PHY_ADDR      _IO(CEC_IOCTL_BASE,CEC_IOCTL_REC_ON_EXT_PHY_ADDR_CMD)
++#define CEC_IOCTL_REC_ON_EXT_PLUG      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_REC_ON_EXT_PLUG_CMD,cec_ext_plug)
++#define CEC_IOCTL_REC_ON_OWN_SRC      _IO(CEC_IOCTL_BASE,CEC_IOCTL_REC_ON_OWN_SRC_CMD)
++#define CEC_IOCTL_REC_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_REC_STATUS_CMD,cec_rec_status)
++#define CEC_IOCTL_REC_TV_SCREEN      _IO(CEC_IOCTL_BASE,CEC_IOCTL_REC_TV_SCREEN_CMD)
++#define CEC_IOCTL_REPORT_AUDIO_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_REPORT_AUDIO_STATUS_CMD,cec_audio_status)
++#define CEC_IOCTL_REPORT_PHY_ADDR      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_REPORT_PHY_ADDR_CMD,cec_device_type)
++#define CEC_IOCTL_REPORT_POWER_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_REPORT_POWER_STATUS_CMD,cec_power_status)
++#define CEC_IOCTL_REQUEST_ACTIVE_SRC      _IO(CEC_IOCTL_BASE,CEC_IOCTL_REQUEST_ACTIVE_SRC_CMD)
++#define CEC_IOCTL_ROUTING_CHANGE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_ROUTING_CHANGE_CMD,cec_routing_change)
++#define CEC_IOCTL_ROUTING_INFORMATION      _IO(CEC_IOCTL_BASE,CEC_IOCTL_ROUTING_INFORMATION_CMD)
++#define CEC_IOCTL_SELECT_ANALOGUE_SERVICE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SELECT_ANALOGUE_SERVICE_CMD,cec_analogue_service)
++#define CEC_IOCTL_SELECT_DIGITAL_SERVICE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SELECT_DIGITAL_SERVICE_CMD,cec_digital_service)
++#define CEC_IOCTL_SET_ANALOGUE_TIMER      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_ANALOGUE_TIMER_CMD,cec_analogue_timer)
++#define CEC_IOCTL_SET_AUDIO_RATE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_AUDIO_RATE_CMD,cec_audio_rate)
++#define CEC_IOCTL_SET_DIGITAL_TIMER      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_DIGITAL_TIMER_CMD,cec_digital_timer)
++#define CEC_IOCTL_SET_EXT_TIMER_WITH_EXT_PLUG      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_EXT_TIMER_WITH_EXT_PLUG_CMD,cec_ext_timer_with_ext_plug)
++#define CEC_IOCTL_SET_EXT_TIMER_WITH_PHY_ADDR      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_EXT_TIMER_WITH_PHY_ADDR_CMD,cec_ext_timer_with_phy_addr)
++#define CEC_IOCTL_SET_MENU_LANGUAGE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_MENU_LANGUAGE_CMD,cec_string)
++#define CEC_IOCTL_SET_OSD_NAME      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_OSD_NAME_CMD,cec_string)
++#define CEC_IOCTL_SET_OSD_STRING      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_OSD_STRING_CMD,cec_osd_string)
++#define CEC_IOCTL_SET_STREAM_PATH      _IO(CEC_IOCTL_BASE,CEC_IOCTL_SET_STREAM_PATH_CMD)
++#define CEC_IOCTL_SET_SYS_AUDIO_MODE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_SYS_AUDIO_MODE_CMD,cec_sys_audio_status)
++#define CEC_IOCTL_SET_TIMER_PROGRAM_TITLE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_TIMER_PROGRAM_TITLE_CMD,cec_string)
++#define CEC_IOCTL_STANDBY      _IO(CEC_IOCTL_BASE,CEC_IOCTL_STANDBY_CMD)
++#define CEC_IOCTL_SYS_AUDIO_MODE_REQUEST      _IO(CEC_IOCTL_BASE,CEC_IOCTL_SYS_AUDIO_MODE_REQUEST_CMD)
++#define CEC_IOCTL_SYS_AUDIO_MODE_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SYS_AUDIO_MODE_STATUS_CMD,cec_sys_audio_status)
++#define CEC_IOCTL_TEXT_VIEW_ON      _IO(CEC_IOCTL_BASE,CEC_IOCTL_TEXT_VIEW_ON_CMD)
++#define CEC_IOCTL_TIMER_CLEARED_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_TIMER_CLEARED_STATUS_CMD,cec_timer_cleared_status)
++#define CEC_IOCTL_TIMER_STATUS      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_TIMER_STATUS_CMD,cec_timer_status)
++#define CEC_IOCTL_TUNER_DEVICE_STATUS_ANALOGUE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_TUNER_DEVICE_STATUS_ANALOGUE_CMD,cec_tuner_device_status_analogue)
++#define CEC_IOCTL_TUNER_DEVICE_STATUS_DIGITAL      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_TUNER_DEVICE_STATUS_DIGITAL_CMD,cec_tuner_device_status_digital)
++#define CEC_IOCTL_TUNER_STEP_DECREMENT      _IO(CEC_IOCTL_BASE,CEC_IOCTL_TUNER_STEP_DECREMENT_CMD)
++#define CEC_IOCTL_TUNER_STEP_INCREMENT      _IO(CEC_IOCTL_BASE,CEC_IOCTL_TUNER_STEP_INCREMENT_CMD)
++#define CEC_IOCTL_USER_CTRL_PRESSED      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_USER_CTRL_CMD,cec_user_ctrl)
++#define CEC_IOCTL_USER_CTRL_PLAY      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_USER_CTRL_PLAY_CMD,cec_play)
++#define CEC_IOCTL_USER_CTRL_SELECT_AUDIOINPUT      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_USER_CTRL_SELECT_AUDIOINPUT_CMD,unsigned char)
++#define CEC_IOCTL_USER_CTRL_SELECT_AVINPUT      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_USER_CTRL_SELECT_AVINPUT_CMD,unsigned char)
++#define CEC_IOCTL_USER_CTRL_SELECT_MEDIA      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_USER_CTRL_SELECT_MEDIA_CMD,unsigned char)
++#define CEC_IOCTL_USER_CTRL_TUNE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_USER_CTRL_TUNE_CMD,cec_user_ctrl_tune)
++#define CEC_IOCTL_USER_CTRL_RELEASED      _IO(CEC_IOCTL_BASE,CEC_IOCTL_USER_CTRL_RELEASED_CMD)
++#define CEC_IOCTL_VENDOR_COMMAND      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_VENDOR_COMMAND_CMD,cec_string)
++#define CEC_IOCTL_VENDOR_COMMAND_WITH_ID      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_VENDOR_COMMAND_WITH_ID_CMD,cec_vendor_command_with_id)
++#define CEC_IOCTL_VENDOR_REMOTE_BUTTON_DOWN      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_VENDOR_REMOTE_BUTTON_DOWN_CMD,cec_string)
++#define CEC_IOCTL_VENDOR_REMOTE_BUTTON_UP      _IO(CEC_IOCTL_BASE,CEC_IOCTL_VENDOR_REMOTE_BUTTON_UP_CMD)
++#define CEC_IOCTL_GET_SW_VERSION      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_GET_SW_VERSION_CMD,cec_sw_version)
++#define CEC_IOCTL_SET_POWER_STATE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SET_POWER_STATE_CMD,cec_power)
++#define CEC_IOCTL_GET_POWER_STATE      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_GET_POWER_STATE_CMD,cec_power)
++#define CEC_IOCTL_INSTANCE_CONFIG      _IO(CEC_IOCTL_BASE,CEC_IOCTL_INSTANCE_CONFIG_CMD)
++#define CEC_IOCTL_INSTANCE_SETUP      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_INSTANCE_SETUP_CMD,cec_setup)
++#define CEC_IOCTL_GET_INSTANCE_SETUP      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_GET_INSTANCE_SETUP_CMD,cec_setup)
++#define CEC_IOCTL_ENABLE_EVENT      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_ENABLE_EVENT_CMD,cec_event)
++#define CEC_IOCTL_DISABLE_EVENT      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_DISABLE_EVENT_CMD,cec_event)
++#define CEC_IOCTL_ENABLE_CALIBRATION      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_ENABLE_CALIBRATION_CMD,cec_clock)
++#define CEC_IOCTL_DISABLE_CALIBRATION      _IO(CEC_IOCTL_BASE,CEC_IOCTL_DISABLE_CALIBRATION_CMD)
++//#define CEC_IOCTL_SEND_MSG      _IOWR(CEC_IOCTL_BASE,CEC_IOCTL_SEND_MSG_CMD,cec_send_msg)
++
++/* --- Full list --- */
++
++/* legend: */
++/* ------- */
++/* [ ] : not supported */
++/* [x] : IOCTL */
++/* [i] : open, init... */
++
++/* [ ] tmdlHdmiCecAbortMessage */
++/* [ ] tmdlHdmiCecActiveSource */
++/* [ ] tmdlHdmiCecVersion */
++/* [ ] tmdlHdmiCecClearAnalogueTimer */
++/* [ ] tmdlHdmiCecClearDigitalTimer */
++/* [ ] tmdlHdmiCecClearExternalTimerWithExternalPlug */
++/* [ ] tmdlHdmiCecClearExternalTimerWithPhysicalAddress */
++/* [ ] tmdlHdmiCecDeckControl */
++/* [ ] tmdlHdmiCecDeckStatus */
++/* [ ] tmdlHdmiCecDeviceVendorID */
++/* [ ] tmdlHdmiCecFeatureAbort */
++/* [ ] tmdlHdmiCecGetCecVersion */
++/* [ ] tmdlHdmiCecGetMenuLanguage */
++/* [ ] tmdlHdmiCecGiveAudioStatus */
++/* [ ] tmdlHdmiCecGiveDeckStatus */
++/* [ ] tmdlHdmiCecGiveDevicePowerStatus */
++/* [ ] tmdlHdmiCecGiveDeviceVendorID */
++/* [ ] tmdlHdmiCecGiveOsdName */
++/* [ ] tmdlHdmiCecGivePhysicalAddress */
++/* [ ] tmdlHdmiCecGiveSystemAudioModeStatus */
++/* [ ] tmdlHdmiCecGiveTunerDeviceStatus */
++/* [ ] tmdlHdmiCecImageViewOn */
++/* [ ] tmdlHdmiCecInactiveSource */
++/* [ ] tmdlHdmiCecMenuRequest */
++/* [ ] tmdlHdmiCecMenuStatus */
++/* [ ] tmdlHdmiCecPlay */
++/* [ ] tmdlHdmiCecPollingMessage */
++/* [ ] tmdlHdmiCecRecordOff */
++/* [ ] tmdlHdmiCecRecordOnAnalogueService */
++/* [ ] tmdlHdmiCecRecordOnDigitalService */
++/* [ ] tmdlHdmiCecRecordOnExternalPhysicalAddress */
++/* [ ] tmdlHdmiCecRecordOnExternalPlug */
++/* [ ] tmdlHdmiCecRecordOnOwnSource */
++/* [ ] tmdlHdmiCecRecordStatus */
++/* [ ] tmdlHdmiCecRecordTvScreen */
++/* [ ] tmdlHdmiCecReportAudioStatus */
++/* [ ] tmdlHdmiCecReportPhysicalAddress */
++/* [ ] tmdlHdmiCecReportPowerStatus */
++/* [ ] tmdlHdmiCecRequestActiveSource */
++/* [ ] tmdlHdmiCecRoutingChange */
++/* [ ] tmdlHdmiCecRoutingInformation */
++/* [ ] tmdlHdmiCecSelectAnalogueService */
++/* [ ] tmdlHdmiCecSelectDigitalService */
++/* [ ] tmdlHdmiCecSetAnalogueTimer */
++/* [ ] tmdlHdmiCecSetAudioRate */
++/* [ ] tmdlHdmiCecSetDigitalTimer */
++/* [ ] tmdlHdmiCecSetExternalTimerWithExternalPlug */
++/* [ ] tmdlHdmiCecSetExternalTimerWithPhysicalAddress */
++/* [ ] tmdlHdmiCecSetMenuLanguage */
++/* [ ] tmdlHdmiCecSetOsdName */
++/* [ ] tmdlHdmiCecSetOsdString */
++/* [ ] tmdlHdmiCecSetStreamPath */
++/* [ ] tmdlHdmiCecSetSystemAudioMode */
++/* [ ] tmdlHdmiCecSetTimerProgramTitle */
++/* [ ] tmdlHdmiCecStandby */
++/* [ ] tmdlHdmiCecSystemAudioModeRequest */
++/* [ ] tmdlHdmiCecSystemAudioModeStatus */
++/* [ ] tmdlHdmiCecTextViewOn */
++/* [ ] tmdlHdmiCecTimerClearedStatus */
++/* [ ] tmdlHdmiCecTimerStatus */
++/* [ ] tmdlHdmiCecTunerDeviceStatusAnalogue */
++/* [ ] tmdlHdmiCecTunerDeviceStatusDigital */
++/* [ ] tmdlHdmiCecTunerStepDecrement */
++/* [ ] tmdlHdmiCecTunerStepIncrement */
++/* [ ] tmdlHdmiCecUserControlPressed */
++/* [ ] tmdlHdmiCecUserControlPressedPlay */
++/* [ ] tmdlHdmiCecUserControlPressedSelectAudioInput */
++/* [ ] tmdlHdmiCecUserControlPressedSelectAVInput */
++/* [ ] tmdlHdmiCecUserControlPressedSelectMedia */
++/* [ ] tmdlHdmiCecUserControlPressedTune */
++/* [ ] tmdlHdmiCecUserControlReleased */
++/* [ ] tmdlHdmiCecVendorCommand */
++/* [ ] tmdlHdmiCecVendorCommandWithID */
++/* [ ] tmdlHdmiCecVendorRemoteButtonDown */
++/* [ ] tmdlHdmiCecVendorRemoteButtonUp */
++/* [ ] tmdlHdmiCecGetSWVersion */
++/* [ ] tmdlHdmiCecGetNumberOfUnits */
++/* [ ] tmdlHdmiCecGetCapabilities */
++/* [ ] tmdlHdmiCecGetCapabilitiesM */
++/* [ ] tmdlHdmiCecOpen */
++/* [ ] tmdlHdmiCecOpenM */
++/* [ ] tmdlHdmiCecClose */
++/* [ ] tmdlHdmiCecSetPowerState */
++/* [ ] tmdlHdmiCecGetPowerState */
++/* [ ] tmdlHdmiCecInstanceConfig */
++/* [ ] tmdlHdmiCecInstanceSetup */
++/* [ ] tmdlHdmiCecGetInstanceSetup */
++/* [ ] tmdlHdmiCecHandleInterrupt */
++/* [ ] tmdlHdmiCecRegisterCallbacks */
++/* [ ] tmdlHdmiCecSetAutoAnswer */
++/* [ ] tmdlHdmiCecSetLogicalAddress */
++/* [ ] tmdlHdmiCecEnableEvent */
++/* [ ] tmdlHdmiCecDisableEvent */
++/* [ ] tmdlHdmiCecEnableCalibration */
++/* [ ] tmdlHdmiCecDisableCalibration */
++/* [ ] tmdlHdmiCecSendMessage */
++/* [ ] tmdlHdmiCecSetRegister */
++
++
++#endif /* __cec_h__ */
++#endif /* __cec_ioctl__ */
+diff --git a/drivers/video/nxp/tda998x_version.h b/drivers/video/nxp/tda998x_version.h
+new file mode 100755
+index 0000000..11233e0
+--- /dev/null
++++ b/drivers/video/nxp/tda998x_version.h
+@@ -0,0 +1,17 @@
++#ifndef __tda_version__
++#define __tda_version__
++
++/* version */
++#define TDA_VERSION_MAJOR	1
++#define TDA_VERSION_MINOR	3
++#define TDA_VERSION_PATCHLEVEL 0
++#define TDA_VERSION_EXTRA	"-ioctl (2009-10-15)"
++
++/* TDA TX chip list */
++#define TDA19989 "tda19989"
++#define TDA19988 "tda19989"
++#define TDA9984  "tda9984"
++#define TDA9983  "tda9983"
++#define TDA9981  "tda9981"
++
++#endif
+diff --git a/drivers/video/nxp/test/Makefile b/drivers/video/nxp/test/Makefile
+new file mode 100755
+index 0000000..fd2fcb8
+--- /dev/null
++++ b/drivers/video/nxp/test/Makefile
+@@ -0,0 +1,28 @@
++PACKAGE_NAME=DEMO_TDA
++
++RULES:=compile
++# ROOT=/home/vadmin/dev/hdmi/omapzoom/nxp-modules
++ROOT=..
++INC=-I${ROOT} -I${ROOT}/inc -I${ROOT}/comps -I${ROOT}/comps/inc -I${ROOT}/comps/tmdlHdmiTx/inc -I${ROOT}/comps/tmdlHdmiCEC/inc
++
++EXTRA_CFLAGS += -DFUNC_PTR=" " -DCONST_DAT="const " -DRAM_DAT=" "
++CFLAGS=  ${INC}
++# LDFLAGS= -lpthread
++ACC=agcc
++# ACC=arm-none-linux-gnueabi-gcc
++
++BINARIES=demo_tda
++
++all: $(RULES)
++
++clean:  
++	@echo "\t-----> $(PACKAGE_NAME):$@"
++	@rm -f $(BINARIES) *.o
++
++compile:
++	$(ACC) $(CFLAGS) $(LDFLAGS) demo_tda.c -o demo_tda
++
++upload: 
++	adb shell rm demo_tda
++	adb push demo_tda demo_tda
++	adb shell ./demo_tda
+diff --git a/drivers/video/nxp/test/demo_tda.c b/drivers/video/nxp/test/demo_tda.c
+new file mode 100755
+index 0000000..0365a6c
+--- /dev/null
++++ b/drivers/video/nxp/test/demo_tda.c
+@@ -0,0 +1,758 @@
++/* *
++ *        Filename:  tda_demo.c
++ * 
++ *     Description:  bench and stress of CEC
++ *                   features for TDA19989
++ */
++/*         Created:  2009-10-20
++ * 
++ *          Author:  Andre Lepine
++ *         Company:  NXP Semiconductors Caen
++ * 
++ */
++#define TDA_DEMO_VERSION "v0.1"
++
++/* linux */
++#include <stdio.h>
++#include <stdlib.h>
++#include <unistd.h>
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <sys/ioctl.h>
++#include <fcntl.h>
++#include <assert.h>
++#include <signal.h>
++#include <string.h>
++#include <pthread.h>
++#include "tmdlHdmiTx_Types.h"
++#include "tmdlHdmiCEC_Types.h"
++#include "tda998x.h"
++#include "tda998x_ioctl.h"
++/* #include "tda998x_cec.h" */
++
++
++/*
++ *
++ * Definitions
++ * -----------
++ * CHAPTER 0
++ *
++ */
++
++#define USERCHECK(x,y) {if (user_request & (x)) {y;}} 
++#define _MY_IOCTL(fd,prefix,io,param) {if (ioctl(fd,prefix##io, param) == -1) {oups("ioctl failed",prefix##io);}}
++#define IO_CEC(io,param) _MY_IOCTL(cec,CEC_IOCTL_,io,param)
++#define IO_TX(io,param) _MY_IOCTL(tx,TDA_IOCTL_,io,param)
++#define IO_RX(io,param) _MY_IOCTL(rx,CEC_IOCTL_,io,param)
++#define CEC_DEV "/dev/hdmicec"
++#define TX_DEV "/dev/hdmitx"
++
++typedef struct {
++   unsigned char received;
++   unsigned char service;
++   unsigned char addr;
++   unsigned char data[15];
++} rx_frame;
++
++unsigned int user_request,user_wait;
++const char cec_name[]=CEC_DEV;
++const char tx_name[]=TX_DEV;
++int rx=0,tx=0,cec=0;
++pthread_t rx_thread;
++unsigned short phy_addr;
++cec_string osd_name = {{78,88,80},3}; /* NXP */
++tmdlHdmiCECDeviceType_t device_type = CEC_DEVICE_TYPE_PLAYBACK_DEVICE;
++
++/*
++ *
++ * Internals
++ * ---------
++ * CHAPTER 1
++ *
++ */
++
++char *cec_service(int service)
++{
++   switch (service)
++      {
++      case CEC_WAITING: {return "waiting";break;}
++      case CEC_RELEASE: {return "release";break;}
++      case CEC_RX_DONE: {return "new message";break;}
++      case CEC_TX_DONE: {return "one message sent";break;}
++      default : {return "unknown";break;}
++      }
++}
++
++/* 
++ * syntax for dumies
++ */
++void print_usage(char *exename)
++{	
++   printf("Usage: %s [test_numer] [loop]\n",exename);
++   printf("0x001: driver open/close\n");
++   printf("0x002: ...\n");
++}
++
++/*
++ * We did it !
++ */
++void my_exit(int signum) {
++   
++   printf("bye\n");
++   
++   /*
++     .last ioctl for releasing
++     .munmap if needed
++     .free 
++   */
++
++   if (tx) close(tx);
++   if (cec) {
++      ioctl(cec,CEC_IOCTL_BYEBYE, NULL);
++      close(cec);
++   }
++   if (rx) close(rx);
++
++   _exit(signum);
++}
++
++/*
++ * Failure
++ */
++void oups(char *s,int io) {
++
++   if (io) {
++      printf("%s (%d)\noups...\n",s,io);
++   }
++   else {
++   }
++
++   /*
++     .specific ioctl for releasing
++   */
++
++   if (tx) close(tx);
++   if (cec) {
++      ioctl(cec,CEC_IOCTL_BYEBYE, NULL);
++      close(cec);
++   }
++   if (rx) close(rx);
++
++   my_exit(EXIT_FAILURE);
++}
++
++
++/*
++ *
++ * Methods
++ * -------
++ * CHAPTER 2
++ *
++ */
++
++/*
++  do some event control here...
++*/
++void read_frame(cec_frame *frame) {
++ 
++   unsigned char initiator, receiver;
++   int param1,param2,param3;
++   UInt32 vendor_ID;
++   UInt32 vendor_CmdID0, vendor_CmdID1, vendor_CmdID2;
++   char language[3] = {0x65,0x6e,0x67}; /* eng */
++   tmdlHdmiCECAudioStatus_t audio;
++   tmdlHdmiCecInstanceSetup_t setup;
++   cec_feature_abort fa;
++   int i;
++
++   printf("CEC module says:%s\n",cec_service(frame->service));
++
++   /*Give receive data from CEC bus*/
++   if (frame->service == CEC_RX_DONE) {
++
++      //initiator and receiver
++      initiator = (frame->addr >> 4) & 0x0f;
++      receiver = frame->addr & 0x0f;
++      printf("[%x]->[%x] data:%02x%02x%02x%02x...\n",        \
++             initiator,                                          \
++             receiver,                                           \
++             frame->data[0],                                        \
++             frame->data[1],                                        \
++             frame->data[2],                                   \
++             frame->data[3]);
++      
++
++      // Particular case of Polling Message//
++      if (frame->count == 0x03)
++         {
++         }
++      else
++         {
++            switch(frame->data[0])
++               {
++                  // Standby
++               case CEC_OPCODE_STANDBY :
++#ifdef CEC_PW_MGT
++                  IO_TX(SET_POWER,tmPowerStandby);
++#endif 
++                  break;
++
++                  // Set Menu Language
++               case CEC_OPCODE_GET_MENU_LANGUAGE :
++                  IO_CEC(SET_MENU_LANGUAGE,language);
++                  break;
++			 
++                  // Set Menu Language
++               case CEC_OPCODE_SET_MENU_LANGUAGE :
++                  param1 = frame->data[1];
++                  param2 = frame->data[2];
++                  param3 = frame->data[3];
++                  printf(" <Language = %c%c%c>\n", param1,param2,param3);
++                  break;
++
++                  // Active Source
++               case CEC_OPCODE_ACTIVE_SOURCE :
++                  param1 = ((int)frame->data[1] << 8) + frame->data[2];
++                  printf(" <Physical Address = %.4x>\n", param1);
++                  break;
++
++                  // Inactive Source
++               case CEC_OPCODE_INACTIVE_SOURCE :
++                  param1 = ((int)frame->data[1] << 8) + frame->data[2];
++                  printf(" <Physical Address = %.4x>\n", param1);
++                  break;
++
++                  // CEC Version
++               case CEC_OPCODE_CEC_VERSION :
++                  param1 = frame->data[1];
++                  printf(" <CEC Version = %x>\n", param1);
++                  break;
++
++                  // Give OSD Name
++               case CEC_OPCODE_GIVE_OSD_NAME :
++                  IO_CEC(SET_OSD_NAME,&osd_name); /* to be check FIXEME */
++                  break;
++
++                  // Give Device vendor_ ID
++               case CEC_OPCODE_GIVE_DEVICE_VENDOR_ID :
++                  IO_CEC(DEVICE_VENDOR_ID,0x000800b7);
++                  break;
++
++                  // Report Physical Address
++               case CEC_OPCODE_REPORT_PHYSICAL_ADDRESS :
++                  param1 = ((int)frame->data[1] << 8) + frame->data[2];
++                  param2 = frame->data[3];
++                  printf(" <Physical Address = %x> <Device Type = %x> \n", param1, param2);
++                  break;
++
++                  // Device vendor_ ID
++               case CEC_OPCODE_DEVICE_VENDOR_ID :
++                  vendor_ID = ((int)frame->data[1] << 16) + \
++                     ((int)frame->data[2] << 8) + \
++                     frame->data[3];
++                  printf(" <vendor_ ID = 0x%lx>\n", vendor_ID);
++                  break;
++
++               case CEC_OPCODE_VENDOR_COMMAND_WITH_ID :
++                  vendor_ID 	 = ((int)frame->data[1] << 16)  + \
++                     ((int)frame->data[2] << 8)+ \
++                     frame->data[3];
++                  vendor_CmdID0 = ((int)frame->data[4] << 24)  + \
++                     ((int)frame->data[5] << 16)+ \
++                     ((int)frame->data[6] << 8)+ \
++                     frame->data[7];
++                  vendor_CmdID1 = ((int)frame->data[8] << 24)  + \
++                     ((int)frame->data[9] << 16)+ \
++                     ((int)frame->data[10] << 8)+ \
++                     frame->data[11];
++                  vendor_CmdID2 = ((int)frame->data[12] << 16) + \
++                     ((int)frame->data[13] << 8)+ \
++                     frame->data[14];
++                  printf(" <vendor_ ID = 0x%lx> <Command ID = 0x%lx%lx%lx>\n", vendor_ID, vendor_CmdID0, vendor_CmdID1, vendor_CmdID2);
++                  break;
++
++                  // Menu Request
++               case CEC_OPCODE_MENU_REQUEST :
++                  param1 = frame->data[1];
++                  printf(" <Menu Request Type = %x>\n", param1);
++                  break;
++
++                  // Report Power Status
++               case CEC_OPCODE_REPORT_POWER_STATUS :
++                  param1 =frame->data[1];
++                  printf(" <Power Status = %x>\n", param1);
++                  break;
++
++                  // Set OSD Name
++               case CEC_OPCODE_SET_OSD_NAME :
++                  for(i=1; i <= (frame->count-4); i++)
++                     printf("%c", frame->data[i]);
++                  printf(" >\n ");
++                  break;
++
++                  // Abort Message
++               case CEC_OPCODE_ABORT_MESSAGE :
++                  fa.FeatureOpcode=CEC_OPCODE_ABORT_MESSAGE;
++                  fa.AbortReason=CEC_ABORT_REFUSED;
++                  printf("ABORT_MESSAGE received\n");
++                  IO_CEC(FEATURE_ABORT,&fa);
++                  break;
++
++                  // Feature Abort
++               case CEC_OPCODE_FEATURE_ABORT :
++                  printf("FEATURE_ABORT");
++                  param1 = frame->data[1];
++                  param2 = frame->data[2];
++                  printf(" <Opcode = %x> <Abort Reason = %x>\n", param1, param2);
++                  break;
++
++                  // Routing Change
++               case CEC_OPCODE_ROUTING_CHANGE :
++                  param1 = ((int)frame->data[1] << 8) + frame->data[2];
++                  param2 = frame->data[3];
++                  printf(" <Physical Address = %x> <New Address = %x>\n", param1, param2);
++                  break;
++
++                  //Set Stream Path
++               case CEC_OPCODE_SET_STREAM_PATH :
++                  param1 = ((int)frame->data[1] << 8) + frame->data[2];           	        
++                  printf(" <Physical Address = %x>\n", param1);
++                  if (param1 == phy_addr) {
++                     /*                      IO_CEC(ACTIVE_SRC,0); Done my module itself */
++                  }
++                  break;
++
++                  //Give Device Power Status
++               case CEC_OPCODE_GIVE_DEVICE_POWER_STATUS :
++                  IO_CEC(REPORT_POWER_STATUS,CEC_POWER_STATUS_ON);
++                  break;
++
++                  //Give Audio Status
++               case CEC_OPCODE_GIVE_AUDIO_STATUS :
++                  audio.audioMuteSatus = CEC_AUDIO_MUTE_OFF; 
++                  audio.audioVolumeSatus = 15;
++                  IO_CEC(REPORT_AUDIO_STATUS,&audio);
++                  break;
++
++               case CEC_OPCODE_PLAY:
++                  switch (frame->data[1]) {
++                  case CEC_MODE_PLAY_FORWARD:
++                     IO_TX(SET_POWER,tmPowerOn);
++                     break;
++                  case CEC_MODE_PLAY_REVERSE:
++                     break;
++                  case CEC_MODE_FAST_FORWARD_MIN_SPEED:
++                     break;
++                  case CEC_MODE_FAST_FORWARD_MEDIUM_SPEED:
++                     break;
++                  case CEC_MODE_FAST_FORWARD_MAX_SPEED:
++                     break;
++                  case CEC_MODE_FAST_REVERSE_MIN_SPEED:
++                     break;
++                  case CEC_MODE_FAST_REVERSE_MEDIUM_SPEED:
++                     break;
++                  case CEC_MODE_FAST_REVERSE_MAX_SPEED:
++                     break;
++                  case CEC_MODE_SLOW_FORWARD_MIN_SPEED:
++                     break;
++                  case CEC_MODE_SLOW_FORWARD_MEDIUM_SPEED:
++                     break;
++                  case CEC_MODE_SLOW_FORWARD_MAX_SPEED:
++                     break;
++                  case CEC_MODE_SLOW_REVERSE_MIN_SPEED:
++                     break;
++                  case CEC_MODE_SLOW_REVERSE_MEDIUM_SPEED:
++                     break;
++                  case CEC_MODE_SLOW_REVERSE_MAX_SPEED:
++                     break;
++                  default:           	 
++                     fa.FeatureOpcode=frame->data[0];
++                     fa.AbortReason=CEC_ABORT_INVALID_OPERAND;
++                     printf("Send feature abort::invalid operand in opcode play\n");
++                     IO_CEC(FEATURE_ABORT,&fa);
++                     break;
++                  }
++                  break;
++
++               case CEC_OPCODE_USER_CONTROL_PRESSED:
++                  switch (frame->data[1]) {
++                  case CEC_REMOTE_BUTTON_SELECT:
++                     break;
++                  case CEC_REMOTE_BUTTON_UP:
++                     break;
++                  case CEC_REMOTE_BUTTON_DOWN:
++                     break;
++                  case CEC_REMOTE_BUTTON_LEFT:
++                     break;
++                  case CEC_REMOTE_BUTTON_RIGHT:
++                     break;
++                  case CEC_REMOTE_BUTTON_RIGHT_UP:
++                     break;
++                  case CEC_REMOTE_BUTTON_RIGHT_DOWN:
++                     break;
++                  case CEC_REMOTE_BUTTON_LEFT_UP:
++                     break;
++                  case CEC_REMOTE_BUTTON_LEFT_DOWN:
++                     break;
++                  case CEC_REMOTE_BUTTON_ROOT_MENU:
++                     break;
++                  case CEC_REMOTE_BUTTON_SETUP_MENU:
++                     break;
++                  case CEC_REMOTE_BUTTON_CONTENTS_MENU:
++                     break;
++                  case CEC_REMOTE_BUTTON_FAVORITE_MENU:
++                     break;
++                  case CEC_REMOTE_BUTTON_EXIT:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_0:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_1:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_2:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_3:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_4:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_5:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_6:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_7:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_8:
++                     break;
++                  case CEC_REMOTE_BUTTON_NUMBER_9:
++                     break;
++                  case CEC_REMOTE_BUTTON_DOT:
++                     break;
++                  case CEC_REMOTE_BUTTON_ENTER:
++                     break;
++                  case CEC_REMOTE_BUTTON_CLEAR:
++                     break;
++                  case CEC_REMOTE_BUTTON_NEXT_FAVORITE:
++                     break;
++                  case CEC_REMOTE_BUTTON_CHANNEL_UP:
++                     break;
++                  case CEC_REMOTE_BUTTON_CHANNEL_DOWN:
++                     break;
++                  case CEC_REMOTE_BUTTON_PREVIOUS_CHANNEL:
++                     break;
++                  case CEC_REMOTE_BUTTON_SOUND_SELECT:
++                     break;
++                  case CEC_REMOTE_BUTTON_INPUT_SELECT:
++                     break;
++                  case CEC_REMOTE_BUTTON_DISPLAY_INFORMATION:
++                     break;
++                  case CEC_REMOTE_BUTTON_HELP:
++                     break;
++                  case CEC_REMOTE_BUTTON_PAGE_UP:
++                     break;
++                  case CEC_REMOTE_BUTTON_PAGE_DOWN:
++                     break;
++                  case CEC_REMOTE_BUTTON_POWER:
++                     break;
++                  case CEC_REMOTE_BUTTON_VOLUME_UP:
++                     break;
++                  case CEC_REMOTE_BUTTON_VOLUME_DOWN:
++                     break;
++                  case CEC_REMOTE_BUTTON_MUTE:
++                     break;
++                  case CEC_REMOTE_BUTTON_PLAY:
++                     break;
++                  case CEC_REMOTE_BUTTON_STOP:
++                     break;
++                  case CEC_REMOTE_BUTTON_PAUSE:
++                     break;
++                  case CEC_REMOTE_BUTTON_RECORD:
++                     break;
++                  case CEC_REMOTE_BUTTON_REWIND:
++                     break;
++                  case CEC_REMOTE_BUTTON_FAST_FORWARD:
++                     break;
++                  case CEC_REMOTE_BUTTON_EJECT:
++                     break;
++                  case CEC_REMOTE_BUTTON_FORWARD:
++                     break;
++                  case CEC_REMOTE_BUTTON_BACKWARD:
++                     break;
++                  case CEC_REMOTE_BUTTON_STOP_RECORD:
++                     break;
++                  case CEC_REMOTE_BUTTON_PAUSE_RECORD:
++                     break;
++                  case CEC_REMOTE_BUTTON_ANGLE:
++                     break;
++                  case CEC_REMOTE_BUTTON_SUB_PICTURE:
++                     break;
++                  case CEC_REMOTE_BUTTON_VIDEO_ON_DEMAND:
++                     break;
++                  case CEC_REMOTE_BUTTON_ELECTRONIC_PROGRAM_GUIDE:
++                     break;
++                  case CEC_REMOTE_BUTTON_TIMER_PROGRAMMING:
++                     break;
++                  case CEC_REMOTE_BUTTON_INITIAL_CONFIGURATION:
++                     break;
++                  case CEC_REMOTE_BUTTON_PLAY_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_PAUSE_PLAY_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_RECORD_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_PAUSE_RECORD_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_STOP_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_MUTE_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_RESTORE_VOLUME_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_TUNE_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_SELECT_MEDIA_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_SELECT_AV_INPUT_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_SELECT_AUDIO_INPUT_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_POWER_TOGGLE_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_POWER_OFF_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_POWER_ON_FUNCTION:
++                     break;
++                  case CEC_REMOTE_BUTTON_F1_BLUE:
++                     break;
++                  case CEC_REMOTE_BUTTON_F2_RED:
++                     break;
++                  case CEC_REMOTE_BUTTON_F3_GREEN:
++                     break;
++                  case CEC_REMOTE_BUTTON_F4_YELLOW:
++                     break;
++                  case CEC_REMOTE_BUTTON_F5:
++                     break;
++                  case CEC_REMOTE_BUTTON_DATA:
++                     break;
++                  default:           	 
++                     fa.FeatureOpcode=frame->data[0];
++                     fa.AbortReason=CEC_ABORT_INVALID_OPERAND;
++                     printf("Send feature abort::invalid operand in user control pressed\n");
++                     IO_CEC(FEATURE_ABORT,&fa);
++                     break;
++                  }
++                  break;
++
++               case CEC_OPCODE_DECK_CONTROL:
++                  switch (frame->data[1]) {
++                  case CEC_DECK_CONTROL_WIND:   /*!< Skip Forward / Wind   */
++                     break;
++                  case CEC_DECK_CONTROL_REWIND: /*!< Skip Reverse / Rewind */
++                     break;
++                  case CEC_DECK_CONTROL_STOP:   /*!< Stop                  */
++                     break;
++                  case CEC_DECK_CONTROL_EJECT:  /*!< Eject                 */
++                     break;
++                  default:           	 
++                     fa.FeatureOpcode=frame->data[0];
++                     fa.AbortReason=CEC_ABORT_INVALID_OPERAND;
++                     printf("Send feature abort::invalid operand in deck control\n");
++                     IO_CEC(FEATURE_ABORT,&fa);
++                     break;
++                  }
++                  break;
++
++               case CEC_OPCODE_DECK_STATUS:
++                  switch (frame->data[1]) {
++                  case CEC_DECK_INFO_PLAY:              /*!< Play                  */
++                        break;
++                  case CEC_DECK_INFO_RECORD:            /*!< Record                */
++                        break;
++                  case CEC_DECK_INFO_PLAY_REVERSE:      /*!< Play Reverse          */
++                        break;
++                  case CEC_DECK_INFO_STILL:             /*!< Still                 */
++                        break;
++                  case CEC_DECK_INFO_SLOW:              /*!< Slow                  */
++                        break;
++                  case CEC_DECK_INFO_SLOW_REVERSE:      /*!< Slow Reverse          */
++                        break;
++                  case CEC_DECK_INFO_FAST_FORWARD:      /*!< Fast Forward          */
++                        break;
++                  case CEC_DECK_INFO_FAST_REVERSE:      /*!< Fast Reverse          */
++                        break;
++                  case CEC_DECK_INFO_NO_MEDIA:          /*!< No Media              */
++                        break;
++                  case CEC_DECK_INFO_STOP:              /*!< Stop                  */
++                        break;
++                  case CEC_DECK_INFO_WIND:              /*!< Skip Forward / Wind   */
++                        break;
++                  case CEC_DECK_INFO_REWIND:            /*!< Skip Reverse / Rewind */
++                        break;
++                  case CEC_DECK_INFO_ID_SEARCH_FORWARD: /*!< Index Search Forward  */
++                        break;
++                  case CEC_DECK_INFO_ID_SEARCH_REVERSE: /*!< Index Search Forward  */
++                        break;
++                  case CEC_DECK_INFO_OTHER_STATUS:      /*!< Other Status          */
++                        break;
++                  default:           	 
++                     fa.FeatureOpcode=frame->data[0];
++                     fa.AbortReason=CEC_ABORT_INVALID_OPERAND;
++                     printf("Send feature abort::invalid operand in deck status\n");
++                     IO_CEC(FEATURE_ABORT,&fa);
++                     break;
++                  }
++                  break;
++
++
++               case CEC_OPCODE_USER_CONTROL_RELEASED:
++                  break;
++
++               default:           	 
++                  fa.FeatureOpcode=frame->data[0];
++                  fa.AbortReason=CEC_ABORT_UNKNOWN_OPCODE;
++                  printf("Send feature abort::unknown opcode\n");
++                  IO_CEC(FEATURE_ABORT,&fa);
++                  break;
++               }
++         }
++   }
++   else if (frame->service == CEC_TX_DONE) {
++      /*          ack */
++   }
++}
++
++
++void *rx_main( void *ptr ) {
++
++   cec_frame frame;
++   memset(&frame,0,sizeof(cec_frame));
++
++   printf("%s is alive\n",__func__);
++
++   /* another cec for event */
++   if ((rx = open(cec_name, O_RDWR)) == -1) {
++      perror(cec_name);
++      oups("can not open hdmicec driver\n",0);
++   }
++
++   /* main loop */
++   while(frame.service!=CEC_RELEASE) {
++      IO_RX(WAIT_FRAME,&frame);
++      read_frame(&frame);
++   }
++
++   close(rx);
++   pthread_exit(0);
++
++   return NULL;
++}
++
++/*
++ *
++ * Bench
++ * ---------
++ * CHAPTER 3
++ *
++ */
++
++/* 0x001: driver open/close */
++void bench0001(void) {
++
++   unsigned long /* tda_power */ power; 
++
++   printf("%s\n",__func__);
++
++
++   /*
++    * init
++    */
++
++   if ((tx = open(tx_name, O_RDWR)) == -1) {
++      perror(tx_name);
++      oups("can not open hdmicec driver (evt mgr)\n",0);
++   }
++
++   printf("Power on device\n");
++   power = tmPowerOn;
++   IO_TX(SET_POWER,&power);
++
++   if ((cec = open(cec_name, O_RDWR)) == -1) {
++      perror(cec_name);
++      oups("can not open hdmicec driver\n",0);
++   }
++
++   IO_CEC(RX_ADDR,CEC_LOGICAL_ADDRESS_PLAYBACK_DEVICE_1);
++   IO_CEC(POLLING_MSG,NULL);
++
++   /* Create independent threads each of which will execute function */
++   if (pthread_create( &rx_thread, NULL, rx_main, NULL)) {
++      oups("can not create rx_thread\n",0);
++   }
++
++   /*
++    * idle
++    */
++   
++   sleep(user_wait);
++   /*    IO_CEC(ACTIVE_SRC,0); */
++   /*    IO_CEC(IMAGE_VIEW_ON,0); */
++
++
++   /*
++    * deinit
++    */
++
++   /* stop rx_thread */
++   printf("rx_thread release request\n");
++   IO_CEC(BYEBYE,0);
++   pthread_join(rx_thread, NULL);
++
++   /* bye bye */
++   close(cec);
++   close(tx);
++}
++
++/* 0x002: ... */
++void bench0002(void) {
++
++   printf("%s\n",__func__);
++
++}
++
++/*
++ *
++ * Entry point
++ * -----------
++ * CHAPTER 4
++ *
++ */
++
++int main(int argc, char *argv[]) {
++
++   printf("tda_demo, %s, %s %s\n",TDA_DEMO_VERSION,__DATE__,__TIME__);
++   printf("any feedback welcome - andre.lepine@nxp.com\n");
++
++   user_wait = 3;
++   user_request=0xFFFF;
++   /* Check command line parameters and init framebuffer */
++   if (argc > 1) user_request = strtol(argv[1],NULL,16);
++   if (argc > 2) user_wait = strtol(argv[2],NULL,16);
++   
++   printf("User request:%x user_wait:%d\n",user_request,user_wait);
++
++   /* hook up our exit handler */
++   signal(SIGINT|SIGTERM|SIGKILL|SIGQUIT, my_exit);
++
++   /*
++    * BENCH 
++    */
++   printf("\nSW raster%s",			\
++          "\n---------\n");
++   USERCHECK(0x01,bench0001());
++   USERCHECK(0x02,bench0002());
++
++   /*
++     Exit with success
++   */
++   print_usage(argv[0]);
++   raise(SIGTERM);
++   return 0;
++}
diff --git a/patches/linux-3.7/0172-Added-DT-binding-to-NXP-driver.patch b/patches/linux-3.7/0172-Added-DT-binding-to-NXP-driver.patch
new file mode 100644
index 0000000..f612484
--- /dev/null
+++ b/patches/linux-3.7/0172-Added-DT-binding-to-NXP-driver.patch
@@ -0,0 +1,34 @@
+From: Joel A Fernandes <joelagnel@ti.com>
+Date: Thu, 15 Nov 2012 16:45:47 -0600
+Subject: [PATCH] Added DT binding to NXP driver
+
+Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
+---
+ drivers/video/nxp/tda998x.c |    7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/video/nxp/tda998x.c b/drivers/video/nxp/tda998x.c
+index 4b45e41..2864221 100755
+--- a/drivers/video/nxp/tda998x.c
++++ b/drivers/video/nxp/tda998x.c
+@@ -1911,6 +1911,12 @@ static int this_i2c_remove(struct i2c_client *client)
+  *  I2C client driver (backend)
+  *  -----------------
+  */
++static const struct of_device_id tda988x_of_match[] = {
++	{ .compatible = "nxp,tda988x", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, tda988x_of_match);
++
+ static const struct i2c_device_id this_i2c_id[] = {
+    { TX_NAME, 0 },
+    { },
+@@ -1922,6 +1928,7 @@ static struct i2c_driver this_i2c_driver = {
+    .driver = {
+       .owner = THIS_MODULE,
+       .name = TX_NAME,
++      .of_match_table = tda988x_of_match
+    },
+    .probe = this_i2c_probe,
+    .remove = this_i2c_remove,
diff --git a/patches/linux-3.7/0173-da8xx-fb-Add-timings-for-720x480-60.patch b/patches/linux-3.7/0173-da8xx-fb-Add-timings-for-720x480-60.patch
new file mode 100644
index 0000000..af6c5e3
--- /dev/null
+++ b/patches/linux-3.7/0173-da8xx-fb-Add-timings-for-720x480-60.patch
@@ -0,0 +1,78 @@
+From: Joel A Fernandes <joelagnel@ti.com>
+Date: Tue, 20 Nov 2012 11:17:33 -0600
+Subject: [PATCH] da8xx-fb: Add timings for 720x480@60
+
+Also add timings for 1080p, 720p and 480p
+
+Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
+---
+ drivers/video/da8xx-fb.c |   56 ++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
+index 6d98184..d6b228f 100644
+--- a/drivers/video/da8xx-fb.c
++++ b/drivers/video/da8xx-fb.c
+@@ -312,6 +312,62 @@ static struct da8xx_panel known_lcd_panels[] = {
+ 		.pxl_clk = 30000000,
+ 		.invert_pxl_clk = 0,
+ 	},
++        [6] = {
++                 /* 1024 x 768 @ 60 Hz  Reduced blanking VESA CVT 0.79M3-R */ 
++                .name = "nxp-720x480@60",
++                .width = 720,
++                .height = 480,
++                .hfp = 15,
++                .hbp = 59,
++                .hsw = 61,
++                .vfp = 9,
++                .vbp = 30,
++                .vsw = 5,
++                .pxl_clk = 27027000,
++                .invert_pxl_clk = 0,
++        },
++	[7] = {
++		 /* 1024 x 768 @ 60 Hz  Reduced blanking VESA CVT 0.79M3-R */ 
++		.name = "nxp-1280x720@60",
++		.width = 1280,
++		.height = 720,
++		.hfp = 109, // 20
++		.hbp = 219, // 54
++		.hsw = 39,
++		.vfp = 5,
++		.vbp = 19,
++		.vsw = 5,
++		.pxl_clk = 74250000,
++		.invert_pxl_clk = 0,
++	},
++	[8] = {
++		 /* 1024 x 768 @ 60 Hz  Reduced blanking VESA CVT 0.79M3-R */ 
++		.name = "nxp-640x480@60",
++		.width = 640,
++		.height = 480,
++		.hfp = 19, // 20 /* Need more changes later */
++		.hbp = 79, // 54
++		.hsw = 59,
++		.vfp = 9,
++		.vbp = 30,
++		.vsw = 6,
++		.pxl_clk = 25200000,
++		.invert_pxl_clk = 0,
++	},
++	[9] = {
++		 /* 1024 x 768 @ 60 Hz  Reduced blanking VESA CVT 0.79M3-R */ 
++		.name = "nxp-1920x1080@24",
++		.width = 1920,
++		.height = 1080,
++		.hfp = 103, // 20
++		.hbp = 311, // 54
++		.hsw = 31,
++		.vfp = 37,
++		.vbp = 60,
++		.vsw = 8,
++		.pxl_clk = 96000000,
++		.invert_pxl_clk = 0,
++	},
+ };
+ 
+ /* Enable the Raster Engine of the LCD Controller */
diff --git a/patches/linux-3.7/0174-Add-capebus-override-and-pinmux-for-da8xx-dt.patch b/patches/linux-3.7/0174-Add-capebus-override-and-pinmux-for-da8xx-dt.patch
new file mode 100644
index 0000000..42a16f4
--- /dev/null
+++ b/patches/linux-3.7/0174-Add-capebus-override-and-pinmux-for-da8xx-dt.patch
@@ -0,0 +1,91 @@
+From: Joel A Fernandes <joelagnel@ti.com>
+Date: Thu, 6 Dec 2012 02:57:00 -0600
+Subject: [PATCH] Add capebus override and pinmux for da8xx-dt
+
+Config da8xx-fb for 1280x720 with disp-pll settings
+Add commented disp-pll settings for other freqs
+
+Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
+---
+ arch/arm/boot/dts/am335x-bone-common.dtsi |   54 +++++++++++++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
+index 0378046..5bb6a1c 100644
+--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
++++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
+@@ -127,6 +127,32 @@
+ 			>;
+ 		};
+ 
++		nxp_hdmi_cape_pins: nxp_hdmi_cape_pins {
++			pinctrl-single,pins = <
++
++				0xa0 0x08	/* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xa4 0x08	/* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xa8 0x08	/* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xac 0x08	/* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xb0 0x08	/* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xb4 0x08	/* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xb8 0x08	/* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xbc 0x08	/* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xc0 0x08	/* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xc4 0x08	/* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xc8 0x08	/* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xcc 0x08	/* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xd0 0x08	/* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xd4 0x08	/* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xd8 0x08	/* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xdc 0x08	/* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++				0xe0 0x00	/* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
++				0xe4 0x00	/* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
++				0xe8 0x00	/* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
++				0xec 0x00	/* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
++			>;
++		};
++
+ 		bone_geiger_cape_led_pins: pinmux_bone_geiger_cape_led_pins {
+ 			pinctrl-single,pins = <
+ 				0xe4 0x07	/* lcd_hsync.gpio2_23, OUTPUT | MODE7 */
+@@ -275,6 +301,10 @@
+ 				compatible = "bone-generic-cape";
+ 			};
+ 
++			nxp_hdmi_capebus: cape@6 {
++				compatible = "bone-generic-cape";
++			};
++
+ 			/* overrides; no EEPROM (prototyping) */
+ //			override@3 {
+ //				compatible = "bone-capebus-slot-override";
+@@ -439,6 +469,30 @@
+ 	slots = <&cape_eeprom_0 &cape_eeprom_1 &cape_eeprom_2 &cape_eeprom_3>;
+ };
+ 
++/* On-board NXP HDMI Part requires LCDC enabled which is currently
++   only registered using capebus infrastructure */
++&nxp_hdmi_capebus {
++	board-name = "NXP HDMI on capebus";
++	version@00A1 {
++		version = "00A1";
++		dvi {
++			compatible = "da8xx-dt";
++			pinctrl-names = "default";
++			pinctrl-0 = <&nxp_hdmi_cape_pins>;
++
++			ti,hwmods = "lcdc";
++/*
++       126000000 - 640x480
++       135000000 - 720x480
++       371000000 - 1280x720
++       192000000 - 1920x1080
++*/
++			disp-pll = <371000000>;
++			panel-type = "nxp-1280x720@60";
++		};
++	};
++};
++
+ &bone_dvi_cape {
+ 	board-name = "BeagleBone DVI-D CAPE";
+ 
diff --git a/patches/linux-3.7/0175-video-Kconfig-Makefile-Add-new-Kconfig-for-old-drive.patch b/patches/linux-3.7/0175-video-Kconfig-Makefile-Add-new-Kconfig-for-old-drive.patch
new file mode 100644
index 0000000..c53cedf
--- /dev/null
+++ b/patches/linux-3.7/0175-video-Kconfig-Makefile-Add-new-Kconfig-for-old-drive.patch
@@ -0,0 +1,48 @@
+From: Joel A Fernandes <joelagnel@ti.com>
+Date: Tue, 20 Nov 2012 14:14:27 -0600
+Subject: [PATCH] video/Kconfig+Makefile: Add new Kconfig for old driver
+
+Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
+---
+ drivers/video/Kconfig     |    2 ++
+ drivers/video/Makefile    |    2 ++
+ drivers/video/nxp/Kconfig |    7 +++++++
+ 3 files changed, 11 insertions(+)
+ create mode 100644 drivers/video/nxp/Kconfig
+
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index e7868d8..3dc4ae8 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -2433,6 +2433,8 @@ source "drivers/video/omap2/Kconfig"
+ source "drivers/video/exynos/Kconfig"
+ source "drivers/video/backlight/Kconfig"
+ 
++source "drivers/video/nxp/Kconfig"
++
+ if VT
+ 	source "drivers/video/console/Kconfig"
+ endif
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index 0e13296..10e0642 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -168,3 +168,5 @@ obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
+ 
+ #video output switch sysfs driver
+ obj-$(CONFIG_VIDEO_OUTPUT_CONTROL) += output.o
++
++obj-$(CONFIG_NXP_TDA998X_OLD) 	  += nxp/
+diff --git a/drivers/video/nxp/Kconfig b/drivers/video/nxp/Kconfig
+new file mode 100644
+index 0000000..1315c5f
+--- /dev/null
++++ b/drivers/video/nxp/Kconfig
+@@ -0,0 +1,7 @@
++config NXP_TDA998X_OLD
++   tristate "NXP TDA998X HDMI video display driver"
++   select REGMAP_I2C
++   depends on I2C
++   help
++     Say Y here if you want to support NXP's TDA998X HDMI driver
++     To compile this driver as a module, choose M here.
diff --git a/patches/linux-3.7/0176-am335x-bonelt-dts-Add-DT-node-to-probe-NXP-driver.patch b/patches/linux-3.7/0176-am335x-bonelt-dts-Add-DT-node-to-probe-NXP-driver.patch
new file mode 100644
index 0000000..97a30e2
--- /dev/null
+++ b/patches/linux-3.7/0176-am335x-bonelt-dts-Add-DT-node-to-probe-NXP-driver.patch
@@ -0,0 +1,34 @@
+From: Joel A Fernandes <joelagnel@ti.com>
+Date: Tue, 20 Nov 2012 14:18:08 -0600
+Subject: [PATCH] am335x-bonelt/dts: Add DT node to probe NXP driver
+
+Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
+---
+ arch/arm/boot/dts/am335x-bonelt.dts |   17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/am335x-bonelt.dts b/arch/arm/boot/dts/am335x-bonelt.dts
+index 87257ac..44814b4 100644
+--- a/arch/arm/boot/dts/am335x-bonelt.dts
++++ b/arch/arm/boot/dts/am335x-bonelt.dts
+@@ -30,3 +30,20 @@
+ 	ti,non-removable;
+ 	status = "okay";
+ };
++
++&i2c0 {
++	tda998X@34 {
++ 		compatible = "nxp,tda988x";
++	 	reg = <0x34>;
++	};
++};
++
++&capebus {
++	override@0 {
++		board-name = "NXP HDMI on CapeBus";
++		compatible = "bone-capebus-slot-override";
++		slot = <1>;
++		version = "00A1";
++		manufacturer = "Beagleboardtoys";
++	};
++};
diff --git a/patches/linux-3.7/0177-tda-driver-enable-1280x720.patch b/patches/linux-3.7/0177-tda-driver-enable-1280x720.patch
new file mode 100644
index 0000000..9a61abe
--- /dev/null
+++ b/patches/linux-3.7/0177-tda-driver-enable-1280x720.patch
@@ -0,0 +1,25 @@
+From: Joel A Fernandes <joelagnel@ti.com>
+Date: Mon, 3 Dec 2012 11:08:39 -0600
+Subject: [PATCH] tda driver: enable 1280x720
+
+Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
+---
+ drivers/video/nxp/tda998x.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/video/nxp/tda998x.c b/drivers/video/nxp/tda998x.c
+index 2864221..de9ce6d 100755
+--- a/drivers/video/nxp/tda998x.c
++++ b/drivers/video/nxp/tda998x.c
+@@ -1034,9 +1034,9 @@ static int hdmi_tx_init(tda_instance *this)
+    /*    this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_31_1920x1080p_50Hz; */
+    /*    this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_PC_640x480p_60Hz; */
+    /*    this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_PC_640x480p_72Hz; */
+-   // this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_04_1280x720p_60Hz; 
++   this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_04_1280x720p_60Hz; 
+    /*    this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_19_1280x720p_50Hz; */
+-   this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_02_720x480p_60Hz;
++   // this->tda.setio.video_out.format = TMDL_HDMITX_VFMT_02_720x480p_60Hz;
+ 
+    this->tda.setio.video_in.mode = TMDL_HDMITX_VINMODE_RGB444;
+    /*    this->tda.setio.video_in.mode = TMDL_HDMITX_VINMODE_CCIR656; */
diff --git a/patches/linux-3.7/0178-Makefile-Disable-CEC.patch b/patches/linux-3.7/0178-Makefile-Disable-CEC.patch
new file mode 100644
index 0000000..944fc74
--- /dev/null
+++ b/patches/linux-3.7/0178-Makefile-Disable-CEC.patch
@@ -0,0 +1,22 @@
+From: Joel A Fernandes <joelagnel@ti.com>
+Date: Mon, 3 Dec 2012 11:09:29 -0600
+Subject: [PATCH] Makefile: Disable CEC
+
+Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
+---
+ drivers/video/nxp/Makefile |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/video/nxp/Makefile b/drivers/video/nxp/Makefile
+index f583226..05dc816 100755
+--- a/drivers/video/nxp/Makefile
++++ b/drivers/video/nxp/Makefile
+@@ -14,7 +14,7 @@ TDA_PLATFORM := ZOOMII
+ 
+ #TDA_HDCP := 0
+ TDA_HDCP := TMFL_HDCP_SUPPORT
+-TDA_CEC := TDA9950
++#TDA_CEC := TDA9950
+ 
+ # add this if INTERRUPT is wired, otherwise polling with timer is used
+ #EXTRA_CFLAGS += -DIRQ
diff --git a/patches/linux-3.7/0180-uio-uio_pruss-port-to-AM33xx.patch b/patches/linux-3.7/0180-uio-uio_pruss-port-to-AM33xx.patch
new file mode 100644
index 0000000..056d96d
--- /dev/null
+++ b/patches/linux-3.7/0180-uio-uio_pruss-port-to-AM33xx.patch
@@ -0,0 +1,239 @@
+From: Matt Porter <mporter@ti.com>
+Date: Fri, 21 Sep 2012 12:23:49 -0400
+Subject: [PATCH] uio: uio_pruss: port to AM33xx
+
+Add ifdefery hacks to only use SRAM on Davinci. This
+needs to be cleaned up with a sane generic SRAM allocator
+(like the DT based driver available that can't be used on
+Davinci which is just starting DT conversion) before it
+can go upstream.
+
+Adds DT, pinctrl, and runtime PM support for use on
+AM33xx.
+
+Signed-off-by: Matt Porter <mporter@ti.com>
+Signed-off-by: Matt Ranostay <mranostay@gmail.com>
+---
+ Documentation/devicetree/bindings/uio/pruss.txt    |   17 ++++++
+ .../devicetree/bindings/uio/uio_pruss.txt          |   17 ++++++
+ drivers/uio/Kconfig                                |    4 +-
+ drivers/uio/uio_pruss.c                            |   63 +++++++++++++++++++-
+ 4 files changed, 98 insertions(+), 3 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/uio/pruss.txt
+ create mode 100644 Documentation/devicetree/bindings/uio/uio_pruss.txt
+
+diff --git a/Documentation/devicetree/bindings/uio/pruss.txt b/Documentation/devicetree/bindings/uio/pruss.txt
+new file mode 100644
+index 0000000..2ac45c5
+--- /dev/null
++++ b/Documentation/devicetree/bindings/uio/pruss.txt
+@@ -0,0 +1,17 @@
++TI PRUSS device
++
++Required properties:
++- compatible :
++  - "ti,pruss-v1" for AM18xx/OMAP-L138/DA850
++  - "ti,pruss-v2" for AM33xx.
++- ti,pintc-offset : Offset of the PINTC from the PRUSS address base
++- ti,hwmods: Name of the hwmod associated to the PRUSS
++
++Example:
++
++pruss: pruss@4a300000 {
++	compatible = "ti,pruss-v2";
++	ti,hwmods = "pruss";
++	reg = <0x4a300000 0x080000>;
++	ti,pintc-offset = <0x20000>;
++};
+diff --git a/Documentation/devicetree/bindings/uio/uio_pruss.txt b/Documentation/devicetree/bindings/uio/uio_pruss.txt
+new file mode 100644
+index 0000000..2ac45c5
+--- /dev/null
++++ b/Documentation/devicetree/bindings/uio/uio_pruss.txt
+@@ -0,0 +1,17 @@
++TI PRUSS device
++
++Required properties:
++- compatible :
++  - "ti,pruss-v1" for AM18xx/OMAP-L138/DA850
++  - "ti,pruss-v2" for AM33xx.
++- ti,pintc-offset : Offset of the PINTC from the PRUSS address base
++- ti,hwmods: Name of the hwmod associated to the PRUSS
++
++Example:
++
++pruss: pruss@4a300000 {
++	compatible = "ti,pruss-v2";
++	ti,hwmods = "pruss";
++	reg = <0x4a300000 0x080000>;
++	ti,pintc-offset = <0x20000>;
++};
+diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig
+index 6f3ea9b..8da7d9b 100644
+--- a/drivers/uio/Kconfig
++++ b/drivers/uio/Kconfig
+@@ -96,9 +96,9 @@ config UIO_NETX
+ 
+ config UIO_PRUSS
+ 	tristate "Texas Instruments PRUSS driver"
+-	depends on ARCH_DAVINCI_DA850
++	depends on ARCH_DAVINCI_DA850 || SOC_AM33XX
+ 	help
+-	  PRUSS driver for OMAPL138/DA850/AM18XX devices
++	  PRUSS driver for OMAPL138/DA850/AM18XX and AM33XX devices
+ 	  PRUSS driver requires user space components, examples and user space
+ 	  driver is available from below SVN repo - you may use anonymous login
+ 
+diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c
+index 33a7a27..326ce40 100644
+--- a/drivers/uio/uio_pruss.c
++++ b/drivers/uio/uio_pruss.c
+@@ -25,7 +25,15 @@
+ #include <linux/clk.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/slab.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/err.h>
++#include <linux/pm_runtime.h>
++
++#ifdef CONFIG_ARCH_DAVINCI_DA850
+ #include <mach/sram.h>
++#endif
+ 
+ #define DRV_NAME "pruss_uio"
+ #define DRV_VERSION "1.0"
+@@ -105,8 +113,10 @@ static void pruss_cleanup(struct platform_device *dev,
+ 		dma_free_coherent(&dev->dev, extram_pool_sz, gdev->ddr_vaddr,
+ 			gdev->ddr_paddr);
+ 	}
++#ifdef CONFIG_ARCH_DAVINCI_DA850
+ 	if (gdev->sram_vaddr)
+ 		sram_free(gdev->sram_vaddr, sram_pool_sz);
++#endif
+ 	kfree(gdev->info);
+ 	clk_put(gdev->pruss_clk);
+ 	kfree(gdev);
+@@ -117,8 +127,10 @@ static int __devinit pruss_probe(struct platform_device *dev)
+ 	struct uio_info *p;
+ 	struct uio_pruss_dev *gdev;
+ 	struct resource *regs_prussio;
++	struct resource res;
+ 	int ret = -ENODEV, cnt = 0, len;
+ 	struct uio_pruss_pdata *pdata = dev->dev.platform_data;
++	struct pinctrl *pinctrl;
+ 
+ 	gdev = kzalloc(sizeof(struct uio_pruss_dev), GFP_KERNEL);
+ 	if (!gdev)
+@@ -129,6 +141,7 @@ static int __devinit pruss_probe(struct platform_device *dev)
+ 		kfree(gdev);
+ 		return -ENOMEM;
+ 	}
++#ifdef CONFIG_ARCH_DAVINCI_DA850
+ 	/* Power on PRU in case its not done as part of boot-loader */
+ 	gdev->pruss_clk = clk_get(&dev->dev, "pruss");
+ 	if (IS_ERR(gdev->pruss_clk)) {
+@@ -140,6 +153,28 @@ static int __devinit pruss_probe(struct platform_device *dev)
+ 	} else {
+ 		clk_enable(gdev->pruss_clk);
+ 	}
++#endif
++
++	if (dev->dev.of_node) {
++		pm_runtime_enable(&dev->dev);
++		ret = pm_runtime_get_sync(&dev->dev);
++		if (IS_ERR_VALUE(ret)) {
++			dev_err(&dev->dev, "pm_runtime_get_sync() failed\n");
++			return ret;
++		}
++
++		ret = of_address_to_resource(dev->dev.of_node, 0, &res);
++		if (IS_ERR_VALUE(ret)) {
++			dev_err(&dev->dev, "failed to parse DT reg\n");
++			return ret;
++		}
++		regs_prussio = &res;
++	}
++
++	pinctrl = devm_pinctrl_get_select_default(&dev->dev);
++	if (IS_ERR(pinctrl))
++		dev_warn(&dev->dev,
++			"pins are not configured from the driver\n");
+ 
+ 	regs_prussio = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ 	if (!regs_prussio) {
+@@ -152,11 +187,13 @@ static int __devinit pruss_probe(struct platform_device *dev)
+ 		goto out_free;
+ 	}
+ 
++#ifdef CONFIG_ARCH_DAVINCI_DA850
+ 	gdev->sram_vaddr = sram_alloc(sram_pool_sz, &(gdev->sram_paddr));
+ 	if (!gdev->sram_vaddr) {
+ 		dev_err(&dev->dev, "Could not allocate SRAM pool\n");
+ 		goto out_free;
+ 	}
++#endif
+ 
+ 	gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz,
+ 				&(gdev->ddr_paddr), GFP_KERNEL | GFP_DMA);
+@@ -172,7 +209,17 @@ static int __devinit pruss_probe(struct platform_device *dev)
+ 		goto out_free;
+ 	}
+ 
+-	gdev->pintc_base = pdata->pintc_base;
++	if (dev->dev.of_node) {
++		ret = of_property_read_u32(dev->dev.of_node,
++					   "ti,pintc-offset",
++					   &gdev->pintc_base);
++		if (ret < 0) {
++			dev_err(&dev->dev,
++				"Can't parse ti,pintc-offset property\n");
++			goto out_free;
++		}
++	} else
++		gdev->pintc_base = pdata->pintc_base;
+ 	gdev->hostirq_start = platform_get_irq(dev, 0);
+ 
+ 	for (cnt = 0, p = gdev->info; cnt < MAX_PRUSS_EVT; cnt++, p++) {
+@@ -180,6 +227,7 @@ static int __devinit pruss_probe(struct platform_device *dev)
+ 		p->mem[0].size = resource_size(regs_prussio);
+ 		p->mem[0].memtype = UIO_MEM_PHYS;
+ 
++#ifdef CONFIG_ARCH_DAVINCI_DA850
+ 		p->mem[1].addr = gdev->sram_paddr;
+ 		p->mem[1].size = sram_pool_sz;
+ 		p->mem[1].memtype = UIO_MEM_PHYS;
+@@ -187,6 +235,11 @@ static int __devinit pruss_probe(struct platform_device *dev)
+ 		p->mem[2].addr = gdev->ddr_paddr;
+ 		p->mem[2].size = extram_pool_sz;
+ 		p->mem[2].memtype = UIO_MEM_PHYS;
++#else
++		p->mem[1].addr = gdev->ddr_paddr;
++		p->mem[1].size = extram_pool_sz;
++		p->mem[1].memtype = UIO_MEM_PHYS;
++#endif
+ 
+ 		p->name = kasprintf(GFP_KERNEL, "pruss_evt%d", cnt);
+ 		p->version = DRV_VERSION;
+@@ -218,12 +271,20 @@ static int __devexit pruss_remove(struct platform_device *dev)
+ 	return 0;
+ }
+ 
++static const struct of_device_id pruss_dt_ids[] = {
++	{ .compatible = "ti,pruss-v1", .data = NULL, },
++	{ .compatible = "ti,pruss-v2", .data = NULL, },
++	{},
++};
++MODULE_DEVICE_TABLE(of, pruss_dt_ids);
++
+ static struct platform_driver pruss_driver = {
+ 	.probe = pruss_probe,
+ 	.remove = __devexit_p(pruss_remove),
+ 	.driver = {
+ 		   .name = DRV_NAME,
+ 		   .owner = THIS_MODULE,
++		   .of_match_table = pruss_dt_ids,
+ 		   },
+ };
+ 
diff --git a/patches/linux-3.7/0181-ARM-omap-add-DT-support-for-deasserting-hardware-res.patch b/patches/linux-3.7/0181-ARM-omap-add-DT-support-for-deasserting-hardware-res.patch
new file mode 100644
index 0000000..bc03cce
--- /dev/null
+++ b/patches/linux-3.7/0181-ARM-omap-add-DT-support-for-deasserting-hardware-res.patch
@@ -0,0 +1,80 @@
+From: Matt Porter <mporter@ti.com>
+Date: Mon, 24 Sep 2012 09:54:17 -0400
+Subject: [PATCH] ARM: omap: add DT support for deasserting hardware reset
+ lines
+
+This optional binding extension allows specification of a hwmod
+and associate hardware reset line which should be deasserted for
+the device to be functional.
+
+The implementation works for reference as to the problem that
+exists for utilizing uio_pruss on AM33xx but is suboptimal. The
+problem is that this deassertion occurs before clocks are enabled
+and we are warned that the hard reset failed. Ideally the list of
+rst lines requested to be deasserted would be cached and used within
+the hwmod enable sequencing (instead of it just returning if any
+hardware reset line is asserted).
+
+Signed-off-by: Matt Porter <mporter@ti.com>
+Signed-off-by: Matt Ranostay <mranostay@gmail.com>
+---
+ .../devicetree/bindings/arm/omap/omap.txt          |    2 ++
+ arch/arm/plat-omap/omap_device.c                   |   25 ++++++++++++++++++--
+ 2 files changed, 25 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
+index d0051a7..3133a4b 100644
+--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
++++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
+@@ -21,6 +21,8 @@ Required properties:
+ Optional properties:
+ - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
+   during suspend.
++- ti,deassert-hard-reset: list of hwmod and hardware reset line name pairs
++  (ascii strings) to be deasserted upon device instantiation.
+ 
+ 
+ Example:
+diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
+index a15b715..b47161a 100644
+--- a/arch/arm/plat-omap/omap_device.c
++++ b/arch/arm/plat-omap/omap_device.c
+@@ -330,8 +330,8 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
+ 	struct omap_device *od;
+ 	struct omap_hwmod *oh;
+ 	struct device_node *node = pdev->dev.of_node;
+-	const char *oh_name;
+-	int oh_cnt, i, ret = 0;
++	const char *oh_name, *rst_name;
++	int oh_cnt, dstr_cnt, i, ret = 0;
+ 
+ 	oh_cnt = of_property_count_strings(node, "ti,hwmods");
+ 	if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
+@@ -376,6 +376,27 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
+ 	if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
+ 		omap_device_disable_idle_on_suspend(pdev);
+ 
++	dstr_cnt =
++		of_property_count_strings(node, "ti,deassert-hard-reset");
++	if (dstr_cnt > 0) {
++		for (i = 0; i < dstr_cnt; i += 2) {
++			of_property_read_string_index(
++				node, "ti,deassert-hard-reset", i,
++				&oh_name);
++			of_property_read_string_index(
++				node, "ti,deassert-hard-reset", i+1,
++				&rst_name);
++			oh = omap_hwmod_lookup(oh_name);
++			if (!oh) {
++				dev_warn(&pdev->dev,
++				"Cannot parse deassert property for '%s'\n",
++				oh_name);
++				break;
++			}
++			omap_hwmod_deassert_hardreset(oh, rst_name);
++		}
++	}
++
+ 	pdev->dev.pm_domain = &omap_device_pm_domain;
+ 
+ odbfd_exit1:
diff --git a/patches/linux-3.7/0182-ARM-dts-AM33xx-PRUSS-support.patch b/patches/linux-3.7/0182-ARM-dts-AM33xx-PRUSS-support.patch
new file mode 100644
index 0000000..77b2dae
--- /dev/null
+++ b/patches/linux-3.7/0182-ARM-dts-AM33xx-PRUSS-support.patch
@@ -0,0 +1,33 @@
+From: Matt Porter <mporter@ti.com>
+Date: Fri, 21 Sep 2012 12:33:14 -0400
+Subject: [PATCH] ARM: dts: AM33xx PRUSS support
+
+Adds a pruss node and an example of use on Beaglebone.
+
+Signed-off-by: Matt Porter <mporter@ti.com>
+Signed-off-by: Matt Ranostay <mranostay@gmail.com>
+---
+ arch/arm/boot/dts/am33xx.dtsi |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
+index 5e418c7..8bff718 100644
+--- a/arch/arm/boot/dts/am33xx.dtsi
++++ b/arch/arm/boot/dts/am33xx.dtsi
+@@ -467,6 +467,16 @@
+ 			interrupt = <61>;
+ 			ti,hwmods = "ecap2";
+ 			#pwm-cells = <3>;
++		};
++
++		pruss: pruss@4a300000 {
++			compatible = "ti,pruss-v2";
++			ti,hwmods = "pruss";
++			ti,deassert-hard-reset = "pruss", "pruss";
++			reg = <0x4a300000 0x080000>;
++			ti,pintc-offset = <0x20000>;
++			interrupt-parent = <&intc>;
++			interrupts = <20 21 22 23 24 25 26 27>;
+ 			status = "disabled";
+ 		};
+ 	};
diff --git a/patches/linux-3.7/0184-kbuild-deb-pkg-set-host-machine-after-dpkg-gencontro.patch b/patches/linux-3.7/0184-kbuild-deb-pkg-set-host-machine-after-dpkg-gencontro.patch
new file mode 100644
index 0000000..4e90647
--- /dev/null
+++ b/patches/linux-3.7/0184-kbuild-deb-pkg-set-host-machine-after-dpkg-gencontro.patch
@@ -0,0 +1,110 @@
+From: Robert Gordon <robert@greenroomsoftware.com>
+Date: Wed, 13 Apr 2011 11:32:29 -0500
+Subject: [PATCH] kbuild, deb-pkg: set host machine after dpkg-gencontrol
+
+scripts/package/builddeb script was setting the host machine
+$arch in the KERNEL/debian/control prior to an invocation of
+dpkg-gencontrol.  The patch modifies the script to guarantee the correct
+debian arch for the target is written to the control file instead.
+
+Signed-off-by: Robert Gordon <robert@greenroomsoftware.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ scripts/package/builddeb |   70 ++++++++++++++++++++++++----------------------
+ 1 file changed, 36 insertions(+), 34 deletions(-)
+
+diff --git a/scripts/package/builddeb b/scripts/package/builddeb
+index acb8650..72d6255 100644
+--- a/scripts/package/builddeb
++++ b/scripts/package/builddeb
+@@ -26,37 +26,7 @@ create_package() {
+ 	chmod -R go-w "$pdir"
+ 
+ 	# Attempt to find the correct Debian architecture
+-	local forcearch="" debarch=""
+-	case "$UTS_MACHINE" in
+-	i386|ia64|alpha)
+-		debarch="$UTS_MACHINE" ;;
+-	x86_64)
+-		debarch=amd64 ;;
+-	sparc*)
+-		debarch=sparc ;;
+-	s390*)
+-		debarch=s390 ;;
+-	ppc*)
+-		debarch=powerpc ;;
+-	parisc*)
+-		debarch=hppa ;;
+-	mips*)
+-		debarch=mips$(grep -q CPU_LITTLE_ENDIAN=y .config && echo el) ;;
+-	arm*)
+-		debarch=arm$(grep -q CONFIG_AEABI=y .config && echo el) ;;
+-	*)
+-		echo "" >&2
+-		echo "** ** **  WARNING  ** ** **" >&2
+-		echo "" >&2
+-		echo "Your architecture doesn't have it's equivalent" >&2
+-		echo "Debian userspace architecture defined!" >&2
+-		echo "Falling back to using your current userspace instead!" >&2
+-		echo "Please add support for $UTS_MACHINE to ${0} ..." >&2
+-		echo "" >&2
+-	esac
+-	if [ -n "$KBUILD_DEBARCH" ] ; then
+-		debarch="$KBUILD_DEBARCH"
+-	fi
++	local forcearch=""
+ 	if [ -n "$debarch" ] ; then
+ 		forcearch="-DArchitecture=$debarch"
+ 	fi
+@@ -66,6 +36,38 @@ create_package() {
+ 	dpkg --build "$pdir" ..
+ }
+ 
++#Set the correct debian arch
++case "$UTS_MACHINE" in
++i386|ia64|alpha)
++    debarch="$UTS_MACHINE" ;;
++x86_64)
++    debarch=amd64 ;;
++sparc*)
++    debarch=sparc ;;
++s390*)
++    debarch=s390 ;;
++ppc*)
++    debarch=powerpc ;;
++parisc*)
++    debarch=hppa ;;
++mips*)
++    debarch=mips$(grep -q CPU_LITTLE_ENDIAN=y .config && echo el) ;;
++arm*)
++    debarch=arm$(grep -q CONFIG_AEABI=y .config && echo el) ;;
++*)
++    echo "" >&2
++    echo "** ** **  WARNING  ** ** **" >&2
++    echo "" >&2
++    echo "Your architecture doesn't have it's equivalent" >&2
++    echo "Debian userspace architecture defined!" >&2
++    echo "Falling back to using your current userspace instead!" >&2
++    echo "Please add support for $UTS_MACHINE to ${0} ..." >&2
++    echo "" >&2
++esac
++if [ -n "$KBUILD_DEBARCH" ] ; then
++    debarch="$KBUILD_DEBARCH"
++fi
++
+ # Some variables and settings used throughout the script
+ version=$KERNELRELEASE
+ revision=$(cat .version)
+@@ -258,9 +260,9 @@ cat <<EOF >> debian/control
+ 
+ Package: $kernel_headers_packagename
+ Provides: linux-headers, linux-headers-2.6
+-Architecture: $arch
+-Description: Linux kernel headers for $KERNELRELEASE on $arch
+- This package provides kernel header files for $KERNELRELEASE on $arch
++Architecture: $debarch
++Description: Linux kernel headers for $KERNELRELEASE on $debarch
++ This package provides kernel header files for $KERNELRELEASE on $debarch
+  .
+  This is useful for people who need to build external modules
+ EOF
diff --git a/patches/linux-3.7/0185-arm-add-definition-of-strstr-to-decompress.c.patch b/patches/linux-3.7/0185-arm-add-definition-of-strstr-to-decompress.c.patch
new file mode 100644
index 0000000..0ec6ef4
--- /dev/null
+++ b/patches/linux-3.7/0185-arm-add-definition-of-strstr-to-decompress.c.patch
@@ -0,0 +1,36 @@
+From: Shawn Landden <shawnlandden@gmail.com>
+Date: Wed, 30 May 2012 13:45:08 -0700
+Subject: [PATCH] arm: add definition of strstr() to decompress.c
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+include/linux/dynamic_debug.h uses strstr from <linux/string.h>
+and is included via <linux/kernel.h> from lib/xz/xz_private.h
+when CONFIG_KERNEL_XZ=y.
+
+However arch/arm/boot/compressed/decompress.c defines _LINUX_STRING_H
+preventing the load of <linux/string.h> resulting in:
+
+include/linux/dynamic_debug.h:111:2: error: implicit declaration of function ‘strstr’
+
+Define strstr in arch/arm/boot/compressed/decompress.c, providing the needed
+subset of <linux/string.h>.
+
+Signed-off-by: Shawn Landden <shawnlandden@gmail.com>
+---
+ arch/arm/boot/compressed/decompress.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
+index 9deb56a..0f96125 100644
+--- a/arch/arm/boot/compressed/decompress.c
++++ b/arch/arm/boot/compressed/decompress.c
+@@ -50,6 +50,7 @@ extern char * strstr(const char * s1, const char *s2);
+ #ifdef CONFIG_KERNEL_XZ
+ #define memmove memmove
+ #define memcpy memcpy
++extern char * strstr(const char *, const char *);
+ #include "../../../../lib/decompress_unxz.c"
+ #endif
+ 
diff --git a/patches/linux-3.7/0187-mach-omap2-board-igep0020.c-Fix-reboot-problem.patch b/patches/linux-3.7/0187-mach-omap2-board-igep0020.c-Fix-reboot-problem.patch
new file mode 100644
index 0000000..0b6bfa7
--- /dev/null
+++ b/patches/linux-3.7/0187-mach-omap2-board-igep0020.c-Fix-reboot-problem.patch
@@ -0,0 +1,65 @@
+From: Matthias Brugger <matthias.bgg@googlemail.com>
+Date: Thu, 15 Nov 2012 17:06:53 +0100
+Subject: [PATCH] mach-omap2/board-igep0020.c: Fix reboot problem
+
+When rebooting an OMAP3530 at 125 MHz, the reboot hangs.
+This patch adds a generic power save script, which resets the TWL4030 when a
+warm reset occures. This way the OMAP3530 does not hang on reboot.
+
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm/mach-omap2/board-igep0020.c |   36 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index 3785906..3a7f295 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -487,11 +487,47 @@ static struct twl4030_keypad_data igep2_keypad_pdata = {
+ 	.rep		= 1,
+ };
+ 
++static struct twl4030_ins wrst_seq[] __initdata = {
++	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
++	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
++	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
++	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
++	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
++	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
++};
++
++static struct twl4030_script wrst_script __initdata = {
++	.script = wrst_seq,
++	.size   = ARRAY_SIZE(wrst_seq),
++	.flags  = TWL4030_WRST_SCRIPT,
++};
++
++static struct twl4030_script *twl4030_scripts[] __initdata = {
++	&wrst_script,
++};
++
++static struct twl4030_resconfig twl4030_rconfig[] = {
++	{ .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3, .type = -1,
++		.type2 = -1 },
++	{ .resource = RES_VDD1, .devgroup = DEV_GRP_P1, .type = -1,
++		.type2 = -1 },
++	{ .resource = RES_VDD2, .devgroup = DEV_GRP_P1, .type = -1,
++		.type2 = -1 },
++	{ 0, 0},
++};
++
++static struct twl4030_power_data igep_twl4030_power_data = {
++	.scripts	= twl4030_scripts,
++	.num		= ARRAY_SIZE(twl4030_scripts),
++	.resource_config = twl4030_rconfig,
++};
++
+ static struct twl4030_platform_data igep_twldata = {
+ 	/* platform_data for children goes here */
+ 	.gpio		= &igep_twl4030_gpio_pdata,
+ 	.vmmc1          = &igep_vmmc1,
+ 	.vio		= &igep_vio,
++	.power		= &igep_twl4030_power_data,
+ };
+ 
+ static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = {
diff --git a/patches/linux-3.7/0188-regulator-core-if-voltage-scaling-fails-restore-orig.patch b/patches/linux-3.7/0188-regulator-core-if-voltage-scaling-fails-restore-orig.patch
new file mode 100644
index 0000000..d811bdf
--- /dev/null
+++ b/patches/linux-3.7/0188-regulator-core-if-voltage-scaling-fails-restore-orig.patch
@@ -0,0 +1,53 @@
+From: Paolo Pisati <paolo.pisati@canonical.com>
+Date: Wed, 12 Dec 2012 12:45:53 +0100
+Subject: [PATCH] regulator: core: if voltage scaling fails, restore original
+ voltage values
+
+Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>
+---
+ drivers/regulator/core.c |   14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
+index e872c8b..564ef9f 100644
+--- a/drivers/regulator/core.c
++++ b/drivers/regulator/core.c
+@@ -2250,6 +2250,7 @@ int regulator_set_voltage(struct regulator *regulator, int min_uV, int max_uV)
+ {
+ 	struct regulator_dev *rdev = regulator->rdev;
+ 	int ret = 0;
++	int old_min_uV, old_max_uV;
+ 
+ 	mutex_lock(&rdev->mutex);
+ 
+@@ -2271,18 +2272,29 @@ int regulator_set_voltage(struct regulator *regulator, int min_uV, int max_uV)
+ 	ret = regulator_check_voltage(rdev, &min_uV, &max_uV);
+ 	if (ret < 0)
+ 		goto out;
++
++	/* restore original values in case of error */
++	old_min_uV = regulator->min_uV;
++	old_max_uV = regulator->max_uV;
+ 	regulator->min_uV = min_uV;
+ 	regulator->max_uV = max_uV;
+ 
+ 	ret = regulator_check_consumers(rdev, &min_uV, &max_uV);
+ 	if (ret < 0)
+-		goto out;
++		goto out2;
+ 
+ 	ret = _regulator_do_set_voltage(rdev, min_uV, max_uV);
++	if (ret < 0)
++		goto out2;
+ 
+ out:
+ 	mutex_unlock(&rdev->mutex);
+ 	return ret;
++out2:
++	regulator->min_uV = old_min_uV;
++	regulator->max_uV = old_max_uV;
++	mutex_unlock(&rdev->mutex);
++	return ret;
+ }
+ EXPORT_SYMBOL_GPL(regulator_set_voltage);
+ 
diff --git a/patches/linux-3.7/0190-OMAP-DSS2-add-bootarg-for-selecting-svideo.patch b/patches/linux-3.7/0190-OMAP-DSS2-add-bootarg-for-selecting-svideo.patch
new file mode 100644
index 0000000..be7a8d9
--- /dev/null
+++ b/patches/linux-3.7/0190-OMAP-DSS2-add-bootarg-for-selecting-svideo.patch
@@ -0,0 +1,74 @@
+From: Steve Sakoman <steve@sakoman.com>
+Date: Tue, 19 Jan 2010 21:19:15 -0800
+Subject: [PATCH] OMAP: DSS2: add bootarg for selecting svideo
+
+ OMAP: DSS2: add bootarg for selecting svideo or composite for tv output
+ also add pal-16 and ntsc-16 omapfb.mode settings for 16bpp
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ drivers/video/omap2/dss/venc.c           |   22 ++++++++++++++++++++++
+ drivers/video/omap2/omapfb/omapfb-main.c |   10 +++++++++-
+ 2 files changed, 31 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
+index 56efa3b..d46f7f8 100644
+--- a/drivers/video/omap2/dss/venc.c
++++ b/drivers/video/omap2/dss/venc.c
+@@ -86,6 +86,11 @@
+ #define VENC_OUTPUT_TEST			0xC8
+ #define VENC_DAC_B__DAC_C			0xC8
+ 
++static char *tv_connection;
++
++module_param_named(tvcable, tv_connection, charp, 0);
++MODULE_PARM_DESC(tvcable, "TV connection type (svideo, composite)");
++
+ struct venc_config {
+ 	u32 f_control;
+ 	u32 vidout_ctrl;
+@@ -465,6 +470,23 @@ static int venc_power_on(struct omap_dss_device *dssdev)
+ 	if (r)
+ 		goto err2;
+ 
++	/* Allow the TV output to be overriden */
++	if (tv_connection) {
++		if (strcmp(tv_connection, "svideo") == 0) {
++			printk(KERN_INFO
++				"omapdss: tv output is svideo.\n");
++			dssdev->phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
++		} else if (strcmp(tv_connection, "composite") == 0) {
++			printk(KERN_INFO
++				"omapdss: tv output is composite.\n");
++			dssdev->phy.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
++		} else {
++			printk(KERN_INFO
++				"omapdss: unsupported output type'%s'.\n",
++				tv_connection);
++		}
++	}
++
+ 	return 0;
+ 
+ err2:
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index 16db158..dca8650 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -2033,7 +2033,15 @@ static int omapfb_mode_to_timings(const char *mode_str,
+ 	int r;
+ 
+ #ifdef CONFIG_OMAP2_DSS_VENC
+-	if (strcmp(mode_str, "pal") == 0) {
++	if (strcmp(mode_str, "pal-16") == 0) {
++		*timings = omap_dss_pal_timings;
++		*bpp = 16;
++		return 0;
++	} else if (strcmp(mode_str, "ntsc-16") == 0) {
++		*timings = omap_dss_ntsc_timings;
++		*bpp = 16;
++		return 0;
++	} else if (strcmp(mode_str, "pal") == 0) {
+ 		*timings = omap_dss_pal_timings;
+ 		*bpp = 24;
+ 		return 0;
diff --git a/patches/linux-3.7/0191-video-add-timings-for-hd720.patch b/patches/linux-3.7/0191-video-add-timings-for-hd720.patch
new file mode 100644
index 0000000..9034278
--- /dev/null
+++ b/patches/linux-3.7/0191-video-add-timings-for-hd720.patch
@@ -0,0 +1,24 @@
+From: Steve Sakoman <steve@sakoman.com>
+Date: Sat, 19 Dec 2009 06:52:43 -0800
+Subject: [PATCH] video: add timings for hd720
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ drivers/video/modedb.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c
+index a9a907c..5b686de 100644
+--- a/drivers/video/modedb.c
++++ b/drivers/video/modedb.c
+@@ -103,6 +103,10 @@ static const struct fb_videomode modedb[] = {
+ 	{ NULL, 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6, 0,
+ 		FB_VMODE_NONINTERLACED },
+ 
++	/* 1280x720 @ 60 Hz, 45 kHz hsync, CEA 681-E Format 4 */
++	{ "hd720", 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5, 0,
++		FB_VMODE_NONINTERLACED },
++
+ 	/* 1280x1024 @ 87 Hz interlaced, 51 kHz hsync */
+ 	{ NULL, 87, 1280, 1024, 12500, 56, 16, 128, 1, 216, 12,	0,
+ 		FB_VMODE_INTERLACED },
diff --git a/patches/linux-3.7/0193-Beagle-expansion-add-buddy-param-for-expansionboard-.patch b/patches/linux-3.7/0193-Beagle-expansion-add-buddy-param-for-expansionboard-.patch
new file mode 100644
index 0000000..3c26820
--- /dev/null
+++ b/patches/linux-3.7/0193-Beagle-expansion-add-buddy-param-for-expansionboard-.patch
@@ -0,0 +1,58 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 11 Dec 2012 06:25:27 -0600
+Subject: [PATCH] Beagle: expansion: add buddy param for expansionboard names
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index d41ab98..dd282d5 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -21,6 +21,7 @@
+ #include <linux/io.h>
+ #include <linux/leds.h>
+ #include <linux/gpio.h>
++#include <linux/irq.h>
+ #include <linux/input.h>
+ #include <linux/gpio_keys.h>
+ #include <linux/opp.h>
+@@ -159,6 +160,8 @@ static void __init omap3_beagle_init_rev(void)
+ 	}
+ }
+ 
++char expansionboard_name[16];
++
+ static struct mtd_partition omap3beagle_nand_partitions[] = {
+ 	/* All the partition sizes are listed in terms of NAND block size */
+ 	{
+@@ -445,6 +448,18 @@ static struct omap_board_mux board_mux[] __initdata = {
+ };
+ #endif
+ 
++static int __init expansionboard_setup(char *str)
++{
++	if (!machine_is_omap3_beagle())
++		return 0;
++
++	if (!str)
++		return -EINVAL;
++	strncpy(expansionboard_name, str, 16);
++	pr_info("Beagle expansionboard: %s\n", expansionboard_name);
++	return 0;
++}
++
+ static int __init beagle_opp_init(void)
+ {
+ 	int r = 0;
+@@ -530,6 +545,8 @@ static void __init omap3_beagle_init(void)
+ 	omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+ }
+ 
++early_param("buddy", expansionboard_setup);
++
+ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
+ 	/* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
+ 	.atag_offset	= 0x100,
diff --git a/patches/linux-3.7/0194-Beagle-expansion-add-zippy.patch b/patches/linux-3.7/0194-Beagle-expansion-add-zippy.patch
new file mode 100644
index 0000000..e1080ec
--- /dev/null
+++ b/patches/linux-3.7/0194-Beagle-expansion-add-zippy.patch
@@ -0,0 +1,227 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 11 Dec 2012 06:30:06 -0600
+Subject: [PATCH] Beagle: expansion: add zippy
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |  163 +++++++++++++++++++++++++++++--
+ 1 file changed, 157 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index dd282d5..35ad593 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -162,6 +162,86 @@ static void __init omap3_beagle_init_rev(void)
+ 
+ char expansionboard_name[16];
+ 
++enum {
++	EXPANSION_MMC_NONE = 0,
++	EXPANSION_MMC_ZIPPY,
++	EXPANSION_MMC_WIFI,
++};
++
++enum {
++	EXPANSION_I2C_NONE = 0,
++	EXPANSION_I2C_ZIPPY,
++};
++
++static struct {
++	int mmc_settings;
++	int i2c_settings;
++} expansion_config = {
++	.mmc_settings = EXPANSION_MMC_NONE,
++	.i2c_settings = EXPANSION_I2C_NONE,
++};
++
++//rcn-ee: this is just a fake regulator, the zippy hardware provides 3.3/1.8 with jumper..
++static struct fixed_voltage_config beagle_vzippy = {
++	.supply_name = "vzippy",
++	.microvolts = 3300000,  /* 3.3V */
++	.startup_delay = 70000, /* 70ms */
++	.enable_high = 1,
++	.enabled_at_boot = 0,
++	.init_data = &beagle_vmmc2,
++};
++
++static struct platform_device omap_zippy_device = {
++	.name	= "reg-fixed-voltage",
++	.id		= 1,
++	.dev = {
++		.platform_data = &beagle_vzippy,
++	},
++};
++
++#define OMAP3BEAGLE_GPIO_ZIPPY_MMC_WP 141
++#define OMAP3BEAGLE_GPIO_ZIPPY_MMC_CD 162
++
++#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
++#include <linux/platform_data/spi-omap2-mcspi.h>
++#include <linux/spi/spi.h>
++
++#define OMAP3BEAGLE_GPIO_ENC28J60_IRQ 157
++
++static struct omap2_mcspi_device_config enc28j60_spi_chip_info = {
++	.turbo_mode	= 0,
++};
++
++static struct spi_board_info omap3beagle_zippy_spi_board_info[] __initdata = {
++	{
++		.modalias		= "enc28j60",
++		.bus_num		= 4,
++		.chip_select	= 0,
++		.max_speed_hz	= 20000000,
++		.controller_data	= &enc28j60_spi_chip_info,
++	},
++};
++
++static void __init omap3beagle_enc28j60_init(void)
++{
++	if ((gpio_request(OMAP3BEAGLE_GPIO_ENC28J60_IRQ, "ENC28J60_IRQ") == 0) &&
++	    (gpio_direction_input(OMAP3BEAGLE_GPIO_ENC28J60_IRQ) == 0)) {
++		gpio_export(OMAP3BEAGLE_GPIO_ENC28J60_IRQ, 0);
++		omap3beagle_zippy_spi_board_info[0].irq = gpio_to_irq(OMAP3BEAGLE_GPIO_ENC28J60_IRQ);
++		irq_set_irq_type(omap3beagle_zippy_spi_board_info[0].irq, IRQ_TYPE_EDGE_FALLING);
++	} else {
++		pr_err("Beagle expansionboard: could not obtain gpio for ENC28J60_IRQ\n");
++		return;
++	}
++
++	spi_register_board_info(omap3beagle_zippy_spi_board_info,
++			ARRAY_SIZE(omap3beagle_zippy_spi_board_info));
++}
++
++#else
++static inline void __init omap3beagle_enc28j60_init(void) { return; }
++#endif
++
+ static struct mtd_partition omap3beagle_nand_partitions[] = {
+ 	/* All the partition sizes are listed in terms of NAND block size */
+ 	{
+@@ -238,6 +318,23 @@ static struct omap2_hsmmc_info mmc[] = {
+ 	{}	/* Terminator */
+ };
+ 
++static struct omap2_hsmmc_info mmc_zippy[] = {
++	{
++		.mmc		= 1,
++		.caps		= MMC_CAP_4_BIT_DATA,
++		.gpio_wp	= -EINVAL,
++		.deferred	= true,
++	},
++	{
++		.mmc		= 2,
++		.caps		= MMC_CAP_4_BIT_DATA,
++		.gpio_wp	= OMAP3BEAGLE_GPIO_ZIPPY_MMC_WP,
++		.gpio_cd	= OMAP3BEAGLE_GPIO_ZIPPY_MMC_CD,
++		.transceiver	= true,
++		.deferred	= true,
++	},
++	{}	/* Terminator */
++};
+ static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
+ 	REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+@@ -253,10 +350,21 @@ static int beagle_twl_gpio_setup(struct device *dev,
+ {
+ 	int r;
+ 
+-	mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
+-	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
+-	mmc[0].gpio_cd = gpio + 0;
+-	omap_hsmmc_late_init(mmc);
++	switch (expansion_config.mmc_settings) {
++	case EXPANSION_MMC_ZIPPY:
++		mmc_zippy[0].gpio_wp = beagle_config.mmc1_gpio_wp;
++		/* gpio + 0 is "mmc0_cd" (input/IRQ) */
++		mmc_zippy[0].gpio_cd = gpio + 0;
++
++		omap_hsmmc_late_init(mmc_zippy);
++		break;
++	default:
++		mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
++		/* gpio + 0 is "mmc0_cd" (input/IRQ) */
++		mmc[0].gpio_cd = gpio + 0;
++
++		omap_hsmmc_late_init(mmc);
++	}
+ 
+ 	/*
+ 	 * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
+@@ -349,6 +457,14 @@ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
+        },
+ };
+ 
++static struct i2c_board_info __initdata zippy_i2c2_rtc[] = {
++#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE)
++	{
++		I2C_BOARD_INFO("ds1307", 0x68),
++	},
++#endif
++};
++
+ static int __init omap3_beagle_i2c_init(void)
+ {
+ 	omap3_pmic_get_config(&beagle_twldata,
+@@ -359,6 +475,15 @@ static int __init omap3_beagle_i2c_init(void)
+ 	beagle_twldata.vpll2->constraints.name = "VDVI";
+ 
+ 	omap3_pmic_init("twl4030", &beagle_twldata);
++
++	switch (expansion_config.i2c_settings) {
++	case EXPANSION_I2C_ZIPPY:
++		omap_register_i2c_bus(2, 400, zippy_i2c2_rtc, ARRAY_SIZE(zippy_i2c2_rtc));
++		break;
++	default:
++		omap_register_i2c_bus(2, 400, NULL, 0);
++	}
++
+ 	/* Bus 3 is attached to the DVI port where devices like the pico DLP
+ 	 * projector don't work reliably with 400kHz */
+ 	omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom));
+@@ -513,10 +638,30 @@ static void __init omap3_beagle_init(void)
+ 	omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ 	omap3_beagle_init_rev();
+ 
++	if (!strcmp(expansionboard_name, "zippy"))
++	{
++		pr_info("Beagle expansionboard: initializing zippy mmc\n");
++		platform_device_register(&omap_zippy_device);
++
++		expansion_config.i2c_settings = EXPANSION_I2C_ZIPPY;
++		expansion_config.mmc_settings = EXPANSION_MMC_ZIPPY;
++
++		omap_mux_init_gpio(OMAP3BEAGLE_GPIO_ZIPPY_MMC_WP, OMAP_PIN_INPUT);
++		omap_mux_init_gpio(OMAP3BEAGLE_GPIO_ZIPPY_MMC_CD, OMAP_PIN_INPUT);
++	}
++
+ 	if (gpio_is_valid(beagle_config.mmc1_gpio_wp))
+ 		omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
+-	mmc[0].caps = beagle_config.mmc_caps;
+-	omap_hsmmc_init(mmc);
++
++	switch (expansion_config.mmc_settings) {
++	case EXPANSION_MMC_ZIPPY:
++		mmc_zippy[0].caps = beagle_config.mmc_caps;
++		omap_hsmmc_init(mmc_zippy);
++		break;
++	default:
++		mmc[0].caps = beagle_config.mmc_caps;
++		omap_hsmmc_init(mmc);
++	}
+ 
+ 	omap3_beagle_i2c_init();
+ 
+@@ -531,6 +676,12 @@ static void __init omap3_beagle_init(void)
+ 	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+ 				  mt46h32m32lf6_sdrc_params);
+ 
++	if (!strcmp(expansionboard_name, "zippy"))
++	{
++		pr_info("Beagle expansionboard: initializing enc28j60\n");
++		omap3beagle_enc28j60_init();
++	}
++
+ 	usb_musb_init(NULL);
+ 	usbhs_init(&usbhs_bdata);
+ 	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
diff --git a/patches/linux-3.7/0195-Beagle-expansion-add-zippy2.patch b/patches/linux-3.7/0195-Beagle-expansion-add-zippy2.patch
new file mode 100644
index 0000000..ab4a4ce
--- /dev/null
+++ b/patches/linux-3.7/0195-Beagle-expansion-add-zippy2.patch
@@ -0,0 +1,82 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 11 Dec 2012 06:32:15 -0600
+Subject: [PATCH] Beagle: expansion: add zippy2
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   48 ++++++++++++++++++++++++++++++-
+ 1 file changed, 47 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 35ad593..c762083 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -242,6 +242,46 @@ static void __init omap3beagle_enc28j60_init(void)
+ static inline void __init omap3beagle_enc28j60_init(void) { return; }
+ #endif
+ 
++#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
++#include <linux/platform_data/spi-omap2-mcspi.h>
++#include <linux/spi/spi.h>
++
++#define OMAP3BEAGLE_GPIO_KS8851_IRQ 157
++
++static struct omap2_mcspi_device_config ks8851_spi_chip_info = {
++	.turbo_mode	= 0,
++};
++
++static struct spi_board_info omap3beagle_zippy2_spi_board_info[] __initdata = {
++	{
++		.modalias		= "ks8851",
++		.bus_num		= 4,
++		.chip_select	= 0,
++		.max_speed_hz	= 36000000,
++		.controller_data	= &ks8851_spi_chip_info,
++	},
++};
++
++static void __init omap3beagle_ks8851_init(void)
++{
++	if ((gpio_request(OMAP3BEAGLE_GPIO_KS8851_IRQ, "KS8851_IRQ") == 0) &&
++	    (gpio_direction_input(OMAP3BEAGLE_GPIO_KS8851_IRQ) == 0)) {
++		gpio_export(OMAP3BEAGLE_GPIO_KS8851_IRQ, 0);
++		omap3beagle_zippy2_spi_board_info[0].irq = gpio_to_irq(OMAP3BEAGLE_GPIO_KS8851_IRQ);
++		irq_set_irq_type(omap3beagle_zippy2_spi_board_info[0].irq, IRQ_TYPE_EDGE_FALLING);
++	} else {
++		pr_err("Beagle expansionboard: could not obtain gpio for KS8851_IRQ\n");
++		return;
++	}
++
++	spi_register_board_info(omap3beagle_zippy2_spi_board_info,
++			ARRAY_SIZE(omap3beagle_zippy2_spi_board_info));
++}
++
++#else
++static inline void __init omap3beagle_ks8851_init(void) { return; }
++#endif
++
+ static struct mtd_partition omap3beagle_nand_partitions[] = {
+ 	/* All the partition sizes are listed in terms of NAND block size */
+ 	{
+@@ -638,7 +678,7 @@ static void __init omap3_beagle_init(void)
+ 	omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ 	omap3_beagle_init_rev();
+ 
+-	if (!strcmp(expansionboard_name, "zippy"))
++	if ((!strcmp(expansionboard_name, "zippy")) || (!strcmp(expansionboard_name, "zippy2")))
+ 	{
+ 		pr_info("Beagle expansionboard: initializing zippy mmc\n");
+ 		platform_device_register(&omap_zippy_device);
+@@ -682,6 +722,12 @@ static void __init omap3_beagle_init(void)
+ 		omap3beagle_enc28j60_init();
+ 	}
+ 
++	if (!strcmp(expansionboard_name, "zippy2"))
++	{
++		pr_info("Beagle expansionboard: initializing ks_8851\n");
++		omap3beagle_ks8851_init();
++	}
++
+ 	usb_musb_init(NULL);
+ 	usbhs_init(&usbhs_bdata);
+ 	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
diff --git a/patches/linux-3.7/0196-Beagle-expansion-add-trainer.patch b/patches/linux-3.7/0196-Beagle-expansion-add-trainer.patch
new file mode 100644
index 0000000..d7e75e5
--- /dev/null
+++ b/patches/linux-3.7/0196-Beagle-expansion-add-trainer.patch
@@ -0,0 +1,51 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 11 Dec 2012 06:33:24 -0600
+Subject: [PATCH] Beagle: expansion: add trainer
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   31 +++++++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index c762083..c6b33e7 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -728,6 +728,37 @@ static void __init omap3_beagle_init(void)
+ 		omap3beagle_ks8851_init();
+ 	}
+ 
++	if (!strcmp(expansionboard_name, "trainer"))
++	{
++		pr_info("Beagle expansionboard: exporting GPIOs 130-141,162 to userspace\n");
++		gpio_request(130, "sysfs");
++		gpio_export(130, 1);
++		gpio_request(131, "sysfs");
++		gpio_export(131, 1);
++		gpio_request(132, "sysfs");
++		gpio_export(132, 1);
++		gpio_request(133, "sysfs");
++		gpio_export(133, 1);
++		gpio_request(134, "sysfs");
++		gpio_export(134, 1);
++		gpio_request(135, "sysfs");
++		gpio_export(135, 1);
++		gpio_request(136, "sysfs");
++		gpio_export(136, 1);
++		gpio_request(137, "sysfs");
++		gpio_export(137, 1);
++		gpio_request(138, "sysfs");
++		gpio_export(138, 1);
++		gpio_request(139, "sysfs");
++		gpio_export(139, 1);
++		gpio_request(140, "sysfs");
++		gpio_export(140, 1);
++		gpio_request(141, "sysfs");
++		gpio_export(141, 1);
++		gpio_request(162, "sysfs");
++		gpio_export(162, 1);
++	}
++
+ 	usb_musb_init(NULL);
+ 	usbhs_init(&usbhs_bdata);
+ 	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
diff --git a/patches/linux-3.7/0197-Beagle-expansion-add-CircuitCo-ulcd-Support.patch b/patches/linux-3.7/0197-Beagle-expansion-add-CircuitCo-ulcd-Support.patch
new file mode 100644
index 0000000..f546eca
--- /dev/null
+++ b/patches/linux-3.7/0197-Beagle-expansion-add-CircuitCo-ulcd-Support.patch
@@ -0,0 +1,290 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 11 Dec 2012 06:42:03 -0600
+Subject: [PATCH] Beagle: expansion: add CircuitCo ulcd Support
+
+This of a cleanup, squashed both ulcd commits into one:
+
+======================================================================
+
+expansion: add ulcd
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+
+======================================================================
+
+beagleboard: fix uLCD7 support
+Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
+
+======================================================================
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c          |  138 ++++++++++++++++++++++
+ drivers/video/omap2/displays/panel-generic-dpi.c |   27 +++++
+ 2 files changed, 165 insertions(+)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index c6b33e7..6cb7815 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -42,6 +42,7 @@
+ 
+ #include "common.h"
+ #include <video/omapdss.h>
++#include <video/omap-panel-generic-dpi.h>
+ #include <video/omap-panel-tfp410.h>
+ #include <plat/gpmc.h>
+ #include <linux/platform_data/mtd-nand-omap2.h>
+@@ -84,12 +85,16 @@ static struct {
+ 	int dvi_pd_gpio;
+ 	int usr_button_gpio;
+ 	int mmc_caps;
++	char *lcd_driver_name;
++	int lcd_pwren;
+ } beagle_config = {
+ 	.mmc1_gpio_wp = -EINVAL,
+ 	.usb_pwr_level = GPIOF_OUT_INIT_LOW,
+ 	.dvi_pd_gpio = -EINVAL,
+ 	.usr_button_gpio = 4,
+ 	.mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
++	.lcd_driver_name = "",
++	.lcd_pwren = 156,
+ };
+ 
+ static struct gpio omap3_beagle_rev_gpios[] __initdata = {
+@@ -161,6 +166,7 @@ static void __init omap3_beagle_init_rev(void)
+ }
+ 
+ char expansionboard_name[16];
++char expansionboard2_name[16];
+ 
+ enum {
+ 	EXPANSION_MMC_NONE = 0,
+@@ -171,6 +177,7 @@ enum {
+ enum {
+ 	EXPANSION_I2C_NONE = 0,
+ 	EXPANSION_I2C_ZIPPY,
++	EXPANSION_I2C_7ULCD,
+ };
+ 
+ static struct {
+@@ -335,9 +342,53 @@ static struct omap_dss_device beagle_tv_device = {
+ 	.phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
+ };
+ 
++static int beagle_enable_lcd(struct omap_dss_device *dssdev)
++{
++	if (gpio_is_valid(beagle_config.lcd_pwren)) {
++		pr_info("%s: Enabling LCD\n", __FUNCTION__);
++		gpio_set_value(beagle_config.lcd_pwren, 0);
++	} else {
++		pr_info("%s: Invalid LCD enable GPIO: %d\n",
++			__FUNCTION__, beagle_config.lcd_pwren);
++	}
++
++	return 0;
++}
++
++static void beagle_disable_lcd(struct omap_dss_device *dssdev)
++{
++	if (gpio_is_valid(beagle_config.lcd_pwren)) {
++		pr_info("%s: Disabling LCD\n", __FUNCTION__);
++		gpio_set_value(beagle_config.lcd_pwren, 1);
++	} else {
++		pr_info("%s: Invalid LCD enable GPIO: %d\n",
++			__FUNCTION__, beagle_config.lcd_pwren);
++	}
++
++	return;
++}
++
++static struct panel_generic_dpi_data lcd_panel = {
++	.name = "tfc_s9700rtwv35tr-01b",
++	.platform_enable = beagle_enable_lcd,
++	.platform_disable = beagle_disable_lcd,
++};
++
++static struct omap_dss_device beagle_lcd_device = {
++	.type                   = OMAP_DISPLAY_TYPE_DPI,
++	.name                   = "lcd",
++	.driver_name		= "generic_dpi_panel",
++	.phy.dpi.data_lines     = 24,
++	.platform_enable        = beagle_enable_lcd,
++	.platform_disable       = beagle_disable_lcd,
++	.reset_gpio 		= -EINVAL,
++	.data			= &lcd_panel,
++};
++
+ static struct omap_dss_device *beagle_dss_devices[] = {
+ 	&beagle_dvi_device,
+ 	&beagle_tv_device,
++	&beagle_lcd_device,
+ };
+ 
+ static struct omap_dss_board_info beagle_dss_data = {
+@@ -505,6 +556,54 @@ static struct i2c_board_info __initdata zippy_i2c2_rtc[] = {
+ #endif
+ };
+ 
++#if defined(CONFIG_TOUCHSCREEN_TSC2007) || defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
++/* Touchscreen */
++#include <linux/i2c/tsc2007.h>
++
++#define OMAP3BEAGLE_TSC2007_GPIO 157
++
++static int omap3beagle_tsc2007_get_pendown_state(void)
++{
++	return !gpio_get_value(OMAP3BEAGLE_TSC2007_GPIO);
++}
++
++static struct tsc2007_platform_data tsc2007_info = {
++	.model = 2007,
++	.x_plate_ohms = 180,
++	.get_pendown_state = omap3beagle_tsc2007_get_pendown_state,
++};
++
++static struct i2c_board_info __initdata beagle_i2c2_bbtoys_ulcd[] = {
++	{
++		I2C_BOARD_INFO("tlc59108", 0x40),
++	},
++	{
++		I2C_BOARD_INFO("tsc2007", 0x48),
++		.platform_data = &tsc2007_info,
++	},
++};
++
++static void __init omap3beagle_tsc2007_init(void)
++{
++	int r;
++
++	omap_mux_init_gpio(OMAP3BEAGLE_TSC2007_GPIO, OMAP_PIN_INPUT_PULLUP);
++
++	r = gpio_request_one(OMAP3BEAGLE_TSC2007_GPIO, GPIOF_IN, "tsc2007_pen_down");
++	if (r < 0) {
++		pr_err("Beagle expansionboard: failed to request GPIO#%d for "
++		"tsc2007 pen down IRQ\n", OMAP3BEAGLE_TSC2007_GPIO);
++		return;
++	}
++
++	beagle_i2c2_bbtoys_ulcd[0].irq = gpio_to_irq(OMAP3BEAGLE_TSC2007_GPIO);
++	irq_set_irq_type(gpio_to_irq(OMAP3BEAGLE_TSC2007_GPIO), IRQ_TYPE_EDGE_FALLING);
++}
++#else
++static struct i2c_board_info __initdata beagle_i2c2_bbtoys_ulcd[] = {};
++static void __init omap3beagle_tsc2007_init(void) { return; }
++#endif
++
+ static int __init omap3_beagle_i2c_init(void)
+ {
+ 	omap3_pmic_get_config(&beagle_twldata,
+@@ -517,6 +616,10 @@ static int __init omap3_beagle_i2c_init(void)
+ 	omap3_pmic_init("twl4030", &beagle_twldata);
+ 
+ 	switch (expansion_config.i2c_settings) {
++	case EXPANSION_I2C_7ULCD:
++		omap_register_i2c_bus(2, 400,  beagle_i2c2_bbtoys_ulcd,
++							ARRAY_SIZE(beagle_i2c2_bbtoys_ulcd));
++		break;
+ 	case EXPANSION_I2C_ZIPPY:
+ 		omap_register_i2c_bus(2, 400, zippy_i2c2_rtc, ARRAY_SIZE(zippy_i2c2_rtc));
+ 		break;
+@@ -625,6 +728,18 @@ static int __init expansionboard_setup(char *str)
+ 	return 0;
+ }
+ 
++static int __init expansionboard2_setup(char *str)
++{
++	if (!machine_is_omap3_beagle())
++		return 0;
++
++	if (!str)
++		return -EINVAL;
++	strncpy(expansionboard2_name, str, 16);
++	pr_info("Beagle expansionboard2: %s\n", expansionboard2_name);
++	return 0;
++}
++
+ static int __init beagle_opp_init(void)
+ {
+ 	int r = 0;
+@@ -690,6 +805,20 @@ static void __init omap3_beagle_init(void)
+ 		omap_mux_init_gpio(OMAP3BEAGLE_GPIO_ZIPPY_MMC_CD, OMAP_PIN_INPUT);
+ 	}
+ 
++	if (!strcmp(expansionboard2_name, "bbtoys-ulcd"))
++	{
++		int r;
++		expansion_config.i2c_settings = EXPANSION_I2C_7ULCD;
++
++		/* TODO: set lcd_driver_name by command line or device tree */
++		beagle_config.lcd_driver_name = "tfc_s9700rtwv35tr-01b",
++		lcd_panel.name = beagle_config.lcd_driver_name;
++
++		r = gpio_request_one(beagle_config.lcd_pwren, GPIOF_OUT_INIT_LOW, "LCD power");
++		if (r < 0)
++			pr_err("Beagle expansionboard: Unable to get LCD power enable GPIO\n");
++	}
++
+ 	if (gpio_is_valid(beagle_config.mmc1_gpio_wp))
+ 		omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
+ 
+@@ -759,6 +888,14 @@ static void __init omap3_beagle_init(void)
+ 		gpio_export(162, 1);
+ 	}
+ 
++	if (!strcmp(expansionboard2_name, "bbtoys-ulcd"))
++	{
++	#if defined(CONFIG_TOUCHSCREEN_TSC2007) || defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
++		pr_info("Beagle expansionboard: initializing touchscreen: tsc2007\n");
++		omap3beagle_tsc2007_init();
++	#endif
++	}
++
+ 	usb_musb_init(NULL);
+ 	usbhs_init(&usbhs_bdata);
+ 	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
+@@ -774,6 +911,7 @@ static void __init omap3_beagle_init(void)
+ }
+ 
+ early_param("buddy", expansionboard_setup);
++early_param("buddy2", expansionboard2_setup);
+ 
+ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
+ 	/* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
+diff --git a/drivers/video/omap2/displays/panel-generic-dpi.c b/drivers/video/omap2/displays/panel-generic-dpi.c
+index 88295c5..b7f296b 100644
+--- a/drivers/video/omap2/displays/panel-generic-dpi.c
++++ b/drivers/video/omap2/displays/panel-generic-dpi.c
+@@ -538,6 +538,33 @@ static struct panel_config generic_dpi_panels[] = {
+ 		},
+ 		.name			= "primeview_pd104slf",
+ 	},
++
++	/* ThreeFiveCorp S9700RTWV35TR-01B */
++	{
++		{
++			.x_res		= 800,
++			.y_res		= 480,
++
++			.pixel_clock	= 30000,
++
++			.hsw		= 49,
++			.hfp		= 41,
++			.hbp		= 40,
++
++			.vsw		= 4,
++			.vfp		= 14,
++			.vbp		= 29,
++
++			.vsync_level	= OMAPDSS_SIG_ACTIVE_LOW,
++			.hsync_level	= OMAPDSS_SIG_ACTIVE_LOW,
++			.data_pclk_edge	= OMAPDSS_DRIVE_SIG_RISING_EDGE,
++			.de_level	= OMAPDSS_SIG_ACTIVE_HIGH,
++			.sync_pclk_edge	= OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
++		},
++		.power_on_delay		= 50,
++		.power_off_delay	= 100,
++		.name			= "tfc_s9700rtwv35tr-01b",
++	},
+ };
+ 
+ struct panel_drv_data {
diff --git a/patches/linux-3.7/0198-Beagle-expansion-add-wifi.patch b/patches/linux-3.7/0198-Beagle-expansion-add-wifi.patch
new file mode 100644
index 0000000..f585673
--- /dev/null
+++ b/patches/linux-3.7/0198-Beagle-expansion-add-wifi.patch
@@ -0,0 +1,172 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 11 Dec 2012 06:48:52 -0600
+Subject: [PATCH] Beagle: expansion: add wifi
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |  117 +++++++++++++++++++++++++++++++
+ 1 file changed, 117 insertions(+)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 6cb7815..03773cb 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -188,6 +188,71 @@ static struct {
+ 	.i2c_settings = EXPANSION_I2C_NONE,
+ };
+ 
++#if defined(CONFIG_WL12XX) || defined(CONFIG_WL12XX_MODULE)
++#include <linux/regulator/fixed.h>
++#include <linux/ti_wilink_st.h>
++#include <linux/wl12xx.h>
++
++#define OMAP_BEAGLE_WLAN_EN_GPIO    (139)
++#define OMAP_BEAGLE_BT_EN_GPIO      (138)
++#define OMAP_BEAGLE_WLAN_IRQ_GPIO   (137)
++#define OMAP_BEAGLE_FM_EN_BT_WU     (136)
++
++struct wl12xx_platform_data omap_beagle_wlan_data __initdata = {
++	.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
++};
++
++static struct ti_st_plat_data wilink_platform_data = {
++	.nshutdown_gpio	= OMAP_BEAGLE_BT_EN_GPIO,
++	.dev_name		= "/dev/ttyO1",
++	.flow_cntrl		= 1,
++	.baud_rate		= 3000000,
++	.chip_enable	= NULL,
++	.suspend		= NULL,
++	.resume			= NULL,
++};
++
++static struct platform_device wl12xx_device = {
++		.name		= "kim",
++		.id			= -1,
++		.dev.platform_data = &wilink_platform_data,
++};
++
++static struct platform_device btwilink_device = {
++	.name	= "btwilink",
++	.id	= -1,
++};
++
++static struct regulator_consumer_supply beagle_vmmc2_supply =
++	REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
++
++static struct regulator_init_data beagle_vmmc2 = {
++	.constraints = {
++		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
++	},
++	.num_consumer_supplies = 1,
++	.consumer_supplies = &beagle_vmmc2_supply,
++};
++
++static struct fixed_voltage_config beagle_vwlan = {
++	.supply_name = "vwl1271",
++	.microvolts = 1800000,  /* 1.8V */
++	.gpio = OMAP_BEAGLE_WLAN_EN_GPIO,
++	.startup_delay = 70000, /* 70ms */
++	.enable_high = 1,
++	.enabled_at_boot = 0,
++	.init_data = &beagle_vmmc2,
++};
++
++static struct platform_device omap_vwlan_device = {
++	.name		= "reg-fixed-voltage",
++	.id		= 1,
++	.dev = {
++		.platform_data = &beagle_vwlan,
++	},
++};
++#endif
++
+ //rcn-ee: this is just a fake regulator, the zippy hardware provides 3.3/1.8 with jumper..
+ static struct fixed_voltage_config beagle_vzippy = {
+ 	.supply_name = "vzippy",
+@@ -426,6 +491,26 @@ static struct omap2_hsmmc_info mmc_zippy[] = {
+ 	},
+ 	{}	/* Terminator */
+ };
++
++static struct omap2_hsmmc_info mmcbbt[] = {
++	{
++		.mmc		= 1,
++		.caps		= MMC_CAP_4_BIT_DATA,
++		.gpio_wp	= -EINVAL,
++		.deferred	= true,
++	},
++	{
++		.name		= "wl1271",
++		.mmc		= 2,
++		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
++		.gpio_wp	= -EINVAL,
++		.gpio_cd	= -EINVAL,
++		.ocr_mask	= MMC_VDD_165_195,
++		.nonremovable	= true,
++	},
++	{}	/* Terminator */
++};
++
+ static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
+ 	REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+@@ -442,6 +527,13 @@ static int beagle_twl_gpio_setup(struct device *dev,
+ 	int r;
+ 
+ 	switch (expansion_config.mmc_settings) {
++	case EXPANSION_MMC_WIFI:
++		mmcbbt[0].gpio_wp = beagle_config.mmc1_gpio_wp;
++		/* gpio + 0 is "mmc0_cd" (input/IRQ) */
++		mmcbbt[0].gpio_cd = gpio + 0;
++
++		omap_hsmmc_late_init(mmcbbt);
++		break;
+ 	case EXPANSION_MMC_ZIPPY:
+ 		mmc_zippy[0].gpio_wp = beagle_config.mmc1_gpio_wp;
+ 		/* gpio + 0 is "mmc0_cd" (input/IRQ) */
+@@ -805,6 +897,13 @@ static void __init omap3_beagle_init(void)
+ 		omap_mux_init_gpio(OMAP3BEAGLE_GPIO_ZIPPY_MMC_CD, OMAP_PIN_INPUT);
+ 	}
+ 
++	if (!strcmp(expansionboard_name, "bbtoys-wifi"))
++	{
++	#if defined(CONFIG_WL12XX) || defined(CONFIG_WL12XX_MODULE)
++		expansion_config.mmc_settings = EXPANSION_MMC_WIFI;
++	#endif
++	}
++
+ 	if (!strcmp(expansionboard2_name, "bbtoys-ulcd"))
+ 	{
+ 		int r;
+@@ -823,6 +922,10 @@ static void __init omap3_beagle_init(void)
+ 		omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
+ 
+ 	switch (expansion_config.mmc_settings) {
++	case EXPANSION_MMC_WIFI:
++		mmcbbt[0].caps = beagle_config.mmc_caps;
++		omap_hsmmc_init(mmcbbt);
++		break;
+ 	case EXPANSION_MMC_ZIPPY:
+ 		mmc_zippy[0].caps = beagle_config.mmc_caps;
+ 		omap_hsmmc_init(mmc_zippy);
+@@ -888,6 +991,20 @@ static void __init omap3_beagle_init(void)
+ 		gpio_export(162, 1);
+ 	}
+ 
++	if (!strcmp(expansionboard_name, "bbtoys-wifi"))
++	{
++	#if defined(CONFIG_WL12XX) || defined(CONFIG_WL12XX_MODULE)
++		omap_beagle_wlan_data.irq = gpio_to_irq(OMAP_BEAGLE_WLAN_IRQ_GPIO);
++		if (wl12xx_set_platform_data(&omap_beagle_wlan_data))
++			pr_err("error setting wl12xx data\n");
++		pr_info("Beagle expansionboard: registering wl12xx bt platform device\n");
++		platform_device_register(&wl12xx_device);
++		platform_device_register(&btwilink_device);
++		pr_info("Beagle expansionboard: registering wl12xx wifi platform device\n");
++		platform_device_register(&omap_vwlan_device);
++	#endif
++	}
++
+ 	if (!strcmp(expansionboard2_name, "bbtoys-ulcd"))
+ 	{
+ 	#if defined(CONFIG_TOUCHSCREEN_TSC2007) || defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
diff --git a/patches/linux-3.7/0199-Beagle-expansion-add-beaglefpga.patch b/patches/linux-3.7/0199-Beagle-expansion-add-beaglefpga.patch
new file mode 100644
index 0000000..2c8efc4
--- /dev/null
+++ b/patches/linux-3.7/0199-Beagle-expansion-add-beaglefpga.patch
@@ -0,0 +1,111 @@
+From: Bas van der Doorn <bas@doornvd.com>
+Date: Tue, 11 Dec 2012 06:52:22 -0600
+Subject: [PATCH] Beagle: expansion: add beaglefpga
+
+Added SPI dev and McBSP 3 mux when FPGA is detected
+
+Signed-off-by: Bas van der Doorn <bas@doornvd.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   74 +++++++++++++++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 03773cb..e6000f4 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -39,6 +39,7 @@
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/mach/flash.h>
++#include <linux/spi/spi.h>
+ 
+ #include "common.h"
+ #include <video/omapdss.h>
+@@ -880,6 +881,68 @@ static int __init beagle_opp_init(void)
+ }
+ device_initcall(beagle_opp_init);
+ 
++static void __init omap3_beagle_config_mcspi3_mux(void)
++{
++	/* NOTE: Clock pins need to be in input mode */
++	omap_mux_init_signal("sdmmc2_clk.mcspi3_clk", OMAP_PIN_INPUT);
++	omap_mux_init_signal("sdmmc2_cmd.mcspi3_simo", OMAP_PIN_OUTPUT);
++	omap_mux_init_signal("sdmmc2_dat0.mcspi3_somi", OMAP_PIN_INPUT_PULLUP);
++	omap_mux_init_signal("sdmmc2_dat2.mcspi3_cs1", OMAP_PIN_OUTPUT);
++	omap_mux_init_signal("sdmmc2_dat3.mcspi3_cs0", OMAP_PIN_OUTPUT);
++}
++
++static void __init omap3_beagle_config_mcspi4_mux(void)
++{
++	/* NOTE: Clock pins need to be in input mode */
++	omap_mux_init_signal("mcbsp1_clkr.mcspi4_clk", OMAP_PIN_INPUT);
++	omap_mux_init_signal("mcbsp1_dx.mcspi4_simo", OMAP_PIN_OUTPUT);
++	omap_mux_init_signal("mcbsp1_dr.mcspi4_somi", OMAP_PIN_INPUT_PULLUP);
++	omap_mux_init_signal("mcbsp1_fsx.mcspi4_cs0", OMAP_PIN_OUTPUT);
++}
++
++static void __init omap3_beagle_config_mcbsp3_mux(void)
++{
++	omap_mux_init_signal("mcbsp3_fsx.uart2_rx", OMAP_PIN_INPUT);
++	omap_mux_init_signal("uart2_cts.mcbsp3_dx", OMAP_PIN_OUTPUT);
++	omap_mux_init_signal("uart2_rts.mcbsp3_dr", OMAP_PIN_INPUT);
++	/* NOTE: Clock pins need to be in input mode */
++	omap_mux_init_signal("uart2_tx.mcbsp3_clkx", OMAP_PIN_INPUT);
++}
++
++static void __init omap3_beagle_config_fpga_mux(void)
++{
++	omap3_beagle_config_mcbsp3_mux();
++	omap3_beagle_config_mcspi3_mux();
++	omap3_beagle_config_mcspi4_mux();
++}
++
++static struct spi_board_info beagle_mcspi_board_info[] = {
++	/* spi 3.0 */
++	{
++		.modalias	= "spidev",
++		.max_speed_hz	= 48000000, //48 Mbps
++		.bus_num	= 3,
++		.chip_select	= 0,
++		.mode = SPI_MODE_1,
++	},
++	/* spi 3.1 */
++	{
++		.modalias	= "spidev",
++		.max_speed_hz	= 48000000, //48 Mbps
++		.bus_num	= 3,
++		.chip_select	= 1,
++		.mode = SPI_MODE_1,
++	},
++	/* spi 4.0 */
++	{
++		.modalias	= "spidev",
++		.max_speed_hz	= 48000000, //48 Mbps
++		.bus_num	= 4,
++		.chip_select	= 0,
++		.mode = SPI_MODE_1,
++	},
++};
++
+ static void __init omap3_beagle_init(void)
+ {
+ 	omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+@@ -1005,6 +1068,17 @@ static void __init omap3_beagle_init(void)
+ 	#endif
+ 	}
+ 
++	if (!strcmp(expansionboard_name, "beaglefpga"))
++	{
++		pr_info("Beagle expansionboard: enabling SPIdev for McSPI3/4 and pin muxing for McBSP3 slave mode\n");
++
++		/* FPGA pin settings configure McSPI 3, McSPI 4 and McBSP 3 */
++		omap3_beagle_config_fpga_mux();
++
++		/* register McSPI 3 and McSPI 4 for FPGA programming and control */
++		spi_register_board_info(beagle_mcspi_board_info, ARRAY_SIZE(beagle_mcspi_board_info));
++	}
++
+ 	if (!strcmp(expansionboard2_name, "bbtoys-ulcd"))
+ 	{
+ 	#if defined(CONFIG_TOUCHSCREEN_TSC2007) || defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
diff --git a/patches/linux-3.7/0200-Beagle-expansion-add-spidev.patch b/patches/linux-3.7/0200-Beagle-expansion-add-spidev.patch
new file mode 100644
index 0000000..47b5ae4
--- /dev/null
+++ b/patches/linux-3.7/0200-Beagle-expansion-add-spidev.patch
@@ -0,0 +1,29 @@
+From: Russell Hay <russell.hay@gmail.com>
+Date: Tue, 11 Dec 2012 06:53:58 -0600
+Subject: [PATCH] Beagle: expansion: add spidev
+
+Signed-off-by: Russell Hay <russell.hay@gmail.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |    8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index e6000f4..64b3444 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -1079,6 +1079,14 @@ static void __init omap3_beagle_init(void)
+ 		spi_register_board_info(beagle_mcspi_board_info, ARRAY_SIZE(beagle_mcspi_board_info));
+ 	}
+ 
++	if (!strcmp(expansionboard_name, "spidev"))
++	{
++		pr_info("Beagle expansionboard: registering spidev\n");
++		omap3_beagle_config_mcspi3_mux();
++		omap3_beagle_config_mcspi4_mux();
++		spi_register_board_info(beagle_mcspi_board_info, ARRAY_SIZE(beagle_mcspi_board_info));
++	}
++
+ 	if (!strcmp(expansionboard2_name, "bbtoys-ulcd"))
+ 	{
+ 	#if defined(CONFIG_TOUCHSCREEN_TSC2007) || defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
diff --git a/patches/linux-3.7/0201-Beagle-expansion-add-Aptina-li5m03-camera.patch b/patches/linux-3.7/0201-Beagle-expansion-add-Aptina-li5m03-camera.patch
new file mode 100644
index 0000000..9099b3c
--- /dev/null
+++ b/patches/linux-3.7/0201-Beagle-expansion-add-Aptina-li5m03-camera.patch
@@ -0,0 +1,223 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 11 Dec 2012 06:58:15 -0600
+Subject: [PATCH] Beagle: expansion: add Aptina li5m03 camera
+
+Based on:
+https://github.com/Aptina/BeagleBoard-xM/blob/master/tools/0266-Adding-MT9P031-Support-files.patch
+
+And on Max Galemin's patch
+https://github.com/MaxGalemin/buildroot/blob/master/board/beagleboard/xm/kernel-patches/linux-0003-Add-support-for-MT9P031-Aptina-image-sensor-driver.patch
+
+And Koen Kooi Previous work's
+https://github.com/beagleboard/kernel/blob/beagleboard-3.2/patches/camera/0003-beagleboard-fix-i2c2-init.patch
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |  152 +++++++++++++++++++++++++++++++
+ 1 file changed, 152 insertions(+)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 64b3444..c64ea55 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -168,6 +168,7 @@ static void __init omap3_beagle_init_rev(void)
+ 
+ char expansionboard_name[16];
+ char expansionboard2_name[16];
++char camera_name[16];
+ 
+ enum {
+ 	EXPANSION_MMC_NONE = 0,
+@@ -520,6 +521,14 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = {
+ 	REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+ };
+ 
++static struct regulator_consumer_supply beagle_vaux3_supply = {
++	.supply		= "cam_1v8",
++};
++
++static struct regulator_consumer_supply beagle_vaux4_supply = {
++	.supply		= "cam_2v8",
++};
++
+ static struct gpio_led gpio_leds[];
+ 
+ static int beagle_twl_gpio_setup(struct device *dev,
+@@ -628,11 +637,43 @@ static struct regulator_init_data beagle_vsim = {
+ 	.consumer_supplies	= beagle_vsim_supply,
+ };
+ 
++/* VAUX3 for CAM_1V8 */
++static struct regulator_init_data beagle_vaux3 = {
++	.constraints = {
++		.min_uV			= 1800000,
++		.max_uV			= 1800000,
++		.apply_uV		= true,
++		.valid_modes_mask	= REGULATOR_MODE_NORMAL
++					| REGULATOR_MODE_STANDBY,
++		.valid_ops_mask		= REGULATOR_CHANGE_MODE
++					| REGULATOR_CHANGE_STATUS,
++	},
++	.num_consumer_supplies	= 1,
++	.consumer_supplies	= &beagle_vaux3_supply,
++};
++
++/* VAUX4 for CAM_2V8 */
++static struct regulator_init_data beagle_vaux4 = {
++	.constraints = {
++		.min_uV			= 1800000,
++		.max_uV			= 1800000,
++		.apply_uV		= true,
++		.valid_modes_mask	= REGULATOR_MODE_NORMAL
++					| REGULATOR_MODE_STANDBY,
++		.valid_ops_mask		= REGULATOR_CHANGE_MODE
++					| REGULATOR_CHANGE_STATUS,
++	},
++	.num_consumer_supplies	= 1,
++	.consumer_supplies	= &beagle_vaux4_supply,
++};
++
+ static struct twl4030_platform_data beagle_twldata = {
+ 	/* platform_data for children goes here */
+ 	.gpio		= &beagle_gpio_data,
+ 	.vmmc1		= &beagle_vmmc1,
+ 	.vsim		= &beagle_vsim,
++	.vaux3		= &beagle_vaux3,
++	.vaux4		= &beagle_vaux4,
+ };
+ 
+ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
+@@ -697,6 +738,71 @@ static struct i2c_board_info __initdata beagle_i2c2_bbtoys_ulcd[] = {};
+ static void __init omap3beagle_tsc2007_init(void) { return; }
+ #endif
+ 
++#if defined(CONFIG_VIDEO_MT9P031)
++/* needed for: omap3_beagle_late_initcall */
++#include "devices.h"
++#include <media/omap3isp.h>
++#include <media/mt9p031.h>
++/* needed for: v4l2_dev_to_isp_device */
++#include "../../../drivers/media/platform/omap3isp/isp.h"
++
++#define MT9P031_XCLK		ISP_XCLK_A
++
++#define MT9P031_RESET_GPIO	98
++#define MT9P031_EXT_FREQ	21000000
++#define MT9P031_TARGET_FREQ	48000000
++
++#define MT9P031_I2C_ADDR	0x48
++#define MT9P031_I2C_BUS		2
++
++static struct regulator *reg_1v8, *reg_2v8;
++
++static int beagle_cam_set_xclk(struct v4l2_subdev *subdev, int hz)
++{
++	struct isp_device *isp = v4l2_dev_to_isp_device(subdev->v4l2_dev);
++
++	return isp->platform_cb.set_xclk(isp, hz, MT9P031_XCLK);
++}
++
++static struct mt9p031_platform_data beagle_mt9p031_platform_data = {
++	.set_xclk	= beagle_cam_set_xclk,
++	.reset		= MT9P031_RESET_GPIO,
++	.ext_freq	= MT9P031_EXT_FREQ,
++	.target_freq	= MT9P031_TARGET_FREQ,
++};
++
++static struct i2c_board_info mt9p031_camera_i2c_device = {
++	I2C_BOARD_INFO("mt9p031", MT9P031_I2C_ADDR),
++	.platform_data = &beagle_mt9p031_platform_data,
++};
++
++static struct isp_subdev_i2c_board_info mt9p031_camera_subdevs[] = {
++	{
++		.board_info = &mt9p031_camera_i2c_device,
++		.i2c_adapter_id = MT9P031_I2C_BUS,
++	},
++	{ NULL, 0, },
++};
++
++static struct isp_v4l2_subdevs_group beagle_camera_subdevs[] = {
++	{
++		.subdevs = mt9p031_camera_subdevs,
++		.interface = ISP_INTERFACE_PARALLEL,
++		.bus = {
++			.parallel = {
++				.data_lane_shift = 0,
++				.clk_pol = 1,
++			}
++		},
++	},
++	{ },
++};
++
++static struct isp_platform_data beagle_isp_platform_data = {
++	.subdevs = beagle_camera_subdevs,
++};
++#endif
++
+ static int __init omap3_beagle_i2c_init(void)
+ {
+ 	omap3_pmic_get_config(&beagle_twldata,
+@@ -833,6 +939,18 @@ static int __init expansionboard2_setup(char *str)
+ 	return 0;
+ }
+ 
++static int __init camera_setup(char *str)
++{
++	if (!machine_is_omap3_beagle())
++		return 0;
++
++	if (!str)
++		return -EINVAL;
++	strncpy(camera_name, str, 16);
++	pr_info("Beagle camera: %s\n", camera_name);
++	return 0;
++}
++
+ static int __init beagle_opp_init(void)
+ {
+ 	int r = 0;
+@@ -1109,8 +1227,42 @@ static void __init omap3_beagle_init(void)
+ 	omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+ }
+ 
++static int __init omap3_beagle_late_initcall(void)
++{
++	if (!machine_is_omap3_beagle())
++		return 0;
++
++	if (!cpu_is_omap3630())
++		return 0;
++
++#if defined(CONFIG_VIDEO_MT9P031)
++	if ((!strcmp(camera_name, "lbcm5m1")) || (!strcmp(camera_name, "li5m03")))
++	{
++		pr_info("Beagle camera: MT9P031 init\n");
++
++		reg_1v8 = regulator_get(NULL, "cam_1v8");
++		if (IS_ERR(reg_1v8))
++			pr_err("%s: cannot get cam_1v8 regulator\n", __func__);
++		else
++			regulator_enable(reg_1v8);
++
++		reg_2v8 = regulator_get(NULL, "cam_2v8");
++		if (IS_ERR(reg_2v8))
++			pr_err("%s: cannot get cam_2v8 regulator\n", __func__);
++		else
++			regulator_enable(reg_2v8);
++
++		omap3_init_camera(&beagle_isp_platform_data);
++	}
++#endif
++	return 0;
++}
++
+ early_param("buddy", expansionboard_setup);
+ early_param("buddy2", expansionboard2_setup);
++early_param("camera", camera_setup);
++
++late_initcall(omap3_beagle_late_initcall);
+ 
+ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
+ 	/* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
diff --git a/patches/linux-3.7/0202-Beagle-expansion-add-LSR-COM6L-Adapter-Board.patch b/patches/linux-3.7/0202-Beagle-expansion-add-LSR-COM6L-Adapter-Board.patch
new file mode 100644
index 0000000..419c4dc
--- /dev/null
+++ b/patches/linux-3.7/0202-Beagle-expansion-add-LSR-COM6L-Adapter-Board.patch
@@ -0,0 +1,119 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 11 Dec 2012 07:02:40 -0600
+Subject: [PATCH] Beagle: expansion: add LSR COM6L Adapter Board
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   60 ++++++++++++++++++++++++++++---
+ 1 file changed, 55 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index c64ea55..4fa880a 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -169,6 +169,7 @@ static void __init omap3_beagle_init_rev(void)
+ char expansionboard_name[16];
+ char expansionboard2_name[16];
+ char camera_name[16];
++char wl12xx_name[16];
+ 
+ enum {
+ 	EXPANSION_MMC_NONE = 0,
+@@ -204,6 +205,10 @@ struct wl12xx_platform_data omap_beagle_wlan_data __initdata = {
+ 	.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
+ };
+ 
++struct wl12xx_platform_data omap_beagle_wlan_data_26mhz __initdata = {
++	.board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
++};
++
+ static struct ti_st_plat_data wilink_platform_data = {
+ 	.nshutdown_gpio	= OMAP_BEAGLE_BT_EN_GPIO,
+ 	.dev_name		= "/dev/ttyO1",
+@@ -951,6 +956,18 @@ static int __init camera_setup(char *str)
+ 	return 0;
+ }
+ 
++static int __init wl12xx_setup(char *str)
++{
++	if (!machine_is_omap3_beagle())
++		return 0;
++
++	if (!str)
++		return -EINVAL;
++	strncpy(wl12xx_name, str, 16);
++	pr_info("Beagle wl12xx clk: %s\n", wl12xx_name);
++	return 0;
++}
++
+ static int __init beagle_opp_init(void)
+ {
+ 	int r = 0;
+@@ -1078,9 +1095,29 @@ static void __init omap3_beagle_init(void)
+ 		omap_mux_init_gpio(OMAP3BEAGLE_GPIO_ZIPPY_MMC_CD, OMAP_PIN_INPUT);
+ 	}
+ 
+-	if (!strcmp(expansionboard_name, "bbtoys-wifi"))
++	if ((!strcmp(expansionboard_name, "bbtoys-wifi")) || (!strcmp(expansionboard_name, "lsr-com6l-adpt")))
+ 	{
+ 	#if defined(CONFIG_WL12XX) || defined(CONFIG_WL12XX_MODULE)
++		pr_info("Beagle expansion: wl12xx: setting up gpio pinmux\n");
++
++		omap_mux_init_gpio(OMAP_BEAGLE_FM_EN_BT_WU, OMAP_PIN_OUTPUT);
++		omap_mux_init_gpio(OMAP_BEAGLE_BT_EN_GPIO, OMAP_PIN_OUTPUT);
++		omap_mux_init_gpio(OMAP_BEAGLE_WLAN_EN_GPIO, OMAP_PIN_OUTPUT);
++
++		omap_mux_init_gpio(OMAP_BEAGLE_WLAN_IRQ_GPIO, OMAP_PIN_INPUT_PULLUP);
++
++		/* WLAN SDIO: MMC2 CLK */
++		omap_mux_init_signal("sdmmc2_clk.sdmmc2_clk", OMAP_PIN_INPUT_PULLUP);
++
++		/* WLAN SDIO: MMC2 CMD */
++		omap_mux_init_signal("sdmmc2_cmd.sdmmc2_cmd", OMAP_PIN_INPUT_PULLUP);
++
++		/* WLAN SDIO: MMC2 DAT[0-3] */
++		omap_mux_init_signal("sdmmc2_dat0.sdmmc2_dat0", OMAP_PIN_INPUT_PULLUP);
++		omap_mux_init_signal("sdmmc2_dat1.sdmmc2_dat1", OMAP_PIN_INPUT_PULLUP);
++		omap_mux_init_signal("sdmmc2_dat2.sdmmc2_dat2", OMAP_PIN_INPUT_PULLUP);
++		omap_mux_init_signal("sdmmc2_dat3.sdmmc2_dat3", OMAP_PIN_INPUT_PULLUP);
++
+ 		expansion_config.mmc_settings = EXPANSION_MMC_WIFI;
+ 	#endif
+ 	}
+@@ -1172,12 +1209,24 @@ static void __init omap3_beagle_init(void)
+ 		gpio_export(162, 1);
+ 	}
+ 
+-	if (!strcmp(expansionboard_name, "bbtoys-wifi"))
++	if ((!strcmp(expansionboard_name, "bbtoys-wifi")) || (!strcmp(expansionboard_name, "lsr-com6l-adpt")))
+ 	{
+ 	#if defined(CONFIG_WL12XX) || defined(CONFIG_WL12XX_MODULE)
+-		omap_beagle_wlan_data.irq = gpio_to_irq(OMAP_BEAGLE_WLAN_IRQ_GPIO);
+-		if (wl12xx_set_platform_data(&omap_beagle_wlan_data))
+-			pr_err("error setting wl12xx data\n");
++		pr_info("Beagle expansionboard: initializing wl12xx platform\n");
++
++		if (!strcmp(wl12xx_name, "wl12xx_26mhz")) {
++			pr_info("wl12xx: 26Mhz reference clock (TiWi5)\n");
++			omap_beagle_wlan_data_26mhz.irq = gpio_to_irq(OMAP_BEAGLE_WLAN_IRQ_GPIO);
++			if (wl12xx_set_platform_data(&omap_beagle_wlan_data_26mhz))
++				pr_err("error setting wl12xx data\n");
++		} else {
++			pr_info("wl12xx: 38.4Mhz reference clock (TiWi2/TiWi-BLE)\n");
++			pr_info("wl12xx: for (TiWi5) support pass kernel [wl12xx_clk=wl12xx_26mhz]\n");
++			omap_beagle_wlan_data.irq = gpio_to_irq(OMAP_BEAGLE_WLAN_IRQ_GPIO);
++			if (wl12xx_set_platform_data(&omap_beagle_wlan_data))
++				pr_err("error setting wl12xx data\n");
++		}
++
+ 		pr_info("Beagle expansionboard: registering wl12xx bt platform device\n");
+ 		platform_device_register(&wl12xx_device);
+ 		platform_device_register(&btwilink_device);
+@@ -1261,6 +1310,7 @@ static int __init omap3_beagle_late_initcall(void)
+ early_param("buddy", expansionboard_setup);
+ early_param("buddy2", expansionboard2_setup);
+ early_param("camera", camera_setup);
++early_param("wl12xx_clk", wl12xx_setup);
+ 
+ late_initcall(omap3_beagle_late_initcall);
+ 
diff --git a/patches/linux-3.7/0204-meego-modedb-add-Toshiba-LTA070B220F-800x480-support.patch b/patches/linux-3.7/0204-meego-modedb-add-Toshiba-LTA070B220F-800x480-support.patch
new file mode 100644
index 0000000..2e4e312
--- /dev/null
+++ b/patches/linux-3.7/0204-meego-modedb-add-Toshiba-LTA070B220F-800x480-support.patch
@@ -0,0 +1,26 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Wed, 23 Mar 2011 08:37:54 -0500
+Subject: [PATCH] meego: modedb add Toshiba LTA070B220F 800x480 support
+
+ from http://wiki.meego.com/ARM/Meego_on_Beagleboard_from_scratch
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ drivers/video/modedb.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c
+index 5b686de..69ad1ec 100644
+--- a/drivers/video/modedb.c
++++ b/drivers/video/modedb.c
+@@ -293,6 +293,10 @@ static const struct fb_videomode modedb[] = {
+ 	/* 864x480 @ 60 Hz, 35.15 kHz hsync */
+ 	{ NULL, 60, 864, 480, 27777, 1, 1, 1, 1, 0, 0,
+ 		0, FB_VMODE_NONINTERLACED },
++
++	/* 800x480 @ 60 Hz, Toshiba LTA070B220F 7 inch LCD */
++	{  NULL, 60, 800, 480, 32787, 48, 80, 33, 31, 32, 2,
++		FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
+ };
+ 
+ #ifdef CONFIG_FB_MODE_HELPERS
diff --git a/patches/linux-3.7/0205-backlight-Add-TLC59108-backlight-control-driver.patch b/patches/linux-3.7/0205-backlight-Add-TLC59108-backlight-control-driver.patch
new file mode 100644
index 0000000..4ae5392
--- /dev/null
+++ b/patches/linux-3.7/0205-backlight-Add-TLC59108-backlight-control-driver.patch
@@ -0,0 +1,212 @@
+From: "Manjunathappa, Prakash" <prakash.pm@ti.com>
+Date: Mon, 1 Aug 2011 18:25:11 +0530
+Subject: [PATCH] backlight: Add TLC59108 backlight control driver
+
+This patch adds support for I2C configurable TLC59108 backlight
+control driver.
+
+Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+---
+ drivers/video/backlight/Kconfig    |    8 ++
+ drivers/video/backlight/Makefile   |    1 +
+ drivers/video/backlight/tlc59108.c |  160 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 169 insertions(+)
+ create mode 100644 drivers/video/backlight/tlc59108.c
+
+diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
+index 765a945..50c9e35 100644
+--- a/drivers/video/backlight/Kconfig
++++ b/drivers/video/backlight/Kconfig
+@@ -390,6 +390,14 @@ config BACKLIGHT_TPS65217
+ 	  If you have a Texas Instruments TPS65217 say Y to enable the
+ 	  backlight driver.
+ 
++config BACKLIGHT_TLC59108
++	tristate "TLC59108 LCD Backlight Driver"
++	depends on I2C && BACKLIGHT_CLASS_DEVICE
++	default n
++	help
++	  If you have an LCD Panel with backlight control via TLC59108,
++	  say Y to enable its LCD control driver.
++
+ endif # BACKLIGHT_CLASS_DEVICE
+ 
+ endif # BACKLIGHT_LCD_SUPPORT
+diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
+index e7ce729..2f4711d 100644
+--- a/drivers/video/backlight/Makefile
++++ b/drivers/video/backlight/Makefile
+@@ -43,5 +43,6 @@ obj-$(CONFIG_BACKLIGHT_ADP8870)	+= adp8870_bl.o
+ obj-$(CONFIG_BACKLIGHT_88PM860X) += 88pm860x_bl.o
+ obj-$(CONFIG_BACKLIGHT_PCF50633)	+= pcf50633-backlight.o
+ obj-$(CONFIG_BACKLIGHT_AAT2870) += aat2870_bl.o
++obj-$(CONFIG_BACKLIGHT_TLC59108)	+= tlc59108.o
+ obj-$(CONFIG_BACKLIGHT_OT200) += ot200_bl.o
+ obj-$(CONFIG_BACKLIGHT_TPS65217) += tps65217_bl.o
+diff --git a/drivers/video/backlight/tlc59108.c b/drivers/video/backlight/tlc59108.c
+new file mode 100644
+index 0000000..4f4ea34
+--- /dev/null
++++ b/drivers/video/backlight/tlc59108.c
+@@ -0,0 +1,160 @@
++/*
++ * ti81xxhdmi_tlc59108.c
++ *
++ * Copyright (C) 2011 Texas Instruments
++ * Author: Senthil Natarajan
++ *
++ * tlc59108 HDMI Driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ * History:
++ *
++ * Senthil Natarajan<senthil.n@ti.com> July 2011 I2C driver for tlc59108
++ *						 backlight control
++ */
++
++#include <linux/i2c.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/backlight.h>
++#include <linux/fb.h>
++
++#define tlc59108_MODULE_NAME	"tlc59108"
++#define TLC59108_MODE1   0x00
++#define TLC59108_PWM2    0x04
++#define TLC59108_LEDOUT0 0x0c
++#define TLC59108_LEDOUT1 0x0d
++#define TLC59108_MAX_BRIGHTNESS 0xFF
++
++struct tlc59108_bl {
++	struct i2c_client *client;
++	struct backlight_device *bl;
++};
++
++static void tlc59108_bl_set_backlight(struct tlc59108_bl *data, int brightness)
++{
++	/* Set Mode1 Register */
++	i2c_smbus_write_byte_data(data->client, TLC59108_MODE1, 0x00);
++
++	/* Set LEDOUT0 Register */
++	i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT0, 0x21);
++
++	/* Set Backlight Duty Cycle*/
++	i2c_smbus_write_byte_data(data->client, TLC59108_PWM2,
++				  brightness & 0xff);
++}
++
++static int tlc59108_bl_get_brightness(struct backlight_device *dev)
++{
++	struct backlight_properties *props = &dev->props;
++
++	return props->brightness;
++}
++
++static int tlc59108_bl_update_status(struct backlight_device *dev)
++{
++	struct backlight_properties *props = &dev->props;
++	struct tlc59108_bl *data = dev_get_drvdata(&dev->dev);
++	int brightness = props->brightness;
++
++	tlc59108_bl_set_backlight(data, brightness);
++
++	return 0;
++}
++
++static const struct backlight_ops bl_ops = {
++	.get_brightness		= tlc59108_bl_get_brightness,
++	.update_status		= tlc59108_bl_update_status,
++};
++
++static int tlc59108_probe(struct i2c_client *c, const struct i2c_device_id *id)
++{
++	struct backlight_properties props;
++	struct tlc59108_bl *data = kzalloc(sizeof(struct tlc59108_bl),
++					   GFP_KERNEL);
++	int ret = 0;
++
++	if (!data)
++		return -ENOMEM;
++
++	i2c_set_clientdata(c, data);
++	data->client = c;
++
++	memset(&props, 0, sizeof(struct backlight_properties));
++	props.max_brightness = TLC59108_MAX_BRIGHTNESS;
++	props.type = BACKLIGHT_RAW;
++	data->bl = backlight_device_register("tlc59108-bl", &c->dev, data,
++					     &bl_ops, &props);
++	if (IS_ERR(data->bl)) {
++		ret = PTR_ERR(data->bl);
++		goto err_reg;
++	}
++
++	data->bl->props.brightness = TLC59108_MAX_BRIGHTNESS;
++
++	backlight_update_status(data->bl);
++
++	return 0;
++
++err_reg:
++	data->bl = NULL;
++	kfree(data);
++	return ret;
++}
++
++static int tlc59108_remove(struct i2c_client *c)
++{
++	struct tlc59108_bl *data = i2c_get_clientdata(c);
++
++	backlight_device_unregister(data->bl);
++	data->bl = NULL;
++
++	kfree(data);
++
++	return 0;
++}
++
++/* I2C Device ID table */
++static const struct i2c_device_id tlc59108_id[] = {
++	{ "tlc59108", 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, tlc59108_id);
++
++/* I2C driver data */
++static struct i2c_driver tlc59108_driver = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = tlc59108_MODULE_NAME,
++	},
++	.probe = tlc59108_probe,
++	.remove = tlc59108_remove,
++	.id_table = tlc59108_id,
++};
++
++static int __init tlc59108_init(void)
++{
++	return i2c_add_driver(&tlc59108_driver);
++}
++
++static void __exit tlc59108_exit(void)
++{
++	i2c_del_driver(&tlc59108_driver);
++}
++
++module_init(tlc59108_init);
++module_exit(tlc59108_exit);
++
++MODULE_DESCRIPTION("LCD/Backlight control for TLC59108");
++MODULE_AUTHOR("Senthil Natarajan <senthil.n@ti.com>");
++MODULE_LICENSE("GPL v2");
diff --git a/patches/linux-3.7/0206-tlc59108-adjust-for-beagleboard-uLCD7.patch b/patches/linux-3.7/0206-tlc59108-adjust-for-beagleboard-uLCD7.patch
new file mode 100644
index 0000000..2e14b13
--- /dev/null
+++ b/patches/linux-3.7/0206-tlc59108-adjust-for-beagleboard-uLCD7.patch
@@ -0,0 +1,120 @@
+From: Koen Kooi <koen@dominion.thruhere.net>
+Date: Fri, 27 Apr 2012 21:30:00 +0200
+Subject: [PATCH] tlc59108: adjust for beagleboard+uLCD7
+
+Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
+---
+ drivers/video/backlight/tlc59108.c |   46 ++++++++++++++++++++++++------------
+ 1 file changed, 31 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/video/backlight/tlc59108.c b/drivers/video/backlight/tlc59108.c
+index 4f4ea34..40a21e7 100644
+--- a/drivers/video/backlight/tlc59108.c
++++ b/drivers/video/backlight/tlc59108.c
+@@ -29,9 +29,16 @@
+ #include <linux/backlight.h>
+ #include <linux/fb.h>
+ 
+-#define tlc59108_MODULE_NAME	"tlc59108"
+ #define TLC59108_MODE1   0x00
+-#define TLC59108_PWM2    0x04
++#define TLC59108_MODE2   0x01
++#define TLC59108_PWM0 0x02
++#define TLC59108_PWM1 0x03
++#define TLC59108_PWM2 0x04
++#define TLC59108_PWM3 0x05
++#define TLC59108_PWM4 0x06
++#define TLC59108_PWM5 0x07
++#define TLC59108_PWM6 0x08
++#define TLC59108_PWM7 0x09
+ #define TLC59108_LEDOUT0 0x0c
+ #define TLC59108_LEDOUT1 0x0d
+ #define TLC59108_MAX_BRIGHTNESS 0xFF
+@@ -43,15 +50,9 @@ struct tlc59108_bl {
+ 
+ static void tlc59108_bl_set_backlight(struct tlc59108_bl *data, int brightness)
+ {
+-	/* Set Mode1 Register */
+-	i2c_smbus_write_byte_data(data->client, TLC59108_MODE1, 0x00);
+-
+-	/* Set LEDOUT0 Register */
+-	i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT0, 0x21);
+-
+ 	/* Set Backlight Duty Cycle*/
+ 	i2c_smbus_write_byte_data(data->client, TLC59108_PWM2,
+-				  brightness & 0xff);
++				  0xff - brightness );
+ }
+ 
+ static int tlc59108_bl_get_brightness(struct backlight_device *dev)
+@@ -65,8 +66,18 @@ static int tlc59108_bl_update_status(struct backlight_device *dev)
+ {
+ 	struct backlight_properties *props = &dev->props;
+ 	struct tlc59108_bl *data = dev_get_drvdata(&dev->dev);
++
+ 	int brightness = props->brightness;
+ 
++	if (dev->props.state & BL_CORE_FBBLANK) {
++		brightness = 0;
++		/* Set LEDOUT0 Register */
++		i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT0, 0x10);
++	} else {
++		/* Set LEDOUT0 Register */
++		i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT0, 0x30);
++	}
++
+ 	tlc59108_bl_set_backlight(data, brightness);
+ 
+ 	return 0;
+@@ -77,7 +88,7 @@ static const struct backlight_ops bl_ops = {
+ 	.update_status		= tlc59108_bl_update_status,
+ };
+ 
+-static int tlc59108_probe(struct i2c_client *c, const struct i2c_device_id *id)
++static int __devinit tlc59108_probe(struct i2c_client *c, const struct i2c_device_id *id)
+ {
+ 	struct backlight_properties props;
+ 	struct tlc59108_bl *data = kzalloc(sizeof(struct tlc59108_bl),
+@@ -104,6 +115,11 @@ static int tlc59108_probe(struct i2c_client *c, const struct i2c_device_id *id)
+ 
+ 	backlight_update_status(data->bl);
+ 
++	i2c_smbus_write_byte_data(data->client, TLC59108_MODE1, 0x00);
++	i2c_smbus_write_byte_data(data->client, TLC59108_PWM2, 0x80);
++	i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT1, 0x05);
++	i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT1, 0x15);
++
+ 	return 0;
+ 
+ err_reg:
+@@ -125,7 +141,7 @@ static int tlc59108_remove(struct i2c_client *c)
+ }
+ 
+ /* I2C Device ID table */
+-static const struct i2c_device_id tlc59108_id[] = {
++static struct i2c_device_id tlc59108_id[] = {
+ 	{ "tlc59108", 0 },
+ 	{ }
+ };
+@@ -134,12 +150,12 @@ MODULE_DEVICE_TABLE(i2c, tlc59108_id);
+ /* I2C driver data */
+ static struct i2c_driver tlc59108_driver = {
+ 	.driver = {
+-		.owner = THIS_MODULE,
+-		.name = tlc59108_MODULE_NAME,
++		.owner	= THIS_MODULE,
++		.name	= "tlc59108"
+ 	},
++	.id_table = tlc59108_id,
+ 	.probe = tlc59108_probe,
+ 	.remove = tlc59108_remove,
+-	.id_table = tlc59108_id,
+ };
+ 
+ static int __init tlc59108_init(void)
+@@ -157,4 +173,4 @@ module_exit(tlc59108_exit);
+ 
+ MODULE_DESCRIPTION("LCD/Backlight control for TLC59108");
+ MODULE_AUTHOR("Senthil Natarajan <senthil.n@ti.com>");
+-MODULE_LICENSE("GPL v2");
++MODULE_LICENSE("GPL");
diff --git a/patches/linux-3.7/0207-zeroMAP-Open-your-eyes.patch b/patches/linux-3.7/0207-zeroMAP-Open-your-eyes.patch
new file mode 100644
index 0000000..967a1a7
--- /dev/null
+++ b/patches/linux-3.7/0207-zeroMAP-Open-your-eyes.patch
@@ -0,0 +1,27 @@
+From: Alexander Holler <holler@ahsoftware.de>
+Date: Wed, 4 Jul 2012 00:03:04 +0200
+Subject: [PATCH] zeroMAP: Open your eyes!
+
+Signed-off-by: Alexander Holler <holler@ahsoftware.de>
+---
+ kernel/printk.c |    7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/kernel/printk.c b/kernel/printk.c
+index 2d607f4..a85e5a4 100644
+--- a/kernel/printk.c
++++ b/kernel/printk.c
+@@ -1753,6 +1753,13 @@ static int __init console_setup(char *str)
+ 	char *s, *options, *brl_options = NULL;
+ 	int idx;
+ 
++#ifdef CONFIG_SERIAL_OMAP
++	if (!strncmp(str, "tty0", 4) && '0' <= str[4] && '9' >= str[4]) {
++		str[3] = 'O';
++		pr_warn("We are opening your eyes, assuming you want to use an OMAP based serial driver and not a zeroMAP based one! ;)\n");
++		pr_warn("Which means 'tty0%s' was changed to 'ttyO%s' automagically for your pleasure.\n", str+4, str+4);
++	}
++#endif
+ #ifdef CONFIG_A11Y_BRAILLE_CONSOLE
+ 	if (!memcmp(str, "brl,", 4)) {
+ 		brl_options = "";
diff --git a/patches/linux-3.7/0208-ARM-OMAP-Beagle-C4-fix-reboot-problem.patch b/patches/linux-3.7/0208-ARM-OMAP-Beagle-C4-fix-reboot-problem.patch
new file mode 100644
index 0000000..0bc2f48
--- /dev/null
+++ b/patches/linux-3.7/0208-ARM-OMAP-Beagle-C4-fix-reboot-problem.patch
@@ -0,0 +1,63 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Thu, 15 Nov 2012 13:06:40 -0600
+Subject: [PATCH] ARM: OMAP: Beagle C4: fix reboot problem
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   36 +++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 4fa880a..f5b7f77 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -672,6 +672,41 @@ static struct regulator_init_data beagle_vaux4 = {
+ 	.consumer_supplies	= &beagle_vaux4_supply,
+ };
+ 
++static struct twl4030_ins wrst_seq[] __initdata = {
++	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
++	{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
++	{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
++	{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
++	{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
++	{MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
++};
++
++static struct twl4030_script wrst_script __initdata = {
++	.script = wrst_seq,
++	.size   = ARRAY_SIZE(wrst_seq),
++	.flags  = TWL4030_WRST_SCRIPT,
++};
++
++static struct twl4030_script *twl4030_scripts[] __initdata = {
++	&wrst_script,
++};
++
++static struct twl4030_resconfig twl4030_rconfig[] = {
++	{ .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3, .type = -1,
++		.type2 = -1 },
++	{ .resource = RES_VDD1, .devgroup = DEV_GRP_P1, .type = -1,
++		.type2 = -1 },
++	{ .resource = RES_VDD2, .devgroup = DEV_GRP_P1, .type = -1,
++		.type2 = -1 },
++	{ 0, 0},
++};
++
++static struct twl4030_power_data beagle_twl4030_power_data = {
++	.scripts	= twl4030_scripts,
++	.num		= ARRAY_SIZE(twl4030_scripts),
++	.resource_config = twl4030_rconfig,
++};
++
+ static struct twl4030_platform_data beagle_twldata = {
+ 	/* platform_data for children goes here */
+ 	.gpio		= &beagle_gpio_data,
+@@ -679,6 +714,7 @@ static struct twl4030_platform_data beagle_twldata = {
+ 	.vsim		= &beagle_vsim,
+ 	.vaux3		= &beagle_vaux3,
+ 	.vaux4		= &beagle_vaux4,
++	.power		= &beagle_twl4030_power_data,
+ };
+ 
+ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
diff --git a/patches/linux-3.7/0210-panda-fix-wl12xx-regulator.patch b/patches/linux-3.7/0210-panda-fix-wl12xx-regulator.patch
new file mode 100644
index 0000000..f1f3959
--- /dev/null
+++ b/patches/linux-3.7/0210-panda-fix-wl12xx-regulator.patch
@@ -0,0 +1,23 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Tue, 2 Aug 2011 21:55:34 -0500
+Subject: [PATCH] panda: fix wl12xx regulator
+
+pulled from: http://elinux.org/Panda_How_to_kernel_3_0_rel
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/twl-common.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
+index a256135..5b7fdd6 100644
+--- a/arch/arm/mach-omap2/twl-common.c
++++ b/arch/arm/mach-omap2/twl-common.c
+@@ -363,6 +363,7 @@ static struct regulator_init_data omap4_vusb_idata = {
+ static struct regulator_init_data omap4_clk32kg_idata = {
+ 	.constraints = {
+ 		.valid_ops_mask		= REGULATOR_CHANGE_STATUS,
++		.always_on		= true,
+ 	},
+ };
+ 
diff --git a/patches/linux-3.7/0211-ti-st-st-kim-fixing-firmware-path.patch b/patches/linux-3.7/0211-ti-st-st-kim-fixing-firmware-path.patch
new file mode 100644
index 0000000..1100acd
--- /dev/null
+++ b/patches/linux-3.7/0211-ti-st-st-kim-fixing-firmware-path.patch
@@ -0,0 +1,32 @@
+From: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
+Date: Tue, 25 Oct 2011 10:06:39 +0200
+Subject: [PATCH] ti-st/st-kim: fixing firmware path
+
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ drivers/misc/ti-st/st_kim.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/misc/ti-st/st_kim.c b/drivers/misc/ti-st/st_kim.c
+index 04a8199..43ef2cb 100644
+--- a/drivers/misc/ti-st/st_kim.c
++++ b/drivers/misc/ti-st/st_kim.c
+@@ -244,7 +244,7 @@ static long read_local_version(struct kim_data_s *kim_gdata, char *bts_scr_name)
+ 	if (version & 0x8000)
+ 		maj_ver |= 0x0008;
+ 
+-	sprintf(bts_scr_name, "TIInit_%d.%d.%d.bts", chip, maj_ver, min_ver);
++	sprintf(bts_scr_name, "ti-connectivity/TIInit_%d.%d.%d.bts", chip, maj_ver, min_ver);
+ 
+ 	/* to be accessed later via sysfs entry */
+ 	kim_gdata->version.full = version;
+@@ -287,7 +287,7 @@ static long download_firmware(struct kim_data_s *kim_gdata)
+ 	long len = 0;
+ 	unsigned char *ptr = NULL;
+ 	unsigned char *action_ptr = NULL;
+-	unsigned char bts_scr_name[30] = { 0 };	/* 30 char long bts scr name? */
++	unsigned char bts_scr_name[50] = { 0 };	/* 50 char long bts scr name? */
+ 	int wr_room_space;
+ 	int cmd_size;
+ 	unsigned long timeout;
diff --git a/patches/linux-3.7/0213-Revert-drm-kill-drm_sman.patch b/patches/linux-3.7/0213-Revert-drm-kill-drm_sman.patch
new file mode 100644
index 0000000..38aebd5
--- /dev/null
+++ b/patches/linux-3.7/0213-Revert-drm-kill-drm_sman.patch
@@ -0,0 +1,400 @@
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Thu, 3 May 2012 19:27:52 -0500
+Subject: [PATCH] Revert "drm: kill drm_sman"
+
+This reverts commit 7a6e0daaf4058d1b7dd515bc470ec904454a798c.
+---
+ drivers/gpu/drm/Makefile   |    2 +-
+ drivers/gpu/drm/drm_sman.c |  211 ++++++++++++++++++++++++++++++++++++++++++++
+ include/drm/drm_sman.h     |  151 +++++++++++++++++++++++++++++++
+ 3 files changed, 363 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/drm_sman.c
+ create mode 100644 include/drm/drm_sman.h
+
+diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
+index 2ff5cef..2ed0fde 100644
+--- a/drivers/gpu/drm/Makefile
++++ b/drivers/gpu/drm/Makefile
+@@ -9,7 +9,7 @@ drm-y       :=	drm_auth.o drm_buffer.o drm_bufs.o drm_cache.o \
+ 		drm_drv.o drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \
+ 		drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \
+ 		drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
+-		drm_platform.o drm_sysfs.o drm_hashtab.o drm_mm.o \
++		drm_platform.o drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
+ 		drm_crtc.o drm_modes.o drm_edid.o \
+ 		drm_info.o drm_debugfs.o drm_encoder_slave.o \
+ 		drm_trace_points.o drm_global.o drm_prime.o
+diff --git a/drivers/gpu/drm/drm_sman.c b/drivers/gpu/drm/drm_sman.c
+new file mode 100644
+index 0000000..a8ff350
+--- /dev/null
++++ b/drivers/gpu/drm/drm_sman.c
+@@ -0,0 +1,211 @@
++/**************************************************************************
++ *
++ * Copyright 2006 Tungsten Graphics, Inc., Bismarck., ND., USA.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ *
++ **************************************************************************/
++/*
++ * Simple memory manager interface that keeps track on allocate regions on a
++ * per "owner" basis. All regions associated with an "owner" can be released
++ * with a simple call. Typically if the "owner" exists. The owner is any
++ * "unsigned long" identifier. Can typically be a pointer to a file private
++ * struct or a context identifier.
++ *
++ * Authors:
++ * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
++ */
++
++#include <linux/export.h>
++#include "drm_sman.h"
++
++struct drm_owner_item {
++	struct drm_hash_item owner_hash;
++	struct list_head sman_list;
++	struct list_head mem_blocks;
++};
++
++void drm_sman_takedown(struct drm_sman * sman)
++{
++	kfree(sman->mm);
++}
++
++EXPORT_SYMBOL(drm_sman_takedown);
++
++int
++drm_sman_init(struct drm_sman * sman, unsigned int num_managers,
++	      unsigned int user_order, unsigned int owner_order)
++{
++	int ret = 0;
++
++	sman->mm = kcalloc(num_managers, sizeof(*sman->mm), GFP_KERNEL);
++	if (!sman->mm) {
++		ret = -ENOMEM;
++		return ret;
++	}
++	sman->num_managers = num_managers;
++
++	return 0;
++}
++
++EXPORT_SYMBOL(drm_sman_init);
++
++static void *drm_sman_mm_allocate(void *private, unsigned long size,
++				  unsigned alignment)
++{
++	struct drm_mm *mm = (struct drm_mm *) private;
++	struct drm_mm_node *tmp;
++
++	tmp = drm_mm_search_free(mm, size, alignment, 1);
++	if (!tmp) {
++		return NULL;
++	}
++	tmp = drm_mm_get_block(tmp, size, alignment);
++	return tmp;
++}
++
++static void drm_sman_mm_free(void *private, void *ref)
++{
++	struct drm_mm_node *node = (struct drm_mm_node *) ref;
++
++	drm_mm_put_block(node);
++}
++
++static void drm_sman_mm_destroy(void *private)
++{
++	struct drm_mm *mm = (struct drm_mm *) private;
++	drm_mm_takedown(mm);
++	kfree(mm);
++}
++
++static unsigned long drm_sman_mm_offset(void *private, void *ref)
++{
++	struct drm_mm_node *node = (struct drm_mm_node *) ref;
++	return node->start;
++}
++
++int
++drm_sman_set_range(struct drm_sman * sman, unsigned int manager,
++		   unsigned long start, unsigned long size)
++{
++	struct drm_sman_mm *sman_mm;
++	struct drm_mm *mm;
++	int ret;
++
++	BUG_ON(manager >= sman->num_managers);
++
++	sman_mm = &sman->mm[manager];
++	mm = kzalloc(sizeof(*mm), GFP_KERNEL);
++	if (!mm) {
++		return -ENOMEM;
++	}
++	sman_mm->private = mm;
++	ret = drm_mm_init(mm, start, size);
++
++	if (ret) {
++		kfree(mm);
++		return ret;
++	}
++
++	sman_mm->allocate = drm_sman_mm_allocate;
++	sman_mm->free = drm_sman_mm_free;
++	sman_mm->destroy = drm_sman_mm_destroy;
++	sman_mm->offset = drm_sman_mm_offset;
++
++	return 0;
++}
++
++EXPORT_SYMBOL(drm_sman_set_range);
++
++int
++drm_sman_set_manager(struct drm_sman * sman, unsigned int manager,
++		     struct drm_sman_mm * allocator)
++{
++	BUG_ON(manager >= sman->num_managers);
++	sman->mm[manager] = *allocator;
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_sman_set_manager);
++
++struct drm_memblock_item *drm_sman_alloc(struct drm_sman *sman, unsigned int manager,
++				    unsigned long size, unsigned alignment,
++				    unsigned long owner)
++{
++	void *tmp;
++	struct drm_sman_mm *sman_mm;
++	struct drm_memblock_item *memblock;
++
++	BUG_ON(manager >= sman->num_managers);
++
++	sman_mm = &sman->mm[manager];
++	tmp = sman_mm->allocate(sman_mm->private, size, alignment);
++
++	if (!tmp) {
++		return NULL;
++	}
++
++	memblock = kzalloc(sizeof(*memblock), GFP_KERNEL);
++
++	if (!memblock)
++		goto out;
++
++	memblock->mm_info = tmp;
++	memblock->mm = sman_mm;
++	memblock->sman = sman;
++
++	return memblock;
++
++out:
++	sman_mm->free(sman_mm->private, tmp);
++
++	return NULL;
++}
++
++EXPORT_SYMBOL(drm_sman_alloc);
++
++void drm_sman_free(struct drm_memblock_item *item)
++{
++	list_del(&item->owner_list);
++	item->mm->free(item->mm->private, item->mm_info);
++	kfree(item);
++}
++EXPORT_SYMBOL(drm_sman_free);
++
++void drm_sman_cleanup(struct drm_sman *sman)
++{
++	unsigned int i;
++	struct drm_sman_mm *sman_mm;
++
++	if (sman->mm) {
++		for (i = 0; i < sman->num_managers; ++i) {
++			sman_mm = &sman->mm[i];
++			if (sman_mm->private) {
++				sman_mm->destroy(sman_mm->private);
++				sman_mm->private = NULL;
++			}
++		}
++	}
++}
++
++EXPORT_SYMBOL(drm_sman_cleanup);
+diff --git a/include/drm/drm_sman.h b/include/drm/drm_sman.h
+new file mode 100644
+index 0000000..031e521
+--- /dev/null
++++ b/include/drm/drm_sman.h
+@@ -0,0 +1,151 @@
++/**************************************************************************
++ *
++ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ *
++ **************************************************************************/
++/*
++ * Simple memory MANager interface that keeps track on allocate regions on a
++ * per "owner" basis. All regions associated with an "owner" can be released
++ * with a simple call. Typically if the "owner" exists. The owner is any
++ * "unsigned long" identifier. Can typically be a pointer to a file private
++ * struct or a context identifier.
++ *
++ * Authors:
++ * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
++ */
++
++#ifndef DRM_SMAN_H
++#define DRM_SMAN_H
++
++#include "drmP.h"
++#include "drm_hashtab.h"
++
++/*
++ * A class that is an abstration of a simple memory allocator.
++ * The sman implementation provides a default such allocator
++ * using the drm_mm.c implementation. But the user can replace it.
++ * See the SiS implementation, which may use the SiS FB kernel module
++ * for memory management.
++ */
++
++struct drm_sman_mm {
++	/* private info. If allocated, needs to be destroyed by the destroy
++	   function */
++	void *private;
++
++	/* Allocate a memory block with given size and alignment.
++	   Return an opaque reference to the memory block */
++
++	void *(*allocate) (void *private, unsigned long size,
++			   unsigned alignment);
++
++	/* Free a memory block. "ref" is the opaque reference that we got from
++	   the "alloc" function */
++
++	void (*free) (void *private, void *ref);
++
++	/* Free all resources associated with this allocator */
++
++	void (*destroy) (void *private);
++
++	/* Return a memory offset from the opaque reference returned from the
++	   "alloc" function */
++
++	unsigned long (*offset) (void *private, void *ref);
++};
++
++struct drm_memblock_item {
++	struct list_head owner_list;
++	struct drm_hash_item user_hash;
++	void *mm_info;
++	struct drm_sman_mm *mm;
++	struct drm_sman *sman;
++};
++
++struct drm_sman {
++	struct drm_sman_mm *mm;
++	int num_managers;
++};
++
++/*
++ * Take down a memory manager. This function should only be called after a
++ * successful init and after a call to drm_sman_cleanup.
++ */
++
++extern void drm_sman_takedown(struct drm_sman * sman);
++
++/*
++ * Allocate structures for a manager.
++ * num_managers are the number of memory pools to manage. (VRAM, AGP, ....)
++ * user_order is the log2 of the number of buckets in the user hash table.
++ *	    set this to approximately log2 of the max number of memory regions
++ *	    that will be allocated for _all_ pools together.
++ * owner_order is the log2 of the number of buckets in the owner hash table.
++ *	    set this to approximately log2 of
++ *	    the number of client file connections that will
++ *	    be using the manager.
++ *
++ */
++
++extern int drm_sman_init(struct drm_sman * sman, unsigned int num_managers,
++			 unsigned int user_order, unsigned int owner_order);
++
++/*
++ * Initialize a drm_mm.c allocator. Should be called only once for each
++ * manager unless a customized allogator is used.
++ */
++
++extern int drm_sman_set_range(struct drm_sman * sman, unsigned int manager,
++			      unsigned long start, unsigned long size);
++
++/*
++ * Initialize a customized allocator for one of the managers.
++ * (See the SiS module). The object pointed to by "allocator" is copied,
++ * so it can be destroyed after this call.
++ */
++
++extern int drm_sman_set_manager(struct drm_sman * sman, unsigned int mananger,
++				struct drm_sman_mm * allocator);
++
++/*
++ * Allocate a memory block. Aligment is not implemented yet.
++ */
++
++extern struct drm_memblock_item *drm_sman_alloc(struct drm_sman * sman,
++						unsigned int manager,
++						unsigned long size,
++						unsigned alignment,
++						unsigned long owner);
++
++extern void drm_sman_free(struct drm_memblock_item *item);
++
++/*
++ * Frees all stale memory blocks associated with the memory manager.
++ * See idling above.
++ */
++
++extern void drm_sman_cleanup(struct drm_sman * sman);
++
++#endif
diff --git a/patches/linux-3.7/0215-omap3-Increase-limit-on-bootarg-mpurate.patch b/patches/linux-3.7/0215-omap3-Increase-limit-on-bootarg-mpurate.patch
new file mode 100644
index 0000000..8f3d0cf
--- /dev/null
+++ b/patches/linux-3.7/0215-omap3-Increase-limit-on-bootarg-mpurate.patch
@@ -0,0 +1,29 @@
+From: Sanjeev Premi <premi@ti.com>
+Date: Thu, 29 Apr 2010 14:09:42 +0530
+Subject: [PATCH] omap3: Increase limit on bootarg 'mpurate'
+
+The value of mpurate is currently expected to be less
+than 1000 when specified in MHz.
+
+This patch raises this limit to 2000 to support 1GHz
+capable processors. The new limit should be reasonable
+for quite some time.
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/plat-omap/clock.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
+index 9d7ac20..20b2de8 100644
+--- a/arch/arm/plat-omap/clock.c
++++ b/arch/arm/plat-omap/clock.c
+@@ -185,7 +185,7 @@ static int __init omap_clk_setup(char *str)
+ 	if (!mpurate)
+ 		return 1;
+ 
+-	if (mpurate < 1000)
++	if (mpurate < 2000)
+ 		mpurate *= 1000000;
+ 
+ 	return 1;
diff --git a/patches/linux-3.7/0217-staging-omap-thermal-fix-compilation.patch b/patches/linux-3.7/0217-staging-omap-thermal-fix-compilation.patch
new file mode 100644
index 0000000..a4bdf2e
--- /dev/null
+++ b/patches/linux-3.7/0217-staging-omap-thermal-fix-compilation.patch
@@ -0,0 +1,24 @@
+From: Eduardo Valentin <eduardo.valentin@ti.com>
+Date: Tue, 13 Nov 2012 14:10:00 -0400
+Subject: [PATCH] staging: omap-thermal: fix compilation
+
+Because we are not including linux/io.h, the driver is not compiling.
+This patch adds the missing header.
+
+Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
+---
+ drivers/staging/omap-thermal/omap-bandgap.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/staging/omap-thermal/omap-bandgap.c b/drivers/staging/omap-thermal/omap-bandgap.c
+index 368a2e1..1cae5ed 100644
+--- a/drivers/staging/omap-thermal/omap-bandgap.c
++++ b/drivers/staging/omap-thermal/omap-bandgap.c
+@@ -38,6 +38,7 @@
+ #include <linux/of_device.h>
+ #include <linux/of_platform.h>
+ #include <linux/of_irq.h>
++#include <linux/io.h>
+ 
+ #include "omap-bandgap.h"
+ 
diff --git a/patches/linux-3.7/0218-staging-omap-thermal-remove-platform-data-nomenclatu.patch b/patches/linux-3.7/0218-staging-omap-thermal-remove-platform-data-nomenclatu.patch
new file mode 100644
index 0000000..ffcab5f
--- /dev/null
+++ b/patches/linux-3.7/0218-staging-omap-thermal-remove-platform-data-nomenclatu.patch
@@ -0,0 +1,40 @@
+From: Eduardo Valentin <eduardo.valentin@ti.com>
+Date: Tue, 13 Nov 2012 14:10:01 -0400
+Subject: [PATCH] staging: omap-thermal: remove platform data nomenclature
+
+Because the driver is not really using platform data, this patch
+removes the pdata nomenclature from this driver.
+
+Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
+---
+ drivers/staging/omap-thermal/omap-thermal-common.c |    6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/staging/omap-thermal/omap-thermal-common.c b/drivers/staging/omap-thermal/omap-thermal-common.c
+index 5c0c203b..5be66d7 100644
+--- a/drivers/staging/omap-thermal/omap-thermal-common.c
++++ b/drivers/staging/omap-thermal/omap-thermal-common.c
+@@ -256,12 +256,12 @@ static struct omap_thermal_data
+ int omap_thermal_expose_sensor(struct omap_bandgap *bg_ptr, int id,
+ 			       char *domain)
+ {
+-	struct omap_thermal_pdata pdata;
++	struct omap_thermal_data *data;
+ 
+ 	data = omap_bandgap_get_sensor_data(bg_ptr, id);
+ 
+ 	if (!data)
+-		data = omap_thermal_build_pdata(bg_ptr, id);
++		data = omap_thermal_build_data(bg_ptr, id);
+ 
+ 	if (!data)
+ 		return -EINVAL;
+@@ -359,7 +359,7 @@ int omap_thermal_register_cpu_cooling(struct omap_bandgap *bg_ptr, int id)
+ 
+ 	data = omap_bandgap_get_sensor_data(bg_ptr, id);
+ 	if (!data)
+-		data = omap_thermal_build_pdata(bg_ptr, id);
++		data = omap_thermal_build_data(bg_ptr, id);
+ 
+ 	if (!data)
+ 		return -EINVAL;
diff --git a/patches/linux-3.7/0219-staging-omap-thermal-remove-freq_clip-table.patch b/patches/linux-3.7/0219-staging-omap-thermal-remove-freq_clip-table.patch
new file mode 100644
index 0000000..7b52eb8
--- /dev/null
+++ b/patches/linux-3.7/0219-staging-omap-thermal-remove-freq_clip-table.patch
@@ -0,0 +1,156 @@
+From: Eduardo Valentin <eduardo.valentin@ti.com>
+Date: Tue, 13 Nov 2012 14:10:02 -0400
+Subject: [PATCH] staging: omap-thermal: remove freq_clip table
+
+The API exposed by cpu cooling does not need any freq clip
+table anymore. Now the cpu cooling device is smart enough
+to build its own table.
+
+For this reason, this patch removes all the code that is
+generating a freq clip table and also removes all references
+in data structures regarding freq clip table.
+
+Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
+---
+ drivers/staging/omap-thermal/omap-bandgap.h        |    9 ---
+ drivers/staging/omap-thermal/omap-thermal-common.c |   63 +-------------------
+ 2 files changed, 3 insertions(+), 69 deletions(-)
+
+diff --git a/drivers/staging/omap-thermal/omap-bandgap.h b/drivers/staging/omap-thermal/omap-bandgap.h
+index 78aed75..2bb14bd 100644
+--- a/drivers/staging/omap-thermal/omap-bandgap.h
++++ b/drivers/staging/omap-thermal/omap-bandgap.h
+@@ -336,14 +336,6 @@ struct temp_sensor_regval {
+ };
+ 
+ /**
+- * struct thermal_cooling_conf - description on how to cool a thermal zone
+- * @freq_clip_count: size of freq_data
+- */
+-struct thermal_cooling_conf {
+-	int freq_clip_count;
+-};
+-
+-/**
+  * struct omap_temp_sensor - bandgap temperature sensor platform data
+  * @ts_data: pointer to struct with thresholds, limits of temperature sensor
+  * @registers: pointer to the list of register offsets and bitfields
+@@ -365,7 +357,6 @@ struct omap_temp_sensor {
+ 	struct temp_sensor_registers	*registers;
+ 	struct temp_sensor_regval	regval;
+ 	char				*domain;
+-	struct thermal_cooling_conf	cooling_data;
+ 	/* for hotspot extrapolation */
+ 	const int			slope;
+ 	const int			constant;
+diff --git a/drivers/staging/omap-thermal/omap-thermal-common.c b/drivers/staging/omap-thermal/omap-thermal-common.c
+index 5be66d7..15e9723 100644
+--- a/drivers/staging/omap-thermal/omap-thermal-common.c
++++ b/drivers/staging/omap-thermal/omap-thermal-common.c
+@@ -29,6 +29,7 @@
+ #include <linux/workqueue.h>
+ #include <linux/thermal.h>
+ #include <linux/cpufreq.h>
++#include <linux/cpumask.h>
+ #include <linux/cpu_cooling.h>
+ 
+ #include "omap-thermal.h"
+@@ -112,7 +113,7 @@ static int omap_thermal_bind(struct thermal_zone_device *thermal,
+ 			      struct thermal_cooling_device *cdev)
+ {
+ 	struct omap_thermal_data *data = thermal->devdata;
+-	int max, id;
++	int id;
+ 
+ 	if (IS_ERR_OR_NULL(data))
+ 		return -ENODEV;
+@@ -122,7 +123,6 @@ static int omap_thermal_bind(struct thermal_zone_device *thermal,
+ 		return 0;
+ 
+ 	id = data->sensor_id;
+-	max = data->bg_ptr->conf->sensors[id].cooling_data.freq_clip_count;
+ 
+ 	/* TODO: bind with min and max states */
+ 	/* Simple thing, two trips, one passive another critical */
+@@ -304,58 +304,9 @@ int omap_thermal_report_sensor_temperature(struct omap_bandgap *bg_ptr, int id)
+ 	return 0;
+ }
+ 
+-static int omap_thermal_build_cpufreq_clip(struct omap_bandgap *bg_ptr,
+-					   struct freq_clip_table **tab_ptr,
+-					   int *tab_size)
+-{
+-	struct cpufreq_frequency_table *freq_table;
+-	struct freq_clip_table *tab;
+-	int i, count = 0;
+-
+-	freq_table = cpufreq_frequency_get_table(0);
+-	if (IS_ERR_OR_NULL(freq_table)) {
+-		dev_err(bg_ptr->dev,
+-			"%s: failed to get cpufreq table (%p)\n",
+-			__func__, freq_table);
+-		return -EINVAL;
+-	}
+-
+-	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+-		unsigned int freq = freq_table[i].frequency;
+-		if (freq == CPUFREQ_ENTRY_INVALID)
+-			continue;
+-		count++;
+-	}
+-
+-	tab = devm_kzalloc(bg_ptr->dev, sizeof(*tab) * count, GFP_KERNEL);
+-	if (!tab) {
+-		dev_err(bg_ptr->dev,
+-			"%s: no memory available\n", __func__);
+-		return -ENOMEM;
+-	}
+-
+-	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+-		unsigned int freq = freq_table[i].frequency;
+-
+-		if (freq == CPUFREQ_ENTRY_INVALID)
+-			continue;
+-
+-		tab[count - i - 1].freq_clip_max = freq;
+-		tab[count - i - 1].temp_level = OMAP_TRIP_HOT;
+-		tab[count - i - 1].mask_val = cpumask_of(0);
+-	}
+-
+-	*tab_ptr = tab;
+-	*tab_size = count;
+-
+-	return 0;
+-}
+-
+ int omap_thermal_register_cpu_cooling(struct omap_bandgap *bg_ptr, int id)
+ {
+ 	struct omap_thermal_data *data;
+-	struct freq_clip_table *tab_ptr;
+-	int tab_size, ret;
+ 
+ 	data = omap_bandgap_get_sensor_data(bg_ptr, id);
+ 	if (!data)
+@@ -364,21 +315,13 @@ int omap_thermal_register_cpu_cooling(struct omap_bandgap *bg_ptr, int id)
+ 	if (!data)
+ 		return -EINVAL;
+ 
+-	ret = omap_thermal_build_cpufreq_clip(bg_ptr, &tab_ptr, &tab_size);
+-	if (ret < 0) {
+-		dev_err(bg_ptr->dev,
+-			"%s: failed to build cpufreq clip table\n", __func__);
+-		return ret;
+-	}
+-
+ 	/* Register cooling device */
+-	data->cool_dev = cpufreq_cooling_register(tab_ptr, tab_size);
++	data->cool_dev = cpufreq_cooling_register(cpu_present_mask);
+ 	if (IS_ERR_OR_NULL(data->cool_dev)) {
+ 		dev_err(bg_ptr->dev,
+ 			"Failed to register cpufreq cooling device\n");
+ 		return PTR_ERR(data->cool_dev);
+ 	}
+-	bg_ptr->conf->sensors[id].cooling_data.freq_clip_count = tab_size;
+ 	omap_bandgap_set_sensor_data(bg_ptr, id, data);
+ 
+ 	return 0;
diff --git a/patches/linux-3.7/0220-staging-omap-thermal-add-IRQ-debugging-messaging.patch b/patches/linux-3.7/0220-staging-omap-thermal-add-IRQ-debugging-messaging.patch
new file mode 100644
index 0000000..ee44bfb
--- /dev/null
+++ b/patches/linux-3.7/0220-staging-omap-thermal-add-IRQ-debugging-messaging.patch
@@ -0,0 +1,28 @@
+From: Eduardo Valentin <eduardo.valentin@ti.com>
+Date: Tue, 13 Nov 2012 14:10:03 -0400
+Subject: [PATCH] staging: omap-thermal: add IRQ debugging messaging
+
+For debugging purposes, print the IRQ event for the domain being processed.
+
+Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
+Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
+---
+ drivers/staging/omap-thermal/omap-bandgap.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/staging/omap-thermal/omap-bandgap.c b/drivers/staging/omap-thermal/omap-bandgap.c
+index 1cae5ed..3eb726f 100644
+--- a/drivers/staging/omap-thermal/omap-bandgap.c
++++ b/drivers/staging/omap-thermal/omap-bandgap.c
+@@ -113,6 +113,11 @@ static irqreturn_t talert_irq_handler(int irq, void *data)
+ 
+ 		omap_bandgap_writel(bg_ptr, ctrl, tsr->bgap_mask_ctrl);
+ 
++		dev_dbg(bg_ptr->dev,
++			"%s: IRQ from %s sensor: hotevent %d coldevent %d\n",
++			__func__, bg_ptr->conf->sensors[i].domain,
++			t_hot, t_cold);
++
+ 		/* read temperature */
+ 		temp = omap_bandgap_readl(bg_ptr, tsr->temp_sensor_ctrl);
+ 		temp &= tsr->bgap_dtemp_mask;
diff --git a/patches/linux-3.7/0221-staging-omap-thermal-fix-context-restore-function.patch b/patches/linux-3.7/0221-staging-omap-thermal-fix-context-restore-function.patch
new file mode 100644
index 0000000..08eb5c8
--- /dev/null
+++ b/patches/linux-3.7/0221-staging-omap-thermal-fix-context-restore-function.patch
@@ -0,0 +1,93 @@
+From: Radhesh Fadnis <radhesh.fadnis@ti.com>
+Date: Tue, 13 Nov 2012 14:10:04 -0400
+Subject: [PATCH] staging: omap-thermal: fix context restore function
+
+In the context restore function, if the context is lost or
+not is being checked by the contents of the counter register.
+But this is logic hold good as long as counter reset value is
+zero, if the reset value is non-zero then above logic doesn't
+hold good. Hence removed checking of the register value and
+restoring the context.
+
+Signed-off-by: Radhesh Fadnis <radhesh.fadnis@ti.com>
+Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
+Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
+---
+ drivers/staging/omap-thermal/omap-bandgap.c |   57 ++++++++++-----------------
+ 1 file changed, 21 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/staging/omap-thermal/omap-bandgap.c b/drivers/staging/omap-thermal/omap-bandgap.c
+index 3eb726f..c17bc95 100644
+--- a/drivers/staging/omap-thermal/omap-bandgap.c
++++ b/drivers/staging/omap-thermal/omap-bandgap.c
+@@ -1065,7 +1065,6 @@ static int omap_bandgap_save_ctxt(struct omap_bandgap *bg_ptr)
+ static int omap_bandgap_restore_ctxt(struct omap_bandgap *bg_ptr)
+ {
+ 	int i;
+-	u32 temp = 0;
+ 
+ 	for (i = 0; i < bg_ptr->conf->sensor_count; i++) {
+ 		struct temp_sensor_registers *tsr;
+@@ -1078,41 +1077,27 @@ static int omap_bandgap_restore_ctxt(struct omap_bandgap *bg_ptr)
+ 		if (OMAP_BANDGAP_HAS(bg_ptr, COUNTER))
+ 			val = omap_bandgap_readl(bg_ptr, tsr->bgap_counter);
+ 
+-		if (val == 0) {
+-			if (OMAP_BANDGAP_HAS(bg_ptr, TSHUT_CONFIG))
+-				omap_bandgap_writel(bg_ptr,
+-					rval->tshut_threshold,
+-						   tsr->tshut_threshold);
+-			/* Force immediate temperature measurement and update
+-			 * of the DTEMP field
+-			 */
+-			omap_bandgap_force_single_read(bg_ptr, i);
+-
+-			if (OMAP_BANDGAP_HAS(bg_ptr, COUNTER))
+-				omap_bandgap_writel(bg_ptr, rval->bg_counter,
+-							   tsr->bgap_counter);
+-			if (OMAP_BANDGAP_HAS(bg_ptr, MODE_CONFIG))
+-				omap_bandgap_writel(bg_ptr, rval->bg_mode_ctrl,
+-							   tsr->bgap_mode_ctrl);
+-			if (OMAP_BANDGAP_HAS(bg_ptr, TALERT)) {
+-				omap_bandgap_writel(bg_ptr,
+-							   rval->bg_threshold,
+-							   tsr->bgap_threshold);
+-				omap_bandgap_writel(bg_ptr, rval->bg_ctrl,
+-							   tsr->bgap_mask_ctrl);
+-			}
+-		} else {
+-			temp = omap_bandgap_readl(bg_ptr,
+-						  tsr->temp_sensor_ctrl);
+-			temp &= (tsr->bgap_dtemp_mask);
+-			omap_bandgap_force_single_read(bg_ptr, i);
+-			if (temp == 0 && OMAP_BANDGAP_HAS(bg_ptr, TALERT)) {
+-				temp = omap_bandgap_readl(bg_ptr,
+-							  tsr->bgap_mask_ctrl);
+-				temp |= 1 << __ffs(tsr->mode_ctrl_mask);
+-				omap_bandgap_writel(bg_ptr, temp,
+-							   tsr->bgap_mask_ctrl);
+-			}
++		if (OMAP_BANDGAP_HAS(bg_ptr, TSHUT_CONFIG))
++			omap_bandgap_writel(bg_ptr,
++				rval->tshut_threshold,
++					   tsr->tshut_threshold);
++		/* Force immediate temperature measurement and update
++		 * of the DTEMP field
++		 */
++		omap_bandgap_force_single_read(bg_ptr, i);
++
++		if (OMAP_BANDGAP_HAS(bg_ptr, COUNTER))
++			omap_bandgap_writel(bg_ptr, rval->bg_counter,
++						   tsr->bgap_counter);
++		if (OMAP_BANDGAP_HAS(bg_ptr, MODE_CONFIG))
++			omap_bandgap_writel(bg_ptr, rval->bg_mode_ctrl,
++						   tsr->bgap_mode_ctrl);
++		if (OMAP_BANDGAP_HAS(bg_ptr, TALERT)) {
++			omap_bandgap_writel(bg_ptr,
++						   rval->bg_threshold,
++						   tsr->bgap_threshold);
++			omap_bandgap_writel(bg_ptr, rval->bg_ctrl,
++						   tsr->bgap_mask_ctrl);
+ 		}
+ 	}
+ 
diff --git a/patches/linux-3.7/0223-Attempted-SMC911x-BQL-patch.patch b/patches/linux-3.7/0223-Attempted-SMC911x-BQL-patch.patch
new file mode 100644
index 0000000..74b2a84
--- /dev/null
+++ b/patches/linux-3.7/0223-Attempted-SMC911x-BQL-patch.patch
@@ -0,0 +1,56 @@
+From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
+Date: Thu, 29 Nov 2012 11:17:05 +0100
+Subject: [PATCH] Attempted SMC911x BQL patch
+
+First attempt at BQL on smsc911x.
+
+Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+---
+ drivers/net/ethernet/smsc/smsc911x.c |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c
+index c53c0f4..f5bedac 100644
+--- a/drivers/net/ethernet/smsc/smsc911x.c
++++ b/drivers/net/ethernet/smsc/smsc911x.c
+@@ -1107,6 +1107,7 @@ static void smsc911x_tx_update_txcounters(struct net_device *dev)
+ {
+ 	struct smsc911x_data *pdata = netdev_priv(dev);
+ 	unsigned int tx_stat;
++	unsigned int bytes_compl = 0, pkts_compl = 0;
+ 
+ 	while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
+ 		if (unlikely(tx_stat & 0x80000000)) {
+@@ -1124,6 +1125,8 @@ static void smsc911x_tx_update_txcounters(struct net_device *dev)
+ 			} else {
+ 				dev->stats.tx_packets++;
+ 				dev->stats.tx_bytes += (tx_stat >> 16);
++				pkts_compl++;
++				bytes_compl += (tx_stat >> 16);
+ 			}
+ 			if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
+ 				dev->stats.collisions += 16;
+@@ -1140,6 +1143,7 @@ static void smsc911x_tx_update_txcounters(struct net_device *dev)
+ 			}
+ 		}
+ 	}
++	netdev_completed_queue(dev, pkts_compl, bytes_compl);
+ }
+ 
+ /* Increments the Rx error counters */
+@@ -1607,6 +1611,7 @@ static int smsc911x_stop(struct net_device *dev)
+ 	/* At this point all Rx and Tx activity is stopped */
+ 	dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
+ 	smsc911x_tx_update_txcounters(dev);
++	netdev_reset_queue(dev);
+ 
+ 	/* Bring the PHY down */
+ 	if (pdata->phy_dev)
+@@ -1650,6 +1655,7 @@ static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
+ 	wrsz >>= 2;
+ 
+ 	pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
++	netdev_sent_queue(dev, skb->len);
+ 	freespace -= (skb->len + 32);
+ 	skb_tx_timestamp(skb);
+ 	dev_kfree_skb(skb);
diff --git a/patches/linux-3.7/0225-spi-spidev-Add-device-tree-bindings.patch b/patches/linux-3.7/0225-spi-spidev-Add-device-tree-bindings.patch
new file mode 100644
index 0000000..aceab2a
--- /dev/null
+++ b/patches/linux-3.7/0225-spi-spidev-Add-device-tree-bindings.patch
@@ -0,0 +1,43 @@
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Fri, 28 Sep 2012 12:50:15 +0000
+Subject: [PATCH] spi: spidev: Add device tree bindings
+
+This will allow to probe spidev from device tree
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ drivers/spi/spidev.c |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 830adbe..8ae0660 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -31,6 +31,8 @@
+ #include <linux/mutex.h>
+ #include <linux/slab.h>
+ #include <linux/compat.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
+ 
+ #include <linux/spi/spi.h>
+ #include <linux/spi/spidev.h>
+@@ -642,10 +644,18 @@ static int __devexit spidev_remove(struct spi_device *spi)
+ 	return 0;
+ }
+ 
++static const struct of_device_id spidev_dt_ids[] = {
++	{ .compatible = "linux,spidev" },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, spidev_dt_ids);
++
+ static struct spi_driver spidev_spi_driver = {
+ 	.driver = {
+ 		.name =		"spidev",
+ 		.owner =	THIS_MODULE,
++		.of_match_table = of_match_ptr(spidev_dt_ids),
+ 	},
+ 	.probe =	spidev_probe,
+ 	.remove =	__devexit_p(spidev_remove),
diff --git a/patches/linux-3.7/0301-Release-distrokit-beaglebone-20121218.patch b/patches/linux-3.7/0301-Release-distrokit-beaglebone-20121218.patch
new file mode 100644
index 0000000..472f2b2
--- /dev/null
+++ b/patches/linux-3.7/0301-Release-distrokit-beaglebone-20121218.patch
@@ -0,0 +1,22 @@
+From: Jan Luebbe <jlu@pengutronix.de>
+Date: Tue, 18 Dec 2012 14:55:28 +0100
+Subject: [PATCH] Release distrokit/beaglebone/20121218
+
+Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
+---
+ Makefile |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile b/Makefile
+index 540f7b2..5fb3b62 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1,7 +1,7 @@
+ VERSION = 3
+ PATCHLEVEL = 7
+ SUBLEVEL = 0
+-EXTRAVERSION =
++EXTRAVERSION =-20121218
+ NAME = Terrified Chipmunk
+ 
+ # *DOCUMENTATION*
diff --git a/patches/linux-3.7/series b/patches/linux-3.7/series
new file mode 100644
index 0000000..b189567
--- /dev/null
+++ b/patches/linux-3.7/series
@@ -0,0 +1,209 @@
+# umpf-base: v3.7
+# umpf-name: distrokit/beaglebone
+# umpf-version: distrokit/beaglebone/20121218
+# umpf-topic: topic/distrokit/beaglebone/board
+# umpf-hashinfo: 1008c9cfa5d53ee128edacdc6608aafb4946f4be
+# umpf-topic-range: 29594404d7fe73cd80eaa4ee8c43dcc53970c60e..1008c9cfa5d53ee128edacdc6608aafb4946f4be
+0001-video-st7735fb-add-st7735-framebuffer-driver.patch
+0002-regulator-tps65910-fix-BUG_ON-shown-with-vrtc-regula.patch
+0003-dmaengine-add-helper-function-to-request-a-slave-DMA.patch
+0004-of-Add-generic-device-tree-DMA-helpers.patch
+0005-of-dma-fix-build-break-for-CONFIG_OF.patch
+0006-of-dma-fix-typos-in-generic-dma-binding-definition.patch
+0007-dmaengine-fix-build-failure-due-to-missing-semi-colo.patch
+0008-dmaengine-edma-fix-slave-config-dependency-on-direct.patch
+0009-ARM-davinci-move-private-EDMA-API-to-arm-common.patch
+0010-ARM-edma-remove-unused-transfer-controller-handlers.patch
+0011-ARM-edma-add-DT-and-runtime-PM-support-for-AM33XX.patch
+0012-ARM-edma-add-AM33XX-crossbar-event-support.patch
+0013-dmaengine-edma-enable-build-for-AM33XX.patch
+0014-dmaengine-edma-Add-TI-EDMA-device-tree-binding.patch
+0015-ARM-dts-add-AM33XX-EDMA-support.patch
+0016-dmaengine-add-dma_request_slave_channel_compat.patch
+0017-mmc-omap_hsmmc-convert-to-dma_request_slave_channel_.patch
+0018-mmc-omap_hsmmc-limit-max_segs-with-the-EDMA-DMAC.patch
+0019-mmc-omap_hsmmc-add-generic-DMA-request-support-to-th.patch
+0020-ARM-dts-add-AM33XX-MMC-support.patch
+0021-spi-omap2-mcspi-convert-to-dma_request_slave_channel.patch
+0022-spi-omap2-mcspi-add-generic-DMA-request-support-to-t.patch
+0023-ARM-dts-add-AM33XX-SPI-support.patch
+0024-Documentation-bindings-add-spansion.patch
+0025-ARM-dts-add-BeagleBone-Adafruit-1.8-LCD-support.patch
+0026-misc-add-gpevt-driver.patch
+0027-ARM-dts-add-BeagleBone-gpevt-support.patch
+0028-ARM-configs-working-AM33XX-edma-dmaengine-defconfig.patch
+0029-ARM-configs-working-da850-edma-dmaengine-defconfig.patch
+0030-misc-gpevt-null-terminate-the-of_match_table.patch
+0031-proposed-probe-fix-works-for-me-on-evm.patch
+0033-ARM-OMAP3-hwmod-Add-AM33XX-HWMOD-data-for-davinci_md.patch
+0034-net-davinci_mdio-Fix-type-mistake-in-calling-runtime.patch
+0035-net-cpsw-Add-parent-child-relation-support-between-c.patch
+0036-arm-dts-am33xx-Add-cpsw-and-mdio-module-nodes-for-AM.patch
+0038-i2c-pinctrl-ify-i2c-omap.c.patch
+0039-arm-dts-AM33XX-Configure-pinmuxs-for-user-leds-contr.patch
+0040-beaglebone-DT-set-default-triggers-for-LEDS.patch
+0041-beaglebone-add-a-cpu-led-trigger.patch
+0043-arm-dts-AM33XX-Add-device-tree-OPP-table.patch
+0044-am33xx-DT-add-commented-out-OPP-values-for-ES2.0.patch
+0046-input-TSC-ti_tscadc-Correct-register-usage.patch
+0047-input-TSC-ti_tscadc-Add-Step-configuration-as-platfo.patch
+0048-input-TSC-ti_tscadc-set-FIFO0-threshold-Interrupt.patch
+0049-input-TSC-ti_tscadc-Remove-definition-of-End-Of-Inte.patch
+0050-input-TSC-ti_tscadc-Rename-the-existing-touchscreen-.patch
+0051-MFD-ti_tscadc-Add-support-for-TI-s-TSC-ADC-MFDevice.patch
+0052-input-TSC-ti_tsc-Convert-TSC-into-a-MFDevice.patch
+0053-IIO-ADC-tiadc-Add-support-of-TI-s-ADC-driver.patch
+0054-input-ti_am335x_tsc-Make-steps-enable-configurable.patch
+0055-input-ti_am335x_tsc-Order-of-TSC-wires-connect-made-.patch
+0056-input-ti_am335x_tsc-Add-variance-filters.patch
+0057-ti_tscadc-Update-with-IIO-map-interface-deal-with-pa.patch
+0058-ti_tscadc-Match-mfd-sub-devices-to-regmap-interface.patch
+0060-ARM-OMAP3-hwmod-Corrects-resource-data-for-PWM-devic.patch
+0061-pwm_backlight-Add-device-tree-support-for-Low-Thresh.patch
+0062-pwm-pwm-tiecap-Add-device-tree-binding-support-in-AP.patch
+0063-Control-module-EHRPWM-clk-enabling.patch
+0064-pwm-pwm-tiecap-Enable-clock-gating.patch
+0065-PWM-ti-ehrpwm-fix-up-merge-conflict.patch
+0066-pwm-pwm_test-Driver-support-for-PWM-module-testing.patch
+0067-arm-dts-DT-support-for-EHRPWM-and-ECAP-device.patch
+0068-pwm-pwm-tiehrpwm-Add-device-tree-binding-support-EHR.patch
+0069-ARM-OMAP2-PWM-limit-am33xx_register_ehrpwm-to-soc_is.patch
+0071-pinctrl-pinctrl-single-must-be-initialized-early.patch
+0072-Bone-DTS-working-i2c2-i2c3-in-the-tree.patch
+0073-am33xx-Convert-I2C-from-omap-to-am33xx-names.patch
+0074-beaglebone-fix-backlight-entry-in-DT.patch
+0076-Shut-up-musb.patch
+0077-musb-Fix-crashes-and-other-weirdness.patch
+0078-musb-revert-parts-of-032ec49f.patch
+0079-usb-musb-dsps-get-the-PHY-using-phandle-api.patch
+0080-drivers-usb-otg-add-device-tree-support-to-otg-libra.patch
+0081-usb-otg-nop-add-dt-support.patch
+0082-usb-musb-dsps-add-phy-control-logic-to-glue.patch
+0083-usb-musb-dsps-enable-phy-control-for-am335x.patch
+0084-ARM-am33xx-fix-mem-regions-in-USB-hwmod.patch
+0086-omap2-clk-Add-missing-lcdc-clock-definition.patch
+0087-da8xx-Allow-use-by-am33xx-based-devices.patch
+0088-da8xx-Fix-revision-check-on-the-da8xx-driver.patch
+0089-da8xx-De-constify-members-in-the-platform-config.patch
+0090-da8xx-Add-standard-panel-definition.patch
+0091-da8xx-Add-CDTech_S035Q01-panel-used-by-LCD3-bone-cap.patch
+0092-da8xx-fb-add-panel-definition-for-beaglebone-LCD7-ca.patch
+0094-mmc-omap_hsmmc-Enable-HSPE-bit-for-high-speed-cards.patch
+0095-am33xx.dtsi-enable-MMC-HSPE-bit-for-all-3-controller.patch
+0096-omap-hsmmc-Correct-usage-of-of_find_node_by_name.patch
+0098-ARM-AM33XX-hwmod-Remove-wrong-INIT_NO_RESET-IDLE-fla.patch
+0100-f2fs-add-document.patch
+0101-f2fs-add-on-disk-layout.patch
+0102-f2fs-add-superblock-and-major-in-memory-structure.patch
+0103-f2fs-add-super-block-operations.patch
+0104-f2fs-add-checkpoint-operations.patch
+0105-f2fs-add-node-operations.patch
+0106-f2fs-add-segment-operations.patch
+0107-f2fs-add-file-operations.patch
+0108-f2fs-add-address-space-operations-for-data.patch
+0109-f2fs-add-core-inode-operations.patch
+0110-f2fs-add-inode-operations-for-special-inodes.patch
+0111-f2fs-add-core-directory-operations.patch
+0112-f2fs-add-xattr-and-acl-functionalities.patch
+0113-f2fs-add-garbage-collection-functions.patch
+0114-f2fs-add-recovery-routines-for-roll-forward.patch
+0115-f2fs-update-Kconfig-and-Makefile.patch
+0116-f2fs-gc.h-make-should_do_checkpoint-inline.patch
+0117-f2fs-move-statistics-code-into-one-file.patch
+0118-f2fs-move-proc-files-to-debugfs.patch
+0119-f2fs-compile-fix.patch
+0121-6lowpan-lowpan_is_iid_16_bit_compressable-does-not-d.patch
+0122-6lowpan-next-header-is-not-properly-set-upon-decompr.patch
+0123-6lowpan-always-enable-link-layer-acknowledgments.patch
+0124-mac802154-turn-on-ACK-when-enabled-by-the-upper-laye.patch
+0125-6lowpan-use-short-IEEE-802.15.4-addresses-for-broadc.patch
+0126-6lowpan-fix-first-fragment-FRAG1-handling.patch
+0127-6lowpan-store-fragment-tag-values-per-device-instead.patch
+0128-6lowpan-obtain-IEEE802.15.4-sequence-number-from-the.patch
+0129-6lowpan-add-a-new-parameter-in-sysfs-to-turn-on-off-.patch
+0130-6lowpan-use-the-PANID-provided-by-the-device-instead.patch
+0131-6lowpan-modify-udp-compression-uncompression-to-matc.patch
+0132-6lowpan-make-memory-allocation-atomic-during-6lowpan.patch
+0133-mac802154-make-mem-alloc-ATOMIC-to-prevent-schedulin.patch
+0134-mac802154-remove-unnecessary-spinlocks.patch
+0135-mac802154-re-introduce-MAC-primitives-required-to-se.patch
+0136-serial-initial-import-of-the-IEEE-802.15.4-serial-dr.patch
+0138-i2c-EEPROM-Export-memory-accessor.patch
+0139-omap-Export-omap_hwmod_lookup-omap_device_build-omap.patch
+0140-gpio-keys-Pinctrl-fy.patch
+0141-tps65217-Allow-placement-elsewhere-than-parent-mfd-d.patch
+0142-pwm-export-of_pwm_request.patch
+0143-i2c-Export-capability-to-probe-devices.patch
+0144-pwm-backlight-Pinctrl-fy.patch
+0145-spi-Export-OF-interfaces-for-capebus-use.patch
+0146-w1-gpio-Pinctrl-fy.patch
+0147-w1-gpio-Simplify-get-rid-of-defines.patch
+0148-arm-dt-Enable-DT-proc-updates.patch
+0149-ARM-CUSTOM-Build-a-uImage-with-dtb-already-appended.patch
+0150-beaglebone-create-a-shared-dtsi-for-beaglebone-based.patch
+0151-beaglebone-enable-emmc-for-bonelt.patch
+0152-da8xx-dt-Create-da8xx-DT-adapter-device.patch
+0153-ti-tscadc-dt-Create-ti-tscadc-dt-DT-adapter-device.patch
+0154-capebus-Core-capebus-support.patch
+0155-capebus-Add-beaglebone-board-support.patch
+0156-capebus-Beaglebone-generic-cape-support.patch
+0157-capebus-Beaglebone-geiger-cape-support.patch
+0158-capebus-Beaglebone-capebus-DT-update.patch
+0159-capebus-Document-DT-bindings.patch
+0160-capebus-Documentation-capebus-summary.patch
+0161-beaglebone-Update-default-config-for-capebus.patch
+0162-capebus-Geiger-Cape-config-bugfixs.patch
+0163-am335x-bone-Add-spi0-pins-defines.patch
+0164-Allow-more-than-one-instance-of-generic-devices.patch
+0165-Mark-the-device-as-PRIVATE.patch
+0166-DT-overlay.patch
+0167-Bug-fixes-pinctl-gpio-reset.patch
+0168-ARM-HSMMC-fix-error-path-when-no-gpio_reset.patch
+0169-capebus-Add-PRUSS-DT-bindings.patch
+0171-Import-working-HDMI-driver-from-3.2-kernel.patch
+0172-Added-DT-binding-to-NXP-driver.patch
+0173-da8xx-fb-Add-timings-for-720x480-60.patch
+0174-Add-capebus-override-and-pinmux-for-da8xx-dt.patch
+0175-video-Kconfig-Makefile-Add-new-Kconfig-for-old-drive.patch
+0176-am335x-bonelt-dts-Add-DT-node-to-probe-NXP-driver.patch
+0177-tda-driver-enable-1280x720.patch
+0178-Makefile-Disable-CEC.patch
+0180-uio-uio_pruss-port-to-AM33xx.patch
+0181-ARM-omap-add-DT-support-for-deasserting-hardware-res.patch
+0182-ARM-dts-AM33xx-PRUSS-support.patch
+0184-kbuild-deb-pkg-set-host-machine-after-dpkg-gencontro.patch
+0185-arm-add-definition-of-strstr-to-decompress.c.patch
+0187-mach-omap2-board-igep0020.c-Fix-reboot-problem.patch
+0188-regulator-core-if-voltage-scaling-fails-restore-orig.patch
+0190-OMAP-DSS2-add-bootarg-for-selecting-svideo.patch
+0191-video-add-timings-for-hd720.patch
+0193-Beagle-expansion-add-buddy-param-for-expansionboard-.patch
+0194-Beagle-expansion-add-zippy.patch
+0195-Beagle-expansion-add-zippy2.patch
+0196-Beagle-expansion-add-trainer.patch
+0197-Beagle-expansion-add-CircuitCo-ulcd-Support.patch
+0198-Beagle-expansion-add-wifi.patch
+0199-Beagle-expansion-add-beaglefpga.patch
+0200-Beagle-expansion-add-spidev.patch
+0201-Beagle-expansion-add-Aptina-li5m03-camera.patch
+0202-Beagle-expansion-add-LSR-COM6L-Adapter-Board.patch
+0204-meego-modedb-add-Toshiba-LTA070B220F-800x480-support.patch
+0205-backlight-Add-TLC59108-backlight-control-driver.patch
+0206-tlc59108-adjust-for-beagleboard-uLCD7.patch
+0207-zeroMAP-Open-your-eyes.patch
+0208-ARM-OMAP-Beagle-C4-fix-reboot-problem.patch
+0210-panda-fix-wl12xx-regulator.patch
+0211-ti-st-st-kim-fixing-firmware-path.patch
+0213-Revert-drm-kill-drm_sman.patch
+0215-omap3-Increase-limit-on-bootarg-mpurate.patch
+0217-staging-omap-thermal-fix-compilation.patch
+0218-staging-omap-thermal-remove-platform-data-nomenclatu.patch
+0219-staging-omap-thermal-remove-freq_clip-table.patch
+0220-staging-omap-thermal-add-IRQ-debugging-messaging.patch
+0221-staging-omap-thermal-fix-context-restore-function.patch
+0223-Attempted-SMC911x-BQL-patch.patch
+0225-spi-spidev-Add-device-tree-bindings.patch
+# umpf-release: distrokit/beaglebone/20121218
+# umpf-topic-range: 1008c9cfa5d53ee128edacdc6608aafb4946f4be..6e88807ad901e9a028fef46f76d7f6e8c40975eb
+0301-Release-distrokit-beaglebone-20121218.patch
+# umpf-end
diff --git a/platformconfig b/platformconfig
index 726a692..11215e2 100644
--- a/platformconfig
+++ b/platformconfig
@@ -83,8 +83,8 @@ PTXCONF_KERNEL_INSTALL=y
 PTXCONF_KERNEL_MODULES=y
 PTXCONF_KERNEL_MODULES_INSTALL=y
 PTXCONF_KERNEL_MODULES_BUILD="modules"
-PTXCONF_KERNEL_VERSION="3.7-rc6"
-PTXCONF_KERNEL_MD5="66a670a84bacec902d548362e9679112"
+PTXCONF_KERNEL_VERSION="3.7"
+PTXCONF_KERNEL_MD5="21223369d682bcf44bcdfe1521095983"
 PTXCONF_KERNEL_ARCH_STRING="arm"
 # PTXCONF_KERNEL_IMAGE_BZ is not set
 # PTXCONF_KERNEL_IMAGE_Z is not set