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authorSascha Hauer <s.hauer@pengutronix.de>2021-01-05 12:56:25 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2021-01-07 11:41:05 +0100
commit6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef (patch)
tree5d16ca525c12dddb21d9c4750dfd1a1e354eb731 /dts/Bindings/interrupt-controller
parent93c4690b4921d3149db3fcf5b62a8aa5010a4ae7 (diff)
downloadbarebox-6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef.tar.gz
dts: update to v5.11-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller')
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.yaml9
-rw-r--r--dts/Bindings/interrupt-controller/fsl,ls-extirq.txt8
-rw-r--r--dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt21
-rw-r--r--dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml64
-rw-r--r--dts/Bindings/interrupt-controller/mti,gic.yaml4
-rw-r--r--dts/Bindings/interrupt-controller/ti,pruss-intc.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/ti,sci-inta.yaml2
7 files changed, 82 insertions, 28 deletions
diff --git a/dts/Bindings/interrupt-controller/arm,gic.yaml b/dts/Bindings/interrupt-controller/arm,gic.yaml
index 0688996..ba282f4 100644
--- a/dts/Bindings/interrupt-controller/arm,gic.yaml
+++ b/dts/Bindings/interrupt-controller/arm,gic.yaml
@@ -35,7 +35,6 @@ properties:
- arm,gic-400
- arm,pl390
- arm,tc11mp-gic
- - nvidia,tegra210-agic
- qcom,msm-8660-qgic
- qcom,msm-qgic2
@@ -53,6 +52,14 @@ properties:
- const: brcm,brahma-b15-gic
- const: arm,cortex-a15-gic
+ - oneOf:
+ - const: nvidia,tegra210-agic
+ - items:
+ - enum:
+ - nvidia,tegra186-agic
+ - nvidia,tegra194-agic
+ - const: nvidia,tegra210-agic
+
interrupt-controller: true
"#address-cells":
diff --git a/dts/Bindings/interrupt-controller/fsl,ls-extirq.txt b/dts/Bindings/interrupt-controller/fsl,ls-extirq.txt
index f0ad780..4d47df1 100644
--- a/dts/Bindings/interrupt-controller/fsl,ls-extirq.txt
+++ b/dts/Bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -1,6 +1,7 @@
* Freescale Layerscape external IRQs
-Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
+LS1088A, LS208xA, LX216xA) support inverting
the polarity of certain external interrupt lines.
The device node must be a child of the node representing the
@@ -8,12 +9,15 @@ Supplemental Configuration Unit (SCFG).
Required properties:
- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+ "fsl,ls1043a-extirq": for LS1043A, LS1046A.
+ "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
- #interrupt-cells: Must be 2. The first element is the index of the
external interrupt line. The second element is the trigger type.
- #address-cells: Must be 0.
- interrupt-controller: Identifies the node as an interrupt controller
- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
- the SCFG.
+ the SCFG or the External Interrupt Control Register (IRQCR) in
+ the ISC.
- interrupt-map: Specifies the mapping from external interrupts to GIC
interrupts.
- interrupt-map-mask: Must be <0xffffffff 0>.
diff --git a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
deleted file mode 100644
index f5baecc..0000000
--- a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Microsemi Ocelot SoC ICPU Interrupt Controller
-
-Required properties:
-
-- compatible : should be "mscc,ocelot-icpu-intr"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value shall be 1.
-- interrupts : Specifies the CPU interrupt the controller is connected to.
-
-Example:
-
- intc: interrupt-controller@70000070 {
- compatible = "mscc,ocelot-icpu-intr";
- reg = <0x70000070 0x70>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&cpuintc>;
- interrupts = <2>;
- };
diff --git a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
new file mode 100644
index 0000000..27b798b
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microsemi Ocelot SoC ICPU Interrupt Controller
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ the Microsemi Ocelot interrupt controller that is part of the
+ ICPU. It is connected directly to the MIPS core interrupt
+ controller.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mscc,jaguar2-icpu-intr
+ - mscc,luton-icpu-intr
+ - mscc,ocelot-icpu-intr
+ - mscc,serval-icpu-intr
+
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+...
diff --git a/dts/Bindings/interrupt-controller/mti,gic.yaml b/dts/Bindings/interrupt-controller/mti,gic.yaml
index 039e08a..91bb3c2 100644
--- a/dts/Bindings/interrupt-controller/mti,gic.yaml
+++ b/dts/Bindings/interrupt-controller/mti,gic.yaml
@@ -42,7 +42,7 @@ properties:
Specifies the list of CPU interrupt vectors to which the GIC may not
route interrupts. This property is ignored if the CPU is started in EIC
mode.
- $ref: /schemas/types.yaml#definitions/uint32-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 6
uniqueItems: true
@@ -56,7 +56,7 @@ properties:
It accepts two values: the 1st is the starting interrupt and the 2nd is
the size of the reserved range. If not specified, the driver will
allocate the last (2 * number of VPEs in the system).
- $ref: /schemas/types.yaml#definitions/uint32-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
items:
- minimum: 0
maximum: 254
diff --git a/dts/Bindings/interrupt-controller/ti,pruss-intc.yaml b/dts/Bindings/interrupt-controller/ti,pruss-intc.yaml
index 1c4c009..c2ce215 100644
--- a/dts/Bindings/interrupt-controller/ti,pruss-intc.yaml
+++ b/dts/Bindings/interrupt-controller/ti,pruss-intc.yaml
@@ -80,7 +80,7 @@ properties:
mapping is provided.
ti,irqs-reserved:
- $ref: /schemas/types.yaml#definitions/uint8
+ $ref: /schemas/types.yaml#/definitions/uint8
description: |
Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
output interrupts 2 through 9) that are not connected to the Arm interrupt
diff --git a/dts/Bindings/interrupt-controller/ti,sci-inta.yaml b/dts/Bindings/interrupt-controller/ti,sci-inta.yaml
index b5af120..3d89668 100644
--- a/dts/Bindings/interrupt-controller/ti,sci-inta.yaml
+++ b/dts/Bindings/interrupt-controller/ti,sci-inta.yaml
@@ -76,7 +76,7 @@ properties:
"limit" specifies the limit for translation
ti,unmapped-event-sources:
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
description:
Array of phandles to DMA controllers where the unmapped events originate.