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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
commit | 2036f2866753a28b2783ad6dc78a40ca5345e6d8 (patch) | |
tree | 468b1c17b06a2377c5f8e6d711d8f3187f60667f /dts/src/arm/nspire.dtsi | |
parent | 785f926d4527184194b6424bc39ce367e2cea7d8 (diff) | |
download | barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.gz barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.xz |
dts: update to v5.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/nspire.dtsi')
-rw-r--r-- | dts/src/arm/nspire.dtsi | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/dts/src/arm/nspire.dtsi b/dts/src/arm/nspire.dtsi index c35fd66677..d9a0fd7524 100644 --- a/dts/src/arm/nspire.dtsi +++ b/dts/src/arm/nspire.dtsi @@ -95,8 +95,14 @@ reg = <0xC0000000 0x1000>; interrupts = <21>; - clocks = <&apb_pclk>; - clock-names = "apb_pclk"; + /* + * We assume the same clock is fed to APB and CLCDCLK. + * There is some code to scale the clock down by a factor + * 48 for the display so likely the frequency to the + * display is 1MHz and the CLCDCLK is 48 MHz. + */ + clocks = <&apb_pclk>, <&apb_pclk>; + clock-names = "clcdclk", "apb_pclk"; }; adc: adc@C4000000 { |