summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--Makefile2
-rw-r--r--arch/arm/boards/Makefile2
-rw-r--r--arch/arm/boards/animeo_ip/init.c23
-rw-r--r--arch/arm/boards/at91rm9200ek/config.h26
-rw-r--r--arch/arm/boards/at91rm9200ek/init.c1
-rw-r--r--arch/arm/boards/at91rm9200ek/lowlevel.c44
-rw-r--r--arch/arm/boards/at91sam9260ek/init.c22
-rw-r--r--arch/arm/boards/at91sam9261ek/init.c1
-rw-r--r--arch/arm/boards/at91sam9261ek/lowlevel_init.c6
-rw-r--r--arch/arm/boards/at91sam9263ek/init.c1
-rw-r--r--arch/arm/boards/at91sam9263ek/lowlevel_init.c8
-rw-r--r--arch/arm/boards/at91sam9263ek/of_init.c8
-rw-r--r--arch/arm/boards/at91sam9m10g45ek/init.c1
-rw-r--r--arch/arm/boards/at91sam9m10ihd/init.c1
-rw-r--r--arch/arm/boards/at91sam9n12ek/init.c1
-rw-r--r--arch/arm/boards/at91sam9x5ek/init.c17
-rw-r--r--arch/arm/boards/dss11/init.c23
-rw-r--r--arch/arm/boards/grinn-liteboard/Makefile2
-rw-r--r--arch/arm/boards/grinn-liteboard/board.c114
-rw-r--r--arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg6
-rw-r--r--arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg6
-rw-r--r--arch/arm/boards/grinn-liteboard/flash-header-liteboard.h68
-rw-r--r--arch/arm/boards/grinn-liteboard/lowlevel.c82
-rw-r--r--arch/arm/boards/haba-knx/init.c24
-rw-r--r--arch/arm/boards/microchip-ksz9477-evb/Makefile1
-rw-r--r--arch/arm/boards/microchip-ksz9477-evb/lowlevel.c28
-rw-r--r--arch/arm/boards/nxp-imx8mq-evk/board.c31
-rw-r--r--arch/arm/boards/pm9261/init.c1
-rw-r--r--arch/arm/boards/pm9261/lowlevel_init.c8
-rw-r--r--arch/arm/boards/pm9263/init.c1
-rw-r--r--arch/arm/boards/pm9263/lowlevel_init.c8
-rw-r--r--arch/arm/boards/pm9g45/init.c1
-rw-r--r--arch/arm/boards/qil-a926x/init.c23
-rw-r--r--arch/arm/boards/sama5d3_xplained/init.c1
-rw-r--r--arch/arm/boards/sama5d3xek/init.c1
-rw-r--r--arch/arm/boards/telit-evk-pro3/init.c22
-rw-r--r--arch/arm/boards/tny-a926x/init.c1
-rw-r--r--arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c8
-rw-r--r--arch/arm/boards/usb-a926x/init.c25
-rw-r--r--arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c8
-rw-r--r--arch/arm/boards/zii-imx51-rdu1/board.c179
-rw-r--r--arch/arm/boards/zii-imx6q-rdu2/board.c82
-rw-r--r--arch/arm/boards/zii-vf610-dev/board.c5
-rw-r--r--arch/arm/configs/imx_v7_defconfig1
-rw-r--r--arch/arm/configs/microchip_ksz9477_evb_defconfig74
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/at91-microchip-ksz9477-evb.dts153
-rw-r--r--arch/arm/dts/imx51-zii-rdu1.dts25
-rw-r--r--arch/arm/dts/imx6qdl-zii-rdu2.dtsi60
-rw-r--r--arch/arm/dts/imx6ul-liteboard.dts96
-rw-r--r--arch/arm/dts/imx7d-zii-rpu2.dts9
-rw-r--r--arch/arm/dts/imx8mq-evk.dts37
-rw-r--r--arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts2
-rw-r--r--arch/arm/dts/vf610-zii-cfu1.dts10
-rw-r--r--arch/arm/dts/vf610-zii-dev-rev-c.dts12
-rw-r--r--arch/arm/dts/vf610-zii-ssmb-spu3.dts11
-rw-r--r--arch/arm/mach-at91/Kconfig21
-rw-r--r--arch/arm/mach-at91/Makefile8
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c21
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c17
-rw-r--r--arch/arm/mach-at91/at91sam9260.c11
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c12
-rw-r--r--arch/arm/mach-at91/at91sam9261.c11
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c8
-rw-r--r--arch/arm/mach-at91/at91sam9263.c11
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c12
-rw-r--r--arch/arm/mach-at91/at91sam9_reset.S12
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c12
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c12
-rw-r--r--arch/arm/mach-at91/at91sam9g45_reset.S12
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c12
-rw-r--r--arch/arm/mach-at91/at91sam9n12_devices.c23
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c20
-rw-r--r--arch/arm/mach-at91/at91sam9x5_devices.c16
-rw-r--r--arch/arm/mach-at91/clock.c22
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rstc.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91_st.h49
-rw-r--r--arch/arm/mach-at91/include/mach/at91_tc.h146
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h39
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_mc.h277
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_st.h49
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h44
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260_matrix.h114
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h30
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261_matrix.h82
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h40
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263_matrix.h208
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam926x.h8
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam926x_board_init.h83
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_matrix.h30
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h5
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_smc.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h56
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h246
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9n12.h67
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h146
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5.h74
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h228
-rw-r--r--arch/arm/mach-at91/include/mach/board.h9
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h7
-rw-r--r--arch/arm/mach-at91/include/mach/io.h38
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3.h44
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d4.h10
-rw-r--r--arch/arm/mach-at91/sam9_smc.c1
-rw-r--r--arch/arm/mach-at91/sama5d3.c12
-rw-r--r--arch/arm/mach-at91/sama5d3_devices.c1
-rw-r--r--arch/arm/mach-at91/sama5d4.c12
-rw-r--r--arch/arm/mach-at91/sama5d4_devices.c1
-rw-r--r--arch/arm/mach-at91/setup.c33
-rw-r--r--arch/arm/mach-imx/Kconfig5
-rw-r--r--commands/gpio.c54
-rw-r--r--common/Makefile4
-rw-r--r--common/calloc.c19
-rw-r--r--common/dummy_malloc.c22
-rw-r--r--common/startup.c3
-rw-r--r--common/tlsf_malloc.c33
-rw-r--r--drivers/base/driver.c53
-rw-r--r--drivers/clocksource/timer-atmel-pit.c1
-rw-r--r--drivers/gpio/gpio-dw.c2
-rw-r--r--drivers/gpio/gpio-imx.c2
-rw-r--r--drivers/gpio/gpio-mxs.c2
-rw-r--r--drivers/gpio/gpio-vf610.c5
-rw-r--r--drivers/gpio/gpiolib.c30
-rw-r--r--drivers/mtd/nand/nand_denali_dt.c2
-rw-r--r--drivers/nvmem/Kconfig8
-rw-r--r--drivers/nvmem/Makefile5
-rw-r--r--drivers/nvmem/eeprom_93xx46.c446
-rw-r--r--drivers/of/fdt.c2
-rw-r--r--drivers/pinctrl/imx-iomux-v1.c2
-rw-r--r--drivers/pinctrl/imx-iomux-v2.c2
-rw-r--r--drivers/pinctrl/imx-iomux-v3.c2
-rw-r--r--drivers/pinctrl/mvebu/armada-370.c2
-rw-r--r--drivers/pinctrl/mvebu/armada-xp.c2
-rw-r--r--drivers/pinctrl/mvebu/dove.c2
-rw-r--r--drivers/pinctrl/mvebu/kirkwood.c2
-rw-r--r--drivers/pinctrl/pinctrl-at91.c4
-rw-r--r--drivers/pinctrl/pinctrl-mxs.c2
-rw-r--r--drivers/pinctrl/pinctrl-single.c2
-rw-r--r--drivers/pinctrl/pinctrl-tegra-xusb.c2
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c2
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c2
-rw-r--r--drivers/pinctrl/pinctrl-vf610.c2
-rw-r--r--drivers/spi/atmel_spi.c1
-rw-r--r--drivers/usb/gadget/at91_udc.c21
-rw-r--r--drivers/usb/gadget/f_fastboot.c1
-rw-r--r--drivers/video/atmel_hlcdfb.c1
-rw-r--r--drivers/video/atmel_lcdfb.c1
-rw-r--r--dts/Bindings/arm/al,alpine.txt72
-rw-r--r--dts/Bindings/arm/amlogic.txt7
-rw-r--r--dts/Bindings/arm/atmel-at91.txt170
-rw-r--r--dts/Bindings/arm/atmel-sysregs.txt171
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm2835.txt8
-rw-r--r--dts/Bindings/arm/coresight.txt120
-rw-r--r--dts/Bindings/arm/cpu-capacity.txt8
-rw-r--r--dts/Bindings/arm/cpu-enable-method/al,alpine-smp34
-rw-r--r--dts/Bindings/arm/cpus.txt4
-rw-r--r--dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt19
-rw-r--r--dts/Bindings/arm/freescale/fsl,layerscape-scfg.txt19
-rw-r--r--dts/Bindings/arm/freescale/fsl,scu.txt183
-rw-r--r--dts/Bindings/arm/fsl.txt83
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.txt8
-rw-r--r--dts/Bindings/arm/keystone/ti,sci.txt4
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,audsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,bdpsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,ethsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,hifsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,imgsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,infracfg.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mmsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,pericfg.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,topckgen.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,vdecsys.txt1
-rw-r--r--dts/Bindings/arm/msm/qcom,kpss-acc.txt19
-rw-r--r--dts/Bindings/arm/msm/qcom,kpss-gcc.txt44
-rw-r--r--dts/Bindings/arm/msm/qcom,llcc.txt19
-rw-r--r--dts/Bindings/arm/rockchip.txt20
-rw-r--r--dts/Bindings/arm/scu.txt2
-rw-r--r--dts/Bindings/arm/secure.txt19
-rw-r--r--dts/Bindings/arm/shmobile.txt16
-rw-r--r--dts/Bindings/arm/syna.txt (renamed from dts/Bindings/arm/marvell/marvell,berlin.txt)11
-rw-r--r--dts/Bindings/arm/tegra.txt9
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt93
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra20-pmc.txt103
-rw-r--r--dts/Bindings/arm/ux500/boards.txt2
-rw-r--r--dts/Bindings/arm/zte,sysctrl.txt30
-rw-r--r--dts/Bindings/arm/zte.txt27
-rw-r--r--dts/Bindings/ata/ahci-platform.txt6
-rw-r--r--dts/Bindings/ata/brcm,sata-brcm.txt1
-rw-r--r--dts/Bindings/clock/actions,owl-cmu.txt2
-rw-r--r--dts/Bindings/clock/at91-clock.txt516
-rw-r--r--dts/Bindings/clock/hi3670-clock.txt43
-rw-r--r--dts/Bindings/clock/imx6q-clock.txt8
-rw-r--r--dts/Bindings/clock/ingenic,cgu.txt7
-rw-r--r--dts/Bindings/clock/qcom,camcc.txt18
-rw-r--r--dts/Bindings/clock/qcom,gcc.txt3
-rw-r--r--dts/Bindings/clock/qcom,hfpll.txt60
-rw-r--r--dts/Bindings/clock/qcom,krait-cc.txt34
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt17
-rw-r--r--dts/Bindings/connector/usb-connector.txt8
-rw-r--r--dts/Bindings/crypto/hisilicon,hip07-sec.txt2
-rw-r--r--dts/Bindings/csky/cpus.txt73
-rw-r--r--dts/Bindings/display/atmel/hlcdc-dc.txt23
-rw-r--r--dts/Bindings/display/bridge/lvds-transmitter.txt8
-rw-r--r--dts/Bindings/display/bridge/renesas,lvds.txt14
-rw-r--r--dts/Bindings/display/bridge/ti,sn65dsi86.txt87
-rw-r--r--dts/Bindings/display/bridge/toshiba,tc358764.txt35
-rw-r--r--dts/Bindings/display/exynos/exynos_dsim.txt25
-rw-r--r--dts/Bindings/display/mipi-dsi-bus.txt153
-rw-r--r--dts/Bindings/display/panel/innolux,p120zdg-bf1.txt (renamed from dts/Bindings/display/panel/innolux,tv123wam.txt)8
-rw-r--r--dts/Bindings/display/panel/simple-panel.txt3
-rw-r--r--dts/Bindings/display/renesas,du.txt4
-rw-r--r--dts/Bindings/display/rockchip/rockchip-vop.txt3
-rw-r--r--dts/Bindings/display/sunxi/sun4i-drm.txt16
-rw-r--r--dts/Bindings/dma/jz4780-dma.txt14
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.txt1
-rw-r--r--dts/Bindings/dma/renesas,usb-dmac.txt1
-rw-r--r--dts/Bindings/firmware/qcom,scm.txt33
-rw-r--r--dts/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt82
-rw-r--r--dts/Bindings/fpga/fpga-region.txt4
-rw-r--r--dts/Bindings/gpio/gpio.txt142
-rw-r--r--dts/Bindings/gpio/ingenic,gpio.txt46
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt65
-rw-r--r--dts/Bindings/gpio/snps,creg-gpio.txt21
-rw-r--r--dts/Bindings/hwmon/ina3221.txt44
-rw-r--r--dts/Bindings/hwmon/ltc2978.txt2
-rw-r--r--dts/Bindings/i2c/i2c-designware.txt7
-rw-r--r--dts/Bindings/i2c/i2c-imx-lpi2c.txt1
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt2
-rw-r--r--dts/Bindings/i2c/i2c-sh_mobile.txt1
-rw-r--r--dts/Bindings/i2c/i2c.txt2
-rw-r--r--dts/Bindings/iio/accel/adxl372.txt33
-rw-r--r--dts/Bindings/iio/adc/mcp3911.txt30
-rw-r--r--dts/Bindings/iio/adc/qcom,spmi-vadc.txt81
-rw-r--r--dts/Bindings/iio/adc/sprd,sc27xx-adc.txt4
-rw-r--r--dts/Bindings/iio/dac/ad5758.txt5
-rw-r--r--dts/Bindings/iio/dac/ltc1660.txt21
-rw-r--r--dts/Bindings/iio/imu/inv_mpu6050.txt1
-rw-r--r--dts/Bindings/iio/imu/st_lsm6dsx.txt1
-rw-r--r--dts/Bindings/iio/light/bh1750.txt18
-rw-r--r--dts/Bindings/iio/light/tsl2772.txt42
-rw-r--r--dts/Bindings/iio/proximity/vl53l0x.txt12
-rw-r--r--dts/Bindings/input/pwm-vibrator.txt4
-rw-r--r--dts/Bindings/input/touchscreen/touchscreen.txt6
-rw-r--r--dts/Bindings/interrupt-controller/csky,apb-intc.txt62
-rw-r--r--dts/Bindings/interrupt-controller/csky,mpintc.txt40
-rw-r--r--dts/Bindings/interrupt-controller/marvell,icu.txt85
-rw-r--r--dts/Bindings/interrupt-controller/marvell,sei.txt36
-rw-r--r--dts/Bindings/interrupt-controller/renesas,irqc.txt5
-rw-r--r--dts/Bindings/iommu/mediatek,iommu.txt4
-rw-r--r--dts/Bindings/iommu/renesas,ipmmu-vmsa.txt1
-rw-r--r--dts/Bindings/leds/leds-an30259a.txt43
-rw-r--r--dts/Bindings/mailbox/qcom,apcs-kpss-global.txt1
-rw-r--r--dts/Bindings/media/cedrus.txt54
-rw-r--r--dts/Bindings/media/fsl-pxp.txt26
-rw-r--r--dts/Bindings/media/i2c/adv748x.txt20
-rw-r--r--dts/Bindings/media/i2c/adv7604.txt2
-rw-r--r--dts/Bindings/media/i2c/dongwoon,dw9807-vcm.txt (renamed from dts/Bindings/media/i2c/dongwoon,dw9807.txt)0
-rw-r--r--dts/Bindings/media/mediatek-jpeg-decoder.txt1
-rw-r--r--dts/Bindings/media/rcar_vin.txt1
-rw-r--r--dts/Bindings/media/renesas,ceu.txt14
-rw-r--r--dts/Bindings/media/rockchip-vpu.txt29
-rw-r--r--dts/Bindings/media/video-interfaces.txt4
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-common.txt1
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-larb.txt3
-rw-r--r--dts/Bindings/mfd/arizona.txt2
-rw-r--r--dts/Bindings/mfd/atmel-usart.txt (renamed from dts/Bindings/serial/atmel-usart.txt)25
-rw-r--r--dts/Bindings/mfd/rohm,bd71837-pmic.txt17
-rw-r--r--dts/Bindings/mips/mscc.txt16
-rw-r--r--dts/Bindings/misc/fsl,qoriq-mc.txt39
-rw-r--r--dts/Bindings/misc/lwn-bk4.txt26
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt1
-rw-r--r--dts/Bindings/mmc/jz4740.txt1
-rw-r--r--dts/Bindings/mmc/mmci.txt11
-rw-r--r--dts/Bindings/mmc/mtk-sd.txt2
-rw-r--r--dts/Bindings/mmc/nvidia,tegra20-sdhci.txt72
-rw-r--r--dts/Bindings/mmc/renesas,mmcif.txt4
-rw-r--r--dts/Bindings/mmc/sdhci-sprd.txt41
-rw-r--r--dts/Bindings/mmc/tmio_mmc.txt10
-rw-r--r--dts/Bindings/mmc/uniphier-sd.txt55
-rw-r--r--dts/Bindings/net/brcm,unimac-mdio.txt3
-rw-r--r--dts/Bindings/net/can/rcar_can.txt1
-rw-r--r--dts/Bindings/net/dsa/b53.txt36
-rw-r--r--dts/Bindings/net/dsa/lantiq-gswip.txt143
-rw-r--r--dts/Bindings/net/lantiq,xrx200-net.txt21
-rw-r--r--dts/Bindings/net/marvell,prestera.txt4
-rw-r--r--dts/Bindings/net/marvell-pp2.txt45
-rw-r--r--dts/Bindings/net/micrel-ksz90x1.txt28
-rw-r--r--dts/Bindings/net/mscc-ocelot.txt9
-rw-r--r--dts/Bindings/net/mscc-phy-vsc8531.txt21
-rw-r--r--dts/Bindings/net/renesas,ravb.txt1
-rw-r--r--dts/Bindings/net/wireless/qcom,ath10k.txt6
-rw-r--r--dts/Bindings/nvmem/allwinner,sunxi-sid.txt1
-rw-r--r--dts/Bindings/pci/fsl,imx6q-pcie.txt1
-rw-r--r--dts/Bindings/pci/pci-keystone.txt3
-rw-r--r--dts/Bindings/pci/pci-rcar-gen2.txt1
-rw-r--r--dts/Bindings/pci/rcar-pci.txt2
-rw-r--r--dts/Bindings/pci/ti-pci.txt5
-rw-r--r--dts/Bindings/phy/brcm-sata-phy.txt1
-rw-r--r--dts/Bindings/phy/phy-cadence-dp.txt30
-rw-r--r--dts/Bindings/phy/phy-ocelot-serdes.txt43
-rw-r--r--dts/Bindings/phy/phy-rockchip-inno-hdmi.txt43
-rw-r--r--dts/Bindings/phy/qcom-qmp-phy.txt23
-rw-r--r--dts/Bindings/phy/rcar-gen2-phy.txt1
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb2.txt11
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb3.txt10
-rw-r--r--dts/Bindings/phy/uniphier-pcie-phy.txt31
-rw-r--r--dts/Bindings/phy/uniphier-usb2-phy.txt45
-rw-r--r--dts/Bindings/phy/uniphier-usb3-hsphy.txt69
-rw-r--r--dts/Bindings/phy/uniphier-usb3-ssphy.txt57
-rw-r--r--dts/Bindings/pinctrl/brcm,bcm4708-pinmux.txt57
-rw-r--r--dts/Bindings/pinctrl/ingenic,pinctrl.txt39
-rw-r--r--dts/Bindings/pinctrl/meson,pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt216
-rw-r--r--dts/Bindings/pinctrl/qcom,pmic-gpio.txt2
-rw-r--r--dts/Bindings/pinctrl/qcom,qcs404-pinctrl.txt199
-rw-r--r--dts/Bindings/pinctrl/qcom,sdm660-pinctrl.txt191
-rw-r--r--dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt3
-rw-r--r--dts/Bindings/pinctrl/renesas,rzn1-pinctrl.txt153
-rw-r--r--dts/Bindings/power/actions,owl-sps.txt2
-rw-r--r--dts/Bindings/power/renesas,apmu.txt2
-rw-r--r--dts/Bindings/power/renesas,rcar-sysc.txt3
-rw-r--r--dts/Bindings/power/reset/qcom,pon.txt5
-rw-r--r--dts/Bindings/power/supply/bq25890.txt3
-rw-r--r--dts/Bindings/power/supply/bq27xxx.txt1
-rw-r--r--dts/Bindings/power/supply/sc2731_charger.txt40
-rw-r--r--dts/Bindings/pwm/pwm-tiecap.txt1
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.txt4
-rw-r--r--dts/Bindings/pwm/renesas,tpu-pwm.txt10
-rw-r--r--dts/Bindings/regulator/pfuze100.txt5
-rw-r--r--dts/Bindings/regulator/qcom,smd-rpm-regulator.txt23
-rw-r--r--dts/Bindings/regulator/rohm,bd71837-regulator.txt12
-rw-r--r--dts/Bindings/regulator/st,stpmic1-regulator.txt68
-rw-r--r--dts/Bindings/remoteproc/qcom,adsp-pil.txt126
-rw-r--r--dts/Bindings/remoteproc/qcom,adsp.txt5
-rw-r--r--dts/Bindings/remoteproc/qcom,q6v5.txt8
-rw-r--r--dts/Bindings/reset/fsl,imx7-src.txt2
-rw-r--r--dts/Bindings/reset/qcom,pdc-global.txt52
-rw-r--r--dts/Bindings/reset/renesas,rst.txt3
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt6
-rw-r--r--dts/Bindings/serial/uniphier-uart.txt3
-rw-r--r--dts/Bindings/soc/amlogic/amlogic,canvas.txt29
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/network.txt6
-rw-r--r--dts/Bindings/soc/mediatek/pwrap.txt2
-rw-r--r--dts/Bindings/soc/qcom/qcom,geni-se.txt29
-rw-r--r--dts/Bindings/soc/rockchip/grf.txt2
-rw-r--r--dts/Bindings/sound/adi,adau1977.txt54
-rw-r--r--dts/Bindings/sound/amlogic,axg-pdm.txt24
-rw-r--r--dts/Bindings/sound/cs42l51.txt17
-rw-r--r--dts/Bindings/sound/maxim,max98088.txt23
-rw-r--r--dts/Bindings/sound/mikroe,mikroe-proto.txt23
-rw-r--r--dts/Bindings/sound/nau8822.txt16
-rw-r--r--dts/Bindings/sound/pcm3060.txt17
-rw-r--r--dts/Bindings/sound/qcom,q6afe.txt18
-rw-r--r--dts/Bindings/sound/renesas,rsnd.txt5
-rw-r--r--dts/Bindings/sound/st,sta32x.txt9
-rw-r--r--dts/Bindings/sound/st,stm32-sai.txt7
-rw-r--r--dts/Bindings/sound/sun4i-i2s.txt2
-rw-r--r--dts/Bindings/sound/sun50i-codec-analog.txt12
-rw-r--r--dts/Bindings/sound/ts3a227e.txt2
-rw-r--r--dts/Bindings/sound/wm8782.txt17
-rw-r--r--dts/Bindings/spi/qcom,spi-geni-qcom.txt39
-rw-r--r--dts/Bindings/spi/qcom,spi-qcom-qspi.txt36
-rw-r--r--dts/Bindings/spi/sh-msiof.txt8
-rw-r--r--dts/Bindings/spi/snps,dw-apb-ssi.txt2
-rw-r--r--dts/Bindings/spi/spi-fsl-lpspi.txt1
-rw-r--r--dts/Bindings/spi/spi-pxa2xx.txt24
-rw-r--r--dts/Bindings/spi/spi-rspi.txt4
-rw-r--r--dts/Bindings/spi/spi-slave-mt27xx.txt32
-rw-r--r--dts/Bindings/spi/spi-sprd.txt26
-rw-r--r--dts/Bindings/spi/spi-stm32-qspi.txt44
-rw-r--r--dts/Bindings/sram/sunxi-sram.txt4
-rw-r--r--dts/Bindings/thermal/qcom-spmi-temp-alarm.txt16
-rw-r--r--dts/Bindings/thermal/qoriq-thermal.txt6
-rw-r--r--dts/Bindings/thermal/rcar-gen3-thermal.txt5
-rw-r--r--dts/Bindings/thermal/rcar-thermal.txt6
-rw-r--r--dts/Bindings/thermal/stm32-thermal.txt61
-rw-r--r--dts/Bindings/thermal/thermal.txt2
-rw-r--r--dts/Bindings/timer/csky,gx6605s-timer.txt42
-rw-r--r--dts/Bindings/timer/csky,mptimer.txt42
-rw-r--r--dts/Bindings/timer/renesas,cmt.txt9
-rw-r--r--dts/Bindings/timer/renesas,ostm.txt3
-rw-r--r--dts/Bindings/timer/renesas,tmu.txt2
-rw-r--r--dts/Bindings/trivial-devices.txt11
-rw-r--r--dts/Bindings/usb/ci-hdrc-usb2.txt2
-rw-r--r--dts/Bindings/usb/dwc2.txt1
-rw-r--r--dts/Bindings/usb/dwc3.txt1
-rw-r--r--dts/Bindings/usb/ehci-mv.txt23
-rw-r--r--dts/Bindings/usb/exynos-usb.txt2
-rw-r--r--dts/Bindings/usb/faraday,fotg210.txt35
-rw-r--r--dts/Bindings/usb/fcs,fusb302.txt32
-rw-r--r--dts/Bindings/usb/renesas_usb3.txt6
-rw-r--r--dts/Bindings/usb/renesas_usbhs.txt11
-rw-r--r--dts/Bindings/usb/usb-ehci.txt6
-rw-r--r--dts/Bindings/usb/usb-ohci.txt6
-rw-r--r--dts/Bindings/usb/usb-xhci.txt5
-rw-r--r--dts/Bindings/vendor-prefixes.txt6
-rw-r--r--dts/Bindings/watchdog/armada-37xx-wdt.txt23
-rw-r--r--dts/Bindings/watchdog/mpc8xxx-wdt.txt25
-rw-r--r--dts/Bindings/watchdog/renesas-wdt.txt2
-rw-r--r--dts/include/dt-bindings/clock/am3.h119
-rw-r--r--dts/include/dt-bindings/clock/am4.h132
-rw-r--r--dts/include/dt-bindings/clock/at91.h15
-rw-r--r--dts/include/dt-bindings/clock/dra7.h326
-rw-r--r--dts/include/dt-bindings/clock/exynos3250.h5
-rw-r--r--dts/include/dt-bindings/clock/exynos4.h37
-rw-r--r--dts/include/dt-bindings/clock/exynos5250.h7
-rw-r--r--dts/include/dt-bindings/clock/exynos5260-clk.h7
-rw-r--r--dts/include/dt-bindings/clock/exynos5410.h7
-rw-r--r--dts/include/dt-bindings/clock/exynos5420.h7
-rw-r--r--dts/include/dt-bindings/clock/exynos5433.h5
-rw-r--r--dts/include/dt-bindings/clock/exynos7-clk.h7
-rw-r--r--dts/include/dt-bindings/clock/hi3670-clock.h348
-rw-r--r--dts/include/dt-bindings/clock/imx6qdl-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/imx6sl-clock.h4
-rw-r--r--dts/include/dt-bindings/clock/imx6sll-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/imx6sx-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/imx6ul-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/jz4725b-cgu.h35
-rw-r--r--dts/include/dt-bindings/clock/maxim,max77686.h5
-rw-r--r--dts/include/dt-bindings/clock/maxim,max77802.h5
-rw-r--r--dts/include/dt-bindings/clock/qcom,camcc-sdm845.h116
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-msm8960.h2
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-msm8996.h9
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-qcs404.h165
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-sdm660.h156
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-sdm845.h3
-rw-r--r--dts/include/dt-bindings/clock/r7s72100-clock.h7
-rw-r--r--dts/include/dt-bindings/clock/r7s9210-cpg-mssr.h20
-rw-r--r--dts/include/dt-bindings/clock/r8a7743-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a7744-cpg-mssr.h39
-rw-r--r--dts/include/dt-bindings/clock/r8a7745-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a774a1-cpg-mssr.h58
-rw-r--r--dts/include/dt-bindings/clock/r8a774c0-cpg-mssr.h60
-rw-r--r--dts/include/dt-bindings/clock/r8a7790-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a7791-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a7792-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a7793-clock.h12
-rw-r--r--dts/include/dt-bindings/clock/r8a7793-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a7794-clock.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a7794-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a7795-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a7796-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a77970-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/renesas-cpg-mssr.h8
-rw-r--r--dts/include/dt-bindings/clock/rk3188-cru-common.h3
-rw-r--r--dts/include/dt-bindings/clock/s3c2410.h5
-rw-r--r--dts/include/dt-bindings/clock/s3c2412.h5
-rw-r--r--dts/include/dt-bindings/clock/s3c2443.h5
-rw-r--r--dts/include/dt-bindings/clock/samsung,s2mps11.h5
-rw-r--r--dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h7
-rw-r--r--dts/include/dt-bindings/clock/sun50i-a64-ccu.h1
-rw-r--r--dts/include/dt-bindings/clock/xlnx,zynqmp-clk.h116
-rw-r--r--dts/include/dt-bindings/gpio/meson-g12a-gpio.h114
-rw-r--r--dts/include/dt-bindings/iio/qcom,spmi-vadc.h125
-rw-r--r--dts/include/dt-bindings/input/linux-event-codes.h18
-rw-r--r--dts/include/dt-bindings/interrupt-controller/arm-gic.h2
-rw-r--r--dts/include/dt-bindings/interrupt-controller/irq.h2
-rw-r--r--dts/include/dt-bindings/mfd/at91-usart.h17
-rw-r--r--dts/include/dt-bindings/net/mscc-phy-vsc8531.h2
-rw-r--r--dts/include/dt-bindings/phy/phy-ocelot-serdes.h12
-rw-r--r--dts/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h18
-rw-r--r--dts/include/dt-bindings/pinctrl/rzn1-pinctrl.h141
-rw-r--r--dts/include/dt-bindings/power/owl-s900-powergate.h23
-rw-r--r--dts/include/dt-bindings/power/r8a7744-sysc.h24
-rw-r--r--dts/include/dt-bindings/power/r8a774a1-sysc.h31
-rw-r--r--dts/include/dt-bindings/power/r8a774c0-sysc.h25
-rw-r--r--dts/include/dt-bindings/reset/actions,s700-reset.h34
-rw-r--r--dts/include/dt-bindings/reset/actions,s900-reset.h65
-rw-r--r--dts/include/dt-bindings/reset/imx7-reset.h4
-rw-r--r--dts/include/dt-bindings/reset/qcom,sdm845-pdc.h20
-rw-r--r--dts/include/dt-bindings/thermal/thermal_exynos.h12
-rw-r--r--dts/include/dt-bindings/usb/pd.h26
-rw-r--r--dts/src/arm/am335x-bone-common.dtsi6
-rw-r--r--dts/src/arm/am335x-boneblack-common.dtsi5
-rw-r--r--dts/src/arm/am335x-chiliboard.dts6
-rw-r--r--dts/src/arm/am335x-cm-t335.dts6
-rw-r--r--dts/src/arm/am335x-evm.dts12
-rw-r--r--dts/src/arm/am335x-evmsk.dts12
-rw-r--r--dts/src/arm/am335x-igep0033.dtsi13
-rw-r--r--dts/src/arm/am335x-lxm.dts12
-rw-r--r--dts/src/arm/am335x-moxa-uc-2100-common.dtsi249
-rw-r--r--dts/src/arm/am335x-moxa-uc-2101.dts69
-rw-r--r--dts/src/arm/am335x-moxa-uc-8100-me-t.dts12
-rw-r--r--dts/src/arm/am335x-nano.dts12
-rw-r--r--dts/src/arm/am335x-osd3358-sm-red.dts8
-rw-r--r--dts/src/arm/am335x-pdu001.dts14
-rw-r--r--dts/src/arm/am335x-pepper.dts12
-rw-r--r--dts/src/arm/am335x-sancloud-bbe.dts6
-rw-r--r--dts/src/arm/am335x-shc.dts1
-rw-r--r--dts/src/arm/am3517-evm-ui.dtsi220
-rw-r--r--dts/src/arm/am3517-evm.dts1
-rw-r--r--dts/src/arm/am4372.dtsi2
-rw-r--r--dts/src/arm/am437x-cm-t43.dts12
-rw-r--r--dts/src/arm/am437x-gp-evm.dts6
-rw-r--r--dts/src/arm/am437x-idk-evm.dts6
-rw-r--r--dts/src/arm/am437x-sk-evm.dts12
-rw-r--r--dts/src/arm/am43x-epos-evm.dts6
-rw-r--r--dts/src/arm/am571x-idk.dts84
-rw-r--r--dts/src/arm/am572x-idk-common.dtsi76
-rw-r--r--dts/src/arm/am572x-idk.dts4
-rw-r--r--dts/src/arm/am57xx-cl-som-am57x.dts14
-rw-r--r--dts/src/arm/am57xx-idk-common.dtsi18
-rw-r--r--dts/src/arm/arm-realview-eb.dtsi2
-rw-r--r--dts/src/arm/arm-realview-pb1176.dts2
-rw-r--r--dts/src/arm/arm-realview-pb11mp.dts2
-rw-r--r--dts/src/arm/arm-realview-pbx.dtsi2
-rw-r--r--dts/src/arm/armada-385-db-88f6820-amc.dts155
-rw-r--r--dts/src/arm/armada-388-clearfog.dtsi2
-rw-r--r--dts/src/arm/armada-xp-98dx3236.dtsi4
-rw-r--r--dts/src/arm/armada-xp-98dx3336.dtsi2
-rw-r--r--dts/src/arm/armada-xp-98dx4251.dtsi2
-rw-r--r--dts/src/arm/armada-xp-db-dxbc2.dts18
-rw-r--r--dts/src/arm/armada-xp-db-xc3-24g4xg.dts18
-rw-r--r--dts/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts207
-rw-r--r--dts/src/arm/aspeed-bmc-facebook-tiogapass.dts146
-rw-r--r--dts/src/arm/aspeed-bmc-quanta-q71l.dts47
-rw-r--r--dts/src/arm/aspeed-g4.dtsi2
-rw-r--r--dts/src/arm/aspeed-g5.dtsi2
-rw-r--r--dts/src/arm/at91-dvk_su60_somc.dtsi4
-rw-r--r--dts/src/arm/at91-dvk_su60_somc_lcm.dtsi4
-rw-r--r--dts/src/arm/at91-nattis-2-natte-2.dts103
-rw-r--r--dts/src/arm/at91-sama5d27_som1_ek.dts42
-rw-r--r--dts/src/arm/at91-sama5d2_ptc_ek.dts8
-rw-r--r--dts/src/arm/at91-sama5d2_xplained.dts30
-rw-r--r--dts/src/arm/at91-sama5d3_xplained.dts11
-rw-r--r--dts/src/arm/at91-sama5d4_xplained.dts13
-rw-r--r--dts/src/arm/at91-tse850-3.dts32
-rw-r--r--dts/src/arm/at91-vinco.dts2
-rw-r--r--dts/src/arm/at91sam9260ek.dts2
-rw-r--r--dts/src/arm/at91sam9261ek.dts2
-rw-r--r--dts/src/arm/at91sam9g20ek_common.dtsi2
-rw-r--r--dts/src/arm/at91sam9g45.dtsi2
-rw-r--r--dts/src/arm/at91sam9x5cm.dtsi18
-rw-r--r--dts/src/arm/bcm-hr2.dtsi2
-rw-r--r--dts/src/arm/bcm-nsp.dtsi33
-rw-r--r--dts/src/arm/bcm2837-rpi-cm3-io3.dts87
-rw-r--r--dts/src/arm/bcm2837-rpi-cm3.dtsi52
-rw-r--r--dts/src/arm/bcm283x-rpi-lan7515.dtsi14
-rw-r--r--dts/src/arm/bcm47081-tplink-archer-c5-v2.dts28
-rw-r--r--dts/src/arm/bcm4709-asus-rt-ac87u.dts31
-rw-r--r--dts/src/arm/bcm4709-tplink-archer-c9-v1.dts28
-rw-r--r--dts/src/arm/bcm5301x-nand-cs0.dtsi4
-rw-r--r--dts/src/arm/bcm5301x.dtsi5
-rw-r--r--dts/src/arm/bcm958625hr.dts26
-rw-r--r--dts/src/arm/da850-evm.dts6
-rw-r--r--dts/src/arm/da850-lego-ev3.dts3
-rw-r--r--dts/src/arm/dm8148-evm.dts14
-rw-r--r--dts/src/arm/dm8148-t410.dts14
-rw-r--r--dts/src/arm/dove-cubox.dts2
-rw-r--r--dts/src/arm/dove.dtsi6
-rw-r--r--dts/src/arm/dra62x-j5eco-evm.dts14
-rw-r--r--dts/src/arm/dra7-evm.dts14
-rw-r--r--dts/src/arm/dra7.dtsi6
-rw-r--r--dts/src/arm/dra71-evm.dts4
-rw-r--r--dts/src/arm/dra72-evm-revc.dts4
-rw-r--r--dts/src/arm/dra72-evm.dts8
-rw-r--r--dts/src/arm/dra76-evm.dts4
-rw-r--r--dts/src/arm/exynos3250-artik5.dtsi7
-rw-r--r--dts/src/arm/exynos4210-origen.dts9
-rw-r--r--dts/src/arm/exynos4210-trats.dts15
-rw-r--r--dts/src/arm/exynos4210-universal_c210.dts11
-rw-r--r--dts/src/arm/exynos4412-midas.dtsi3
-rw-r--r--dts/src/arm/exynos4412-odroid-common.dtsi3
-rw-r--r--dts/src/arm/exynos5250-arndale.dts102
-rw-r--r--dts/src/arm/exynos5250-pinctrl.dtsi11
-rw-r--r--dts/src/arm/exynos5250-snow-rev5.dts11
-rw-r--r--dts/src/arm/exynos5250.dtsi152
-rw-r--r--dts/src/arm/exynos5410-odroidxu.dts10
-rw-r--r--dts/src/arm/exynos5420-peach-pit.dts5
-rw-r--r--dts/src/arm/exynos5422-odroid-core.dtsi157
-rw-r--r--dts/src/arm/exynos5422-odroidxu3-common.dtsi6
-rw-r--r--dts/src/arm/exynos5422-odroidxu3.dts6
-rw-r--r--dts/src/arm/exynos5800-peach-pi.dts5
-rw-r--r--dts/src/arm/gr-peach-audiocamerashield.dtsi4
-rw-r--r--dts/src/arm/hip04.dtsi346
-rw-r--r--dts/src/arm/imx1.dtsi4
-rw-r--r--dts/src/arm/imx23-evk.dts2
-rw-r--r--dts/src/arm/imx23-olinuxino.dts4
-rw-r--r--dts/src/arm/imx23-sansa.dts4
-rw-r--r--dts/src/arm/imx23-stmp378x_devb.dts2
-rw-r--r--dts/src/arm/imx23-xfi3.dts4
-rw-r--r--dts/src/arm/imx23.dtsi4
-rw-r--r--dts/src/arm/imx25.dtsi6
-rw-r--r--dts/src/arm/imx27.dtsi6
-rw-r--r--dts/src/arm/imx28-apf28dev.dts4
-rw-r--r--dts/src/arm/imx28-apx4devkit.dts4
-rw-r--r--dts/src/arm/imx28-cfa10036.dts2
-rw-r--r--dts/src/arm/imx28-duckbill-2-485.dts4
-rw-r--r--dts/src/arm/imx28-duckbill-2-enocean.dts4
-rw-r--r--dts/src/arm/imx28-duckbill-2-spi.dts4
-rw-r--r--dts/src/arm/imx28-duckbill-2.dts4
-rw-r--r--dts/src/arm/imx28-duckbill.dts4
-rw-r--r--dts/src/arm/imx28-evk.dts6
-rw-r--r--dts/src/arm/imx28-m28cu3.dts4
-rw-r--r--dts/src/arm/imx28-m28evk.dts4
-rw-r--r--dts/src/arm/imx28-sps1.dts4
-rw-r--r--dts/src/arm/imx28-ts4600.dts2
-rw-r--r--dts/src/arm/imx28.dtsi8
-rw-r--r--dts/src/arm/imx31.dtsi4
-rw-r--r--dts/src/arm/imx35.dtsi4
-rw-r--r--dts/src/arm/imx50.dtsi6
-rw-r--r--dts/src/arm/imx51-babbage.dts1
-rw-r--r--dts/src/arm/imx51-zii-rdu1.dts2
-rw-r--r--dts/src/arm/imx51-zii-scu2-mezz.dts8
-rw-r--r--dts/src/arm/imx51-zii-scu3-esb.dts4
-rw-r--r--dts/src/arm/imx51.dtsi8
-rw-r--r--dts/src/arm/imx53-ppd.dts1
-rw-r--r--dts/src/arm/imx53-qsb-common.dtsi11
-rw-r--r--dts/src/arm/imx53.dtsi6
-rw-r--r--dts/src/arm/imx6dl-colibri-eval-v3.dts2
-rw-r--r--dts/src/arm/imx6dl-icore-mipi.dts2
-rw-r--r--dts/src/arm/imx6dl-icore-rqs.dts38
-rw-r--r--dts/src/arm/imx6dl-icore.dts38
-rw-r--r--dts/src/arm/imx6dl-riotboard.dts5
-rw-r--r--dts/src/arm/imx6q-apalis-eval.dts2
-rw-r--r--dts/src/arm/imx6q-apalis-ixora-v1.1.dts2
-rw-r--r--dts/src/arm/imx6q-apalis-ixora.dts2
-rw-r--r--dts/src/arm/imx6q-icore-mipi.dts6
-rw-r--r--dts/src/arm/imx6q-icore-ofcap10.dts38
-rw-r--r--dts/src/arm/imx6q-icore-ofcap12.dts38
-rw-r--r--dts/src/arm/imx6q-icore-rqs.dts39
-rw-r--r--dts/src/arm/imx6q-icore.dts38
-rw-r--r--dts/src/arm/imx6q.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-apalis.dtsi4
-rw-r--r--dts/src/arm/imx6qdl-icore-1.5.dtsi34
-rw-r--r--dts/src/arm/imx6qdl-icore-rqs.dtsi41
-rw-r--r--dts/src/arm/imx6qdl-icore.dtsi42
-rw-r--r--dts/src/arm/imx6qdl-sabreauto.dtsi67
-rw-r--r--dts/src/arm/imx6qdl-wandboard.dtsi4
-rw-r--r--dts/src/arm/imx6qdl-zii-rdu2.dtsi4
-rw-r--r--dts/src/arm/imx6qdl.dtsi8
-rw-r--r--dts/src/arm/imx6sl.dtsi8
-rw-r--r--dts/src/arm/imx6sll.dtsi31
-rw-r--r--dts/src/arm/imx6sx-sdb.dtsi2
-rw-r--r--dts/src/arm/imx6sx.dtsi14
-rw-r--r--dts/src/arm/imx6ul-ccimx6ulsbcpro.dts390
-rw-r--r--dts/src/arm/imx6ul-geam.dts40
-rw-r--r--dts/src/arm/imx6ul-isiot-emmc.dts61
-rw-r--r--dts/src/arm/imx6ul-isiot-nand.dts63
-rw-r--r--dts/src/arm/imx6ul-isiot.dtsi90
-rw-r--r--dts/src/arm/imx6ul.dtsi28
-rw-r--r--dts/src/arm/imx6ull-14x14-evk.dts2
-rw-r--r--dts/src/arm/imx6ull-pinfunc.h39
-rw-r--r--dts/src/arm/imx6ull.dtsi2
-rw-r--r--dts/src/arm/imx6ulz-14x14-evk.dts20
-rw-r--r--dts/src/arm/imx6ulz.dtsi38
-rw-r--r--dts/src/arm/imx7d-sdb.dts2
-rw-r--r--dts/src/arm/imx7d.dtsi20
-rw-r--r--dts/src/arm/imx7s-warp.dts53
-rw-r--r--dts/src/arm/imx7s.dtsi131
-rw-r--r--dts/src/arm/imx7ulp-pinfunc.h16
-rw-r--r--dts/src/arm/iwg20d-q7-common.dtsi4
-rw-r--r--dts/src/arm/keystone-k2g.dtsi2
-rw-r--r--dts/src/arm/lpc32xx.dtsi4
-rw-r--r--dts/src/arm/ls1021a-qds.dts2
-rw-r--r--dts/src/arm/ls1021a-twr.dts2
-rw-r--r--dts/src/arm/ls1021a.dtsi12
-rw-r--r--dts/src/arm/meson8.dtsi2
-rw-r--r--dts/src/arm/meson8b-ec100.dts248
-rw-r--r--dts/src/arm/meson8b-odroidc1.dts109
-rw-r--r--dts/src/arm/meson8b.dtsi47
-rw-r--r--dts/src/arm/mt7623.dtsi124
-rw-r--r--dts/src/arm/omap2.dtsi4
-rw-r--r--dts/src/arm/omap2430.dtsi2
-rw-r--r--dts/src/arm/omap3-beagle-xm.dts17
-rw-r--r--dts/src/arm/omap3-beagle.dts17
-rw-r--r--dts/src/arm/omap3-gta04.dtsi262
-rw-r--r--dts/src/arm/omap3-gta04a3.dts2
-rw-r--r--dts/src/arm/omap3-gta04a4.dts2
-rw-r--r--dts/src/arm/omap3-gta04a5.dts129
-rw-r--r--dts/src/arm/omap3-gta04a5one.dts114
-rw-r--r--dts/src/arm/omap3-n9.dts2
-rw-r--r--dts/src/arm/omap5-board-common.dtsi4
-rw-r--r--dts/src/arm/orion5x-linkstation.dtsi2
-rw-r--r--dts/src/arm/owl-s500-cubieboard6.dts3
-rw-r--r--dts/src/arm/owl-s500-guitar-bb-rev-b.dts3
-rw-r--r--dts/src/arm/owl-s500-guitar.dtsi3
-rw-r--r--dts/src/arm/owl-s500.dtsi3
-rw-r--r--dts/src/arm/pxa25x.dtsi4
-rw-r--r--dts/src/arm/pxa27x.dtsi6
-rw-r--r--dts/src/arm/pxa2xx.dtsi27
-rw-r--r--dts/src/arm/qcom-apq8064.dtsi71
-rw-r--r--dts/src/arm/qcom-ipq4019.dtsi143
-rw-r--r--dts/src/arm/qcom-ipq8064-ap148.dts83
-rw-r--r--dts/src/arm/qcom-ipq8064-v1.0.dtsi125
-rw-r--r--dts/src/arm/qcom-ipq8064.dtsi286
-rw-r--r--dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts83
-rw-r--r--dts/src/arm/qcom-msm8974.dtsi198
-rw-r--r--dts/src/arm/r8a7743-iwg20d-q7-dbcm-ca.dts4
-rw-r--r--dts/src/arm/r8a7743-iwg20d-q7.dts4
-rw-r--r--dts/src/arm/r8a77470-iwg23s-sbc.dts12
-rw-r--r--dts/src/arm/r8a77470.dtsi168
-rw-r--r--dts/src/arm/r8a7778-bockw.dts2
-rw-r--r--dts/src/arm/r8a7778.dtsi2
-rw-r--r--dts/src/arm/r8a7779-marzen.dts2
-rw-r--r--dts/src/arm/r8a7779.dtsi4
-rw-r--r--dts/src/arm/r8a7790-stout.dts4
-rw-r--r--dts/src/arm/r8a7790.dtsi6
-rw-r--r--dts/src/arm/r8a7791.dtsi6
-rw-r--r--dts/src/arm/r8a7792.dtsi3
-rw-r--r--dts/src/arm/r8a7793-gose.dts16
-rw-r--r--dts/src/arm/r8a7793.dtsi2
-rw-r--r--dts/src/arm/r8a7794-silk.dts25
-rw-r--r--dts/src/arm/r8a7794.dtsi3
-rw-r--r--dts/src/arm/r9a06g032.dtsi88
-rw-r--r--dts/src/arm/rk3036.dtsi2
-rw-r--r--dts/src/arm/rk3188-radxarock.dts8
-rw-r--r--dts/src/arm/rk3188.dtsi82
-rw-r--r--dts/src/arm/rk3288-tinker-s.dts26
-rw-r--r--dts/src/arm/rk3288-tinker.dts498
-rw-r--r--dts/src/arm/rk3288-tinker.dtsi502
-rw-r--r--dts/src/arm/s5pv210.dtsi2
-rw-r--r--dts/src/arm/sama5d2.dtsi123
-rw-r--r--dts/src/arm/sama5d4.dtsi8
-rw-r--r--dts/src/arm/socfpga.dtsi22
-rw-r--r--dts/src/arm/socfpga_arria10.dtsi32
-rw-r--r--dts/src/arm/socfpga_cyclone5_de0_nano_soc.dts (renamed from dts/src/arm/socfpga_cyclone5_de0_sockit.dts)2
-rw-r--r--dts/src/arm/socfpga_cyclone5_socrates.dts7
-rw-r--r--dts/src/arm/socfpga_cyclone5_vining_fpga.dts3
-rw-r--r--dts/src/arm/ste-dbx5x0.dtsi80
-rw-r--r--dts/src/arm/ste-href-family-pinctrl.dtsi8
-rw-r--r--dts/src/arm/ste-href.dtsi1
-rw-r--r--dts/src/arm/ste-hrefprev60.dtsi2
-rw-r--r--dts/src/arm/ste-snowball.dts3
-rw-r--r--dts/src/arm/ste-u300.dts2
-rw-r--r--dts/src/arm/stih410-b2260.dts5
-rw-r--r--dts/src/arm/stihxxx-b2120.dtsi11
-rw-r--r--dts/src/arm/stm32429i-eval.dts3
-rw-r--r--dts/src/arm/stm32f429.dtsi2
-rw-r--r--dts/src/arm/stm32f469-disco.dts3
-rw-r--r--dts/src/arm/stm32f746-disco.dts3
-rw-r--r--dts/src/arm/stm32f769-disco.dts3
-rw-r--r--dts/src/arm/stm32h743.dtsi2
-rw-r--r--dts/src/arm/stm32mp157c-ev1.dts73
-rw-r--r--dts/src/arm/stm32mp157c.dtsi4
-rw-r--r--dts/src/arm/sun5i-reference-design-tablet.dtsi3
-rw-r--r--dts/src/arm/sun5i.dtsi26
-rw-r--r--dts/src/arm/sun7i-a20.dtsi26
-rw-r--r--dts/src/arm/sun8i-a33.dtsi26
-rw-r--r--dts/src/arm/sun8i-a83t-bananapi-m3.dts5
-rw-r--r--dts/src/arm/sun8i-a83t.dtsi18
-rw-r--r--dts/src/arm/sun8i-h3-bananapi-m2-plus-v1.2.dts13
-rw-r--r--dts/src/arm/sun8i-h3-bananapi-m2-plus.dts190
-rw-r--r--dts/src/arm/sun8i-h3-orangepi-zero-plus2.dts140
-rw-r--r--dts/src/arm/sun8i-h3.dtsi25
-rw-r--r--dts/src/arm/sun8i-r40-bananapi-m2-ultra.dts21
-rw-r--r--dts/src/arm/sun8i-r40.dtsi13
-rw-r--r--dts/src/arm/sun8i-reference-design-tablet.dtsi3
-rw-r--r--dts/src/arm/sun8i-v40-bananapi-m2-berry.dts2
-rw-r--r--dts/src/arm/sun9i-a80.dtsi2
-rw-r--r--dts/src/arm/sunxi-bananapi-m2-plus-v1.2.dtsi31
-rw-r--r--dts/src/arm/sunxi-bananapi-m2-plus.dtsi231
-rw-r--r--dts/src/arm/sunxi-h3-h5.dtsi2
-rw-r--r--dts/src/arm/tegra124-apalis-eval.dts40
-rw-r--r--dts/src/arm/tegra124-apalis-v1.2-eval.dts43
-rw-r--r--dts/src/arm/tegra124-apalis-v1.2.dtsi452
-rw-r--r--dts/src/arm/tegra124-apalis.dtsi451
-rw-r--r--dts/src/arm/tegra20-colibri-eval-v3.dts262
-rw-r--r--dts/src/arm/tegra20-colibri-iris.dts200
-rw-r--r--dts/src/arm/tegra20-colibri.dtsi657
-rw-r--r--dts/src/arm/tegra20-paz00.dts12
-rw-r--r--dts/src/arm/tegra20.dtsi28
-rw-r--r--dts/src/arm/tegra30-apalis-eval.dts148
-rw-r--r--dts/src/arm/tegra30-apalis-v1.1-eval.dts266
-rw-r--r--dts/src/arm/tegra30-apalis-v1.1.dtsi1189
-rw-r--r--dts/src/arm/tegra30-apalis.dtsi705
-rw-r--r--dts/src/arm/tegra30-colibri-eval-v3.dts130
-rw-r--r--dts/src/arm/tegra30-colibri.dtsi780
-rw-r--r--dts/src/arm/tegra30.dtsi10
-rw-r--r--dts/src/arm/uniphier-ld4-ref.dts4
-rw-r--r--dts/src/arm/uniphier-ld4.dtsi48
-rw-r--r--dts/src/arm/uniphier-ld6b-ref.dts12
-rw-r--r--dts/src/arm/uniphier-pinctrl.dtsi25
-rw-r--r--dts/src/arm/uniphier-pro4-ace.dts12
-rw-r--r--dts/src/arm/uniphier-pro4-ref.dts12
-rw-r--r--dts/src/arm/uniphier-pro4-sanji.dts12
-rw-r--r--dts/src/arm/uniphier-pro4.dtsi189
-rw-r--r--dts/src/arm/uniphier-pro5.dtsi59
-rw-r--r--dts/src/arm/uniphier-pxs2-gentil.dts12
-rw-r--r--dts/src/arm/uniphier-pxs2-vodka.dts8
-rw-r--r--dts/src/arm/uniphier-pxs2.dtsi239
-rw-r--r--dts/src/arm/uniphier-sld8-ref.dts4
-rw-r--r--dts/src/arm/uniphier-sld8.dtsi48
-rw-r--r--dts/src/arm/versatile-ab.dts2
-rw-r--r--dts/src/arm/vf500.dtsi43
-rw-r--r--dts/src/arm/vf610-twr.dts43
-rw-r--r--dts/src/arm/vf610-zii-cfu1.dts30
-rw-r--r--dts/src/arm/vf610-zii-dev-rev-c.dts44
-rw-r--r--dts/src/arm/vf610.dtsi44
-rw-r--r--dts/src/arm/vfxxx.dtsi55
-rw-r--r--dts/src/arm/zynq-zc702.dts12
-rw-r--r--dts/src/arm/zynq-zc770-xm010.dts2
-rw-r--r--dts/src/arm/zynq-zc770-xm013.dts2
-rw-r--r--dts/src/arm64/actions/s700-cubieboard7.dts7
-rw-r--r--dts/src/arm64/actions/s700.dtsi21
-rw-r--r--dts/src/arm64/actions/s900-bubblegum-96.dts224
-rw-r--r--dts/src/arm64/actions/s900.dtsi118
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-amarula-relic.dts2
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts30
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-nanopi-a64.dts85
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-olinuxino.dts99
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-orangepi-win.dts175
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pine64-lts.dts13
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pine64.dts28
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinebook.dts9
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts28
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-teres-i.dts2
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64.dtsi193
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts11
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5-bananapi-m2-plus.dts11
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5.dtsi43
-rw-r--r--dts/src/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts150
-rw-r--r--dts/src/arm64/allwinner/sun50i-h6.dtsi23
-rw-r--r--dts/src/arm64/altera/socfpga_stratix10.dtsi45
-rw-r--r--dts/src/arm64/altera/socfpga_stratix10_socdk.dts7
-rw-r--r--dts/src/arm64/amd/amd-seattle-soc.dtsi4
-rw-r--r--dts/src/arm64/amlogic/meson-axg-s400.dts370
-rw-r--r--dts/src/arm64/amlogic/meson-axg.dtsi1575
-rw-r--r--dts/src/arm64/amlogic/meson-g12a-u200.dts29
-rw-r--r--dts/src/arm64/amlogic/meson-g12a.dtsi172
-rw-r--r--dts/src/arm64/amlogic/meson-gx.dtsi19
-rw-r--r--dts/src/arm64/amlogic/meson-gxbb.dtsi2
-rw-r--r--dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts2
-rw-r--r--dts/src/arm64/amlogic/meson-gxl.dtsi2
-rw-r--r--dts/src/arm64/arm/juno-base.dtsi162
-rw-r--r--dts/src/arm64/arm/juno-cs-r1r2.dtsi52
-rw-r--r--dts/src/arm64/arm/juno.dts13
-rw-r--r--dts/src/arm64/broadcom/bcm2837-rpi-cm3-io3.dts2
-rw-r--r--dts/src/arm64/broadcom/northstar2/ns2.dtsi4
-rw-r--r--dts/src/arm64/broadcom/stingray/bcm958742-base.dtsi2
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray.dtsi4
-rw-r--r--dts/src/arm64/exynos/exynos5433-tm2-common.dtsi18
-rw-r--r--dts/src/arm64/freescale/fsl-ls1012a.dtsi2
-rw-r--r--dts/src/arm64/freescale/fsl-ls1043a-qds.dts2
-rw-r--r--dts/src/arm64/freescale/fsl-ls1043a-rdb.dts2
-rw-r--r--dts/src/arm64/freescale/fsl-ls1043a.dtsi8
-rw-r--r--dts/src/arm64/freescale/fsl-ls1046a-qds.dts2
-rw-r--r--dts/src/arm64/freescale/fsl-ls1046a-rdb.dts4
-rw-r--r--dts/src/arm64/freescale/fsl-ls1046a.dtsi6
-rw-r--r--dts/src/arm64/freescale/fsl-ls208xa.dtsi27
-rw-r--r--dts/src/arm64/hisilicon/hi3670-hikey970.dts35
-rw-r--r--dts/src/arm64/hisilicon/hi3670.dtsi162
-rw-r--r--dts/src/arm64/hisilicon/hi6220-coresight.dtsi181
-rw-r--r--dts/src/arm64/hisilicon/hi6220.dtsi7
-rw-r--r--dts/src/arm64/lg/lg1312.dtsi4
-rw-r--r--dts/src/arm64/lg/lg1313.dtsi4
-rw-r--r--dts/src/arm64/marvell/armada-372x.dtsi2
-rw-r--r--dts/src/arm64/marvell/armada-37xx.dtsi15
-rw-r--r--dts/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts441
-rw-r--r--dts/src/arm64/marvell/armada-ap806-dual.dtsi4
-rw-r--r--dts/src/arm64/marvell/armada-ap806-quad.dtsi12
-rw-r--r--dts/src/arm64/marvell/armada-ap806.dtsi110
-rw-r--r--dts/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi16
-rw-r--r--dts/src/arm64/marvell/armada-common.dtsi1
-rw-r--r--dts/src/arm64/marvell/armada-cp110.dtsi189
-rw-r--r--dts/src/arm64/mediatek/mt2712e.dtsi11
-rw-r--r--dts/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts530
-rw-r--r--dts/src/arm64/mediatek/mt7622-rfb1.dts196
-rw-r--r--dts/src/arm64/mediatek/mt7622.dtsi62
-rw-r--r--dts/src/arm64/nvidia/tegra186.dtsi76
-rw-r--r--dts/src/arm64/nvidia/tegra194.dtsi16
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2180.dtsi12
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2597.dtsi1
-rw-r--r--dts/src/arm64/nvidia/tegra210.dtsi57
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc.dtsi14
-rw-r--r--dts/src/arm64/qcom/apq8096-db820c.dts2
-rw-r--r--dts/src/arm64/qcom/apq8096-db820c.dtsi14
-rw-r--r--dts/src/arm64/qcom/msm8916.dtsi98
-rw-r--r--dts/src/arm64/qcom/msm8996.dtsi15
-rw-r--r--dts/src/arm64/qcom/msm8998-mtp.dts13
-rw-r--r--dts/src/arm64/qcom/msm8998-mtp.dtsi243
-rw-r--r--dts/src/arm64/qcom/msm8998.dtsi690
-rw-r--r--dts/src/arm64/qcom/pm8916.dtsi18
-rw-r--r--dts/src/arm64/qcom/pm8994.dtsi18
-rw-r--r--dts/src/arm64/qcom/pm8998.dtsi75
-rw-r--r--dts/src/arm64/qcom/pmi8998.dtsi40
-rw-r--r--dts/src/arm64/qcom/sdm845-mtp.dts382
-rw-r--r--dts/src/arm64/qcom/sdm845.dtsi300
-rw-r--r--dts/src/arm64/renesas/r8a774a1.dtsi1663
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts3
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1.dtsi18
-rw-r--r--dts/src/arm64/renesas/r8a7795-h3ulcb.dts3
-rw-r--r--dts/src/arm64/renesas/r8a7795-salvator-x.dts3
-rw-r--r--dts/src/arm64/renesas/r8a7795-salvator-xs.dts17
-rw-r--r--dts/src/arm64/renesas/r8a7795.dtsi137
-rw-r--r--dts/src/arm64/renesas/r8a7796-m3ulcb.dts3
-rw-r--r--dts/src/arm64/renesas/r8a7796-salvator-x.dts3
-rw-r--r--dts/src/arm64/renesas/r8a7796.dtsi103
-rw-r--r--dts/src/arm64/renesas/r8a77965-m3nulcb-kf.dts16
-rw-r--r--dts/src/arm64/renesas/r8a77965-m3nulcb.dts33
-rw-r--r--dts/src/arm64/renesas/r8a77965-salvator-xs.dts14
-rw-r--r--dts/src/arm64/renesas/r8a77965.dtsi417
-rw-r--r--dts/src/arm64/renesas/r8a77970-v3msk.dts26
-rw-r--r--dts/src/arm64/renesas/r8a77970.dtsi116
-rw-r--r--dts/src/arm64/renesas/r8a77980-condor.dts123
-rw-r--r--dts/src/arm64/renesas/r8a77980-v3hsk.dts134
-rw-r--r--dts/src/arm64/renesas/r8a77980.dtsi677
-rw-r--r--dts/src/arm64/renesas/r8a77990-ebisu.dts272
-rw-r--r--dts/src/arm64/renesas/r8a77990.dtsi681
-rw-r--r--dts/src/arm64/renesas/r8a77995-draak.dts362
-rw-r--r--dts/src/arm64/renesas/r8a77995.dtsi82
-rw-r--r--dts/src/arm64/renesas/salvator-common.dtsi9
-rw-r--r--dts/src/arm64/renesas/ulcb-kf.dtsi2
-rw-r--r--dts/src/arm64/renesas/ulcb.dtsi4
-rw-r--r--dts/src/arm64/rockchip/px30-evb.dts235
-rw-r--r--dts/src/arm64/rockchip/px30.dtsi2047
-rw-r--r--dts/src/arm64/rockchip/rk3328-roc-cc.dts30
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock64.dts61
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi74
-rw-r--r--dts/src/arm64/rockchip/rk3399-ficus.dts524
-rw-r--r--dts/src/arm64/rockchip/rk3399-firefly.dts36
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma-haikou.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3399-roc-pc.dts680
-rw-r--r--dts/src/arm64/rockchip/rk3399-rock960.dts52
-rw-r--r--dts/src/arm64/rockchip/rk3399-rock960.dtsi542
-rw-r--r--dts/src/arm64/rockchip/rk3399-rockpro64.dts692
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire.dtsi68
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi32
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11.dtsi52
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-global.dts4
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-ref.dts4
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20.dtsi255
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3-ref.dts12
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3.dtsi283
-rw-r--r--dts/src/arm64/synaptics/as370.dtsi173
-rw-r--r--dts/src/arm64/ti/k3-am65-main.dtsi51
-rw-r--r--dts/src/arm64/ti/k3-am65-mcu.dtsi18
-rw-r--r--dts/src/arm64/ti/k3-am65-wakeup.dtsi46
-rw-r--r--dts/src/arm64/ti/k3-am65.dtsi54
-rw-r--r--dts/src/arm64/ti/k3-am654-base-board.dts5
-rw-r--r--dts/src/mips/ingenic/jz4740.dtsi15
-rw-r--r--dts/src/mips/ingenic/jz4770.dtsi30
-rw-r--r--dts/src/mips/ingenic/jz4780.dtsi3
-rw-r--r--dts/src/mips/lantiq/danube.dtsi42
-rw-r--r--dts/src/mips/lantiq/easy50712.dts14
-rw-r--r--dts/src/mips/mscc/ocelot.dtsi38
-rw-r--r--dts/src/mips/mscc/ocelot_pcb120.dts107
-rw-r--r--dts/src/mips/mscc/ocelot_pcb123.dts6
-rw-r--r--dts/src/powerpc/fsl/t2080rdb.dts4
-rw-r--r--dts/src/powerpc/mpc885ads.dts13
-rw-r--r--fs/devfs.c27
-rw-r--r--fs/fs.c37
-rw-r--r--images/Makefile.at914
-rw-r--r--images/Makefile.imx10
-rw-r--r--include/driver.h4
-rw-r--r--include/gpio.h6
-rw-r--r--include/linux/crc8.h101
-rw-r--r--include/linux/ctype.h9
-rw-r--r--include/linux/dcache.h3
-rw-r--r--include/linux/kernel.h95
-rw-r--r--include/linux/string.h2
-rw-r--r--lib/Kconfig7
-rw-r--r--lib/Makefile2
-rw-r--r--lib/crc8.c82
-rw-r--r--lib/kstrtox.c366
-rw-r--r--lib/kstrtox.h9
-rw-r--r--lib/libfile.c6
-rw-r--r--net/dhcp.c3
-rw-r--r--scripts/imx/imx-image.c6
-rw-r--r--scripts/imx/imx-usb-loader.c4
-rw-r--r--scripts/imx/imx.c2
-rw-r--r--scripts/kconfig/confdata.c2
966 files changed, 40299 insertions, 9662 deletions
diff --git a/Makefile b/Makefile
index db474af..10e1b74 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
VERSION = 2018
-PATCHLEVEL = 10
+PATCHLEVEL = 11
SUBLEVEL = 0
EXTRAVERSION =
NAME = None
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index c737cf3..3bf176b 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_MACH_GE863) += telit-evk-pro3/
obj-$(CONFIG_MACH_GK802) += gk802/
obj-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += globalscale-guruplug/
obj-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += globalscale-mirabox/
+obj-$(CONFIG_MACH_GRINN_LITEBOARD) += grinn-liteboard/
obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/
obj-$(CONFIG_MACH_GUF_SANTARO) += guf-santaro/
obj-$(CONFIG_MACH_GUF_VINCELL) += guf-vincell/
@@ -110,6 +111,7 @@ obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/
obj-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += freescale-mx6sx-sabresdb/
obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/
obj-$(CONFIG_MACH_SAMA5D3_XPLAINED) += sama5d3_xplained/
+obj-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += microchip-ksz9477-evb/
obj-$(CONFIG_MACH_SAMA5D4_XPLAINED) += sama5d4_xplained/
obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/
obj-$(CONFIG_MACH_SCB9328) += scb9328/
diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c
index 8474173..07daaf4 100644
--- a/arch/arm/boards/animeo_ip/init.c
+++ b/arch/arm/boards/animeo_ip/init.c
@@ -24,7 +24,6 @@
#include <mach/at91sam9_smc.h>
#include <gpio.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <local_mac_address.h>
@@ -231,30 +230,12 @@ static void animeo_ip_power_control(void)
static void animeo_ip_phy_reset(void)
{
- unsigned long rstc;
int i;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
for (i = AT91_PIN_PA12; i <= AT91_PIN_PA29; i++)
at91_set_gpio_input(i, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
- ;
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
#define MACB_SA1B 0x0098
@@ -345,7 +326,7 @@ static void animeo_ip_shutdown(void)
* so linux can detect that we only enable the uart2
* and use it for decompress
*/
- animeo_ip_shutdown_uart(IOMEM(AT91_DBGU + AT91_BASE_SYS));
+ animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_DBGU));
animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_US0));
animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_US1));
}
diff --git a/arch/arm/boards/at91rm9200ek/config.h b/arch/arm/boards/at91rm9200ek/config.h
index 070c9a1..5f4f6fe 100644
--- a/arch/arm/boards/at91rm9200ek/config.h
+++ b/arch/arm/boards/at91rm9200ek/config.h
@@ -30,30 +30,30 @@
/* flash */
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL \
- (AT91_SMC_NWS_(4) | /* Number of Wait States */ \
- AT91_SMC_WSEN | /* Wait State Enable */ \
- AT91_SMC_TDF_(2) | /* Data Float Time */ \
- AT91_SMC_BAT | /* Byte Access Type */ \
- AT91_SMC_DBW_16) /* Data Bus Width */
+ (AT91RM9200_SMC_NWS_(4) | /* Number of Wait States */ \
+ AT91RM9200_SMC_WSEN | /* Wait State Enable */ \
+ AT91RM9200_SMC_TDF_(2) | /* Data Float Time */ \
+ AT91RM9200_SMC_BAT | /* Byte Access Type */ \
+ AT91RM9200_SMC_DBW_16) /* Data Bus Width */
/* sdram */
#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL \
- (AT91_EBI_CS0A_SMC | \
- AT91_EBI_CS1A_SDRAMC | \
- AT91_EBI_CS3A_SMC | \
- AT91_EBI_CS4A_SMC) \
+ (AT91RM9200_EBI_CS0A_SMC | \
+ AT91RM9200_EBI_CS1A_SDRAMC | \
+ AT91RM9200_EBI_CS3A_SMC | \
+ AT91RM9200_EBI_CS4A_SMC) \
/* SDRAM */
/* SDRAMC_MR Mode register */
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_12 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
+ (AT91RM9200_SDRAMC_NC_9 | \
+ AT91RM9200_SDRAMC_NR_12 | \
+ AT91RM9200_SDRAMC_NB_4 | \
+ AT91RM9200_SDRAMC_CAS_2 | \
(1 << 8) | /* Write Recovery Delay */ \
(12 << 12) | /* Row Cycle Delay */ \
(8 << 16) | /* Row Precharge Delay */ \
diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c
index 7626786..2d93185 100644
--- a/arch/arm/boards/at91rm9200ek/init.c
+++ b/arch/arm/boards/at91rm9200ek/init.c
@@ -31,7 +31,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <spi/spi.h>
static struct macb_platform_data ether_pdata = {
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c
index a85a22e..a5c9058 100644
--- a/arch/arm/boards/at91rm9200ek/lowlevel.c
+++ b/arch/arm/boards/at91rm9200ek/lowlevel.c
@@ -18,41 +18,43 @@
void static inline access_sdram(void)
{
- writel(0x00000000, AT91_SDRAM_BASE);
+ writel(0x00000000, AT91_CHIPSELECT_1);
}
void __naked __bare_init barebox_arm_reset_vector(void)
{
u32 r;
int i;
+ void __iomem *mc = IOMEM(AT91RM9200_BASE_MC);
+ void __iomem *pmc = IOMEM(AT91RM9200_BASE_PMC);
arm_cpu_lowlevel_init();
/*
* PMC Check if the PLL is already initialized
*/
- r = at91_pmc_read(AT91_PMC_MCKR);
+ r = __raw_readl(pmc + AT91_PMC_MCKR);
if (r & AT91_PMC_CSS)
goto end;
/*
* Enable the Main Oscillator
*/
- at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
+ __raw_writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = __raw_readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/*
* EBI_CFGR
*/
- at91_sys_write(AT91_EBI_CFGR, CONFIG_SYS_EBI_CFGR_VAL);
+ __raw_writel(CONFIG_SYS_EBI_CFGR_VAL, mc + AT91RM9200_EBI_CFGR);
/*
* SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
*/
- at91_sys_write(AT91_SMC_CSR(0), CONFIG_SYS_SMC_CSR0_VAL);
+ __raw_writel(CONFIG_SYS_SMC_CSR0_VAL, mc + AT91RM9200_SMC_CSR(0));
/*
* Init Clocks
@@ -61,24 +63,24 @@ void __naked __bare_init barebox_arm_reset_vector(void)
/*
* PLLAR: x MHz for PCK
*/
- at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
+ __raw_writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = __raw_readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/*
* PCK/x = MCK Master Clock from SLOW
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1);
+ __raw_writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR);
/*
* PCK/x = MCK Master Clock from PLLA
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2);
+ __raw_writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = __raw_readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MCKRDY));
/*
@@ -86,38 +88,38 @@ void __naked __bare_init barebox_arm_reset_vector(void)
*/
/* PIOC_ASR: Configure PIOC as peripheral (D16/D31) */
- __raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91_BASE_PIOC + PIO_ASR);
+ __raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91RM9200_BASE_PIOC + PIO_ASR);
/* PIOC_BSR */
- __raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91_BASE_PIOC + PIO_BSR);
+ __raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91RM9200_BASE_PIOC + PIO_BSR);
/* PIOC_PDR */
- __raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91_BASE_PIOC + PIO_PDR);
+ __raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR);
/* EBI_CSA : CS1=SDRAM */
- at91_sys_write(AT91_EBI_CSA, CONFIG_SYS_EBI_CSA_VAL);
+ __raw_writel(CONFIG_SYS_EBI_CSA_VAL, mc + AT91RM9200_EBI_CSA);
/* SDRC_CR */
- at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);
+ __raw_writel(CONFIG_SYS_SDRC_CR_VAL, mc + AT91RM9200_SDRAMC_CR);
/* SDRC_MR : Precharge All */
- at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
+ __raw_writel(AT91RM9200_SDRAMC_MODE_PRECHARGE, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM */
access_sdram();
/* SDRC_MR : refresh */
- at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
+ __raw_writel(AT91RM9200_SDRAMC_MODE_REFRESH, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM 8 times */
for (i = 0; i < 8; i++)
access_sdram();
/* SDRC_MR : Load Mode Register */
- at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
+ __raw_writel(AT91RM9200_SDRAMC_MODE_LMR, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM */
access_sdram();
/* SDRC_TR : Write refresh rate */
- at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL);
+ __raw_writel(CONFIG_SYS_SDRC_TR_VAL, mc + AT91RM9200_SDRAMC_TR);
/* access SDRAM */
access_sdram();
/* SDRC_MR : Normal Mode */
- at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
+ __raw_writel(AT91RM9200_SDRAMC_MODE_NORMAL, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM */
access_sdram();
diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c
index 5a21ac1..037f46a 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -24,7 +24,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_rstc.h>
#include <linux/clk.h>
@@ -125,11 +124,6 @@ static struct macb_platform_data macb_pdata = {
static void at91sam9260ek_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -137,21 +131,7 @@ static void at91sam9260ek_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
- ;
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
/*
diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c
index 58f253b..a469dba 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -32,7 +32,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91sam9_smc.h>
#include <platform_data/eth-dm9000.h>
diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c
index c4e4957..33aa943 100644
--- a/arch/arm/boards/at91sam9261ek/lowlevel_init.c
+++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c
@@ -34,7 +34,7 @@ static void __bare_init at91sam9261ek_board_config(struct at91sam926x_board_cfg
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
+ AT91SAM9261_MATRIX_DBPUC | AT91SAM9261_MATRIX_CS1A_SDRAMC;
cfg->smc_cs = 3;
cfg->smc_mode =
@@ -108,10 +108,10 @@ static void __bare_init at91sam9261ek_init(void)
cfg.pio = IOMEM(AT91SAM9261_BASE_PIOC);
cfg.sdramc = IOMEM(AT91SAM9261_BASE_SDRAMC);
cfg.ebi_pio_is_peripha = false;
- cfg.matrix_csa = AT91_MATRIX_EBICSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
at91sam9261ek_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9261_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
NULL);
diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c
index b71cc55..f7461ce 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -35,7 +35,6 @@
#include <mach/board.h>
#include <mach/iomux.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/at91sam9_smc.h>
static struct atmel_nand_data nand_pdata = {
diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
index 30c1408..f5d68cd 100644
--- a/arch/arm/boards/at91sam9263ek/lowlevel_init.c
+++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
@@ -29,8 +29,8 @@ static void __bare_init at91sam9263ek_board_config(struct at91sam926x_board_cfg
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
- AT91_MATRIX_EBI0_CS1A_SDRAMC;
+ AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 0;
cfg->smc_mode =
@@ -106,10 +106,10 @@ static void __bare_init at91sam9263ek_init(void *fdt)
cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
cfg.ebi_pio_is_peripha = true;
- cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
at91sam9263ek_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9263_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
fdt);
diff --git a/arch/arm/boards/at91sam9263ek/of_init.c b/arch/arm/boards/at91sam9263ek/of_init.c
index b4d216f..259287c 100644
--- a/arch/arm/boards/at91sam9263ek/of_init.c
+++ b/arch/arm/boards/at91sam9263ek/of_init.c
@@ -16,13 +16,13 @@
#include <envfs.h>
#include <init.h>
#include <gpio.h>
+#include <io.h>
#include <mach/at91sam9263_matrix.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91_rtt.h>
#include <mach/hardware.h>
#include <mach/iomux.h>
-#include <mach/io.h>
static int add_smc_devices(void)
{
@@ -66,9 +66,9 @@ static int at91sam9263_smc_init(void)
else
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
- csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
- csa |= AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
- at91_sys_write(AT91_MATRIX_EBI0CSA, csa);
+ csa = readl(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
+ csa |= AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
/* configure chip-select 3 (NAND) */
sam9_smc_configure(0, 3, &ek_nand_smc_config);
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c
index ee69263..2660104 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -36,7 +36,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <gpio_keys.h>
#include <readkey.h>
diff --git a/arch/arm/boards/at91sam9m10ihd/init.c b/arch/arm/boards/at91sam9m10ihd/init.c
index de601d5..5008e0f 100644
--- a/arch/arm/boards/at91sam9m10ihd/init.c
+++ b/arch/arm/boards/at91sam9m10ihd/init.c
@@ -21,7 +21,6 @@
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91sam9_smc.h>
#include <input/qt1070.h>
diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c
index bc3fb8e..72c6ff8 100644
--- a/arch/arm/boards/at91sam9n12ek/init.c
+++ b/arch/arm/boards/at91sam9n12ek/init.c
@@ -32,7 +32,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c
index 649545e..65493eb 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -32,7 +32,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
@@ -70,16 +69,16 @@ static int ek_add_device_smc(void)
if (!of_machine_is_compatible("atmel,at91sam9x5ek"))
return 0;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ csa = readl(AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
/* Enable CS3 */
- csa |= AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH;
+ csa |= AT91SAM9X5_MATRIX_EBI_CS3A_SMC_NANDFLASH;
/* NAND flash on D16 */
- csa |= AT91_MATRIX_NFD0_ON_D16;
+ csa |= AT91SAM9X5_MATRIX_NFD0_ON_D16;
/* Configure IO drive */
- csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
- at91_sys_write(AT91_MATRIX_EBICSA, csa);
+ csa &= ~AT91SAM9X5_MATRIX_EBI_EBI_IOSR_NORMAL;
+ writel(csa, AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
add_generic_device("at91sam9-smc",
DEVICE_ID_SINGLE, NULL,
@@ -96,9 +95,9 @@ static int ek_add_device_smc(void)
sam9_smc_configure(0, 3, &cm_nand_smc_config);
if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT)) {
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- csa |= AT91_MATRIX_EBI_VDDIOMSEL_1_8V;
- at91_sys_write(AT91_MATRIX_EBICSA, csa);
+ csa = readl(AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
+ csa |= AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_1_8V;
+ writel(csa, AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
}
return 0;
diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c
index 321c383..0d0b5e2 100644
--- a/arch/arm/boards/dss11/init.c
+++ b/arch/arm/boards/dss11/init.c
@@ -29,7 +29,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_rstc.h>
#include <linux/clk.h>
@@ -80,11 +79,6 @@ static struct macb_platform_data macb_pdata = {
static void dss11_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -92,22 +86,7 @@ static void dss11_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
static struct atmel_mci_platform_data dss11_mci_data = {
diff --git a/arch/arm/boards/grinn-liteboard/Makefile b/arch/arm/boards/grinn-liteboard/Makefile
new file mode 100644
index 0000000..01c7a25
--- /dev/null
+++ b/arch/arm/boards/grinn-liteboard/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/grinn-liteboard/board.c b/arch/arm/boards/grinn-liteboard/board.c
new file mode 100644
index 0000000..8e5a91e
--- /dev/null
+++ b/arch/arm/boards/grinn-liteboard/board.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2018 Grinn
+ *
+ * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "liteboard: " fmt
+
+#include <bootsource.h>
+#include <common.h>
+#include <envfs.h>
+#include <init.h>
+#include <mach/bbu.h>
+#include <mach/imx6.h>
+#include <malloc.h>
+#include <mfd/imx6q-iomuxc-gpr.h>
+#include <of.h>
+
+static void bbu_register_handler_sd(bool is_boot_source)
+{
+ imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc0.barebox",
+ is_boot_source ? BBU_HANDLER_FLAG_DEFAULT : 0);
+}
+
+static void bbu_register_handler_emmc(bool is_boot_source)
+{
+ int emmc_boot_flag = 0, emmc_flag = 0;
+ const char *bootpart;
+ struct device_d *dev;
+ int ret;
+
+ if (!is_boot_source)
+ goto bbu_register;
+
+ dev = get_device_by_name("mmc1");
+ if (!dev) {
+ pr_warn("Failed to get eMMC device\n");
+ goto bbu_register;
+ }
+
+ ret = device_detect(dev);
+ if (ret) {
+ pr_warn("Failed to probe eMMC\n");
+ goto bbu_register;
+ }
+
+ bootpart = dev_get_param(dev, "boot");
+ if (!bootpart) {
+ pr_warn("Failed to get eMMC boot configuration\n");
+ goto bbu_register;
+ }
+
+ if (!strncmp(bootpart, "boot", 4))
+ emmc_boot_flag |= BBU_HANDLER_FLAG_DEFAULT;
+ else
+ emmc_flag |= BBU_HANDLER_FLAG_DEFAULT;
+
+bbu_register:
+ imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc1.barebox",
+ emmc_flag);
+ imx6_bbu_internal_mmcboot_register_handler("emmc-boot", "mmc1",
+ emmc_boot_flag);
+}
+
+static const struct {
+ const char *name;
+ const char *env;
+ void (*bbu_register_handler)(bool);
+} boot_sources[] = {
+ {"SD", "/chosen/environment-sd", bbu_register_handler_sd},
+ {"eMMC", "/chosen/environment-emmc", bbu_register_handler_emmc},
+};
+
+static int liteboard_devices_init(void)
+{
+ int boot_source_idx = 0;
+ int ret;
+ int i;
+
+ if (!of_machine_is_compatible("grinn,imx6ul-liteboard"))
+ return 0;
+
+ barebox_set_hostname("liteboard");
+
+ if (bootsource_get() == BOOTSOURCE_MMC) {
+ int mmc_idx = bootsource_get_instance();
+
+ if (0 <= mmc_idx && mmc_idx < ARRAY_SIZE(boot_sources))
+ boot_source_idx = mmc_idx;
+ }
+
+ ret = of_device_enable_path(boot_sources[boot_source_idx].env);
+ if (ret < 0)
+ pr_warn("Failed to enable environment partition '%s' (%d)\n",
+ boot_sources[boot_source_idx].env, ret);
+
+ pr_notice("Using environment in %s\n",
+ boot_sources[boot_source_idx].name);
+
+ for (i = 0; i < ARRAY_SIZE(boot_sources); i++)
+ boot_sources[i].bbu_register_handler(boot_source_idx == i);
+
+ return 0;
+}
+device_initcall(liteboard_devices_init);
diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg
new file mode 100644
index 0000000..1b980c7
--- /dev/null
+++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg
@@ -0,0 +1,6 @@
+
+#define SETUP_MDASP_MDCTL \
+ wm 32 0x021B0040 0x00000047; \
+ wm 32 0x021B0000 0x83180000
+
+#include "flash-header-liteboard.h"
diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg
new file mode 100644
index 0000000..c93a2cc
--- /dev/null
+++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg
@@ -0,0 +1,6 @@
+
+#define SETUP_MDASP_MDCTL \
+ wm 32 0x021B0040 0x0000004F; \
+ wm 32 0x021B0000 0x84180000
+
+#include "flash-header-liteboard.h"
diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h
new file mode 100644
index 0000000..60a39f5
--- /dev/null
+++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h
@@ -0,0 +1,68 @@
+
+loadaddr 0x80000000
+soc imx6
+dcdofs 0x400
+
+wm 32 0x020c4068 0xffffffff
+wm 32 0x020c406c 0xffffffff
+wm 32 0x020c4070 0xffffffff
+wm 32 0x020c4074 0xffffffff
+wm 32 0x020c4078 0xffffffff
+wm 32 0x020c407c 0xffffffff
+wm 32 0x020c4080 0xffffffff
+
+wm 32 0x020E04B4 0x000C0000
+wm 32 0x020E04AC 0x00000000
+wm 32 0x020E027C 0x00000030
+wm 32 0x020E0250 0x00000030
+wm 32 0x020E024C 0x00000030
+wm 32 0x020E0490 0x00000030
+wm 32 0x020E0288 0x00000030
+wm 32 0x020E0270 0x00000000
+wm 32 0x020E0260 0x00000030
+wm 32 0x020E0264 0x00000030
+wm 32 0x020E04A0 0x00000030
+wm 32 0x020E0494 0x00020000
+wm 32 0x020E0280 0x00000030
+wm 32 0x020E0284 0x00000030
+wm 32 0x020E04B0 0x00020000
+wm 32 0x020E0498 0x00000030
+wm 32 0x020E04A4 0x00000030
+wm 32 0x020E0244 0x00000030
+wm 32 0x020E0248 0x00000030
+wm 32 0x021B001C 0x00008000
+wm 32 0x021B0800 0xA1390003
+wm 32 0x021B080C 0x00000000
+wm 32 0x021B083C 0x41480148
+wm 32 0x021B0848 0x40403E42
+wm 32 0x021B0850 0x40405852
+wm 32 0x021B081C 0x33333333
+wm 32 0x021B0820 0x33333333
+wm 32 0x021B082C 0xf3333333
+wm 32 0x021B0830 0xf3333333
+wm 32 0x021B08C0 0x00922012
+wm 32 0x021B0858 0x00000F00
+wm 32 0x021B08b8 0x00000800
+wm 32 0x021B0004 0x0002002D
+wm 32 0x021B0008 0x1B333030
+wm 32 0x021B000C 0x676B52F3
+wm 32 0x021B0010 0xB66D0B63
+wm 32 0x021B0014 0x01FF00DB
+wm 32 0x021B0018 0x00211740
+wm 32 0x021B001C 0x00008000
+wm 32 0x021B002C 0x000026D2
+wm 32 0x021B0030 0x006B1023
+
+SETUP_MDASP_MDCTL
+
+wm 32 0x021b0890 0x00400A38
+wm 32 0x021B001C 0x02008032
+wm 32 0x021B001C 0x00008033
+wm 32 0x021B001C 0x00048031
+wm 32 0x021B001C 0x15208030
+wm 32 0x021B001C 0x04008040
+wm 32 0x021B0020 0x00007800
+wm 32 0x021B0818 0x00000227
+wm 32 0x021B0004 0x0002556D
+wm 32 0x021B0404 0x00011006
+wm 32 0x021B001C 0x00000000
diff --git a/arch/arm/boards/grinn-liteboard/lowlevel.c b/arch/arm/boards/grinn-liteboard/lowlevel.c
new file mode 100644
index 0000000..331ccc2
--- /dev/null
+++ b/arch/arm/boards/grinn-liteboard/lowlevel.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2018 Grinn
+ *
+ * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include <debug_ll.h>
+#include <common.h>
+#include <linux/sizes.h>
+#include <io.h>
+#include <image-metadata.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/sections.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <mach/esdctl.h>
+#include <mach/imx6.h>
+
+static inline void setup_uart(void)
+{
+ void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+ void __iomem *uart = IOMEM(MX6_UART1_BASE_ADDR);
+
+ relocate_to_current_adr();
+ setup_c();
+ barrier();
+
+ imx6_ungate_all_peripherals();
+
+ writel(0x0, iomuxbase + 0x84);
+ writel(0x1b0b1, iomuxbase + 0x0310);
+
+ imx6_uart_setup(uart);
+
+ pbl_set_putc(imx_uart_putc, uart);
+
+ putchar('>');
+}
+
+BAREBOX_IMD_TAG_STRING(liteboard_memsize_SZ_256M, IMD_TYPE_PARAMETER,
+ "memsize=256", 0);
+BAREBOX_IMD_TAG_STRING(liteboard_memsize_SZ_512M, IMD_TYPE_PARAMETER,
+ "memsize=512", 0);
+
+extern char __dtb_imx6ul_liteboard_start[];
+
+static void __noreturn start_imx6_liteboard(void)
+{
+ imx6ul_cpu_lowlevel_init();
+
+ arm_setup_stack(0x00910000 - 8);
+
+ arm_early_mmu_cache_invalidate();
+
+ if (IS_ENABLED(CONFIG_PBL_CONSOLE))
+ setup_uart();
+
+ imx6ul_barebox_entry(__dtb_imx6ul_liteboard_start +
+ get_runtime_offset());
+}
+
+#define LITEBOARD_ENTRY(name, memory_size) \
+ ENTRY_FUNCTION(name, r0, r1, r2) \
+ { \
+ IMD_USED(liteboard_memsize_##memory_size); \
+ \
+ start_imx6_liteboard(); \
+ }
+
+
+LITEBOARD_ENTRY(start_imx6ul_liteboard_256mb, SZ_256M);
+LITEBOARD_ENTRY(start_imx6ul_liteboard_512mb, SZ_512M);
diff --git a/arch/arm/boards/haba-knx/init.c b/arch/arm/boards/haba-knx/init.c
index 36f1e8b..55441b6 100644
--- a/arch/arm/boards/haba-knx/init.c
+++ b/arch/arm/boards/haba-knx/init.c
@@ -35,7 +35,6 @@
#include <mach/at91sam9_smc.h>
#include <gpio.h>
#include <led.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
@@ -91,33 +90,12 @@ static struct macb_platform_data macb_pdata = {
static void haba_knx_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
at91_set_gpio_input(AT91_PIN_PA18, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
- ;
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
#define MACB_SA1B 0x0098
diff --git a/arch/arm/boards/microchip-ksz9477-evb/Makefile b/arch/arm/boards/microchip-ksz9477-evb/Makefile
new file mode 100644
index 0000000..b08c4a9
--- /dev/null
+++ b/arch/arm/boards/microchip-ksz9477-evb/Makefile
@@ -0,0 +1 @@
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
new file mode 100644
index 0000000..639958a
--- /dev/null
+++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2018 Ahmad Fatoum, Pengutronix
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+#include <mach/hardware.h>
+
+extern char __dtb_at91_microchip_ksz9477_evb_start[];
+
+ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
+{
+ void *fdt;
+
+ arm_cpu_lowlevel_init();
+
+ arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
+
+ fdt = __dtb_at91_microchip_ksz9477_evb_start + get_runtime_offset();
+
+ barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
+}
diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c
index 764eadb..299d056 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -17,11 +17,12 @@
*
*/
+#include <asm/memory.h>
+#include <bootsource.h>
#include <common.h>
#include <init.h>
-#include <asm/memory.h>
-#include <linux/sizes.h>
#include <linux/phy.h>
+#include <linux/sizes.h>
#include <mach/bbu.h>
#include <envfs.h>
@@ -45,25 +46,27 @@ static int ar8031_phy_fixup(struct phy_device *phydev)
return 0;
}
-static int imx8mq_evk_mem_init(void)
-{
- if (!of_machine_is_compatible("fsl,imx8mq-evk"))
- return 0;
-
- request_sdram_region("ATF", 0x40000000, SZ_128K);
-
- return 0;
-}
-mem_initcall(imx8mq_evk_mem_init);
-
static int nxp_imx8mq_evk_init(void)
{
+ int flags;
+
if (!of_machine_is_compatible("fsl,imx8mq-evk"))
return 0;
barebox_set_hostname("imx8mq-evk");
- imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0", 0);
+ flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0;
+ imx8mq_bbu_internal_mmc_register_handler("eMMC",
+ "/dev/mmc0.barebox", flags);
+
+ flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0;
+ imx8mq_bbu_internal_mmc_register_handler("SD",
+ "/dev/mmc1.barebox", flags);
+
+ if (bootsource_get_instance() == 0)
+ of_device_enable_path("/chosen/environment-emmc");
+ else
+ of_device_enable_path("/chosen/environment-sd");
phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
ar8031_phy_fixup);
diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
index b0377d0..33c2a54 100644
--- a/arch/arm/boards/pm9261/init.c
+++ b/arch/arm/boards/pm9261/init.c
@@ -34,7 +34,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <platform_data/eth-dm9000.h>
#include <linux/w1-gpio.h>
diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c
index a4cb8af..0ab34b0 100644
--- a/arch/arm/boards/pm9261/lowlevel_init.c
+++ b/arch/arm/boards/pm9261/lowlevel_init.c
@@ -7,7 +7,7 @@
#include <asm/barebox-arm.h>
#include <mach/at91sam926x_board_init.h>
-#include <mach/at91sam9_matrix.h>
+#include <mach/at91sam9261_matrix.h>
#define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162
@@ -28,7 +28,7 @@ static void __bare_init pm9261_board_config(struct at91sam926x_board_cfg *cfg)
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
+ AT91SAM9261_MATRIX_DBPUC | AT91SAM9261_MATRIX_CS1A_SDRAMC;
cfg->smc_cs = 0;
cfg->smc_mode =
@@ -102,10 +102,10 @@ static void __bare_init pm9261_init(void)
cfg.pio = IOMEM(AT91SAM9261_BASE_PIOC);
cfg.sdramc = IOMEM(AT91SAM9261_BASE_SDRAMC);
cfg.ebi_pio_is_peripha = false;
- cfg.matrix_csa = AT91_MATRIX_EBICSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
pm9261_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9261_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
NULL);
diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c
index e9f8588..30b3d26 100644
--- a/arch/arm/boards/pm9263/init.c
+++ b/arch/arm/boards/pm9263/init.c
@@ -32,7 +32,6 @@
#include <linux/mtd/nand.h>
#include <mach/at91_pmc.h>
#include <mach/board.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91sam9_smc.h>
#include <linux/w1-gpio.h>
diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c
index 6849f0a..32850b2 100644
--- a/arch/arm/boards/pm9263/lowlevel_init.c
+++ b/arch/arm/boards/pm9263/lowlevel_init.c
@@ -30,8 +30,8 @@ static void __bare_init pm9263_board_config(struct at91sam926x_board_cfg *cfg)
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
- AT91_MATRIX_EBI0_CS1A_SDRAMC;
+ AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 0;
cfg->smc_mode =
@@ -123,10 +123,10 @@ static void __bare_init pm9263_board_init(void)
cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
cfg.ebi_pio_is_peripha = true;
- cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
pm9263_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9263_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
NULL);
diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
index efa5dc0..0565657 100644
--- a/arch/arm/boards/pm9g45/init.c
+++ b/arch/arm/boards/pm9g45/init.c
@@ -34,7 +34,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <linux/w1-gpio.h>
#include <w1_mac_address.h>
diff --git a/arch/arm/boards/qil-a926x/init.c b/arch/arm/boards/qil-a926x/init.c
index 3ef9872..fa7575d 100644
--- a/arch/arm/boards/qil-a926x/init.c
+++ b/arch/arm/boards/qil-a926x/init.c
@@ -25,7 +25,6 @@
#include <mach/at91sam9_smc.h>
#include <gpio.h>
#include <led.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
@@ -118,11 +117,6 @@ static struct macb_platform_data macb_pdata = {
static void qil_a9260_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -130,22 +124,7 @@ static void qil_a9260_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
/*
diff --git a/arch/arm/boards/sama5d3_xplained/init.c b/arch/arm/boards/sama5d3_xplained/init.c
index fda4c56..2433e25 100644
--- a/arch/arm/boards/sama5d3_xplained/init.c
+++ b/arch/arm/boards/sama5d3_xplained/init.c
@@ -30,7 +30,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c
index b35bdb5..08ccbcf 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -33,7 +33,6 @@
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/telit-evk-pro3/init.c b/arch/arm/boards/telit-evk-pro3/init.c
index ea63b1a..f6ee715 100644
--- a/arch/arm/boards/telit-evk-pro3/init.c
+++ b/arch/arm/boards/telit-evk-pro3/init.c
@@ -22,7 +22,6 @@
#include <mach/at91_rstc.h>
#include <mach/at91sam9_smc.h>
#include <mach/board.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <nand.h>
@@ -72,11 +71,6 @@ static struct macb_platform_data macb_pdata = {
static void evk_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -84,21 +78,7 @@ static void evk_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
- ;
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
/*
diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c
index 3b83c9f..dab3730 100644
--- a/arch/arm/boards/tny-a926x/init.c
+++ b/arch/arm/boards/tny-a926x/init.c
@@ -34,7 +34,6 @@
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
index 4b57b74..8566d27 100644
--- a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
+++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
@@ -33,8 +33,8 @@ static void __bare_init tny_a9263_board_config(struct at91sam926x_board_cfg *cfg
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
- AT91_MATRIX_EBI0_CS1A_SDRAMC;
+ AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 3;
cfg->smc_mode =
@@ -107,11 +107,11 @@ static void __bare_init tny_a9263_init(void)
cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
cfg.ebi_pio_is_peripha = true;
- cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
tny_a9263_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9263_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1,
at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC0)),
diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
index 12e8f4e..8969cbd 100644
--- a/arch/arm/boards/usb-a926x/init.c
+++ b/arch/arm/boards/usb-a926x/init.c
@@ -26,6 +26,7 @@
#include <io.h>
#include <envfs.h>
#include <mach/hardware.h>
+#include <mach/at91sam926x.h>
#include <nand.h>
#include <linux/sizes.h>
#include <linux/mtd/nand.h>
@@ -35,7 +36,6 @@
#include <mach/at91sam9_sdramc.h>
#include <gpio.h>
#include <led.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
@@ -128,11 +128,6 @@ static struct macb_platform_data macb_pdata = {
static void usb_a9260_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -140,22 +135,8 @@ static void usb_a9260_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ /* same address for the different supported SoCs */
+ at91sam_phy_reset(IOMEM(AT91SAM926X_BASE_RSTC));
}
static void usb_a9260_add_device_eth(void)
diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
index 066452b..a7dd2b2 100644
--- a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
+++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
@@ -35,8 +35,8 @@ static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
- AT91_MATRIX_EBI0_CS1A_SDRAMC;
+ AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 3;
cfg->smc_mode =
@@ -113,10 +113,10 @@ static void __bare_init usb_a9263_init(void)
cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
cfg.ebi_pio_is_peripha = true;
- cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
usb_a9263_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9263_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
NULL);
diff --git a/arch/arm/boards/zii-imx51-rdu1/board.c b/arch/arm/boards/zii-imx51-rdu1/board.c
index 46368cc..f739f3b 100644
--- a/arch/arm/boards/zii-imx51-rdu1/board.c
+++ b/arch/arm/boards/zii-imx51-rdu1/board.c
@@ -17,9 +17,16 @@
#include <common.h>
#include <init.h>
+#include <environment.h>
#include <mach/bbu.h>
#include <libfile.h>
#include <mach/imx5.h>
+#include <net.h>
+#include <linux/crc8.h>
+#include <linux/sizes.h>
+#include <linux/nvmem-consumer.h>
+
+#include <envfs.h>
static int zii_rdu1_init(void)
{
@@ -45,3 +52,175 @@ static int zii_rdu1_init(void)
return 0;
}
coredevice_initcall(zii_rdu1_init);
+
+#define KEY 0
+#define VALUE 1
+#define STRINGS_NUM 2
+
+static int zii_rdu1_load_config(void)
+{
+ struct device_node *np, *root;
+ size_t len, remaining_space;
+ const uint8_t crc8_polynomial = 0x8c;
+ DECLARE_CRC8_TABLE(crc8_table);
+ const char *cursor, *end;
+ const char *file = "/dev/dataflash0.config";
+ uint8_t *config;
+ int ret = 0;
+ enum {
+ BLOB_SPINOR,
+ BLOB_RAVE_SP_EEPROM,
+ BLOB_MICROWIRE,
+ } blob;
+
+ if (!of_machine_is_compatible("zii,imx51-rdu1"))
+ return 0;
+
+ crc8_populate_lsb(crc8_table, crc8_polynomial);
+
+ for (blob = BLOB_SPINOR; blob <= BLOB_MICROWIRE; blob++) {
+ switch (blob) {
+ case BLOB_MICROWIRE:
+ file = "/dev/microwire-eeprom";
+ /* FALLTHROUGH */
+ case BLOB_SPINOR:
+ config = read_file(file, &remaining_space);
+ if (!config) {
+ pr_err("Failed to read %s\n", file);
+ return -EIO;
+ }
+ break;
+ case BLOB_RAVE_SP_EEPROM:
+ /* Needed for error logging below */
+ file = "shadow copy in RAVE SP EEPROM";
+
+ root = of_get_root_node();
+ np = of_find_node_by_name(root, "eeprom@a4");
+ if (!np)
+ return -ENODEV;
+
+ pr_info("Loading %s, this may take a while\n", file);
+
+ remaining_space = SZ_1K;
+ config = nvmem_cell_get_and_read(np, "shadow-config",
+ remaining_space);
+ if (IS_ERR(config))
+ return PTR_ERR(config);
+
+ break;
+ }
+
+ /*
+ * The environment blob has its CRC8 stored as the
+ * last byte of the blob, so calculating CRC8 over the
+ * whole things should return 0
+ */
+ if (crc8(crc8_table, config, remaining_space, 0)) {
+ pr_err("CRC mismatch for %s\n", file);
+ free(config);
+ config = NULL;
+ } else {
+ /*
+ * We are done if there's a blob with a valid
+ * CRC8
+ */
+ break;
+ }
+ }
+
+ if (!config) {
+ pr_err("No valid config blobs were found\n");
+ ret = -EINVAL;
+ goto free_config;
+ }
+
+ /*
+ * Last byte is CRC8, so it is of no use for our parsing
+ * algorithm
+ */
+ remaining_space--;
+
+ cursor = config;
+ end = cursor + remaining_space;
+
+ /*
+ * The environemnt is stored a a bunch of zero-terminated
+ * ASCII strings in "key":"value" pairs
+ */
+ while (cursor < end) {
+ const char *strings[STRINGS_NUM] = { NULL, NULL };
+ char *key;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(strings); i++) {
+ if (!*cursor) {
+ /* We assume that last key:value pair
+ * will be terminated by an extra '\0'
+ * at the end */
+ goto free_config;
+ }
+
+ len = strnlen(cursor, remaining_space);
+ if (len >= remaining_space) {
+ ret = -EOVERFLOW;
+ goto free_config;
+ }
+
+ strings[i] = cursor;
+
+ len++; /* Account for '\0' at the end of the string */
+ cursor += len;
+ remaining_space -= len;
+
+ if (cursor > end) {
+ ret = -EOVERFLOW;
+ goto free_config;
+ }
+ }
+
+ key = basprintf("config_%s", strings[KEY]);
+ ret = setenv(key, strings[VALUE]);
+ free(key);
+
+ if (ret)
+ goto free_config;
+ }
+
+free_config:
+ free(config);
+ return ret;
+}
+late_initcall(zii_rdu1_load_config);
+
+static int zii_rdu1_ethernet_init(void)
+{
+ const char *mac_string;
+ struct device_node *np, *root;
+ uint8_t mac[ETH_ALEN];
+ int ret;
+
+ if (!of_machine_is_compatible("zii,imx51-rdu1"))
+ return 0;
+
+ root = of_get_root_node();
+
+ np = of_find_node_by_alias(root, "ethernet0");
+ if (!np) {
+ pr_warn("Failed to find ethernet0\n");
+ return -ENOENT;
+ }
+
+ mac_string = getenv("config_mac");
+ if (!mac_string)
+ return -ENOENT;
+
+ ret = string_to_ethaddr(mac_string, mac);
+ if (ret < 0)
+ return ret;
+
+ of_eth_register_ethaddr(np, mac);
+ return 0;
+}
+/* This needs to happen only after zii_rdu1_load_config was
+ * executed */
+environment_initcall(zii_rdu1_ethernet_init);
diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c
index c99f993..6352f49 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/board.c
+++ b/arch/arm/boards/zii-imx6q-rdu2/board.c
@@ -15,7 +15,9 @@
#include <common.h>
#include <envfs.h>
+#include <fs.h>
#include <gpio.h>
+#include <i2c/i2c.h>
#include <init.h>
#include <mach/bbu.h>
#include <mach/imx6.h>
@@ -97,50 +99,29 @@ static int rdu2_reset_audio_touchscreen_nfc(void)
*/
late_initcall(rdu2_reset_audio_touchscreen_nfc);
-static const struct gpio rdu2_front_panel_usb_gpios[] = {
- {
- .gpio = IMX_GPIO_NR(3, 19),
- .flags = GPIOF_OUT_INIT_LOW,
- .label = "usb-emulation",
- },
- {
- .gpio = IMX_GPIO_NR(3, 20),
- .flags = GPIOF_OUT_INIT_HIGH,
- .label = "usb-mode1",
- },
- {
- .gpio = IMX_GPIO_NR(3, 23),
- .flags = GPIOF_OUT_INIT_HIGH,
- .label = "usb-mode2",
- },
-};
-
-static int rdu2_enable_front_panel_usb(void)
+static int rdu2_devices_init(void)
{
- int ret;
+ struct i2c_client client;
if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") &&
!of_machine_is_compatible("zii,imx6qp-zii-rdu2"))
return 0;
- ret = gpio_request_array(rdu2_front_panel_usb_gpios,
- ARRAY_SIZE(rdu2_front_panel_usb_gpios));
- if (ret) {
- pr_err("Failed to request RDU2 front panel USB gpios: %s\n",
- strerror(-ret));
-
+ client.adapter = i2c_get_adapter(1);
+ if (client.adapter) {
+ u8 reg;
+
+ /*
+ * Reset PMIC SW1AB and SW1C rails to 1.375V. If an event
+ * caused only the i.MX6 SoC reset, the PMIC might still be
+ * stuck on the low voltage for the slow operating point.
+ */
+ client.addr = 0x08; /* PMIC i2c address */
+ reg = 0x2b; /* 1.375V, valid for both rails */
+ i2c_write_reg(&client, 0x20, &reg, 1);
+ i2c_write_reg(&client, 0x2e, &reg, 1);
}
- return ret;
-}
-late_initcall(rdu2_enable_front_panel_usb);
-
-static int rdu2_devices_init(void)
-{
- if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") &&
- !of_machine_is_compatible("zii,imx6qp-zii-rdu2"))
- return 0;
-
barebox_set_hostname("rdu2");
imx6_bbu_internal_spi_i2c_register_handler("SPI", "/dev/m25p0.barebox",
@@ -208,3 +189,32 @@ static int rdu2_ethernet_init(void)
return 0;
}
late_initcall(rdu2_ethernet_init);
+
+#define I210_CFGWORD_PCIID_157B 0x157b1a11
+static int rdu2_i210_invm(void)
+{
+ int fd;
+ u32 val;
+
+ if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") &&
+ !of_machine_is_compatible("zii,imx6qp-zii-rdu2"))
+ return 0;
+
+ fd = open("/dev/e1000-invm0", O_RDWR);
+ if (fd < 0) {
+ pr_err("could not open e1000 iNVM device!\n");
+ return fd;
+ }
+
+ pread(fd, &val, sizeof(val), 0);
+ if (val == I210_CFGWORD_PCIID_157B) {
+ pr_debug("i210 already programmed correctly\n");
+ return 0;
+ }
+
+ val = I210_CFGWORD_PCIID_157B;
+ pwrite(fd, &val, sizeof(val), 0);
+
+ return 0;
+}
+late_initcall(rdu2_i210_invm);
diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c
index 275d0a4..a8fa1ef 100644
--- a/arch/arm/boards/zii-vf610-dev/board.c
+++ b/arch/arm/boards/zii-vf610-dev/board.c
@@ -64,11 +64,6 @@ static int zii_vf610_cfu1_spu3_expose_signals(void)
{
static const struct gpio signals[] = {
{
- .gpio = 107,
- .flags = GPIOF_OUT_INIT_HIGH,
- .label = "soc_sw_rstn",
- },
- {
.gpio = 98,
.flags = GPIOF_IN,
.label = "e6352_intn",
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 0fc3c9c..bf84dfa 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -41,6 +41,7 @@ CONFIG_MACH_ZII_VF610_DEV=y
CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y
CONFIG_MACH_FREESCALE_MX7_SABRESD=y
CONFIG_MACH_NXP_IMX6ULL_EVK=y
+CONFIG_MACH_GRINN_LITEBOARD=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_THUMB2_BAREBOX=y
diff --git a/arch/arm/configs/microchip_ksz9477_evb_defconfig b/arch/arm/configs/microchip_ksz9477_evb_defconfig
new file mode 100644
index 0000000..e7d05bd
--- /dev/null
+++ b/arch/arm/configs/microchip_ksz9477_evb_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARCH_SAMA5D3=y
+CONFIG_AT91_MULTI_BOARDS=y
+CONFIG_MACH_MICROCHIP_KSZ9477_EVB=y
+CONFIG_AEABI=y
+CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEBUG_INFO=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_AT91_BOOT_TEST=y
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_GO=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_NET=y
+CONFIG_NET_NFS=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_OF_BAREBOX_ENV_IN_FS=y
+CONFIG_DRIVER_NET_MACB=y
+CONFIG_DRIVER_NET_MICREL=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_ATMEL=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1caeca3..4ecb3c2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -27,6 +27,7 @@ pbl-dtb-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o
pbl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
+pbl-dtb-$(CONFIG_MACH_GRINN_LITEBOARD) += imx6ul-liteboard.dtb.o
pbl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
pbl-dtb-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o
pbl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
@@ -115,6 +116,7 @@ pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \
vf610-zii-ssmb-spu3.dtb.o \
vf610-zii-scu4-aib-rev-c.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o
+pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o
diff --git a/arch/arm/dts/at91-microchip-ksz9477-evb.dts b/arch/arm/dts/at91-microchip-ksz9477-evb.dts
new file mode 100644
index 0000000..075cdcd
--- /dev/null
+++ b/arch/arm/dts/at91-microchip-ksz9477-evb.dts
@@ -0,0 +1,153 @@
+/*
+ * at91-microchip-ksz9477-evb.dts - Device Tree file for the EVB-KSZ9477 board
+ *
+ * Copyright (C) 2014 Atmel,
+ * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
+ * 2018 Ahmad Fatoum <a.fatoum@pengutronix.de>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include <arm/sama5d36.dtsi>
+
+/ {
+ model = "Microchip EVB-KSZ9477";
+ compatible = "atmel,sama5d3-ksz9477-evb", "atmel,sama5d3", "atmel,sama5";
+
+ aliases {
+ mmc0 = &mmc0;
+ };
+
+ chosen {
+ stdout-path = &dbgu;
+
+ environment {
+ compatible = "barebox,environment";
+ device-path = &mmc0, "partname:0";
+ file-path = "barebox.env";
+ };
+ };
+
+ memory {
+ reg = <0x20000000 0x10000000>;
+ };
+};
+
+&pinctrl {
+ board {
+ pinctrl_mmc0_cd: mmc0_cd {
+ atmel,pins =
+ <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+
+ pinctrl_spi_ksz: spi_ksz {
+ atmel,pins =
+ <
+ AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH
+ AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH
+ >;
+ };
+ };
+};
+
+&slow_xtal {
+ clock-frequency = <32768>;
+};
+
+&main_xtal {
+ clock-frequency = <12000000>;
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&macb0 {
+ phy-mode = "rgmii";
+ gpios = <&pioB 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&mmc0 {
+ pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
+ status = "okay";
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pmc {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-0 = <&pinctrl_spi_ksz>;
+ cs-gpios = <&pioC 25 0>;
+ id = <1>;
+ status = "okay";
+
+ ksz9477: ksz9477@0 {
+ compatible = "microchip,ksz9477", "microchip,ksz9893";
+ reg = <0>;
+
+ /* Bus clock is 132 MHz. */
+ spi-max-frequency = <44000000>;
+ spi-cpha;
+ spi-cpol;
+ gpios = <&pioB 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&macb0>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ /* port 6 is connected to eth0 */
+ };
+ };
+};
diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts
index 93bb344..01e46ba 100644
--- a/arch/arm/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/dts/imx51-zii-rdu1.dts
@@ -24,6 +24,16 @@
device-path = &spinor, "partname:barebox-environment";
};
};
+
+ aliases {
+ /*
+ * NVMEM device corresponding to EEPROM attached to
+ * the switch shared DT node with it, so we use that
+ * fact to create a desirable naming
+ */
+ switch-eeprom = &switch;
+ microwire-eeprom = &microwire_eeprom;
+ };
};
&ecspi1 {
@@ -51,6 +61,14 @@
};
};
+&mdio_gpio {
+ switch: switch@0 {};
+};
+
+&spi_gpio {
+ microwire_eeprom: eeprom@0 {};
+};
+
&uart3 {
rave-sp {
watchdog {
@@ -59,9 +77,16 @@
};
eeprom@a4 {
+ nvmem-cells = <&shadow_config>;
+ nvmem-cell-names = "shadow-config";
+
boot_source: boot-source@83 {
reg = <0x83 1>;
};
+
+ shadow_config: shadow-config@1000 {
+ reg = <0x1000 0x400>;
+ };
};
};
};
diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
index f63b5d2..fea219f 100644
--- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
@@ -52,6 +52,12 @@
aliases {
ethernet0 = &fec;
ethernet1 = &i210;
+ /*
+ * NVMEM device corresponding to EEPROM attached to
+ * the switch shared DT node with it, so we use that
+ * fact to create a desirable naming
+ */
+ switch-eeprom = &switch;
};
};
@@ -110,17 +116,47 @@
};
};
-&pcie {
- host@0 {
- #address-cells = <3>;
- #size-cells = <2>;
- reg = <0 0 0 0 0>;
- device_type = "pci";
-
- i210: i210@0 {
- reg = <0 0 0 0 0>;
- nvmem-cells = <&mac_address_1>;
- nvmem-cell-names = "mac-address";
- };
+&i210 {
+ nvmem-cells = <&mac_address_1>;
+ nvmem-cell-names = "mac-address";
+};
+
+&usbotg {
+ dr_mode = "otg";
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio3_hog>;
+
+ usb-emulation {
+ gpio-hog;
+ gpios = <19 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "usb-emulation";
+ };
+
+ usb-mode1 {
+ gpio-hog;
+ gpios = <20 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-mode1";
+ };
+
+ usb-mode2 {
+ gpio-hog;
+ gpios = <23 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-mode2";
+ };
+};
+
+&iomuxc {
+ pinctrl_gpio3_hog: gpio3hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40000038
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x40000038
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x40000038
+ >;
};
};
diff --git a/arch/arm/dts/imx6ul-liteboard.dts b/arch/arm/dts/imx6ul-liteboard.dts
new file mode 100644
index 0000000..03a4bfc
--- /dev/null
+++ b/arch/arm/dts/imx6ul-liteboard.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2018 Grinn
+ *
+ * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <arm/imx6ul-liteboard.dts>
+
+/ {
+ chosen {
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &environment_sd;
+ status = "disabled";
+ };
+
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &environment_emmc;
+ status = "disabled";
+ };
+ };
+};
+
+&usdhc1 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ environment_sd: partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+ };
+};
+
+&usdhc2 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ environment_emmc: partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/imx7d-zii-rpu2.dts b/arch/arm/dts/imx7d-zii-rpu2.dts
index 6fba73f..24a6d40 100644
--- a/arch/arm/dts/imx7d-zii-rpu2.dts
+++ b/arch/arm/dts/imx7d-zii-rpu2.dts
@@ -19,6 +19,15 @@
stdout-path = &uart2;
};
+ aliases {
+ /*
+ * NVMEM device corresponding to EEPROM attached to
+ * the switch shared DT node with it, so we use that
+ * fact to create a desirable naming
+ */
+ switch-eeprom = &switch0;
+ };
+
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&pinctrl_leds_debug>;
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index a6e724e..56a3517 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -15,6 +15,17 @@
chosen {
stdout-path = &uart1;
+
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &usdhc1, "partname:barebox-environment";
+ status = "disabled";
+ };
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &usdhc2, "partname:barebox-environment";
+ status = "disabled";
+ };
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
@@ -177,6 +188,19 @@
no-sd;
no-sdio;
status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
};
&usdhc2 {
@@ -190,6 +214,19 @@
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
};
&wdog1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
index 234995b..40a7a9c 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -15,7 +15,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <arm/socfpga_cyclone5_de0_sockit.dts>
+#include <arm/socfpga_cyclone5_de0_nano_soc.dts>
#include "socfpga.dtsi"
/ {
diff --git a/arch/arm/dts/vf610-zii-cfu1.dts b/arch/arm/dts/vf610-zii-cfu1.dts
index 80d3f54..1de9ee9 100644
--- a/arch/arm/dts/vf610-zii-cfu1.dts
+++ b/arch/arm/dts/vf610-zii-cfu1.dts
@@ -8,3 +8,13 @@
#include "vf610-zii-dev.dtsi"
+/ {
+ aliases {
+ /*
+ * NVMEM device corresponding to EEPROM attached to
+ * the switch shared DT node with it, so we use that
+ * fact to create a desirable naming
+ */
+ switch-eeprom = &switch0;
+ };
+};
diff --git a/arch/arm/dts/vf610-zii-dev-rev-c.dts b/arch/arm/dts/vf610-zii-dev-rev-c.dts
index 797b31b..c6341a0 100644
--- a/arch/arm/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/dts/vf610-zii-dev-rev-c.dts
@@ -46,6 +46,18 @@
#include "vf610-zii-dev.dtsi"
+/ {
+ aliases {
+ /*
+ * NVMEM device corresponding to EEPROM attached to
+ * the switch shared DT node with it, so we use that
+ * fact to create a desirable naming
+ */
+ switch0-eeprom = &switch0;
+ switch1-eeprom = &switch1;
+ };
+};
+
&dspi0 {
m25p128@0 {
partition@0 {
diff --git a/arch/arm/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/dts/vf610-zii-ssmb-spu3.dts
index e030109..5b2460c 100644
--- a/arch/arm/dts/vf610-zii-ssmb-spu3.dts
+++ b/arch/arm/dts/vf610-zii-ssmb-spu3.dts
@@ -3,3 +3,14 @@
#include <arm/vf610-zii-ssmb-spu3.dts>
#include "vf610-zii-dev.dtsi"
+
+/ {
+ aliases {
+ /*
+ * NVMEM device corresponding to EEPROM attached to
+ * the switch shared DT node with it, so we use that
+ * fact to create a desirable naming
+ */
+ switch-eeprom = &switch0;
+ };
+};
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0a9cf3a..7a895c2 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -74,12 +74,6 @@ config HAVE_NAND_ATMEL_BUSWIDTH_16
config HAVE_AT91_DATAFLASH_CARD
bool
-config AT91SAM9_RESET
- bool
-
-config AT91SAM9G45_RESET
- bool
-
config HAVE_AT91_LOAD_BAREBOX_SRAM
bool
@@ -96,7 +90,6 @@ config SOC_AT91SAM9260
select SOC_AT91SAM9
select HAVE_AT91_DBGU0
select HAS_MACB
- select AT91SAM9_RESET
help
Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
or AT91SAM9G20 SoC.
@@ -105,7 +98,6 @@ config SOC_AT91SAM9261
bool
select SOC_AT91SAM9
select HAVE_AT91_DBGU0
- select AT91SAM9_RESET
help
Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
@@ -114,7 +106,6 @@ config SOC_AT91SAM9263
select SOC_AT91SAM9
select HAVE_AT91_DBGU1
select HAS_MACB
- select AT91SAM9_RESET
select HAVE_AT91_LOAD_BAREBOX_SRAM
config SOC_AT91SAM9G45
@@ -122,7 +113,6 @@ config SOC_AT91SAM9G45
select SOC_AT91SAM9
select HAVE_AT91_DBGU1
select HAS_MACB
- select AT91SAM9G45_RESET
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -132,7 +122,6 @@ config SOC_AT91SAM9X5
select SOC_AT91SAM9
select HAVE_AT91_DBGU0
select HAS_MACB
- select AT91SAM9G45_RESET
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
select HAVE_AT91_UTMI
@@ -148,7 +137,6 @@ config SOC_AT91SAM9N12
bool
select SOC_AT91SAM9
select HAVE_AT91_DBGU0
- select AT91SAM9G45_RESET
help
Select this if you are using Atmel's AT91SAM9N12 SoC.
@@ -203,7 +191,6 @@ config ARCH_SAMA5D3
select SOC_SAMA5
select HAVE_AT91_DBGU1
select HAS_MACB
- select AT91SAM9G45_RESET
select HAVE_MACH_ARM_HEAD
config ARCH_SAMA5D4
@@ -211,7 +198,6 @@ config ARCH_SAMA5D4
select SOC_SAMA5
select HAVE_AT91_DBGU2
select HAS_MACB
- select AT91SAM9G45_RESET
select HAVE_MACH_ARM_HEAD
endchoice
@@ -550,6 +536,13 @@ config MACH_AT91SAM9X5EK
Select this if you re using Atmel's AT91SAM9x5-EK Evaluation Kit.
Supported chips are sam9g15, sam9g25, sam9x25, sam9g35 and sam9x35.
+config MACH_MICROCHIP_KSZ9477_EVB
+ bool "Microchip EVB-KSZ9477 Evaluation Kit"
+ select OFDEVICE
+ select COMMON_CLK_OF_PROVIDER
+ help
+ Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
+
endif
comment "AT91 Board Options"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 664201c..d81683a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -8,8 +8,8 @@ obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o
obj-$(CONFIG_AT91_BOOTSTRAP) += bootstrap.o
-obj-$(CONFIG_AT91SAM9_RESET) += at91sam9_reset.o
-obj-$(CONFIG_AT91SAM9G45_RESET) += at91sam9g45_reset.o
+obj-y += at91sam9_reset.o
+obj-y += at91sam9g45_reset.o
obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o
@@ -20,10 +20,10 @@ obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o
ifeq ($(CONFIG_OFDEVICE),)
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o
+obj-$(CONFIG_ARCH_SAMA5D3) += sama5d3.o sama5d3_devices.o
endif
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o
obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o
-obj-$(CONFIG_ARCH_SAMA5D3) += sama5d3.o sama5d3_devices.o
obj-$(CONFIG_ARCH_SAMA5D4) += sama5d4.o sama5d4_devices.o
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index a110ee3..f370160 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -17,7 +17,6 @@
#include <mach/at91rm9200.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91rm9200_mc.h>
#include <i2c/i2c-gpio.h>
#include <linux/sizes.h>
@@ -135,15 +134,19 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
return;
/* enable the address range of CS3 */
- csa = at91_sys_read(AT91_EBI_CSA);
- at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91RM9200_BASE_MC + AT91RM9200_EBI_CSA);
+ csa |= AT91RM9200_EBI_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91RM9200_BASE_MC + AT91RM9200_EBI_CSA);
/* set the bus interface characteristics */
- at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
- | AT91_SMC_NWS_(5)
- | AT91_SMC_TDF_(1)
- | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
- | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
+ writel(AT91RM9200_SMC_ACSS_STD |
+ AT91RM9200_SMC_DBW_8 |
+ AT91RM9200_SMC_WSEN |
+ AT91RM9200_SMC_NWS_(5) |
+ AT91RM9200_SMC_TDF_(1) |
+ AT91RM9200_SMC_RWSETUP_(0) | /* tDS Data Set up Time 30 - ns */
+ AT91RM9200_SMC_RWHOLD_(1), /* tDH Data Hold Time 20 - ns */
+ AT91RM9200_BASE_MC + AT91RM9200_SMC_CSR(3)
);
/* enable pin */
@@ -253,7 +256,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PA30, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PA31, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91RM9200_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index fd11223..b4021b5 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -30,12 +30,11 @@
#include <clock.h>
#include <restart.h>
#include <mach/hardware.h>
-#include <mach/at91_tc.h>
-#include <mach/at91_st.h>
-#include <mach/at91_pmc.h>
-#include <mach/io.h>
+#include <mach/at91rm9200_st.h>
#include <io.h>
+static void __iomem *st = IOMEM(AT91RM9200_BASE_ST);
+
/*
* The ST_CRTR is updated asynchronously to the master clock ... but
* the updates as seen by the CPU don't seem to be strictly monotonic.
@@ -45,9 +44,9 @@ uint64_t at91rm9200_clocksource_read(void)
{
unsigned long x1, x2;
- x1 = at91_sys_read(AT91_ST_CRTR);
+ x1 = readl(st + AT91RM9200_ST_CRTR);
do {
- x2 = at91_sys_read(AT91_ST_CRTR);
+ x2 = readl(st + AT91RM9200_ST_CRTR);
if (x1 == x2)
break;
x1 = x2;
@@ -67,7 +66,7 @@ static int clocksource_init (void)
* directly for the clocksource and all clockevents, after adjusting
* its prescaler from the 1 Hz default.
*/
- at91_sys_write(AT91_ST_RTMR, 1);
+ writel(1, st + AT91RM9200_ST_RTMR);
cs.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, cs.shift);
@@ -83,8 +82,8 @@ static void __noreturn at91rm9200_restart_soc(struct restart_handler *rst)
/*
* Perform a hardware reset with the use of the Watchdog timer.
*/
- at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
- at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
+ writel(AT91RM9200_ST_RSTEN | AT91RM9200_ST_EXTEN | 1, st + AT91RM9200_ST_WDMR);
+ writel(AT91RM9200_ST_WDRST, st + AT91RM9200_ST_CR);
/* Not reached */
hang();
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 8975bf4..56327a2 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -1,8 +1,11 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
#include "clock.h"
@@ -221,6 +224,12 @@ static void __init at91sam9260_register_clocks(void)
clk_register(&pck1);
}
+static void at91sam9260_restart(struct restart_handler *rst)
+{
+ at91sam9_reset(IOMEM(AT91SAM9260_BASE_SDRAMC),
+ IOMEM(AT91SAM9260_BASE_RSTC + AT91_RSTC_CR));
+}
+
static void at91sam9260_initialize(void)
{
/* Register the processor-specific clocks */
@@ -233,6 +242,8 @@ static void at91sam9260_initialize(void)
at91_add_pit(AT91SAM9260_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9260_BASE_SMC, 0x200);
+
+ restart_handler_register_fn(at91sam9260_restart);
}
static int at91sam9260_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 1cb8983..eafcfea 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91sam9_sdramc.h>
#include <mach/at91_rtt.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
@@ -132,8 +131,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_ECC,
- .end = AT91_BASE_SYS + AT91_ECC + 512 - 1,
+ .start = AT91SAM9260_BASE_ECC,
+ .end = AT91SAM9260_BASE_ECC + 512 - 1,
.flags = IORESOURCE_MEM,
}
};
@@ -145,8 +144,9 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91SAM9260_BASE_MATRIX + AT91SAM9260_MATRIX_EBICSA);
+ csa |= AT91SAM9260_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9260_BASE_MATRIX + AT91SAM9260_MATRIX_EBICSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
@@ -265,7 +265,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PB14, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PB15, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9260_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 35aaa9c..4abc556 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -1,8 +1,11 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
#include "clock.h"
@@ -213,6 +216,12 @@ static void at91sam9261_register_clocks(void)
clk_register(&hck1);
}
+static void at91sam9261_restart(struct restart_handler *rst)
+{
+ at91sam9_reset(IOMEM(AT91SAM9261_BASE_SDRAMC),
+ IOMEM(AT91SAM9261_BASE_RSTC + AT91_RSTC_CR));
+}
+
static void at91sam9261_initialize(void)
{
/* Register the processor-specific clocks */
@@ -225,6 +234,8 @@ static void at91sam9261_initialize(void)
at91_add_pit(AT91SAM9261_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200);
+
+ restart_handler_register_fn(at91sam9261_restart);
}
static int at91sam9261_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 6be3909..fcf719a 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91_rtt.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
@@ -94,8 +93,9 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
+ csa |= AT91SAM9261_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
@@ -269,7 +269,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PA9, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9261_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index ee48115..690f8e0 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -1,8 +1,11 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "clock.h"
#include "generic.h"
@@ -231,6 +234,12 @@ static void __init at91sam9263_register_clocks(void)
clk_register(&pck3);
}
+static void at91sam9263_restart(struct restart_handler *rst)
+{
+ at91sam9_reset(IOMEM(AT91SAM9263_BASE_SDRAMC0),
+ IOMEM(AT91SAM9263_BASE_RSTC + AT91_RSTC_CR));
+}
+
static void at91sam9263_initialize(void)
{
/* Register the processor-specific clocks */
@@ -246,6 +255,8 @@ static void at91sam9263_initialize(void)
at91_add_pit(AT91SAM9263_BASE_PIT);
at91_add_sam9_smc(0, AT91SAM9263_BASE_SMC0, 0x200);
at91_add_sam9_smc(1, AT91SAM9263_BASE_SMC1, 0x200);
+
+ restart_handler_register_fn(at91sam9263_restart);
}
static int at91sam9263_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 6302684..a67345f 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91_rtt.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <i2c/i2c-gpio.h>
#include "generic.h"
@@ -126,8 +125,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_ECC0,
- .end = AT91_BASE_SYS + AT91_ECC0 + 512 - 1,
+ .start = AT91SAM9263_BASE_ECC0,
+ .end = AT91SAM9263_BASE_ECC0 + 512 - 1,
.flags = IORESOURCE_MEM,
}
};
@@ -139,8 +138,9 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
- at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
+ csa |= AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
@@ -300,7 +300,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PC30, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9263_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9_reset.S b/arch/arm/mach-at91/at91sam9_reset.S
index 890545e..65e22f4 100644
--- a/arch/arm/mach-at91/at91sam9_reset.S
+++ b/arch/arm/mach-at91/at91sam9_reset.S
@@ -20,12 +20,9 @@
.arm
- .globl restart_sam9
+ .globl at91sam9_reset
-restart_sam9: ldr r0, .at91_va_base_sdramc @ preload constants
- ldr r1, .at91_va_base_rstc_cr
-
- mov r2, #1
+at91sam9_reset: mov r2, #1
mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
@@ -36,8 +33,3 @@ restart_sam9: ldr r0, .at91_va_base_sdramc @ preload constants
str r4, [r1] @ reset processor
b .
-
-.at91_va_base_sdramc:
- .word AT91_BASE_SYS + AT91_SDRAMC
-.at91_va_base_rstc_cr:
- .word AT91_BASE_SYS + AT91_RSTC_CR
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index c70036b..569aa27 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -1,10 +1,12 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
-#include <mach/io.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
#include "clock.h"
@@ -247,6 +249,12 @@ static void __init at91sam9g45_register_clocks(void)
clk_register(&pck1);
}
+static void at91sam9g45_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(AT91SAM9G45_BASE_DDRSDRC0),
+ IOMEM(AT91SAM9G45_BASE_RSTC + AT91_RSTC_CR));
+}
+
static void at91sam9g45_initialize(void)
{
/* Register the processor-specific clocks */
@@ -261,6 +269,8 @@ static void at91sam9g45_initialize(void)
at91_add_pit(AT91SAM9G45_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200);
+
+ restart_handler_register_fn(at91sam9g45_restart);
}
static int at91sam9g45_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 67ca359..43d8d5f 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91_rtt.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <i2c/i2c-gpio.h>
#include "generic.h"
@@ -128,8 +127,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_ECC,
- .end = AT91_BASE_SYS + AT91_ECC + 512 - 1,
+ .start = AT91SAM9G45_BASE_ECC,
+ .end = AT91SAM9G45_BASE_ECC + 512 - 1,
.flags = IORESOURCE_MEM,
}
};
@@ -141,8 +140,9 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91SAM9G45_BASE_MATRIX + AT91SAM9G45_MATRIX_EBICSA);
+ csa |= AT91SAM9G45_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9G45_BASE_MATRIX + AT91SAM9G45_MATRIX_EBICSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
@@ -217,7 +217,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PB12, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PB13, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9G45_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 2cb113c..6a58de6 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -17,12 +17,9 @@
.arm
- .globl restart_sam9g45
+ .globl at91sam9g45_reset
-restart_sam9g45: ldr r0, .at91_va_base_sdramc @ preload constants
- ldr r1, .at91_va_base_rstc_cr
-
- mov r2, #1
+at91sam9g45_reset: mov r2, #1
mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
@@ -33,8 +30,3 @@ restart_sam9g45: ldr r0, .at91_va_base_sdramc @ preload constants
str r4, [r1] @ reset processor
b .
-
-.at91_va_base_sdramc:
- .word AT91_BASE_SYS + AT91_DDRSDRC0
-.at91_va_base_rstc_cr:
- .word AT91_BASE_SYS + AT91_RSTC_CR
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 7ab44e4..365bded 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -1,10 +1,12 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
-#include <mach/io.h>
#include <mach/cpu.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
#include "clock.h"
@@ -200,6 +202,12 @@ static void __init at91sam9n12_register_clocks(void)
}
+static void at91sam9n12_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(AT91SAM9N12_BASE_DDRSDRC0),
+ IOMEM(AT91SAM9N12_BASE_RSTC + AT91_RSTC_CR));
+}
+
/* --------------------------------------------------------------------
* AT91SAM9N12 processor initialization
* -------------------------------------------------------------------- */
@@ -217,6 +225,8 @@ static void at91sam9n12_initialize(void)
at91_add_pit(AT91SAM9N12_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200);
+
+ restart_handler_register_fn(at91sam9n12_restart);
}
static int at91sam9n12_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c
index 84c871c..43cbb79 100644
--- a/arch/arm/mach-at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/at91sam9n12_devices.c
@@ -19,7 +19,6 @@
#include <mach/at91_pmc.h>
#include <mach/at91sam9n12_matrix.h>
#include <mach/at91sam9_ddrsdr.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
@@ -133,13 +132,13 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_PMECC,
- .end = AT91_BASE_SYS + AT91_PMECC + 0x600 - 1,
+ .start = AT91SAM9N12_BASE_PMECC,
+ .end = AT91SAM9N12_BASE_PMECC + 0x600 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
- .start = AT91_BASE_SYS + AT91_PMERRLOC,
- .end = AT91_BASE_SYS + AT91_PMERRLOC + 0x200 - 1,
+ .start = AT91SAM9N12_BASE_PMERRLOC,
+ .end = AT91SAM9N12_BASE_PMERRLOC + 0x200 - 1,
.flags = IORESOURCE_MEM,
},
[3] = {
@@ -158,19 +157,19 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
data->pmecc_lookup_table_offset = 0x8000;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ csa = readl(AT91SAM9N12_BASE_MATRIX + AT91SAM9N12_MATRIX_EBICSA);
/* Assign CS3 to NAND/SmartMedia Interface */
- csa |= AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH;
+ csa |= AT91SAM9N12_MATRIX_EBI_CS3A_SMC_NANDFLASH;
/* Configure databus */
if (!data->bus_on_d0)
- csa |= AT91_MATRIX_NFD0_ON_D16;
+ csa |= AT91SAM9N12_MATRIX_NFD0_ON_D16;
else
- csa &= ~AT91_MATRIX_NFD0_ON_D16;
+ csa &= ~AT91SAM9N12_MATRIX_NFD0_ON_D16;
/* Configure IO drive */
- csa |= AT91_MATRIX_EBI_HIGH_DRIVE;
+ csa |= AT91SAM9N12_MATRIX_EBI_HIGH_DRIVE;
- at91_sys_write(AT91_MATRIX_EBICSA, csa);
+ writel(csa, AT91SAM9N12_BASE_MATRIX + AT91SAM9N12_MATRIX_EBICSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
@@ -373,7 +372,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PA9, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9N12_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
new file mode 100644
index 0000000..40ba9ed
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -0,0 +1,20 @@
+#include <common.h>
+#include <init.h>
+#include <restart.h>
+#include <mach/at91sam9x5.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
+
+static void at91sam9x5_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(AT91SAM9X5_BASE_DDRSDRC0),
+ IOMEM(AT91SAM9X5_BASE_RSTC + AT91_RSTC_CR));
+}
+
+static int at91sam9x5_initialize(void)
+{
+ restart_handler_register_fn(at91sam9x5_restart);
+
+ return 0;
+}
+coredevice_initcall(at91sam9x5_initialize);
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index d7ddda4..ab506a1 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -18,7 +18,6 @@
#include <mach/at91_pmc.h>
#include <mach/at91sam9x5_matrix.h>
#include <mach/at91sam9_ddrsdr.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
@@ -225,13 +224,13 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_PMECC,
- .end = AT91_BASE_SYS + AT91_PMECC + 0x600 - 1,
+ .start = AT91SAM9X5_BASE_PMECC,
+ .end = AT91SAM9X5_BASE_PMECC + 0x600 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
- .start = AT91_BASE_SYS + AT91_PMERRLOC,
- .end = AT91_BASE_SYS + AT91_PMERRLOC + 0x200 - 1,
+ .start = AT91SAM9X5_BASE_PMERRLOC,
+ .end = AT91SAM9X5_BASE_PMERRLOC + 0x200 - 1,
.flags = IORESOURCE_MEM,
},
[3] = {
@@ -248,8 +247,9 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH);
+ csa = readl(AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
+ csa |= AT91SAM9X5_MATRIX_EBI_CS3A_SMC_NANDFLASH;
+ writel(csa, AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
data->pmecc_lookup_table_offset = 0x8000;
@@ -456,7 +456,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PA9, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9X5_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 125d169..9d2e3a3 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -20,7 +20,6 @@
#include <init.h>
#include <mach/hardware.h>
-#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
@@ -109,6 +108,18 @@
#define cpu_has_dual_matrix() (cpu_is_sama5d4())
+static void *pmc;
+
+static inline void at91_pmc_write(unsigned int offset, u32 val)
+{
+ writel(val, pmc + offset);
+}
+
+static inline u32 at91_pmc_read(unsigned int offset)
+{
+ return readl(pmc + offset);
+}
+
static LIST_HEAD(clocks);
static u32 at91_pllb_usb_init;
@@ -649,6 +660,15 @@ int at91_clock_init(void)
int i;
unsigned long main_clock;
+ if (cpu_is_sama5d4())
+ pmc = IOMEM(0xf0018000);
+ else
+ pmc = IOMEM(0xfffffc00); /*
+ * All other supported SoCs use this
+ * base address (new ones should use of
+ * clock support)
+ */
+
main_clock = at91_main_clock;
/*
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index d74c140..bbbd497 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -16,12 +16,6 @@
#ifndef AT91_PMC_H
#define AT91_PMC_H
-#define at91_pmc_read(field) \
- __raw_readl(AT91_PMC + field)
-
-#define at91_pmc_write(field, value) \
- __raw_writel(value, AT91_PMC + field)
-
#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
index e49caef..d67bed5 100644
--- a/arch/arm/mach-at91/include/mach/at91_rstc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -16,13 +16,13 @@
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
-#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
+#define AT91_RSTC_CR (0x00) /* Reset Controller Control Register */
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
-#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
+#define AT91_RSTC_SR (0x04) /* Reset Controller Status Register */
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
@@ -33,7 +33,7 @@
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
-#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
+#define AT91_RSTC_MR (0x08) /* Reset Controller Mode Register */
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
deleted file mode 100644
index 8847173..0000000
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_st.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * System Timer (ST) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_ST_H
-#define AT91_ST_H
-
-#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
-#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
-
-#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
-#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
-
-#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
-#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
-#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
-#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
-
-#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
-#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
-
-#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
-#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
-#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
-#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
-#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
-
-#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
-#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
-#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
-
-#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
-#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
-
-#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
-#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/include/mach/at91_tc.h
deleted file mode 100644
index 5a064b4..0000000
--- a/arch/arm/mach-at91/include/mach/at91_tc.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_tc.h]
- *
- * Copyright (C) SAN People
- *
- * Timer/Counter Unit (TC) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_TC_H
-#define AT91_TC_H
-
-#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
-#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
-
-#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
-#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
-#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
-#define AT91_TC_TC0XC0S_NONE (1 << 0)
-#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
-#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
-#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
-#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
-#define AT91_TC_TC1XC1S_NONE (1 << 2)
-#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
-#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
-#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
-#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
-#define AT91_TC_TC2XC2S_NONE (1 << 4)
-#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
-#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
-
-
-#define AT91_TC_CCR 0x00 /* Channel Control Register */
-#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
-#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
-#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
-
-#define AT91_TC_CMR 0x04 /* Channel Mode Register */
-#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
-#define AT91_TC_TIMER_CLOCK1 (0 << 0)
-#define AT91_TC_TIMER_CLOCK2 (1 << 0)
-#define AT91_TC_TIMER_CLOCK3 (2 << 0)
-#define AT91_TC_TIMER_CLOCK4 (3 << 0)
-#define AT91_TC_TIMER_CLOCK5 (4 << 0)
-#define AT91_TC_XC0 (5 << 0)
-#define AT91_TC_XC1 (6 << 0)
-#define AT91_TC_XC2 (7 << 0)
-#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
-#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
-#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
-#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
-#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
-#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
-#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
-#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
-#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
-#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
-
-#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
-#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
-#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
-#define AT91_TC_EEVTEDG_NONE (0 << 8)
-#define AT91_TC_EEVTEDG_RISING (1 << 8)
-#define AT91_TC_EEVTEDG_FALLING (2 << 8)
-#define AT91_TC_EEVTEDG_BOTH (3 << 8)
-#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
-#define AT91_TC_EEVT_TIOB (0 << 10)
-#define AT91_TC_EEVT_XC0 (1 << 10)
-#define AT91_TC_EEVT_XC1 (2 << 10)
-#define AT91_TC_EEVT_XC2 (3 << 10)
-#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
-#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
-#define AT91_TC_WAVESEL_UP (0 << 13)
-#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
-#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
-#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
-#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
-#define AT91_TC_ACPA_NONE (0 << 16)
-#define AT91_TC_ACPA_SET (1 << 16)
-#define AT91_TC_ACPA_CLEAR (2 << 16)
-#define AT91_TC_ACPA_TOGGLE (3 << 16)
-#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
-#define AT91_TC_ACPC_NONE (0 << 18)
-#define AT91_TC_ACPC_SET (1 << 18)
-#define AT91_TC_ACPC_CLEAR (2 << 18)
-#define AT91_TC_ACPC_TOGGLE (3 << 18)
-#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
-#define AT91_TC_AEEVT_NONE (0 << 20)
-#define AT91_TC_AEEVT_SET (1 << 20)
-#define AT91_TC_AEEVT_CLEAR (2 << 20)
-#define AT91_TC_AEEVT_TOGGLE (3 << 20)
-#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
-#define AT91_TC_ASWTRG_NONE (0 << 22)
-#define AT91_TC_ASWTRG_SET (1 << 22)
-#define AT91_TC_ASWTRG_CLEAR (2 << 22)
-#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
-#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
-#define AT91_TC_BCPB_NONE (0 << 24)
-#define AT91_TC_BCPB_SET (1 << 24)
-#define AT91_TC_BCPB_CLEAR (2 << 24)
-#define AT91_TC_BCPB_TOGGLE (3 << 24)
-#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
-#define AT91_TC_BCPC_NONE (0 << 26)
-#define AT91_TC_BCPC_SET (1 << 26)
-#define AT91_TC_BCPC_CLEAR (2 << 26)
-#define AT91_TC_BCPC_TOGGLE (3 << 26)
-#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
-#define AT91_TC_BEEVT_NONE (0 << 28)
-#define AT91_TC_BEEVT_SET (1 << 28)
-#define AT91_TC_BEEVT_CLEAR (2 << 28)
-#define AT91_TC_BEEVT_TOGGLE (3 << 28)
-#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
-#define AT91_TC_BSWTRG_NONE (0 << 30)
-#define AT91_TC_BSWTRG_SET (1 << 30)
-#define AT91_TC_BSWTRG_CLEAR (2 << 30)
-#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
-
-#define AT91_TC_CV 0x10 /* Counter Value */
-#define AT91_TC_RA 0x14 /* Register A */
-#define AT91_TC_RB 0x18 /* Register B */
-#define AT91_TC_RC 0x1c /* Register C */
-
-#define AT91_TC_SR 0x20 /* Status Register */
-#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
-#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
-#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
-#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
-#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
-#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
-#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
-#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
-#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
-#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
-#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
-
-#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
-#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
-#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 4fe8fd8..01f5d23 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -19,8 +19,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripheral */
#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
@@ -76,7 +74,6 @@
#define AT91RM9200_BASE_SSC1 0xfffd4000
#define AT91RM9200_BASE_SSC2 0xfffd8000
#define AT91RM9200_BASE_SPI 0xfffe0000
-#define AT91_BASE_SYS 0xfffff000
/*
* System Peripherals
@@ -86,40 +83,11 @@
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
+#define AT91RM9200_BASE_PMC 0xfffffc00
#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
-#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
-#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
-#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
-
-#define AT91_BASE_PIOA AT91RM9200_BASE_PIOA /* PIO Controller A */
-#define AT91_BASE_PIOB AT91RM9200_BASE_PIOB /* PIO Controller B */
-#define AT91_BASE_PIOC AT91RM9200_BASE_PIOC /* PIO Controller C */
-#define AT91_BASE_PIOD AT91RM9200_BASE_PIOD /* PIO Controller D */
-
-#define AT91_USART0 AT91RM9200_BASE_US0
-#define AT91_USART1 AT91RM9200_BASE_US1
-#define AT91_USART2 AT91RM9200_BASE_US2
-#define AT91_USART3 AT91RM9200_BASE_US3
-#define AT91_NB_USART 5
-
-#define AT91_BASE_SPI AT91RM9200_BASE_SPI
-#define AT91_BASE_TWI AT91RM9200_BASE_TWI
-#define AT91_ID_UHP AT91RM9200_ID_UHP
-#define AT91_PMC_UHP AT91RM9200_PMC_UHP
-#define AT91_TC (AT91RM9200_BASE_TC0 - AT91_BASE_SYS)
-
-#define AT91_MATRIX 0 /* not supported */
-
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
@@ -133,9 +101,4 @@
#define AT91_VA_BASE_EMAC AT91RM9200_BASE_EMAC
-/*
- * Cpu Name
- */
-#define AT91_CPU_NAME "AT91RM9200"
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index fc44a61..03e1b87 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -17,155 +17,156 @@
#define AT91RM9200_MC_H
/* Memory Controller */
-#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
-#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
-
-#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
-#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
-#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
-#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
-#define AT91_MC_ABTSZ_BYTE (0 << 8)
-#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
-#define AT91_MC_ABTSZ_WORD (2 << 8)
-#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
-#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
-#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
-#define AT91_MC_ABTTYP_FETCH (2 << 10)
-#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
-#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
-#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
-#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
-#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
-#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
-#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
-#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
-
-#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
-
-#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
-#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
-#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
-#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
-#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
+#define AT91RM9200_MC_RCR (0x00) /* MC Remap Control Register */
+#define AT91RM9200_MC_RCB (1 << 0) /* Remap Command Bit */
+
+#define AT91RM9200_MC_ASR (0x04) /* MC Abort Status Register */
+#define AT91RM9200_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
+#define AT91RM9200_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
+#define AT91RM9200_MC_ABTSZ (3 << 8) /* Abort Size Status */
+#define AT91RM9200_MC_ABTSZ_BYTE (0 << 8)
+#define AT91RM9200_MC_ABTSZ_HALFWORD (1 << 8)
+#define AT91RM9200_MC_ABTSZ_WORD (2 << 8)
+#define AT91RM9200_MC_ABTTYP (3 << 10) /* Abort Type Status */
+#define AT91RM9200_MC_ABTTYP_DATAREAD (0 << 10)
+#define AT91RM9200_MC_ABTTYP_DATAWRITE (1 << 10)
+#define AT91RM9200_MC_ABTTYP_FETCH (2 << 10)
+#define AT91RM9200_MC_MST0 (1 << 16) /* ARM920T Abort Source */
+#define AT91RM9200_MC_MST1 (1 << 17) /* PDC Abort Source */
+#define AT91RM9200_MC_MST2 (1 << 18) /* UHP Abort Source */
+#define AT91RM9200_MC_MST3 (1 << 19) /* EMAC Abort Source */
+#define AT91RM9200_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
+#define AT91RM9200_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
+#define AT91RM9200_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
+#define AT91RM9200_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
+
+#define AT91RM9200_MC_AASR (0x08) /* MC Abort Address Status Register */
+
+#define AT91RM9200_MC_MPR (0x0c) /* MC Master Priority Register */
+#define AT91RM9200_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
+#define AT91RM9200_MPR_MSTP1 (7 << 4) /* PDC Priority */
+#define AT91RM9200_MPR_MSTP2 (7 << 8) /* UHP Priority */
+#define AT91RM9200_MPR_MSTP3 (7 << 12) /* EMAC Priority */
/* External Bus Interface (EBI) registers */
-#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
-#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
-#define AT91_EBI_CS0A_SMC (0 << 0)
-#define AT91_EBI_CS0A_BFC (1 << 0)
-#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_EBI_CS1A_SMC (0 << 1)
-#define AT91_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
-#define AT91_EBI_CS3A_SMC (0 << 3)
-#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
-#define AT91_EBI_CS4A_SMC (0 << 4)
-#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
-#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
-#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
+#define AT91RM9200_EBI_CSA (0x60) /* Chip Select Assignment Register */
+#define AT91RM9200_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
+#define AT91RM9200_EBI_CS0A_SMC (0 << 0)
+#define AT91RM9200_EBI_CS0A_BFC (1 << 0)
+#define AT91RM9200_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91RM9200_EBI_CS1A_SMC (0 << 1)
+#define AT91RM9200_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91RM9200_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
+#define AT91RM9200_EBI_CS3A_SMC (0 << 3)
+#define AT91RM9200_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91RM9200_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
+#define AT91RM9200_EBI_CS4A_SMC (0 << 4)
+#define AT91RM9200_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
+#define AT91RM9200_EBI_CFGR (0x64) /* Configuration Register */
+#define AT91RM9200_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
-#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
-#define AT91_SMC_NWS_(x) ((x) << 0)
-#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
-#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
-#define AT91_SMC_TDF_(x) ((x) << 8)
-#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
-#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
-#define AT91_SMC_DBW_16 (1 << 13)
-#define AT91_SMC_DBW_8 (2 << 13)
-#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
-#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
-#define AT91_SMC_ACSS_STD (0 << 16)
-#define AT91_SMC_ACSS_1 (1 << 16)
-#define AT91_SMC_ACSS_2 (2 << 16)
-#define AT91_SMC_ACSS_3 (3 << 16)
-#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
-#define AT91_SMC_RWSETUP_(x) ((x) << 24)
-#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
-#define AT91_SMC_RWHOLD_(x) ((x) << 28)
+#define AT91RM9200_SMC_CSR(n) (0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define AT91RM9200_SMC_NWS (0x7f << 0) /* Number of Wait States */
+#define AT91RM9200_SMC_NWS_(x) ((x) << 0)
+#define AT91RM9200_SMC_WSEN (1 << 7) /* Wait State Enable */
+#define AT91RM9200_SMC_TDF (0xf << 8) /* Data Float Time */
+#define AT91RM9200_SMC_TDF_(x) ((x) << 8)
+#define AT91RM9200_SMC_BAT (1 << 12) /* Byte Access Type */
+#define AT91RM9200_SMC_DBW (3 << 13) /* Data Bus Width */
+#define AT91RM9200_SMC_DBW_16 (1 << 13)
+#define AT91RM9200_SMC_DBW_8 (2 << 13)
+#define AT91RM9200_SMC_DPR (1 << 15) /* Data Read Protocol */
+#define AT91RM9200_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
+#define AT91RM9200_SMC_ACSS_STD (0 << 16)
+#define AT91RM9200_SMC_ACSS_1 (1 << 16)
+#define AT91RM9200_SMC_ACSS_2 (2 << 16)
+#define AT91RM9200_SMC_ACSS_3 (3 << 16)
+#define AT91RM9200_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
+#define AT91RM9200_SMC_RWSETUP_(x) ((x) << 24)
+#define AT91RM9200_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
+#define AT91RM9200_SMC_RWHOLD_(x) ((x) << 28)
/* SDRAM Controller registers */
-#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
-#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
-#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
-#define AT91_SDRAMC_MODE_NOP (1 << 0)
-#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
-#define AT91_SDRAMC_MODE_LMR (3 << 0)
-#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
-#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
-#define AT91_SDRAMC_DBW_32 (0 << 4)
-#define AT91_SDRAMC_DBW_16 (1 << 4)
-
-#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
-#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
-
-#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
-#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
-#define AT91_SDRAMC_NC_8 (0 << 0)
-#define AT91_SDRAMC_NC_9 (1 << 0)
-#define AT91_SDRAMC_NC_10 (2 << 0)
-#define AT91_SDRAMC_NC_11 (3 << 0)
-#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
-#define AT91_SDRAMC_NR_11 (0 << 2)
-#define AT91_SDRAMC_NR_12 (1 << 2)
-#define AT91_SDRAMC_NR_13 (2 << 2)
-#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
-#define AT91_SDRAMC_NB_2 (0 << 4)
-#define AT91_SDRAMC_NB_4 (1 << 4)
-#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
-#define AT91_SDRAMC_CAS_2 (2 << 5)
-#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
-#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
-#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
-#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
-#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
-#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
-#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
-#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
-#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
-#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
-#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
+#define AT91RM9200_SDRAMC_MR (0x90) /* Mode Register */
+#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
+#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
+#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
+#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
+#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
+#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
+#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
+#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
+#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
+
+#define AT91RM9200_SDRAMC_TR (0x94) /* Refresh Timer Register */
+#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
+
+#define AT91RM9200_SDRAMC_CR (0x98) /* Configuration Register */
+#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
+#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
+#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
+#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
+#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
+#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
+#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
+#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
+#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
+#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
+#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
+#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
+#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
+#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
+#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
+#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
+#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
+#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
+#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
+#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
+
+#define AT91RM9200_SDRAMC_SRR (0x9c) /* Self Refresh Register */
+#define AT91RM9200_SDRAMC_LPR (0xa0) /* Low Power Register */
+#define AT91RM9200_SDRAMC_IER (0xa4) /* Interrupt Enable Register */
+#define AT91RM9200_SDRAMC_IDR (0xa8) /* Interrupt Disable Register */
+#define AT91RM9200_SDRAMC_IMR (0xac) /* Interrupt Mask Register */
+#define AT91RM9200_SDRAMC_ISR (0xb0) /* Interrupt Status Register */
/* Burst Flash Controller register */
-#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
-#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
-#define AT91_BFC_BFCOM_DISABLED (0 << 0)
-#define AT91_BFC_BFCOM_ASYNC (1 << 0)
-#define AT91_BFC_BFCOM_BURST (2 << 0)
-#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
-#define AT91_BFC_BFCC_MCK (1 << 2)
-#define AT91_BFC_BFCC_DIV2 (2 << 2)
-#define AT91_BFC_BFCC_DIV4 (3 << 2)
-#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
-#define AT91_BFC_PAGES (7 << 8) /* Page Size */
-#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
-#define AT91_BFC_PAGES_16 (1 << 8)
-#define AT91_BFC_PAGES_32 (2 << 8)
-#define AT91_BFC_PAGES_64 (3 << 8)
-#define AT91_BFC_PAGES_128 (4 << 8)
-#define AT91_BFC_PAGES_256 (5 << 8)
-#define AT91_BFC_PAGES_512 (6 << 8)
-#define AT91_BFC_PAGES_1024 (7 << 8)
-#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
-#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
-#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
-#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
-#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
+#define AT91RM9200_BFC_MR (0xc0) /* Mode Register */
+#define AT91RM9200_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
+#define AT91RM9200_BFC_BFCOM_DISABLED (0 << 0)
+#define AT91RM9200_BFC_BFCOM_ASYNC (1 << 0)
+#define AT91RM9200_BFC_BFCOM_BURST (2 << 0)
+#define AT91RM9200_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
+#define AT91RM9200_BFC_BFCC_MCK (1 << 2)
+#define AT91RM9200_BFC_BFCC_DIV2 (2 << 2)
+#define AT91RM9200_BFC_BFCC_DIV4 (3 << 2)
+#define AT91RM9200_BFC_AVL (0xf << 4) /* Address Valid Latency */
+#define AT91RM9200_BFC_PAGES (7 << 8) /* Page Size */
+#define AT91RM9200_BFC_PAGES_NO_PAGE (0 << 8)
+#define AT91RM9200_BFC_PAGES_16 (1 << 8)
+#define AT91RM9200_BFC_PAGES_32 (2 << 8)
+#define AT91RM9200_BFC_PAGES_64 (3 << 8)
+#define AT91RM9200_BFC_PAGES_128 (4 << 8)
+#define AT91RM9200_BFC_PAGES_256 (5 << 8)
+#define AT91RM9200_BFC_PAGES_512 (6 << 8)
+#define AT91RM9200_BFC_PAGES_1024 (7 << 8)
+#define AT91RM9200_BFC_OEL (3 << 12) /* Output Enable Latency */
+#define AT91RM9200_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
+#define AT91RM9200_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
+#define AT91RM9200_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
+#define AT91RM9200_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
#ifndef __ASSEMBLY__
-#include <mach/io.h>
+#include <io.h>
+#include <mach/at91rm9200.h>
static inline u32 at91rm9200_get_sdram_size(void)
{
u32 cr, mr;
u32 size;
- cr = at91_sys_read(AT91_SDRAMC_CR);
- mr = at91_sys_read(AT91_SDRAMC_MR);
+ cr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_CR);
+ mr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_MR);
/* Formula:
* size = bank << (col + row + 1);
@@ -174,13 +175,13 @@ static inline u32 at91rm9200_get_sdram_size(void)
*/
size = 1;
/* COL */
- size += (cr & AT91_SDRAMC_NC) + 8;
+ size += (cr & AT91RM9200_SDRAMC_NC) + 8;
/* ROW */
- size += ((cr & AT91_SDRAMC_NR) >> 2) + 11;
+ size += ((cr & AT91RM9200_SDRAMC_NR) >> 2) + 11;
/* BANK */
- size = ((cr & AT91_SDRAMC_NB) ? 4 : 2) << size;
+ size = ((cr & AT91RM9200_SDRAMC_NB) ? 4 : 2) << size;
/* bandwidth */
- if (!(mr & AT91_SDRAMC_DBW))
+ if (!(mr & AT91RM9200_SDRAMC_DBW))
size <<= 1;
return size;
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_st.h b/arch/arm/mach-at91/include/mach/at91rm9200_st.h
new file mode 100644
index 0000000..bd676a7
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_st.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_st.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * System Timer (ST) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_ST_H
+#define AT91RM9200_ST_H
+
+#define AT91RM9200_ST_CR (0x00) /* Control Register */
+#define AT91RM9200_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
+
+#define AT91RM9200_ST_PIMR (0x04) /* Period Interval Mode Register */
+#define AT91RM9200_ST_PIV (0xffff << 0) /* Period Interval Value */
+
+#define AT91RM9200_ST_WDMR (0x08) /* Watchdog Mode Register */
+#define AT91RM9200_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
+#define AT91RM9200_ST_RSTEN (1 << 16) /* Reset Enable */
+#define AT91RM9200_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
+
+#define AT91RM9200_ST_RTMR (0x0c) /* Real-time Mode Register */
+#define AT91RM9200_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
+
+#define AT91RM9200_ST_SR (0x10) /* Status Register */
+#define AT91RM9200_ST_PITS (1 << 0) /* Period Interval Timer Status */
+#define AT91RM9200_ST_WDOVF (1 << 1) /* Watchdog Overflow */
+#define AT91RM9200_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
+#define AT91RM9200_ST_ALMS (1 << 3) /* Alarm Status */
+
+#define AT91RM9200_ST_IER (0x14) /* Interrupt Enable Register */
+#define AT91RM9200_ST_IDR (0x18) /* Interrupt Disable Register */
+#define AT91RM9200_ST_IMR (0x1c) /* Interrupt Mask Register */
+
+#define AT91RM9200_ST_RTAR (0x20) /* Real-time Alarm Register */
+#define AT91RM9200_ST_ALMV (0xfffff << 0) /* Alarm Value */
+
+#define AT91RM9200_ST_CRTR (0x24) /* Current Real-time Register */
+#define AT91RM9200_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 919901d..708e661 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
@@ -75,7 +73,6 @@
#define AT91SAM9260_BASE_TC4 0xfffdc040
#define AT91SAM9260_BASE_TC5 0xfffdc080
#define AT91SAM9260_BASE_ADC 0xfffe0000
-#define AT91_BASE_SYS 0xffffe800
/*
* System Peripherals
@@ -96,38 +93,6 @@
#define AT91SAM9260_BASE_GPBR 0xfffffd50
/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-
-#define AT91_BASE_WDT AT91SAM9260_BASE_WDT
-#define AT91_BASE_SMC AT91SAM9260_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
-#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9260_BASE_PIOC
-
-#define AT91_USART0 AT91SAM9260_BASE_US0
-#define AT91_USART1 AT91SAM9260_BASE_US1
-#define AT91_USART2 AT91SAM9260_BASE_US2
-#define AT91_USART3 AT91SAM9260_BASE_US3
-#define AT91_USART4 AT91SAM9260_BASE_US4
-#define AT91_USART5 AT91SAM9260_BASE_US5
-#define AT91_NB_USART 7
-
-#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0
-#define AT91_BASE_TWI AT91SAM9260_BASE_TWI
-#define AT91_ID_UHP AT91SAM9260_ID_UHP
-#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
-
-#define AT91_PMC 0xfffffc00
-
-/*
* Internal Memory.
*/
#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
@@ -157,13 +122,4 @@
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
-/*
- * Cpu Name
- */
-#if defined(CONFIG_AT91SAM9260)
-#define AT91_CPU_NAME "AT91SAM9260"
-#elif defined(CONFIG_AT91SAM9G20)
-#define AT91_CPU_NAME "AT91SAM9G20"
-#endif
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index 020f02e..792afa3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -15,66 +15,66 @@
#ifndef AT91SAM9260_MATRIX_H
#define AT91SAM9260_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9260_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9260_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9260_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9260_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9260_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9260_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9260_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9260_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9260_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9260_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9260_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9260_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+#define AT91SAM9260_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9260_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9260_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9260_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9260_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9260_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9260_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9260_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+#define AT91SAM9260_MATRIX_ARBT (3 << 24) /* Arbitration Type */
+#define AT91SAM9260_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91SAM9260_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9260_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9260_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9260_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9260_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9260_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9260_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9260_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9260_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9260_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9260_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9260_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9260_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9260_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9260_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9260_MATRIX_EBICSA (0x11C) /* EBI Chip Select Assignment Register */
+#define AT91SAM9260_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9260_MATRIX_CS1A_SMC (0 << 1)
+#define AT91SAM9260_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9260_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9260_MATRIX_CS3A_SMC (0 << 3)
+#define AT91SAM9260_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9260_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91SAM9260_MATRIX_CS4A_SMC (0 << 4)
+#define AT91SAM9260_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91SAM9260_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91SAM9260_MATRIX_CS5A_SMC (0 << 5)
+#define AT91SAM9260_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91SAM9260_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9260_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9260_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9260_MATRIX_VDDIOMSEL_3_3V (1 << 16)
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 9124df5..df948d3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
@@ -62,7 +60,6 @@
#define AT91SAM9261_BASE_SSC2 0xfffc4000
#define AT91SAM9261_BASE_SPI0 0xfffc8000
#define AT91SAM9261_BASE_SPI1 0xfffcc000
-#define AT91_BASE_SYS 0xffffea00
/*
@@ -83,28 +80,6 @@
#define AT91SAM9261_BASE_GPBR 0xfffffd50
/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-
-#define AT91_BASE_WDT AT91SAM9261_BASE_WDT
-#define AT91_BASE_SMC AT91SAM9261_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9261_BASE_PIOC
-
-#define AT91_USART0 AT91SAM9261_BASE_US0
-#define AT91_USART1 AT91SAM9261_BASE_US1
-#define AT91_USART2 AT91SAM9261_BASE_US2
-#define AT91_NB_USART 4
-
-#define AT91_PMC 0xfffffc00
-
-/*
* Internal Memory.
*/
#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
@@ -119,9 +94,4 @@
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
-/*
- * Cpu Name
- */
-#define AT91_CPU_NAME "AT91SAM9261"
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index 7de0157..63e92cc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -15,50 +15,50 @@
#ifndef AT91SAM9261_MATRIX_H
#define AT91SAM9261_MATRIX_H
-#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9261_MATRIX_MCFG (0x00) /* Master Configuration Register */
+#define AT91SAM9261_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9261_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+#define AT91SAM9261_MATRIX_SCFG0 (0x04) /* Slave Configuration Register 0 */
+#define AT91SAM9261_MATRIX_SCFG1 (0x08) /* Slave Configuration Register 1 */
+#define AT91SAM9261_MATRIX_SCFG2 (0x0C) /* Slave Configuration Register 2 */
+#define AT91SAM9261_MATRIX_SCFG3 (0x10) /* Slave Configuration Register 3 */
+#define AT91SAM9261_MATRIX_SCFG4 (0x14) /* Slave Configuration Register 4 */
+#define AT91SAM9261_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9261_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9261_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
-#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
-#define AT91_MATRIX_ITCM_0 (0 << 0)
-#define AT91_MATRIX_ITCM_16 (5 << 0)
-#define AT91_MATRIX_ITCM_32 (6 << 0)
-#define AT91_MATRIX_ITCM_64 (7 << 0)
-#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
-#define AT91_MATRIX_DTCM_0 (0 << 4)
-#define AT91_MATRIX_DTCM_16 (5 << 4)
-#define AT91_MATRIX_DTCM_32 (6 << 4)
-#define AT91_MATRIX_DTCM_64 (7 << 4)
+#define AT91SAM9261_MATRIX_TCR (0x24) /* TCM Configuration Register */
+#define AT91SAM9261_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91SAM9261_MATRIX_ITCM_0 (0 << 0)
+#define AT91SAM9261_MATRIX_ITCM_16 (5 << 0)
+#define AT91SAM9261_MATRIX_ITCM_32 (6 << 0)
+#define AT91SAM9261_MATRIX_ITCM_64 (7 << 0)
+#define AT91SAM9261_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91SAM9261_MATRIX_DTCM_0 (0 << 4)
+#define AT91SAM9261_MATRIX_DTCM_16 (5 << 4)
+#define AT91SAM9261_MATRIX_DTCM_32 (6 << 4)
+#define AT91SAM9261_MATRIX_DTCM_64 (7 << 4)
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9261_MATRIX_EBICSA (0x30) /* EBI Chip Select Assignment Register */
+#define AT91SAM9261_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9261_MATRIX_CS1A_SMC (0 << 1)
+#define AT91SAM9261_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9261_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9261_MATRIX_CS3A_SMC (0 << 3)
+#define AT91SAM9261_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9261_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91SAM9261_MATRIX_CS4A_SMC (0 << 4)
+#define AT91SAM9261_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91SAM9261_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91SAM9261_MATRIX_CS5A_SMC (0 << 5)
+#define AT91SAM9261_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91SAM9261_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
-#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
+#define AT91SAM9261_MATRIX_USBPUCR (0x34) /* USB Pad Pull-Up Control Register */
+#define AT91SAM9261_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index e7ca8b6..a357ea8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
@@ -72,7 +70,6 @@
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
-#define AT91_BASE_SYS 0xffffe000
/*
@@ -100,38 +97,6 @@
#define AT91SAM9263_BASE_GPBR 0xfffffd60
/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
-#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
-#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-
-#define AT91_BASE_WDT AT91SAM9263_BASE_WDT
-#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0
-#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9263_BASE_PIOC
-#define AT91_BASE_PIOD AT91SAM9263_BASE_PIOD
-#define AT91_BASE_PIOE AT91SAM9263_BASE_PIOE
-
-#define AT91_USART0 AT91SAM9263_BASE_US0
-#define AT91_USART1 AT91SAM9263_BASE_US1
-#define AT91_USART2 AT91SAM9263_BASE_US2
-#define AT91_NB_USART 4
-
-#define AT91_SDRAMC AT91_SDRAMC0
-
-#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0
-#define AT91_BASE_TWI AT91SAM9263_BASE_TWI
-#define AT91_ID_UHP AT91SAM9263_ID_UHP
-#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
-
-#define AT91_PMC 0xfffffc00
-
-/*
* Internal Memory.
*/
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
@@ -147,9 +112,4 @@
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
-/*
- * Cpu Name
- */
-#define AT91_CPU_NAME "AT91SAM9263"
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 83aaaab..0082666 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -15,115 +15,115 @@
#ifndef AT91SAM9263_MATRIX_H
#define AT91SAM9263_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9263_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9263_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9263_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9263_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9263_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9263_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9263_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */
+#define AT91SAM9263_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */
+#define AT91SAM9263_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */
+#define AT91SAM9263_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9263_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9263_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9263_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9263_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+#define AT91SAM9263_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9263_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9263_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9263_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9263_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9263_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */
+#define AT91SAM9263_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */
+#define AT91SAM9263_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */
+#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9263_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9263_MATRIX_ARBT (3 << 24) /* Arbitration Type */
+#define AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
-#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
-#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91SAM9263_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9263_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */
+#define AT91SAM9263_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9263_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */
+#define AT91SAM9263_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9263_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */
+#define AT91SAM9263_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9263_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */
+#define AT91SAM9263_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9263_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */
+#define AT91SAM9263_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */
+#define AT91SAM9263_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */
+#define AT91SAM9263_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */
+#define AT91SAM9263_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */
+#define AT91SAM9263_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */
+#define AT91SAM9263_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */
+#define AT91SAM9263_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9263_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9263_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9263_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9263_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9263_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9263_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91SAM9263_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91SAM9263_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
+#define AT91SAM9263_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9263_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9263_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9263_MATRIX_RCB2 (1 << 2)
+#define AT91SAM9263_MATRIX_RCB3 (1 << 3)
+#define AT91SAM9263_MATRIX_RCB4 (1 << 4)
+#define AT91SAM9263_MATRIX_RCB5 (1 << 5)
+#define AT91SAM9263_MATRIX_RCB6 (1 << 6)
+#define AT91SAM9263_MATRIX_RCB7 (1 << 7)
+#define AT91SAM9263_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
-#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
-#define AT91_MATRIX_ITCM_0 (0 << 0)
-#define AT91_MATRIX_ITCM_16 (5 << 0)
-#define AT91_MATRIX_ITCM_32 (6 << 0)
-#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
-#define AT91_MATRIX_DTCM_0 (0 << 4)
-#define AT91_MATRIX_DTCM_16 (5 << 4)
-#define AT91_MATRIX_DTCM_32 (6 << 4)
+#define AT91SAM9263_MATRIX_TCMR (0x114) /* TCM Configuration Register */
+#define AT91SAM9263_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91SAM9263_MATRIX_ITCM_0 (0 << 0)
+#define AT91SAM9263_MATRIX_ITCM_16 (5 << 0)
+#define AT91SAM9263_MATRIX_ITCM_32 (6 << 0)
+#define AT91SAM9263_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91SAM9263_MATRIX_DTCM_0 (0 << 4)
+#define AT91SAM9263_MATRIX_DTCM_16 (5 << 4)
+#define AT91SAM9263_MATRIX_DTCM_32 (6 << 4)
-#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
-#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9263_MATRIX_EBI0CSA (0x120) /* EBI0 Chip Select Assignment Register */
+#define AT91SAM9263_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9263_MATRIX_EBI0_CS1A_SMC (0 << 1)
+#define AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9263_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9263_MATRIX_EBI0_CS3A_SMC (0 << 3)
+#define AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9263_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91SAM9263_MATRIX_EBI0_CS4A_SMC (0 << 4)
+#define AT91SAM9263_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
+#define AT91SAM9263_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91SAM9263_MATRIX_EBI0_CS5A_SMC (0 << 5)
+#define AT91SAM9263_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
+#define AT91SAM9263_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
-#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
-#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
-#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9263_MATRIX_EBI1CSA (0x124) /* EBI1 Chip Select Assignment Register */
+#define AT91SAM9263_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9263_MATRIX_EBI1_CS1A_SMC (0 << 1)
+#define AT91SAM9263_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9263_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9263_MATRIX_EBI1_CS2A_SMC (0 << 3)
+#define AT91SAM9263_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9263_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x.h b/arch/arm/mach-at91/include/mach/at91sam926x.h
new file mode 100644
index 0000000..ab5cf51
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam926x.h
@@ -0,0 +1,8 @@
+#ifndef __MACH_AT91SAM926X_H
+#define __MACH_AT91SAM926X_H
+
+#define AT91SAM926X_BASE_PMC 0xfffffc00
+#define AT91SAM926X_BASE_RSTC 0xfffffd00
+#define AT91SAM926X_BASE_WDT 0xfffffd40
+
+#endif /* __MACH_AT91SAM926X_H */
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index 70ae903..9ab0eef 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -18,13 +18,14 @@
#include <mach/at91_wdt.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
+#include <mach/at91sam926x.h>
struct at91sam926x_board_cfg {
/* SoC specific */
void __iomem *pio;
void __iomem *sdramc;
u32 ebi_pio_is_peripha;
- u32 matrix_csa;
+ void __iomem *matrix_csa;
/* board specific */
u32 wdt_mr;
@@ -50,7 +51,7 @@ struct at91sam926x_board_cfg {
static void __always_inline access_sdram(void)
{
- writel(0x00000000, AT91_SDRAM_BASE);
+ writel(0x00000000, AT91_CHIPSELECT_1);
}
static void __always_inline pmc_check_mckrdy(void)
@@ -58,7 +59,7 @@ static void __always_inline pmc_check_mckrdy(void)
u32 r;
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = readl(AT91SAM926X_BASE_PMC + AT91_PMC_SR);
} while (!(r & AT91_PMC_MCKRDY));
}
@@ -82,49 +83,51 @@ static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg
return;
/* SDRAMC_MR : Normal Mode */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_NORMAL);
+ __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
/* SDRAMC_TR - Refresh Timer register */
- __raw_writel(AT91_SDRAMC_TR, cfg->sdramc + cfg->sdrc_tr1);
+ __raw_writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR);
/* SDRAMC_CR - Configuration register*/
- __raw_writel(AT91_SDRAMC_CR, cfg->sdramc + cfg->sdrc_cr);
+ __raw_writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR);
/* Memory Device Type */
- __raw_writel(AT91_SDRAMC_MDR, cfg->sdramc + cfg->sdrc_mdr);
+ __raw_writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR);
/* SDRAMC_MR : Precharge All */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_PRECHARGE);
+ __raw_writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR);
access_sdram();
/* SDRAMC_MR : refresh */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_REFRESH);
+ __raw_writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR);
/* access SDRAM 8 times */
for (i = 0; i < 8; i++)
access_sdram();
/* SDRAMC_MR : Load Mode Register */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_LMR);
+ __raw_writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR);
access_sdram();
/* SDRAMC_MR : Normal Mode */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_NORMAL);
+ __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
access_sdram();
/* SDRAMC_TR : Refresh Timer Counter */
- __raw_writel(AT91_SDRAMC_TR, cfg->sdramc + cfg->sdrc_tr2);
+ __raw_writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR);
access_sdram();
}
-static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg *cfg)
+static void __always_inline at91sam926x_board_init(void __iomem *smcbase,
+ struct at91sam926x_board_cfg *cfg)
{
u32 r;
+ void __iomem *pmc = IOMEM(AT91SAM926X_BASE_PMC);
if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT))
return;
- __raw_writel(cfg->wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
+ __raw_writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR);
/* configure PIOx as EBI0 D[16-31] */
at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr);
@@ -132,44 +135,44 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
if (cfg->ebi_pio_is_peripha)
at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr);
- at91_sys_write(cfg->matrix_csa, cfg->ebi_csa);
+ writel(cfg->ebi_csa, cfg->matrix_csa);
/* flash */
- at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode);
- at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle);
- at91_smc_write(cfg->smc_cs, AT91_SMC_PULSE, cfg->smc_pulse);
- at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup);
+ writel(cfg->smc_mode, smcbase + cfg->smc_cs * 0x10 + AT91_SAM9_SMC_MODE);
+ writel(cfg->smc_cycle, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_CYCLE);
+ writel(cfg->smc_pulse, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_PULSE);
+ writel(cfg->smc_setup, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_SETUP);
/* PMC Check if the PLL is already initialized */
- r = at91_pmc_read(AT91_PMC_MCKR);
+ r = readl(pmc + AT91_PMC_MCKR);
if ((r & AT91_PMC_CSS) && !running_in_sram())
return;
/* Enable the Main Oscillator */
- at91_pmc_write(AT91_CKGR_MOR, cfg->pmc_mor);
+ writel(cfg->pmc_mor, pmc + AT91_CKGR_MOR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/* PLLAR: x MHz for PCK */
- at91_pmc_write(AT91_CKGR_PLLAR, cfg->pmc_pllar);
+ writel(cfg->pmc_pllar, pmc + AT91_CKGR_PLLAR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/* PCK/x = MCK Master Clock from SLOW */
- at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr1);
+ writel(cfg->pmc_mckr1, pmc + AT91_PMC_MCKR);
pmc_check_mckrdy();
/* PCK/x = MCK Master Clock from PLLA */
- at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr2);
+ writel(cfg->pmc_mckr2, pmc + AT91_PMC_MCKR);
pmc_check_mckrdy();
/* Init SDRAM */
at91sam926x_sdramc_init(cfg);
/* User reset enable*/
- at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr);
+ writel(cfg->rstc_rmr, AT91SAM926X_BASE_RSTC + AT91_RSTC_MR);
/*
* When boot from external boot
@@ -177,7 +180,31 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
* so enable all of them
* We will shutdown what we don't need later
*/
- at91_pmc_write(AT91_PMC_PCER, 0xffffffff);
+ writel(0xffffffff, pmc + AT91_PMC_PCER);
}
+#if defined CONFIG_ARCH_AT91SAM9260
+#include <mach/at91sam9260.h>
+static void __always_inline at91sam9260_board_init(struct at91sam926x_board_cfg *cfg)
+{
+ at91sam926x_board_init(IOMEM(AT91SAM9260_BASE_SMC), cfg);
+}
+#endif
+
+#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10
+#include <mach/at91sam9261.h>
+static void __always_inline at91sam9261_board_init(struct at91sam926x_board_cfg *cfg)
+{
+ at91sam926x_board_init(IOMEM(AT91SAM9261_BASE_SMC), cfg);
+}
+#endif
+
+#if defined CONFIG_ARCH_AT91SAM9263
+#include <mach/at91sam9263.h>
+static void __always_inline at91sam9263_board_init(struct at91sam926x_board_cfg *cfg)
+{
+ at91sam926x_board_init(IOMEM(AT91SAM9263_BASE_SMC0), cfg);
+}
+#endif
+
#endif /* __AT91SAM926X_BOARD_INIT_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index 88796a6..1c4d313 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -136,7 +136,7 @@ Banks [not SAM9G45] */
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
#ifndef __ASSEMBLY__
-#include <mach/io.h>
+#include <io.h>
static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
{
@@ -176,6 +176,7 @@ static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
}
#ifdef CONFIG_SOC_AT91SAM9G45
+#include <mach/at91sam9g45.h>
static inline u32 at91sam9g45_get_ddram_size(int bank)
{
switch (bank) {
@@ -195,6 +196,7 @@ static inline u32 at91sam9g45_get_ddram_size(int bank)
#endif
#ifdef CONFIG_SOC_AT91SAM9X5
+#include <mach/at91sam9x5.h>
static inline u32 at91sam9x5_get_ddram_size(void)
{
return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true);
@@ -207,6 +209,7 @@ static inline u32 at91sam9x5_get_ddram_size(void)
#endif
#ifdef CONFIG_SOC_AT91SAM9N12
+#include <mach/at91sam9n12.h>
static inline u32 at91sam9n12_get_ddram_size(void)
{
return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true);
@@ -219,6 +222,7 @@ static inline u32 at91sam9n12_get_ddram_size(void)
#endif
#ifdef CONFIG_SOC_SAMA5
+#include <mach/sama5d3.h>
static inline u32 at91sama5_get_ddram_size(void)
{
u32 cr;
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h
deleted file mode 100644
index 1d1d905..0000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_matrix.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H
-#define __ASM_ARCH_AT91SAM9_MATRIX_H
-
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
-#include <mach/at91sam9260_matrix.h>
-#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
-#include <mach/at91sam9261_matrix.h>
-#elif defined(CONFIG_ARCH_AT91SAM9263)
-#include <mach/at91sam9263_matrix.h>
-#elif defined(CONFIG_ARCH_AT91SAM9RL)
-#include <mach/at91sam9rl_matrix.h>
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91cap9_matrix.h>
-#elif defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9M10G45)
-#include <mach/at91sam9g45_matrix.h>
-#else
-#error "Unsupported AT91SAM9/CAP9 processor"
-#endif
-
-#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 91efa67..8595f9c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -84,7 +84,7 @@
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
#ifndef __ASSEMBLY__
-#include <mach/io.h>
+#include <io.h>
static inline u32 at91_get_sdram_size(void *base)
{
u32 val;
@@ -118,6 +118,7 @@ static inline bool at91_is_low_power_sdram(void *base)
}
#ifdef CONFIG_SOC_AT91SAM9260
+#include <mach/at91sam9260.h>
static inline u32 at91sam9260_get_sdram_size(void)
{
return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC));
@@ -140,6 +141,7 @@ static inline bool at91sam9260_is_low_power_sdram(void)
#endif
#ifdef CONFIG_SOC_AT91SAM9261
+#include <mach/at91sam9261.h>
static inline u32 at91sam9261_get_sdram_size(void)
{
return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC));
@@ -162,6 +164,7 @@ static inline bool at91sam9261_is_low_power_sdram(void)
#endif
#ifdef CONFIG_SOC_AT91SAM9263
+#include <mach/at91sam9263.h>
static inline u32 at91sam9263_get_sdram_size(int bank)
{
switch (bank) {
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index d19cf82..0908f6d 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -16,12 +16,6 @@
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
-#define at91_smc_read(id, field) \
- __raw_readl(AT91_BASE_SMC + ((id) * 0x10) + field)
-
-#define at91_smc_write(id, field, value) \
- __raw_writel(value, AT91_BASE_SMC + ((id) * 0x10) + field)
-
#ifndef __ASSEMBLY__
struct sam9_smc_config {
/* Setup register */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index ff12ce4..f79df0b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Controller Interrupt */
#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
@@ -84,7 +82,6 @@
#define AT91SAM9G45_BASE_TC3 0xfffd4000
#define AT91SAM9G45_BASE_TC4 0xfffd4040
#define AT91SAM9G45_BASE_TC5 0xfffd4080
-#define AT91_BASE_SYS 0xffffe200
/*
* System Peripherals
@@ -110,33 +107,6 @@
#define AT91SAM9G45_BASE_GPBR 0xfffffd60
/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
-#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
-#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
-#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-
-#define AT91_BASE_WDT AT91SAM9G45_BASE_WDT
-#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOC
-#define AT91_BASE_PIOD AT91SAM9G45_BASE_PIOD
-#define AT91_BASE_PIOE AT91SAM9G45_BASE_PIOE
-
-#define AT91_USART0 AT91SAM9G45_BASE_US0
-#define AT91_USART1 AT91SAM9G45_BASE_US1
-#define AT91_USART2 AT91SAM9G45_BASE_US2
-#define AT91_USART3 AT91SAM9G45_BASE_US3
-#define AT91_NB_USART 5
-
-#define AT91_PMC 0xfffffc00
-
-/*
* Internal Memory.
*/
#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
@@ -151,30 +121,4 @@
#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
-#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
-
-#define CONSISTENT_DMA_SIZE SZ_4M
-
-/*
- * DMA peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI0 0
-#define AT_DMA_ID_SPI0_TX 1
-#define AT_DMA_ID_SPI0_RX 2
-#define AT_DMA_ID_SPI1_TX 3
-#define AT_DMA_ID_SPI1_RX 4
-#define AT_DMA_ID_SSC0_TX 5
-#define AT_DMA_ID_SSC0_RX 6
-#define AT_DMA_ID_SSC1_TX 7
-#define AT_DMA_ID_SSC1_RX 8
-#define AT_DMA_ID_AC97_TX 9
-#define AT_DMA_ID_AC97_RX 10
-#define AT_DMA_ID_MCI1 13
-
-/*
- * Cpu Name
- */
-#define AT91_CPU_NAME "AT91SAM9G45"
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
index c972d60..53f50fe 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -15,139 +15,139 @@
#ifndef AT91SAM9G45_MATRIX_H
#define AT91SAM9G45_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
-#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
-#define AT91_MATRIX_ULBT_128 (7 << 0)
+#define AT91SAM9G45_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9G45_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9G45_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9G45_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9G45_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9G45_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9G45_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */
+#define AT91SAM9G45_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */
+#define AT91SAM9G45_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */
+#define AT91SAM9G45_MATRIX_MCFG9 (0x24) /* Master Configuration Register 9 */
+#define AT91SAM9G45_MATRIX_MCFG10 (0x28) /* Master Configuration Register 10 */
+#define AT91SAM9G45_MATRIX_MCFG11 (0x2C) /* Master Configuration Register 11 */
+#define AT91SAM9G45_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9G45_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_128 (7 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9G45_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9G45_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9G45_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9G45_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9G45_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9G45_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */
+#define AT91SAM9G45_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */
+#define AT91SAM9G45_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */
+#define AT91SAM9G45_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9G45_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
-#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
-#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
-#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
-#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
+#define AT91SAM9G45_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9G45_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */
+#define AT91SAM9G45_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9G45_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */
+#define AT91SAM9G45_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9G45_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */
+#define AT91SAM9G45_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9G45_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */
+#define AT91SAM9G45_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9G45_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */
+#define AT91SAM9G45_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */
+#define AT91SAM9G45_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */
+#define AT91SAM9G45_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */
+#define AT91SAM9G45_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */
+#define AT91SAM9G45_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */
+#define AT91SAM9G45_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */
+#define AT91SAM9G45_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9G45_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9G45_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9G45_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9G45_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9G45_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9G45_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91SAM9G45_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91SAM9G45_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91SAM9G45_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
+#define AT91SAM9G45_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
+#define AT91SAM9G45_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_RCB9 (1 << 9)
-#define AT91_MATRIX_RCB10 (1 << 10)
-#define AT91_MATRIX_RCB11 (1 << 11)
+#define AT91SAM9G45_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9G45_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9G45_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9G45_MATRIX_RCB2 (1 << 2)
+#define AT91SAM9G45_MATRIX_RCB3 (1 << 3)
+#define AT91SAM9G45_MATRIX_RCB4 (1 << 4)
+#define AT91SAM9G45_MATRIX_RCB5 (1 << 5)
+#define AT91SAM9G45_MATRIX_RCB6 (1 << 6)
+#define AT91SAM9G45_MATRIX_RCB7 (1 << 7)
+#define AT91SAM9G45_MATRIX_RCB8 (1 << 8)
+#define AT91SAM9G45_MATRIX_RCB9 (1 << 9)
+#define AT91SAM9G45_MATRIX_RCB10 (1 << 10)
+#define AT91SAM9G45_MATRIX_RCB11 (1 << 11)
-#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */
-#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
-#define AT91_MATRIX_ITCM_0 (0 << 0)
-#define AT91_MATRIX_ITCM_32 (6 << 0)
-#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
-#define AT91_MATRIX_DTCM_0 (0 << 4)
-#define AT91_MATRIX_DTCM_32 (6 << 4)
-#define AT91_MATRIX_DTCM_64 (7 << 4)
-#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
-#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
-#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
+#define AT91SAM9G45_MATRIX_TCMR (0x110) /* TCM Configuration Register */
+#define AT91SAM9G45_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91SAM9G45_MATRIX_ITCM_0 (0 << 0)
+#define AT91SAM9G45_MATRIX_ITCM_32 (6 << 0)
+#define AT91SAM9G45_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91SAM9G45_MATRIX_DTCM_0 (0 << 4)
+#define AT91SAM9G45_MATRIX_DTCM_32 (6 << 4)
+#define AT91SAM9G45_MATRIX_DTCM_64 (7 << 4)
+#define AT91SAM9G45_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
+#define AT91SAM9G45_MATRIX_TCM_NO_WS (0x0 << 11)
+#define AT91SAM9G45_MATRIX_TCM_ONE_WS (0x1 << 11)
-#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */
+#define AT91SAM9G45_MATRIX_VIDEO (0x118) /* Video Mode Configuration Register */
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
#define AT91C_VDEC_SEL_OFF (0 << 0)
#define AT91C_VDEC_SEL_ON (1 << 0)
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
-#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
-#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
-#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
-#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
-#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
-#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
-#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
-#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
-#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
+#define AT91SAM9G45_MATRIX_EBICSA (0x128) /* EBI Chip Select Assignment Register */
+#define AT91SAM9G45_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9G45_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91SAM9G45_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9G45_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9G45_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91SAM9G45_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9G45_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91SAM9G45_MATRIX_EBI_CS4A_SMC (0 << 4)
+#define AT91SAM9G45_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
+#define AT91SAM9G45_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91SAM9G45_MATRIX_EBI_CS5A_SMC (0 << 5)
+#define AT91SAM9G45_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
+#define AT91SAM9G45_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9G45_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91SAM9G45_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
+#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
+#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
+#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
+#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
+#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
-#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
-#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
-#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
-#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
-#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
+#define AT91SAM9G45_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */
+#define AT91SAM9G45_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
+#define AT91SAM9G45_MATRIX_WPMR_WP_WPDIS (0 << 0)
+#define AT91SAM9G45_MATRIX_WPMR_WP_WPEN (1 << 0)
+#define AT91SAM9G45_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
-#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
-#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
-#define AT91_MATRIX_WPSR_WPV (1 << 0)
-#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
+#define AT91SAM9G45_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */
+#define AT91SAM9G45_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
+#define AT91SAM9G45_MATRIX_WPSR_NO_WPV (0 << 0)
+#define AT91SAM9G45_MATRIX_WPSR_WPV (1 << 0)
+#define AT91SAM9G45_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index 249bde4..dd9c0fc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Controller Interrupt */
#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
/* Reserved 4 */
@@ -79,7 +77,6 @@
#define AT91SAM9N12_BASE_UART1 0xf8044000
#define AT91SAM9N12_BASE_TRNG 0xf8048000
#define AT91SAM9N12_BASE_ADC 0xf804c000
-#define AT91_BASE_SYS 0xffffc000
/*
* System Peripherals
@@ -106,32 +103,6 @@
#define AT91SAM9N12_BASE_RTC 0xfffffeb0
/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)
-#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
-#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-
-#define AT91_BASE_WDT AT91SAM9N12_BASE_WDT
-#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC
-#define AT91_BASE_PIOD AT91SAM9N12_BASE_PIOD
-
-#define AT91_USART0 AT91SAM9X5_BASE_US0
-#define AT91_USART1 AT91SAM9X5_BASE_US1
-#define AT91_USART2 AT91SAM9X5_BASE_US2
-#define AT91_USART3 AT91SAM9X5_BASE_US3
-#define AT91_NB_USART 5
-
-#define AT91_PMC 0xfffffc00
-
-/*
* Internal Memory.
*/
#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
@@ -143,42 +114,4 @@
#define AT91SAM9N12_SMD_BASE 0x00400000 /* SMD Controller */
#define AT91SAM9N12_OHCI_BASE 0x00500000 /* USB Host controller (OHCI) */
-#define CONFIG_DRAM_BASE AT91_CHIPSELECT_1
-
-#define CONSISTENT_DMA_SIZE (14 * SZ_1M)
-
-/*
- * DMA0 peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI 0
-#define AT_DMA_ID_SPI0_TX 1
-#define AT_DMA_ID_SPI0_RX 2
-#define AT_DMA_ID_SPI1_TX 3
-#define AT_DMA_ID_SPI1_RX 4
-#define AT_DMA_ID_USART0_TX 5
-#define AT_DMA_ID_USART0_RX 6
-#define AT_DMA_ID_USART1_TX 7
-#define AT_DMA_ID_USART1_RX 8
-#define AT_DMA_ID_USART2_TX 9
-#define AT_DMA_ID_USART2_RX 10
-#define AT_DMA_ID_USART3_TX 11
-#define AT_DMA_ID_USART3_RX 12
-#define AT_DMA_ID_TWI0_TX 13
-#define AT_DMA_ID_TWI0_RX 14
-#define AT_DMA_ID_TWI1_TX 15
-#define AT_DMA_ID_TWI1_RX 16
-#define AT_DMA_ID_UART0_TX 17
-#define AT_DMA_ID_UART0_RX 18
-#define AT_DMA_ID_UART1_TX 19
-#define AT_DMA_ID_UART1_RX 20
-#define AT_DMA_ID_SSC_TX 21
-#define AT_DMA_ID_SSC_RX 22
-#define AT_DMA_ID_ADC_RX 23
-#define AT_DMA_ID_DBGU_TX 24
-#define AT_DMA_ID_DBGU_RX 25
-#define AT_DMA_ID_AES_TX 26
-#define AT_DMA_ID_AES_RX 27
-#define AT_DMA_ID_SHA_RX 28
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
index 0e42918..bdb0211 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
@@ -15,84 +15,84 @@
#ifndef _AT91SAM9N12_MATRIX_H_
#define _AT91SAM9N12_MATRIX_H_
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
-#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
-#define AT91_MATRIX_ULBT_128 (7 << 0)
+#define AT91SAM9N12_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9N12_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9N12_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9N12_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9N12_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9N12_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9N12_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9N12_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_128 (7 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9N12_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9N12_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9N12_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9N12_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9N12_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9N12_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9N12_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9N12_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9N12_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9N12_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9N12_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9N12_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9N12_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9N12_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9N12_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9N12_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9N12_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9N12_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
+#define AT91SAM9N12_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9N12_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9N12_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9N12_MATRIX_RCB2 (1 << 2)
+#define AT91SAM9N12_MATRIX_RCB3 (1 << 3)
+#define AT91SAM9N12_MATRIX_RCB4 (1 << 4)
+#define AT91SAM9N12_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
-#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
-#define AT91_MATRIX_EBI_DBPDC (1 << 9) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DBPD_ON (0 << 9)
-#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9)
-#define AT91_MATRIX_EBI_DRIVE (1 << 17) /* EBI I/O Drive Configuration */
-#define AT91_MATRIX_EBI_LOW_DRIVE (0 << 17)
-#define AT91_MATRIX_EBI_HIGH_DRIVE (1 << 17)
-#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
-#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
-#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
+#define AT91SAM9N12_MATRIX_EBICSA (0x118) /* EBI Chip Select Assignment Register */
+#define AT91SAM9N12_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9N12_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91SAM9N12_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9N12_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9N12_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91SAM9N12_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
+#define AT91SAM9N12_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9N12_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91SAM9N12_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91SAM9N12_MATRIX_EBI_DBPDC (1 << 9) /* Data Bus Pull-up Configuration */
+#define AT91SAM9N12_MATRIX_EBI_DBPD_ON (0 << 9)
+#define AT91SAM9N12_MATRIX_EBI_DBPD_OFF (1 << 9)
+#define AT91SAM9N12_MATRIX_EBI_DRIVE (1 << 17) /* EBI I/O Drive Configuration */
+#define AT91SAM9N12_MATRIX_EBI_LOW_DRIVE (0 << 17)
+#define AT91SAM9N12_MATRIX_EBI_HIGH_DRIVE (1 << 17)
+#define AT91SAM9N12_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
+#define AT91SAM9N12_MATRIX_NFD0_ON_D0 (0 << 24)
+#define AT91SAM9N12_MATRIX_NFD0_ON_D16 (1 << 24)
-#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
-#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
-#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
-#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
-#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
+#define AT91SAM9N12_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */
+#define AT91SAM9N12_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
+#define AT91SAM9N12_MATRIX_WPMR_WP_WPDIS (0 << 0)
+#define AT91SAM9N12_MATRIX_WPMR_WP_WPEN (1 << 0)
+#define AT91SAM9N12_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
-#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
-#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
-#define AT91_MATRIX_WPSR_WPV (1 << 0)
-#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
+#define AT91SAM9N12_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */
+#define AT91SAM9N12_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
+#define AT91SAM9N12_MATRIX_WPSR_NO_WPV (0 << 0)
+#define AT91SAM9N12_MATRIX_WPSR_WPV (1 << 0)
+#define AT91SAM9N12_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index e230577..f9d54df 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Controller Interrupt */
#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
@@ -86,13 +84,12 @@
#define AT91SAM9X5_BASE_UART1 0xf8044000
#define AT91SAM9X5_BASE_ISI 0xf8048000
#define AT91SAM9X5_BASE_ADC 0xf804c000
-#define AT91_BASE_SYS 0xffffc000
/*
* System Peripherals
*/
#define AT91SAM9X5_BASE_MATRIX 0xffffde00
-#define AT9SAM9X5_BASE1_PMECC 0xffffe000
+#define AT91SAM9X5_BASE_PMECC 0xffffe000
#define AT91SAM9X5_BASE_PMERRLOC 0xffffe600
#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
#define AT91SAM9X5_BASE_SMC 0xffffea00
@@ -113,32 +110,6 @@
#define AT91SAM9X5_BASE_RTC 0xfffffeb0
/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)
-#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
-#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-
-#define AT91_BASE_WDT AT91SAM9X5_BASE_WDT
-#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOC
-#define AT91_BASE_PIOD AT91SAM9X5_BASE_PIOD
-
-#define AT91_USART0 AT91SAM9X5_BASE_US0
-#define AT91_USART1 AT91SAM9X5_BASE_US1
-#define AT91_USART2 AT91SAM9X5_BASE_US2
-#define AT91_USART3 AT91SAM9X5_BASE_US3
-#define AT91_NB_USART 5
-
-#define AT91_PMC 0xfffffc00
-
-/*
* Internal Memory.
*/
#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
@@ -152,47 +123,4 @@
#define AT91SAM9X5_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */
#define AT91SAM9X5_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */
-#define CONSISTENT_DMA_SIZE SZ_4M
-
-/*
- * DMA0 peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI0 0
-#define AT_DMA_ID_SPI0_TX 1
-#define AT_DMA_ID_SPI0_RX 2
-#define AT_DMA_ID_USART0_TX 3
-#define AT_DMA_ID_USART0_RX 4
-#define AT_DMA_ID_USART1_TX 5
-#define AT_DMA_ID_USART1_RX 6
-#define AT_DMA_ID_TWI0_TX 7
-#define AT_DMA_ID_TWI0_RX 8
-#define AT_DMA_ID_TWI2_TX 9
-#define AT_DMA_ID_TWI2_RX 10
-#define AT_DMA_ID_UART0_TX 11
-#define AT_DMA_ID_UART0_RX 12
-#define AT_DMA_ID_SSC_TX 13
-#define AT_DMA_ID_SSC_RX 14
-
-/*
- * DMA1 peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI1 0
-#define AT_DMA_ID_SPI1_TX 1
-#define AT_DMA_ID_SPI1_RX 2
-#define AT_DMA_ID_SMD_TX 3
-#define AT_DMA_ID_SMD_RX 4
-#define AT_DMA_ID_TWI1_TX 5
-#define AT_DMA_ID_TWI1_RX 6
-#define AT_DMA_ID_ADC_RX 7
-#define AT_DMA_ID_DBGU_TX 8
-#define AT_DMA_ID_DBGU_RX 9
-#define AT_DMA_ID_UART1_TX 10
-#define AT_DMA_ID_UART1_RX 11
-#define AT_DMA_ID_USART2_TX 12
-#define AT_DMA_ID_USART2_RX 13
-#define AT_DMA_ID_USART3_TX 14
-#define AT_DMA_ID_USART3_RX 15
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
index b070a40..fca7646 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
@@ -15,125 +15,125 @@
#ifndef AT91SAM9X5_MATRIX_H
#define AT91SAM9X5_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
-#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
-#define AT91_MATRIX_ULBT_128 (7 << 0)
+#define AT91SAM9X5_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9X5_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9X5_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9X5_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9X5_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9X5_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9X5_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */
+#define AT91SAM9X5_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */
+#define AT91SAM9X5_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */
+#define AT91SAM9X5_MATRIX_MCFG9 (0x24) /* Master Configuration Register 9 */
+#define AT91SAM9X5_MATRIX_MCFG10 (0x28) /* Master Configuration Register 10 */
+#define AT91SAM9X5_MATRIX_MCFG11 (0x2C) /* Master Configuration Register 11 */
+#define AT91SAM9X5_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9X5_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_128 (7 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
-#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9X5_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9X5_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9X5_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9X5_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9X5_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9X5_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */
+#define AT91SAM9X5_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */
+#define AT91SAM9X5_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */
+#define AT91SAM9X5_MATRIX_SCFG8 (0x60) /* Slave Configuration Register 8 */
+#define AT91SAM9X5_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9X5_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
-#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
-#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
-#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
-#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
-#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
+#define AT91SAM9X5_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9X5_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */
+#define AT91SAM9X5_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9X5_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */
+#define AT91SAM9X5_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9X5_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */
+#define AT91SAM9X5_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9X5_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */
+#define AT91SAM9X5_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9X5_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */
+#define AT91SAM9X5_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */
+#define AT91SAM9X5_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */
+#define AT91SAM9X5_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */
+#define AT91SAM9X5_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */
+#define AT91SAM9X5_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */
+#define AT91SAM9X5_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */
+#define AT91SAM9X5_MATRIX_PRAS8 (0xC0) /* Priority Register A for Slave 8 */
+#define AT91SAM9X5_MATRIX_PRBS8 (0xC4) /* Priority Register B for Slave 8 */
+#define AT91SAM9X5_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9X5_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9X5_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9X5_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9X5_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9X5_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9X5_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91SAM9X5_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91SAM9X5_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91SAM9X5_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
+#define AT91SAM9X5_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
+#define AT91SAM9X5_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_RCB9 (1 << 9)
-#define AT91_MATRIX_RCB10 (1 << 10)
-#define AT91_MATRIX_RCB11 (1 << 11)
+#define AT91SAM9X5_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9X5_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9X5_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9X5_MATRIX_RCB2 (1 << 2)
+#define AT91SAM9X5_MATRIX_RCB3 (1 << 3)
+#define AT91SAM9X5_MATRIX_RCB4 (1 << 4)
+#define AT91SAM9X5_MATRIX_RCB5 (1 << 5)
+#define AT91SAM9X5_MATRIX_RCB6 (1 << 6)
+#define AT91SAM9X5_MATRIX_RCB7 (1 << 7)
+#define AT91SAM9X5_MATRIX_RCB8 (1 << 8)
+#define AT91SAM9X5_MATRIX_RCB9 (1 << 9)
+#define AT91SAM9X5_MATRIX_RCB10 (1 << 10)
+#define AT91SAM9X5_MATRIX_RCB11 (1 << 11)
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
-#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
-#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
-#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
-#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
-#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
-#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
-#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
-#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
-#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
-#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
-#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
-#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
-#define AT91_MATRIX_MP_OFF (0 << 25)
-#define AT91_MATRIX_MP_ON (1 << 25)
+#define AT91SAM9X5_MATRIX_EBICSA (0x120) /* EBI Chip Select Assignment Register */
+#define AT91SAM9X5_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9X5_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91SAM9X5_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9X5_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9X5_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91SAM9X5_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
+#define AT91SAM9X5_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9X5_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91SAM9X5_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
+#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
+#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
+#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
+#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
+#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
+#define AT91SAM9X5_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
+#define AT91SAM9X5_MATRIX_NFD0_ON_D0 (0 << 24)
+#define AT91SAM9X5_MATRIX_NFD0_ON_D16 (1 << 24)
+#define AT91SAM9X5_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
+#define AT91SAM9X5_MATRIX_MP_OFF (0 << 25)
+#define AT91SAM9X5_MATRIX_MP_ON (1 << 25)
-#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
-#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
-#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
-#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
-#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
+#define AT91SAM9X5_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */
+#define AT91SAM9X5_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
+#define AT91SAM9X5_MATRIX_WPMR_WP_WPDIS (0 << 0)
+#define AT91SAM9X5_MATRIX_WPMR_WP_WPEN (1 << 0)
+#define AT91SAM9X5_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
-#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
-#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
-#define AT91_MATRIX_WPSR_WPV (1 << 0)
-#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
+#define AT91SAM9X5_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */
+#define AT91SAM9X5_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
+#define AT91SAM9X5_MATRIX_WPSR_NO_WPV (0 << 0)
+#define AT91SAM9X5_MATRIX_WPSR_WPV (1 << 0)
+#define AT91SAM9X5_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#endif
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 5d76e00..0f2c269 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -107,9 +107,6 @@ static inline struct device_d * at91_register_uart(unsigned id, unsigned pins)
resource_size_t start;
resource_size_t size = SZ_16K;
- if (id >= AT91_NB_USART)
- return NULL;
-
switch (id) {
case 0: /* DBGU */
start = at91_configure_dbgu();
@@ -167,4 +164,10 @@ struct at91_spi_platform_data {
void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata);
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data);
+
+void at91sam_phy_reset(void __iomem *rstc_base);
+
+void at91sam9_reset(void __iomem *sdram, void __iomem *rstc_cr);
+void at91sam9g45_reset(void __iomem *sdram, void __iomem *rstc_cr);
+
#endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index bbaad71..e2e0134 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -66,13 +66,6 @@
#define SAMA5_CHIPSELECT_2 0x50000000
#define SAMA5_CHIPSELECT_3 0x60000000
-/* SDRAM */
-#ifdef CONFIG_DRAM_BASE
-#define AT91_SDRAM_BASE CONFIG_DRAM_BASE
-#else
-#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
-#endif
-
/* Clocks */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
deleted file mode 100644
index a1d970f..0000000
--- a/arch/arm/mach-at91/include/mach/io.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/io.h]
- *
- * Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include <io.h>
-#include <mach/hardware.h>
-
-static inline unsigned int at91_sys_read(unsigned int reg_offset)
-{
- void *addr = (void *)AT91_BASE_SYS;
-
- return __raw_readl(addr + reg_offset);
-}
-
-static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
-{
- void *addr = (void *)AT91_BASE_SYS;
-
- __raw_writel(value, addr + reg_offset);
-}
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index e98b101..f0e5361 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -15,8 +15,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */
#define SAMA5D3_ID_PIT 3 /* Periodic Interval Timer Interrupt */
#define SAMA5D3_ID_WDT 4 /* Watchdog timer Interrupt */
@@ -83,15 +81,6 @@
#define SAMA5D3_BASE_SPI1 0xf8008000
#define SAMA5D3_BASE_EMAC 0xf802c000 /* (EMAC) Base Address */
#define SAMA5D3_BASE_UDPHS 0xf8030000
-#define AT91_BASE_SYS 0xffffc000
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS) // KO OAR_TEMP, NO GPBR, error while building in "drivers/rtc/rtc-at91sam9.c"
-#define AT91_DDRSDRC0 (0xffffea00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define SAMA5D3_BASE_PIOA 0xfffff200
#define SAMA5D3_BASE_PIOB 0xfffff400
@@ -100,16 +89,13 @@
#define SAMA5D3_BASE_PIOE 0xfffffa00
#define SAMA5D3_BASE_MPDDRC 0xffffea00
#define SAMA5D3_BASE_HSMC 0xffffc000
+#define SAMA5D3_BASE_RSTC 0xfffffe00
#define SAMA5D3_BASE_PIT 0xfffffe30
#define SAMA5D3_BASE_WDT 0xfffffe40
#define SAMA5D3_BASE_PMECC 0xffffc070
#define SAMA5D3_BASE_PMERRLOC 0xffffc500
-#define AT91_NB_USART 3
-
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
@@ -123,32 +109,4 @@
#define SAMA5D3_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */
#define SAMA5D3_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */
-/*
- * DMA0 peripheral identifiers
- * for hardware handshaking interface
- */
-#define SAMA5_DMA_ID_MCI0 0
-#define SAMA5_DMA_ID_SPI0_TX 1
-#define SAMA5_DMA_ID_SPI0_RX 2
-#define SAMA5_DMA_ID_USART0_TX 3
-#define SAMA5_DMA_ID_USART0_RX 4
-#define SAMA5_DMA_ID_USART1_TX 5
-#define SAMA5_DMA_ID_USART1_RX 6
-#define SAMA5_DMA_ID_TWI0_TX 7
-#define SAMA5_DMA_ID_TWI0_RX 8
-#define SAMA5_DMA_ID_TWI1_TX 9
-#define SAMA5_DMA_ID_TWI1_RX 10
-#define SAMA5_DMA_ID_UART0_TX 11
-#define SAMA5_DMA_ID_UART0_RX 12
-#define SAMA5_DMA_ID_SSC0_TX 13
-#define SAMA5_DMA_ID_SSC0_RX 14
-#define SAMA5_DMA_ID_SMD_TX 15
-#define SAMA5_DMA_ID_SMD_RX 16
-
-/*
- * DMA1 peripheral identifiers
- * for hardware handshaking interface
- */
-#define SAMA5_DMA_ID_MCI1 0
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index 046fdb0..6d621e0 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -106,6 +106,7 @@
#define SAMA5D4_BASE_PMECC 0xfc05c070 /* (PMECC) Base Address */
#define SAMA5D4_BASE_PMERRLOC 0xfc05c500 /* (PMERRLOC) Base Address */
#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */
+#define SAMA5D4_BASE_RSTC 0xfc068600
#define SAMA5D4_BASE_PIT 0xfc068630 /* (PIT) Base Address */
#define SAMA5D4_BASE_DBGU 0xfc069000 /* (DBGU) Base Address */
#define SAMA5D4_BASE_PIOA 0xfc06a000 /* (PIOA) Base Address */
@@ -122,13 +123,4 @@
#define SAMA5D4_SRAM_BASE 0x00200000 /* Internal SRAM base address */
#define SAMA5D4_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size */
-#define AT91_NB_USART 7
-#define AT91_BASE_SYS 0xf0000000
-#define AT91_PMC SAMA5D4_BASE_PMC
-#define AT91_DDRSDRC0 (0xf0010000 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfc068600 - AT91_BASE_SYS)
-#define SAMA5D3_BASE_MPDDRC SAMA5D4_BASE_MPDDRC
-#define SAMA5D3_SRAM_BASE SAMA5D4_SRAM_BASE
-#define SAMA5D3_SRAM_SIZE SAMA5D4_SRAM_SIZE
-
#endif
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index d2b075e..dc1f2ed 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -13,7 +13,6 @@
#include <io.h>
#include <mach/hardware.h>
#include <mach/cpu.h>
-#include <mach/io.h>
#include <linux/err.h>
#include <mach/at91sam9_smc.h>
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index b52c6b4..a5d464e 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -1,10 +1,12 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
-#include <mach/io.h>
#include <mach/cpu.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include <linux/clk.h>
#include "generic.h"
@@ -370,6 +372,12 @@ static void __init sama5d3_register_clocks(void)
//clk_enable(&dma1_clk);
}
+static void sama5d3_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(SAMA5D3_BASE_MPDDRC),
+ IOMEM(SAMA5D3_BASE_RSTC + AT91_RSTC_CR));
+}
+
/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
@@ -388,6 +396,8 @@ static void sama5d3_initialize(void)
at91_add_pit(SAMA5D3_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D3_BASE_HSMC + 0x600, 0xa0);
+
+ restart_handler_register_fn(sama5d3_restart);
}
static int sama5d3_setup(void)
diff --git a/arch/arm/mach-at91/sama5d3_devices.c b/arch/arm/mach-at91/sama5d3_devices.c
index c6f5e3a..f5075b3 100644
--- a/arch/arm/mach-at91/sama5d3_devices.c
+++ b/arch/arm/mach-at91/sama5d3_devices.c
@@ -20,7 +20,6 @@
#include <mach/at91sam9x5_matrix.h>
#include <mach/at91sam9_ddrsdr.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c
index d6b18fc..ca09dfe 100644
--- a/arch/arm/mach-at91/sama5d4.c
+++ b/arch/arm/mach-at91/sama5d4.c
@@ -10,10 +10,12 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
-#include <mach/io.h>
#include <mach/cpu.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include <linux/clk.h>
#include "generic.h"
@@ -279,6 +281,12 @@ static void __init sama5d4_register_clocks(void)
clk_register(&pck2);
}
+static void sama5d4_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(SAMA5D4_BASE_MPDDRC),
+ IOMEM(SAMA5D4_BASE_RSTC + AT91_RSTC_CR));
+}
+
/* --------------------------------------------------------------------
* Processor initialization
* -------------------------------------------------------------------- */
@@ -296,6 +304,8 @@ static void sama5d4_initialize(void)
at91_add_pit(SAMA5D4_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D4_BASE_HSMC + 0x600, 0xa0);
+
+ restart_handler_register_fn(sama5d4_restart);
}
static int sama5d4_setup(void)
diff --git a/arch/arm/mach-at91/sama5d4_devices.c b/arch/arm/mach-at91/sama5d4_devices.c
index c2f171a..4064e44 100644
--- a/arch/arm/mach-at91/sama5d4_devices.c
+++ b/arch/arm/mach-at91/sama5d4_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91sam9x5_matrix.h>
#include <mach/at91sam9_ddrsdr.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 7a19c45..adc614c 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -9,10 +9,12 @@
#include <io.h>
#include <init.h>
#include <restart.h>
+#include <linux/clk.h>
#include <mach/hardware.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
@@ -281,9 +283,6 @@ static int at91_detect(void)
}
postcore_initcall(at91_detect);
-void restart_sam9(struct restart_handler *rst);
-void restart_sam9g45(struct restart_handler *rst);
-
static int at91_soc_device(void)
{
struct device_d *dev;
@@ -292,11 +291,29 @@ static int at91_soc_device(void)
dev_add_param_fixed(dev, "name", (char*)at91_get_soc_type(&at91_soc_initdata));
dev_add_param_fixed(dev, "subname", (char*)at91_get_soc_subtype(&at91_soc_initdata));
- if (IS_ENABLED(CONFIG_AT91SAM9_RESET))
- restart_handler_register_fn(restart_sam9);
- if (IS_ENABLED(CONFIG_AT91SAM9G45_RESET))
- restart_handler_register_fn(restart_sam9g45);
-
return 0;
}
coredevice_initcall(at91_soc_device);
+
+void at91sam_phy_reset(void __iomem *rstc_base)
+{
+ unsigned long rstc;
+ struct clk *clk = clk_get(NULL, "macb_clk");
+
+ clk_enable(clk);
+
+ rstc = readl(rstc_base + AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
+ /* Need to reset PHY -> 500ms reset */
+ writel(AT91_RSTC_KEY | (AT91_RSTC_ERSTL & (0x0d << 8)) | AT91_RSTC_URSTEN,
+ rstc_base + AT91_RSTC_MR);
+
+ writel(AT91_RSTC_KEY | AT91_RSTC_EXTRST, rstc_base + AT91_RSTC_CR);
+
+ /* Wait for end hardware reset */
+ while (!(readl(rstc_base + AT91_RSTC_SR) & AT91_RSTC_NRSTL))
+ ;
+
+ /* Restore NRST value */
+ writel(AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN, rstc_base + AT91_RSTC_MR);
+}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 63a92bd..b2b250f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -413,6 +413,7 @@ config MACH_ZII_RDU1
bool "ZII i.MX51 RDU1"
select ARCH_IMX51
select MACH_FREESCALE_MX51_PDK_POWER
+ select CRC8
config MACH_ZII_RDU2
bool "ZII i.MX6Q(+) RDU2"
@@ -454,6 +455,10 @@ config MACH_NXP_IMX8MQ_EVK
select FIRMWARE_IMX8MQ_ATF
select ARM_SMCCC
+config MACH_GRINN_LITEBOARD
+ bool "Grinn liteboard"
+ select ARCH_IMX6UL
+
endif
# ----------------------------------------------------------
diff --git a/commands/gpio.c b/commands/gpio.c
index 08ecc15..951ad2c 100644
--- a/commands/gpio.c
+++ b/commands/gpio.c
@@ -16,14 +16,35 @@
#include <errno.h>
#include <gpio.h>
-static int do_gpio_get_value(int argc, char *argv[])
+static int get_gpio_and_value(int argc, char *argv[],
+ int *gpio, int *value)
{
- int gpio, value;
+ const int count = value ? 3 : 2;
+ int ret = 0;
- if (argc < 2)
+ if (argc < count)
return COMMAND_ERROR_USAGE;
- gpio = simple_strtoul(argv[1], NULL, 0);
+ *gpio = gpio_find_by_label(argv[1]);
+ if (*gpio < 0) {
+ ret = kstrtoint(argv[1], 0, gpio);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (value)
+ ret = kstrtoint(argv[2], 0, value);
+
+ return ret;
+}
+
+static int do_gpio_get_value(int argc, char *argv[])
+{
+ int gpio, value, ret;
+
+ ret = get_gpio_and_value(argc, argv, &gpio, NULL);
+ if (ret)
+ return ret;
value = gpio_get_value(gpio);
if (value < 0)
@@ -41,13 +62,11 @@ BAREBOX_CMD_END
static int do_gpio_set_value(int argc, char *argv[])
{
- int gpio, value;
-
- if (argc < 3)
- return COMMAND_ERROR_USAGE;
+ int gpio, value, ret;
- gpio = simple_strtoul(argv[1], NULL, 0);
- value = simple_strtoul(argv[2], NULL, 0);
+ ret = get_gpio_and_value(argc, argv, &gpio, &value);
+ if (ret)
+ return ret;
gpio_set_value(gpio, value);
@@ -65,10 +84,9 @@ static int do_gpio_direction_input(int argc, char *argv[])
{
int gpio, ret;
- if (argc < 2)
- return COMMAND_ERROR_USAGE;
-
- gpio = simple_strtoul(argv[1], NULL, 0);
+ ret = get_gpio_and_value(argc, argv, &gpio, NULL);
+ if (ret)
+ return ret;
ret = gpio_direction_input(gpio);
if (ret)
@@ -88,11 +106,9 @@ static int do_gpio_direction_output(int argc, char *argv[])
{
int gpio, value, ret;
- if (argc < 3)
- return COMMAND_ERROR_USAGE;
-
- gpio = simple_strtoul(argv[1], NULL, 0);
- value = simple_strtoul(argv[2], NULL, 0);
+ ret = get_gpio_and_value(argc, argv, &gpio, &value);
+ if (ret)
+ return ret;
ret = gpio_direction_output(gpio, value);
if (ret)
diff --git a/common/Makefile b/common/Makefile
index 13920cc..861365b 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -34,8 +34,8 @@ obj-$(CONFIG_GLOBALVAR) += globalvar.o
obj-$(CONFIG_GREGORIAN_CALENDER) += date.o
obj-$(CONFIG_KALLSYMS) += kallsyms.o
obj-$(CONFIG_MALLOC_DLMALLOC) += dlmalloc.o
-obj-$(CONFIG_MALLOC_TLSF) += tlsf_malloc.o tlsf.o
-obj-$(CONFIG_MALLOC_DUMMY) += dummy_malloc.o
+obj-$(CONFIG_MALLOC_TLSF) += tlsf_malloc.o tlsf.o calloc.o
+obj-$(CONFIG_MALLOC_DUMMY) += dummy_malloc.o calloc.o
obj-$(CONFIG_MEMINFO) += meminfo.o
obj-$(CONFIG_MENU) += menu.o
obj-$(CONFIG_MODULES) += module.o
diff --git a/common/calloc.c b/common/calloc.c
new file mode 100644
index 0000000..2b933ec
--- /dev/null
+++ b/common/calloc.c
@@ -0,0 +1,19 @@
+#include <common.h>
+#include <malloc.h>
+
+/*
+ * calloc calls malloc, then zeroes out the allocated chunk.
+ */
+void *calloc(size_t n, size_t elem_size)
+{
+ size_t size = elem_size * n;
+ void *r = malloc(size);
+
+ if (!r)
+ return r;
+
+ memset(r, 0x0, size);
+
+ return r;
+}
+EXPORT_SYMBOL(calloc);
diff --git a/common/dummy_malloc.c b/common/dummy_malloc.c
index 641baa1..0120d9b 100644
--- a/common/dummy_malloc.c
+++ b/common/dummy_malloc.c
@@ -30,11 +30,14 @@ void malloc_stats(void)
void *memalign(size_t alignment, size_t bytes)
{
- unsigned long mem = (unsigned long)sbrk(bytes + alignment);
+ void *mem = sbrk(bytes + alignment);
- mem = (mem + alignment) & ~(alignment - 1);
+ if (!mem) {
+ errno = ENOMEM;
+ return NULL;
+ }
- return (void *)mem;
+ return PTR_ALIGN(mem, alignment);
}
void *malloc(size_t size)
@@ -50,16 +53,3 @@ void *realloc(void *ptr, size_t size)
{
BUG();
}
-
-void *calloc(size_t n, size_t elem_size)
-{
- size_t size = elem_size * n;
- void *r = malloc(size);
-
- if (!r)
- return r;
-
- memset(r, 0x0, size);
-
- return r;
-}
diff --git a/common/startup.c b/common/startup.c
index 5793ea2..28edee4 100644
--- a/common/startup.c
+++ b/common/startup.c
@@ -91,6 +91,9 @@ static int check_overlap(const char *path)
if (!cenv)
return -EINVAL;
+ if (cenv->mtd)
+ return 0;
+
cdisk = cenv->master;
if (!cdisk)
diff --git a/common/tlsf_malloc.c b/common/tlsf_malloc.c
index a3541d8..c8900fc 100644
--- a/common/tlsf_malloc.c
+++ b/common/tlsf_malloc.c
@@ -28,6 +28,7 @@ extern tlsf_pool tlsf_mem_pool;
void *malloc(size_t bytes)
{
+ void *mem;
/*
* tlsf_malloc returns NULL for zero bytes, we instead want
* to have a valid pointer.
@@ -35,25 +36,13 @@ void *malloc(size_t bytes)
if (!bytes)
bytes = 1;
- return tlsf_malloc(tlsf_mem_pool, bytes);
-}
-EXPORT_SYMBOL(malloc);
-
-/*
- * calloc calls malloc, then zeroes out the allocated chunk.
- */
-void *calloc(size_t n, size_t elem_size)
-{
- void *mem;
- size_t sz;
-
- sz = n * elem_size;
- mem = malloc(sz);
- memset(mem, 0, sz);
+ mem = tlsf_malloc(tlsf_mem_pool, bytes);
+ if (!mem)
+ errno = ENOMEM;
return mem;
}
-EXPORT_SYMBOL(calloc);
+EXPORT_SYMBOL(malloc);
void free(void *mem)
{
@@ -63,13 +52,21 @@ EXPORT_SYMBOL(free);
void *realloc(void *oldmem, size_t bytes)
{
- return tlsf_realloc(tlsf_mem_pool, oldmem, bytes);
+ void *mem = tlsf_realloc(tlsf_mem_pool, oldmem, bytes);
+ if (!mem)
+ errno = ENOMEM;
+
+ return mem;
}
EXPORT_SYMBOL(realloc);
void *memalign(size_t alignment, size_t bytes)
{
- return tlsf_memalign(tlsf_mem_pool, alignment, bytes);
+ void *mem = tlsf_memalign(tlsf_mem_pool, alignment, bytes);
+ if (!mem)
+ errno = ENOMEM;
+
+ return mem;
}
EXPORT_SYMBOL(memalign);
diff --git a/drivers/base/driver.c b/drivers/base/driver.c
index c43a4bd..3b39c28 100644
--- a/drivers/base/driver.c
+++ b/drivers/base/driver.c
@@ -368,18 +368,6 @@ struct resource *dev_get_resource_by_name(struct device_d *dev,
return ERR_PTR(-ENOENT);
}
-void *dev_get_mem_region_by_name(struct device_d *dev, const char *name)
-{
- struct resource *res;
-
- res = dev_get_resource_by_name(dev, IORESOURCE_MEM, name);
- if (IS_ERR(res))
- return ERR_CAST(res);
-
- return (void __force *)res->start;
-}
-EXPORT_SYMBOL(dev_get_mem_region_by_name);
-
void __iomem *dev_request_mem_region_by_name(struct device_d *dev, const char *name)
{
struct resource *res;
@@ -396,32 +384,28 @@ void __iomem *dev_request_mem_region_by_name(struct device_d *dev, const char *n
}
EXPORT_SYMBOL(dev_request_mem_region_by_name);
-void __iomem *dev_request_mem_region_err_null(struct device_d *dev, int num)
+struct resource *dev_request_mem_resource(struct device_d *dev, int num)
{
struct resource *res;
res = dev_get_resource(dev, IORESOURCE_MEM, num);
if (IS_ERR(res))
- return NULL;
-
- res = request_iomem_region(dev_name(dev), res->start, res->end);
- if (IS_ERR(res))
- return NULL;
+ return ERR_CAST(res);
- return IOMEM(res->start);
+ return request_iomem_region(dev_name(dev), res->start, res->end);
}
-EXPORT_SYMBOL(dev_request_mem_region_err_null);
-struct resource *dev_request_mem_resource(struct device_d *dev, int num)
+void __iomem *dev_request_mem_region_err_null(struct device_d *dev, int num)
{
struct resource *res;
- res = dev_get_resource(dev, IORESOURCE_MEM, num);
+ res = dev_request_mem_resource(dev, num);
if (IS_ERR(res))
- return ERR_CAST(res);
+ return NULL;
- return request_iomem_region(dev_name(dev), res->start, res->end);
+ return IOMEM(res->start);
}
+EXPORT_SYMBOL(dev_request_mem_region_err_null);
void __iomem *dev_request_mem_region(struct device_d *dev, int num)
{
@@ -435,29 +419,22 @@ void __iomem *dev_request_mem_region(struct device_d *dev, int num)
}
EXPORT_SYMBOL(dev_request_mem_region);
-int generic_memmap_ro(struct cdev *cdev, void **map, int flags)
+int generic_memmap_rw(struct cdev *cdev, void **map, int flags)
{
if (!cdev->dev)
return -EINVAL;
- if (flags & PROT_WRITE)
- return -EACCES;
*map = dev_get_mem_region(cdev->dev, 0);
- if (IS_ERR(*map))
- return PTR_ERR(*map);
- return 0;
+
+ return PTR_ERR_OR_ZERO(*map);
}
-int generic_memmap_rw(struct cdev *cdev, void **map, int flags)
+int generic_memmap_ro(struct cdev *cdev, void **map, int flags)
{
- if (!cdev->dev)
- return -EINVAL;
-
- *map = dev_get_mem_region(cdev->dev, 0);
- if (IS_ERR(*map))
- return PTR_ERR(*map);
+ if (flags & PROT_WRITE)
+ return -EACCES;
- return 0;
+ return generic_memmap_rw(cdev, map, flags);
}
int dummy_probe(struct device_d *dev)
diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
index 947a1e7..4089584 100644
--- a/drivers/clocksource/timer-atmel-pit.c
+++ b/drivers/clocksource/timer-atmel-pit.c
@@ -30,7 +30,6 @@
#include <clock.h>
#include <mach/hardware.h>
#include <mach/at91_pit.h>
-#include <mach/io.h>
#include <io.h>
#include <linux/clk.h>
#include <linux/err.h>
diff --git a/drivers/gpio/gpio-dw.c b/drivers/gpio/gpio-dw.c
index f145c01..b81e6a7 100644
--- a/drivers/gpio/gpio-dw.c
+++ b/drivers/gpio/gpio-dw.c
@@ -199,4 +199,4 @@ static int __init dwgpio_init(void)
{
return platform_driver_register(&dwgpio_driver);
}
-core_initcall(dwgpio_init);
+postcore_initcall(dwgpio_init);
diff --git a/drivers/gpio/gpio-imx.c b/drivers/gpio/gpio-imx.c
index d618e60..2827e11 100644
--- a/drivers/gpio/gpio-imx.c
+++ b/drivers/gpio/gpio-imx.c
@@ -222,4 +222,4 @@ static int imx_gpio_add(void)
platform_driver_register(&imx_gpio_driver);
return 0;
}
-core_initcall(imx_gpio_add);
+postcore_initcall(imx_gpio_add);
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index b2b3ad3..ef78873 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -183,4 +183,4 @@ static int mxs_gpio_add(void)
platform_driver_register(&mxs_gpio_driver);
return 0;
}
-core_initcall(mxs_gpio_add);
+postcore_initcall(mxs_gpio_add);
diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
index 2aff62b..ab35310 100644
--- a/drivers/gpio/gpio-vf610.c
+++ b/drivers/gpio/gpio-vf610.c
@@ -142,9 +142,8 @@ static int vf610_gpio_probe(struct device_d *dev)
port->chip.base *= VF610_GPIO_PER_PORT;
port->chip.dev = dev;
- gpiochip_add(&port->chip);
- return 0;
+ return gpiochip_add(&port->chip);
free_port:
free(port);
@@ -161,4 +160,4 @@ static int __init gpio_vf610_init(void)
{
return platform_driver_register(&vf610_gpio_driver);
}
-core_initcall(gpio_vf610_init);
+postcore_initcall(gpio_vf610_init);
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index b83a27d..4c7aee4 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -91,6 +91,23 @@ done:
return ret;
}
+int gpio_find_by_label(const char *label)
+{
+ int i;
+
+ for (i = 0; i < ARCH_NR_GPIOS; i++) {
+ struct gpio_info *info = &gpio_desc[i];
+
+ if (!info->requested || !info->chip || !info->label)
+ continue;
+
+ if (!strcmp(info->label, label))
+ return i;
+ }
+
+ return -ENOENT;
+}
+
void gpio_free(unsigned gpio)
{
struct gpio_info *gi = gpio_to_desc(gpio);
@@ -352,12 +369,12 @@ static int of_hog_gpio(struct device_node *np, struct gpio_chip *chip,
flags |= GPIOF_ACTIVE_LOW;
gpio = gpio_get_num(chip->dev, gpio_num);
- if (ret == -EPROBE_DEFER)
- return ret;
+ if (gpio == -EPROBE_DEFER)
+ return gpio;
- if (ret < 0) {
+ if (gpio < 0) {
dev_err(chip->dev, "unable to get gpio %u\n", gpio_num);
- return ret;
+ return gpio;
}
@@ -382,7 +399,10 @@ static int of_hog_gpio(struct device_node *np, struct gpio_chip *chip,
else
return -EINVAL;
- of_property_read_string(np, "line-name", &name);
+ /* The line-name is optional and if not present the node name is used */
+ ret = of_property_read_string(np, "line-name", &name);
+ if (ret < 0)
+ name = np->name;
return gpio_request_one(gpio, flags, name);
}
diff --git a/drivers/mtd/nand/nand_denali_dt.c b/drivers/mtd/nand/nand_denali_dt.c
index 2c6b188..e302454 100644
--- a/drivers/mtd/nand/nand_denali_dt.c
+++ b/drivers/mtd/nand/nand_denali_dt.c
@@ -86,7 +86,7 @@ out_disable_clk:
static __maybe_unused struct of_device_id denali_nand_compatible[] = {
{
- .compatible = "denali,denali-nand-dt"
+ .compatible = "altr,socfpga-denali-nand"
}, {
/* sentinel */
}
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 38b6f42..c28a6d4 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -43,4 +43,12 @@ config RAVE_SP_EEPROM
help
Say y here to enable Rave SP EEPROM support.
+config EEPROM_93XX46
+ bool "Microwire EEPROM 93XX46 support"
+ depends on SPI
+ help
+ Driver for the microwire EEPROM chipsets 93xx46x. The driver
+ supports both read and write commands and also the command to
+ erase the whole EEPROM.
+
endif
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 716e5db..abf9dae 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -13,4 +13,7 @@ obj-$(CONFIG_IMX_OCOTP) += nvmem_ocotp.o
nvmem_ocotp-y := ocotp.o
obj-$(CONFIG_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o
-nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o \ No newline at end of file
+nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o
+
+obj-$(CONFIG_EEPROM_93XX46) += nvmem_eeprom_93xx46.o
+nvmem_eeprom_93xx46-y := eeprom_93xx46.o \ No newline at end of file
diff --git a/drivers/nvmem/eeprom_93xx46.c b/drivers/nvmem/eeprom_93xx46.c
new file mode 100644
index 0000000..d96ba32
--- /dev/null
+++ b/drivers/nvmem/eeprom_93xx46.c
@@ -0,0 +1,446 @@
+/*
+ * Driver for 93xx46 EEPROMs
+ *
+ * (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <of.h>
+#include <spi/spi.h>
+#include <of.h>
+#include <spi/spi.h>
+#include <malloc.h>
+#include <gpio.h>
+#include <of_gpio.h>
+#include <of_device.h>
+
+#include <linux/nvmem-provider.h>
+
+
+#define OP_START 0x4
+#define OP_WRITE (OP_START | 0x1)
+#define OP_READ (OP_START | 0x2)
+#define ADDR_EWDS 0x00
+#define ADDR_ERAL 0x20
+#define ADDR_EWEN 0x30
+
+struct eeprom_93xx46_platform_data {
+ unsigned char flags;
+#define EE_ADDR8 0x01 /* 8 bit addr. cfg */
+#define EE_ADDR16 0x02 /* 16 bit addr. cfg */
+#define EE_READONLY 0x08 /* forbid writing */
+
+ unsigned int quirks;
+/* Single word read transfers only; no sequential read. */
+#define EEPROM_93XX46_QUIRK_SINGLE_WORD_READ (1 << 0)
+/* Instructions such as EWEN are (addrlen + 2) in length. */
+#define EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH (1 << 1)
+
+ /*
+ * optional hooks to control additional logic
+ * before and after spi transfer.
+ */
+ void (*prepare)(void *);
+ void (*finish)(void *);
+ int select;
+};
+
+struct eeprom_93xx46_devtype_data {
+ unsigned int quirks;
+};
+
+static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = {
+ .quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ |
+ EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH,
+};
+
+struct eeprom_93xx46_dev {
+ struct spi_device *spi;
+ struct eeprom_93xx46_platform_data *pdata;
+ struct nvmem_config nvmem_config;
+ struct nvmem_device *nvmem;
+ int addrlen;
+ int size;
+};
+
+static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
+{
+ return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
+}
+
+static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
+{
+ return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
+}
+
+static int eeprom_93xx46_read(struct device_d *dev, int off,
+ void *val, int count)
+{
+ struct eeprom_93xx46_dev *edev = dev->parent->priv;
+ char *buf = val;
+ int err = 0;
+
+ if (unlikely(off >= edev->size))
+ return 0;
+ if ((off + count) > edev->size)
+ count = edev->size - off;
+ if (unlikely(!count))
+ return count;
+
+ if (edev->pdata->prepare)
+ edev->pdata->prepare(edev);
+
+ while (count) {
+ struct spi_message m;
+ struct spi_transfer t[2] = { { 0 } };
+ u16 cmd_addr = OP_READ << edev->addrlen;
+ size_t nbytes = count;
+ int bits;
+
+ if (edev->addrlen == 7) {
+ cmd_addr |= off & 0x7f;
+ bits = 10;
+ if (has_quirk_single_word_read(edev))
+ nbytes = 1;
+ } else {
+ cmd_addr |= (off >> 1) & 0x3f;
+ bits = 9;
+ if (has_quirk_single_word_read(edev))
+ nbytes = 2;
+ }
+
+ dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
+ cmd_addr, edev->spi->max_speed_hz);
+
+ spi_message_init(&m);
+
+ t[0].tx_buf = (char *)&cmd_addr;
+ t[0].len = 2;
+ t[0].bits_per_word = bits;
+ spi_message_add_tail(&t[0], &m);
+
+ t[1].rx_buf = buf;
+ t[1].len = count;
+ t[1].bits_per_word = 8;
+ spi_message_add_tail(&t[1], &m);
+
+ err = spi_sync(edev->spi, &m);
+ /* have to wait at least Tcsl ns */
+ ndelay(250);
+
+ if (err) {
+ dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
+ nbytes, (int)off, err);
+ break;
+ }
+
+ buf += nbytes;
+ off += nbytes;
+ count -= nbytes;
+ }
+
+ if (edev->pdata->finish)
+ edev->pdata->finish(edev);
+
+ return err;
+}
+
+static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
+{
+ struct spi_message m;
+ struct spi_transfer t;
+ int bits, ret;
+ u16 cmd_addr;
+
+ cmd_addr = OP_START << edev->addrlen;
+ if (edev->addrlen == 7) {
+ cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS) << 1;
+ bits = 10;
+ } else {
+ cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS);
+ bits = 9;
+ }
+
+ if (has_quirk_instruction_length(edev)) {
+ cmd_addr <<= 2;
+ bits += 2;
+ }
+
+ dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n",
+ is_on ? "en" : "ds", cmd_addr, bits);
+
+ spi_message_init(&m);
+ memset(&t, 0, sizeof(t));
+
+ t.tx_buf = &cmd_addr;
+ t.len = 2;
+ t.bits_per_word = bits;
+ spi_message_add_tail(&t, &m);
+
+ if (edev->pdata->prepare)
+ edev->pdata->prepare(edev);
+
+ ret = spi_sync(edev->spi, &m);
+ /* have to wait at least Tcsl ns */
+ ndelay(250);
+ if (ret)
+ dev_err(&edev->spi->dev, "erase/write %sable error %d\n",
+ is_on ? "en" : "dis", ret);
+
+ if (edev->pdata->finish)
+ edev->pdata->finish(edev);
+
+ return ret;
+}
+
+static ssize_t
+eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
+ const char *buf, unsigned off)
+{
+ struct spi_message m;
+ struct spi_transfer t[2];
+ int bits, data_len, ret;
+ u16 cmd_addr;
+
+ cmd_addr = OP_WRITE << edev->addrlen;
+
+ if (edev->addrlen == 7) {
+ cmd_addr |= off & 0x7f;
+ bits = 10;
+ data_len = 1;
+ } else {
+ cmd_addr |= (off >> 1) & 0x3f;
+ bits = 9;
+ data_len = 2;
+ }
+
+ dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);
+
+ spi_message_init(&m);
+ memset(t, 0, sizeof(t));
+
+ t[0].tx_buf = (char *)&cmd_addr;
+ t[0].len = 2;
+ t[0].bits_per_word = bits;
+ spi_message_add_tail(&t[0], &m);
+
+ t[1].tx_buf = buf;
+ t[1].len = data_len;
+ t[1].bits_per_word = 8;
+ spi_message_add_tail(&t[1], &m);
+
+ ret = spi_sync(edev->spi, &m);
+ /* have to wait program cycle time Twc ms */
+ mdelay(6);
+ return ret;
+}
+
+static int eeprom_93xx46_write(struct device_d *dev, const int off,
+ const void *val, int count)
+{
+ struct eeprom_93xx46_dev *edev = dev->parent->priv;
+ const char *buf = val;
+ int i, ret, step = 1;
+
+ if (unlikely(off >= edev->size))
+ return -EFBIG;
+ if ((off + count) > edev->size)
+ count = edev->size - off;
+ if (unlikely(!count))
+ return count;
+
+ /* only write even number of bytes on 16-bit devices */
+ if (edev->addrlen == 6) {
+ step = 2;
+ count &= ~1;
+ }
+
+ /* erase/write enable */
+ ret = eeprom_93xx46_ew(edev, 1);
+ if (ret)
+ return ret;
+
+ if (edev->pdata->prepare)
+ edev->pdata->prepare(edev);
+
+ for (i = 0; i < count; i += step) {
+ ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
+ if (ret) {
+ dev_err(&edev->spi->dev, "write failed at %d: %d\n",
+ (int)off + i, ret);
+ break;
+ }
+ }
+
+ if (edev->pdata->finish)
+ edev->pdata->finish(edev);
+
+ /* erase/write disable */
+ eeprom_93xx46_ew(edev, 0);
+ return ret;
+}
+
+static void select_assert(void *context)
+{
+ struct eeprom_93xx46_dev *edev = context;
+
+ if (gpio_is_valid(edev->pdata->select))
+ gpio_set_active(edev->pdata->select, true);
+}
+
+static void select_deassert(void *context)
+{
+ struct eeprom_93xx46_dev *edev = context;
+
+ if (gpio_is_valid(edev->pdata->select))
+ gpio_set_active(edev->pdata->select, false);
+}
+
+static const struct of_device_id eeprom_93xx46_of_table[] = {
+ { .compatible = "eeprom-93xx46", },
+ { .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
+ {}
+};
+
+static int eeprom_93xx46_probe_dt(struct spi_device *spi)
+{
+ const struct of_device_id *of_id =
+ of_match_device(eeprom_93xx46_of_table, &spi->dev);
+ struct device_node *np = spi->dev.device_node;
+ struct eeprom_93xx46_platform_data *pd;
+ enum of_gpio_flags of_flags;
+ unsigned long flags = GPIOF_OUT_INIT_INACTIVE;
+ u32 tmp;
+ int ret;
+
+ pd = xzalloc(sizeof(*pd));
+
+ ret = of_property_read_u32(np, "data-size", &tmp);
+ if (ret < 0) {
+ dev_err(&spi->dev, "data-size property not found\n");
+ return ret;
+ }
+
+ if (tmp == 8) {
+ pd->flags |= EE_ADDR8;
+ } else if (tmp == 16) {
+ pd->flags |= EE_ADDR16;
+ } else {
+ dev_err(&spi->dev, "invalid data-size (%d)\n", tmp);
+ return -EINVAL;
+ }
+
+ if (of_property_read_bool(np, "read-only"))
+ pd->flags |= EE_READONLY;
+
+ pd->select =of_get_named_gpio_flags(np, "select", 0, &of_flags);
+ if (gpio_is_valid(pd->select)) {
+ char *name;
+
+ if (of_flags & OF_GPIO_ACTIVE_LOW)
+ flags |= GPIOF_ACTIVE_LOW;
+
+ name = basprintf("%s select", dev_name(&spi->dev));
+ ret = gpio_request_one(pd->select, flags, name);
+ if (ret < 0)
+ return ret;
+ }
+
+ pd->prepare = select_assert;
+ pd->finish = select_deassert;
+
+ if (gpio_is_valid(pd->select))
+ gpio_set_active(pd->select, false);
+
+ if (of_id->data) {
+ const struct eeprom_93xx46_devtype_data *data = of_id->data;
+
+ pd->quirks = data->quirks;
+ }
+
+ spi->dev.platform_data = pd;
+
+ return 0;
+}
+
+static const struct nvmem_bus eeprom_93xx46_nvmem_bus = {
+ .write = eeprom_93xx46_write,
+ .read = eeprom_93xx46_read,
+};
+
+static int eeprom_93xx46_probe(struct device_d *dev)
+{
+ struct spi_device *spi = (struct spi_device *)dev->type_data;
+ struct eeprom_93xx46_platform_data *pd;
+ struct eeprom_93xx46_dev *edev;
+ int err;
+
+ if (dev->device_node) {
+ err = eeprom_93xx46_probe_dt(spi);
+ if (err < 0)
+ return err;
+ }
+
+ pd = spi->dev.platform_data;
+ if (!pd) {
+ dev_err(&spi->dev, "missing platform data\n");
+ return -ENODEV;
+ }
+
+ edev = xzalloc(sizeof(*edev));
+
+ if (pd->flags & EE_ADDR8)
+ edev->addrlen = 7;
+ else if (pd->flags & EE_ADDR16)
+ edev->addrlen = 6;
+ else {
+ dev_err(&spi->dev, "unspecified address type\n");
+ err = -EINVAL;
+ goto fail;
+ }
+
+ edev->spi = spi;
+ edev->pdata = pd;
+
+ edev->size = 128;
+ edev->nvmem_config.name = dev_name(&spi->dev);
+ edev->nvmem_config.dev = &spi->dev;
+ edev->nvmem_config.read_only = pd->flags & EE_READONLY;
+ edev->nvmem_config.bus = &eeprom_93xx46_nvmem_bus;
+ edev->nvmem_config.stride = 4;
+ edev->nvmem_config.word_size = 1;
+ edev->nvmem_config.size = edev->size;
+
+ dev->priv = edev;
+
+ edev->nvmem = nvmem_register(&edev->nvmem_config);
+ if (IS_ERR(edev->nvmem)) {
+ err = PTR_ERR(edev->nvmem);
+ goto fail;
+ }
+
+ dev_info(&spi->dev, "%d-bit eeprom %s\n",
+ (pd->flags & EE_ADDR8) ? 8 : 16,
+ (pd->flags & EE_READONLY) ? "(readonly)" : "");
+
+ return 0;
+fail:
+ kfree(edev);
+ return err;
+}
+
+static struct driver_d eeprom_93xx46_driver = {
+ .name = "93xx46",
+ .probe = eeprom_93xx46_probe,
+ .of_compatible = DRV_OF_COMPAT(eeprom_93xx46_of_table),
+};
+device_spi_driver(eeprom_93xx46_driver);
+
+
+
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index 92dd86e..cf3f1ee 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -227,7 +227,7 @@ static struct device_node *__of_unflatten_dtb(const void *infdt, bool constprops
p = of_new_property(node, name, nodep, len);
if (!strcmp(name, "phandle") && len == 4)
- node->phandle = be32_to_cpup(p->value);
+ node->phandle = be32_to_cpup(of_property_get_value(p));
dt_struct = dt_struct_advance(&f, dt_struct,
sizeof(struct fdt_property) + len);
diff --git a/drivers/pinctrl/imx-iomux-v1.c b/drivers/pinctrl/imx-iomux-v1.c
index a3f0480..61e8f96 100644
--- a/drivers/pinctrl/imx-iomux-v1.c
+++ b/drivers/pinctrl/imx-iomux-v1.c
@@ -314,4 +314,4 @@ static int imx_iomux_v1_init(void)
{
return platform_driver_register(&imx_iomux_v1_driver);
}
-postcore_initcall(imx_iomux_v1_init);
+core_initcall(imx_iomux_v1_init);
diff --git a/drivers/pinctrl/imx-iomux-v2.c b/drivers/pinctrl/imx-iomux-v2.c
index 0c985a6..60b635a 100644
--- a/drivers/pinctrl/imx-iomux-v2.c
+++ b/drivers/pinctrl/imx-iomux-v2.c
@@ -154,4 +154,4 @@ static int imx_iomux_init(void)
{
return platform_driver_register(&imx_iomux_driver);
}
-postcore_initcall(imx_iomux_init);
+core_initcall(imx_iomux_init);
diff --git a/drivers/pinctrl/imx-iomux-v3.c b/drivers/pinctrl/imx-iomux-v3.c
index 0ab9704..b2a67fc 100644
--- a/drivers/pinctrl/imx-iomux-v3.c
+++ b/drivers/pinctrl/imx-iomux-v3.c
@@ -266,4 +266,4 @@ static int imx_iomux_v3_init(void)
{
return platform_driver_register(&imx_iomux_v3_driver);
}
-postcore_initcall(imx_iomux_v3_init);
+core_initcall(imx_iomux_v3_init);
diff --git a/drivers/pinctrl/mvebu/armada-370.c b/drivers/pinctrl/mvebu/armada-370.c
index 2fd07a7..4fde16a 100644
--- a/drivers/pinctrl/mvebu/armada-370.c
+++ b/drivers/pinctrl/mvebu/armada-370.c
@@ -415,4 +415,4 @@ static int armada_370_pinctrl_init(void)
{
return platform_driver_register(&armada_370_pinctrl_driver);
}
-postcore_initcall(armada_370_pinctrl_init);
+core_initcall(armada_370_pinctrl_init);
diff --git a/drivers/pinctrl/mvebu/armada-xp.c b/drivers/pinctrl/mvebu/armada-xp.c
index 2657db5..089942d 100644
--- a/drivers/pinctrl/mvebu/armada-xp.c
+++ b/drivers/pinctrl/mvebu/armada-xp.c
@@ -405,4 +405,4 @@ static int armada_xp_pinctrl_init(void)
{
return platform_driver_register(&armada_xp_pinctrl_driver);
}
-postcore_initcall(armada_xp_pinctrl_init);
+core_initcall(armada_xp_pinctrl_init);
diff --git a/drivers/pinctrl/mvebu/dove.c b/drivers/pinctrl/mvebu/dove.c
index 8de01e7..2d9d809 100644
--- a/drivers/pinctrl/mvebu/dove.c
+++ b/drivers/pinctrl/mvebu/dove.c
@@ -742,4 +742,4 @@ static int dove_pinctrl_init(void)
{
return platform_driver_register(&dove_pinctrl_driver);
}
-postcore_initcall(dove_pinctrl_init);
+core_initcall(dove_pinctrl_init);
diff --git a/drivers/pinctrl/mvebu/kirkwood.c b/drivers/pinctrl/mvebu/kirkwood.c
index 4b2618c..a347239 100644
--- a/drivers/pinctrl/mvebu/kirkwood.c
+++ b/drivers/pinctrl/mvebu/kirkwood.c
@@ -456,4 +456,4 @@ static int kirkwood_pinctrl_init(void)
{
return platform_driver_register(&kirkwood_pinctrl_driver);
}
-postcore_initcall(kirkwood_pinctrl_init);
+core_initcall(kirkwood_pinctrl_init);
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 630f11b..3201eb9 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -538,7 +538,7 @@ static int at91_pinctrl_init(void)
{
return platform_driver_register(&at91_pinctrl_driver);
}
-postcore_initcall(at91_pinctrl_init);
+core_initcall(at91_pinctrl_init);
static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
{
@@ -718,4 +718,4 @@ static int at91_gpio_init(void)
{
return platform_driver_register(&at91_gpio_driver);
}
-postcore_initcall(at91_gpio_init);
+core_initcall(at91_gpio_init);
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
index 479c31a..b48ed2a 100644
--- a/drivers/pinctrl/pinctrl-mxs.c
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -168,4 +168,4 @@ static int mxs_pinctrl_init(void)
{
return platform_driver_register(&mxs_pinctrl_driver);
}
-postcore_initcall(mxs_pinctrl_init);
+core_initcall(mxs_pinctrl_init);
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 15b74cc..3c581ed 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -167,4 +167,4 @@ static int pcs_init(void)
{
return platform_driver_register(&pcs_driver);
}
-postcore_initcall(pcs_init);
+core_initcall(pcs_init);
diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c
index a7a75bb..e477280 100644
--- a/drivers/pinctrl/pinctrl-tegra-xusb.c
+++ b/drivers/pinctrl/pinctrl-tegra-xusb.c
@@ -518,4 +518,4 @@ static int pinctrl_tegra_xusb_init(void)
{
return platform_driver_register(&pinctrl_tegra_xusb_driver);
}
-postcore_initcall(pinctrl_tegra_xusb_init);
+core_initcall(pinctrl_tegra_xusb_init);
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index eaaba9e..337992c 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -350,4 +350,4 @@ static int pinctrl_tegra20_init(void)
{
return platform_driver_register(&pinctrl_tegra20_driver);
}
-postcore_initcall(pinctrl_tegra20_init);
+core_initcall(pinctrl_tegra20_init);
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 4b271dd..d9b49c5 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -935,4 +935,4 @@ static int pinctrl_tegra30_init(void)
{
return platform_driver_register(&pinctrl_tegra30_driver);
}
-postcore_initcall(pinctrl_tegra30_init);
+core_initcall(pinctrl_tegra30_init);
diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/pinctrl-vf610.c
index a46b0e2..662fa9b 100644
--- a/drivers/pinctrl/pinctrl-vf610.c
+++ b/drivers/pinctrl/pinctrl-vf610.c
@@ -165,4 +165,4 @@ static int pinctrl_vf610_init(void)
{
return platform_driver_register(&pinctrl_vf610_driver);
}
-postcore_initcall(pinctrl_vf610_init);
+core_initcall(pinctrl_vf610_init);
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index a0243be..55bea79 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -32,7 +32,6 @@
#include <of_gpio.h>
#include <io.h>
#include <spi/spi.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include <mach/cpu.h>
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 1842711..645275a 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -18,6 +18,7 @@
#include <errno.h>
#include <init.h>
#include <gpio.h>
+#include <io.h>
#include <clock.h>
#include <usb/ch9.h>
#include <usb/gadget.h>
@@ -30,7 +31,9 @@
#include <asm/byteorder.h>
#include <mach/hardware.h>
-#include <mach/io.h>
+#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10
+#include <mach/at91sam9261.h>
+#endif
#include <mach/board.h>
#include <mach/cpu.h>
#include <mach/at91sam9261_matrix.h>
@@ -691,10 +694,12 @@ static void pullup(struct at91_udc *udc, int is_on)
txvc |= AT91_UDP_TXVC_PUON;
at91_udp_write(udc, AT91_UDP_TXVC, txvc);
} else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) {
+#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10
u32 usbpucr;
- usbpucr = at91_sys_read(AT91_MATRIX_USBPUCR);
- usbpucr |= AT91_MATRIX_USBPUCR_PUON;
- at91_sys_write(AT91_MATRIX_USBPUCR, usbpucr);
+ usbpucr = readl(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_USBPUCR);
+ usbpucr |= AT91SAM9261_MATRIX_USBPUCR_PUON;
+ writel(usbpucr, AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_USBPUCR);
+#endif
}
} else {
stop_activity(udc);
@@ -708,10 +713,12 @@ static void pullup(struct at91_udc *udc, int is_on)
txvc &= ~AT91_UDP_TXVC_PUON;
at91_udp_write(udc, AT91_UDP_TXVC, txvc);
} else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) {
+#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10
u32 usbpucr;
- usbpucr = at91_sys_read(AT91_MATRIX_USBPUCR);
- usbpucr &= ~AT91_MATRIX_USBPUCR_PUON;
- at91_sys_write(AT91_MATRIX_USBPUCR, usbpucr);
+ usbpucr = readl(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_USBPUCR);
+ usbpucr &= ~AT91SAM9261_MATRIX_USBPUCR_PUON;
+ writel(usbpucr, AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_USBPUCR);
+#endif
}
clk_off(udc);
}
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 23f2ab6..d61920e 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -697,7 +697,6 @@ static void cb_download(struct f_fastboot *f_fb, const char *cmd)
fastboot_tx_print(f_fb, "FAILdata invalid size");
} else {
struct usb_request *req = f_fb->out_req;
- struct usb_ep *ep = f_fb->out_ep;
fastboot_tx_print(f_fb, "DATA%08x", f_fb->download_size);
req->complete = rx_handler_dl_image;
req->length = rx_bytes_expected(f_fb);
diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index 5d130f5..aa84334 100644
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -24,7 +24,6 @@
#include <linux/clk.h>
#include <mach/hardware.h>
#include <mach/atmel_hlcdc.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <errno.h>
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index d343c5c..322404f 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -22,7 +22,6 @@
#include <io.h>
#include <init.h>
#include <mach/hardware.h>
-#include <mach/io.h>
#include <errno.h>
#include <linux/clk.h>
diff --git a/dts/Bindings/arm/al,alpine.txt b/dts/Bindings/arm/al,alpine.txt
index f404a4f..d00debe 100644
--- a/dts/Bindings/arm/al,alpine.txt
+++ b/dts/Bindings/arm/al,alpine.txt
@@ -14,75 +14,3 @@ compatible: must contain "al,alpine"
...
}
-
-* CPU node:
-
-The Alpine platform includes cortex-a15 cores.
-enable-method: must be "al,alpine-smp" to allow smp [1]
-
-Example:
-
-cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "al,alpine-smp";
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu@2 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu@3 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <3>;
- };
-};
-
-
-* Alpine CPU resume registers
-
-The CPU resume register are used to define required resume address after
-reset.
-
-Properties:
-- compatible : Should contain "al,alpine-cpu-resume".
-- reg : Offset and length of the register set for the device
-
-Example:
-
-cpu_resume {
- compatible = "al,alpine-cpu-resume";
- reg = <0xfbff5ed0 0x30>;
-};
-
-* Alpine System-Fabric Service Registers
-
-The System-Fabric Service Registers allow various operation on CPU and
-system fabric, like powering CPUs off.
-
-Properties:
-- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
-- reg : Offset and length of the register set for the device
-
-Example:
-
-nb_service {
- compatible = "al,alpine-sysfabric-service", "syscon";
- reg = <0xfb070000 0x10000>;
-};
-
-[1] arm/cpu-enable-method/al,alpine-smp
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index b5c2b5c..4498292 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -57,12 +57,17 @@ Boards with the Amlogic Meson AXG A113D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,a113d", "amlogic,meson-axg";
+Boards with the Amlogic Meson G12A S905D2 SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,g12a";
+
Board compatible values (alphabetically, grouped by SoC):
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
+ - "endless,ec100" (Meson8b)
- "hardkernel,odroid-c1" (Meson8b)
- "tronfy,mxq" (Meson8b)
@@ -101,6 +106,8 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,s400" (Meson axg a113d)
+ - "amlogic,u200" (Meson g12a s905d2)
+
Amlogic Meson Firmware registers Interface
------------------------------------------
diff --git a/dts/Bindings/arm/atmel-at91.txt b/dts/Bindings/arm/atmel-at91.txt
index 31220b5..4bf1b4d 100644
--- a/dts/Bindings/arm/atmel-at91.txt
+++ b/dts/Bindings/arm/atmel-at91.txt
@@ -70,173 +70,3 @@ compatible: must be one of:
- "atmel,samv71q19"
- "atmel,samv71q20"
- "atmel,samv71q21"
-
-Chipid required properties:
-- compatible: Should be "atmel,sama5d2-chipid"
-- reg : Should contain registers location and length
-
-PIT Timer required properties:
-- compatible: Should be "atmel,at91sam9260-pit"
-- reg: Should contain registers location and length
-- interrupts: Should contain interrupt for the PIT which is the IRQ line
- shared across all System Controller members.
-
-System Timer (ST) required properties:
-- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
-- reg: Should contain registers location and length
-- interrupts: Should contain interrupt for the ST which is the IRQ line
- shared across all System Controller members.
-- clocks: phandle to input clock.
-Its subnodes can be:
-- watchdog: compatible should be "atmel,at91rm9200-wdt"
-
-RSTC Reset Controller required properties:
-- compatible: Should be "atmel,<chip>-rstc".
- <chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
-- reg: Should contain registers location and length
-- clocks: phandle to input clock.
-
-Example:
-
- rstc@fffffd00 {
- compatible = "atmel,at91sam9260-rstc";
- reg = <0xfffffd00 0x10>;
- clocks = <&clk32k>;
- };
-
-RAMC SDRAM/DDR Controller required properties:
-- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
- "atmel,at91sam9260-sdramc",
- "atmel,at91sam9g45-ddramc",
- "atmel,sama5d3-ddramc",
-- reg: Should contain registers location and length
-
-Examples:
-
- ramc0: ramc@ffffe800 {
- compatible = "atmel,at91sam9g45-ddramc";
- reg = <0xffffe800 0x200>;
- };
-
-SHDWC Shutdown Controller
-
-required properties:
-- compatible: Should be "atmel,<chip>-shdwc".
- <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
-- reg: Should contain registers location and length
-- clocks: phandle to input clock.
-
-optional properties:
-- atmel,wakeup-mode: String, operation mode of the wakeup mode.
- Supported values are: "none", "high", "low", "any".
-- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
-
-optional at91sam9260 properties:
-- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
-
-optional at91sam9rl properties:
-- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
-- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
-
-optional at91sam9x5 properties:
-- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
-
-Example:
-
- shdwc@fffffd10 {
- compatible = "atmel,at91sam9260-shdwc";
- reg = <0xfffffd10 0x10>;
- clocks = <&clk32k>;
- };
-
-SHDWC SAMA5D2-Compatible Shutdown Controller
-
-1) shdwc node
-
-required properties:
-- compatible: should be "atmel,sama5d2-shdwc".
-- reg: should contain registers location and length
-- clocks: phandle to input clock.
-- #address-cells: should be one. The cell is the wake-up input index.
-- #size-cells: should be zero.
-
-optional properties:
-
-- debounce-delay-us: minimum wake-up inputs debouncer period in
- microseconds. It's usually a board-related property.
-- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
-
-The node contains child nodes for each wake-up input that the platform uses.
-
-2) input nodes
-
-Wake-up input nodes are usually described in the "board" part of the Device
-Tree. Note also that input 0 is linked to the wake-up pin and is frequently
-used.
-
-Required properties:
-- reg: should contain the wake-up input index [0 - 15].
-
-Optional properties:
-- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
- by the child, forces the wake-up of the core power supply on a high level.
- The default is to be active low.
-
-Example:
-
-On the SoC side:
- shdwc@f8048010 {
- compatible = "atmel,sama5d2-shdwc";
- reg = <0xf8048010 0x10>;
- clocks = <&clk32k>;
- #address-cells = <1>;
- #size-cells = <0>;
- atmel,wakeup-rtc-timer;
- };
-
-On the board side:
- shdwc@f8048010 {
- debounce-delay-us = <976>;
-
- input@0 {
- reg = <0>;
- };
-
- input@1 {
- reg = <1>;
- atmel,wakeup-active-high;
- };
- };
-
-Special Function Registers (SFR)
-
-Special Function Registers (SFR) manage specific aspects of the integrated
-memory, bridge implementations, processor and other functionality not controlled
-elsewhere.
-
-required properties:
-- compatible: Should be "atmel,<chip>-sfr", "syscon" or
- "atmel,<chip>-sfrbu", "syscon"
- <chip> can be "sama5d3", "sama5d4" or "sama5d2".
-- reg: Should contain registers location and length
-
- sfr@f0038000 {
- compatible = "atmel,sama5d3-sfr", "syscon";
- reg = <0xf0038000 0x60>;
- };
-
-Security Module (SECUMOD)
-
-The Security Module macrocell provides all necessary secure functions to avoid
-voltage, temperature, frequency and mechanical attacks on the chip. It also
-embeds secure memories that can be scrambled
-
-required properties:
-- compatible: Should be "atmel,<chip>-secumod", "syscon".
- <chip> can be "sama5d2".
-- reg: Should contain registers location and length
-
- secumod@fc040000 {
- compatible = "atmel,sama5d2-secumod", "syscon";
- reg = <0xfc040000 0x100>;
- };
diff --git a/dts/Bindings/arm/atmel-sysregs.txt b/dts/Bindings/arm/atmel-sysregs.txt
new file mode 100644
index 0000000..4b96608
--- /dev/null
+++ b/dts/Bindings/arm/atmel-sysregs.txt
@@ -0,0 +1,171 @@
+Atmel system registers
+
+Chipid required properties:
+- compatible: Should be "atmel,sama5d2-chipid"
+- reg : Should contain registers location and length
+
+PIT Timer required properties:
+- compatible: Should be "atmel,at91sam9260-pit"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the PIT which is the IRQ line
+ shared across all System Controller members.
+
+System Timer (ST) required properties:
+- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the ST which is the IRQ line
+ shared across all System Controller members.
+- clocks: phandle to input clock.
+Its subnodes can be:
+- watchdog: compatible should be "atmel,at91rm9200-wdt"
+
+RSTC Reset Controller required properties:
+- compatible: Should be "atmel,<chip>-rstc".
+ <chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
+- reg: Should contain registers location and length
+- clocks: phandle to input clock.
+
+Example:
+
+ rstc@fffffd00 {
+ compatible = "atmel,at91sam9260-rstc";
+ reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
+ };
+
+RAMC SDRAM/DDR Controller required properties:
+- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
+ "atmel,at91sam9260-sdramc",
+ "atmel,at91sam9g45-ddramc",
+ "atmel,sama5d3-ddramc",
+- reg: Should contain registers location and length
+
+Examples:
+
+ ramc0: ramc@ffffe800 {
+ compatible = "atmel,at91sam9g45-ddramc";
+ reg = <0xffffe800 0x200>;
+ };
+
+SHDWC Shutdown Controller
+
+required properties:
+- compatible: Should be "atmel,<chip>-shdwc".
+ <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
+- reg: Should contain registers location and length
+- clocks: phandle to input clock.
+
+optional properties:
+- atmel,wakeup-mode: String, operation mode of the wakeup mode.
+ Supported values are: "none", "high", "low", "any".
+- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
+
+optional at91sam9260 properties:
+- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
+
+optional at91sam9rl properties:
+- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
+- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
+
+optional at91sam9x5 properties:
+- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
+
+Example:
+
+ shdwc@fffffd10 {
+ compatible = "atmel,at91sam9260-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
+ };
+
+SHDWC SAMA5D2-Compatible Shutdown Controller
+
+1) shdwc node
+
+required properties:
+- compatible: should be "atmel,sama5d2-shdwc".
+- reg: should contain registers location and length
+- clocks: phandle to input clock.
+- #address-cells: should be one. The cell is the wake-up input index.
+- #size-cells: should be zero.
+
+optional properties:
+
+- debounce-delay-us: minimum wake-up inputs debouncer period in
+ microseconds. It's usually a board-related property.
+- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
+
+The node contains child nodes for each wake-up input that the platform uses.
+
+2) input nodes
+
+Wake-up input nodes are usually described in the "board" part of the Device
+Tree. Note also that input 0 is linked to the wake-up pin and is frequently
+used.
+
+Required properties:
+- reg: should contain the wake-up input index [0 - 15].
+
+Optional properties:
+- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
+ by the child, forces the wake-up of the core power supply on a high level.
+ The default is to be active low.
+
+Example:
+
+On the SoC side:
+ shdwc@f8048010 {
+ compatible = "atmel,sama5d2-shdwc";
+ reg = <0xf8048010 0x10>;
+ clocks = <&clk32k>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,wakeup-rtc-timer;
+ };
+
+On the board side:
+ shdwc@f8048010 {
+ debounce-delay-us = <976>;
+
+ input@0 {
+ reg = <0>;
+ };
+
+ input@1 {
+ reg = <1>;
+ atmel,wakeup-active-high;
+ };
+ };
+
+Special Function Registers (SFR)
+
+Special Function Registers (SFR) manage specific aspects of the integrated
+memory, bridge implementations, processor and other functionality not controlled
+elsewhere.
+
+required properties:
+- compatible: Should be "atmel,<chip>-sfr", "syscon" or
+ "atmel,<chip>-sfrbu", "syscon"
+ <chip> can be "sama5d3", "sama5d4" or "sama5d2".
+- reg: Should contain registers location and length
+
+ sfr@f0038000 {
+ compatible = "atmel,sama5d3-sfr", "syscon";
+ reg = <0xf0038000 0x60>;
+ };
+
+Security Module (SECUMOD)
+
+The Security Module macrocell provides all necessary secure functions to avoid
+voltage, temperature, frequency and mechanical attacks on the chip. It also
+embeds secure memories that can be scrambled
+
+required properties:
+- compatible: Should be "atmel,<chip>-secumod", "syscon".
+ <chip> can be "sama5d2".
+- reg: Should contain registers location and length
+
+ secumod@fc040000 {
+ compatible = "atmel,sama5d2-secumod", "syscon";
+ reg = <0xfc040000 0x100>;
+ };
diff --git a/dts/Bindings/arm/bcm/brcm,bcm2835.txt b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
index 1e3e29a..0dcc3ea 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm2835.txt
+++ b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
@@ -42,6 +42,14 @@ Raspberry Pi Compute Module
Required root node properties:
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
+Raspberry Pi Compute Module 3
+Required root node properties:
+compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
+
+Raspberry Pi Compute Module 3 Lite
+Required root node properties:
+compatible = "raspberrypi,3-compute-module-lite", "brcm,bcm2837";
+
Raspberry Pi Zero
Required root node properties:
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 5d1ad09..f8aff65 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -54,9 +54,7 @@ its hardware characteristcs.
clocks the core of that coresight component. The latter clock
is optional.
- * port or ports: The representation of the component's port
- layout using the generic DT graph presentation found in
- "bindings/graph.txt".
+ * port or ports: see "Graph bindings for Coresight" below.
* Additional required properties for System Trace Macrocells (STM):
* reg: along with the physical base address and length of the register
@@ -73,7 +71,7 @@ its hardware characteristcs.
AMBA markee):
- "arm,coresight-replicator"
- * port or ports: same as above.
+ * port or ports: see "Graph bindings for Coresight" below.
* Optional properties for ETM/PTMs:
@@ -96,6 +94,20 @@ its hardware characteristcs.
* interrupts : Exactly one SPI may be listed for reporting the address
error
+Graph bindings for Coresight
+-------------------------------
+
+Coresight components are interconnected to create a data path for the flow of
+trace data generated from the "sources" to their collection points "sink".
+Each coresight component must describe the "input" and "output" connections.
+The connections must be described via generic DT graph bindings as described
+by the "bindings/graph.txt", where each "port" along with an "endpoint"
+component represents a hardware port and the connection.
+
+ * All output ports must be listed inside a child node named "out-ports"
+ * All input ports must be listed inside a child node named "in-ports".
+ * Port address must match the hardware port number.
+
Example:
1. Sinks
@@ -105,10 +117,11 @@ Example:
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- port {
- etb_in_port: endpoint@0 {
- slave-mode;
- remote-endpoint = <&replicator_out_port0>;
+ in-ports {
+ port {
+ etb_in_port: endpoint@0 {
+ remote-endpoint = <&replicator_out_port0>;
+ };
};
};
};
@@ -119,10 +132,11 @@ Example:
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- port {
- tpiu_in_port: endpoint@0 {
- slave-mode;
- remote-endpoint = <&replicator_out_port1>;
+ in-ports {
+ port {
+ tpiu_in_port: endpoint@0 {
+ remote-endpoint = <&replicator_out_port1>;
+ };
};
};
};
@@ -133,22 +147,16 @@ Example:
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* input port */
- port@0 {
- reg = <0>;
+ in-ports {
+ port {
etr_in_port: endpoint {
- slave-mode;
remote-endpoint = <&replicator2_out_port0>;
};
};
+ };
- /* CATU link represented by output port */
- port@1 {
- reg = <1>;
+ out-ports {
+ port {
etr_out_port: endpoint {
remote-endpoint = <&catu_in_port>;
};
@@ -163,7 +171,7 @@ Example:
*/
compatible = "arm,coresight-replicator";
- ports {
+ out-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -181,12 +189,11 @@ Example:
remote-endpoint = <&tpiu_in_port>;
};
};
+ };
- /* replicator input port */
- port@2 {
- reg = <0>;
+ in-ports {
+ port {
replicator_in_port0: endpoint {
- slave-mode;
remote-endpoint = <&funnel_out_port0>;
};
};
@@ -199,40 +206,36 @@ Example:
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* funnel output port */
- port@0 {
- reg = <0>;
+ out-ports {
+ port {
funnel_out_port0: endpoint {
remote-endpoint =
<&replicator_in_port0>;
};
};
+ };
- /* funnel input ports */
- port@1 {
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
reg = <0>;
funnel_in_port0: endpoint {
- slave-mode;
remote-endpoint = <&ptm0_out_port>;
};
};
- port@2 {
+ port@1 {
reg = <1>;
funnel_in_port1: endpoint {
- slave-mode;
remote-endpoint = <&ptm1_out_port>;
};
};
- port@3 {
+ port@2 {
reg = <2>;
funnel_in_port2: endpoint {
- slave-mode;
remote-endpoint = <&etm0_out_port>;
};
};
@@ -248,9 +251,11 @@ Example:
cpu = <&cpu0>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- port {
- ptm0_out_port: endpoint {
- remote-endpoint = <&funnel_in_port0>;
+ out-ports {
+ port {
+ ptm0_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port0>;
+ };
};
};
};
@@ -262,9 +267,11 @@ Example:
cpu = <&cpu1>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
- port {
- ptm1_out_port: endpoint {
- remote-endpoint = <&funnel_in_port1>;
+ out-ports {
+ port {
+ ptm1_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port1>;
+ };
};
};
};
@@ -278,9 +285,11 @@ Example:
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
- port {
- stm_out_port: endpoint {
- remote-endpoint = <&main_funnel_in_port2>;
+ out-ports {
+ port {
+ stm_out_port: endpoint {
+ remote-endpoint = <&main_funnel_in_port2>;
+ };
};
};
};
@@ -295,10 +304,11 @@ Example:
clock-names = "apb_pclk";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- port {
- catu_in_port: endpoint {
- slave-mode;
- remote-endpoint = <&etr_out_port>;
+ in-ports {
+ port {
+ catu_in_port: endpoint {
+ remote-endpoint = <&etr_out_port>;
+ };
};
};
};
diff --git a/dts/Bindings/arm/cpu-capacity.txt b/dts/Bindings/arm/cpu-capacity.txt
index 9b5685a..84262cd 100644
--- a/dts/Bindings/arm/cpu-capacity.txt
+++ b/dts/Bindings/arm/cpu-capacity.txt
@@ -59,9 +59,11 @@ mhz values (normalized w.r.t. the highest value found while parsing the DT).
===========================================
Example 1 (ARM 64-bit, 6-cpu system, two clusters):
-capacities-dmips-mhz are scaled w.r.t. 1024 (cpu@0 and cpu@1)
-supposing cluster0@max-freq=1100 and custer1@max-freq=850,
-final capacities are 1024 for cluster0 and 446 for cluster1
+The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
+are 1024 and 578 for cluster0 and cluster1. Further normalization
+is done by the operating system based on cluster0@max-freq=1100 and
+custer1@max-freq=850, final capacities are 1024 for cluster0 and
+446 for cluster1 (576*850/1100).
cpus {
#address-cells = <2>;
diff --git a/dts/Bindings/arm/cpu-enable-method/al,alpine-smp b/dts/Bindings/arm/cpu-enable-method/al,alpine-smp
index c2e0cc5..35e5afb 100644
--- a/dts/Bindings/arm/cpu-enable-method/al,alpine-smp
+++ b/dts/Bindings/arm/cpu-enable-method/al,alpine-smp
@@ -14,7 +14,28 @@ Related properties: (none)
Note:
This enable method requires valid nodes compatible with
-"al,alpine-cpu-resume" and "al,alpine-nb-service"[1].
+"al,alpine-cpu-resume" and "al,alpine-nb-service".
+
+
+* Alpine CPU resume registers
+
+The CPU resume register are used to define required resume address after
+reset.
+
+Properties:
+- compatible : Should contain "al,alpine-cpu-resume".
+- reg : Offset and length of the register set for the device
+
+
+* Alpine System-Fabric Service Registers
+
+The System-Fabric Service Registers allow various operation on CPU and
+system fabric, like powering CPUs off.
+
+Properties:
+- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
+- reg : Offset and length of the register set for the device
+
Example:
@@ -48,5 +69,12 @@ cpus {
};
};
---
-[1] arm/al,alpine.txt
+cpu_resume {
+ compatible = "al,alpine-cpu-resume";
+ reg = <0xfbff5ed0 0x30>;
+};
+
+nb_service {
+ compatible = "al,alpine-sysfabric-service", "syscon";
+ reg = <0xfb070000 0x10000>;
+};
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index 96dfccc..b0198a1 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -276,7 +276,7 @@ described below.
Usage: optional
Value type: <prop-encoded-array>
Definition: A u32 value that represents the running time dynamic
- power coefficient in units of mW/MHz/uV^2. The
+ power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
@@ -287,7 +287,7 @@ described below.
Pdyn = dynamic-power-coefficient * V^2 * f
- where voltage is in uV, frequency is in MHz.
+ where voltage is in V, frequency is in MHz.
Example 1 (dual-cluster big.LITTLE system 32-bit):
diff --git a/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt b/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt
new file mode 100644
index 0000000..b5cb374
--- /dev/null
+++ b/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt
@@ -0,0 +1,19 @@
+Freescale DCFG
+
+DCFG is the device configuration unit, that provides general purpose
+configuration and status for the device. Such as setting the secondary
+core start address and release the secondary core from holdoff and startup.
+
+Required properties:
+ - compatible: Should contain a chip-specific compatible string,
+ Chip-specific strings are of the form "fsl,<chip>-dcfg",
+ The following <chip>s are known to be supported:
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+
+ - reg : should contain base address and length of DCFG memory-mapped registers
+
+Example:
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1021a-dcfg";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
diff --git a/dts/Bindings/arm/freescale/fsl,layerscape-scfg.txt b/dts/Bindings/arm/freescale/fsl,layerscape-scfg.txt
new file mode 100644
index 0000000..0ab67b0
--- /dev/null
+++ b/dts/Bindings/arm/freescale/fsl,layerscape-scfg.txt
@@ -0,0 +1,19 @@
+Freescale SCFG
+
+SCFG is the supplemental configuration unit, that provides SoC specific
+configuration and status registers for the chip. Such as getting PEX port
+status.
+
+Required properties:
+ - compatible: Should contain a chip-specific compatible string,
+ Chip-specific strings are of the form "fsl,<chip>-scfg",
+ The following <chip>s are known to be supported:
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+
+ - reg: should contain base address and length of SCFG memory-mapped registers
+
+Example:
+ scfg: scfg@1570000 {
+ compatible = "fsl,ls1021a-scfg";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ };
diff --git a/dts/Bindings/arm/freescale/fsl,scu.txt b/dts/Bindings/arm/freescale/fsl,scu.txt
new file mode 100644
index 0000000..46d0af1
--- /dev/null
+++ b/dts/Bindings/arm/freescale/fsl,scu.txt
@@ -0,0 +1,183 @@
+NXP i.MX System Controller Firmware (SCFW)
+--------------------------------------------------------------------
+
+The System Controller Firmware (SCFW) is a low-level system function
+which runs on a dedicated Cortex-M core to provide power, clock, and
+resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
+(QM, QP), and i.MX8QX (QXP, DX).
+
+The AP communicates with the SC using a multi-ported MU module found
+in the LSIO subsystem. The current definition of this MU module provides
+5 remote AP connections to the SC to support up to 5 execution environments
+(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
+with the LSIO DSC IP bus. The SC firmware will communicate with this MU
+using the MSI bus.
+
+System Controller Device Node:
+============================================================
+
+The scu node with the following properties shall be under the /firmware/ node.
+
+Required properties:
+-------------------
+- compatible: should be "fsl,imx-scu".
+- mbox-names: should include "tx0", "tx1", "tx2", "tx3",
+ "rx0", "rx1", "rx2", "rx3".
+- mboxes: List of phandle of 4 MU channels for tx and 4 MU channels
+ for rx. All 8 MU channels must be in the same MU instance.
+ Cross instances are not allowed. The MU instance can only
+ be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
+ to make sure use the one which is not conflict with other
+ execution environments. e.g. ATF.
+ Note:
+ Channel 0 must be "tx0" or "rx0".
+ Channel 1 must be "tx1" or "rx1".
+ Channel 2 must be "tx2" or "rx2".
+ Channel 3 must be "tx3" or "rx3".
+ e.g.
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 0 1
+ &lsio_mu1 0 2
+ &lsio_mu1 0 3
+ &lsio_mu1 1 0
+ &lsio_mu1 1 1
+ &lsio_mu1 1 2
+ &lsio_mu1 1 3>;
+ See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
+ for detailed mailbox binding.
+
+i.MX SCU Client Device Node:
+============================================================
+
+Client nodes are maintained as children of the relevant IMX-SCU device node.
+
+Power domain bindings based on SCU Message Protocol
+------------------------------------------------------------
+
+This binding for the SCU power domain providers uses the generic power
+domain binding[2].
+
+Required properties:
+- compatible: Should be "fsl,scu-pd".
+- #address-cells: Should be 1.
+- #size-cells: Should be 0.
+
+Required properties for power domain sub nodes:
+- #power-domain-cells: Must be 0.
+
+Optional Properties:
+- reg: Resource ID of this power domain.
+ No exist means uncontrollable by user.
+ See detailed Resource ID list from:
+ include/dt-bindings/power/imx-rsrc.h
+- power-domains: phandle pointing to the parent power domain.
+
+Clock bindings based on SCU Message Protocol
+------------------------------------------------------------
+
+This binding uses the common clock binding[1].
+
+Required properties:
+- compatible: Should be "fsl,imx8qxp-clock".
+- #clock-cells: Should be 1. Contains the Clock ID value.
+- clocks: List of clock specifiers, must contain an entry for
+ each required entry in clock-names
+- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+
+See the full list of clock IDs from:
+include/dt-bindings/clock/imx8qxp-clock.h
+
+Pinctrl bindings based on SCU Message Protocol
+------------------------------------------------------------
+
+This binding uses the i.MX common pinctrl binding[3].
+
+Required properties:
+- compatible: Should be "fsl,imx8qxp-iomuxc".
+
+Required properties for Pinctrl sub nodes:
+- fsl,pins: Each entry consists of 3 integers which represents
+ the mux and config setting for one pin. The first 2
+ integers <pin_id mux_mode> are specified using a
+ PIN_FUNC_ID macro, which can be found in
+ <dt-bindings/pinctrl/pads-imx8qxp.h>.
+ The last integer CONFIG is the pad setting value like
+ pull-up on this pin.
+
+ Please refer to i.MX8QXP Reference Manual for detailed
+ CONFIG settings.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/power/power_domain.txt
+[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+
+Example (imx8qxp):
+-------------
+lsio_mu1: mailbox@5d1c0000 {
+ ...
+ #mbox-cells = <2>;
+};
+
+firmware {
+ scu {
+ compatible = "fsl,imx-scu";
+ mbox-names = "tx0", "tx1", "tx2", "tx3",
+ "rx0", "rx1", "rx2", "rx3";
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 0 1
+ &lsio_mu1 0 2
+ &lsio_mu1 0 3
+ &lsio_mu1 1 0
+ &lsio_mu1 1 1
+ &lsio_mu1 1 2
+ &lsio_mu1 1 3>;
+
+ clk: clk {
+ compatible = "fsl,imx8qxp-clk";
+ #clock-cells = <1>;
+ };
+
+ iomuxc {
+ compatible = "fsl,imx8qxp-iomuxc";
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
+ SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+ ...
+ };
+
+ imx8qx-pm {
+ compatible = "fsl,scu-pd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_dma: dma-power-domain {
+ #power-domain-cells = <0>;
+
+ pd_dma_lpuart0: dma-lpuart0@57 {
+ reg = <SC_R_UART_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ ...
+ };
+ ...
+ };
+ };
+};
+
+serial@5a060000 {
+ ...
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ clocks = <&clk IMX8QXP_UART0_CLK>,
+ <&clk IMX8QXP_UART0_IPG_CLK>;
+ clock-names = "per", "ipg";
+ power-domains = <&pd_dma_lpuart0>;
+};
diff --git a/dts/Bindings/arm/fsl.txt b/dts/Bindings/arm/fsl.txt
index 8a1baa2..5074aee 100644
--- a/dts/Bindings/arm/fsl.txt
+++ b/dts/Bindings/arm/fsl.txt
@@ -57,6 +57,50 @@ i.MX6SLL EVK board
Required root node properties:
- compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+i.MX6 Quad Plus SABRE Smart Device Board
+Required root node properties:
+ - compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
+
+i.MX6 Quad Plus SABRE Automotive Board
+Required root node properties:
+ - compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
+
+i.MX6 DualLite SABRE Smart Device Board
+Required root node properties:
+ - compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+
+i.MX6 DualLite/Solo SABRE Automotive Board
+Required root node properties:
+ - compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
+
+i.MX6 SoloLite EVK Board
+Required root node properties:
+ - compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
+
+i.MX6 UltraLite 14x14 EVK Board
+Required root node properties:
+ - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
+
+i.MX6 UltraLiteLite 14x14 EVK Board
+Required root node properties:
+ - compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+
+i.MX6 ULZ 14x14 EVK Board
+Required root node properties:
+ - compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
+
+i.MX6 SoloX SDB Board
+Required root node properties:
+ - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
+
+i.MX6 SoloX Sabre Auto Board
+Required root node properties:
+ - compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
+
+i.MX7 SabreSD Board
+Required root node properties:
+ - compatible = "fsl,imx7d-sdb", "fsl,imx7d";
+
Generic i.MX boards
-------------------
@@ -101,45 +145,6 @@ Freescale LS1021A Platform Device Tree Bindings
Required root node compatible properties:
- compatible = "fsl,ls1021a";
-Freescale SoC-specific Device Tree Bindings
--------------------------------------------
-
-Freescale SCFG
- SCFG is the supplemental configuration unit, that provides SoC specific
-configuration and status registers for the chip. Such as getting PEX port
-status.
- Required properties:
- - compatible: Should contain a chip-specific compatible string,
- Chip-specific strings are of the form "fsl,<chip>-scfg",
- The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
-
- - reg: should contain base address and length of SCFG memory-mapped registers
-
-Example:
- scfg: scfg@1570000 {
- compatible = "fsl,ls1021a-scfg";
- reg = <0x0 0x1570000 0x0 0x10000>;
- };
-
-Freescale DCFG
- DCFG is the device configuration unit, that provides general purpose
-configuration and status for the device. Such as setting the secondary
-core start address and release the secondary core from holdoff and startup.
- Required properties:
- - compatible: Should contain a chip-specific compatible string,
- Chip-specific strings are of the form "fsl,<chip>-dcfg",
- The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
-
- - reg : should contain base address and length of DCFG memory-mapped registers
-
-Example:
- dcfg: dcfg@1ee0000 {
- compatible = "fsl,ls1021a-dcfg";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
- };
-
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
----------------------------------------------------------------
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt
index 199cd36..a97f643 100644
--- a/dts/Bindings/arm/hisilicon/hisilicon.txt
+++ b/dts/Bindings/arm/hisilicon/hisilicon.txt
@@ -8,6 +8,14 @@ HiKey960 Board
Required root node properties:
- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
+Hi3670 SoC
+Required root node properties:
+ - compatible = "hisilicon,hi3670";
+
+HiKey970 Board
+Required root node properties:
+ - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
+
Hi3798cv200 SoC
Required root node properties:
- compatible = "hisilicon,hi3798cv200";
diff --git a/dts/Bindings/arm/keystone/ti,sci.txt b/dts/Bindings/arm/keystone/ti,sci.txt
index 31f5f9a..b56a02c 100644
--- a/dts/Bindings/arm/keystone/ti,sci.txt
+++ b/dts/Bindings/arm/keystone/ti,sci.txt
@@ -45,11 +45,15 @@ Optional Properties:
debug_messages - Map the Debug message region
- reg: register space corresponding to the debug_messages
- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot
+- ti,host-id: Integer value corresponding to the host ID assigned by Firmware
+ for identification of host processing entities such as virtual
+ machines
Example (K2G):
-------------
pmmc: pmmc {
compatible = "ti,k2g-sci";
+ ti,host-id = <2>;
mbox-names = "rx", "tx";
mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>,
<&msgmgr &msgmgr_proxy_pmmc_tx>;
diff --git a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt
index b404d59..4e4a3c0 100644
--- a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt2712-apmixedsys", "syscon"
- "mediatek,mt6797-apmixedsys"
- "mediatek,mt7622-apmixedsys"
+ - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,audsys.txt b/dts/Bindings/arm/mediatek/mediatek,audsys.txt
index 34a69ba..d1606b2 100644
--- a/dts/Bindings/arm/mediatek/mediatek,audsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,audsys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
+ - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- #clock-cells: Must be 1
The AUDSYS controller uses the common clk binding from
diff --git a/dts/Bindings/arm/mediatek/mediatek,bdpsys.txt b/dts/Bindings/arm/mediatek/mediatek,bdpsys.txt
index 4010e37..149567a 100644
--- a/dts/Bindings/arm/mediatek/mediatek,bdpsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,bdpsys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-bdpsys", "syscon"
- "mediatek,mt2712-bdpsys", "syscon"
+ - "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon"
- #clock-cells: Must be 1
The bdpsys controller uses the common clk binding from
diff --git a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
index 8f5335b..f17cfe6 100644
--- a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
+ - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,hifsys.txt b/dts/Bindings/arm/mediatek/mediatek,hifsys.txt
index f5629d6..323905a 100644
--- a/dts/Bindings/arm/mediatek/mediatek,hifsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,hifsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-hifsys", "syscon"
- "mediatek,mt7622-hifsys", "syscon"
+ - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"
- #clock-cells: Must be 1
The hifsys controller uses the common clk binding from
diff --git a/dts/Bindings/arm/mediatek/mediatek,imgsys.txt b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
index 868bd51..3f99672 100644
--- a/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt2712-imgsys", "syscon"
- "mediatek,mt6797-imgsys", "syscon"
+ - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt
index 566f153..89f4272 100644
--- a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt
@@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt2712-infracfg", "syscon"
- "mediatek,mt6797-infracfg", "syscon"
- "mediatek,mt7622-infracfg", "syscon"
+ - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.txt b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
index 4eb8bbe..15d977a 100644
--- a/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt2712-mmsys", "syscon"
- "mediatek,mt6797-mmsys", "syscon"
+ - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,pericfg.txt b/dts/Bindings/arm/mediatek/mediatek,pericfg.txt
index fb58ca8..6755514 100644
--- a/dts/Bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,pericfg.txt
@@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt2701-pericfg", "syscon"
- "mediatek,mt2712-pericfg", "syscon"
- "mediatek,mt7622-pericfg", "syscon"
+ - "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
- "mediatek,mt8135-pericfg", "syscon"
- "mediatek,mt8173-pericfg", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt
index 24014a7..d849465 100644
--- a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt
@@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt2712-topckgen", "syscon"
- "mediatek,mt6797-topckgen"
- "mediatek,mt7622-topckgen"
+ - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8173-topckgen"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
index ea40d05..3212afc 100644
--- a/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt2712-vdecsys", "syscon"
- "mediatek,mt6797-vdecsys", "syscon"
+ - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/msm/qcom,kpss-acc.txt b/dts/Bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..7f69636 100644
--- a/dts/Bindings/arm/msm/qcom,kpss-acc.txt
+++ b/dts/Bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,29 @@ PROPERTIES
the register region. An optional second element specifies
the base address and size of the alias register region.
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to the pll parents.
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: optional
+ Value type: <string>
+ Definition: Name of the output clock. Typically acpuX_aux where X is a
+ CPU number starting at 0.
+
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu0_aux";
};
diff --git a/dts/Bindings/arm/msm/qcom,kpss-gcc.txt b/dts/Bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 0000000..e628758
--- /dev/null
+++ b/dts/Bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,44 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: should be one of the following. The generic compatible
+ "qcom,kpss-gcc" should also be included.
+ "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+ "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: base address and size of the register region
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to the pll parents.
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+ Usage: required
+ Value type: <string>
+ Definition: Name of the output clock. Typically acpu_l2_aux indicating
+ an L2 cache auxiliary clock.
+
+Example:
+
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+ reg = <0x2011000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu_l2_aux";
+ };
diff --git a/dts/Bindings/arm/msm/qcom,llcc.txt b/dts/Bindings/arm/msm/qcom,llcc.txt
index 5e85749..eaee06b 100644
--- a/dts/Bindings/arm/msm/qcom,llcc.txt
+++ b/dts/Bindings/arm/msm/qcom,llcc.txt
@@ -16,11 +16,26 @@ Properties:
- reg:
Usage: required
Value Type: <prop-encoded-array>
- Definition: Start address and the the size of the register region.
+ Definition: The first element specifies the llcc base start address and
+ the size of the register region. The second element specifies
+ the llcc broadcast base address and size of the register region.
+
+- reg-names:
+ Usage: required
+ Value Type: <stringlist>
+ Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".
+
+- interrupts:
+ Usage: required
+ Definition: The interrupt is associated with the llcc edac device.
+ It's used for llcc cache single and double bit error detection
+ and reporting.
Example:
cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
- reg = <0x1100000 0x250000>;
+ reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index acfd3c7..0cc7123 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -5,6 +5,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "vamrs,ficus", "rockchip,rk3399";
+- 96boards RK3399 Rock960 (ROCK960 Consumer Edition)
+ Required root node properties:
+ - compatible = "vamrs,rock960", "rockchip,rk3399";
+
- Amarula Vyasa RK3288 board
Required root node properties:
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
@@ -13,6 +17,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "asus,rk3288-tinker", "rockchip,rk3288";
+- Asus Tinker board S
+ Required root node properties:
+ - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
+
- Kylin RK3036 board:
Required root node properties:
- compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
@@ -59,6 +67,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+- Firefly ROC-RK3399-PC board:
+ Required root node properties:
+ - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@@ -160,6 +172,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "pine64,rock64", "rockchip,rk3328";
+- Pine64 RockPro64 board:
+ Required root node properties:
+ - compatible = "pine64,rockpro64", "rockchip,rk3399";
+
- Rockchip PX3 Evaluation board:
Required root node properties:
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
@@ -168,6 +184,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
+- Rockchip PX30 Evaluation board:
+ Required root node properties:
+ - compatible = "rockchip,px30-evb", "rockchip,px30";
+
- Rockchip RV1108 Evaluation board
Required root node properties:
- compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
diff --git a/dts/Bindings/arm/scu.txt b/dts/Bindings/arm/scu.txt
index 08a5878..74d0a78 100644
--- a/dts/Bindings/arm/scu.txt
+++ b/dts/Bindings/arm/scu.txt
@@ -22,7 +22,7 @@ References:
Example:
-scu@a04100000 {
+scu@a0410000 {
compatible = "arm,cortex-a9-scu";
reg = <0xa0410000 0x100>;
};
diff --git a/dts/Bindings/arm/secure.txt b/dts/Bindings/arm/secure.txt
index e31303f..f27bbff 100644
--- a/dts/Bindings/arm/secure.txt
+++ b/dts/Bindings/arm/secure.txt
@@ -32,7 +32,8 @@ describe the view of Secure world using the standard bindings. These
secure- bindings only need to be used where both the Secure and Normal
world views need to be described in a single device tree.
-Valid Secure world properties:
+Valid Secure world properties
+-----------------------------
- secure-status : specifies whether the device is present and usable
in the secure world. The combination of this with "status" allows
@@ -51,3 +52,19 @@ Valid Secure world properties:
status = "disabled"; secure-status = "okay"; /* S-only */
status = "disabled"; /* disabled in both */
status = "disabled"; secure-status = "disabled"; /* disabled in both */
+
+The secure-chosen node
+----------------------
+
+Similar to the /chosen node which serves as a place for passing data
+between firmware and the operating system, the /secure-chosen node may
+be used to pass data to the Secure OS. Only the properties defined
+below may appear in the /secure-chosen node.
+
+- stdout-path : specifies the device to be used by the Secure OS for
+ its console output. The syntax is the same as for /chosen/stdout-path.
+ If the /secure-chosen node exists but the stdout-path property is not
+ present, the Secure OS should not perform any console output. If
+ /secure-chosen does not exist, the Secure OS should use the value of
+ /chosen/stdout-path instead (that is, use the same device as the
+ Normal world OS).
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index 89b4a38..f5e0f82 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -7,6 +7,8 @@ SoCs:
compatible = "renesas,emev2"
- RZ/A1H (R7S72100)
compatible = "renesas,r7s72100"
+ - RZ/A2 (R7S9210)
+ compatible = "renesas,r7s9210"
- SH-Mobile AG5 (R8A73A00/SH73A0)
compatible = "renesas,sh73a0"
- R-Mobile APE6 (R8A73A40)
@@ -23,6 +25,10 @@ SoCs:
compatible = "renesas,r8a7745"
- RZ/G1C (R8A77470)
compatible = "renesas,r8a77470"
+ - RZ/G2M (R8A774A1)
+ compatible = "renesas,r8a774a1"
+ - RZ/G2E (RA8774C0)
+ compatible = "renesas,r8a774c0"
- R-Car M1A (R8A77781)
compatible = "renesas,r8a7778"
- R-Car H1 (R8A77790)
@@ -107,6 +113,8 @@ Boards:
compatible = "renesas,lager", "renesas,r8a7790"
- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
compatible = "renesas,m3ulcb", "renesas,r8a7796"
+ - M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1))
+ compatible = "renesas,m3nulcb", "renesas,r8a77965"
- Marzen (R0P7779A00010S)
compatible = "renesas,marzen", "renesas,r8a7779"
- Porter (M2-LCDP)
@@ -143,12 +151,12 @@ Boards:
compatible = "renesas,wheat", "renesas,r8a7792"
-Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC
-product and revision information. If present, a device node for this register
-should be added.
+Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
+allows to retrieve SoC product and revision information. If present, a device
+node for this register should be added.
Required properties:
- - compatible: Must be "renesas,prr".
+ - compatible: Must be "renesas,prr" or "renesas,bsid"
- reg: Base address and length of the register block.
diff --git a/dts/Bindings/arm/marvell/marvell,berlin.txt b/dts/Bindings/arm/syna.txt
index 3bab184..2face46 100644
--- a/dts/Bindings/arm/marvell/marvell,berlin.txt
+++ b/dts/Bindings/arm/syna.txt
@@ -1,4 +1,9 @@
-Marvell Berlin SoC Family Device Tree Bindings
+Synaptics SoC Device Tree Bindings
+
+According to https://www.synaptics.com/company/news/conexant-marvell
+Synaptics has acquired the Multimedia Solutions Business of Marvell, so
+berlin SoCs are now Synaptics' SoCs now.
+
---------------------------------------------------------------
Work in progress statement:
@@ -13,6 +18,10 @@ stable binding/ABI.
---------------------------------------------------------------
+Boards with the Synaptics AS370 SoC shall have the following properties:
+ Required root node property:
+ compatible: "syna,as370"
+
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:
diff --git a/dts/Bindings/arm/tegra.txt b/dts/Bindings/arm/tegra.txt
index 32f62bb..c59b15f 100644
--- a/dts/Bindings/arm/tegra.txt
+++ b/dts/Bindings/arm/tegra.txt
@@ -47,12 +47,17 @@ board-specific compatible values:
nvidia,ventana
toradex,apalis_t30
toradex,apalis_t30-eval
+ toradex,apalis_t30-v1.1
+ toradex,apalis_t30-v1.1-eval
toradex,apalis-tk1
toradex,apalis-tk1-eval
- toradex,colibri_t20-512
+ toradex,apalis-tk1-v1.2
+ toradex,apalis-tk1-v1.2-eval
+ toradex,colibri_t20
+ toradex,colibri_t20-eval-v3
+ toradex,colibri_t20-iris
toradex,colibri_t30
toradex,colibri_t30-eval-v3
- toradex,iris
Trusted Foundations
-------------------------------------------
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
index 5a3bf7c..c9fd6d1 100644
--- a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
+++ b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
@@ -34,3 +34,96 @@ Board DTS:
pmc@c360000 {
nvidia,invert-interrupt;
};
+
+== Pad Control ==
+
+On Tegra SoCs a pad is a set of pins which are configured as a group.
+The pin grouping is a fixed attribute of the hardware. The PMC can be
+used to set pad power state and signaling voltage. A pad can be either
+in active or power down mode. The support for power state and signaling
+voltage configuration varies depending on the pad in question. 3.3 V and
+1.8 V signaling voltages are supported on pins where software
+controllable signaling voltage switching is available.
+
+Pad configurations are described with pin configuration nodes which
+are placed under the pmc node and they are referred to by the pinctrl
+client properties. For more information see
+Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
+
+The following pads are present on Tegra186:
+csia csib dsi mipi-bias
+pex-clk-bias pex-clk3 pex-clk2 pex-clk1
+usb0 usb1 usb2 usb-bias
+uart audio hsic dbg
+hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
+sdmmc4 cam dsib dsic
+dsid csic csid csie
+dsif spi ufs dmic-hv
+edp sdmmc1-hv sdmmc3-hv conn
+audio-hv ao-hv
+
+Required pin configuration properties:
+ - pins: A list of strings, each of which contains the name of a pad
+ to be configured.
+
+Optional pin configuration properties:
+ - low-power-enable: Configure the pad into power down mode
+ - low-power-disable: Configure the pad into active mode
+ - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
+ TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
+ The values are defined in
+ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
+
+Note: The power state can be configured on all of the above pads except
+ for ao-hv. Following pads have software configurable signaling
+ voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
+ ao-hv.
+
+Pad configuration state example:
+ pmc: pmc@7000e400 {
+ compatible = "nvidia,tegra186-pmc";
+ reg = <0 0x0c360000 0 0x10000>,
+ <0 0x0c370000 0 0x10000>,
+ <0 0x0c380000 0 0x10000>,
+ <0 0x0c390000 0 0x10000>;
+ reg-names = "pmc", "wake", "aotag", "scratch";
+
+ ...
+
+ sdmmc1_3v3: sdmmc1-3v3 {
+ pins = "sdmmc1-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+ };
+
+ sdmmc1_1v8: sdmmc1-1v8 {
+ pins = "sdmmc1-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+ };
+
+ hdmi_off: hdmi-off {
+ pins = "hdmi";
+ low-power-enable;
+ }
+
+ hdmi_on: hdmi-on {
+ pins = "hdmi";
+ low-power-disable;
+ }
+ };
+
+Pinctrl client example:
+ sdmmc1: sdhci@3400000 {
+ ...
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <&sdmmc1_3v3>;
+ pinctrl-1 = <&sdmmc1_1v8>;
+ };
+
+ ...
+
+ sor0: sor@15540000 {
+ ...
+ pinctrl-0 = <&hdmi_off>;
+ pinctrl-1 = <&hdmi_on>;
+ pinctrl-names = "hdmi-on", "hdmi-off";
+ };
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.txt b/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.txt
index a74b37b..cb12f33 100644
--- a/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -195,3 +195,106 @@ Example:
power-domains = <&pd_audio>;
...
};
+
+== Pad Control ==
+
+On Tegra SoCs a pad is a set of pins which are configured as a group.
+The pin grouping is a fixed attribute of the hardware. The PMC can be
+used to set pad power state and signaling voltage. A pad can be either
+in active or power down mode. The support for power state and signaling
+voltage configuration varies depending on the pad in question. 3.3 V and
+1.8 V signaling voltages are supported on pins where software
+controllable signaling voltage switching is available.
+
+The pad configuration state nodes are placed under the pmc node and they
+are referred to by the pinctrl client properties. For more information
+see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
+The pad name should be used as the value of the pins property in pin
+configuration nodes.
+
+The following pads are present on Tegra124 and Tegra132:
+audio bb cam comp
+csia csb cse dsi
+dsib dsic dsid hdmi
+hsic hv lvds mipi-bias
+nand pex-bias pex-clk1 pex-clk2
+pex-cntrl sdmmc1 sdmmc3 sdmmc4
+sys_ddc uart usb0 usb1
+usb2 usb_bias
+
+The following pads are present on Tegra210:
+audio audio-hv cam csia
+csib csic csid csie
+csif dbg debug-nonao dmic
+dp dsi dsib dsic
+dsid emmc emmc2 gpio
+hdmi hsic lvds mipi-bias
+pex-bias pex-clk1 pex-clk2 pex-cntrl
+sdmmc1 sdmmc3 spi spi-hv
+uart usb0 usb1 usb2
+usb3 usb-bias
+
+Required pin configuration properties:
+ - pins: Must contain name of the pad(s) to be configured.