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Currently arch specific headers can be included with #include <mach/xxx.h>.
With upcoming multi-arch support this is no longer possible as there
won't be a single mach anymore.
Move all i.MX specific header files to include/mach/imx/ to prepare for
multi-arch support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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i.MX7 xload NAND support works like on i.MX6, but the FCB is in a
different format. The FCB page uses BCH62 ECC, has 8 ECC chunks with
128 bytes each with a resulting total page size of 1862 bytes. Also
the page data is written with a pseudo randomizer enabled.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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One particular NAND chip here (Toshiba TC58NVG2S0H) doesn't like it when
the ID or ONFI information is read before the NAND chip is resetted. It
works once, but with the second read the chip will not deliver data
anymore. Reset the NAND chip before accessing it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For non ONFI NAND chips we decode the page layout from the extended ID
information from NAND (basically what nand_decode_ext_id() does in the
MTD layer). For some chips this information is not entirely correct
though. For example some Toshiba chips have this quirk:
/*
* Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
* 512B page. For Toshiba SLC, we decode the 5th/6th byte as
* follows:
* - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
* 110b -> 24nm
* - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
*/
if (chip->id.len >= 6 && nand_is_slc(chip) &&
(chip->id.data[5] & 0x7) == 0x6 /* 24nm */ &&
!(chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND) /* !BENAND */) {
memorg->oobsize = 32 * memorg->pagesize >> 9;
mtd->oobsize = memorg->oobsize;
}
We could try and add these kind of quirks into the xload code, but we
already have the correct information in the FCB. So as long as the
initial information from the ID is enough to read the FCB, we can use
the information containekd therein for further reading from the NAND.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The read page code can be reused by upcoming i.MX7 support, but the ECC
checking will be different. Pull ECC status checking out of the read
page code to make that reusable on i.MX7.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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get_fcb() will be split into SoC specific variants. As a preparation
pull printing the fcb debug info out of this function to not have
to duplicate it in the SoC specific variants later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The code hardcodes i.MX6 addresses, which needs to be factored out for
use in other SoCs' startup. Do this by creating a new imx_nand_params
to hold these information and passing it into the now more generic
code.
No functional change intended. Untested as I got no i.MX6 directly
booting from NAND.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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We have different register defines for the apbh-dma controller. One set
is used in the regular driver, the other one in the xload code. Move the
register defines to a common place and unify their names.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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mxs_nand_check_onfi() and mxs_nand_read_id() setup the same DMA
descriptors with only a small difference. factor out a common
read_id function from it and share the code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We have a set of GPMI register defines in include/, so use them for the
xload driver as well.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Converts the files that licensecheck can determine to be licensed under
GPL-2.0-only or GPL-2.0-or-later and also convert their copyright
statements to SPDX.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.barebox.org/20210522143431.824057-1-u.kleine-koenig@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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'pdesc' is a pointer casted to a 32bit value. This rightfully issues a
compiler warning when being compiled with a 64bit toolchain. This code
is compiled on 64bit systems, but the hardware won't be used there.
Just silence the warning by casting the pointer to unsigned long.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-6-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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During raw NAND booting, GPMI/BCH clock generation might fail due to
improper clock gating conditions and consequently booting from NAND will
fail. This is caused by silicon errata ERR007117. Apply errata fix
workaround before GPMI NAND xload to prevent this from occurring.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Commit is based on initial Sascha Hauer's work. It implements PBL xload
mechanism to load image from GPMI NAND flash.
Additional work was done, so that the NAND's size, page size and OOB's
size are autodetected and not hardcoded. Detection method follows the
same methods as used in NAND driver, meaning NAND ONFI support is probed
and if NAND supports ONFI, NAND memory organization is read from ONFI
parameter page otherwise "READ ID" is used.
Currently only implemented for i.MX6 familly of SoCs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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