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The layerscape images are preceeded by a RCW and PBI, which are interpreted
by the Layerscape Hardware Pre-Bootloader and aren't executable as ARM code.
To maintain the ability to network boot them, add a bootm handler that
skips the fixed-size header.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The "Primary Protected Application" (PPA) is a PSCI compliant firmware
distributed by NXP. It is needed to start the secondary cores on
Layerscape SoCs. Without it Linux will be started in EL3 and doesn't
work properly. The precompiled firmware images can be found on
https://github.com/NXP/qoriq-ppa-binary and are not included in
barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We have several places in the code which which prepares just modified code
for execution. This is done differently in all the places, so add a common
function to be used by all.
Most places called arm_early_mmu_cache_flush(). This function includes
invalidating the instruction cache, so doing it again is unnecessary.
Sometimes we had arm_early_mmu_cache_flush() inside #ifdef CONFIG_MMU.
The ifdef seems unnecessary since we do not have it consistently, so
remove the ifdef.
Some early i.MX xload code had icache_invalidate() but forgot to flush
the caches. Replace the instruction cache invalidation with
sync_caches_for_execution().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The barebox images can simply be written to the partitions, so we can
use bbu_register_std_file_update() for updating to MMC and QSPI.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add a helper function which continues booting from the detected
boot source.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Booting Layerscape from QSPI is a bit tricky and the approach we take is
different from the one U-Boot has taken, so it's worth writing and
reading the following explanation.
The QSPI controller can map the Flash contents into the memory space (On
LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this
memory window. The Layerscape SoCs have a PowerPC history, so it seemed
appropriate for the designers to let the QSPI controller operate in
big endian mode by default. To let the SoC see the correct RCW we have
to write the RCW and PBI data with be64 endianess. Our PBL image tool
pokes the initial binary into the SoC internal SRAM using PBI data as
done with SD/MMC boot aswell. barebox then changes the QSPI controller
endianess to le64 to properly read the barebox binary (placed at an
flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and
jumps to it.
U-Boot has another approach. Here the initial binary is executed in
place directly at 0x40100000. This means the QSPI controller endianess
must be swapped inside the PBI data. This has the effect that the whole
RCW/PBI data must be 64bit endianess swapped *except* the very last word
of the PBI data which contains the CRC command and is read already with
changed endianess. As a conclusion when porting QSPI PBI files from U-Boot
to barebox skip commands changing the endianess in the QSPI controller
and make sure the image is executed in internal SRAM and not in the
Flash memory window.
Lines like this should be removed:
09550000 000f400c
This sets the binary execution address:
09570604 40100000
For barebox it should be changed to 0x10000000.
As a result the PBI files can probably be unified between SD and QSPI
boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Not much to do, there are only a few boot sources supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds support for the TQ TQMLS1046a board. Currently supported:
- UART
- SD/MMC
- Network on eth3, eth2 currently not working for unknown reasons
First stage support exists but is currently untested. Serdes ports are
not yet supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The RDB is the Freescale LS1046a reference board. This patch adds
support for it. Currently supported:
- DDR4 RAM as read from SPD EEPROM
- UART
- SD/MMC
- RGMII network ports
The Serdes ports are currently not supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds basic Layerscape support:
- Makefile/Kconfig
- Register maps
- errata workarounds
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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