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* ARM: Layerscape: Add device tree compatible to image metadataSascha Hauer2019-05-102-0/+6
| | | | | | | Enrich the image metadata with the device tree compatible string the image supports. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: Add environment and update handlersSascha Hauer2019-05-102-0/+80
| | | | | | | The TQMLS1046a can boot from QSPI and SD/MMC. Add partitioning for these devices and barebox environment / barebox update handlers on them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: Support booting from QSPISascha Hauer2019-05-101-1/+1
| | | | | | | | | We have to build correct images suitable for QSPI, thus have to call lspbl_spi_image instead of lspbl_image. In lowlevel code call the xload function which detects the bootsource rather than hardcoding SD/MMC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: unify pbi filesSascha Hauer2019-05-102-33/+2
| | | | | | | | | | | This unifies the two different pbi files. With our approach for QSPI booting differences in the pbi files are not necessary: - We do not do execute in place for QSPI, so we do not need different image execution addresses - Setting up the QSPI clock doesn't hurt even for SD boot Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: print life signs when debuggingSascha Hauer2019-05-101-1/+5
| | | | | | | | Do the UART initialization after the SoC specific lowlevel setup and print the usual '>' when early debuging is enabled. To let this go out properly it seems we have to wait a small amount of time beforehand. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: Sync qspi RCW from TQ U-BootSascha Hauer2019-05-101-4/+4
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: configure qspi dividerSascha Hauer2019-05-101-0/+3
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: ls1046a: Add bbu handlersSascha Hauer2019-05-101-0/+22
| | | | | | | The barebox images can simply be written to the partitions, so we can use bbu_register_std_file_update() for updating to MMC and QSPI. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: ls1046a: Add automatic bootsource detection xload functionSascha Hauer2019-05-103-1/+27
| | | | | | | Add a helper function which continues booting from the detected boot source. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: Add QSPI boot supportSascha Hauer2019-05-103-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting Layerscape from QSPI is a bit tricky and the approach we take is different from the one U-Boot has taken, so it's worth writing and reading the following explanation. The QSPI controller can map the Flash contents into the memory space (On LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this memory window. The Layerscape SoCs have a PowerPC history, so it seemed appropriate for the designers to let the QSPI controller operate in big endian mode by default. To let the SoC see the correct RCW we have to write the RCW and PBI data with be64 endianess. Our PBL image tool pokes the initial binary into the SoC internal SRAM using PBI data as done with SD/MMC boot aswell. barebox then changes the QSPI controller endianess to le64 to properly read the barebox binary (placed at an flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and jumps to it. U-Boot has another approach. Here the initial binary is executed in place directly at 0x40100000. This means the QSPI controller endianess must be swapped inside the PBI data. This has the effect that the whole RCW/PBI data must be 64bit endianess swapped *except* the very last word of the PBI data which contains the CRC command and is read already with changed endianess. As a conclusion when porting QSPI PBI files from U-Boot to barebox skip commands changing the endianess in the QSPI controller and make sure the image is executed in internal SRAM and not in the Flash memory window. Lines like this should be removed: 09550000 000f400c This sets the binary execution address: 09570604 40100000 For barebox it should be changed to 0x10000000. As a result the PBI files can probably be unified between SD and QSPI boot. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: ls1046a: Add bootsource detection supportSascha Hauer2019-05-103-0/+42
| | | | | | Not much to do, there are only a few boot sources supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: defconfig: Enable more featuresSascha Hauer2019-05-091-1/+7
| | | | | | | | The TQMLS1046a has an i2c mux and a i2c gpio expander. Add support for it and also disable early debugging as these are for a single board only. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: Fix pinmux setup for i2c4Sascha Hauer2019-05-081-0/+6
| | | | | | With this the I2C mux on i2c4 works properly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: Unify SD and eMMC imagesSascha Hauer2019-05-082-91/+7
| | | | | | | TQ has unified SD and eMMC images in their U-Boot. Do the same in barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: Update device tree files from tq repositorySascha Hauer2019-05-082-25/+46
| | | | | | Update TQMLS1046a device tree files from TQ repository as of rocko.TQMLS1046A.BSP.SW.0002 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: Use static DDR settingsSascha Hauer2019-05-081-14/+68
| | | | | | | TQ prefers static values in their U-Boot, so use these values in barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: Set cpo_sample valueSascha Hauer2019-05-081-1/+1
| | | | | | | | | | Starting the board issues the warning: WARN: pls set popts->cpo_sample = 0x48 So set the value to the desired value. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: do not use 32bit optimized find bit functionsMichael Tretter2019-05-062-0/+9
| | | | | | | | | | | | | | | | The optimized find bit functions are only implemented for 32 bit and are not built on aarch64 systems. Therefore, for example bootchooser cannot be build for aarch64. Select the generic find_bit implementations on aarch64. As the decision, if lib64 or lib32 is build or not, directly depends on CPU_V8, the generic implementation also should be used if CPU_V8 is selected. Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zii-imx8mq-dev: select ZII_COMMONLucas Stach2019-05-061-0/+1
| | | | | | | | | The RDU3 shares some of the board fixups with the other Zii boards. For those to work ZII_COMMON needs to be enabled. Fixes: d76ba38a1605 (ARM: zii-common: reuse i210 config check for RDU3) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx: disable IPU QoS setup for correct SoCsRouven Czerwinski2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL"), but instead it bails at the Solo, not the SX and SL. The original intent was most probably to add an exception for the i.MX6 Solo as well, so everything else is skipped, including the SX, SL and now the UL and ULL. Fix the code to reflect this. On the SX, SL, UL, ULL, this now avoids writes to memory, which isn't described in the datasheets. On the S, it now configures the QoS settings. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynqmp'Sascha Hauer2019-04-095-2/+177
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| * ARM: zynqmp: switch to firmware clock driverMichael Tretter2019-03-182-0/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | In the device tree, the clock controller is a subnode of the firmware node. Devices refer to the clocks by an id that is shared between the ATF and the driver. While the bindings for the clock controller are already upstream, the device in mainline Linux does not use them, yet. Add them in the Barebox device tree for now. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: add firmware DT nodeThomas Haemmerle2019-03-182-0/+18
| | | | | | | | | | | | | | | | | | Add firmware DT node in ZynqMP device tree. This node uses bindings as per new firmware interface driver. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: move PAYLOAD_ARG_CNT to firmware headerMichael Tretter2019-03-182-2/+2
| | | | | | | | | | | | | | | | In order to use the query() call, the users of the firmware driver need to know the number of arguments. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: populate zynqmp_firmware dt nodeThomas Haemmerle2019-03-181-0/+1
| | | | | | | | | | | | | | | | | | | | The zynqmp_firmware node has sub-nodes for the various APIs to expose the platform management, as e.g. clock management. Therefore, the driver must populate the subnodes to initialize these drivers. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/warnings'Sascha Hauer2019-04-0991-161/+122
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| * | ARM: PXA: Provide prototype for pxa_clear_reset_source()Sascha Hauer2019-03-182-2/+4
| | | | | | | | | | | | | | | | | | | | | Move pxa_clear_reset_source() declaration to a header file where the file implementing it can see it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: sha256: Remove unused header fileSascha Hauer2019-03-181-23/+0
| | | | | | | | | | | | | | | | | | sha256_glue.h is not being unsed in the tree. Remove it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: sha256: Remove unused functionsSascha Hauer2019-03-181-18/+0
| | | | | | | | | | | | | | | | | | sha256_export and sha256_import are not used in the tree. remove them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: boards: Harmonize barebox_arm_reset_vector() prototypeSascha Hauer2019-03-1861-67/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox_arm_reset_vector() is a global function but we never provided a prototype anywhere. The prototypes differ for the different boards, so to provide a common prototype we must harmonize them. void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) Should be suitable for all boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: external-nand-boot: remove unused i.MX21 entrySascha Hauer2019-03-181-3/+0
| | | | | | | | | | | | | | | | | | | | | external nand boot on i.MX21 depends on broken for a long time no. As noone cared we remove it now. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | treewide: Add missing includesSascha Hauer2019-03-1814-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Many files in the tree implement functions, but do not include the header files which provide the prototypes for these functions. This means conflicting prototypes remain undetected. Add the missing includes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | treewide: Make locally used functions staticSascha Hauer2019-03-1816-47/+32
| | | | | | | | | | | | | | | | | | | | | Many functions are only used locally but still are globally visible. Make these function static. Avoids warnings generated with -Wmissing-prototypes Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: semihosting: Fix function prototypeSascha Hauer2019-03-181-1/+1
| | | | | | | | | | | | | | | | | | lsee takes a loff_t pos argument and not a off_t argument. Fix. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/stm32'Sascha Hauer2019-04-0924-62/+359
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| * | | ARM: i.MX8MQ: Don't use cpu_is_mx8mq() at core_initcall levelAndrey Smirnov2019-03-186-25/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since __imx_cpu_type won't be initialized until imx_init()@postcore_initcall is executed cpu_is_mx8mq() will only work correctly at core_initcall level so long as imx_cpu_type does not resolve into __imx_cpu_type. This is currently the case and imx8mq_init_syscnt_frequency() works as expected, but it probably won't be in the future. To avoid this problem introduce imx8mq_cpu_lowlevel_init() and do system counter frequency initialization there. Also convert all of the i.MX8MQ boards to use this new function. Fixes: 5691aed9a ("ARM: i.MX8MQ: Check CPU type in imx8mq_init_syscnt_frequency()") Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX7: Make sure CNTFRQ is initialized early enoughAndrey Smirnov2019-03-183-35/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to make sure that CNTFRQ is initialized before corresponding clocksource driver tries to use it, otherwise we'll end up crashing due to division by zero. We can't convert imx7_timer_init() to be an initcall since it is an i.MX7 specific task, but CPU type information won't be availible until after imx_init() gets executed at postcore_initcall() level. To solve this move all of the necessary code to be a part of imx7_cpu_lowlevel_init(). Note, that original code both hardcoded frequency value to 8MHz as well as tried to write it to the first element of the frequency mode table which appears to be read-only on i.MX7. So while we are at it, simplify the code by adding set_cntfrq() implementation for ARMv7 and copy the code we already using for i.MX8MQ. Fixes: dece70752 ("clocksource: Enable architected timer support for CPU_V7") Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Add initial STM32MP1 supportSascha Hauer2019-03-1315-0/+307
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial STMicroelectronics MP1 support along with support for the DK2 devel board. Only very basic support: - UART - SDRAM memory base/size - No 1st stage support Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clocksource: Enable architected timer support for CPU_V7Sascha Hauer2019-03-111-0/+19
| | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: divider: pass divider flagsSascha Hauer2019-03-111-2/+2
| | |/ | |/| | | | | | | | | | | | | | | | The generic clk divider needs clock flags and divider flags. Fix prototypes to take both as separate arguments. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/misc'Sascha Hauer2019-04-096-30/+33
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| * | | ARM: rpi: add board revision for Compute Module 3+Tomaz Solc2019-03-272-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raspberry Pi Compute Module 3+ was released in January 2019. Source for the new board revision code: https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md Signed-off-by: Tomaz Solc <tomaz.solc@tablix.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | treewide: surround Kconfig file paths with double quotesMasahiro Yamada2019-03-214-29/+29
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Based on Linux commit 8636a1f9677db4f883f29a072f401303acfc2edd This will be needed when you sync Kconfig with Linux 5.0 or later. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/lseek'Sascha Hauer2019-04-082-8/+12
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| * | | ARM: i.MX: bbu: Fix variable type in imx_bbu_internal_v2_write_nand_dbbt()Andrey Smirnov2019-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MEMGETBADBLOCK returns loff_t, so that's the type we should use to store its result. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: bbu: Fix lseek error check in imx_bbu_internal_v2_write_nand_dbbt()Andrey Smirnov2019-03-111-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't use 'int' to store lseek()'s return value to avoid problems with large seek offsets. While at it, make sure to populate return error code from 'errno'. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: bbu: Fix lseek error check in imx_bbu_external_nand_update()Andrey Smirnov2019-03-111-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't use 'int' to store lseek()'s return value to avoid problems with large seek offsets. While at it, make sure to populate return error code from 'errno'. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: bbu: Fix variable type in imx_bbu_external_nand_update()Andrey Smirnov2019-03-111-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | MEMGETBADBLOCK returns loff_t, so that's the type we should use to store its result. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/layerscape'Sascha Hauer2019-04-0848-1/+2273
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| * | | ARM: Add layerscape_defconfigSascha Hauer2019-03-131-0/+111
| | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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