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Most barebox clocksources have a zero priority and if multiple of them
exist, but no higher priority ones, the first to call init_clock wins.
Some supported boards like the Raspberry Pi additionally depended on
initcall ordering to favor one zero-priority clocksource over another.
With the move to deep probe and with Commit b641580deb8c ("of: platform:
Ensure timers are probed early"), device tree blob iteration order could
now dictate which clocksource is ultimately used. This led to a 20 times
slower clock source being chosen on the Raspberry Pi, because the ARM
architected timer was taken instead of the bcm2835 timer.
Fix the root cause by assigning priorities to all clocksource drivers.
Priorities chosen are:
50: device_initcall
60: coredevice_initcall
70: postcore_initcall
80: core_initcall
These priorities are all below 100, which was previously the lowest
positive priority and as they are positive, they win against the dummy
clocksource. This should ensure no priority inversion happens.
Fixes: b641580deb8c ("of: platform: Ensure timers are probed early")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220425094857.674044-4-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The CREDITS file was removed from barebox in 2015 by commit 6570288f2d97
("Remove the CREDITS file"). Remove references to it from several files.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The FSF address has changed in the past. Instead of updating it
each time the address changes, just drop it completely treewide.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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OpenRISC is the original flagship project of the OpenCores community.
This project aims to develop a series of general purpose open source
RISC CPU architectures.
A team from OpenCores provided the first implementation, the OpenRISC
1200, written in the Verilog hardware description language.
Even though I should have created an mach-or1200 directory, it is not
necessary for now. The OpenRISC 1200 CPU is the only one available and
it will be for some time.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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