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* ARM: dts: Add *.dtb.lzo to clean filesSascha Hauer2015-12-111-1/+1
| | | | | | *.dtb.lzo are generated during compilatiion, delete them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: ccxmx53: properly guard initcall for multiimageLucas Stach2015-12-101-0/+3
| | | | | | | | Make sure to not run this board specific initcall on any other board. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2015-12-081-3/+31
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| * socfpga: Initialize emac physels to RGMII correctlyTrent Piepho2015-11-111-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A comment in the socfpga init said that it was "Clearing emac0 PHY interface select to 0", but this was doubly incorrect. It was setting physel for emac1, not emac0, and it was setting physel to 1 (RGMII) not 0 (GMII). All supported socfpga boards use RGMII, and use emac1, so fix the comment to reflect the code. But then extend the code to set the physel for both emac0 and emac1, so it can work on boards that use either or both emacs (which are called gmac0/1 in the dts). The Cyclone V datasheet, page 17-60 "EMAC HPS Interface Initialization", says to set physel while the EMAC is in reset. So place the EMAC in reset while changing physel. The emacs are not in reset as code earlier in the boot has already taken most of the modules out of reset. So put them back in reset while the physel is changed. The Linux kernel does it this way too. If barebox has no network support, there is not much point in configuring the emac physel lines. This would be the case for the xloader pre-bootloader config, which configures physel, doesn't use the network, loads the main barebox, which then reconfigures physel again. Make this code depend on CONFIG_NET so it's just done in the main barebox. The Linux kernel does not need barebox to do this initialization to use networking. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/omap'Sascha Hauer2015-12-081-14/+7
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| * | ARM: omap: Use correct device to mount on /bootSascha Hauer2015-11-101-14/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code tests if a partition (i.e. disk0.0) exists and instead of mounting boot from this partition it uses the whole device (disk0). This only works because the the FAT code accepts a MBR as input and automatically skips it. Let the code use the partition to mount /boot instead as it was intended. We don't have to stat() the partition device, since this error will be caught by mount() anyway, so remove the unnecessary stat(). Reported-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mtd'Sascha Hauer2015-12-085-6/+25
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| * | arm: pxa: Remove pxa_get_nandclk()Sebastian Hesselbarth2015-11-232-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With a common clock provided for NAND controller, get rid of the mach/clock.h way of getting the NAND clock. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | arm: pxa: Add clock for Zylonite NFCSebastian Hesselbarth2015-11-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a clock with clk_add_physbase for the NAND flash controller on Zylonite board. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | arm: pxa: Prepare for NAND clkdev lookup on PXA3xxSebastian Hesselbarth2015-11-233-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP, prepare to provide a common clock for the NAND driver on PXA3xx. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/mmc'Sascha Hauer2015-12-081-0/+2
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| * | | mci: dw_mmc: socfpga: Supply bus-width in platform_dataTrent Piepho2015-11-191-0/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since there is no OF support in the xloader on socfpga it uses the platform_data system. There needs to be a way to supply the equivalent of the DT property bus-width this way to support devices that need to use a smaller bus. So that we don't need to put every flag that might get added to the MMC_CAP list into platform_data, just put the bus width ones into platform_data. The socfpga dts sources specify a bus-width of 4 so use that in the platform_data for socfpga. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/mips'Sascha Hauer2015-12-0812-13/+609
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| * | | MIPS: import optimized string functions from LinuxAleksey Kuleshov2015-11-265-1/+441
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 10x performance gain according to simple test on QEMU malta: barebox:/ time memcpy 0xa0000000 0xa0001000 0x100000 Signed-off-by: Aleksey Kuleshov <rndfax@yandex.ru> Acked-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: tplink-mr3020: skip pbl lowlevel init if running from RAMAntony Pavlov2015-11-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TP-Link MR3020 has 4 MiB flash boot ROM. Usually boot ROM is mapped to 0xbfc00000. However, as AR9331 allows to remap boot ROM to 0xbf000000 it's better to assume that boot ROM starts at 0xbf000000. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: black-swift: skip pbl lowlevel init if running from RAMAntony Pavlov2015-11-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Black Swift has 16 MiB flash boot ROM. The standard board's bootloader (U-Boot_mod) remaps boot ROM to 0xbf000000. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Tested-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: pbl: add pbl_blt macroOleksij Rempel2015-11-131-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Barebox' PBL is able to initialize SoC's memory controller, but it can be used only if PBL runs from ROM or on-chip SRAM. MIPS architecture standard boot vector is 0xbfc00000 so on most MIPS SoCs all addresses higher than 0xbfc00000 belong to boot ROM or on-chip SRAM. Thus there's a simple criterion to check if PBL runs from ROM: just check if current PC is higher than 0xbfc00000. Some MIPS boards have ROM start address lower than 0xbfc00000 so it's reasonable to make ROM start address checking board-dependant. The pbl_blt macro checks if current pc is lower than the first argument (ROM start address). If so then next instruction executed is defined by the second argument of the macro. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Tested-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: allow user to pass incorrect address to md commandAntony Pavlov2015-11-113-7/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit makes it possible to handle exception on incorrect data access so 'md' command just show 'xxxxxxxx' instead of crashing the system. barebox:/ md -l 0xa0000003+4 a0000003: xxxxxxxx .... Without this commit we will get this barebox:/ md -l 0xa0000003+4 a0000003: Ooops, address error on load or ifetch! ... ### ERROR ### Please RESET the board ### Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: import exception registers restoring macros from linux kernelAntony Pavlov2015-11-111-0/+87
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: avoid excessive exceptionAntony Pavlov2015-11-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit clears ERL (ERror Level) flag on start. If this flag is set then we get 'TLB miss on load or ifetch' just after return from exception. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: traps.c: separate registers print stuff to show_regs()Antony Pavlov2015-11-111-7/+12
| | |/ | |/| | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2015-12-0884-331/+1847
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| * | | imx: ocotp: Add code to initialize 'cdev->device_node'Andrey Smirnov2015-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order for cdev_by_device_node() to be able to return approprate character device for <&ocotp> phandle cdev->device_node needs to be initialized with dev->device_node. This patche takes care of that Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | eukrea-cpuimx35: update defconfigFlorian Vallee2015-12-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | enable chipidea usb driver Signed-off-by: Florian Vallee <fvallee@eukrea.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | eukrea-cpuimx35: setup usb through chipidea-imx driverFlorian Vallee2015-12-021-22/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OTG and HOST port are tested with a mass storage device. Signed-off-by: Florian Vallee <fvallee@eukrea.fr> Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | imx35: register usb-misc by defaultFlorian Vallee2015-12-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Florian Vallee <fvallee@eukrea.fr> Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | video: i.MX IPUv3: Set ldb clocks correctlySascha Hauer2015-11-303-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocks for the LVDS display bridge have a fixed /3.5 and a configurable /1,/2 divider in their path. The configurable divider has to be explicitly configured for single/dual channel support, so we can't rely on clock rate parent propagation here. Clear the CLK_SET_RATE_PARENT flag for the configurable divider and configure the clock explicitly in the ldb driver. Tested on a custom i.MX6 board, currently untested on i.MX53. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: mx6sx-sabresdb: set proper hostnameLucas Stach2015-11-3012-1/+433
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also move the initcall to the level matching the name of the function. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: mx6sx-sabresdb: drop unneeded makefile rulesLucas Stach2015-11-301-2/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: ventana: remove unneeded clock init in DCDLucas Stach2015-11-132-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock driver will overwrite those values anyway, so no point in setting them in the DCD. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: imx6dl: Add support for Phytec phyCORE-i.MX6 SOMChristian Hemp2015-11-116-3/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Phytec phyCORE-i.MX6 SOM. - imx6dl-phytec-phycore-som-nand - 256GB RAM on 1 Bank with 32Bit - 10/100MBit Ethernet - NAND - SD - UART Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: imx6q: Add support for Phytec phyCORE-i.MX6 SOMChristian Hemp2015-11-0910-1/+532
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Phytec phyCORE-i.MX6 SOM. Support: - imx6q-phytec-phycore-som-nand: - 1GB RAM on 1 Bank with 64Bit - 1GBit Ethernet - SPI NOR - NAND - SD - UART - imx6q-phytec-phycore-som-emmc - 1GB RAM on 1 Bank with 64Bit - 1GBit Ethernet - SPI NOR - eMMC - SD - UART Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: imx6q: pfla02: add phyFLEX-i.MX6 DualLite 1GiB on one bankStefan Christ2015-11-092-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for phyFLEX-i.MX6 DualLite 1GiB on one bank with NOR. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: imx6dl: pfla02: Add support for 128MB and 256MB RAMStefan Christ2015-11-093-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for phyFLEX-i.MX6 Solo with 128MB and 256MB RAM on one memory bank. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: imx6q: pfla02: Add support for 512MiB RAM on one bankStefan Christ2015-11-092-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for phyFLEX-i.MX6 Quad 512MiB RAM on one bank. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: pfla02: append suffix 1bankStefan Christ2015-11-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current naming schema the phyFLEX-i.MX6 variants which only use one bank for memory have the suffix "1bank". The variants which use two banks of memory have no suffix. The patch fixes the name of the phyFLEX-i.MX6 Solo variant with 512MiB on one bank. So the name of the image file changes from barebox-phytec-pbab01s-512mb.img barebox-phytec-phyboard-subra-512mb.img to barebox-phytec-pbab01s-512mb-1bank.img barebox-phytec-phyboard-subra-512mb-1bank.img This patch touches the phyFLEX-i.MX6 Kit variant and the phyBOARD-SUBRA-i.MX6 which shares the same phyFLEX-i.MX6 module. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: phytec-som-imx6: update environmentChristian Hemp2015-11-096-8/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename sd-ext3 to mmc, remove filesystem type from bootargs and remove bootargs-ip. Add init script 'bootsource' to set boot source priority and bootscript 'spi' for SPI NOR. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: phytec-som-imx6: set loadaddr to start of DDR memory.Stefan Christ2015-11-093-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The loadaddr in the flash-headers for the phyFLEX/phyCARD-i.MX6 was set to 0x20000000 (512MiB). The start of the DDR memory in CPU's memory map is 0x10000000 (256MiB). So the ROM loader loads the barebox image at the memory position 256MiB and higher in the DDR memory. This is a problem when the module doesn't have more than 256MiB of memory. Therefore the loadaddr is set to the start of the DDR memory. The patch was tested on a phyFLEX-i.MX6 Quad with 1GiB RAM on one bank and on a phyCARD-i.MX6 Quad 1GiB RAM on two banks. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | boards: Add phytec-som-imx6Stefan Christ2015-11-0932-205/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The main idea behind this patch is to avoid redundant code. Because of the module similarities of all i.MX6 based phytec boards, we can merge its code. The phytec-som-imx6 merges the code of all i.MX6 based phytec SOMs. So we will have only one "board" in the barebox for phyCARD-i.MX6 and phyFLEX-i.MX6. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: imx6: phycard: use numeric suffix in device treeStefan Christ2015-11-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use numeric suffix for 'environment-sd3' in device tree. This patch prepares phytec-phycard-imx6 for the SOM unification. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: microsom: get MAC address from fusesLucas Stach2015-11-092-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The production models have the MAC fuses blown, so we can use a real MAC address instead of a random one. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: microsom: make ETH work on production modulesLucas Stach2015-11-091-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pre-production modules had an external crystal to generate the PHY reference clock. Production modules rely on the i.MX6 to output the correct clock. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: microsom: add full set of module variants on HummingboardLucas Stach2015-11-095-7/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a full set of DRAM configuration entries we can build images for the full set of modules on Hummingboard. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: microsom: import DCD from SolidRun U-BootLucas Stach2015-11-0912-79/+469
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a complete set of DRAM configuration values for all of the MicroSOM variants extracted from SolidRun U-Boot. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: microsom: change barebox image name for HummingboardLucas Stach2015-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To reflect that the current image is in fact for a combination of a MicroSOM i1 with a Hummingboard baseboard. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: microsom: delete cargo-cult from MakefileLucas Stach2015-11-091-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to carry this cruft around. It's not needed anymore. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: imx6: add MMDC arbitration control register defineLucas Stach2015-11-091-0/+1
| |/ / | | | | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/arm'Sascha Hauer2015-12-085-46/+5
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| * | | ARM: Remove do_execute and thumb2_executeTrent Piepho2015-12-071-26/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 104a6a7ccfb7928ca5dc28c8cbe0ea231ffc45ee support was added for Thumb2. It added do_execute() as a way to provide arch dependent calling veneers for use in "go" and thumb2_execute() as the thumb2 to arm veneer. But thumb2_execute() isn't necessary as gcc generates a proper calling sequence from a standard function pointer call. Thumb2 barebox is compiled with the AAPCS ABI which requires this. It also had a bug and didn't pass the arguments properly, but code execute via "go" rarely uses arguments so this wasn't very noticeable. Since thumb2 was always the only user of do_execute(), go ahead and delete that too. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Remove kernel booting call for thumb2 modeTrent Piepho2015-12-041-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The asm code to do the actual call into the kernel (or another barebox) when compiled in thumb2 mode isn't necessary. gcc generates a perfectly good calling sequence from a normal function pointer call. If it didn't, the code in bootstrap_boot() that uses a function pointer to jump to the 2nd stage barebox from an xloader wouldn't work. It appears to be allowed that the call to kernel() could return, as neither start_linux() nor kernel() are marked noreturn, and there is code after calls to start_linux(). The asm code has a bug in this case, as it uses bx and not blx, and thus doesn't set the link register. Since it's a tail call, this would be okay, but only if the LR value from the start of start_linux() (and the callee-saved registers) are restored beforehand, which isn't done. The gcc generated call sequence will do this. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 20:25:18 +0000