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| * | ARM: dts: imx6: pcaaxl3: Make use of the simpler name phycardStefan Riedmueller2019-12-124-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | Use the simpler name phycard instead of the article number pcaaxl3 for device tree file names and image names of the phyCARD-i.MX 6. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: dts: imx6: pcaaxl3: Update license and model descriptionStefan Riedmueller2019-12-122-18/+8
| | | | | | | | | | | | | | | | | | | | | | | | Make use of SPDX license identifiers and update copyright notices and model descriptions of the phyCARD-i.MX 6 SOM. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: dts: imx6: pcaaxl3: Order nodes alphabeticallyStefan Riedmueller2019-12-121-92/+90
| |/ | | | | | | | | | | | | | | Bring the device tree nodes in alphabetical order and in this context also remove the deprecated iomux group. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: cache_64: invalidate icache in arm_early_mmu_cache_flushAhmad Fatoum2019-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far arm_early_mmu_cache_flush has only been used in preparation for executing newly-written code. For this reason, on ARMv7 and below, it had always invalidate the icache after the dcache flush. We don't do this on ARM64, but sync_caches_for_execution depends on this, which had this comment that didn't hold true for ARM64: > Despite the name arm_early_mmu_cache_flush not only flushes the > data cache, but also invalidates the instruction cache. It might be worthwhile to decouple dcache flushing from icache invalidation, but for now, align what we do on ARM64 with what we do for 32-bit ARMs. This fixes a potential read of stale instructions when loading second-stage barebox from the PBL with MMU disabled. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: cache_64: invalidate dcache in arm_early_mmu_cache_invalidateAhmad Fatoum2019-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some ARM cores, cache contents are indeterminate after a Power-On Reset. Turning on the MMU on such cores risks interpreting random cache lines as valid, causing hard-to-debug errors. For this reason, we always invalidate the dcache on <= ARMv7. Let's do likewise for ARM64. Newer ARM cores tend to come up with their dcaches invalidated already, but for some, like the Cortex-A72, L2 caches are invalidated dependent on a signal sampled at reset, so better play it safe. The icache invalidate here seems to serve no useful purpose. It's kept for now for symmetry with ARM32. Note that this is wrong should barebox be entered with the MMU enabled, but this is so far not the case with any ARM64 platform we support. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM64: entry: save/restore potentially clobbered registersLucas Stach2019-12-201-5/+7
| | | | | | | | | | | | | | | | | | | | | | While the comment is correct that currently arm_early_mmu_cache_invalidate() is only a call to to v8_invalidate_icache_all() , which doesn't clobber x0-x2, this starts to fall apart as soon as we do something more in this function. Make sure to properly save/restore the parameters passed to the entry function. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: aarch64: Add support for passing initrd to LinuxAndrey Smirnov2019-12-201-1/+13
|/ | | | | | | This adds basic support for passing intird to Linux Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynq'Sascha Hauer2019-12-1020-600/+147
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| * ARM: zynqmp: defconfig: reenable DRIVER_NET_MACBMichael Tretter2019-11-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Commit d952a0eeba37 ("Regenerate defconfig files") disabled the macb driver in the ZynqMP defconfig, because CONFIG_NET was not enabled in the defconfig. While not strictly required, you probably want to enable the macb driver on the ZynqMP. Enable CONFIG_NET and reenable CONFIG_DRIVER_NET_MACB. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: defconfig: fix FIRMWARE_ZYNQMP_FPGAMichael Tretter2019-11-251-1/+1
| | | | | | | | | | | | | | | | | | The config item has been renamed from FIRMWARE_ZYNQMP_PL to FIRMWARE_ZYNQMP_FPGA, but the defconfig has not been updated. Update it now. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: add bootsource detectionLucas Stach2019-11-112-2/+26
| | | | | | | | | | | | | | | | Implement the bootsource detection by reading the BOOT_MODE SLCR register which holds the strap values used to select the boot source. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: switch to multi-image buildLucas Stach2019-11-113-12/+10
| | | | | | | | | | | | | | Finally move over to a multi-image based build. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: switch to DT based probingLucas Stach2019-11-116-62/+4
| | | | | | | | | | | | | | | | All the currently supported devices can now be probed from the DT. Remove platform devices and switch to DT. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: zynq: use base address of clock controllerLucas Stach2019-11-111-1/+2
| | | | | | | | | | | | | | | | | | The clock controller is a subregion of the SLCR, use the real base of this region for mapping the registers. This will allow to switch to DT based probing later. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: move clock controller driver to drivers/clkLucas Stach2019-11-112-427/+1
| | | | | | | | | | | | | | No functional change, just adjusting the Zynq code to common practise. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: zedboard: provide DTBLucas Stach2019-11-113-1/+15
| | | | | | | | | | | | | | | | Provide the DTB to allow devices to be probed from there, instead of board code. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: move header generation to zynq_mkimageLucas Stach2019-11-116-96/+87
| | | | | | | | | | | | | | | | | | | | Instead of generating a suitable image header with linker magic, move all of this into zynq_mkimage. The configuration file format and parsing is based on imx-image. This gets us one step further on the road to proper multi-image support. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: add trivial image build mechanismLucas Stach2019-11-112-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Currently this just calls the zynq_mkimage script to stamp in the header checksum. Can be extended to a proper multi-image build later on. This requires a PBL to be build, but as the only supported Zynq board already selects the PBL option in the defconfig there is no big change to the previous status Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: zedboard: enable MACB driver in defconfigLucas Stach2019-11-111-0/+1
| | | | | | | | | | | | | | The board support is a bit more useful with active networking. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/usb'Sascha Hauer2019-12-102-4/+4
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| * | usb: i.MX: Use usb_register_otg_device()Sascha Hauer2019-11-212-4/+4
| | | | | | | | | | | | | | | | | | | | | We now have usb_register_otg_device() to register an "otg" device. Use it and drop the custom code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/stm32'Sascha Hauer2019-12-109-20/+565
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| * | | ARM: stm32mp: dk2: don't hard-code memory sizeAhmad Fatoum2019-11-133-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's new infrastructure for runtime determining RAM size. Use it so we don't need to hard code it in PBL and board code. Because this new infrastructure has some nested function calls, my arm-v7a-linux-gnueabihf-gcc 9.2.1 (OSELAS.Toolchain-2019.09.0) spills to the stack. Add stm32mp_cpu_lowlevel_init, which also sets up a stack after barebox end so this works. Lastly, there's no upstream device tree node for the DDR controller. Add one in the barebox device tree, so we don't have to hardcode the DDRCTRL address into non-pbl code that's run everywhere. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: stm32mp: add stm32mp_cpu_lowlevel_init with stack set upAhmad Fatoum2019-11-131-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When barebox is invoked out of the TF-A v2.1, it's started with sp, r0, r1, r2 all equal to zero. To use the new RAM size calculating stm32mp1_barebox_entry, we need to have a stack to handle spillage. Add a stm32mp_cpu_lowlevel_init wrapper around arm_cpu_lowlevel_init, which additionally configures a 64 byte stack after the end of the barebox binary. This should be enough to help us through the RAM size calculation. If not, compression will fail because of data corruption and stack size can be increased as necessary. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: stm32mp: add basic DDR controller driverAhmad Fatoum2019-11-131-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32MP DDR Controller has a very flexible way of mapping address bits to columns/rows/banks. This is so far configured by the ARM TF-A as part of the SDRAM setup, so we don't need to do this in barebox. Nevertheless reading it out in barebox, allows us to determine unused address bits and thus the total size of SDRAM configured. Add a simple driver that parses the ddrctrl node and adds an appropriate memory bank. This can later be used to remove explicit calls to arm_add_mem_device in board code. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: stm32mp: add helper for querying ram sizeAhmad Fatoum2019-11-135-0/+500
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32MP DDR Controller has a very flexible way of mapping address bits to columns/rows/banks. This is so far configured by the ARM TF-A as part of the SDRAM setup, so we don't need to do this in barebox. Nevertheless reading it out in barebox, allows us to determine unused address bits and thus the total size of SDRAM configured. Add a barebox_arm_entry wrapper that computes the SDRAM size internally, so boards may drop their hard-coded RAM size specifications. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: stm32mp157c-dk2: add optional DEBUG_LL print to entry pointAhmad Fatoum2019-11-131-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TF-A sets up pin muxing and clocking for the UART4 which is the UART suggested by ST for use as debug console. Eventually, we might want to do this ourselves to be sure, but for now lets just stick in a putc_ll('>'), so user selecting DEBUG_LL can see that barebox started. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: dts: stm32mp: move alias to SoC device treeAhmad Fatoum2019-11-132-4/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | We'll want reliable ordering for other SD/MMC using boards as well, thus move the alias out of the board device tree into the SoC's. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/randfixes'Sascha Hauer2019-12-1014-7/+27
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| * | | ARM: mvebu: correct DTB rule for MARVELL_ARMADA_XP_DBLucas Stach2019-12-021-1/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: omap: pfc200: NAND support requires CONFIG_OMAP_GPMCLucas Stach2019-12-021-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: davinci: virt2real: select OFTREE and OFDEVICELucas Stach2019-12-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board probes from DT, so there is no point in allowing a configuration without OF support. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: layerscape: ppa: use sync_for_execution instead of a manual cache flushLucas Stach2019-12-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The copied code is then jumped to, so we need to sync the caches for execution instead of just flushing the data caches. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | pinctrl: at91pio4: move to correct location in KconfigLucas Stach2019-12-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver also depends on PINCTRL, so we should only allow it to be enabled if this option is selected. We can also drop the OFDEVICE dependency then, as this is required for PINCTRL. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: layerscape: select OFTREE and OFDEVICELucas Stach2019-12-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Layerscape architectures probes exclusively from DT, so make sure the correct config options are enabled. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: ARM_SMCCC is only available on >= ARMv7Lucas Stach2019-12-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So anything selecting this option must depend on those CPU architectures. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: layerscape: add missing selects for TQMLS1046ALucas Stach2019-12-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure that all the lowlevel components are selected when only this board is built. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: mxs: bcb: declare locally used functions as staticLucas Stach2019-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: psci: declare locally used functions as staticLucas Stach2019-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: implement CONFIG_PBL_BREAK for ARM64Lucas Stach2019-12-022-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM64 uses a different assembler mnemonic for the breakpoint. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: move into ARM32 specific optee kernel start into lib32 dirLucas Stach2019-12-023-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | Otherwise it may also get built on a ARM64 config, which obviously fails. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/pci'Sascha Hauer2019-12-102-6/+2
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| * | | x86: efi: lds: don't discard any relocation sectionsAhmad Fatoum2019-12-091-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The incoming EFI PCI root bridge IO protocol driver will register PCI fixups. Executing them will fail because the hook function's relocation information is stripped from the final barebox.efi binary. Instead of adding each section by name, just keep all .rela* sections in the final binary. This doesn't yet increase the size of the resulting barebox (yet). Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | PCI: Add layerscape PCIe driverSascha Hauer2019-11-271-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | This adds support for the designware based PCIe controller found on Layerscape SoCs. The driver is based on Linux-5.4. The device tree fixups have been taken from U-Boot 2019.10. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/misc'Sascha Hauer2019-12-104-14/+2
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| * | | MIPS: Makefile: minor codingstyle fixDu Huanpeng2019-11-271-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | it exceeds 80 chararacters per line, but is more readable and agrees agrees with the previous lines. Signed-off-by: Du Huanpeng <duhuanpeng@loongson.cn> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: ath79: art: fix typo in SPDX-License-IdentifierOleksij Rempel2019-11-191-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX6: sabresd: remove inaccurate commentAhmad Fatoum2019-11-081-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board support is likely copied from the freescale-mx6-sabrelite, which requires some GPIOs setup before Ethernet is usable. There is no GPIOs used in this board's code, so remove the comment and along it the <gpio.h> header. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX6: Embedsky E9: remove inaccurate commentAhmad Fatoum2019-11-081-5/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | The board support is likely copied from the freescale-mx6-sabrelite, which requires some GPIOs setup before Ethernet is usable. There is no GPIOs used in this board's code, so remove the comment and along it the <gpio.h> header. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/layerscape'Sascha Hauer2019-12-104-3/+186
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