| Commit message (Collapse) | Author | Age | Files | Lines |
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Define one common state partition for all Protonic related boards
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Link: https://lore.barebox.org/20210607121354.31183-1-o.rempel@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The i.MX8MM USB host controller uses the standard EHCI interface. Enable
support in the defconfig to make this work out of the box.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.barebox.org/20210528133041.1109923-4-l.stach@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.barebox.org/20210528133041.1109923-3-l.stach@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This board is a low-cost 7" touchscreen virtual terminal for
agricultural applications.
There is no upstream Linux DT yet, so we add a minimal DT for use with the
bootloader in this patch.
Signed-off-by: David Jander <david@protonic.nl>
[lst: fixed and cleaned up for upstream]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.barebox.org/20210528133041.1109923-2-l.stach@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The SabreSD comes with different SoC variants. This patch adds support
for the i.MX6QP based board. the DCD data has been taken from U-Boot
2021.04
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210415140313.29161-1-s.hauer@pengutronix.de
Link: https://lore.barebox.org/20210526064249.25378-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The DCD data for the SabreSD board goes back to 2013. This updates the
DCD data with the values from U-Boot-2021.04 which are likely better
maintained.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add variant for 512MB RAM board.
Two firmware files will be generated - one for 256MB and 512MB
respectively; the choice for shipment has to be done and depends on the
underlying hardware.
Signed-off-by: Holger Assmann <h.assmann@pengutronix.de>
v4 ARM: webasto-ccbv2: Add variant with 512MB RAM
Link: https://lore.barebox.org/20210521144313.14990-1-h.assmann@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Converts the files that licensecheck can determine to be licensed under
GPL-2.0-only or GPL-2.0-or-later and also convert their copyright
statements to SPDX.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.barebox.org/20210522143431.824057-1-u.kleine-koenig@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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unsigned idx is checked for >= 0 which is always true and < 0 which is
never true. Use a signed type instead.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-16-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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rel->r_offset < 0 is always false because r_offset is unsigned. Remove
check.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-13-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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'char' can be unsigned, make it signed explicitly to let the check for
being smaller than 0 work..
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-11-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The return value of get_fman_port_icid() is assigned to an unsigned
variable which is then error checked for being smaller than 0. Convert
the variable to a signed type to make this work.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-10-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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struct bbu_data::image is const, so do not modify the image, but create
a copy instead.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-9-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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'pdesc' is a pointer casted to a 32bit value. This rightfully issues a
compiler warning when being compiled with a 64bit toolchain. This code
is compiled on 64bit systems, but the hardware won't be used there.
Just silence the warning by casting the pointer to unsigned long.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-6-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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A timeout is never detected as timeout is tested for being smaller than
0 which never happens for an unsigned variable. Change to a signed type.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-3-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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pin_usage[] is an empty array, no need to iterate over it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-2-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This sets the core processor speed to 800Mhz (from 500). Doing this helps
speed the boot up a bit until the CPU freq govenor takes over.
Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
Link: https://lore.barebox.org/20210613222639.13190-4-marc@cpdesign.com.au
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
Link: https://lore.barebox.org/20210613222639.13190-3-marc@cpdesign.com.au
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Terasic DE10-Nano board is based on CycloneV SoCFPGA (5CSEBA6) with
What has been tested to work:
- SD card
- Gigabit network
- FPGA (FPPx16 & FPPx32)
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Link: https://lore.barebox.org/20210531194019.951-1-gwenj@trabucayre.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Use SAMA5D3_ID_PIOD instead of SAMA5D2_ID_PIOD
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Link: https://lore.barebox.org/20210601084233.7948-1-o.rempel@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The nitrogen6x comes in different memory configurations. Remove the
hardcoded 1G memory node from the upstream device tree.
This fixes booting the 2G variants which otherwise complain with:
CRITICAL: mmu: Critical Error: Can't request SDRAM region for ttb at 8ffe4000
Reported-by: Michael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Michael Olbrich <m.olbrich@pengutronix.de>
Link: https://lore.barebox.org/20210525055007.9207-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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If on-die termination is enabled, the RXC pin of iMX6 will be pulled
high. Since we already have an 10K pull-down on board, the RXC level on
PHY reset will be ~800mV, which is mostly interpreted as 1. On some
reboots we get 0 instead and kernel can't detect the PHY properly.
Since the default 0x020e07ac value is 0, it is sufficient to remove this
entry from the affected imxcfg files.
Since we get stable 0 on pin PHYADDR[2], the PHY address is changed from
4 to 0.
Reported-by: Robin van der Gracht <robin@protonic.nl>
Fixes: 00adc1e33ef8 ("ARM: add imx6 based Protonic boads")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Link: https://lore.barebox.org/20210518083707.15428-1-o.rempel@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Variants of the iTCO are integrated into many Intel southbridges.
They are most often accessed via PCI. Add a driver for the variant
found in the q35 QEMU machine.
It should be straight forward to extend the itco_chipset_info array
to support more variants in future as the need arises. To test, use:
qemu-system-x86_64 -M q35 -global ICH9-LPC.noreboot=false
The last option corresponds to a pin strap option, which can't be
influenced from within the VM.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20210416062436.332665-5-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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UEFI specifies two protocols for abstracting both the PCI host bus
controller and for PCI devices. The protocol for PCI devices provides
function pointers for accessing IO Port, Memory and PCI configuration
space, among others. The protocol for bus controllers provides the
ability to read the root bridge's PCI configuration space and to query
resources.
In barebox, we would want to reuse existing PCI drivers unmodified, so
we utilize the root bridge protocol, unlike most other EFI payloads.
We still utilize the PCI (device) IO protocol, but not for core
functionality: EFI has already enumerated the bus for us and allocated
the EFI handles. It thus makes sense to have the new pci device have the
EFI handle as parent and the controller as grand parent instead of
being sibling with the EFI handles. This is done with an early PCI fixup
that patches the device's parent pointer after consulting the PCI IO
GetLocation.
Driver is written from scratch and hasn't seen heavy usage yet, so it
should be used with care. It was written while consulting the UEFI
2.1D specification.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20210416062436.332665-4-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When running under UEFI, barebox should no redo PCI enumeration,
because the UEFI implementation will likely already have drivers
that won't cope with e.g. BAR addresses changing.
The user-visible effect of this is that likely the framebuffer will
stop working because the UEFI driver won't be able to access it
any longer.
Support this configuration by changing the PCI code to consult the
new pcibios_assign_all_busses().
When it's true, there is no change to previous behavior.
When it's false, reconfiguration is omitted and instead current
configuration is read back from the bus.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20210416062436.332665-3-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Both interconnect and PCI are cache coherent on x86, so we shouldn't
need any special CPU barriers for DMA. Indeed, Linux defined neither
ARCH_HAS_SYNC_DMA_FOR_CPU nor ARCH_HAS_SYNC_DMA_FOR_DEVICE on x86.
It thus seems that the only reordering we need to take care of is
compiler-induced reordering. The Linux memory model that barebox adheres
to as well demands that all accesses to shared data are volatile.
volatile accesses are already guarnateed to not be reordered against
each other, so we don't even need an explicit barrier(), which is
already the case on other architectures that have a disabled MMU.
Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20210416062436.332665-2-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Linux kernel RISC-V header has the same structure as on ARM64. The
barebox header for the architecture also follows the same structure.
Add the architecture-specific glue for barebox to be able to boot both
RISC-V Linux and barebox.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210504104513.2640-3-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Incoming RISC-V bootm implementation will use the same bootm handler for
booting both kernel and barebox. For this to work, the load offset in
the header needs to make sense. As non-generic DT barebox images have
enough knowledge about the platform to know where to place the stack,
they don't require a load offset, thus set it to zero.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210504104513.2640-2-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Linux on RISC-V adopts the same structure as on ARM64 for both 32-
and 64-bit kernel images and it's likely future architectures will
as well. In preparation for adding RISC-V Linux boot support,
move the bulk of the code to a common location for reusability.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210504104513.2640-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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With the recently added SiFive support, we now have enough functionality
to boot a HiFive board to shell:
qemu-system-riscv64 -M sifive_u serial_stdio \
-kernel./images/barebox-hifive-unleashed.img
Some more drivers need to be ported for this to be useful:
- sifive,spi0 needed for talking to SD-Card
- clocksource The riscv-timer seems to be 10x too fast
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210427202309.32077-12-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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SBI appeared to be especially useful to implement a generic console
driver. However, SBI v0.2 removes these services without substitute.
We might find other use for it later, but for now, add the bare minimum
of querying the version of the running SBI implementation.
The cpuinfo command is intentionally kept generic. It can later be
extended to support CONFIG_RISCV_M_MODE as well.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210427202309.32077-7-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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With the recent changes, we can now delete mach-erizo. Do so.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210427202309.32077-6-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Erizo is a RISC-V 32-bit softcore. Because ARCH_RV32I can be selected
independently, a 64-bit barebox images could be built, but the image
produced would be useless. Avoid this by not showing the SOC_ERIZO
prompt when compiling for 64-bit.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210427202309.32077-5-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We already got rid of arch/riscv/mach-virt. Now do the same for
arch/riscv/mach-erizo. This will enable us to build images for all
RISC-V boards at once.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210427202309.32077-4-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The code within was unused and was kept only to make patching the
machine for DEBUG_LL easier. Now that we have PBL console support, this
is no longer needed, so remove it.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20210410110638.2106658-4-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Virt machine has a ns16550a UART at address 0x10000000. As we reuse
the generic DT image for this platform, we can't use either DEBUG_LL or
pbl_console as we would need to hardcode information on what UART is
available where, which wouldn't be correct for other boards.
However, if we parse the board compatible, we could match it with the
appropriate PBL console implementation without sacrificing portability.
Do so.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20210410110638.2106658-3-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The early NS16550 code is written for DEBUG_LL and can't be directly
used with pbl_set_putc if it's disabled. Split off the generic parts
into a new header that can be used by the virt board for PBL console.
DEBUG_LL functionality is unaffected.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20210410110638.2106658-2-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Link: https://lore.barebox.org/20210425063517.120260-1-antonynpavlov@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The environment is unused currently. It should either be included using
bbenv-y or not at all. For now remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This board was merged in 2014 and had no active maintenance since then.
No defconfig even builds this board, so remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This directory was merged accidently as part of the Datamodul Realq7
board support. Remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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So far nobody cared enough to convert the board to multiimage support.
Given that nobody seems to care for this board remove it and reduce the
number of defconfigs by one.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The vendor prefix for MNT Research GmbH in the upstream kernel will be
mntre (not yet landed, but acked by the maintainer). Switch to this
prefix in Barebox now to keep bootspec booting working.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Link: https://lore.barebox.org/20210511201729.63076-1-l.stach@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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