| Commit message (Collapse) | Author | Age | Files | Lines |
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Those will differ between i.MX8MQ and i.MX8MM, so give them the
appropriate prefix before introducing i.MX8MM support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Most of the code in imx8mq.c can be reused for i.MX8MM, so rename it
and compile depending on CONFIG_ARCH_IMX8M.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The imx8mq_* functions can be reused for all i.MX8M SoCs, so rename
them accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Several things are common between the different i.MX8M variants. Add a
Kconfig symbol for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add various base addresses for the i.MX8MM.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds the iomux definitions for the i.MX8MM, taken from U-Boot
2020-rc1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The name mx7_setup_pad already implies the SoC where it runs on, so we
do not have to pass the iomux base address but can hardcode it in the
function. While at it rename it to imx7_setup_pad() which is more
consistent to other i.MX specific functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We already have a mx8_setup_pad() function for early iomux setup, but it
is unused. Add a i.MX8MQ specific wrapper for the function which passes
the correct base address to mx8_setup_pad(). Let the boards use this
function. While at it rename mx8_setup_pad() to imx8_setup_pad() which
is more consistent to other i.MX specific functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds defines for the base addresses common to all currently
existing i.MX8M SoCs. Only the base addresses that are known to be
needed for the early SoC code are added. With this we can reuse the
early code for all variants without guessing that the base addresses
are the same for the other variants.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Parts of iomux-mx8.h are for i.MX8M and others for i.MX8MQ only, but
never for i.MX8 in general. Split this up into different file and
avoid the imx8_ prefix.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Make sure scb9328_devices_init() is only executed on the correct
machine.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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If OP-TEE early loading is performed, OP-TEE will configure the PL210
and lock write access to the controller from the normal world. Test this
by trying to write the same value back and do not configure if we can
not write to the PL310.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add a OP-TEE early loading function which expects a pointer to a valid
tee binary and the device tree. OP-TEE will then be started and barebox
will continue to run in normal mode.
The function start_optee_early should be used in a boards lowlevel.c
file. Ensure that barebox has been relocated and a proper c environment
has been setup beforehand. Depending on the OP-TEE configuration, the
fdt will be modified. If the internal barebox device tree is passed,
OP-TEE will overwrite barebox PBL memory during this modification. Copy
the fdt to a save memory location beforehand to avoid a corruption of
barebox PBL memory.
This also moves the OP-TEE Kconfig symbols into a separate menu.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Subsequent patches will use this to verify the header in the PBL, move
it to common to make it potentially available for both.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The full "STMicroelectronics STM32MP157C-DK2 Discovery Board" is a tad
too long. Abbreviate it to STM32MP157C-DK2 instead.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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On 32-bit hosts, UBSan reports:
====================================================================
UBSAN: Undefined behaviour in ./arch/sandbox/board/hostfile.c:135:12
shift exponent 32 is too large for 32-bit type 'long unsigned int'
====================================================================
Fix this by using a unsigned long long for base. The upper 32-bit
won't be set, but device tree fixups can now read them.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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On a 32-bit host system, UBSan reports:
===============================================================
UBSAN: Undefined behaviour in ./arch/sandbox/os/common.c:115:32
signed integer overflow:
83598 * 1000000000 cannot be represented in type 'long int'
===============================================================
Fix this.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When setting CONFIG_PBL_RELOCATABLE=y (selected by PBL_MULTI_IMAGES) and
CONFIG_RELOCATABLE=n (trying to reduce image size), the PBL is also
linked with "-static" instead of "-pie". The result is a non-working
PBL.
As a side effect, also get rid of erroneous "-Map barebox.map" when
linking the PBL.
Only changed for ARM, are any other platforms affected?
Signed-off-by: Christian Eggers <ceggers@arri.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patch is adding the same PMIC handling as the u-boot spl does for
this Board. It ensures sane defaults.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Currently the pfuze driver is build dependent to ARCH_IMX6. To make it
possible to work with ARCH_IMX8 we move the imx6_poweroff call to an own
poweroff handler.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There is no mx25 board in mainline that actually uses USB. My
(out-of-tree) board has active low polarity which makes it necessary to
have
/delete-property/ over-current-active-high;
over-current-active-low;
in the board's dts which is ugly.
In the absence of this property Linux defaults to active-high and
encourages explicit configuration (see commit 1bf4743f641d ("usb:
chipidea: imx: Warn if oc polarity isn't specified")), so other external
board dts files likely already have this setting anyhow. (OK, maybe a
bit optimistic here :-)
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The commit c5d38e92010174 ("lds: Add and use RO_DATA_SECTION macro")
consolidates all RO sections link script declaration in the single
RO_DATA_SECTION macro. So all all individual RO section declarations
have to be removed from per-arch linker scripts.
Alas the BAREBOX_CLK_TABLE and the BAREBOX_DTB link script sections
were not removed from RISC-V linker script making these sections
declared twice. As a result incorrect __clk_of_table_start and
__dtb_start addresses are passed to the barebox code therefore
the RISC-V barebox is completely unusable.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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.bss __rel_start (OVERLAY) was used to optimize RAM size used by
barebox. Since .bss and __rel_start overlap, we should clear bss only
after __rel_start was used. Following patch changed initialization
sequence to clear .bss before __rel_start:
1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu")
This make relocation buffer unusable and broke relocation with different
symptoms reported by Antony Pavlov <antonynpavlov@gmail.com>:
* iomem output has no information on sdram regions, so memtest is unusable;
* pc = 0xa081232c, relocation does not work, barebox is located with 8M offset
from start of RAM. The board has 256M and relocation routine
should move barebox code much higher;
* pc = 0xa081232c, so barebox code works from KSEG1 not from KSEG0 as MMU=y option implies.
There is a choice of moving .bss clear sequence after __rel_start or
remove this optimization. Since the use of this optimization is minimal
and danger to trap in to similar issue is still high, i prefer to remove
this optimization.
As result of this change, we need to fix calculation of relocation are
size:
relocate_code() calculates relocation area size as a sum (barebox_image_size +
bss_len). barebox_image_size and bss_len are calculated as (__image_end -
__image_start) and (__bss_stop - __bss_start) respectively. This doesn't take
into account relocation data placed between __image_end and __bss_start.
However relocation preserves BSS position relative to image start, as if
relocation data is still there. This causes RAM overflow during BSS
initialization in main_entry(). This problem may be hidden due to the alignment
of the `relocaddr`.
Reported-by: Antony Pavlov <antonynpavlov@gmail.com>
Fixes: 1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since a73850bd76d0 (ARM: imx: disable IPU QoS setup for correct SoCs), which
fixed the condition to not execute the IPU QoS fixups on SoCs that don't have
a IPU, the fixups aren't applied on i.MX6Q/DP anymore, since those SoCs were
missing from the whitelist.
Add a function to make it a bit more clearer what we are checking here and add
the Q/DP SoCs.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The commit 28ed10d6a67c9 ("MIPS: relocation: add relocation support")
introduce the Kconfig CONFIG_MIPS_RELOCATION_TABLE_SIZE parameter
but it is never used.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The C entry function isn't naked, so tries to push to the stack
in the function prologue. This doesn't work on QEMU where there
is no valid SP on entry. Convert the lowlevel entry to the
assembly facilities provided for this case.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Allows for significantly easier debugging of PBL functions.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Calling arm_cpu_lowlevel_init() from zynq_cpu_lowlevel_init() adds a stack
push/pop to the latter function which doesn't work this early in the boot.
As the BootROM apparently hands proccessor control to us in abort(!?!)
mode, setting up a stack requires duplicating most of arm_cpu_lowlevel_init().
To get around this catch-22 move the call to arm_cpu_lowlevel_init back into
the board lowlevel start function, so we don't need a stack at all.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Make sure the required workarounds for CPU errata are applied.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds a Zynq specific CPU lowlevel init function, which applies
the required workarounds for the Cortex A9 r3p0 core.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The node is not available in the upstream DT, yet. Add it
to the Barebox DT extensions.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds a bootm handler for the Zynq image, to allow second
stage booting of a unchanged Zynq boot image.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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If the code is already executing in DRAM, the PS7 init must not be
executed, as it initializes the DRAM controller.
As the OCM can be configured to an address which aliases with the DRAM
address space we can't reliably infer if we are running from OCM or
DRAM from the execution address. So instead of using the address, look
at the OCM mapping, as the BootROM leaves a quite unique mapping behind
with 192KB OCM mapped at the low address and 64KB mapped to the high
address.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Move the PS7 inititalization into its own function. This helps
readability and logically splits the FPGA toolchain generated
setup from the reset of the board init.
Also execute the PS7 setup after the lowlevel CPU init, as this
is the regular order used in the Barebox codebase.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This enabled more features for the rasperrypi boards:
- DWC2 USB driver
- Networking support
- GPIO EXP driver
- LED support
- more commands
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This makes sure that during a mailbox transfer no other mailbox transfer
is started. This happens on a raspberrypi3 where one GPIO on the
firmware GPIO controller (which is controlled via mailbox) is registered
as a heartbeat LED. With this it can happen that during a mailbox
transfer the poller which drives the heartbeat LED is triggered in
is_timeout() which results in corrupted transfers.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Enable the recently introduced GPIO exp driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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To give the user an idea where the messages come from.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Taken from the kernel adopted to barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Not all messages return a valid response as they do not send a response
at all. This is at least true for the SET_GPIO_STATE and SET_GPIO_CONFIG
messages.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Enable the USB Power domain during startup. The power domain is
abstracted as a regulator in barebox, but modelled as a power domain in
the device tree. Until this is sorted out just enable the power domain
or regulator in the board code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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