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* arm: baltos: use compressed DTB imagesYegor Yefremov2020-02-251-3/+3
| | | | | | | This reduces the size of MLO enough to fit into SRAM. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: dts: stm32mp: align barebox dtsi name with upstreamAhmad Fatoum2020-02-192-1/+1
| | | | | | | | | | | | | Upstream has split stm32mp157c.dtsi into three files: - stm32mp157.dtsi: GPU, DSI and stm32mp153.dtsi - stm32mp153.dtsi: 2x CAN, 2nd Cortex-A7 and stm32mp151.dtsi - stm32mp151.dtsi: everything else Have our barebox specific fixup file follow the new naming scheme. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: scb9328: Add missing machine protectionSascha Hauer2020-02-181-0/+3
| | | | | | | Make sure scb9328_devices_init() is only executed on the correct machine. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/optee'Sascha Hauer2020-02-189-10/+172
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| * ARM: mach-imx: test PL310 write accessRouven Czerwinski2020-01-301-0/+20
| | | | | | | | | | | | | | | | | | | | If OP-TEE early loading is performed, OP-TEE will configure the PL210 and lock write access to the controller from the normal world. Test this by trying to write the same value back and do not configure if we can not write to the PL310. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: add optee early loading functionRouven Czerwinski2020-01-303-1/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a OP-TEE early loading function which expects a pointer to a valid tee binary and the device tree. OP-TEE will then be started and barebox will continue to run in normal mode. The function start_optee_early should be used in a boards lowlevel.c file. Ensure that barebox has been relocated and a proper c environment has been setup beforehand. Depending on the OP-TEE configuration, the fdt will be modified. If the internal barebox device tree is passed, OP-TEE will overwrite barebox PBL memory during this modification. Copy the fdt to a save memory location beforehand to avoid a corruption of barebox PBL memory. This also moves the OP-TEE Kconfig symbols into a separate menu. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: import setjmp implementation from U-BootRouven Czerwinski2020-01-305-0/+108
| | | | | | | | | | Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * optee: move optee_verify_header() to commonRouven Czerwinski2020-01-281-9/+3
| | | | | | | | | | | | | | | | Subsequent patches will use this to verify the header in the PBL, move it to common to make it potentially available for both. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2020-02-185-2/+12
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| * | ARM: stm32mp: dk2: barebox_set_model to shorter nameAhmad Fatoum2020-02-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The full "STMicroelectronics STM32MP157C-DK2 Discovery Board" is a tad too long. Abbreviate it to STM32MP157C-DK2 instead. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: hostfile: fix UB-inducing shiftAhmad Fatoum2020-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 32-bit hosts, UBSan reports: ==================================================================== UBSAN: Undefined behaviour in ./arch/sandbox/board/hostfile.c:135:12 shift exponent 32 is too large for 32-bit type 'long unsigned int' ==================================================================== Fix this by using a unsigned long long for base. The upper 32-bit won't be set, but device tree fixups can now read them. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: fix signed integer overflowAhmad Fatoum2020-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a 32-bit host system, UBSan reports: =============================================================== UBSAN: Undefined behaviour in ./arch/sandbox/os/common.c:115:32 signed integer overflow: 83598 * 1000000000 cannot be represented in type 'long int' =============================================================== Fix this. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | images: Use separate LDFLAGS for PBLChristian Eggers2020-02-102-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting CONFIG_PBL_RELOCATABLE=y (selected by PBL_MULTI_IMAGES) and CONFIG_RELOCATABLE=n (trying to reduce image size), the PBL is also linked with "-static" instead of "-pie". The result is a non-working PBL. As a side effect, also get rid of erroneous "-Map barebox.map" when linking the PBL. Only changed for ARM, are any other platforms affected? Signed-off-by: Christian Eggers <ceggers@arri.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2020-02-184-12/+50
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| * | | ARM: phyCORE-i.MX8M SOM: add pmic initialisation for power goodMichael Grzeschik2020-02-031-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding the same PMIC handling as the u-boot spl does for this Board. It ensures sane defaults. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | regulator: pfuze: add support to other architecturesMichael Grzeschik2020-02-032-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the pfuze driver is build dependent to ARCH_IMX6. To make it possible to work with ARCH_IMX8 we move the imx6_poweroff call to an own poweroff handler. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | imx25: drop global over-current setting for USBUwe Kleine-König2020-01-161-8/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no mx25 board in mainline that actually uses USB. My (out-of-tree) board has active low polarity which makes it necessary to have /delete-property/ over-current-active-high; over-current-active-low; in the board's dts which is ugly. In the absence of this property Linux defaults to active-high and encourages explicit configuration (see commit 1bf4743f641d ("usb: chipidea: imx: Warn if oc polarity isn't specified")), so other external board dts files likely already have this setting anyhow. (OK, maybe a bit optimistic here :-) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/dts'Sascha Hauer2020-02-181-8/+0
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| * | | dts: update to v5.6-rc1Sascha Hauer2020-02-181-8/+0
| | |/ | |/| | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | RISC-V: unbreak built-in dtbAntony Pavlov2020-02-031-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit c5d38e92010174 ("lds: Add and use RO_DATA_SECTION macro") consolidates all RO sections link script declaration in the single RO_DATA_SECTION macro. So all all individual RO section declarations have to be removed from per-arch linker scripts. Alas the BAREBOX_CLK_TABLE and the BAREBOX_DTB link script sections were not removed from RISC-V linker script making these sections declared twice. As a result incorrect __clk_of_table_start and __dtb_start addresses are passed to the barebox code therefore the RISC-V barebox is completely unusable. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | MIPS: don't overlay relocation data with BSSOleksij Rempel2020-02-032-2/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | .bss __rel_start (OVERLAY) was used to optimize RAM size used by barebox. Since .bss and __rel_start overlap, we should clear bss only after __rel_start was used. Following patch changed initialization sequence to clear .bss before __rel_start: 1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu") This make relocation buffer unusable and broke relocation with different symptoms reported by Antony Pavlov <antonynpavlov@gmail.com>: * iomem output has no information on sdram regions, so memtest is unusable; * pc = 0xa081232c, relocation does not work, barebox is located with 8M offset from start of RAM. The board has 256M and relocation routine should move barebox code much higher; * pc = 0xa081232c, so barebox code works from KSEG1 not from KSEG0 as MMU=y option implies. There is a choice of moving .bss clear sequence after __rel_start or remove this optimization. Since the use of this optimization is minimal and danger to trap in to similar issue is still high, i prefer to remove this optimization. As result of this change, we need to fix calculation of relocation are size: relocate_code() calculates relocation area size as a sum (barebox_image_size + bss_len). barebox_image_size and bss_len are calculated as (__image_end - __image_start) and (__bss_stop - __bss_start) respectively. This doesn't take into account relocation data placed between __image_end and __bss_start. However relocation preserves BSS position relative to image start, as if relocation data is still there. This causes RAM overflow during BSS initialization in main_entry(). This problem may be hidden due to the alignment of the `relocaddr`. Reported-by: Antony Pavlov <antonynpavlov@gmail.com> Fixes: 1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / ARM: imx6: properly check for IPU presenceLucas Stach2020-01-271-2/+11
|/ | | | | | | | | | | | | Since a73850bd76d0 (ARM: imx: disable IPU QoS setup for correct SoCs), which fixed the condition to not execute the IPU QoS fixups on SoCs that don't have a IPU, the fixups aren't applied on i.MX6Q/DP anymore, since those SoCs were missing from the whitelist. Add a function to make it a bit more clearer what we are checking here and add the Q/DP SoCs. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: actually use CONFIG_MIPS_RELOCATION_TABLE_SIZEAntony Pavlov2020-01-161-1/+1
| | | | | | | | | The commit 28ed10d6a67c9 ("MIPS: relocation: add relocation support") introduce the Kconfig CONFIG_MIPS_RELOCATION_TABLE_SIZE parameter but it is never used. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: qemu-virt64: convert to assembly entryLucas Stach2020-01-163-2/+16
| | | | | | | | | | The C entry function isn't naked, so tries to push to the stack in the function prologue. This doesn't work on QEMU where there is no valid SP on entry. Convert the lowlevel entry to the assembly facilities provided for this case. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynq'Sascha Hauer2020-01-157-4/+150
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| * ARM: zynq: zedboard: add PBL console supportLucas Stach2020-01-141-0/+16
| | | | | | | | | | | | | | Allows for significantly easier debugging of PBL functions. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: zed: partially revert zynq_cpu_lowlevel_init() chnagesLucas Stach2020-01-142-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Calling arm_cpu_lowlevel_init() from zynq_cpu_lowlevel_init() adds a stack push/pop to the latter function which doesn't work this early in the boot. As the BootROM apparently hands proccessor control to us in abort(!?!) mode, setting up a stack requires duplicating most of arm_cpu_lowlevel_init(). To get around this catch-22 move the call to arm_cpu_lowlevel_init back into the board lowlevel start function, so we don't need a stack at all. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: zed: use zynq_cpu_lowlevel_init()Lucas Stach2020-01-081-1/+2
| | | | | | | | | | | | | | Make sure the required workarounds for CPU errata are applied. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: add Zynq specific lowlevel CPU init functionLucas Stach2020-01-083-0/+24
| | | | | | | | | | | | | | | | This adds a Zynq specific CPU lowlevel init function, which applies the required workarounds for the Cortex A9 r3p0 core. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: zed: add QSPI flash supportLucas Stach2019-12-202-0/+27
| | | | | | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: add QSPI DT nodeLucas Stach2019-12-201-0/+15
| | | | | | | | | | | | | | | | The node is not available in the upstream DT, yet. Add it to the Barebox DT extensions. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: add Zynq image bootm handlerLucas Stach2019-12-112-1/+50
| | | | | | | | | | | | | | | | This adds a bootm handler for the Zynq image, to allow second stage booting of a unchanged Zynq boot image. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: zedboard: allow lowlevel init to be called as second stageLucas Stach2019-12-111-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the code is already executing in DRAM, the PS7 init must not be executed, as it initializes the DRAM controller. As the OCM can be configured to an address which aliases with the DRAM address space we can't reliably infer if we are running from OCM or DRAM from the execution address. So instead of using the address, look at the OCM mapping, as the BootROM leaves a quite unique mapping behind with 192KB OCM mapped at the low address and 64KB mapped to the high address. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: zedboard: split out PS7 initLucas Stach2019-12-111-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | Move the PS7 inititalization into its own function. This helps readability and logically splits the FPGA toolchain generated setup from the reset of the board init. Also execute the PS7 setup after the lowlevel CPU init, as this is the regular order used in the Barebox codebase. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/rpi'Sascha Hauer2020-01-158-34/+114
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| * | ARM: rpi_defconfig: Enable more featuresSascha Hauer2020-01-081-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enabled more features for the rasperrypi boards: - DWC2 USB driver - Networking support - GPIO EXP driver - LED support - more commands Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: rpi mailbox: Use non interruptible timeoutSascha Hauer2020-01-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes sure that during a mailbox transfer no other mailbox transfer is started. This happens on a raspberrypi3 where one GPIO on the firmware GPIO controller (which is controlled via mailbox) is registered as a heartbeat LED. With this it can happen that during a mailbox transfer the poller which drives the heartbeat LED is triggered in is_timeout() which results in corrupted transfers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: rpi_defconfig: Enable raspberry GPIO exp driverSascha Hauer2020-01-081-0/+1
| | | | | | | | | | | | | | | | | | Enable the recently introduced GPIO exp driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: bcm2835 mbox: use pr_* to print messagesSascha Hauer2020-01-081-17/+19
| | | | | | | | | | | | | | | | | | To give the user an idea where the messages come from. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | gpio: Add raspberrypi exp gpio driverSascha Hauer2020-01-081-0/+4
| | | | | | | | | | | | | | | | | | Taken from the kernel adopted to barebox. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: bcm2835 mbox: Remove response valid checkSascha Hauer2020-01-081-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | Not all messages return a valid response as they do not send a response at all. This is at least true for the SET_GPIO_STATE and SET_GPIO_CONFIG messages. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | rpi: Enable USB Power domain during startupSascha Hauer2019-12-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the USB Power domain during startup. The power domain is abstracted as a regulator in barebox, but modelled as a power domain in the device tree. Until this is sorted out just enable the power domain or regulator in the board code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | device: Introduce dma_offsetSascha Hauer2019-12-203-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For devices that do not have a 1:1 mapping between DMA and CPU we need a dma_offset. This adds dma_offset to struct device_d and starts honoring it in ARM dma_(un)map_single(). Also we add some comments to functions that would normally need a device argument to make the DMA <-> CPU translations device specific. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: rpi: Do not warn when firmware doesn't pass a dtbSascha Hauer2019-12-192-5/+15
| |/ | | | | | | | | | | | | When there is no dtb placed in the boot partition then none is passed by the firmware to barebox. This may be intended, so do not warn about it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2020-01-157-9/+9
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| * | MIPS: dts: rename tplink-mr3020.dts -> ar9331_tl_mr3020.dtsAntony Pavlov2020-01-143-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Linux MIPS uses <soc-name>_<board-name>.dts board dts-file naming scheme so use it in barebox too. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | MIPS: loongson: rename CPU_LOONGSON1 to CPU_GS232Du Huanpeng2020-01-064-7/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU in the loongson 1b SoC is called GS232. Here is some active chips and it's core: NAME CPU Core(s) The loongson 3 series/server & desktop 3A3000/3B3000 GS464E 64bit x4 3A2000/3B2000 GS464E 64bit x4 3B1500 GS464 64bit x8 3A1000 GS464 64bit x4 The loongson 2 series/low power 2K1000 GS264 64bit x2 2F GS464 64bit x1 2H GS464 64bit x1 The loongson 1 series/embeded 1C101 GS132R 32bit ? 1D GS132 32bit ? 1C GS232 32bit x1 1B GS232 32bit x1 1A GS232 32bit x1 see: [1] http://www.loongson.cn/product/ Signed-off-by: Du Huanpeng <duhuanpeng@loongson.cn> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/layerscape'Sascha Hauer2020-01-151-148/+463
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| * | ARM: Layerscape: setup icids for the IOMMUSascha Hauer2020-01-131-16/+265
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Isolation Context Identifiers (icid) have to be configured in the hardware and communicated to the Kernel via device tree fixups. This adds the missing bits and pieces to make the IOMMU work under Linux. As of Linux-5.5 the SMMU doesn't work out of the box. This series has been tested in conjunction with this Kernel series: https://lore.kernel.org/patchwork/cover/997994/ Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | include/soc/fsl: Make struct ccsr_qman v3 specificSascha Hauer2020-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct ccsr_qman is ifdeffed for different versions of this structure. CONFIG_SYS_FSL_QMAN_V3 is not defined which means we happen to use the wrong version on LS1046a. Hardcode it to the v3 version to make it work on LS1046a and rename it to ccsr_qman_v3 to make it obvious that it needs a change on non v3 versions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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