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* RISC-V: drop old timer handling codeAntony Pavlov2021-03-302-64/+1
| | | | | | | | | Use drivers/clocksource/timer-riscv.c driver introduced in '2ee369dcf7a5 ("clocksource: add driver for RISC-V and CLINT timers")' instead. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: erizo.dtsi: set timebase-frequency = <24000000>Antony Pavlov2021-03-301-0/+2
| | | | | | | | | | | This patch makes it possible to use drivers/clocksource/timer-riscv.c with erizo. Without timebase-frequency initialized we have this warning at startup: RISC-V system with no 'timebase-frequency' in DTS Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: boot: move stack top to very end of memoryAhmad Fatoum2021-03-291-1/+1
| | | | | | | | | | | Now that the generic DT entry point used for QEMU virt takes care to prevent the PBL common code from overwriting the FDT, we can remove the 2M wasteland after the stack top. This reduces fragmentation on low memory platforms like erizo. Reported-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: board-dt-2nd: ensure FDT doesn't overlap with early mem regionsAhmad Fatoum2021-03-293-6/+28
| | | | | | | | | | | | | | RISC-V PBL code currently reserves the last 2M of the memory for firmware and places the stack before that. This serves virt, as qemu places the FDT here, but negatively impacts normal targets with embedded device tree as it increases fragmentation. Add code to the generic DT entry point that cuts of a number of MiB from the end of RAM, so the PBL arrives at a stack top that doesn't overlap FDT. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: cpu: request stack memory regionAhmad Fatoum2021-03-291-0/+12
| | | | | | | | | | | Now that the stack base region is determined dynamically, mem_malloc_resource can no longer reserve the stack space. Do as ARM does and add a RISC-V specific initcall to reserve the main thread's stack space. Reported-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: Fix overwriting defaultenv with zii board specific envSascha Hauer2021-03-261-0/+2
| | | | | | | | | zii_imx7d_dev_init() lacks a protection against running on the wrong hardware. Add it so that the defaultenv no longer gets overwritten with a board specific variant. Fixes: 31300d79e8 ("ARM: zii-common: Add common environment directory") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: dts: protonic: drop all devictree copies and start to use mainlined ↵Oleksij Rempel2021-03-2320-4278/+133
| | | | | | | | | kernel versions This should make maintaining work easier. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add Qemu virt supportRouven Czerwinski2021-03-236-1/+271
| | | | | | | | | | | | | | | | The generic dt board added in a previous commit can be booted on RISC-V qemu -M virt. Add defconfigs for both 32- and 64-bit machines. We could in theory drop the mach directory altogether like it's done on arm64, but for now it's left in as it provides <mach/debug_ll.h>. It's expected that we can drop it in future in favor of generic earlycon support (which also wouldn't require manual adjustment of the shared entry point like with debug_ll). Signed-off-by: Rouven Czerwinski <r.czerwinksi@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clocksource: add driver for RISC-V and CLINT timersAhmad Fatoum2021-03-2310-1/+483
| | | | | | | | | | | | | CLINT is selected by Linux on nommu RISC-V machines, while the RISC-V timer with SBI is selected on MMU enabled ones. Both are also available on the Qemu Virt machine, but only SBI is available on TinyEmu. As we'll add Virt support in a follow-up commit, import both drivers now. Erizo could in theory make use of the RISC-V timer, but even a 2GHz timer base is too slow for it to be accurate. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add generic DT imageAhmad Fatoum2021-03-233-0/+46
| | | | | | | | | This barebox image implements the same header as Linux and receives the device tree in the same register. It can be booted from barebox or loaded by Qemu -kernel option. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add 64-bit supportRouven Czerwinski2021-03-236-18/+35
| | | | | | | | | As our assembly routines are now written to work correctly on 32-bit as well as 64-bit, nothing is holding us back from adding 64-bit support. Signed-off-by: Rouven Czerwinski <r.czerwinksi@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: support symbol names in barebox imageAhmad Fatoum2021-03-231-0/+1
| | | | | | | | Make debugging a bit more convenient by providing users the option to include symbol names. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: erizo: migrate to PBLAhmad Fatoum2021-03-2312-173/+80
| | | | | | | | | | We now have everything in place to migrate erizo to PBL. As currently, this is the only board, we can drop all non-PBL support in the same go. Cc: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: implement PBL and relocation supportAhmad Fatoum2021-03-2318-4/+682
| | | | | | | | | | | | | | | | | Given that we only support a single RISC-V board, this puts us in a good position to make this a multi-image-only architecture. This commit adds the necessary bits. It's highly inspired by the ARM PBL support. Notable difference is that for relocations to be generated, it was necessary to compile with -fpic. The relocation code assumes the relocation entries to preprocessed. This is done at build-time by means of the prelink-riscv script imported from U-Boot. Actual migration to -fpic and prelinking is done along with porting erizo in a follow-up commit. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: implement PBL image headerAhmad Fatoum2021-03-232-0/+101
| | | | | | | | | | | We'll adopt the RISC-V Linux kernel image header structure for the barebox images as well. The __barebox_riscv_header() macro implementing it can customize some fields to allow differentiating between barebox and kernel images. It will be used in follow-up commits to implement the entry points of both the erizo image and the generic DT image. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: import Linux' optimized string functionsAhmad Fatoum2021-03-236-1/+313
| | | | | | | | For non-NMON enabled board the RISC-V specific settings menu will be empty. Improve UI/UX by adding something there. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: erizo: move to arch/riscv/boards/erizoAhmad Fatoum2021-03-237-4/+8
| | | | | | | | In preparation for migrating to PBL for RISC-V platforms, move the only existing board support to a new arch/riscv/boards/ directory. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add cacheless HAS_DMA supportAhmad Fatoum2021-03-232-0/+45
| | | | | | | | Define some stubs, so we can get virtio MMIO working on RISC-V in QEMU. As we don't yet have MMU support, this is sufficient. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: drop duplicate or unneeded cflagsAhmad Fatoum2021-03-231-3/+1
| | | | | | | | -pipe -Wall is specified in top-level Makefile. Disabling warnings is unneeded on the arch and is a left-over from MIPS port probably. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: debug_ll: ns16550: align C access size with assembly'sAhmad Fatoum2021-03-231-6/+10
| | | | | | | | The assembly putc routines do accesses the same size of the register stride. Do likewise for the C implementation. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: <asm/unaligned.h>: don't do unaligned accessesAhmad Fatoum2021-03-231-12/+4
| | | | | | | | While HW can emulate unaligned accesses at a performance penalty, it's probably best to just not generate them. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: omit unused label in assemblyAhmad Fatoum2021-03-231-1/+1
| | | | | | | | The 1: is a left-over from before 5f04e5e03e94 ("ARM: aarch64: Fix get_runtime_offset after relocation"). It's unused now, so drop it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: make ARM_USE_COMPRESSED_DTB available for other archesAhmad Fatoum2021-03-233-26/+6
| | | | | | | | | | Other PBL-enabled architecture can benefit from compressed dtbs as well. Move symbol and code to a comm place to be able to use it from RISC-V in a later commit. In order not to break out of tree boards at runtime, the old symbol name is maintained for ARM. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: make BOARD_ARM_GENERIC_DT available for other archesAhmad Fatoum2021-03-231-1/+1
| | | | | | | | | | | Other architectures would benefit from the generic DT image too. Add a new arch-agnostic symbol that arches besides ARM can select. The new symbol itself should not have a prompt as the help text for each architecture likely differs (e.g. device tree handoff register). Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/virtio'Sascha Hauer2021-03-233-62/+1
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| * dma: move dma_map/unmap_single from ARM to common codeAhmad Fatoum2021-03-043-62/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There's nothing ARM specific about these functions. Move them to a common location, so other arches can use them as well. This also fixes a bug on ARM MMU=n configurations: Previously these two functions these functions only respected dma-ranges translation when compiled with MMU support. DMA address translation is applicable regardless of CPU use of MMU though. Now, dma-ranges should be respected unconditionally. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2021-03-2316-165/+184
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| * | dts: zcu104: remove unnecessary ZynqMP clock dtsiMichael Tretter2021-03-222-156/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock definitions are now available from the Linux device tree as dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi and the clock-controller is defined in dts/src/arm64/xilinx/zynqmp.dtsi. Defining the clocks in a Barebox-specific file is not necessary anymore. Remove zynqmp-clk.dtsi and the include from the board device tree. The files are already correctly included by the imported board device trees (dts/src/arm64/xilinx/zynqmp-zcu104-revA.dts). Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: stm32mp: defconfig: enable DWC2 USB OTG controllerAhmad Fatoum2021-03-171-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | We have had all parts in place to use the OTG port on the STM32MP1 boards for a while now. Enable it in the defconfig. USB EHCI has a driver, but still needs some glue, however. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: stm32mp: add support for STM32MP157-EV1 boardAhmad Fatoum2021-03-178-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32MP157A-EV1 and STM32MP157C-EV1 Evaluation boards are the full-feature demonstration and development platforms for STMicroelectronics Arm®-based dual Cortex®-A7 32 bits and Cortex®-M4 32 bits MPUs in the STM32MP1 Series. Add support for running barebox as SSBL on either of them. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: add Xterm escape sequence backed LED driverAhmad Fatoum2021-03-163-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is value in testing LED trigger conditions in sandbox, especially with the coming bthread work that should replace pollers, like the one used by the heartbeat trigger. To make this testable on sandbox as well, add a simple LED driver. It supports 5 brightness levels, which are reflected as dots in the terminal title. This requires a Xterm compatible terminal, but the LED is inactive by default, so other terminals aren't affected if they lack support. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8M: bbu: fix variable name to used semanticAlexander Kurz2021-03-042-6/+6
| | | | | | | | | | | | | | | | | | | | | Both flags handle BBU behavior and should be bbu_flags. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | MIPS: qemu-malta: make barebox Malta images detectableAhmad Fatoum2021-03-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | is_barebox_mips_head checks whether 0x10-0x16 is "barebox". Have the Malta images provide this signature like other MIPS boards already do. This makes bootm work. Cc: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/dts'Sascha Hauer2021-03-231-0/+5
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| * | | phy: stm32: sync with upstreamAhmad Fatoum2021-03-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This imports following Linux patches by Amelie Delaunay <amelie.delaunay@foss.st.com>: phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation phy: stm32: replace regulator_bulk* by multiple regulator_* phy: stm32: ensure pll is disabled before phys creation phy: stm32: ensure phy are no more active when removing the driver phy: stm32: rework PLL Lock detection ARM: dts: stm32: add usbphyc vdda1v1 and vdda1v8 supplies on stm32mp151 This makes barebox compatible to the new device tree binding, reduces our differences to the upstream driver and removes the power_on, power_off callbacks which are now integrated into init/exit. The device tree override is necessary, because unlike with Linux, barebox regulator core doesn't descend into child nodes to enable their regulators, but that's a fix for another day. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/bthreads'Sascha Hauer2021-03-2350-14/+1155
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| * | | | bthread: disable ASan accounting for fibers on 32-bit sandboxAhmad Fatoum2021-03-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the sandbox architecture, we use __sanitizer_start_switch_fiber and __sanitizer_finish_switch_fiber to tell ASan when we switch stacks. If we don't, ASan complains that: ==2472828==WARNING: ASan is ignoring requested __asan_handle_no_return: stack top: 0xff9fc000; bottom 0xf3be8000; size: 0x0be14000 (199311360) False positive error reports may follow For details see https://github.com/google/sanitizers/issues/189 This works on 64-bit sandbox, but 32-bit sandbox currently crashes on bthread -v: ==2469590==AddressSanitizer CHECK failed: ../../../../../src/libsanitizer/asan/asan_poisoning.cpp:37 "((AddrIsAlignedByGranularity(addr + size))) != (0)" (0x0, 0x0) #0 0xf7a4aa46 in AsanCheckFailed ../../../../../src/libsanitizer/asan/asan_rtl.cpp:73 #1 0xf7a6b5cf in __sanitizer::CheckFailed(char const*, int, char const*, unsigned long long, unsigned long long) ../../../../../src/libsanitizer/sanitizer_common/sanitizer_termination.cpp:78 #2 0xf7a4489f in __asan::PoisonShadow(unsigned long, unsigned long, unsigned char) ../../../../../src/libsanitizer/asan/asan_poisoning.cpp:37 #3 0xf7a4c81b in __asan_handle_no_return ../../../../../src/libsanitizer/asan/asan_rtl.cpp:595 #4 0x566a1ce7 in bthread_schedule /home/a3f/dl/barebox-stm32mp/common/bthread.c:178 #5 0x566a1d54 in bthread_reschedule /home/a3f/dl/barebox-stm32mp/common/bthread.c:165 #6 0x566a1d80 in bthread_trampoline /home/a3f/dl/barebox-stm32mp/common/bthread.c:56 #7 0x567f5bfb in coroutine_bootstrap (/home/a3f/dl/build/barebox/sandbox/barebox+0x1bdbfb) #8 0x567f5c4b in coroutine_trampoline (/home/a3f/dl/build/barebox/sandbox/barebox+0x1bdc4b) #9 0xf7f7056f (linux-gate.so.1+0x56f) #10 0xf7f70558 (linux-gate.so.1+0x558) #11 0x56892fff (/home/a3f/dl/build/barebox/sandbox/barebox+0x25afff) Just disable the special ASan accounting there until this is figured out. bthreads still function there, but ASan may yield false positives according to the message. This does not affect non-sandbox platforms. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | openrisc: Implement setjmp/longjmp/initjmpStafford Horne2021-03-174-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested on or1ksim and this seems to work. This is mostly the same as the glibc port implementation, but adjusted as per requirements per barebox. Signed-off-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | openrisc: Add linkage.hStafford Horne2021-03-171-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copied from glibc minus bits we don't need. Signed-off-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | openrisc: Add gitignore for dtb filesStafford Horne2021-03-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | openrisc: Use movhi to zero registersStafford Horne2021-03-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed when running on FPGA as registers are not guaranteed to be initialized to 0. Using movhi allows to explicitly set 0. Signed-off-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | kvx: lib: dtb: Remove unused variableJules Maselbas2021-03-171-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Local variables `root` and `ret` are not used anymore, remove them. Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | kvx: Request enough privilege to boot LinuxJules Maselbas2021-03-172-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At startup barebox must take all the privileges that will be requested by Linux. Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | kvx: Implement dma handling primitivesYann Sionneau2021-03-175-1/+131
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | kvx: Implement dcache invalidation primitiveYann Sionneau2021-03-174-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | kvx: Implement setjmp/longjmp/initjmpJules Maselbas2021-03-174-1/+102
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | x86: implement setjmp/longjmp/initjmpAhmad Fatoum2021-03-175-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For use with bthreads, implement CONFIG_HAS_ARCH_SJLJ. Code is taken from U-Boot, itself based on the Linux ARCH=um. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | powerpc: Implement initjmp/setjmp/longjmpSascha Hauer2021-03-175-1/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementation has been taken from newlib as this is much simpler than the glibc version. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | mips: Implement setjmp/longjmp/initjmp for 32BITSascha Hauer2021-03-174-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header has been taken from glibc, the implementation itself is based on the newlib implementation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | mips: Add linkage.hSascha Hauer2021-03-171-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Taken from Linux Kernel with unnecessary bits removed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-01 18:44:44 +0000