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authorSascha Hauer <s.hauer@pengutronix.de>2022-06-08 09:15:32 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2022-06-08 10:41:39 +0200
commite54923b76e345080b73f3ae7f508657e5c63a9eb (patch)
tree8ea04209dd330c4a1257efade74fdda32bc7bb62 /dts/src/arm
parentd4fd877cc4c6439a806f9c5f1b8c561605ee1167 (diff)
downloadbarebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.gz
barebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.xz
dts: update to v5.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm')
-rw-r--r--dts/src/arm/am335x-baltos.dtsi2
-rw-r--r--dts/src/arm/am335x-bone-common.dtsi4
-rw-r--r--dts/src/arm/am335x-evm.dts4
-rw-r--r--dts/src/arm/am335x-evmsk.dts4
-rw-r--r--dts/src/arm/am335x-guardian.dts376
-rw-r--r--dts/src/arm/am335x-moxa-uc-2100-common.dtsi2
-rw-r--r--dts/src/arm/am335x-moxa-uc-8100-common.dtsi2
-rw-r--r--dts/src/arm/am335x-myirtech-myc.dtsi12
-rw-r--r--dts/src/arm/am335x-myirtech-myd.dts20
-rw-r--r--dts/src/arm/am335x-phycore-som.dtsi2
-rw-r--r--dts/src/arm/am335x-sl50.dts2
-rw-r--r--dts/src/arm/am33xx-clocks.dtsi373
-rw-r--r--dts/src/arm/am33xx.dtsi3
-rw-r--r--dts/src/arm/am35xx-clocks.dtsi52
-rw-r--r--dts/src/arm/am3874-iceboard.dts2
-rw-r--r--dts/src/arm/am437x-cm-t43.dts2
-rw-r--r--dts/src/arm/am437x-gp-evm.dts5
-rw-r--r--dts/src/arm/am437x-idk-evm.dts2
-rw-r--r--dts/src/arm/am437x-sk-evm.dts6
-rw-r--r--dts/src/arm/am43x-epos-evm.dts6
-rw-r--r--dts/src/arm/am43xx-clocks.dtsi339
-rw-r--r--dts/src/arm/am574x-idk.dts2
-rw-r--r--dts/src/arm/am57xx-cl-som-am57x.dts2
-rw-r--r--dts/src/arm/am57xx-idk-common.dtsi2
-rw-r--r--dts/src/arm/armada-370-db.dts2
-rw-r--r--dts/src/arm/armada-370-seagate-personal-cloud.dtsi2
-rw-r--r--dts/src/arm/armada-370-synology-ds213j.dts2
-rw-r--r--dts/src/arm/armada-375-db.dts2
-rw-r--r--dts/src/arm/armada-381-netgear-gs110emx.dts2
-rw-r--r--dts/src/arm/armada-385-atl-x530.dts2
-rw-r--r--dts/src/arm/armada-385-clearfog-gtr.dtsi2
-rw-r--r--dts/src/arm/armada-385-db-88f6820-amc.dts2
-rw-r--r--dts/src/arm/armada-385-db-ap.dts2
-rw-r--r--dts/src/arm/armada-385-synology-ds116.dts2
-rw-r--r--dts/src/arm/armada-385-turris-omnia.dts8
-rw-r--r--dts/src/arm/armada-388-db.dts2
-rw-r--r--dts/src/arm/armada-388-gp.dts2
-rw-r--r--dts/src/arm/armada-388-rd.dts2
-rw-r--r--dts/src/arm/armada-38x-solidrun-microsom.dtsi2
-rw-r--r--dts/src/arm/armada-390-db.dts2
-rw-r--r--dts/src/arm/armada-398-db.dts2
-rw-r--r--dts/src/arm/armada-xp-axpwifiap.dts2
-rw-r--r--dts/src/arm/armada-xp-crs305-1g-4s-bit.dts2
-rw-r--r--dts/src/arm/armada-xp-crs305-1g-4s.dtsi2
-rw-r--r--dts/src/arm/armada-xp-crs326-24g-2s-bit.dts2
-rw-r--r--dts/src/arm/armada-xp-crs326-24g-2s.dtsi2
-rw-r--r--dts/src/arm/armada-xp-crs328-4c-20s-4s-bit.dts2
-rw-r--r--dts/src/arm/armada-xp-crs328-4c-20s-4s.dtsi2
-rw-r--r--dts/src/arm/armada-xp-db-dxbc2.dts2
-rw-r--r--dts/src/arm/armada-xp-db-xc3-24g4xg.dts2
-rw-r--r--dts/src/arm/armada-xp-db.dts2
-rw-r--r--dts/src/arm/armada-xp-gp.dts2
-rw-r--r--dts/src/arm/armada-xp-linksys-mamba.dts2
-rw-r--r--dts/src/arm/armada-xp-synology-ds414.dts2
-rw-r--r--dts/src/arm/aspeed-ast2600-evb.dts39
-rw-r--r--dts/src/arm/aspeed-bmc-facebook-bletchley.dts182
-rw-r--r--dts/src/arm/aspeed-bmc-ibm-everest.dts2
-rw-r--r--dts/src/arm/aspeed-bmc-ibm-rainier.dts2
-rw-r--r--dts/src/arm/aspeed-bmc-nuvia-dc-scm.dts190
-rw-r--r--dts/src/arm/aspeed-g4.dtsi16
-rw-r--r--dts/src/arm/aspeed-g5.dtsi16
-rw-r--r--dts/src/arm/aspeed-g6.dtsi42
-rw-r--r--dts/src/arm/at91-sama7g5ek.dts21
-rw-r--r--dts/src/arm/at91sam9261ek.dts4
-rw-r--r--dts/src/arm/at91sam9263ek.dts4
-rw-r--r--dts/src/arm/at91sam9rlek.dts4
-rw-r--r--dts/src/arm/bcm-cygnus.dtsi12
-rw-r--r--dts/src/arm/bcm2835-rpi-a-plus.dts21
-rw-r--r--dts/src/arm/bcm2835-rpi-a.dts35
-rw-r--r--dts/src/arm/bcm2835-rpi-b-plus.dts19
-rw-r--r--dts/src/arm/bcm2835-rpi-b-rev2.dts35
-rw-r--r--dts/src/arm/bcm2835-rpi-b.dts48
-rw-r--r--dts/src/arm/bcm2835-rpi-cm1-io1.dts1
-rw-r--r--dts/src/arm/bcm2835-rpi-zero-w.dts25
-rw-r--r--dts/src/arm/bcm2835-rpi-zero.dts29
-rw-r--r--dts/src/arm/bcm2836-rpi-2-b.dts3
-rw-r--r--dts/src/arm/bcm2837-rpi-3-a-plus.dts1
-rw-r--r--dts/src/arm/bcm2837-rpi-3-b-plus.dts5
-rw-r--r--dts/src/arm/bcm2837-rpi-3-b.dts3
-rw-r--r--dts/src/arm/bcm2837-rpi-cm3-io3.dts5
-rw-r--r--dts/src/arm/bcm2837-rpi-cm3.dtsi12
-rw-r--r--dts/src/arm/bcm283x-rpi-smsc9512.dtsi2
-rw-r--r--dts/src/arm/bcm283x-rpi-smsc9514.dtsi2
-rw-r--r--dts/src/arm/bcm4708-buffalo-wzr-1166dhp-common.dtsi192
-rw-r--r--dts/src/arm/bcm4708-buffalo-wzr-1166dhp.dts26
-rw-r--r--dts/src/arm/bcm4708-buffalo-wzr-1166dhp2.dts26
-rw-r--r--dts/src/arm/bcm47094-asus-rt-ac88u.dts19
-rw-r--r--dts/src/arm/bcm47622.dtsi126
-rw-r--r--dts/src/arm/bcm53016-meraki-mr32.dts2
-rw-r--r--dts/src/arm/bcm5301x.dtsi2
-rw-r--r--dts/src/arm/bcm53340-ubnt-unifi-switch8.dts2
-rw-r--r--dts/src/arm/bcm947622.dts30
-rw-r--r--dts/src/arm/bcm953012er.dts2
-rw-r--r--dts/src/arm/bcm953012hr.dts2
-rw-r--r--dts/src/arm/bcm953012k.dts2
-rw-r--r--dts/src/arm/bcm958522er.dts2
-rw-r--r--dts/src/arm/bcm958525er.dts2
-rw-r--r--dts/src/arm/bcm958525xmc.dts2
-rw-r--r--dts/src/arm/bcm958622hr.dts2
-rw-r--r--dts/src/arm/bcm958623hr.dts2
-rw-r--r--dts/src/arm/bcm958625hr.dts2
-rw-r--r--dts/src/arm/bcm958625k.dts2
-rw-r--r--dts/src/arm/bcm988312hr.dts2
-rw-r--r--dts/src/arm/da850.dtsi2
-rw-r--r--dts/src/arm/dm814x.dtsi3
-rw-r--r--dts/src/arm/dm816x.dtsi3
-rw-r--r--dts/src/arm/dove-cubox.dts2
-rw-r--r--dts/src/arm/dove-d2plug.dts2
-rw-r--r--dts/src/arm/dove-d3plug.dts2
-rw-r--r--dts/src/arm/dove-dove-db.dts2
-rw-r--r--dts/src/arm/dra7-evm-common.dtsi2
-rw-r--r--dts/src/arm/dra72-evm-common.dtsi2
-rw-r--r--dts/src/arm/dra76-evm.dts2
-rw-r--r--dts/src/arm/dra7xx-clocks.dtsi693
-rw-r--r--dts/src/arm/exynos3250.dtsi7
-rw-r--r--dts/src/arm/exynos4.dtsi10
-rw-r--r--dts/src/arm/exynos4210-universal_c210.dts2
-rw-r--r--dts/src/arm/exynos4412-odroidu3.dts4
-rw-r--r--dts/src/arm/exynos4412-odroidx.dts8
-rw-r--r--dts/src/arm/exynos5250-smdk5250.dts4
-rw-r--r--dts/src/arm/exynos5250.dtsi16
-rw-r--r--dts/src/arm/exynos5260.dtsi3
-rw-r--r--dts/src/arm/exynos5410-odroidxu.dts4
-rw-r--r--dts/src/arm/exynos5410.dtsi4
-rw-r--r--dts/src/arm/exynos5420.dtsi10
-rw-r--r--dts/src/arm/exynos5422-odroid-core.dtsi7
-rw-r--r--dts/src/arm/exynos5422-odroidxu3-lite.dts6
-rw-r--r--dts/src/arm/exynos5422-odroidxu3.dts6
-rw-r--r--dts/src/arm/exynos54xx.dtsi3
-rw-r--r--dts/src/arm/hpe-bmc-dl360gen10.dts26
-rw-r--r--dts/src/arm/hpe-gxp.dtsi127
-rw-r--r--dts/src/arm/imx27.dtsi2
-rw-r--r--dts/src/arm/imx28-evk.dts2
-rw-r--r--dts/src/arm/imx28-m28evk.dts2
-rw-r--r--dts/src/arm/imx28-sps1.dts2
-rw-r--r--dts/src/arm/imx51-digi-connectcore-jsk.dts8
-rw-r--r--dts/src/arm/imx51-digi-connectcore-som.dtsi25
-rw-r--r--dts/src/arm/imx51.dtsi6
-rw-r--r--dts/src/arm/imx6dl-colibri-aster.dts113
-rw-r--r--dts/src/arm/imx6dl-colibri-eval-v3.dts110
-rw-r--r--dts/src/arm/imx6dl-colibri-iris-v2.dts46
-rw-r--r--dts/src/arm/imx6dl-colibri-iris.dts152
-rw-r--r--dts/src/arm/imx6dl-colibri-v1_1-eval-v3.dts31
-rw-r--r--dts/src/arm/imx6dl-eckelmann-ci4x10.dts6
-rw-r--r--dts/src/arm/imx6dl-plybas.dts2
-rw-r--r--dts/src/arm/imx6dl-rex-basic.dts2
-rw-r--r--dts/src/arm/imx6dl-victgo.dts657
-rw-r--r--dts/src/arm/imx6dl-vicut1.dts1
-rw-r--r--dts/src/arm/imx6q-ba16.dtsi2
-rw-r--r--dts/src/arm/imx6q-bosch-acc.dts779
-rw-r--r--dts/src/arm/imx6q-bx50v3.dtsi2
-rw-r--r--dts/src/arm/imx6q-cm-fx6.dts2
-rw-r--r--dts/src/arm/imx6q-dmo-edmqmx6.dts2
-rw-r--r--dts/src/arm/imx6q-dms-ba16.dts2
-rw-r--r--dts/src/arm/imx6q-gw5400-a.dts2
-rw-r--r--dts/src/arm/imx6q-marsboard.dts2
-rw-r--r--dts/src/arm/imx6q-rex-pro.dts2
-rw-r--r--dts/src/arm/imx6q-vicut1.dts5
-rw-r--r--dts/src/arm/imx6qdl-aristainetos.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-aristainetos2.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-colibri-v1_1-uhs.dtsi44
-rw-r--r--dts/src/arm/imx6qdl-colibri.dtsi771
-rw-r--r--dts/src/arm/imx6qdl-dfi-fs700-m60.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-kontron-samx6i.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-nit6xlite.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-nitrogen6_max.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-nitrogen6_som2.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-nitrogen6x.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-phytec-pfla02.dtsi4
-rw-r--r--dts/src/arm/imx6qdl-sabreauto.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-sabrelite.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-sabresd.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-sr-som.dtsi10
-rw-r--r--dts/src/arm/imx6qdl-tx6.dtsi5
-rw-r--r--dts/src/arm/imx6qdl-udoo.dtsi2
-rw-r--r--dts/src/arm/imx6qdl-vicut1-12inch.dtsi128
-rw-r--r--dts/src/arm/imx6qdl-vicut1.dtsi261
-rw-r--r--dts/src/arm/imx6qp-vicutp.dts1
-rw-r--r--dts/src/arm/imx6sl-evk.dts2
-rw-r--r--dts/src/arm/imx6sl.dtsi2
-rw-r--r--dts/src/arm/imx6sx-nitrogen6sx.dts2
-rw-r--r--dts/src/arm/imx6sx-sdb-reva.dts4
-rw-r--r--dts/src/arm/imx6sx-sdb.dts4
-rw-r--r--dts/src/arm/imx6ul-14x14-evk.dtsi2
-rw-r--r--dts/src/arm/imx6ul-kontron-n6310-som.dtsi2
-rw-r--r--dts/src/arm/imx6ul-kontron-n6311-som.dtsi2
-rw-r--r--dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi2
-rw-r--r--dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi2
-rw-r--r--dts/src/arm/imx6ul-phytec-segin-peb-av-02.dtsi3
-rw-r--r--dts/src/arm/imx6ul-tqma6ul-common.dtsi211
-rw-r--r--dts/src/arm/imx6ul-tqma6ul1-mba6ulx.dts55
-rw-r--r--dts/src/arm/imx6ul-tqma6ul1.dtsi37
-rw-r--r--dts/src/arm/imx6ul-tqma6ul2-mba6ulx.dts15
-rw-r--r--dts/src/arm/imx6ul-tqma6ul2.dtsi71
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-rw-r--r--dts/src/arm/imx6ul-tqma6ulx-common.dtsi43
-rw-r--r--dts/src/arm/imx6ul-tqma6ulxl-common.dtsi48
-rw-r--r--dts/src/arm/imx6ull-colibri-aster.dts20
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-rw-r--r--dts/src/arm/imx6ull-colibri-emmc-aster.dts17
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-rw-r--r--dts/src/arm/imx6ull-colibri-emmc-iris.dts17
-rw-r--r--dts/src/arm/imx6ull-colibri-emmc-nonwifi.dtsi8
-rw-r--r--dts/src/arm/imx6ull-colibri-eval-v3.dts6
-rw-r--r--dts/src/arm/imx6ull-colibri-eval-v3.dtsi63
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-rw-r--r--dts/src/arm/imx6ull-colibri-nonwifi.dtsi145
-rw-r--r--dts/src/arm/imx6ull-colibri-wifi-aster.dts20
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-rw-r--r--dts/src/arm/ls1021a-iot.dts227
-rw-r--r--dts/src/arm/ls1021a.dtsi6
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-rw-r--r--dts/src/arm/nuvoton-npcm750-evb.dts8
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-rw-r--r--dts/src/arm/omap3-beagle-xm.dts2
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-rw-r--r--dts/src/arm/omap34xx-omap36xx-clocks.dtsi275
-rw-r--r--dts/src/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi79
-rw-r--r--dts/src/arm/omap36xx-clocks.dtsi17
-rw-r--r--dts/src/arm/omap36xx-omap3430es2plus-clocks.dtsi136
-rw-r--r--dts/src/arm/omap3xxx-clocks.dtsi2044
-rw-r--r--dts/src/arm/omap4-panda-common.dtsi2
-rw-r--r--dts/src/arm/omap443x-clocks.dtsi1
-rw-r--r--dts/src/arm/omap446x-clocks.dtsi2
-rw-r--r--dts/src/arm/omap44xx-clocks.dtsi173
-rw-r--r--dts/src/arm/omap5-igep0050.dts2
-rw-r--r--dts/src/arm/omap5-uevm.dts2
-rw-r--r--dts/src/arm/omap54xx-clocks.dtsi160
-rw-r--r--dts/src/arm/ox820.dtsi2
-rw-r--r--dts/src/arm/pxa25x.dtsi5
-rw-r--r--dts/src/arm/pxa27x.dtsi5
-rw-r--r--dts/src/arm/pxa3xx.dtsi5
-rw-r--r--dts/src/arm/qcom-apq8026-asus-sparrow.dts294
-rw-r--r--dts/src/arm/qcom-apq8064-sony-xperia-lagan-yuga.dts (renamed from dts/src/arm/qcom-apq8064-sony-xperia-yuga.dts)0
-rw-r--r--dts/src/arm/qcom-apq8064.dtsi16
-rw-r--r--dts/src/arm/qcom-apq8074-dragonboard.dts582
-rw-r--r--dts/src/arm/qcom-apq8084.dtsi2
-rw-r--r--dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi4
-rw-r--r--dts/src/arm/qcom-ipq4019-ap.dk04.1-c1.dts2
-rw-r--r--dts/src/arm/qcom-ipq4019-ap.dk04.1.dtsi4
-rw-r--r--dts/src/arm/qcom-ipq4019-ap.dk07.1-c1.dts2
-rw-r--r--dts/src/arm/qcom-ipq4019-ap.dk07.1.dtsi4
-rw-r--r--dts/src/arm/qcom-ipq4019.dtsi44
-rw-r--r--dts/src/arm/qcom-ipq8064-v1.0.dtsi2
-rw-r--r--dts/src/arm/qcom-ipq8064.dtsi12
-rw-r--r--dts/src/arm/qcom-mdm9615.dtsi4
-rw-r--r--dts/src/arm/qcom-msm8226.dtsi9
-rw-r--r--dts/src/arm/qcom-msm8660.dtsi1
-rw-r--r--dts/src/arm/qcom-msm8974-fairphone-fp2.dts409
-rw-r--r--dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts1052
-rw-r--r--dts/src/arm/qcom-msm8974-samsung-klte.dts908
-rw-r--r--dts/src/arm/qcom-msm8974-sony-xperia-amami.dts435
-rw-r--r--dts/src/arm/qcom-msm8974-sony-xperia-castor.dts723
-rw-r--r--dts/src/arm/qcom-msm8974-sony-xperia-honami.dts484
-rw-r--r--dts/src/arm/qcom-msm8974-sony-xperia-rhine-amami.dts13
-rw-r--r--dts/src/arm/qcom-msm8974-sony-xperia-rhine-honami.dts7
-rw-r--r--dts/src/arm/qcom-msm8974-sony-xperia-rhine.dtsi457
-rw-r--r--dts/src/arm/qcom-msm8974.dtsi1730
-rw-r--r--dts/src/arm/qcom-msm8974pro-fairphone-fp2.dts432
-rw-r--r--dts/src/arm/qcom-msm8974pro-samsung-klte.dts813
-rw-r--r--dts/src/arm/qcom-msm8974pro-sony-xperia-shinano-castor.dts608
-rw-r--r--dts/src/arm/qcom-msm8974pro.dtsi32
-rw-r--r--dts/src/arm/qcom-pm8226.dtsi41
-rw-r--r--dts/src/arm/qcom-pm8941.dtsi2
-rw-r--r--dts/src/arm/qcom-pmx65.dtsi32
-rw-r--r--dts/src/arm/qcom-sdx55.dtsi20
-rw-r--r--dts/src/arm/qcom-sdx65-mtp.dts221
-rw-r--r--dts/src/arm/qcom-sdx65.dtsi193
-rw-r--r--dts/src/arm/r8a7743.dtsi1
-rw-r--r--dts/src/arm/r8a7744.dtsi1
-rw-r--r--dts/src/arm/r8a7745.dtsi1
-rw-r--r--dts/src/arm/r8a77470.dtsi1
-rw-r--r--dts/src/arm/r8a7790.dtsi1
-rw-r--r--dts/src/arm/r8a7791.dtsi1
-rw-r--r--dts/src/arm/r8a7792.dtsi1
-rw-r--r--dts/src/arm/r8a7793.dtsi1
-rw-r--r--dts/src/arm/r8a7794.dtsi1
-rw-r--r--dts/src/arm/r9a06g032.dtsi113
-rw-r--r--dts/src/arm/rk3036.dtsi6
-rw-r--r--dts/src/arm/rk3066a.dtsi3
-rw-r--r--dts/src/arm/rk3188-bqedison2qc.dts3
-rw-r--r--dts/src/arm/rk3188.dtsi3
-rw-r--r--dts/src/arm/rk322x.dtsi4
-rw-r--r--dts/src/arm/rk3288.dtsi2
-rw-r--r--dts/src/arm/rv1108.dtsi31
-rw-r--r--dts/src/arm/s5pv210-aquila.dts3
-rw-r--r--dts/src/arm/s5pv210-aries.dtsi11
-rw-r--r--dts/src/arm/s5pv210-goni.dts6
-rw-r--r--dts/src/arm/s5pv210.dtsi46
-rw-r--r--dts/src/arm/sam9x60.dtsi2
-rw-r--r--dts/src/arm/sama7g5.dtsi27
-rw-r--r--dts/src/arm/socfpga.dtsi4
-rw-r--r--dts/src/arm/socfpga_arria10.dtsi4
-rw-r--r--dts/src/arm/socfpga_arria10_socdk_qspi.dts2
-rw-r--r--dts/src/arm/socfpga_cyclone5_socdk.dts2
-rw-r--r--dts/src/arm/socfpga_cyclone5_sodia.dts2
-rw-r--r--dts/src/arm/socfpga_cyclone5_vining_fpga.dts4
-rw-r--r--dts/src/arm/ste-dbx5x0.dtsi12
-rw-r--r--dts/src/arm/ste-ux500-samsung-codina-tmo.dts785
-rw-r--r--dts/src/arm/ste-ux500-samsung-codina.dts80
-rw-r--r--dts/src/arm/ste-ux500-samsung-gavini.dts4
-rw-r--r--dts/src/arm/ste-ux500-samsung-golden.dts4
-rw-r--r--dts/src/arm/ste-ux500-samsung-janice.dts44
-rw-r--r--dts/src/arm/ste-ux500-samsung-kyle.dts4
-rw-r--r--dts/src/arm/ste-ux500-samsung-skomer.dts35
-rw-r--r--dts/src/arm/stm32f4-pinctrl.dtsi2
-rw-r--r--dts/src/arm/stm32f7-pinctrl.dtsi2
-rw-r--r--dts/src/arm/stm32h743.dtsi2
-rw-r--r--dts/src/arm/stm32mp131.dtsi19
-rw-r--r--dts/src/arm/stm32mp135f-dk.dts29
-rw-r--r--dts/src/arm/stm32mp15-pinctrl.dtsi64
-rw-r--r--dts/src/arm/stm32mp151.dtsi45
-rw-r--r--dts/src/arm/stm32mp151a-prtt1a.dts52
-rw-r--r--dts/src/arm/stm32mp151a-prtt1c.dts304
-rw-r--r--dts/src/arm/stm32mp151a-prtt1l.dtsi229
-rw-r--r--dts/src/arm/stm32mp151a-prtt1s.dts63
-rw-r--r--dts/src/arm/stm32mp157a-dk1-scmi.dts86
-rw-r--r--dts/src/arm/stm32mp157c-dk2-scmi.dts95
-rw-r--r--dts/src/arm/stm32mp157c-ed1-scmi.dts91
-rw-r--r--dts/src/arm/stm32mp157c-ev1-scmi.dts100
-rw-r--r--dts/src/arm/stm32mp15xx-dhcom-som.dtsi22
-rw-r--r--dts/src/arm/stm32mp15xx-dhcor-avenger96.dtsi1
-rw-r--r--dts/src/arm/sun8i-h3-nanopi.dtsi1
-rw-r--r--dts/src/arm/suniv-f1c100s-licheepi-nano.dts31
-rw-r--r--dts/src/arm/suniv-f1c100s.dtsi104
-rw-r--r--dts/src/arm/zynq-7000.dtsi2
369 files changed, 18440 insertions, 8496 deletions
diff --git a/dts/src/arm/am335x-baltos.dtsi b/dts/src/arm/am335x-baltos.dtsi
index 3667026302..d3eafee79a 100644
--- a/dts/src/arm/am335x-baltos.dtsi
+++ b/dts/src/arm/am335x-baltos.dtsi
@@ -285,7 +285,7 @@
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
- regulator-max-microvolt = <1312500>;
+ regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};
diff --git a/dts/src/arm/am335x-bone-common.dtsi b/dts/src/arm/am335x-bone-common.dtsi
index 56ae5095a5..02e04a12a2 100644
--- a/dts/src/arm/am335x-bone-common.dtsi
+++ b/dts/src/arm/am335x-bone-common.dtsi
@@ -405,3 +405,7 @@
&pruss_tm {
status = "okay";
};
+
+&wkup_m3_ipc {
+ firmware-name = "am335x-bone-scale-data.bin";
+};
diff --git a/dts/src/arm/am335x-evm.dts b/dts/src/arm/am335x-evm.dts
index 659e99eabe..b9745a2f0e 100644
--- a/dts/src/arm/am335x-evm.dts
+++ b/dts/src/arm/am335x-evm.dts
@@ -782,3 +782,7 @@
&pruss_tm {
status = "okay";
};
+
+&wkup_m3_ipc {
+ firmware-name = "am335x-evm-scale-data.bin";
+};
diff --git a/dts/src/arm/am335x-evmsk.dts b/dts/src/arm/am335x-evmsk.dts
index a2db65538e..9c458e5a95 100644
--- a/dts/src/arm/am335x-evmsk.dts
+++ b/dts/src/arm/am335x-evmsk.dts
@@ -719,3 +719,7 @@
&pruss_tm {
status = "okay";
};
+
+&wkup_m3_ipc {
+ firmware-name = "am335x-evm-scale-data.bin";
+};
diff --git a/dts/src/arm/am335x-guardian.dts b/dts/src/arm/am335x-guardian.dts
index 1918766c1f..1a7e187b19 100644
--- a/dts/src/arm/am335x-guardian.dts
+++ b/dts/src/arm/am335x-guardian.dts
@@ -29,39 +29,44 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
- gpio_keys {
+ guardian_buttons: gpio-keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&guardian_button_pins>;
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pins>;
- button21 {
+ select-button {
+ label = "guardian-select-button";
+ linux,code = <KEY_5>;
+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ power-button {
label = "guardian-power-button";
linux,code = <KEY_POWER>;
- gpios = <&gpio2 21 0>;
+ gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
- leds {
- compatible = "gpio-leds";
+ guardian_leds: gpio-leds {
pinctrl-names = "default";
- pinctrl-0 = <&leds_pins>;
+ pinctrl-0 = <&guardian_led_pins>;
+ compatible = "gpio-leds";
- led1 {
- label = "green:heartbeat";
- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ life-led {
+ label = "guardian:life-led";
+ gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
+ };
- led2 {
- label = "green:mmc0";
- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
panel {
@@ -100,20 +105,36 @@
};
- pwm7: dmtimer-pwm {
+ guardian_beeper: dmtimer-pwm@7 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer7>;
pinctrl-names = "default";
- pinctrl-0 = <&dmtimer7_pins>;
+ pinctrl-0 = <&guardian_beeper_pins>;
ti,clock-source = <0x01>;
};
- vmmcsd_fixed: regulator-3v3 {
+ vmmcsd_fixed: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ mt_keypad: mt_keypad@0 {
+ compatible = "gpio-mt-keypad";
+ debounce-delay-ms = <10>;
+ col-scan-delay-us = <2>;
+ keypad,num-lines = <5>;
+ linux,no-autorepeat;
+ gpio-activelow;
+ line-gpios = <
+ &gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/
+ &gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/
+ &gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/
+ &gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/
+ &gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/
+ >;
+ };
};
&elm {
@@ -133,28 +154,29 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
+ gpmc,cs-rd-off-ns = <30>;
+ gpmc,cs-wr-off-ns = <30>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <30>;
+ gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <0>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-on-ns = <0>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
+ gpmc,we-off-ns = <15>;
+ gpmc,oe-on-ns = <1>;
+ gpmc,oe-off-ns = <15>;
+ gpmc,access-ns = <30>;
+ gpmc,rd-cycle-ns = <30>;
+ gpmc,wr-cycle-ns = <30>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wr-access-ns = <40>;
+ gpmc,wr-access-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/*
@@ -198,18 +220,33 @@
};
partition@6 {
- label = "u-boot-env";
- reg = <0x300000 0x40000>;
+ label = "u-boot-2";
+ reg = <0x300000 0x100000>;
};
partition@7 {
- label = "u-boot-env.backup1";
- reg = <0x340000 0x40000>;
+ label = "u-boot-2.backup1";
+ reg = <0x400000 0x100000>;
};
partition@8 {
+ label = "u-boot-env";
+ reg = <0x500000 0x40000>;
+ };
+
+ partition@9 {
+ label = "u-boot-env.backup1";
+ reg = <0x540000 0x40000>;
+ };
+
+ partition@10 {
+ label = "splash-screen";
+ reg = <0x580000 0x40000>;
+ };
+
+ partition@11 {
label = "UBI";
- reg = <0x380000 0x1fc80000>;
+ reg = <0x5c0000 0x1fa40000>;
};
};
};
@@ -228,6 +265,11 @@
&lcdc {
blue-and-red-wiring = "crossed";
status = "okay";
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <0>;
+ };
+ };
};
&mmc1 {
@@ -242,7 +284,6 @@
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
- system-power-controller;
};
&spi0 {
@@ -255,14 +296,34 @@
#include "tps65217.dtsi"
&tps {
+ /*
+ * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
+ * mode") at poweroff. Most BeagleBone versions do not support RTC-only
+ * mode and risk hardware damage if this mode is entered.
+ *
+ * For details, see linux-omap mailing list May 2015 thread
+ * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
+ * In particular, messages:
+ * http://www.spinics.net/lists/linux-omap/msg118585.html
+ * http://www.spinics.net/lists/linux-omap/msg118615.html
+ *
+ * You can override this later with
+ * &tps { /delete-property/ ti,pmic-shutdown-controller; }
+ * if you want to use RTC-only mode and made sure you are not affected
+ * by the hardware problems. (Tip: double-check by performing a current
+ * measurement after shutdown: it should be less than 1 mA.)
+ */
ti,pmic-shutdown-controller;
interrupt-parent = <&intc>;
interrupts = <7>; /* NMI */
backlight {
isel = <1>; /* 1 - ISET1, 2 ISET2 */
- fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
- default-brightness = <100>;
+ fdim = <500>; /* TPS65217_BL_FDIM_500HZ */
+ default-brightness = <50>;
+ /* 1(on) - enable current sink, while initialization */
+ /* 0(off) - disable current sink, while initialization */
+ isink-en = <1>;
};
regulators {
@@ -272,6 +333,7 @@
};
dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1351500>;
@@ -280,6 +342,7 @@
};
dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
@@ -319,171 +382,364 @@
};
};
+&gpio0 {
+ gpio-line-names =
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "MirxWakeup",
+ "",
+ "";
+};
+
+&gpio3 {
+ ti,gpio-always-on;
+ ti,no-reset-on-init;
+ gpio-line-names =
+ "",
+ "MirxBtReset",
+ "",
+ "CcVolAdcEn",
+ "MirxBlePause",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AspEn",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "BatVolAdcEn",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
&usb0 {
dr_mode = "peripheral";
};
&usb1 {
dr_mode = "host";
+ /delete-property/dmas;
+ /delete-property/dma-names;
};
&am33xx_pinmux {
pinctrl-names = "default";
- pinctrl-0 = <&clkout2_pin &gpio_pins>;
+ pinctrl-0 = <&clkout2_pin &guardian_interface_pins>;
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
+ /* xdma_event_intr1.clkout2 */
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
>;
};
- dmtimer7_pins: pinmux_dmtimer7_pins {
+ guardian_interface_pins: pinmux_interface_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5)
+ /* ADC_BATSENSE_EN */
+ /* (A14) MCASP0_AHCLKx.gpio3[21] */
+ AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* ADC_COINCELL_EN */
+ /* (J16) MII1_TX_EN.gpio3[3] */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* ASP_ENABLE */
+ /* (A13) MCASP0_ACLKx.gpio3[14] */
+ AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ /* (D16) uart1_rxd.uart1_rxd */
+ AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7)
+ /* (D15) uart1_txd.uart1_txd */
+ AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7)
+ /*SWITCH-OFF_3V6*/
+ /* (M18) gpio0[1] */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ /* MIRACULIX */
+ /* (H17) gmii1_crs.gpio3[1] */
+ AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* (H18) rmii1_refclk.gpio0[29] */
+ AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* (J18) gmii1_txd3.gpio0[16] */
+ AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 )
+ /* (J17) gmii1_rxdv.gpio3[4] */
+ AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
>;
};
- gpio_keys_pins: pinmux_gpio_keys_pins {
+ guardian_beeper_pins: pinmux_dmtimer7_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */
>;
};
- gpio_pins: pinmux_gpio_pins {
+ guardian_button_pins: pinmux_guardian_button_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */
+ AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */
>;
};
+
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ led_bl_pins: gpio_led_bl_pins {
+ pinctrl-single,pins = <
+ /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */
+ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
>;
};
lcd_disen_pins: pinmux_lcd_disen_pins {
pinctrl-single,pins = <
+ /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */
AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7)
>;
};
lcd_pins_default: pinmux_lcd_pins_default {
pinctrl-single,pins = <
+ /* (U10) gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (T10) gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (T11) gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (U12) gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (T12) gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (R12) gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (V13) gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (U13) gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
>;
};
lcd_pins_sleep: pinmux_lcd_pins_sleep {
pinctrl-single,pins = <
+ /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
>;
};
- leds_pins: pinmux_leds_pins {
+ guardian_led_pins: pinmux_guardian_led_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
+ /* SPI0_CLK - spi0_clk.spi */
AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ /* SPI0_MOSI - spi0_d0.spi0 */
AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ /* SPI0_MISO - spi0_d1.spi0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)
+ /* SPI0_CS0 - spi */
AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
+ /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
+ /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
>;
};
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ /* K18 uart2_rxd.mirx_txd */
+ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1)
+ /* L18 uart2_txd.mirx_rxd */
+ AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)
+ >;
+ };
+
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
+ /* (U7) gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0)
+ /* (V7) gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0)
+ /* (R8) gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0)
+ /* (T8) gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0)
+ /* (U8) gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0)
+ /* (V8) gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0)
+ /* (R9) gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0)
+ /* (T9) gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0)
+ /* (T17) gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0)
+ /* (U17) gpmc_wpn.gpmc_wpn */
AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0)
+ /* (V6) gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
+ /* (R7) gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
+ /* (T7) gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
+ /* (U6) gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
+ /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
>;
};
diff --git a/dts/src/arm/am335x-moxa-uc-2100-common.dtsi b/dts/src/arm/am335x-moxa-uc-2100-common.dtsi
index 11e8f64b66..92a0e98ec2 100644
--- a/dts/src/arm/am335x-moxa-uc-2100-common.dtsi
+++ b/dts/src/arm/am335x-moxa-uc-2100-common.dtsi
@@ -182,7 +182,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
- m25p80@0 {
+ flash@0 {
compatible = "mx25l6405d";
spi-max-frequency = <40000000>;
diff --git a/dts/src/arm/am335x-moxa-uc-8100-common.dtsi b/dts/src/arm/am335x-moxa-uc-8100-common.dtsi
index a7269b90d7..e7e439a063 100644
--- a/dts/src/arm/am335x-moxa-uc-8100-common.dtsi
+++ b/dts/src/arm/am335x-moxa-uc-8100-common.dtsi
@@ -394,7 +394,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
- m25p80@0 {
+ flash@0 {
compatible = "mx25l6405d";
spi-max-frequency = <40000000>;
diff --git a/dts/src/arm/am335x-myirtech-myc.dtsi b/dts/src/arm/am335x-myirtech-myc.dtsi
index 245c35f41c..6eea18b293 100644
--- a/dts/src/arm/am335x-myirtech-myc.dtsi
+++ b/dts/src/arm/am335x-myirtech-myc.dtsi
@@ -27,6 +27,13 @@
reg = <0x80000000 0x10000000>;
};
+ clk32k: clk32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+
+ #clock-cells = <0>;
+ };
+
vdd_mod: vdd_mod_reg {
compatible = "regulator-fixed";
regulator-name = "vdd-mod";
@@ -124,9 +131,6 @@
gpmc,wr-data-mux-bus-ns = <0>;
ti,elm-id = <&elm>;
ti,nand-ecc-opt = "bch8";
-
- #address-cells = <1>;
- #size-cells = <1>;
};
};
@@ -149,6 +153,8 @@
};
&rtc {
+ clocks = <&clk32k>;
+ clock-names = "ext-clk";
system-power-controller;
};
diff --git a/dts/src/arm/am335x-myirtech-myd.dts b/dts/src/arm/am335x-myirtech-myd.dts
index 1479fd95de..9d81d4cc68 100644
--- a/dts/src/arm/am335x-myirtech-myd.dts
+++ b/dts/src/arm/am335x-myirtech-myd.dts
@@ -227,14 +227,20 @@
};
&nand0 {
- partition@0 {
- label = "MLO";
- reg = <0x00000 0x20000>;
- };
+ nand_parts: partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- partition@20000 {
- label = "boot";
- reg = <0x20000 0x80000>;
+ partition@0 {
+ label = "MLO";
+ reg = <0x00000 0x20000>;
+ };
+
+ partition@80000 {
+ label = "boot";
+ reg = <0x80000 0x100000>;
+ };
};
};
diff --git a/dts/src/arm/am335x-phycore-som.dtsi b/dts/src/arm/am335x-phycore-som.dtsi
index f65cd13313..e2cec1ffaa 100644
--- a/dts/src/arm/am335x-phycore-som.dtsi
+++ b/dts/src/arm/am335x-phycore-som.dtsi
@@ -331,7 +331,7 @@
pinctrl-0 = <&spi0_pins>;
status = "okay";
- serial_flash: m25p80@0 {
+ serial_flash: flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <48000000>;
reg = <0x0>;
diff --git a/dts/src/arm/am335x-sl50.dts b/dts/src/arm/am335x-sl50.dts
index 6516907ed5..73b5d1a024 100644
--- a/dts/src/arm/am335x-sl50.dts
+++ b/dts/src/arm/am335x-sl50.dts
@@ -588,7 +588,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
- flash: n25q032@1 {
+ flash: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q032";
diff --git a/dts/src/arm/am33xx-clocks.dtsi b/dts/src/arm/am33xx-clocks.dtsi
index b7b7106f2d..d34483ae17 100644
--- a/dts/src/arm/am33xx-clocks.dtsi
+++ b/dts/src/arm/am33xx-clocks.dtsi
@@ -5,251 +5,288 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&scm_clocks {
- sys_clkin_ck: sys_clkin_ck@40 {
+ sys_clkin_ck: clock-sys-clkin-22@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <22>;
reg = <0x0040>;
};
- adc_tsc_fck: adc_tsc_fck {
+ adc_tsc_fck: clock-adc-tsc-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "adc_tsc_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan0_fck: dcan0_fck {
+ dcan0_fck: clock-dcan0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan1_fck: dcan1_fck {
+ dcan1_fck: clock-dcan1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp0_fck: mcasp0_fck {
+ mcasp0_fck: clock-mcasp0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp1_fck: mcasp1_fck {
+ mcasp1_fck: clock-mcasp1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex0_fck: smartreflex0_fck {
+ smartreflex0_fck: clock-smartreflex0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex1_fck: smartreflex1_fck {
+ smartreflex1_fck: clock-smartreflex1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- sha0_fck: sha0_fck {
+ sha0_fck: clock-sha0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sha0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- aes0_fck: aes0_fck {
+ aes0_fck: clock-aes0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "aes0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- rng_fck: rng_fck {
+ rng_fck: clock-rng-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "rng_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4ls_gclk>;
- ti,bit-shift = <0>;
- reg = <0x0664>;
- };
+ clock@664 {
+ compatible = "ti,clksel";
+ reg = <0x664>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4ls_gclk>;
- ti,bit-shift = <1>;
- reg = <0x0664>;
- };
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <0>;
+ };
- ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4ls_gclk>;
- ti,bit-shift = <2>;
- reg = <0x0664>;
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <1>;
+ };
+
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <2>;
+ };
};
};
&prcm_clocks {
- clk_32768_ck: clk_32768_ck {
+ clk_32768_ck: clock-clk-32768 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32768_ck";
clock-frequency = <32768>;
};
- clk_rc32k_ck: clk_rc32k_ck {
+ clk_rc32k_ck: clock-clk-rc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_rc32k_ck";
clock-frequency = <32000>;
};
- virt_19200000_ck: virt_19200000_ck {
+ virt_19200000_ck: clock-virt-19200000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
- virt_24000000_ck: virt_24000000_ck {
+ virt_24000000_ck: clock-virt-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_24000000_ck";
clock-frequency = <24000000>;
};
- virt_25000000_ck: virt_25000000_ck {
+ virt_25000000_ck: clock-virt-25000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_25000000_ck";
clock-frequency = <25000000>;
};
- virt_26000000_ck: virt_26000000_ck {
+ virt_26000000_ck: clock-virt-26000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
- tclkin_ck: tclkin_ck {
+ tclkin_ck: clock-tclkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "tclkin_ck";
clock-frequency = <12000000>;
};
- dpll_core_ck: dpll_core_ck@490 {
+ dpll_core_ck: clock@490 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
- dpll_core_x2_ck: dpll_core_x2_ck {
+ dpll_core_x2_ck: clock-dpll-core-x2 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
- dpll_core_m4_ck: dpll_core_m4_ck@480 {
+ dpll_core_m4_ck: clock-dpll-core-m4@480 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0480>;
ti,index-starts-at-one;
};
- dpll_core_m5_ck: dpll_core_m5_ck@484 {
+ dpll_core_m5_ck: clock-dpll-core-m5@484 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0484>;
ti,index-starts-at-one;
};
- dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
+ dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x04d8>;
ti,index-starts-at-one;
};
- dpll_mpu_ck: dpll_mpu_ck@488 {
+ dpll_mpu_ck: clock@488 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
+ dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
reg = <0x04a8>;
ti,index-starts-at-one;
};
- dpll_ddr_ck: dpll_ddr_ck@494 {
+ dpll_ddr_ck: clock@494 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
+ clock-output-names = "dpll_ddr_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
+ dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
reg = <0x04a0>;
ti,index-starts-at-one;
};
- dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+ dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_ddr_m2_div2_ck";
clocks = <&dpll_ddr_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- dpll_disp_ck: dpll_disp_ck@498 {
+ dpll_disp_ck: clock@498 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
+ clock-output-names = "dpll_disp_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
- dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
+ dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_disp_m2_ck";
clocks = <&dpll_disp_ck>;
ti,max-div = <31>;
reg = <0x04a4>;
@@ -257,418 +294,484 @@
ti,set-rate-parent;
};
- dpll_per_ck: dpll_per_ck@48c {
+ dpll_per_ck: clock@48c {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
- dpll_per_m2_ck: dpll_per_m2_ck@4ac {
+ dpll_per_m2_ck: clock-dpll-per-m2@4ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
reg = <0x04ac>;
ti,index-starts-at-one;
};
- dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- clk_24mhz: clk_24mhz {
+ clk_24mhz: clock-clk-24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clk_24mhz";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <8>;
};
- clkdiv32k_ck: clkdiv32k_ck {
+ clkdiv32k_ck: clock-clkdiv32k {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clkdiv32k_ck";
clocks = <&clk_24mhz>;
clock-mult = <1>;
clock-div = <732>;
};
- l3_gclk: l3_gclk {
+ l3_gclk: clock-l3-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- pruss_ocp_gclk: pruss_ocp_gclk@530 {
+ pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "pruss_ocp_gclk";
clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
reg = <0x0530>;
};
- mmu_fck: mmu_fck@914 {
+ mmu_fck: clock-mmu-fck-1@914 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "mmu_fck";
clocks = <&dpll_core_m4_ck>;
ti,bit-shift = <1>;
reg = <0x0914>;
};
- timer1_fck: timer1_fck@528 {
+ timer1_fck: clock-timer1-fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer1_fck";
clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
- timer2_fck: timer2_fck@508 {
+ timer2_fck: clock-timer2-fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer2_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
- timer3_fck: timer3_fck@50c {
+ timer3_fck: clock-timer3-fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer3_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
- timer4_fck: timer4_fck@510 {
+ timer4_fck: clock-timer4-fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer4_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
- timer5_fck: timer5_fck@518 {
+ timer5_fck: clock-timer5-fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer5_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
- timer6_fck: timer6_fck@51c {
+ timer6_fck: clock-timer6-fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer6_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
- timer7_fck: timer7_fck@504 {
+ timer7_fck: clock-timer7-fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer7_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
- usbotg_fck: usbotg_fck@47c {
+ usbotg_fck: clock-usbotg-fck-8@47c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usbotg_fck";
clocks = <&dpll_per_ck>;
ti,bit-shift = <8>;
reg = <0x047c>;
};
- dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_core_m4_div2_ck";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- ieee5000_fck: ieee5000_fck@e4 {
+ ieee5000_fck: clock-ieee5000-fck-1@e4 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ieee5000_fck";
clocks = <&dpll_core_m4_div2_ck>;
ti,bit-shift = <1>;
reg = <0x00e4>;
};
- wdt1_fck: wdt1_fck@538 {
+ wdt1_fck: clock-wdt1-fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wdt1_fck";
clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
- l4_rtc_gclk: l4_rtc_gclk {
+ l4_rtc_gclk: clock-l4-rtc-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4_rtc_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- l4hs_gclk: l4hs_gclk {
+ l4hs_gclk: clock-l4hs-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4hs_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l3s_gclk: l3s_gclk {
+ l3s_gclk: clock-l3s-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3s_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l4fw_gclk: l4fw_gclk {
+ l4fw_gclk: clock-l4fw-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4fw_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l4ls_gclk: l4ls_gclk {
+ l4ls_gclk: clock-l4ls-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4ls_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- sysclk_div_ck: sysclk_div_ck {
+ sysclk_div_ck: clock-sysclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sysclk_div_ck";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_125mhz_gclk";
clocks = <&dpll_core_m5_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
+ cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "cpsw_cpts_rft_clk";
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
reg = <0x0520>;
};
- gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
+ gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpio0_dbclk_mux_ck";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
- lcd_gclk: lcd_gclk@534 {
+ lcd_gclk: clock-lcd-gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "lcd_gclk";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
reg = <0x0534>;
ti,set-rate-parent;
};
- mmc_clk: mmc_clk {
+ mmc_clk: clock-mmc {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mmc_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
- ti,bit-shift = <1>;
- reg = <0x052c>;
- };
+ clock@52c {
+ compatible = "ti,clksel";
+ reg = <0x52c>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- gfx_fck_div_ck: gfx_fck_div_ck@52c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&gfx_fclk_clksel_ck>;
- reg = <0x052c>;
- ti,max-div = <2>;
- };
+ gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "gfx_fclk_clksel_ck";
+ clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+ ti,bit-shift = <1>;
+ };
- sysclkout_pre_ck: sysclkout_pre_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
- reg = <0x0700>;
+ gfx_fck_div_ck: clock-gfx-fck-div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "gfx_fck_div_ck";
+ clocks = <&gfx_fclk_clksel_ck>;
+ ti,max-div = <2>;
+ };
};
- clkout2_div_ck: clkout2_div_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sysclkout_pre_ck>;
- ti,bit-shift = <3>;
- ti,max-div = <8>;
- reg = <0x0700>;
- };
+ clock@700 {
+ compatible = "ti,clksel";
+ reg = <0x700>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- clkout2_ck: clkout2_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkout2_div_ck>;
- ti,bit-shift = <7>;
- reg = <0x0700>;
+ sysclkout_pre_ck: clock-sysclkout-pre {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "sysclkout_pre_ck";
+ clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+ };
+
+ clkout2_div_ck: clock-clkout2-div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "clkout2_div_ck";
+ clocks = <&sysclkout_pre_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <8>;
+ };
+
+ clkout2_ck: clock-clkout2 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "clkout2_ck";
+ clocks = <&clkout2_div_ck>;
+ ti,bit-shift = <7>;
+ };
};
};
&prcm {
- per_cm: per-cm@0 {
+ per_cm: clock@0 {
compatible = "ti,omap4-cm";
+ clock-output-names = "per_cm";
reg = <0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x400>;
- l4ls_clkctrl: l4ls-clkctrl@38 {
+ l4ls_clkctrl: clock@38 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4ls_clkctrl";
reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
#clock-cells = <2>;
};
- l3s_clkctrl: l3s-clkctrl@1c {
+ l3s_clkctrl: clock@1c {
compatible = "ti,clkctrl";
+ clock-output-names = "l3s_clkctrl";
reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
#clock-cells = <2>;
};
- l3_clkctrl: l3-clkctrl@24 {
+ l3_clkctrl: clock@24 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_clkctrl";
reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
#clock-cells = <2>;
};
- l4hs_clkctrl: l4hs-clkctrl@120 {
+ l4hs_clkctrl: clock@120 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4hs_clkctrl";
reg = <0x120 0x4>;
#clock-cells = <2>;
};
- pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
+ pruss_ocp_clkctrl: clock@e8 {
compatible = "ti,clkctrl";
+ clock-output-names = "pruss_ocp_clkctrl";
reg = <0xe8 0x4>;
#clock-cells = <2>;
};
- cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
+ cpsw_125mhz_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "cpsw_125mhz_clkctrl";
reg = <0x0 0x18>;
#clock-cells = <2>;
};
- lcdc_clkctrl: lcdc-clkctrl@18 {
+ lcdc_clkctrl: clock@18 {
compatible = "ti,clkctrl";
+ clock-output-names = "lcdc_clkctrl";
reg = <0x18 0x4>;
#clock-cells = <2>;
};
- clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
+ clk_24mhz_clkctrl: clock@14c {
compatible = "ti,clkctrl";
+ clock-output-names = "clk_24mhz_clkctrl";
reg = <0x14c 0x4>;
#clock-cells = <2>;
};
};
- wkup_cm: wkup-cm@400 {
+ wkup_cm: clock@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkup_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
- l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
+ l4_wkup_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
reg = <0x0 0x10>, <0xb4 0x24>;
#clock-cells = <2>;
};
- l3_aon_clkctrl: l3-aon-clkctrl@14 {
+ l3_aon_clkctrl: clock@14 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_aon_clkctrl";
reg = <0x14 0x4>;
#clock-cells = <2>;
};
- l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
+ l4_wkup_aon_clkctrl: clock@b0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_aon_clkctrl";
reg = <0xb0 0x4>;
#clock-cells = <2>;
};
};
- mpu_cm: mpu-cm@600 {
+ mpu_cm: clock@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- mpu_clkctrl: mpu-clkctrl@0 {
+ mpu_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_rtc_cm: l4-rtc-cm@800 {
+ l4_rtc_cm: clock@800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_rtc_cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
- l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
+ l4_rtc_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_rtc_clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
- gfx_l3_cm: gfx-l3-cm@900 {
+ gfx_l3_cm: clock@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gfx_l3_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
- gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
+ gfx_l3_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "gfx_l3_clkctrl";
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_cefuse_cm: l4-cefuse-cm@a00 {
+ l4_cefuse_cm: clock@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_cefuse_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
- l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
+ l4_cefuse_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_cefuse_clkctrl";
reg = <0x0 0x24>;
#clock-cells = <2>;
};
diff --git a/dts/src/arm/am33xx.dtsi b/dts/src/arm/am33xx.dtsi
index f6ec85d58d..9a8698bd28 100644
--- a/dts/src/arm/am33xx.dtsi
+++ b/dts/src/arm/am33xx.dtsi
@@ -461,8 +461,11 @@
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
+ /* For backwards compatibility: */
#dma-channels = <30>;
+ dma-channels = <30>;
#dma-requests = <256>;
+ dma-requests = <256>;
};
};
diff --git a/dts/src/arm/am35xx-clocks.dtsi b/dts/src/arm/am35xx-clocks.dtsi
index 220d0a5279..0ee7afaa0e 100644
--- a/dts/src/arm/am35xx-clocks.dtsi
+++ b/dts/src/arm/am35xx-clocks.dtsi
@@ -62,12 +62,27 @@
};
};
&cm_clocks {
- ipss_ick: ipss_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,am35xx-interface-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <4>;
+ clock@a10 {
+ compatible = "ti,clksel";
+ reg = <0xa10>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ ipss_ick: clock-ipss-ick {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-interface-clock";
+ clock-output-names = "ipss_ick";
+ clocks = <&core_l3_ick>;
+ ti,bit-shift = <4>;
+ };
+
+ uart4_ick_am35xx: clock-uart4-ick-am35xx {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "uart4_ick_am35xx";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <23>;
+ };
};
rmii_ck: rmii_ck {
@@ -82,20 +97,19 @@
clock-frequency = <27000000>;
};
- uart4_ick_am35xx: uart4_ick_am35xx@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <23>;
- };
+ clock@a00 {
+ compatible = "ti,clksel";
+ reg = <0xa00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- uart4_fck_am35xx: uart4_fck_am35xx@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <23>;
+ uart4_fck_am35xx: clock-uart4-fck-am35xx {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "uart4_fck_am35xx";
+ clocks = <&core_48m_fck>;
+ ti,bit-shift = <23>;
+ };
};
};
diff --git a/dts/src/arm/am3874-iceboard.dts b/dts/src/arm/am3874-iceboard.dts
index 9423e9feaa..c9323d1df3 100644
--- a/dts/src/arm/am3874-iceboard.dts
+++ b/dts/src/arm/am3874-iceboard.dts
@@ -434,7 +434,7 @@
};
&mcspi1 {
- s25fl256@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/am437x-cm-t43.dts b/dts/src/arm/am437x-cm-t43.dts
index 3e3354780d..0861e868b7 100644
--- a/dts/src/arm/am437x-cm-t43.dts
+++ b/dts/src/arm/am437x-cm-t43.dts
@@ -302,7 +302,7 @@
&edma 17 0>;
dma-names = "tx0", "rx0";
- flash: w25q64cvzpig@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/am437x-gp-evm.dts b/dts/src/arm/am437x-gp-evm.dts
index 4416ddb559..46d5361fe8 100644
--- a/dts/src/arm/am437x-gp-evm.dts
+++ b/dts/src/arm/am437x-gp-evm.dts
@@ -1127,6 +1127,11 @@
cpu0-supply = <&dcdc2>;
};
+&wkup_m3_ipc {
+ ti,set-io-isolation;
+ firmware-name = "am43x-evm-scale-data.bin";
+};
+
&pruss1_mdio {
status = "disabled";
};
diff --git a/dts/src/arm/am437x-idk-evm.dts b/dts/src/arm/am437x-idk-evm.dts
index 53f64e3ce7..5a74b83145 100644
--- a/dts/src/arm/am437x-idk-evm.dts
+++ b/dts/src/arm/am437x-idk-evm.dts
@@ -437,7 +437,7 @@
pinctrl-1 = <&qspi_pins_sleep>;
spi-max-frequency = <48000000>;
- m25p80@0 {
+ flash@0 {
compatible = "mx66l51235l";
spi-max-frequency = <48000000>;
reg = <0>;
diff --git a/dts/src/arm/am437x-sk-evm.dts b/dts/src/arm/am437x-sk-evm.dts
index 20a34d2d85..036f3831dc 100644
--- a/dts/src/arm/am437x-sk-evm.dts
+++ b/dts/src/arm/am437x-sk-evm.dts
@@ -746,7 +746,7 @@
pinctrl-0 = <&qspi_pins>;
spi-max-frequency = <48000000>;
- m25p80@0 {
+ flash@0 {
compatible = "mx66l51235l";
spi-max-frequency = <48000000>;
reg = <0>;
@@ -893,6 +893,10 @@
};
};
+&wkup_m3_ipc {
+ firmware-name = "am43x-evm-scale-data.bin";
+};
+
&pruss1_mdio {
status = "disabled";
};
diff --git a/dts/src/arm/am43x-epos-evm.dts b/dts/src/arm/am43x-epos-evm.dts
index 4f9a7251a1..27f4ce8555 100644
--- a/dts/src/arm/am43x-epos-evm.dts
+++ b/dts/src/arm/am43x-epos-evm.dts
@@ -902,7 +902,7 @@
pinctrl-1 = <&qspi1_pins_sleep>;
spi-max-frequency = <48000000>;
- m25p80@0 {
+ flash@0 {
compatible = "mx66l51235l";
spi-max-frequency = <48000000>;
reg = <0>;
@@ -1019,6 +1019,10 @@
cpu0-supply = <&dcdc2>;
};
+&wkup_m3_ipc {
+ firmware-name = "am43x-evm-scale-data.bin";
+};
+
&pruss1_mdio {
status = "disabled";
};
diff --git a/dts/src/arm/am43xx-clocks.dtsi b/dts/src/arm/am43xx-clocks.dtsi
index 66e892fa33..9a5437b3d6 100644
--- a/dts/src/arm/am43xx-clocks.dtsi
+++ b/dts/src/arm/am43xx-clocks.dtsi
@@ -5,217 +5,246 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&scm_clocks {
- sys_clkin_ck: sys_clkin_ck@40 {
+ sys_clkin_ck: clock-sys-clkin-31@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
ti,bit-shift = <31>;
reg = <0x0040>;
};
- crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
+ crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "crystal_freq_sel_ck";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <29>;
reg = <0x0040>;
};
- sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
+ sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sysboot_freq_sel_ck";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <22>;
reg = <0x0040>;
};
- adc_tsc_fck: adc_tsc_fck {
+ adc_tsc_fck: clock-adc-tsc-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "adc_tsc_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan0_fck: dcan0_fck {
+ dcan0_fck: clock-dcan0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan1_fck: dcan1_fck {
+ dcan1_fck: clock-dcan1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp0_fck: mcasp0_fck {
+ mcasp0_fck: clock-mcasp0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp1_fck: mcasp1_fck {
+ mcasp1_fck: clock-mcasp1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex0_fck: smartreflex0_fck {
+ smartreflex0_fck: clock-smartreflex0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex1_fck: smartreflex1_fck {
+ smartreflex1_fck: clock-smartreflex1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- sha0_fck: sha0_fck {
+ sha0_fck: clock-sha0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sha0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- aes0_fck: aes0_fck {
+ aes0_fck: clock-aes0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "aes0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- rng_fck: rng_fck {
+ rng_fck: clock-rng-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "rng_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
- ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
- ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
- ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
+ ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm3_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <4>;
reg = <0x0664>;
};
- ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
+ ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm4_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <5>;
reg = <0x0664>;
};
- ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
+ ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm5_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <6>;
reg = <0x0664>;
};
};
&prcm_clocks {
- clk_32768_ck: clk_32768_ck {
+ clk_32768_ck: clock-clk-32768 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32768_ck";
clock-frequency = <32768>;
};
- clk_rc32k_ck: clk_rc32k_ck {
+ clk_rc32k_ck: clock-clk-rc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_rc32k_ck";
clock-frequency = <32768>;
};
- virt_19200000_ck: virt_19200000_ck {
+ virt_19200000_ck: clock-virt-19200000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
- virt_24000000_ck: virt_24000000_ck {
+ virt_24000000_ck: clock-virt-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_24000000_ck";
clock-frequency = <24000000>;
};
- virt_25000000_ck: virt_25000000_ck {
+ virt_25000000_ck: clock-virt-25000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_25000000_ck";
clock-frequency = <25000000>;
};
- virt_26000000_ck: virt_26000000_ck {
+ virt_26000000_ck: clock-virt-26000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
- tclkin_ck: tclkin_ck {
+ tclkin_ck: clock-tclkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "tclkin_ck";
clock-frequency = <26000000>;
};
- dpll_core_ck: dpll_core_ck@2d20 {
+ dpll_core_ck: clock@2d20 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
- dpll_core_x2_ck: dpll_core_x2_ck {
+ dpll_core_x2_ck: clock-dpll-core-x2 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
- dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
+ dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -224,9 +253,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
+ dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -235,9 +265,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
+ dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -246,16 +277,18 @@
ti,invert-autoidle-bit;
};
- dpll_mpu_ck: dpll_mpu_ck@2d60 {
+ dpll_mpu_ck: clock@2d60 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
+ dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -264,24 +297,27 @@
ti,invert-autoidle-bit;
};
- mpu_periphclk: mpu_periphclk {
+ mpu_periphclk: clock-mpu-periphclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_periphclk";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- dpll_ddr_ck: dpll_ddr_ck@2da0 {
+ dpll_ddr_ck: clock@2da0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_ddr_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
+ dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -290,16 +326,18 @@
ti,invert-autoidle-bit;
};
- dpll_disp_ck: dpll_disp_ck@2e20 {
+ dpll_disp_ck: clock@2e20 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_disp_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
- dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
+ dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_disp_m2_ck";
clocks = <&dpll_disp_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -309,16 +347,18 @@
ti,set-rate-parent;
};
- dpll_per_ck: dpll_per_ck@2de0 {
+ dpll_per_ck: clock@2de0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
- dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
+ dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -327,119 +367,135 @@
ti,invert-autoidle-bit;
};
- dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- clk_24mhz: clk_24mhz {
+ clk_24mhz: clock-clk-24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clk_24mhz";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <8>;
};
- clkdiv32k_ck: clkdiv32k_ck {
+ clkdiv32k_ck: clock-clkdiv32k {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clkdiv32k_ck";
clocks = <&clk_24mhz>;
clock-mult = <1>;
clock-div = <732>;
};
- clkdiv32k_ick: clkdiv32k_ick@2a38 {
+ clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "clkdiv32k_ick";
clocks = <&clkdiv32k_ck>;
ti,bit-shift = <8>;
reg = <0x2a38>;
};
- sysclk_div: sysclk_div {
+ sysclk_div: clock-sysclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sysclk_div";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- pruss_ocp_gclk: pruss_ocp_gclk@4248 {
+ pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "pruss_ocp_gclk";
clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
reg = <0x4248>;
};
- clk_32k_tpm_ck: clk_32k_tpm_ck {
+ clk_32k_tpm_ck: clock-clk-32k-tpm {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32k_tpm_ck";
clock-frequency = <32768>;
};
- timer1_fck: timer1_fck@4200 {
+ timer1_fck: clock-timer1-fck@4200 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer1_fck";
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
reg = <0x4200>;
};
- timer2_fck: timer2_fck@4204 {
+ timer2_fck: clock-timer2-fck@4204 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer2_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4204>;
};
- timer3_fck: timer3_fck@4208 {
+ timer3_fck: clock-timer3-fck@4208 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer3_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4208>;
};
- timer4_fck: timer4_fck@420c {
+ timer4_fck: clock-timer4-fck@420c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer4_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x420c>;
};
- timer5_fck: timer5_fck@4210 {
+ timer5_fck: clock-timer5-fck@4210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer5_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4210>;
};
- timer6_fck: timer6_fck@4214 {
+ timer6_fck: clock-timer6-fck@4214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer6_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4214>;
};
- timer7_fck: timer7_fck@4218 {
+ timer7_fck: clock-timer7-fck@4218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer7_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4218>;
};
- wdt1_fck: wdt1_fck@422c {
+ wdt1_fck: clock-wdt1-fck@422c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wdt1_fck";
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
reg = <0x422c>;
};
@@ -451,125 +507,141 @@
reg = <0x424c>;
};
- l3_gclk: l3_gclk {
+ l3_gclk: clock-l3-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_core_m4_div2_ck";
clocks = <&sysclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
- l4hs_gclk: l4hs_gclk {
+ l4hs_gclk: clock-l4hs-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4hs_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l3s_gclk: l3s_gclk {
+ l3s_gclk: clock-l3s-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3s_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l4ls_gclk: l4ls_gclk {
+ l4ls_gclk: clock-l4ls-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4ls_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_125mhz_gclk";
clocks = <&dpll_core_m5_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
+ cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "cpsw_cpts_rft_clk";
clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
reg = <0x4238>;
};
- dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
+ dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_clksel_mac_clk";
clocks = <&dpll_core_m5_ck>;
reg = <0x4234>;
ti,bit-shift = <2>;
ti,dividers = <2>, <5>;
};
- clk_32k_mosc_ck: clk_32k_mosc_ck {
+ clk_32k_mosc_ck: clock-clk-32k-mosc {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32k_mosc_ck";
clock-frequency = <32768>;
};
- gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
+ gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpio0_dbclk_mux_ck";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
reg = <0x4240>;
};
- mmc_clk: mmc_clk {
+ mmc_clk: clock-mmc {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mmc_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
+ gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gfx_fclk_clksel_ck";
clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
ti,bit-shift = <1>;
reg = <0x423c>;
};
- gfx_fck_div_ck: gfx_fck_div_ck@423c {
+ gfx_fck_div_ck: clock-gfx-fck-div@423c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "gfx_fck_div_ck";
clocks = <&gfx_fclk_clksel_ck>;
reg = <0x423c>;
ti,max-div = <2>;
};
- disp_clk: disp_clk@4244 {
+ disp_clk: clock-disp@4244 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "disp_clk";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
reg = <0x4244>;
ti,set-rate-parent;
};
- dpll_extdev_ck: dpll_extdev_ck@2e60 {
+ dpll_extdev_ck: clock@2e60 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_extdev_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
- dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
+ dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_extdev_m2_ck";
clocks = <&dpll_extdev_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -578,66 +650,75 @@
ti,invert-autoidle-bit;
};
- mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
+ mux_synctimer32k_ck: clock-mux-synctimer32k@4230 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "mux_synctimer32k_ck";
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
reg = <0x4230>;
};
- timer8_fck: timer8_fck@421c {
+ timer8_fck: clock-timer8-fck@421c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer8_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x421c>;
};
- timer9_fck: timer9_fck@4220 {
+ timer9_fck: clock-timer9-fck@4220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer9_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4220>;
};
- timer10_fck: timer10_fck@4224 {
+ timer10_fck: clock-timer10-fck@4224 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer10_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4224>;
};
- timer11_fck: timer11_fck@4228 {
+ timer11_fck: clock-timer11-fck@4228 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer11_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4228>;
};
- cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+ cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_50m_clkdiv";
clocks = <&dpll_core_m5_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+ cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_5m_clkdiv";
clocks = <&cpsw_50m_clkdiv>;
clock-mult = <1>;
clock-div = <10>;
};
- dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_ddr_x2_ck";
clocks = <&dpll_ddr_ck>;
};
- dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
+ dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m4_ck";
clocks = <&dpll_ddr_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -646,9 +727,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
+ dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
+ clock-output-names = "dpll_per_clkdcoldo";
clocks = <&dpll_per_ck>;
ti,clock-mult = <1>;
ti,clock-div = <1>;
@@ -657,91 +739,102 @@
ti,invert-autoidle-bit;
};
- dll_aging_clk_div: dll_aging_clk_div@4250 {
+ dll_aging_clk_div: clock-dll-aging-clk-div@4250 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dll_aging_clk_div";
clocks = <&sys_clkin_ck>;
reg = <0x4250>;
ti,dividers = <8>, <16>, <32>;
};
- div_core_25m_ck: div_core_25m_ck {
+ div_core_25m_ck: clock-div-core-25m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "div_core_25m_ck";
clocks = <&sysclk_div>;
clock-mult = <1>;
clock-div = <8>;
};
- func_12m_clk: func_12m_clk {
+ func_12m_clk: clock-func-12m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
- vtp_clk_div: vtp_clk_div {
+ vtp_clk_div: clock-vtp-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "vtp_clk_div";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
+ usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "usbphy_32khz_clkmux";
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
reg = <0x4260>;
};
- usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
+ usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy0_always_on_clk32k";
clocks = <&usbphy_32khz_clkmux>;
ti,bit-shift = <8>;
reg = <0x2a40>;
};
- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
+ usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy1_always_on_clk32k";
clocks = <&usbphy_32khz_clkmux>;
ti,bit-shift = <8>;
reg = <0x2a48>;
};
- clkout1_osc_div_ck: clkout1-osc-div-ck {
+ clkout1_osc_div_ck: clock-clkout1-osc-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "clkout1_osc_div_ck";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
};
- clkout1_src2_mux_ck: clkout1-src2-mux-ck {
+ clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkout1_src2_mux_ck";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
};
- clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
+ clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "clkout1_src2_pre_div_ck";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
- clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
+ clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "clkout1_src2_post_div_ck";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
@@ -749,18 +842,20 @@
reg = <0x4100>;
};
- clkout1_mux_ck: clkout1-mux-ck {
+ clkout1_mux_ck: clock-clkout1-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkout1_mux_ck";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
- clkout1_ck: clkout1-ck {
+ clkout1_ck: clock-clkout1-ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "clkout1_ck";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
@@ -768,120 +863,138 @@
};
&prcm {
- wkup_cm: wkup-cm@2800 {
+ wkup_cm: clock@2800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkup_cm";
reg = <0x2800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x400>;
- l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
+ l3s_tsc_clkctrl: clock@120 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3s_tsc_clkctrl";
reg = <0x120 0x4>;
#clock-cells = <2>;
};
- l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
+ l4_wkup_aon_clkctrl: clock@228 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_aon_clkctrl";
reg = <0x228 0xc>;
#clock-cells = <2>;
};
- l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
+ l4_wkup_clkctrl: clock@220 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
reg = <0x220 0x4>, <0x328 0x44>;
#clock-cells = <2>;
};
};
- mpu_cm: mpu-cm@8300 {
+ mpu_cm: clock@8300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x8300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8300 0x100>;
- mpu_clkctrl: mpu-clkctrl@20 {
+ mpu_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- gfx_l3_cm: gfx-l3-cm@8400 {
+ gfx_l3_cm: clock@8400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gfx_l3_cm";
reg = <0x8400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
- gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
+ gfx_l3_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "gfx_l3_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- l4_rtc_cm: l4-rtc-cm@8500 {
+ l4_rtc_cm: clock@8500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_rtc_cm";
reg = <0x8500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
- l4_rtc_clkctrl: l4-rtc-clkctrl@20 {
+ l4_rtc_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_rtc_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- per_cm: per-cm@8800 {
+ per_cm: clock@8800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "per_cm";
reg = <0x8800 0xc00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8800 0xc00>;
- l3_clkctrl: l3-clkctrl@20 {
+ l3_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_clkctrl";
reg = <0x20 0x3c>, <0x78 0x2c>;
#clock-cells = <2>;
};
- l3s_clkctrl: l3s-clkctrl@68 {
+ l3s_clkctrl: clock@68 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3s_clkctrl";
reg = <0x68 0xc>, <0x220 0x4c>;
#clock-cells = <2>;
};
- pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 {
+ pruss_ocp_clkctrl: clock@320 {
compatible = "ti,clkctrl";
+ clock-output-names = "pruss_ocp_clkctrl";
reg = <0x320 0x4>;
#clock-cells = <2>;
};
- l4ls_clkctrl: l4ls-clkctrl@420 {
+ l4ls_clkctrl: clock@420 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4ls_clkctrl";
reg = <0x420 0x1a4>;
#clock-cells = <2>;
};
- emif_clkctrl: emif-clkctrl@720 {
+ emif_clkctrl: clock@720 {
compatible = "ti,clkctrl";
+ clock-output-names = "emif_clkctrl";
reg = <0x720 0x4>;
#clock-cells = <2>;
};
- dss_clkctrl: dss-clkctrl@a20 {
+ dss_clkctrl: clock@a20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dss_clkctrl";
reg = <0xa20 0x4>;
#clock-cells = <2>;
};
- cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 {
+ cpsw_125mhz_clkctrl: clock@b20 {
compatible = "ti,clkctrl";
+ clock-output-names = "cpsw_125mhz_clkctrl";
reg = <0xb20 0x4>;
#clock-cells = <2>;
};
diff --git a/dts/src/arm/am574x-idk.dts b/dts/src/arm/am574x-idk.dts
index 6dff3660bf..47b9174d23 100644
--- a/dts/src/arm/am574x-idk.dts
+++ b/dts/src/arm/am574x-idk.dts
@@ -18,7 +18,7 @@
&qspi {
spi-max-frequency = <96000000>;
- m25p80@0 {
+ flash@0 {
spi-max-frequency = <96000000>;
};
};
diff --git a/dts/src/arm/am57xx-cl-som-am57x.dts b/dts/src/arm/am57xx-cl-som-am57x.dts
index 2e94f32d9d..2fc9a5d5e0 100644
--- a/dts/src/arm/am57xx-cl-som-am57x.dts
+++ b/dts/src/arm/am57xx-cl-som-am57x.dts
@@ -491,7 +491,7 @@
spi-max-frequency = <48000000>;
- spi_flash: spi_flash@0 {
+ spi_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80", "jedec,spi-nor";
diff --git a/dts/src/arm/am57xx-idk-common.dtsi b/dts/src/arm/am57xx-idk-common.dtsi
index 9fcb8944aa..c06eda8172 100644
--- a/dts/src/arm/am57xx-idk-common.dtsi
+++ b/dts/src/arm/am57xx-idk-common.dtsi
@@ -526,7 +526,7 @@
status = "okay";
spi-max-frequency = <76800000>;
- m25p80@0 {
+ flash@0 {
compatible = "s25fl256s1", "jedec,spi-nor";
spi-max-frequency = <76800000>;
reg = <0>;
diff --git a/dts/src/arm/armada-370-db.dts b/dts/src/arm/armada-370-db.dts
index 77261a2fb9..a7dc4c04d1 100644
--- a/dts/src/arm/armada-370-db.dts
+++ b/dts/src/arm/armada-370-db.dts
@@ -203,7 +203,7 @@
pinctrl-names = "default";
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mx25l25635e", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-370-seagate-personal-cloud.dtsi b/dts/src/arm/armada-370-seagate-personal-cloud.dtsi
index a624b2371f..0abac5ffe4 100644
--- a/dts/src/arm/armada-370-seagate-personal-cloud.dtsi
+++ b/dts/src/arm/armada-370-seagate-personal-cloud.dtsi
@@ -159,7 +159,7 @@
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
/* MX25L8006E */
diff --git a/dts/src/arm/armada-370-synology-ds213j.dts b/dts/src/arm/armada-370-synology-ds213j.dts
index 64f2ce254f..e72b8ed4b9 100644
--- a/dts/src/arm/armada-370-synology-ds213j.dts
+++ b/dts/src/arm/armada-370-synology-ds213j.dts
@@ -258,7 +258,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-375-db.dts b/dts/src/arm/armada-375-db.dts
index 0e679465cb..4c4092790a 100644
--- a/dts/src/arm/armada-375-db.dts
+++ b/dts/src/arm/armada-375-db.dts
@@ -64,7 +64,7 @@
status = "disabled";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-381-netgear-gs110emx.dts b/dts/src/arm/armada-381-netgear-gs110emx.dts
index 0a961116a1..396172067f 100644
--- a/dts/src/arm/armada-381-netgear-gs110emx.dts
+++ b/dts/src/arm/armada-381-netgear-gs110emx.dts
@@ -242,7 +242,7 @@
pinctrl-names = "default";
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/armada-385-atl-x530.dts b/dts/src/arm/armada-385-atl-x530.dts
index ed3f41c7df..241f5d7c80 100644
--- a/dts/src/arm/armada-385-atl-x530.dts
+++ b/dts/src/arm/armada-385-atl-x530.dts
@@ -168,7 +168,7 @@
pinctrl-0 = <&spi1_pins>;
status = "okay";
- spi-flash@1 {
+ flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/armada-385-clearfog-gtr.dtsi b/dts/src/arm/armada-385-clearfog-gtr.dtsi
index 624bbcae68..10ad46f293 100644
--- a/dts/src/arm/armada-385-clearfog-gtr.dtsi
+++ b/dts/src/arm/armada-385-clearfog-gtr.dtsi
@@ -365,7 +365,7 @@
pinctrl-names = "default";
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "w25q32", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-385-db-88f6820-amc.dts b/dts/src/arm/armada-385-db-88f6820-amc.dts
index 7881df3b28..389d9c75d5 100644
--- a/dts/src/arm/armada-385-db-88f6820-amc.dts
+++ b/dts/src/arm/armada-385-db-88f6820-amc.dts
@@ -126,7 +126,7 @@
pinctrl-0 = <&spi1_pins>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/armada-385-db-ap.dts b/dts/src/arm/armada-385-db-ap.dts
index 0e4613bb56..332f8fce77 100644
--- a/dts/src/arm/armada-385-db-ap.dts
+++ b/dts/src/arm/armada-385-db-ap.dts
@@ -192,7 +192,7 @@
pinctrl-0 = <&spi1_pins>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-385-synology-ds116.dts b/dts/src/arm/armada-385-synology-ds116.dts
index d8769956cb..2622af73c9 100644
--- a/dts/src/arm/armada-385-synology-ds116.dts
+++ b/dts/src/arm/armada-385-synology-ds116.dts
@@ -223,7 +223,7 @@
pinctrl-0 = <&spi0_pins>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "macronix,mx25l6405d", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-385-turris-omnia.dts b/dts/src/arm/armada-385-turris-omnia.dts
index f240018148..f4878df397 100644
--- a/dts/src/arm/armada-385-turris-omnia.dts
+++ b/dts/src/arm/armada-385-turris-omnia.dts
@@ -348,7 +348,11 @@
#size-cells = <0>;
reg = <5>;
- /* ATSHA204A at address 0x64 */
+ /* ATSHA204A-MAHDA-T crypto module */
+ crypto@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
};
i2c@6 {
@@ -485,7 +489,7 @@
pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "spansion,s25fl164k", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/src/arm/armada-388-db.dts b/dts/src/arm/armada-388-db.dts
index a2bec07bf4..5130eccc32 100644
--- a/dts/src/arm/armada-388-db.dts
+++ b/dts/src/arm/armada-388-db.dts
@@ -133,7 +133,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-388-gp.dts b/dts/src/arm/armada-388-gp.dts
index 9d873257ac..e2ba50520b 100644
--- a/dts/src/arm/armada-388-gp.dts
+++ b/dts/src/arm/armada-388-gp.dts
@@ -395,7 +395,7 @@
pinctrl-0 = <&spi0_pins>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-388-rd.dts b/dts/src/arm/armada-388-rd.dts
index 328a4d6afd..c0efafd45b 100644
--- a/dts/src/arm/armada-388-rd.dts
+++ b/dts/src/arm/armada-388-rd.dts
@@ -97,7 +97,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-38x-solidrun-microsom.dtsi b/dts/src/arm/armada-38x-solidrun-microsom.dtsi
index 363ac42388..2c64bc6e5a 100644
--- a/dts/src/arm/armada-38x-solidrun-microsom.dtsi
+++ b/dts/src/arm/armada-38x-solidrun-microsom.dtsi
@@ -101,7 +101,7 @@
/* The microsom has an optional W25Q32 on board, connected to CS0 */
pinctrl-0 = <&spi1_pins>;
- w25q32: spi-flash@0 {
+ w25q32: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-390-db.dts b/dts/src/arm/armada-390-db.dts
index 0e29474ae9..792d0a0184 100644
--- a/dts/src/arm/armada-390-db.dts
+++ b/dts/src/arm/armada-390-db.dts
@@ -81,7 +81,7 @@
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
- spi-flash@1 {
+ flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13",
diff --git a/dts/src/arm/armada-398-db.dts b/dts/src/arm/armada-398-db.dts
index fc28308e5b..ec6cdbeedd 100644
--- a/dts/src/arm/armada-398-db.dts
+++ b/dts/src/arm/armada-398-db.dts
@@ -79,7 +79,7 @@
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "n25q128a13", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-axpwifiap.dts b/dts/src/arm/armada-xp-axpwifiap.dts
index 606fd3476a..3e77b43378 100644
--- a/dts/src/arm/armada-xp-axpwifiap.dts
+++ b/dts/src/arm/armada-xp-axpwifiap.dts
@@ -134,7 +134,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-crs305-1g-4s-bit.dts b/dts/src/arm/armada-xp-crs305-1g-4s-bit.dts
index a022c68dc9..c28e140b4a 100644
--- a/dts/src/arm/armada-xp-crs305-1g-4s-bit.dts
+++ b/dts/src/arm/armada-xp-crs305-1g-4s-bit.dts
@@ -15,7 +15,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-crs305-1g-4s.dtsi b/dts/src/arm/armada-xp-crs305-1g-4s.dtsi
index 32fb21b2bf..47b003a81b 100644
--- a/dts/src/arm/armada-xp-crs305-1g-4s.dtsi
+++ b/dts/src/arm/armada-xp-crs305-1g-4s.dtsi
@@ -80,7 +80,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-crs326-24g-2s-bit.dts b/dts/src/arm/armada-xp-crs326-24g-2s-bit.dts
index 21f442afab..20ba5c823b 100644
--- a/dts/src/arm/armada-xp-crs326-24g-2s-bit.dts
+++ b/dts/src/arm/armada-xp-crs326-24g-2s-bit.dts
@@ -15,7 +15,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-crs326-24g-2s.dtsi b/dts/src/arm/armada-xp-crs326-24g-2s.dtsi
index f3e1a25ca5..cab99d8e29 100644
--- a/dts/src/arm/armada-xp-crs326-24g-2s.dtsi
+++ b/dts/src/arm/armada-xp-crs326-24g-2s.dtsi
@@ -80,7 +80,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-crs328-4c-20s-4s-bit.dts b/dts/src/arm/armada-xp-crs328-4c-20s-4s-bit.dts
index e05aee6cdc..2caa3980fd 100644
--- a/dts/src/arm/armada-xp-crs328-4c-20s-4s-bit.dts
+++ b/dts/src/arm/armada-xp-crs328-4c-20s-4s-bit.dts
@@ -15,7 +15,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-crs328-4c-20s-4s.dtsi b/dts/src/arm/armada-xp-crs328-4c-20s-4s.dtsi
index c8b1355ce1..7028482ce4 100644
--- a/dts/src/arm/armada-xp-crs328-4c-20s-4s.dtsi
+++ b/dts/src/arm/armada-xp-crs328-4c-20s-4s.dtsi
@@ -80,7 +80,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-db-dxbc2.dts b/dts/src/arm/armada-xp-db-dxbc2.dts
index 8a3aa616bb..02bef8dc42 100644
--- a/dts/src/arm/armada-xp-db-dxbc2.dts
+++ b/dts/src/arm/armada-xp-db-dxbc2.dts
@@ -93,7 +93,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
diff --git a/dts/src/arm/armada-xp-db-xc3-24g4xg.dts b/dts/src/arm/armada-xp-db-xc3-24g4xg.dts
index 4ec0ae01b6..d1b61dad0c 100644
--- a/dts/src/arm/armada-xp-db-xc3-24g4xg.dts
+++ b/dts/src/arm/armada-xp-db-xc3-24g4xg.dts
@@ -89,7 +89,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
diff --git a/dts/src/arm/armada-xp-db.dts b/dts/src/arm/armada-xp-db.dts
index 5d04dc68cf..75318fd0fc 100644
--- a/dts/src/arm/armada-xp-db.dts
+++ b/dts/src/arm/armada-xp-db.dts
@@ -235,7 +235,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-gp.dts b/dts/src/arm/armada-xp-gp.dts
index b4cca507cf..d1d348b91c 100644
--- a/dts/src/arm/armada-xp-gp.dts
+++ b/dts/src/arm/armada-xp-gp.dts
@@ -220,7 +220,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
diff --git a/dts/src/arm/armada-xp-linksys-mamba.dts b/dts/src/arm/armada-xp-linksys-mamba.dts
index 8480a16919..36932e3b78 100644
--- a/dts/src/arm/armada-xp-linksys-mamba.dts
+++ b/dts/src/arm/armada-xp-linksys-mamba.dts
@@ -255,7 +255,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "everspin,mr25h256";
diff --git a/dts/src/arm/armada-xp-synology-ds414.dts b/dts/src/arm/armada-xp-synology-ds414.dts
index 809e821d73..5551bac196 100644
--- a/dts/src/arm/armada-xp-synology-ds414.dts
+++ b/dts/src/arm/armada-xp-synology-ds414.dts
@@ -274,7 +274,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064", "jedec,spi-nor";
diff --git a/dts/src/arm/aspeed-ast2600-evb.dts b/dts/src/arm/aspeed-ast2600-evb.dts
index b7eb552640..5a6063bd45 100644
--- a/dts/src/arm/aspeed-ast2600-evb.dts
+++ b/dts/src/arm/aspeed-ast2600-evb.dts
@@ -23,6 +23,26 @@
reg = <0x80000000 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ video_engine_memory: video {
+ size = <0x04000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
vcc_sdhci0: regulator-vcc-sdhci0 {
compatible = "regulator-fixed";
regulator-name = "SDHCI0 Vcc";
@@ -103,7 +123,7 @@
&mac0 {
status = "okay";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-rxid";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
@@ -114,7 +134,7 @@
&mac1 {
status = "okay";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-rxid";
phy-handle = <&ethphy1>;
pinctrl-names = "default";
@@ -300,3 +320,18 @@
vqmmc-supply = <&vccq_sdhci1>;
clk-phase-sd-hs = <7>, <200>;
};
+
+&vhub {
+ status = "okay";
+ pinctrl-names = "default";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
diff --git a/dts/src/arm/aspeed-bmc-facebook-bletchley.dts b/dts/src/arm/aspeed-bmc-facebook-bletchley.dts
index eaf1bc261e..41d2b1535d 100644
--- a/dts/src/arm/aspeed-bmc-facebook-bletchley.dts
+++ b/dts/src/arm/aspeed-bmc-facebook-bletchley.dts
@@ -51,26 +51,6 @@
};
};
- spi2_gpio: spi2-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
- num-chipselects = <1>;
- cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- m25p,fast-read;
- label = "pnor";
- spi-max-frequency = <100000000>;
- };
- };
-
switchphy: ethernet-phy@0 {
// Fixed link
};
@@ -242,6 +222,19 @@
};
};
+&spi2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <50000000>;
+ };
+};
+
&i2c0 {
status = "okay";
ina230@45 {
@@ -260,6 +253,17 @@
reg = <0x4f>;
};
+ sled1_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED1_SWD_MUX", "SLED1_XRES_SWD_N",
+ "SLED1_CLKREQ_N", "SLED1_PCIE_PWR_EN";
+ };
+
sled1_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -310,6 +314,11 @@
op-sink-microwatt = <10000000>;
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c1 {
@@ -330,6 +339,17 @@
reg = <0x4f>;
};
+ sled2_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED2_SWD_MUX", "SLED2_XRES_SWD_N",
+ "SLED2_CLKREQ_N", "SLED2_PCIE_PWR_EN";
+ };
+
sled2_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -380,6 +400,11 @@
op-sink-microwatt = <10000000>;
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c2 {
@@ -400,6 +425,17 @@
reg = <0x4f>;
};
+ sled3_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED3_SWD_MUX", "SLED3_XRES_SWD_N",
+ "SLED3_CLKREQ_N", "SLED3_PCIE_PWR_EN";
+ };
+
sled3_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -450,6 +486,11 @@
op-sink-microwatt = <10000000>;
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c3 {
@@ -470,6 +511,17 @@
reg = <0x4f>;
};
+ sled4_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED4_SWD_MUX", "SLED4_XRES_SWD_N",
+ "SLED4_CLKREQ_N", "SLED4_PCIE_PWR_EN";
+ };
+
sled4_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -520,6 +572,11 @@
op-sink-microwatt = <10000000>;
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c4 {
@@ -540,6 +597,17 @@
reg = <0x4f>;
};
+ sled5_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED5_SWD_MUX", "SLED5_XRES_SWD_N",
+ "SLED5_CLKREQ_N", "SLED5_PCIE_PWR_EN";
+ };
+
sled5_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -590,6 +658,11 @@
op-sink-microwatt = <10000000>;
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c5 {
@@ -610,6 +683,17 @@
reg = <0x4f>;
};
+ sled6_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED6_SWD_MUX", "SLED6_XRES_SWD_N",
+ "SLED6_CLKREQ_N", "SLED6_PCIE_PWR_EN";
+ };
+
sled6_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -660,6 +744,11 @@
op-sink-microwatt = <10000000>;
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c6 {
@@ -732,6 +821,8 @@
compatible = "adi,adm1278";
reg = <0x11>;
shunt-resistor-micro-ohms = <300>;
+ adi,volt-curr-sample-average = <128>;
+ adi,power-sample-average = <128>;
};
tmp421@4c {
@@ -771,43 +862,55 @@
&gpio0 {
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
- /*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1",
- "SPI2_MUX2","SPI2_MUX3","","",
+ /*B0-B7*/ "FUSB302_SLED1_INT_N","FUSB302_SLED2_INT_N",
+ "SEL_SPI2_MUX","SPI2_MUX1",
+ "SPI2_MUX2","SPI2_MUX3",
+ "","FUSB302_SLED3_INT_N",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
- /*F0-F7*/ "","","","","","","","",
- /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","",
+ /*F0-F7*/ "BMC_SLED1_STCK","BMC_SLED2_STCK",
+ "BMC_SLED3_STCK","BMC_SLED4_STCK",
+ "BMC_SLED5_STCK","BMC_SLED6_STCK",
+ "","",
+ /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","FM_SOL_UART_CH_SEL",
"PWRGD_P1V05_VDDCORE","PWRGD_P1V5_VDD","","",
/*H0-H7*/ "presence-riser1","presence-riser2",
"presence-sled1","presence-sled2",
"presence-sled3","presence-sled4",
"presence-sled5","presence-sled6",
- /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2",
- "","BSM_FLASH_WP_STATUS","BMC_TPM_PRES","",
+ /*I0-I7*/ "REV_ID0","",
+ "REV_ID1","REV_ID2",
+ "","BSM_FLASH_WP_STATUS",
+ "BMC_TPM_PRES_N","FUSB302_SLED6_INT_N",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","BMC_RTC_INT","","",
- /*M0-M7*/ "ALERT_SLED1","ALERT_SLED2",
- "ALERT_SLED3","ALERT_SLED4",
- "ALERT_SLED5","ALERT_SLED6",
- "P12V_AUX_ALERT1","",
- /*N0-N7*/ "","","","","","","","",
+ /*M0-M7*/ "ALERT_SLED1_N","ALERT_SLED2_N",
+ "ALERT_SLED3_N","ALERT_SLED4_N",
+ "ALERT_SLED5_N","ALERT_SLED6_N",
+ "","",
+ /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1",
+ "LED_POSTCODE_2","LED_POSTCODE_3",
+ "LED_POSTCODE_4","LED_POSTCODE_5",
+ "LED_POSTCODE_5","LED_POSTCODE_7",
/*O0-O7*/ "","","","",
"","BOARD_ID0","BOARD_ID1","BOARD_ID2",
/*P0-P7*/ "","","","","","","","BMC_HEARTBEAT",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","BAT_DETECT",
- "BMC_BT_WP0","BMC_BT_WP1","","",
+ "BMC_BT_WP0_N","BMC_BT_WP1_N","","FUSB302_SLED4_INT_N",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
- /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL","","PSU_PRSNT",
+ /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL_N",
+ "P12V_AUX_ALERT1_N","PSU_PRSNT",
"USB2_SEL0_A","USB2_SEL1_A",
"USB2_SEL0_B","USB2_SEL1_B",
- /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","",
+ /*W0-W7*/ "RST_FRONT_IOEXP_N","","","","","","","",
/*X0-X7*/ "","","","","","","","",
- /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT","BSM_FLASH_LATCH","",
+ /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT_N",
+ "BSM_FLASH_LATCH_N","FUSB302_SLED5_INT_N",
"","","","",
/*Z0-Z7*/ "","","","","","","","";
};
@@ -834,7 +937,16 @@
&pinctrl_adc14_default &pinctrl_adc15_default>;
};
+&mdio0 {
+ status = "okay";
+ /* TODO: Add Marvell 88E6191X */
+};
+
&mdio3 {
status = "okay";
/* TODO: Add Marvell 88X3310 */
};
+
+&ehci0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/aspeed-bmc-ibm-everest.dts b/dts/src/arm/aspeed-bmc-ibm-everest.dts
index 578f9e2fc7..382da7934e 100644
--- a/dts/src/arm/aspeed-bmc-ibm-everest.dts
+++ b/dts/src/arm/aspeed-bmc-ibm-everest.dts
@@ -283,7 +283,7 @@
/*P0-P7*/ "","","","","led-pcieslot-power","","","",
/*Q0-Q7*/ "","","regulator-standby-faulted","","","","","",
/*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","",
- /*S0-S7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","power-ffs-sync-history","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","",
diff --git a/dts/src/arm/aspeed-bmc-ibm-rainier.dts b/dts/src/arm/aspeed-bmc-ibm-rainier.dts
index 528b49e2c0..7213434695 100644
--- a/dts/src/arm/aspeed-bmc-ibm-rainier.dts
+++ b/dts/src/arm/aspeed-bmc-ibm-rainier.dts
@@ -265,7 +265,7 @@
/*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","",
/*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","",
/*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3",
- "","","","",
+ "power-ffs-sync-history","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
diff --git a/dts/src/arm/aspeed-bmc-nuvia-dc-scm.dts b/dts/src/arm/aspeed-bmc-nuvia-dc-scm.dts
new file mode 100644
index 0000000000..f4a97cfb0f
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-nuvia-dc-scm.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+
+/ {
+ model = "Nuvia DC-SCM BMC";
+ compatible = "nuvia,dc-scm-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial4 = &uart5;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&mdio3 {
+ status = "okay";
+
+ ethphy3: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mac2 {
+ status = "okay";
+
+ /* Bootloader sets up the MAC to insert delay */
+ phy-mode = "rgmii";
+ phy-handle = <&ethphy3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii3_default>;
+};
+
+&mac3 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii4_default>;
+
+ use-ncsi;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <133000000>;
+#include "openbmc-flash-layout-64.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <133000000>;
+#include "openbmc-flash-layout-64-alt.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bios";
+ spi-max-frequency = <133000000>;
+ };
+};
+
+&gpio0 {
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "","","","","","","","",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","",
+ /*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3",
+ "SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3",
+ "SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","",
+ /*AA0-AA7*/ "","","","","","","","",
+ /*AB0-AB7*/ "","","","","","","","",
+ /*AC0-AC7*/ "","","","","","","","";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*A0-A7*/ "GPI_1_BMC_1V8","","","","","",
+ "SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8",
+ /*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8",
+ "SCMFPGA_SPARE_GPIO5_1V8","","","","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","",
+ "","TPM2_PIRQ_N","TPM2_RST_N","",
+ /*E0-E7*/ "","","","","","","","";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+};
diff --git a/dts/src/arm/aspeed-g4.dtsi b/dts/src/arm/aspeed-g4.dtsi
index fa8b581c3d..530491ae5e 100644
--- a/dts/src/arm/aspeed-g4.dtsi
+++ b/dts/src/arm/aspeed-g4.dtsi
@@ -54,8 +54,7 @@
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0x94
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
@@ -65,34 +64,42 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@3 {
reg = < 3 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@4 {
reg = < 4 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
spi: spi@1e630000 {
- reg = < 0x1e630000 0x18
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
@@ -102,6 +109,7 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
diff --git a/dts/src/arm/aspeed-g5.dtsi b/dts/src/arm/aspeed-g5.dtsi
index 4147b397c8..c89092c390 100644
--- a/dts/src/arm/aspeed-g5.dtsi
+++ b/dts/src/arm/aspeed-g5.dtsi
@@ -55,8 +55,7 @@
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
@@ -67,25 +66,27 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x08000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
@@ -95,19 +96,20 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x38000000 0x08000000 >;
+ reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
@@ -117,12 +119,14 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
diff --git a/dts/src/arm/aspeed-g6.dtsi b/dts/src/arm/aspeed-g6.dtsi
index 9d2a0ce4ca..6660564855 100644
--- a/dts/src/arm/aspeed-g6.dtsi
+++ b/dts/src/arm/aspeed-g6.dtsi
@@ -95,8 +95,7 @@
};
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-fmc";
@@ -107,25 +106,27 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
@@ -135,19 +136,20 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x50000000 0x10000000 >;
+ reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
@@ -157,18 +159,21 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -181,6 +186,7 @@
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio1_default>;
+ resets = <&syscon ASPEED_RESET_MII>;
};
mdio1: mdio@1e650008 {
@@ -191,6 +197,7 @@
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio2_default>;
+ resets = <&syscon ASPEED_RESET_MII>;
};
mdio2: mdio@1e650010 {
@@ -201,6 +208,7 @@
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio3_default>;
+ resets = <&syscon ASPEED_RESET_MII>;
};
mdio3: mdio@1e650018 {
@@ -211,6 +219,7 @@
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio4_default>;
+ resets = <&syscon ASPEED_RESET_MII>;
};
mac0: ftgmac@1e660000 {
@@ -298,6 +307,16 @@
status = "disabled";
};
+ udc: usb@1e6a2000 {
+ compatible = "aspeed,ast2600-udc";
+ reg = <0x1e6a2000 0x300>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2bd_default>;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -351,6 +370,17 @@
quality = <100>;
};
+ gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2600-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ reg-io-width = <4>;
+ clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
+ resets = <&syscon ASPEED_RESET_GRAPHICS>;
+ syscon = <&syscon>;
+ status = "disabled";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
xdma: xdma@1e6e7000 {
compatible = "aspeed,ast2600-xdma";
reg = <0x1e6e7000 0x100>;
diff --git a/dts/src/arm/at91-sama7g5ek.dts b/dts/src/arm/at91-sama7g5ek.dts
index d83f76a6cd..103544620f 100644
--- a/dts/src/arm/at91-sama7g5ek.dts
+++ b/dts/src/arm/at91-sama7g5ek.dts
@@ -14,6 +14,7 @@
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/sound/microchip,pdmc.h>
/ {
model = "Microchip SAMA7G5-EK";
@@ -456,7 +457,7 @@
&pinctrl_gmac1_mdio_default
&pinctrl_gmac1_phy_irq>;
phy-mode = "rmii";
- status = "okay";
+ status = "okay"; /* Conflict with pdmc0. */
ethernet-phy@0 {
reg = <0x0>;
@@ -470,6 +471,17 @@
pinctrl-0 = <&pinctrl_i2s0_default>;
};
+&pdmc0 {
+ #sound-dai-cells = <0>;
+ microchip,mic-pos = <MCHP_PDMC_DS0 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 1 */
+ <MCHP_PDMC_DS1 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 2 */
+ <MCHP_PDMC_DS0 MCHP_PDMC_CLK_POSITIVE>, /* MIC 3 */
+ <MCHP_PDMC_DS1 MCHP_PDMC_CLK_POSITIVE>; /* MIC 4 */
+ status = "disabled"; /* Conflict with gmac1. */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pdmc0_default>;
+};
+
&pioA {
pinctrl_can0_default: can0_default {
@@ -639,6 +651,13 @@
bias-disable;
};
+ pinctrl_pdmc0_default: pdmc0_default {
+ pinmux = <PIN_PD23__PDMC0_DS0>,
+ <PIN_PD24__PDMC0_DS1>,
+ <PIN_PD22__PDMC0_CLK>;
+ bias_disable;
+ };
+
pinctrl_qspi: qspi {
pinmux = <PIN_PB12__QSPI0_IO0>,
<PIN_PB11__QSPI0_IO1>,
diff --git a/dts/src/arm/at91sam9261ek.dts b/dts/src/arm/at91sam9261ek.dts
index 8f11c0b7d7..6fb4fe49cf 100644
--- a/dts/src/arm/at91sam9261ek.dts
+++ b/dts/src/arm/at91sam9261ek.dts
@@ -178,6 +178,10 @@
status = "okay";
};
+ rtc@fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ };
+
watchdog@fffffd40 {
status = "okay";
};
diff --git a/dts/src/arm/at91sam9263ek.dts b/dts/src/arm/at91sam9263ek.dts
index 42e7340202..e732565913 100644
--- a/dts/src/arm/at91sam9263ek.dts
+++ b/dts/src/arm/at91sam9263ek.dts
@@ -102,6 +102,10 @@
};
};
+ rtc@fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ };
+
watchdog@fffffd40 {
status = "okay";
};
diff --git a/dts/src/arm/at91sam9rlek.dts b/dts/src/arm/at91sam9rlek.dts
index d74b8d9d84..ddaadfec67 100644
--- a/dts/src/arm/at91sam9rlek.dts
+++ b/dts/src/arm/at91sam9rlek.dts
@@ -212,6 +212,10 @@
status = "okay";
};
+ rtc@fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ };
+
rtc@fffffe00 {
status = "okay";
};
diff --git a/dts/src/arm/bcm-cygnus.dtsi b/dts/src/arm/bcm-cygnus.dtsi
index ad65be8719..f9f79ed825 100644
--- a/dts/src/arm/bcm-cygnus.dtsi
+++ b/dts/src/arm/bcm-cygnus.dtsi
@@ -397,8 +397,8 @@
#size-cells = <0>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi_0>;
- clocks = <&axi81_clk>;
- clock-names = "apb_pclk";
+ clocks = <&axi81_clk>, <&axi81_clk>;
+ clock-names = "sspclk", "apb_pclk";
status = "disabled";
};
@@ -409,8 +409,8 @@
#size-cells = <0>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi_1>;
- clocks = <&axi81_clk>;
- clock-names = "apb_pclk";
+ clocks = <&axi81_clk>, <&axi81_clk>;
+ clock-names = "sspclk", "apb_pclk";
status = "disabled";
};
@@ -421,8 +421,8 @@
#size-cells = <0>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi_2>;
- clocks = <&axi81_clk>;
- clock-names = "apb_pclk";
+ clocks = <&axi81_clk>, <&axi81_clk>;
+ clock-names = "sspclk", "apb_pclk";
status = "disabled";
};
diff --git a/dts/src/arm/bcm2835-rpi-a-plus.dts b/dts/src/arm/bcm2835-rpi-a-plus.dts
index 40b9405f1a..9b9a18bbb2 100644
--- a/dts/src/arm/bcm2835-rpi-a-plus.dts
+++ b/dts/src/arm/bcm2835-rpi-a-plus.dts
@@ -32,7 +32,6 @@
* This is based on the unreleased schematic for the Model A+.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -67,21 +66,21 @@
"GPIO27",
"SDA0",
"SCL0",
- "NC", /* GPIO30 */
- "NC", /* GPIO31 */
+ "", /* GPIO30 */
+ "", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
"PWR_LOW_N", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
"USB_LIMIT", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
"PWM1_OUT", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED",
diff --git a/dts/src/arm/bcm2835-rpi-a.dts b/dts/src/arm/bcm2835-rpi-a.dts
index 11edb581db..f664e4fced 100644
--- a/dts/src/arm/bcm2835-rpi-a.dts
+++ b/dts/src/arm/bcm2835-rpi-a.dts
@@ -26,7 +26,6 @@
* RPI00021 sheet 02
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -42,41 +41,41 @@
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
- "NC", /* GPIO12 */
- "NC", /* GPIO13 */
+ "", /* GPIO12 */
+ "", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
- "NC", /* GPIO19 */
- "NC", /* GPIO20 */
+ "", /* GPIO19 */
+ "", /* GPIO20 */
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
- "NC", /* GPIO26 */
+ "", /* GPIO26 */
"CAM_GPIO0",
/* Binary number representing build/revision */
"CONFIG0",
"CONFIG1",
"CONFIG2",
"CONFIG3",
- "NC", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO32 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
+ "", /* GPIO35 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
+ "", /* GPIO38 */
+ "", /* GPIO39 */
"PWM0_OUT",
- "NC", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
+ "", /* GPIO41 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
diff --git a/dts/src/arm/bcm2835-rpi-b-plus.dts b/dts/src/arm/bcm2835-rpi-b-plus.dts
index 1b435c64bd..248feb2ed2 100644
--- a/dts/src/arm/bcm2835-rpi-b-plus.dts
+++ b/dts/src/arm/bcm2835-rpi-b-plus.dts
@@ -34,7 +34,6 @@
* RPI-BPLUS sheet 1
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -69,21 +68,21 @@
"GPIO27",
"SDA0",
"SCL0",
- "NC", /* GPIO30 */
+ "", /* GPIO30 */
"LAN_RUN", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
"PWR_LOW_N", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
"USB_LIMIT", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "ETHCLK", /* GPIO44 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "ETH_CLK", /* GPIO44 */
"PWM1_OUT", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED",
diff --git a/dts/src/arm/bcm2835-rpi-b-rev2.dts b/dts/src/arm/bcm2835-rpi-b-rev2.dts
index a23c25c00e..f5b66d3f4f 100644
--- a/dts/src/arm/bcm2835-rpi-b-rev2.dts
+++ b/dts/src/arm/bcm2835-rpi-b-rev2.dts
@@ -27,7 +27,6 @@
* RPI00022 sheet 02
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -43,40 +42,40 @@
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
- "NC", /* GPIO12 */
- "NC", /* GPIO13 */
+ "", /* GPIO12 */
+ "", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
- "NC", /* GPIO19 */
- "NC", /* GPIO20 */
+ "", /* GPIO19 */
+ "", /* GPIO20 */
"CAM_GPIO",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
- "NC", /* GPIO26 */
+ "", /* GPIO26 */
"GPIO27",
"GPIO28",
"GPIO29",
"GPIO30",
"GPIO31",
- "NC", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO32 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
+ "", /* GPIO35 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
+ "", /* GPIO38 */
+ "", /* GPIO39 */
"PWM0_OUT",
- "NC", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
+ "", /* GPIO41 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
diff --git a/dts/src/arm/bcm2835-rpi-b.dts b/dts/src/arm/bcm2835-rpi-b.dts
index 1b63d6b197..f589bede2b 100644
--- a/dts/src/arm/bcm2835-rpi-b.dts
+++ b/dts/src/arm/bcm2835-rpi-b.dts
@@ -27,7 +27,6 @@
* RPI00021 sheet 02
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -43,41 +42,40 @@
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
- "NC", /* GPIO12 */
- "NC", /* GPIO13 */
+ "", /* GPIO12 */
+ "", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
- "NC", /* GPIO19 */
- "NC", /* GPIO20 */
- "GPIO21",
+ "", /* GPIO19 */
+ "", /* GPIO20 */
+ "CAM_GPIO0",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
- "NC", /* GPIO26 */
- "CAM_GPIO0",
- /* Binary number representing build/revision */
- "CONFIG0",
- "CONFIG1",
- "CONFIG2",
- "CONFIG3",
- "NC", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO26 */
+ "GPIO27",
+ "GPIO28",
+ "GPIO29",
+ "GPIO30",
+ "GPIO31",
+ "", /* GPIO32 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
+ "", /* GPIO35 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
+ "", /* GPIO38 */
+ "", /* GPIO39 */
"PWM0_OUT",
- "NC", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
+ "", /* GPIO41 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
diff --git a/dts/src/arm/bcm2835-rpi-cm1-io1.dts b/dts/src/arm/bcm2835-rpi-cm1-io1.dts
index a75c882e65..87958a96c3 100644
--- a/dts/src/arm/bcm2835-rpi-cm1-io1.dts
+++ b/dts/src/arm/bcm2835-rpi-cm1-io1.dts
@@ -13,7 +13,6 @@
* This is based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
diff --git a/dts/src/arm/bcm2835-rpi-zero-w.dts b/dts/src/arm/bcm2835-rpi-zero-w.dts
index 243236bc1e..596bb1ef99 100644
--- a/dts/src/arm/bcm2835-rpi-zero-w.dts
+++ b/dts/src/arm/bcm2835-rpi-zero-w.dts
@@ -39,7 +39,6 @@
* This is based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -74,19 +73,21 @@
"GPIO27",
"SDA0",
"SCL0",
- "NC", /* GPIO30 */
- "NC", /* GPIO31 */
- "NC", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
+ /* Used by BT module */
+ "CTS0",
+ "RTS0",
+ "TXD0",
+ "RXD0",
+ /* Used by Wifi */
+ "SD1_CLK",
+ "SD1_CMD",
+ "SD1_DATA0",
+ "SD1_DATA1",
+ "SD1_DATA2",
+ "SD1_DATA3",
"CAM_GPIO1", /* GPIO40 */
"WL_ON", /* GPIO41 */
- "NC", /* GPIO42 */
+ "", /* GPIO42 */
"WIFI_CLK", /* GPIO43 */
"CAM_GPIO0", /* GPIO44 */
"BT_ON", /* GPIO45 */
diff --git a/dts/src/arm/bcm2835-rpi-zero.dts b/dts/src/arm/bcm2835-rpi-zero.dts
index 6f9b3a908f..a65c2bca69 100644
--- a/dts/src/arm/bcm2835-rpi-zero.dts
+++ b/dts/src/arm/bcm2835-rpi-zero.dts
@@ -29,7 +29,6 @@
* This is based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -64,22 +63,22 @@
"GPIO27",
"SDA0",
"SCL0",
- "NC", /* GPIO30 */
- "NC", /* GPIO31 */
+ "", /* GPIO30 */
+ "", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
- "NC", /* GPIO40 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
+ "", /* GPIO35 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
+ "", /* GPIO38 */
+ "", /* GPIO39 */
+ "", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
- "NC", /* GPIO45 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
+ "", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED_N",
/* Used by SD Card */
diff --git a/dts/src/arm/bcm2836-rpi-2-b.dts b/dts/src/arm/bcm2836-rpi-2-b.dts
index d8af8eeac7..3635502b1e 100644
--- a/dts/src/arm/bcm2836-rpi-2-b.dts
+++ b/dts/src/arm/bcm2836-rpi-2-b.dts
@@ -34,7 +34,6 @@
* the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -83,7 +82,7 @@
"CAM_GPIO0",
"SMPS_SCL",
"SMPS_SDA",
- "ETHCLK",
+ "ETH_CLK",
"PWM1_OUT",
"HDMI_HPD_N",
"STATUS_LED",
diff --git a/dts/src/arm/bcm2837-rpi-3-a-plus.dts b/dts/src/arm/bcm2837-rpi-3-a-plus.dts
index d73daf5bff..f7222a2890 100644
--- a/dts/src/arm/bcm2837-rpi-3-a-plus.dts
+++ b/dts/src/arm/bcm2837-rpi-3-a-plus.dts
@@ -55,7 +55,6 @@
* This is mostly based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
diff --git a/dts/src/arm/bcm2837-rpi-3-b-plus.dts b/dts/src/arm/bcm2837-rpi-3-b-plus.dts
index e12938baaf..ec721d323a 100644
--- a/dts/src/arm/bcm2837-rpi-3-b-plus.dts
+++ b/dts/src/arm/bcm2837-rpi-3-b-plus.dts
@@ -45,7 +45,7 @@
#gpio-cells = <2>;
gpio-line-names = "BT_ON",
"WL_ON",
- "STATUS_LED_R",
+ "PWR_LED_R",
"LAN_RUN",
"",
"CAM_GPIO0",
@@ -61,7 +61,6 @@
* the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -110,7 +109,7 @@
"SD1_DATA3",
"PWM0_OUT",
"PWM1_OUT",
- "ETHCLK",
+ "ETH_CLK",
"WIFI_CLK",
"SDA0",
"SCL0",
diff --git a/dts/src/arm/bcm2837-rpi-3-b.dts b/dts/src/arm/bcm2837-rpi-3-b.dts
index 42b5383b55..fb6a417d73 100644
--- a/dts/src/arm/bcm2837-rpi-3-b.dts
+++ b/dts/src/arm/bcm2837-rpi-3-b.dts
@@ -54,7 +54,6 @@
* the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -103,7 +102,7 @@
"SD1_DATA3",
"PWM0_OUT",
"PWM1_OUT",
- "ETHCLK",
+ "ETH_CLK",
"WIFI_CLK",
"SDA0",
"SCL0",
diff --git a/dts/src/arm/bcm2837-rpi-cm3-io3.dts b/dts/src/arm/bcm2837-rpi-cm3-io3.dts
index 588d9411ce..cf84e69fce 100644
--- a/dts/src/arm/bcm2837-rpi-cm3-io3.dts
+++ b/dts/src/arm/bcm2837-rpi-cm3-io3.dts
@@ -13,7 +13,6 @@
* This is based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -63,8 +62,8 @@
"GPIO43",
"GPIO44",
"GPIO45",
- "GPIO46",
- "GPIO47",
+ "SMPS_SCL",
+ "SMPS_SDA",
/* Used by eMMC */
"SD_CLK_R",
"SD_CMD_R",
diff --git a/dts/src/arm/bcm2837-rpi-cm3.dtsi b/dts/src/arm/bcm2837-rpi-cm3.dtsi
index 828a20561b..f57b4ca145 100644
--- a/dts/src/arm/bcm2837-rpi-cm3.dtsi
+++ b/dts/src/arm/bcm2837-rpi-cm3.dtsi
@@ -41,12 +41,12 @@
#gpio-cells = <2>;
gpio-line-names = "HDMI_HPD_N",
"EMMC_EN_N",
- "NC",
- "NC",
- "NC",
- "NC",
- "NC",
- "NC";
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
status = "okay";
};
};
diff --git a/dts/src/arm/bcm283x-rpi-smsc9512.dtsi b/dts/src/arm/bcm283x-rpi-smsc9512.dtsi
index 967e081cb9..882b138070 100644
--- a/dts/src/arm/bcm283x-rpi-smsc9512.dtsi
+++ b/dts/src/arm/bcm283x-rpi-smsc9512.dtsi
@@ -12,7 +12,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
+ ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
diff --git a/dts/src/arm/bcm283x-rpi-smsc9514.dtsi b/dts/src/arm/bcm283x-rpi-smsc9514.dtsi
index dc7ae776db..4273b90b53 100644
--- a/dts/src/arm/bcm283x-rpi-smsc9514.dtsi
+++ b/dts/src/arm/bcm283x-rpi-smsc9514.dtsi
@@ -11,7 +11,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
+ ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
diff --git a/dts/src/arm/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/dts/src/arm/bcm4708-buffalo-wzr-1166dhp-common.dtsi
new file mode 100644
index 0000000000..d659e409a1
--- /dev/null
+++ b/dts/src/arm/bcm4708-buffalo-wzr-1166dhp-common.dtsi
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Buffalo WZR-1166DHP and WZR-1166DHP2
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com>
+ */
+
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ spi {
+ compatible = "spi-gpio";
+ num-chipselects = <1>;
+ gpio-sck = <&chipcommon 7 0>;
+ gpio-mosi = <&chipcommon 4 0>;
+ cs-gpios = <&chipcommon 6 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hc595: gpio_spi@0 {
+ compatible = "fairchild,74hc595";
+ reg = <0>;
+ registers-number = <1>;
+ spi-max-frequency = <100000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ usb {
+ /* label = "bcm53xx:blue:usb"; */
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
+ <&xhci_port1>, <&ohci_port2>,
+ <&ehci_port2>;
+ linux,default-trigger = "usbport";
+ };
+
+ power0 {
+ /* label = "bcm53xx:red:power"; */
+ function = LED_FUNCTION_FAULT;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ power1 {
+ /* label = "bcm53xx:white:power"; */
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ router0 {
+ /* label = "bcm53xx:blue:router"; */
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ router1 {
+ /* label = "bcm53xx:amber:router"; */
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ wan {
+ /* label = "bcm53xx:blue:wan"; */
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ wireless0 {
+ /* label = "bcm53xx:blue:wireless"; */
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ wireless1 {
+ /* label = "bcm53xx:amber:wireless"; */
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ };
+
+ aoss {
+ label = "AOSS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
+ };
+
+ /* Commit mode set by switch? */
+ mode {
+ label = "Mode";
+ linux,code = <KEY_SETUP>;
+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+ };
+
+ /* Switch: AP mode */
+ sw_ap {
+ label = "AP";
+ linux,code = <BTN_0>;
+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+ };
+
+ eject {
+ label = "USB eject";
+ linux,code = <KEY_EJECTCD>;
+ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&usb2 {
+ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+};
+
+&spi_nor {
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/dts/src/arm/bcm4708-buffalo-wzr-1166dhp.dts b/dts/src/arm/bcm4708-buffalo-wzr-1166dhp.dts
new file mode 100644
index 0000000000..8e506269fa
--- /dev/null
+++ b/dts/src/arm/bcm4708-buffalo-wzr-1166dhp.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindigs for Buffalo WZR-1166DHP
+ *
+ * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi"
+
+/ {
+ compatible = "buffalo,wzr-1166dhp", "brcm,bcm4708";
+ model = "Buffalo WZR-1166DHP";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
+ };
+
+};
diff --git a/dts/src/arm/bcm4708-buffalo-wzr-1166dhp2.dts b/dts/src/arm/bcm4708-buffalo-wzr-1166dhp2.dts
new file mode 100644
index 0000000000..5961290270
--- /dev/null
+++ b/dts/src/arm/bcm4708-buffalo-wzr-1166dhp2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindigs for Buffalo WZR-1166DHP2
+ *
+ * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi"
+
+/ {
+ compatible = "buffalo,wzr-1166dhp2", "brcm,bcm4708";
+ model = "Buffalo WZR-1166DHP2";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
+ };
+
+};
diff --git a/dts/src/arm/bcm47094-asus-rt-ac88u.dts b/dts/src/arm/bcm47094-asus-rt-ac88u.dts
index 82f9629f0a..d850375834 100644
--- a/dts/src/arm/bcm47094-asus-rt-ac88u.dts
+++ b/dts/src/arm/bcm47094-asus-rt-ac88u.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright (C) 2021 Arınç ÜNAL <arinc.unal@arinc9.com>
+ * Copyright (C) 2021-2022 Arınç ÜNAL <arinc.unal@arinc9.com>
*/
/dts-v1/;
@@ -25,6 +25,9 @@
nvram@1c080000 {
compatible = "brcm,nvram";
reg = <0x1c080000 0x00180000>;
+
+ et1macaddr: et1macaddr {
+ };
};
leds {
@@ -177,9 +180,6 @@
dsa,member = <0 0>;
ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
port@0 {
reg = <0>;
label = "lan4";
@@ -208,6 +208,7 @@
sw0_p5: port@5 {
reg = <5>;
label = "extsw";
+ phy-mode = "rgmii";
fixed-link {
speed = <1000>;
@@ -231,7 +232,6 @@
reg = <8>;
ethernet = <&gmac2>;
label = "cpu";
- status = "disabled";
fixed-link {
speed = <1000>;
@@ -241,6 +241,15 @@
};
};
+&gmac0 {
+ status = "disabled";
+};
+
+&gmac1 {
+ nvmem-cells = <&et1macaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
&usb2 {
vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/src/arm/bcm47622.dtsi b/dts/src/arm/bcm47622.dtsi
new file mode 100644
index 0000000000..c016e12b73
--- /dev/null
+++ b/dts/src/arm/bcm47622.dtsi
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm47622", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+ CA7_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>,
+ <&CA7_2>, <&CA7_3>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ cpu_off = <1>;
+ cpu_on = <2>;
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x818000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/dts/src/arm/bcm53016-meraki-mr32.dts b/dts/src/arm/bcm53016-meraki-mr32.dts
index 66c64a6ec4..daca63f251 100644
--- a/dts/src/arm/bcm53016-meraki-mr32.dts
+++ b/dts/src/arm/bcm53016-meraki-mr32.dts
@@ -13,7 +13,7 @@
#include <dt-bindings/leds/common.h>
/ {
- compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708";
+ compatible = "meraki,mr32", "brcm,bcm53016", "brcm,bcm4708";
model = "Meraki MR32";
chosen {
diff --git a/dts/src/arm/bcm5301x.dtsi b/dts/src/arm/bcm5301x.dtsi
index 603c700c70..65f8a759f1 100644
--- a/dts/src/arm/bcm5301x.dtsi
+++ b/dts/src/arm/bcm5301x.dtsi
@@ -455,7 +455,7 @@
reg = <0x180 0x4>;
};
- pinctrl: pin-controller@1c0 {
+ pinctrl: pinctrl@1c0 {
compatible = "brcm,bcm4708-pinmux";
reg = <0x1c0 0x24>;
reg-names = "cru_gpio_control";
diff --git a/dts/src/arm/bcm53340-ubnt-unifi-switch8.dts b/dts/src/arm/bcm53340-ubnt-unifi-switch8.dts
index 2e7fda9b99..975f854f65 100644
--- a/dts/src/arm/bcm53340-ubnt-unifi-switch8.dts
+++ b/dts/src/arm/bcm53340-ubnt-unifi-switch8.dts
@@ -34,7 +34,7 @@
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "m25p80";
reg = <0>;
#address-cells = <1>;
diff --git a/dts/src/arm/bcm947622.dts b/dts/src/arm/bcm947622.dts
new file mode 100644
index 0000000000..6f083724ab
--- /dev/null
+++ b/dts/src/arm/bcm947622.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm47622.dtsi"
+
+/ {
+ model = "Broadcom BCM947622 Reference Board";
+ compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm953012er.dts b/dts/src/arm/bcm953012er.dts
index 52feca0fb9..dd63a148a1 100644
--- a/dts/src/arm/bcm953012er.dts
+++ b/dts/src/arm/bcm953012er.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar Enterprise Router (BCM953012ER)";
- compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708";
+ compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708";
memory@0 {
device_type = "memory";
diff --git a/dts/src/arm/bcm953012hr.dts b/dts/src/arm/bcm953012hr.dts
index 9140be7ec0..b070b69466 100644
--- a/dts/src/arm/bcm953012hr.dts
+++ b/dts/src/arm/bcm953012hr.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar HR (BCM953012HR)";
- compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708";
+ compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708";
aliases {
ethernet0 = &gmac0;
diff --git a/dts/src/arm/bcm953012k.dts b/dts/src/arm/bcm953012k.dts
index de40bd59a5..f1e6bcaa1e 100644
--- a/dts/src/arm/bcm953012k.dts
+++ b/dts/src/arm/bcm953012k.dts
@@ -36,7 +36,7 @@
/ {
model = "NorthStar SVK (BCM953012K)";
- compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708";
+ compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708";
aliases {
serial0 = &uart0;
diff --git a/dts/src/arm/bcm958522er.dts b/dts/src/arm/bcm958522er.dts
index 60376b62cd..15f023656d 100644
--- a/dts/src/arm/bcm958522er.dts
+++ b/dts/src/arm/bcm958522er.dts
@@ -136,7 +136,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/dts/src/arm/bcm958525er.dts b/dts/src/arm/bcm958525er.dts
index 8eeb319f5b..9b9c225a1f 100644
--- a/dts/src/arm/bcm958525er.dts
+++ b/dts/src/arm/bcm958525er.dts
@@ -136,7 +136,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/dts/src/arm/bcm958525xmc.dts b/dts/src/arm/bcm958525xmc.dts
index dc86d5a912..ca93114527 100644
--- a/dts/src/arm/bcm958525xmc.dts
+++ b/dts/src/arm/bcm958525xmc.dts
@@ -152,7 +152,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/dts/src/arm/bcm958622hr.dts b/dts/src/arm/bcm958622hr.dts
index c457e53d88..9db3c85145 100644
--- a/dts/src/arm/bcm958622hr.dts
+++ b/dts/src/arm/bcm958622hr.dts
@@ -140,7 +140,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/dts/src/arm/bcm958623hr.dts b/dts/src/arm/bcm958623hr.dts
index c06871915a..32786e7c4e 100644
--- a/dts/src/arm/bcm958623hr.dts
+++ b/dts/src/arm/bcm958623hr.dts
@@ -144,7 +144,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/dts/src/arm/bcm958625hr.dts b/dts/src/arm/bcm958625hr.dts
index b22fc6624a..74263d98de 100644
--- a/dts/src/arm/bcm958625hr.dts
+++ b/dts/src/arm/bcm958625hr.dts
@@ -151,7 +151,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/dts/src/arm/bcm958625k.dts b/dts/src/arm/bcm958625k.dts
index 0183f8965a..69ebc7a913 100644
--- a/dts/src/arm/bcm958625k.dts
+++ b/dts/src/arm/bcm958625k.dts
@@ -155,7 +155,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/dts/src/arm/bcm988312hr.dts b/dts/src/arm/bcm988312hr.dts
index 007e347159..e96bc3f2d5 100644
--- a/dts/src/arm/bcm988312hr.dts
+++ b/dts/src/arm/bcm988312hr.dts
@@ -140,7 +140,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/dts/src/arm/da850.dtsi b/dts/src/arm/da850.dtsi
index c3942b4e82..0386376fa4 100644
--- a/dts/src/arm/da850.dtsi
+++ b/dts/src/arm/da850.dtsi
@@ -679,7 +679,9 @@
"scheduler", "queuemgr";
interrupts = <58>;
#dma-cells = <2>;
+ /* For backwards compatibility: */
#dma-channels = <4>;
+ dma-channels = <4>;
power-domains = <&psc1 1>;
status = "okay";
};
diff --git a/dts/src/arm/dm814x.dtsi b/dts/src/arm/dm814x.dtsi
index 7702e048e1..a92630113f 100644
--- a/dts/src/arm/dm814x.dtsi
+++ b/dts/src/arm/dm814x.dtsi
@@ -167,8 +167,11 @@
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
+ /* For backwards compatibility: */
#dma-channels = <30>;
+ dma-channels = <30>;
#dma-requests = <256>;
+ dma-requests = <256>;
};
};
diff --git a/dts/src/arm/dm816x.dtsi b/dts/src/arm/dm816x.dtsi
index a9e7274806..eb0a95da94 100644
--- a/dts/src/arm/dm816x.dtsi
+++ b/dts/src/arm/dm816x.dtsi
@@ -655,8 +655,11 @@
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
+ /* For backwards compatibility: */
#dma-channels = <30>;
+ dma-channels = <30>;
#dma-requests = <256>;
+ dma-requests = <256>;
};
};
diff --git a/dts/src/arm/dove-cubox.dts b/dts/src/arm/dove-cubox.dts
index 3e1584e787..2639b9fe0a 100644
--- a/dts/src/arm/dove-cubox.dts
+++ b/dts/src/arm/dove-cubox.dts
@@ -127,7 +127,7 @@
status = "okay";
/* spi0.0: 4M Flash Winbond W25Q32BV */
- spi-flash@0 {
+ flash@0 {
compatible = "st,w25q32";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/dove-d2plug.dts b/dts/src/arm/dove-d2plug.dts
index 273f12ca25..a0e8996c2f 100644
--- a/dts/src/arm/dove-d2plug.dts
+++ b/dts/src/arm/dove-d2plug.dts
@@ -62,7 +62,7 @@
status = "okay";
/* spi0.0: 4M Flash Macronix MX25L3205D */
- spi-flash@0 {
+ flash@0 {
compatible = "st,m25l3205d";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/dove-d3plug.dts b/dts/src/arm/dove-d3plug.dts
index 826026c28f..1e81d1b970 100644
--- a/dts/src/arm/dove-d3plug.dts
+++ b/dts/src/arm/dove-d3plug.dts
@@ -79,7 +79,7 @@
status = "okay";
/* spi0.0: 2M Flash Macronix MX25L1605D */
- spi-flash@0 {
+ flash@0 {
compatible = "st,m25l1605d";
spi-max-frequency = <86000000>;
reg = <0>;
diff --git a/dts/src/arm/dove-dove-db.dts b/dts/src/arm/dove-dove-db.dts
index 1754a62e01..c1912dc6bf 100644
--- a/dts/src/arm/dove-dove-db.dts
+++ b/dts/src/arm/dove-dove-db.dts
@@ -27,7 +27,7 @@
status = "okay";
/* spi0.0: 4M Flash ST-M25P32-VMF6P */
- spi-flash@0 {
+ flash@0 {
compatible = "st,m25p32";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/dra7-evm-common.dtsi b/dts/src/arm/dra7-evm-common.dtsi
index 0f71a9f37a..68c43eb12c 100644
--- a/dts/src/arm/dra7-evm-common.dtsi
+++ b/dts/src/arm/dra7-evm-common.dtsi
@@ -135,7 +135,7 @@
status = "okay";
spi-max-frequency = <76800000>;
- m25p80@0 {
+ flash@0 {
compatible = "s25fl256s1";
spi-max-frequency = <76800000>;
reg = <0>;
diff --git a/dts/src/arm/dra72-evm-common.dtsi b/dts/src/arm/dra72-evm-common.dtsi
index f128252681..8948e10dbe 100644
--- a/dts/src/arm/dra72-evm-common.dtsi
+++ b/dts/src/arm/dra72-evm-common.dtsi
@@ -474,7 +474,7 @@
status = "okay";
spi-max-frequency = <76800000>;
- m25p80@0 {
+ flash@0 {
compatible = "s25fl256s1";
spi-max-frequency = <76800000>;
reg = <0>;
diff --git a/dts/src/arm/dra76-evm.dts b/dts/src/arm/dra76-evm.dts
index e2b7fcb061..57868ac60d 100644
--- a/dts/src/arm/dra76-evm.dts
+++ b/dts/src/arm/dra76-evm.dts
@@ -511,7 +511,7 @@
&qspi {
spi-max-frequency = <96000000>;
- m25p80@0 {
+ flash@0 {
spi-max-frequency = <96000000>;
};
};
diff --git a/dts/src/arm/dra7xx-clocks.dtsi b/dts/src/arm/dra7xx-clocks.dtsi
index 2365554eef..04a7a6d1d5 100644
--- a/dts/src/arm/dra7xx-clocks.dtsi
+++ b/dts/src/arm/dra7xx-clocks.dtsi
@@ -5,210 +5,244 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&cm_core_aon_clocks {
- atl_clkin0_ck: atl_clkin0_ck {
+ atl_clkin0_ck: clock-atl-clkin0 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin0_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- atl_clkin1_ck: atl_clkin1_ck {
+ atl_clkin1_ck: clock-atl-clkin1 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin1_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- atl_clkin2_ck: atl_clkin2_ck {
+ atl_clkin2_ck: clock-atl-clkin2 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin2_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- atl_clkin3_ck: atl_clkin3_ck {
+ atl_clkin3_ck: clock-atl-clkin3 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin3_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- hdmi_clkin_ck: hdmi_clkin_ck {
+ hdmi_clkin_ck: clock-hdmi-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "hdmi_clkin_ck";
clock-frequency = <0>;
};
- mlb_clkin_ck: mlb_clkin_ck {
+ mlb_clkin_ck: clock-mlb-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "mlb_clkin_ck";
clock-frequency = <0>;
};
- mlbp_clkin_ck: mlbp_clkin_ck {
+ mlbp_clkin_ck: clock-mlbp-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "mlbp_clkin_ck";
clock-frequency = <0>;
};
- pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+ pciesref_acs_clk_ck: clock-pciesref-acs {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pciesref_acs_clk_ck";
clock-frequency = <100000000>;
};
- ref_clkin0_ck: ref_clkin0_ck {
+ ref_clkin0_ck: clock-ref-clkin0 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin0_ck";
clock-frequency = <0>;
};
- ref_clkin1_ck: ref_clkin1_ck {
+ ref_clkin1_ck: clock-ref-clkin1 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin1_ck";
clock-frequency = <0>;
};
- ref_clkin2_ck: ref_clkin2_ck {
+ ref_clkin2_ck: clock-ref-clkin2 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin2_ck";
clock-frequency = <0>;
};
- ref_clkin3_ck: ref_clkin3_ck {
+ ref_clkin3_ck: clock-ref-clkin3 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin3_ck";
clock-frequency = <0>;
};
- rmii_clk_ck: rmii_clk_ck {
+ rmii_clk_ck: clock-rmii {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "rmii_clk_ck";
clock-frequency = <0>;
};
- sdvenc_clkin_ck: sdvenc_clkin_ck {
+ sdvenc_clkin_ck: clock-sdvenc-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sdvenc_clkin_ck";
clock-frequency = <0>;
};
- secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ secure_32k_clk_src_ck: clock-secure-32k-clk-src {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "secure_32k_clk_src_ck";
clock-frequency = <32768>;
};
- sys_clk32_crystal_ck: sys_clk32_crystal_ck {
+ sys_clk32_crystal_ck: clock-sys-clk32-crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_clk32_crystal_ck";
clock-frequency = <32768>;
};
- sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+ sys_clk32_pseudo_ck: clock-sys-clk32-pseudo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sys_clk32_pseudo_ck";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <610>;
};
- virt_12000000_ck: virt_12000000_ck {
+ virt_12000000_ck: clock-virt-12000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_12000000_ck";
clock-frequency = <12000000>;
};
- virt_13000000_ck: virt_13000000_ck {
+ virt_13000000_ck: clock-virt-13000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_13000000_ck";
clock-frequency = <13000000>;
};
- virt_16800000_ck: virt_16800000_ck {
+ virt_16800000_ck: clock-virt-16800000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_16800000_ck";
clock-frequency = <16800000>;
};
- virt_19200000_ck: virt_19200000_ck {
+ virt_19200000_ck: clock-virt-19200000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
- virt_20000000_ck: virt_20000000_ck {
+ virt_20000000_ck: clock-virt-20000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_20000000_ck";
clock-frequency = <20000000>;
};
- virt_26000000_ck: virt_26000000_ck {
+ virt_26000000_ck: clock-virt-26000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
- virt_27000000_ck: virt_27000000_ck {
+ virt_27000000_ck: clock-virt-27000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_27000000_ck";
clock-frequency = <27000000>;
};
- virt_38400000_ck: virt_38400000_ck {
+ virt_38400000_ck: clock-virt-38400000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_38400000_ck";
clock-frequency = <38400000>;
};
- sys_clkin2: sys_clkin2 {
+ sys_clkin2: clock-sys-clkin2 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_clkin2";
clock-frequency = <22579200>;
};
- usb_otg_clkin_ck: usb_otg_clkin_ck {
+ usb_otg_clkin_ck: clock-usb-otg-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "usb_otg_clkin_ck";
clock-frequency = <0>;
};
- video1_clkin_ck: video1_clkin_ck {
+ video1_clkin_ck: clock-video1-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video1_clkin_ck";
clock-frequency = <0>;
};
- video1_m2_clkin_ck: video1_m2_clkin_ck {
+ video1_m2_clkin_ck: clock-video1-m2-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video1_m2_clkin_ck";
clock-frequency = <0>;
};
- video2_clkin_ck: video2_clkin_ck {
+ video2_clkin_ck: clock-video2-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video2_clkin_ck";
clock-frequency = <0>;
};
- video2_m2_clkin_ck: video2_m2_clkin_ck {
+ video2_m2_clkin_ck: clock-video2-m2-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video2_m2_clkin_ck";
clock-frequency = <0>;
};
- dpll_abe_ck: dpll_abe_ck@1e0 {
+ dpll_abe_ck: clock@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
+ clock-output-names = "dpll_abe_ck";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
- dpll_abe_x2_ck: dpll_abe_x2_ck {
+ dpll_abe_x2_ck: clock-dpll-abe-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_abe_x2_ck";
clocks = <&dpll_abe_ck>;
};
- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
+ dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -217,18 +251,20 @@
ti,invert-autoidle-bit;
};
- abe_clk: abe_clk@108 {
+ abe_clk: clock-abe@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_clk";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
ti,index-power-of-two;
};
- dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
+ dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2_ck";
clocks = <&dpll_abe_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -237,9 +273,10 @@
ti,invert-autoidle-bit;
};
- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
+ dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m3x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -248,30 +285,34 @@
ti,invert-autoidle-bit;
};
- dpll_core_byp_mux: dpll_core_byp_mux@12c {
+ dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_core_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
};
- dpll_core_ck: dpll_core_ck@120 {
+ dpll_core_ck: clock@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
- dpll_core_x2_ck: dpll_core_x2_ck {
+ dpll_core_x2_ck: clock-dpll-core-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
- dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
+ dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h12x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -280,24 +321,27 @@
ti,invert-autoidle-bit;
};
- mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_mpu_ck: dpll_mpu_ck@160 {
+ dpll_mpu_ck: clock@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
+ dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -306,42 +350,47 @@
ti,invert-autoidle-bit;
};
- mpu_dclk_div: mpu_dclk_div {
+ mpu_dclk_div: clock-mpu-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_dclk_div";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+ dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dsp_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
+ dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_dsp_byp_mux";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0240>;
};
- dpll_dsp_ck: dpll_dsp_ck@234 {
+ dpll_dsp_ck: clock@234 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_dsp_ck";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
assigned-clocks = <&dpll_dsp_ck>;
assigned-clock-rates = <600000000>;
};
- dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
+ dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_dsp_m2_ck";
clocks = <&dpll_dsp_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -352,34 +401,38 @@
assigned-clock-rates = <600000000>;
};
- iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "iva_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
+ dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_iva_byp_mux";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
};
- dpll_iva_ck: dpll_iva_ck@1a0 {
+ dpll_iva_ck: clock@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_iva_ck";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
assigned-clock-rates = <1165000000>;
};
- dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
+ dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_m2_ck";
clocks = <&dpll_iva_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -390,34 +443,38 @@
assigned-clock-rates = <388333334>;
};
- iva_dclk: iva_dclk {
+ iva_dclk: clock-iva-dclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "iva_dclk";
clocks = <&dpll_iva_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
+ dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_gpu_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02e4>;
};
- dpll_gpu_ck: dpll_gpu_ck@2d8 {
+ dpll_gpu_ck: clock@2d8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_gpu_ck";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
assigned-clocks = <&dpll_gpu_ck>;
assigned-clock-rates = <1277000000>;
};
- dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
+ dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gpu_m2_ck";
clocks = <&dpll_gpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -428,9 +485,10 @@
assigned-clock-rates = <425666667>;
};
- dpll_core_m2_ck: dpll_core_m2_ck@130 {
+ dpll_core_m2_ck: clock-dpll-core-m2-8@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m2_ck";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -439,32 +497,36 @@
ti,invert-autoidle-bit;
};
- core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+ core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "core_dpll_out_dclk_div";
clocks = <&dpll_core_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
+ dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_ddr_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x021c>;
};
- dpll_ddr_ck: dpll_ddr_ck@210 {
+ dpll_ddr_ck: clock@210 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_ddr_ck";
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
+ dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -473,24 +535,27 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
+ dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_gmac_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02b4>;
};
- dpll_gmac_ck: dpll_gmac_ck@2a8 {
+ dpll_gmac_ck: clock@2a8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_gmac_ck";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
- dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
+ dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_m2_ck";
clocks = <&dpll_gmac_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -499,72 +564,81 @@
ti,invert-autoidle-bit;
};
- video2_dclk_div: video2_dclk_div {
+ video2_dclk_div: clock-video2-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video2_dclk_div";
clocks = <&video2_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video1_dclk_div: video1_dclk_div {
+ video1_dclk_div: clock-video1-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video1_dclk_div";
clocks = <&video1_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- hdmi_dclk_div: hdmi_dclk_div {
+ hdmi_dclk_div: clock-hdmi-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "hdmi_dclk_div";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "usb_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
};
- eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+ eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "eve_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
+ dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_eve_byp_mux";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0290>;
};
- dpll_eve_ck: dpll_eve_ck@284 {
+ dpll_eve_ck: clock@284 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_eve_ck";
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
- dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
+ dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_eve_m2_ck";
clocks = <&dpll_eve_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -573,17 +647,19 @@
ti,invert-autoidle-bit;
};
- eve_dclk_div: eve_dclk_div {
+ eve_dclk_div: clock-eve-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "eve_dclk_div";
clocks = <&dpll_eve_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
+ dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h13x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -592,9 +668,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
+ dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h14x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -603,9 +680,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
+ dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h22x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -614,9 +692,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
+ dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h23x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -625,9 +704,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
+ dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h24x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -636,15 +716,17 @@
ti,invert-autoidle-bit;
};
- dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_ddr_x2_ck";
clocks = <&dpll_ddr_ck>;
};
- dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
+ dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_h11x2_ck";
clocks = <&dpll_ddr_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -653,15 +735,17 @@
ti,invert-autoidle-bit;
};
- dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+ dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_dsp_x2_ck";
clocks = <&dpll_dsp_ck>;
};
- dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
+ dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_dsp_m3x2_ck";
clocks = <&dpll_dsp_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -672,15 +756,17 @@
assigned-clock-rates = <400000000>;
};
- dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+ dpll_gmac_x2_ck: clock-dpll-gmac-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_gmac_x2_ck";
clocks = <&dpll_gmac_ck>;
};
- dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
+ dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_h11x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -689,9 +775,10 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
+ dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_h12x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -700,9 +787,10 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
+ dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_h13x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -711,9 +799,10 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
+ dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_m3x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -722,33 +811,37 @@
ti,invert-autoidle-bit;
};
- gmii_m_clk_div: gmii_m_clk_div {
+ gmii_m_clk_div: clock-gmii-m-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "gmii_m_clk_div";
clocks = <&dpll_gmac_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- hdmi_clk2_div: hdmi_clk2_div {
+ hdmi_clk2_div: clock-hdmi-clk2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "hdmi_clk2_div";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- hdmi_div_clk: hdmi_div_clk {
+ hdmi_div_clk: clock-hdmi-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "hdmi_div_clk";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l3_iclk_div: l3_iclk_div@100 {
+ l3_iclk_div: clock-l3-iclk-div-4@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3_iclk_div";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x0100>;
@@ -756,374 +849,420 @@
ti,index-power-of-two;
};
- l4_root_clk_div: l4_root_clk_div {
+ l4_root_clk_div: clock-l4-root-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4_root_clk_div";
clocks = <&l3_iclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
- video1_clk2_div: video1_clk2_div {
+ video1_clk2_div: clock-video1-clk2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video1_clk2_div";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video1_div_clk: video1_div_clk {
+ video1_div_clk: clock-video1-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video1_div_clk";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video2_clk2_div: video2_clk2_div {
+ video2_clk2_div: clock-video2-clk2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video2_clk2_div";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video2_div_clk: video2_div_clk {
+ video2_div_clk: clock-video2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video2_div_clk";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dummy_ck: dummy_ck {
+ dummy_ck: clock-dummy {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "dummy_ck";
clock-frequency = <0>;
};
};
&prm_clocks {
- sys_clkin1: sys_clkin1@110 {
+ sys_clkin1: clock-sys-clkin1@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin1";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
};
- abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
+ abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_sys_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0118>;
};
- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
+ abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_bypass_clk_mux";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x0114>;
};
- abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
+ abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_clk_mux";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x010c>;
};
- abe_24m_fclk: abe_24m_fclk@11c {
+ abe_24m_fclk: clock-abe-24m@11c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_24m_fclk";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x011c>;
ti,dividers = <8>, <16>;
};
- aess_fclk: aess_fclk@178 {
+ aess_fclk: clock-aess@178 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "aess_fclk";
clocks = <&abe_clk>;
reg = <0x0178>;
ti,max-div = <2>;
};
- abe_giclk_div: abe_giclk_div@174 {
+ abe_giclk_div: clock-abe-giclk-div@174 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_giclk_div";
clocks = <&aess_fclk>;
reg = <0x0174>;
ti,max-div = <2>;
};
- abe_lp_clk_div: abe_lp_clk_div@1d8 {
+ abe_lp_clk_div: clock-abe-lp-clk-div@1d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_lp_clk_div";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x01d8>;
ti,dividers = <16>, <32>;
};
- abe_sys_clk_div: abe_sys_clk_div@120 {
+ abe_sys_clk_div: clock-abe-sys-clk-div@120 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_sys_clk_div";
clocks = <&sys_clkin1>;
reg = <0x0120>;
ti,max-div = <2>;
};
- adc_gfclk_mux: adc_gfclk_mux@1dc {
+ adc_gfclk_mux: clock-adc-gfclk-mux@1dc {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "adc_gfclk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
reg = <0x01dc>;
};
- sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
+ sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "sys_clk1_dclk_div";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c8>;
ti,index-power-of-two;
};
- sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
+ sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "sys_clk2_dclk_div";
clocks = <&sys_clkin2>;
ti,max-div = <64>;
reg = <0x01cc>;
ti,index-power-of-two;
};
- per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
+ per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "per_abe_x1_dclk_div";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x01bc>;
ti,index-power-of-two;
};
- dsp_gclk_div: dsp_gclk_div@18c {
+ dsp_gclk_div: clock-dsp-gclk-div@18c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dsp_gclk_div";
clocks = <&dpll_dsp_m2_ck>;
ti,max-div = <64>;
reg = <0x018c>;
ti,index-power-of-two;
};
- gpu_dclk: gpu_dclk@1a0 {
+ gpu_dclk: clock-gpu-dclk@1a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "gpu_dclk";
clocks = <&dpll_gpu_m2_ck>;
ti,max-div = <64>;
reg = <0x01a0>;
ti,index-power-of-two;
};
- emif_phy_dclk_div: emif_phy_dclk_div@190 {
+ emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "emif_phy_dclk_div";
clocks = <&dpll_ddr_m2_ck>;
ti,max-div = <64>;
reg = <0x0190>;
ti,index-power-of-two;
};
- gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
+ gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "gmac_250m_dclk_div";
clocks = <&dpll_gmac_m2_ck>;
ti,max-div = <64>;
reg = <0x019c>;
ti,index-power-of-two;
};
- gmac_main_clk: gmac_main_clk {
+ gmac_main_clk: clock-gmac-main {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "gmac_main_clk";
clocks = <&gmac_250m_dclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
- l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
+ l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3init_480m_dclk_div";
clocks = <&dpll_usb_m2_ck>;
ti,max-div = <64>;
reg = <0x01ac>;
ti,index-power-of-two;
};
- usb_otg_dclk_div: usb_otg_dclk_div@184 {
+ usb_otg_dclk_div: clock-usb-otg-dclk-div@184 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "usb_otg_dclk_div";
clocks = <&usb_otg_clkin_ck>;
ti,max-div = <64>;
reg = <0x0184>;
ti,index-power-of-two;
};
- sata_dclk_div: sata_dclk_div@1c0 {
+ sata_dclk_div: clock-sata-dclk-div@1c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "sata_dclk_div";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c0>;
ti,index-power-of-two;
};
- pcie2_dclk_div: pcie2_dclk_div@1b8 {
+ pcie2_dclk_div: clock-pcie2-dclk-div@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "pcie2_dclk_div";
clocks = <&dpll_pcie_ref_m2_ck>;
ti,max-div = <64>;
reg = <0x01b8>;
ti,index-power-of-two;
};
- pcie_dclk_div: pcie_dclk_div@1b4 {
+ pcie_dclk_div: clock-pcie-dclk-div@1b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "pcie_dclk_div";
clocks = <&apll_pcie_m2_ck>;
ti,max-div = <64>;
reg = <0x01b4>;
ti,index-power-of-two;
};
- emu_dclk_div: emu_dclk_div@194 {
+ emu_dclk_div: clock-emu-dclk-div@194 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "emu_dclk_div";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x0194>;
ti,index-power-of-two;
};
- secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
+ secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "secure_32k_dclk_div";
clocks = <&secure_32k_clk_src_ck>;
ti,max-div = <64>;
reg = <0x01c4>;
ti,index-power-of-two;
};
- clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
+ clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkoutmux0_clk_mux";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0158>;
};
- clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
+ clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkoutmux1_clk_mux";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x015c>;
};
- clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
+ clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkoutmux2_clk_mux";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0160>;
};
- custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "custefuse_sys_gfclk_div";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <2>;
};
- eve_clk: eve_clk@180 {
+ eve_clk: clock-eve@180 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "eve_clk";
clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
reg = <0x0180>;
};
- hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
+ hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "hdmi_dpll_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0164>;
};
- mlb_clk: mlb_clk@134 {
+ mlb_clk: clock-mlb@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "mlb_clk";
clocks = <&mlb_clkin_ck>;
ti,max-div = <64>;
reg = <0x0134>;
ti,index-power-of-two;
};
- mlbp_clk: mlbp_clk@130 {
+ mlbp_clk: clock-mlbp@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "mlbp_clk";
clocks = <&mlbp_clkin_ck>;
ti,max-div = <64>;
reg = <0x0130>;
ti,index-power-of-two;
};
- per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
+ per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "per_abe_x1_gfclk2_div";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x0138>;
ti,index-power-of-two;
};
- timer_sys_clk_div: timer_sys_clk_div@144 {
+ timer_sys_clk_div: clock-timer-sys-clk-div@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "timer_sys_clk_div";
clocks = <&sys_clkin1>;
reg = <0x0144>;
ti,max-div = <2>;
};
- video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
+ video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "video1_dpll_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0168>;
};
- video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
+ video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "video2_dpll_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x016c>;
};
- wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
+ wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wkupaon_iclk_mux";
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
};
&cm_core_clocks {
- dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
+ dpll_pcie_ref_ck: clock@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_pcie_ref_ck";
clocks = <&sys_clkin1>, <&sys_clkin1>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
- dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
+ dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_pcie_ref_m2ldo_ck";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -1132,23 +1271,26 @@
ti,invert-autoidle-bit;
};
- apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+ apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
compatible = "ti,mux-clock";
+ clock-output-names = "apll_pcie_in_clk_mux";
clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
};
- apll_pcie_ck: apll_pcie_ck@21c {
+ apll_pcie_ck: clock@21c {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
+ clock-output-names = "apll_pcie_ck";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x021c>, <0x0220>;
};
- optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+ optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
compatible = "ti,divider-clock";
+ clock-output-names = "optfclk_pciephy_div";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x021c>;
@@ -1157,48 +1299,54 @@
ti,max-div = <2>;
};
- apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+ apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "apll_pcie_clkvcoldo";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+ apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "apll_pcie_clkvcoldo_div";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- apll_pcie_m2_ck: apll_pcie_m2_ck {
+ apll_pcie_m2_ck: clock-apll-pcie-m2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "apll_pcie_m2_ck";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_per_byp_mux: dpll_per_byp_mux@14c {
+ dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_per_byp_mux";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
};
- dpll_per_ck: dpll_per_ck@140 {
+ dpll_per_ck: clock@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
- dpll_per_m2_ck: dpll_per_m2_ck@150 {
+ dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -1207,32 +1355,36 @@
ti,invert-autoidle-bit;
};
- func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+ func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_96m_aon_dclk_div";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
+ dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_usb_byp_mux";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
};
- dpll_usb_ck: dpll_usb_ck@180 {
+ dpll_usb_ck: clock@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
+ clock-output-names = "dpll_usb_ck";
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
- dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
+ dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_usb_m2_ck";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -1241,9 +1393,10 @@
ti,invert-autoidle-bit;
};
- dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
+ dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_pcie_ref_m2_ck";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -1252,15 +1405,17 @@
ti,invert-autoidle-bit;
};
- dpll_per_x2_ck: dpll_per_x2_ck {
+ dpll_per_x2_ck: clock-dpll-per-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
clocks = <&dpll_per_ck>;
};
- dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
+ dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h11x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1269,9 +1424,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
+ dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h12x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1280,9 +1436,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
+ dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h13x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1291,9 +1448,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
+ dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h14x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1302,9 +1460,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
+ dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -1313,105 +1472,118 @@
ti,invert-autoidle-bit;
};
- dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_usb_clkdcoldo";
clocks = <&dpll_usb_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- func_128m_clk: func_128m_clk {
+ func_128m_clk: clock-func-128m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_128m_clk";
clocks = <&dpll_per_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- func_12m_fclk: func_12m_fclk {
+ func_12m_fclk: clock-func-12m-fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
- func_24m_clk: func_24m_clk {
+ func_24m_clk: clock-func-24m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- func_48m_fclk: func_48m_fclk {
+ func_48m_fclk: clock-func-48m-fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_48m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- func_96m_fclk: func_96m_fclk {
+ func_96m_fclk: clock-func-96m-fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_96m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- l3init_60m_fclk: l3init_60m_fclk@104 {
+ l3init_60m_fclk: clock-l3init-60m@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3init_60m_fclk";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
};
- clkout2_clk: clkout2_clk@6b0 {
+ clkout2_clk: clock-clkout2-8@6b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "clkout2_clk";
clocks = <&clkoutmux2_clk_mux>;
ti,bit-shift = <8>;
reg = <0x06b0>;
};
- l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
+ l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "l3init_960m_gfclk";
clocks = <&dpll_usb_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x06c0>;
};
- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
+ usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy1_always_on_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
};
- usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
+ usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy2_always_on_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0688>;
};
- usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
+ usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy3_always_on_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0698>;
};
- gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
+ gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_core_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <24>;
reg = <0x1220>;
@@ -1419,9 +1591,10 @@
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
+ gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_hyd_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <26>;
reg = <0x1220>;
@@ -1429,34 +1602,38 @@
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
- l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
+ l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3instr_ts_gclk_div";
clocks = <&wkupaon_iclk_mux>;
ti,bit-shift = <24>;
reg = <0x0e50>;
ti,dividers = <8>, <16>, <32>;
};
- vip1_gclk_mux: vip1_gclk_mux@1020 {
+ vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "vip1_gclk_mux";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1020>;
};
- vip2_gclk_mux: vip2_gclk_mux@1028 {
+ vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "vip2_gclk_mux";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1028>;
};
- vip3_gclk_mux: vip3_gclk_mux@1030 {
+ vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "vip3_gclk_mux";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1030>;
@@ -1464,48 +1641,54 @@
};
&cm_core_clockdomains {
- coreaon_clkdm: coreaon_clkdm {
+ coreaon_clkdm: clock-coreaon-clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "coreaon_clkdm";
clocks = <&dpll_usb_ck>;
};
};
&scm_conf_clocks {
- dss_deshdcp_clk: dss_deshdcp_clk@558 {
+ dss_deshdcp_clk: clock-dss-deshdcp-0@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "dss_deshdcp_clk";
clocks = <&l3_iclk_div>;
ti,bit-shift = <0>;
reg = <0x558>;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <20>;
reg = <0x0558>;
};
- ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <21>;
reg = <0x0558>;
};
- ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <22>;
reg = <0x0558>;
};
- sys_32k_ck: sys_32k_ck {
+ sys_32k_ck: clock-sys-32k {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_32k_ck";
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
ti,bit-shift = <8>;
reg = <0x6c4>;
@@ -1513,97 +1696,110 @@
};
&cm_core_aon {
- mpu_cm: mpu-cm@300 {
+ mpu_cm: clock@300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x300 0x100>;
- mpu_clkctrl: mpu-clkctrl@20 {
+ mpu_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- dsp1_cm: dsp1-cm@400 {
+ dsp1_cm: clock@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dsp1_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
- dsp1_clkctrl: dsp1-clkctrl@20 {
+ dsp1_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dsp1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- ipu_cm: ipu-cm@500 {
+ ipu_cm: clock@500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ipu_cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x500 0x100>;
- ipu1_clkctrl: ipu1-clkctrl@20 {
+ ipu1_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
- ipu_clkctrl: ipu-clkctrl@50 {
+ ipu_clkctrl: clock@50 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu_clkctrl";
reg = <0x50 0x34>;
#clock-cells = <2>;
};
};
- dsp2_cm: dsp2-cm@600 {
+ dsp2_cm: clock@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dsp2_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- dsp2_clkctrl: dsp2-clkctrl@20 {
+ dsp2_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dsp2_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- rtc_cm: rtc-cm@700 {
+ rtc_cm: clock@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "rtc_cm";
reg = <0x700 0x60>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x60>;
- rtc_clkctrl: rtc-clkctrl@20 {
+ rtc_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "rtc_clkctrl";
reg = <0x20 0x28>;
#clock-cells = <2>;
};
};
- vpe_cm: vpe-cm@760 {
+ vpe_cm: clock@760 {
compatible = "ti,omap4-cm";
+ clock-output-names = "vpe_cm";
reg = <0x760 0xc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x760 0xc>;
- vpe_clkctrl: vpe-clkctrl@0 {
+ vpe_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "vpe_clkctrl";
reg = <0x0 0xc>;
#clock-cells = <2>;
};
@@ -1612,212 +1808,242 @@
};
&cm_core {
- coreaon_cm: coreaon-cm@600 {
+ coreaon_cm: clock@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "coreaon_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- coreaon_clkctrl: coreaon-clkctrl@20 {
+ coreaon_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "coreaon_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
};
- l3main1_cm: l3main1-cm@700 {
+ l3main1_cm: clock@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3main1_cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x100>;
- l3main1_clkctrl: l3main1-clkctrl@20 {
+ l3main1_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3main1_clkctrl";
reg = <0x20 0x74>;
#clock-cells = <2>;
};
};
- ipu2_cm: ipu2-cm@900 {
+ ipu2_cm: clock@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ipu2_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
- ipu2_clkctrl: ipu2-clkctrl@20 {
+ ipu2_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu2_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- dma_cm: dma-cm@a00 {
+ dma_cm: clock@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dma_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
- dma_clkctrl: dma-clkctrl@20 {
+ dma_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dma_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- emif_cm: emif-cm@b00 {
+ emif_cm: clock@b00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "emif_cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xb00 0x100>;
- emif_clkctrl: emif-clkctrl@20 {
+ emif_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "emif_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- atl_cm: atl-cm@c00 {
+ atl_cm: clock@c00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "atl_cm";
reg = <0xc00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xc00 0x100>;
- atl_clkctrl: atl-clkctrl@0 {
+ atl_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "atl_clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
- l4cfg_cm: l4cfg-cm@d00 {
+ l4cfg_cm: clock@d00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4cfg_cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xd00 0x100>;
- l4cfg_clkctrl: l4cfg-clkctrl@20 {
+ l4cfg_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4cfg_clkctrl";
reg = <0x20 0x84>;
#clock-cells = <2>;
};
};
- l3instr_cm: l3instr-cm@e00 {
+ l3instr_cm: clock@e00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3instr_cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe00 0x100>;
- l3instr_clkctrl: l3instr-clkctrl@20 {
+ l3instr_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3instr_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
- iva_cm: iva-cm@f00 {
+ iva_cm: clock@f00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "iva_cm";
reg = <0xf00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xf00 0x100>;
- iva_clkctrl: iva-clkctrl@20 {
+ iva_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "iva_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
- cam_cm: cam-cm@1000 {
+ cam_cm: clock@1000 {
compatible = "ti,omap4-cm";
+ clock-output-names = "cam_cm";
reg = <0x1000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x100>;
- cam_clkctrl: cam-clkctrl@20 {
+ cam_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "cam_clkctrl";
reg = <0x20 0x2c>;
#clock-cells = <2>;
};
};
- dss_cm: dss-cm@1100 {
+ dss_cm: clock@1100 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dss_cm";
reg = <0x1100 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1100 0x100>;
- dss_clkctrl: dss-clkctrl@20 {
+ dss_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dss_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
};
- gpu_cm: gpu-cm@1200 {
+ gpu_cm: clock@1200 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gpu_cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1200 0x100>;
- gpu_clkctrl: gpu-clkctrl@20 {
+ gpu_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "gpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- l3init_cm: l3init-cm@1300 {
+ l3init_cm: clock@1300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3init_cm";
reg = <0x1300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1300 0x100>;
- l3init_clkctrl: l3init-clkctrl@20 {
+ l3init_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3init_clkctrl";
reg = <0x20 0x6c>, <0xe0 0x14>;
#clock-cells = <2>;
};
- pcie_clkctrl: pcie-clkctrl@b0 {
+ pcie_clkctrl: clock@b0 {
compatible = "ti,clkctrl";
+ clock-output-names = "pcie_clkctrl";
reg = <0xb0 0xc>;
#clock-cells = <2>;
};
- gmac_clkctrl: gmac-clkctrl@d0 {
+ gmac_clkctrl: clock@d0 {
compatible = "ti,clkctrl";
+ clock-output-names = "gmac_clkctrl";
reg = <0xd0 0x4>;
#clock-cells = <2>;
};
};
- l4per_cm: l4per-cm@1700 {
+ l4per_cm: clock@1700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4per_cm";
reg = <0x1700 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1700 0x300>;
- l4per_clkctrl: l4per-clkctrl@28 {
+ l4per_clkctrl: clock@28 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4per_clkctrl";
reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
#clock-cells = <2>;
@@ -1825,20 +2051,23 @@
assigned-clock-parents = <&abe_24m_fclk>;
};
- l4sec_clkctrl: l4sec-clkctrl@1a0 {
+ l4sec_clkctrl: clock@1a0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4sec_clkctrl";
reg = <0x1a0 0x2c>;
#clock-cells = <2>;
};
- l4per2_clkctrl: l4per2-clkctrl@c {
+ l4per2_clkctrl: clock@c {
compatible = "ti,clkctrl";
+ clock-output-names = "l4per2_clkctrl";
reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
#clock-cells = <2>;
};
- l4per3_clkctrl: l4per3-clkctrl@14 {
+ l4per3_clkctrl: clock@14 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4per3_clkctrl";
reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
#clock-cells = <2>;
};
@@ -1847,15 +2076,17 @@
};
&prm {
- wkupaon_cm: wkupaon-cm@1800 {
+ wkupaon_cm: clock@1800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkupaon_cm";
reg = <0x1800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1800 0x100>;
- wkupaon_clkctrl: wkupaon-clkctrl@20 {
+ wkupaon_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "wkupaon_clkctrl";
reg = <0x20 0x6c>;
#clock-cells = <2>;
};
diff --git a/dts/src/arm/exynos3250.dtsi b/dts/src/arm/exynos3250.dtsi
index ae64431585..78dad233ff 100644
--- a/dts/src/arm/exynos3250.dtsi
+++ b/dts/src/arm/exynos3250.dtsi
@@ -269,7 +269,8 @@
};
timer@10050000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos3250-mct",
+ "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
@@ -428,8 +429,6 @@
clocks = <&cmu CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@12690000 {
@@ -439,8 +438,6 @@
clocks = <&cmu CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
adc: adc@126c0000 {
diff --git a/dts/src/arm/exynos4.dtsi b/dts/src/arm/exynos4.dtsi
index e81b3ee4e0..6f0ca3354e 100644
--- a/dts/src/arm/exynos4.dtsi
+++ b/dts/src/arm/exynos4.dtsi
@@ -373,7 +373,7 @@
status = "disabled";
};
- ehci: ehci@12580000 {
+ ehci: usb@12580000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12580000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -384,7 +384,7 @@
phy-names = "host", "hsic0", "hsic1";
};
- ohci: ohci@12590000 {
+ ohci: usb@12590000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12590000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -676,8 +676,6 @@
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@12690000 {
@@ -687,8 +685,6 @@
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
mdma1: dma-controller@12850000 {
@@ -698,8 +694,6 @@
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
};
fimd: fimd@11c00000 {
diff --git a/dts/src/arm/exynos4210-universal_c210.dts b/dts/src/arm/exynos4210-universal_c210.dts
index 138d606d58..62bf335d5b 100644
--- a/dts/src/arm/exynos4210-universal_c210.dts
+++ b/dts/src/arm/exynos4210-universal_c210.dts
@@ -666,8 +666,6 @@
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
power-domains = <&pd_lcd0>;
};
};
diff --git a/dts/src/arm/exynos4412-odroidu3.dts b/dts/src/arm/exynos4412-odroidu3.dts
index efaf7533e8..36c369c42b 100644
--- a/dts/src/arm/exynos4412-odroidu3.dts
+++ b/dts/src/arm/exynos4412-odroidu3.dts
@@ -119,8 +119,8 @@
phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
phy-names = "hsic0", "hsic1";
- ethernet: usbether@2 {
- compatible = "usb0424,9730";
+ ethernet: ethernet@2 {
+ compatible = "usb424,9730";
reg = <2>;
local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
};
diff --git a/dts/src/arm/exynos4412-odroidx.dts b/dts/src/arm/exynos4412-odroidx.dts
index a9fada51eb..1f17cc30ed 100644
--- a/dts/src/arm/exynos4412-odroidx.dts
+++ b/dts/src/arm/exynos4412-odroidx.dts
@@ -70,19 +70,19 @@
phy-names = "hsic0";
hub@2 {
- compatible = "usb0424,3503";
+ compatible = "usb424,3503";
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
hub@1 {
- compatible = "usb0424,9514";
+ compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
- compatible = "usb0424,ec00";
+ ethernet: ethernet@1 {
+ compatible = "usb424,ec00";
reg = <1>;
/* Filled in by a bootloader */
local-mac-address = [00 00 00 00 00 00];
diff --git a/dts/src/arm/exynos5250-smdk5250.dts b/dts/src/arm/exynos5250-smdk5250.dts
index 21fbbf3d86..71293749ac 100644
--- a/dts/src/arm/exynos5250-smdk5250.dts
+++ b/dts/src/arm/exynos5250-smdk5250.dts
@@ -129,7 +129,7 @@
samsung,i2c-max-bus-freq = <20000>;
eeprom@50 {
- compatible = "samsung,s524ad0xd1";
+ compatible = "samsung,s524ad0xd1", "atmel,24c128";
reg = <0x50>;
};
@@ -289,7 +289,7 @@
samsung,i2c-max-bus-freq = <20000>;
eeprom@51 {
- compatible = "samsung,s524ad0xd1";
+ compatible = "samsung,s524ad0xd1", "atmel,24c128";
reg = <0x51>;
};
diff --git a/dts/src/arm/exynos5250.dtsi b/dts/src/arm/exynos5250.dtsi
index 5baaa7eb71..4708dcd575 100644
--- a/dts/src/arm/exynos5250.dtsi
+++ b/dts/src/arm/exynos5250.dtsi
@@ -245,7 +245,8 @@
};
timer@101c0000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos5250-mct",
+ "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
@@ -699,8 +700,6 @@
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@121b0000 {
@@ -710,8 +709,6 @@
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
mdma0: dma-controller@10800000 {
@@ -721,8 +718,6 @@
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
};
mdma1: dma-controller@11c10000 {
@@ -732,8 +727,6 @@
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
};
gsc_0: gsc@13e00000 {
@@ -817,15 +810,14 @@
status = "disabled";
};
- dp_phy: video-phy {
+ dp_phy: video-phy-0 {
compatible = "samsung,exynos5250-dp-video-phy";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <0>;
};
- mipi_phy: video-phy@10040710 {
+ mipi_phy: video-phy-1 {
compatible = "samsung,s5pv210-mipi-video-phy";
- reg = <0x10040710 0x100>;
#phy-cells = <1>;
syscon = <&pmu_system_controller>;
};
diff --git a/dts/src/arm/exynos5260.dtsi b/dts/src/arm/exynos5260.dtsi
index 56271e7c45..ff1ee409ef 100644
--- a/dts/src/arm/exynos5260.dtsi
+++ b/dts/src/arm/exynos5260.dtsi
@@ -333,7 +333,8 @@
};
mct: timer@100b0000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos5260-mct",
+ "samsung,exynos4210-mct";
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
clock-names = "fin_pll", "mct";
diff --git a/dts/src/arm/exynos5410-odroidxu.dts b/dts/src/arm/exynos5410-odroidxu.dts
index e54a339185..d1cbc6b8a5 100644
--- a/dts/src/arm/exynos5410-odroidxu.dts
+++ b/dts/src/arm/exynos5410-odroidxu.dts
@@ -655,8 +655,8 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@2 {
- compatible = "usb0424,9730";
+ ethernet: ethernet@2 {
+ compatible = "usb424,9730";
reg = <2>;
local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
};
diff --git a/dts/src/arm/exynos5410.dtsi b/dts/src/arm/exynos5410.dtsi
index 4d797a9abb..8a6b890fb8 100644
--- a/dts/src/arm/exynos5410.dtsi
+++ b/dts/src/arm/exynos5410.dtsi
@@ -196,8 +196,6 @@
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@121b0000 {
@@ -207,8 +205,6 @@
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
audi2s0: i2s@3830000 {
diff --git a/dts/src/arm/exynos5420.dtsi b/dts/src/arm/exynos5420.dtsi
index 21b6087050..9f2523a873 100644
--- a/dts/src/arm/exynos5420.dtsi
+++ b/dts/src/arm/exynos5420.dtsi
@@ -437,8 +437,6 @@
clocks = <&clock_audss EXYNOS_ADMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <6>;
- #dma-requests = <16>;
power-domains = <&mau_pd>;
};
@@ -449,8 +447,6 @@
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@121b0000 {
@@ -460,8 +456,6 @@
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
mdma0: dma-controller@10800000 {
@@ -471,8 +465,6 @@
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
};
mdma1: dma-controller@11c10000 {
@@ -482,8 +474,6 @@
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in
diff --git a/dts/src/arm/exynos5422-odroid-core.dtsi b/dts/src/arm/exynos5422-odroid-core.dtsi
index 2f65dcf6ba..35818c4cd8 100644
--- a/dts/src/arm/exynos5422-odroid-core.dtsi
+++ b/dts/src/arm/exynos5422-odroid-core.dtsi
@@ -333,8 +333,6 @@
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
- #address-cells = <1>;
- #size-cells = <0>;
tRFC-min-tck = <17>;
tRRD-min-tck = <2>;
@@ -358,10 +356,9 @@
tCKESR-min-tck = <2>;
tMRD-min-tck = <5>;
- timings_samsung_K3QF2F20DB_800mhz: timings@800000000 {
+ timings_samsung_K3QF2F20DB_800mhz: timings {
compatible = "jedec,lpddr3-timings";
- /* workaround: 'reg' shows max-freq */
- reg = <800000000>;
+ max-freq = <800000000>;
min-freq = <100000000>;
tRFC = <65000>;
tRRD = <6000>;
diff --git a/dts/src/arm/exynos5422-odroidxu3-lite.dts b/dts/src/arm/exynos5422-odroidxu3-lite.dts
index 62c5928aa9..e3154a1cae 100644
--- a/dts/src/arm/exynos5422-odroidxu3-lite.dts
+++ b/dts/src/arm/exynos5422-odroidxu3-lite.dts
@@ -113,13 +113,13 @@
#size-cells = <0>;
hub@1 {
- compatible = "usb0424,9514";
+ compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
- compatible = "usb0424,ec00";
+ ethernet: ethernet@1 {
+ compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
};
diff --git a/dts/src/arm/exynos5422-odroidxu3.dts b/dts/src/arm/exynos5422-odroidxu3.dts
index cecaeb69e6..a378d4937f 100644
--- a/dts/src/arm/exynos5422-odroidxu3.dts
+++ b/dts/src/arm/exynos5422-odroidxu3.dts
@@ -80,13 +80,13 @@
#size-cells = <0>;
hub@1 {
- compatible = "usb0424,9514";
+ compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
- compatible = "usb0424,ec00";
+ ethernet: ethernet@1 {
+ compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
};
diff --git a/dts/src/arm/exynos54xx.dtsi b/dts/src/arm/exynos54xx.dtsi
index 2ddb7a5f12..3ec43761d8 100644
--- a/dts/src/arm/exynos54xx.dtsi
+++ b/dts/src/arm/exynos54xx.dtsi
@@ -74,7 +74,8 @@
};
mct: timer@101c0000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos5420-mct",
+ "samsung,exynos4210-mct";
reg = <0x101c0000 0xb00>;
interrupts-extended = <&combiner 23 3>,
<&combiner 23 4>,
diff --git a/dts/src/arm/hpe-bmc-dl360gen10.dts b/dts/src/arm/hpe-bmc-dl360gen10.dts
new file mode 100644
index 0000000000..3a7382ce40
--- /dev/null
+++ b/dts/src/arm/hpe-bmc-dl360gen10.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE DL360Gen10
+ */
+
+/include/ "hpe-gxp.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "hpe,gxp-dl360gen10", "hpe,gxp";
+ model = "Hewlett Packard Enterprise ProLiant dl360 Gen10";
+
+ aliases {
+ serial0 = &uartc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x20000000>;
+ };
+};
diff --git a/dts/src/arm/hpe-gxp.dtsi b/dts/src/arm/hpe-gxp.dtsi
new file mode 100644
index 0000000000..cf735b3c4f
--- /dev/null
+++ b/dts/src/arm/hpe-gxp.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE GXP
+ */
+
+/dts-v1/;
+/ {
+ model = "Hewlett Packard Enterprise GXP BMC";
+ compatible = "hpe,gxp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&L2>;
+ };
+ };
+
+ clocks {
+ pll: clock-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1600000000>;
+ };
+
+ iopclk: clock-1 {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&pll>;
+ };
+ };
+
+ axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges;
+
+ L2: cache-controller@b0040000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xb0040000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ ahb@c0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc0000000 0x30000000>;
+ dma-ranges;
+
+ vic0: interrupt-controller@eff0000 {
+ compatible = "arm,pl192-vic";
+ reg = <0xeff0000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ vic1: interrupt-controller@80f00000 {
+ compatible = "arm,pl192-vic";
+ reg = <0x80f00000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uarta: serial@e0 {
+ compatible = "ns16550a";
+ reg = <0xe0 0x8>;
+ interrupts = <17>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uartb: serial@e8 {
+ compatible = "ns16550a";
+ reg = <0xe8 0x8>;
+ interrupts = <18>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uartc: serial@f0 {
+ compatible = "ns16550a";
+ reg = <0xf0 0x8>;
+ interrupts = <19>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ usb0: usb@efe0000 {
+ compatible = "hpe,gxp-ehci", "generic-ehci";
+ reg = <0xefe0000 0x100>;
+ interrupts = <7>;
+ interrupt-parent = <&vic0>;
+ };
+
+ st: timer@80 {
+ compatible = "hpe,gxp-timer";
+ reg = <0x80 0x16>;
+ interrupts = <0>;
+ interrupt-parent = <&vic0>;
+ clocks = <&iopclk>;
+ clock-names = "iop";
+ };
+
+ usb1: usb@efe0100 {
+ compatible = "hpe,gxp-ohci", "generic-ohci";
+ reg = <0xefe0100 0x110>;
+ interrupts = <6>;
+ interrupt-parent = <&vic0>;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/imx27.dtsi b/dts/src/arm/imx27.dtsi
index fd525c3b16..b660c7d055 100644
--- a/dts/src/arm/imx27.dtsi
+++ b/dts/src/arm/imx27.dtsi
@@ -96,7 +96,7 @@
<&clks IMX27_CLK_DMA_AHB_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <1>;
- #dma-channels = <16>;
+ dma-channels = <16>;
};
wdog: watchdog@10002000 {
diff --git a/dts/src/arm/imx28-evk.dts b/dts/src/arm/imx28-evk.dts
index 7e2b0f198d..1053b7c584 100644
--- a/dts/src/arm/imx28-evk.dts
+++ b/dts/src/arm/imx28-evk.dts
@@ -129,7 +129,7 @@
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf016b", "jedec,spi-nor";
diff --git a/dts/src/arm/imx28-m28evk.dts b/dts/src/arm/imx28-m28evk.dts
index f3bddc5ada..13acdc7916 100644
--- a/dts/src/arm/imx28-m28evk.dts
+++ b/dts/src/arm/imx28-m28evk.dts
@@ -33,7 +33,7 @@
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80", "jedec,spi-nor";
diff --git a/dts/src/arm/imx28-sps1.dts b/dts/src/arm/imx28-sps1.dts
index 43be7a6a76..90928db0df 100644
--- a/dts/src/arm/imx28-sps1.dts
+++ b/dts/src/arm/imx28-sps1.dts
@@ -51,7 +51,7 @@
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "everspin,mr25h256", "mr25h256";
diff --git a/dts/src/arm/imx51-digi-connectcore-jsk.dts b/dts/src/arm/imx51-digi-connectcore-jsk.dts
index aab8d6f137..10cae7c3a8 100644
--- a/dts/src/arm/imx51-digi-connectcore-jsk.dts
+++ b/dts/src/arm/imx51-digi-connectcore-jsk.dts
@@ -13,6 +13,13 @@
chosen {
stdout-path = &uart1;
};
+
+ usbphy1: usbphy1 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
+ clock-names = "main_clk";
+ #phy-cells = <0>;
+ };
};
&esdhc1 {
@@ -63,6 +70,7 @@
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
+ fsl,usbphy = <&usbphy1>;
dr_mode = "host";
phy_type = "ulpi";
disable-over-current;
diff --git a/dts/src/arm/imx51-digi-connectcore-som.dtsi b/dts/src/arm/imx51-digi-connectcore-som.dtsi
index 7d4970417d..f0809a16a2 100644
--- a/dts/src/arm/imx51-digi-connectcore-som.dtsi
+++ b/dts/src/arm/imx51-digi-connectcore-som.dtsi
@@ -34,22 +34,22 @@
regulators {
sw1_reg: sw1 {
- regulator-min-microvolt = <1000000>;
+ regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
+ regulator-min-microvolt = <1175000>;
+ regulator-max-microvolt = <1275000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
@@ -102,18 +102,6 @@
regulator-always-on;
};
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <3150000>;
- regulator-max-microvolt = <3150000>;
- regulator-always-on;
- };
-
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -124,8 +112,6 @@
regulator-always-on;
};
- gpo1_reg: gpo1 { };
-
gpo2_reg: gpo2 { };
gpo3_reg: gpo3 { };
@@ -198,6 +184,7 @@
&usbotg {
phy_type = "utmi_wide";
disable-over-current;
+ vbus-supply = <&swbst_reg>;
/* Device role is not known, keep status disabled */
};
diff --git a/dts/src/arm/imx51.dtsi b/dts/src/arm/imx51.dtsi
index 56c8d87864..1e20a6639e 100644
--- a/dts/src/arm/imx51.dtsi
+++ b/dts/src/arm/imx51.dtsi
@@ -215,6 +215,8 @@
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -426,6 +428,8 @@
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -436,6 +440,8 @@
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
diff --git a/dts/src/arm/imx6dl-colibri-aster.dts b/dts/src/arm/imx6dl-colibri-aster.dts
new file mode 100644
index 0000000000..74e8a6cd8b
--- /dev/null
+++ b/dts/src/arm/imx6dl-colibri-aster.dts
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl.dtsi"
+#include "imx6qdl-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Aster Board";
+ compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl",
+ "fsl,imx6dl";
+
+ aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/* Colibri SSP */
+&ecspi4 {
+ cs-gpios = <
+ &gpio5 2 GPIO_ACTIVE_HIGH
+ &gpio5 4 GPIO_ACTIVE_HIGH
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>;
+ status = "okay";
+};
+
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
+&i2c3 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_csi_gpio_1
+ &pinctrl_gpio_2
+ &pinctrl_gpio_aster
+ &pinctrl_usbh_oc_1
+ &pinctrl_usbc_id_1
+ &pinctrl_weim_gpio_5
+ >;
+
+ pinctrl_gpio_aster: gpioaster {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
+ >;
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_host_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6dl-colibri-eval-v3.dts b/dts/src/arm/imx6dl-colibri-eval-v3.dts
index 7da74e6f46..7272edd85a 100644
--- a/dts/src/arm/imx6dl-colibri-eval-v3.dts
+++ b/dts/src/arm/imx6dl-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
@@ -17,12 +17,6 @@
compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
"fsl,imx6dl";
- /* Will be filled by the bootloader */
- memory@10000000 {
- device_type = "memory";
- reg = <0x10000000 0>;
- };
-
aliases {
i2c0 = &i2c2;
i2c1 = &i2c3;
@@ -44,67 +38,6 @@
clock-frequency = <16000000>;
clock-output-names = "clk16m";
};
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- wakeup {
- label = "Wake-Up";
- gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
- lcd_display: disp0 {
- compatible = "fsl,imx-parallel-display";
- #address-cells = <1>;
- #size-cells = <0>;
- interface-pix-fmt = "bgr666";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_lcdif>;
- status = "okay";
-
- port@0 {
- reg = <0>;
-
- lcd_display_in: endpoint {
- remote-endpoint = <&ipu1_di0_disp0>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
- };
-
- panel: panel {
- /*
- * edt,et057090dhu: EDT 5.7" LCD TFT
- * edt,et070080dh6: EDT 7.0" LCD TFT
- */
- compatible = "edt,et057090dhu";
- backlight = <&backlight>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-};
-
-&backlight {
- brightness-levels = <0 127 191 223 239 247 251 255>;
- default-brightness-level = <1>;
- status = "okay";
};
/* Colibri SSP */
@@ -113,40 +46,21 @@
mcp251x0: mcp251x@0 {
compatible = "microchip,mcp2515";
- reg = <0>;
clocks = <&clk16m>;
interrupt-parent = <&gpio3>;
interrupts = <27 0x2>;
+ reg = <0>;
spi-max-frequency = <10000000>;
status = "okay";
};
};
-&hdmi {
- status = "okay";
-};
-
/*
* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
&i2c3 {
status = "okay";
- /*
- * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
- */
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcap_1>;
- reg = <0x4a>;
- interrupt-parent = <&gpio1>;
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */
- status = "disabled";
- };
-
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
@@ -162,24 +76,6 @@
&pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
&pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
>;
-
- pinctrl_pcap_1: pcap1grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
- >;
- };
-
- pinctrl_mxt_ts: mxttsgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */
- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
- >;
- };
-};
-
-&ipu1_di0_disp0 {
- remote-endpoint = <&lcd_display_in>;
};
&pwm1 {
diff --git a/dts/src/arm/imx6dl-colibri-iris-v2.dts b/dts/src/arm/imx6dl-colibri-iris-v2.dts
new file mode 100644
index 0000000000..3a6d388976
--- /dev/null
+++ b/dts/src/arm/imx6dl-colibri-iris-v2.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6dl-colibri-iris.dts"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board";
+ compatible = "toradex,colibri_imx6dl-iris-v2", "toradex,colibri_imx6dl",
+ "fsl,imx6dl";
+
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
+ regulator-name = "3v3_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_iris &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>;
+
+ pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
+ >;
+ };
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ cap-power-off-card;
+ /* uncomment the following to enable SD card UHS mode if you have a V1.1 module */
+ /* /delete-property/ no-1-8-v; */
+ vmmc-supply = <&reg_3v3_vmmc>;
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6dl-colibri-iris.dts b/dts/src/arm/imx6dl-colibri-iris.dts
new file mode 100644
index 0000000000..cf77d894f6
--- /dev/null
+++ b/dts/src/arm/imx6dl-colibri-iris.dts
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl.dtsi"
+#include "imx6qdl-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Iris Board";
+ compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl",
+ "fsl,imx6dl";
+
+ aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c3;
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/* Colibri SSP */
+&ecspi4 {
+ status = "okay";
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>;
+
+ /*
+ * uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one
+ * wants to turn the transceiver off, that property has to be deleted
+ * and the gpio handled in userspace.
+ * The same applies to uart-b-c-on-x14-enable where the UART_B and
+ * UART_C transceiver is turned on.
+ */
+ uart-a-on-x13-enable-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
+ output-high;
+ };
+
+ uart-b-c-on-x14-enable-hog {
+ gpio-hog;
+ gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
+ output-high;
+ };
+};
+
+/*
+ * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
+&i2c3 {
+ status = "okay";
+
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_gpio_iris
+ &pinctrl_usbh_oc_1
+ &pinctrl_usbc_id_1
+ >;
+
+ pinctrl_gpio_iris: gpioirisgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart1_forceoff: uart1forceoffgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart23_forceoff: uart23forceoffgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
+ >;
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_host_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6dl-colibri-v1_1-eval-v3.dts b/dts/src/arm/imx6dl-colibri-v1_1-eval-v3.dts
deleted file mode 100644
index 223275f028..0000000000
--- a/dts/src/arm/imx6dl-colibri-v1_1-eval-v3.dts
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Copyright 2020 Toradex
- */
-
-/dts-v1/;
-
-#include "imx6dl-colibri-eval-v3.dts"
-#include "imx6qdl-colibri-v1_1-uhs.dtsi"
-
-/ {
- model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3";
- compatible = "toradex,colibri_imx6dl-v1_1-eval-v3",
- "toradex,colibri_imx6dl-v1_1",
- "toradex,colibri_imx6dl-eval-v3",
- "toradex,colibri_imx6dl",
- "fsl,imx6dl";
-};
-
-/* Colibri MMC */
-&usdhc1 {
- status = "okay";
- /*
- * Please make sure your carrier board does not pull-up any of
- * the MMC/SD signals to 3.3 volt before attempting to activate
- * UHS-I support.
- * To let signaling voltage be changed to 1.8V, please
- * delete no-1-8-v property (example below):
- * /delete-property/no-1-8-v;
- */
-};
diff --git a/dts/src/arm/imx6dl-eckelmann-ci4x10.dts b/dts/src/arm/imx6dl-eckelmann-ci4x10.dts
index b4a9523e32..864dc50184 100644
--- a/dts/src/arm/imx6dl-eckelmann-ci4x10.dts
+++ b/dts/src/arm/imx6dl-eckelmann-ci4x10.dts
@@ -297,7 +297,11 @@
phy-mode = "rmii";
phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
- clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
+ clocks = <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&rmii_clk>,
+ <&clks IMX6QDL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp", "enet_out";
status = "okay";
mdio {
diff --git a/dts/src/arm/imx6dl-plybas.dts b/dts/src/arm/imx6dl-plybas.dts
index bf72a67a9c..c52e6caf39 100644
--- a/dts/src/arm/imx6dl-plybas.dts
+++ b/dts/src/arm/imx6dl-plybas.dts
@@ -214,7 +214,7 @@
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
- fsl,uart-has-rtscts;
+ uart-has-rtscts;
linux,rs485-enabled-at-boot-time;
rs485-rts-delay = <0 20>;
status = "okay";
diff --git a/dts/src/arm/imx6dl-rex-basic.dts b/dts/src/arm/imx6dl-rex-basic.dts
index 0f1616bfa9..b72f8ea1e6 100644
--- a/dts/src/arm/imx6dl-rex-basic.dts
+++ b/dts/src/arm/imx6dl-rex-basic.dts
@@ -19,7 +19,7 @@
};
&ecspi3 {
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6dl-victgo.dts b/dts/src/arm/imx6dl-victgo.dts
index 227c952543..516ec915a9 100644
--- a/dts/src/arm/imx6dl-victgo.dts
+++ b/dts/src/arm/imx6dl-victgo.dts
@@ -5,46 +5,13 @@
*/
/dts-v1/;
-#include <dt-bindings/display/sdtv-standards.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/media/tvp5150.h>
-#include <dt-bindings/sound/fsl-imx-audmux.h>
#include "imx6dl.dtsi"
+#include "imx6qdl-vicut1.dtsi"
/ {
model = "Kverneland TGO";
compatible = "kvg,victgo", "fsl,imx6dl";
- chosen {
- stdout-path = &uart4;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_backlight>;
- pwms = <&pwm1 0 5000000 0>;
- brightness-levels = <0 16 64 255>;
- num-interpolated-steps = <16>;
- default-brightness-level = <1>;
- power-supply = <&reg_3v3>;
- enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
- };
-
- connector {
- compatible = "composite-video-connector";
- label = "Composite0";
- sdtv-standards = <SDTV_STD_PAL_B>;
-
- port {
- comp0_out: endpoint {
- remote-endpoint = <&tvp5150_comp0_in>;
- };
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -71,36 +38,9 @@
io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>;
};
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
-
- led-0 {
- label = "debug0";
- function = LED_FUNCTION_HEARTBEAT;
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- label = "debug1";
- function = LED_FUNCTION_DISK;
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "disk-activity";
- };
-
- led-2 {
- label = "power_led";
- function = LED_FUNCTION_POWER;
- gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
panel {
- compatible = "kyo,tcg121xglp";
- backlight = <&backlight>;
+ compatible = "lg,lb070wv8";
+ backlight = <&backlight_lcd>;
power-supply = <&reg_3v3>;
port {
@@ -116,38 +56,6 @@
clock-frequency = <50000000>;
};
- reg_1v8: regulator-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_h1_vbus: regulator-h1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "h1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_otg_vbus: regulator-otg-vbus {
- compatible = "regulator-fixed";
- regulator-name = "otg-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
rotary-encoder {
compatible = "rotary-encoder";
pinctrl-0 = <&pinctrl_rotary_ch>;
@@ -160,33 +68,6 @@
wakeup-source;
};
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "prti6q-sgtl5000";
- simple-audio-card,format = "i2s";
- simple-audio-card,widgets =
- "Microphone", "Microphone Jack",
- "Line", "Line In Jack",
- "Headphone", "Headphone Jack",
- "Speaker", "External Speaker";
- simple-audio-card,routing =
- "MIC_IN", "Microphone Jack",
- "LINE_IN", "Line In Jack",
- "Headphone Jack", "HP_OUT",
- "External Speaker", "LINE_OUT";
-
- simple-audio-card,cpu {
- sound-dai = <&ssi1>;
- system-clock-frequency = <0>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&codec>;
- bitclock-master;
- frame-master;
- };
- };
-
thermal-zones {
chassis-thermal {
polling-delay = <20000>;
@@ -213,7 +94,6 @@
<&adc_ts 5>;
io-channel-names = "y", "z1", "z2", "x";
touchscreen-min-pressure = <64687>;
- touchscreen-inverted-x;
touchscreen-inverted-y;
touchscreen-x-plate-ohms = <300>;
touchscreen-y-plate-ohms = <800>;
@@ -254,61 +134,6 @@
};
};
-&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux>;
- status = "okay";
-
- mux-ssi1 {
- fsl,audmux-port = <0>;
- fsl,port-config = <
- IMX_AUDMUX_V2_PTCR_SYN 0
- IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
- IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
- IMX_AUDMUX_V2_PTCR_TFSDIR 0
- IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
- >;
- };
-
- mux-pins3 {
- fsl,audmux-port = <2>;
- fsl,port-config = <
- IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
- 0 IMX_AUDMUX_V2_PDCR_TXRXEN
- >;
- };
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can2>;
- status = "okay";
-};
-
-&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
-};
-
-&ecspi1 {
- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <20000000>;
- };
-};
-
&ecspi2 {
cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -385,36 +210,19 @@
"CAM2_MIRROR", "", "", "SMBALERT",
"DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
"SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
- "SD1_DATA3", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
- "BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
- "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH",
- "POWER_LED", "", "", "", "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
- "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ",
- "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0",
- "YACO_RESET";
+ "SD1_DATA3", "ETH_MDIO", "",
+ "", "", "", "", "", "", "", "ETH_MDC";
};
&gpio4 {
gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX",
- "", "", "DIP1_FB", "", "VCAM_EN", "", "", "",
- "CPU_LIGHT_ON", "", "ETH_RESET", "CPU_CONTACT_IN", "BL_EN",
- "BL_PWM", "ETH_INTRP", "ISB_LED";
+ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
+ "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR",
+ "CAN2_SR", "CAN2_TX", "CAN2_RX",
+ "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL",
+ "HITCH_IN_OUT",
+ "LIGHT_ON", "", "ETH_RESET", "CONTACT_IN", "BL_EN",
+ "BL_PWM", "ETH_INT", "ISB_LED";
};
&gpio5 {
@@ -422,51 +230,22 @@
"", "", "", "", "", "", "", "",
"TSC_PENIRQ", "TSC_BUSY", "ECSPI2_MOSI", "ECSPI2_MISO",
"ECSPI2_SS0", "ECSPI2_SCLK", "", "",
- "", "", "", "", "", "", "", "",
+ "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET",
+ "I2S_BITCLK", "I2S_DOUT",
"I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
"YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
};
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- codec: audio-codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0xa>;
- #sound-dai-cells = <0>;
- clocks = <&clks 201>;
- VDDA-supply = <&reg_3v3>;
- VDDIO-supply = <&reg_3v3>;
- VDDD-supply = <&reg_1v8>;
- };
-
- video-decoder@5c {
- compatible = "ti,tvp5150";
- reg = <0x5c>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tvp5150_comp0_in: endpoint {
- remote-endpoint = <&comp0_out>;
- };
- };
-
- /* Output port 2 is video output pad */
- port@2 {
- reg = <2>;
-
- tvp5151_to_ipu1_csi0_mux: endpoint {
- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
- };
- };
- };
+&gpio6 {
+ gpio-line-names =
+ "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5",
+ "ITU656_D6", "ITU656_D7", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+&i2c1 {
keypad@70 {
compatible = "holtek,ht16k33";
pinctrl-names = "default";
@@ -490,225 +269,9 @@
MATRIX_KEY(6, 1, KEY_F1)
>;
};
-
- /* additional i2c devices are added automatically by the boot loader */
-};
-
-&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- adc@49 {
- compatible = "ti,ads1015";
- reg = <0x49>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@4 {
- reg = <4>;
- ti,gain = <3>;
- ti,datarate = <3>;
- };
-
- channel@5 {
- reg = <5>;
- ti,gain = <3>;
- ti,datarate = <3>;
- };
-
- channel@6 {
- reg = <6>;
- ti,gain = <3>;
- ti,datarate = <3>;
- };
-
- channel@7 {
- reg = <7>;
- ti,gain = <3>;
- ti,datarate = <3>;
- };
- };
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-
- tsens0: temperature-sensor@70 {
- compatible = "ti,tmp103";
- reg = <0x70>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&ipu1_csi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_csi0>;
- status = "okay";
-};
-
-&ipu1_csi0_mux_from_parallel_sensor {
- remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>;
-};
-
-&ldb {
- status = "okay";
-
- lvds-channel@0 {
- status = "okay";
-
- port@4 {
- reg = <4>;
-
- lvds0_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- };
-};
-
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
- status = "okay";
-};
-
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
- status = "okay";
-};
-
-&ssi1 {
- #sound-dai-cells = <0>;
- fsl,mode = "ac97-slave";
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
- status = "okay";
-};
-
-&usbh1 {
- vbus-supply = <&reg_h1_vbus>;
- pinctrl-names = "default";
- phy_type = "utmi";
- dr_mode = "host";
- status = "okay";
-};
-
-&usbotg {
- vbus-supply = <&reg_otg_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- phy_type = "utmi";
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
- no-1-8-v;
- disable-wp;
- cap-sd-highspeed;
- no-mmc;
- no-sdio;
- status = "okay";
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- bus-width = <8>;
- no-1-8-v;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
};
&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_audmux: audmuxgrp {
- fsl,pins = <
- /* SGTL5000 sys_mclk */
- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
- >;
- };
-
- pinctrl_backlight: backlightgrp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
- >;
- };
-
- pinctrl_can1: can1grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
- /* CAN1_SR */
- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
- /* CAN1_TERM */
- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088
- >;
- };
-
- pinctrl_can2: can2grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
- /* CAN2_SR */
- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- /* CS */
- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
- >;
- };
-
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
@@ -747,113 +310,12 @@
>;
};
- pinctrl_hog: hoggrp {
- fsl,pins = <
- /* ITU656_nRESET */
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
- /* CAM1_MIRROR */
- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0
- /* CAM2_MIRROR */
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0
- /* CAM_nDETECT */
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
- /* ISB_IN1 */
- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
- /* ISB_nIN2 */
- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
- /* WARN_LIGHT */
- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0
- /* ON2_FB */
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0
- /* YACO_nIRQ */
- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
- /* YACO_BOOT0 */
- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0
- /* YACO_nRESET */
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
- /* FORCE_ON1 */
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
- /* AUDIO_nRESET */
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
- /* ITU656_nPDN */
- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
-
- /* HW revision detect */
- /* REV_ID0 */
- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
- /* REV_ID1 is shared with PWM3 */
- /* REV_ID2 */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
- /* REV_ID3 */
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
- /* REV_ID4 */
- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
-
- /* New in HW revision 1 */
- /* ON1_FB */
- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0
- /* DIP1_FB */
- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_ipu1_csi0: ipu1csi0grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
- >;
- };
-
pinctrl_keypad: keypadgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
- pinctrl_leds: ledsgrp {
- fsl,pins = <
- /* DEBUG0 */
- MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0
- /* DEBUG1 */
- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0
- /* POWER_LED */
- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0
- >;
- };
-
- pinctrl_pwm1: pwm1grp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
- >;
- };
-
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
- >;
- };
-
pinctrl_rotary_ch: rotarychgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@@ -867,77 +329,4 @@
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
>;
};
-
- /* YaCO AUX Uart */
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
- >;
- };
-
- /* YaCO Touchscreen UART */
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart5: uart5grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
- /* power enable, high active */
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
- >;
- };
};
diff --git a/dts/src/arm/imx6dl-vicut1.dts b/dts/src/arm/imx6dl-vicut1.dts
index 174fd913bf..5035d30344 100644
--- a/dts/src/arm/imx6dl-vicut1.dts
+++ b/dts/src/arm/imx6dl-vicut1.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-vicut1.dtsi"
+#include "imx6qdl-vicut1-12inch.dtsi"
/ {
model = "Kverneland UT1 Board";
diff --git a/dts/src/arm/imx6q-ba16.dtsi b/dts/src/arm/imx6q-ba16.dtsi
index 6330d75f8f..f266f1b7e0 100644
--- a/dts/src/arm/imx6q-ba16.dtsi
+++ b/dts/src/arm/imx6q-ba16.dtsi
@@ -142,7 +142,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: n25q032@0 {
+ flash: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/src/arm/imx6q-bosch-acc.dts b/dts/src/arm/imx6q-bosch-acc.dts
new file mode 100644
index 0000000000..8768222e18
--- /dev/null
+++ b/dts/src/arm/imx6q-bosch-acc.dts
@@ -0,0 +1,779 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support for the i.MX6-based Bosch ACC board.
+ *
+ * Copyright (C) 2016 Garz & Fricke GmbH
+ * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus@denx.de>
+ * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
+ * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "imx6q.dtsi"
+
+/ {
+ model = "Bosch ACC";
+ compatible = "bosch,imx6q-acc", "fsl,imx6q";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ mmc0 = &usdhc4;
+ mmc1 = &usdhc2;
+ serial0 = &uart2;
+ serial1 = &uart1;
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+
+ backlight_lvds: backlight-lvds {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 200000>;
+ brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
+ num-interpolated-steps = <10>;
+ default-brightness-level = <60>;
+ power-supply = <&reg_lcd>;
+ };
+
+ panel {
+ compatible = "dataimage,fg1001l0dsswmg01";
+ backlight = <&backlight_lvds>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ refclk: refclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "12mhz_refclk";
+ assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
+ <&clks IMX6QDL_CLK_CKO2>,
+ <&clks IMX6QDL_CLK_CKO2_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
+ <&clks IMX6QDL_CLK_CKO2_PODF>,
+ <&clks IMX6QDL_CLK_OSC>;
+ assigned-clock-rates = <0>, <12000000>, <0>;
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1225000
+ 852000 1225000
+ 792000 1150000
+ 396000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 1200000 1225000
+ 996000 1175000
+ 852000 1175000
+ 792000 1150000
+ 396000 1150000
+ >;
+ };
+
+ cpu1: cpu@1 {
+ operating-points = <
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1225000
+ 852000 1225000
+ 792000 1150000
+ 396000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 1200000 1225000
+ 996000 1175000
+ 852000 1175000
+ 792000 1150000
+ 396000 1150000
+ >;
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led_red: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ max-brightness = <248>;
+ default-state = "off";
+ pwms = <&pwm2 0 500000>;
+ };
+
+ led_white: led-1 {
+ color = <LED_COLOR_ID_WHITE>;
+ max-brightness = <248>;
+ default-state = "off";
+ pwms = <&pwm3 0 500000>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_gpio_led>;
+
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_5p0: regulator-5p0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5p0";
+ };
+
+ reg_vin: regulator-vin {
+ compatible = "regulator-fixed";
+ regulator-name = "VIN";
+ regulator-min-microvolt = <4500000>;
+ regulator-max-microvolt = <4500000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+
+ reg_usb_h2_vbus: regulator-usb-h2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&reg_5p0> ;
+ regulator-always-on;
+ };
+
+ reg_vsnvs: regulator-vsnvs {
+ compatible = "regulator-fixed";
+ regulator-name = "VSNVS_3V0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+
+ reg_lcd: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD0 POWER";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_enable>;
+ gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ reg_dac: regulator-dac {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_dac";
+ regulator-min-microvolt = <20000>;
+ regulator-max-microvolt = <20000>;
+ vin-supply = <&reg_5p0> ;
+ regulator-boot-on;
+ };
+
+ reg_sw4: regulator-sw4 {
+ compatible = "regulator-fixed";
+ regulator-name = "SW4_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+
+ reg_sys: regulator-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "SYS_4V2";
+ regulator-min-microvolt = <4200000>;
+ regulator-max-microvolt = <4200000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+};
+
+&reg_arm {
+ vin-supply = <&sw2_reg>;
+};
+
+&reg_soc {
+ vin-supply = <&sw1c_reg>;
+};
+
+&reg_vdd1p1 {
+ vin-supply = <&reg_vsnvs>;
+};
+
+&reg_vdd2p5 {
+ vin-supply = <&reg_vsnvs>;
+};
+
+&reg_vdd3p0 {
+ vin-supply = <&reg_vsnvs>;
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ clocks = <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp", "enet_out";
+ phy-mode = "rmii";
+ phy-supply = <&reg_sw4>;
+ phy-handle = <&ethphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+ smsc,disable-energy-detect;
+ };
+ };
+};
+
+&gpu_vg {
+ status = "disabled";
+};
+
+&gpu_2d {
+ status = "disabled";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pmic: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1c_reg: sw1c {
+ regulator-name = "VDD_SOC (sw1abc)";
+ regulator-min-microvolt = <1275000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-name = "VDD_ARM (sw2)";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ compatible = "regulator-fixed";
+ regulator-name = "DDR_1V5a";
+ regulator-boot-on;
+ regulator-always-on;
+
+ };
+
+ sw3b_reg: sw3b {
+ compatible = "regulator-fixed";
+ regulator-name = "DDR_1V5b";
+ regulator-boot-on;
+ regulator-always-on;
+
+ };
+
+ sw4_reg: sw4 {
+ regulator-name = "AUX 3V15 (sw4)";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ status = "disabled";
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ lm75: sensor@49 {
+ compatible = "national,lm75b";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm75>;
+ reg = <0x49>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ rtc: rtc@51 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ eeprom_ext: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ usb3503: usb@8 {
+ compatible = "smsc,usb3503";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3503>;
+ reg = <0x08>;
+ connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */
+ intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */
+ initial-mode = <1>;
+ clocks = <&refclk>;
+ clock-names = "refclk";
+ refclk-frequency = <12000000>;
+ };
+
+ exc3000: touchscreen@2a {
+ compatible = "eeti,exc3000";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctouch>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ touchscreen-size-x = <4096>;
+ touchscreen-size-y = <4096>;
+ };
+
+ vcnl4035: light-sensor@60 {
+ compatible = "vishay,vcnl4035";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_proximity>;
+ reg = <0x60>;
+ };
+};
+
+&ldb {
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&pwm1 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm3 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbh2 {
+ pinctrl-names = "idle", "active";
+ pinctrl-0 = <&pinctrl_usbh2_idle>;
+ pinctrl-1 = <&pinctrl_usbh2_active>;
+ vbus-supply = <&reg_usb_h2_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ vbus-supply = <&reg_usb_otg_vbus>;
+ disable-over-current;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbphynop1 {
+ clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+ clock-names = "main_clk";
+ vcc-supply = <&reg_usb_h1_vbus>;
+};
+
+&usbphynop2 {
+ vcc-supply = <&reg_usb_h2_vbus>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ voltage-ranges = <3300 3300>;
+ vmmc-supply = <&reg_sw4>;
+ fsl,wp-controller;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ keep-power-in-suspend;
+ voltage-ranges = <3300 3300>;
+ vmmc-supply = <&reg_sw4>;
+ fsl,wp-controller;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog1>;
+ fsl,ext-reset-output;
+ timeout-sec=<10>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
+ };
+
+ pinctrl_reset_gpio_led: reset-gpio-led-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_lcd_enable: lcdenablegrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */
+ MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */
+ >;
+ };
+
+ pinctrl_lm75: lm75grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_proximity: proximitygrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_rtc: rtc-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */
+ >;
+ };
+
+ pinctrl_ctouch: ctouch-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh2_idle: usbh2-idle-grp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
+ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018
+ >;
+ };
+
+ pinctrl_usbh2_active: usbh2-active-grp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
+ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018
+ >;
+ };
+
+ pinctrl_usb3503: usb3503-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */
+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069
+ MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059
+ >;
+ };
+
+ pinctrl_wdog1: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6q-bx50v3.dtsi b/dts/src/arm/imx6q-bx50v3.dtsi
index 10922375c5..ead83091e1 100644
--- a/dts/src/arm/imx6q-bx50v3.dtsi
+++ b/dts/src/arm/imx6q-bx50v3.dtsi
@@ -160,7 +160,7 @@
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";
- m25_eeprom: m25p80@0 {
+ m25_eeprom: flash@0 {
compatible = "atmel,at25";
spi-max-frequency = <10000000>;
size = <0x8000>;
diff --git a/dts/src/arm/imx6q-cm-fx6.dts b/dts/src/arm/imx6q-cm-fx6.dts
index bfb530f29d..1ad41c944b 100644
--- a/dts/src/arm/imx6q-cm-fx6.dts
+++ b/dts/src/arm/imx6q-cm-fx6.dts
@@ -260,7 +260,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- m25p80@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p", "jedec,spi-nor";
diff --git a/dts/src/arm/imx6q-dmo-edmqmx6.dts b/dts/src/arm/imx6q-dmo-edmqmx6.dts
index c713ac03b3..9591848cbd 100644
--- a/dts/src/arm/imx6q-dmo-edmqmx6.dts
+++ b/dts/src/arm/imx6q-dmo-edmqmx6.dts
@@ -102,7 +102,7 @@
cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "m25p80", "jedec,spi-nor";
spi-max-frequency = <40000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6q-dms-ba16.dts b/dts/src/arm/imx6q-dms-ba16.dts
index 48fb47e715..137db38f0d 100644
--- a/dts/src/arm/imx6q-dms-ba16.dts
+++ b/dts/src/arm/imx6q-dms-ba16.dts
@@ -47,7 +47,7 @@
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";
- m25_eeprom: m25p80@0 {
+ m25_eeprom: flash@0 {
compatible = "atmel,at25256B", "atmel,at25";
spi-max-frequency = <20000000>;
size = <0x8000>;
diff --git a/dts/src/arm/imx6q-gw5400-a.dts b/dts/src/arm/imx6q-gw5400-a.dts
index 4cde45d5c9..e894faba57 100644
--- a/dts/src/arm/imx6q-gw5400-a.dts
+++ b/dts/src/arm/imx6q-gw5400-a.dts
@@ -137,7 +137,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,w25q256", "jedec,spi-nor";
spi-max-frequency = <30000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6q-marsboard.dts b/dts/src/arm/imx6q-marsboard.dts
index 05ee283882..cc18010023 100644
--- a/dts/src/arm/imx6q-marsboard.dts
+++ b/dts/src/arm/imx6q-marsboard.dts
@@ -100,7 +100,7 @@
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6q-rex-pro.dts b/dts/src/arm/imx6q-rex-pro.dts
index 1767e1a3cd..271f4b2d9b 100644
--- a/dts/src/arm/imx6q-rex-pro.dts
+++ b/dts/src/arm/imx6q-rex-pro.dts
@@ -19,7 +19,7 @@
};
&ecspi3 {
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,sst25vf032b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6q-vicut1.dts b/dts/src/arm/imx6q-vicut1.dts
index 0a4e251be1..dd91aff3f9 100644
--- a/dts/src/arm/imx6q-vicut1.dts
+++ b/dts/src/arm/imx6q-vicut1.dts
@@ -6,12 +6,9 @@
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-vicut1.dtsi"
+#include "imx6qdl-vicut1-12inch.dtsi"
/ {
model = "Kverneland UT1Q Board";
compatible = "kvg,vicut1q", "fsl,imx6q";
};
-
-&sata {
- status = "okay";
-};
diff --git a/dts/src/arm/imx6qdl-aristainetos.dtsi b/dts/src/arm/imx6qdl-aristainetos.dtsi
index e21f6ac864..baa197c900 100644
--- a/dts/src/arm/imx6qdl-aristainetos.dtsi
+++ b/dts/src/arm/imx6qdl-aristainetos.dtsi
@@ -96,7 +96,7 @@
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11", "jedec,spi-nor";
diff --git a/dts/src/arm/imx6qdl-aristainetos2.dtsi b/dts/src/arm/imx6qdl-aristainetos2.dtsi
index 0b90c3f59f..6b64b2fc39 100644
--- a/dts/src/arm/imx6qdl-aristainetos2.dtsi
+++ b/dts/src/arm/imx6qdl-aristainetos2.dtsi
@@ -131,7 +131,7 @@
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
- flash: m25p80@1 {
+ flash: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11", "jedec,spi-nor";
diff --git a/dts/src/arm/imx6qdl-colibri-v1_1-uhs.dtsi b/dts/src/arm/imx6qdl-colibri-v1_1-uhs.dtsi
deleted file mode 100644
index 7672fbfc29..0000000000
--- a/dts/src/arm/imx6qdl-colibri-v1_1-uhs.dtsi
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Copyright 2020 Toradex
- */
-
-&iomuxc {
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
- >;
- };
-};
-
-/* Colibri MMC */
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
- vmmc-supply = <&reg_module_3v3>;
- vqmmc-supply = <&vgen3_reg>;
- wakeup-source;
- keep-power-in-suspend;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
-};
diff --git a/dts/src/arm/imx6qdl-colibri.dtsi b/dts/src/arm/imx6qdl-colibri.dtsi
index 4e2a309c93..c383e0e411 100644
--- a/dts/src/arm/imx6qdl-colibri.dtsi
+++ b/dts/src/arm/imx6qdl-colibri.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
@@ -13,13 +13,79 @@
backlight: backlight {
compatible = "pwm-backlight";
+ brightness-levels = <0 127 191 223 239 247 251 255>;
+ default-brightness-level = <1>;
+ enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
+ power-supply = <&reg_module_3v3>;
pwms = <&pwm3 0 5000000>;
- enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
status = "disabled";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ debounce-interval = <10>;
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ lcd_display: disp0 {
+ compatible = "fsl,imx-parallel-display";
+ interface-pix-fmt = "bgr666";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0>;
+ };
+
+ panel_dpi: panel-dpi {
+ /*
+ * edt,et057090dhu: EDT 5.7" LCD TFT
+ * edt,et070080dh6: EDT 7.0" LCD TFT
+ */
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+ status = "disabled";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
regulator-name = "+V3.3";
@@ -38,36 +104,36 @@
reg_usb_host_vbus: regulator-usb-host-vbus {
compatible = "regulator-fixed";
+ gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
- regulator-name = "usb_host_vbus";
- regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb_host_vbus";
status = "disabled";
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
- model = "imx6dl-colibri-sgtl5000";
- ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HP_OUT",
"LINE_IN", "Line In Jack",
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias";
+ model = "imx6dl-colibri-sgtl5000";
mux-int-port = <1>;
mux-ext-port = <5>;
+ ssi-controller = <&ssi1>;
};
/* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
sound_spdif: sound-spdif {
compatible = "fsl,imx-audio-spdif";
- model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
spdif-out;
+ model = "imx-spdif";
status = "disabled";
};
};
@@ -92,6 +158,10 @@
status = "disabled";
};
+&clks {
+ fsl,pmic-stby-poweroff;
+};
+
/* Colibri SSP */
&ecspi4 {
cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
@@ -101,10 +171,10 @@
};
&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
phy-handle = <&ethphy>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
status = "okay";
mdio {
@@ -118,6 +188,224 @@
};
};
+&gpio1 {
+ gpio-line-names = "",
+ "SODIMM_67",
+ "SODIMM_180",
+ "SODIMM_196",
+ "SODIMM_174",
+ "SODIMM_176",
+ "SODIMM_194",
+ "SODIMM_55",
+ "SODIMM_63",
+ "SODIMM_28",
+ "SODIMM_93",
+ "SODIMM_69",
+ "SODIMM_99",
+ "SODIMM_130",
+ "SODIMM_106",
+ "SODIMM_98",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_190",
+ "SODIMM_51",
+ "SODIMM_47",
+ "SODIMM_53",
+ "",
+ "SODIMM_22";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_132",
+ "SODIMM_134",
+ "SODIMM_135",
+ "SODIMM_133",
+ "SODIMM_102",
+ "SODIMM_43",
+ "SODIMM_127",
+ "SODIMM_37",
+ "SODIMM_104",
+ "SODIMM_59",
+ "SODIMM_30",
+ "SODIMM_100",
+ "SODIMM_38",
+ "SODIMM_34",
+ "SODIMM_32",
+ "SODIMM_36",
+ "SODIMM_59",
+ "SODIMM_67",
+ "SODIMM_97",
+ "SODIMM_79",
+ "SODIMM_103",
+ "SODIMM_101",
+ "SODIMM_45",
+ "SODIMM_105",
+ "SODIMM_107",
+ "SODIMM_91",
+ "SODIMM_89",
+ "SODIMM_150",
+ "SODIMM_126",
+ "SODIMM_128",
+ "",
+ "SODIMM_94";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_111",
+ "SODIMM_113",
+ "SODIMM_115",
+ "SODIMM_117",
+ "SODIMM_119",
+ "SODIMM_121",
+ "SODIMM_123",
+ "SODIMM_125",
+ "SODIMM_110",
+ "SODIMM_112",
+ "SODIMM_114",
+ "SODIMM_116",
+ "SODIMM_118",
+ "SODIMM_120",
+ "SODIMM_122",
+ "SODIMM_124",
+ "",
+ "SODIMM_96",
+ "SODIMM_77",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_88",
+ "SODIMM_90",
+ "SODIMM_31",
+ "SODIMM_23",
+ "SODIMM_29",
+ "SODIMM_71",
+ "SODIMM_73",
+ "SODIMM_92",
+ "SODIMM_81",
+ "SODIMM_131",
+ "SODIMM_129";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_168",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_184",
+ "SODIMM_186",
+ "HDMI_15",
+ "HDMI_16",
+ "SODIMM_178",
+ "SODIMM_188",
+ "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "SODIMM_24",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_95",
+ "",
+ "SODIMM_86",
+ "",
+ "SODIMM_65",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_136",
+ "SODIMM_138",
+ "SODIMM_140",
+ "SODIMM_142",
+ "SODIMM_144",
+ "SODIMM_146",
+ "SODIMM_172",
+ "SODIMM_170",
+ "SODIMM_149",
+ "SODIMM_151",
+ "SODIMM_153",
+ "SODIMM_155",
+ "SODIMM_157",
+ "SODIMM_159",
+ "SODIMM_161",
+ "SODIMM_163",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_165",
+ "SODIMM_167";
+};
+
+&gpio6 {
+ gpio-line-names = "SODIMM_169",
+ "SODIMM_171",
+ "SODIMM_173",
+ "SODIMM_175",
+ "SODIMM_177",
+ "SODIMM_179",
+ "SODIMM_85",
+ "SODIMM_166",
+ "SODIMM_160",
+ "SODIMM_162",
+ "SODIMM_158",
+ "SODIMM_164",
+ "",
+ "",
+ "SODIMM_156",
+ "SODIMM_75",
+ "SODIMM_154",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_152";
+};
+
+&gpio7 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_19",
+ "SODIMM_21",
+ "",
+ "SODIMM_137";
+};
+
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_ddc>;
@@ -132,65 +420,66 @@
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-0 = <&pinctrl_i2c2_gpio>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
- pmic: pfuze100@8 {
+ pmic: pmic@8 {
compatible = "fsl,pfuze100";
+ fsl,pmic-stby-poweroff;
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1875000>;
+ regulator-min-microvolt = <300000>;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1875000>;
+ regulator-min-microvolt = <300000>;
regulator-ramp-delay = <6250>;
};
sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1975000>;
+ regulator-min-microvolt = <400000>;
};
swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5150000>;
+ regulator-min-microvolt = <5000000>;
};
snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <1000000>;
};
vref_reg: vrefddr {
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
};
/* vgen1: unused */
vgen2_reg: vgen2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1550000>;
+ regulator-min-microvolt = <800000>;
};
/*
@@ -198,57 +487,58 @@
* the i.MX 6 NVCC_SD1.
*/
vgen3_reg: vgen3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
vgen4_reg: vgen4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
};
vgen5_reg: vgen5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
};
};
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
- reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
+ lrclk-strength = <3>;
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_module_3v3_audio>;
VDDIO-supply = <&reg_module_3v3>;
VDDD-supply = <&vgen4_reg>;
- lrclk-strength = <3>;
};
/* STMPE811 touch screen controller */
stmpe811@41 {
compatible = "st,stmpe811";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touch_int>;
- reg = <0x41>;
+ blocks = <0x5>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio6>;
interrupt-controller;
id = <0>;
- blocks = <0x5>;
irq-trigger = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch_int>;
+ reg = <0x41>;
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;
/* 12-bit ADC */
@@ -258,7 +548,7 @@
/* ADC converstion time: 80 clocks */
st,sample-time = <4>;
- stmpe_touchscreen {
+ stmpe_ts: stmpe_touchscreen {
compatible = "st,stmpe-ts";
/* 8 sample average control */
st,ave-ctrl = <3>;
@@ -273,9 +563,10 @@
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
+ status = "disabled";
};
- stmpe_adc {
+ stmpe_adc: stmpe_adc {
compatible = "st,stmpe-adc";
/* forbid to use ADC channels 3-0 (touch) */
st,norequest-mask = <0x0F>;
@@ -294,6 +585,21 @@
scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
+
+ atmel_mxt_ts: touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ interrupt-parent = <&gpio2>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_atmel_conn>;
+ reg = <0x4a>;
+ reset-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */
+ status = "disabled";
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
};
/* Colibri PWM<B> */
@@ -338,27 +644,27 @@
/* Colibri UART_A */
&uart1 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
- fsl,dte-mode;
uart-has-rtscts;
status = "disabled";
};
/* Colibri UART_B */
&uart2 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_dte>;
- fsl,dte-mode;
uart-has-rtscts;
status = "disabled";
};
/* Colibri UART_C */
&uart3 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_dte>;
- fsl,dte-mode;
status = "disabled";
};
@@ -370,24 +676,28 @@
/* Colibri MMC */
&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
- disable-wp;
- vqmmc-supply = <&reg_module_3v3>;
bus-width = <4>;
no-1-8-v;
+ disable-wp;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
+ pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>;
+ vmmc-supply = <&reg_module_3v3>;
+ vqmmc-supply = <&vgen3_reg>;
status = "disabled";
};
/* eMMC */
&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- vqmmc-supply = <&reg_module_3v3>;
bus-width = <8>;
no-1-8-v;
non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ vqmmc-supply = <&reg_module_3v3>;
status = "okay";
};
@@ -405,14 +715,36 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh_oc_1>;
+ /* Atmel MXT touchsceen + Capacitive Touch Adapter */
+ /* NOTE: This pin group conflicts with pin groups
+ * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously.
+ */
+ pinctrl_atmel_adap: atmeladaptergrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */
+ >;
+ };
+
+ /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
+ /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and
+ * pinctrl_weim_cs2. Don't use them simultaneously.
+ */
+ pinctrl_atmel_conn: atmelconnectorgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */
+ >;
+ };
+
pinctrl_audmux: audmuxgrp {
fsl,pins = <
+ /* SGTL5000 sys_mclk */
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
- /* SGTL5000 sys_mclk */
- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
>;
};
@@ -423,28 +755,52 @@
>;
};
+ /* CSI pins used as GPIOs */
+ pinctrl_csi_gpio_1: csigpio1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0
+ MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_csi_gpio_2: csigpio2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0
+ >;
+ };
+
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
+ /* SPI CS */
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
- /* SPI CS */
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
>;
};
@@ -462,13 +818,32 @@
>;
};
- pinctrl_gpio_bl_on: gpioblon {
+ pinctrl_gpio_1: gpio1grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
+ >;
+ };
+ pinctrl_gpio_2: gpio2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
>;
};
- pinctrl_gpio_keys: gpiokeys {
+ pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
>;
@@ -483,15 +858,15 @@
pinctrl_i2c2: i2c2grp {
fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
>;
};
- pinctrl_i2c2_gpio: i2c2grp {
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
>;
};
@@ -523,8 +898,8 @@
MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
/* Disable PWM pins on camera interface */
- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
+ MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
>;
};
@@ -555,19 +930,34 @@
>;
};
- pinctrl_mic_gnd: gpiomicgnd {
+ pinctrl_lvds_transceiver: lvdstxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */
+ >;
+ };
+
+ pinctrl_mic_gnd: micgndgrp {
fsl,pins = <
/* Controls Mic GND, PU or '1' pull Mic GND to GND */
MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
>;
};
- pinctrl_mmc_cd: gpiommccd {
+ pinctrl_mmc_cd: mmccdgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
>;
};
+ pinctrl_mmc_cd_sleep: mmccdslpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0
+ >;
+ };
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
@@ -576,15 +966,15 @@
pinctrl_pwm2: pwm2grp {
fsl,pins = <
- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
@@ -601,13 +991,6 @@
>;
};
- pinctrl_usbh_oc_1: usbhoc1grp {
- fsl,pins = <
- /* USBH_OC */
- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
- >;
- };
-
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
@@ -650,9 +1033,9 @@
pinctrl_uart2_dte: uart2dtegrp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
>;
};
@@ -667,20 +1050,27 @@
fsl,pins = <
/* USBC_DET */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
- /* USBC_DET_EN */
- MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
/* USBC_DET_OVERWRITE */
MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
+ /* USBC_DET_EN */
+ MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
>;
};
- pinctrl_usbc_id_1: usbc_id-1 {
+ pinctrl_usbc_id_1: usbcid1grp {
fsl,pins = <
/* USBC_ID */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
>;
};
+ pinctrl_usbh_oc_1: usbhoc1grp {
+ fsl,pins = <
+ /* USBH_OC */
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
@@ -692,6 +1082,40 @@
>;
};
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
+ >;
+ };
+
+ /* avoid backfeeding with removed card power */
+ pinctrl_usdhc1_sleep: usdhc1sleepgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000
+ >;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
@@ -730,135 +1154,136 @@
>;
};
- pinctrl_weim_sram: weimsramgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
- /* Data */
- MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
- MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
- MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
- MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
- MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
- MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
- MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
- MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
- MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
- MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
- MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
- MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
- MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
- MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
- MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
- MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
- /* Address */
- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
- >;
- };
-
- pinctrl_weim_rdnwr: weimrdnwr {
- fsl,pins = <
- MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
- MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
- >;
- };
-
- pinctrl_weim_npwe: weimnpwe {
- fsl,pins = <
- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
- MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
- >;
- };
-
/* ADDRESS[16:18] [25] used as GPIO */
- pinctrl_weim_gpio_1: weimgpio-1 {
+ pinctrl_weim_gpio_1: weimgpio1grp {
fsl,pins = <
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
>;
};
/* ADDRESS[19:24] used as GPIO */
- pinctrl_weim_gpio_2: weimgpio-2 {
+ pinctrl_weim_gpio_2: weimgpio2grp {
fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
>;
};
/* DATA[16:31] used as GPIO */
- pinctrl_weim_gpio_3: weimgpio-3 {
+ pinctrl_weim_gpio_3: weimgpio3grp {
fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
- MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
>;
};
/* DQM[0:3] used as GPIO */
- pinctrl_weim_gpio_4: weimgpio-4 {
+ pinctrl_weim_gpio_4: weimgpio4grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
- MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
>;
};
/* RDY used as GPIO */
- pinctrl_weim_gpio_5: weimgpio-5 {
+ pinctrl_weim_gpio_5: weimgpio5grp {
fsl,pins = <
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
>;
};
/* ADDRESS[16] DATA[30] used as GPIO */
- pinctrl_weim_gpio_6: weimgpio-6 {
+ pinctrl_weim_gpio_6: weimgpio6grp {
fsl,pins = <
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_weim_npwe: weimnpwegrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
+ >;
+ };
+
+ pinctrl_weim_sram: weimsramgrp {
+ fsl,pins = <
+ /* Data */
+ MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
+ /* Address */
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ /* Ctrl */
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_rdnwr: weimrdnwrgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
+ MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
>;
};
};
diff --git a/dts/src/arm/imx6qdl-dfi-fs700-m60.dtsi b/dts/src/arm/imx6qdl-dfi-fs700-m60.dtsi
index 648f5fcb72..2c1d6f28e6 100644
--- a/dts/src/arm/imx6qdl-dfi-fs700-m60.dtsi
+++ b/dts/src/arm/imx6qdl-dfi-fs700-m60.dtsi
@@ -35,7 +35,7 @@
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf040b", "jedec,spi-nor";
diff --git a/dts/src/arm/imx6qdl-kontron-samx6i.dtsi b/dts/src/arm/imx6qdl-kontron-samx6i.dtsi
index b167b33bd1..095c9143d9 100644
--- a/dts/src/arm/imx6qdl-kontron-samx6i.dtsi
+++ b/dts/src/arm/imx6qdl-kontron-samx6i.dtsi
@@ -258,7 +258,7 @@
status = "okay";
/* default boot source: workaround #1 for errata ERR006282 */
- smarc_flash: spi-flash@0 {
+ smarc_flash: flash@0 {
compatible = "winbond,w25q16dw", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
diff --git a/dts/src/arm/imx6qdl-nit6xlite.dtsi b/dts/src/arm/imx6qdl-nit6xlite.dtsi
index ac34709e97..0ad4cb4f1e 100644
--- a/dts/src/arm/imx6qdl-nit6xlite.dtsi
+++ b/dts/src/arm/imx6qdl-nit6xlite.dtsi
@@ -179,7 +179,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi
index c96f4d7e1e..beaa2dcd43 100644
--- a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi
+++ b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi
@@ -321,7 +321,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi
index 92d09a3ebe..ee7e2371f9 100644
--- a/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi
+++ b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi
@@ -252,7 +252,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6qdl-nitrogen6x.dtsi b/dts/src/arm/imx6qdl-nitrogen6x.dtsi
index 49da30d751..904d5d051d 100644
--- a/dts/src/arm/imx6qdl-nitrogen6x.dtsi
+++ b/dts/src/arm/imx6qdl-nitrogen6x.dtsi
@@ -237,7 +237,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
index 1f2ba6f625..768bc0e3a2 100644
--- a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
+++ b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
@@ -47,12 +47,12 @@
pinctrl-0 = <&pinctrl_leds>;
compatible = "gpio-leds";
- green {
+ led_green: green {
label = "phyflex:green";
gpios = <&gpio1 30 0>;
};
- red {
+ led_red: red {
label = "phyflex:red";
gpios = <&gpio2 31 0>;
};
diff --git a/dts/src/arm/imx6qdl-sabreauto.dtsi b/dts/src/arm/imx6qdl-sabreauto.dtsi
index 5e58740d40..1368a47620 100644
--- a/dts/src/arm/imx6qdl-sabreauto.dtsi
+++ b/dts/src/arm/imx6qdl-sabreauto.dtsi
@@ -272,7 +272,7 @@
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
status = "disabled"; /* pin conflict with WEIM NOR */
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
diff --git a/dts/src/arm/imx6qdl-sabrelite.dtsi b/dts/src/arm/imx6qdl-sabrelite.dtsi
index eb9a0b104f..901b9a761b 100644
--- a/dts/src/arm/imx6qdl-sabrelite.dtsi
+++ b/dts/src/arm/imx6qdl-sabrelite.dtsi
@@ -313,7 +313,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6qdl-sabresd.dtsi b/dts/src/arm/imx6qdl-sabresd.dtsi
index 0c0105468a..37482a9023 100644
--- a/dts/src/arm/imx6qdl-sabresd.dtsi
+++ b/dts/src/arm/imx6qdl-sabresd.dtsi
@@ -197,7 +197,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
diff --git a/dts/src/arm/imx6qdl-sr-som.dtsi b/dts/src/arm/imx6qdl-sr-som.dtsi
index f86efd0ccc..ce543e325c 100644
--- a/dts/src/arm/imx6qdl-sr-som.dtsi
+++ b/dts/src/arm/imx6qdl-sr-som.dtsi
@@ -83,6 +83,16 @@
qca,clk-out-frequency = <125000000>;
qca,smarteee-tw-us-1g = <24>;
};
+
+ /*
+ * ADIN1300 (som rev 1.9 or later) is always at address 1. It
+ * will be enabled automatically by U-Boot if detected.
+ */
+ ethernet-phy@1 {
+ reg = <1>;
+ adi,phy-output-clock = "125mhz-free-running";
+ status = "disabled";
+ };
};
};
diff --git a/dts/src/arm/imx6qdl-tx6.dtsi b/dts/src/arm/imx6qdl-tx6.dtsi
index bcc5bbcce7..f41f86a76e 100644
--- a/dts/src/arm/imx6qdl-tx6.dtsi
+++ b/dts/src/arm/imx6qdl-tx6.dtsi
@@ -264,11 +264,6 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET_REF>,
- <&clks IMX6QDL_CLK_ENET_REF>;
- clock-names = "ipg", "ahb", "ptp", "enet_out";
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
phy-reset-post-delay = <10>;
diff --git a/dts/src/arm/imx6qdl-udoo.dtsi b/dts/src/arm/imx6qdl-udoo.dtsi
index ccfa8e320b..93a8123da2 100644
--- a/dts/src/arm/imx6qdl-udoo.dtsi
+++ b/dts/src/arm/imx6qdl-udoo.dtsi
@@ -295,7 +295,7 @@
pinctrl-0 = <&pinctrl_usbh>;
vbus-supply = <&reg_usb_h1_vbus>;
clocks = <&clks IMX6QDL_CLK_CKO>;
- status = "okay";
+ status = "disabled";
};
&usbotg {
diff --git a/dts/src/arm/imx6qdl-vicut1-12inch.dtsi b/dts/src/arm/imx6qdl-vicut1-12inch.dtsi
new file mode 100644
index 0000000000..f505f27045
--- /dev/null
+++ b/dts/src/arm/imx6qdl-vicut1-12inch.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021 Protonic Holland
+ */
+
+/ {
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+ autorepeat;
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ panel {
+ compatible = "kyo,tcg121xglp";
+ backlight = <&backlight_lcd>;
+ power-supply = <&reg_3v3>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&rgmii_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Microchip KSZ9031RNX PHY */
+ rgmii_phy: ethernet-phy@0 {
+ reg = <0>;
+ interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <300>;
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
+ "CAM2_MIRROR", "", "", "SMBALERT",
+ "DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
+ "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
+ "SD1_DATA3", "ETH_MDIO", "",
+ "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
+ "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR",
+ "CAN2_SR", "CAN2_TX", "CAN2_RX",
+ "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL",
+ "HITCH_IN_OUT",
+ "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "",
+ "ISB_LED";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET",
+ "I2S_BITCLK", "I2S_DOUT",
+ "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
+ "YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
+};
+
+&gpio6 {
+ gpio-line-names =
+ "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5",
+ "ITU656_D6", "ITU656_D7", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2",
+ "RGMII_TD3",
+ "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1",
+ "RGMII_RD2", "RGMII_RD3", "", "";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
+ /* Phy reset */
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
+ >;
+ };
+
+ pinctrl_gpiokeys: gpiokeygrp {
+ fsl,pins = <
+ /* nON_SWITCH */
+ MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6qdl-vicut1.dtsi b/dts/src/arm/imx6qdl-vicut1.dtsi
index 1ac7e13249..a1676b5d29 100644
--- a/dts/src/arm/imx6qdl-vicut1.dtsi
+++ b/dts/src/arm/imx6qdl-vicut1.dtsi
@@ -16,18 +16,27 @@
stdout-path = &uart4;
};
- backlight: backlight {
+ backlight_lcd: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm1 0 5000000 0>;
brightness-levels = <0 16 64 255>;
num-interpolated-steps = <16>;
- default-brightness-level = <1>;
+ default-brightness-level = <48>;
power-supply = <&reg_3v3>;
enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
};
+ backlight_led: backlight_led {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 5000000 0>;
+ brightness-levels = <0 16 64 255>;
+ num-interpolated-steps = <16>;
+ default-brightness-level = <48>;
+ power-supply = <&reg_3v3>;
+ };
+
connector {
compatible = "composite-video-connector";
label = "Composite0";
@@ -61,54 +70,37 @@
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
};
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
-
- power {
- label = "Power Button";
- gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
- label = "LED_DI0_DEBUG_0";
+ label = "debug0";
function = LED_FUNCTION_HEARTBEAT;
- gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-1 {
- label = "LED_DI0_DEBUG_1";
+ label = "debug1";
function = LED_FUNCTION_DISK;
- gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "disk-activity";
};
led-2 {
- label = "POWER_LED";
+ label = "power_led";
function = LED_FUNCTION_POWER;
gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- };
-
- panel {
- compatible = "kyo,tcg121xglp";
- backlight = <&backlight>;
- power-supply = <&reg_3v3>;
- port {
- panel_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
+ led-3 {
+ label = "isb_led";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
};
};
@@ -135,18 +127,6 @@
enable-active-high;
};
- reg_wifi: regulator-wifi {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wifi_npd>;
- regulator-name = "wifi";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <70000>;
- };
-
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "prti6q-sgtl5000";
@@ -173,6 +153,14 @@
frame-master;
};
};
+
+ thermal-zones {
+ chassis-thermal {
+ polling-delay = <20000>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&tsens0>;
+ };
+ };
};
&audmux {
@@ -232,47 +220,13 @@
};
};
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii-id";
- phy-handle = <&rgmii_phy>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* Microchip KSZ9031RNX PHY */
- rgmii_phy: ethernet-phy@0 {
- reg = <0>;
- interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <300>;
- };
- };
-};
-
-&gpio1 {
- gpio-line-names =
- "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
- "CAM2_MIRROR", "", "", "SMBALERT",
- "DEBUG_0", "DEBUG_1", "SDIO_SCK", "SDIO_CMD", "SDIO_D3",
- "SDIO_D2", "SDIO_D1", "SDIO_D0",
- "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
- "SD1_DATA3", "", "",
- "", "ETH_RESET", "WIFI_PD", "WIFI_BT_RST", "ETH_INT", "",
- "WL_IRQ", "ETH_MDC";
-};
-
&gpio2 {
gpio-line-names =
- "count0", "count1", "count2", "", "", "", "", "",
- "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
- "BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
- "", "", "", "", "", "", "", "ON_SWITCH",
- "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", "";
+ "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "",
+ "", "LED_PWM", "", "", "",
+ "", "", "",
+ "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH",
+ "POWER_LED", "", "", "", "", "", "", "";
};
&gpio3 {
@@ -281,37 +235,8 @@
"", "", "", "", "", "", "", "",
"ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
"CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names =
- "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
- "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR",
- "CAN2_SR", "CAN2_TX", "CAN2_RX",
- "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "",
- "", "", "", "", "BL_EN", "BL_PWM", "", "";
-};
-
-&gpio5 {
- gpio-line-names =
- "", "", "", "", "", "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_W_DIS",
- "PCIE_RESET", "", "", "", "", "", "", "",
- "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET",
- "I2S_BITCLK", "I2S_DOUT",
- "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
- "YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
-};
-
-&gpio6 {
- gpio-line-names =
- "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5",
- "ITU656_D6", "ITU656_D7", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2",
- "RGMII_TD3",
- "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1",
- "RGMII_RD2", "RGMII_RD3", "", "";
+ "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0",
+ "YACO_RESET";
};
&gpio7 {
@@ -406,9 +331,10 @@
reg = <0x51>;
};
- temperature-sensor@70 {
+ tsens0: temperature-sensor@70 {
compatible = "ti,tmp103";
reg = <0x70>;
+ #thermal-sensor-cells = <0>;
};
};
@@ -438,13 +364,15 @@
};
};
-&pcie {
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
-&pwm1 {
+&pwm3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
+ pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
@@ -460,12 +388,6 @@
status = "okay";
};
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
@@ -513,26 +435,6 @@
status = "okay";
};
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- vmmc-supply = <&reg_wifi>;
- non-removable;
- cap-power-off-card;
- keep-power-in-suspend;
- no-1-8-v;
- no-mmc;
- no-sd;
- status = "okay";
-
- wifi {
- compatible = "ti,wl1271";
- interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
- ref-clock-frequency = "38400000";
- tcxo-clock-frequency = "19200000";
- };
-};
-
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
@@ -613,29 +515,6 @@
>;
};
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
- /* Phy reset */
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
- >;
- };
-
pinctrl_hog: hoggrp {
fsl,pins = <
/* ITU656_nRESET */
@@ -646,8 +525,6 @@
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0
/* CAM_nDETECT */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
- /* nON_SWITCH */
- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0
/* ISB_IN1 */
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
/* ISB_nIN2 */
@@ -669,27 +546,11 @@
/* ITU656_nPDN */
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
- /* HW revision detect */
- /* REV_ID0 */
- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
- /* REV_ID1 */
- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
- /* REV_ID2 */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
- /* REV_ID3 */
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
- /* REV_ID4 */
- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
-
/* New in HW revision 1 */
/* ON1_FB */
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0
/* DIP1_FB */
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
-
- /* New in UT2: FIXME: ISB PWM should start off, PD */
- /* ISB_LED_PWM */
- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x130b0
>;
};
@@ -729,6 +590,8 @@
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0
/* POWER_LED */
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0
+ /* ISB_LED */
+ MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0
>;
};
@@ -738,20 +601,17 @@
>;
};
- /* YaCO AUX Uart */
- pinctrl_uart1: uart1grp {
+ pinctrl_pwm3: pwm3grp {
fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
>;
};
- pinctrl_uart2: uart2grp {
+ /* YaCO AUX Uart */
+ pinctrl_uart1: uart1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
@@ -797,19 +657,6 @@
>;
};
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
- /* WL12xx IRQ */
- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880
- >;
- };
-
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
@@ -825,10 +672,4 @@
MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
>;
};
-
- pinctrl_wifi_npd: wifinpdgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0
- >;
- };
};
diff --git a/dts/src/arm/imx6qp-vicutp.dts b/dts/src/arm/imx6qp-vicutp.dts
index 7bad7ca6b1..49ff145fff 100644
--- a/dts/src/arm/imx6qp-vicutp.dts
+++ b/dts/src/arm/imx6qp-vicutp.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-vicut1.dtsi"
+#include "imx6qdl-vicut1-12inch.dtsi"
/ {
model = "Kverneland UT1P Board";
diff --git a/dts/src/arm/imx6sl-evk.dts b/dts/src/arm/imx6sl-evk.dts
index 25f6f2fb15..f16c830f1e 100644
--- a/dts/src/arm/imx6sl-evk.dts
+++ b/dts/src/arm/imx6sl-evk.dts
@@ -137,7 +137,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi
index c7d907c5c3..06a515121d 100644
--- a/dts/src/arm/imx6sl.dtsi
+++ b/dts/src/arm/imx6sl.dtsi
@@ -50,7 +50,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
diff --git a/dts/src/arm/imx6sx-nitrogen6sx.dts b/dts/src/arm/imx6sx-nitrogen6sx.dts
index 66af78e83b..a2c79bcf9a 100644
--- a/dts/src/arm/imx6sx-nitrogen6sx.dts
+++ b/dts/src/arm/imx6sx-nitrogen6sx.dts
@@ -107,7 +107,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6sx-sdb-reva.dts b/dts/src/arm/imx6sx-sdb-reva.dts
index dce5dcf96c..7dda42553f 100644
--- a/dts/src/arm/imx6sx-sdb-reva.dts
+++ b/dts/src/arm/imx6sx-sdb-reva.dts
@@ -123,7 +123,7 @@
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
- flash0: s25fl128s@0 {
+ flash0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
@@ -133,7 +133,7 @@
spi-tx-bus-width = <4>;
};
- flash1: s25fl128s@2 {
+ flash1: flash@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/src/arm/imx6sx-sdb.dts b/dts/src/arm/imx6sx-sdb.dts
index 99f4cf777a..969cfe920d 100644
--- a/dts/src/arm/imx6sx-sdb.dts
+++ b/dts/src/arm/imx6sx-sdb.dts
@@ -108,7 +108,7 @@
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
- flash0: n25q256a@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
@@ -118,7 +118,7 @@
reg = <0>;
};
- flash1: n25q256a@2 {
+ flash1: flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
diff --git a/dts/src/arm/imx6ul-14x14-evk.dtsi b/dts/src/arm/imx6ul-14x14-evk.dtsi
index a3fde3316c..1a18c41ce3 100644
--- a/dts/src/arm/imx6ul-14x14-evk.dtsi
+++ b/dts/src/arm/imx6ul-14x14-evk.dtsi
@@ -286,7 +286,7 @@
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
- flash0: n25q256a@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
diff --git a/dts/src/arm/imx6ul-kontron-n6310-som.dtsi b/dts/src/arm/imx6ul-kontron-n6310-som.dtsi
index 47d3ce5d25..acd936540d 100644
--- a/dts/src/arm/imx6ul-kontron-n6310-som.dtsi
+++ b/dts/src/arm/imx6ul-kontron-n6310-som.dtsi
@@ -19,7 +19,7 @@
};
&qspi {
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
diff --git a/dts/src/arm/imx6ul-kontron-n6311-som.dtsi b/dts/src/arm/imx6ul-kontron-n6311-som.dtsi
index a095a7654a..29ed38dce5 100644
--- a/dts/src/arm/imx6ul-kontron-n6311-som.dtsi
+++ b/dts/src/arm/imx6ul-kontron-n6311-som.dtsi
@@ -18,7 +18,7 @@
};
&qspi {
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
diff --git a/dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi b/dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi
index 770f59b231..a6cf0f21c6 100644
--- a/dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi
+++ b/dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi
@@ -178,7 +178,7 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
- fsl,uart-has-rtscts;
+ uart-has-rtscts;
status = "okay";
};
diff --git a/dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi b/dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi
index 2a449a3c1a..09a83dbdf6 100644
--- a/dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi
+++ b/dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi
@@ -19,7 +19,7 @@
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
diff --git a/dts/src/arm/imx6ul-phytec-segin-peb-av-02.dtsi b/dts/src/arm/imx6ul-phytec-segin-peb-av-02.dtsi
index 205e4d4627..ec042648bd 100644
--- a/dts/src/arm/imx6ul-phytec-segin-peb-av-02.dtsi
+++ b/dts/src/arm/imx6ul-phytec-segin-peb-av-02.dtsi
@@ -11,7 +11,7 @@
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <5>;
power-supply = <&reg_backlight_en>;
- pwms = <&pwm3 0 5000000>;
+ pwms = <&pwm3 0 5000000 0>;
status = "disabled";
};
@@ -91,7 +91,6 @@
};
&pwm3 {
- #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
diff --git a/dts/src/arm/imx6ul-tqma6ul-common.dtsi b/dts/src/arm/imx6ul-tqma6ul-common.dtsi
new file mode 100644
index 0000000000..eca94ed645
--- /dev/null
+++ b/dts/src/arm/imx6ul-tqma6ul-common.dtsi
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/*
+ * Common for
+ * - TQMa6ULx
+ * - TQMa6ULxL
+ * - TQMa6ULLx
+ * - TQMa6ULLxL
+ */
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_recovery>;
+ scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pfuze3000: pmic@8 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ reg_sw1a: sw1a {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-ramp-delay = <6250>;
+ /* not used */
+ };
+
+ reg_sw1b_core: sw1b {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ reg_sw2: sw2 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_sw3_ddr: sw3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_swbst: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ /* not used */
+ };
+
+ reg_snvs_3v0: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vrefddr: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vccsd: vccsd {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_v33_3v3: v33 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_vldo1_3v3: vldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ /* not used */
+ };
+
+ reg_vldo2: vldo2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ /* not used */
+ };
+
+ reg_vldo3: vldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ /* not used */
+ };
+
+ reg_vldo4: vldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ jc42_1a: eeprom-temperature-sensor@1a {
+ compatible = "nxp,se97", "jedec,jc-42.4-temp";
+ reg = <0x1a>;
+ };
+
+ m24c64_50: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ m24c02_52: eeprom@52 {
+ compatible = "nxp,se97b", "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ read-only;
+ };
+
+ rtc0: rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+
+ /*
+ * PMIC & temperature sensor IRQ
+ * Both do currently not use IRQ
+ * potentially dangerous if used on baseboard
+ */
+ pmic-int-hog {
+ gpio-hog;
+ gpios = <24 0>;
+ input;
+ };
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ flash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <33000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ reg = <0>;
+ };
+};
+
+/* eMMC */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz" , "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+
+ bus-width = <8>;
+ disable-wp;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4_recovery: i2c4recoverygrp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0
+ MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0
+ >;
+ };
+
+ pinctrl_pmic: pmic {
+ fsl,pins = <
+ /* PMIC irq */
+ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ul-tqma6ul1-mba6ulx.dts b/dts/src/arm/imx6ul-tqma6ul1-mba6ulx.dts
new file mode 100644
index 0000000000..f2a5f17f31
--- /dev/null
+++ b/dts/src/arm/imx6ul-tqma6ul1-mba6ulx.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-tqma6ul1.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board";
+ compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
+};
+
+/*
+ * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage)
+ * and need to be disabled here again
+ */
+&can2 {
+ status = "disabled";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ max-speed = <100>;
+ reg = <0>;
+ };
+ };
+};
+
+&fec2 {
+ /delete-property/ phy-handle;
+ /delete-node/ mdio;
+};
+
+&iomuxc {
+ pinctrl_enet1_mdc: enet1mdcgrp {
+ fsl,pins = <
+ /* mdio */
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ul-tqma6ul1.dtsi b/dts/src/arm/imx6ul-tqma6ul1.dtsi
new file mode 100644
index 0000000000..24192d012e
--- /dev/null
+++ b/dts/src/arm/imx6ul-tqma6ul1.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ul-tqma6ul2.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6UL1 SoM";
+ compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
+};
+
+/*
+ * There are no module specific differences compared to TQMa6UL2,
+ * only external interfaces differ
+ */
+
+/*
+ * Devices not available on i.MX6ULG1 and should not be enabled on
+ * mainboard level (again)
+ */
+&can2 {
+ status = "disabled";
+};
+
+&csi {
+ status = "disabled";
+};
+
+&fec2 {
+ status = "disabled";
+};
+
+&lcdif {
+ status = "disabled";
+};
diff --git a/dts/src/arm/imx6ul-tqma6ul2-mba6ulx.dts b/dts/src/arm/imx6ul-tqma6ul2-mba6ulx.dts
new file mode 100644
index 0000000000..0757df2b8f
--- /dev/null
+++ b/dts/src/arm/imx6ul-tqma6ul2-mba6ulx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-tqma6ul2.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board";
+ compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul";
+};
diff --git a/dts/src/arm/imx6ul-tqma6ul2.dtsi b/dts/src/arm/imx6ul-tqma6ul2.dtsi
new file mode 100644
index 0000000000..e2e95dd922
--- /dev/null
+++ b/dts/src/arm/imx6ul-tqma6ul2.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-tqma6ul-common.dtsi"
+#include "imx6ul-tqma6ulx-common.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6UL2 SoM";
+ compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul";
+};
+
+&usdhc2 {
+ fsl,tuning-step = <6>;
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ul-tqma6ul2l-mba6ulx.dts b/dts/src/arm/imx6ul-tqma6ul2l-mba6ulx.dts
new file mode 100644
index 0000000000..9d9b6b744a
--- /dev/null
+++ b/dts/src/arm/imx6ul-tqma6ul2l-mba6ulx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-tqma6ul2l.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board";
+ compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
+};
diff --git a/dts/src/arm/imx6ul-tqma6ul2l.dtsi b/dts/src/arm/imx6ul-tqma6ul2l.dtsi
new file mode 100644
index 0000000000..caf2c5d03f
--- /dev/null
+++ b/dts/src/arm/imx6ul-tqma6ul2l.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-tqma6ul-common.dtsi"
+#include "imx6ul-tqma6ulxl-common.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6UL2L SoM";
+ compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
+};
+
+&usdhc2 {
+ fsl,tuning-step= <6>;
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ul-tqma6ulx-common.dtsi b/dts/src/arm/imx6ul-tqma6ulx-common.dtsi
new file mode 100644
index 0000000000..5afb9046c2
--- /dev/null
+++ b/dts/src/arm/imx6ul-tqma6ulx-common.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/*
+ * Common for
+ * - TQMa6ULx
+ * - TQMa6ULLx
+ */
+
+&m24c64_50 {
+ vcc-supply = <&reg_sw2>;
+};
+
+&m24c02_52 {
+ vcc-supply = <&reg_sw2>;
+};
+
+&reg_sw2 {
+ regulator-boot-on;
+ regulator-always-on;
+};
+
+/* eMMC */
+&usdhc2 {
+ vmmc-supply = <&reg_sw2>;
+ vqmmc-supply = <&reg_vldo4>;
+};
+
+&iomuxc {
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ul-tqma6ulxl-common.dtsi b/dts/src/arm/imx6ul-tqma6ulxl-common.dtsi
new file mode 100644
index 0000000000..ba84a4f70e
--- /dev/null
+++ b/dts/src/arm/imx6ul-tqma6ulxl-common.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/*
+ * Common for
+ * - TQMa6ULxL
+ * - TQMa6ULLxL
+ */
+
+/ {
+ reg_vin: reg-vin {
+ compatible = "regulator-fixed";
+ regulator-name = "VIN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&m24c64_50 {
+ vcc-supply = <&reg_vin>;
+};
+
+&m24c02_52 {
+ vcc-supply = <&reg_vin>;
+};
+
+/* eMMC */
+&usdhc2 {
+ vmmc-supply = <&reg_vin>;
+ vqmmc-supply = <&reg_vldo4>;
+};
+
+&iomuxc {
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ull-colibri-aster.dts b/dts/src/arm/imx6ull-colibri-aster.dts
new file mode 100644
index 0000000000..d3f2fb7c6c
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-aster.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-aster",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-colibri-aster.dtsi b/dts/src/arm/imx6ull-colibri-aster.dtsi
new file mode 100644
index 0000000000..c9133ba2d7
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-aster.dtsi
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <&reg_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&ecspi1 {
+ status = "okay";
+
+ num-cs = <2>;
+ cs-gpios = <
+ &gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */
+ &gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */
+ >;
+};
+
+/*
+ * Following SODIMM Pins should not be accessed as GPIO on Aster board:
+ * 134 - AIN5_SCL (no connection)
+ * 127 - Voltage Level Translator OE# signal (IC11 and IC12)
+ *
+ * To configure GPIO to LED5, please disable FEC2 and uncomment the following:
+ * &iomuxc {
+ * pinctrl-names = "default";
+ * pinctrl-0 = <
+ * &pinctrl_gpio1
+ * &pinctrl_gpio2
+ * &pinctrl_gpio3
+ * &pinctrl_gpio4
+ * &pinctrl_gpio6 - for non-WiFi modules only
+ * &pinctrl_gpio7
+ * &pinctrl_gpio_aster
+ * >;
+ *
+ * pinctrl_gpio_aster: gpio-aster {
+ * fsl,pins = <
+ * MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0
+ * >;
+ * };
+ * };
+ */
+
+&i2c1 {
+ status = "okay";
+
+ m41t0m6: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ vmmc-supply = <&reg_3v3>;
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-colibri-emmc-aster.dts b/dts/src/arm/imx6ull-colibri-emmc-aster.dts
new file mode 100644
index 0000000000..919c0464d6
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-emmc-aster.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-emmc-aster",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/dts/src/arm/imx6ull-colibri-emmc-iris-v2.dts b/dts/src/arm/imx6ull-colibri-emmc-iris-v2.dts
new file mode 100644
index 0000000000..b9060c2f79
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-emmc-iris-v2.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-iris-v2",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/dts/src/arm/imx6ull-colibri-emmc-iris.dts b/dts/src/arm/imx6ull-colibri-emmc-iris.dts
new file mode 100644
index 0000000000..0ab71f2f5d
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-emmc-iris.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-emmc-iris",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/dts/src/arm/imx6ull-colibri-emmc-nonwifi.dtsi b/dts/src/arm/imx6ull-colibri-emmc-nonwifi.dtsi
index a099abfdfa..ea238525d5 100644
--- a/dts/src/arm/imx6ull-colibri-emmc-nonwifi.dtsi
+++ b/dts/src/arm/imx6ull-colibri-emmc-nonwifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2021 Toradex
+ * Copyright 2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
@@ -8,7 +8,7 @@
/ {
aliases {
mmc0 = &usdhc2; /* eMMC */
- mmc1 = &usdhc1; /* MMC 4bit slot */
+ mmc1 = &usdhc1; /* MMC 4-bit slot */
};
memory@80000000 {
@@ -154,6 +154,7 @@
"SODIMM_127";
};
+/* NAND */
&gpmi {
status = "disabled";
};
@@ -170,6 +171,7 @@
pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};
+/* eMMC */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2emmc>;
diff --git a/dts/src/arm/imx6ull-colibri-eval-v3.dts b/dts/src/arm/imx6ull-colibri-eval-v3.dts
index 08669a1834..9bf7111d7b 100644
--- a/dts/src/arm/imx6ull-colibri-eval-v3.dts
+++ b/dts/src/arm/imx6ull-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
/dts-v1/;
@@ -9,6 +9,6 @@
#include "imx6ull-colibri-eval-v3.dtsi"
/ {
- model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3";
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull";
};
diff --git a/dts/src/arm/imx6ull-colibri-eval-v3.dtsi b/dts/src/arm/imx6ull-colibri-eval-v3.dtsi
index a78849fd2a..e29907428c 100644
--- a/dts/src/arm/imx6ull-colibri-eval-v3.dtsi
+++ b/dts/src/arm/imx6ull-colibri-eval-v3.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017 Toradex AG
+ * Copyright 2017-2022 Toradex
*/
/ {
@@ -8,20 +8,6 @@
stdout-path = "serial0:115200n8";
};
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
-
- power {
- label = "Wake-Up";
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
/* fixed crystal dedicated to mcp2515 */
clk16m: clk16m {
compatible = "fixed-clock";
@@ -29,18 +15,6 @@
clock-frequency = <16000000>;
};
- panel: panel {
- compatible = "edt,et057090dhu";
- backlight = <&bl>;
- power-supply = <&reg_3v3>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lcdif_out>;
- };
- };
- };
-
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3.3V";
@@ -71,14 +45,6 @@
status = "okay";
};
-&bl {
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- power-supply = <&reg_3v3>;
- pwms = <&pwm4 0 5000000 1>;
- status = "okay";
-};
-
&ecspi1 {
status = "okay";
@@ -107,16 +73,6 @@
};
};
-&lcdif {
- status = "okay";
-
- port {
- lcdif_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
/* PWM <A> */
&pwm4 {
status = "okay";
@@ -150,6 +106,7 @@
};
&usbotg1 {
+ vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};
@@ -159,20 +116,6 @@
};
&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
- pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>;
- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- disable-wp;
- wakeup-source;
- keep-power-in-suspend;
vmmc-supply = <&reg_3v3>;
- vqmmc-supply = <&reg_sd1_vmmc>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
status = "okay";
};
diff --git a/dts/src/arm/imx6ull-colibri-iris-v2.dts b/dts/src/arm/imx6ull-colibri-iris-v2.dts
new file mode 100644
index 0000000000..afc1e01197
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-iris-v2.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-iris-v2",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&gpio1 {
+ /* This turns the LVDS transceiver on */
+ lvds-power-on {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+ line-name = "LVDS_POWER_ON";
+ output-high;
+ };
+};
+
+&gpio2 {
+ /*
+ * This switches the LVDS transceiver to the single-channel
+ * output mode.
+ */
+ lvds-ch-mode {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+ line-name = "LVDS_CH_MODE";
+ output-high;
+ };
+
+ /*
+ * This switches the LVDS transceiver to the 24-bit RGB mode.
+ */
+ lvds-rgb-mode {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+ line-name = "LVDS_RGB_MODE";
+ output-low;
+ };
+};
+
+&gpio5 {
+ /*
+ * This switches the LVDS transceiver to VESA color mapping mode.
+ */
+ lvds-color-map {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+ line-name = "LVDS_COLOR_MAP";
+ output-low;
+ };
+};
diff --git a/dts/src/arm/imx6ull-colibri-iris-v2.dtsi b/dts/src/arm/imx6ull-colibri-iris-v2.dtsi
new file mode 100644
index 0000000000..93649cad0c
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-iris-v2.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+};
+
+
+&usdhc1 {
+ cap-power-off-card;
+ vmmc-supply = <&reg_3v3_vmmc>;
+ /delete-property/ keep-power-in-suspend;
+ /delete-property/ no-1-8-v;
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-colibri-iris.dts b/dts/src/arm/imx6ull-colibri-iris.dts
new file mode 100644
index 0000000000..4fb97b0fe3
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-iris.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-iris",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-colibri-iris.dtsi b/dts/src/arm/imx6ull-colibri-iris.dtsi
new file mode 100644
index 0000000000..7f3b37baba
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-iris.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <&reg_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&gpio1 {
+ /*
+ * uart25_tx_on turns the UART transceiver on. If one wants to turn the
+ * transceiver off, that property has to be deleted and the gpio handled
+ * in userspace.
+ * The same applies to uart1_tx_on.
+ */
+ uart25_tx_on {
+ gpio-hog;
+ gpios = <15 0>;
+ output-high;
+ };
+};
+
+&gpio2 {
+ uart1_tx_on {
+ gpio-hog;
+ gpios = <7 0>;
+ output-high;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ m41t0m6: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ vmmc-supply = <&reg_3v3>;
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-colibri-nonwifi.dtsi b/dts/src/arm/imx6ull-colibri-nonwifi.dtsi
index 95a11b8bcb..88901db255 100644
--- a/dts/src/arm/imx6ull-colibri-nonwifi.dtsi
+++ b/dts/src/arm/imx6ull-colibri-nonwifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
@@ -12,13 +12,150 @@
};
};
+&gpio1 {
+ gpio-line-names = "SODIMM_8",
+ "SODIMM_6",
+ "SODIMM_129",
+ "SODIMM_89",
+ "SODIMM_19",
+ "SODIMM_21",
+ "UNUSABLE_SODIMM_180",
+ "UNUSABLE_SODIMM_184",
+ "SODIMM_4",
+ "SODIMM_2",
+ "SODIMM_106",
+ "SODIMM_71",
+ "SODIMM_23",
+ "SODIMM_31",
+ "SODIMM_99",
+ "SODIMM_102",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_36",
+ "SODIMM_38",
+ "SODIMM_32",
+ "SODIMM_34",
+ "SODIMM_135",
+ "SODIMM_77",
+ "SODIMM_100",
+ "SODIMM_186",
+ "SODIMM_196",
+ "SODIMM_194";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_55",
+ "SODIMM_63",
+ "SODIMM_178",
+ "SODIMM_188",
+ "SODIMM_73",
+ "SODIMM_30",
+ "SODIMM_67",
+ "SODIMM_104",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_190",
+ "SODIMM_47",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_51",
+ "SODIMM_53";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_29",
+ "SODIMM_37",
+ "SODIMM_88",
+ "SODIMM_86",
+ "SODIMM_92",
+ "SODIMM_90";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_59",
+ "",
+ "",
+ "SODIMM_133",
+ "",
+ "SODIMM_28",
+ "SODIMM_75",
+ "SODIMM_96",
+ "SODIMM_81",
+ "SODIMM_94",
+ "SODIMM_101",
+ "SODIMM_103",
+ "SODIMM_79",
+ "SODIMM_97",
+ "SODIMM_69",
+ "SODIMM_98",
+ "SODIMM_85",
+ "SODIMM_65";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_43",
+ "SODIMM_45",
+ "SODIMM_137",
+ "SODIMM_95",
+ "SODIMM_107",
+ "SODIMM_131",
+ "SODIMM_93",
+ "",
+ "SODIMM_138",
+ "",
+ "SODIMM_105",
+ "SODIMM_127";
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;
+ &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7>;
};
&iomuxc_snvs {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>;
+ pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};
diff --git a/dts/src/arm/imx6ull-colibri-wifi-aster.dts b/dts/src/arm/imx6ull-colibri-wifi-aster.dts
new file mode 100644
index 0000000000..b4f65e8c58
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-wifi-aster.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-wifi-aster",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-colibri-wifi-eval-v3.dts b/dts/src/arm/imx6ull-colibri-wifi-eval-v3.dts
index df72ce1ae2..1d64d1a5d8 100644
--- a/dts/src/arm/imx6ull-colibri-wifi-eval-v3.dts
+++ b/dts/src/arm/imx6ull-colibri-wifi-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
/dts-v1/;
diff --git a/dts/src/arm/imx6ull-colibri-wifi-iris-v2.dts b/dts/src/arm/imx6ull-colibri-wifi-iris-v2.dts
new file mode 100644
index 0000000000..ce02f8a9dd
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-wifi-iris-v2.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-wifi-iris-v2",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&gpio1 {
+ /* This turns the LVDS transceiver on */
+ lvds-power-on {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+ line-name = "LVDS_POWER_ON";
+ output-high;
+ };
+};
+
+&gpio2 {
+ /*
+ * This switches the LVDS transceiver to the single-channel
+ * output mode.
+ */
+ lvds-ch-mode {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+ line-name = "LVDS_CH_MODE";
+ output-high;
+ };
+
+ /*
+ * This switches the LVDS transceiver to the 24-bit RGB mode.
+ */
+ lvds-rgb-mode {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+ line-name = "LVDS_RGB_MODE";
+ output-low;
+ };
+};
+
+&gpio5 {
+ /*
+ * This switches the LVDS transceiver to VESA color mapping mode.
+ */
+ lvds-color-map {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+ line-name = "LVDS_COLOR_MAP";
+ output-low;
+ };
+};
diff --git a/dts/src/arm/imx6ull-colibri-wifi-iris.dts b/dts/src/arm/imx6ull-colibri-wifi-iris.dts
new file mode 100644
index 0000000000..5ac1aa298c
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-wifi-iris.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-wifi-iris",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-colibri-wifi.dtsi b/dts/src/arm/imx6ull-colibri-wifi.dtsi
index 9f1e38282b..db59ee6b1c 100644
--- a/dts/src/arm/imx6ull-colibri-wifi.dtsi
+++ b/dts/src/arm/imx6ull-colibri-wifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
@@ -23,16 +23,152 @@
clock-frequency = <792000000>;
};
+&gpio1 {
+ gpio-line-names = "SODIMM_8",
+ "SODIMM_6",
+ "SODIMM_129",
+ "",
+ "SODIMM_19",
+ "SODIMM_21",
+ "UNUSABLE_SODIMM_180",
+ "UNUSABLE_SODIMM_184",
+ "SODIMM_4",
+ "SODIMM_2",
+ "SODIMM_106",
+ "SODIMM_71",
+ "SODIMM_23",
+ "SODIMM_31",
+ "SODIMM_99",
+ "SODIMM_102",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_36",
+ "SODIMM_38",
+ "SODIMM_32",
+ "SODIMM_34",
+ "SODIMM_135",
+ "SODIMM_77",
+ "SODIMM_100",
+ "SODIMM_186",
+ "SODIMM_196",
+ "SODIMM_194";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_55",
+ "SODIMM_63",
+ "SODIMM_178",
+ "SODIMM_188",
+ "SODIMM_73",
+ "SODIMM_30",
+ "SODIMM_67",
+ "SODIMM_104",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_190",
+ "SODIMM_47",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_51",
+ "SODIMM_53";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_29",
+ "SODIMM_37",
+ "SODIMM_88",
+ "SODIMM_86",
+ "SODIMM_92",
+ "SODIMM_90";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_59",
+ "",
+ "",
+ "SODIMM_133",
+ "",
+ "SODIMM_28",
+ "SODIMM_75",
+ "SODIMM_96",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_69",
+ "SODIMM_98",
+ "SODIMM_85",
+ "SODIMM_65";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_43",
+ "SODIMM_45",
+ "SODIMM_137",
+ "SODIMM_95",
+ "SODIMM_107",
+ "SODIMM_131",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_105";
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>;
+ &pinctrl_gpio4 &pinctrl_gpio7>;
};
&iomuxc_snvs {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>;
+ pinctrl-0 = <&pinctrl_snvs_gpio1>;
};
&usdhc2 {
diff --git a/dts/src/arm/imx6ull-colibri.dtsi b/dts/src/arm/imx6ull-colibri.dtsi
index 951a2a6c5a..15621e03fa 100644
--- a/dts/src/arm/imx6ull-colibri.dtsi
+++ b/dts/src/arm/imx6ull-colibri.dtsi
@@ -1,22 +1,54 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018-2021 Toradex
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull.dtsi"
/ {
+ /* Ethernet aliases to ensure correct MAC addresses */
aliases {
ethernet0 = &fec2;
ethernet1 = &fec1;
};
- bl: backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
- enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- status = "disabled";
+ power-supply = <&reg_3v3>;
+ pwms = <&pwm4 0 5000000 1>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ wakeup {
+ debounce-interval = <10>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ panel_dpi: panel-dpi {
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+ power-supply = <&reg_3v3>;
+ status = "okay";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
};
reg_module_3v3: regulator-module-3v3 {
@@ -35,7 +67,7 @@
regulator-max-microvolt = <3300000>;
};
- reg_sd1_vmmc: regulator-sd1-vmmc {
+ reg_sd1_vqmmc: regulator-sd1-vqmmc {
compatible = "regulator-gpio";
gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@@ -47,11 +79,25 @@
states = <1800000 0x1 3300000 0x0>;
vin-supply = <&reg_module_3v3>;
};
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed-clock";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "+V3.3_ETH";
+ regulator-type = "voltage";
+ vin-supply = <&reg_module_3v3>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ startup-delay-us = <150000>;
+ };
};
&adc1 {
num-channels = <10>;
vref-supply = <&reg_module_3v3_avdd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
};
&can1 {
@@ -73,12 +119,14 @@
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};
+/* Ethernet */
&fec2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet2>;
pinctrl-1 = <&pinctrl_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
+ phy-supply = <&reg_eth_phy>;
status = "okay";
mdio {
@@ -93,9 +141,11 @@
};
};
+/* NAND */
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
@@ -103,15 +153,35 @@
status = "okay";
};
+/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_atmel_conn>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
+ status = "disabled";
+ };
};
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
&i2c2 {
+ /* Use low frequency to compensate for the high pull-up values. */
+ clock-frequency = <40000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
@@ -119,7 +189,7 @@
scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
- ad7879@2c {
+ ad7879_ts: touchscreen@2c {
compatible = "adi,ad7879-1";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
@@ -140,23 +210,33 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
};
+/* PWM <A> */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
};
+/* PWM <B> */
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
};
+/* PWM <C> */
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
};
+/* PWM <D> */
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
@@ -170,6 +250,7 @@
status = "disabled";
};
+/* Colibri UART_A */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
@@ -177,6 +258,7 @@
fsl,dte-mode;
};
+/* Colibri UART_B */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@@ -184,12 +266,14 @@
fsl,dte-mode;
};
+/* Colibri UART_C */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,dte-mode;
};
+/* Colibri USBC */
&usbotg1 {
dr_mode = "otg";
srp-disable;
@@ -197,14 +281,28 @@
adp-disable;
};
+/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
};
+/* Colibri MMC/SD */
&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>;
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
+ bus-width = <4>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
+ disable-wp;
+ keep-power-in-suspend;
+ no-1-8-v;
+ vqmmc-supply = <&reg_sd1_vqmmc>;
+ wakeup-source;
};
&wdog1 {
@@ -214,13 +312,36 @@
};
&iomuxc {
- pinctrl_can_int: canint-grp {
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
+ >;
+ };
+
+ pinctrl_atmel_adap: atmeladapgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */
+ MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */
+ >;
+ };
+
+ pinctrl_atmel_conn: atmelconngrp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
+ >;
+ };
+
+ pinctrl_can_int: canintgrp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
>;
};
- pinctrl_enet2: enet2-grp {
+ pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
@@ -235,7 +356,7 @@
>;
};
- pinctrl_enet2_sleep: enet2sleepgrp {
+ pinctrl_enet2_sleep: enet2-sleepgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
@@ -250,13 +371,13 @@
>;
};
- pinctrl_ecspi1_cs: ecspi1-cs-grp {
+ pinctrl_ecspi1_cs: ecspi1csgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */
>;
};
- pinctrl_ecspi1: ecspi1-grp {
+ pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */
@@ -264,27 +385,27 @@
>;
};
- pinctrl_flexcan1: flexcan1-grp {
+ pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
>;
};
- pinctrl_flexcan2: flexcan2-grp {
+ pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
>;
};
- pinctrl_gpio_bl_on: gpio-bl-on-grp {
+ pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */
>;
};
- pinctrl_gpio1: gpio1-grp {
+ pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */
@@ -297,7 +418,7 @@
>;
};
- pinctrl_gpio2: gpio2-grp { /* Camera */
+ pinctrl_gpio2: gpio2grp { /* Camera */
fsl,pins = <
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */
MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
@@ -307,26 +428,20 @@
>;
};
- pinctrl_gpio3: gpio3-grp { /* CAN2 */
+ pinctrl_gpio3: gpio3grp { /* CAN2 */
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */
MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */
>;
};
- pinctrl_gpio4: gpio4-grp {
+ pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
>;
};
- pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
- fsl,pins = <
- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
- >;
- };
-
- pinctrl_gpio6: gpio6-grp { /* Wifi pins */
+ pinctrl_gpio6: gpio6grp { /* Wifi pins */
fsl,pins = <
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */
@@ -338,7 +453,7 @@
>;
};
- pinctrl_gpio7: gpio7-grp { /* CAN1 */
+ pinctrl_gpio7: gpio7grp { /* CAN1 */
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */
MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
@@ -347,9 +462,9 @@
/*
* With an eMMC instead of a raw NAND device the following pins
- * are available at SODIMM pins
+ * are available at SODIMM pins.
*/
- pinctrl_gpmi_gpio: gpmi-gpio-grp {
+ pinctrl_gpmi_gpio: gpmigpiogrp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */
MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */
@@ -358,7 +473,7 @@
>;
};
- pinctrl_gpmi_nand: gpmi-nand-grp {
+ pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
@@ -377,35 +492,35 @@
>;
};
- pinctrl_i2c1: i2c1-grp {
+ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */
>;
};
- pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ pinctrl_i2c1_gpio: i2c1-gpiogrp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
>;
};
- pinctrl_i2c2: i2c2-grp {
+ pinctrl_i2c2: i2c2grp {
fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
>;
};
- pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
- MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
+ MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
>;
};
- pinctrl_lcdif_dat: lcdif-dat-grp {
+ pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */
@@ -428,7 +543,7 @@
>;
};
- pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */
@@ -437,31 +552,31 @@
>;
};
- pinctrl_pwm4: pwm4-grp {
+ pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */
>;
};
- pinctrl_pwm5: pwm5-grp {
+ pinctrl_pwm5: pwm5grp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */
>;
};
- pinctrl_pwm6: pwm6-grp {
+ pinctrl_pwm6: pwm6grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */
>;
};
- pinctrl_pwm7: pwm7-grp {
+ pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */
>;
};
- pinctrl_uart1: uart1-grp {
+ pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */
MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */
@@ -470,16 +585,16 @@
>;
};
- pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
+ pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */
fsl,pins = <
- MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */
- MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */
- MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */
- MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */
>;
};
- pinctrl_uart2: uart2-grp {
+ pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */
@@ -487,23 +602,23 @@
MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */
>;
};
- pinctrl_uart5: uart5-grp {
+ pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */
MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
>;
};
- pinctrl_usbh_reg: gpio-usbh-reg {
+ pinctrl_usbh_reg: usbhreggrp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */
>;
};
- pinctrl_usdhc1: usdhc1-grp {
+ pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
@@ -511,10 +626,10 @@
>;
};
- pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@@ -522,25 +637,25 @@
>;
};
- pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
- pinctrl_usdhc2: usdhc2-grp {
+ pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069
- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17069
+ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
>;
@@ -561,7 +676,7 @@
>;
};
- pinctrl_wdog: wdog-grp {
+ pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
@@ -569,65 +684,59 @@
};
&iomuxc_snvs {
- pinctrl_snvs_gpio1: snvs-gpio1-grp {
+ pinctrl_snvs_gpio1: snvsgpio1grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
- MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
>;
};
- pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
- fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
- >;
- };
-
- pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
+ pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
>;
};
- pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
+ pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
>;
};
- pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
+ pinctrl_snvs_reg_sd: snvsregsdgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
>;
};
- pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
+ pinctrl_snvs_usbc_det: snvsusbcdetgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
>;
};
- pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
+ pinctrl_snvs_gpiokeys: snvsgpiokeysgrp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */
>;
};
- pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
+ pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */
>;
};
- pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp {
+ pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
>;
};
- pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
+ pinctrl_snvs_wifi_pdn: snvswifipdngrp {
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
>;
diff --git a/dts/src/arm/imx6ull-kontron-n6411-som.dtsi b/dts/src/arm/imx6ull-kontron-n6411-som.dtsi
index b7e984284e..d000606c07 100644
--- a/dts/src/arm/imx6ull-kontron-n6411-som.dtsi
+++ b/dts/src/arm/imx6ull-kontron-n6411-som.dtsi
@@ -18,7 +18,7 @@
};
&qspi {
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
diff --git a/dts/src/arm/imx6ull-phytec-tauri-emmc.dts b/dts/src/arm/imx6ull-phytec-tauri-emmc.dts
new file mode 100644
index 0000000000..14adb87da9
--- /dev/null
+++ b/dts/src/arm/imx6ull-phytec-tauri-emmc.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Alexander Bauer <a.bauer@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull-phytec-tauri.dtsi"
+
+/ {
+ model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
+ compatible = "phytec,imx6ull-phygate-tauri",
+ "phytec,imx6ull-phygate-tauri-emmc",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+/* EMMC-Version */
+&usdhc2 {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-phytec-tauri-nand.dts b/dts/src/arm/imx6ull-phytec-tauri-nand.dts
new file mode 100644
index 0000000000..ae396ac634
--- /dev/null
+++ b/dts/src/arm/imx6ull-phytec-tauri-nand.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Alexander Bauer <a.bauer@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull-phytec-tauri.dtsi"
+
+/ {
+ model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
+ compatible = "phytec,imx6ull-phygate-tauri",
+ "phytec,imx6ull-phygate-tauri-nand",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+/* NAND-Version */
+&gpmi {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-phytec-tauri.dtsi b/dts/src/arm/imx6ull-phytec-tauri.dtsi
new file mode 100644
index 0000000000..5464a52a1f
--- /dev/null
+++ b/dts/src/arm/imx6ull-phytec-tauri.dtsi
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Alexander Bauer <a.bauer@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+
+/ {
+
+ model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
+ compatible = "phytec,imx6ull-phygate-tauri",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+
+ aliases {
+ rtc0 = &i2c_rtc;
+ rtc1 = &snvs_rtc;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-key";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key {
+ label = "KEY-A";
+ gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ wakeup-source;
+ };
+ };
+
+ reg_adc1_vref_3v3: regulator-vref-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_s25fl064_hold: regulator-s25fl064-hold {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_s25fl064_hold>;
+ compatible = "regulator-fixed";
+ regulator-name = "s25fl064_hold";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usb_hub_vbus: regulator-hub-otg1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbhubpwr>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_hub_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1pwr>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ user_leds: user-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_user_leds>,
+ <&pinctrl_user_leds_snvs>;
+
+ user-led1 {
+ label = "yellow";
+ gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "off";
+ };
+
+ user-led2 {
+ label = "red";
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "off";
+ };
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>,
+ <&pinctrl_ecspi1_cs>;
+ cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>,
+ <&gpio3 10 GPIO_ACTIVE_LOW>,
+ <&gpio3 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm_tis: tpm@1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm>;
+ compatible = "tcg,tpm_tis-spi";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ s25fl064: flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = " jedec,spi-nor";
+ reg = <2>;
+ spi-max-frequency = <40000000>;
+ m25p,fast-read;
+ status = "disabled";
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ dmas = <&sdma 7 8 0>,
+ <&sdma 8 8 0>;
+ dma-names = "rx", "tx";
+ status = "okay";
+};
+
+&ethphy1 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy2>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ tmp102: tmp@49 {
+ compatible = "ti,tmp102";
+ reg = <0x49>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tempsense>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ i2c_rtc: rtc@68 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc_int>;
+ compatible = "microcrystal,rv4162";
+ reg = <0x68>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&mdio {
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <1>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ status = "okay";
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm6>;
+ status = "okay";
+};
+
+&pwm7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm7>;
+ status = "okay";
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* UART4 * RS485 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+ rs485-rts-active-high;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+/* UART5 * RS232 */
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7>;
+ status = "okay";
+};
+
+/* USB */
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usb_hub_vbus>;
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "disabled";
+};
+
+&iomuxc_snvs {
+ pinctrl_rtc_int: rtcintgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
+ >;
+ };
+
+ pinctrl_stmpe: stmpegrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
+ >;
+ };
+
+ pinctrl_tempsense: tempsensegrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
+ >;
+ };
+
+ pinctrl_tpm: tpmgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
+ >;
+ };
+
+ pinctrl_usbhubpwr: usbhubpwrgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059
+ >;
+ };
+
+ pinctrl_user_leds_snvs: user_ledsgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
+ >;
+ };
+};
+
+&iomuxc {
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */
+ MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1
+ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1
+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1
+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1csgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0
+ MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0
+ MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0
+ >;
+ };
+
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0
+ MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0
+ >;
+ };
+
+ princtrl_flexcan2_en: flexcan2engrp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0
+ MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0
+ MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0
+ MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0
+ MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0
+ MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0
+ >;
+ };
+
+ pinctrl_pwm6: pwm6grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0
+ >;
+ };
+
+ pinctrl_pwm7: pwm7grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0
+ >;
+ };
+
+ pinctrl_s25fl064_hold: s25fl064holdgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
+ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
+ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
+ MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
+ MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1
+ MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart7: uart7grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1
+ MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80
+ >;
+ };
+
+ pinctrl_usbotg1pwr: usbotg1pwrgrp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_user_leds: userledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ull-tqma6ull2-mba6ulx.dts b/dts/src/arm/imx6ull-tqma6ull2-mba6ulx.dts
new file mode 100644
index 0000000000..e593b7036f
--- /dev/null
+++ b/dts/src/arm/imx6ull-tqma6ull2-mba6ulx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ull-tqma6ull2.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board";
+ compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
+};
diff --git a/dts/src/arm/imx6ull-tqma6ull2.dtsi b/dts/src/arm/imx6ull-tqma6ull2.dtsi
new file mode 100644
index 0000000000..326e6da91e
--- /dev/null
+++ b/dts/src/arm/imx6ull-tqma6ull2.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-tqma6ul-common.dtsi"
+#include "imx6ul-tqma6ulx-common.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6ULL2 SoM";
+ compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
+};
+
+&usdhc2 {
+ fsl,tuning-step= <6>;
+ /* Errata ERR010450 Workaround */
+ max-frequency = <99000000>;
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ull-tqma6ull2l-mba6ulx.dts b/dts/src/arm/imx6ull-tqma6ull2l-mba6ulx.dts
new file mode 100644
index 0000000000..33437aae98
--- /dev/null
+++ b/dts/src/arm/imx6ull-tqma6ull2l-mba6ulx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ull-tqma6ull2l.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board";
+ compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
+};
diff --git a/dts/src/arm/imx6ull-tqma6ull2l.dtsi b/dts/src/arm/imx6ull-tqma6ull2l.dtsi
new file mode 100644
index 0000000000..8e4d5cd186
--- /dev/null
+++ b/dts/src/arm/imx6ull-tqma6ull2l.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-tqma6ul-common.dtsi"
+#include "imx6ul-tqma6ulxl-common.dtsi"
+
+/ {
+ model = "TQ Systems TQMa6ULL2L SoM";
+ compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
+};
+
+&usdhc2 {
+ fsl,tuning-step= <6>;
+ /* Errata ERR010450 Workaround */
+ max-frequency = <99000000>;
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+};
diff --git a/dts/src/arm/imx7d-smegw01.dts b/dts/src/arm/imx7d-smegw01.dts
new file mode 100644
index 0000000000..c6b32064a0
--- /dev/null
+++ b/dts/src/arm/imx7d-smegw01.dts
@@ -0,0 +1,469 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright (C) 2020 PHYTEC Messtechnik GmbH
+// Author: Jens Lang <J.Lang@phytec.de>
+// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx7d.dtsi"
+
+/ {
+ model = "Storopack SMEGW01 board";
+ compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
+
+ aliases {
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc3;
+ mmc2 = &usdhc2;
+ rtc0 = &i2c_rtc;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reg_lte_on: regulator-lte-on {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lte_on>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "lte_on";
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_lte_nreset: regulator-lte-nreset {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lte_nreset>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "LTE_nReset";
+ gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_wifi: regulator-wifi {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi>;
+ regulator-name = "wifi_reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_wlan_rfkill: regulator-wlan-rfkill {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-2 = <&pinctrl_rfkill>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "wlan_rfkill";
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usbotg_vbus: regulator-usbotg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ sram@0 {
+ compatible = "microchip,48l640";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <16000000>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ };
+
+ ethphy1: ethernet-phy@2 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+ };
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy1>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ i2c_rtc: rtc@52 {
+ compatible = "microcrystal,rv3028";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc_int>;
+ reg = <0x52>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
+ dr_mode = "otg";
+ vbus-supply = <&reg_usbotg_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg2>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ non-removable;
+ cap-sd-highspeed;
+ sd-uhs-ddr50;
+ mmc-ddr-1_8v;
+ vmmc-supply = <&reg_wifi>;
+ enable-sdio-wakeup;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+ assigned-clock-rates = <400000000>;
+ max-frequency = <200000000>;
+ bus-width = <8>;
+ fsl,tuning-step = <1>;
+ non-removable;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04
+ MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04
+ MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04
+ MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
+ MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
+ MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
+ MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5
+ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5
+ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5
+ MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5
+ MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5
+ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5
+ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5
+ MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5
+ MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5
+ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
+ MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004
+ MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0
+ MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0
+ MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0
+ >;
+ };
+
+ pinctrl_lte_on: lteongrp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059
+ >;
+ };
+
+ pinctrl_lte_nreset: ltenresetgrp {
+ fsl,pins = <
+ MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059
+ >;
+ };
+
+ pinctrl_rfkill: rfkillrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059
+ >;
+ };
+
+ pinctrl_rtc_int: rtcintgrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c
+ MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74
+ >;
+ };
+
+ pinctrl_usbotg1_lpsr: usbotg1 {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04
+ >;
+ };
+
+ pinctrl_usbotg1_pwr: usbotg1-pwr {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04
+ >;
+ };
+
+ pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04
+ >;
+ };
+
+ pinctrl_usbotg2: usbotg2grp {
+ fsl,pins = <
+ MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x04
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_CLK__SD2_CLK 0x19
+ MX7D_PAD_SD2_CMD__SD2_CMD 0x59
+ MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
+ MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
+ MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
+ MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
+ MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
+ >;
+ };
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04
+ MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
+ >;
+ };
+};
diff --git a/dts/src/arm/imx7s.dtsi b/dts/src/arm/imx7s.dtsi
index 5af6d58666..008e3da460 100644
--- a/dts/src/arm/imx7s.dtsi
+++ b/dts/src/arm/imx7s.dtsi
@@ -446,7 +446,7 @@
status = "disabled";
};
- iomuxc_lpsr: iomuxc-lpsr@302c0000 {
+ iomuxc_lpsr: pinctrl@302c0000 {
compatible = "fsl,imx7d-iomuxc-lpsr";
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;
diff --git a/dts/src/arm/imxrt1050-evk.dts b/dts/src/arm/imxrt1050-evk.dts
new file mode 100644
index 0000000000..6a9c10decf
--- /dev/null
+++ b/dts/src/arm/imxrt1050-evk.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1050.dtsi"
+#include "imxrt1050-pinfunc.h"