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* ARM: psci: implement PSCI client driverAhmad Fatoum2019-11-072-0/+191
| | | | | | | | | | | | System reset on the STM32MP may be done via PSCI when running TF-A as first-stage boot loader. Provide a PSCI driver to simplify using it: - A psci_invoke function is exported, so other code can use it - A fixup for the PSCI device tree node is registered - A reset and poweroff handler via PSCI is registered for PSCI >= v0.2 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: wire in smc command helpAhmad Fatoum2019-11-071-2/+4
| | | | | | | | | | | | | The smc command has a help defined, but unused. Wire it in, so help smc and smc -invalidoption work as expected. While at it, remove the unimplemented -z option. It's unneeded, because -c turns off the CPU after starting it again already. Also it seems it's not implementable without interprocessor communication, which is probably overkill here. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: use CONFIG_ARM_PSCI_DEBUG for smc commandAhmad Fatoum2019-11-071-1/+1
| | | | | | | | | There's already an option to use when debugging PSCI. Instead of requiring users to #define DEBUG 1 as well, have the smc command be usable when CONFIG_ARM_PSCI_DEBUG, not DEBUG is defined. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: translate PSCI error codes in smc commandAhmad Fatoum2019-11-071-1/+37
| | | | | | | | | | For more usability, translate CPU_ON error codes into the error descriptions found in the PSCI Platform Design Document[1]. [1]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mxs'Sascha Hauer2019-10-171-1/+13
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| * ARM: start: Allow to pass machine type as boarddataSascha Hauer2019-10-021-1/+13
| | | | | | | | | | | | | | | | Allow to pass a machine type number as directly as boarddata. This makes it easy for non device tree boards to pass a machine type and to identify themselves during runtime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: use client domain permissions to support ARMv7 eXecute NeverAhmad Fatoum2019-10-143-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual notes[1]: > When using the Short-descriptor translation table format, the XN > attribute is not checked for domains marked as Manager. > Therefore, the system must not include read-sensitive memory in > domains marked as Manager, because the XN bit does not prevent > speculative fetches from a Manager domain. To avoid speculative access to read-sensitive memory-mapped peripherals on ARMv7, let's use client domain permissions for all memory, so the XN bit (and also R/W bits) can function. This aligns us with what Linux is doing on ARMv7. This fixes cache corruption instances that had been observed on the i.MX6UL(L) when the instruction prefetcher speculates into memory following the end of a 512M SDRAM[2]. While this is not necessary to avoid speculative accesses on < ARMv7, we could probably have everything there in client domain as well, but due to lack of test coverage, we'll restrict the change to ARMv7. [1]: B3.7.2 - Execute-never restrictions on instruction fetching [2]: "Cache Corruption on MX6UL(L)": https://community.nxp.com/thread/511925 Fixes: 0198567c4 ("ARM: mmu: mark uncached regions as eXecute never on v7") Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: set R/W bits in ARMv7 translation tableAhmad Fatoum2019-10-141-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | With barebox using the manager permissions for domain 0 that's used for all page table entries and directories, we never had the need so far to explicitly set R/W bits. We did so anyway for sections in the early MMU code, but later on in the normal MMU setup, we didn't do so consistently. In preparation for switching to DOMAIN_CLIENT for ARMv7, configure R/W everywhere in normal MMU code as well. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: cache-armv7: remove duplicate domain initializationAhmad Fatoum2019-10-141-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | We already call set_domain each time we do __mmu_cache_on. Writing the DACR in the armv7 __mmu_cache_on is thus superfluous. Drop it. This changes existing behavior, whereas all 16 memory domains had the same access permissions set (manager) before, now only the first domain has. This is ok, as we only ever use domain 0 in barebox and on non-armv7, we don't bother with the other ones at all. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: cache-armv7: remove superfluous instructionAhmad Fatoum2019-10-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | There are two tst r11, #0xf with nothing in between them that changes r11. This a left over from the kernel code that checks for VMSA twice, once to check if the page table should be setup and once to more to flush the TLB. We do the setup in the caller already, so the tst serves no useful purpose. Delete one. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: remove no longer accurate commentAhmad Fatoum2019-10-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | This comment refers to the state of things prior to e3e54c644 ("ARM: mmu: Implement on-demand PTE allocation"). Since then, we no longer generate 2nd level page tables directly below. Remove it to avoid confusion. Cc: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: use system.h's get_cr() for cpuinfoAhmad Fatoum2019-10-141-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of open-coding the get_cr(), use the already available helper in <asm/system.h> same as we do for 64-bit ARMv8. The only difference is that the "memory" clobber is replaced by "cc". This is ok as we don't expect get_cr() to affect memory and because we do it elsewhere in barebox without a "memory" clobber already. While at it, move it out the #if/#else clause as the helper changes behavior depending on the same CONFIG option anyway. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: aarch64: Re-implement most of barebox_arm_entry() in assemblyAndrey Smirnov2019-10-014-10/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC9 now produces the following warning: common.h:51:2: warning: listing the stack pointer register ‘sp’ in a clobber list is deprecated [-Wdeprecated] 51 | __asm__ __volatile__("mov sp, %0" | ^~~~~~~ common.h:51:2: note: the value of the stack pointer after an ‘asm’ statement must be the same as it was before the statement Stack pointer was added to clobber list in commit f9fc8254b2 ("ARM: Mark SP as being clobbered in arm_setup_stack()") to prevent GCC from generating code that would corrupt 'boarddata' pointer by trying to restore it from invalid stack frame. Interestingly enough, seemingly unrelated change in commit 64d95896cf ("ARM: aarch64: compile with general-regs-only") changed generated code such that adding SP to clobber list became no longer necessary. While the above can probably be a fix by itself, it seems a better and more future proof approach would be to address the problem at its root and re-implement offending startup sequence in assembly. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Merge single pbl with multi pblSascha Hauer2019-10-015-111/+21
| | | | | | | | | | | | | | | | | | So far we have two different implementations for PBL: One for a single PBL and one for multiple images. This patch implements the single PBL case as a special case of the multi PBL case. With this the single PBL becomes a multi PBL image with the entry point start_pbl. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: drop bultin DTBSascha Hauer2019-10-011-6/+0
| | | | | | | | | | | | | | | | We can build multiple DTBs into the binary and board code can select which one to use. Drop the single builtin DTB and let the boards using it pass the correct one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: remove PBL_FORCE_PIGGYDATA_COPYSascha Hauer2019-09-231-13/+0
|/ | | | | | | This option is unused in the tree, remove it for now. If you need this option, let me know, we'll find another solution. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/qemu'Sascha Hauer2019-09-123-0/+148
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| * ARM: Add generic device tree 2nd stage supportSascha Hauer2019-08-193-0/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for building a barebox image that boots with the Linux ARM Kernel booting convention. Support for this image can be enabled in Kconfig. It picks up a device tree passed in r2. This new image helps for example with qemu. It can be started with: qemu-system-aarch64 -m 2G -M virt -kernel images/barebox-dt-2nd.img -cpu cortex-a57 -serial stdio or: qemu-system-arm -m 1G -M sabrelite -kernel images/barebox-dt-2nd.img -nographic -dtb arch/arm/dts/imx6q-sabrelite.dtb Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/fsanitize'Sascha Hauer2019-09-121-0/+1
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| * | Kconfig: create Kconfig symbol for ARCH_HAS_STACK_DUMPAhmad Fatoum2019-08-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Other arch-specific features are exposed in Kconfig too, so do here likewise. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/arm'Sascha Hauer2019-09-121-1/+1
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| * | ARM: Cleanup stack offset cargo cultSascha Hauer2019-09-091-1/+1
| |/ | | | | | | | | | | | | | | | | Most callers of arm_setup_stack substract a fixed offset of 8, 12 or 16 bytes from the stack top. This is unnecessary as on ARM we have a stack that decrements before storing values. Substracting this offset probably goes back to the U-Boot version we forked from. Stop this now. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | pbl: Move piggy verification into pbl_barebox_uncompress()Sascha Hauer2019-08-231-16/+1
| | | | | | | | | | | | | | | | piggy verification is a direct prerequisite of uncompressing the piggydata, so move the verification there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
* | ARM: aarch64: Fixup relocation table for the second relocationSascha Hauer2019-08-231-0/+2
|/ | | | | | | | In case we want to relocate the binary multiple times we have to adjust the relocation table itself for any further relocations. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
* Merge branch 'for-next/imx8-hab'Sascha Hauer2019-08-151-1/+16
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| * arm: uncompress: verify sha256 if enabledRouven Czerwinski2019-08-071-1/+16
| | | | | | | | | | | | | | | | | | Add piggydata verification before the ARM uncompress function. This calculates the sha256sum of the compressed barebox binary and only continues if the builtin sha256sum matches the calculated sha256sum. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: access __boot_cpu_mode with a functionSascha Hauer2019-08-074-4/+12
|/ | | | | | | | | | | | | | | | __boot_cpu_mode is accessed from barebox_multi_pbl_start() and barebox_single_pbl_start(). These functions may be called at an address different from the address they are linked at. Calculating the address of global variables can yield wrong results when it is done before setup_c() is called. We can't make sure when the address is calculated, OSELAS.Toolchain-2018.12.0 indeed calculates the address after setup_c() is called, but Debian arm-linux-gnueabihf-gcc 8.3.0 does it before setup_c() is called and thus doesn't work. This is solved by accessing __boot_cpu_mode with a wrapper function which we call explicitly after setup_c() is done. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32'Sascha Hauer2019-07-122-31/+4
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| * ARM: sm: move get_gicd_base_address to header for reuseAhmad Fatoum2019-07-041-28/+1
| | | | | | | | | | | | | | | | | | Incoming PSCI implementation for the STM32MP1 needs to get_gicd_base_address as well, so move it to gic.h to avoid code duplication. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: psci: fix erroneous call of ->system_reset on system_offAhmad Fatoum2019-07-041-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Both psci_system_reset and psci_system_off call psci_ops->system_reset, which seems like a copy-paste error as there is an unused ->system_off as well. Adjust psci_system_off to use ->system_off instead. This won't matter for the existing i.MX7 PSCI implementation because it defines neither callback, but it will for the upcoming STM32MP PSCI support. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | add CONFIG_PBL_BREAK optionOleksij Rempel2019-06-272-0/+15
|/ | | | | | | | With this option barebox will be build with breakpoint instruction in early pbl stage. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Initial OP-TEE supportSascha Hauer2019-06-073-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for OP-TEE, see https://www.op-tee.org/ barebox starts in secure mode as usual. When booting a kernel the bootm code also loads the optee_os binary. Instead of jumping into the kernel barebox jumps into the optee_os binary and puts the kernel execution address into the lr register. OP-TEE then jumps into the kernel in nonsecure mode. The optee_os binary is passed with the -t option to bootm or with global.bootm.tee. Optionally OP-TEE can be compiled into barebox using the builtin firmware feature. Enable the Kconfig option and place or link your tee binary as optee.bin into the firmware directory. The amount of SDRAM which is kept free for OP-TEE is configurable. This patch was tested on a i.MX6 Nitrogen6x board. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: factor out of_psci_fixup() to separate fileSascha Hauer2019-05-133-21/+61
| | | | | | | | | of_psci_fixup() can be used by code which doesn't use the barebox psci implementation, but provides its own PSCI compatible firmware. Factor it out to a separate file to compile it independently of the barebox PSCI implementation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: unify asm/arm-smccc.h and linux/arm-smccc.hSascha Hauer2019-05-133-10/+12
| | | | | | | | | | Since 2c20674f0c ("ARM: Add code to support SMCCC on AArch64") we have both arch/arm/include/asm/arm-smccc.h and include/linux/arm-smccc.h. The latter was introduced with Kernel commit 680a0873e ("arm: kernel: Add SMC structure parameter") included, so we have to add the parameter for ARM32 aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: introduce sync_caches_for_executionSascha Hauer2019-05-135-19/+23
| | | | | | | | | | | | | | | | | | | We have several places in the code which which prepares just modified code for execution. This is done differently in all the places, so add a common function to be used by all. Most places called arm_early_mmu_cache_flush(). This function includes invalidating the instruction cache, so doing it again is unnecessary. Sometimes we had arm_early_mmu_cache_flush() inside #ifdef CONFIG_MMU. The ifdef seems unnecessary since we do not have it consistently, so remove the ifdef. Some early i.MX xload code had icache_invalidate() but forgot to flush the caches. Replace the instruction cache invalidation with sync_caches_for_execution(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/arm'Sascha Hauer2019-05-105-11/+60
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| * ARM: mmu: mark uncached regions as eXecute never on v7Ahmad Fatoum2019-04-293-9/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM Cortex-A Series Programmer's Guide notes[1]: > When set, the Execute Never (XN) bit in the translation table entry > prevents speculative instruction fetches taking place from desired > memory locations and will cause a prefetch abort to occur if execution > from the memory location is attempted. > > Typically device memory regions are marked as execute never to prevent > accidental execution from such locations, and to prevent undesirable > side-effects which might be caused by speculative instruction fetches. Heed the advice and mark uncached memory with the XN bit, when the CPU is >=v7. It's possible that there are SoCs that have a section shared between device memory and the on-chip RAM hosting the PBL. In such a section, every page except for the OCRAM's should be mapped XN, but as we know of no SoC with such an OCRAM layout, we ignore this possibility for now and let mmu_early_enable map sections only. [1]: 9.6.3 "Execute Never", Version 4.0 Suggested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: mmu: remove doubly defined macroAhmad Fatoum2019-04-291-1/+0
| | | | | | | | | | | | | | | | PMD_SECT_DEF_CACHED is defined along with PMD_SECT_DEF_UNCACHED in mmu.h, which is included two lines prior. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: cache-armv7: start invalidation from outer levelsAhmad Fatoum2019-04-291-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 25/4/19 11:57, Lucas Stach wrote: > [T]he sequence that could go wrong in Barebox is as follows: > 1. CPU core starts invalidating at L1 cache level > 2. HW prefetcher decides that a specific address should be brought into > the L1 cache. > 3. HW prefetcher finds a valid block for the requested address in L2 > cache and moves cached data from L2 to L1. > 4. Only now CPU core invalidates L2 cache. > > In the above sequence we now have invalid data in the L1 cache line. > The correct sequence will avoid this issue: > > 1. CPU core starts invalidating at L2 cache level > 2. HW prefetcher decides that a specific address should be brought into > the L1 cache. > 3. HW prefetcher sees invalid tags for the requested address in L2 > cache and brings in the data from external memory. > 4. CPU core invalidates L1 cache, discarding the prefetched data. > The ARM Cortex-A Series Programmer's Guide addresses this issue in the SMP-context[1]: > If another core were to access the affected address between those > two actions, a coherency problem can occur. Such problems can be avoided > by following two simple rules. > > * When cleaning, always clean the innermost (L1) cache first and then > clean the outer cache(s). > * When invalidating, always invalidate the outermost cache first and > the L1 cache last. The current code correctly iterates from inner to outer cache levels when flushing/cleaning (r8 == 0), invalidation (r8 == 1) occurs in the same direction though. Adjust the invalidation iteration order to start from the outermost cache instead. Equivalent C-Code: enum cache_op { CACHE_FLUSH = 0, CACHE_INVAL = 1 }; register enum cache_op operation asm("r8"); register int i asm("r12"); register int limit asm("r3") = max_cache_level << 1; // e.g. 4 with L2 max +if (operation == CACHE_FLUSH) { i = 0; +} else { + i = limit - 2; +} bool loop_again; do { /* [snip] */ + if (operation == CACHE_FLUSH) { i += 2; loop_again = limit > i; + } else { + loop_again = i > 0; + i -= 2; + } } while (loop_again); [1]: 18.6 "TLB and cache maintenance broadcast", Version 4.0 Suggested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: cache-armv7: work around Cortex-A7 erratum 814220Ahmad Fatoum2019-04-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on 0e9a87bb from the linux-imx kernel: ------------------------------------------------------------------------------ | ARM/MP: 814220—B-Cache maintenance by set/way operations can execute | out of order. | | Description: | The v7 ARM states that all cache and branch predictor maintenance operations | that do not specify an address execute, relative to each other, in program | order. However, because of this erratum, an L2 set/way cache maintenance | operation can overtake an L1 set/way cache maintenance operation, this would | cause the data corruption. | | This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. | | This patch is the SW workaround by adding a DSB before changing cache levels | as the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation. | Signed-off-by: Jason Liu <r64343@freescale.com> ------------------------------------------------------------------------------ It was later posted to LKML for Linux inclusion, but is not yet mainline: <20190214083145.15148-1-benjamin.gaignard@linaro.org> Unlike the Linux version, we don't make the barrier dependent on a Kconfig option and always execute the dsb: On 25/4/19 12:02, Lucas Stach wrote: > I don't think we need a Kconfig option here. This function is not > really performance critical. The short pipeline stall introduced by the > dsb when switching the cache level is minor compared to the time it > takes to actually move the cache blocks on a clean. > > Just always execute the [dsb] and add a comment on why it is needed. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init()Andrey Smirnov2019-04-261-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3, SCTLR will be in a state we expect it to be. Add code to reset it to a known state, so we'd always start form clean slate. This is also matches what we've been doing non 64-bit ARMs. Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon appear to have different mask ROM behaviour where it now leaves MMU enabled if no valid boot source is found. Page table it sets up doesn't include DDR range, so trying to bootstrap the device via JTAG/OpenOCD results in an abort. The value for SCTLR_ELx_FLAGS was taken from Linux kernel. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: aarch64: do not use 32bit optimized find bit functionsMichael Tretter2019-05-061-0/+1
|/ | | | | | | | | | | | | | | | The optimized find bit functions are only implemented for 32 bit and are not built on aarch64 systems. Therefore, for example bootchooser cannot be build for aarch64. Select the generic find_bit implementations on aarch64. As the decision, if lib64 or lib32 is build or not, directly depends on CPU_V8, the generic implementation also should be used if CPU_V8 is selected. Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rpi'Sascha Hauer2019-03-071-0/+8
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| * ARM: start: save end of memory passed to start.Tomaz Solc2019-03-041-0/+8
| | | | | | | | | | | | | | | | Knowing the address of the end of the memory area used by Barebox is useful if PBL stores some extra data after it, so that board init code can later retrieve it from there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Fix cpu_info for armv8Sascha Hauer2019-03-041-5/+2
|/ | | | | | | We have get_cr() to get the control register for the different exception levels. Use it rather than the variant hardcoded for EL1. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/e1000'Sascha Hauer2019-02-131-0/+1
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| * ARM: Select HAS_DMA for AArch64Andrey Smirnov2019-02-111-0/+1
| | | | | | | | | | | | | | | | AArch64 implements all of the DMA API functions, so it should select HAS_DMA to allow building drivers that depend on that. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: Make sure DMA coherent memory is zeroed outAndrey Smirnov2019-01-214-2/+12
| | | | | | | | | | | | | | | | | | | | | | In order to avoid passing random/junky values to DMA/HW as well as to allow simplifying memory initialization in individual drivers, change dma_alloc_coherent() to guarantee that memory it returns is properly zeroed out. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: Share code for arm_mmu_not_initialized_error()Andrey Smirnov2019-01-213-22/+11
| | | | | | | | | | | | Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: Share sanity checking code in mmu_init()Andrey Smirnov2019-01-214-30/+26
| | | | | | | | | | | | | | | | | | Share sanity checking code in mmu_init() as well as code to detect if MMU is on or not on both ARM and ARM64. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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