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* ARM: socfpga: Move mach header files to include/mach/socfpgaSascha Hauer2023-03-061-6/+6
| | | | | | | | | | Currently arch specific headers can be included with longer possible as there won't be a single mach anymore. Move all socfpga specific header files to include/mach/socfpga/ to prepare for multi-arch support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: SoCFPGA: arria10: Fix DMA accesses at addresses < 256KiBSascha Hauer2022-11-021-1/+1
| | | | | | | | | | | | | | | Setting BIT(1) in the ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE results in mapping the OCRAM to 0x0, at least for the CPU. Peripherals doing DMA like the SDMMC controller see the SDRAM instead. Linux happens to use this low memory for DMA sometimes and things explode nicely at that point. Clear the OCRAM mapping so that both the CPU and DMA controllers access SDRAM. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20221026125451.3357318-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10-init: split pinsetupSteffen Trumtrar2018-08-081-23/+26
| | | | | | | | | Move the setup of the shared- and fpgapins to its own function. These pins can only be configured and let out of reset after the FPGA has been programmed. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10: move debug_ll to common codeSteffen Trumtrar2018-08-081-0/+2
| | | | | | | | Instead of copy+pasting the debug_ll messages to every new board, move them to the respective functions. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: arria10: enable errata 794072 and 845369Oleksij Rempel2018-07-021-0/+4
| | | | | | | | Enable workarounds for two of the errata the CPU is affected with. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add arria10 supportSteffen Trumtrar2017-05-031-0/+193
Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>