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* ARM: socfpga: mach/pll_config.h: add guard macroAntony Pavlov2018-04-121-0/+4
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: remove nonexistent Kconfig dependencySascha Hauer2018-04-061-5/+0
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: SoCFPGA: remove emac init codeSteffen Trumtrar2018-01-111-35/+0
| | | | | | | | There is a proper driver now that handles the PHY setup for SoCFPGA. Get rid of the code from mach-socfpga. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* net: add SoCFPGA-specific designware driverSteffen Trumtrar2018-01-111-0/+3
| | | | | | | Add a driver for the SoCFPGA-specific version of the designware ethernet ip core. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: remove unused fpgaintf setupSteffen Trumtrar2017-06-301-8/+0
| | | | | | | | | | | The disable bits for the ethernet interfaces between FPGA and HPS are read and configured, but never written back. The configuration itself doesn't make that much sense however. So instead of writing it back to the register, remove the whole read-modify operation altogether. Reported-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: fix QSPI platform data initLucas Stach2017-05-171-1/+1
| | | | | | | | The struct member has been renamed, fix it. Fixes: fddf254b8b9a (mtd: spi-nor: cadence: change devicetree bindings to upstream) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2017-05-0543-269/+3719
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| * ARM: socfpga: add support for reflex achilles boardSteffen Trumtrar2017-05-041-0/+5
| | | | | | | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: add arria10 supportSteffen Trumtrar2017-05-0320-196/+3420
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: make debug_ll configurableSteffen Trumtrar2017-05-031-25/+44
| | | | | | | | | | | | | | | | Allow configuring the serial port and clock rate instead of hardcoding it. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: rename socfpga->cyclone5Steffen Trumtrar2017-05-0326-49/+251
| | | | | | | | | | | | | | | | Prepare the SoCFPGA code base for different system types (Arria10, Stratix10,...). Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/parameter-types'Sascha Hauer2017-05-051-1/+1
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| * | ARM: socfpga: change param_type struct nameSascha Hauer2017-04-101-1/+1
| |/ | | | | | | | | | | | | | | We are going to introduce a "enum param_type" in barebox, so rename the struct type of the same name in the socfpga sequencer code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / mtd: spi-nor: cadence: change devicetree bindings to upstreamSteffen Trumtrar2017-04-191-1/+1
|/ | | | | | | | | Upstream devicetree bindings where changed to use "cdns,is-decoded-cs" instead of "external-decoder". Use it. Also, get rid of the clock-names "qspi_clk" dependency. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: remove unused entry from MakefileSteffen Trumtrar2017-01-101-1/+0
| | | | | | | | There is no fpga.c file. Remove the entry. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: fix compiler warningSascha Hauer2017-01-101-1/+1
| | | | | | | Fixes: arch/arm/mach-socfpga/xload.c:121:13: warning: assignment discards 'const' qualifier from pointer target type Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: fix compiler warningSascha Hauer2017-01-101-1/+1
| | | | | | | Fixes: arm/mach-socfpga/xload.c:31:52: warning: initialization from incompatible pointer type Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/defenv'Sascha Hauer2016-10-101-4/+0
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| * Make generic default environment type a use choiceSascha Hauer2016-10-101-4/+0
| | | | | | | | | | | | | | | | So far it was hardcoded for each board if defenv-1 or defenv-2 is used. Make this a user choice so that a particular board no longer enforces a defenv type. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: socfpga: xload: support more qspi partitionsUlrich Ölmann2016-08-181-15/+41
|/ | | | | | Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2016-05-091-219/+219
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| * whole tree: remove trailing whitespacesDu Huanpeng2016-04-211-219/+219
| | | | | | | | | | Signed-off-by: Du Huanpeng <u74147@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | include: Move ns16550 serial platform_data to include/platform_dataSascha Hauer2016-04-151-1/+1
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | include: Move designware eth platform_data to include/platform_dataSascha Hauer2016-04-151-1/+0
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Terasic DE0-Nano-SoC: add supportTim Sander2016-03-011-0/+4
| | | | | | | | | | | | v7: eof whitespace fixes A Patch for supporting the Terasic DE0 NANO-SoC with barebox. The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign Signed-off-by: Tim Sander <tim@krieglstein.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2016-01-112-5/+7
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| * socfpga: Allow setting partition xloader boots from for mmcTrent Piepho2015-12-142-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The xloader boots the 2nd stage barebox from socfpga_barebox_part when using NOR. But when using MMC it boots from a hardcoded "disk0.1". Add the mmc device name to the partition description and use it for mmc booting. Add an extern declaration of socfpga_barebox_part to the socfpga header so that a board can change it to use a different partition. Initialize socfpga_barebox_part to the default value instead of NULL to avoid the NULL check later. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | socfpga: Find partition with environment via device treeTrent Piepho2016-01-081-38/+0
|/ | | | | | | | | | | | | | | | | socfpga would load the environment from a file named "barebox.env" located on the device "/dev/mmc0.1". Both those names are hard-coded in the socfpga code and can't be changed. Barebox supports selecting the location of the environment using a "barebox,environment" node in device tree's "chosen" node. And recently supports specifying that the env should come from a file on this device. Change socfpga to use this mechanism by adding the appropriate device node. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2015-12-081-3/+31
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| * socfpga: Initialize emac physels to RGMII correctlyTrent Piepho2015-11-111-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A comment in the socfpga init said that it was "Clearing emac0 PHY interface select to 0", but this was doubly incorrect. It was setting physel for emac1, not emac0, and it was setting physel to 1 (RGMII) not 0 (GMII). All supported socfpga boards use RGMII, and use emac1, so fix the comment to reflect the code. But then extend the code to set the physel for both emac0 and emac1, so it can work on boards that use either or both emacs (which are called gmac0/1 in the dts). The Cyclone V datasheet, page 17-60 "EMAC HPS Interface Initialization", says to set physel while the EMAC is in reset. So place the EMAC in reset while changing physel. The emacs are not in reset as code earlier in the boot has already taken most of the modules out of reset. So put them back in reset while the physel is changed. The Linux kernel does it this way too. If barebox has no network support, there is not much point in configuring the emac physel lines. This would be the case for the xloader pre-bootloader config, which configures physel, doesn't use the network, loads the main barebox, which then reconfigures physel again. Make this code depend on CONFIG_NET so it's just done in the main barebox. The Linux kernel does not need barebox to do this initialization to use networking. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mci: dw_mmc: socfpga: Supply bus-width in platform_dataTrent Piepho2015-11-191-0/+2
|/ | | | | | | | | | | | | | | | | Since there is no OF support in the xloader on socfpga it uses the platform_data system. There needs to be a way to supply the equivalent of the DT property bus-width this way to support devices that need to use a smaller bus. So that we don't need to put every flag that might get added to the MMC_CAP list into platform_data, just put the bus width ones into platform_data. The socfpga dts sources specify a bus-width of 4 so use that in the platform_data for socfpga. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* omap socfpga: Switch in flash env loading to use different configTrent Piepho2015-11-051-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | On these systems, the base arch has code to load the in flash environment from a file located in a FAT filesystem. This was controlled by the config option DEFAULT_ENVIRONMENT. However, that option turns on compiling the env into the barebox binary itself, as a backup if the in flash env can't be loaded. Most other boards have in flash env support unconditionally. But omap and socfpga also have xloader configurations, which aren't supposed to have environment support, either in flash or compiled in. If the in flash env code were unconditional, then the xloaders would gain it. So the code depends on ENV_HANDLING, which is only set on those boards that are supposed to have an in flash env and not set on all the boards that aren't supposed to have it. If someone wanted to create a board that did have a saved env, but used an alternate to this generic omap/socfpga file in FAT method, then they'd probably want to create a new config option to control this code and have it not be enabled for their board. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* restart: replace reset_cpu with registered restart handlersSascha Hauer2015-08-271-2/+12
| | | | | | | | | | | | | | | | | | | | | | This replaces the reset_cpu() function which every SoC or board must provide with registered handlers. This makes it possible to have multiple reset functions for boards which have multiple ways to reset the machine. Also boards which have no way at all to reset the machine no longer have to provide a dummy reset_cpu() function. The problem this solves is that some machines have external PMICs or similar to reset the system which have to be preferred over the internal SoC reset, because the PMIC can reset not only the SoC but also the external devices. To pick the right way to reset a machine each handler has a priority. The default priority is 100 and all currently existing restart handlers are registered with this priority. of_get_restart_priority() allows to retrieve the priority from the device tree which makes it possible for boards to give certain restart handlers a higher priority in order to use this one instead of the default one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add default ARCH_TEXT_BASELucas Stach2015-06-261-0/+4
| | | | | | | | | | | | As SoCFPGA is multi-image enabled there is no real reason to bother the user with asking for the text base. Fixes a bunch of randcfg failures. Regenerate defconfig to drop the explicit config there, which unfortunately introduces quite a bit of churn. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/spi-nor'Sascha Hauer2015-06-093-2/+63
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| * ARM: socfpga: xload: support qspi bootsourceSteffen Trumtrar2015-05-293-2/+63
| | | | | | | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: socfpga: update sdram calibration to 15.0Steffen Trumtrar2015-05-152-234/+61
|/ | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add Altera SoCFPGA Development Kit supportSteffen Trumtrar2015-03-021-0/+4
| | | | | | | | Add support for the Altera SoCFPGA Development Kit. The setup is based on the GHRD from Altera. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: cleanup sequencer warningsSteffen Trumtrar2015-01-132-233/+10
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: Import sequencer code from generated ubootMarkus Pargmann2015-01-136-2566/+3929
| | | | | | | | | This patch imports the sequencer code from uboot using the new script scripts/socfpga_get_sequencer. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: clock-manager: set mainnandsdmmcclkSteffen Trumtrar2015-01-131-0/+1
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: clkmgr: bypass debug root clockSteffen Trumtrar2015-01-132-0/+5
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: clkmgr: set alteragrp clocksSteffen Trumtrar2015-01-133-0/+11
| | | | | | | | | | | | | | | | Altera's U-Boot tree has following commit FogBugz #159721: Enhance Arria V MPU clock to 1050MHz It writes to the two undocumented registers CLKMGR_ALTERAGRP_MPUCLK and CLKMGR_ALTERAGRP_MAINCLK to setup the SoC for higher clocks. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: avoid using external regulator for PLLSteffen Trumtrar2015-01-132-7/+18
| | | | | | | | From Altera U-Boot: FogBugz #210587: Fixing PLL HW configuration issue Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sizes.h: move include/sizes.h to include/linux/sizes.hMasahiro Yamada2015-01-081-1/+1
| | | | | | | | | | | | | | This file originates in Linux. Linux has it under include/linux/ directory since commit dccd2304cc90. Let's move it to the same place as well in barebox. This commit was generated by the following commands: find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:' git mv include/sizes.h include/linux/ Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: update sdram calibration to 14.0Steffen Trumtrar2014-12-082-91/+159
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: move iocsr from mach to board folderSteffen Trumtrar2014-12-085-665/+18
| | | | | | | | | | The current iocsr-config-cyclone5.c is actually board specific, although the file name suggests otherwise. As the file was generated for the SoCkit, move it there and add a new one for the socrates. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Firmware: socfpga: Add SoCFPGA FPGA program supportSascha Hauer2014-09-092-0/+3
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* x86: ns16550: Rework driver to allow for x86 I/O spaceMichel Stam2014-04-091-2/+2
| | | | | | | | | | | | The current implementation fakes a memory-mapped I/O device at 0x3f8 and 0x2f8, then uses platform read/write functions to do the actual reading and writing. These platform functions only exist for the x86 platform; better to move the I/O routines into the driver and have the driver request I/O ports using request_ioport_region. Signed-off-by: Michel Stam <michel@reverze.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/nfs'Sascha Hauer2014-03-071-1/+1
|\ | | | | | | | | Conflicts: defaultenv/defaultenv-2-base/bin/ifup
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