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The ZCU102 is a potentially interesting platform, because there's Qemu
support for it. It's not very straight forward to use, because the
ZynqMP support in barebox and Linux relies heavily on firmware services,
which are lacking when naively using Qemu.
Still, let's add support now and worry about running it as part of the
test suite later.
Board support was not tested on actual hardware, but on Qemu with
changes on top of barebox to skip the firmware communication.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20230913130150.2159921-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Move ZynqMP feature selection into submenu like done on the
other multiarch supporting architectures as well.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add support for the Xilinx Zynq UltraScale+ MPSoC ZCU106 evaluation
board.
The changes are derived from the ZCU104 board support by applying
s/104/106/g (more or less).
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.barebox.org/20210913121350.9307-2-michael.riesch@wolfvision.net
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP)
and the Xilinx ZCU104 board.
Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL)
already took care of initializing the RAM. Also for debug_ll, the UART
is expected to be already setup correctly. Thus, you have to add the
Barebox binary to a boot image as described in "Chapter 11: Boot and
Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual".
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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