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* treewide: Remove trailing whitespaces and tabsAlexander Shiyan2019-01-211-1/+1
| | | | | | | Just a cleanup over barebox tree Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: sync imx8mq clock driver with upstream kernelLucas Stach2019-01-152-277/+265
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: add imx8mq composite clockLucas Stach2019-01-153-0/+184
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: add divider_recalc_rate helperLucas Stach2019-01-151-8/+22
| | | | | | | | Closer to Linux kernel implementation and needed for imx8mq composite clock. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: move struct clk_mux into headerLucas Stach2019-01-151-10/+1
| | | | | | | To make it reusable in a composite clock. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: move struct clk_gate into headerLucas Stach2019-01-151-11/+1
| | | | | | | To make it reusable in a composite clock. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx5: add di_predLucas Stach2018-12-131-0/+3
| | | | | | | | | This was missing, so the default external DI clock source on i.MX51 was missing. Also set the divider to a division ratio of 1 initially, to avoid complicating the logic in the IPU driver further. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/missing-prototypes'Sascha Hauer2018-12-071-8/+1
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| * clk: imx: Avoid missing prototype warningsSascha Hauer2018-11-121-8/+1
| | | | | | | | | | | | | | clk_gate2_free() is unused, so remove it. clk_gate2_alloc() is only used locally, so make it static. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2018-12-071-0/+9
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| * | ARM: i.MX5 clock: add clock provider supportMichael Grzeschik2018-11-191-0/+9
| |/ | | | | | | | | | | | | | | Currently it is impossible to get clks with clk_get(&clk, "name"); on the mx5 platform. Change that by adding clk-imx5 as clk_provider. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/checkpatch'Sascha Hauer2018-12-071-1/+3
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| * | clk: imx: cpu: avoid use after free on errorOleksij Rempel2018-11-191-1/+3
| |/ | | | | | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / clk: fix NULL deref without OF node in debug messageMatthias Schiffer2018-11-231-1/+1
|/ | | | | | | | | | | | of_clk_add_provider() may be called for devices added via add_generic_device(). There is no OF node in this case, leading to a crash when debug logs are enabled. This affects various i.MX CPUs, which add imx*-ccm clock devices using add_generic_device(). Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/missing-prototypes'Sascha Hauer2018-11-091-3/+3
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| * drivers: clk: imx5: Make locally used functions staticSascha Hauer2018-10-231-3/+3
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: clk: rk3188: don't set same clk rate twiceperachet7@gmail.com2018-11-091-0/+3
|/ | | | | | | | | | | We found setting a clock rate which has already been set, rk3188 (radxa rock pro) bails out. This is a quick fix only. Underlying situation not (yet) investigated: why it is even trying to set it to the same rate again. It remains to state that some but not all rrpro boards exhibit this behaviour, no other rk3188 boards have been tested. Signed-off-by: P. Rachet <perachet7@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX8MQ: Add missing IMX8MQ_CLK_TMU_ROOT clockAndrey Smirnov2018-09-241-0/+1
| | | | | | | Add missing IMX8MQ_CLK_TMU_ROOT clock needed for CPU thermal sensor. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX8MQ: Bump refcounters of various important clocksAndrey Smirnov2018-09-241-0/+12
| | | | | | | | | Bump refcounters of various important clocks in order to make sure their parents are not disabled during clock re-configuration added by commits that follow. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX28: Add APBH clk supportOleksij Rempel2018-09-181-0/+1
| | | | | | | | | | i.MX28 fails to use DMA and NAND because it cannot find its clock. Add the clock for APBH. Fixes: 6eb2ba6f1b ("dma: apbh: Enable clock as a part of probing") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: clk-sccg-pll: Remove leftover debug outputAndrey Smirnov2018-08-311-2/+0
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2018-07-092-18/+0
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| * mtd: gpmi-nand: Make sure clock is disabled during rate changeSascha Hauer2018-07-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On i.MX6 GPMI Nand controller the clock must be disabled during a rate change. Otherwise glitches on the clock line may occur which result in errors like: MXS NAND: Error sending command MXS NAND: DMA read error There were previous attempts to fix this. One is in: 54961378f0 imx6: clk: Gate off ENFC clock before setting clock rate This patch added a clk_disable() right before the rate change. Since a clk_disable() on a disabled clk is a no-op, the patch added a clk_enable() to the i.MX6 clk driver in the hope that the clk is enabled in the nand driver probe and the clk_disable() really takes place. This patch doesn't work. First of all it enabled the enfc_podf clk which was not the one that was actually disabled in the nand driver, resulting in the nand drivers call to clk_disable() still being a no-op. Then this patch also only works only on the classic i.MX6 which was the only one supported at that time, but not on the i.MX6UL, i.MX6SX and i.MX6SL which have a separate clk driver. Instead of adding more quirks to the other i.MX6 clk drivers, fix this in the GPMI driver. We no longer call clk_disable() on a disabled clk, but instead do a clk_enable() first which makes sure the hardware state is synchronized to the usage count and the following clk_disable() is really effective. At the same time we can (and actually must) remove the quirk in the i.MX6 clk driver. Also add clk_disable()/clk_enable() around another rate change in the GPMI driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: imx: remove unused clk_gate2_invertedSascha Hauer2018-07-061-17/+0
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | dts: update to v4.18-rc1Sascha Hauer2018-06-221-9/+8
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2018-06-115-0/+1078
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| * clock: Add i.MX8MQ clock driverSascha Hauer2018-06-115-0/+1078
| | | | | | | | | | | | | | | | | | | | | | | | | | This is based on Lucas' patch sent as "[PATCH v2 4/4] clk: imx: add clock driver for i.MX8MQ CCM" to the mailing list. It will likely need some rework before it is finally merged, so apply the reworks here before merging into barebox. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [andrew.smirnov@gmail.com: Fix pll type for IMX8MQ_VIDEO2_PLL1] Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: support pinmux configuration in clock provider nodesNikita Yushchenko2018-05-141-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some device trees use pinctrl-* settings inside device tree nodes for clock providers. Barebox does not threat clock providers (such as fixed-clock or gpio-gate-clock) as conventional devices, thus setting default pinctrl configuration in driver binding code does not happen for clock providers. This patch adds setting default pinctrl configuration to of_clk_init(), just before calling clock provider's probe routine. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: add clk-gpio driverNikita Yushchenko2018-05-142-1/+131
|/ | | | | | | | This implements support for gpio-gate-clock device tree nodes, that define clocks that can be enabled or disabled via GPIO line. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX6: Fix enfc_sel for i.MX6dqpSascha Hauer2018-04-161-1/+18
| | | | | | | | The plus SoC variants have some differences in the clock controller. For now fix the NAND controller clock. There are more differences that might be relevant, but for now are left for a future excercise. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX6: Adjust GPMI parent clockSascha Hauer2018-04-121-0/+7
| | | | | | | | | | Based on the corresponding Kernel code: The gpmi needs 100MHz frequency in the EDO/Sync mode, We can not get the 100MHz from the pll2_pfd0_352m. So choose pll2_pfd2_396m as enfc_sel's parent. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: Port NAND clock setup code from LinuxAndrey Smirnov2018-04-032-2/+10
| | | | | | | | | Port Linux kernel commit 22039d150f716e4e ("clk: imx7d: create clocks behind rawnand clock gate") in order to correctly initialize clocks necessary for APBH DMA block to be functional on i.MX7 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx25: clk: add rngb clockSteffen Trumtrar2018-02-091-2/+3
| | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
* clk: sp810: hardwire parent to 1MHz clockLucas Stach2017-11-171-13/+7
| | | | | | | | | | | | | This works around a limitation in our handling of the vexpress config bus. For now just hardcode the clock parent to the 1MHz clock, which is the default as emulated by QEMU and also the setting the Linux kernel will configure later. This fixes the vexpress clocksource running at a wrong rate leading to bogus delays and sleep times. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2017-10-193-6/+0
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| * remove checks for xzalloc() returning NULLUwe Kleine-König2017-09-263-6/+0
| | | | | | | | | | | | | | xzalloc() either returns memory or panics, so checking for NULL is useless. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mips'Sascha Hauer2017-10-192-1/+150
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| * | clk: add ar9344 clock driverOleksij Rempel2017-10-062-1/+150
| |/ | | | | | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / clk: versatile: add basic clocksLucas Stach2017-10-174-0/+180
|/ | | | | | | | This adds the necessary basic clocks used on the ARM versatile platforms. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: cpu: don't store the address of a function parameterUwe Kleine-König2017-08-151-2/+10
| | | | | | | | | | | | | | | The function imx_clk_cpu takes a const char *parent_name as second paramter. The implementation introduced in commit 9a89ed9d281e then uses the address of this function parameter to assign clk.parent_names. This is an address on the stack that is saved in the clk tree and of course this is easily overwritten by later execution paths of barebox. Without this fix the clk_dump command reproducibly crashes on i.MX7 (which is the only SoC that makes use of imx_clk_cpu()). Fixes: 9a89ed9d281e ("clk: imx: Add clk-cpu support") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* Merge branch 'for-next/misc'Lucas Stach2017-07-311-1/+0
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| * clk: clk-fixed-factor: remove leftover debuggingLucas Stach2017-07-201-1/+0
| | | | | | | | | | | | | | Don't spam the output with rate propagation messages. It isn't done for any other clock. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* | Merge branch 'for-next/imx'Lucas Stach2017-07-311-11/+0
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| * | clk: i.MX7: Remove unused UART clocks arrayAndrey Smirnov2017-07-301-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove what looks like unused leftover from analogous Linux kernel code. Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* | | Merge branch 'for-next/at91'Lucas Stach2017-07-311-0/+1
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| * | clk: at91: fix clk-mainSam Ravnborg2017-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following warning was reported during boot with at91sam9263ek with DT enabled. "Main crystal frequency not set, using approximate value" This occured due to a missing parent in clk_rm9200_main. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* | | i.MX: clk-pllv3: Initially disable PLL_BYPASS bitPhilipp Zabel2017-07-121-0/+5
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit cbff8031b491 ("i.MX: clk-pllv3: Do not touch PLL_BYPASS bit") overreached a bit by removing the code that disables the PLL_BYPASS bit for all architectures instead of making an exception for Vybrid and i.MX6SL. This causes the USB controller on i.MX6Q to run at bypass frequency and fail: barebox@Boundary Devices i.MX6 Quad Nitrogen6x Board:/ usb usb: USB: scanning bus for devices... usb: Bus 001 Device 001: ID 0000:0000 EHCI Host Controller imx-usb 2184200.usb: port(0) reset error This patch adds code to unconditionally disable the PLL_BYPASS bit initially, when the PLL clocks are registered. Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Fixes: cbff8031b491 ("i.MX: clk-pllv3: Do not touch PLL_BYPASS bit") Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* | clk: fix clk_get error handlingSam Ravnborg2017-07-071-1/+1
|/ | | | | | | | | | | | | | | | | If there is no OFTREE support of_clk_get_by_name failed with -ENOENT, which caused clk_get to bail out. This had the effect that nothing was printed on the serial console with at91sam9263-ek. There are no error paths that will return -ENODEV as we test for today, so change this to -ENOENT which is in use. This allows us to contine with clk_get_sys() in case of other errors as was the intention of the original fix. Fixes: 90f7eacb ("clk: let clk_get return errors from of_clk_get_by_name") Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* Merge branch 'for-next/mvebu'Sascha Hauer2017-06-304-0/+157
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| * clk: mvebu: Add support for Armada 38x's coreclkUwe Kleine-König2017-06-194-0/+157
| | | | | | | | | | | | | | | | This is a mixture of the Armada 370 barebox driver and the Armada 38x Linux driver. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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