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-rw-r--r--dts/Bindings/arc/hsdk.txt7
-rw-r--r--dts/Bindings/arm/amlogic.txt41
-rw-r--r--dts/Bindings/arm/arch_timer.txt1
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm2835.txt4
-rw-r--r--dts/Bindings/arm/bhf.txt6
-rw-r--r--dts/Bindings/arm/coresight.txt4
-rw-r--r--dts/Bindings/arm/cpus.txt1
-rw-r--r--dts/Bindings/arm/marvell/armada-8kp.txt15
-rw-r--r--dts/Bindings/arm/marvell/cp110-system-controller0.txt1
-rw-r--r--dts/Bindings/arm/mediatek.txt18
-rw-r--r--dts/Bindings/arm/omap/omap.txt9
-rw-r--r--dts/Bindings/arm/pmu.txt2
-rw-r--r--dts/Bindings/arm/qcom.txt2
-rw-r--r--dts/Bindings/arm/rockchip.txt12
-rw-r--r--dts/Bindings/arm/shmobile.txt8
-rw-r--r--dts/Bindings/ata/ahci-mtk.txt51
-rw-r--r--dts/Bindings/ata/apm-xgene.txt2
-rw-r--r--dts/Bindings/ata/imx-pata.txt1
-rw-r--r--dts/Bindings/bus/mvebu-mbus.txt3
-rw-r--r--dts/Bindings/bus/nvidia,tegra20-gmi.txt2
-rw-r--r--dts/Bindings/bus/nvidia,tegra210-aconnect.txt1
-rw-r--r--dts/Bindings/chosen.txt26
-rw-r--r--dts/Bindings/clock/alphascale,acc.txt1
-rw-r--r--dts/Bindings/clock/amlogic,gxbb-aoclkc.txt23
-rw-r--r--dts/Bindings/clock/amlogic,gxbb-clkc.txt1
-rw-r--r--dts/Bindings/clock/amlogic,meson8b-clkc.txt10
-rw-r--r--dts/Bindings/clock/at91-clock.txt10
-rw-r--r--dts/Bindings/clock/brcm,kona-ccu.txt1
-rw-r--r--dts/Bindings/clock/exynos5433-clock.txt1
-rw-r--r--dts/Bindings/clock/hi3660-clock.txt1
-rw-r--r--dts/Bindings/clock/hix5hd2-clock.txt1
-rw-r--r--dts/Bindings/clock/idt,versaclock5.txt30
-rw-r--r--dts/Bindings/clock/imx21-clock.txt1
-rw-r--r--dts/Bindings/clock/imx23-clock.txt1
-rw-r--r--dts/Bindings/clock/imx25-clock.txt1
-rw-r--r--dts/Bindings/clock/imx27-clock.txt1
-rw-r--r--dts/Bindings/clock/imx28-clock.txt1
-rw-r--r--dts/Bindings/clock/imx31-clock.txt1
-rw-r--r--dts/Bindings/clock/imx5-clock.txt1
-rw-r--r--dts/Bindings/clock/imx6q-clock.txt1
-rw-r--r--dts/Bindings/clock/mt8173-cpu-dvfs.txt83
-rw-r--r--dts/Bindings/clock/nvidia,tegra124-dfll.txt1
-rw-r--r--dts/Bindings/clock/pxa-clock.txt1
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt4
-rw-r--r--dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt1
-rw-r--r--dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt55
-rw-r--r--dts/Bindings/clock/renesas,rz-cpg-clocks.txt1
-rw-r--r--dts/Bindings/clock/rockchip,rk3128-cru.txt8
-rw-r--r--dts/Bindings/clock/samsung,s3c2410-clock.txt1
-rw-r--r--dts/Bindings/clock/samsung,s3c2412-clock.txt1
-rw-r--r--dts/Bindings/clock/samsung,s3c2443-clock.txt1
-rw-r--r--dts/Bindings/clock/samsung,s3c64xx-clock.txt1
-rw-r--r--dts/Bindings/clock/samsung,s5pv210-clock.txt1
-rw-r--r--dts/Bindings/clock/silabs,si5351.txt6
-rw-r--r--dts/Bindings/clock/snps,hsdk-pll-clock.txt28
-rw-r--r--dts/Bindings/clock/snps,pll-clock.txt28
-rw-r--r--dts/Bindings/clock/st,stm32h7-rcc.txt71
-rw-r--r--dts/Bindings/clock/sunxi-ccu.txt6
-rw-r--r--dts/Bindings/clock/ti,sci-clk.txt7
-rw-r--r--dts/Bindings/clock/ti/dra7-atl.txt2
-rw-r--r--dts/Bindings/clock/uniphier-clock.txt8
-rw-r--r--dts/Bindings/clock/zx296702-clk.txt1
-rw-r--r--dts/Bindings/clock/zx296718-clk.txt1
-rw-r--r--dts/Bindings/cpufreq/cpufreq-mediatek.txt247
-rw-r--r--dts/Bindings/crypto/artpec6-crypto.txt16
-rw-r--r--dts/Bindings/crypto/atmel-crypto.txt13
-rw-r--r--dts/Bindings/crypto/fsl-dcp.txt1
-rw-r--r--dts/Bindings/crypto/inside-secure-safexcel.txt1
-rw-r--r--dts/Bindings/crypto/marvell-cesa.txt1
-rw-r--r--dts/Bindings/crypto/mv_cesa.txt1
-rw-r--r--dts/Bindings/crypto/rockchip-crypto.txt1
-rw-r--r--dts/Bindings/crypto/st,stm32-hash.txt30
-rw-r--r--dts/Bindings/devfreq/event/rockchip-dfi.txt1
-rw-r--r--dts/Bindings/devfreq/rk3399_dmc.txt1
-rw-r--r--dts/Bindings/display/atmel,lcdc.txt1
-rw-r--r--dts/Bindings/display/atmel/hlcdc-dc.txt1
-rw-r--r--dts/Bindings/display/bridge/dw_mipi_dsi.txt32
-rw-r--r--dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt1
-rw-r--r--dts/Bindings/display/bridge/renesas,dw-hdmi.txt2
-rw-r--r--dts/Bindings/display/exynos/exynos5433-decon.txt12
-rw-r--r--dts/Bindings/display/fsl,tcon.txt1
-rw-r--r--dts/Bindings/display/imx/fsl-imx-drm.txt2
-rw-r--r--dts/Bindings/display/marvell,pxa2xx-lcdc.txt1
-rw-r--r--dts/Bindings/display/panel/innolux,p079zca.txt1
-rw-r--r--dts/Bindings/display/renesas,du.txt51
-rw-r--r--dts/Bindings/display/repaper.txt52
-rw-r--r--dts/Bindings/display/rockchip/analogix_dp-rockchip.txt1
-rw-r--r--dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt8
-rw-r--r--dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt2
-rw-r--r--dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt1
-rw-r--r--dts/Bindings/display/rockchip/rockchip-vop.txt4
-rw-r--r--dts/Bindings/display/simple-framebuffer-sunxi.txt1
-rw-r--r--dts/Bindings/display/sitronix,st7586.txt22
-rw-r--r--dts/Bindings/display/st,stm32-ltdc.txt105
-rw-r--r--dts/Bindings/display/sunxi/sun4i-drm.txt37
-rw-r--r--dts/Bindings/dma/fsl-edma.txt1
-rw-r--r--dts/Bindings/dma/mv-xor.txt1
-rw-r--r--dts/Bindings/dma/qcom_adm.txt1
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.txt1
-rw-r--r--dts/Bindings/dma/renesas,usb-dmac.txt1
-rw-r--r--dts/Bindings/dma/snps-dma.txt1
-rw-r--r--dts/Bindings/dma/st_fdma.txt1
-rw-r--r--dts/Bindings/dma/ste-dma40.txt1
-rw-r--r--dts/Bindings/dma/sun4i-dma.txt1
-rw-r--r--dts/Bindings/dma/sun6i-dma.txt1
-rw-r--r--dts/Bindings/dma/ti-dma-crossbar.txt1
-rw-r--r--dts/Bindings/dma/ti-edma.txt96
-rw-r--r--dts/Bindings/eeprom/eeprom.txt6
-rw-r--r--dts/Bindings/extcon/extcon-usbc-cros-ec.txt24
-rw-r--r--dts/Bindings/fpga/altera-passive-serial.txt29
-rw-r--r--dts/Bindings/fpga/xilinx-pr-decoupler.txt36
-rw-r--r--dts/Bindings/fpga/xilinx-slave-serial.txt1
-rw-r--r--dts/Bindings/gpio/gpio-74x164.txt3
-rw-r--r--dts/Bindings/gpio/gpio-aspeed.txt2
-rw-r--r--dts/Bindings/gpio/gpio-davinci.txt91
-rw-r--r--dts/Bindings/gpio/gpio-mpc8xxx.txt1
-rw-r--r--dts/Bindings/gpio/gpio-vf610.txt4
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt16
-rw-r--r--dts/Bindings/gpio/spear_spics.txt1
-rw-r--r--dts/Bindings/gpu/arm,mali-midgard.txt1
-rw-r--r--dts/Bindings/gpu/arm,mali-utgard.txt5
-rw-r--r--dts/Bindings/gpu/nvidia,gk20a.txt3
-rw-r--r--dts/Bindings/gpu/samsung-g2d.txt1
-rw-r--r--dts/Bindings/hsi/omap-ssi.txt1
-rw-r--r--dts/Bindings/hwmon/aspeed-pwm-tacho.txt9
-rw-r--r--dts/Bindings/hwmon/ibm,cffps1.txt21
-rw-r--r--dts/Bindings/hwmon/ltq-cputemp.txt10
-rw-r--r--dts/Bindings/i2c/i2c-altera.txt39
-rw-r--r--dts/Bindings/i2c/i2c-cbus-gpio.txt4
-rw-r--r--dts/Bindings/i2c/i2c-demux-pinctrl.txt1
-rw-r--r--dts/Bindings/i2c/i2c-efm32.txt1
-rw-r--r--dts/Bindings/i2c/i2c-mtk.txt15
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt5
-rw-r--r--dts/Bindings/i2c/i2c-rk3x.txt1
-rw-r--r--dts/Bindings/i2c/i2c-sh_mobile.txt5
-rw-r--r--dts/Bindings/i2c/i2c-sprd.txt31
-rw-r--r--dts/Bindings/i2c/i2c-stm32.txt29
-rw-r--r--dts/Bindings/i2c/nvidia,tegra20-i2c.txt1
-rw-r--r--dts/Bindings/iio/adc/at91-sama5d2_adc.txt6
-rw-r--r--dts/Bindings/iio/adc/brcm,iproc-static-adc.txt1
-rw-r--r--dts/Bindings/iio/adc/lpc1850-adc.txt1
-rw-r--r--dts/Bindings/iio/adc/mt6577_auxadc.txt1
-rw-r--r--dts/Bindings/iio/adc/rockchip-saradc.txt1
-rw-r--r--dts/Bindings/iio/adc/st,stm32-adc.txt5
-rw-r--r--dts/Bindings/iio/counter/stm32-lptimer-cnt.txt27
-rw-r--r--dts/Bindings/iio/dac/lpc1850-dac.txt1
-rw-r--r--dts/Bindings/iio/dac/st,stm32-dac.txt4
-rw-r--r--dts/Bindings/iio/humidity/hdc100x.txt17
-rw-r--r--dts/Bindings/iio/humidity/hts221.txt11
-rw-r--r--dts/Bindings/iio/humidity/htu21.txt13
-rw-r--r--dts/Bindings/iio/imu/st_lsm6dsx.txt8
-rw-r--r--dts/Bindings/iio/pressure/ms5637.txt17
-rw-r--r--dts/Bindings/iio/st-sensors.txt3
-rw-r--r--dts/Bindings/iio/temperature/tsys01.txt19
-rw-r--r--dts/Bindings/iio/timer/stm32-lptimer-trigger.txt23
-rw-r--r--dts/Bindings/iio/timer/stm32-timer-trigger.txt6
-rw-r--r--dts/Bindings/input/atmel,maxtouch.txt2
-rw-r--r--dts/Bindings/input/brcm,bcm-keypad.txt1
-rw-r--r--dts/Bindings/input/pwm-vibrator.txt66
-rw-r--r--dts/Bindings/input/ti,drv260x.txt2
-rw-r--r--dts/Bindings/input/touchscreen/colibri-vf50-ts.txt1
-rw-r--r--dts/Bindings/input/touchscreen/imx6ul_tsc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt8
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,sysirq.txt1
-rw-r--r--dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt32
-rw-r--r--dts/Bindings/iommu/qcom,iommu.txt121
-rw-r--r--dts/Bindings/iommu/rockchip,iommu.txt5
-rw-r--r--dts/Bindings/leds/ams,as3645a.txt71
-rw-r--r--dts/Bindings/leds/irled/gpio-ir-tx.txt14
-rw-r--r--dts/Bindings/leds/irled/pwm-ir-tx.txt13
-rw-r--r--dts/Bindings/leds/leds-gpio.txt3
-rw-r--r--dts/Bindings/leds/leds-pca955x.txt88
-rw-r--r--dts/Bindings/media/i2c/adv748x.txt95
-rw-r--r--dts/Bindings/media/i2c/dongwoon,dw9714.txt9
-rw-r--r--dts/Bindings/media/meson-ao-cec.txt28
-rw-r--r--dts/Bindings/media/mtk-cir.txt8
-rw-r--r--dts/Bindings/media/pxa-camera.txt1
-rw-r--r--dts/Bindings/media/qcom,camss.txt197
-rw-r--r--dts/Bindings/media/renesas,drif.txt1
-rw-r--r--dts/Bindings/media/s5p-cec.txt1
-rw-r--r--dts/Bindings/media/samsung-fimc.txt2
-rw-r--r--dts/Bindings/media/stih407-c8sectpfe.txt1
-rw-r--r--dts/Bindings/media/ti,da850-vpif.txt1
-rw-r--r--dts/Bindings/media/video-interfaces.txt8
-rw-r--r--dts/Bindings/media/zx-irdec.txt14
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-larb.txt15
-rw-r--r--dts/Bindings/memory-controllers/mvebu-devbus.txt1
-rw-r--r--dts/Bindings/mfd/act8945a.txt2
-rw-r--r--dts/Bindings/mfd/atmel-hlcdc.txt1
-rw-r--r--dts/Bindings/mfd/atmel-smc.txt1
-rw-r--r--dts/Bindings/mfd/axp20x.txt50
-rw-r--r--dts/Bindings/mfd/bd9571mwv.txt49
-rw-r--r--dts/Bindings/mfd/da9052-i2c.txt9
-rw-r--r--dts/Bindings/mfd/mc13xxx.txt1
-rw-r--r--dts/Bindings/mfd/mxs-lradc.txt2
-rw-r--r--dts/Bindings/mfd/retu.txt25
-rw-r--r--dts/Bindings/mfd/rk808.txt22
-rw-r--r--dts/Bindings/mfd/samsung,exynos5433-lpass.txt2
-rw-r--r--dts/Bindings/mfd/stm32-lptimer.txt48
-rw-r--r--dts/Bindings/mfd/tps6105x.txt17
-rw-r--r--dts/Bindings/mfd/wm831x.txt1
-rw-r--r--dts/Bindings/mfd/zii,rave-sp.txt39
-rw-r--r--dts/Bindings/mips/lantiq/fpi-bus.txt31
-rw-r--r--dts/Bindings/mips/lantiq/rcu-gphy.txt36
-rw-r--r--dts/Bindings/mips/lantiq/rcu.txt89
-rw-r--r--dts/Bindings/mips/ni.txt7
-rw-r--r--dts/Bindings/mips/ralink.txt1
-rw-r--r--dts/Bindings/misc/atmel-ssc.txt1
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt1
-rw-r--r--dts/Bindings/mmc/davinci_mmc.txt1
-rw-r--r--dts/Bindings/mmc/fsl-imx-mmc.txt1
-rw-r--r--dts/Bindings/mmc/mmc-card.txt1
-rw-r--r--dts/Bindings/mmc/mmc.txt1
-rw-r--r--dts/Bindings/mmc/orion-sdio.txt1
-rw-r--r--dts/Bindings/mmc/renesas,mmcif.txt4
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt1
-rw-r--r--dts/Bindings/mmc/sdhci-st.txt3
-rw-r--r--dts/Bindings/mmc/sunxi-mmc.txt1
-rw-r--r--dts/Bindings/mmc/ti-omap-hsmmc.txt52
-rw-r--r--dts/Bindings/mmc/tmio_mmc.txt8
-rw-r--r--dts/Bindings/mmc/zx-dw-mshc.txt1
-rw-r--r--dts/Bindings/mtd/atmel-quadspi.txt1
-rw-r--r--dts/Bindings/mtd/mtk-quadspi.txt1
-rw-r--r--dts/Bindings/mtd/qcom_nandc.txt65
-rw-r--r--dts/Bindings/mtd/st-fsm.txt1
-rw-r--r--dts/Bindings/mtd/sunxi-nand.txt1
-rw-r--r--dts/Bindings/net/anarion-gmac.txt25
-rw-r--r--dts/Bindings/net/brcm,amac.txt1
-rw-r--r--dts/Bindings/net/broadcom-bluetooth.txt35
-rw-r--r--dts/Bindings/net/btusb.txt1
-rw-r--r--dts/Bindings/net/can/c_can.txt13
-rw-r--r--dts/Bindings/net/can/m_can.txt1
-rw-r--r--dts/Bindings/net/dsa/ksz.txt2
-rw-r--r--dts/Bindings/net/dsa/lan9303.txt3
-rw-r--r--dts/Bindings/net/ethernet.txt4
-rw-r--r--dts/Bindings/net/ftgmac100.txt1
-rw-r--r--dts/Bindings/net/marvell-armada-370-neta.txt1
-rw-r--r--dts/Bindings/net/marvell-bt-8xxx.txt2
-rw-r--r--dts/Bindings/net/marvell-neta-bm.txt2
-rw-r--r--dts/Bindings/net/marvell-pp2.txt32
-rw-r--r--dts/Bindings/net/mediatek-net.txt18
-rw-r--r--dts/Bindings/net/meson-dwmac.txt1
-rw-r--r--dts/Bindings/net/micrel-ksz90x1.txt1
-rw-r--r--dts/Bindings/net/microchip,enc28j60.txt1
-rw-r--r--dts/Bindings/net/nfc/nfcmrvl.txt2
-rw-r--r--dts/Bindings/net/nfc/nxp-nci.txt1
-rw-r--r--dts/Bindings/net/nfc/pn533-i2c.txt1
-rw-r--r--dts/Bindings/net/nfc/pn544.txt1
-rw-r--r--dts/Bindings/net/nfc/s3fwrn5.txt1
-rw-r--r--dts/Bindings/net/nfc/st-nci-i2c.txt1
-rw-r--r--dts/Bindings/net/nfc/st-nci-spi.txt1
-rw-r--r--dts/Bindings/net/nfc/st21nfca.txt1
-rw-r--r--dts/Bindings/net/nfc/st95hf.txt2
-rw-r--r--dts/Bindings/net/nfc/trf7970a.txt2
-rw-r--r--dts/Bindings/net/oxnas-dwmac.txt1
-rw-r--r--dts/Bindings/net/phy.txt15
-rw-r--r--dts/Bindings/net/qca,qca7000.txt2
-rw-r--r--dts/Bindings/net/renesas,ravb.txt30
-rw-r--r--dts/Bindings/net/rockchip-dwmac.txt2
-rw-r--r--dts/Bindings/net/sff,sfp.txt76
-rw-r--r--dts/Bindings/net/smsc-lan87xx.txt1
-rw-r--r--dts/Bindings/net/socfpga-dwmac.txt1
-rw-r--r--dts/Bindings/net/sti-dwmac.txt1
-rw-r--r--dts/Bindings/net/stm32-dwmac.txt1
-rw-r--r--dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt1
-rw-r--r--dts/Bindings/net/wireless/esp,esp8089.txt1
-rw-r--r--dts/Bindings/net/wireless/marvell-8xxx.txt1
-rw-r--r--dts/Bindings/net/wireless/ti,wlcore.txt1
-rw-r--r--dts/Bindings/net/xilinx_axienet.txt55
-rw-r--r--dts/Bindings/nvmem/mtk-efuse.txt5
-rw-r--r--dts/Bindings/nvmem/mxs-ocotp.txt1
-rw-r--r--dts/Bindings/opp/opp.txt1
-rw-r--r--dts/Bindings/pci/83xx-512x-pci.txt6
-rw-r--r--dts/Bindings/pci/aardvark-pci.txt1
-rw-r--r--dts/Bindings/pci/altera-pcie.txt18
-rw-r--r--dts/Bindings/pci/axis,artpec6-pcie.txt2
-rw-r--r--dts/Bindings/pci/designware-pcie.txt24
-rw-r--r--dts/Bindings/pci/fsl,imx6q-pcie.txt2
-rw-r--r--dts/Bindings/pci/hisilicon-pcie.txt6
-rw-r--r--dts/Bindings/pci/kirin-pcie.txt8
-rw-r--r--dts/Bindings/pci/layerscape-pci.txt4
-rw-r--r--dts/Bindings/pci/mediatek,mt7623-pcie.txt130
-rw-r--r--dts/Bindings/pci/mediatek-pcie.txt284
-rw-r--r--dts/Bindings/pci/mvebu-pci.txt15
-rw-r--r--dts/Bindings/pci/pci-armada8k.txt3
-rw-r--r--dts/Bindings/pci/pci-keystone.txt15
-rw-r--r--dts/Bindings/pci/pci-rcar-gen2.txt7
-rw-r--r--dts/Bindings/pci/pci.txt4
-rw-r--r--dts/Bindings/pci/qcom,pcie.txt27
-rw-r--r--dts/Bindings/pci/ralink,rt3883-pci.txt2
-rw-r--r--dts/Bindings/pci/rcar-pci.txt8
-rw-r--r--dts/Bindings/pci/rockchip-pcie.txt28
-rw-r--r--dts/Bindings/pci/samsung,exynos5440-pcie.txt22
-rw-r--r--dts/Bindings/pci/spear13xx-pcie.txt6
-rw-r--r--dts/Bindings/pci/ti-pci.txt8
-rw-r--r--dts/Bindings/pci/versatile.txt2
-rw-r--r--dts/Bindings/pci/xgene-pci-msi.txt6
-rw-r--r--dts/Bindings/pci/xgene-pci.txt8
-rw-r--r--dts/Bindings/pci/xilinx-nwl-pcie.txt7
-rw-r--r--dts/Bindings/phy/apm-xgene-phy.txt3
-rw-r--r--dts/Bindings/phy/keystone-usb-phy.txt1
-rw-r--r--dts/Bindings/phy/phy-bindings.txt4
-rw-r--r--dts/Bindings/phy/phy-lantiq-rcu-usb2.txt40
-rw-r--r--dts/Bindings/phy/phy-mtk-tphy.txt (renamed from dts/Bindings/phy/phy-mt65xx-usb.txt)21
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-rw-r--r--dts/Bindings/phy/phy-mvebu.txt1
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-rw-r--r--dts/Bindings/phy/qcom-dwc3-usb-phy.txt2
-rw-r--r--dts/Bindings/phy/qcom-qmp-phy.txt11
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-rw-r--r--dts/Bindings/phy/rockchip-pcie-phy.txt7
-rw-r--r--dts/Bindings/phy/samsung-phy.txt1
-rw-r--r--dts/Bindings/phy/sun4i-usb-phy.txt10
-rw-r--r--dts/Bindings/phy/sun9i-usb-phy.txt1
-rw-r--r--dts/Bindings/pinctrl/atmel,at91-pinctrl.txt1
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-rw-r--r--dts/Bindings/pinctrl/fsl,imx-pinctrl.txt1
-rw-r--r--dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt1
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-rw-r--r--dts/Bindings/pinctrl/oxnas,pinctrl.txt1
-rw-r--r--dts/Bindings/pinctrl/pinctrl-aspeed.txt8
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-rw-r--r--dts/Bindings/pinctrl/pinctrl-mt65xx.txt1
-rw-r--r--dts/Bindings/pinctrl/pinctrl-rk805.txt63
-rw-r--r--dts/Bindings/pinctrl/pinctrl-zx.txt1
-rw-r--r--dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt3
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-rw-r--r--dts/Bindings/pinctrl/qcom,pmic-gpio.txt26
-rw-r--r--dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt4
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-rw-r--r--dts/Bindings/pinctrl/st,stm32-pinctrl.txt1
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-rw-r--r--dts/Bindings/power/renesas,apmu.txt3
-rw-r--r--dts/Bindings/power/renesas,rcar-sysc.txt1
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-rw-r--r--dts/Bindings/power/rockchip-io-domain.txt2
-rw-r--r--dts/Bindings/power/supply/act8945a-charger.txt2
-rw-r--r--dts/Bindings/power/supply/bq24190.txt51
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-rw-r--r--dts/Bindings/power/supply/max8903-charger.txt1
-rw-r--r--dts/Bindings/power/supply/maxim,max14656.txt1
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-rw-r--r--dts/Bindings/pps/pps-gpio.txt8
-rw-r--r--dts/Bindings/ptp/brcm,ptp-dte.txt1
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-rw-r--r--dts/Bindings/pwm/pwm-mediatek.txt6
-rw-r--r--dts/Bindings/pwm/pwm-meson.txt1
-rw-r--r--dts/Bindings/pwm/pwm-rockchip.txt11
-rw-r--r--dts/Bindings/pwm/pwm-stm32-lp.txt24
-rw-r--r--dts/Bindings/pwm/pwm-sun4i.txt1
-rw-r--r--dts/Bindings/pwm/pwm-tiecap.txt1
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-rw-r--r--dts/Bindings/pwm/renesas,tpu-pwm.txt1
-rw-r--r--dts/Bindings/regulator/act8865-regulator.txt1
-rw-r--r--dts/Bindings/regulator/act8945a-regulator.txt1
-rw-r--r--dts/Bindings/regulator/mt6311-regulator.txt2
-rw-r--r--dts/Bindings/regulator/mt6323-regulator.txt2
-rw-r--r--dts/Bindings/regulator/mt6380-regulator.txt89
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-rw-r--r--dts/Bindings/remoteproc/imx-rproc.txt33
-rw-r--r--dts/Bindings/remoteproc/qcom,adsp.txt7
-rw-r--r--dts/Bindings/remoteproc/qcom,q6v5.txt5
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-rw-r--r--dts/Bindings/reset/nxp,lpc1850-rgu.txt1
-rw-r--r--dts/Bindings/reset/renesas,rst.txt1
-rw-r--r--dts/Bindings/reset/uniphier-reset.txt27
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-rw-r--r--dts/Bindings/rtc/google,goldfish-rtc.txt17
-rw-r--r--dts/Bindings/rtc/isil,isl12057.txt1
-rw-r--r--dts/Bindings/rtc/realtek,rtd119x.txt16
-rw-r--r--dts/Bindings/rtc/st,stm32-rtc.txt1
-rw-r--r--dts/Bindings/rtc/sun6i-rtc.txt4
-rw-r--r--dts/Bindings/scsi/hisilicon-sas.txt1
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-rw-r--r--dts/Bindings/serial/arc-uart.txt1
-rw-r--r--dts/Bindings/serial/axis,etraxfs-uart.txt1
-rw-r--r--dts/Bindings/serial/mtk-uart.txt1
-rw-r--r--dts/Bindings/serial/nvidia,tegra20-hsuart.txt1
-rw-r--r--dts/Bindings/serial/qcom,msm-uartdm.txt3
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt2
-rw-r--r--dts/Bindings/serial/rs485.txt5
-rw-r--r--dts/Bindings/serial/serial.txt2
-rw-r--r--dts/Bindings/serial/st,stm32-usart.txt17
-rw-r--r--dts/Bindings/serio/allwinner,sun4i-ps2.txt1
-rw-r--r--dts/Bindings/serio/ps2-gpio.txt23
-rw-r--r--dts/Bindings/soc/mediatek/scpsys.txt3
-rw-r--r--dts/Bindings/soc/qcom/qcom,glink.txt13
-rw-r--r--dts/Bindings/soc/qcom/qcom,gsbi.txt1
-rw-r--r--dts/Bindings/soc/rockchip/grf.txt3
-rw-r--r--dts/Bindings/soc/rockchip/power_domain.txt3
-rw-r--r--dts/Bindings/soc/ti/sci-pm-domain.txt5
-rw-r--r--dts/Bindings/sound/armada-370db-audio.txt1
-rw-r--r--dts/Bindings/sound/atmel-classd.txt9
-rw-r--r--dts/Bindings/sound/axentia,tse850-pcm5142.txt1
-rw-r--r--dts/Bindings/sound/brcm,cygnus-audio.txt4
-rw-r--r--dts/Bindings/sound/cs43130.txt67
-rw-r--r--dts/Bindings/sound/davinci-mcbsp.txt1
-rw-r--r--dts/Bindings/sound/dmic.txt16
-rw-r--r--dts/Bindings/sound/fsl,asrc.txt1
-rw-r--r--dts/Bindings/sound/fsl,esai.txt1
-rw-r--r--dts/Bindings/sound/fsl,spdif.txt1
-rw-r--r--dts/Bindings/sound/hdmi.txt1
-rw-r--r--dts/Bindings/sound/mt2701-afe-pcm.txt4
-rw-r--r--dts/Bindings/sound/qcom,msm8916-wcd-analog.txt18
-rw-r--r--dts/Bindings/sound/renesas,rsnd.txt70
-rw-r--r--dts/Bindings/sound/rockchip,pdm.txt8
-rw-r--r--dts/Bindings/sound/rockchip,rk3399-gru-sound.txt2
-rw-r--r--dts/Bindings/sound/rockchip-i2s.txt4
-rw-r--r--dts/Bindings/sound/rockchip-spdif.txt1
-rw-r--r--dts/Bindings/sound/rt274.txt33
-rw-r--r--dts/Bindings/sound/rt5663.txt8
-rw-r--r--dts/Bindings/sound/samsung,odroid.txt6
-rw-r--r--dts/Bindings/sound/simple-card.txt3
-rw-r--r--dts/Bindings/sound/simple-scu-card.txt1
-rw-r--r--dts/Bindings/sound/st,sti-asoc-card.txt5
-rw-r--r--dts/Bindings/sound/sun4i-i2s.txt2
-rw-r--r--dts/Bindings/sound/sunxi,sun4i-spdif.txt1
-rw-r--r--dts/Bindings/sound/tas5720.txt1
-rw-r--r--dts/Bindings/sound/tlv320aic32x4.txt13
-rw-r--r--dts/Bindings/sound/tlv320aic3x.txt5
-rw-r--r--dts/Bindings/sound/wm8524.txt16
-rw-r--r--dts/Bindings/sound/zte,zx-i2s.txt1
-rw-r--r--dts/Bindings/sound/zte,zx-spdif.txt1
-rw-r--r--dts/Bindings/spi/efm32-spi.txt2
-rw-r--r--dts/Bindings/spi/fsl-imx-cspi.txt1
-rw-r--r--dts/Bindings/spi/nvidia,tegra114-spi.txt1
-rw-r--r--dts/Bindings/spi/nvidia,tegra20-sflash.txt1
-rw-r--r--dts/Bindings/spi/nvidia,tegra20-slink.txt1
-rw-r--r--dts/Bindings/spi/sh-hspi.txt1
-rw-r--r--dts/Bindings/spi/sh-msiof.txt2
-rw-r--r--dts/Bindings/spi/spi-clps711x.txt1
-rw-r--r--dts/Bindings/spi/spi-fsl-dspi.txt1
-rw-r--r--dts/Bindings/spi/spi-mt65xx.txt1
-rw-r--r--dts/Bindings/spi/spi-orion.txt2
-rw-r--r--dts/Bindings/spi/spi-rockchip.txt1
-rw-r--r--dts/Bindings/spi/spi-sun4i.txt1
-rw-r--r--dts/Bindings/spi/spi-sun6i.txt1
-rw-r--r--dts/Bindings/spi/spi_atmel.txt1
-rw-r--r--dts/Bindings/sram/renesas,smp-sram.txt27
-rw-r--r--dts/Bindings/sram/sunxi-sram.txt10
-rw-r--r--dts/Bindings/thermal/armada-thermal.txt1
-rw-r--r--dts/Bindings/thermal/exynos-thermal.txt1
-rw-r--r--dts/Bindings/thermal/mediatek-thermal.txt1
-rw-r--r--dts/Bindings/thermal/rcar-gen3-thermal.txt1
-rw-r--r--dts/Bindings/thermal/rockchip-thermal.txt1
-rw-r--r--dts/Bindings/thermal/uniphier-thermal.txt64
-rw-r--r--dts/Bindings/timer/nxp,tpm-timer.txt28
-rw-r--r--dts/Bindings/timer/renesas,cmt.txt73
-rw-r--r--dts/Bindings/trivial-devices.txt14
-rw-r--r--dts/Bindings/unittest.txt5
-rw-r--r--dts/Bindings/usb/allwinner,sun4i-a10-musb.txt1
-rw-r--r--dts/Bindings/usb/am33xx-usb.txt4
-rw-r--r--dts/Bindings/usb/brcm,bdc.txt29
-rw-r--r--dts/Bindings/usb/da8xx-usb.txt2
-rw-r--r--dts/Bindings/usb/dwc3-st.txt1
-rw-r--r--dts/Bindings/usb/dwc3-xilinx.txt1
-rw-r--r--dts/Bindings/usb/ehci-st.txt1
-rw-r--r--dts/Bindings/usb/exynos-usb.txt2
-rw-r--r--dts/Bindings/usb/fcs,fusb302.txt29
-rw-r--r--dts/Bindings/usb/isp1301.txt1
-rw-r--r--dts/Bindings/usb/keystone-usb.txt18
-rw-r--r--dts/Bindings/usb/mediatek,mtk-xhci.txt (renamed from dts/Bindings/usb/mt8173-xhci.txt)14
-rw-r--r--dts/Bindings/usb/mediatek,mtu3.txt (renamed from dts/Bindings/usb/mt8173-mtu3.txt)10
-rw-r--r--dts/Bindings/usb/ohci-st.txt1
-rw-r--r--dts/Bindings/usb/qcom,dwc3.txt3
-rw-r--r--dts/Bindings/usb/renesas_usb3.txt16
-rw-r--r--dts/Bindings/usb/rockchip,dwc3.txt4
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-rw-r--r--dts/Bindings/w1/fsl-imx-owire.txt1
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-rw-r--r--dts/Bindings/watchdog/mtk-wdt.txt8
-rw-r--r--dts/Bindings/watchdog/renesas-wdt.txt1
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-rw-r--r--dts/include/dt-bindings/clock/gxbb-aoclkc.h1
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-rw-r--r--dts/include/dt-bindings/clock/meson8b-clkc.h70
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-msm8996.h2
-rw-r--r--dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h57
-rw-r--r--dts/include/dt-bindings/clock/rk3228-cru.h1
-rw-r--r--dts/include/dt-bindings/clock/rv1108-cru.h125
-rw-r--r--dts/include/dt-bindings/clock/stm32h7-clks.h165
-rw-r--r--dts/include/dt-bindings/clock/sun4i-a10-ccu.h200
-rw-r--r--dts/include/dt-bindings/clock/sun7i-a20-ccu.h53
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-rw-r--r--dts/include/dt-bindings/pinctrl/dra.h3
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-rw-r--r--dts/include/dt-bindings/power/r8a77995-sysc.h23
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-rw-r--r--dts/src/arm64/broadcom/stingray/bcm958742k.dts4
-rw-r--r--dts/src/arm64/broadcom/stingray/bcm958742t.dts4
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray-fs4.dtsi118
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray-sata.dtsi278
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray.dtsi136
-rw-r--r--dts/src/arm64/exynos/exynos5433-tm2-common.dtsi25
-rw-r--r--dts/src/arm64/exynos/exynos5433.dtsi4
-rw-r--r--dts/src/arm64/exynos/exynos7-espresso.dts2
-rw-r--r--dts/src/arm64/freescale/fsl-ls1012a.dtsi17
-rw-r--r--dts/src/arm64/freescale/fsl-ls1043a.dtsi12
-rw-r--r--dts/src/arm64/freescale/fsl-ls1046a.dtsi31
-rw-r--r--dts/src/arm64/freescale/fsl-ls1088a-rdb.dts2
-rw-r--r--dts/src/arm64/freescale/fsl-ls1088a.dtsi65
-rw-r--r--dts/src/arm64/freescale/fsl-ls2080a-qds.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2080a-rdb.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2080a-simu.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2080a.dtsi17
-rw-r--r--dts/src/arm64/freescale/fsl-ls2088a-qds.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2088a-rdb.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2088a.dtsi17
-rw-r--r--dts/src/arm64/freescale/fsl-ls208xa.dtsi51
-rw-r--r--dts/src/arm64/hisilicon/hi3660-hikey960.dts37
-rw-r--r--dts/src/arm64/hisilicon/hi3660.dtsi130
-rw-r--r--dts/src/arm64/hisilicon/hi6220.dtsi9
-rw-r--r--dts/src/arm64/hisilicon/hip07-d05.dts4
-rw-r--r--dts/src/arm64/hisilicon/hip07.dtsi22
-rw-r--r--dts/src/arm64/marvell/armada-3720-espressobin.dts30
-rw-r--r--dts/src/arm64/marvell/armada-37xx.dtsi11
-rw-r--r--dts/src/arm64/marvell/armada-7040-db.dts39
-rw-r--r--dts/src/arm64/marvell/armada-8040-db.dts65
-rw-r--r--dts/src/arm64/marvell/armada-8040-mcbin.dts124
-rw-r--r--dts/src/arm64/marvell/armada-8080-db.dts67
-rw-r--r--dts/src/arm64/marvell/armada-8080.dtsi53
-rw-r--r--dts/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi104
-rw-r--r--dts/src/arm64/marvell/armada-ap810-ap0.dtsi163
-rw-r--r--dts/src/arm64/marvell/armada-cp110-master.dtsi83
-rw-r--r--dts/src/arm64/marvell/armada-cp110-slave.dtsi83
-rw-r--r--dts/src/arm64/mediatek/mt2712-evb.dts32
-rw-r--r--dts/src/arm64/mediatek/mt2712e.dtsi171
-rw-r--r--dts/src/arm64/mediatek/mt6797.dtsi12
-rw-r--r--dts/src/arm64/mediatek/mt7622-rfb1.dts27
-rw-r--r--dts/src/arm64/mediatek/mt7622.dtsi110
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi1
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc.dtsi17
-rw-r--r--dts/src/arm64/qcom/apq8096-db820c-pmic-pins.dtsi24
-rw-r--r--dts/src/arm64/qcom/apq8096-db820c.dtsi198
-rw-r--r--dts/src/arm64/qcom/ipq8074-hk01.dts52
-rw-r--r--dts/src/arm64/qcom/ipq8074.dtsi194
-rw-r--r--dts/src/arm64/qcom/msm8916.dtsi120
-rw-r--r--dts/src/arm64/qcom/msm8996.dtsi314
-rw-r--r--dts/src/arm64/qcom/pmi8994.dtsi17
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts2
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts2
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1.dtsi9
-rw-r--r--dts/src/arm64/renesas/r8a7795-h3ulcb.dts16
-rw-r--r--dts/src/arm64/renesas/r8a7795-salvator-x.dts2
-rw-r--r--dts/src/arm64/renesas/r8a7795-salvator-xs.dts8
-rw-r--r--dts/src/arm64/renesas/r8a7795.dtsi314
-rw-r--r--dts/src/arm64/renesas/r8a7796-m3ulcb.dts14
-rw-r--r--dts/src/arm64/renesas/r8a7796-salvator-x.dts31
-rw-r--r--dts/src/arm64/renesas/r8a7796.dtsi414
-rw-r--r--dts/src/arm64/renesas/r8a77995-draak.dts46
-rw-r--r--dts/src/arm64/renesas/r8a77995.dtsi155
-rw-r--r--dts/src/arm64/renesas/salvator-common.dtsi4
-rw-r--r--dts/src/arm64/renesas/salvator-xs.dtsi10
-rw-r--r--dts/src/arm64/renesas/ulcb.dtsi51
-rw-r--r--dts/src/arm64/rockchip/rk3328-evb.dts181
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock64.dts333
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi437
-rw-r--r--dts/src/arm64/rockchip/rk3368-evb.dtsi1
-rw-r--r--dts/src/arm64/rockchip/rk3368-geekbox.dts1
-rw-r--r--dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3368-px5-evb.dts3
-rw-r--r--dts/src/arm64/rockchip/rk3368-r88.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3368.dtsi140
-rw-r--r--dts/src/arm64/rockchip/rk3399-evb.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3399-firefly.dts16
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-kevin.dts44
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru.dtsi132
-rw-r--r--dts/src/arm64/rockchip/rk3399-op1-opp.dtsi33
-rw-r--r--dts/src/arm64/rockchip/rk3399-opp.dtsi33
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma-haikou.dts228
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma.dtsi547
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire-excavator.dts240
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire.dtsi644
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi292
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-global.dts6
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-ref.dts6
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11.dtsi35
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-global.dts6
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-ref.dts6
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20.dtsi37
-rw-r--r--dts/src/arm64/socionext/uniphier-pinctrl.dtsi142
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3-ref.dts62
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3.dtsi367
-rw-r--r--dts/src/arm64/socionext/uniphier-ref-daughter.dtsi17
-rw-r--r--dts/src/arm64/socionext/uniphier-support-card.dtsi35
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108-clk.dtsi50
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108.dts18
-rw-r--r--dts/src/arm64/xilinx/zynqmp.dtsi277
-rw-r--r--dts/src/arm64/zte/zx296718-evb.dts68
-rw-r--r--dts/src/arm64/zte/zx296718-pcbox.dts143
-rw-r--r--dts/src/arm64/zte/zx296718.dtsi171
-rw-r--r--dts/src/mips/ingenic/ci20.dts37
-rw-r--r--dts/src/mips/ingenic/jz4780.dtsi11
-rw-r--r--dts/src/mips/ni/169445.dts100
-rw-r--r--dts/src/mips/ralink/mt7628a.dtsi126
-rw-r--r--dts/src/mips/ralink/omega2p.dts18
-rw-r--r--dts/src/mips/ralink/vocore2.dts18
-rw-r--r--dts/src/nios2/3c120_devboard.dts3
-rw-r--r--dts/src/powerpc/fsp2.dts33
981 files changed, 29785 insertions, 4030 deletions
diff --git a/dts/Bindings/arc/hsdk.txt b/dts/Bindings/arc/hsdk.txt
new file mode 100644
index 0000000000..be50654bbf
--- /dev/null
+++ b/dts/Bindings/arc/hsdk.txt
@@ -0,0 +1,7 @@
+Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
+---------------------------------------------------------------------------
+
+ARC HSDK Board with quad-core ARC HS38x4 in silicon.
+
+Required root node properties:
+ - compatible = "snps,hsdk";
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index 0fff40a633..4e4bc0bae5 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -1,6 +1,18 @@
Amlogic MesonX device tree bindings
-------------------------------------------
+Work in progress statement:
+
+Device tree files and bindings applying to Amlogic SoCs and boards are
+considered "unstable". Any Amlogic device tree binding may change at
+any time. Be sure to use a device tree binary and a kernel image
+generated from the same source tree.
+
+Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
+stable binding/ABI.
+
+---------------------------------------------------------------
+
Boards with the Amlogic Meson6 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson6"
@@ -61,3 +73,32 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,q201" (Meson gxm s912)
- "kingnovel,r-box-pro" (Meson gxm S912)
- "nexbox,a1" (Meson gxm s912)
+
+Amlogic Meson Firmware registers Interface
+------------------------------------------
+
+The Meson SoCs have a register bank with status and data shared with the
+secure firmware.
+
+Required properties:
+ - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
+
+Properties should indentify components of this register interface :
+
+Meson GX SoC Information
+------------------------
+A firmware register encodes the SoC type, package and revision information on
+the Meson GX SoCs.
+If present, the following property should be added :
+
+Optional properties:
+ - amlogic,has-chip-id: If present, the interface gives the current SoC version.
+
+Example
+-------
+
+ao-secure@140 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x0 0x140 0x0 0x140>;
+ amlogic,has-chip-id;
+};
diff --git a/dts/Bindings/arm/arch_timer.txt b/dts/Bindings/arm/arch_timer.txt
index e926aea114..68301b77e8 100644
--- a/dts/Bindings/arm/arch_timer.txt
+++ b/dts/Bindings/arm/arch_timer.txt
@@ -108,6 +108,5 @@ Example:
frame-number = <1>
interrupts = <0 15 0x8>;
reg = <0xf0003000 0x1000>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/arm/bcm/brcm,bcm2835.txt b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
index 9c97de2391..3e3efa046a 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm2835.txt
+++ b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
@@ -42,6 +42,10 @@ Raspberry Pi Zero
Required root node properties:
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
+Raspberry Pi Zero W
+Required root node properties:
+compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
+
Generic BCM2835 board
Required root node properties:
compatible = "brcm,bcm2835";
diff --git a/dts/Bindings/arm/bhf.txt b/dts/Bindings/arm/bhf.txt
new file mode 100644
index 0000000000..886b503caf
--- /dev/null
+++ b/dts/Bindings/arm/bhf.txt
@@ -0,0 +1,6 @@
+Beckhoff Automation Platforms Device Tree Bindings
+--------------------------------------------------
+
+CX9020 Embedded PC
+Required root node properties:
+ - compatible = "bhf,cx9020", "fsl,imx53";
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index fcbae6a5e6..15ac8e8dcf 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -34,8 +34,8 @@ its hardware characteristcs.
- Embedded Trace Macrocell (version 4.x):
"arm,coresight-etm4x", "arm,primecell";
- - Qualcomm Configurable Replicator (version 1.x):
- "qcom,coresight-replicator1x", "arm,primecell";
+ - Coresight programmable Replicator :
+ "arm,coresight-dynamic-replicator", "arm,primecell";
- System Trace Macrocell:
"arm,coresight-stm", "arm,primecell"; [1]
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index a44253cad2..b92f12bd52 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -200,6 +200,7 @@ described below.
"arm,realview-smp"
"brcm,bcm11351-cpu-method"
"brcm,bcm23550"
+ "brcm,bcm2836-smp"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"
diff --git a/dts/Bindings/arm/marvell/armada-8kp.txt b/dts/Bindings/arm/marvell/armada-8kp.txt
new file mode 100644
index 0000000000..f3e9624534
--- /dev/null
+++ b/dts/Bindings/arm/marvell/armada-8kp.txt
@@ -0,0 +1,15 @@
+Marvell Armada 8KPlus Platforms Device Tree Bindings
+----------------------------------------------------
+
+Boards using a SoC of the Marvell Armada 8KP families must carry
+the following root node property:
+
+ - compatible, with one of the following values:
+
+ - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810"
+ when the SoC being used is the Armada 8080
+
+Example:
+
+compatible = "marvell,armada-8080-db", "marvell,armada-8080",
+ "marvell,armada-ap810-octa", "marvell,armada-ap810"
diff --git a/dts/Bindings/arm/marvell/cp110-system-controller0.txt b/dts/Bindings/arm/marvell/cp110-system-controller0.txt
index 171d02cade..29cdbae6c5 100644
--- a/dts/Bindings/arm/marvell/cp110-system-controller0.txt
+++ b/dts/Bindings/arm/marvell/cp110-system-controller0.txt
@@ -183,7 +183,6 @@ cpm_syscon0: system-controller@440000 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 0 32>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index da7bd138e6..91d5178494 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -1,12 +1,12 @@
-MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
+MediaTek SoC based Platforms Device Tree Bindings
-Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
-following property:
+Boards with a MediaTek SoC shall have the following property:
Required root node property:
compatible: Must contain one of
"mediatek,mt2701"
+ "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -14,7 +14,8 @@ compatible: Must contain one of
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
- "mediatek,mt7623"
+ "mediatek,mt7623" which is referred to MT7623N SoC
+ "mediatek,mt7623a"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
@@ -25,6 +26,9 @@ Supported boards:
- Evaluation board for MT2701:
Required root node properties:
- compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+ Required root node properties:
+ - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
- Evaluation board for MT6580:
Required root node properties:
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
@@ -46,9 +50,11 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
-- Evaluation board for MT7623:
+- Reference board for MT7623n with NAND:
Required root node properties:
- - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
+ - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+- Bananapi BPI-R2 board:
+ - compatible = "bananapi,bpi-r2", "mediatek,mt7623";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/dts/Bindings/arm/omap/omap.txt b/dts/Bindings/arm/omap/omap.txt
index 8219b2c6bb..2ecc712bf7 100644
--- a/dts/Bindings/arm/omap/omap.txt
+++ b/dts/Bindings/arm/omap/omap.txt
@@ -80,6 +80,9 @@ SoCs:
- OMAP5432
compatible = "ti,omap5432", "ti,omap5"
+- DRA762
+ compatible = "ti,dra762", "ti,dra7"
+
- DRA742
compatible = "ti,dra742", "ti,dra74", "ti,dra7"
@@ -154,6 +157,9 @@ Boards:
- AM335X phyCORE-AM335x: Development kit
compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
+- AM335X UC-8100-ME-T: Communication-centric industrial computing platform
+ compatible = "moxa,uc-8100-me-t", "ti,am33xx";
+
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
@@ -184,6 +190,9 @@ Boards:
- AM5718 IDK
compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"
+- DRA762 EVM: Software Development Board for DRA762
+ compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"
+
- DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
diff --git a/dts/Bindings/arm/pmu.txt b/dts/Bindings/arm/pmu.txt
index 61c8b46204..13611a8199 100644
--- a/dts/Bindings/arm/pmu.txt
+++ b/dts/Bindings/arm/pmu.txt
@@ -9,9 +9,11 @@ Required properties:
- compatible : should be one of
"apm,potenza-pmu"
"arm,armv8-pmuv3"
+ "arm,cortex-a73-pmu"
"arm,cortex-a72-pmu"
"arm,cortex-a57-pmu"
"arm,cortex-a53-pmu"
+ "arm,cortex-a35-pmu"
"arm,cortex-a17-pmu"
"arm,cortex-a15-pmu"
"arm,cortex-a12-pmu"
diff --git a/dts/Bindings/arm/qcom.txt b/dts/Bindings/arm/qcom.txt
index 028d16e721..0ed4d39d7f 100644
--- a/dts/Bindings/arm/qcom.txt
+++ b/dts/Bindings/arm/qcom.txt
@@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
msm8994
msm8996
mdm9615
+ ipq8074
The 'board' element must be one of the following strings:
@@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
dragonboard
mtp
sbc
+ hk01
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 11c0ac4a2d..b003148e29 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -134,6 +134,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
+- Pine64 Rock64 board:
+ Required root node properties:
+ - compatible = "pine64,rock64", "rockchip,rk3328";
+
- Rockchip PX3 Evaluation board:
Required root node properties:
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
@@ -173,6 +177,14 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
+- Rockchip RK3399 Sapphire Excavator board:
+ Required root node properties:
+ - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
+
+- Theobroma Systems RK3399-Q7 Haikou Baseboard:
+ Required root node properties:
+ - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
+
- Tronsmart Orion R68 Meta
Required root node properties:
- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index 1a671e3298..ae75cb3b13 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -39,6 +39,8 @@ SoCs:
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
+ - R-Car D3 (R8A77995)
+ compatible = "renesas,r8a77995"
Boards:
@@ -53,6 +55,8 @@ Boards:
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
+ - Draak (RTP0RC77995SEB0010S)
+ compatible = "renesas,draak", "renesas,r8a77995"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- GR-Peach (X28A-M01-E/F)
@@ -64,6 +68,10 @@ Boards:
compatible = "renesas,h3ulcb", "renesas,r8a7795";
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
+ - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
+ compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
+ - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
+ compatible = "iwave,g22m", "renesas,r8a7745"
- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
diff --git a/dts/Bindings/ata/ahci-mtk.txt b/dts/Bindings/ata/ahci-mtk.txt
new file mode 100644
index 0000000000..d2aa696b16
--- /dev/null
+++ b/dts/Bindings/ata/ahci-mtk.txt
@@ -0,0 +1,51 @@
+MediaTek Serial ATA controller
+
+Required properties:
+ - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
+ When using "mediatek,mtk-ahci" compatible strings, you
+ need SoC specific ones in addition, one of:
+ - "mediatek,mt7622-ahci"
+ - reg : Physical base addresses and length of register sets.
+ - interrupts : Interrupt associated with the SATA device.
+ - interrupt-names : Associated name must be: "hostc".
+ - clocks : A list of phandle and clock specifier pairs, one for each
+ entry in clock-names.
+ - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
+ - phys : A phandle and PHY specifier pair for the PHY port.
+ - phy-names : Associated name must be: "sata-phy".
+ - ports-implemented : See ./ahci-platform.txt for details.
+
+Optional properties:
+ - power-domains : A phandle and power domain specifier pair to the power
+ domain which is responsible for collapsing and restoring
+ power to the peripheral.
+ - resets : Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names : Associated names must be: "axi", "sw", "reg".
+ - mediatek,phy-mode : A phandle to the system controller, used to enable
+ SATA function.
+
+Example:
+
+ sata: sata@1a200000 {
+ compatible = "mediatek,mt7622-ahci",
+ "mediatek,mtk-ahci";
+ reg = <0 0x1a200000 0 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&u3port1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ };
diff --git a/dts/Bindings/ata/apm-xgene.txt b/dts/Bindings/ata/apm-xgene.txt
index a668f0e7d0..02e690a675 100644
--- a/dts/Bindings/ata/apm-xgene.txt
+++ b/dts/Bindings/ata/apm-xgene.txt
@@ -57,7 +57,6 @@ Example:
<0x0 0x1f227000 0x0 0x1000>;
interrupts = <0x0 0x87 0x4>;
dma-coherent;
- status = "ok";
clocks = <&sataclk 0>;
phys = <&phy2 0>;
phy-names = "sata-phy";
@@ -72,7 +71,6 @@ Example:
<0x0 0x1f237000 0x0 0x1000>;
interrupts = <0x0 0x88 0x4>;
dma-coherent;
- status = "ok";
clocks = <&sataclk 0>;
phys = <&phy3 0>;
phy-names = "sata-phy";
diff --git a/dts/Bindings/ata/imx-pata.txt b/dts/Bindings/ata/imx-pata.txt
index e38d73414b..f1172f0018 100644
--- a/dts/Bindings/ata/imx-pata.txt
+++ b/dts/Bindings/ata/imx-pata.txt
@@ -13,5 +13,4 @@ Example:
reg = <0x83fe0000 0x4000>;
interrupts = <70>;
clocks = <&clks 161>;
- status = "disabled";
};
diff --git a/dts/Bindings/bus/mvebu-mbus.txt b/dts/Bindings/bus/mvebu-mbus.txt
index fa6cde41b4..f2ab7fd013 100644
--- a/dts/Bindings/bus/mvebu-mbus.txt
+++ b/dts/Bindings/bus/mvebu-mbus.txt
@@ -227,7 +227,6 @@ See the example below, where a more complete device tree is shown:
};
devbus-bootcs {
- status = "okay";
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
/* NOR */
@@ -240,7 +239,6 @@ See the example below, where a more complete device tree is shown:
pcie-controller {
compatible = "marvell,armada-xp-pcie";
- status = "okay";
device_type = "pci";
#address-cells = <3>;
@@ -258,7 +256,6 @@ See the example below, where a more complete device tree is shown:
pcie@1,0 {
/* Port 0, Lane 0 */
- status = "okay";
};
};
diff --git a/dts/Bindings/bus/nvidia,tegra20-gmi.txt b/dts/Bindings/bus/nvidia,tegra20-gmi.txt
index 83b0e54f72..3e21eb8228 100644
--- a/dts/Bindings/bus/nvidia,tegra20-gmi.txt
+++ b/dts/Bindings/bus/nvidia,tegra20-gmi.txt
@@ -84,7 +84,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
- status = "okay";
bus@4,0 {
compatible = "simple-bus";
@@ -121,7 +120,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
- status = "okay";
can@4,0 {
reg = <4 0 0x100>;
diff --git a/dts/Bindings/bus/nvidia,tegra210-aconnect.txt b/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
index 7ff13be175..3108d03802 100644
--- a/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
+++ b/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
@@ -33,7 +33,6 @@ Example:
#size-cells = <1>;
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
- status = "disabled";
child1 {
...
diff --git a/dts/Bindings/chosen.txt b/dts/Bindings/chosen.txt
index dee3f5d9df..e3b13ea7d2 100644
--- a/dts/Bindings/chosen.txt
+++ b/dts/Bindings/chosen.txt
@@ -5,9 +5,31 @@ The chosen node does not represent a real device, but serves as a place
for passing data between firmware and the operating system, like boot
arguments. Data in the chosen node does not represent the hardware.
+The following properties are recognized:
-stdout-path property
---------------------
+
+kaslr-seed
+-----------
+
+This property is used when booting with CONFIG_RANDOMIZE_BASE as the
+entropy used to randomize the kernel image base address location. Since
+it is used directly, this value is intended only for KASLR, and should
+not be used for other purposes (as it may leak information about KASLR
+offsets). It is parsed as a u64 value, e.g.
+
+/ {
+ chosen {
+ kaslr-seed = <0xfeedbeef 0xc0def00d>;
+ };
+};
+
+Note that if this property is set from UEFI (or a bootloader in EFI
+mode) when EFI_RNG_PROTOCOL is supported, it will be overwritten by
+the Linux EFI stub (which will populate the property itself, using
+EFI_RNG_PROTOCOL).
+
+stdout-path
+-----------
Device trees may specify the device to be used for boot console output
with a stdout-path property under /chosen, as described in the Devicetree
diff --git a/dts/Bindings/clock/alphascale,acc.txt b/dts/Bindings/clock/alphascale,acc.txt
index 62e67e883e..b3205b21c9 100644
--- a/dts/Bindings/clock/alphascale,acc.txt
+++ b/dts/Bindings/clock/alphascale,acc.txt
@@ -102,7 +102,6 @@ uart4: serial@80010000 {
reg = <0x80010000 0x4000>;
clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
interrupts = <19>;
- status = "disabled";
};
Clock consumer with only one, _AHB_ sink.
diff --git a/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt b/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt
index a55d31b48d..786dc39ca9 100644
--- a/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC.
Required Properties:
-- compatible: should be "amlogic,gxbb-aoclkc"
-- reg: physical base address of the clock controller and length of memory
- mapped region.
+- compatible: value should be different for each SoC family as :
+ - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
+ - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
+ - GXM (S912) : "amlogic,meson-gxm-aoclkc"
+ followed by the common "amlogic,meson-gx-aoclkc"
- #clock-cells: should be 1.
@@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
used in device tree sources.
+Parent node should have the following properties :
+- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
+- reg: base address and size of the AO system control register space.
+
Example: AO Clock controller node:
- clkc_AO: clock-controller@040 {
- compatible = "amlogic,gxbb-aoclkc";
- reg = <0x0 0x040 0x0 0x4>;
+ao_sysctrl: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+ reg = <0x0 0x0 0x0 0x100>;
+
+ clkc_AO: clock-controller {
+ compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
};
+};
Example: UART controller node that consumes the clock and reset generated
by the clock controller:
@@ -41,5 +51,4 @@ Example: UART controller node that consumes the clock and reset generated
interrupts = <0 90 1>;
clocks = <&clkc_AO CLKID_AO_UART1>;
resets = <&clkc_AO RESET_AO_UART1>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/amlogic,gxbb-clkc.txt b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
index a09d627b55..9240407691 100644
--- a/dts/Bindings/clock/amlogic,gxbb-clkc.txt
+++ b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
@@ -33,5 +33,4 @@ Example: UART controller node that consumes the clock generated by the clock
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/amlogic,meson8b-clkc.txt b/dts/Bindings/clock/amlogic,meson8b-clkc.txt
index 606da38c09..b455c5aa91 100644
--- a/dts/Bindings/clock/amlogic,meson8b-clkc.txt
+++ b/dts/Bindings/clock/amlogic,meson8b-clkc.txt
@@ -16,18 +16,25 @@ Required Properties:
mapped region.
- #clock-cells: should be 1.
+- #reset-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
used in device tree sources.
+Similarly a preprocessor macro for each reset line is defined in
+dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
+device tree sources).
+
+
Example: Clock controller node:
clkc: clock-controller@c1104000 {
- #clock-cells = <1>;
compatible = "amlogic,meson8b-clkc";
reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
@@ -39,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/at91-clock.txt b/dts/Bindings/clock/at91-clock.txt
index 5f3ad65daf..51c259a92d 100644
--- a/dts/Bindings/clock/at91-clock.txt
+++ b/dts/Bindings/clock/at91-clock.txt
@@ -81,6 +81,16 @@ Required properties:
"atmel,sama5d2-clk-generated":
at91 generated clock
+ "atmel,sama5d2-clk-audio-pll-frac":
+ at91 audio fractional pll
+
+ "atmel,sama5d2-clk-audio-pll-pad":
+ at91 audio pll CLK_AUDIO output pin
+
+ "atmel,sama5d2-clk-audio-pll-pmc"
+ at91 audio pll output on AUDIOPLLCLK that feeds the PMC
+ and can be used by peripheral clock or generic clock
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
diff --git a/dts/Bindings/clock/brcm,kona-ccu.txt b/dts/Bindings/clock/brcm,kona-ccu.txt
index 5286e260fc..8e5a7d8685 100644
--- a/dts/Bindings/clock/brcm,kona-ccu.txt
+++ b/dts/Bindings/clock/brcm,kona-ccu.txt
@@ -46,7 +46,6 @@ Device tree example:
uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
- status = "disabled";
reg = <0x3e002000 0x1000>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/Bindings/clock/exynos5433-clock.txt b/dts/Bindings/clock/exynos5433-clock.txt
index 1dc80f8811..fe885abc9c 100644
--- a/dts/Bindings/clock/exynos5433-clock.txt
+++ b/dts/Bindings/clock/exynos5433-clock.txt
@@ -465,5 +465,4 @@ Example 3: UART controller node that consumes the clock generated by the clock
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/hi3660-clock.txt b/dts/Bindings/clock/hi3660-clock.txt
index cc9b86c357..0035a7ecaf 100644
--- a/dts/Bindings/clock/hi3660-clock.txt
+++ b/dts/Bindings/clock/hi3660-clock.txt
@@ -38,5 +38,4 @@ Examples:
clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/hix5hd2-clock.txt b/dts/Bindings/clock/hix5hd2-clock.txt
index 7894a64887..4733e58e49 100644
--- a/dts/Bindings/clock/hix5hd2-clock.txt
+++ b/dts/Bindings/clock/hix5hd2-clock.txt
@@ -27,5 +27,4 @@ Examples:
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/idt,versaclock5.txt b/dts/Bindings/clock/idt,versaclock5.txt
index 53d7e50ed8..05a245c9df 100644
--- a/dts/Bindings/clock/idt,versaclock5.txt
+++ b/dts/Bindings/clock/idt,versaclock5.txt
@@ -1,24 +1,32 @@
-Binding for IDT VersaClock5 programmable i2c clock generator.
+Binding for IDT VersaClock 5,6 programmable i2c clock generators.
-The IDT VersaClock5 are programmable i2c clock generators providing
-from 3 to 12 output clocks.
+The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
+generators providing from 3 to 12 output clocks.
==I2C device node==
Required properties:
-- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
- "idt,5p49v5935".
+- compatible: shall be one of
+ "idt,5p49v5923"
+ "idt,5p49v5925"
+ "idt,5p49v5933"
+ "idt,5p49v5935"
+ "idt,5p49v6901"
- reg: i2c device address, shall be 0x68 or 0x6a.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock handles,
- - 5p49v5923: (required) either or both of XTAL or CLKIN
+ - 5p49v5923 and
+ 5p49v5925 and
+ 5p49v6901: (required) either or both of XTAL or CLKIN
reference clock.
- 5p49v5933 and
- 5p49v5935: (optional) property not present (internal
Xtal used) or CLKIN reference
clock.
- clock-names: from common clock binding; clock input names, can be
- - 5p49v5923: (required) either or both of "xin", "clkin".
+ - 5p49v5923 and
+ 5p49v5925 and
+ 5p49v6901: (required) either or both of "xin", "clkin".
- 5p49v5933 and
- 5p49v5935: (optional) property not present or "clkin".
@@ -37,6 +45,7 @@ clock specifier, the following mapping applies:
1 -- OUT1
2 -- OUT4
+5P49V5925 and
5P49V5935:
0 -- OUT0_SEL_I2CB
1 -- OUT1
@@ -44,6 +53,13 @@ clock specifier, the following mapping applies:
3 -- OUT3
4 -- OUT4
+5P49V6901:
+ 0 -- OUT0_SEL_I2CB
+ 1 -- OUT1
+ 2 -- OUT2
+ 3 -- OUT3
+ 4 -- OUT4
+
==Example==
/* 25MHz reference crystal */
diff --git a/dts/Bindings/clock/imx21-clock.txt b/dts/Bindings/clock/imx21-clock.txt
index c3b0db437c..806f63d628 100644
--- a/dts/Bindings/clock/imx21-clock.txt
+++ b/dts/Bindings/clock/imx21-clock.txt
@@ -24,5 +24,4 @@ Examples:
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
<&clks IMX21_CLK_PER1>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx23-clock.txt b/dts/Bindings/clock/imx23-clock.txt
index 5083c0b834..8385348d3b 100644
--- a/dts/Bindings/clock/imx23-clock.txt
+++ b/dts/Bindings/clock/imx23-clock.txt
@@ -67,5 +67,4 @@ auart0: serial@8006c000 {
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
clocks = <&clks 32>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx25-clock.txt b/dts/Bindings/clock/imx25-clock.txt
index ba6b312ff8..f8135ea9ca 100644
--- a/dts/Bindings/clock/imx25-clock.txt
+++ b/dts/Bindings/clock/imx25-clock.txt
@@ -157,5 +157,4 @@ uart1: serial@43f90000 {
interrupts = <45>;
clocks = <&clks 79>, <&clks 50>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx27-clock.txt b/dts/Bindings/clock/imx27-clock.txt
index cc05de9ec3..4c95c048d3 100644
--- a/dts/Bindings/clock/imx27-clock.txt
+++ b/dts/Bindings/clock/imx27-clock.txt
@@ -24,5 +24,4 @@ Examples:
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
<&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx28-clock.txt b/dts/Bindings/clock/imx28-clock.txt
index e6587af62f..d84a37d288 100644
--- a/dts/Bindings/clock/imx28-clock.txt
+++ b/dts/Bindings/clock/imx28-clock.txt
@@ -90,5 +90,4 @@ auart0: serial@8006a000 {
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
clocks = <&clks 45>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx31-clock.txt b/dts/Bindings/clock/imx31-clock.txt
index 8163d565f6..0a291090e5 100644
--- a/dts/Bindings/clock/imx31-clock.txt
+++ b/dts/Bindings/clock/imx31-clock.txt
@@ -87,5 +87,4 @@ uart1: serial@43f90000 {
interrupts = <45>;
clocks = <&clks 10>, <&clks 30>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx5-clock.txt b/dts/Bindings/clock/imx5-clock.txt
index cadc4d29ad..a24ca9e582 100644
--- a/dts/Bindings/clock/imx5-clock.txt
+++ b/dts/Bindings/clock/imx5-clock.txt
@@ -25,5 +25,4 @@ can1: can@53fc8000 {
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx6q-clock.txt b/dts/Bindings/clock/imx6q-clock.txt
index 9252912a5b..aa0a4d423e 100644
--- a/dts/Bindings/clock/imx6q-clock.txt
+++ b/dts/Bindings/clock/imx6q-clock.txt
@@ -27,5 +27,4 @@ uart1: serial@02020000 {
interrupts = <0 26 0x04>;
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/mt8173-cpu-dvfs.txt b/dts/Bindings/clock/mt8173-cpu-dvfs.txt
deleted file mode 100644
index 52b457c23e..0000000000
--- a/dts/Bindings/clock/mt8173-cpu-dvfs.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
-
-Required properties:
-- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
-- clock-names: Should contain the following:
- "cpu" - The multiplexer for clock input of CPU cluster.
- "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
- source (usually MAINPLL) when the original CPU PLL is under
- transition and not stable yet.
- Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
- generic clock consumer properties.
-- proc-supply: Regulator for Vproc of CPU cluster.
-
-Optional properties:
-- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
- needs to do "voltage tracking" to step by step scale up/down Vproc and
- Vsram to fit SoC specific needs. When absent, the voltage scaling
- flow is handled by hardware, hence no software "voltage tracking" is
- needed.
-
-Example:
---------
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x000>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA53SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x001>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA53SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- cpu2: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x100>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA57SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- cpu3: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x101>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA57SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- &cpu0 {
- proc-supply = <&mt6397_vpca15_reg>;
- };
-
- &cpu1 {
- proc-supply = <&mt6397_vpca15_reg>;
- };
-
- &cpu2 {
- proc-supply = <&da9211_vcpu_reg>;
- sram-supply = <&mt6397_vsramca7_reg>;
- };
-
- &cpu3 {
- proc-supply = <&da9211_vcpu_reg>;
- sram-supply = <&mt6397_vsramca7_reg>;
- };
diff --git a/dts/Bindings/clock/nvidia,tegra124-dfll.txt b/dts/Bindings/clock/nvidia,tegra124-dfll.txt
index 63f9d8277d..dff236f524 100644
--- a/dts/Bindings/clock/nvidia,tegra124-dfll.txt
+++ b/dts/Bindings/clock/nvidia,tegra124-dfll.txt
@@ -66,7 +66,6 @@ clock@70110000 {
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
vdd-cpu-supply = <&vdd_cpu>;
- status = "okay";
nvidia,sample-rate = <12500>;
nvidia,droop-ctrl = <0x00000f00>;
diff --git a/dts/Bindings/clock/pxa-clock.txt b/dts/Bindings/clock/pxa-clock.txt
index 4b4a9024bd..8f67239411 100644
--- a/dts/Bindings/clock/pxa-clock.txt
+++ b/dts/Bindings/clock/pxa-clock.txt
@@ -12,5 +12,4 @@ Examples:
pxa2xx_clks: pxa2xx_clks@41300004 {
compatible = "marvell,pxa-clocks";
#clock-cells = <1>;
- status = "okay";
};
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
index 0cd894f987..316e136865 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.txt
+++ b/dts/Bindings/clock/renesas,cpg-mssr.txt
@@ -22,6 +22,7 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+ - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
block
@@ -30,7 +31,7 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796)
+ r8a7795, r8a7796, r8a77995)
- "extalr" (r8a7795, r8a7796)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
@@ -81,5 +82,4 @@ Examples
dma-names = "tx", "rx";
power-domains = <&cpg>;
resets = <&cpg 310>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt b/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
index e4cdaf1cb3..7cc4c0330b 100644
--- a/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -44,5 +44,4 @@ Examples
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
power-domains = <&cpg_clocks>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
new file mode 100644
index 0000000000..e96e085271
--- /dev/null
+++ b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
@@ -0,0 +1,55 @@
+* Renesas R-Car USB 2.0 clock selector
+
+This file provides information on what the device node for the R-Car USB 2.0
+clock selector.
+
+If you connect an external clock to the USB_EXTAL pin only, you should set
+the clock rate to "usb_extal" node only.
+If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
+is not needed because this is default setting. (Of course, you can set the
+clock rates to both "usb_extal" and "usb_xtal" nodes.
+
+Case 1: An external clock connects to R-Car SoC
+ +----------+ +--- R-Car ---------------------+
+ |External |---|USB_EXTAL ---> all usb channels|
+ |clock | |USB_XTAL |
+ +----------+ +-------------------------------+
+In this case, we need this driver with "usb_extal" clock.
+
+Case 2: An oscillator connects to R-Car SoC
+ +----------+ +--- R-Car ---------------------+
+ |Oscillator|---|USB_EXTAL -+-> all usb channels|
+ | |---|USB_XTAL --+ |
+ +----------+ +-------------------------------+
+In this case, we don't need this selector.
+
+Required properties:
+- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
+ an R8A7795 SoC.
+ "renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
+ an R8A7796 SoC.
+ "renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
+ compatible device.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
+- reg: offset and length of the USB 2.0 clock selector register block.
+- clocks: A list of phandles and specifier pairs.
+- clock-names: Name of the clocks.
+ - The functional clock must be "ehci_ohci"
+ - The USB_EXTAL clock pin must be "usb_extal"
+ - The USB_XTAL clock pin must be "usb_xtal"
+- #clock-cells: Must be 0
+
+Example (R-Car H3):
+
+ usb2_clksel: clock-controller@e6590630 {
+ compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
+ "renesas,rcar-gen3-usb2-clock-sel";
+ reg = <0 0xe6590630 0 0x02>;
+ clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
+ clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
+ #clock-cells = <0>;
+ };
diff --git a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt
index bb51a33a1f..bb5d942075 100644
--- a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt
@@ -50,5 +50,4 @@ Examples
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/rockchip,rk3128-cru.txt b/dts/Bindings/clock/rockchip,rk3128-cru.txt
index 455a9a00a6..6f8744fd30 100644
--- a/dts/Bindings/clock/rockchip,rk3128-cru.txt
+++ b/dts/Bindings/clock/rockchip,rk3128-cru.txt
@@ -1,12 +1,14 @@
-* Rockchip RK3128 Clock and Reset Unit
+* Rockchip RK3126/RK3128 Clock and Reset Unit
-The RK3128 clock controller generates and supplies clock to various
+The RK3126/RK3128 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
-- compatible: should be "rockchip,rk3128-cru"
+- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
+ "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
+ "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
diff --git a/dts/Bindings/clock/samsung,s3c2410-clock.txt b/dts/Bindings/clock/samsung,s3c2410-clock.txt
index 822505e715..2632d3f130 100644
--- a/dts/Bindings/clock/samsung,s3c2410-clock.txt
+++ b/dts/Bindings/clock/samsung,s3c2410-clock.txt
@@ -46,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/samsung,s3c2412-clock.txt b/dts/Bindings/clock/samsung,s3c2412-clock.txt
index 2b430960ba..21a8c23e65 100644
--- a/dts/Bindings/clock/samsung,s3c2412-clock.txt
+++ b/dts/Bindings/clock/samsung,s3c2412-clock.txt
@@ -46,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/samsung,s3c2443-clock.txt b/dts/Bindings/clock/samsung,s3c2443-clock.txt
index e67bb05478..985c0f574e 100644
--- a/dts/Bindings/clock/samsung,s3c2443-clock.txt
+++ b/dts/Bindings/clock/samsung,s3c2443-clock.txt
@@ -52,5 +52,4 @@ Example: UART controller node that consumes the clock generated by the clock
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/samsung,s3c64xx-clock.txt b/dts/Bindings/clock/samsung,s3c64xx-clock.txt
index fa171dc4bd..872ee8e0f0 100644
--- a/dts/Bindings/clock/samsung,s3c64xx-clock.txt
+++ b/dts/Bindings/clock/samsung,s3c64xx-clock.txt
@@ -73,5 +73,4 @@ Example: UART controller node that consumes the clock generated by the clock
"clk_uart_baud3";
clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
<&clock SCLK_UART>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/samsung,s5pv210-clock.txt b/dts/Bindings/clock/samsung,s5pv210-clock.txt
index effd9401c1..15b48e20a0 100644
--- a/dts/Bindings/clock/samsung,s5pv210-clock.txt
+++ b/dts/Bindings/clock/samsung,s5pv210-clock.txt
@@ -74,5 +74,4 @@ Example: UART controller node that consumes the clock generated by the clock
"clk_uart_baud1";
clocks = <&clocks UART0>, <&clocks UART0>,
<&clocks SCLK_UART0>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/silabs,si5351.txt b/dts/Bindings/clock/silabs,si5351.txt
index 28b28309f5..a6c4ef343b 100644
--- a/dts/Bindings/clock/silabs,si5351.txt
+++ b/dts/Bindings/clock/silabs,si5351.txt
@@ -12,7 +12,11 @@ generators can be found in [1].
==I2C device node==
Required properties:
-- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
+- compatible: shall be one of the following:
+ "silabs,si5351a" - Si5351a, QFN20 package
+ "silabs,si5351a-msop" - Si5351a, MSOP10 package
+ "silabs,si5351b" - Si5351b, QFN20 package
+ "silabs,si5351c" - Si5351c, QFN20 package
- reg: i2c device address, shall be 0x60 or 0x61.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock
diff --git a/dts/Bindings/clock/snps,hsdk-pll-clock.txt b/dts/Bindings/clock/snps,hsdk-pll-clock.txt
new file mode 100644
index 0000000000..c56c7553c7
--- /dev/null
+++ b/dts/Bindings/clock/snps,hsdk-pll-clock.txt
@@ -0,0 +1,28 @@
+Binding for the HSDK Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,hsdk-<name>-pll-clock"
+ "snps,hsdk-core-pll-clock"
+ "snps,hsdk-gp-pll-clock"
+ "snps,hsdk-hdmi-pll-clock"
+- reg : should contain base register location and length.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+ input_clk: input-clk {
+ clock-frequency = <33333333>;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ cpu_clk: cpu-clk@0 {
+ compatible = "snps,hsdk-core-pll-clock";
+ reg = <0x00 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
+ };
diff --git a/dts/Bindings/clock/snps,pll-clock.txt b/dts/Bindings/clock/snps,pll-clock.txt
new file mode 100644
index 0000000000..11fe487661
--- /dev/null
+++ b/dts/Bindings/clock/snps,pll-clock.txt
@@ -0,0 +1,28 @@
+Binding for the AXS10X Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,axs10x-<name>-pll-clock"
+ "snps,axs10x-arc-pll-clock"
+ "snps,axs10x-pgu-pll-clock"
+- reg: should always contain 2 pairs address - length: first for PLL config
+registers and second for corresponding LOCK CGU register.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+ input-clk: input-clk {
+ clock-frequency = <33333333>;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ core-clk: core-clk@80 {
+ compatible = "snps,axs10x-arc-pll-clock";
+ reg = <0x80 0x10>, <0x100 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input-clk>;
+ };
diff --git a/dts/Bindings/clock/st,stm32h7-rcc.txt b/dts/Bindings/clock/st,stm32h7-rcc.txt
new file mode 100644
index 0000000000..a135504c7d
--- /dev/null
+++ b/dts/Bindings/clock/st,stm32h7-rcc.txt
@@ -0,0 +1,71 @@
+STMicroelectronics STM32H7 Reset and Clock Controller
+=====================================================
+
+The RCC IP is both a reset and a clock controller.
+
+Please refer to clock-bindings.txt for common clock controller binding usage.
+Please also refer to reset.txt for common reset controller binding usage.
+
+Required properties:
+- compatible: Should be:
+ "st,stm32h743-rcc"
+
+- reg: should be register base and length as documented in the
+ datasheet
+
+- #reset-cells: 1, see below
+
+- #clock-cells : from common clock binding; shall be set to 1
+
+- clocks: External oscillator clock phandle
+ - high speed external clock signal (HSE)
+ - low speed external clock signal (LSE)
+ - external I2S clock (I2S_CKIN)
+
+Optional properties:
+- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
+ write protection (RTC clock).
+
+Example:
+
+ rcc: reset-clock-controller@58024400 {
+ compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+ reg = <0x58024400 0x400>;
+ #reset-cells = <1>;
+ #clock-cells = <2>;
+ clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
+
+ st,syscfg = <&pwrcfg>;
+};
+
+The peripheral clock consumer should specify the desired clock by
+having the clock ID in its "clocks" phandle cell.
+
+Example:
+
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&rcc TIM5_CK>;
+ };
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the reset device node and an index specifying
+which channel to use.
+The index is the bit number within the RCC registers bank, starting from RCC
+base address.
+It is calculated as: index = register_offset / 4 * 32 + bit_offset.
+Where bit_offset is the bit offset within the register.
+
+For example, for CRC reset:
+ crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
+
+Example:
+
+ timer2 {
+ resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
+ };
diff --git a/dts/Bindings/clock/sunxi-ccu.txt b/dts/Bindings/clock/sunxi-ccu.txt
index df9fad58fa..7eda08eb8a 100644
--- a/dts/Bindings/clock/sunxi-ccu.txt
+++ b/dts/Bindings/clock/sunxi-ccu.txt
@@ -3,18 +3,24 @@ Allwinner Clock Control Unit Binding
Required properties :
- compatible: must contain one of the following compatibles:
+ - "allwinner,sun4i-a10-ccu"
+ - "allwinner,sun5i-a10s-ccu"
+ - "allwinner,sun5i-a13-ccu"
- "allwinner,sun6i-a31-ccu"
+ - "allwinner,sun7i-a20-ccu"
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-a83t-ccu"
- "allwinner,sun8i-a83t-r-ccu"
- "allwinner,sun8i-h3-ccu"
- "allwinner,sun8i-h3-r-ccu"
++ - "allwinner,sun8i-r40-ccu"
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
+ - "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
diff --git a/dts/Bindings/clock/ti,sci-clk.txt b/dts/Bindings/clock/ti,sci-clk.txt
index 1e884c40ab..4e59dc6b17 100644
--- a/dts/Bindings/clock/ti,sci-clk.txt
+++ b/dts/Bindings/clock/ti,sci-clk.txt
@@ -14,10 +14,9 @@ Required properties:
- compatible: Must be "ti,k2g-sci-clk"
- #clock-cells: Shall be 2.
In clock consumers, this cell represents the device ID and clock ID
- exposed by the PM firmware. The assignments can be found in the header
- files <dt-bindings/genpd/<soc>.h> (which covers the device IDs) and
- <dt-bindings/clock/<soc>.h> (which covers the clock IDs), where <soc>
- is the SoC involved, for example 'k2g'.
+ exposed by the PM firmware. The list of valid values for the device IDs
+ and clocks IDs for 66AK2G SoC are documented at
+ http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data
Examples:
--------
diff --git a/dts/Bindings/clock/ti/dra7-atl.txt b/dts/Bindings/clock/ti/dra7-atl.txt
index 585e8c191f..10f7047755 100644
--- a/dts/Bindings/clock/ti/dra7-atl.txt
+++ b/dts/Bindings/clock/ti/dra7-atl.txt
@@ -81,13 +81,11 @@ atl: atl@4843c000 {
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
clocks = <&atl_gfclk_mux>;
clock-names = "fck";
- status = "disabled";
};
#include <dt-bindings/clk/ti-dra7-atl.h>
&atl {
- status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
diff --git a/dts/Bindings/clock/uniphier-clock.txt b/dts/Bindings/clock/uniphier-clock.txt
index 812163060f..7b5f602765 100644
--- a/dts/Bindings/clock/uniphier-clock.txt
+++ b/dts/Bindings/clock/uniphier-clock.txt
@@ -6,7 +6,6 @@ System clock
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-clock" - for LD4 SoC.
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
@@ -14,6 +13,7 @@ Required properties:
"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-clock" - for LD11 SoC.
"socionext,uniphier-ld20-clock" - for LD20 SoC.
+ "socionext,uniphier-pxs3-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
@@ -48,7 +48,6 @@ Media I/O (MIO) clock, SD clock
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
@@ -56,6 +55,7 @@ Required properties:
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
+ "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
@@ -82,11 +82,9 @@ Provided clocks:
8: USB2 ch0 host
9: USB2 ch1 host
10: USB2 ch2 host
-11: USB2 ch3 host
12: USB2 ch0 PHY
13: USB2 ch1 PHY
14: USB2 ch2 PHY
-15: USB2 ch3 PHY
Peripheral clock
@@ -94,7 +92,6 @@ Peripheral clock
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
@@ -102,6 +99,7 @@ Required properties:
"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
+ "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
diff --git a/dts/Bindings/clock/zx296702-clk.txt b/dts/Bindings/clock/zx296702-clk.txt
index 750442b655..e85ecb510d 100644
--- a/dts/Bindings/clock/zx296702-clk.txt
+++ b/dts/Bindings/clock/zx296702-clk.txt
@@ -31,5 +31,4 @@ uart0: serial@0x09405000 {
reg = <0x09405000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lsp1clk ZX296702_UART0_PCLK>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/zx296718-clk.txt b/dts/Bindings/clock/zx296718-clk.txt
index 4ad7038084..3a46bf0b25 100644
--- a/dts/Bindings/clock/zx296718-clk.txt
+++ b/dts/Bindings/clock/zx296718-clk.txt
@@ -34,5 +34,4 @@ usbphy0:usb-phy0 {
#phy-cells = <0>;
clocks = <&topclk USB20_PHY_CLK>;
clock-names = "phyclk";
- status = "okay";
};
diff --git a/dts/Bindings/cpufreq/cpufreq-mediatek.txt b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
new file mode 100644
index 0000000000..f6403089ed
--- /dev/null
+++ b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
@@ -0,0 +1,247 @@
+Binding for MediaTek's CPUFreq driver
+=====================================
+
+Required properties:
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
+- clock-names: Should contain the following:
+ "cpu" - The multiplexer for clock input of CPU cluster.
+ "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
+ source (usually MAINPLL) when the original CPU PLL is under
+ transition and not stable yet.
+ Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
+ generic clock consumer properties.
+- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
+ for detail.
+- proc-supply: Regulator for Vproc of CPU cluster.
+
+Optional properties:
+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
+ needs to do "voltage tracking" to step by step scale up/down Vproc and
+ Vsram to fit SoC specific needs. When absent, the voltage scaling
+ flow is handled by hardware, hence no software "voltage tracking" is
+ needed.
+- #cooling-cells:
+- cooling-min-level:
+- cooling-max-level:
+ Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
+ for detail.
+
+Example 1 (MT7623 SoC):
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-598000000 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-747500000 {
+ opp-hz = /bits/ 64 <747500000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-1040000000 {
+ opp-hz = /bits/ 64 <1040000000>;
+ opp-microvolt = <1150000>;
+ };
+
+ opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1200000>;
+ };
+
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1300000>;
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+Example 2 (MT8173 SoC):
+ cpu_opp_table_a: opp_table_a {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-507000000 {
+ opp-hz = /bits/ 64 <507000000>;
+ opp-microvolt = <859000>;
+ };
+
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <908000>;
+ };
+
+ opp-1001000000 {
+ opp-hz = /bits/ 64 <1001000000>;
+ opp-microvolt = <983000>;
+ };
+
+ opp-1105000000 {
+ opp-hz = /bits/ 64 <1105000000>;
+ opp-microvolt = <1009000>;
+ };
+
+ opp-1183000000 {
+ opp-hz = /bits/ 64 <1183000000>;
+ opp-microvolt = <1028000>;
+ };
+
+ opp-1404000000 {
+ opp-hz = /bits/ 64 <1404000000>;
+ opp-microvolt = <1083000>;
+ };
+
+ opp-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <1109000>;
+ };
+
+ opp-1573000000 {
+ opp-hz = /bits/ 64 <1573000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cpu_opp_table_b: opp_table_b {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-507000000 {
+ opp-hz = /bits/ 64 <507000000>;
+ opp-microvolt = <828000>;
+ };
+
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <867000>;
+ };
+
+ opp-1001000000 {
+ opp-hz = /bits/ 64 <1001000000>;
+ opp-microvolt = <927000>;
+ };
+
+ opp-1209000000 {
+ opp-hz = /bits/ 64 <1209000000>;
+ opp-microvolt = <968000>;
+ };
+
+ opp-1404000000 {
+ opp-hz = /bits/ 64 <1007000000>;
+ opp-microvolt = <1028000>;
+ };
+
+ opp-1612000000 {
+ opp-hz = /bits/ 64 <1612000000>;
+ opp-microvolt = <1049000>;
+ };
+
+ opp-1807000000 {
+ opp-hz = /bits/ 64 <1807000000>;
+ opp-microvolt = <1089000>;
+ };
+
+ opp-1989000000 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_a>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_a>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_b>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_b>;
+ };
+
+ &cpu0 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu1 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu2 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
+
+ &cpu3 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
diff --git a/dts/Bindings/crypto/artpec6-crypto.txt b/dts/Bindings/crypto/artpec6-crypto.txt
new file mode 100644
index 0000000000..d9cca4875b
--- /dev/null
+++ b/dts/Bindings/crypto/artpec6-crypto.txt
@@ -0,0 +1,16 @@
+Axis crypto engine with PDMA interface.
+
+Required properties:
+- compatible : Should be one of the following strings:
+ "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
+ "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
+- reg: Base address and size for the PDMA register area.
+- interrupts: Interrupt handle for the PDMA interrupt line.
+
+Example:
+
+crypto@f4264000 {
+ compatible = "axis,artpec6-crypto";
+ reg = <0xf4264000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/dts/Bindings/crypto/atmel-crypto.txt b/dts/Bindings/crypto/atmel-crypto.txt
index f2aab3dc2b..7de1a9674c 100644
--- a/dts/Bindings/crypto/atmel-crypto.txt
+++ b/dts/Bindings/crypto/atmel-crypto.txt
@@ -66,3 +66,16 @@ sha@f8034000 {
dmas = <&dma1 2 17>;
dma-names = "tx";
};
+
+* Eliptic Curve Cryptography (I2C)
+
+Required properties:
+- compatible : must be "atmel,atecc508a".
+- reg: I2C bus address of the device.
+- clock-frequency: must be present in the i2c controller node.
+
+Example:
+atecc508a@C0 {
+ compatible = "atmel,atecc508a";
+ reg = <0xC0>;
+};
diff --git a/dts/Bindings/crypto/fsl-dcp.txt b/dts/Bindings/crypto/fsl-dcp.txt
index 6949e50f1f..76a0b4e80e 100644
--- a/dts/Bindings/crypto/fsl-dcp.txt
+++ b/dts/Bindings/crypto/fsl-dcp.txt
@@ -13,5 +13,4 @@ dcp@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <52 53>;
- status = "okay";
};
diff --git a/dts/Bindings/crypto/inside-secure-safexcel.txt b/dts/Bindings/crypto/inside-secure-safexcel.txt
index 941bb6a6fb..fbc07d1232 100644
--- a/dts/Bindings/crypto/inside-secure-safexcel.txt
+++ b/dts/Bindings/crypto/inside-secure-safexcel.txt
@@ -23,5 +23,4 @@ Example:
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
"eip";
clocks = <&cpm_syscon0 1 26>;
- status = "disabled";
};
diff --git a/dts/Bindings/crypto/marvell-cesa.txt b/dts/Bindings/crypto/marvell-cesa.txt
index c6c6a4a045..28d3f2496b 100644
--- a/dts/Bindings/crypto/marvell-cesa.txt
+++ b/dts/Bindings/crypto/marvell-cesa.txt
@@ -41,5 +41,4 @@ Examples:
clock-names = "cesa0", "cesa1";
marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>;
marvell,crypto-sram-size = <0x600>;
- status = "okay";
};
diff --git a/dts/Bindings/crypto/mv_cesa.txt b/dts/Bindings/crypto/mv_cesa.txt
index c0c35f0033..d9b92e2f31 100644
--- a/dts/Bindings/crypto/mv_cesa.txt
+++ b/dts/Bindings/crypto/mv_cesa.txt
@@ -29,5 +29,4 @@ Examples:
interrupts = <22>;
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x600>;
- status = "okay";
};
diff --git a/dts/Bindings/crypto/rockchip-crypto.txt b/dts/Bindings/crypto/rockchip-crypto.txt
index 096df34b11..5e2ba385b8 100644
--- a/dts/Bindings/crypto/rockchip-crypto.txt
+++ b/dts/Bindings/crypto/rockchip-crypto.txt
@@ -25,5 +25,4 @@ Examples:
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
resets = <&cru SRST_CRYPTO>;
reset-names = "crypto-rst";
- status = "okay";
};
diff --git a/dts/Bindings/crypto/st,stm32-hash.txt b/dts/Bindings/crypto/st,stm32-hash.txt
new file mode 100644
index 0000000000..04fc246f02
--- /dev/null
+++ b/dts/Bindings/crypto/st,stm32-hash.txt
@@ -0,0 +1,30 @@
+* STMicroelectronics STM32 HASH
+
+Required properties:
+- compatible: Should contain entries for this and backward compatible
+ HASH versions:
+ - "st,stm32f456-hash" for stm32 F456.
+ - "st,stm32f756-hash" for stm32 F756.
+- reg: The address and length of the peripheral registers space
+- interrupts: the interrupt specifier for the HASH
+- clocks: The input clock of the HASH instance
+
+Optional properties:
+- resets: The input reset of the HASH instance
+- dmas: DMA specifiers for the HASH. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request name. Should be "in" if a dma is present.
+- dma-maxburst: Set number of maximum dma burst supported
+
+Example:
+
+hash1: hash@50060400 {
+ compatible = "st,stm32f756-hash";
+ reg = <0x50060400 0x400>;
+ interrupts = <80>;
+ clocks = <&rcc 0 STM32F7_AHB2_CLOCK(HASH)>;
+ resets = <&rcc STM32F7_AHB2_RESET(HASH)>;
+ dmas = <&dma2 7 2 0x400 0x0>;
+ dma-names = "in";
+ dma-maxburst = <0>;
+};
diff --git a/dts/Bindings/devfreq/event/rockchip-dfi.txt b/dts/Bindings/devfreq/event/rockchip-dfi.txt
index f2233138eb..001dd63979 100644
--- a/dts/Bindings/devfreq/event/rockchip-dfi.txt
+++ b/dts/Bindings/devfreq/event/rockchip-dfi.txt
@@ -15,5 +15,4 @@ Example:
rockchip,pmu = <&pmugrf>;
clocks = <&cru PCLK_DDR_MON>;
clock-names = "pclk_ddr_mon";
- status = "disabled";
};
diff --git a/dts/Bindings/devfreq/rk3399_dmc.txt b/dts/Bindings/devfreq/rk3399_dmc.txt
index 7a9e8603c1..d6d2833482 100644
--- a/dts/Bindings/devfreq/rk3399_dmc.txt
+++ b/dts/Bindings/devfreq/rk3399_dmc.txt
@@ -205,5 +205,4 @@ Example:
rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
- status = "disabled";
};
diff --git a/dts/Bindings/display/atmel,lcdc.txt b/dts/Bindings/display/atmel,lcdc.txt
index ecb8da063d..1a21202778 100644
--- a/dts/Bindings/display/atmel,lcdc.txt
+++ b/dts/Bindings/display/atmel,lcdc.txt
@@ -34,7 +34,6 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
display = <&display0>;
- status = "okay";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/Bindings/display/atmel/hlcdc-dc.txt b/dts/Bindings/display/atmel/hlcdc-dc.txt
index ec94468b35..82f2acb3d3 100644
--- a/dts/Bindings/display/atmel/hlcdc-dc.txt
+++ b/dts/Bindings/display/atmel/hlcdc-dc.txt
@@ -23,7 +23,6 @@ Example:
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
- status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
diff --git a/dts/Bindings/display/bridge/dw_mipi_dsi.txt b/dts/Bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 0000000000..b13adf30b8
--- /dev/null
+++ b/dts/Bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,32 @@
+Synopsys DesignWare MIPI DSI host controller
+============================================
+
+This document defines device tree properties for the Synopsys DesignWare MIPI
+DSI host controller. It doesn't constitue a device tree binding specification
+by itself but is meant to be referenced by platform-specific device tree
+bindings.
+
+When referenced from platform device tree bindings the properties defined in
+this document are defined as follows. The platform device tree bindings are
+responsible for defining whether each optional property is used or not.
+
+- reg: Memory mapped base address and length of the DesignWare MIPI DSI
+ host controller registers. (mandatory)
+
+- clocks: References to all the clocks specified in the clock-names property
+ as specified in [1]. (mandatory)
+
+- clock-names:
+ - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
+ - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
+
+- resets: References to all the resets specified in the reset-names property
+ as specified in [2]. (optional)
+
+- reset-names: string reset name, must be "apb" if used. (optional)
+
+- panel or bridge node: see [3]. (mandatory)
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
diff --git a/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt b/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
index 7baa658251..aacc8b9296 100644
--- a/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
+++ b/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
@@ -33,7 +33,6 @@ stdp2690-ge-b850v3-fw required properties:
Example:
&mux2_i2c2 {
- status = "okay";
clock-frequency = <100000>;
stdp4028@73 {
diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
index 81b68580e1..b1a8929c25 100644
--- a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
+++ b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
@@ -13,6 +13,7 @@ Required properties:
- compatible : Shall contain one or more of
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
+ - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
When compatible with generic versions, nodes must list the SoC-specific
@@ -43,7 +44,6 @@ Example:
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
clock-names = "iahb", "isfr";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/dts/Bindings/display/exynos/exynos5433-decon.txt b/dts/Bindings/display/exynos/exynos5433-decon.txt
index 549c538b38..fc2588292a 100644
--- a/dts/Bindings/display/exynos/exynos5433-decon.txt
+++ b/dts/Bindings/display/exynos/exynos5433-decon.txt
@@ -25,12 +25,6 @@ Required properties:
size-cells must 1 and 0, respectively.
- port: contains an endpoint node which is connected to the endpoint in the mic
node. The reg value muset be 0.
-- i80-if-timings: specify whether the panel which is connected to decon uses
- i80 lcd interface or mipi video interface. This node contains
- no timing information as that of fimd does. Because there is
- no register in decon to specify i80 interface timing value,
- it is not needed, but make it remain to use same kind of node
- in fimd and exynos7 decon.
Example:
SoC specific DT entry:
@@ -59,9 +53,3 @@ decon: decon@13800000 {
};
};
};
-
-Board specific DT entry:
-&decon {
- i80-if-timings {
- };
-};
diff --git a/dts/Bindings/display/fsl,tcon.txt b/dts/Bindings/display/fsl,tcon.txt
index 6fa4ab668d..4750087478 100644
--- a/dts/Bindings/display/fsl,tcon.txt
+++ b/dts/Bindings/display/fsl,tcon.txt
@@ -14,5 +14,4 @@ timing-controller@4003d000 {
reg = <0x4003d000 0x1000>;
clocks = <&clks VF610_CLK_TCON0>;
clock-names = "ipg";
- status = "okay";
};
diff --git a/dts/Bindings/display/imx/fsl-imx-drm.txt b/dts/Bindings/display/imx/fsl-imx-drm.txt
index fa01db7eb6..f79854783c 100644
--- a/dts/Bindings/display/imx/fsl-imx-drm.txt
+++ b/dts/Bindings/display/imx/fsl-imx-drm.txt
@@ -116,7 +116,7 @@ Parallel display support
Required properties:
- compatible: Should be "fsl,imx-parallel-display"
Optional properties:
-- interface_pix_fmt: How this display is connected to the
+- interface-pix-fmt: How this display is connected to the
display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
and "lvds666".
- edid: verbatim EDID data block describing attached display.
diff --git a/dts/Bindings/display/marvell,pxa2xx-lcdc.txt b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
index 309c47f25b..f79641bd5f 100644
--- a/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
+++ b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
@@ -23,7 +23,6 @@ Example:
reg = <0x44000000 0x10000>;
interrupts = <17>;
clocks = <&clks CLK_LCD>;
- status = "okay";
port {
lcdc_out: endpoint {
diff --git a/dts/Bindings/display/panel/innolux,p079zca.txt b/dts/Bindings/display/panel/innolux,p079zca.txt
index 5c70a8380e..d0f5516157 100644
--- a/dts/Bindings/display/panel/innolux,p079zca.txt
+++ b/dts/Bindings/display/panel/innolux,p079zca.txt
@@ -18,6 +18,5 @@ Example:
power-supply = <...>;
backlight = <&backlight>;
enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- status = "okay";
};
};
diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt
index c6cb96a4fa..4bbd1e9bf3 100644
--- a/dts/Bindings/display/renesas,du.txt
+++ b/dts/Bindings/display/renesas,du.txt
@@ -36,8 +36,10 @@ Required Properties:
When supplied they must be named "dclkin.x" with "x" being the input
clock numerical index.
- - vsps: A list of phandles to the VSP nodes that handle the memory
- interfaces for the DU channels.
+ - vsps: A list of phandle and channel index tuples to the VSPs that handle
+ the memory interfaces for the DU channels. The phandle identifies the VSP
+ instance that serves the DU channel, and the channel index identifies the
+ LIF instance in that VSP.
Required nodes:
@@ -59,24 +61,24 @@ corresponding to each DU output.
R8A7796 (M3-W) DPAD HDMI LVDS -
-Example: R8A7790 (R-Car H2) DU
+Example: R8A7795 (R-Car H3) ES2.0 DU
- du: du@feb00000 {
- compatible = "renesas,du-r8a7790";
- reg = <0 0xfeb00000 0 0x70000>,
- <0 0xfeb90000 0 0x1c>,
- <0 0xfeb94000 0 0x1c>;
- reg-names = "du", "lvds.0", "lvds.1";
- interrupt-parent = <&gic>;
- interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
- <0 268 IRQ_TYPE_LEVEL_HIGH>,
- <0 269 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp7_clks R8A7790_CLK_DU0>,
- <&mstp7_clks R8A7790_CLK_DU1>,
- <&mstp7_clks R8A7790_CLK_DU2>,
- <&mstp7_clks R8A7790_CLK_LVDS0>,
- <&mstp7_clks R8A7790_CLK_LVDS1>;
- clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7795";
+ reg = <0 0xfeb00000 0 0x80000>,
+ <0 0xfeb90000 0 0x14>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 727>;
+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+ vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
ports {
#address-cells = <1>;
@@ -89,12 +91,19 @@ Example: R8A7790 (R-Car H2) DU
};
port@1 {
reg = <1>;
- du_out_lvds0: endpoint {
+ du_out_hdmi0: endpoint {
+ remote-endpoint = <&dw_hdmi0_in>;
};
};
port@2 {
reg = <2>;
- du_out_lvds1: endpoint {
+ du_out_hdmi1: endpoint {
+ remote-endpoint = <&dw_hdmi1_in>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ du_out_lvds0: endpoint {
};
};
};
diff --git a/dts/Bindings/display/repaper.txt b/dts/Bindings/display/repaper.txt
new file mode 100644
index 0000000000..f5f9f9cf6a
--- /dev/null
+++ b/dts/Bindings/display/repaper.txt
@@ -0,0 +1,52 @@
+Pervasive Displays RePaper branded e-ink displays
+
+Required properties:
+- compatible: "pervasive,e1144cs021" for 1.44" display
+ "pervasive,e1190cs021" for 1.9" display
+ "pervasive,e2200cs021" for 2.0" display
+ "pervasive,e2271cs021" for 2.7" display
+
+- panel-on-gpios: Timing controller power control
+- discharge-gpios: Discharge control
+- reset-gpios: RESET pin
+- busy-gpios: BUSY pin
+
+Required property for e2271cs021:
+- border-gpios: Border control
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional property:
+- pervasive,thermal-zone: name of thermometer's thermal zone
+
+Example:
+
+ display_temp: lm75@48 {
+ compatible = "lm75b";
+ reg = <0x48>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ display {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&display_temp>;
+ };
+ };
+
+ papirus27@0{
+ compatible = "pervasive,e2271cs021";
+ reg = <0>;
+
+ spi-max-frequency = <8000000>;
+
+ panel-on-gpios = <&gpio 23 0>;
+ border-gpios = <&gpio 14 0>;
+ discharge-gpios = <&gpio 15 0>;
+ reset-gpios = <&gpio 24 0>;
+ busy-gpios = <&gpio 25 0>;
+
+ pervasive,thermal-zone = "display";
+ };
diff --git a/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt b/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt
index 47665a1278..43561584c1 100644
--- a/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -59,7 +59,6 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt b/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
index 046076c6b2..adc94fc3c9 100644
--- a/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ b/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
@@ -11,7 +11,9 @@ following device-specific properties.
Required properties:
-- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
+- compatible: should be one of the following:
+ "rockchip,rk3288-dw-hdmi"
+ "rockchip,rk3399-dw-hdmi"
- reg: See dw_hdmi.txt.
- reg-io-width: See dw_hdmi.txt. Shall be 4.
- interrupts: HDMI interrupt number
@@ -30,7 +32,8 @@ Optional properties
I2C master controller.
- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
- clock-names: May contain "cec" as defined in dw_hdmi.txt.
-
+- clock-names: May contain "grf", power for grf io.
+- clock-names: May contain "vpll", external clock for some hdmi phy.
Example:
@@ -43,7 +46,6 @@ hdmi: hdmi@ff980000 {
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
clock-names = "iahb", "isfr";
- status = "disabled";
ports {
hdmi_in: port {
#address-cells = <1>;
diff --git a/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 543b07435f..6bb59ab39f 100644
--- a/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -36,7 +36,6 @@ Example:
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
rockchip,grf = <&grf>;
- status = "okay";
ports {
#address-cells = <1>;
@@ -65,6 +64,5 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
- status = "okay";
};
};
diff --git a/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt b/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt
index 8096a29f97..cec21714f0 100644
--- a/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt
+++ b/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt
@@ -25,7 +25,6 @@ hdmi: hdmi@20034000 {
clock-names = "pclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
- status = "disabled";
hdmi_in: port {
#address-cells = <1>;
diff --git a/dts/Bindings/display/rockchip/rockchip-vop.txt b/dts/Bindings/display/rockchip/rockchip-vop.txt
index 9eb3f0a2a0..5d835d9c1b 100644
--- a/dts/Bindings/display/rockchip/rockchip-vop.txt
+++ b/dts/Bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
- compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+ "rockchip,rk3368-vop";
+ "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+ "rockchip,rk3228-vop";
+ "rockchip,rk3328-vop";
- interrupts: should contain a list of all VOP IP block interrupts in the
order: VSYNC, LCD_SYSTEM. The interrupt specifier
diff --git a/dts/Bindings/display/simple-framebuffer-sunxi.txt b/dts/Bindings/display/simple-framebuffer-sunxi.txt
index c46ba641a1..a9168ae694 100644
--- a/dts/Bindings/display/simple-framebuffer-sunxi.txt
+++ b/dts/Bindings/display/simple-framebuffer-sunxi.txt
@@ -28,6 +28,5 @@ chosen {
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
<&ahb_gates 44>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/display/sitronix,st7586.txt b/dts/Bindings/display/sitronix,st7586.txt
new file mode 100644
index 0000000000..1d0dad1210
--- /dev/null
+++ b/dts/Bindings/display/sitronix,st7586.txt
@@ -0,0 +1,22 @@
+Sitronix ST7586 display panel
+
+Required properties:
+- compatible: "lego,ev3-lcd".
+- a0-gpios: The A0 signal (since this binding is for serial mode, this is
+ the pin labeled D1 on the controller, not the pin labeled A0)
+- reset-gpios: Reset pin
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
+
+Example:
+ display@0{
+ compatible = "lego,ev3-lcd";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/Bindings/display/st,stm32-ltdc.txt b/dts/Bindings/display/st,stm32-ltdc.txt
index 8e1476941c..74b5ac7b26 100644
--- a/dts/Bindings/display/st,stm32-ltdc.txt
+++ b/dts/Bindings/display/st,stm32-ltdc.txt
@@ -1,7 +1,6 @@
* STMicroelectronics STM32 lcd-tft display controller
- ltdc: lcd-tft display controller host
- must be a sub-node of st-display-subsystem
Required properties:
- compatible: "st,stm32-ltdc"
- reg: Physical base address of the IP registers and length of memory mapped region.
@@ -13,8 +12,40 @@
Required nodes:
- Video port for RGB output.
-Example:
+* STMicroelectronics STM32 DSI controller specific extensions to Synopsys
+ DesignWare MIPI DSI host controller
+The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI
+DSI host controller. For all mandatory properties & nodes, please refer
+to the related documentation in [5].
+
+Mandatory properties specific to STM32 DSI:
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "st,stm32-dsi".
+- clock-names:
+ - phy pll reference clock string name, must be "ref".
+- resets: see [5].
+- reset-names: see [5].
+
+Mandatory nodes specific to STM32 DSI:
+- ports: A node containing DSI input & output port nodes with endpoint
+ definitions as documented in [3] & [4].
+ - port@0: DSI input port node, connected to the ltdc rgb output port.
+ - port@1: DSI output port node, connected to a panel or a bridge input port.
+- panel or bridge node: A node containing the panel or bridge description as
+ documented in [6].
+ - port: panel or bridge port node, connected to the DSI output port (port@1).
+
+Note: You can find more documentation in the following references
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/graph.txt
+[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+Example 1: RGB panel
/ {
...
soc {
@@ -34,3 +65,73 @@ Example:
};
};
};
+
+Example 2: DSI panel
+
+/ {
+ ...
+ soc {
+ ...
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+
+ port {
+ ltdc_out_dsi: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
+
+
+ dsi: dsi@40016c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-dsi";
+ reg = <0x40016c00 0x800>;
+ clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
+ clock-names = "ref", "pclk";
+ resets = <&rcc STM32F4_APB2_RESET(DSI)>;
+ reset-names = "apb";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_in_panel>;
+ };
+ };
+
+ };
+
+ panel-dsi@0 {
+ reg = <0>; /* dsi virtual channel (0..3) */
+ compatible = ...;
+ enable-gpios = ...;
+
+ port {
+ dsi_in_panel: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ };
+
+ };
+
+ };
+};
diff --git a/dts/Bindings/display/sunxi/sun4i-drm.txt b/dts/Bindings/display/sunxi/sun4i-drm.txt
index b83e601804..92441086ca 100644
--- a/dts/Bindings/display/sunxi/sun4i-drm.txt
+++ b/dts/Bindings/display/sunxi/sun4i-drm.txt
@@ -4,15 +4,33 @@ Allwinner A10 Display Pipeline
The Allwinner A10 Display pipeline is composed of several components
that are going to be documented below:
-For the input port of all components up to the TCON in the display
-pipeline, if there are multiple components, the local endpoint IDs
-must correspond to the index of the upstream block. For example, if
-the remote endpoint is Frontend 1, then the local endpoint ID must
-be 1.
-
-Conversely, for the output ports of the same group, the remote endpoint
-ID must be the index of the local hardware block. If the local backend
-is backend 1, then the remote endpoint ID must be 1.
+For all connections between components up to the TCONs in the display
+pipeline, when there are multiple components of the same type at the
+same depth, the local endpoint ID must be the same as the remote
+component's index. For example, if the remote endpoint is Frontend 1,
+then the local endpoint ID must be 1.
+
+ Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
+ [1] -- -- [1] [1] -- -- [1]
+ \ / \ /
+ X X
+ / \ / \
+ [0] -- -- [0] [0] -- -- [0]
+ Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
+
+For a two pipeline system such as the one depicted above, the lines
+represent the connections between the components, while the numbers
+within the square brackets corresponds to the ID of the local endpoint.
+
+The same rule also applies to DE 2.0 mixer-TCON connections:
+
+ Mixer 0 [0] ----------- [0] TCON 0
+ [1] ---- ---- [1]
+ \ /
+ X
+ / \
+ [0] ---- ---- [0]
+ Mixer 1 [1] ----------- [1] TCON 1
HDMI Encoder
------------
@@ -260,7 +278,6 @@ hdmi: hdmi@01c16000 {
<&dma SUN4I_DMA_NORMAL 16>,
<&dma SUN4I_DMA_DEDICATED 24>;
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/dts/Bindings/dma/fsl-edma.txt b/dts/Bindings/dma/fsl-edma.txt
index 191d7bd8a6..97e213e076 100644
--- a/dts/Bindings/dma/fsl-edma.txt
+++ b/dts/Bindings/dma/fsl-edma.txt
@@ -72,5 +72,4 @@ sai2: sai@40031000 {
dma-names = "tx", "rx";
dmas = <&edma0 0 21>,
<&edma0 0 20>;
- status = "disabled";
};
diff --git a/dts/Bindings/dma/mv-xor.txt b/dts/Bindings/dma/mv-xor.txt
index c075f59881..0ffb4d8766 100644
--- a/dts/Bindings/dma/mv-xor.txt
+++ b/dts/Bindings/dma/mv-xor.txt
@@ -30,7 +30,6 @@ xor@d0060900 {
reg = <0xd0060900 0x100
0xd0060b00 0x100>;
clocks = <&coreclk 0>;
- status = "okay";
xor00 {
interrupts = <51>;
diff --git a/dts/Bindings/dma/qcom_adm.txt b/dts/Bindings/dma/qcom_adm.txt
index 9bcab91159..9d3b2f917b 100644
--- a/dts/Bindings/dma/qcom_adm.txt
+++ b/dts/Bindings/dma/qcom_adm.txt
@@ -48,7 +48,6 @@ Each dmas request consists of 3 cells:
Example:
spi4: spi@1a280000 {
- status = "ok";
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
diff --git a/dts/Bindings/dma/renesas,rcar-dmac.txt b/dts/Bindings/dma/renesas,rcar-dmac.txt
index 79a204d502..891db41e94 100644
--- a/dts/Bindings/dma/renesas,rcar-dmac.txt
+++ b/dts/Bindings/dma/renesas,rcar-dmac.txt
@@ -25,6 +25,7 @@ Required Properties:
- "renesas,dmac-r8a7794" (R-Car E2)
- "renesas,dmac-r8a7795" (R-Car H3)
- "renesas,dmac-r8a7796" (R-Car M3-W)
+ - "renesas,dmac-r8a77970" (R-Car V3M)
- reg: base address and length of the registers block for the DMAC
diff --git a/dts/Bindings/dma/renesas,usb-dmac.txt b/dts/Bindings/dma/renesas,usb-dmac.txt
index e7780a186a..1be6941ac1 100644
--- a/dts/Bindings/dma/renesas,usb-dmac.txt
+++ b/dts/Bindings/dma/renesas,usb-dmac.txt
@@ -8,6 +8,7 @@ Required Properties:
- "renesas,r8a7793-usb-dmac" (R-Car M2-N)
- "renesas,r8a7794-usb-dmac" (R-Car E2)
- "renesas,r8a7795-usb-dmac" (R-Car H3)
+ - "renesas,r8a7796-usb-dmac" (R-Car M3-W)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
diff --git a/dts/Bindings/dma/snps-dma.txt b/dts/Bindings/dma/snps-dma.txt
index 4775c66f45..a122723907 100644
--- a/dts/Bindings/dma/snps-dma.txt
+++ b/dts/Bindings/dma/snps-dma.txt
@@ -63,7 +63,6 @@ Example:
compatible = "arm,pl011", "arm,primecell";
reg = <0xe0000000 0x1000>;
interrupts = <0 35 0x4>;
- status = "disabled";
dmas = <&dmahost 12 0 1>,
<&dmahost 13 0 1 0>;
dma-names = "rx", "rx";
diff --git a/dts/Bindings/dma/st_fdma.txt b/dts/Bindings/dma/st_fdma.txt
index 495d853c56..52cfec9e77 100644
--- a/dts/Bindings/dma/st_fdma.txt
+++ b/dts/Bindings/dma/st_fdma.txt
@@ -69,7 +69,6 @@ Example:
sti_uni_player2: sti-uni-player@2 {
compatible = "st,sti-uni-player";
- status = "disabled";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
diff --git a/dts/Bindings/dma/ste-dma40.txt b/dts/Bindings/dma/ste-dma40.txt
index 95800ab37b..aa7dbd565a 100644
--- a/dts/Bindings/dma/ste-dma40.txt
+++ b/dts/Bindings/dma/ste-dma40.txt
@@ -135,5 +135,4 @@ Example:
<&dma 13 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "rx";
- status = "disabled";
};
diff --git a/dts/Bindings/dma/sun4i-dma.txt b/dts/Bindings/dma/sun4i-dma.txt
index f1634a27a8..3b484380c5 100644
--- a/dts/Bindings/dma/sun4i-dma.txt
+++ b/dts/Bindings/dma/sun4i-dma.txt
@@ -40,7 +40,6 @@ Example:
clock-names = "ahb", "mod";
dmas = <&dma 1 29>, <&dma 1 28>;
dma-names = "rx", "tx";
- status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
diff --git a/dts/Bindings/dma/sun6i-dma.txt b/dts/Bindings/dma/sun6i-dma.txt
index 6b267045f5..98fbe1a5c6 100644
--- a/dts/Bindings/dma/sun6i-dma.txt
+++ b/dts/Bindings/dma/sun6i-dma.txt
@@ -9,6 +9,7 @@ Required properties:
"allwinner,sun8i-a23-dma"
"allwinner,sun8i-a83t-dma"
"allwinner,sun8i-h3-dma"
+ "allwinner,sun8i-v3s-dma"
- reg: Should contain the registers base address and length
- interrupts: Should contain a reference to the interrupt used by this device
- clocks: Should contain a reference to the parent AHB clock
diff --git a/dts/Bindings/dma/ti-dma-crossbar.txt b/dts/Bindings/dma/ti-dma-crossbar.txt
index aead5869a2..b849a1ed38 100644
--- a/dts/Bindings/dma/ti-dma-crossbar.txt
+++ b/dts/Bindings/dma/ti-dma-crossbar.txt
@@ -62,7 +62,6 @@ uart1: serial@4806a000 {
interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
- status = "disabled";
/* Requesting crossbar input 49 and 50 */
dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
dma-names = "tx", "rx";
diff --git a/dts/Bindings/dma/ti-edma.txt b/dts/Bindings/dma/ti-edma.txt
index 18090e7226..41f0c1a07c 100644
--- a/dts/Bindings/dma/ti-edma.txt
+++ b/dts/Bindings/dma/ti-edma.txt
@@ -9,7 +9,12 @@ execute the actual DMA tansfer.
eDMA3 Channel Controller
Required properties:
-- compatible: "ti,edma3-tpcc" for the channel controller(s)
+--------------------
+- compatible: Should be:
+ - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
+ AM33xx and AM43xx SoCs.
+ - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
+ channel controller(s) on 66AK2G.
- #dma-cells: Should be set to <2>. The first number is the DMA request
number and the second is the TC the channel is serviced on.
- reg: Memory map of eDMA CC
@@ -19,8 +24,19 @@ Required properties:
- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
<&tptc_phandle TC_priority_number>. The highest priority is 0.
+SoC-specific Required properties:
+--------------------------------
+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Name of the hwmods associated to the eDMA CC.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+ and an args specifier containing the device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
Optional properties:
-- ti,hwmods: Name of the hwmods associated to the eDMA CC
+-------------------
- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
these channels will be SW triggered channels. See example.
- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
@@ -31,17 +47,34 @@ Optional properties:
eDMA3 Transfer Controller
Required properties:
-- compatible: "ti,edma3-tptc" for the transfer controller(s)
+--------------------
+- compatible: Should be:
+ - "ti,edma3-tptc" for the transfer controller(s) on OMAP,
+ AM33xx and AM43xx SoCs.
+ - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
+ transfer controller(s) on 66AK2G.
- reg: Memory map of eDMA TC
- interrupts: Interrupt number for TCerrint.
+SoC-specific Required properties:
+--------------------------------
+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Name of the hwmods associated to the eDMA TC.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+ and an args specifier containing the device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
Optional properties:
-- ti,hwmods: Name of the hwmods associated to the given eDMA TC
+-------------------
- interrupt-names: "edma3_tcerrint"
------------------------------------------------------------------------------
-Example:
+Examples:
+1.
edma: edma@49000000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
@@ -102,13 +135,64 @@ mcasp0: mcasp@48038000 {
reg-names = "mpu", "dat";
interrupts = <80>, <81>;
interrupt-names = "tx", "rx";
- status = "disabled";
/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
+2.
+edma1: edma@02728000 {
+ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
+ reg = <0x02728000 0x8000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "edma3_ccint", "emda3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
+
+ /*
+ * memcpy is disabled, can be enabled with:
+ * ti,edma-memcpy-channels = <12 13 14 15>;
+ * for example.
+ */
+
+ power-domains = <&k2g_pds 0x4f>;
+};
+
+edma1_tptc0: tptc@027b0000 {
+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x027b0000 0x400>;
+ power-domains = <&k2g_pds 0x4f>;
+};
+
+edma1_tptc1: tptc@027b8000 {
+ compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x027b8000 0x400>;
+ power-domains = <&k2g_pds 0x4f>;
+};
+
+mmc0: mmc@23000000 {
+ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
+ reg = <0x23000000 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
+ dmas = <&edma1 24 0>, <&edma1 25 0>;
+ dma-names = "tx", "rx";
+ bus-width = <4>;
+ ti,needs-special-reset;
+ no-1-8-v;
+ max-frequency = <96000000>;
+ power-domains = <&k2g_pds 0xb>;
+ clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
+ clock-names = "fck", "mmchsdb_fck";
+ status = "disabled";
+};
+
------------------------------------------------------------------------------
DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
binding.
diff --git a/dts/Bindings/eeprom/eeprom.txt b/dts/Bindings/eeprom/eeprom.txt
index 5696eb508e..afc04589ea 100644
--- a/dts/Bindings/eeprom/eeprom.txt
+++ b/dts/Bindings/eeprom/eeprom.txt
@@ -16,8 +16,12 @@ Required properties:
"renesas,r1ex24002"
+ The following manufacturers values have been deprecated:
+ "at", "at24"
+
If there is no specific driver for <manufacturer>, a generic
- driver based on <type> is selected. Possible types are:
+ device with <type> and manufacturer "atmel" should be used.
+ Possible types are:
"24c00", "24c01", "24c02", "24c04", "24c08", "24c16", "24c32", "24c64",
"24c128", "24c256", "24c512", "24c1024", "spd"
diff --git a/dts/Bindings/extcon/extcon-usbc-cros-ec.txt b/dts/Bindings/extcon/extcon-usbc-cros-ec.txt
new file mode 100644
index 0000000000..8e8625c00d
--- /dev/null
+++ b/dts/Bindings/extcon/extcon-usbc-cros-ec.txt
@@ -0,0 +1,24 @@
+ChromeOS EC USB Type-C cable and accessories detection
+
+On ChromeOS systems with USB Type C ports, the ChromeOS Embedded Controller is
+able to detect the state of external accessories such as display adapters
+or USB devices when said accessories are attached or detached.
+
+The node for this device must be under a cros-ec node like google,cros-ec-spi
+or google,cros-ec-i2c.
+
+Required properties:
+- compatible: Should be "google,extcon-usbc-cros-ec".
+- google,usb-port-id: Specifies the USB port ID to use.
+
+Example:
+ cros-ec@0 {
+ compatible = "google,cros-ec-i2c";
+
+ ...
+
+ extcon {
+ compatible = "google,extcon-usbc-cros-ec";
+ google,usb-port-id = <0>;
+ };
+ }
diff --git a/dts/Bindings/fpga/altera-passive-serial.txt b/dts/Bindings/fpga/altera-passive-serial.txt
new file mode 100644
index 0000000000..48478bc07e
--- /dev/null
+++ b/dts/Bindings/fpga/altera-passive-serial.txt
@@ -0,0 +1,29 @@
+Altera Passive Serial SPI FPGA Manager
+
+Altera FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically SPI, and might require extra
+circuits in order to play nicely with other SPI slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible: Must be one of the following:
+ "altr,fpga-passive-serial",
+ "altr,fpga-arria10-passive-serial"
+- reg: SPI chip select of the FPGA
+- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
+- nstat-gpios: status pin (referred to as nSTATUS in the manual)
+
+Optional properties:
+- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
+
+Example:
+ fpga: fpga@0 {
+ compatible = "altr,fpga-passive-serial";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+ };
diff --git a/dts/Bindings/fpga/xilinx-pr-decoupler.txt b/dts/Bindings/fpga/xilinx-pr-decoupler.txt
new file mode 100644
index 0000000000..8dcfba926b
--- /dev/null
+++ b/dts/Bindings/fpga/xilinx-pr-decoupler.txt
@@ -0,0 +1,36 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge. The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
+ "xlnx,pr-decoupler"
+- regs : base address and size for decoupler module
+- clocks : input clock to IP
+- clock-names : should contain "aclk"
+
+Optional properties:
+- bridge-enable : 0 if driver should disable bridge at startup
+ 1 if driver should enable bridge at startup
+ Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+ fpga-bridge@100000450 {
+ compatible = "xlnx,pr-decoupler-1.00",
+ "xlnx-pr-decoupler";
+ regs = <0x10000045 0x10>;
+ clocks = <&clkc 15>;
+ clock-names = "aclk";
+ bridge-enable = <0>;
+ };
diff --git a/dts/Bindings/fpga/xilinx-slave-serial.txt b/dts/Bindings/fpga/xilinx-slave-serial.txt
index 9766f7472f..cfa4ed42b6 100644
--- a/dts/Bindings/fpga/xilinx-slave-serial.txt
+++ b/dts/Bindings/fpga/xilinx-slave-serial.txt
@@ -31,7 +31,6 @@ Example for full FPGA configuration:
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
- status = "okay";
fpga_mgr_spi: fpga-mgr@0 {
compatible = "xlnx,fpga-slave-serial";
diff --git a/dts/Bindings/gpio/gpio-74x164.txt b/dts/Bindings/gpio/gpio-74x164.txt
index ce1b2231bf..2a97553d8d 100644
--- a/dts/Bindings/gpio/gpio-74x164.txt
+++ b/dts/Bindings/gpio/gpio-74x164.txt
@@ -12,6 +12,9 @@ Required properties:
1 = active low
- registers-number: Number of daisy-chained shift registers
+Optional properties:
+- enable-gpios: GPIO connected to the OE (Output Enable) pin.
+
Example:
gpio5: gpio5@0 {
diff --git a/dts/Bindings/gpio/gpio-aspeed.txt b/dts/Bindings/gpio/gpio-aspeed.txt
index c756afa88c..fc6378c778 100644
--- a/dts/Bindings/gpio/gpio-aspeed.txt
+++ b/dts/Bindings/gpio/gpio-aspeed.txt
@@ -18,7 +18,7 @@ Required properties:
Optional properties:
- interrupt-parent : The parent interrupt controller, optional if inherited
-- clocks : A phandle to the HPLL clock node for debounce timings
+- clocks : A phandle to the clock to use for debounce timings
The gpio and interrupt properties are further described in their respective
bindings documentation:
diff --git a/dts/Bindings/gpio/gpio-davinci.txt b/dts/Bindings/gpio/gpio-davinci.txt
index 5079ba7d65..8beb0539b6 100644
--- a/dts/Bindings/gpio/gpio-davinci.txt
+++ b/dts/Bindings/gpio/gpio-davinci.txt
@@ -1,7 +1,10 @@
Davinci/Keystone GPIO controller bindings
Required Properties:
-- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio"
+- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
+ "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
+ 66AK2E SoCs
+ "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
- reg: Physical base address of the controller and the size of memory mapped
registers.
@@ -20,7 +23,21 @@ Required Properties:
- ti,ngpio: The number of GPIO pins supported.
- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt
- line to processor.
+ line to processor.
+
+- clocks: Should contain the device's input clock, and should be defined as per
+ the appropriate clock bindings consumer usage in,
+
+ Documentation/devicetree/bindings/clock/keystone-gate.txt
+ for 66AK2HK/66AK2L/66AK2E SoCs or,
+
+ Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ for 66AK2G SoCs
+
+- clock-names: Name should be "gpio";
+
+Currently clock-names and clocks are needed for all keystone 2 platforms
+Davinci platforms do not have DT clocks as of now.
The GPIO controller also acts as an interrupt controller. It uses the default
two cells specifier as described in Documentation/devicetree/bindings/
@@ -60,3 +77,73 @@ leds {
...
};
};
+
+Example for 66AK2G:
+
+gpio0: gpio@2603000 {
+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+ reg = <0x02603000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <144>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k2g_clks 0x001b 0x0>;
+ clock-names = "gpio";
+};
+
+Example for 66AK2HK/66AK2L/66AK2E:
+
+gpio0: gpio@260bf00 {
+ compatible = "ti,keystone-gpio";
+ reg = <0x0260bf00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* HW Interrupts mapped to GPIO pins */
+ interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkgpio>;
+ clock-names = "gpio";
+ ti,ngpio = <32>;
+ ti,davinci-gpio-unbanked = <32>;
+};
diff --git a/dts/Bindings/gpio/gpio-mpc8xxx.txt b/dts/Bindings/gpio/gpio-mpc8xxx.txt
index 4b6cc632ca..69d46162d0 100644
--- a/dts/Bindings/gpio/gpio-mpc8xxx.txt
+++ b/dts/Bindings/gpio/gpio-mpc8xxx.txt
@@ -23,7 +23,6 @@ gpio0: gpio@1100 {
#gpio-cells = <2>;
reg = <0x1100 0x080>;
interrupts = <78 0x8>;
- status = "okay";
};
Example of gpio-controller node for a ls2080a SoC:
diff --git a/dts/Bindings/gpio/gpio-vf610.txt b/dts/Bindings/gpio/gpio-vf610.txt
index 436cc99c65..0ccbae4401 100644
--- a/dts/Bindings/gpio/gpio-vf610.txt
+++ b/dts/Bindings/gpio/gpio-vf610.txt
@@ -5,7 +5,9 @@ functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
each, and each PORT module has its own interrupt.
Required properties for GPIO node:
-- compatible : Should be "fsl,<soc>-gpio", currently "fsl,vf610-gpio"
+- compatible : Should be "fsl,<soc>-gpio", below is supported list:
+ "fsl,vf610-gpio"
+ "fsl,imx7ulp-gpio"
- reg : The first reg tuple represents the PORT module, the second tuple
the GPIO module.
- interrupts : Should be the port interrupt shared by all 32 pins.
diff --git a/dts/Bindings/gpio/renesas,gpio-rcar.txt b/dts/Bindings/gpio/renesas,gpio-rcar.txt
index 6826a371fb..51c86f6999 100644
--- a/dts/Bindings/gpio/renesas,gpio-rcar.txt
+++ b/dts/Bindings/gpio/renesas,gpio-rcar.txt
@@ -2,8 +2,9 @@
Required Properties:
- - compatible: should contain one of the following.
+ - compatible: should contain one or more of the following:
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
+ - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
- "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
@@ -13,7 +14,14 @@ Required Properties:
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
- "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
- - "renesas,gpio-rcar": for generic R-Car GPIO controller.
+ - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
+ - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
+ - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller.
+ - "renesas,gpio-rcar": deprecated.
+
+ When compatible with the generic version nodes must list the
+ SoC-specific version corresponding to the platform first followed by
+ the generic version.
- reg: Base address and length of each memory resource used by the GPIO
controller hardware module.
@@ -43,7 +51,7 @@ interrupt-controller/interrupts.txt.
Example: R8A7779 (R-Car H1) GPIO controller nodes
gpio0: gpio@ffc40000 {
- compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+ compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc40000 0x2c>;
interrupt-parent = <&gic>;
interrupts = <0 141 0x4>;
@@ -55,7 +63,7 @@ Example: R8A7779 (R-Car H1) GPIO controller nodes
};
...
gpio6: gpio@ffc46000 {
- compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+ compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc46000 0x2c>;
interrupt-parent = <&gic>;
interrupts = <0 147 0x4>;
diff --git a/dts/Bindings/gpio/spear_spics.txt b/dts/Bindings/gpio/spear_spics.txt
index 96c37eb150..dd04d96e6f 100644
--- a/dts/Bindings/gpio/spear_spics.txt
+++ b/dts/Bindings/gpio/spear_spics.txt
@@ -42,7 +42,6 @@ spics: spics@e0700000{
spi0: spi@e0100000 {
- status = "okay";
num-cs = <3>;
cs-gpios = <&gpio1 7 0>, <&spics 0>,
<&spics 1>;
diff --git a/dts/Bindings/gpu/arm,mali-midgard.txt b/dts/Bindings/gpu/arm,mali-midgard.txt
index 5aa5926029..039219df05 100644
--- a/dts/Bindings/gpu/arm,mali-midgard.txt
+++ b/dts/Bindings/gpu/arm,mali-midgard.txt
@@ -17,6 +17,7 @@ Required properties:
* which must be preceded by one of the following vendor specifics:
+ "amlogic,meson-gxm-mali"
+ "rockchip,rk3288-mali"
+ + "rockchip,rk3399-mali"
- reg : Physical base address of the device and length of the register area.
diff --git a/dts/Bindings/gpu/arm,mali-utgard.txt b/dts/Bindings/gpu/arm,mali-utgard.txt
index 2b6243e730..b4ebd56d03 100644
--- a/dts/Bindings/gpu/arm,mali-utgard.txt
+++ b/dts/Bindings/gpu/arm,mali-utgard.txt
@@ -10,6 +10,7 @@ Required properties:
* And, optionally, one of the vendor specific compatible:
+ allwinner,sun4i-a10-mali
+ allwinner,sun7i-a20-mali
+ + allwinner,sun50i-h5-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali
+ stericsson,db8500-mali
@@ -58,6 +59,10 @@ to specify one more vendor-specific compatible, among:
Required properties:
* resets: phandle to the reset line for the GPU
+ - allwinner,sun50i-h5-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
- stericsson,db8500-mali
Required properties:
* interrupt-names and interrupts:
diff --git a/dts/Bindings/gpu/nvidia,gk20a.txt b/dts/Bindings/gpu/nvidia,gk20a.txt
index b7e4c74445..f32bbba4d3 100644
--- a/dts/Bindings/gpu/nvidia,gk20a.txt
+++ b/dts/Bindings/gpu/nvidia,gk20a.txt
@@ -51,7 +51,6 @@ Example for GK20A:
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
- status = "disabled";
};
Example for GM20B:
@@ -70,7 +69,6 @@ Example for GM20B:
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
- status = "disabled";
};
Example for GP10B:
@@ -89,5 +87,4 @@ Example for GP10B:
reset-names = "gpu";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA186_SID_GPU>;
- status = "disabled";
};
diff --git a/dts/Bindings/gpu/samsung-g2d.txt b/dts/Bindings/gpu/samsung-g2d.txt
index c4f358dafd..1e7959332d 100644
--- a/dts/Bindings/gpu/samsung-g2d.txt
+++ b/dts/Bindings/gpu/samsung-g2d.txt
@@ -24,5 +24,4 @@ Example:
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
- status = "disabled";
};
diff --git a/dts/Bindings/hsi/omap-ssi.txt b/dts/Bindings/hsi/omap-ssi.txt
index f26625e426..b8eca3c781 100644
--- a/dts/Bindings/hsi/omap-ssi.txt
+++ b/dts/Bindings/hsi/omap-ssi.txt
@@ -92,6 +92,5 @@ ssi-controller@48058000 {
interrupts = <69>,
<70>;
- status = "disabled"; /* second port is not used on N900 */
}
}
diff --git a/dts/Bindings/hwmon/aspeed-pwm-tacho.txt b/dts/Bindings/hwmon/aspeed-pwm-tacho.txt
index cf4460564a..367c820321 100644
--- a/dts/Bindings/hwmon/aspeed-pwm-tacho.txt
+++ b/dts/Bindings/hwmon/aspeed-pwm-tacho.txt
@@ -11,6 +11,8 @@ Required properties for pwm-tacho node:
- #size-cells : should be 1.
+- #cooling-cells: should be 2.
+
- reg : address and length of the register set for the device.
- pinctrl-names : a pinctrl state named "default" must be defined.
@@ -28,12 +30,17 @@ fan subnode format:
Under fan subnode there can upto 8 child nodes, with each child node
representing a fan. If there are 8 fans each fan can have one PWM port and
one/two Fan tach inputs.
+For PWM port can be configured cooling-levels to create cooling device.
+Cooling device could be bound to a thermal zone for the thermal control.
Required properties for each child node:
- reg : should specify PWM source port.
integer value in the range 0 to 7 with 0 indicating PWM port A and
7 indicating PWM port H.
+- cooling-levels: PWM duty cycle values in a range from 0 to 255
+ which correspond to thermal cooling states.
+
- aspeed,fan-tach-ch : should specify the Fan tach input channel.
integer value in the range 0 through 15, with 0 indicating
Fan tach channel 0 and 15 indicating Fan tach channel 15.
@@ -50,6 +57,7 @@ pwm_tacho_fixed_clk: fixedclk {
pwm_tacho: pwmtachocontroller@1e786000 {
#address-cells = <1>;
#size-cells = <1>;
+ #cooling-cells = <2>;
reg = <0x1E786000 0x1000>;
compatible = "aspeed,ast2500-pwm-tacho";
clocks = <&pwm_tacho_fixed_clk>;
@@ -58,6 +66,7 @@ pwm_tacho: pwmtachocontroller@1e786000 {
fan@0 {
reg = <0x00>;
+ cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
diff --git a/dts/Bindings/hwmon/ibm,cffps1.txt b/dts/Bindings/hwmon/ibm,cffps1.txt
new file mode 100644
index 0000000000..f68a0a68fc
--- /dev/null
+++ b/dts/Bindings/hwmon/ibm,cffps1.txt
@@ -0,0 +1,21 @@
+Device-tree bindings for IBM Common Form Factor Power Supply Version 1
+----------------------------------------------------------------------
+
+Required properties:
+ - compatible = "ibm,cffps1";
+ - reg = < I2C bus address >; : Address of the power supply on the
+ I2C bus.
+
+Example:
+
+ i2c-bus@100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ < more properties >
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+ };
diff --git a/dts/Bindings/hwmon/ltq-cputemp.txt b/dts/Bindings/hwmon/ltq-cputemp.txt
new file mode 100644
index 0000000000..33fd00a987
--- /dev/null
+++ b/dts/Bindings/hwmon/ltq-cputemp.txt
@@ -0,0 +1,10 @@
+Lantiq cpu temperatur sensor
+
+Requires node properties:
+- compatible value :
+ "lantiq,cputemp"
+
+Example:
+ cputemp@0 {
+ compatible = "lantiq,cputemp";
+ };
diff --git a/dts/Bindings/i2c/i2c-altera.txt b/dts/Bindings/i2c/i2c-altera.txt
new file mode 100644
index 0000000000..767664f448
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-altera.txt
@@ -0,0 +1,39 @@
+* Altera I2C Controller
+* This is Altera's synthesizable logic block I2C Controller for use
+* in Altera's FPGAs.
+
+Required properties :
+ - compatible : should be "altr,softip-i2c-v1.0"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number.
+ - clocks : phandle to input clock.
+ - #address-cells = <1>;
+ - #size-cells = <0>;
+
+Recommended properties :
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+
+Optional properties :
+ - fifo-size : Size of the RX and TX FIFOs in bytes.
+ - Child nodes conforming to i2c bus binding
+
+Example :
+
+ i2c@100080000 {
+ compatible = "altr,softip-i2c-v1.0";
+ reg = <0x00000001 0x00080000 0x00000040>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 43 4>;
+ clocks = <&clk_0>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fifo-size = <4>;
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+ };
+
diff --git a/dts/Bindings/i2c/i2c-cbus-gpio.txt b/dts/Bindings/i2c/i2c-cbus-gpio.txt
index 8ce9cd2855..c143948b2a 100644
--- a/dts/Bindings/i2c/i2c-cbus-gpio.txt
+++ b/dts/Bindings/i2c/i2c-cbus-gpio.txt
@@ -20,8 +20,8 @@ i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
- retu-mfd: retu@1 {
- compatible = "retu-mfd";
+ retu: retu@1 {
+ compatible = "nokia,retu";
reg = <0x1>;
};
};
diff --git a/dts/Bindings/i2c/i2c-demux-pinctrl.txt b/dts/Bindings/i2c/i2c-demux-pinctrl.txt
index 7ce23ac613..81b5d55086 100644
--- a/dts/Bindings/i2c/i2c-demux-pinctrl.txt
+++ b/dts/Bindings/i2c/i2c-demux-pinctrl.txt
@@ -102,7 +102,6 @@ And for clarification, here are the snipplets for the i2c-parents:
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
- status = "disabled";
gpios = <&gpio5 6 GPIO_ACTIVE_HIGH /* sda */
&gpio5 5 GPIO_ACTIVE_HIGH /* scl */
>;
diff --git a/dts/Bindings/i2c/i2c-efm32.txt b/dts/Bindings/i2c/i2c-efm32.txt
index 50b25c3da1..3b30e54ae3 100644
--- a/dts/Bindings/i2c/i2c-efm32.txt
+++ b/dts/Bindings/i2c/i2c-efm32.txt
@@ -22,7 +22,6 @@ Example:
interrupts = <9>;
clocks = <&cmu clk_HFPERCLKI2C0>;
clock-frequency = <100000>;
- status = "ok";
energymicro,location = <3>;
eeprom@50 {
diff --git a/dts/Bindings/i2c/i2c-mtk.txt b/dts/Bindings/i2c/i2c-mtk.txt
index bd5a7befd9..ff7bf37deb 100644
--- a/dts/Bindings/i2c/i2c-mtk.txt
+++ b/dts/Bindings/i2c/i2c-mtk.txt
@@ -1,14 +1,15 @@
-* Mediatek's I2C controller
+* MediaTek's I2C controller
-The Mediatek's I2C controller is used to interface with I2C devices.
+The MediaTek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: value should be either of the following.
- "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for Mediatek mt2701
- "mediatek,mt6577-i2c": for i2c compatible with mt6577.
- "mediatek,mt6589-i2c": for i2c compatible with mt6589.
- "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for i2c compatible with mt7623.
- "mediatek,mt8173-i2c": for i2c compatible with mt8173.
+ "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
+ "mediatek,mt6577-i2c": for MediaTek MT6577
+ "mediatek,mt6589-i2c": for MediaTek MT6589
+ "mediatek,mt7622-i2c": for MediaTek MT7622
+ "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
+ "mediatek,mt8173-i2c": for MediaTek MT8173
- reg: physical base address of the controller and dma base, length of memory
mapped region.
- interrupts: interrupt number to the cpu.
diff --git a/dts/Bindings/i2c/i2c-rcar.txt b/dts/Bindings/i2c/i2c-rcar.txt
index 2b8bd33dbf..cad39aee9f 100644
--- a/dts/Bindings/i2c/i2c-rcar.txt
+++ b/dts/Bindings/i2c/i2c-rcar.txt
@@ -2,6 +2,8 @@ I2C for R-Car platforms
Required properties:
- compatible:
+ "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
+ "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
@@ -12,7 +14,8 @@ Required properties:
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
- "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 compatible device.
+ "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
+ device.
"renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device.
"renesas,i2c-rcar" (deprecated)
diff --git a/dts/Bindings/i2c/i2c-rk3x.txt b/dts/Bindings/i2c/i2c-rk3x.txt
index e18445d098..22f2eeb2c4 100644
--- a/dts/Bindings/i2c/i2c-rk3x.txt
+++ b/dts/Bindings/i2c/i2c-rk3x.txt
@@ -7,6 +7,7 @@ Required properties :
- reg : Offset and length of the register set for the device
- compatible: should be one of the following:
+ - "rockchip,rv1108-i2c": for rv1108
- "rockchip,rk3066-i2c": for rk3066
- "rockchip,rk3188-i2c": for rk3188
- "rockchip,rk3228-i2c": for rk3228
diff --git a/dts/Bindings/i2c/i2c-sh_mobile.txt b/dts/Bindings/i2c/i2c-sh_mobile.txt
index ae9c2a735f..224390999e 100644
--- a/dts/Bindings/i2c/i2c-sh_mobile.txt
+++ b/dts/Bindings/i2c/i2c-sh_mobile.txt
@@ -4,6 +4,8 @@ Required properties:
- compatible :
- "renesas,iic-r8a73a4" (R-Mobile APE6)
- "renesas,iic-r8a7740" (R-Mobile A1)
+ - "renesas,iic-r8a7743" (RZ/G1M)
+ - "renesas,iic-r8a7745" (RZ/G1E)
- "renesas,iic-r8a7790" (R-Car H2)
- "renesas,iic-r8a7791" (R-Car M2-W)
- "renesas,iic-r8a7792" (R-Car V2H)
@@ -12,7 +14,8 @@ Required properties:
- "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-r8a7796" (R-Car M3-W)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)
+ - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
+ compatible device)
- "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
- "renesas,rmobile-iic" (generic device)
diff --git a/dts/Bindings/i2c/i2c-sprd.txt b/dts/Bindings/i2c/i2c-sprd.txt
new file mode 100644
index 0000000000..60b7cda15d
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-sprd.txt
@@ -0,0 +1,31 @@
+I2C for Spreadtrum platforms
+
+Required properties:
+- compatible: Should be "sprd,sc9860-i2c".
+- reg: Specify the physical base address of the controller and length
+ of memory mapped region.
+- interrupts: Should contain I2C interrupt.
+- clock-names: Should contain following entries:
+ "i2c" for I2C clock,
+ "source" for I2C source (parent) clock,
+ "enable" for I2C module enable clock.
+- clocks: Should contain a clock specifier for each entry in clock-names.
+- clock-frequency: Constains desired I2C bus clock frequency in Hz.
+- #address-cells: Should be 1 to describe address cells for I2C device address.
+- #size-cells: Should be 0 means no size cell for I2C device address.
+
+Optional properties:
+- Child nodes conforming to I2C bus binding
+
+Examples:
+i2c0: i2c@70500000 {
+ compatible = "sprd,sc9860-i2c";
+ reg = <0 0x70500000 0 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c", "source", "enable";
+ clocks = <&clk_i2c3>, <&ext_26m>, <&clk_ap_apb_gates 11>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
diff --git a/dts/Bindings/i2c/i2c-stm32.txt b/dts/Bindings/i2c/i2c-stm32.txt
index 78eaf7b718..3b54899666 100644
--- a/dts/Bindings/i2c/i2c-stm32.txt
+++ b/dts/Bindings/i2c/i2c-stm32.txt
@@ -1,7 +1,9 @@
* I2C controller embedded in STMicroelectronics STM32 I2C platform
Required properties :
-- compatible : Must be "st,stm32f4-i2c"
+- compatible : Must be one of the following
+ - "st,stm32f4-i2c"
+ - "st,stm32f7-i2c"
- reg : Offset and length of the register set for the device
- interrupts : Must contain the interrupt id for I2C event and then the
interrupt id for I2C error.
@@ -14,8 +16,16 @@ Required properties :
Optional properties :
- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
- the default 100 kHz frequency will be used. As only Normal and Fast modes
- are supported, possible values are 100000 and 400000.
+ the default 100 kHz frequency will be used.
+ For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
+ 100000 and 400000.
+ For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,
+ possible values are 100000, 400000 and 1000000.
+- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board
+ (default: 25)
+- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board
+ (default: 10)
+ I2C Timings are derived from these 2 values
Example :
@@ -31,3 +41,16 @@ Example :
pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
pinctrl-names = "default";
};
+
+ i2c@40005400 {
+ compatible = "st,stm32f7-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
+ clocks = <&rcc 1 CLK_I2C1>;
+ pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
+ pinctrl-names = "default";
+ };
diff --git a/dts/Bindings/i2c/nvidia,tegra20-i2c.txt b/dts/Bindings/i2c/nvidia,tegra20-i2c.txt
index 656716b72c..f64064f8bd 100644
--- a/dts/Bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/dts/Bindings/i2c/nvidia,tegra20-i2c.txt
@@ -71,5 +71,4 @@ Example:
reset-names = "i2c";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
- status = "disabled";
};
diff --git a/dts/Bindings/iio/adc/at91-sama5d2_adc.txt b/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
index 3223684a64..552e7a8395 100644
--- a/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
+++ b/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
@@ -11,6 +11,11 @@ Required properties:
- atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
- atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
- atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC.
+ - atmel,trigger-edge-type: One of possible edge types for the ADTRG hardware
+ trigger pin. When the specific edge type is detected, the conversion will
+ start. Possible values are rising, falling, or both.
+ This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING ,
+ IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH
Example:
@@ -25,4 +30,5 @@ adc: adc@fc030000 {
atmel,startup-time-ms = <4>;
vddana-supply = <&vdd_3v3_lp_reg>;
vref-supply = <&vdd_3v3_lp_reg>;
+ atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
}
diff --git a/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt b/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
index caaaed765c..7b1b1e4086 100644
--- a/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
+++ b/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
@@ -37,5 +37,4 @@ For example:
clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
clock-names = "tsc_clk";
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
};
diff --git a/dts/Bindings/iio/adc/lpc1850-adc.txt b/dts/Bindings/iio/adc/lpc1850-adc.txt
index 0bcae5140b..9ada5abd45 100644
--- a/dts/Bindings/iio/adc/lpc1850-adc.txt
+++ b/dts/Bindings/iio/adc/lpc1850-adc.txt
@@ -17,5 +17,4 @@ adc0: adc@400e3000 {
clocks = <&ccu1 CLK_APB3_ADC0>;
vref-supply = <&reg_vdda>;
resets = <&rgu 40>;
- status = "disabled";
};
diff --git a/dts/Bindings/iio/adc/mt6577_auxadc.txt b/dts/Bindings/iio/adc/mt6577_auxadc.txt
index 68c45cbbe3..64dc4843c1 100644
--- a/dts/Bindings/iio/adc/mt6577_auxadc.txt
+++ b/dts/Bindings/iio/adc/mt6577_auxadc.txt
@@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
+ - "mediatek,mt7622-auxadc": For MT7622 family of SoCs
- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
- reg: Address range of the AUXADC unit.
- clocks: Should contain a clock specifier for each entry in clock-names
diff --git a/dts/Bindings/iio/adc/rockchip-saradc.txt b/dts/Bindings/iio/adc/rockchip-saradc.txt
index e0a9b9d6d6..c2c50b5987 100644
--- a/dts/Bindings/iio/adc/rockchip-saradc.txt
+++ b/dts/Bindings/iio/adc/rockchip-saradc.txt
@@ -6,6 +6,7 @@ Required properties:
- "rockchip,rk3066-tsadc": for rk3036
- "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328
- "rockchip,rk3399-saradc": for rk3399
+ - "rockchip,rv1108-saradc", "rockchip,rk3399-saradc": for rv1108
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/dts/Bindings/iio/adc/st,stm32-adc.txt b/dts/Bindings/iio/adc/st,stm32-adc.txt
index 8310073f14..48bfcaa3ff 100644
--- a/dts/Bindings/iio/adc/st,stm32-adc.txt
+++ b/dts/Bindings/iio/adc/st,stm32-adc.txt
@@ -74,6 +74,11 @@ Optional properties:
* can be 6, 8, 10 or 12 on stm32f4
* can be 8, 10, 12, 14 or 16 on stm32h7
Default is maximum resolution if unset.
+- st,min-sample-time-nsecs: Minimum sampling time in nanoseconds.
+ Depending on hardware (board) e.g. high/low analog input source impedance,
+ fine tune of ADC sampling time may be recommended.
+ This can be either one value or an array that matches 'st,adc-channels' list,
+ to set sample time resp. for all channels, or independently for each channel.
Example:
adc: adc@40012000 {
diff --git a/dts/Bindings/iio/counter/stm32-lptimer-cnt.txt b/dts/Bindings/iio/counter/stm32-lptimer-cnt.txt
new file mode 100644
index 0000000000..a04aa5c041
--- /dev/null
+++ b/dts/Bindings/iio/counter/stm32-lptimer-cnt.txt
@@ -0,0 +1,27 @@
+STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter
+
+STM32 Low-Power Timer provides several counter modes. It can be used as:
+- quadrature encoder to detect angular position and direction of rotary
+ elements, from IN1 and IN2 input signals.
+- simple counter from IN1 input signal.
+
+Must be a sub-node of an STM32 Low-Power Timer device tree node.
+See ../mfd/stm32-lptimer.txt for details about the parent node.
+
+Required properties:
+- compatible: Must be "st,stm32-lptimer-counter".
+- pinctrl-names: Set to "default".
+- pinctrl-0: List of phandles pointing to pin configuration nodes,
+ to set IN1/IN2 pins in mode of operation for Low-Power
+ Timer input on external pin.
+
+Example:
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ ...
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lptim1_in_pins>;
+ };
+ };
diff --git a/dts/Bindings/iio/dac/lpc1850-dac.txt b/dts/Bindings/iio/dac/lpc1850-dac.txt
index 7d6647d4af..42db783c4e 100644
--- a/dts/Bindings/iio/dac/lpc1850-dac.txt
+++ b/dts/Bindings/iio/dac/lpc1850-dac.txt
@@ -16,5 +16,4 @@ dac: dac@400e1000 {
clocks = <&ccu1 CLK_APB3_DAC>;
vref-supply = <&reg_vdda>;
resets = <&rgu 42>;
- status = "disabled";
};
diff --git a/dts/Bindings/iio/dac/st,stm32-dac.txt b/dts/Bindings/iio/dac/st,stm32-dac.txt
index bcee71f808..bf2925c671 100644
--- a/dts/Bindings/iio/dac/st,stm32-dac.txt
+++ b/dts/Bindings/iio/dac/st,stm32-dac.txt
@@ -10,7 +10,9 @@ current.
Contents of a stm32 dac root node:
-----------------------------------
Required properties:
-- compatible: Must be "st,stm32h7-dac-core".
+- compatible: Should be one of:
+ "st,stm32f4-dac-core"
+ "st,stm32h7-dac-core"
- reg: Offset and length of the device's register set.
- clocks: Must contain an entry for pclk (which feeds the peripheral bus
interface)
diff --git a/dts/Bindings/iio/humidity/hdc100x.txt b/dts/Bindings/iio/humidity/hdc100x.txt
new file mode 100644
index 0000000000..c52333bdfd
--- /dev/null
+++ b/dts/Bindings/iio/humidity/hdc100x.txt
@@ -0,0 +1,17 @@
+* HDC100x temperature + humidity sensors
+
+Required properties:
+ - compatible: Should contain one of the following:
+ ti,hdc1000
+ ti,hdc1008
+ ti,hdc1010
+ ti,hdc1050
+ ti,hdc1080
+ - reg: i2c address of the sensor
+
+Example:
+
+hdc100x@40 {
+ compatible = "ti,hdc1000";
+ reg = <0x40>;
+};
diff --git a/dts/Bindings/iio/humidity/hts221.txt b/dts/Bindings/iio/humidity/hts221.txt
index b20ab9c120..10adeb0d70 100644
--- a/dts/Bindings/iio/humidity/hts221.txt
+++ b/dts/Bindings/iio/humidity/hts221.txt
@@ -5,9 +5,18 @@ Required properties:
- reg: i2c address of the sensor / spi cs line
Optional properties:
+- drive-open-drain: the interrupt/data ready line will be configured
+ as open drain, which is useful if several sensors share the same
+ interrupt line. This is a boolean property.
+ If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or
+ IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
+ when it is not active, whereas a pull-up one is needed when interrupt
+ line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
+ Refer to pinctrl/pinctrl-bindings.txt for the property description.
- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
- flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
+ flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
+ IRQ_TYPE_EDGE_FALLING.
Refer to interrupt-controller/interrupts.txt for generic interrupt
client node bindings.
diff --git a/dts/Bindings/iio/humidity/htu21.txt b/dts/Bindings/iio/humidity/htu21.txt
new file mode 100644
index 0000000000..97d79636f7
--- /dev/null
+++ b/dts/Bindings/iio/humidity/htu21.txt
@@ -0,0 +1,13 @@
+*HTU21 - Measurement-Specialties htu21 temperature & humidity sensor and humidity part of MS8607 sensor
+
+Required properties:
+
+ - compatible: should be "meas,htu21" or "meas,ms8607-humidity"
+ - reg: I2C address of the sensor
+
+Example:
+
+htu21@40 {
+ compatible = "meas,htu21";
+ reg = <0x40>;
+};
diff --git a/dts/Bindings/iio/imu/st_lsm6dsx.txt b/dts/Bindings/iio/imu/st_lsm6dsx.txt
index 6f28ff55f3..1ff1af799c 100644
--- a/dts/Bindings/iio/imu/st_lsm6dsx.txt
+++ b/dts/Bindings/iio/imu/st_lsm6dsx.txt
@@ -11,6 +11,14 @@ Required properties:
Optional properties:
- st,drdy-int-pin: the pin on the package that will be used to signal
"data ready" (valid values: 1 or 2).
+- drive-open-drain: the interrupt/data ready line will be configured
+ as open drain, which is useful if several sensors share the same
+ interrupt line. This is a boolean property.
+ (This binding is taken from pinctrl/pinctrl-bindings.txt)
+ If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or
+ IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
+ when it is not active, whereas a pull-up one is needed when interrupt
+ line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
diff --git a/dts/Bindings/iio/pressure/ms5637.txt b/dts/Bindings/iio/pressure/ms5637.txt
new file mode 100644
index 0000000000..1f43ffa068
--- /dev/null
+++ b/dts/Bindings/iio/pressure/ms5637.txt
@@ -0,0 +1,17 @@
+* MS5637 - Measurement-Specialties MS5637, MS5805, MS5837 and MS8607 pressure & temperature sensor
+
+Required properties:
+
+ -compatible: should be one of the following
+ meas,ms5637
+ meas,ms5805
+ meas,ms5837
+ meas,ms8607-temppressure
+ -reg: I2C address of the sensor
+
+Example:
+
+ms5637@76 {
+ compatible = "meas,ms5637";
+ reg = <0x76>;
+};
diff --git a/dts/Bindings/iio/st-sensors.txt b/dts/Bindings/iio/st-sensors.txt
index eaa8fbba34..9ec6f5ce54 100644
--- a/dts/Bindings/iio/st-sensors.txt
+++ b/dts/Bindings/iio/st-sensors.txt
@@ -45,6 +45,7 @@ Accelerometers:
- st,lis2dh12-accel
- st,h3lis331dl-accel
- st,lng2dm-accel
+- st,lis3l02dq
Gyroscopes:
- st,l3g4200d-gyro
@@ -52,6 +53,7 @@ Gyroscopes:
- st,lsm330dl-gyro
- st,lsm330dlc-gyro
- st,l3gd20-gyro
+- st,l3gd20h-gyro
- st,l3g4is-gyro
- st,lsm330-gyro
- st,lsm9ds0-gyro
@@ -62,6 +64,7 @@ Magnetometers:
- st,lsm303dlhc-magn
- st,lsm303dlm-magn
- st,lis3mdl-magn
+- st,lis2mdl
Pressure sensors:
- st,lps001wp-press
diff --git a/dts/Bindings/iio/temperature/tsys01.txt b/dts/Bindings/iio/temperature/tsys01.txt
new file mode 100644
index 0000000000..0d5cc5595d
--- /dev/null
+++ b/dts/Bindings/iio/temperature/tsys01.txt
@@ -0,0 +1,19 @@
+* TSYS01 - Measurement Specialties temperature sensor
+
+Required properties:
+
+ - compatible: should be "meas,tsys01"
+ - reg: I2C address of the sensor (changeable via CSB pin)
+
+ ------------------------
+ | CSB | Device Address |
+ ------------------------
+ 1 0x76
+ 0 0x77
+
+Example:
+
+tsys01@76 {
+ compatible = "meas,tsys01";
+ reg = <0x76>;
+};
diff --git a/dts/Bindings/iio/timer/stm32-lptimer-trigger.txt b/dts/Bindings/iio/timer/stm32-lptimer-trigger.txt
new file mode 100644
index 0000000000..85e6806b17
--- /dev/null
+++ b/dts/Bindings/iio/timer/stm32-lptimer-trigger.txt
@@ -0,0 +1,23 @@
+STMicroelectronics STM32 Low-Power Timer Trigger
+
+STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used
+by STM32 internal ADC and/or DAC.
+
+Must be a sub-node of an STM32 Low-Power Timer device tree node.
+See ../mfd/stm32-lptimer.txt for details about the parent node.
+
+Required properties:
+- compatible: Must be "st,stm32-lptimer-trigger".
+- reg: Identify trigger hardware block. Must be 0, 1 or 2
+ respectively for lptimer1, lptimer2 or lptimer3
+ trigger output.
+
+Example:
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ ...
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ };
+ };
diff --git a/dts/Bindings/iio/timer/stm32-timer-trigger.txt b/dts/Bindings/iio/timer/stm32-timer-trigger.txt
index 55a653d153..b8e8c769d4 100644
--- a/dts/Bindings/iio/timer/stm32-timer-trigger.txt
+++ b/dts/Bindings/iio/timer/stm32-timer-trigger.txt
@@ -4,7 +4,9 @@ Must be a sub-node of an STM32 Timers device tree node.
See ../mfd/stm32-timers.txt for details about the parent node.
Required parameters:
-- compatible: Must be "st,stm32-timer-trigger".
+- compatible: Must be one of:
+ "st,stm32-timer-trigger"
+ "st,stm32h7-timer-trigger"
- reg: Identify trigger hardware block.
Example:
@@ -14,7 +16,7 @@ Example:
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc 0 160>;
- clock-names = "clk_int";
+ clock-names = "int";
timer@0 {
compatible = "st,stm32-timer-trigger";
diff --git a/dts/Bindings/input/atmel,maxtouch.txt b/dts/Bindings/input/atmel,maxtouch.txt
index 1852906517..23e3abc3fd 100644
--- a/dts/Bindings/input/atmel,maxtouch.txt
+++ b/dts/Bindings/input/atmel,maxtouch.txt
@@ -22,6 +22,8 @@ Optional properties for main touchpad device:
experiment to determine which bit corresponds to which input. Use
KEY_RESERVED for unused padding values.
+- reset-gpios: GPIO specifier for the touchscreen's reset pin (active low)
+
Example:
touch@4b {
diff --git a/dts/Bindings/input/brcm,bcm-keypad.txt b/dts/Bindings/input/brcm,bcm-keypad.txt
index b77f50bd64..262deab735 100644
--- a/dts/Bindings/input/brcm,bcm-keypad.txt
+++ b/dts/Bindings/input/brcm,bcm-keypad.txt
@@ -72,7 +72,6 @@ Example:
/* Required Board specific properties */
keypad,num-rows = <5>;
keypad,num-columns = <5>;
- status = "okay";
linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
diff --git a/dts/Bindings/input/pwm-vibrator.txt b/dts/Bindings/input/pwm-vibrator.txt
new file mode 100644
index 0000000000..09145d1849
--- /dev/null
+++ b/dts/Bindings/input/pwm-vibrator.txt
@@ -0,0 +1,66 @@
+* PWM vibrator device tree bindings
+
+Registers a PWM device as vibrator. It is expected, that the vibrator's
+strength increases based on the duty cycle of the enable PWM channel
+(100% duty cycle meaning strongest vibration, 0% meaning no vibration).
+
+The binding supports an optional direction PWM channel, that can be
+driven at fixed duty cycle. If available this is can be used to increase
+the vibration effect of some devices.
+
+Required properties:
+- compatible: should contain "pwm-vibrator"
+- pwm-names: Should contain "enable" and optionally "direction"
+- pwms: Should contain a PWM handle for each entry in pwm-names
+
+Optional properties:
+- vcc-supply: Phandle for the regulator supplying power
+- direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
+ nanoseconds, defaults to 50% of the channel's
+ period.
+
+Example from Motorola Droid 4:
+
+&omap4_pmx_core {
+ vibrator_direction_pin: pinmux_vibrator_direction_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
+ >;
+ };
+
+ vibrator_enable_pin: pinmux_vibrator_enable_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
+ >;
+ };
+};
+
+/ {
+ pwm8: dmtimer-pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_direction_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer8>;
+ ti,clock-source = <0x01>;
+ };
+
+ pwm9: dmtimer-pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_enable_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer9>;
+ ti,clock-source = <0x01>;
+ };
+
+ vibrator {
+ compatible = "pwm-vibrator";
+ pwms = <&pwm8 0 1000000000 0>,
+ <&pwm9 0 1000000000 0>;
+ pwm-names = "enable", "direction";
+ direction-duty-cycle-ns = <1000000000>;
+ };
+};
diff --git a/dts/Bindings/input/ti,drv260x.txt b/dts/Bindings/input/ti,drv260x.txt
index ee09c8f447..4c5312eaaa 100644
--- a/dts/Bindings/input/ti,drv260x.txt
+++ b/dts/Bindings/input/ti,drv260x.txt
@@ -43,7 +43,7 @@ haptics: haptics@5a {
mode = <DRV260X_LRA_MODE>;
library-sel = <DRV260X_LIB_LRA>;
vib-rated-mv = <3200>;
- vib-overdriver-mv = <3200>;
+ vib-overdrive-mv = <3200>;
}
For more product information please see the link below:
diff --git a/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
index 9d9e930f32..df531b5b6a 100644
--- a/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
+++ b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
@@ -32,5 +32,4 @@ Example:
pinctrl-1 = <&pinctrl_touchctrl_default>;
pinctrl-2 = <&pinctrl_touchctrl_gpios>;
vf50-ts-min-pressure = <200>;
- status = "disabled";
};
diff --git a/dts/Bindings/input/touchscreen/imx6ul_tsc.txt b/dts/Bindings/input/touchscreen/imx6ul_tsc.txt
index d4927c202a..e67e58b617 100644
--- a/dts/Bindings/input/touchscreen/imx6ul_tsc.txt
+++ b/dts/Bindings/input/touchscreen/imx6ul_tsc.txt
@@ -35,5 +35,4 @@ Example:
measure-delay-time = <0xfff>;
pre-charge-time = <0xffff>;
touchscreen-average-samples = <32>;
- status = "okay";
};
diff --git a/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index 9e38949320..49ccabbfa6 100644
--- a/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -4,8 +4,10 @@ Required properties:
- compatible: should be "fsl,<soc-name>-msi" to identify
Layerscape PCIe MSI controller block such as:
- "fsl,1s1021a-msi"
- "fsl,1s1043a-msi"
+ "fsl,ls1021a-msi"
+ "fsl,ls1043a-msi"
+ "fsl,ls1046a-msi"
+ "fsl,ls1043a-v1.1-msi"
- msi-controller: indicates that this is a PCIe MSI controller node
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
@@ -23,7 +25,7 @@ MSI controller node
Examples:
msi1: msi-controller@1571000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1571000 0x0 0x8>,
msi-controller;
interrupts = <0 116 0x4>;
diff --git a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
index 11cc87aeb2..07bf0b9a51 100644
--- a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
@@ -17,6 +17,7 @@ Required properties:
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
+ "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
diff --git a/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt b/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt
new file mode 100644
index 0000000000..48e71d3ac2
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt
@@ -0,0 +1,32 @@
+UniPhier AIDET
+
+UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic
+Interrupt Controller). GIC itself can handle only high level and rising edge
+interrupts. The AIDET provides logic inverter to support low level and falling
+edge interrupts.
+
+Required properties:
+- compatible: Should be one of the following:
+ "socionext,uniphier-ld4-aidet" - for LD4 SoC
+ "socionext,uniphier-pro4-aidet" - for Pro4 SoC
+ "socionext,uniphier-sld8-aidet" - for sLD8 SoC
+ "socionext,uniphier-pro5-aidet" - for Pro5 SoC
+ "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC
+ "socionext,uniphier-ld11-aidet" - for LD11 SoC
+ "socionext,uniphier-ld20-aidet" - for LD20 SoC
+ "socionext,uniphier-pxs3-aidet" - for PXs3 SoC
+- reg: Specifies offset and length of the register set for the device.
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an interrupt
+ source. The value should be 2. The first cell defines the interrupt number
+ (corresponds to the SPI interrupt number of GIC). The second cell specifies
+ the trigger type as defined in interrupts.txt in this directory.
+
+Example:
+
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pro4-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/dts/Bindings/iommu/qcom,iommu.txt b/dts/Bindings/iommu/qcom,iommu.txt
new file mode 100644
index 0000000000..b2641ceb2b
--- /dev/null
+++ b/dts/Bindings/iommu/qcom,iommu.txt
@@ -0,0 +1,121 @@
+* QCOM IOMMU v1 Implementation
+
+Qualcomm "B" family devices which are not compatible with arm-smmu have
+a similar looking IOMMU but without access to the global register space,
+and optionally requiring additional configuration to route context irqs
+to non-secure vs secure interrupt line.
+
+** Required properties:
+
+- compatible : Should be one of:
+
+ "qcom,msm8916-iommu"
+
+ Followed by "qcom,msm-iommu-v1".
+
+- clock-names : Should be a pair of "iface" (required for IOMMUs
+ register group access) and "bus" (required for
+ the IOMMUs underlying bus access).
+
+- clocks : Phandles for respective clocks described by
+ clock-names.
+
+- #address-cells : must be 1.
+
+- #size-cells : must be 1.
+
+- #iommu-cells : Must be 1. Index identifies the context-bank #.
+
+- ranges : Base address and size of the iommu context banks.
+
+- qcom,iommu-secure-id : secure-id.
+
+- List of sub-nodes, one per translation context bank. Each sub-node
+ has the following required properties:
+
+ - compatible : Should be one of:
+ - "qcom,msm-iommu-v1-ns" : non-secure context bank
+ - "qcom,msm-iommu-v1-sec" : secure context bank
+ - reg : Base address and size of context bank within the iommu
+ - interrupts : The context fault irq.
+
+** Optional properties:
+
+- reg : Base address and size of the SMMU local base, should
+ be only specified if the iommu requires configuration
+ for routing of context bank irq's to secure vs non-
+ secure lines. (Ie. if the iommu contains secure
+ context banks)
+
+
+** Examples:
+
+ apps_iommu: iommu@1e20000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1e20000 0x40000>;
+ reg = <0x1ef0000 0x3000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_CLK>;
+ clock-names = "iface", "bus";
+ qcom,iommu-secure-id = <17>;
+
+ // mdp_0:
+ iommu-ctx@4000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x4000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ // venus_ns:
+ iommu-ctx@5000 {
+ compatible = "qcom,msm-iommu-v1-sec";
+ reg = <0x5000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpu_iommu: iommu@1f08000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1f08000 0x10000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_GFX_TCU_CLK>;
+ clock-names = "iface", "bus";
+ qcom,iommu-secure-id = <18>;
+
+ // gfx3d_user:
+ iommu-ctx@1000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ // gfx3d_priv:
+ iommu-ctx@2000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ ...
+
+ venus: video-codec@1d00000 {
+ ...
+ iommus = <&apps_iommu 5>;
+ };
+
+ mdp: mdp@1a01000 {
+ ...
+ iommus = <&apps_iommu 4>;
+ };
+
+ gpu@01c00000 {
+ ...
+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+ };
diff --git a/dts/Bindings/iommu/rockchip,iommu.txt b/dts/Bindings/iommu/rockchip,iommu.txt
index 9a55ac3735..2098f77322 100644
--- a/dts/Bindings/iommu/rockchip,iommu.txt
+++ b/dts/Bindings/iommu/rockchip,iommu.txt
@@ -15,6 +15,11 @@ Required properties:
to associate with its master device. See:
Documentation/devicetree/bindings/iommu/iommu.txt
+Optional properties:
+- rockchip,disable-mmu-reset : Don't use the mmu reset operation.
+ Some mmu instances may produce unexpected results
+ when the reset operation is used.
+
Example:
vopl_mmu: iommu@ff940300 {
diff --git a/dts/Bindings/leds/ams,as3645a.txt b/dts/Bindings/leds/ams,as3645a.txt
new file mode 100644
index 0000000000..12c5ef26ec
--- /dev/null
+++ b/dts/Bindings/leds/ams,as3645a.txt
@@ -0,0 +1,71 @@
+Analog devices AS3645A device tree bindings
+
+The AS3645A flash LED controller can drive two LEDs, one high current
+flash LED and one indicator LED. The high current flash LED can be
+used in torch mode as well.
+
+Ranges below noted as [a, b] are closed ranges between a and b, i.e. a
+and b are included in the range.
+
+Please also see common.txt in the same directory.
+
+
+Required properties
+===================
+
+compatible : Must be "ams,as3645a".
+reg : The I2C address of the device. Typically 0x30.
+
+
+Required properties of the "flash" child node
+=============================================
+
+flash-timeout-us: Flash timeout in microseconds. The value must be in
+ the range [100000, 850000] and divisible by 50000.
+flash-max-microamp: Maximum flash current in microamperes. Has to be
+ in the range between [200000, 500000] and
+ divisible by 20000.
+led-max-microamp: Maximum torch (assist) current in microamperes. The
+ value must be in the range between [20000, 160000] and
+ divisible by 20000.
+ams,input-max-microamp: Maximum flash controller input current. The
+ value must be in the range [1250000, 2000000]
+ and divisible by 50000.
+
+
+Optional properties of the "flash" child node
+=============================================
+
+label : The label of the flash LED.
+
+
+Required properties of the "indicator" child node
+=================================================
+
+led-max-microamp: Maximum indicator current. The allowed values are
+ 2500, 5000, 7500 and 10000.
+
+Optional properties of the "indicator" child node
+=================================================
+
+label : The label of the indicator LED.
+
+
+Example
+=======
+
+ as3645a@30 {
+ reg = <0x30>;
+ compatible = "ams,as3645a";
+ flash {
+ flash-timeout-us = <150000>;
+ flash-max-microamp = <320000>;
+ led-max-microamp = <60000>;
+ ams,input-max-microamp = <1750000>;
+ label = "as3645a:flash";
+ };
+ indicator {
+ led-max-microamp = <10000>;
+ label = "as3645a:indicator";
+ };
+ };
diff --git a/dts/Bindings/leds/irled/gpio-ir-tx.txt b/dts/Bindings/leds/irled/gpio-ir-tx.txt
new file mode 100644
index 0000000000..cbe8dfd297
--- /dev/null
+++ b/dts/Bindings/leds/irled/gpio-ir-tx.txt
@@ -0,0 +1,14 @@
+Device tree bindings for IR LED connected through gpio pin which is used as
+remote controller transmitter.
+
+Required properties:
+ - compatible: should be "gpio-ir-tx".
+ - gpios : Should specify the IR LED GPIO, see "gpios property" in
+ Documentation/devicetree/bindings/gpio/gpio.txt. Active low LEDs
+ should be indicated using flags in the GPIO specifier.
+
+Example:
+ irled@0 {
+ compatible = "gpio-ir-tx";
+ gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/Bindings/leds/irled/pwm-ir-tx.txt b/dts/Bindings/leds/irled/pwm-ir-tx.txt
new file mode 100644
index 0000000000..66e5672c2e
--- /dev/null
+++ b/dts/Bindings/leds/irled/pwm-ir-tx.txt
@@ -0,0 +1,13 @@
+Device tree bindings for IR LED connected through pwm pin which is used as
+remote controller transmitter.
+
+Required properties:
+ - compatible: should be "pwm-ir-tx".
+ - pwms : PWM property to point to the PWM device (phandle)/port (id)
+ and to specify the period time to be used: <&phandle id period_ns>;
+
+Example:
+ irled {
+ compatible = "pwm-ir-tx";
+ pwms = <&pwm0 0 10000000>;
+ };
diff --git a/dts/Bindings/leds/leds-gpio.txt b/dts/Bindings/leds/leds-gpio.txt
index 76535ca371..a48dda268f 100644
--- a/dts/Bindings/leds/leds-gpio.txt
+++ b/dts/Bindings/leds/leds-gpio.txt
@@ -18,6 +18,9 @@ LED sub-node properties:
see Documentation/devicetree/bindings/leds/common.txt
- retain-state-suspended: (optional) The suspend state can be retained.Such
as charge-led gpio.
+- retain-state-shutdown: (optional) Retain the state of the LED on shutdown.
+ Useful in BMC systems, for example when the BMC is rebooted while the host
+ remains up.
- panic-indicator : (optional)
see Documentation/devicetree/bindings/leds/common.txt
diff --git a/dts/Bindings/leds/leds-pca955x.txt b/dts/Bindings/leds/leds-pca955x.txt
new file mode 100644
index 0000000000..7984efb767
--- /dev/null
+++ b/dts/Bindings/leds/leds-pca955x.txt
@@ -0,0 +1,88 @@
+* NXP - pca955x LED driver
+
+The PCA955x family of chips are I2C LED blinkers whose pins not used
+to control LEDs can be used as general purpose I/Os. The GPIO pins can
+be input or output, and output pins can also be pulse-width controlled.
+
+Required properties:
+- compatible : should be one of :
+ "nxp,pca9550"
+ "nxp,pca9551"
+ "nxp,pca9552"
+ "nxp,pca9553"
+- #address-cells: must be 1
+- #size-cells: must be 0
+- reg: I2C slave address. depends on the model.
+
+Optional properties:
+- gpio-controller: allows pins to be used as GPIOs.
+- #gpio-cells: must be 2.
+- gpio-line-names: define the names of the GPIO lines
+
+LED sub-node properties:
+- reg : number of LED line.
+ from 0 to 1 for the pca9550
+ from 0 to 7 for the pca9551
+ from 0 to 15 for the pca9552
+ from 0 to 3 for the pca9553
+- type: (optional) either
+ PCA9532_TYPE_NONE
+ PCA9532_TYPE_LED
+ PCA9532_TYPE_GPIO
+ see dt-bindings/leds/leds-pca955x.h (default to LED)
+- label : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+- linux,default-trigger : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+
+Examples:
+
+pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x60>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "GPIO12", "GPIO13", "GPIO14", "GPIO15";
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ led@0 {
+ label = "red:power";
+ linux,default-trigger = "default-on";
+ reg = <0>;
+ type = <PCA955X_TYPE_LED>;
+ };
+ led@1 {
+ label = "green:power";
+ reg = <1>;
+ type = <PCA955X_TYPE_LED>;
+ };
+ led@2 {
+ label = "pca9552:yellow";
+ reg = <2>;
+ type = <PCA955X_TYPE_LED>;
+ };
+ led@3 {
+ label = "pca9552:white";
+ reg = <3>;
+ type = <PCA955X_TYPE_LED>;
+ };
+};
diff --git a/dts/Bindings/media/i2c/adv748x.txt b/dts/Bindings/media/i2c/adv748x.txt
new file mode 100644
index 0000000000..21ffb5ed81
--- /dev/null
+++ b/dts/Bindings/media/i2c/adv748x.txt
@@ -0,0 +1,95 @@
+* Analog Devices ADV748X video decoder with HDMI receiver
+
+The ADV7481 and ADV7482 are multi format video decoders with an integrated
+HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
+from three input sources HDMI, analog and TTL.
+
+Required Properties:
+
+ - compatible: Must contain one of the following
+ - "adi,adv7481" for the ADV7481
+ - "adi,adv7482" for the ADV7482
+
+ - reg: I2C slave address
+
+Optional Properties:
+
+ - interrupt-names: Should specify the interrupts as "intrq1", "intrq2" and/or
+ "intrq3". All interrupts are optional. The "intrq3" interrupt
+ is only available on the adv7481
+ - interrupts: Specify the interrupt lines for the ADV748x
+
+The device node must contain one 'port' child node per device input and output
+port, in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
+are numbered as follows.
+
+ Name Type Port
+ ---------------------------------------
+ AIN0 sink 0
+ AIN1 sink 1
+ AIN2 sink 2
+ AIN3 sink 3
+ AIN4 sink 4
+ AIN5 sink 5
+ AIN6 sink 6
+ AIN7 sink 7
+ HDMI sink 8
+ TTL sink 9
+ TXA source 10
+ TXB source 11
+
+The digital output port nodes must contain at least one endpoint.
+
+Ports are optional if they are not connected to anything at the hardware level.
+
+Example:
+
+ video-receiver@70 {
+ compatible = "adi,adv7482";
+ reg = <0x70>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gpio6>;
+ interrupt-names = "intrq1", "intrq2";
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
+ <31 IRQ_TYPE_LEVEL_LOW>;
+
+ port@7 {
+ reg = <7>;
+
+ adv7482_ain7: endpoint {
+ remote-endpoint = <&cvbs_in>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+
+ adv7482_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+
+ port@10 {
+ reg = <10>;
+
+ adv7482_txa: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csi40_in>;
+ };
+ };
+
+ port@11 {
+ reg = <11>;
+
+ adv7482_txb: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1>;
+ remote-endpoint = <&csi20_in>;
+ };
+ };
+ };
diff --git a/dts/Bindings/media/i2c/dongwoon,dw9714.txt b/dts/Bindings/media/i2c/dongwoon,dw9714.txt
new file mode 100644
index 0000000000..b88dcdd41d
--- /dev/null
+++ b/dts/Bindings/media/i2c/dongwoon,dw9714.txt
@@ -0,0 +1,9 @@
+Dongwoon Anatech DW9714 camera voice coil lens driver
+
+DW9174 is a 10-bit DAC with current sink capability. It is intended
+for driving voice coil lenses in camera modules.
+
+Mandatory properties:
+
+- compatible: "dongwoon,dw9714"
+- reg: I²C slave address
diff --git a/dts/Bindings/media/meson-ao-cec.txt b/dts/Bindings/media/meson-ao-cec.txt
new file mode 100644
index 0000000000..8671bdb080
--- /dev/null
+++ b/dts/Bindings/media/meson-ao-cec.txt
@@ -0,0 +1,28 @@
+* Amlogic Meson AO-CEC driver
+
+The Amlogic Meson AO-CEC module is present is Amlogic SoCs and its purpose is
+to handle communication between HDMI connected devices over the CEC bus.
+
+Required properties:
+ - compatible : value should be following
+ "amlogic,meson-gx-ao-cec"
+
+ - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+ - interrupts : AO-CEC interrupt number to the CPU.
+ - clocks : from common clock binding: handle to AO-CEC clock.
+ - clock-names : from common clock binding: must contain "core",
+ corresponding to entry in the clocks property.
+ - hdmi-phandle: phandle to the HDMI controller
+
+Example:
+
+cec_AO: cec@100 {
+ compatible = "amlogic,meson-gx-ao-cec";
+ reg = <0x0 0x00100 0x0 0x14>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_AO CLKID_AO_CEC_32K>;
+ clock-names = "core";
+ hdmi-phandle = <&hdmi_tx>;
+};
diff --git a/dts/Bindings/media/mtk-cir.txt b/dts/Bindings/media/mtk-cir.txt
index 2be2005577..5e18087ce1 100644
--- a/dts/Bindings/media/mtk-cir.txt
+++ b/dts/Bindings/media/mtk-cir.txt
@@ -2,10 +2,14 @@ Device-Tree bindings for Mediatek consumer IR controller
found in Mediatek SoC family
Required properties:
-- compatible : "mediatek,mt7623-cir"
+- compatible : Should be
+ "mediatek,mt7623-cir": for MT7623 SoC
+ "mediatek,mt7622-cir": for MT7622 SoC
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
-- clock-names : should contain "clk" entries;
+- clock-names : should contain
+ - "clk" entries: for MT7623 SoC
+ - "clk", "bus" entries: for MT7622 SoC
- interrupts : should contain IR IRQ number;
- reg : should contain IO map address for IR.
diff --git a/dts/Bindings/media/pxa-camera.txt b/dts/Bindings/media/pxa-camera.txt
index 11f5b5d51a..bc03ec0962 100644
--- a/dts/Bindings/media/pxa-camera.txt
+++ b/dts/Bindings/media/pxa-camera.txt
@@ -24,7 +24,6 @@ Example:
clock-frequency = <50000000>;
clock-output-names = "qci_mclk";
- status = "okay";
port {
#address-cells = <1>;
diff --git a/dts/Bindings/media/qcom,camss.txt b/dts/Bindings/media/qcom,camss.txt
new file mode 100644
index 0000000000..cadecebc73
--- /dev/null
+++ b/dts/Bindings/media/qcom,camss.txt
@@ -0,0 +1,197 @@
+Qualcomm Camera Subsystem
+
+* Properties
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain:
+ - "qcom,msm8916-camss"
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Register ranges as listed in the reg-names property.
+- reg-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "csiphy0"
+ - "csiphy0_clk_mux"
+ - "csiphy1"
+ - "csiphy1_clk_mux"
+ - "csid0"
+ - "csid1"
+ - "ispif"
+ - "csi_clk_mux"
+ - "vfe0"
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Interrupts as listed in the interrupt-names property.
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "csiphy0"
+ - "csiphy1"
+ - "csid0"
+ - "csid1"
+ - "ispif"
+ - "vfe0"
+- power-domains:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A phandle and power domain specifier pairs to the
+ power domain which is responsible for collapsing
+ and restoring power to the peripheral.
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A list of phandle and clock specifier pairs as listed
+ in clock-names property.
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "camss_top_ahb"
+ - "ispif_ahb"
+ - "csiphy0_timer"
+ - "csiphy1_timer"
+ - "csi0_ahb"
+ - "csi0"
+ - "csi0_phy"
+ - "csi0_pix"
+ - "csi0_rdi"
+ - "csi1_ahb"
+ - "csi1"
+ - "csi1_phy"
+ - "csi1_pix"
+ - "csi1_rdi"
+ - "camss_ahb"
+ - "camss_vfe_vfe"
+ - "camss_csi_vfe"
+ - "iface"
+ - "bus"
+- vdda-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: A phandle to voltage supply for CSI2.
+- iommus:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A list of phandle and IOMMU specifier pairs.
+
+* Nodes
+
+- ports:
+ Usage: required
+ Definition: As described in video-interfaces.txt in same directory.
+ Properties:
+ - reg:
+ Usage: required
+ Value type: <u32>
+ Definition: Selects CSI2 PHY interface - PHY0 or PHY1.
+ Endpoint node properties:
+ - clock-lanes:
+ Usage: required
+ Value type: <u32>
+ Definition: The physical clock lane index. The value
+ must always be <1> as the physical clock
+ lane is lane 1.
+ - data-lanes:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: An array of physical data lanes indexes.
+ Position of an entry determines the logical
+ lane number, while the value of an entry
+ indicates physical lane index. Lane swapping
+ is supported.
+
+* An Example
+
+ camss: camss@1b00000 {
+ compatible = "qcom,msm8916-camss";
+ reg = <0x1b0ac00 0x200>,
+ <0x1b00030 0x4>,
+ <0x1b0b000 0x200>,
+ <0x1b00038 0x4>,
+ <0x1b08000 0x100>,
+ <0x1b08400 0x100>,
+ <0x1b0a000 0x500>,
+ <0x1b00020 0x10>,
+ <0x1b10000 0x1000>;
+ reg-names = "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csid0",
+ "csid1",
+ "ispif",
+ "csi_clk_mux",
+ "vfe0";
+ interrupts = <GIC_SPI 78 0>,
+ <GIC_SPI 79 0>,
+ <GIC_SPI 51 0>,
+ <GIC_SPI 52 0>,
+ <GIC_SPI 55 0>,
+ <GIC_SPI 57 0>;
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csid0",
+ "csid1",
+ "ispif",
+ "vfe0";
+ power-domains = <&gcc VFE_GDSC>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>;
+ clock-names = "camss_top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "camss_ahb",
+ "camss_vfe_vfe",
+ "camss_csi_vfe",
+ "iface",
+ "bus";
+ vdda-supply = <&pm8916_l2>;
+ iommus = <&apps_iommu 3>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ csiphy0_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&ov5645_ep>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/media/renesas,drif.txt b/dts/Bindings/media/renesas,drif.txt
index 39516b94c2..0d8974aa8b 100644
--- a/dts/Bindings/media/renesas,drif.txt
+++ b/dts/Bindings/media/renesas,drif.txt
@@ -40,6 +40,7 @@ To summarize,
Required properties of an internal channel:
-------------------------------------------
- compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
+ "renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
"renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
When compatible with the generic version, nodes must list the
diff --git a/dts/Bindings/media/s5p-cec.txt b/dts/Bindings/media/s5p-cec.txt
index 1b1a10ba48..6f3756da90 100644
--- a/dts/Bindings/media/s5p-cec.txt
+++ b/dts/Bindings/media/s5p-cec.txt
@@ -33,5 +33,4 @@ hdmicec: cec@100B0000 {
hdmi-phandle = <&hdmi>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
- status = "okay";
};
diff --git a/dts/Bindings/media/samsung-fimc.txt b/dts/Bindings/media/samsung-fimc.txt
index 922d6f8e74..e4e15d8d75 100644
--- a/dts/Bindings/media/samsung-fimc.txt
+++ b/dts/Bindings/media/samsung-fimc.txt
@@ -166,7 +166,6 @@ Example:
clock-output-names = "cam_a_clkout", "cam_b_clkout";
pinctrl-names = "default";
pinctrl-0 = <&cam_port_a_clk_active>;
- status = "okay";
#address-cells = <1>;
#size-cells = <1>;
@@ -189,7 +188,6 @@ Example:
compatible = "samsung,exynos4210-fimc";
reg = <0x11800000 0x1000>;
interrupts = <0 85 0>;
- status = "okay";
};
csis_0: csis@11880000 {
diff --git a/dts/Bindings/media/stih407-c8sectpfe.txt b/dts/Bindings/media/stih407-c8sectpfe.txt
index cc51b1fd6e..6af3fc210e 100644
--- a/dts/Bindings/media/stih407-c8sectpfe.txt
+++ b/dts/Bindings/media/stih407-c8sectpfe.txt
@@ -52,7 +52,6 @@ Example:
c8sectpfe@08a20000 {
compatible = "st,stih407-c8sectpfe";
- status = "okay";
reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
reg-names = "stfe", "stfe-ram";
interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>, <GIC_SPI 35 IRQ_TYPE_NONE>;
diff --git a/dts/Bindings/media/ti,da850-vpif.txt b/dts/Bindings/media/ti,da850-vpif.txt
index df7182a63e..e47c7ccc57 100644
--- a/dts/Bindings/media/ti,da850-vpif.txt
+++ b/dts/Bindings/media/ti,da850-vpif.txt
@@ -59,7 +59,6 @@ I2C-connected TVP5147 decoder:
tvp5147@5d {
compatible = "ti,tvp5147";
reg = <0x5d>;
- status = "okay";
port {
composite_in: endpoint {
diff --git a/dts/Bindings/media/video-interfaces.txt b/dts/Bindings/media/video-interfaces.txt
index 9cd2a36912..852041a748 100644
--- a/dts/Bindings/media/video-interfaces.txt
+++ b/dts/Bindings/media/video-interfaces.txt
@@ -76,6 +76,11 @@ Optional endpoint properties
mode horizontal and vertical synchronization signals are provided to the
slave device (data source) by the master device (data sink). In the master
mode the data source device is also the source of the synchronization signals.
+- bus-type: data bus type. Possible values are:
+ 0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656)
+ 1 - MIPI CSI-2 C-PHY
+ 2 - MIPI CSI1
+ 3 - CCP2
- bus-width: number of data lines actively used, valid for the parallel busses.
- data-shift: on the parallel data busses, if bus-width is used to specify the
number of data lines, data-shift can be used to specify which data lines are
@@ -112,7 +117,8 @@ Optional endpoint properties
should be the combined length of data-lanes and clock-lanes properties.
If the lane-polarities property is omitted, the value must be interpreted
as 0 (normal). This property is valid for serial busses only.
-
+- strobe: Whether the clock signal is used as clock (0) or strobe (1). Used
+ with CCP2, for instance.
Example
-------
diff --git a/dts/Bindings/media/zx-irdec.txt b/dts/Bindings/media/zx-irdec.txt
new file mode 100644
index 0000000000..295b9fab59
--- /dev/null
+++ b/dts/Bindings/media/zx-irdec.txt
@@ -0,0 +1,14 @@
+IR Decoder (IRDEC) on ZTE ZX family SoCs
+
+Required properties:
+ - compatible: Should be "zte,zx296718-irdec".
+ - reg: Physical base address and length of IRDEC registers.
+ - interrupts: Interrupt number of IRDEC.
+
+Exmaples:
+
+ irdec: ir-decoder@111000 {
+ compatible = "zte,zx296718-irdec";
+ reg = <0x111000 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
index 21277a56e9..ddf46b8856 100644
--- a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
@@ -15,6 +15,9 @@ Required properties:
the register.
- "smi" : It's the clock for transfer data and command.
+Required property for mt2701:
+- mediatek,larb-id :the hardware id of this larb.
+
Example:
larb1: larb@16010000 {
compatible = "mediatek,mt8173-smi-larb";
@@ -25,3 +28,15 @@ Example:
<&vdecsys CLK_VDEC_LARB_CKEN>;
clock-names = "apb", "smi";
};
+
+Example for mt2701:
+ larb0: larb@14010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x14010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <0>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
diff --git a/dts/Bindings/memory-controllers/mvebu-devbus.txt b/dts/Bindings/memory-controllers/mvebu-devbus.txt
index 1ee3bc09f3..8b9388cc1c 100644
--- a/dts/Bindings/memory-controllers/mvebu-devbus.txt
+++ b/dts/Bindings/memory-controllers/mvebu-devbus.txt
@@ -130,7 +130,6 @@ The reg property implicitly specifies the chip select as this:
Example:
devbus-bootcs@d0010400 {
- status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/Bindings/mfd/act8945a.txt b/dts/Bindings/mfd/act8945a.txt
index 462819ac3d..e6f168db6c 100644
--- a/dts/Bindings/mfd/act8945a.txt
+++ b/dts/Bindings/mfd/act8945a.txt
@@ -12,7 +12,6 @@ Example:
pmic@5b {
compatible = "active-semi,act8945a";
reg = <0x5b>;
- status = "okay";
active-semi,vsel-high;
@@ -79,6 +78,5 @@ Example:
active-semi,input-voltage-threshold-microvolt = <6600>;
active-semi,precondition-timeout = <40>;
active-semi,total-timeout = <3>;
- status = "okay";
};
};
diff --git a/dts/Bindings/mfd/atmel-hlcdc.txt b/dts/Bindings/mfd/atmel-hlcdc.txt
index eec40be7f7..3f643ef121 100644
--- a/dts/Bindings/mfd/atmel-hlcdc.txt
+++ b/dts/Bindings/mfd/atmel-hlcdc.txt
@@ -25,7 +25,6 @@ Example:
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
- status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
diff --git a/dts/Bindings/mfd/atmel-smc.txt b/dts/Bindings/mfd/atmel-smc.txt
index 26eeed3739..1103ce2030 100644
--- a/dts/Bindings/mfd/atmel-smc.txt
+++ b/dts/Bindings/mfd/atmel-smc.txt
@@ -8,6 +8,7 @@ Required properties:
- compatible: Should be one of the following
"atmel,at91sam9260-smc", "syscon"
"atmel,sama5d3-smc", "syscon"
+ "atmel,sama5d2-smc", "syscon"
- reg: Contains offset/length value of the SMC memory
region.
diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt
index aca09af665..9455503b02 100644
--- a/dts/Bindings/mfd/axp20x.txt
+++ b/dts/Bindings/mfd/axp20x.txt
@@ -7,7 +7,14 @@ axp209 (X-Powers)
axp221 (X-Powers)
axp223 (X-Powers)
axp803 (X-Powers)
+axp806 (X-Powers)
axp809 (X-Powers)
+axp813 (X-Powers)
+
+The AXP813 is 2 chips packaged into 1. The 2 chips do not share anything
+other than the packaging. Pins are routed separately. As such they should
+be treated as separate entities. The other half is an AC100 RTC/codec
+combo chip. Please see ./ac100.txt for its bindings.
Required properties:
- compatible: should be one of:
@@ -19,6 +26,7 @@ Required properties:
* "x-powers,axp803"
* "x-powers,axp806"
* "x-powers,axp809"
+ * "x-powers,axp813"
- reg: The I2C slave address or RSB hardware address for the AXP chip
- interrupt-parent: The parent interrupt controller
- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
@@ -28,12 +36,14 @@ Required properties:
Optional properties:
- x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz
AXP152/20X: range: 750-1875, Default: 1.5 MHz
- AXP22X/80X: range: 1800-4050, Default: 3 MHz
+ AXP22X/8XX: range: 1800-4050, Default: 3 MHz
-- x-powers,drive-vbus-en: axp221 / axp223 only boolean, set this when the
- N_VBUSEN pin is used as an output pin to control an external
- regulator to drive the OTG VBus, rather then as an input pin
- which signals whether the board is driving OTG VBus or not.
+- x-powers,drive-vbus-en: boolean, set this when the N_VBUSEN pin is
+ used as an output pin to control an external
+ regulator to drive the OTG VBus, rather then
+ as an input pin which signals whether the
+ board is driving OTG VBus or not.
+ (axp221 / axp223 / axp813 only)
- x-powers,master-mode: Boolean (axp806 only). Set this when the PMIC is
wired for master mode. The default is slave mode.
@@ -171,6 +181,36 @@ LDO_IO1 : LDO : ips-supply : GPIO 1
RTC_LDO : LDO : ips-supply : always on
SW : On/Off Switch : swin-supply
+AXP813 regulators, type, and corresponding input supply names:
+
+Regulator Type Supply Name Notes
+--------- ---- ----------- -----
+DCDC1 : DC-DC buck : vin1-supply
+DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
+DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
+DCDC4 : DC-DC buck : vin4-supply
+DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
+DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
+DCDC7 : DC-DC buck : vin7-supply
+ALDO1 : LDO : aldoin-supply : shared supply
+ALDO2 : LDO : aldoin-supply : shared supply
+ALDO3 : LDO : aldoin-supply : shared supply
+DLDO1 : LDO : dldoin-supply : shared supply
+DLDO2 : LDO : dldoin-supply : shared supply
+DLDO3 : LDO : dldoin-supply : shared supply
+DLDO4 : LDO : dldoin-supply : shared supply
+ELDO1 : LDO : eldoin-supply : shared supply
+ELDO2 : LDO : eldoin-supply : shared supply
+ELDO3 : LDO : eldoin-supply : shared supply
+FLDO1 : LDO : fldoin-supply : shared supply
+FLDO2 : LDO : fldoin-supply : shared supply
+FLDO3 : LDO : fldoin-supply : shared supply
+LDO_IO0 : LDO : ips-supply : GPIO 0
+LDO_IO1 : LDO : ips-supply : GPIO 1
+RTC_LDO : LDO : ips-supply : always on
+SW : On/Off Switch : swin-supply
+DRIVEVBUS : Enable output : drivevbus-supply : external regulator
+
Example:
axp209: pmic@34 {
diff --git a/dts/Bindings/mfd/bd9571mwv.txt b/dts/Bindings/mfd/bd9571mwv.txt
new file mode 100644
index 0000000000..9ab216a851
--- /dev/null
+++ b/dts/Bindings/mfd/bd9571mwv.txt
@@ -0,0 +1,49 @@
+* ROHM BD9571MWV Power Management Integrated Circuit (PMIC) bindings
+
+Required properties:
+ - compatible : Should be "rohm,bd9571mwv".
+ - reg : I2C slave address.
+ - interrupt-parent : Phandle to the parent interrupt controller.
+ - interrupts : The interrupt line the device is connected to.
+ - interrupt-controller : Marks the device node as an interrupt controller.
+ - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as trigger
+ masks from ../interrupt-controller/interrupts.txt.
+ - gpio-controller : Marks the device node as a GPIO Controller.
+ - #gpio-cells : Should be two. The first cell is the pin number and
+ the second cell is used to specify flags.
+ See ../gpio/gpio.txt for more information.
+ - regulators: : List of child nodes that specify the regulator
+ initialization data. Child nodes must be named
+ after their hardware counterparts:
+ - vd09
+ - vd18
+ - vd25
+ - vd33
+ - dvfs
+ Each child node is defined using the standard
+ binding for regulators.
+
+Example:
+
+ pmic: pmic@30 {
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ regulators {
+ dvfs: dvfs {
+ regulator-name = "dvfs";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1030000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/da9052-i2c.txt b/dts/Bindings/mfd/da9052-i2c.txt
index 9554292dc6..07c69c0c66 100644
--- a/dts/Bindings/mfd/da9052-i2c.txt
+++ b/dts/Bindings/mfd/da9052-i2c.txt
@@ -4,6 +4,14 @@ Required properties:
- compatible : Should be "dlg,da9052", "dlg,da9053-aa",
"dlg,da9053-ab", or "dlg,da9053-bb"
+Optional properties:
+- dlg,tsi-as-adc : Boolean, if set the X+, X-, Y+, Y- touchscreen
+ input lines are used as general purpose analogue
+ input.
+- tsiref-supply: Phandle to the regulator, which provides the reference
+ voltage for the TSIREF pin. Must be provided when the
+ touchscreen pins are used for ADC purposes.
+
Sub-nodes:
- regulators : Contain the regulator nodes. The DA9052/53 regulators are
bound using their names as listed below:
@@ -29,7 +37,6 @@ Sub-nodes:
Examples:
i2c@63fc8000 { /* I2C1 */
- status = "okay";
pmic: dialog@48 {
compatible = "dlg,da9053-aa";
diff --git a/dts/Bindings/mfd/mc13xxx.txt b/dts/Bindings/mfd/mc13xxx.txt
index 8aba48821a..39ba414676 100644
--- a/dts/Bindings/mfd/mc13xxx.txt
+++ b/dts/Bindings/mfd/mc13xxx.txt
@@ -116,7 +116,6 @@ ecspi@70010000 { /* ECSPI1 */
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */
<&gpio4 25 0>; /* GPIO4_25 */
- status = "okay";
pmic: mc13892@0 {
#address-cells = <1>;
diff --git a/dts/Bindings/mfd/mxs-lradc.txt b/dts/Bindings/mfd/mxs-lradc.txt
index 555fb117d4..755cbef064 100644
--- a/dts/Bindings/mfd/mxs-lradc.txt
+++ b/dts/Bindings/mfd/mxs-lradc.txt
@@ -26,7 +26,6 @@ Example for i.MX23 SoC:
compatible = "fsl,imx23-lradc";
reg = <0x80050000 0x2000>;
interrupts = <36 37 38 39 40 41 42 43 44>;
- status = "okay";
fsl,lradc-touchscreen-wires = <4>;
fsl,ave-ctrl = <4>;
fsl,ave-delay = <2>;
@@ -39,7 +38,6 @@ Example for i.MX28 SoC:
compatible = "fsl,imx28-lradc";
reg = <0x80050000 0x2000>;
interrupts = <10 14 15 16 17 18 19 20 21 22 23 24 25>;
- status = "okay";
fsl,lradc-touchscreen-wires = <5>;
fsl,ave-ctrl = <4>;
fsl,ave-delay = <2>;
diff --git a/dts/Bindings/mfd/retu.txt b/dts/Bindings/mfd/retu.txt
new file mode 100644
index 0000000000..876242394a
--- /dev/null
+++ b/dts/Bindings/mfd/retu.txt
@@ -0,0 +1,25 @@
+* Device tree bindings for Nokia Retu and Tahvo multi-function device
+
+Retu and Tahvo are a multi-function devices found on Nokia Internet
+Tablets (770, N800 and N810). The Retu chip provides watchdog timer
+and power button control functionalities while Tahvo chip provides
+USB transceiver functionality.
+
+Required properties:
+- compatible: "nokia,retu" or "nokia,tahvo"
+- reg: Specifies the CBUS slave address of the ASIC chip
+- interrupts: The interrupt line the device is connected to
+- interrupt-parent: The parent interrupt controller
+
+Example:
+
+cbus0 {
+ compatible = "i2c-cbus-gpio";
+ ...
+ retu: retu@1 {
+ compatible = "nokia,retu";
+ interrupt-parent = <&gpio4>;
+ interrupts = <12 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x1>;
+ };
+};
diff --git a/dts/Bindings/mfd/rk808.txt b/dts/Bindings/mfd/rk808.txt
index 9636ae8d8d..91b65227af 100644
--- a/dts/Bindings/mfd/rk808.txt
+++ b/dts/Bindings/mfd/rk808.txt
@@ -1,11 +1,14 @@
RK8XX Power Management Integrated Circuit
The rk8xx family current members:
+rk805
rk808
rk818
Required properties:
-- compatible: "rockchip,rk808", "rockchip,rk818"
+- compatible: "rockchip,rk805"
+- compatible: "rockchip,rk808"
+- compatible: "rockchip,rk818"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
@@ -18,6 +21,14 @@ Optional properties:
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
+Optional RK805 properties:
+- vcc1-supply: The input supply for DCDC_REG1
+- vcc2-supply: The input supply for DCDC_REG2
+- vcc3-supply: The input supply for DCDC_REG3
+- vcc4-supply: The input supply for DCDC_REG4
+- vcc5-supply: The input supply for LDO_REG1 and LDO_REG2
+- vcc6-supply: The input supply for LDO_REG3
+
Optional RK808 properties:
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
@@ -56,6 +67,15 @@ by a child node of the 'regulators' node.
/* standard regulator bindings here */
};
+Following regulators of the RK805 PMIC regulators are supported. Note that
+the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
+number as described in RK805 datasheet.
+
+ - DCDC_REGn
+ - valid values for n are 1 to 4.
+ - LDO_REGn
+ - valid values for n are 1 to 3
+
Following regulators of the RK808 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK808 datasheet.
diff --git a/dts/Bindings/mfd/samsung,exynos5433-lpass.txt b/dts/Bindings/mfd/samsung,exynos5433-lpass.txt
index df664018c1..d759da606f 100644
--- a/dts/Bindings/mfd/samsung,exynos5433-lpass.txt
+++ b/dts/Bindings/mfd/samsung,exynos5433-lpass.txt
@@ -57,7 +57,6 @@ audio-subsystem {
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
- status = "disabled";
};
serial_3: serial@11460000 {
@@ -69,6 +68,5 @@ audio-subsystem {
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart_aud_bus>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/mfd/stm32-lptimer.txt b/dts/Bindings/mfd/stm32-lptimer.txt
new file mode 100644
index 0000000000..2a9ff29db9
--- /dev/null
+++ b/dts/Bindings/mfd/stm32-lptimer.txt
@@ -0,0 +1,48 @@
+STMicroelectronics STM32 Low-Power Timer
+
+The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
+functions:
+- PWM output (with programmable prescaler, configurable polarity)
+- Quadrature encoder, counter
+- Trigger source for STM32 ADC/DAC (LPTIM_OUT)
+
+Required properties:
+- compatible: Must be "st,stm32-lptimer".
+- reg: Offset and length of the device's register set.
+- clocks: Phandle to the clock used by the LP Timer module.
+- clock-names: Must be "mux".
+- #address-cells: Should be '<1>'.
+- #size-cells: Should be '<0>'.
+
+Optional subnodes:
+- pwm: See ../pwm/pwm-stm32-lp.txt
+- counter: See ../iio/timer/stm32-lptimer-cnt.txt
+- trigger: See ../iio/timer/stm32-lptimer-trigger.txt
+
+Example:
+
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x40002400 0x400>;
+ clocks = <&timer_clk>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lppwm1_pins>;
+ };
+
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lptim1_in_pins>;
+ };
+ };
diff --git a/dts/Bindings/mfd/tps6105x.txt b/dts/Bindings/mfd/tps6105x.txt
new file mode 100644
index 0000000000..93602c7a19
--- /dev/null
+++ b/dts/Bindings/mfd/tps6105x.txt
@@ -0,0 +1,17 @@
+* Device tree bindings for TI TPS61050/61052 Boost Converters
+
+The TP61050/TPS61052 is a high-power "white LED driver". The
+device provides LED, GPIO and regulator functionalities.
+
+Required properties:
+- compatible: "ti,tps61050" or "ti,tps61052"
+- reg: Specifies the I2C slave address
+
+Example:
+
+i2c0 {
+ tps61052@33 {
+ compatible = "ti,tps61052";
+ reg = <0x33>;
+ };
+};
diff --git a/dts/Bindings/mfd/wm831x.txt b/dts/Bindings/mfd/wm831x.txt
index 9f8b743067..505709403d 100644
--- a/dts/Bindings/mfd/wm831x.txt
+++ b/dts/Bindings/mfd/wm831x.txt
@@ -31,6 +31,7 @@ Required properties:
../interrupt-controller/interrupts.txt
Optional sub-nodes:
+ - phys : Contains a phandle to the USB PHY.
- regulators : Contains sub-nodes for each of the regulators supplied by
the device. The regulators are bound using their names listed below:
diff --git a/dts/Bindings/mfd/zii,rave-sp.txt b/dts/Bindings/mfd/zii,rave-sp.txt
new file mode 100644
index 0000000000..088eff9ddb
--- /dev/null
+++ b/dts/Bindings/mfd/zii,rave-sp.txt
@@ -0,0 +1,39 @@
+Zodiac Inflight Innovations RAVE Supervisory Processor
+
+RAVE Supervisory Processor communicates with SoC over UART. It is
+expected that its Device Tree node is specified as a child of a node
+corresponding to UART controller used for communication.
+
+Required parent device properties:
+
+ - compatible: Should be one of:
+ - "zii,rave-sp-niu"
+ - "zii,rave-sp-mezz"
+ - "zii,rave-sp-esb"
+ - "zii,rave-sp-rdu1"
+ - "zii,rave-sp-rdu2"
+
+ - current-speed: Should be set to baud rate SP device is using
+
+RAVE SP consists of the following sub-devices:
+
+Device Description
+------ -----------
+rave-sp-wdt : Watchdog
+rave-sp-nvmem : Interface to onborad EEPROM
+rave-sp-backlight : Display backlight
+rave-sp-hwmon : Interface to onboard hardware sensors
+rave-sp-leds : Interface to onboard LEDs
+rave-sp-input : Interface to onboard power button
+
+Example of usage:
+
+ rdu {
+ compatible = "zii,rave-sp-rdu2";
+ current-speed = <1000000>;
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ };
+ };
+
diff --git a/dts/Bindings/mips/lantiq/fpi-bus.txt b/dts/Bindings/mips/lantiq/fpi-bus.txt
new file mode 100644
index 0000000000..0a2df43383
--- /dev/null
+++ b/dts/Bindings/mips/lantiq/fpi-bus.txt
@@ -0,0 +1,31 @@
+Lantiq XWAY SoC FPI BUS binding
+============================
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200-fpi"
+- reg : The address and length of the XBAR
+ configuration register.
+ Address and length of the FPI bus itself.
+- lantiq,rcu : A phandle to the RCU syscon
+- lantiq,offset-endianness : Offset of the endianness configuration
+ register
+
+-------------------------------------------------------------------------------
+Example for the FPI on the xrx200 SoCs:
+ fpi@10000000 {
+ compatible = "lantiq,xrx200-fpi";
+ ranges = <0x0 0x10000000 0xf000000>;
+ reg = <0x1f400000 0x1000>,
+ <0x10000000 0xf000000>;
+ lantiq,rcu = <&rcu0>;
+ lantiq,offset-endianness = <0x4c>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gptu@e100a00 {
+ ......
+ };
+ };
diff --git a/dts/Bindings/mips/lantiq/rcu-gphy.txt b/dts/Bindings/mips/lantiq/rcu-gphy.txt
new file mode 100644
index 0000000000..a0c19bd1ce
--- /dev/null
+++ b/dts/Bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,36 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200a1x-gphy"
+ "lantiq,xrx200a2x-gphy"
+ "lantiq,xrx300-gphy"
+ "lantiq,xrx330-gphy"
+- reg : Addrress of the GPHY FW load address register
+- resets : Must reference the RCU GPHY reset bit
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
+- clocks : A reference to the (PMU) GPHY clock gate
+
+Optional properties:
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+ <dt-bindings/mips/lantiq_xway_gphy.h>
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
diff --git a/dts/Bindings/mips/lantiq/rcu.txt b/dts/Bindings/mips/lantiq/rcu.txt
new file mode 100644
index 0000000000..a086f1e1cd
--- /dev/null
+++ b/dts/Bindings/mips/lantiq/rcu.txt
@@ -0,0 +1,89 @@
+Lantiq XWAY SoC RCU binding
+===========================
+
+This binding describes the RCU (reset controller unit) multifunction device,
+where each sub-device has it's own set of registers.
+
+The RCU register range is used for multiple purposes. Mostly one device
+uses one or multiple register exclusively, but for some registers some
+bits are for one driver and some other bits are for a different driver.
+With this patch all accesses to the RCU registers will go through
+syscon.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : The first and second values must be:
+ "lantiq,xrx200-rcu", "simple-mfd", "syscon"
+- reg : The address and length of the system control registers
+
+
+-------------------------------------------------------------------------------
+Example of the RCU bindings on a xRX200 SoC:
+ rcu0: rcu@203000 {
+ compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
+ reg = <0x203000 0x100>;
+ ranges = <0x0 0x203000 0x100>;
+ big-endian;
+
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ gphy1: gphy@68 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x68 0x4>;
+
+ resets = <&reset0 29 28>, <&reset1 6 6>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ reset0: reset-controller@10 {
+ compatible = "lantiq,xrx200-reset";
+ reg = <0x10 4>, <0x14 4>;
+
+ #reset-cells = <2>;
+ };
+
+ reset1: reset-controller@48 {
+ compatible = "lantiq,xrx200-reset";
+ reg = <0x48 4>, <0x24 4>;
+
+ #reset-cells = <2>;
+ };
+
+ usb_phy0: usb2-phy@18 {
+ compatible = "lantiq,xrx200-usb2-phy";
+ reg = <0x18 4>, <0x38 4>;
+ status = "disabled";
+
+ resets = <&reset1 4 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: usb2-phy@34 {
+ compatible = "lantiq,xrx200-usb2-phy";
+ reg = <0x34 4>, <0x3C 4>;
+ status = "disabled";
+
+ resets = <&reset1 5 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ reboot@10 {
+ compatible = "syscon-reboot";
+ reg = <0x10 4>;
+
+ regmap = <&rcu0>;
+ offset = <0x10>;
+ mask = <0x40000000>;
+ };
+ };
diff --git a/dts/Bindings/mips/ni.txt b/dts/Bindings/mips/ni.txt
new file mode 100644
index 0000000000..722bf2d62d
--- /dev/null
+++ b/dts/Bindings/mips/ni.txt
@@ -0,0 +1,7 @@
+National Instruments MIPS platforms
+
+required root node properties:
+ - compatible: must be "ni,169445"
+
+CPU Nodes
+ - compatible: must be "mti,mips14KEc"
diff --git a/dts/Bindings/mips/ralink.txt b/dts/Bindings/mips/ralink.txt
index b35a8d04f8..a16e8d7fe5 100644
--- a/dts/Bindings/mips/ralink.txt
+++ b/dts/Bindings/mips/ralink.txt
@@ -15,3 +15,4 @@ value must be one of the following values:
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc
+ ralink,mt7628a-soc
diff --git a/dts/Bindings/misc/atmel-ssc.txt b/dts/Bindings/misc/atmel-ssc.txt
index f8629bb739..f9fb412642 100644
--- a/dts/Bindings/misc/atmel-ssc.txt
+++ b/dts/Bindings/misc/atmel-ssc.txt
@@ -47,5 +47,4 @@ ssc0: ssc@f0010000 {
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- status = "disabled";
};
diff --git a/dts/Bindings/mmc/arasan,sdhci.txt b/dts/Bindings/mmc/arasan,sdhci.txt
index 49df630bd4..60481bfc3d 100644
--- a/dts/Bindings/mmc/arasan,sdhci.txt
+++ b/dts/Bindings/mmc/arasan,sdhci.txt
@@ -74,5 +74,4 @@ Example:
phys = <&emmc_phy>;
phy-names = "phy_arasan";
#clock-cells = <0>;
- status = "disabled";
};
diff --git a/dts/Bindings/mmc/davinci_mmc.txt b/dts/Bindings/mmc/davinci_mmc.txt
index e5a0140b23..516fb0143d 100644
--- a/dts/Bindings/mmc/davinci_mmc.txt
+++ b/dts/Bindings/mmc/davinci_mmc.txt
@@ -24,7 +24,6 @@ mmc0: mmc@1c40000 {
compatible = "ti,da830-mmc",
reg = <0x40000 0x1000>;
interrupts = <16>;
- status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
dmas = <&edma 16
diff --git a/dts/Bindings/mmc/fsl-imx-mmc.txt b/dts/Bindings/mmc/fsl-imx-mmc.txt
index db442355cd..184ccffe27 100644
--- a/dts/Bindings/mmc/fsl-imx-mmc.txt
+++ b/dts/Bindings/mmc/fsl-imx-mmc.txt
@@ -20,5 +20,4 @@ sdhci1: sdhci@10014000 {
dma-names = "rx-tx";
bus-width = <4>;
cd-gpios = <&gpio3 29>;
- status = "okay";
};
diff --git a/dts/Bindings/mmc/mmc-card.txt b/dts/Bindings/mmc/mmc-card.txt
index a70fcd65b9..8d2d717589 100644
--- a/dts/Bindings/mmc/mmc-card.txt
+++ b/dts/Bindings/mmc/mmc-card.txt
@@ -21,7 +21,6 @@ Example:
vmmc-supply = <&reg_vcc3v3>;
bus-width = <8>;
non-removable;
- status = "okay";
mmccard: mmccard@0 {
reg = <0>;
diff --git a/dts/Bindings/mmc/mmc.txt b/dts/Bindings/mmc/mmc.txt
index c7f4a0ec48..b32ade645a 100644
--- a/dts/Bindings/mmc/mmc.txt
+++ b/dts/Bindings/mmc/mmc.txt
@@ -153,7 +153,6 @@ mmc3: mmc@01c12000 {
bus-width = <4>;
non-removable;
mmc-pwrseq = <&sdhci0_pwrseq>
- status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
diff --git a/dts/Bindings/mmc/orion-sdio.txt b/dts/Bindings/mmc/orion-sdio.txt
index 84f0ebd67a..10f0818a34 100644
--- a/dts/Bindings/mmc/orion-sdio.txt
+++ b/dts/Bindings/mmc/orion-sdio.txt
@@ -13,5 +13,4 @@ Example:
reg = <0xd00d4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
- status = "disabled";
};
diff --git a/dts/Bindings/mmc/renesas,mmcif.txt b/dts/Bindings/mmc/renesas,mmcif.txt
index c32dc5a9db..5ff1e12c65 100644
--- a/dts/Bindings/mmc/renesas,mmcif.txt
+++ b/dts/Bindings/mmc/renesas,mmcif.txt
@@ -11,6 +11,8 @@ Required properties:
- "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs
- "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
+ - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
+ - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
- "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs
- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
@@ -21,7 +23,7 @@ Required properties:
- interrupts: Some SoCs have only 1 shared interrupt, while others have either
2 or 3 individual interrupts (error, int, card detect). Below is the number
of interrupts for each SoC:
- 1: r8a73a4, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794
+ 1: r8a73a4, r8a7743, r8a7745, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794
2: r8a7740, sh73a0
3: r7s72100
diff --git a/dts/Bindings/mmc/rockchip-dw-mshc.txt b/dts/Bindings/mmc/rockchip-dw-mshc.txt
index 49ed3ad252..c6558785e6 100644
--- a/dts/Bindings/mmc/rockchip-dw-mshc.txt
+++ b/dts/Bindings/mmc/rockchip-dw-mshc.txt
@@ -15,6 +15,7 @@ Required Properties:
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
+ - "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322x
- "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
diff --git a/dts/Bindings/mmc/sdhci-st.txt b/dts/Bindings/mmc/sdhci-st.txt
index 230fd696eb..e356455983 100644
--- a/dts/Bindings/mmc/sdhci-st.txt
+++ b/dts/Bindings/mmc/sdhci-st.txt
@@ -63,7 +63,6 @@ Example:
mmc0: sdhci@fe81e000 {
compatible = "st,sdhci";
- status = "disabled";
reg = <0xfe81e000 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
interrupt-names = "mmcirq";
@@ -77,7 +76,6 @@ mmc0: sdhci@fe81e000 {
mmc1: sdhci@09080000 {
compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
reg = <0x09080000 0x7ff>;
reg-names = "mmc";
interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
@@ -94,7 +92,6 @@ mmc1: sdhci@09080000 {
mmc0: sdhci@09060000 {
compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
reg-names = "mmc", "top-mmc-delay";
interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
diff --git a/dts/Bindings/mmc/sunxi-mmc.txt b/dts/Bindings/mmc/sunxi-mmc.txt
index 7d53a799f1..63b57e2a10 100644
--- a/dts/Bindings/mmc/sunxi-mmc.txt
+++ b/dts/Bindings/mmc/sunxi-mmc.txt
@@ -12,6 +12,7 @@ Required properties:
* "allwinner,sun4i-a10-mmc"
* "allwinner,sun5i-a13-mmc"
* "allwinner,sun7i-a20-mmc"
+ * "allwinner,sun8i-a83t-emmc"
* "allwinner,sun9i-a80-mmc"
* "allwinner,sun50i-a64-emmc"
* "allwinner,sun50i-a64-mmc"
diff --git a/dts/Bindings/mmc/ti-omap-hsmmc.txt b/dts/Bindings/mmc/ti-omap-hsmmc.txt
index 0e026c151c..3a4ac401e6 100644
--- a/dts/Bindings/mmc/ti-omap-hsmmc.txt
+++ b/dts/Bindings/mmc/ti-omap-hsmmc.txt
@@ -1,33 +1,55 @@
-* TI Highspeed MMC host controller for OMAP
+* TI Highspeed MMC host controller for OMAP and 66AK2G family.
-The Highspeed MMC Host Controller on TI OMAP family
+The Highspeed MMC Host Controller on TI OMAP and 66AK2G family
provides an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the omap_hsmmc driver.
Required properties:
+--------------------
- compatible:
Should be "ti,omap2-hsmmc", for OMAP2 controllers
Should be "ti,omap3-hsmmc", for OMAP3 controllers
Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
Should be "ti,omap4-hsmmc", for OMAP4 controllers
Should be "ti,am33xx-hsmmc", for AM335x controllers
-- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
+ Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
+
+SoC specific required properties:
+---------------------------------
+The following are mandatory properties for OMAPs, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+ and an args specifier containing the MMC device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+- clocks: Must contain an entry for each entry in clock-names. Should
+ be defined as per the he appropriate clock bindings consumer
+ usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+- clock-names: Shall be "fck" for the functional clock,
+ and "mmchsdb_fck" for the debounce clock.
+
Optional properties:
-ti,dual-volt: boolean, supports dual voltage cards
-<supply-name>-supply: phandle to the regulator device tree node
-"supply-name" examples are "vmmc", "vmmc_aux"(deprecated)/"vqmmc" etc
-ti,non-removable: non-removable slot (like eMMC)
-ti,needs-special-reset: Requires a special softreset sequence
-ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
-dmas: List of DMA specifiers with the controller specific format
-as described in the generic DMA client binding. A tx and rx
-specifier is required.
-dma-names: List of DMA request names. These strings correspond
-1:1 with the DMA specifiers listed in dmas. The string naming is
-to be "rx" and "tx" for RX and TX DMA requests, respectively.
+--------------------
+- ti,dual-volt: boolean, supports dual voltage cards
+- <supply-name>-supply: phandle to the regulator device tree node
+ "supply-name" examples are "vmmc",
+ "vmmc_aux"(deprecated)/"vqmmc" etc
+- ti,non-removable: non-removable slot (like eMMC)
+- ti,needs-special-reset: Requires a special softreset sequence
+- ti,needs-special-hs-handling: HSMMC IP needs special setting
+ for handling High Speed
+- dmas: List of DMA specifiers with the controller specific
+ format as described in the generic DMA client
+ binding. A tx and rx specifier is required.
+- dma-names: List of DMA request names. These strings correspond
+ 1:1 with the DMA specifiers listed in dmas.
+ The string naming is to be "rx" and "tx" for
+ RX and TX DMA requests, respectively.
Examples:
diff --git a/dts/Bindings/mmc/tmio_mmc.txt b/dts/Bindings/mmc/tmio_mmc.txt
index 4fd8b7acc5..54ef642f23 100644
--- a/dts/Bindings/mmc/tmio_mmc.txt
+++ b/dts/Bindings/mmc/tmio_mmc.txt
@@ -15,6 +15,8 @@ Required properties:
"renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
+ "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
+ "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
@@ -33,10 +35,8 @@ Required properties:
If 2 clocks are specified by the hardware, you must name them as
"core" and "cd". If the controller only has 1 clock, naming is not
required.
- Below is the number clocks for each supported SoC:
- 1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790
- R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
- 2: R7S72100
+ Devices which have more than 1 clock are listed below:
+ 2: R7S72100
Optional properties:
- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
diff --git a/dts/Bindings/mmc/zx-dw-mshc.txt b/dts/Bindings/mmc/zx-dw-mshc.txt
index 906819a90c..0f59bd5361 100644
--- a/dts/Bindings/mmc/zx-dw-mshc.txt
+++ b/dts/Bindings/mmc/zx-dw-mshc.txt
@@ -28,5 +28,4 @@ Example:
max-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
- status = "disabled";
};
diff --git a/dts/Bindings/mtd/atmel-quadspi.txt b/dts/Bindings/mtd/atmel-quadspi.txt
index 489807005e..b93c1e2f25 100644
--- a/dts/Bindings/mtd/atmel-quadspi.txt
+++ b/dts/Bindings/mtd/atmel-quadspi.txt
@@ -24,7 +24,6 @@ spi@f0020000 {
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
- status = "okay";
m25p80@0 {
...
diff --git a/dts/Bindings/mtd/mtk-quadspi.txt b/dts/Bindings/mtd/mtk-quadspi.txt
index 5ded66ad7a..840f9405dc 100644
--- a/dts/Bindings/mtd/mtk-quadspi.txt
+++ b/dts/Bindings/mtd/mtk-quadspi.txt
@@ -37,7 +37,6 @@ nor_flash: spi@1100d000 {
clock-names = "spi", "sf";
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
diff --git a/dts/Bindings/mtd/qcom_nandc.txt b/dts/Bindings/mtd/qcom_nandc.txt
index 70dd5118a3..73d336befa 100644
--- a/dts/Bindings/mtd/qcom_nandc.txt
+++ b/dts/Bindings/mtd/qcom_nandc.txt
@@ -1,11 +1,20 @@
* Qualcomm NAND controller
Required properties:
-- compatible: should be "qcom,ipq806x-nand"
+- compatible: must be one of the following:
+ * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
+ SoC and it uses ADM DMA
+ * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
+ IPQ4019 SoC and it uses BAM DMA
+ * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
+ IPQ8074 SoC and it uses BAM DMA
+
- reg: MMIO address range
- clocks: must contain core clock and always on clock
- clock-names: must contain "core" for the core clock and "aon" for the
always on clock
+
+EBI2 specific properties:
- dmas: DMA specifier, consisting of a phandle to the ADM DMA
controller node and the channel number to be used for
NAND. Refer to dma.txt and qcom_adm.txt for more details
@@ -16,6 +25,12 @@ Required properties:
- qcom,data-crci: must contain the ADM data type CRCI block instance
number specified for the NAND controller on the given
platform
+
+QPIC specific properties:
+- dmas: DMA specifier, consisting of a phandle to the BAM DMA
+ and the channel number to be used for NAND. Refer to
+ dma.txt, qcom_bam_dma.txt for more details
+- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
- #address-cells: <1> - subnodes give the chip-select number
- #size-cells: <0>
@@ -26,7 +41,6 @@ chip-selects which (may) contain NAND flash chips. Their properties are as
follows.
Required properties:
-- compatible: should contain "qcom,nandcs"
- reg: a single integer representing the chip-select
number (e.g., 0, 1, 2, etc.)
- #address-cells: see partition.txt
@@ -43,8 +57,8 @@ partition.txt for more detail.
Example:
-nand@1ac00000 {
- compatible = "qcom,ebi2-nandc";
+nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
clocks = <&gcc EBI2_CLK>,
@@ -59,8 +73,7 @@ nand@1ac00000 {
#address-cells = <1>;
#size-cells = <0>;
- nandcs@0 {
- compatible = "qcom,nandcs";
+ nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
@@ -84,3 +97,43 @@ nand@1ac00000 {
};
};
};
+
+nand-controller@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpicbam 0>,
+ <&qpicbam 1>,
+ <&qpicbam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/mtd/st-fsm.txt b/dts/Bindings/mtd/st-fsm.txt
index c2489391c4..54cef9ef30 100644
--- a/dts/Bindings/mtd/st-fsm.txt
+++ b/dts/Bindings/mtd/st-fsm.txt
@@ -21,6 +21,5 @@ Example:
st,syscfg = <&syscfg_rear>;
st,boot-device-reg = <0x958>;
st,boot-device-spi = <0x1a>;
- status = "okay";
};
diff --git a/dts/Bindings/mtd/sunxi-nand.txt b/dts/Bindings/mtd/sunxi-nand.txt
index f322f56aef..a37c67bcb4 100644
--- a/dts/Bindings/mtd/sunxi-nand.txt
+++ b/dts/Bindings/mtd/sunxi-nand.txt
@@ -41,7 +41,6 @@ nfc: nand@01c03000 {
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
- status = "okay";
nand@0 {
reg = <0>;
diff --git a/dts/Bindings/net/anarion-gmac.txt b/dts/Bindings/net/anarion-gmac.txt
new file mode 100644
index 0000000000..fe678965ae
--- /dev/null
+++ b/dts/Bindings/net/anarion-gmac.txt
@@ -0,0 +1,25 @@
+* Adaptrum Anarion ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+ - compatible: Should be "adaptrum,anarion-gmac", "snps,dwmac"
+ - phy-mode: Should be "rgmii". Other modes are not currently supported.
+
+
+Examples:
+
+ gmac1: ethernet@f2014000 {
+ compatible = "adaptrum,anarion-gmac", "snps,dwmac";
+ reg = <0xf2014000 0x4000>, <0xf2018100 8>;
+
+ interrupt-parent = <&core_intc>;
+ interrupts = <21>;
+ interrupt-names = "macirq";
+
+ clocks = <&core_clk>;
+ clock-names = "stmmaceth";
+
+ phy-mode = "rgmii";
+ };
diff --git a/dts/Bindings/net/brcm,amac.txt b/dts/Bindings/net/brcm,amac.txt
index ad16c1f481..0bfad656a9 100644
--- a/dts/Bindings/net/brcm,amac.txt
+++ b/dts/Bindings/net/brcm,amac.txt
@@ -27,5 +27,4 @@ amac0: ethernet@18022000 {
<0x18110000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
};
diff --git a/dts/Bindings/net/broadcom-bluetooth.txt b/dts/Bindings/net/broadcom-bluetooth.txt
new file mode 100644
index 0000000000..4194ff7e6e
--- /dev/null
+++ b/dts/Bindings/net/broadcom-bluetooth.txt
@@ -0,0 +1,35 @@
+Broadcom Bluetooth Chips
+---------------------
+
+This documents the binding structure and common properties for serial
+attached Broadcom devices.
+
+Serial attached Broadcom devices shall be a child node of the host UART
+device the slave device is attached to.
+
+Required properties:
+
+ - compatible: should contain one of the following:
+ * "brcm,bcm43438-bt"
+
+Optional properties:
+
+ - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt
+ - shutdown-gpios: GPIO specifier, used to enable the BT module
+ - device-wakeup-gpios: GPIO specifier, used to wakeup the controller
+ - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor
+ - clocks: clock specifier if external clock provided to the controller
+ - clock-names: should be "extclk"
+
+
+Example:
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <921600>;
+ };
+};
diff --git a/dts/Bindings/net/btusb.txt b/dts/Bindings/net/btusb.txt
index 01fa2d4188..9c5e663fa1 100644
--- a/dts/Bindings/net/btusb.txt
+++ b/dts/Bindings/net/btusb.txt
@@ -29,7 +29,6 @@ Example:
Following example uses irq pin number 3 of gpio0 for out of band wake-on-bt:
&usb_host1_ehci {
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/net/can/c_can.txt b/dts/Bindings/net/can/c_can.txt
index 5a1d8b0c39..2d504256b0 100644
--- a/dts/Bindings/net/can/c_can.txt
+++ b/dts/Bindings/net/can/c_can.txt
@@ -11,9 +11,20 @@ Required properties:
- interrupts : property with a value describing the interrupt
number
-Optional properties:
+The following are mandatory properties for DRA7x, AM33xx and AM43xx SoCs only:
- ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the
instance number
+
+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
+- power-domains : Should contain a phandle to a PM domain provider node
+ and an args specifier containing the DCAN device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+- clocks : CAN functional clock phandle. This property is as per the
+ binding,
+ Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+
+Optional properties:
- syscon-raminit : Handle to system control region that contains the
RAMINIT register, register offset to the RAMINIT
register and the CAN instance number (0 offset).
diff --git a/dts/Bindings/net/can/m_can.txt b/dts/Bindings/net/can/m_can.txt
index 9e331777c2..78138333ff 100644
--- a/dts/Bindings/net/can/m_can.txt
+++ b/dts/Bindings/net/can/m_can.txt
@@ -56,7 +56,6 @@ m_can1: can@020e8000 {
<&clks IMX6SX_CLK_CANFD>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
- status = "disabled";
};
Board dts:
diff --git a/dts/Bindings/net/dsa/ksz.txt b/dts/Bindings/net/dsa/ksz.txt
index 0ab8b39d0b..fd23904ac6 100644
--- a/dts/Bindings/net/dsa/ksz.txt
+++ b/dts/Bindings/net/dsa/ksz.txt
@@ -24,7 +24,6 @@ Ethernet switch connected via SPI to the host, CPU port wired to eth0:
pinctrl-0 = <&pinctrl_spi_ksz>;
cs-gpios = <&pioC 25 0>;
id = <1>;
- status = "okay";
ksz9477: ksz9477@0 {
compatible = "microchip,ksz9477";
@@ -34,7 +33,6 @@ Ethernet switch connected via SPI to the host, CPU port wired to eth0:
spi-cpha;
spi-cpol;
- status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/net/dsa/lan9303.txt b/dts/Bindings/net/dsa/lan9303.txt
index 04f2965a44..4448d063dd 100644
--- a/dts/Bindings/net/dsa/lan9303.txt
+++ b/dts/Bindings/net/dsa/lan9303.txt
@@ -27,7 +27,6 @@ Example:
I2C managed mode:
master: masterdevice@X {
- status = "okay";
fixed-link { /* RMII fixed link to LAN9303 */
speed = <100>;
@@ -38,7 +37,6 @@ I2C managed mode:
switch: switch@a {
compatible = "smsc,lan9303-i2c";
reg = <0xa>;
- status = "okay";
reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
reset-duration = <200>;
@@ -67,7 +65,6 @@ I2C managed mode:
MDIO managed mode:
master: masterdevice@X {
- status = "okay";
phy-handle = <&switch>;
mdio {
diff --git a/dts/Bindings/net/ethernet.txt b/dts/Bindings/net/ethernet.txt
index 7da86f22a1..2974e63ba3 100644
--- a/dts/Bindings/net/ethernet.txt
+++ b/dts/Bindings/net/ethernet.txt
@@ -1,5 +1,9 @@
The following properties are common to the Ethernet controllers:
+NOTE: All 'phy*' properties documented below are Ethernet specific. For the
+generic PHY 'phys' property, see
+Documentation/devicetree/bindings/phy/phy-bindings.txt.
+
- local-mac-address: array of 6 bytes, specifies the MAC address that was
assigned to the network device;
- mac-address: array of 6 bytes, specifies the MAC address that was last used by
diff --git a/dts/Bindings/net/ftgmac100.txt b/dts/Bindings/net/ftgmac100.txt
index c1ce168024..72e7aaf724 100644
--- a/dts/Bindings/net/ftgmac100.txt
+++ b/dts/Bindings/net/ftgmac100.txt
@@ -30,6 +30,5 @@ Example:
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
- status = "okay";
use-ncsi;
};
diff --git a/dts/Bindings/net/marvell-armada-370-neta.txt b/dts/Bindings/net/marvell-armada-370-neta.txt
index ae4234ca4e..bedcfd5a52 100644
--- a/dts/Bindings/net/marvell-armada-370-neta.txt
+++ b/dts/Bindings/net/marvell-armada-370-neta.txt
@@ -41,7 +41,6 @@ ethernet@70000 {
interrupts = <8>;
clocks = <&gate_clk 4>;
tx-csum-limit = <9800>
- status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
buffer-manager = <&bm>;
diff --git a/dts/Bindings/net/marvell-bt-8xxx.txt b/dts/Bindings/net/marvell-bt-8xxx.txt
index 9be1059ff0..3d27c68613 100644
--- a/dts/Bindings/net/marvell-bt-8xxx.txt
+++ b/dts/Bindings/net/marvell-bt-8xxx.txt
@@ -44,7 +44,6 @@ Example for SDIO device follows (calibration data is also available in
below example).
&mmc3 {
- status = "okay";
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
cap-power-off-card;
@@ -70,7 +69,6 @@ below example).
Example for USB device:
&usb_host1_ohci {
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/net/marvell-neta-bm.txt b/dts/Bindings/net/marvell-neta-bm.txt
index c1b1d7c3bd..07b31050db 100644
--- a/dts/Bindings/net/marvell-neta-bm.txt
+++ b/dts/Bindings/net/marvell-neta-bm.txt
@@ -31,7 +31,6 @@ bm: bm@c8000 {
reg = <0xc8000 0xac>;
clocks = <&gateclk 13>;
internal-mem = <&bm_bppi>;
- status = "okay";
pool2,capacity = <4096>;
pool1,pkt-size = <512>;
};
@@ -45,5 +44,4 @@ bm_bppi: bm-bppi {
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gateclk 13>;
- status = "okay";
};
diff --git a/dts/Bindings/net/marvell-pp2.txt b/dts/Bindings/net/marvell-pp2.txt
index 6b4956beff..7e2dad08a1 100644
--- a/dts/Bindings/net/marvell-pp2.txt
+++ b/dts/Bindings/net/marvell-pp2.txt
@@ -41,6 +41,11 @@ Optional properties (port):
- marvell,loopback: port is loopback mode
- phy: a phandle to a phy node defining the PHY address (as the reg
property, a single integer).
+- interrupt-names: if more than a single interrupt for rx is given, must
+ be the name associated to the interrupts listed. Valid
+ names are: "tx-cpu0", "tx-cpu1", "tx-cpu2", "tx-cpu3",
+ "rx-shared", "link".
+- marvell,system-controller: a phandle to the system controller.
Example for marvell,armada-375-pp2:
@@ -52,12 +57,10 @@ ethernet@f0000 {
<0xc5000 0x100>;
clocks = <&gateclk 3>, <&gateclk 19>;
clock-names = "pp_clk", "gop_clk";
- status = "okay";
eth0: eth0@c4000 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
- status = "okay";
phy = <&phy0>;
phy-mode = "gmii";
};
@@ -65,7 +68,6 @@ ethernet@f0000 {
eth1: eth1@c5000 {
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
- status = "okay";
phy = <&phy3>;
phy-mode = "gmii";
};
@@ -80,19 +82,37 @@ cpm_ethernet: ethernet@0 {
clock-names = "pp_clk", "gop_clk", "gp_clk";
eth0: eth0 {
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <0>;
gop-port-id = <0>;
};
eth1: eth1 {
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <1>;
gop-port-id = <2>;
};
eth2: eth2 {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <2>;
gop-port-id = <3>;
};
diff --git a/dts/Bindings/net/mediatek-net.txt b/dts/Bindings/net/mediatek-net.txt
index c7194e87d5..214eaa9a66 100644
--- a/dts/Bindings/net/mediatek-net.txt
+++ b/dts/Bindings/net/mediatek-net.txt
@@ -7,24 +7,32 @@ have dual GMAC each represented by a child node..
* Ethernet controller node
Required properties:
-- compatible: Should be "mediatek,mt2701-eth"
+- compatible: Should be
+ "mediatek,mt2701-eth": for MT2701 SoC
+ "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
+ "mediatek,mt7622-eth": for MT7622 SoC
- reg: Address and length of the register set for the device
- interrupts: Should contain the three frame engines interrupts in numeric
order. These are fe_int0, fe_int1 and fe_int2.
- clocks: the clock used by the core
- clock-names: the names of the clock listed in the clocks property. These are
- "ethif", "esw", "gp2", "gp1"
+ "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC
+ "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
+ "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
- power-domains: phandle to the power domain that the ethernet is part of
-- resets: Should contain a phandle to the ethsys reset signal
-- reset-names: Should contain the reset signal name "eth"
+- resets: Should contain phandles to the ethsys reset signals
+- reset-names: Should contain the names of reset signal listed in the resets
+ property
+ These are "fe", "gmac" and "ppe"
- mediatek,ethsys: phandle to the syscon node that handles the port setup
+- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
+ which is required for those SoCs equipped with SGMII such as MT7622 SoC.
- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
and driver current
Optional properties:
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
-
* Ethernet MAC node
Required properties:
diff --git a/dts/Bindings/net/meson-dwmac.txt b/dts/Bindings/net/meson-dwmac.txt
index 0703ad3f3c..354dd9896b 100644
--- a/dts/Bindings/net/meson-dwmac.txt
+++ b/dts/Bindings/net/meson-dwmac.txt
@@ -66,5 +66,4 @@ Example for GXBB:
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
phy-mode = "rgmii";
- status = "disabled";
};
diff --git a/dts/Bindings/net/micrel-ksz90x1.txt b/dts/Bindings/net/micrel-ksz90x1.txt
index c35b5b428a..42a2483016 100644
--- a/dts/Bindings/net/micrel-ksz90x1.txt
+++ b/dts/Bindings/net/micrel-ksz90x1.txt
@@ -69,7 +69,6 @@ Examples:
};
};
ethernet@70000 {
- status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
diff --git a/dts/Bindings/net/microchip,enc28j60.txt b/dts/Bindings/net/microchip,enc28j60.txt
index 1dc3bc7553..44dff53d4d 100644
--- a/dts/Bindings/net/microchip,enc28j60.txt
+++ b/dts/Bindings/net/microchip,enc28j60.txt
@@ -33,7 +33,6 @@ Example (for NXP i.MX28 with pin control stuff for GPIO irq):
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>;
- status = "okay";
enc28j60: ethernet@0 {
compatible = "microchip,enc28j60";
diff --git a/dts/Bindings/net/nfc/nfcmrvl.txt b/dts/Bindings/net/nfc/nfcmrvl.txt
index 76df917382..c9b35251bb 100644
--- a/dts/Bindings/net/nfc/nfcmrvl.txt
+++ b/dts/Bindings/net/nfc/nfcmrvl.txt
@@ -25,7 +25,6 @@ Optional I2C-based chip specific properties:
Example (for ARM-based BeagleBoard Black with 88W8887 on UART5):
&uart5 {
- status = "okay";
nfcmrvluart: nfcmrvluart@5 {
compatible = "marvell,nfc-uart";
@@ -41,7 +40,6 @@ Example (for ARM-based BeagleBoard Black with 88W8887 on UART5):
Example (for ARM-based BeagleBoard Black with 88W8887 on I2C1):
&i2c1 {
- status = "okay";
clock-frequency = <400000>;
nfcmrvli2c0: i2c@1 {
diff --git a/dts/Bindings/net/nfc/nxp-nci.txt b/dts/Bindings/net/nfc/nxp-nci.txt
index 5b6cd9b3f6..92486733df 100644
--- a/dts/Bindings/net/nfc/nxp-nci.txt
+++ b/dts/Bindings/net/nfc/nxp-nci.txt
@@ -17,7 +17,6 @@ Example (for ARM-based BeagleBone with NPC100 NFC controller on I2C2):
&i2c2 {
- status = "okay";
npc100: npc100@29 {
diff --git a/dts/Bindings/net/nfc/pn533-i2c.txt b/dts/Bindings/net/nfc/pn533-i2c.txt
index 1aea822d45..122460e42e 100644
--- a/dts/Bindings/net/nfc/pn533-i2c.txt
+++ b/dts/Bindings/net/nfc/pn533-i2c.txt
@@ -15,7 +15,6 @@ Example (for ARM-based BeagleBone with PN532 on I2C2):
&i2c2 {
- status = "okay";
pn532: pn532@24 {
diff --git a/dts/Bindings/net/nfc/pn544.txt b/dts/Bindings/net/nfc/pn544.txt
index dab69f3616..538a86f7b2 100644
--- a/dts/Bindings/net/nfc/pn544.txt
+++ b/dts/Bindings/net/nfc/pn544.txt
@@ -17,7 +17,6 @@ Example (for ARM-based BeagleBone with PN544 on I2C2):
&i2c2 {
- status = "okay";
pn544: pn544@28 {
diff --git a/dts/Bindings/net/nfc/s3fwrn5.txt b/dts/Bindings/net/nfc/s3fwrn5.txt
index fb1e75facf..ed5b3eaadb 100644
--- a/dts/Bindings/net/nfc/s3fwrn5.txt
+++ b/dts/Bindings/net/nfc/s3fwrn5.txt
@@ -12,7 +12,6 @@ Required properties:
Example:
&hsi2c_4 {
- status = "okay";
s3fwrn5@27 {
compatible = "samsung,s3fwrn5-i2c";
diff --git a/dts/Bindings/net/nfc/st-nci-i2c.txt b/dts/Bindings/net/nfc/st-nci-i2c.txt
index 263732e887..b46d473be4 100644
--- a/dts/Bindings/net/nfc/st-nci-i2c.txt
+++ b/dts/Bindings/net/nfc/st-nci-i2c.txt
@@ -20,7 +20,6 @@ Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2):
&i2c2 {
- status = "okay";
st21nfcb: st21nfcb@8 {
diff --git a/dts/Bindings/net/nfc/st-nci-spi.txt b/dts/Bindings/net/nfc/st-nci-spi.txt
index 711ca85a36..54ce8e7ac6 100644
--- a/dts/Bindings/net/nfc/st-nci-spi.txt
+++ b/dts/Bindings/net/nfc/st-nci-spi.txt
@@ -19,7 +19,6 @@ Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4):
&mcspi4 {
- status = "okay";
st21nfcb: st21nfcb@0 {
diff --git a/dts/Bindings/net/nfc/st21nfca.txt b/dts/Bindings/net/nfc/st21nfca.txt
index 7bb2e213d6..5ee9440fa9 100644
--- a/dts/Bindings/net/nfc/st21nfca.txt
+++ b/dts/Bindings/net/nfc/st21nfca.txt
@@ -20,7 +20,6 @@ Example (for ARM-based BeagleBoard xM with ST21NFCA on I2C2):
&i2c2 {
- status = "okay";
st21nfca: st21nfca@1 {
diff --git a/dts/Bindings/net/nfc/st95hf.txt b/dts/Bindings/net/nfc/st95hf.txt
index ea3178bc9d..08a202e00d 100644
--- a/dts/Bindings/net/nfc/st95hf.txt
+++ b/dts/Bindings/net/nfc/st95hf.txt
@@ -35,12 +35,10 @@ spi@9840000 {
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <&pio0 4>;
- status = "okay";
st95hf@0{
reg = <0>;
compatible = "st,st95hf";
- status = "okay";
spi-max-frequency = <1000000>;
enable-gpio = <&pio4 0>;
interrupt-parent = <&pio0>;
diff --git a/dts/Bindings/net/nfc/trf7970a.txt b/dts/Bindings/net/nfc/trf7970a.txt
index 60c833d621..5ca9362ef1 100644
--- a/dts/Bindings/net/nfc/trf7970a.txt
+++ b/dts/Bindings/net/nfc/trf7970a.txt
@@ -23,7 +23,6 @@ Optional SoC Specific Properties:
Example (for ARM-based BeagleBone with TRF7970A on SPI1):
&spi1 {
- status = "okay";
nfc@0 {
compatible = "ti,trf7970a";
@@ -41,6 +40,5 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1):
irq-status-read-quirk;
en2-rf-quirk;
clock-frequency = <27120000>;
- status = "okay";
};
};
diff --git a/dts/Bindings/net/oxnas-dwmac.txt b/dts/Bindings/net/oxnas-dwmac.txt
index df0534e2ed..d7117a22fd 100644
--- a/dts/Bindings/net/oxnas-dwmac.txt
+++ b/dts/Bindings/net/oxnas-dwmac.txt
@@ -35,5 +35,4 @@ etha: ethernet@40400000 {
/* Regmap for sys registers */
oxsemi,sys-ctrl = <&sys>;
- status = "disabled";
};
diff --git a/dts/Bindings/net/phy.txt b/dts/Bindings/net/phy.txt
index b55857696f..77d0b2a61f 100644
--- a/dts/Bindings/net/phy.txt
+++ b/dts/Bindings/net/phy.txt
@@ -2,11 +2,7 @@ PHY nodes
Required properties:
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
+ - interrupts : interrupt specifier for the sole interrupt.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
- reg : The ID number for the phy, usually a small integer
@@ -52,11 +48,16 @@ Optional Properties:
Mark the corresponding energy efficient ethernet mode as broken and
request the ethernet to stop advertising it.
+- phy-is-integrated: If set, indicates that the PHY is integrated into the same
+ physical package as the Ethernet MAC. If needed, muxers should be configured
+ to ensure the integrated PHY is used. The absence of this property indicates
+ the muxers should be configured so that the external PHY is used.
+
Example:
ethernet-phy@0 {
compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <40000>;
- interrupts = <35 1>;
+ interrupt-parent = <&PIC>;
+ interrupts = <35 IRQ_TYPE_EDGE_RISING>;
reg = <0>;
};
diff --git a/dts/Bindings/net/qca,qca7000.txt b/dts/Bindings/net/qca,qca7000.txt
index 6d9efb2eb9..3987846b3f 100644
--- a/dts/Bindings/net/qca,qca7000.txt
+++ b/dts/Bindings/net/qca,qca7000.txt
@@ -41,7 +41,6 @@ ssp2: spi@80014000 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
qca7000: ethernet@0 {
compatible = "qca,qca7000";
@@ -78,7 +77,6 @@ auart0: serial@8006a000 {
reg = <0x8006a000 0x2000>;
pinctrl-names = "default";
pinctrl-0 = <&auart0_2pins_a>;
- status = "okay";
qca7000: ethernet {
compatible = "qca,qca7000";
diff --git a/dts/Bindings/net/renesas,ravb.txt b/dts/Bindings/net/renesas,ravb.txt
index b519503be5..16723535e1 100644
--- a/dts/Bindings/net/renesas,ravb.txt
+++ b/dts/Bindings/net/renesas,ravb.txt
@@ -4,19 +4,25 @@ This file provides information on what the device node for the Ethernet AVB
interface contains.
Required properties:
-- compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC.
- "renesas,etheravb-r8a7791" if the device is a part of R8A7791 SoC.
- "renesas,etheravb-r8a7792" if the device is a part of R8A7792 SoC.
- "renesas,etheravb-r8a7793" if the device is a part of R8A7793 SoC.
- "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC.
- "renesas,etheravb-r8a7795" if the device is a part of R8A7795 SoC.
- "renesas,etheravb-r8a7796" if the device is a part of R8A7796 SoC.
- "renesas,etheravb-rcar-gen2" for generic R-Car Gen 2 compatible interface.
- "renesas,etheravb-rcar-gen3" for generic R-Car Gen 3 compatible interface.
+- compatible: Must contain one or more of the following:
+ - "renesas,etheravb-r8a7743" for the R8A7743 SoC.
+ - "renesas,etheravb-r8a7745" for the R8A7745 SoC.
+ - "renesas,etheravb-r8a7790" for the R8A7790 SoC.
+ - "renesas,etheravb-r8a7791" for the R8A7791 SoC.
+ - "renesas,etheravb-r8a7792" for the R8A7792 SoC.
+ - "renesas,etheravb-r8a7793" for the R8A7793 SoC.
+ - "renesas,etheravb-r8a7794" for the R8A7794 SoC.
+ - "renesas,etheravb-rcar-gen2" as a fallback for the above
+ R-Car Gen2 and RZ/G1 devices.
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
+ - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
+ - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
+ - "renesas,etheravb-rcar-gen3" as a fallback for the above
+ R-Car Gen3 devices.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first followed by
+ the generic version.
- reg: offset and length of (1) the register block and (2) the stream buffer.
- interrupts: A list of interrupt-specifiers, one for each entry in
diff --git a/dts/Bindings/net/rockchip-dwmac.txt b/dts/Bindings/net/rockchip-dwmac.txt
index 8f42755072..6af8eed1ad 100644
--- a/dts/Bindings/net/rockchip-dwmac.txt
+++ b/dts/Bindings/net/rockchip-dwmac.txt
@@ -10,6 +10,7 @@ Required properties:
"rockchip,rk3366-gmac": found on RK3366 SoCs
"rockchip,rk3368-gmac": found on RK3368 SoCs
"rockchip,rk3399-gmac": found on RK3399 SoCs
+ "rockchip,rv1108-gmac": found on RV1108 SoCs
- reg: addresses and length of the register sets for the device.
- interrupts: Should contain the GMAC interrupts.
- interrupt-names: Should contain the interrupt names "macirq".
@@ -70,5 +71,4 @@ gmac: ethernet@ff290000 {
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
};
diff --git a/dts/Bindings/net/sff,sfp.txt b/dts/Bindings/net/sff,sfp.txt
new file mode 100644
index 0000000000..60e970ce10
--- /dev/null
+++ b/dts/Bindings/net/sff,sfp.txt
@@ -0,0 +1,76 @@
+Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
+Transceiver
+
+Required properties:
+
+- compatible : must be "sff,sfp"
+
+Optional Properties:
+
+- i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
+ interface
+
+- mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
+ module presence input gpio signal, active (module absent) high
+
+- los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
+ Indication input gpio signal, active (signal lost) high
+
+- tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
+ Fault input gpio signal, active (fault condition) high
+
+- tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
+ output gpio signal, active (Tx disable) high
+
+- rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate
+ Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate
+
+- rate-select1-gpios : GPIO phandle and a specifier of the Tx Signaling Rate
+ Select (AKA RS1) output gpio signal (SFP+ only), low: low Tx rate, high:
+ high Tx rate
+
+Example #1: Direct serdes to SFP connection
+
+sfp_eth3: sfp-eth3 {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_1g_i2c>;
+ los-gpios = <&cpm_gpio2 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&cpm_gpio2 21 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sfp_1g_pins &cps_sfp_1g_pins>;
+ tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&cpm_gpio2 19 GPIO_ACTIVE_HIGH>;
+};
+
+&cps_emac3 {
+ phy-names = "comphy";
+ phys = <&cps_comphy5 0>;
+ sfp = <&sfp_eth3>;
+};
+
+Example #2: Serdes to PHY to SFP connection
+
+sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfpp0_i2c>;
+ los-gpios = <&cps_gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&cps_gpio1 27 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cps_sfpp0_pins>;
+ tx-disable-gpios = <&cps_gpio1 29 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>;
+};
+
+p0_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_phy0_pins &cps_phy0_pins>;
+ reg = <0>;
+ interrupt = <&cpm_gpio2 18 IRQ_TYPE_EDGE_FALLING>;
+ sfp = <&sfp_eth0>;
+};
+
+&cpm_eth0 {
+ phy = <&p0_phy>;
+ phy-mode = "10gbase-kr";
+};
diff --git a/dts/Bindings/net/smsc-lan87xx.txt b/dts/Bindings/net/smsc-lan87xx.txt
index 974edd5c85..8b7c719b0b 100644
--- a/dts/Bindings/net/smsc-lan87xx.txt
+++ b/dts/Bindings/net/smsc-lan87xx.txt
@@ -15,7 +15,6 @@ smsc phy with disabled energy detect mode on an am335x based board.
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
ethernetphy0: ethernet-phy@0 {
reg = <0>;
diff --git a/dts/Bindings/net/socfpga-dwmac.txt b/dts/Bindings/net/socfpga-dwmac.txt
index 2e68a3cd85..b30d04b54e 100644
--- a/dts/Bindings/net/socfpga-dwmac.txt
+++ b/dts/Bindings/net/socfpga-dwmac.txt
@@ -40,7 +40,6 @@ gmii_to_sgmii_converter: phy@0x100000240 {
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
- status = "disabled";
reg = <0xff700000 0x2000>;
interrupts = <0 115 4>;
interrupt-names = "macirq";
diff --git a/dts/Bindings/net/sti-dwmac.txt b/dts/Bindings/net/sti-dwmac.txt
index d05c1e1fd9..062c5174ad 100644
--- a/dts/Bindings/net/sti-dwmac.txt
+++ b/dts/Bindings/net/sti-dwmac.txt
@@ -34,7 +34,6 @@ Example:
ethernet0: dwmac@9630000 {
device_type = "network";
- status = "disabled";
compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
reg = <0x9630000 0x8000>;
reg-names = "stmmaceth";
diff --git a/dts/Bindings/net/stm32-dwmac.txt b/dts/Bindings/net/stm32-dwmac.txt
index c35afb7e95..489dbcb66c 100644
--- a/dts/Bindings/net/stm32-dwmac.txt
+++ b/dts/Bindings/net/stm32-dwmac.txt
@@ -18,7 +18,6 @@ Example:
ethernet@40028000 {
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
- status = "disabled";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
interrupts = <0 61 0>, <0 62 0>;
diff --git a/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt b/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
index 590f622188..b2bd4704f8 100644
--- a/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
+++ b/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
@@ -29,7 +29,6 @@ mmc3: mmc@01c12000 {
vmmc-supply = <&reg_vmmc3>;
bus-width = <4>;
non-removable;
- status = "okay";
brcmf: wifi@1 {
reg = <1>;
diff --git a/dts/Bindings/net/wireless/esp,esp8089.txt b/dts/Bindings/net/wireless/esp,esp8089.txt
index 19331bb4ff..6830c4786f 100644
--- a/dts/Bindings/net/wireless/esp,esp8089.txt
+++ b/dts/Bindings/net/wireless/esp,esp8089.txt
@@ -21,7 +21,6 @@ Example:
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
- status = "okay";
esp8089: sdio_wifi@1 {
compatible = "esp,esp8089";
diff --git a/dts/Bindings/net/wireless/marvell-8xxx.txt b/dts/Bindings/net/wireless/marvell-8xxx.txt
index 0854451ff9..59de864686 100644
--- a/dts/Bindings/net/wireless/marvell-8xxx.txt
+++ b/dts/Bindings/net/wireless/marvell-8xxx.txt
@@ -48,7 +48,6 @@ IRQ pin 38 is used as system wakeup source interrupt. wakeup pin 3 is configured
so that firmware can wakeup host using this device side pin.
&mmc3 {
- status = "okay";
vmmc-supply = <&wlan_en_reg>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
diff --git a/dts/Bindings/net/wireless/ti,wlcore.txt b/dts/Bindings/net/wireless/ti,wlcore.txt
index 7b2cbb1411..f42f6b0f1b 100644
--- a/dts/Bindings/net/wireless/ti,wlcore.txt
+++ b/dts/Bindings/net/wireless/ti,wlcore.txt
@@ -31,7 +31,6 @@ clock, new bindings (for parsing the clock nodes) have to be added.
Example:
&mmc3 {
- status = "okay";
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
cap-power-off-card;
diff --git a/dts/Bindings/net/xilinx_axienet.txt b/dts/Bindings/net/xilinx_axienet.txt
new file mode 100644
index 0000000000..38f9ec0767
--- /dev/null
+++ b/dts/Bindings/net/xilinx_axienet.txt
@@ -0,0 +1,55 @@
+XILINX AXI ETHERNET Device Tree Bindings
+--------------------------------------------------------
+
+Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
+provides connectivity to an external ethernet PHY supporting different
+interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
+segments of memory for buffering TX and RX, as well as the capability of
+offloading TX/RX checksum calculation off the processor.
+
+Management configuration is done through the AXI interface, while payload is
+sent and received through means of an AXI DMA controller. This driver
+includes the DMA driver code, so this driver is incompatible with AXI DMA
+driver.
+
+For more details about mdio please refer phy.txt file in the same directory.
+
+Required properties:
+- compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
+ "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
+- reg : Address and length of the IO space.
+- interrupts : Should be a list of two interrupt, TX and RX.
+- phy-handle : Should point to the external phy device.
+ See ethernet.txt file in the same directory.
+- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
+
+Optional properties:
+- phy-mode : See ethernet.txt
+- xlnx,phy-type : Deprecated, do not use, but still accepted in preference
+ to phy-mode.
+- xlnx,txcsum : 0 or empty for disabling TX checksum offload,
+ 1 to enable partial TX checksum offload,
+ 2 to enable full TX checksum offload
+- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload
+
+Example:
+ axi_ethernet_eth: ethernet@40c00000 {
+ compatible = "xlnx,axi-ethernet-1.00.a";
+ device_type = "network";
+ interrupt-parent = <&microblaze_0_axi_intc>;
+ interrupts = <2 0>;
+ phy-mode = "mii";
+ reg = <0x40c00000 0x40000>;
+ xlnx,rxcsum = <0x2>;
+ xlnx,rxmem = <0x800>;
+ xlnx,txcsum = <0x2>;
+ phy-handle = <&phy0>;
+ axi_ethernetlite_0_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: phy@0 {
+ device_type = "ethernet-phy";
+ reg = <1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/nvmem/mtk-efuse.txt b/dts/Bindings/nvmem/mtk-efuse.txt
index 74cf52908a..0668c45a15 100644
--- a/dts/Bindings/nvmem/mtk-efuse.txt
+++ b/dts/Bindings/nvmem/mtk-efuse.txt
@@ -3,7 +3,10 @@
This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs.
Required properties:
-- compatible: should be "mediatek,mt8173-efuse" or "mediatek,efuse"
+- compatible: should be
+ "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
+ "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
+ "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
- reg: Should contain registers location and length
= Data cells =
diff --git a/dts/Bindings/nvmem/mxs-ocotp.txt b/dts/Bindings/nvmem/mxs-ocotp.txt
index daebce9e6b..372c72fd64 100644
--- a/dts/Bindings/nvmem/mxs-ocotp.txt
+++ b/dts/Bindings/nvmem/mxs-ocotp.txt
@@ -21,5 +21,4 @@ Example for i.MX28:
#size-cells = <1>;
reg = <0x8002c000 0x2000>;
clocks = <&clks 25>;
- status = "okay";
};
diff --git a/dts/Bindings/opp/opp.txt b/dts/Bindings/opp/opp.txt
index e36d261b9b..9d733af26b 100644
--- a/dts/Bindings/opp/opp.txt
+++ b/dts/Bindings/opp/opp.txt
@@ -464,7 +464,6 @@ Example 5: opp-supported-hw
opp_table {
compatible = "operating-points-v2";
- status = "okay";
opp-shared;
opp-600000000 {
diff --git a/dts/Bindings/pci/83xx-512x-pci.txt b/dts/Bindings/pci/83xx-512x-pci.txt
index 35a4653624..b9165b7247 100644
--- a/dts/Bindings/pci/83xx-512x-pci.txt
+++ b/dts/Bindings/pci/83xx-512x-pci.txt
@@ -1,11 +1,11 @@
* Freescale 83xx and 512x PCI bridges
-Freescale 83xx and 512x SOCs include the same pci bridge core.
+Freescale 83xx and 512x SOCs include the same PCI bridge core.
83xx/512x specific notes:
- reg: should contain two address length tuples
- The first is for the internal pci bridge registers
- The second is for the pci config space access registers
+ The first is for the internal PCI bridge registers
+ The second is for the PCI config space access registers
Example (MPC8313ERDB)
pci0: pci@e0008500 {
diff --git a/dts/Bindings/pci/aardvark-pci.txt b/dts/Bindings/pci/aardvark-pci.txt
index bbcd9f4c50..310ef7145c 100644
--- a/dts/Bindings/pci/aardvark-pci.txt
+++ b/dts/Bindings/pci/aardvark-pci.txt
@@ -33,7 +33,6 @@ Example:
pcie0: pcie@d0070000 {
compatible = "marvell,armada-3700-pcie";
device_type = "pci";
- status = "disabled";
reg = <0 0xd0070000 0 0x20000>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/dts/Bindings/pci/altera-pcie.txt b/dts/Bindings/pci/altera-pcie.txt
index 2951a6a507..495880193a 100644
--- a/dts/Bindings/pci/altera-pcie.txt
+++ b/dts/Bindings/pci/altera-pcie.txt
@@ -7,21 +7,21 @@ Required properties:
"Txs": TX slave port region
"Cra": Control register access region
- interrupt-parent: interrupt source phandle.
-- interrupts: specifies the interrupt source of the parent interrupt controller.
- The format of the interrupt specifier depends on the parent interrupt
- controller.
+- interrupts: specifies the interrupt source of the parent interrupt
+ controller. The format of the interrupt specifier depends
+ on the parent interrupt controller.
- device_type: must be "pci"
- #address-cells: set to <3>
-- #size-cells: set to <2>
+- #size-cells: set to <2>
- #interrupt-cells: set to <1>
-- ranges: describes the translation of addresses for root ports and standard
- PCI regions.
+- ranges: describes the translation of addresses for root ports and
+ standard PCI regions.
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
mapping of the PCIe interface to interrupt numbers.
Optional properties:
-- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe
- controller.
+- msi-parent: Link to the hardware entity that serves as the MSI controller
+ for this PCIe controller.
- bus-range: PCI bus numbers covered
Example
@@ -45,5 +45,5 @@ Example
<0 0 0 3 &pcie_0 3>,
<0 0 0 4 &pcie_0 4>;
ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
- 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
+ 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
};
diff --git a/dts/Bindings/pci/axis,artpec6-pcie.txt b/dts/Bindings/pci/axis,artpec6-pcie.txt
index 5ecaea1e6e..4e4aee4439 100644
--- a/dts/Bindings/pci/axis,artpec6-pcie.txt
+++ b/dts/Bindings/pci/axis,artpec6-pcie.txt
@@ -6,7 +6,7 @@ and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
- reg: base addresses and lengths of the PCIe controller (DBI),
- the phy controller, and configuration address space.
+ the PHY controller, and configuration address space.
- reg-names: Must include the following entries:
- "dbi"
- "phy"
diff --git a/dts/Bindings/pci/designware-pcie.txt b/dts/Bindings/pci/designware-pcie.txt
index b2480dd38c..1da7ade318 100644
--- a/dts/Bindings/pci/designware-pcie.txt
+++ b/dts/Bindings/pci/designware-pcie.txt
@@ -1,4 +1,4 @@
-* Synopsys Designware PCIe interface
+* Synopsys DesignWare PCIe interface
Required properties:
- compatible: should contain "snps,dw-pcie" to identify the core.
@@ -17,29 +17,27 @@ RC mode:
properties to define the mapping of the PCIe interface to interrupt
numbers.
EP mode:
-- num-ib-windows: number of inbound address translation
- windows
-- num-ob-windows: number of outbound address translation
- windows
+- num-ib-windows: number of inbound address translation windows
+- num-ob-windows: number of outbound address translation windows
Optional properties:
- num-lanes: number of lanes to use (this property should be specified unless
the link is brought already up in BIOS)
-- reset-gpio: gpio pin number of power good signal
+- reset-gpio: GPIO pin number of power good signal
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
RC mode:
-- num-viewport: number of view ports configured in
- hardware. If a platform does not specify it, the driver assumes 2.
-- bus-range: PCI bus numbers covered (it is recommended
- for new devicetrees to specify this property, to keep backwards
- compatibility a range of 0x00-0xff is assumed if not present)
+- num-viewport: number of view ports configured in hardware. If a platform
+ does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
+ to specify this property, to keep backwards compatibility a range of
+ 0x00-0xff is assumed if not present)
+
EP mode:
-- max-functions: maximum number of functions that can be
- configured
+- max-functions: maximum number of functions that can be configured
Example configuration:
diff --git a/dts/Bindings/pci/fsl,imx6q-pcie.txt b/dts/Bindings/pci/fsl,imx6q-pcie.txt
index cf92d3ba5a..7b1e48bf17 100644
--- a/dts/Bindings/pci/fsl,imx6q-pcie.txt
+++ b/dts/Bindings/pci/fsl,imx6q-pcie.txt
@@ -1,6 +1,6 @@
* Freescale i.MX6 PCIe interface
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
diff --git a/dts/Bindings/pci/hisilicon-pcie.txt b/dts/Bindings/pci/hisilicon-pcie.txt
index a339dbb154..bdb7ab39d2 100644
--- a/dts/Bindings/pci/hisilicon-pcie.txt
+++ b/dts/Bindings/pci/hisilicon-pcie.txt
@@ -1,7 +1,7 @@
HiSilicon Hip05 and Hip06 PCIe host bridge DT description
-HiSilicon PCIe host controller is based on Designware PCI core.
-It shares common functions with PCIe Designware core driver and inherits
+HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
+It shares common functions with the PCIe DesignWare core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.
@@ -40,7 +40,6 @@ Hip05 Example (note that Hip06 is the same except compatible):
0x0 0 0 2 &mbigen_pcie 2 11
0x0 0 0 3 &mbigen_pcie 3 12
0x0 0 0 4 &mbigen_pcie 4 13>;
- status = "ok";
};
HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description.
@@ -83,5 +82,4 @@ Example:
0x0 0 0 2 &mbigen_pcie0 650 4
0x0 0 0 3 &mbigen_pcie0 650 4
0x0 0 0 4 &mbigen_pcie0 650 4>;
- status = "ok";
};
diff --git a/dts/Bindings/pci/kirin-pcie.txt b/dts/Bindings/pci/kirin-pcie.txt
index 68ffa0fbcd..6e217c6312 100644
--- a/dts/Bindings/pci/kirin-pcie.txt
+++ b/dts/Bindings/pci/kirin-pcie.txt
@@ -1,8 +1,8 @@
HiSilicon Kirin SoCs PCIe host DT description
-Kirin PCIe host controller is based on Designware PCI core.
-It shares common functions with PCIe Designware core driver
-and inherits common properties defined in
+Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.
Additional properties are described here:
@@ -16,7 +16,7 @@ Required properties
"apb": apb Ctrl register defined by Kirin;
"phy": apb PHY register defined by Kirin;
"config": PCIe configuration space registers.
-- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
Optional properties:
diff --git a/dts/Bindings/pci/layerscape-pci.txt b/dts/Bindings/pci/layerscape-pci.txt
index ee1c72d516..c0484da0f2 100644
--- a/dts/Bindings/pci/layerscape-pci.txt
+++ b/dts/Bindings/pci/layerscape-pci.txt
@@ -15,8 +15,10 @@ Required properties:
- compatible: should contain the platform identifier such as:
"fsl,ls1021a-pcie", "snps,dw-pcie"
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
+ "fsl,ls2088a-pcie"
+ "fsl,ls1088a-pcie"
"fsl,ls1046a-pcie"
-- reg: base addresses and lengths of the PCIe controller
+- reg: base addresses and lengths of the PCIe controller register blocks.
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
diff --git a/dts/Bindings/pci/mediatek,mt7623-pcie.txt b/dts/Bindings/pci/mediatek,mt7623-pcie.txt
deleted file mode 100644
index fe80dda9bf..0000000000
--- a/dts/Bindings/pci/mediatek,mt7623-pcie.txt
+++ /dev/null
@@ -1,130 +0,0 @@
-MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs
-
-PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
-ports supports a Gen2 1-lane Link and has PIPE interface to PHY.
-
-Required properties:
-- compatible: Should contain "mediatek,mt7623-pcie".
-- device_type: Must be "pci"
-- reg: Base addresses and lengths of the PCIe controller.
-- #address-cells: Address representation for root ports (must be 3)
-- #size-cells: Size representation for root ports (must be 2)
-- #interrupt-cells: Size representation for interrupts (must be 1)
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - free_ck :for reference clock of PCIe subsys
- - sys_ck0 :for clock of Port0
- - sys_ck1 :for clock of Port1
- - sys_ck2 :for clock of Port2
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - pcie-rst0 :port0 reset
- - pcie-rst1 :port1 reset
- - pcie-rst2 :port2 reset
-- phys: List of PHY specifiers (used by generic PHY framework).
-- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
- number of PHYs as specified in *phys* property.
-- power-domains: A phandle and power domain specifier pair to the power domain
- which is responsible for collapsing and restoring power to the peripheral.
-- bus-range: Range of bus numbers associated with this controller.
-- ranges: Ranges for the PCI memory and I/O regions.
-
-In addition, the device tree node must have sub-nodes describing each
-PCIe port interface, having the following mandatory properties:
-
-Required properties:
-- device_type: Must be "pci"
-- reg: Only the first four bytes are used to refer to the correct bus number
- and device number.
-- #address-cells: Must be 3
-- #size-cells: Must be 2
-- #interrupt-cells: Must be 1
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-- ranges: Sub-ranges distributed from the PCIe controller node. An empty
- property is sufficient.
-- num-lanes: Number of lanes to use for this port.
-
-Examples:
-
- hifsys: syscon@1a000000 {
- compatible = "mediatek,mt7623-hifsys",
- "mediatek,mt2701-hifsys",
- "syscon";
- reg = <0 0x1a000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- pcie: pcie-controller@1a140000 {
- compatible = "mediatek,mt7623-pcie";
- device_type = "pci";
- reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
- <0 0x1a142000 0 0x1000>, /* Port0 registers */
- <0 0x1a143000 0 0x1000>, /* Port1 registers */
- <0 0x1a144000 0 0x1000>; /* Port2 registers */
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0xf800 0 0 0>;
- interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
- <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
- <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
- <&hifsys CLK_HIFSYS_PCIE0>,
- <&hifsys CLK_HIFSYS_PCIE1>,
- <&hifsys CLK_HIFSYS_PCIE2>;
- clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
- resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
- <&hifsys MT2701_HIFSYS_PCIE1_RST>,
- <&hifsys MT2701_HIFSYS_PCIE2_RST>;
- reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
- phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;
- phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
- bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
- 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
-
- pcie@0,0 {
- device_type = "pci";
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
- ranges;
- num-lanes = <1>;
- };
-
- pcie@1,0 {
- device_type = "pci";
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
- ranges;
- num-lanes = <1>;
- };
-
- pcie@2,0 {
- device_type = "pci";
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
- ranges;
- num-lanes = <1>;
- };
- };
diff --git a/dts/Bindings/pci/mediatek-pcie.txt b/dts/Bindings/pci/mediatek-pcie.txt
new file mode 100644
index 0000000000..3a6ce55dd3
--- /dev/null
+++ b/dts/Bindings/pci/mediatek-pcie.txt
@@ -0,0 +1,284 @@
+MediaTek Gen2 PCIe controller
+
+Required properties:
+- compatible: Should contain one of the following strings:
+ "mediatek,mt2701-pcie"
+ "mediatek,mt2712-pcie"
+ "mediatek,mt7622-pcie"
+ "mediatek,mt7623-pcie"
+- device_type: Must be "pci"
+- reg: Base addresses and lengths of the PCIe subsys and root ports.
+- reg-names: Names of the above areas to use during resource lookup.
+- #address-cells: Address representation for root ports (must be 3)
+- #size-cells: Size representation for root ports (must be 2)
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names:
+ Mandatory entries:
+ - sys_ckN :transaction layer and data link layer clock
+ Required entries for MT2701/MT7623:
+ - free_ck :for reference clock of PCIe subsys
+ Required entries for MT2712/MT7622:
+ - ahb_ckN :AHB slave interface operating clock for CSR access and RC
+ initiated MMIO access
+ Required entries for MT7622:
+ - axi_ckN :application layer MMIO channel operating clock
+ - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
+ pcie_mac_ck/pcie_pipe_ck is turned off
+ - obff_ckN :OBFF functional block operating clock
+ - pipe_ckN :LTSSM and PHY/MAC layer operating clock
+ where N starting from 0 to one less than the number of root ports.
+- phys: List of PHY specifiers (used by generic PHY framework).
+- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+ number of PHYs as specified in *phys* property.
+- power-domains: A phandle and power domain specifier pair to the power domain
+ which is responsible for collapsing and restoring power to the peripheral.
+- bus-range: Range of bus numbers associated with this controller.
+- ranges: Ranges for the PCI memory and I/O regions.
+
+Required properties for MT7623/MT2701:
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
+ number of root ports.
+
+Required properties for MT2712/MT7622:
+-interrupts: A list of interrupt outputs of the controller, must have one
+ entry for each PCIe port
+
+In addition, the device tree node must have sub-nodes describing each
+PCIe port interface, having the following mandatory properties:
+
+Required properties:
+- device_type: Must be "pci"
+- reg: Only the first four bytes are used to refer to the correct bus number
+ and device number.
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- #interrupt-cells: Must be 1
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+ property is sufficient.
+- num-lanes: Number of lanes to use for this port.
+
+Examples for MT7623:
+
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt7623-hifsys",
+ "mediatek,mt2701-hifsys",
+ "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pcie: pcie-controller@1a140000 {
+ compatible = "mediatek,mt7623-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
+ reg-names = "subsys", "port0", "port1", "port2";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&hifsys CLK_HIFSYS_PCIE0>,
+ <&hifsys CLK_HIFSYS_PCIE1>,
+ <&hifsys CLK_HIFSYS_PCIE2>;
+ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
+ <&pcie2_phy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
+ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
+
+ pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ };
+
+ pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ };
+
+ pcie@2,0 {
+ device_type = "pci";
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ };
+ };
+
+Examples for MT2712:
+ pcie: pcie@11700000 {
+ compatible = "mediatek,mt2712-pcie";
+ device_type = "pci";
+ reg = <0 0x11700000 0 0x1000>,
+ <0 0x112ff000 0 0x1000>;
+ reg-names = "port0", "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+ <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+ <&pericfg CLK_PERI_PCIE0>,
+ <&pericfg CLK_PERI_PCIE1>;
+ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+
+ pcie0: pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+Examples for MT7622:
+ pcie: pcie@1a140000 {
+ compatible = "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>,
+ <0 0x1a143000 0 0x1000>,
+ <0 0x1a145000 0 0x1000>;
+ reg-names = "subsys", "port0", "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+ <&pciesys CLK_PCIE_P1_MAC_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P1_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AUX_EN>,
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P0_AXI_EN>,
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P0_OBFF_EN>,
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
+ <&pciesys CLK_PCIE_P0_PIPE_EN>,
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
+ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+ "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+ "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1";
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+
+ pcie0: pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/pci/mvebu-pci.txt b/dts/Bindings/pci/mvebu-pci.txt
index 2de6f65ecf..6173af6885 100644
--- a/dts/Bindings/pci/mvebu-pci.txt
+++ b/dts/Bindings/pci/mvebu-pci.txt
@@ -77,7 +77,7 @@ and the following optional properties:
- marvell,pcie-lane: the physical PCIe lane number, for ports having
multiple lanes. If this property is not found, we assume that the
value is 0.
-- reset-gpios: optional gpio to PERST#
+- reset-gpios: optional GPIO to PERST#
- reset-delay-us: delay in us to wait after reset de-assertion, if not
specified will default to 100ms, as required by the PCIe specification.
@@ -85,7 +85,6 @@ Example:
pcie-controller {
compatible = "marvell,armada-xp-pcie";
- status = "disabled";
device_type = "pci";
#address-cells = <3>;
@@ -147,7 +146,6 @@ pcie-controller {
/* wait 20ms for device settle after reset deassertion */
reset-delay-us = <20000>;
clocks = <&gateclk 5>;
- status = "disabled";
};
pcie@2,0 {
@@ -164,7 +162,6 @@ pcie-controller {
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
- status = "disabled";
};
pcie@3,0 {
@@ -181,7 +178,6 @@ pcie-controller {
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
- status = "disabled";
};
pcie@4,0 {
@@ -198,7 +194,6 @@ pcie-controller {
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
- status = "disabled";
};
pcie@5,0 {
@@ -215,7 +210,6 @@ pcie-controller {
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
- status = "disabled";
};
pcie@6,0 {
@@ -232,7 +226,6 @@ pcie-controller {
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
- status = "disabled";
};
pcie@7,0 {
@@ -249,7 +242,6 @@ pcie-controller {
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
- status = "disabled";
};
pcie@8,0 {
@@ -266,7 +258,6 @@ pcie-controller {
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
- status = "disabled";
};
pcie@9,0 {
@@ -283,10 +274,9 @@ pcie-controller {
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
- status = "disabled";
};
- pcie@10,0 {
+ pcie@a,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
@@ -300,6 +290,5 @@ pcie-controller {
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/pci/pci-armada8k.txt b/dts/Bindings/pci/pci-armada8k.txt
index 598533a57d..c1e4c3d10a 100644
--- a/dts/Bindings/pci/pci-armada8k.txt
+++ b/dts/Bindings/pci/pci-armada8k.txt
@@ -1,6 +1,6 @@
* Marvell Armada 7K/8K PCIe interface
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
@@ -34,5 +34,4 @@ Example:
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 13>;
- status = "disabled";
};
diff --git a/dts/Bindings/pci/pci-keystone.txt b/dts/Bindings/pci/pci-keystone.txt
index d08a4d5110..7e05487544 100644
--- a/dts/Bindings/pci/pci-keystone.txt
+++ b/dts/Bindings/pci/pci-keystone.txt
@@ -1,12 +1,12 @@
TI Keystone PCIe interface
-Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
-It shares common functions with PCIe Designware core driver and inherit
-common properties defined in
+Keystone PCI host Controller is based on the Synopsys DesignWare PCI
+hardware version 3.65. It shares common functions with the PCIe DesignWare
+core driver and inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt
Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
-for the details of Designware DT bindings. Additional properties are
+for the details of DesignWare DT bindings. Additional properties are
described here as well as properties that are not applicable.
Required Properties:-
@@ -52,13 +52,12 @@ pcie_intc: Interrupt controller device node for Legacy IRQ chip
};
Optional properties:-
- phys: phandle to Generic Keystone SerDes phy for PCI
- phy-names: name of the Generic Keystine SerDes phy for PCI
+ phys: phandle to generic Keystone SerDes PHY for PCI
+ phy-names: name of the generic Keystone SerDes PHY for PCI
- If boot loader already does PCI link establishment, then phys and
phy-names shouldn't be present.
interrupts: platform interrupt for error interrupts.
-Designware DT Properties not applicable for Keystone PCI
+DesignWare DT Properties not applicable for Keystone PCI
1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
-
diff --git a/dts/Bindings/pci/pci-rcar-gen2.txt b/dts/Bindings/pci/pci-rcar-gen2.txt
index 07a75094c5..3d03863861 100644
--- a/dts/Bindings/pci/pci-rcar-gen2.txt
+++ b/dts/Bindings/pci/pci-rcar-gen2.txt
@@ -6,11 +6,14 @@ AHB. There is one bridge instance per USB port connected to the internal
OHCI and EHCI controllers.
Required properties:
-- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
+- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC;
+ "renesas,pci-r8a7745" for the R8A7745 SoC;
+ "renesas,pci-r8a7790" for the R8A7790 SoC;
"renesas,pci-r8a7791" for the R8A7791 SoC;
"renesas,pci-r8a7793" for the R8A7793 SoC;
"renesas,pci-r8a7794" for the R8A7794 SoC;
- "renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
+ "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
+ RZ/G1 compatible device.
When compatible with the generic version, nodes must list the
diff --git a/dts/Bindings/pci/pci.txt b/dts/Bindings/pci/pci.txt
index 50f9e2ca5b..c77981c5dd 100644
--- a/dts/Bindings/pci/pci.txt
+++ b/dts/Bindings/pci/pci.txt
@@ -1,12 +1,12 @@
PCI bus bridges have standardized Device Tree bindings:
PCI Bus Binding to: IEEE Std 1275-1994
-http://www.firmware.org/1275/bindings/pci/pci2_1.pdf
+http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
And for the interrupt mapping part:
Open Firmware Recommended Practice: Interrupt Mapping
-http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
+http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
Additionally to the properties specified in the above standards a host bridge
driver implementation may support the following properties:
diff --git a/dts/Bindings/pci/qcom,pcie.txt b/dts/Bindings/pci/qcom,pcie.txt
index 9d418b7177..3c9d321b3d 100644
--- a/dts/Bindings/pci/qcom,pcie.txt
+++ b/dts/Bindings/pci/qcom,pcie.txt
@@ -9,6 +9,7 @@
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
- "qcom,pcie-ipq4019" for ipq4019
+ - "qcom,pcie-ipq8074" for ipq8074
- reg:
Usage: required
@@ -20,7 +21,7 @@
Value type: <stringlist>
Definition: Must include the following entries
- "parf" Qualcomm specific registers
- - "dbi" Designware PCIe registers
+ - "dbi" DesignWare PCIe registers
- "elbi" External local bus interface registers
- "config" PCIe configuration space
@@ -105,6 +106,16 @@
- "bus_master" Master AXI clock
- "bus_slave" Slave AXI clock
+- clock-names:
+ Usage: required for ipq8074
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "iface" PCIe to SysNOC BIU clock
+ - "axi_m" AXI Master clock
+ - "axi_s" AXI Slave clock
+ - "ahb" AHB clock
+ - "aux" Auxiliary clock
+
- resets:
Usage: required
Value type: <prop-encoded-array>
@@ -144,6 +155,18 @@
- "ahb" AHB reset
- "phy_ahb" PHY AHB reset
+- reset-names:
+ Usage: required for ipq8074
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "pipe" PIPE reset
+ - "sleep" Sleep reset
+ - "sticky" Core Sticky reset
+ - "axi_m" AXI Master reset
+ - "axi_s" AXI Slave reset
+ - "ahb" AHB Reset
+ - "axi_m_sticky" AXI Master Sticky reset
+
- power-domains:
Usage: required for apq8084 and msm8996/apq8096
Value type: <prop-encoded-array>
@@ -180,7 +203,7 @@
- <name>-gpios:
Usage: optional
Value type: <prop-encoded-array>
- Definition: List of phandle and gpio specifier pairs. Should contain
+ Definition: List of phandle and GPIO specifier pairs. Should contain
- "perst-gpios" PCIe endpoint reset signal line
- "wake-gpios" PCIe endpoint wake signal line
diff --git a/dts/Bindings/pci/ralink,rt3883-pci.txt b/dts/Bindings/pci/ralink,rt3883-pci.txt
index 8e0a1eb0ac..a04ab1b762 100644
--- a/dts/Bindings/pci/ralink,rt3883-pci.txt
+++ b/dts/Bindings/pci/ralink,rt3883-pci.txt
@@ -71,7 +71,7 @@
- interrupt-map: standard PCI properties to define the mapping of the
PCI interface to interrupt numbers.
- The PCI host bridge node migh have additional sub-nodes representing
+ The PCI host bridge node might have additional sub-nodes representing
the onboard PCI devices/PCI slots. Each such sub-node must have the
following mandatory properties:
diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt
index bd27428dda..76ba3a61d1 100644
--- a/dts/Bindings/pci/rcar-pci.txt
+++ b/dts/Bindings/pci/rcar-pci.txt
@@ -14,7 +14,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
SoC-specific version corresponding to the platform first
followed by the generic version.
-- reg: base address and length of the pcie controller registers.
+- reg: base address and length of the PCIe controller registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
- bus-range: PCI bus numbers covered
@@ -25,15 +25,14 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
source for hardware related interrupts (e.g. link speed change).
- #interrupt-cells: set to <1>
- interrupt-map-mask and interrupt-map: standard PCI properties
- to define the mapping of the PCIe interface to interrupt
- numbers.
+ to define the mapping of the PCIe interface to interrupt numbers.
- clocks: from common clock binding: clock specifiers for the PCIe controller
and PCIe bus clocks.
- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie: pcie@fe000000 {
compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
@@ -54,5 +53,4 @@ SoC specific DT Entry:
interrupt-map = <0 0 0 0 &gic 0 116 4>;
clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
- status = "disabled";
};
diff --git a/dts/Bindings/pci/rockchip-pcie.txt b/dts/Bindings/pci/rockchip-pcie.txt
index 1453a734c2..af34c65773 100644
--- a/dts/Bindings/pci/rockchip-pcie.txt
+++ b/dts/Bindings/pci/rockchip-pcie.txt
@@ -19,8 +19,6 @@ Required properties:
- "pm"
- msi-map: Maps a Requester ID to an MSI controller and associated
msi-specifier data. See ./pci-msi.txt
-- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
-- phy-names: MUST be "pcie-phy".
- interrupts: Three interrupt entries must be specified.
- interrupt-names: Must include the following names
- "sys"
@@ -42,11 +40,24 @@ Required properties:
interrupt source. The value must be 1.
- interrupt-map-mask and interrupt-map: standard PCI properties
+Required properties for legacy PHY model (deprecated):
+- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
+- phy-names: MUST be "pcie-phy".
+
+Required properties for per-lane PHY model (preferred):
+- phys: Must contain an phandle to a PHY for each entry in phy-names.
+- phy-names: Must include 4 entries for all 4 lanes even if some of
+ them won't be used for your cases. Entries are of the form "pcie-phy-N":
+ where N ranges from 0 to 3.
+ (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+ for changing the #phy-cells of phy node to support it)
+
Optional Property:
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
using 24MHz OSC for RC's PHY.
-- ep-gpios: contain the entry for pre-reset gpio
+- ep-gpios: contain the entry for pre-reset GPIO
- num-lanes: number of lanes to use
+- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
@@ -95,6 +106,7 @@ pcie0: pcie@f8000000 {
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
"pm", "pclk", "aclk";
+ /* deprecated legacy PHY model */
phys = <&pcie_phy>;
phy-names = "pcie-phy";
pinctrl-names = "default";
@@ -111,3 +123,13 @@ pcie0: pcie@f8000000 {
#interrupt-cells = <1>;
};
};
+
+pcie0: pcie@f8000000 {
+ ...
+
+ /* preferred per-lane PHY model */
+ phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
+ phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
+
+ ...
+};
diff --git a/dts/Bindings/pci/samsung,exynos5440-pcie.txt b/dts/Bindings/pci/samsung,exynos5440-pcie.txt
index 7d3b094746..34a11bfbfb 100644
--- a/dts/Bindings/pci/samsung,exynos5440-pcie.txt
+++ b/dts/Bindings/pci/samsung,exynos5440-pcie.txt
@@ -1,29 +1,29 @@
* Samsung Exynos 5440 PCIe interface
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
- compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the pcie controller,
- the phy controller, additional register for the phy controller.
- (Registers for the phy controller are DEPRECATED.
+- reg: base addresses and lengths of the PCIe controller,
+ the PHY controller, additional register for the PHY controller.
+ (Registers for the PHY controller are DEPRECATED.
Use the PHY framework.)
- reg-names : First name should be set to "elbi".
- And use the "config" instead of getting the confgiruation address space
+ And use the "config" instead of getting the configuration address space
from "ranges".
- NOTE: When use the "config" property, reg-names must be set.
+ NOTE: When using the "config" property, reg-names must be set.
- interrupts: A list of interrupt outputs for level interrupt,
pulse interrupt, special interrupt.
-- phys: From PHY binding. Phandle for the Generic PHY.
+- phys: From PHY binding. Phandle for the generic PHY.
Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
-Other common properties refer to
- Documentation/devicetree/binding/pci/designware-pcie.txt
+For other common properties, refer to
+ Documentation/devicetree/bindings/pci/designware-pcie.txt
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie@290000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
@@ -83,7 +83,7 @@ With using PHY framework:
...
};
-Board specific DT Entry:
+Board-specific DT Entry:
pcie@290000 {
reset-gpio = <&pin_ctrl 5 0>;
diff --git a/dts/Bindings/pci/spear13xx-pcie.txt b/dts/Bindings/pci/spear13xx-pcie.txt
index 49ea76da77..d5a14f5dad 100644
--- a/dts/Bindings/pci/spear13xx-pcie.txt
+++ b/dts/Bindings/pci/spear13xx-pcie.txt
@@ -1,12 +1,12 @@
SPEAr13XX PCIe DT detail:
================================
-SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy
+SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
controller.
Required properties:
-- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
-- phys : phandle to phy node associated with pcie controller
+- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
+- phys : phandle to PHY node associated with PCIe controller
- phy-names : must be "pcie-phy"
- All other definitions as per generic PCI bindings
diff --git a/dts/Bindings/pci/ti-pci.txt b/dts/Bindings/pci/ti-pci.txt
index 6a07c96227..7f7af30440 100644
--- a/dts/Bindings/pci/ti-pci.txt
+++ b/dts/Bindings/pci/ti-pci.txt
@@ -1,6 +1,6 @@
TI PCI Controllers
-PCIe Designware Controller
+PCIe DesignWare Controller
- compatible: Should be "ti,dra7-pcie" for RC
Should be "ti,dra7-pcie-ep" for EP
- phys : list of PHY specifiers (used by generic PHY framework)
@@ -13,7 +13,7 @@ PCIe Designware Controller
HOST MODE
=========
- reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ - reg-names : The first entry must be "ti-conf" for the TI-specific registers
The second entry must be "rc-dbics" for the DesignWare PCIe
registers
The third entry must be "config" for the PCIe configuration space
@@ -30,7 +30,7 @@ HOST MODE
DEVICE MODE
===========
- reg : Four register ranges as listed in the reg-names property
- - reg-names : "ti-conf" for the TI specific registers
+ - reg-names : "ti-conf" for the TI-specific registers
"ep_dbics" for the standard configuration registers as
they are locally accessed within the DIF CS space
"ep_dbics2" for the standard configuration registers as
@@ -46,7 +46,7 @@ DEVICE MODE
access.
Optional Property:
- - gpios : Should be added if a gpio line is required to drive PERST# line
+ - gpios : Should be added if a GPIO line is required to drive PERST# line
NOTE: Two DT nodes may be added for each PCI controller; one for host
mode and another for device mode. So in order for PCI to
diff --git a/dts/Bindings/pci/versatile.txt b/dts/Bindings/pci/versatile.txt
index ebd1e7d040..0a702b13d2 100644
--- a/dts/Bindings/pci/versatile.txt
+++ b/dts/Bindings/pci/versatile.txt
@@ -5,7 +5,7 @@ PCI host controller found on the ARM Versatile PB board's FPGA.
Required properties:
- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI
controller.
-- reg: base addresses and lengths of the pci controller. There must be 3
+- reg: base addresses and lengths of the PCI controller. There must be 3
entries:
- Versatile-specific registers
- Self Config space
diff --git a/dts/Bindings/pci/xgene-pci-msi.txt b/dts/Bindings/pci/xgene-pci-msi.txt
index 36d881c8e6..85d9b95234 100644
--- a/dts/Bindings/pci/xgene-pci-msi.txt
+++ b/dts/Bindings/pci/xgene-pci-msi.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible: should be "apm,xgene1-msi" to identify
X-Gene v1 PCIe MSI controller block.
-- msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node
+- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
- reg: physical base address (0x79000000) and length (0x900000) for controller
registers. These registers include the MSI termination address and data
registers as well as the MSI interrupt status registers.
@@ -13,7 +13,8 @@ Required properties:
interrupt number 0x10 to 0x1f.
- interrupt-names: not required
-Each PCIe node needs to have property msi-parent that points to msi controller node
+Each PCIe node needs to have property msi-parent that points to an MSI
+controller node
Examples:
@@ -44,7 +45,6 @@ SoC DTSI:
+ PCIe controller node with msi-parent property pointing to MSI node:
pcie0: pcie@1f2b0000 {
- status = "disabled";
device_type = "pci";
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
#interrupt-cells = <1>;
diff --git a/dts/Bindings/pci/xgene-pci.txt b/dts/Bindings/pci/xgene-pci.txt
index 1070b068c7..6fd2decfa6 100644
--- a/dts/Bindings/pci/xgene-pci.txt
+++ b/dts/Bindings/pci/xgene-pci.txt
@@ -8,7 +8,7 @@ Required properties:
property.
- reg-names: Must include the following entries:
"csr": controller configuration registers.
- "cfg": pcie configuration space registers.
+ "cfg": PCIe configuration space registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
- ranges: ranges for the outbound memory, I/O regions.
@@ -21,11 +21,11 @@ Required properties:
Optional properties:
- status: Either "ok" or "disabled".
-- dma-coherent: Present if dma operations are coherent
+- dma-coherent: Present if DMA operations are coherent
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie0: pcie@1f2b0000 {
status = "disabled";
@@ -51,7 +51,7 @@ SoC specific DT Entry:
};
-Board specific DT Entry:
+Board-specific DT Entry:
&pcie0 {
status = "ok";
};
diff --git a/dts/Bindings/pci/xilinx-nwl-pcie.txt b/dts/Bindings/pci/xilinx-nwl-pcie.txt
index 3259798a11..01bf7fdf4c 100644
--- a/dts/Bindings/pci/xilinx-nwl-pcie.txt
+++ b/dts/Bindings/pci/xilinx-nwl-pcie.txt
@@ -15,9 +15,9 @@ Required properties:
- device_type: must be "pci"
- interrupts: Should contain NWL PCIe interrupt
- interrupt-names: Must include the following entries:
- "msi1, msi0": interrupt asserted when MSI is received
+ "msi1, msi0": interrupt asserted when an MSI is received
"intx": interrupt asserted when a legacy interrupt is received
- "misc": interrupt asserted when miscellaneous is received
+ "misc": interrupt asserted when miscellaneous interrupt is received
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
mapping of the PCI interface to interrupt numbers.
- ranges: ranges for the PCI memory regions (I/O space region is not
@@ -26,7 +26,8 @@ Required properties:
detailed explanation
- msi-controller: indicates that this is MSI controller node
- msi-parent: MSI parent of the root complex itself
-- legacy-interrupt-controller: Interrupt controller device node for Legacy interrupts
+- legacy-interrupt-controller: Interrupt controller device node for Legacy
+ interrupts
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: should be set to 1
- #address-cells: specifies the number of cells needed to encode an
diff --git a/dts/Bindings/phy/apm-xgene-phy.txt b/dts/Bindings/phy/apm-xgene-phy.txt
index 5f3a65a9dd..e1bb12711f 100644
--- a/dts/Bindings/phy/apm-xgene-phy.txt
+++ b/dts/Bindings/phy/apm-xgene-phy.txt
@@ -61,19 +61,16 @@ Example:
compatible = "apm,xgene-phy";
reg = <0x0 0x1f21a000 0x0 0x100>;
#phy-cells = <1>;
- status = "disabled";
};
phy2: phy@1f22a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f22a000 0x0 0x100>;
#phy-cells = <1>;
- status = "ok";
};
phy3: phy@1f23a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f23a000 0x0 0x100>;
#phy-cells = <1>;
- status = "ok";
};
diff --git a/dts/Bindings/phy/keystone-usb-phy.txt b/dts/Bindings/phy/keystone-usb-phy.txt
index f37b3a8634..300830dda0 100644
--- a/dts/Bindings/phy/keystone-usb-phy.txt
+++ b/dts/Bindings/phy/keystone-usb-phy.txt
@@ -16,5 +16,4 @@ usb_phy: usb_phy@2620738 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2620738 32>;
- status = "disabled";
};
diff --git a/dts/Bindings/phy/phy-bindings.txt b/dts/Bindings/phy/phy-bindings.txt
index 1293c32175..a403b81d06 100644
--- a/dts/Bindings/phy/phy-bindings.txt
+++ b/dts/Bindings/phy/phy-bindings.txt
@@ -34,7 +34,9 @@ PHY user node
=============
Required Properties:
-phys : the phandle for the PHY device (used by the PHY subsystem)
+phys : the phandle for the PHY device (used by the PHY subsystem; not to be
+ confused with the Ethernet specific 'phy' and 'phy-handle' properties,
+ see Documentation/devicetree/bindings/net/ethernet.txt for these)
phy-names : the names of the PHY corresponding to the PHYs present in the
*phys* phandle
diff --git a/dts/Bindings/phy/phy-lantiq-rcu-usb2.txt b/dts/Bindings/phy/phy-lantiq-rcu-usb2.txt
new file mode 100644
index 0000000000..643948b6b5
--- /dev/null
+++ b/dts/Bindings/phy/phy-lantiq-rcu-usb2.txt
@@ -0,0 +1,40 @@
+Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
+===========================================
+
+This binding describes the USB PHY hardware provided by the RCU module on the
+Lantiq XWAY SoCs.
+
+This node has to be a sub node of the Lantiq RCU block.
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible : Should be one of
+ "lantiq,ase-usb2-phy"
+ "lantiq,danube-usb2-phy"
+ "lantiq,xrx100-usb2-phy"
+ "lantiq,xrx200-usb2-phy"
+ "lantiq,xrx300-usb2-phy"
+- reg : Defines the following sets of registers in the parent
+ syscon device
+ - Offset of the USB PHY configuration register
+ - Offset of the USB Analog configuration
+ register (only for xrx200 and xrx200)
+- clocks : References to the (PMU) "phy" clk gate.
+- clock-names : Must be "phy"
+- resets : References to the RCU USB configuration reset bits.
+- reset-names : Must be one of the following:
+ "phy" (optional)
+ "ctrl" (shared)
+
+-------------------------------------------------------------------------------
+Example for the USB PHYs on an xRX200 SoC:
+ usb_phy0: usb2-phy@18 {
+ compatible = "lantiq,xrx200-usb2-phy";
+ reg = <0x18 4>, <0x38 4>;
+
+ clocks = <&pmu PMU_GATE_USB0_PHY>;
+ clock-names = "phy";
+ resets = <&reset1 4 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
diff --git a/dts/Bindings/phy/phy-mt65xx-usb.txt b/dts/Bindings/phy/phy-mtk-tphy.txt
index 0acc5a99fb..41e09ed2ca 100644
--- a/dts/Bindings/phy/phy-mt65xx-usb.txt
+++ b/dts/Bindings/phy/phy-mtk-tphy.txt
@@ -1,13 +1,18 @@
-mt65xx USB3.0 PHY binding
+MediaTek T-PHY binding
--------------------------
-This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
+T-phy controller supports physical layer functionality for a number of
+controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
Required properties (controller (parent) node):
- compatible : should be one of
- "mediatek,mt2701-u3phy"
- "mediatek,mt2712-u3phy"
- "mediatek,mt8173-u3phy"
+ "mediatek,generic-tphy-v1"
+ "mediatek,generic-tphy-v2"
+ "mediatek,mt2701-u3phy" (deprecated)
+ "mediatek,mt2712-u3phy" (deprecated)
+ "mediatek,mt8173-u3phy";
+ make use of "mediatek,generic-tphy-v1" on mt2701 instead and
+ "mediatek,generic-tphy-v2" on mt2712 instead.
- clocks : (deprecated, use port's clocks instead) a list of phandle +
clock-specifier pairs, one for each entry in clock-names
- clock-names : (deprecated, use port's one instead) must contain
@@ -35,6 +40,8 @@ Required properties (port (child) node):
cell after port phandle is phy type from:
- PHY_TYPE_USB2
- PHY_TYPE_USB3
+ - PHY_TYPE_PCIE
+ - PHY_TYPE_SATA
Example:
@@ -44,14 +51,12 @@ u3phy: usb-phy@11290000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
- status = "okay";
u2port0: usb-phy@11290800 {
reg = <0 0x11290800 0 0x100>;
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
clock-names = "ref";
#phy-cells = <1>;
- status = "okay";
};
u3port0: usb-phy@11290900 {
@@ -59,7 +64,6 @@ u3phy: usb-phy@11290000 {
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
- status = "okay";
};
u2port1: usb-phy@11291000 {
@@ -67,7 +71,6 @@ u3phy: usb-phy@11290000 {
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
clock-names = "ref";
#phy-cells = <1>;
- status = "okay";
};
};
diff --git a/dts/Bindings/phy/phy-mvebu-comphy.txt b/dts/Bindings/phy/phy-mvebu-comphy.txt
new file mode 100644
index 0000000000..bfcf803416
--- /dev/null
+++ b/dts/Bindings/phy/phy-mvebu-comphy.txt
@@ -0,0 +1,43 @@
+mvebu comphy driver
+-------------------
+
+A comphy controller can be found on Marvell Armada 7k/8k on the CP110. It
+provides a number of shared PHYs used by various interfaces (network, sata,
+usb, PCIe...).
+
+Required properties:
+
+- compatible: should be "marvell,comphy-cp110"
+- reg: should contain the comphy register location and length.
+- marvell,system-controller: should contain a phandle to the
+ system controller node.
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+
+A sub-node is required for each comphy lane provided by the comphy.
+
+Required properties (child nodes):
+
+- reg: comphy lane number.
+- #phy-cells : from the generic phy bindings, must be 1. Defines the
+ input port to use for a given comphy lane.
+
+Example:
+
+ cpm_comphy: phy@120000 {
+ compatible = "marvell,comphy-cp110";
+ reg = <0x120000 0x6000>;
+ marvell,system-controller = <&cpm_syscon0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpm_comphy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ cpm_comphy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/phy/phy-mvebu.txt b/dts/Bindings/phy/phy-mvebu.txt
index f95b6260a3..64afdd13d9 100644
--- a/dts/Bindings/phy/phy-mvebu.txt
+++ b/dts/Bindings/phy/phy-mvebu.txt
@@ -18,7 +18,6 @@ Example:
clocks = <&gate_clk 15>;
clock-names = "sata";
#phy-cells = <0>;
- status = "ok";
};
Armada 375 USB cluster
diff --git a/dts/Bindings/phy/phy-rockchip-inno-usb2.txt b/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
index 84d59b0db8..074a7b3b04 100644
--- a/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
+++ b/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
@@ -6,6 +6,7 @@ Required properties (phy (parent) node):
* "rockchip,rk3328-usb2phy"
* "rockchip,rk3366-usb2phy"
* "rockchip,rk3399-usb2phy"
+ * "rockchip,rv1108-usb2phy"
- reg : the address offset of grf for usb-phy configuration.
- #clock-cells : should be 0.
- clock-output-names : specify the 480m output clock name.
@@ -18,6 +19,10 @@ Optional properties:
usb-phy output 480m and xin24m.
Refer to clk/clock-bindings.txt for generic clock
consumer properties.
+ - rockchip,usbgrf : phandle to the syscon managing the "usb general
+ register files". When set driver will request its
+ phandle as one companion-grf for some special SoCs
+ (e.g RV1108).
Required nodes : a sub-node is required for each port the phy provides.
The sub-node name is used to identify host or otg port,
@@ -28,10 +33,14 @@ Required nodes : a sub-node is required for each port the phy provides.
Required properties (port (child) node):
- #phy-cells : must be 0. See ./phy-bindings.txt for details.
- interrupts : specify an interrupt for each entry in interrupt-names.
- - interrupt-names : a list which shall be the following entries:
+ - interrupt-names : a list which should be one of the following cases:
+ Regular case:
* "otg-id" : for the otg id interrupt.
* "otg-bvalid" : for the otg vbus interrupt.
* "linestate" : for the host/otg linestate interrupt.
+ Some SoCs use one interrupt with the above muxed together, so for these
+ * "otg-mux" : otg-port interrupt, which mux otg-id/otg-bvalid/linestate
+ to one.
Optional properties:
- phy-supply : phandle to a regulator that provides power to VBUS.
@@ -58,14 +67,12 @@ grf: syscon@ff770000 {
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-id", "otg-bvalid", "linestate";
- status = "okay";
};
u2phy_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
- status = "okay";
};
};
};
diff --git a/dts/Bindings/phy/qcom-dwc3-usb-phy.txt b/dts/Bindings/phy/qcom-dwc3-usb-phy.txt
index 86f2dbe07e..a1697c27ae 100644
--- a/dts/Bindings/phy/qcom-dwc3-usb-phy.txt
+++ b/dts/Bindings/phy/qcom-dwc3-usb-phy.txt
@@ -25,7 +25,6 @@ Example:
clock-names = "ref";
#phy-cells = <0>;
- status = "ok";
};
phy@100f8830 {
@@ -35,5 +34,4 @@ Example:
clock-names = "ref";
#phy-cells = <0>;
- status = "ok";
};
diff --git a/dts/Bindings/phy/qcom-qmp-phy.txt b/dts/Bindings/phy/qcom-qmp-phy.txt
index e11c563a65..b6a9f2b92b 100644
--- a/dts/Bindings/phy/qcom-qmp-phy.txt
+++ b/dts/Bindings/phy/qcom-qmp-phy.txt
@@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
Required properties:
- compatible: compatible list, contains:
+ "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
@@ -38,6 +39,8 @@ Required properties:
"phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
"phy", "common".
+ For "qcom,ipq8074-qmp-pcie-phy" must contain:
+ "phy", "common".
- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -60,6 +63,13 @@ Required properties for child node:
one for each entry in clock-names.
- clock-names: Must contain following for pcie and usb qmp phys:
"pipe<lane-number>" for pipe clock specific to each lane.
+ - clock-output-names: Name of the PHY clock that will be the parent for
+ the above pipe clock.
+
+ For "qcom,ipq8074-qmp-pcie-phy":
+ - "pcie20_phy0_pipe_clk" Pipe Clock parent
+ (or)
+ "pcie20_phy1_pipe_clk"
- resets: a list of phandles and reset controller specifier pairs,
one for each entry in reset-names.
@@ -96,6 +106,7 @@ Example:
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
+ clock-output-names = "pcie_0_pipe_clk_src";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
};
diff --git a/dts/Bindings/phy/ralink-usb-phy.txt b/dts/Bindings/phy/ralink-usb-phy.txt
new file mode 100644
index 0000000000..9d2868a437
--- /dev/null
+++ b/dts/Bindings/phy/ralink-usb-phy.txt
@@ -0,0 +1,23 @@
+Mediatek/Ralink USB PHY
+
+Required properties:
+ - compatible: "ralink,rt3352-usbphy"
+ "mediatek,mt7620-usbphy"
+ "mediatek,mt7628-usbphy"
+ - reg: required for "mediatek,mt7628-usbphy", unused otherwise
+ - #phy-cells: should be 0
+ - ralink,sysctl: a phandle to a ralink syscon register region
+ - resets: the two reset controllers for host and device
+ - reset-names: the names of the 2 reset controllers
+
+Example:
+
+usbphy: phy {
+ compatible = "mediatek,mt7628-usbphy";
+ reg = <0x10120000 0x1000>;
+ #phy-cells = <0>;
+
+ ralink,sysctl = <&sysc>;
+ resets = <&rstctrl 22 &rstctrl 25>;
+ reset-names = "host", "device";
+};
diff --git a/dts/Bindings/phy/rockchip-pcie-phy.txt b/dts/Bindings/phy/rockchip-pcie-phy.txt
index 0f6222a672..b496042f1f 100644
--- a/dts/Bindings/phy/rockchip-pcie-phy.txt
+++ b/dts/Bindings/phy/rockchip-pcie-phy.txt
@@ -3,7 +3,6 @@ Rockchip PCIE PHY
Required properties:
- compatible: rockchip,rk3399-pcie-phy
- - #phy-cells: must be 0
- clocks: Must contain an entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must be "refclk"
@@ -11,6 +10,12 @@ Required properties:
See ../reset/reset.txt for details.
- reset-names: Must be "phy"
+Required properties for legacy PHY mode (deprecated):
+ - #phy-cells: must be 0
+
+Required properties for per-lane PHY mode (preferred):
+ - #phy-cells: must be 1
+
Example:
grf: syscon@ff770000 {
diff --git a/dts/Bindings/phy/samsung-phy.txt b/dts/Bindings/phy/samsung-phy.txt
index ab80bfe31c..1c40ccd40c 100644
--- a/dts/Bindings/phy/samsung-phy.txt
+++ b/dts/Bindings/phy/samsung-phy.txt
@@ -82,7 +82,6 @@ usbphy: phy@125b0000 {
reg = <0x125b0000 0x100>;
clocks = <&clock 305>, <&clock 2>;
clock-names = "phy", "ref";
- status = "okay";
#phy-cells = <1>;
samsung,sysreg-phandle = <&sys_reg>;
samsung,pmureg-phandle = <&pmu_reg>;
diff --git a/dts/Bindings/phy/sun4i-usb-phy.txt b/dts/Bindings/phy/sun4i-usb-phy.txt
index 005bc22938..cbc7847dbf 100644
--- a/dts/Bindings/phy/sun4i-usb-phy.txt
+++ b/dts/Bindings/phy/sun4i-usb-phy.txt
@@ -9,6 +9,7 @@ Required properties:
* allwinner,sun7i-a20-usb-phy
* allwinner,sun8i-a23-usb-phy
* allwinner,sun8i-a33-usb-phy
+ * allwinner,sun8i-a83t-usb-phy
* allwinner,sun8i-h3-usb-phy
* allwinner,sun8i-v3s-usb-phy
* allwinner,sun50i-a64-usb-phy
@@ -17,18 +18,22 @@ Required properties:
* "phy_ctrl"
* "pmu0" for H3, V3s and A64
* "pmu1"
- * "pmu2" for sun4i, sun6i or sun7i
+ * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
+ * "pmu3" for sun8i-h3
- #phy-cells : from the generic phy bindings, must be 1
- clocks : phandle + clock specifier for the phy clocks
- clock-names :
* "usb_phy" for sun4i, sun5i or sun7i
* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
* "usb0_phy", "usb1_phy" for sun8i
+ * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
+ * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
- resets : a list of phandle + reset specifier pairs
- reset-names :
* "usb0_reset"
* "usb1_reset"
- * "usb2_reset" for sun4i, sun6i or sun7i
+ * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
+ * "usb3_reset" for sun8i-h3
Optional properties:
- usb0_id_det-gpios : gpio phandle for reading the otg id pin value
@@ -37,6 +42,7 @@ Optional properties:
- usb0_vbus-supply : regulator phandle for controller usb0 vbus
- usb1_vbus-supply : regulator phandle for controller usb1 vbus
- usb2_vbus-supply : regulator phandle for controller usb2 vbus
+- usb3_vbus-supply : regulator phandle for controller usb3 vbus
Example:
usbphy: phy@0x01c13400 {
diff --git a/dts/Bindings/phy/sun9i-usb-phy.txt b/dts/Bindings/phy/sun9i-usb-phy.txt
index 1cca85c709..f9853156e3 100644
--- a/dts/Bindings/phy/sun9i-usb-phy.txt
+++ b/dts/Bindings/phy/sun9i-usb-phy.txt
@@ -33,6 +33,5 @@ Example:
clock-names = "hsic_480M", "hsic_12M", "phy";
resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
reset-names = "hsic", "phy";
- status = "disabled";
#phy-cells = <0>;
};
diff --git a/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt b/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt
index 590e60378b..3e23fece99 100644
--- a/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -148,5 +148,4 @@ dbgu: serial@fffff200 {
interrupts = <1 4 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- status = "disabled";
};
diff --git a/dts/Bindings/pinctrl/cortina,gemini-pinctrl.txt b/dts/Bindings/pinctrl/cortina,gemini-pinctrl.txt
new file mode 100644
index 0000000000..61466c58fa
--- /dev/null
+++ b/dts/Bindings/pinctrl/cortina,gemini-pinctrl.txt
@@ -0,0 +1,59 @@
+Cortina Systems Gemini pin controller
+
+This pin controller is found in the Cortina Systems Gemini SoC family,
+see further arm/gemini.txt. It is a purely group-based multiplexing pin
+controller.
+
+The pin controller node must be a subnode of the system controller node.
+
+Required properties:
+- compatible: "cortina,gemini-pinctrl"
+
+Subnodes of the pin controller contain pin control multiplexing set-up.
+Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes.
+
+Example:
+
+
+syscon {
+ compatible = "cortina,gemini-syscon";
+ ...
+ pinctrl {
+ compatible = "cortina,gemini-pinctrl";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
+ <&vcontrol_default_pins>;
+
+ dram_default_pins: pinctrl-dram {
+ mux {
+ function = "dram";
+ groups = "dramgrp";
+ };
+ };
+ rtc_default_pins: pinctrl-rtc {
+ mux {
+ function = "rtc";
+ groups = "rtcgrp";
+ };
+ };
+ power_default_pins: pinctrl-power {
+ mux {
+ function = "power";
+ groups = "powergrp";
+ };
+ };
+ system_default_pins: pinctrl-system {
+ mux {
+ function = "system";
+ groups = "systemgrp";
+ };
+ };
+ (...)
+ uart_default_pins: pinctrl-uart {
+ mux {
+ function = "uart";
+ groups = "uartrxtxgrp";
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/pinctrl/fsl,imx-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx-pinctrl.txt
index 9fde25f140..42d74f8a1b 100644
--- a/dts/Bindings/pinctrl/fsl,imx-pinctrl.txt
+++ b/dts/Bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -61,7 +61,6 @@ Examples:
usdhc@0219c000 { /* uSDHC4 */
non-removable;
vmmc-supply = <&reg_3p3v>;
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
};
diff --git a/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8c5d27c5b5..6666277c3a 100644
--- a/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -61,7 +61,6 @@ iomuxc-lpsr controller and SDA pad from iomuxc controller as:
i2c1: i2c@30a20000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
- status = "okay";
};
iomuxc-lpsr@302c0000 {
diff --git a/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
new file mode 100644
index 0000000000..44ad670ae1
--- /dev/null
+++ b/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
@@ -0,0 +1,61 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
+ports and IOMUXC DDR for DDR interface.
+
+Note:
+This binding doc is only for the IOMUXC1 support in A7 Domain and it only
+supports generic pin config.
+
+Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
+binding.
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible: "fsl,imx7ulp-iomuxc1"
+- reg: Should contain the base physical address and size of the iomuxc
+ registers.
+
+=== Pin Configuration Node ===
+- pinmux: One integers array, represents a group of pins mux setting.
+ The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
+ a specific function.
+
+ NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
+ and config register as follows:
+ <mux_conf_reg input_reg mux_mode input_val>
+
+ Refer to imx7ulp-pinfunc.h in in device tree source folder for all
+ available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- drive-strength Integer. Controls Drive Strength
+ 0: Standard
+ 1: Hi Driver
+- drive-push-pull Bool. Enable Pin Push-pull
+- drive-open-drain Bool. Enable Pin Open-drian
+- slew-rate: Integer. Controls Slew Rate
+ 0: Standard
+ 1: Slow
+- bias-disable: Bool. Pull disabled
+- bias-pull-down: Bool. Pull down on pin
+- bias-pull-up: Bool. Pull up on pin
+
+Examples:
+#include "imx7ulp-pinfunc.h"
+
+/* Pin Controller Node */
+iomuxc1: iomuxc@40ac0000 {
+ compatible = "fsl,imx7ulp-iomuxc1";
+ reg = <0x40ac0000 0x1000>;
+
+ /* Pin Configuration Node */
+ pinctrl_lpuart4: lpuart4grp {
+ pinmux = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX
+ IMX7ULP_PAD_PTC2__LPUART4_TX
+ >;
+ bias-pull-up;
+ };
+};
diff --git a/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt b/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
index f2abdaee90..e0e886b735 100644
--- a/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
+++ b/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
@@ -56,5 +56,4 @@ Example:
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
pinctrl-names = "default", "idle";
- status = "disabled";
};
diff --git a/dts/Bindings/pinctrl/oxnas,pinctrl.txt b/dts/Bindings/pinctrl/oxnas,pinctrl.txt
index 09e81a95bb..b1159434f5 100644
--- a/dts/Bindings/pinctrl/oxnas,pinctrl.txt
+++ b/dts/Bindings/pinctrl/oxnas,pinctrl.txt
@@ -50,7 +50,6 @@ uart2: serial@900000 {
reg-io-width = <1>;
current-speed = <115200>;
no-loopback-test;
- status = "disabled";
resets = <&reset 22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
diff --git a/dts/Bindings/pinctrl/pinctrl-aspeed.txt b/dts/Bindings/pinctrl/pinctrl-aspeed.txt
index ca01710ee2..3b7266c7c4 100644
--- a/dts/Bindings/pinctrl/pinctrl-aspeed.txt
+++ b/dts/Bindings/pinctrl/pinctrl-aspeed.txt
@@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
-TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
-VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
+TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
+USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
+WDTRST2
aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
@@ -86,7 +87,8 @@ SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
-TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
+TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS
+VGAVS VPI24 VPO WDTRST1 WDTRST2
Examples
========
diff --git a/dts/Bindings/pinctrl/pinctrl-bindings.txt b/dts/Bindings/pinctrl/pinctrl-bindings.txt
index 62d0f33fa6..4483cc31e5 100644
--- a/dts/Bindings/pinctrl/pinctrl-bindings.txt
+++ b/dts/Bindings/pinctrl/pinctrl-bindings.txt
@@ -268,6 +268,8 @@ output-enable - enable output on a pin without actively driving it
(such as enabling an output buffer)
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
+sleep-hardware-state - indicate this is sleep related state which will be programmed
+ into the registers for the sleep state.
slew-rate - set the slew rate
For example:
diff --git a/dts/Bindings/pinctrl/pinctrl-mt65xx.txt b/dts/Bindings/pinctrl/pinctrl-mt65xx.txt
index 17631d0a9a..37d7447505 100644
--- a/dts/Bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/dts/Bindings/pinctrl/pinctrl-mt65xx.txt
@@ -5,6 +5,7 @@ The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
+ "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
diff --git a/dts/Bindings/pinctrl/pinctrl-rk805.txt b/dts/Bindings/pinctrl/pinctrl-rk805.txt
new file mode 100644
index 0000000000..eee3dc2609
--- /dev/null
+++ b/dts/Bindings/pinctrl/pinctrl-rk805.txt
@@ -0,0 +1,63 @@
+Pincontrol driver for RK805 Power management IC.
+
+RK805 has 2 pins which can be configured as GPIO output only.
+
+Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
+for details of the common pinctrl bindings used by client devices,
+including the meaning of the phrase "pin configuration node".
+
+Optional Pinmux properties:
+--------------------------
+Following properties are required if default setting of pins are required
+at boot.
+- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
+- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
+ <pinctrl-binding.txt>.
+
+The pin configurations are defined as child of the pinctrl states node. Each
+sub-node have following properties:
+
+Required properties:
+------------------
+- #gpio-cells: Should be two. The first cell is the pin number and the
+ second is the GPIO flags.
+
+- gpio-controller: Marks the device node as a GPIO controller.
+
+- pins: List of pins. Valid values of pins properties are: gpio0, gpio1.
+
+First 2 properties must be added in the RK805 PMIC node, documented in
+Documentation/devicetree/bindings/mfd/rk808.txt
+
+Optional properties:
+-------------------
+Following are optional properties defined as pinmux DT binding document
+<pinctrl-bindings.txt>. Absence of properties will leave the configuration
+on default.
+ function,
+ output-low,
+ output-high.
+
+Valid values for function properties are: gpio.
+
+Theres is also not customised properties for any GPIO.
+
+Example:
+--------
+rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ ...
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>, <&rk805_default>;
+
+ rk805_default: pinmux {
+ gpio01 {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ output-high;
+ };
+ };
+};
diff --git a/dts/Bindings/pinctrl/pinctrl-zx.txt b/dts/Bindings/pinctrl/pinctrl-zx.txt
index e219849b21..39170f3725 100644
--- a/dts/Bindings/pinctrl/pinctrl-zx.txt
+++ b/dts/Bindings/pinctrl/pinctrl-zx.txt
@@ -81,5 +81,4 @@ pmm: pin-controller@1462000 {
&vga {
pinctrl-names = "default";
pinctrl-0 = <&vga_pins>;
- status = "okay";
};
diff --git a/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt b/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt
index a7bde64798..a752a47164 100644
--- a/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt
+++ b/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt
@@ -46,7 +46,8 @@ Valid values for pins are:
gpio0-gpio89
Valid values for function are:
- cam_mclk, codec_mic_i2s, codec_spkr_i2s, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
+ cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a,
+ gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
diff --git a/dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt b/dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt
index cfb8500dd5..93374f478b 100644
--- a/dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt
+++ b/dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt
@@ -50,7 +50,11 @@ Valid values for qcom,pins are:
Supports mux, bias and drive-strength
Valid values for qcom,function are:
-gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
+aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
+blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
+jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
+mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
+smart2, smart3, tm, wifi0, wifi1
Example:
diff --git a/dts/Bindings/pinctrl/qcom,pmic-gpio.txt b/dts/Bindings/pinctrl/qcom,pmic-gpio.txt
index 8d893a8746..5b12c57e7f 100644
--- a/dts/Bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/dts/Bindings/pinctrl/qcom,pmic-gpio.txt
@@ -16,6 +16,7 @@ PMIC's from Qualcomm.
"qcom,pm8941-gpio"
"qcom,pm8994-gpio"
"qcom,pma8084-gpio"
+ "qcom,pmi8994-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
@@ -85,6 +86,7 @@ to specify in a pin configuration subnode:
gpio1-gpio36 for pm8941
gpio1-gpio22 for pm8994
gpio1-gpio22 for pma8084
+ gpio1-gpio10 for pmi8994
- function:
Usage: required
@@ -98,7 +100,10 @@ to specify in a pin configuration subnode:
"dtest1",
"dtest2",
"dtest3",
- "dtest4"
+ "dtest4",
+ And following values are supported by LV/MV GPIO subtypes:
+ "func3",
+ "func4"
- bias-disable:
Usage: optional
@@ -183,6 +188,25 @@ to specify in a pin configuration subnode:
Value type: <none>
Definition: The specified pins are configured in open-source mode.
+- qcom,analog-pass:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in analog-pass-through mode.
+
+- qcom,atest:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects ATEST rail to route to GPIO when it's configured
+ in analog-pass-through mode.
+ Valid values are 1-4 corresponding to ATEST1 to ATEST4.
+
+- qcom,dtest-buffer:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects DTEST rail to route to GPIO when it's configured
+ as digital input.
+ Valid values are 1-4 corresponding to DTEST1 to DTEST4.
+
Example:
pm8921_gpio: gpio@150 {
diff --git a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
index 645082f032..9b4f8041c3 100644
--- a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -24,6 +24,7 @@ Required Properties:
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
+ - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
@@ -111,7 +112,7 @@ Examples
Example 1: SH73A0 (SH-Mobile AG5) pin controller node
- pfc: pfc@e6050000 {
+ pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
@@ -172,5 +173,4 @@ Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
- status = "okay";
};
diff --git a/dts/Bindings/pinctrl/rockchip,pinctrl.txt b/dts/Bindings/pinctrl/rockchip,pinctrl.txt
index ee01ab5822..4864e3a74d 100644
--- a/dts/Bindings/pinctrl/rockchip,pinctrl.txt
+++ b/dts/Bindings/pinctrl/rockchip,pinctrl.txt
@@ -24,6 +24,7 @@ Required properties for iomux controller:
"rockchip,rk2928-pinctrl": for Rockchip RK2928
"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
"rockchip,rk3066b-pinctrl": for Rockchip RK3066b
+ "rockchip,rk3128-pinctrl": for Rockchip RK3128
"rockchip,rk3188-pinctrl": for Rockchip RK3188
"rockchip,rk3228-pinctrl": for Rockchip RK3228
"rockchip,rk3288-pinctrl": for Rockchip RK3288
@@ -120,7 +121,6 @@ uart2: serial@20064000 {
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&mux_uart2>;
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
diff --git a/dts/Bindings/pinctrl/sprd,pinctrl.txt b/dts/Bindings/pinctrl/sprd,pinctrl.txt
new file mode 100644
index 0000000000..b1cea7a3a0
--- /dev/null
+++ b/dts/Bindings/pinctrl/sprd,pinctrl.txt
@@ -0,0 +1,83 @@
+* Spreadtrum Pin Controller
+
+The Spreadtrum pin controller are organized in 3 blocks (types).
+
+The first block comprises some global control registers, and each
+register contains several bit fields with one bit or several bits
+to configure for some global common configuration, such as domain
+pad driving level, system control select and so on ("domain pad
+driving level": One pin can output 3.0v or 1.8v, depending on the
+related domain pad driving selection, if the related domain pad
+slect 3.0v, then the pin can output 3.0v. "system control" is used
+to choose one function (like: UART0) for which system, since we
+have several systems (AP/CP/CM4) on one SoC.).
+
+There are too much various configuration that we can not list all
+of them, so we can not make every Spreadtrum-special configuration
+as one generic configuration, and maybe it will add more strange
+global configuration in future. Then we add one "sprd,control" to
+set these various global control configuration, and we need use
+magic number for this property.
+
+Moreover we recognise every fields comprising one bit or several
+bits in one global control register as one pin, thus we should
+record every pin's bit offset, bit width and register offset to
+configure this field (pin).
+
+The second block comprises some common registers which have unified
+register definition, and each register described one pin is used
+to configure the pin sleep mode, function select and sleep related
+configuration.
+
+Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
+PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
+related configuration are:
+- input-enable
+- input-disable
+- output-high
+- output-low
+- bias-pull-up
+- bias-pull-down
+
+In some situation we need set the pin sleep mode and pin sleep related
+configuration, to set the pin sleep related configuration automatically
+by hardware when the system specified by sleep mode goes into deep
+sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP
+and set the pin sleep related configuration as "input-enable", which
+means when PUBCP system goes into deep sleep mode, this pin will be set
+input enable automatically.
+
+Moreover we can not use the "sleep" state, since some systems (like:
+PUBCP system) do not run linux kernel OS (only AP system run linux
+kernel on SC9860 platform), then we can not select "sleep" state
+when the PUBCP system goes into deep sleep mode. Thus we introduce
+"sprd,sleep-mode" property to set pin sleep mode.
+
+The last block comprises some misc registers which also have unified
+register definition, and each register described one pin is used to
+configure drive strength, pull up/down and so on. Especially for pull
+up, we have two kind pull up resistor: 20K and 4.7K.
+
+Required properties for Spreadtrum pin controller:
+- compatible: "sprd,<soc>-pinctrl"
+ Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs.
+- reg: The register address of pin controller device.
+- pins : An array of pin names.
+
+Optional properties:
+- function: Specified the function name.
+- drive-strength: Drive strength in mA.
+- input-schmitt-disable: Enable schmitt-trigger mode.
+- input-schmitt-enable: Disable schmitt-trigger mode.
+- bias-disable: Disable pin bias.
+- bias-pull-down: Pull down on pin.
+- bias-pull-up: Pull up on pin.
+- input-enable: Enable pin input.
+- input-disable: Enable pin output.
+- output-high: Set the pin as an output level high.
+- output-low: Set the pin as an output level low.
+- sleep-hardware-state: Indicate these configs in this state are sleep related.
+- sprd,control: Control values referring to databook for global control pins.
+- sprd,sleep-mode: Sleep mode selection.
+
+Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported values.
diff --git a/dts/Bindings/pinctrl/sprd,sc9860-pinctrl.txt b/dts/Bindings/pinctrl/sprd,sc9860-pinctrl.txt
new file mode 100644
index 0000000000..5a628333d5
--- /dev/null
+++ b/dts/Bindings/pinctrl/sprd,sc9860-pinctrl.txt
@@ -0,0 +1,70 @@
+* Spreadtrum SC9860 Pin Controller
+
+Please refer to sprd,pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: Must be "sprd,sc9860-pinctrl".
+- reg: The register address of pin controller device.
+- pins : An array of strings, each string containing the name of a pin.
+
+Optional properties:
+- function: A string containing the name of the function, values must be
+ one of: "func1", "func2", "func3" and "func4".
+- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
+ 12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33.
+- input-schmitt-disable: Enable schmitt-trigger mode.
+- input-schmitt-enable: Disable schmitt-trigger mode.
+- bias-disable: Disable pin bias.
+- bias-pull-down: Pull down on pin.
+- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
+ is 20K and 4700 for pull-up resistor is 4.7K.
+- input-enable: Enable pin input.
+- input-disable: Enable pin output.
+- output-high: Set the pin as an output level high.
+- output-low: Set the pin as an output level low.
+- sleep-hardware-state: Indicate these configs in this state are sleep related.
+- sprd,control: Control values referring to databook for global control pins.
+- sprd,sleep-mode: Choose the pin sleep mode, and supported values are:
+ AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP.
+
+Pin sleep mode definition:
+enum pin_sleep_mode {
+ AP_SLEEP = BIT(0),
+ PUBCP_SLEEP = BIT(1),
+ TGLDSP_SLEEP = BIT(2),
+ AGDSP_SLEEP = BIT(3),
+};
+
+Example:
+pin_controller: pinctrl@402a0000 {
+ compatible = "sprd,sc9860-pinctrl";
+ reg = <0x402a0000 0x10000>;
+
+ grp1: sd0 {
+ pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE";
+ sprd,control = <0x1>;
+ };
+
+ grp2: rfctl_33 {
+ pins = "SC9860_RFCTL33";
+ function = "func2";
+ sprd,sleep-mode = <AP_SLEEP | PUBCP_SLEEP>;
+ grp2_sleep_mode: rfctl_33_sleep {
+ pins = "SC9860_RFCTL33";
+ sleep-hardware-state;
+ output-low;
+ }
+ };
+
+ grp3: rfctl_misc_20 {
+ pins = "SC9860_RFCTL20_MISC";
+ drive-strength = <10>;
+ bias-pull-up = <4700>;
+ grp3_sleep_mode: rfctl_misc_sleep {
+ pins = "SC9860_RFCTL20_MISC";
+ sleep-hardware-state;
+ bias-pull-up;
+ }
+ };
+};
diff --git a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
index d907a74f8d..33e3d3c475 100644
--- a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
@@ -180,5 +180,4 @@ pin-controller {
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
- status = "okay";
};
diff --git a/dts/Bindings/power/power-controller.txt b/dts/Bindings/power/power-controller.txt
index 4f7a3bc9c4..e45affea80 100644
--- a/dts/Bindings/power/power-controller.txt
+++ b/dts/Bindings/power/power-controller.txt
@@ -13,6 +13,5 @@ Example:
act8846: act8846@5 {
compatible = "active-semi,act8846";
- status = "okay";
system-power-controller;
}
diff --git a/dts/Bindings/power/renesas,apmu.txt b/dts/Bindings/power/renesas,apmu.txt
index 84404c9edf..af21502e93 100644
--- a/dts/Bindings/power/renesas,apmu.txt
+++ b/dts/Bindings/power/renesas,apmu.txt
@@ -1,12 +1,13 @@
DT bindings for the Renesas Advanced Power Management Unit
-Renesas R-Car line of SoCs utilize one or more APMU hardware units
+Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units
for CPU core power domain control including SMP boot and CPU Hotplug.
Required properties:
- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
Examples with soctypes are:
+ - "renesas,r8a7743-apmu" (RZ/G1M)
- "renesas,r8a7790-apmu" (R-Car H2)
- "renesas,r8a7791-apmu" (R-Car M2-W)
- "renesas,r8a7792-apmu" (R-Car V2H)
diff --git a/dts/Bindings/power/renesas,rcar-sysc.txt b/dts/Bindings/power/renesas,rcar-sysc.txt
index d91715bc8d..98cc8c09d0 100644
--- a/dts/Bindings/power/renesas,rcar-sysc.txt
+++ b/dts/Bindings/power/renesas,rcar-sysc.txt
@@ -17,6 +17,7 @@ Required properties:
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
- "renesas,r8a7796-sysc" (R-Car M3-W)
+ - "renesas,r8a77995-sysc" (R-Car D3)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.
diff --git a/dts/Bindings/power/reset/st-reset.txt b/dts/Bindings/power/reset/st-reset.txt
index 83734dc3a3..b63948737d 100644
--- a/dts/Bindings/power/reset/st-reset.txt
+++ b/dts/Bindings/power/reset/st-reset.txt
@@ -8,5 +8,4 @@ Example node:
restart {
compatible = "st,stih407-restart";
st,syscfg = <&syscfg_sbc_reg>;
- status = "okay";
};
diff --git a/dts/Bindings/power/rockchip-io-domain.txt b/dts/Bindings/power/rockchip-io-domain.txt
index 43c21fb045..4a4766e9c2 100644
--- a/dts/Bindings/power/rockchip-io-domain.txt
+++ b/dts/Bindings/power/rockchip-io-domain.txt
@@ -39,6 +39,8 @@ Required properties:
- "rockchip,rk3368-pmu-io-voltage-domain" for rk3368 pmu-domains
- "rockchip,rk3399-io-voltage-domain" for rk3399
- "rockchip,rk3399-pmu-io-voltage-domain" for rk3399 pmu-domains
+ - "rockchip,rv1108-io-voltage-domain" for rv1108
+ - "rockchip,rv1108-pmu-io-voltage-domain" for rv1108 pmu-domains
Deprecated properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
diff --git a/dts/Bindings/power/supply/act8945a-charger.txt b/dts/Bindings/power/supply/act8945a-charger.txt
index de78d761ce..b86ecada4f 100644
--- a/dts/Bindings/power/supply/act8945a-charger.txt
+++ b/dts/Bindings/power/supply/act8945a-charger.txt
@@ -29,7 +29,6 @@ Example:
pmic@5b {
compatible = "active-semi,act8945a";
reg = <0x5b>;
- status = "okay";
charger {
compatible = "active-semi,act8945a-charger";
@@ -43,6 +42,5 @@ Example:
active-semi,input-voltage-threshold-microvolt = <6600>;
active-semi,precondition-timeout = <40>;
active-semi,total-timeout = <3>;
- status = "okay";
};
};
diff --git a/dts/Bindings/power/supply/bq24190.txt b/dts/Bindings/power/supply/bq24190.txt
new file mode 100644
index 0000000000..9e517d3070
--- /dev/null
+++ b/dts/Bindings/power/supply/bq24190.txt
@@ -0,0 +1,51 @@
+TI BQ24190 Li-Ion Battery Charger
+
+Required properties:
+- compatible: contains one of the following:
+ * "ti,bq24190"
+ * "ti,bq24192i"
+- reg: integer, I2C address of the charger.
+- interrupts[-extended]: configuration for charger INT pin.
+
+Optional properties:
+- monitored-battery: phandle of battery characteristics devicetree node
+ The charger uses the following battery properties:
+ + precharge-current-microamp: maximum charge current during precharge
+ phase (typically 20% of battery capacity).
+ + charge-term-current-microamp: a charge cycle terminates when the
+ battery voltage is above recharge threshold, and the current is below
+ this setting (typically 10% of battery capacity).
+ See also Documentation/devicetree/bindings/power/supply/battery.txt
+- ti,system-minimum-microvolt: when power is connected and the battery is below
+ minimum system voltage, the system will be regulated above this setting.
+
+Notes:
+- Some circuit boards wire the chip's "OTG" pin high (enabling 500mA default
+ charge current on USB SDP ports, among other features). To simulate this on
+ boards that wire the pin to a GPIO, set a gpio-hog.
+
+Example:
+
+ bat: battery {
+ compatible = "simple-battery";
+ precharge-current-microamp = <256000>;
+ charge-term-current-microamp = <128000>;
+ // etc.
+ };
+
+ bq24190: charger@6a {
+ compatible = "ti,bq24190";
+ reg = <0x6a>;
+ interrupts-extended = <&gpiochip 10 IRQ_TYPE_EDGE_FALLING>;
+ monitored-battery = <&bat>;
+ ti,system-minimum-microvolt = <3200000>;
+ };
+
+ &twl_gpio {
+ otg {
+ gpio-hog;
+ gpios = <6 0>;
+ output-high;
+ line-name = "otg-gpio";
+ };
+ };
diff --git a/dts/Bindings/power/supply/ltc2941.txt b/dts/Bindings/power/supply/ltc2941.txt
index a9d7aa6055..3b9ba147b0 100644
--- a/dts/Bindings/power/supply/ltc2941.txt
+++ b/dts/Bindings/power/supply/ltc2941.txt
@@ -1,13 +1,14 @@
-binding for LTC2941 and LTC2943 battery gauges
+binding for LTC2941, LTC2942, LTC2943 and LTC2944 battery gauges
-Both the LTC2941 and LTC2943 measure battery capacity.
-The LTC2943 is compatible with the LTC2941, it adds voltage and
-temperature monitoring, and uses a slightly different conversion
-formula for the charge counter.
+All chips measure battery capacity.
+The LTC2942 is pin compatible with the LTC2941, it adds voltage and
+temperature monitoring, and is runtime detected. LTC2943 and LTC2944
+is software compatible, uses a slightly different conversion formula
+for the charge counter and adds voltage, current and temperature monitoring.
Required properties:
-- compatible: Should contain "lltc,ltc2941" or "lltc,ltc2943" which also
- indicates the type of I2C chip attached.
+- compatible: Should contain "lltc,ltc2941", "lltc,ltc2942", "lltc,ltc2943"
+ or "lltc,ltc2944" which also indicates the type of I2C chip attached.
- reg: The 7-bit I2C address.
- lltc,resistor-sense: The sense resistor value in milli-ohms. Can be a 32-bit
negative value when the battery has been connected to the wrong end of the
diff --git a/dts/Bindings/power/supply/max8903-charger.txt b/dts/Bindings/power/supply/max8903-charger.txt
index f0f4e12b07..bab947fef0 100644
--- a/dts/Bindings/power/supply/max8903-charger.txt
+++ b/dts/Bindings/power/supply/max8903-charger.txt
@@ -21,5 +21,4 @@ Example:
flt-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
chg-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
cen-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
- status = "okay";
};
diff --git a/dts/Bindings/power/supply/maxim,max14656.txt b/dts/Bindings/power/supply/maxim,max14656.txt
index e03e85ae65..d6e8dfd0a5 100644
--- a/dts/Bindings/power/supply/maxim,max14656.txt
+++ b/dts/Bindings/power/supply/maxim,max14656.txt
@@ -12,7 +12,6 @@ Example:
clock-frequency = <50000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
max14656@35 {
compatible = "maxim,max14656";
diff --git a/dts/Bindings/power/wakeup-source.txt b/dts/Bindings/power/wakeup-source.txt
index 963c6dfd48..3c81f78b5c 100644
--- a/dts/Bindings/power/wakeup-source.txt
+++ b/dts/Bindings/power/wakeup-source.txt
@@ -20,13 +20,12 @@ List of legacy properties and respective binding document
1. "enable-sdio-wakeup" Documentation/devicetree/bindings/mmc/mmc.txt
2. "gpio-key,wakeup" Documentation/devicetree/bindings/input/gpio-keys{,-polled}.txt
3. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt
-4. "isil,irq2-can-wakeup-machine" Documentation/devicetree/bindings/rtc/isil,isl12057.txt
-5. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
+4. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
Documentation/devicetree/bindings/mfd/tc3589x.txt
Documentation/devicetree/bindings/input/ads7846.txt
-6. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
-7. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt
-8. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+5. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
+6. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt
+7. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
Examples
--------
diff --git a/dts/Bindings/powerpc/ibm,vas.txt b/dts/Bindings/powerpc/ibm,vas.txt
new file mode 100644
index 0000000000..bf11d2faf7
--- /dev/null
+++ b/dts/Bindings/powerpc/ibm,vas.txt
@@ -0,0 +1,22 @@
+* IBM Powerpc Virtual Accelerator Switchboard (VAS)
+
+VAS is a hardware mechanism that allows kernel subsystems and user processes
+to directly submit compression and other requests to Nest accelerators (NX)
+or other coprocessors functions.
+
+Required properties:
+- compatible : should be "ibm,vas".
+- ibm,vas-id : A unique identifier for each instance of VAS in the system
+- reg : Should contain 4 pairs of 64-bit fields specifying the Hypervisor
+ window context start and length, OS/User window context start and length,
+ "Paste address" start and length, "Paste window id" start bit and number
+ of bits)
+
+Example:
+
+ vas@6019100000000 {
+ compatible = "ibm,vas", "ibm,power9-vas";
+ reg = <0x6019100000000 0x2000000 0x6019000000000 0x100000000 0x8000000000000 0x100000000 0x20 0x10>;
+ name = "vas";
+ ibm,vas-id = <0x1>;
+ };
diff --git a/dts/Bindings/powerpc/opal/sensor-groups.txt b/dts/Bindings/powerpc/opal/sensor-groups.txt
new file mode 100644
index 0000000000..6ad881cbff
--- /dev/null
+++ b/dts/Bindings/powerpc/opal/sensor-groups.txt
@@ -0,0 +1,27 @@
+IBM OPAL Sensor Groups Binding
+-------------------------------
+
+Node: /ibm,opal/sensor-groups
+
+Description: Contains sensor groups available in the Powernv P9
+servers. Each child node indicates a sensor group.
+
+- compatible : Should be "ibm,opal-sensor-group"
+
+Each child node contains below properties:
+
+- type : String to indicate the type of sensor-group
+
+- sensor-group-id: Abstract unique identifier provided by firmware of
+ type <u32> which is used for sensor-group
+ operations like clearing the min/max history of all
+ sensors belonging to the group.
+
+- ibm,chip-id : Chip ID
+
+- sensors : Phandle array of child nodes of /ibm,opal/sensor/
+ belonging to this group
+
+- ops : Array of opal-call numbers indicating available operations on
+ sensor groups like clearing min/max, enabling/disabling sensor
+ group.
diff --git a/dts/Bindings/pps/pps-gpio.txt b/dts/Bindings/pps/pps-gpio.txt
index 40bf9c3564..0de23b7936 100644
--- a/dts/Bindings/pps/pps-gpio.txt
+++ b/dts/Bindings/pps/pps-gpio.txt
@@ -13,8 +13,12 @@ Optional properties:
Example:
pps {
- compatible = "pps-gpio";
- gpios = <&gpio2 6 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
assert-falling-edge;
+
+ compatible = "pps-gpio";
+ status = "okay";
};
diff --git a/dts/Bindings/ptp/brcm,ptp-dte.txt b/dts/Bindings/ptp/brcm,ptp-dte.txt
index 7c04e22a5d..6b1075ee8a 100644
--- a/dts/Bindings/ptp/brcm,ptp-dte.txt
+++ b/dts/Bindings/ptp/brcm,ptp-dte.txt
@@ -16,5 +16,4 @@ Example:
ptp: ptp-dte@180af650 {
compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
reg = <0x180af650 0x10>;
- status = "okay";
};
diff --git a/dts/Bindings/pwm/pwm-bcm2835.txt b/dts/Bindings/pwm/pwm-bcm2835.txt
index cf573e85b1..8cf87d1bfc 100644
--- a/dts/Bindings/pwm/pwm-bcm2835.txt
+++ b/dts/Bindings/pwm/pwm-bcm2835.txt
@@ -6,7 +6,7 @@ Required properties:
- clocks: This clock defines the base clock frequency of the PWM hardware
system, the period and the duty_cycle of the PWM signal is a multiple of
the base period.
-- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of
+- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
the cells format.
Examples:
@@ -15,7 +15,7 @@ pwm@2020c000 {
compatible = "brcm,bcm2835-pwm";
reg = <0x2020c000 0x28>;
clocks = <&clk_pwm>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
clocks {
diff --git a/dts/Bindings/pwm/pwm-mediatek.txt b/dts/Bindings/pwm/pwm-mediatek.txt
index 54c59b0560..ef8bd3cb67 100644
--- a/dts/Bindings/pwm/pwm-mediatek.txt
+++ b/dts/Bindings/pwm/pwm-mediatek.txt
@@ -2,6 +2,8 @@ MediaTek PWM controller
Required properties:
- compatible: should be "mediatek,<name>-pwm":
+ - "mediatek,mt2712-pwm": found on mt2712 SoC.
+ - "mediatek,mt7622-pwm": found on mt7622 SoC.
- "mediatek,mt7623-pwm": found on mt7623 SoC.
- reg: physical base address and length of the controller's registers.
- #pwm-cells: must be 2. See pwm.txt in this directory for a description of
@@ -10,7 +12,9 @@ Required properties:
- clock-names: must contain the following:
- "top": the top clock generator
- "main": clock used by the PWM core
- - "pwm1-5": the five per PWM clocks
+ - "pwm1-8": the eight per PWM clocks for mt2712
+ - "pwm1-6": the six per PWM clocks for mt7622
+ - "pwm1-5": the five per PWM clocks for mt7623
- pinctrl-names: Must contain a "default" entry.
- pinctrl-0: One property must exist for each entry in pinctrl-names.
See pinctrl/pinctrl-bindings.txt for details of the property values.
diff --git a/dts/Bindings/pwm/pwm-meson.txt b/dts/Bindings/pwm/pwm-meson.txt
index 5b07bebbf6..1ee81321c3 100644
--- a/dts/Bindings/pwm/pwm-meson.txt
+++ b/dts/Bindings/pwm/pwm-meson.txt
@@ -19,7 +19,6 @@ Example:
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x08550 0x0 0x10>;
#pwm-cells = <3>;
- status = "disabled";
clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
}
diff --git a/dts/Bindings/pwm/pwm-rockchip.txt b/dts/Bindings/pwm/pwm-rockchip.txt
index b8be3d09ee..2c5e52a5be 100644
--- a/dts/Bindings/pwm/pwm-rockchip.txt
+++ b/dts/Bindings/pwm/pwm-rockchip.txt
@@ -3,10 +3,17 @@ Rockchip PWM controller
Required properties:
- compatible: should be "rockchip,<name>-pwm"
"rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs
- "rockchip,rk3288-pwm": found on RK3288 SoC
+ "rockchip,rk3288-pwm": found on RK3288 SOC
+ "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC
"rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
- reg: physical base address and length of the controller's registers
- - clocks: phandle and clock specifier of the PWM reference clock
+ - clocks: See ../clock/clock-bindings.txt
+ - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):
+ - There is one clock that's used both to derive the functional clock
+ for the device and as the bus clock.
+ - For newer hardware (rk3328 and future socs): specified by name
+ - "pwm": This is used to derive the functional clock.
+ - "pclk": This is the APB bus clock.
- #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory
for a description of the cell format.
diff --git a/dts/Bindings/pwm/pwm-stm32-lp.txt b/dts/Bindings/pwm/pwm-stm32-lp.txt
new file mode 100644
index 0000000000..f8338d11fd
--- /dev/null
+++ b/dts/Bindings/pwm/pwm-stm32-lp.txt
@@ -0,0 +1,24 @@
+STMicroelectronics STM32 Low-Power Timer PWM
+
+STM32 Low-Power Timer provides single channel PWM.
+
+Must be a sub-node of an STM32 Low-Power Timer device tree node.
+See ../mfd/stm32-lptimer.txt for details about the parent node.
+
+Required parameters:
+- compatible: Must be "st,stm32-pwm-lp".
+
+Optional properties:
+- pinctrl-names: Set to "default".
+- pinctrl-0: Phandle pointing to pin configuration node for PWM.
+
+Example:
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ ...
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lppwm1_pins>;
+ };
+ };
diff --git a/dts/Bindings/pwm/pwm-sun4i.txt b/dts/Bindings/pwm/pwm-sun4i.txt
index f1cbeefb30..c5171660ea 100644
--- a/dts/Bindings/pwm/pwm-sun4i.txt
+++ b/dts/Bindings/pwm/pwm-sun4i.txt
@@ -19,5 +19,4 @@ Example:
reg = <0x01c20e00 0xc>;
clocks = <&osc24M>;
#pwm-cells = <3>;
- status = "disabled";
};
diff --git a/dts/Bindings/pwm/pwm-tiecap.txt b/dts/Bindings/pwm/pwm-tiecap.txt
index 8007e839a7..06a363d9cc 100644
--- a/dts/Bindings/pwm/pwm-tiecap.txt
+++ b/dts/Bindings/pwm/pwm-tiecap.txt
@@ -6,6 +6,7 @@ Required properties:
for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";
+ for 66ak2g - compatible = "ti,k2g-ecap", "ti,am3352-ecap";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The PWM channel index ranges from 0 to 4. The only third
cell flag supported by this binding is PWM_POLARITY_INVERTED.
diff --git a/dts/Bindings/pwm/pwm-tipwmss.txt b/dts/Bindings/pwm/pwm-tipwmss.txt
index 1a5d7b71db..4633697fbd 100644
--- a/dts/Bindings/pwm/pwm-tipwmss.txt
+++ b/dts/Bindings/pwm/pwm-tipwmss.txt
@@ -26,7 +26,6 @@ epwmss0: epwmss@48300000 { /* PWMSS for am33xx */
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
- status = "disabled";
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
0x48300180 0x48300180 0x80 /* EQEP */
0x48300200 0x48300200 0x80>; /* EHRPWM */
@@ -40,7 +39,6 @@ epwmss0: epwmss@48300000 { /* PWMSS for am4372 */
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
- status = "disabled";
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
0x48300180 0x48300180 0x80 /* EQEP */
0x48300200 0x48300200 0x80>; /* EHRPWM */
diff --git a/dts/Bindings/pwm/pwm-zx.txt b/dts/Bindings/pwm/pwm-zx.txt
new file mode 100644
index 0000000000..a6bcc75c91
--- /dev/null
+++ b/dts/Bindings/pwm/pwm-zx.txt
@@ -0,0 +1,22 @@
+ZTE ZX PWM controller
+
+Required properties:
+ - compatible: Should be "zte,zx296718-pwm".
+ - reg: Physical base address and length of the controller's registers.
+ - clocks : The phandle and specifier referencing the controller's clocks.
+ - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The
+ PCLK is for register access, while WCLK is the reference clock for
+ calculating period and duty cycles.
+ - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
+ the cells format.
+
+Example:
+
+ pwm: pwm@1439000 {
+ compatible = "zte,zx296718-pwm";
+ reg = <0x1439000 0x1000>;
+ clocks = <&lsp1crm LSP1_PWM_PCLK>,
+ <&lsp1crm LSP1_PWM_WCLK>;
+ clock-names = "pclk", "wclk";
+ #pwm-cells = <3>;
+ };
diff --git a/dts/Bindings/pwm/renesas,tpu-pwm.txt b/dts/Bindings/pwm/renesas,tpu-pwm.txt
index b067e84a94..1aadc804da 100644
--- a/dts/Bindings/pwm/renesas,tpu-pwm.txt
+++ b/dts/Bindings/pwm/renesas,tpu-pwm.txt
@@ -6,7 +6,6 @@ Required Properties:
- "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller.
- "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller.
- "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller.
- - "renesas,tpu-sh7372": for SH7372 (SH-Mobile AP4) compatible PWM controller.
- "renesas,tpu": for generic R-Car TPU PWM controller.
- reg: Base address and length of each memory resource used by the PWM
diff --git a/dts/Bindings/regulator/act8865-regulator.txt b/dts/Bindings/regulator/act8865-regulator.txt
index 6067d9830d..3ae9f10888 100644
--- a/dts/Bindings/regulator/act8865-regulator.txt
+++ b/dts/Bindings/regulator/act8865-regulator.txt
@@ -52,7 +52,6 @@ Example:
compatible = "active-semi,act8865";
reg = <0x5b>;
active-semi,vsel-high;
- status = "disabled";
regulators {
vcc_1v8_reg: DCDC_REG1 {
diff --git a/dts/Bindings/regulator/act8945a-regulator.txt b/dts/Bindings/regulator/act8945a-regulator.txt
index 5c80a77795..ac955dea00 100644
--- a/dts/Bindings/regulator/act8945a-regulator.txt
+++ b/dts/Bindings/regulator/act8945a-regulator.txt
@@ -23,7 +23,6 @@ Example:
pmic@5b {
compatible = "active-semi,act8945a";
reg = <0x5b>;
- status = "okay";
active-semi,vsel-high;
diff --git a/dts/Bindings/regulator/mt6311-regulator.txt b/dts/Bindings/regulator/mt6311-regulator.txt
index 02649d8b3f..84d544d8c1 100644
--- a/dts/Bindings/regulator/mt6311-regulator.txt
+++ b/dts/Bindings/regulator/mt6311-regulator.txt
@@ -1,4 +1,4 @@
-Mediatek MT6311 Regulator Driver
+Mediatek MT6311 Regulator
Required properties:
- compatible: "mediatek,mt6311-regulator"
diff --git a/dts/Bindings/regulator/mt6323-regulator.txt b/dts/Bindings/regulator/mt6323-regulator.txt
index c35d878b09..a48749db4d 100644
--- a/dts/Bindings/regulator/mt6323-regulator.txt
+++ b/dts/Bindings/regulator/mt6323-regulator.txt
@@ -1,4 +1,4 @@
-Mediatek MT6323 Regulator Driver
+Mediatek MT6323 Regulator
All voltage regulators are defined as subnodes of the regulators node. A list
of regulators provided by this controller are defined as subnodes of the
diff --git a/dts/Bindings/regulator/mt6380-regulator.txt b/dts/Bindings/regulator/mt6380-regulator.txt
new file mode 100644
index 0000000000..0058441f16
--- /dev/null
+++ b/dts/Bindings/regulator/mt6380-regulator.txt
@@ -0,0 +1,89 @@
+MediaTek MT6380 Regulator
+
+All voltage regulators provided by the MT6380 PMIC are described as the
+subnodes of the MT6380 regulators node. Each regulator is named according
+to its regulator type, buck-<name> and ldo-<name>. The definition for each
+of these nodes is defined using the standard binding for regulators at
+Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are:
+BUCK:
+ buck-core1, buck-vcore, buck-vrf
+LDO:
+ ldo-vm ,ldo-va , ldo-vphy, ldo-vddr, ldo-vt
+
+Example:
+
+ regulators {
+ compatible = "mediatek,mt6380-regulator";
+
+ mt6380_vcpu_reg: buck-vcore1 {
+ regulator-name = "vcore1";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1393750>;
+ regulator-ramp-delay = <6250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vcore_reg: buck-vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1393750>;
+ regulator-ramp-delay = <6250>;
+ };
+
+ mt6380_vrf_reg: buck-vrf {
+ regulator-name = "vrf";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1575000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vm_reg: ldo-vm {
+ regulator-name = "vm";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_va_reg: ldo-va {
+ regulator-name = "va";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vphy_reg: ldo-vphy {
+ regulator-name = "vphy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vddr_reg: ldo-vddr {
+ regulator-name = "vddr";
+ regulator-min-microvolt = <1240000>;
+ regulator-max-microvolt = <1840000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vt_reg: ldo-vt {
+ regulator-name = "vt";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
diff --git a/dts/Bindings/regulator/mt6397-regulator.txt b/dts/Bindings/regulator/mt6397-regulator.txt
index a42b1d6e98..01141fb008 100644
--- a/dts/Bindings/regulator/mt6397-regulator.txt
+++ b/dts/Bindings/regulator/mt6397-regulator.txt
@@ -1,4 +1,4 @@
-Mediatek MT6397 Regulator Driver
+Mediatek MT6397 Regulator
Required properties:
- compatible: "mediatek,mt6397-regulator"
diff --git a/dts/Bindings/regulator/pwm-regulator.txt b/dts/Bindings/regulator/pwm-regulator.txt
index bf85aa9ad6..3d78d507e2 100644
--- a/dts/Bindings/regulator/pwm-regulator.txt
+++ b/dts/Bindings/regulator/pwm-regulator.txt
@@ -71,7 +71,7 @@ Continuous Voltage With Enable GPIO Example:
* Inverted PWM logic, and the duty cycle range is limited
* to 30%-70%.
*/
- pwm-dutycycle-range <700 300>; /* */
+ pwm-dutycycle-range = <700 300>; /* */
};
Voltage Table Example:
diff --git a/dts/Bindings/regulator/st,stm32-vrefbuf.txt b/dts/Bindings/regulator/st,stm32-vrefbuf.txt
new file mode 100644
index 0000000000..3944ee3e73
--- /dev/null
+++ b/dts/Bindings/regulator/st,stm32-vrefbuf.txt
@@ -0,0 +1,20 @@
+STM32 VREFBUF - Voltage reference buffer
+
+Some STM32 devices embed a voltage reference buffer which can be used as
+voltage reference for ADCs, DACs and also as voltage reference for external
+components through the dedicated VREF+ pin.
+
+Required properties:
+- compatible: Must be "st,stm32-vrefbuf".
+- reg: Offset and length of VREFBUF register set.
+- clocks: Must contain an entry for peripheral clock.
+
+Example:
+ vrefbuf: regulator@58003C00 {
+ compatible = "st,stm32-vrefbuf";
+ reg = <0x58003C00 0x8>;
+ clocks = <&rcc VREF_CK>;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2500000>;
+ vdda-supply = <&vdda>;
+ };
diff --git a/dts/Bindings/remoteproc/imx-rproc.txt b/dts/Bindings/remoteproc/imx-rproc.txt
new file mode 100644
index 0000000000..fbcefd965d
--- /dev/null
+++ b/dts/Bindings/remoteproc/imx-rproc.txt
@@ -0,0 +1,33 @@
+NXP iMX6SX/iMX7D Co-Processor Bindings
+----------------------------------------
+
+This binding provides support for ARM Cortex M4 Co-processor found on some
+NXP iMX SoCs.
+
+Required properties:
+- compatible Should be one of:
+ "fsl,imx7d-cm4"
+ "fsl,imx6sx-cm4"
+- clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
+- syscon Phandle to syscon block which provide access to
+ System Reset Controller
+
+Optional properties:
+- memory-region list of phandels to the reserved memory regions.
+ (See: ../reserved-memory/reserved-memory.txt)
+
+Example:
+ m4_reserved_sysmem1: cm4@80000000 {
+ reg = <0x80000000 0x80000>;
+ };
+
+ m4_reserved_sysmem2: cm4@81000000 {
+ reg = <0x81000000 0x80000>;
+ };
+
+ imx7d-cm4 {
+ compatible = "fsl,imx7d-cm4";
+ memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>;
+ syscon = <&src>;
+ clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>;
+ };
diff --git a/dts/Bindings/remoteproc/qcom,adsp.txt b/dts/Bindings/remoteproc/qcom,adsp.txt
index 75ad7b8df0..728e4193f7 100644
--- a/dts/Bindings/remoteproc/qcom,adsp.txt
+++ b/dts/Bindings/remoteproc/qcom,adsp.txt
@@ -63,9 +63,10 @@ on the Qualcomm ADSP Hexagon core.
= SUBNODES
-The adsp node may have an subnode named "smd-edge" that describes the SMD edge,
-channels and devices related to the ADSP. See ../soc/qcom/qcom,smd.txt for
-details on how to describe the SMD edge.
+The adsp node may have an subnode named either "smd-edge" or "glink-edge" that
+describes the communication edge, channels and devices related to the ADSP.
+See ../soc/qcom/qcom,smd.txt and ../soc/qcom/qcom,glink.txt for details on how
+to describe these.
= EXAMPLE
diff --git a/dts/Bindings/remoteproc/qcom,q6v5.txt b/dts/Bindings/remoteproc/qcom,q6v5.txt
index 92347fe689..7ff3f7903f 100644
--- a/dts/Bindings/remoteproc/qcom,q6v5.txt
+++ b/dts/Bindings/remoteproc/qcom,q6v5.txt
@@ -90,6 +90,11 @@ the memory regions used by the Hexagon firmware. Each sub-node must contain:
Value type: <phandle>
Definition: reference to the reserved-memory for the region
+The Hexagon node may also have an subnode named either "smd-edge" or
+"glink-edge" that describes the communication edge, channels and devices
+related to the Hexagon. See ../soc/qcom/qcom,smd.txt and
+../soc/qcom/qcom,glink.txt for details on how to describe these.
+
= EXAMPLE
The following example describes the resources needed to boot control the
Hexagon, as it is found on MSM8974 boards.
diff --git a/dts/Bindings/remoteproc/ti,davinci-rproc.txt b/dts/Bindings/remoteproc/ti,davinci-rproc.txt
new file mode 100644
index 0000000000..e44a97e211
--- /dev/null
+++ b/dts/Bindings/remoteproc/ti,davinci-rproc.txt
@@ -0,0 +1,86 @@
+TI Davinci DSP devices
+=======================
+
+Binding status: Unstable - Subject to changes for DT representation of clocks
+ and resets
+
+The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
+is used to offload some of the processor-intensive tasks or algorithms, for
+achieving various system level goals.
+
+The processor cores in the sub-system usually contain additional sub-modules
+like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
+controller, a dedicated local power/sleep controller etc. The DSP processor
+core used in Davinci SoCs is usually a C674x DSP CPU.
+
+DSP Device Node:
+================
+Each DSP Core sub-system is represented as a single DT node.
+
+Required properties:
+--------------------
+The following are the mandatory properties:
+
+- compatible: Should be one of the following,
+ "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
+
+- reg: Should contain an entry for each value in 'reg-names'.
+ Each entry should have the memory region's start address
+ and the size of the region, the representation matching
+ the parent node's '#address-cells' and '#size-cells' values.
+
+- reg-names: Should contain strings with the following names, each
+ representing a specific internal memory region or a
+ specific register space,
+ "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig_base"
+
+- interrupts: Should contain the interrupt number used to receive the
+ interrupts from the DSP. The value should follow the
+ interrupt-specifier format as dictated by the
+ 'interrupt-parent' node.
+
+- memory-region: phandle to the reserved memory node to be associated
+ with the remoteproc device. The reserved memory node
+ can be a CMA memory node, and should be defined as
+ per the bindings in
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+
+Optional properties:
+--------------------
+- interrupt-parent: phandle to the interrupt controller node. This property
+ is needed if the device node hierarchy doesn't have an
+ interrupt controller.
+
+
+Example:
+--------
+
+ /* DSP Reserved Memory node */
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dsp_memory_region: dsp-memory@c3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0xc3000000 0x1000000>;
+ reusable;
+ };
+ };
+
+ /* DSP node */
+ {
+ dsp: dsp@11800000 {
+ compatible = "ti,da850-dsp";
+ reg = <0x11800000 0x40000>,
+ <0x11e00000 0x8000>,
+ <0x11f00000 0x8000>,
+ <0x01c14044 0x4>,
+ <0x01c14174 0x8>;
+ reg-names = "l2sram", "l1pram", "l1dram", "host1cfg",
+ "chipsig";
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ memory-region = <&dsp_memory_region>;
+ };
+ };
diff --git a/dts/Bindings/remoteproc/ti,keystone-rproc.txt b/dts/Bindings/remoteproc/ti,keystone-rproc.txt
index 2aac1aa412..1eb7287413 100644
--- a/dts/Bindings/remoteproc/ti,keystone-rproc.txt
+++ b/dts/Bindings/remoteproc/ti,keystone-rproc.txt
@@ -26,6 +26,7 @@ The following are the mandatory properties:
"ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
"ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
"ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
+ "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
- reg: Should contain an entry for each value in 'reg-names'.
Each entry should have the memory region's start address
@@ -37,20 +38,18 @@ The following are the mandatory properties:
should be defined in this order,
"l2sram", "l1pram", "l1dram"
-- clocks: Should contain the device's input clock, and should be
- defined as per the bindings in,
- Documentation/devicetree/bindings/clock/keystone-gate.txt
-
- ti,syscon-dev: Should be a pair of the phandle to the Keystone Device
State Control node, and the register offset of the DSP
boot address register within that node's address space.
- resets: Should contain the phandle to the reset controller node
managing the resets for this device, and a reset
- specifier. Please refer to the following reset bindings
- for the reset argument specifier as per SoC,
+ specifier. Please refer to either of the following reset
+ bindings for the reset argument specifier as per SoC,
Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
- for 66AK2HK/66AK2L/66AK2E SoCs
+ for 66AK2HK/66AK2L/66AK2E SoCs or,
+ Documentation/devicetree/bindings/reset/ti,sci-reset.txt
+ for 66AK2G SoCs
- interrupt-parent: Should contain a phandle to the Keystone 2 IRQ controller
IP node that is used by the ARM CorePac processor to
@@ -75,6 +74,22 @@ The following are the mandatory properties:
The gpio device to be used is as per the bindings in,
Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
+SoC-specific Required properties:
+---------------------------------
+The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E
+SoCs only:
+
+- clocks: Should contain the device's input clock, and should be
+ defined as per the bindings in,
+ Documentation/devicetree/bindings/clock/keystone-gate.txt
+
+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
+
+- power-domains: Should contain a phandle to a PM domain provider node
+ and an args specifier containing the DSP device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
Optional properties:
--------------------
@@ -85,8 +100,10 @@ Optional properties:
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
-Example:
---------
+Examples:
+---------
+
+1.
/* 66AK2H/K DSP aliases */
aliases {
rproc0 = &dsp0;
@@ -131,3 +148,41 @@ Example:
};
};
+
+2.
+ /* 66AK2G DSP alias */
+ aliases {
+ rproc0 = &dsp0;
+ };
+
+ /* 66AK2G DSP memory node */
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_common_memory: dsp-common-memory@81f800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
+ reusable;
+ };
+ };
+
+ /* 66AK2G DSP node */
+ soc {
+ dsp0: dsp@10800000 {
+ compatible = "ti,k2g-dsp";
+ reg = <0x10800000 0x00100000>,
+ <0x10e00000 0x00008000>,
+ <0x10f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ power-domains = <&k2g_pds 0x0046>;
+ ti,syscon-dev = <&devctrl 0x40>;
+ resets = <&k2g_reset 0x0046 0x1>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <0 8>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio0 27 0>;
+ memory-region = <&dsp_common_memory>;
+ };
+ };
diff --git a/dts/Bindings/reset/lantiq,reset.txt b/dts/Bindings/reset/lantiq,reset.txt
new file mode 100644
index 0000000000..c6aef36b7d
--- /dev/null
+++ b/dts/Bindings/reset/lantiq,reset.txt
@@ -0,0 +1,30 @@
+Lantiq XWAY SoC RCU reset controller binding
+============================================
+
+This binding describes a reset-controller found on the RCU module on Lantiq
+XWAY SoCs.
+
+This node has to be a sub node of the Lantiq RCU block.
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,danube-reset"
+ "lantiq,xrx200-reset"
+- reg : Defines the following sets of registers in the parent
+ syscon device
+ - Offset of the reset set register
+ - Offset of the reset status register
+- #reset-cells : Specifies the number of cells needed to encode the
+ reset line, should be 2.
+ The first cell takes the reset set bit and the
+ second cell takes the status bit.
+
+-------------------------------------------------------------------------------
+Example for the reset-controllers on the xRX200 SoCs:
+ reset0: reset-controller@10 {
+ compatible = "lantiq,xrx200-reset";
+ reg <0x10 0x04>, <0x14 0x04>;
+
+ #reset-cells = <2>;
+ };
diff --git a/dts/Bindings/reset/nxp,lpc1850-rgu.txt b/dts/Bindings/reset/nxp,lpc1850-rgu.txt
index b4e96a2784..05d5be48da 100644
--- a/dts/Bindings/reset/nxp,lpc1850-rgu.txt
+++ b/dts/Bindings/reset/nxp,lpc1850-rgu.txt
@@ -80,5 +80,4 @@ mac: ethernet@40010000 {
clock-names = "stmmaceth";
resets = <&rgu 22>;
reset-names = "stmmaceth";
- status = "disabled";
};
diff --git a/dts/Bindings/reset/renesas,rst.txt b/dts/Bindings/reset/renesas,rst.txt
index fe5e0f37b3..e5a03ffe04 100644
--- a/dts/Bindings/reset/renesas,rst.txt
+++ b/dts/Bindings/reset/renesas,rst.txt
@@ -26,6 +26,7 @@ Required properties:
- "renesas,r8a7794-rst" (R-Car E2)
- "renesas,r8a7795-rst" (R-Car H3)
- "renesas,r8a7796-rst" (R-Car M3-W)
+ - "renesas,r8a77995-rst" (R-Car D3)
- reg: Address start and address range for the device.
diff --git a/dts/Bindings/reset/uniphier-reset.txt b/dts/Bindings/reset/uniphier-reset.txt
index 83ab0f599c..68a6f487c4 100644
--- a/dts/Bindings/reset/uniphier-reset.txt
+++ b/dts/Bindings/reset/uniphier-reset.txt
@@ -6,7 +6,6 @@ System reset
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-reset" - for sLD3 SoC
"socionext,uniphier-ld4-reset" - for LD4 SoC
"socionext,uniphier-pro4-reset" - for Pro4 SoC
"socionext,uniphier-sld8-reset" - for sLD8 SoC
@@ -37,7 +36,6 @@ Media I/O (MIO) reset, SD reset
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC
"socionext,uniphier-ld4-mio-reset" - for LD4 SoC
"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC
"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC
@@ -92,3 +90,28 @@ Example:
other nodes ...
};
+
+
+Analog signal amplifier reset
+-----------------------------
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-ld11-adamv-reset" - for LD11 SoC
+ "socionext,uniphier-ld20-adamv-reset" - for LD20 SoC
+- #reset-cells: should be 1.
+
+Example:
+
+ adamv@57920000 {
+ compatible = "socionext,uniphier-ld11-adamv",
+ "simple-mfd", "syscon";
+ reg = <0x57920000 0x1000>;
+
+ adamv_rst: reset {
+ compatible = "socionext,uniphier-ld11-adamv-reset";
+ #reset-cells = <1>;
+ };
+
+ other nodes ...
+ };
diff --git a/dts/Bindings/rng/imx-rngc.txt b/dts/Bindings/rng/imx-rngc.txt
new file mode 100644
index 0000000000..93c7174a7b
--- /dev/null
+++ b/dts/Bindings/rng/imx-rngc.txt
@@ -0,0 +1,21 @@
+Freescale RNGC (Random Number Generator Version C)
+
+The driver also supports version B, which is mostly compatible
+to version C.
+
+Required properties:
+- compatible : should be one of
+ "fsl,imx25-rngb"
+ "fsl,imx35-rngc"
+- reg : offset and length of the register set of this block
+- interrupts : the interrupt number for the RNGC block
+- clocks : the RNGC clk source
+
+Example:
+
+rng@53fb0000 {
+ compatible = "fsl,imx25-rngb";
+ reg = <0x53fb0000 0x4000>;
+ interrupts = <22>;
+ clocks = <&trng_clk>;
+};
diff --git a/dts/Bindings/rtc/google,goldfish-rtc.txt b/dts/Bindings/rtc/google,goldfish-rtc.txt
new file mode 100644
index 0000000000..634312dd95
--- /dev/null
+++ b/dts/Bindings/rtc/google,goldfish-rtc.txt
@@ -0,0 +1,17 @@
+Android Goldfish RTC
+
+Android Goldfish RTC device used by Android emulator.
+
+Required properties:
+
+- compatible : should contain "google,goldfish-rtc"
+- reg : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+ goldfish_timer@9020000 {
+ compatible = "google,goldfish-rtc";
+ reg = <0x9020000 0x1000>;
+ interrupts = <0x3>;
+ };
diff --git a/dts/Bindings/rtc/isil,isl12057.txt b/dts/Bindings/rtc/isil,isl12057.txt
index cf83e09403..fbbdd92e5a 100644
--- a/dts/Bindings/rtc/isil,isl12057.txt
+++ b/dts/Bindings/rtc/isil,isl12057.txt
@@ -24,7 +24,6 @@ Optional properties:
- "wakeup-source": mark the chip as a wakeup source, independently of
the availability of an IRQ line connected to the SoC.
- (Legacy property supported: "isil,irq2-can-wakeup-machine")
- "interrupt-parent", "interrupts": for passing the interrupt line
of the SoC connected to IRQ#2 of the RTC chip.
diff --git a/dts/Bindings/rtc/realtek,rtd119x.txt b/dts/Bindings/rtc/realtek,rtd119x.txt
new file mode 100644
index 0000000000..bbf1ccb5df
--- /dev/null
+++ b/dts/Bindings/rtc/realtek,rtd119x.txt
@@ -0,0 +1,16 @@
+Realtek RTD129x Real-Time Clock
+===============================
+
+Required properties:
+- compatible : Should be "realtek,rtd1295-rtc"
+- reg : Specifies the physical base address and size
+- clocks : Specifies the clock gate
+
+
+Example:
+
+ rtc@9801b600 {
+ compatible = "realtek,rtd1295-clk";
+ reg = <0x9801b600 0x100>;
+ clocks = <&clkc RTD1295_CLK_EN_MISC_RTC>;
+ };
diff --git a/dts/Bindings/rtc/st,stm32-rtc.txt b/dts/Bindings/rtc/st,stm32-rtc.txt
index 0a4c371a9b..a66692a08a 100644
--- a/dts/Bindings/rtc/st,stm32-rtc.txt
+++ b/dts/Bindings/rtc/st,stm32-rtc.txt
@@ -45,5 +45,4 @@ Example:
interrupts = <17 1>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg>;
- status = "disabled";
};
diff --git a/dts/Bindings/rtc/sun6i-rtc.txt b/dts/Bindings/rtc/sun6i-rtc.txt
index 945934918b..d5e26d313f 100644
--- a/dts/Bindings/rtc/sun6i-rtc.txt
+++ b/dts/Bindings/rtc/sun6i-rtc.txt
@@ -10,7 +10,7 @@ Required properties:
Required properties for new device trees
- clocks : phandle to the 32kHz external oscillator
-- clock-output-names : name of the LOSC clock created
+- clock-output-names : names of the LOSC and its external output clocks created
- #clock-cells : must be equals to 1. The RTC provides two clocks: the
LOSC and its external output, with index 0 and 1
respectively.
@@ -21,7 +21,7 @@ rtc: rtc@01f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <0 40 4>, <0 41 4>;
- clock-output-names = "osc32k";
+ clock-output-names = "osc32k", "osc32k-out";
clocks = <&ext_osc32k>;
#clock-cells = <1>;
};
diff --git a/dts/Bindings/scsi/hisilicon-sas.txt b/dts/Bindings/scsi/hisilicon-sas.txt
index 2a42a323fa..b6a869f977 100644
--- a/dts/Bindings/scsi/hisilicon-sas.txt
+++ b/dts/Bindings/scsi/hisilicon-sas.txt
@@ -85,5 +85,4 @@ Example:
<366 1>,<367 1>/* cq30-31 */
<376 4>,/* fatal ecc */
<381 4>;/* fatal axi */
- status = "disabled";
};
diff --git a/dts/Bindings/security/tpm/st33zp24-i2c.txt b/dts/Bindings/security/tpm/st33zp24-i2c.txt
index 3ad115efed..6a4e0d30d8 100644
--- a/dts/Bindings/security/tpm/st33zp24-i2c.txt
+++ b/dts/Bindings/security/tpm/st33zp24-i2c.txt
@@ -19,7 +19,6 @@ Example (for ARM-based BeagleBoard xM with ST33ZP24 on I2C2):
&i2c2 {
- status = "okay";
st33zp24: st33zp24@13 {
diff --git a/dts/Bindings/security/tpm/st33zp24-spi.txt b/dts/Bindings/security/tpm/st33zp24-spi.txt
index 158b0165e0..604dce901b 100644
--- a/dts/Bindings/security/tpm/st33zp24-spi.txt
+++ b/dts/Bindings/security/tpm/st33zp24-spi.txt
@@ -18,7 +18,6 @@ Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4):
&mcspi4 {
- status = "okay";
st33zp24@0 {
diff --git a/dts/Bindings/security/tpm/tpm-i2c.txt b/dts/Bindings/security/tpm/tpm-i2c.txt
index 8cb638b7e8..3eca6de636 100644
--- a/dts/Bindings/security/tpm/tpm-i2c.txt
+++ b/dts/Bindings/security/tpm/tpm-i2c.txt
@@ -17,5 +17,4 @@ tpm@57 {
compatible = "nuvoton,npct650", "nuvoton,npct601";
linux,sml-base = <0x7f 0xfd450000>;
linux,sml-size = <0x10000>;
- status = "okay";
};
diff --git a/dts/Bindings/security/tpm/tpm_tis_spi.txt b/dts/Bindings/security/tpm/tpm_tis_spi.txt
index 85741cd468..b800667da9 100644
--- a/dts/Bindings/security/tpm/tpm_tis_spi.txt
+++ b/dts/Bindings/security/tpm/tpm_tis_spi.txt
@@ -13,7 +13,6 @@ Example (for ARM-based BeagleBoard xM with TPM_TIS on SPI4):
&mcspi4 {
- status = "okay";
tpm_tis@0 {
diff --git a/dts/Bindings/serial/8250.txt b/dts/Bindings/serial/8250.txt
index 419ff6c0a4..dad3b2ec66 100644
--- a/dts/Bindings/serial/8250.txt
+++ b/dts/Bindings/serial/8250.txt
@@ -14,6 +14,8 @@ Required properties:
tegra132, or tegra210.
- "nxp,lpc3220-uart"
- "ralink,rt2880-uart"
+ - For MediaTek BTIF, must contain '"mediatek,<chip>-btif",
+ "mediatek,mtk-btif"' where <chip> is mt7622, mt7623.
- "altr,16550-FIFO32"
- "altr,16550-FIFO64"
- "altr,16550-FIFO128"
diff --git a/dts/Bindings/serial/arc-uart.txt b/dts/Bindings/serial/arc-uart.txt
index 5cae2eb686..256cc150ca 100644
--- a/dts/Bindings/serial/arc-uart.txt
+++ b/dts/Bindings/serial/arc-uart.txt
@@ -15,7 +15,6 @@ arcuart0: serial@c0fc1000 {
interrupts = <5>;
clock-frequency = <80000000>;
current-speed = <115200>;
- status = "okay";
};
Note: Each port should have an alias correctly numbered in "aliases" node.
diff --git a/dts/Bindings/serial/axis,etraxfs-uart.txt b/dts/Bindings/serial/axis,etraxfs-uart.txt
index 51b3c9e80a..048c3818c8 100644
--- a/dts/Bindings/serial/axis,etraxfs-uart.txt
+++ b/dts/Bindings/serial/axis,etraxfs-uart.txt
@@ -15,7 +15,6 @@ serial@b00260000 {
compatible = "axis,etraxfs-uart";
reg = <0xb0026000 0x1000>;
interrupts = <68>;
- status = "disabled";
dtr-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
rng-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
index b6cf384597..f73abff3de 100644
--- a/dts/Bindings/serial/mtk-uart.txt
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
Required properties:
- compatible should contain:
* "mediatek,mt2701-uart" for MT2701 compatible UARTS
+ * "mediatek,mt2712-uart" for MT2712 compatible UARTS
* "mediatek,mt6580-uart" for MT6580 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
diff --git a/dts/Bindings/serial/nvidia,tegra20-hsuart.txt b/dts/Bindings/serial/nvidia,tegra20-hsuart.txt
index c93a2d1c1a..d7edf732eb 100644
--- a/dts/Bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/dts/Bindings/serial/nvidia,tegra20-hsuart.txt
@@ -33,5 +33,4 @@ serial@70006000 {
reset-names = "serial";
dmas = <&apbdma 8>, <&apbdma 8>;
dma-names = "rx", "tx";
- status = "disabled";
};
diff --git a/dts/Bindings/serial/qcom,msm-uartdm.txt b/dts/Bindings/serial/qcom,msm-uartdm.txt
index d5f73b8f61..9d098cf73b 100644
--- a/dts/Bindings/serial/qcom,msm-uartdm.txt
+++ b/dts/Bindings/serial/qcom,msm-uartdm.txt
@@ -72,13 +72,10 @@ Examples:
};
uarta: serial@12490000 {
- status = "ok";
};
uartb: serial@16340000 {
- status = "ok";
};
uartc: serial@1a240000 {
- status = "ok";
};
diff --git a/dts/Bindings/serial/renesas,sci-serial.txt b/dts/Bindings/serial/renesas,sci-serial.txt
index 8d27d1a603..4fc96946f8 100644
--- a/dts/Bindings/serial/renesas,sci-serial.txt
+++ b/dts/Bindings/serial/renesas,sci-serial.txt
@@ -41,6 +41,8 @@ Required properties:
- "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
- "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART.
- "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
+ - "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART.
+ - "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART.
- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
- "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
- "renesas,rcar-gen1-scif" for R-Car Gen1 SCIF compatible UART,
diff --git a/dts/Bindings/serial/rs485.txt b/dts/Bindings/serial/rs485.txt
index 32b1fa1f2a..b8415936df 100644
--- a/dts/Bindings/serial/rs485.txt
+++ b/dts/Bindings/serial/rs485.txt
@@ -5,14 +5,13 @@ the built-in half-duplex mode.
The properties described hereafter shall be given to a half-duplex capable
UART node.
-Required properties:
+Optional properties:
- rs485-rts-delay: prop-encoded-array <a b> where:
* a is the delay between rts signal and beginning of data sent in milliseconds.
it corresponds to the delay before sending data.
* b is the delay between end of data sent and rts signal in milliseconds
it corresponds to the delay after sending data and actual release of the line.
-
-Optional properties:
+ If this property is not specified, <0 0> is assumed.
- linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485
feature at boot time. It can be disabled later with proper ioctl.
- rs485-rx-during-tx: empty property that enables the receiving of data even
diff --git a/dts/Bindings/serial/serial.txt b/dts/Bindings/serial/serial.txt
index b542a0ecf0..863c289375 100644
--- a/dts/Bindings/serial/serial.txt
+++ b/dts/Bindings/serial/serial.txt
@@ -43,7 +43,6 @@ Examples:
rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
- status = "okay";
};
scifa4: serial@e6c80000 {
@@ -54,5 +53,4 @@ Examples:
clock-names = "fck";
power-domains = <&pd_a3sp>;
uart-has-rtscts;
- status = "okay";
};
diff --git a/dts/Bindings/serial/st,stm32-usart.txt b/dts/Bindings/serial/st,stm32-usart.txt
index 85ec5f2b19..3657f9f9d1 100644
--- a/dts/Bindings/serial/st,stm32-usart.txt
+++ b/dts/Bindings/serial/st,stm32-usart.txt
@@ -1,12 +1,19 @@
* STMicroelectronics STM32 USART
Required properties:
-- compatible: Can be either "st,stm32-usart", "st,stm32-uart",
-"st,stm32f7-usart" or "st,stm32f7-uart" depending on whether
-the device supports synchronous mode and is compatible with
-stm32(f4) or stm32f7.
+- compatible: can be either:
+ - "st,stm32-usart",
+ - "st,stm32-uart",
+ - "st,stm32f7-usart",
+ - "st,stm32f7-uart",
+ - "st,stm32h7-usart"
+ - "st,stm32h7-uart".
+ depending on whether the device supports synchronous mode
+ and is compatible with stm32(f4), stm32f7 or stm32h7.
- reg: The address and length of the peripheral registers space
-- interrupts: The interrupt line of the USART instance
+- interrupts:
+ - The interrupt line for the USART instance,
+ - An optional wake-up interrupt.
- clocks: The input clock of the USART instance
Optional properties:
diff --git a/dts/Bindings/serio/allwinner,sun4i-ps2.txt b/dts/Bindings/serio/allwinner,sun4i-ps2.txt
index 362a76925b..f311472990 100644
--- a/dts/Bindings/serio/allwinner,sun4i-ps2.txt
+++ b/dts/Bindings/serio/allwinner,sun4i-ps2.txt
@@ -19,5 +19,4 @@ Example:
reg = <0x01c2a000 0x400>;
interrupts = <0 62 4>;
clocks = <&apb1_gates 6>;
- status = "disabled";
};
diff --git a/dts/Bindings/serio/ps2-gpio.txt b/dts/Bindings/serio/ps2-gpio.txt
new file mode 100644
index 0000000000..7b7bc9cdf9
--- /dev/null
+++ b/dts/Bindings/serio/ps2-gpio.txt
@@ -0,0 +1,23 @@
+Device-Tree binding for ps/2 gpio device
+
+Required properties:
+ - compatible = "ps2-gpio"
+ - data-gpios: the data pin
+ - clk-gpios: the clock pin
+ - interrupts: Should trigger on the falling edge of the clock line.
+
+Optional properties:
+ - write-enable: Indicates whether write function is provided
+ to serio device. Possibly providing the write fn will not work, because
+ of the tough timing requirements.
+
+Example nodes:
+
+ps2@0 {
+ compatible = "ps2-gpio";
+ interrupt-parent = <&gpio>;
+ interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+ data-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ clk-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ write-enable;
+};
diff --git a/dts/Bindings/soc/mediatek/scpsys.txt b/dts/Bindings/soc/mediatek/scpsys.txt
index b1d165b4d4..40056f7990 100644
--- a/dts/Bindings/soc/mediatek/scpsys.txt
+++ b/dts/Bindings/soc/mediatek/scpsys.txt
@@ -12,11 +12,13 @@ power/power_domain.txt. It provides the power domains defined in
- include/dt-bindings/power/mt8173-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt2701-power.h
+- include/dt-bindings/power/mt7622-power.h
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
- "mediatek,mt6797-scpsys"
+ - "mediatek,mt7622-scpsys"
- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
@@ -26,6 +28,7 @@ Required properties:
enabled before enabling certain power domains.
Required clocks for MT2701: "mm", "mfg", "ethif"
Required clocks for MT6797: "mm", "mfg", "vdec"
+ Required clocks for MT7622: "hif_sel"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:
diff --git a/dts/Bindings/soc/qcom/qcom,glink.txt b/dts/Bindings/soc/qcom/qcom,glink.txt
index 50fc20c6ce..b277eca861 100644
--- a/dts/Bindings/soc/qcom/qcom,glink.txt
+++ b/dts/Bindings/soc/qcom/qcom,glink.txt
@@ -1,11 +1,12 @@
-Qualcomm RPM GLINK binding
+Qualcomm GLINK edge binding
-This binding describes the Qualcomm RPM GLINK, a fifo based mechanism for
-communication with the Resource Power Management system on various Qualcomm
-platforms.
+This binding describes a Qualcomm GLINK edge, a fifo based mechanism for
+communication between subsystem-pairs on various Qualcomm platforms. Two types
+of edges can be described by the binding; the GLINK RPM edge and a SMEM based
+edge.
- compatible:
- Usage: required
+ Usage: required for glink-rpm
Value type: <stringlist>
Definition: must be "qcom,glink-rpm"
@@ -16,7 +17,7 @@ platforms.
signal this processor about communication related events
- qcom,rpm-msg-ram:
- Usage: required
+ Usage: required for glink-rpm
Value type: <prop-encoded-array>
Definition: handle to RPM message memory resource
diff --git a/dts/Bindings/soc/qcom/qcom,gsbi.txt b/dts/Bindings/soc/qcom/qcom,gsbi.txt
index 2f5ede39be..fe1855f09d 100644
--- a/dts/Bindings/soc/qcom/qcom,gsbi.txt
+++ b/dts/Bindings/soc/qcom/qcom,gsbi.txt
@@ -78,7 +78,6 @@ Example for APQ8064:
interrupts = <0 152 0x0>;
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
- status = "ok";
};
};
diff --git a/dts/Bindings/soc/rockchip/grf.txt b/dts/Bindings/soc/rockchip/grf.txt
index cc9f05d3cb..7dc5ce858a 100644
--- a/dts/Bindings/soc/rockchip/grf.txt
+++ b/dts/Bindings/soc/rockchip/grf.txt
@@ -21,6 +21,7 @@ Required Properties:
- "rockchip,rk3328-grf", "syscon": for rk3328
- "rockchip,rk3368-grf", "syscon": for rk3368
- "rockchip,rk3399-grf", "syscon": for rk3399
+ - "rockchip,rv1108-grf", "syscon": for rv1108
- compatible: PMUGRF should be one of the following:
- "rockchip,rk3368-pmugrf", "syscon": for rk3368
- "rockchip,rk3399-pmugrf", "syscon": for rk3399
@@ -28,6 +29,8 @@ Required Properties:
- "rockchip,rk3288-sgrf", "syscon": for rk3288
- compatible: USB2PHYGRF should be one of the followings
- "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
+- compatible: USBGRF should be one of the following
+ - "rockchip,rv1108-usbgrf", "syscon": for rv1108
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/dts/Bindings/soc/rockchip/power_domain.txt b/dts/Bindings/soc/rockchip/power_domain.txt
index 01bfb6745f..301d2a9bc1 100644
--- a/dts/Bindings/soc/rockchip/power_domain.txt
+++ b/dts/Bindings/soc/rockchip/power_domain.txt
@@ -7,6 +7,7 @@ Required properties for power domain controller:
- compatible: Should be one of the following.
"rockchip,rk3288-power-controller" - for RK3288 SoCs.
"rockchip,rk3328-power-controller" - for RK3328 SoCs.
+ "rockchip,rk3366-power-controller" - for RK3366 SoCs.
"rockchip,rk3368-power-controller" - for RK3368 SoCs.
"rockchip,rk3399-power-controller" - for RK3399 SoCs.
- #power-domain-cells: Number of cells in a power-domain specifier.
@@ -18,6 +19,7 @@ Required properties for power domain sub nodes:
- reg: index of the power domain, should use macros in:
"include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
"include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain.
+ "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain.
"include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain.
"include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain.
- clocks (optional): phandles to clocks which need to be enabled while power domain
@@ -93,6 +95,7 @@ power domain to use.
The index should use macros in:
"include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
"include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain.
+ "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain.
"include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain.
"include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain.
diff --git a/dts/Bindings/soc/ti/sci-pm-domain.txt b/dts/Bindings/soc/ti/sci-pm-domain.txt
index c705db07d8..66e6265fb0 100644
--- a/dts/Bindings/soc/ti/sci-pm-domain.txt
+++ b/dts/Bindings/soc/ti/sci-pm-domain.txt
@@ -46,12 +46,13 @@ Required Properties:
- power-domains: phandle pointing to the corresponding PM domain node
and an ID representing the device.
-See dt-bindings/genpd/k2g.h for the list of valid identifiers for k2g.
+See http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data for the list
+of valid identifiers for k2g.
Example (K2G):
--------------------
uart0: serial@02530c00 {
compatible = "ns16550a";
...
- power-domains = <&k2g_pds K2G_DEV_UART0>;
+ power-domains = <&k2g_pds 0x002c>;
};
diff --git a/dts/Bindings/sound/armada-370db-audio.txt b/dts/Bindings/sound/armada-370db-audio.txt
index bf984d2386..953c092db7 100644
--- a/dts/Bindings/sound/armada-370db-audio.txt
+++ b/dts/Bindings/sound/armada-370db-audio.txt
@@ -23,5 +23,4 @@ Example:
compatible = "marvell,a370db-audio";
marvell,audio-controller = <&audio_controller>;
marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>;
- status = "okay";
};
diff --git a/dts/Bindings/sound/atmel-classd.txt b/dts/Bindings/sound/atmel-classd.txt
index 549e701cb7..8985510763 100644
--- a/dts/Bindings/sound/atmel-classd.txt
+++ b/dts/Bindings/sound/atmel-classd.txt
@@ -13,13 +13,11 @@ Required properties:
Must be "tx".
- clock-names
Tuple listing input clock names.
- Required elements: "pclk", "gclk" and "aclk".
+ Required elements: "pclk" and "gclk".
- clocks
Please refer to clock-bindings.txt.
- assigned-clocks
Should be <&classd_gclk>.
-- assigned-clock-parents
- Should be <&audio_pll_pmc>.
Optional properties:
- pinctrl-names, pinctrl-0
@@ -45,10 +43,9 @@ classd: classd@fc048000 {
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(47))>;
dma-names = "tx";
- clocks = <&classd_clk>, <&classd_gclk>, <&audio_pll_pmc>;
- clock-names = "pclk", "gclk", "aclk";
+ clocks = <&classd_clk>, <&classd_gclk>;
+ clock-names = "pclk", "gclk";
assigned-clocks = <&classd_gclk>;
- assigned-clock-parents = <&audio_pll_pmc>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_classd_default>;
diff --git a/dts/Bindings/sound/axentia,tse850-pcm5142.txt b/dts/Bindings/sound/axentia,tse850-pcm5142.txt
index fdb25b4925..9d049d4bfd 100644
--- a/dts/Bindings/sound/axentia,tse850-pcm5142.txt
+++ b/dts/Bindings/sound/axentia,tse850-pcm5142.txt
@@ -45,7 +45,6 @@ Example:
&ssc0 {
#sound-dai-cells = <0>;
- status = "okay";
};
&i2c {
diff --git a/dts/Bindings/sound/brcm,cygnus-audio.txt b/dts/Bindings/sound/brcm,cygnus-audio.txt
index b139e66d2a..630bf7c034 100644
--- a/dts/Bindings/sound/brcm,cygnus-audio.txt
+++ b/dts/Bindings/sound/brcm,cygnus-audio.txt
@@ -47,21 +47,17 @@ Example:
ssp0: ssp_port@0 {
reg = <0>;
- status = "okay";
};
ssp1: ssp_port@1 {
reg = <1>;
- status = "disabled";
};
ssp2: ssp_port@2 {
reg = <2>;
- status = "disabled";
};
spdif: spdif_port@3 {
reg = <3>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/sound/cs43130.txt b/dts/Bindings/sound/cs43130.txt
new file mode 100644
index 0000000000..8b1dd5aeb0
--- /dev/null
+++ b/dts/Bindings/sound/cs43130.txt
@@ -0,0 +1,67 @@
+CS43130 DAC
+
+Required properties:
+
+ - compatible : "cirrus,cs43130", "cirrus,cs4399", "cirrus,cs43131",
+ "cirrus,cs43198"
+
+ - reg : the I2C address of the device for I2C
+
+ - VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply:
+ power supplies for the device, as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+
+
+Optional properties:
+
+ - reset-gpios : Active low GPIO used to reset the device
+
+ - cirrus,xtal-ibias:
+ When external MCLK is generated by external crystal
+ oscillator, CS43130 can be used to provide bias current
+ for external crystal. Amount of bias current sent is
+ set as:
+ 1 = 7.5uA
+ 2 = 12.5uA
+ 3 = 15uA
+
+ - cirrus,dc-measure:
+ Boolean, define to enable headphone DC impedance measurement.
+
+ - cirrus,ac-measure:
+ Boolean, define to enable headphone AC impedance measurement.
+ DC impedance must also be enabled for AC impedance measurement.
+
+ - cirrus,dc-threshold:
+ Define 2 DC impedance thresholds in ohms for HP output control.
+ Default values are 50 and 120 Ohms.
+
+ - cirrus,ac-freq:
+ Define the frequencies at which to measure HP AC impedance.
+ Only used if "cirrus,dc-measure" is defined.
+ Exactly 10 frequencies must be defined.
+ If this properties is undefined, by default,
+ following frequencies are used:
+ <24 43 93 200 431 928 2000 4309 9283 20000>
+ The above frequencies are logarithmically equally spaced.
+ Log base is 10.
+
+Example:
+
+cs43130: audio-codec@30 {
+ compatible = "cirrus,cs43130";
+ reg = <0x30>;
+ reset-gpios = <&axi_gpio 54 0>;
+ VA-supply = <&dummy_vreg>;
+ VP-supply = <&dummy_vreg>;
+ VL-supply = <&dummy_vreg>;
+ VCP-supply = <&dummy_vreg>;
+ VD-supply = <&dummy_vreg>;
+ cirrus,xtal-ibias = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <55 8>;
+ cirrus,dc-measure;
+ cirrus,ac-measure;
+ cirrus,dc-threshold = /bits/ 16 <20 100>;
+ cirrus,ac-freq = /bits/ 16 <24 43 93 200 431 928 2000 4309 9283 20000>;
+};
diff --git a/dts/Bindings/sound/davinci-mcbsp.txt b/dts/Bindings/sound/davinci-mcbsp.txt
index e0b6165c9c..3ffc2562fb 100644
--- a/dts/Bindings/sound/davinci-mcbsp.txt
+++ b/dts/Bindings/sound/davinci-mcbsp.txt
@@ -47,5 +47,4 @@ mcbsp0: mcbsp@1d10000 {
dmas = <&edma0 3 1
&edma0 2 1>;
dma-names = "tx", "rx";
- status = "okay";
};
diff --git a/dts/Bindings/sound/dmic.txt b/dts/Bindings/sound/dmic.txt
new file mode 100644
index 0000000000..54c8ef6498
--- /dev/null
+++ b/dts/Bindings/sound/dmic.txt
@@ -0,0 +1,16 @@
+Device-Tree bindings for Digital microphone (DMIC) codec
+
+This device support generic PDM digital microphone.
+
+Required properties:
+ - compatible: should be "dmic-codec".
+
+Optional properties:
+ - dmicen-gpios: GPIO specifier for dmic to control start and stop
+
+Example node:
+
+ dmic_codec: dmic@0 {
+ compatible = "dmic-codec";
+ dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/Bindings/sound/fsl,asrc.txt b/dts/Bindings/sound/fsl,asrc.txt
index 3e26a9478e..65979b2058 100644
--- a/dts/Bindings/sound/fsl,asrc.txt
+++ b/dts/Bindings/sound/fsl,asrc.txt
@@ -61,5 +61,4 @@ asrc: asrc@02034000 {
"txa", "txb", "txc";
fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
- status = "okay";
};
diff --git a/dts/Bindings/sound/fsl,esai.txt b/dts/Bindings/sound/fsl,esai.txt
index cd3ee5d84f..21c401e2cc 100644
--- a/dts/Bindings/sound/fsl,esai.txt
+++ b/dts/Bindings/sound/fsl,esai.txt
@@ -59,5 +59,4 @@ esai: esai@02024000 {
fsl,fifo-depth = <128>;
fsl,esai-synchronous;
big-endian;
- status = "disabled";
};
diff --git a/dts/Bindings/sound/fsl,spdif.txt b/dts/Bindings/sound/fsl,spdif.txt
index 4ca39ddc04..0f97e54c3d 100644
--- a/dts/Bindings/sound/fsl,spdif.txt
+++ b/dts/Bindings/sound/fsl,spdif.txt
@@ -59,5 +59,4 @@ spdif: spdif@02004000 {
"rxtx7";
big-endian;
- status = "okay";
};
diff --git a/dts/Bindings/sound/hdmi.txt b/dts/Bindings/sound/hdmi.txt
index 31af7bca30..56407c30e9 100644
--- a/dts/Bindings/sound/hdmi.txt
+++ b/dts/Bindings/sound/hdmi.txt
@@ -13,5 +13,4 @@ Example node:
hdmi_audio: hdmi_audio@0 {
compatible = "linux,hdmi-audio";
- status = "okay";
};
diff --git a/dts/Bindings/sound/mt2701-afe-pcm.txt b/dts/Bindings/sound/mt2701-afe-pcm.txt
index 9800a560e0..77a57f84be 100644
--- a/dts/Bindings/sound/mt2701-afe-pcm.txt
+++ b/dts/Bindings/sound/mt2701-afe-pcm.txt
@@ -3,7 +3,8 @@ Mediatek AFE PCM controller for mt2701
Required properties:
- compatible = "mediatek,mt2701-audio";
- reg: register location and size
-- interrupts: Should contain AFE interrupt
+- interrupts: should contain AFE and ASYS interrupts
+- interrupt-names: should be "afe" and "asys"
- power-domains: should define the power domain
- clock-names: should have these clock names:
"infra_sys_audio_clk",
@@ -59,6 +60,7 @@ Example:
<0 0x112A0000 0 0x20000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
diff --git a/dts/Bindings/sound/qcom,msm8916-wcd-analog.txt b/dts/Bindings/sound/qcom,msm8916-wcd-analog.txt
index ccb401cfef..551ecab67e 100644
--- a/dts/Bindings/sound/qcom,msm8916-wcd-analog.txt
+++ b/dts/Bindings/sound/qcom,msm8916-wcd-analog.txt
@@ -31,8 +31,22 @@ Required properties
- vdd-cdc-io-supply: phandle to VDD_CDC_IO regulator DT node.
- vdd-cdc-tx-rx-cx-supply: phandle to VDD_CDC_TX/RX/CX regulator DT node.
- vdd-micbias-supply: phandle of VDD_MICBIAS supply's regulator DT node.
-
Optional Properties:
+ - qcom,mbhc-vthreshold-low: Array of 5 threshold voltages in mV for 5 buttons
+ detection on headset when the mbhc is powered up
+ by internal current source, this is a low power.
+ - qcom,mbhc-vthreshold-high: Array of 5 thresold voltages in mV for 5 buttons
+ detection on headset when mbhc is powered up
+ from micbias.
+- qcom,micbias-lvl: Voltage (mV) for Mic Bias
+- qcom,hphl-jack-type-normally-open: boolean, present if hphl pin on jack is a
+ NO (Normally Open). If not specified, then
+ its assumed that hphl pin on jack is NC
+ (Normally Closed).
+- qcom,gnd-jack-type-normally-open: boolean, present if gnd pin on jack is
+ NO (Normally Open). If not specified, then
+ its assumed that gnd pin on jack is NC
+ (Normally Closed).
- qcom,micbias1-ext-cap: boolean, present if micbias1 has external capacitor
connected.
- qcom,micbias2-ext-cap: boolean, present if micbias2 has external capacitor
@@ -48,6 +62,8 @@ spmi_bus {
reg-names = "pmic-codec-core";
clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
clock-names = "mclk";
+ qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
+ qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
interrupt-parent = <&spmi_bus>;
interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
<0x1 0xf0 0x1 IRQ_TYPE_NONE>,
diff --git a/dts/Bindings/sound/renesas,rsnd.txt b/dts/Bindings/sound/renesas,rsnd.txt
index 7246bb268b..085bec364c 100644
--- a/dts/Bindings/sound/renesas,rsnd.txt
+++ b/dts/Bindings/sound/renesas,rsnd.txt
@@ -199,10 +199,10 @@ Ex)
sound {
compatible = "simple-scu-audio-card";
...
- simple-audio-card,cpu@0 {
+ simple-audio-card,cpu-0 {
sound-dai = <&rcar_sound 0>;
};
- simple-audio-card,cpu@1 {
+ simple-audio-card,cpu-1 {
sound-dai = <&rcar_sound 1>;
};
simple-audio-card,codec {
@@ -441,79 +441,79 @@ rcar_sound: sound@ec500000 {
"clk_a", "clk_b", "clk_c", "clk_i";
rcar_sound,dvc {
- dvc0: dvc@0 {
+ dvc0: dvc-0 {
dmas = <&audma0 0xbc>;
dma-names = "tx";
};
- dvc1: dvc@1 {
+ dvc1: dvc-1 {
dmas = <&audma0 0xbe>;
dma-names = "tx";
};
};
rcar_sound,mix {
- mix0: mix@0 { };
- mix1: mix@1 { };
+ mix0: mix-0 { };
+ mix1: mix-1 { };
};
rcar_sound,ctu {
- ctu00: ctu@0 { };
- ctu01: ctu@1 { };
- ctu02: ctu@2 { };
- ctu03: ctu@3 { };
- ctu10: ctu@4 { };
- ctu11: ctu@5 { };
- ctu12: ctu@6 { };
- ctu13: ctu@7 { };
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
};
rcar_sound,src {
- src0: src@0 {
+ src0: src-0 {
interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x85>, <&audma1 0x9a>;
dma-names = "rx", "tx";
};
- src1: src@1 {
+ src1: src-1 {
interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x87>, <&audma1 0x9c>;
dma-names = "rx", "tx";
};
- src2: src@2 {
+ src2: src-2 {
interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x89>, <&audma1 0x9e>;
dma-names = "rx", "tx";
};
- src3: src@3 {
+ src3: src-3 {
interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
dma-names = "rx", "tx";
};
- src4: src@4 {
+ src4: src-4 {
interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
dma-names = "rx", "tx";
};
- src5: src@5 {
+ src5: src-5 {
interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
dma-names = "rx", "tx";
};
- src6: src@6 {
+ src6: src-6 {
interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x91>, <&audma1 0xb4>;
dma-names = "rx", "tx";
};
- src7: src@7 {
+ src7: src-7 {
interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x93>, <&audma1 0xb6>;
dma-names = "rx", "tx";
};
- src8: src@8 {
+ src8: src-8 {
interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x95>, <&audma1 0xb8>;
dma-names = "rx", "tx";
};
- src9: src@9 {
+ src9: src-9 {
interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x97>, <&audma1 0xba>;
dma-names = "rx", "tx";
@@ -521,52 +521,52 @@ rcar_sound: sound@ec500000 {
};
rcar_sound,ssi {
- ssi0: ssi@0 {
+ ssi0: ssi-0 {
interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi1: ssi@1 {
+ ssi1: ssi-1 {
interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi2: ssi@2 {
+ ssi2: ssi-2 {
interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi3: ssi@3 {
+ ssi3: ssi-3 {
interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi4: ssi@4 {
+ ssi4: ssi-4 {
interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi5: ssi@5 {
+ ssi5: ssi-5 {
interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi6: ssi@6 {
+ ssi6: ssi-6 {
interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi7: ssi@7 {
+ ssi7: ssi-7 {
interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi8: ssi@8 {
+ ssi8: ssi-8 {
interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx", "rxu", "txu";
};
- ssi9: ssi@9 {
+ ssi9: ssi-9 {
interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx", "rxu", "txu";
@@ -621,7 +621,6 @@ Example: simple sound card
/* Single DAI */
#sound-dai-cells = <0>;
- status = "okay";
rcar_sound,dai {
dai0 {
@@ -667,7 +666,6 @@ Example: simple sound card for Multi channel
/* Single DAI */
#sound-dai-cells = <0>;
- status = "okay";
rcar_sound,dai {
dai0 {
diff --git a/dts/Bindings/sound/rockchip,pdm.txt b/dts/Bindings/sound/rockchip,pdm.txt
index 921729de73..47f164fbd1 100644
--- a/dts/Bindings/sound/rockchip,pdm.txt
+++ b/dts/Bindings/sound/rockchip,pdm.txt
@@ -29,11 +29,13 @@ pdm: pdm@ff040000 {
dma-names = "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pdmm0_clk
- &pdmm0_fsync
&pdmm0_sdi0
&pdmm0_sdi1
&pdmm0_sdi2
&pdmm0_sdi3>;
- pinctrl-1 = <&pdmm0_sleep>;
- status = "disabled";
+ pinctrl-1 = <&pdmm0_clk_sleep
+ &pdmm0_sdi0_sleep
+ &pdmm0_sdi1_sleep
+ &pdmm0_sdi2_sleep
+ &pdmm0_sdi3_sleep>;
};
diff --git a/dts/Bindings/sound/rockchip,rk3399-gru-sound.txt b/dts/Bindings/sound/rockchip,rk3399-gru-sound.txt
index eac91db071..72d3cf4c26 100644
--- a/dts/Bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/dts/Bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible: "rockchip,rk3399-gru-sound"
- rockchip,cpu: The phandle of the Rockchip I2S controller that's
connected to the codecs
-- rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
+- rockchip,codec: The phandle of the audio codecs
Optional properties:
- dmic-wakeup-delay-ms : specify delay time (ms) for DMIC ready.
diff --git a/dts/Bindings/sound/rockchip-i2s.txt b/dts/Bindings/sound/rockchip-i2s.txt
index 206aba1b34..b208a75257 100644
--- a/dts/Bindings/sound/rockchip-i2s.txt
+++ b/dts/Bindings/sound/rockchip-i2s.txt
@@ -7,8 +7,12 @@ Required properties:
- compatible: should be one of the following:
- "rockchip,rk3066-i2s": for rk3066
+ - "rockchip,rk3036-i2s", "rockchip,rk3066-i2s": for rk3036
- "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188
+ - "rockchip,rk3228-i2s", "rockchip,rk3066-i2s": for rk3228
- "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288
+ - "rockchip,rk3328-i2s", "rockchip,rk3066-i2s": for rk3328
+ - "rockchip,rk3366-i2s", "rockchip,rk3066-i2s": for rk3366
- "rockchip,rk3368-i2s", "rockchip,rk3066-i2s": for rk3368
- "rockchip,rk3399-i2s", "rockchip,rk3066-i2s": for rk3399
- reg: physical base address of the controller and length of memory mapped
diff --git a/dts/Bindings/sound/rockchip-spdif.txt b/dts/Bindings/sound/rockchip-spdif.txt
index 4706b96d45..0a1dc4e181 100644
--- a/dts/Bindings/sound/rockchip-spdif.txt
+++ b/dts/Bindings/sound/rockchip-spdif.txt
@@ -41,6 +41,5 @@ spdif: spdif@0x1011e000 {
dma-names = "tx";
clock-names = "hclk", "mclk";
clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
- status = "disabled";
#sound-dai-cells = <0>;
};
diff --git a/dts/Bindings/sound/rt274.txt b/dts/Bindings/sound/rt274.txt
new file mode 100644
index 0000000000..e9a6178c78
--- /dev/null
+++ b/dts/Bindings/sound/rt274.txt
@@ -0,0 +1,33 @@
+RT274 audio CODEC
+
+This device supports I2C only.
+
+Required properties:
+
+- compatible : "realtek,rt274".
+
+- reg : The I2C address of the device.
+
+Optional properties:
+
+- interrupts : The CODEC's interrupt output.
+
+
+Pins on the device (for linking into audio routes) for RT274:
+
+ * DMIC1 Pin
+ * DMIC2 Pin
+ * MIC
+ * LINE1
+ * LINE2
+ * HPO Pin
+ * SPDIF
+ * LINE3
+
+Example:
+
+codec: rt274@1c {
+ compatible = "realtek,rt274";
+ reg = <0x1c>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+};
diff --git a/dts/Bindings/sound/rt5663.txt b/dts/Bindings/sound/rt5663.txt
index 70eaeaed2b..ff381718c5 100644
--- a/dts/Bindings/sound/rt5663.txt
+++ b/dts/Bindings/sound/rt5663.txt
@@ -12,6 +12,14 @@ Required properties:
Optional properties:
+- "realtek,dc_offset_l_manual"
+- "realtek,dc_offset_r_manual"
+- "realtek,dc_offset_l_manual_mic"
+- "realtek,dc_offset_r_manual_mic"
+ Based on the different PCB layout, add the manual offset value to
+ compensate the DC offset for each L and R channel, and they are different
+ between headphone and headset.
+
Pins on the device (for linking into audio routes) for RT5663:
* IN1P
diff --git a/dts/Bindings/sound/samsung,odroid.txt b/dts/Bindings/sound/samsung,odroid.txt
index c30934dd97..625b1b18fd 100644
--- a/dts/Bindings/sound/samsung,odroid.txt
+++ b/dts/Bindings/sound/samsung,odroid.txt
@@ -7,9 +7,6 @@ Required properties:
- model - the user-visible name of this sound complex
- clocks - should contain entries matching clock names in the clock-names
property
- - clock-names - should contain following entries:
- - "epll" - indicating the EPLL output clock
- - "i2s_rclk" - indicating the RCLK (root) clock of the I2S0 controller
- samsung,audio-widgets - this property specifies off-codec audio elements
like headphones or speakers, for details see widgets.txt
- samsung,audio-routing - a list of the connections between audio
@@ -46,9 +43,6 @@ sound {
"IN1", "Mic Jack",
"Mic Jack", "MICBIAS";
- clocks = <&clock CLK_FOUT_EPLL>, <&i2s0 CLK_I2S_RCLK_SRC>;
- clock-names = "epll", "sclk_i2s";
-
cpu {
sound-dai = <&i2s0 0>;
};
diff --git a/dts/Bindings/sound/simple-card.txt b/dts/Bindings/sound/simple-card.txt
index c7a93931fa..166f229023 100644
--- a/dts/Bindings/sound/simple-card.txt
+++ b/dts/Bindings/sound/simple-card.txt
@@ -86,6 +86,9 @@ Optional CPU/CODEC subnodes properties:
in dai startup() and disabled with
clk_disable_unprepare() in dai
shutdown().
+- system-clock-direction-out : specifies clock direction as 'out' on
+ initialization. It is useful for some aCPUs with
+ fixed clocks.
Example 1 - single DAI link:
diff --git a/dts/Bindings/sound/simple-scu-card.txt b/dts/Bindings/sound/simple-scu-card.txt
index 327d229a51..32f8dbce52 100644
--- a/dts/Bindings/sound/simple-scu-card.txt
+++ b/dts/Bindings/sound/simple-scu-card.txt
@@ -24,6 +24,7 @@ Optional subnode properties:
- simple-audio-card,convert-rate : platform specified sampling rate convert
- simple-audio-card,convert-channels : platform specified converted channel size (2 - 8 ch)
- simple-audio-card,prefix : see routing
+- simple-audio-card,widgets : Please refer to widgets.txt.
- simple-audio-card,routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources.
diff --git a/dts/Bindings/sound/st,sti-asoc-card.txt b/dts/Bindings/sound/st,sti-asoc-card.txt
index 745dc62f76..40068ec0e9 100644
--- a/dts/Bindings/sound/st,sti-asoc-card.txt
+++ b/dts/Bindings/sound/st,sti-asoc-card.txt
@@ -53,7 +53,6 @@ Example:
sti_uni_player1: sti-uni-player@0x8D81000 {
compatible = "st,stih407-uni-player-hdmi";
- status = "okay";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
@@ -66,7 +65,6 @@ Example:
sti_uni_player2: sti-uni-player@0x8D82000 {
compatible = "st,stih407-uni-player-pcm-out";
- status = "okay";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
@@ -78,7 +76,6 @@ Example:
sti_uni_player3: sti-uni-player@0x8D85000 {
compatible = "st,stih407-uni-player-spdif";
- status = "okay";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
@@ -90,7 +87,6 @@ Example:
sti_uni_reader1: sti-uni-reader@0x8D84000 {
compatible = "st,stih407-uni-reader-hdmi";
- status = "disabled";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
reg = <0x8D84000 0x158>;
@@ -125,7 +121,6 @@ Example of audio card declaration:
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "sti audio card";
- status = "okay";
simple-audio-card,dai-link@0 {
/* DAC */
diff --git a/dts/Bindings/sound/sun4i-i2s.txt b/dts/Bindings/sound/sun4i-i2s.txt
index ee21da8657..fc5da60807 100644
--- a/dts/Bindings/sound/sun4i-i2s.txt
+++ b/dts/Bindings/sound/sun4i-i2s.txt
@@ -8,6 +8,7 @@ Required properties:
- compatible: should be one of the following:
- "allwinner,sun4i-a10-i2s"
- "allwinner,sun6i-a31-i2s"
+ - "allwinner,sun8i-h3-i2s"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: should contain the I2S interrupt.
@@ -22,6 +23,7 @@ Required properties:
Required properties for the following compatibles:
- "allwinner,sun6i-a31-i2s"
+ - "allwinner,sun8i-h3-i2s"
- resets: phandle to the reset line for this codec
Example:
diff --git a/dts/Bindings/sound/sunxi,sun4i-spdif.txt b/dts/Bindings/sound/sunxi,sun4i-spdif.txt
index fe0a65e6d6..70ee177901 100644
--- a/dts/Bindings/sound/sunxi,sun4i-spdif.txt
+++ b/dts/Bindings/sound/sunxi,sun4i-spdif.txt
@@ -39,5 +39,4 @@ spdif: spdif@01c21000 {
clock-names = "apb", "spdif";
dmas = <&dma 0 2>, <&dma 0 2>;
dma-names = "rx", "tx";
- status = "okay";
};
diff --git a/dts/Bindings/sound/tas5720.txt b/dts/Bindings/sound/tas5720.txt
index 806ea73814..40d94f82be 100644
--- a/dts/Bindings/sound/tas5720.txt
+++ b/dts/Bindings/sound/tas5720.txt
@@ -17,7 +17,6 @@ Required properties:
Example:
tas5720: tas5720@6c {
- status = "okay";
compatible = "ti,tas5720";
reg = <0x6c>;
dvdd-supply = <&vdd_3v3_reg>;
diff --git a/dts/Bindings/sound/tlv320aic32x4.txt b/dts/Bindings/sound/tlv320aic32x4.txt
index 5e2741af27..ca75890f0d 100644
--- a/dts/Bindings/sound/tlv320aic32x4.txt
+++ b/dts/Bindings/sound/tlv320aic32x4.txt
@@ -3,7 +3,9 @@ Texas Instruments - tlv320aic32x4 Codec module
The tlv320aic32x4 serial control bus communicates through I2C protocols
Required properties:
- - compatible: Should be "ti,tlv320aic32x4"
+ - compatible - "string" - One of:
+ "ti,tlv320aic32x4" TLV320AIC3204
+ "ti,tlv320aic32x6" TLV320AIC3206, TLV320AIC3256
- reg: I2C slave address
- supply-*: Required supply regulators are:
"iov" - digital IO power supply
@@ -18,6 +20,8 @@ Optional properties:
- reset-gpios: Reset-GPIO phandle with args as described in gpio/gpio.txt
- clocks/clock-names: Clock named 'mclk' for the master clock of the codec.
See clock/clock-bindings.txt for information about the detailed format.
+ - aic32x4-gpio-func - <array of 5 int>
+ - Types are defined in include/sound/tlv320aic32x4.h
Example:
@@ -27,4 +31,11 @@ codec: tlv320aic32x4@18 {
reg = <0x18>;
clocks = <&clks 201>;
clock-names = "mclk";
+ aic32x4-gpio-func= <
+ 0xff /* AIC32X4_MFPX_DEFAULT_VALUE */
+ 0xff /* AIC32X4_MFPX_DEFAULT_VALUE */
+ 0x04 /* MFP3 AIC32X4_MFP3_GPIO_ENABLED */
+ 0xff /* AIC32X4_MFPX_DEFAULT_VALUE */
+ 0x08 /* MFP5 AIC32X4_MFP5_GPIO_INPUT */
+ >;
};
diff --git a/dts/Bindings/sound/tlv320aic3x.txt b/dts/Bindings/sound/tlv320aic3x.txt
index 47a213c411..ba5b45c483 100644
--- a/dts/Bindings/sound/tlv320aic3x.txt
+++ b/dts/Bindings/sound/tlv320aic3x.txt
@@ -26,6 +26,11 @@ Optional properties:
3 - MICBIAS output is connected to AVDD,
If this node is not mentioned or if the value is incorrect, then MicBias
is powered down.
+- ai3x-ocmv - Output Common-Mode Voltage selection:
+ 0 - 1.35V,
+ 1 - 1.5V,
+ 2 - 1.65V,
+ 3 - 1.8V
- AVDD-supply, IOVDD-supply, DRVDD-supply, DVDD-supply : power supplies for the
device as covered in Documentation/devicetree/bindings/regulator/regulator.txt
diff --git a/dts/Bindings/sound/wm8524.txt b/dts/Bindings/sound/wm8524.txt
new file mode 100644
index 0000000000..20c62002cb
--- /dev/null
+++ b/dts/Bindings/sound/wm8524.txt
@@ -0,0 +1,16 @@
+WM8524 audio CODEC
+
+This device does not use I2C or SPI but a simple Hardware Control Interface.
+
+Required properties:
+
+ - compatible : "wlf,wm8524"
+
+ - wlf,mute-gpios: a GPIO spec for the MUTE pin.
+
+Example:
+
+codec: wm8524@0 {
+ compatible = "wlf,wm8524";
+ wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/Bindings/sound/zte,zx-i2s.txt b/dts/Bindings/sound/zte,zx-i2s.txt
index 292ad50837..3927251464 100644
--- a/dts/Bindings/sound/zte,zx-i2s.txt
+++ b/dts/Bindings/sound/zte,zx-i2s.txt
@@ -27,7 +27,6 @@ Example:
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma 5>, <&dma 6>;
dma-names = "tx", "rx";
- status = "okay";
};
sound {
diff --git a/dts/Bindings/sound/zte,zx-spdif.txt b/dts/Bindings/sound/zte,zx-spdif.txt
index 989544ea6e..b5a5ca4502 100644
--- a/dts/Bindings/sound/zte,zx-spdif.txt
+++ b/dts/Bindings/sound/zte,zx-spdif.txt
@@ -24,5 +24,4 @@ Example:
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma 4>;
dma-names = "tx";
- status = "okay";
};
diff --git a/dts/Bindings/spi/efm32-spi.txt b/dts/Bindings/spi/efm32-spi.txt
index 750e29aff9..2c1e6a4393 100644
--- a/dts/Bindings/spi/efm32-spi.txt
+++ b/dts/Bindings/spi/efm32-spi.txt
@@ -28,7 +28,6 @@ spi1: spi@0x4000c400 { /* USART1 */
clocks = <&cmu 20>;
cs-gpios = <&gpio 51 1>; // D3
energymicro,location = <1>;
- status = "ok";
ks8851@0 {
compatible = "ks8851";
@@ -36,6 +35,5 @@ spi1: spi@0x4000c400 { /* USART1 */
reg = <0>;
interrupt-parent = <&boardfpga>;
interrupts = <4>;
- status = "ok";
};
};
diff --git a/dts/Bindings/spi/fsl-imx-cspi.txt b/dts/Bindings/spi/fsl-imx-cspi.txt
index 31b5b21598..5bf13960f7 100644
--- a/dts/Bindings/spi/fsl-imx-cspi.txt
+++ b/dts/Bindings/spi/fsl-imx-cspi.txt
@@ -9,6 +9,7 @@ Required properties:
- "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31
- "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
- "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
+ - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
- reg : Offset and length of the register set for the device
- interrupts : Should contain CSPI/eCSPI interrupt
- cs-gpios : Specifies the gpio pins to be used for chipselects.
diff --git a/dts/Bindings/spi/nvidia,tegra114-spi.txt b/dts/Bindings/spi/nvidia,tegra114-spi.txt
index b785976fe9..9ba7c5a273 100644
--- a/dts/Bindings/spi/nvidia,tegra114-spi.txt
+++ b/dts/Bindings/spi/nvidia,tegra114-spi.txt
@@ -38,5 +38,4 @@ spi@7000d600 {
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
- status = "disabled";
};
diff --git a/dts/Bindings/spi/nvidia,tegra20-sflash.txt b/dts/Bindings/spi/nvidia,tegra20-sflash.txt
index bdf08e6dec..c212491929 100644
--- a/dts/Bindings/spi/nvidia,tegra20-sflash.txt
+++ b/dts/Bindings/spi/nvidia,tegra20-sflash.txt
@@ -34,5 +34,4 @@ spi@7000c380 {
reset-names = "spi";
dmas = <&apbdma 11>, <&apbdma 11>;
dma-names = "rx", "tx";
- status = "disabled";
};
diff --git a/dts/Bindings/spi/nvidia,tegra20-slink.txt b/dts/Bindings/spi/nvidia,tegra20-slink.txt
index 5db9144a33..40d80b93e3 100644
--- a/dts/Bindings/spi/nvidia,tegra20-slink.txt
+++ b/dts/Bindings/spi/nvidia,tegra20-slink.txt
@@ -34,5 +34,4 @@ spi@7000d600 {
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
- status = "disabled";
};
diff --git a/dts/Bindings/spi/sh-hspi.txt b/dts/Bindings/spi/sh-hspi.txt
index 319bad4af8..585fed9037 100644
--- a/dts/Bindings/spi/sh-hspi.txt
+++ b/dts/Bindings/spi/sh-hspi.txt
@@ -24,6 +24,5 @@ Example:
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
};
diff --git a/dts/Bindings/spi/sh-msiof.txt b/dts/Bindings/spi/sh-msiof.txt
index 64ee489571..e865855726 100644
--- a/dts/Bindings/spi/sh-msiof.txt
+++ b/dts/Bindings/spi/sh-msiof.txt
@@ -6,6 +6,7 @@ Required properties:
"renesas,msiof-r8a7792" (R-Car V2H)
"renesas,msiof-r8a7793" (R-Car M2-N)
"renesas,msiof-r8a7794" (R-Car E2)
+ "renesas,msiof-r8a7795" (R-Car H3)
"renesas,msiof-r8a7796" (R-Car M3-W)
"renesas,msiof-sh73a0" (SH-Mobile AG5)
"renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
@@ -78,5 +79,4 @@ Example:
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
};
diff --git a/dts/Bindings/spi/spi-clps711x.txt b/dts/Bindings/spi/spi-clps711x.txt
index 4c3ec13f42..5122dc7860 100644
--- a/dts/Bindings/spi/spi-clps711x.txt
+++ b/dts/Bindings/spi/spi-clps711x.txt
@@ -23,7 +23,6 @@ spi@80000500 {
reg = <0x80000500 0x4>;
interrupts = <15>;
clocks = <&clks CLPS711X_CLK_SPI>;
- status = "disabled";
};
syscon3: syscon@80002200 {
diff --git a/dts/Bindings/spi/spi-fsl-dspi.txt b/dts/Bindings/spi/spi-fsl-dspi.txt
index ff5893d275..13b1fcc846 100644
--- a/dts/Bindings/spi/spi-fsl-dspi.txt
+++ b/dts/Bindings/spi/spi-fsl-dspi.txt
@@ -39,7 +39,6 @@ dspi0@4002c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi0_1>;
big-endian;
- status = "okay";
sflash: at26df081a@0 {
#address-cells = <1>;
diff --git a/dts/Bindings/spi/spi-mt65xx.txt b/dts/Bindings/spi/spi-mt65xx.txt
index e0318cf92d..236dcb0faf 100644
--- a/dts/Bindings/spi/spi-mt65xx.txt
+++ b/dts/Bindings/spi/spi-mt65xx.txt
@@ -57,5 +57,4 @@ spi: spi@1100a000 {
clock-names = "parent-clk", "sel-clk", "spi-clk";
cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
mediatek,pad-select = <1>, <0>;
- status = "disabled";
};
diff --git a/dts/Bindings/spi/spi-orion.txt b/dts/Bindings/spi/spi-orion.txt
index 4f629cc763..df8ec31f2f 100644
--- a/dts/Bindings/spi/spi-orion.txt
+++ b/dts/Bindings/spi/spi-orion.txt
@@ -29,7 +29,6 @@ Example:
cell-index = <0>;
reg = <0x10600 0x28>;
interrupts = <23>;
- status = "disabled";
};
Example with SPI direct mode support (optionally):
@@ -48,7 +47,6 @@ Example with SPI direct mode support (optionally):
<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
interrupts = <23>;
- status = "disabled";
};
To enable the direct mode, the board specific 'ranges' property in the
diff --git a/dts/Bindings/spi/spi-rockchip.txt b/dts/Bindings/spi/spi-rockchip.txt
index 83da4931d8..6e3ffacbba 100644
--- a/dts/Bindings/spi/spi-rockchip.txt
+++ b/dts/Bindings/spi/spi-rockchip.txt
@@ -6,6 +6,7 @@ and display controllers using the SPI communication interface.
Required Properties:
- compatible: should be one of the following.
+ "rockchip,rv1108-spi" for rv1108 SoCs.
"rockchip,rk3036-spi" for rk3036 SoCS.
"rockchip,rk3066-spi" for rk3066 SoCs.
"rockchip,rk3188-spi" for rk3188 SoCs.
diff --git a/dts/Bindings/spi/spi-sun4i.txt b/dts/Bindings/spi/spi-sun4i.txt
index de827f5a30..484bbff533 100644
--- a/dts/Bindings/spi/spi-sun4i.txt
+++ b/dts/Bindings/spi/spi-sun4i.txt
@@ -18,7 +18,6 @@ spi1: spi@01c06000 {
interrupts = <11>;
clocks = <&ahb_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
- status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
diff --git a/dts/Bindings/spi/spi-sun6i.txt b/dts/Bindings/spi/spi-sun6i.txt
index 2ec99b86b6..ab1811354c 100644
--- a/dts/Bindings/spi/spi-sun6i.txt
+++ b/dts/Bindings/spi/spi-sun6i.txt
@@ -39,7 +39,6 @@ spi0: spi@01c68000 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
resets = <&ccu RST_BUS_SPI0>;
- status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
diff --git a/dts/Bindings/spi/spi_atmel.txt b/dts/Bindings/spi/spi_atmel.txt
index fb588b3e6a..f99c733d75 100644
--- a/dts/Bindings/spi/spi_atmel.txt
+++ b/dts/Bindings/spi/spi_atmel.txt
@@ -26,7 +26,6 @@ spi1: spi@fffcc000 {
clock-names = "spi_clk";
cs-gpios = <&pioB 3 0>;
atmel,fifo-size = <32>;
- status = "okay";
mmc-slot@0 {
compatible = "mmc-spi-slot";
diff --git a/dts/Bindings/sram/renesas,smp-sram.txt b/dts/Bindings/sram/renesas,smp-sram.txt
new file mode 100644
index 0000000000..712d05e3e1
--- /dev/null
+++ b/dts/Bindings/sram/renesas,smp-sram.txt
@@ -0,0 +1,27 @@
+* Renesas SMP SRAM
+
+Renesas R-Car Gen2 and RZ/G1 SoCs need a small piece of SRAM for the jump stub
+for secondary CPU bringup and CPU hotplug.
+This memory is reserved by adding a child node to a "mmio-sram" node, cfr.
+Documentation/devicetree/bindings/sram/sram.txt.
+
+Required child node properties:
+ - compatible: Must be "renesas,smp-sram",
+ - reg: Address and length of the reserved SRAM.
+ The full physical (bus) address must be aligned to a 256 KiB boundary.
+
+
+Example:
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
diff --git a/dts/Bindings/sram/sunxi-sram.txt b/dts/Bindings/sram/sunxi-sram.txt
index 8d5665468f..6bb92a1df7 100644
--- a/dts/Bindings/sram/sunxi-sram.txt
+++ b/dts/Bindings/sram/sunxi-sram.txt
@@ -9,7 +9,9 @@ Controller Node
---------------
Required properties:
-- compatible : "allwinner,sun4i-a10-sram-controller"
+- compatible : should be:
+ - "allwinner,sun4i-a10-sram-controller"
+ - "allwinner,sun50i-a64-sram-controller"
- reg : sram controller register offset + length
SRAM nodes
@@ -22,10 +24,13 @@ Each SRAM will have SRAM sections that are going to be handled by the
SRAM controller as subnodes. These sections are represented following
once again the representation described in the mmio-sram binding.
-The valid sections compatible are:
+The valid sections compatible for A10 are:
- allwinner,sun4i-a10-sram-a3-a4
- allwinner,sun4i-a10-sram-d
+The valid sections compatible for A64 are:
+ - allwinner,sun50i-a64-sram-c
+
Devices using SRAM sections
---------------------------
@@ -59,7 +64,6 @@ sram-controller@01c00000 {
emac_sram: sram-section@8000 {
compatible = "allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
- status = "disabled";
};
};
};
diff --git a/dts/Bindings/thermal/armada-thermal.txt b/dts/Bindings/thermal/armada-thermal.txt
index 4698e0edc2..24aacf8948 100644
--- a/dts/Bindings/thermal/armada-thermal.txt
+++ b/dts/Bindings/thermal/armada-thermal.txt
@@ -20,5 +20,4 @@ Example:
compatible = "marvell,armada370-thermal";
reg = <0xd0018300 0x4
0xd0018304 0x4>;
- status = "okay";
};
diff --git a/dts/Bindings/thermal/exynos-thermal.txt b/dts/Bindings/thermal/exynos-thermal.txt
index 70b4c16c7e..9b4c7b0174 100644
--- a/dts/Bindings/thermal/exynos-thermal.txt
+++ b/dts/Bindings/thermal/exynos-thermal.txt
@@ -77,7 +77,6 @@ Example 1):
interrupts = <2 4>;
clocks = <&clock 383>;
clock-names = "tmu_apbif";
- status = "disabled";
vtmu-supply = <&tmu_regulator_node>;
#include "exynos4412-tmu-sensor-conf.dtsi"
};
diff --git a/dts/Bindings/thermal/mediatek-thermal.txt b/dts/Bindings/thermal/mediatek-thermal.txt
index e2f494d74d..0d73ea5e9c 100644
--- a/dts/Bindings/thermal/mediatek-thermal.txt
+++ b/dts/Bindings/thermal/mediatek-thermal.txt
@@ -11,6 +11,7 @@ Required properties:
- compatible:
- "mediatek,mt8173-thermal" : For MT8173 family of SoCs
- "mediatek,mt2701-thermal" : For MT2701 family of SoCs
+ - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
- reg: Address range of the thermal controller
- interrupts: IRQ for the thermal controller
- clocks, clock-names: Clocks needed for the thermal controller. required
diff --git a/dts/Bindings/thermal/rcar-gen3-thermal.txt b/dts/Bindings/thermal/rcar-gen3-thermal.txt
index 07a9713ae6..fdf5caa622 100644
--- a/dts/Bindings/thermal/rcar-gen3-thermal.txt
+++ b/dts/Bindings/thermal/rcar-gen3-thermal.txt
@@ -36,7 +36,6 @@ Example:
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#thermal-sensor-cells = <1>;
- status = "okay";
};
thermal-zones {
diff --git a/dts/Bindings/thermal/rockchip-thermal.txt b/dts/Bindings/thermal/rockchip-thermal.txt
index 43003aec94..e3a6234fb1 100644
--- a/dts/Bindings/thermal/rockchip-thermal.txt
+++ b/dts/Bindings/thermal/rockchip-thermal.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible : should be "rockchip,<name>-tsadc"
"rockchip,rk3228-tsadc": found on RK3228 SoCs
"rockchip,rk3288-tsadc": found on RK3288 SoCs
+ "rockchip,rk3328-tsadc": found on RK3328 SoCs
"rockchip,rk3368-tsadc": found on RK3368 SoCs
"rockchip,rk3399-tsadc": found on RK3399 SoCs
- reg : physical base address of the controller and length of memory mapped
diff --git a/dts/Bindings/thermal/uniphier-thermal.txt b/dts/Bindings/thermal/uniphier-thermal.txt
new file mode 100644
index 0000000000..686c0b42ed
--- /dev/null
+++ b/dts/Bindings/thermal/uniphier-thermal.txt
@@ -0,0 +1,64 @@
+* UniPhier Thermal bindings
+
+This describes the devicetree bindings for thermal monitor supported by
+PVT(Process, Voltage and Temperature) monitoring unit implemented on Socionext
+UniPhier SoCs.
+
+Required properties:
+- compatible :
+ - "socionext,uniphier-pxs2-thermal" : For UniPhier PXs2 SoC
+ - "socionext,uniphier-ld20-thermal" : For UniPhier LD20 SoC
+- interrupts : IRQ for the temperature alarm
+- #thermal-sensor-cells : Should be 0. See ./thermal.txt for details.
+
+Optional properties:
+- socionext,tmod-calibration: A pair of calibrated values referred from PVT,
+ in case that the values aren't set on SoC,
+ like a reference board.
+
+Example:
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-ld20-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+ ...
+ pvtctl: pvtctl {
+ compatible = "socionext,uniphier-ld20-thermal";
+ interrupts = <0 3 1>;
+ #thermal-sensor-cells = <0>;
+ };
+ ...
+ };
+
+ thermal-zones {
+ cpu_thermal {
+ polling-delay-passive = <250>; /* 250ms */
+ polling-delay = <1000>; /* 1000ms */
+ thermal-sensors = <&pvtctl>;
+
+ trips {
+ cpu_crit: cpu_crit {
+ temperature = <110000>; /* 110C */
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ cpu_alert: cpu_alert {
+ temperature = <100000>; /* 100C */
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 (-1) (-1)>;
+ };
+ map1 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu2 (-1) (-1)>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/timer/nxp,tpm-timer.txt b/dts/Bindings/timer/nxp,tpm-timer.txt
new file mode 100644
index 0000000000..b4aa7ddb5b
--- /dev/null
+++ b/dts/Bindings/timer/nxp,tpm-timer.txt
@@ -0,0 +1,28 @@
+NXP Low Power Timer/Pulse Width Modulation Module (TPM)
+
+The Timer/PWM Module (TPM) supports input capture, output compare,
+and the generation of PWM signals to control electric motor and power
+management applications. The counter, compare and capture registers
+are clocked by an asynchronous clock that can remain enabled in low
+power modes. TPM can support global counter bus where one TPM drives
+the counter bus for the others, provided bit width is the same.
+
+Required properties:
+
+- compatible : should be "fsl,imx7ulp-tpm"
+- reg : Specifies base physical address and size of the register sets
+ for the clock event device and clock source device.
+- interrupts : Should be the clock event device interrupt.
+- clocks : The clocks provided by the SoC to drive the timer, must contain
+ an entry for each entry in clock-names.
+- clock-names : Must include the following entries: "igp" and "per".
+
+Example:
+tpm5: tpm@40260000 {
+ compatible = "fsl,imx7ulp-tpm";
+ reg = <0x40260000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_LPTPM5>;
+ clock-names = "ipg", "per";
+};
diff --git a/dts/Bindings/timer/renesas,cmt.txt b/dts/Bindings/timer/renesas,cmt.txt
index 1a05c1b243..6ca6b9e582 100644
--- a/dts/Bindings/timer/renesas,cmt.txt
+++ b/dts/Bindings/timer/renesas,cmt.txt
@@ -12,46 +12,29 @@ datasheets.
Required Properties:
- compatible: must contain one or more of the following:
- - "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT
- (CMT0)
- - "renesas,cmt-32-sh7372" for the sh7372 32-bit CMT
- (CMT0)
- - "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT
- (CMT0)
- - "renesas,cmt-32" for all 32-bit CMT without fast clock support
- (CMT0 on sh7372, sh73a0 and r8a7740)
- This is a fallback for the above renesas,cmt-32-* entries.
-
- - "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast
- clock support (CMT[234])
- - "renesas,cmt-32-fast-sh7372" for the sh7372 32-bit CMT with fast
- clock support (CMT[234])
- - "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast
- clock support (CMT[234])
- - "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support
- (CMT[234] on sh7372, sh73a0 and r8a7740)
- This is a fallback for the above renesas,cmt-32-fast-* entries.
-
- - "renesas,cmt-48-sh7372" for the sh7372 48-bit CMT
- (CMT1)
- "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT
(CMT1)
- "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT
(CMT1)
- "renesas,cmt-48" for all non-second generation 48-bit CMT
- (CMT1 on sh7372, sh73a0 and r8a7740)
+ (CMT1 on sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-48-* entries.
- - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT
- (CMT[01])
- - "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT
- (CMT[01])
- - "renesas,cmt-48-r8a7791" for the r8a7791 48-bit CMT
- (CMT[01])
- - "renesas,cmt-48-gen2" for all second generation 48-bit CMT
- (CMT[01] on r8a73a4, r8a7790 and r8a7791)
- This is a fallback for the renesas,cmt-48-r8a73a4,
- renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries.
+ - "renesas,cmt0-r8a73a4" for the 32-bit CMT0 device included in r8a73a4.
+ - "renesas,cmt1-r8a73a4" for the 48-bit CMT1 device included in r8a73a4.
+ - "renesas,cmt0-r8a7790" for the 32-bit CMT0 device included in r8a7790.
+ - "renesas,cmt1-r8a7790" for the 48-bit CMT1 device included in r8a7790.
+ - "renesas,cmt0-r8a7791" for the 32-bit CMT0 device included in r8a7791.
+ - "renesas,cmt1-r8a7791" for the 48-bit CMT1 device included in r8a7791.
+ - "renesas,cmt0-r8a7793" for the 32-bit CMT0 device included in r8a7793.
+ - "renesas,cmt1-r8a7793" for the 48-bit CMT1 device included in r8a7793.
+ - "renesas,cmt0-r8a7794" for the 32-bit CMT0 device included in r8a7794.
+ - "renesas,cmt1-r8a7794" for the 48-bit CMT1 device included in r8a7794.
+
+ - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2.
+ - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2.
+ These are fallbacks for r8a73a4 and all the R-Car Gen2
+ entries listed above.
- reg: base address and length of the registers block for the timer module.
- interrupts: interrupt-specifier for the timer, one per channel.
@@ -59,21 +42,29 @@ Required Properties:
in clock-names.
- clock-names: must contain "fck" for the functional clock.
- - renesas,channels-mask: bitmask of the available channels.
-
-Example: R8A7790 (R-Car H2) CMT0 node
-
- CMT0 on R8A7790 implements hardware channels 5 and 6 only and names
- them channels 0 and 1 in the documentation.
+Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes
cmt0: timer@ffca0000 {
- compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+ compatible = "renesas,cmt0-r8a7790", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
<0 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
clock-names = "fck";
+ };
- renesas,channels-mask = <0x60>;
+ cmt1: timer@e6130000 {
+ compatible = "renesas,cmt1-r8a7790", "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
+ <0 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
+ clock-names = "fck";
};
diff --git a/dts/Bindings/trivial-devices.txt b/dts/Bindings/trivial-devices.txt
index 35f406dd86..af284fbd4d 100644
--- a/dts/Bindings/trivial-devices.txt
+++ b/dts/Bindings/trivial-devices.txt
@@ -21,6 +21,16 @@ adi,adt7490 +/-1C TDM Extended Temp Range I.C
adi,adxl345 Three-Axis Digital Accelerometer
adi,adxl346 Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too)
ams,iaq-core AMS iAQ-Core VOC Sensor
+amstaos,tsl2571 AMS/TAOS ALS and proximity sensor
+amstaos,tsl2671 AMS/TAOS ALS and proximity sensor
+amstaos,tmd2671 AMS/TAOS ALS and proximity sensor
+amstaos,tsl2771 AMS/TAOS ALS and proximity sensor
+amstaos,tmd2771 AMS/TAOS ALS and proximity sensor
+amstaos,tsl2572 AMS/TAOS ALS and proximity sensor
+amstaos,tsl2672 AMS/TAOS ALS and proximity sensor
+amstaos,tmd2672 AMS/TAOS ALS and proximity sensor
+amstaos,tsl2772 AMS/TAOS ALS and proximity sensor
+amstaos,tmd2772 AMS/TAOS ALS and proximity sensor
at,24c08 i2c serial eeprom (24cxx)
atmel,at97sc3204t i2c trusted platform module (TPM)
capella,cm32181 CM32181: Ambient Light Sensor
@@ -36,7 +46,9 @@ dallas,ds1775 Tiny Digital Thermometer and Thermostat
dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
dallas,ds75 Digital Thermometer and Thermostat
+devantech,srf02 Devantech SRF02 ultrasonic ranger in I2C mode
devantech,srf08 Devantech SRF08 ultrasonic ranger
+devantech,srf10 Devantech SRF10 ultrasonic ranger
dlg,da9053 DA9053: flexible system level PMIC with multicore support
dlg,da9063 DA9063: system PMIC for quad-core application processors
domintech,dmard09 DMARD09: 3-axis Accelerometer
@@ -54,6 +66,7 @@ fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz)
+isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM
isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor
isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor
maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
@@ -168,6 +181,7 @@ st,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
ti,ads7828 8-Channels, 12-bit ADC
ti,ads7830 8-Channels, 8-bit ADC
+ti,amc6821 Temperature Monitoring and Fan Control
ti,tsc2003 I2C Touch-Screen Controller
ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
diff --git a/dts/Bindings/unittest.txt b/dts/Bindings/unittest.txt
index 3bf58c20fe..9a5b311f44 100644
--- a/dts/Bindings/unittest.txt
+++ b/dts/Bindings/unittest.txt
@@ -10,7 +10,6 @@ All other properties are optional.
Example:
unittest {
compatible = "unittest";
- status = "okay";
};
2) OF unittest i2c adapter platform device
@@ -25,7 +24,6 @@ Children nodes contain unittest i2c devices.
Example:
unittest-i2c-bus {
compatible = "unittest-i2c-bus";
- status = "okay";
};
3) OF unittest i2c device
@@ -40,7 +38,6 @@ All other properties are optional
Example:
unittest-i2c-dev {
compatible = "unittest-i2c-dev";
- status = "okay";
};
4) OF unittest i2c mux device
@@ -55,7 +52,6 @@ Children nodes contain unittest i2c bus nodes per channel.
Example:
unittest-i2c-mux {
compatible = "unittest-i2c-mux";
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
channel-0 {
@@ -65,7 +61,6 @@ Example:
i2c-dev {
reg = <8>;
compatible = "unittest-i2c-dev";
- status = "okay";
};
};
};
diff --git a/dts/Bindings/usb/allwinner,sun4i-a10-musb.txt b/dts/Bindings/usb/allwinner,sun4i-a10-musb.txt
index d9b42da016..cb2bd83fa8 100644
--- a/dts/Bindings/usb/allwinner,sun4i-a10-musb.txt
+++ b/dts/Bindings/usb/allwinner,sun4i-a10-musb.txt
@@ -25,5 +25,4 @@ Example:
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
- status = "disabled";
};
diff --git a/dts/Bindings/usb/am33xx-usb.txt b/dts/Bindings/usb/am33xx-usb.txt
index 20c2ff2ba0..16920d78e1 100644
--- a/dts/Bindings/usb/am33xx-usb.txt
+++ b/dts/Bindings/usb/am33xx-usb.txt
@@ -4,9 +4,9 @@
- reg: offset and length of the usbss register sets
- ti,hwmods : must be "usb_otg_hs"
-The glue layer contains multiple child nodes. It is required the have
+The glue layer contains multiple child nodes. It is required to have
at least a control module node, USB node and a PHY node. The second USB
-node and its PHY node is optional. The DMA node is also optional.
+node and its PHY node are optional. The DMA node is also optional.
Reset module
~~~~~~~~~~~~
diff --git a/dts/Bindings/usb/brcm,bdc.txt b/dts/Bindings/usb/brcm,bdc.txt
new file mode 100644
index 0000000000..63e63af3bf
--- /dev/null
+++ b/dts/Bindings/usb/brcm,bdc.txt
@@ -0,0 +1,29 @@
+Broadcom USB Device Controller (BDC)
+====================================
+
+Required properties:
+
+- compatible: must be one of:
+ "brcm,bdc-v0.16"
+ "brcm,bdc"
+- reg: the base register address and length
+- interrupts: the interrupt line for this controller
+
+Optional properties:
+
+On Broadcom STB platforms, these properties are required:
+
+- phys: phandle to one or two USB PHY blocks
+ NOTE: Some SoC's have a single phy and some have
+ USB 2.0 and USB 3.0 phys
+- clocks: phandle to the functional clock of this block
+
+Example:
+
+ bdc@f0b02000 {
+ compatible = "brcm,bdc-v0.16";
+ reg = <0xf0b02000 0xfc4>;
+ interrupts = <0x0 0x60 0x0>;
+ phys = <&usbphy_0 0x0>;
+ clocks = <&sw_usbd>;
+ };
diff --git a/dts/Bindings/usb/da8xx-usb.txt b/dts/Bindings/usb/da8xx-usb.txt
index 717c5f6562..9ce22551b2 100644
--- a/dts/Bindings/usb/da8xx-usb.txt
+++ b/dts/Bindings/usb/da8xx-usb.txt
@@ -42,7 +42,6 @@ Example:
usb_phy: usb-phy {
compatible = "ti,da830-usb-phy";
#phy-cells = <0>;
- status = "okay";
};
usb0: usb@200000 {
compatible = "ti,da830-musb";
@@ -66,7 +65,6 @@ Example:
"rx1", "rx2", "rx3", "rx4",
"tx1", "tx2", "tx3", "tx4";
- status = "okay";
cppi41dma: dma-controller@201000 {
compatible = "ti,da830-cppi41";
diff --git a/dts/Bindings/usb/dwc3-st.txt b/dts/Bindings/usb/dwc3-st.txt
index 50dee3b446..df0e02e1ee 100644
--- a/dts/Bindings/usb/dwc3-st.txt
+++ b/dts/Bindings/usb/dwc3-st.txt
@@ -42,7 +42,6 @@ or "device".
Example:
st_dwc3: dwc3@8f94000 {
- status = "disabled";
compatible = "st,stih407-dwc3";
reg = <0x08f94000 0x1000>, <0x110 0x4>;
reg-names = "reg-glue", "syscfg-reg";
diff --git a/dts/Bindings/usb/dwc3-xilinx.txt b/dts/Bindings/usb/dwc3-xilinx.txt
index 30361b32a4..4aae5b2cef 100644
--- a/dts/Bindings/usb/dwc3-xilinx.txt
+++ b/dts/Bindings/usb/dwc3-xilinx.txt
@@ -18,7 +18,6 @@ Example device node:
usb@0 {
#address-cells = <0x2>;
#size-cells = <0x1>;
- status = "okay";
compatible = "xlnx,zynqmp-dwc3";
clock-names = "bus_clk" "ref_clk";
clocks = <&clk125>, <&clk125>;
diff --git a/dts/Bindings/usb/ehci-st.txt b/dts/Bindings/usb/ehci-st.txt
index 410d922cfd..9feea6c3e4 100644
--- a/dts/Bindings/usb/ehci-st.txt
+++ b/dts/Bindings/usb/ehci-st.txt
@@ -31,7 +31,6 @@ Example:
clocks = <&clk_s_a1_ls 0>;
phys = <&usb2_phy>;
phy-names = "usb";
- status = "okay";
resets = <&powerdown STIH416_USB1_POWERDOWN>,
<&softreset STIH416_USB1_SOFTRESET>;
diff --git a/dts/Bindings/usb/exynos-usb.txt b/dts/Bindings/usb/exynos-usb.txt
index 78ebebb66d..c973743150 100644
--- a/dts/Bindings/usb/exynos-usb.txt
+++ b/dts/Bindings/usb/exynos-usb.txt
@@ -40,7 +40,6 @@ Example:
port@0 {
reg = <0>;
phys = <&usb2phy 1>;
- status = "disabled";
};
};
@@ -75,7 +74,6 @@ Example:
port@0 {
reg = <0>;
phys = <&usb2phy 1>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/usb/fcs,fusb302.txt b/dts/Bindings/usb/fcs,fusb302.txt
new file mode 100644
index 0000000000..472facfa5a
--- /dev/null
+++ b/dts/Bindings/usb/fcs,fusb302.txt
@@ -0,0 +1,29 @@
+Fairchild FUSB302 Type-C Port controllers
+
+Required properties :
+- compatible : "fcs,fusb302"
+- reg : I2C slave address
+- interrupts : Interrupt specifier
+
+Optional properties :
+- fcs,max-sink-microvolt : Maximum voltage to negotiate when configured as sink
+- fcs,max-sink-microamp : Maximum current to negotiate when configured as sink
+- fcs,max-sink-microwatt : Maximum power to negotiate when configured as sink
+ If this is less then max-sink-microvolt *
+ max-sink-microamp then the configured current will
+ be clamped.
+- fcs,operating-sink-microwatt :
+ Minimum amount of power accepted from a sink
+ when negotiating
+
+Example:
+
+fusb302: typec-portc@54 {
+ compatible = "fcs,fusb302";
+ reg = <0x54>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ fcs,max-sink-microvolt = <12000000>;
+ fcs,max-sink-microamp = <3000000>;
+ fcs,max-sink-microwatt = <36000000>;
+};
diff --git a/dts/Bindings/usb/isp1301.txt b/dts/Bindings/usb/isp1301.txt
index 5405d99d9a..ecd607dacb 100644
--- a/dts/Bindings/usb/isp1301.txt
+++ b/dts/Bindings/usb/isp1301.txt
@@ -21,5 +21,4 @@ Example:
interrupt-parent = <&mic>;
interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
transceiver = <&isp1301>;
- status = "okay";
};
diff --git a/dts/Bindings/usb/keystone-usb.txt b/dts/Bindings/usb/keystone-usb.txt
index 60527d335b..f96e09f784 100644
--- a/dts/Bindings/usb/keystone-usb.txt
+++ b/dts/Bindings/usb/keystone-usb.txt
@@ -12,8 +12,21 @@ Required properties:
MPU.
- ranges: allows valid 1:1 translation between child's address space and
parent's address space.
- - clocks: Clock IDs array as required by the controller.
- - clock-names: names of clocks correseponding to IDs in the clock property.
+
+SoC-specific Required Properties:
+The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E
+SoCs only:
+
+- clocks: Clock ID for USB functional clock.
+- clock-names: Must be "usb".
+
+
+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
+
+- power-domains: Should contain a phandle to a PM domain provider node
+ and an args specifier containing the USB device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
Sub-nodes:
The dwc3 core should be added as subnode to Keystone DWC3 glue.
@@ -31,7 +44,6 @@ Example:
clock-names = "usb";
interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
ranges;
- status = "disabled";
dwc3@2690000 {
compatible = "synopsys,dwc3";
diff --git a/dts/Bindings/usb/mt8173-xhci.txt b/dts/Bindings/usb/mediatek,mtk-xhci.txt
index 0acfc8acbe..5611a2e4dd 100644
--- a/dts/Bindings/usb/mt8173-xhci.txt
+++ b/dts/Bindings/usb/mediatek,mtk-xhci.txt
@@ -11,7 +11,11 @@ into two parts.
------------------------------------------------------------------------
Required properties:
- - compatible : should contain "mediatek,mt8173-xhci"
+ - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
+ soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
+ "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
+ addition, one of:
+ - "mediatek,mt8173-xhci"
- reg : specifies physical base address and size of the registers
- reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
- interrupts : interrupt used by the controller
@@ -68,10 +72,14 @@ usb30: usb@11270000 {
In the case, xhci is added as subnode to mtu3. An example and the DT binding
details of mtu3 can be found in:
-Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
+Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
Required properties:
- - compatible : should contain "mediatek,mt8173-xhci"
+ - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
+ soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
+ "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
+ addition, one of:
+ - "mediatek,mt8173-xhci"
- reg : specifies physical base address and size of the registers
- reg-names: should be "mac" for xHCI MAC
- interrupts : interrupt used by the host controller
diff --git a/dts/Bindings/usb/mt8173-mtu3.txt b/dts/Bindings/usb/mediatek,mtu3.txt
index 1d7c3bc677..49f54767cd 100644
--- a/dts/Bindings/usb/mt8173-mtu3.txt
+++ b/dts/Bindings/usb/mediatek,mtu3.txt
@@ -1,7 +1,11 @@
The device node for Mediatek USB3.0 DRD controller
Required properties:
- - compatible : should be "mediatek,mt8173-mtu3"
+ - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3",
+ soc-model is the name of SoC, such as mt8173, mt2712 etc,
+ when using "mediatek,mtu3" compatible string, you need SoC specific
+ ones in addition, one of:
+ - "mediatek,mt8173-mtu3"
- reg : specifies physical base address and size of the registers
- reg-names: should be "mac" for device IP and "ippc" for IP port control
- interrupts : interrupt used by the device IP
@@ -44,7 +48,7 @@ Optional properties:
Sub-nodes:
The xhci should be added as subnode to mtu3 as shown in the following example
if host mode is enabled. The DT binding details of xhci can be found in:
-Documentation/devicetree/bindings/usb/mt8173-xhci.txt
+Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
Example:
ssusb: usb@11271000 {
@@ -71,7 +75,6 @@ ssusb: usb@11271000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
- status = "disabled";
usb_host: xhci@11270000 {
compatible = "mediatek,mt8173-xhci";
@@ -82,6 +85,5 @@ ssusb: usb@11271000 {
clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
clock-names = "sys_ck", "ref_ck";
vusb33-supply = <&mt6397_vusb_reg>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/usb/ohci-st.txt b/dts/Bindings/usb/ohci-st.txt
index 6d8393748d..d893ec9131 100644
--- a/dts/Bindings/usb/ohci-st.txt
+++ b/dts/Bindings/usb/ohci-st.txt
@@ -29,7 +29,6 @@ Example:
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
- status = "okay";
resets = <&powerdown STIH416_USB0_POWERDOWN>,
<&softreset STIH416_USB0_SOFTRESET>;
diff --git a/dts/Bindings/usb/qcom,dwc3.txt b/dts/Bindings/usb/qcom,dwc3.txt
index 73cc0963e8..bc8a2fa5d2 100644
--- a/dts/Bindings/usb/qcom,dwc3.txt
+++ b/dts/Bindings/usb/qcom,dwc3.txt
@@ -29,7 +29,6 @@ Example device nodes:
clock-names = "ref";
#phy-cells = <0>;
- status = "ok";
};
ss_phy: phy@100f8830 {
@@ -39,7 +38,6 @@ Example device nodes:
clock-names = "ref";
#phy-cells = <0>;
- status = "ok";
};
usb3_0: usb30@0 {
@@ -51,7 +49,6 @@ Example device nodes:
ranges;
- status = "ok";
dwc3@10000000 {
compatible = "snps,dwc3";
diff --git a/dts/Bindings/usb/renesas_usb3.txt b/dts/Bindings/usb/renesas_usb3.txt
index 8d52766f07..e28025883b 100644
--- a/dts/Bindings/usb/renesas_usb3.txt
+++ b/dts/Bindings/usb/renesas_usb3.txt
@@ -3,20 +3,30 @@ Renesas Electronics USB3.0 Peripheral driver
Required properties:
- compatible: Must contain one of the following:
- "renesas,r8a7795-usb3-peri"
+ - "renesas,r8a7796-usb3-peri"
+ - "renesas,rcar-gen3-usb3-peri" for a generic R-Car Gen3 compatible
+ device
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
- reg: Base address and length of the register for the USB3.0 Peripheral
- interrupts: Interrupt specifier for the USB3.0 Peripheral
- clocks: clock phandle and specifier pair
-Example:
+Example of R-Car H3 ES1.x:
usb3_peri0: usb@ee020000 {
- compatible = "renesas,r8a7795-usb3-peri";
+ compatible = "renesas,r8a7795-usb3-peri",
+ "renesas,rcar-gen3-usb3-peri";
reg = <0 0xee020000 0 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
};
usb3_peri1: usb@ee060000 {
- compatible = "renesas,r8a7795-usb3-peri";
+ compatible = "renesas,r8a7795-usb3-peri",
+ "renesas,rcar-gen3-usb3-peri";
reg = <0 0xee060000 0 0x400>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 327>;
diff --git a/dts/Bindings/usb/rockchip,dwc3.txt b/dts/Bindings/usb/rockchip,dwc3.txt
index 0536a938e3..50a31536e9 100644
--- a/dts/Bindings/usb/rockchip,dwc3.txt
+++ b/dts/Bindings/usb/rockchip,dwc3.txt
@@ -29,13 +29,11 @@ Example device nodes:
#address-cells = <2>;
#size-cells = <2>;
ranges;
- status = "disabled";
usbdrd_dwc3_0: dwc3@fe800000 {
compatible = "snps,dwc3";
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "otg";
- status = "disabled";
};
};
@@ -48,12 +46,10 @@ Example device nodes:
#address-cells = <2>;
#size-cells = <2>;
ranges;
- status = "disabled";
usbdrd_dwc3_1: dwc3@fe900000 {
compatible = "snps,dwc3";
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "otg";
- status = "disabled";
};
};
diff --git a/dts/Bindings/usb/usb-device.txt b/dts/Bindings/usb/usb-device.txt
index 1c35e7b665..ce02cebac2 100644
--- a/dts/Bindings/usb/usb-device.txt
+++ b/dts/Bindings/usb/usb-device.txt
@@ -2,7 +2,7 @@ Generic USB Device Properties
Usually, we only use device tree for hard wired USB device.
The reference binding doc is from:
-http://www.firmware.org/1275/bindings/usb/usb-1_0.ps
+http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps
Required properties:
- compatible: usbVID,PID. The textual representation of VID, PID shall
@@ -16,7 +16,6 @@ Required properties:
Example:
&usb1 {
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/vendor-prefixes.txt b/dts/Bindings/vendor-prefixes.txt
index daf465bef7..1ea1fd4232 100644
--- a/dts/Bindings/vendor-prefixes.txt
+++ b/dts/Bindings/vendor-prefixes.txt
@@ -9,6 +9,7 @@ actions Actions Semiconductor Co., Ltd.
active-semi Active-Semi International Inc
ad Avionic Design GmbH
adapteva Adapteva, Inc.
+adaptrum Adaptrum, Inc.
adh AD Holdings Plc.
adi Analog Devices, Inc.
advantech Advantech Corporation
@@ -47,6 +48,7 @@ avic Shanghai AVIC Optoelectronics Co., Ltd.
axentia Axentia Technologies AB
axis Axis Communications AB
bananapi BIPAI KEJI LIMITED
+bhf Beckhoff Automation GmbH & Co. KG
boe BOE Technology Group Co., Ltd.
bosch Bosch Sensortec GmbH
boundary Boundary Devices Inc.
@@ -88,6 +90,7 @@ dlg Dialog Semiconductor
dlink D-Link Corporation
dmo Data Modul AG
domintech Domintech Co., Ltd.
+dongwoon Dongwoon Anatech
dptechnics DPTechnics
dragino Dragino Technology Co., Limited
ea Embedded Artists AB
@@ -175,6 +178,7 @@ kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation
lacie LaCie
lantiq Lantiq Semiconductor
+lattice Lattice Semiconductor
lego LEGO Systems A/S
lenovo Lenovo Group Ltd.
lg LG Corporation
@@ -195,6 +199,7 @@ mediatek MediaTek Inc.
megachips MegaChips
melexis Melexis N.V.
melfas MELFAS Inc.
+mellanox Mellanox Technologies
memsic MEMSIC Inc.
merrii Merrii Technology Co., Ltd.
micrel Micrel Inc.
@@ -206,7 +211,7 @@ miramems MiraMEMS Sensing Technology Co., Ltd.
mitsubishi Mitsubishi Electric Corporation
mosaixtech Mosaix Technologies, Inc.
motorola Motorola, Inc.
-moxa Moxa
+moxa Moxa Inc.
mpl MPL AG
mqmaker mqmaker Inc.
msi Micro-Star International Co. Ltd.
@@ -249,6 +254,7 @@ oxsemi Oxford Semiconductor, Ltd.
panasonic Panasonic Corporation
parade Parade Technologies Inc.
pericom Pericom Technology Inc.
+pervasive Pervasive Displays, Inc.
phytec PHYTEC Messtechnik GmbH
picochip Picochip Ltd
pine64 Pine64
@@ -287,6 +293,7 @@ schindler Schindler
seagate Seagate Technology PLC
semtech Semtech Corporation
sensirion Sensirion AG
+sff Small Form Factor Committee
sgx SGX Sensortech
sharp Sharp Corporation
si-en Si-En Technology Ltd.
@@ -341,6 +348,7 @@ tpo TPO
tronfy Tronfy
tronsmart Tronsmart
truly Truly Semiconductors Limited
+tsd Theobroma Systems Design und Consulting GmbH
tyan Tyan Computer Corporation
ucrobotics uCRobotics
udoo Udoo
@@ -353,6 +361,7 @@ variscite Variscite Ltd.
via VIA Technologies, Inc.
virtio Virtual I/O Device Specification, developed by the OASIS consortium
vivante Vivante Corporation
+vocore VoCore Studio
voipac Voipac Technologies s.r.o.
wd Western Digital Corp.
wetek WeTek Electronics, limited.
diff --git a/dts/Bindings/w1/fsl-imx-owire.txt b/dts/Bindings/w1/fsl-imx-owire.txt
index ecf42c0768..cbaa6467ab 100644
--- a/dts/Bindings/w1/fsl-imx-owire.txt
+++ b/dts/Bindings/w1/fsl-imx-owire.txt
@@ -15,5 +15,4 @@ owire: owire@63fa4000 {
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
reg = <0x63fa4000 0x4000>;
clocks = <&clks 159>;
- status = "disabled";
};
diff --git a/dts/Bindings/watchdog/aspeed-wdt.txt b/dts/Bindings/watchdog/aspeed-wdt.txt
index c5e74d7b44..c5077a1f5c 100644
--- a/dts/Bindings/watchdog/aspeed-wdt.txt
+++ b/dts/Bindings/watchdog/aspeed-wdt.txt
@@ -8,9 +8,49 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped
region
+Optional properties:
+
+ - aspeed,reset-type = "cpu|soc|system|none"
+
+ Reset behavior - Whenever a timeout occurs the watchdog can be programmed
+ to generate one of three different, mutually exclusive, types of resets.
+
+ Type "none" can be specified to indicate that no resets are to be done.
+ This is useful in situations where another watchdog engine on chip is
+ to perform the reset.
+
+ If 'aspeed,reset-type=' is not specfied the default is to enable system
+ reset.
+
+ Reset types:
+
+ - cpu: Reset CPU on watchdog timeout
+
+ - soc: Reset 'System on Chip' on watchdog timeout
+
+ - system: Reset system on watchdog timeout
+
+ - none: No reset is performed on timeout. Assumes another watchdog
+ engine is responsible for this.
+
+ - aspeed,alt-boot: If property is present then boot from alternate block.
+ - aspeed,external-signal: If property is present then signal is sent to
+ external reset counter (only WDT1 and WDT2). If not
+ specified no external signal is sent.
+ - aspeed,ext-pulse-duration: External signal pulse duration in microseconds
+
+Optional properties for AST2500-compatible watchdogs:
+ - aspeed,ext-push-pull: If aspeed,external-signal is present, set the pin's
+ drive type to push-pull. The default is open-drain.
+ - aspeed,ext-active-high: If aspeed,external-signal is present and and the pin
+ is configured as push-pull, then set the pulse
+ polarity to active-high. The default is active-low.
+
Example:
wdt1: watchdog@1e785000 {
compatible = "aspeed,ast2400-wdt";
reg = <0x1e785000 0x1c>;
+ aspeed,reset-type = "system";
+ aspeed,external-signal;
};
diff --git a/dts/Bindings/watchdog/atmel-sama5d4-wdt.txt b/dts/Bindings/watchdog/atmel-sama5d4-wdt.txt
index f7cc7c0609..4fec1e3725 100644
--- a/dts/Bindings/watchdog/atmel-sama5d4-wdt.txt
+++ b/dts/Bindings/watchdog/atmel-sama5d4-wdt.txt
@@ -31,5 +31,4 @@ Example:
atmel,watchdog-type = "hardware";
atmel,dbg-halt;
atmel,idle-halt;
- status = "okay";
};
diff --git a/dts/Bindings/watchdog/atmel-wdt.txt b/dts/Bindings/watchdog/atmel-wdt.txt
index 86fa6de101..711a880b3d 100644
--- a/dts/Bindings/watchdog/atmel-wdt.txt
+++ b/dts/Bindings/watchdog/atmel-wdt.txt
@@ -48,5 +48,4 @@ Example:
atmel,idle-halt;
atmel,max-heartbeat-sec = <16>;
atmel,min-heartbeat-sec = <0>;
- status = "okay";
};
diff --git a/dts/Bindings/watchdog/lantiq-wdt.txt b/dts/Bindings/watchdog/lantiq-wdt.txt
new file mode 100644
index 0000000000..18d4d83027
--- /dev/null
+++ b/dts/Bindings/watchdog/lantiq-wdt.txt
@@ -0,0 +1,24 @@
+Lantiq WTD watchdog binding
+============================
+
+This describes the binding of the Lantiq watchdog driver.
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,wdt"
+ "lantiq,xrx100-wdt"
+ "lantiq,xrx200-wdt", "lantiq,xrx100-wdt"
+ "lantiq,falcon-wdt"
+- reg : Address of the watchdog block
+- lantiq,rcu : A phandle to the RCU syscon (required for
+ "lantiq,falcon-wdt" and "lantiq,xrx100-wdt")
+
+-------------------------------------------------------------------------------
+Example for the watchdog on the xRX200 SoCs:
+ watchdog@803f0 {
+ compatible = "lantiq,xrx200-wdt", "lantiq,xrx100-wdt";
+ reg = <0x803f0 0x10>;
+
+ lantiq,rcu = <&rcu0>;
+ };
diff --git a/dts/Bindings/watchdog/marvel.txt b/dts/Bindings/watchdog/marvel.txt
index 858ed9221a..c1b67a78f0 100644
--- a/dts/Bindings/watchdog/marvel.txt
+++ b/dts/Bindings/watchdog/marvel.txt
@@ -41,6 +41,5 @@ Example:
reg = <0x20300 0x28>, <0x20108 0x4>;
interrupts = <3>;
timeout-sec = <10>;
- status = "okay";
clocks = <&gate_clk 7>;
};
diff --git a/dts/Bindings/watchdog/meson-wdt.txt b/dts/Bindings/watchdog/meson-wdt.txt
index ae70185d96..8a6d84cb36 100644
--- a/dts/Bindings/watchdog/meson-wdt.txt
+++ b/dts/Bindings/watchdog/meson-wdt.txt
@@ -2,7 +2,11 @@ Meson SoCs Watchdog timer
Required properties:
-- compatible : should be "amlogic,meson6-wdt" or "amlogic,meson8b-wdt"
+- compatible : depending on the SoC this should be one of:
+ "amlogic,meson6-wdt" on Meson6 SoCs
+ "amlogic,meson8-wdt" and "amlogic,meson6-wdt" on Meson8 SoCs
+ "amlogic,meson8b-wdt" on Meson8b SoCs
+ "amlogic,meson8m2-wdt" and "amlogic,meson8b-wdt" on Meson8m2 SoCs
- reg : Specifies base physical address and size of the registers.
Example:
diff --git a/dts/Bindings/watchdog/mtk-wdt.txt b/dts/Bindings/watchdog/mtk-wdt.txt
index 6a00939a05..235de0683b 100644
--- a/dts/Bindings/watchdog/mtk-wdt.txt
+++ b/dts/Bindings/watchdog/mtk-wdt.txt
@@ -3,9 +3,11 @@ Mediatek SoCs Watchdog timer
Required properties:
- compatible should contain:
- * "mediatek,mt2701-wdt" for MT2701 compatible watchdog timers
- * "mediatek,mt6589-wdt" for all compatible watchdog timers (MT2701,
- MT6589)
+ "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
+ "mediatek,mt6589-wdt": for MT6589
+ "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
+ "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
+ "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
- reg : Specifies base physical address and size of the registers.
diff --git a/dts/Bindings/watchdog/renesas-wdt.txt b/dts/Bindings/watchdog/renesas-wdt.txt
index 9e306afbbd..bf6d1ca58a 100644
--- a/dts/Bindings/watchdog/renesas-wdt.txt
+++ b/dts/Bindings/watchdog/renesas-wdt.txt
@@ -6,6 +6,7 @@ Required properties:
Examples with soctypes are:
- "renesas,r8a7795-wdt" (R-Car H3)
- "renesas,r8a7796-wdt" (R-Car M3-W)
+ - "renesas,r8a77995-wdt" (R-Car D3)
- "renesas,r7s72100-wdt" (RZ/A1)
When compatible with the generic version, nodes must list the SoC-specific
diff --git a/dts/Bindings/xilinx.txt b/dts/Bindings/xilinx.txt
index 299d092353..1d11b9002e 100644
--- a/dts/Bindings/xilinx.txt
+++ b/dts/Bindings/xilinx.txt
@@ -281,6 +281,8 @@
capabilities of the underlying ICAP hardware
differ between different families. May be
'virtex2p', 'virtex4', or 'virtex5'.
+ - compatible : should contain "xlnx,xps-hwicap-1.00.a" or
+ "xlnx,opb-hwicap-1.00.b".
vi) Xilinx Uart 16550
diff --git a/dts/include/dt-bindings/clock/gxbb-aoclkc.h b/dts/include/dt-bindings/clock/gxbb-aoclkc.h
index 31751482d1..9d15e2221f 100644
--- a/dts/include/dt-bindings/clock/gxbb-aoclkc.h
+++ b/dts/include/dt-bindings/clock/gxbb-aoclkc.h
@@ -62,5 +62,6 @@
#define CLKID_AO_UART1 3
#define CLKID_AO_UART2 4
#define CLKID_AO_IR_BLASTER 5
+#define CLKID_AO_CEC_32K 6
#endif
diff --git a/dts/include/dt-bindings/clock/gxbb-clkc.h b/dts/include/dt-bindings/clock/gxbb-clkc.h
index e3e9f7919c..c04a76d8fa 100644
--- a/dts/include/dt-bindings/clock/gxbb-clkc.h
+++ b/dts/include/dt-bindings/clock/gxbb-clkc.h
@@ -5,37 +5,96 @@
#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H
+#define CLKID_SYS_PLL 0
#define CLKID_HDMI_PLL 2
+#define CLKID_FIXED_PLL 3
#define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
+#define CLKID_FCLK_DIV5 7
+#define CLKID_FCLK_DIV7 8
#define CLKID_GP0_PLL 9
#define CLKID_CLK81 12
+#define CLKID_MPLL0 13
+#define CLKID_MPLL1 14
#define CLKID_MPLL2 15
+#define CLKID_DDR 16
+#define CLKID_DOS 17
+#define CLKID_ISA 18
+#define CLKID_PL301 19
+#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
+#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
+#define CLKID_SDHC 27
+#define CLKID_STREAM 28
+#define CLKID_ASYNC_FIFO 29
+#define CLKID_SDIO 30
+#define CLKID_ABUF 31
+#define CLKID_HIU_IFACE 32
+#define CLKID_ASSIST_MISC 33
#define CLKID_SPI 34
#define CLKID_ETH 36
+#define CLKID_I2S_SPDIF 35
+#define CLKID_DEMUX 37
#define CLKID_AIU_GLUE 38
#define CLKID_IEC958 39
#define CLKID_I2S_OUT 40
+#define CLKID_AMCLK 41
+#define CLKID_AIFIFO2 42
+#define CLKID_MIXER 43
#define CLKID_MIXER_IFACE 44
+#define CLKID_ADC 45
+#define CLKID_BLKMV 46
#define CLKID_AIU 47
#define CLKID_UART1 48
+#define CLKID_G2D 49
#define CLKID_USB0 50
#define CLKID_USB1 51
+#define CLKID_RESET 52
+#define CLKID_NAND 53
+#define CLKID_DOS_PARSER 54
#define CLKID_USB 55
+#define CLKID_VDIN1 56
+#define CLKID_AHB_ARB0 57
+#define CLKID_EFUSE 58
+#define CLKID_BOOT_ROM 59
+#define CLKID_AHB_DATA_BUS 60
+#define CLKID_AHB_CTRL_BUS 61
+#define CLKID_HDMI_INTR_SYNC 62
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_MMC_PCLK 66
+#define CLKID_DVIN 67
#define CLKID_UART2 68
#define CLKID_SANA 69
+#define CLKID_VPU_INTR 70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A53 72
+#define CLKID_VCLK2_VENCI0 73
+#define CLKID_VCLK2_VENCI1 74
+#define CLKID_VCLK2_VENCP0 75
+#define CLKID_VCLK2_VENCP1 76
#define CLKID_GCLK_VENCI_INT0 77
+#define CLKID_GCLK_VENCI_INT 78
+#define CLKID_DAC_CLK 79
#define CLKID_AOCLK_GATE 80
#define CLKID_IEC958_GATE 81
+#define CLKID_ENC480P 82
+#define CLKID_RNG1 83
+#define CLKID_GCLK_VENCI_INT1 84
+#define CLKID_VCLK2_VENCLMCC 85
+#define CLKID_VCLK2_VENCL 86
+#define CLKID_VCLK_OTHER 87
+#define CLKID_EDP 88
+#define CLKID_AO_MEDIA_CPU 89
+#define CLKID_AO_AHB_SRAM 90
+#define CLKID_AO_AHB_BUS 91
+#define CLKID_AO_IFACE 92
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
@@ -50,5 +109,9 @@
#define CLKID_CTS_AMCLK 107
#define CLKID_CTS_MCLK_I958 110
#define CLKID_CTS_I958 113
+#define CLKID_32K_CLK 114
+#define CLKID_SD_EMMC_A_CLK0 119
+#define CLKID_SD_EMMC_B_CLK0 122
+#define CLKID_SD_EMMC_C_CLK0 125
#endif /* __GXBB_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/meson8b-clkc.h b/dts/include/dt-bindings/clock/meson8b-clkc.h
index e29227fb52..a9c0306330 100644
--- a/dts/include/dt-bindings/clock/meson8b-clkc.h
+++ b/dts/include/dt-bindings/clock/meson8b-clkc.h
@@ -21,15 +21,85 @@
#define CLKID_ZERO 13
#define CLKID_MPEG_SEL 14
#define CLKID_MPEG_DIV 15
+#define CLKID_DDR 16
+#define CLKID_DOS 17
+#define CLKID_ISA 18
+#define CLKID_PL301 19
+#define CLKID_PERIPHS 20
+#define CLKID_SPICC 21
+#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
+#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
+#define CLKID_UART0 26
+#define CLKID_SDHC 27
+#define CLKID_STREAM 28
+#define CLKID_ASYNC_FIFO 29
#define CLKID_SDIO 30
+#define CLKID_ABUF 31
+#define CLKID_HIU_IFACE 32
+#define CLKID_ASSIST_MISC 33
+#define CLKID_SPI 34
+#define CLKID_I2S_SPDIF 35
#define CLKID_ETH 36
+#define CLKID_DEMUX 37
+#define CLKID_AIU_GLUE 38
+#define CLKID_IEC958 39
+#define CLKID_I2S_OUT 40
+#define CLKID_AMCLK 41
+#define CLKID_AIFIFO2 42
+#define CLKID_MIXER 43
+#define CLKID_MIXER_IFACE 44
+#define CLKID_ADC 45
+#define CLKID_BLKMV 46
+#define CLKID_AIU 47
+#define CLKID_UART1 48
+#define CLKID_G2D 49
#define CLKID_USB0 50
#define CLKID_USB1 51
+#define CLKID_RESET 52
+#define CLKID_NAND 53
+#define CLKID_DOS_PARSER 54
#define CLKID_USB 55
+#define CLKID_VDIN1 56
+#define CLKID_AHB_ARB0 57
+#define CLKID_EFUSE 58
+#define CLKID_BOOT_ROM 59
+#define CLKID_AHB_DATA_BUS 60
+#define CLKID_AHB_CTRL_BUS 61
+#define CLKID_HDMI_INTR_SYNC 62
+#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_MMC_PCLK 66
+#define CLKID_DVIN 67
+#define CLKID_UART2 68
#define CLKID_SANA 69
+#define CLKID_VPU_INTR 70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A9 72
+#define CLKID_VCLK2_VENCI0 73
+#define CLKID_VCLK2_VENCI1 74
+#define CLKID_VCLK2_VENCP0 75
+#define CLKID_VCLK2_VENCP1 76
+#define CLKID_GCLK_VENCI_INT 77
+#define CLKID_GCLK_VENCP_INT 78
+#define CLKID_DAC_CLK 79
+#define CLKID_AOCLK_GATE 80
+#define CLKID_IEC958_GATE 81
+#define CLKID_ENC480P 82
+#define CLKID_RNG1 83
+#define CLKID_GCLK_VENCL_INT 84
+#define CLKID_VCLK2_VENCLMCC 85
+#define CLKID_VCLK2_VENCL 86
+#define CLKID_VCLK2_OTHER 87
+#define CLKID_EDP 88
+#define CLKID_AO_MEDIA_CPU 89
+#define CLKID_AO_AHB_SRAM 90
+#define CLKID_AO_AHB_BUS 91
+#define CLKID_AO_IFACE 92
+#define CLKID_MPLL0 93
+#define CLKID_MPLL1 94
+#define CLKID_MPLL2 95
#endif /* __MESON8B_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h b/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 1f5c422547..75b07cf5ee 100644
--- a/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -233,6 +233,8 @@
#define GCC_PCIE_CLKREF_CLK 216
#define GCC_RX2_USB2_CLKREF_CLK 217
#define GCC_RX1_USB2_CLKREF_CLK 218
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1
diff --git a/dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h
new file mode 100644
index 0000000000..4e8ae3dee5
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77995 CPG Core Clocks */
+#define R8A77995_CLK_Z2 0
+#define R8A77995_CLK_ZG 1
+#define R8A77995_CLK_ZTR 2
+#define R8A77995_CLK_ZT 3
+#define R8A77995_CLK_ZX 4
+#define R8A77995_CLK_S0D1 5
+#define R8A77995_CLK_S1D1 6
+#define R8A77995_CLK_S1D2 7
+#define R8A77995_CLK_S1D4 8
+#define R8A77995_CLK_S2D1 9
+#define R8A77995_CLK_S2D2 10
+#define R8A77995_CLK_S2D4 11
+#define R8A77995_CLK_S3D1 12
+#define R8A77995_CLK_S3D2 13
+#define R8A77995_CLK_S3D4 14
+#define R8A77995_CLK_S1D4C 15
+#define R8A77995_CLK_S3D1C 16
+#define R8A77995_CLK_S3D2C 17
+#define R8A77995_CLK_S3D4C 18
+#define R8A77995_CLK_LB 19
+#define R8A77995_CLK_CL 20
+#define R8A77995_CLK_ZB3 21
+#define R8A77995_CLK_ZB3D2 22
+#define R8A77995_CLK_CR 23
+#define R8A77995_CLK_CRD2 24
+#define R8A77995_CLK_SD0H 25
+#define R8A77995_CLK_SD0 26
+#define R8A77995_CLK_SSP2 27
+#define R8A77995_CLK_SSP1 28
+#define R8A77995_CLK_RPC 29
+#define R8A77995_CLK_RPCD2 30
+#define R8A77995_CLK_ZA2 31
+#define R8A77995_CLK_ZA8 32
+#define R8A77995_CLK_Z2D 33
+#define R8A77995_CLK_CANFD 34
+#define R8A77995_CLK_MSO 35
+#define R8A77995_CLK_R 36
+#define R8A77995_CLK_OSC 37
+#define R8A77995_CLK_LV0 38
+#define R8A77995_CLK_LV1 39
+#define R8A77995_CLK_CP 40
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/rk3228-cru.h b/dts/include/dt-bindings/clock/rk3228-cru.h
index 56f841c228..55655ab0a4 100644
--- a/dts/include/dt-bindings/clock/rk3228-cru.h
+++ b/dts/include/dt-bindings/clock/rk3228-cru.h
@@ -49,6 +49,7 @@
#define SCLK_EMMC_DRV 117
#define SCLK_SDMMC_SAMPLE 118
#define SCLK_SDIO_SAMPLE 119
+#define SCLK_SDIO_SRC 120
#define SCLK_EMMC_SAMPLE 121
#define SCLK_VOP 122
#define SCLK_HDMI_HDCP 123
diff --git a/dts/include/dt-bindings/clock/rv1108-cru.h b/dts/include/dt-bindings/clock/rv1108-cru.h
index ae26f81059..d8d0e0456d 100644
--- a/dts/include/dt-bindings/clock/rv1108-cru.h
+++ b/dts/include/dt-bindings/clock/rv1108-cru.h
@@ -43,12 +43,74 @@
#define SCLK_SDMMC_SAMPLE 84
#define SCLK_SDIO_SAMPLE 85
#define SCLK_EMMC_SAMPLE 86
+#define SCLK_VENC_CORE 87
+#define SCLK_HEVC_CORE 88
+#define SCLK_HEVC_CABAC 89
+#define SCLK_PWM0_PMU 90
+#define SCLK_I2C0_PMU 91
+#define SCLK_WIFI 92
+#define SCLK_CIFOUT 93
+#define SCLK_MIPI_CSI_OUT 94
+#define SCLK_CIF0 95
+#define SCLK_CIF1 96
+#define SCLK_CIF2 97
+#define SCLK_CIF3 98
+#define SCLK_DSP 99
+#define SCLK_DSP_IOP 100
+#define SCLK_DSP_EPP 101
+#define SCLK_DSP_EDP 102
+#define SCLK_DSP_EDAP 103
+#define SCLK_CVBS_HOST 104
+#define SCLK_HDMI_SFR 105
+#define SCLK_HDMI_CEC 106
+#define SCLK_CRYPTO 107
+#define SCLK_SPI 108
+#define SCLK_SARADC 109
+#define SCLK_TSADC 110
+#define SCLK_MAC_PRE 111
+#define SCLK_MAC 112
+#define SCLK_MAC_RX 113
+#define SCLK_MAC_REF 114
+#define SCLK_MAC_REFOUT 115
+#define SCLK_DSP_PFM 116
+#define SCLK_RGA 117
+#define SCLK_I2C1 118
+#define SCLK_I2C2 119
+#define SCLK_I2C3 120
+#define SCLK_PWM 121
+#define SCLK_ISP 122
+#define SCLK_USBPHY 123
+#define SCLK_I2S0_SRC 124
+#define SCLK_I2S1_SRC 125
+#define SCLK_I2S2_SRC 126
+#define SCLK_UART0_SRC 127
+#define SCLK_UART1_SRC 128
+#define SCLK_UART2_SRC 129
+
+#define DCLK_VOP_SRC 185
+#define DCLK_HDMIPHY 186
+#define DCLK_VOP 187
/* aclk gates */
#define ACLK_DMAC 192
#define ACLK_PRE 193
#define ACLK_CORE 194
#define ACLK_ENMCORE 195
+#define ACLK_RKVENC 196
+#define ACLK_RKVDEC 197
+#define ACLK_VPU 198
+#define ACLK_CIF0 199
+#define ACLK_VIO0 200
+#define ACLK_VIO1 201
+#define ACLK_VOP 202
+#define ACLK_IEP 203
+#define ACLK_RGA 204
+#define ACLK_ISP 205
+#define ACLK_CIF1 206
+#define ACLK_CIF2 207
+#define ACLK_CIF3 208
+#define ACLK_PERI 209
+#define ACLK_GMAC 210
/* pclk gates */
#define PCLK_GPIO1 256
@@ -67,10 +129,24 @@
#define PCLK_PWM 269
#define PCLK_TIMER 270
#define PCLK_PERI 271
+#define PCLK_GPIO0_PMU 272
+#define PCLK_I2C0_PMU 273
+#define PCLK_PWM0_PMU 274
+#define PCLK_ISP 275
+#define PCLK_VIO 276
+#define PCLK_MIPI_DSI 277
+#define PCLK_HDMI_CTRL 278
+#define PCLK_SARADC 279
+#define PCLK_DSP_CFG 280
+#define PCLK_BUS 281
+#define PCLK_EFUSE0 282
+#define PCLK_EFUSE1 283
+#define PCLK_WDT 284
+#define PCLK_GMAC 285
/* hclk gates */
#define HCLK_I2S0_8CH 320
-#define HCLK_I2S1_8CH 321
+#define HCLK_I2S1_2CH 321
#define HCLK_I2S2_2CH 322
#define HCLK_NANDC 323
#define HCLK_SDMMC 324
@@ -78,20 +154,37 @@
#define HCLK_EMMC 326
#define HCLK_PERI 327
#define HCLK_SFC 328
+#define HCLK_RKVENC 329
+#define HCLK_RKVDEC 330
+#define HCLK_CIF0 331
+#define HCLK_VIO 332
+#define HCLK_VOP 333
+#define HCLK_IEP 334
+#define HCLK_RGA 335
+#define HCLK_ISP 336
+#define HCLK_CRYPTO_MST 337
+#define HCLK_CRYPTO_SLV 338
+#define HCLK_HOST0 339
+#define HCLK_OTG 340
+#define HCLK_CIF1 341
+#define HCLK_CIF2 342
+#define HCLK_CIF3 343
+#define HCLK_BUS 344
+#define HCLK_VPU 345
-#define CLK_NR_CLKS (HCLK_SFC + 1)
+#define CLK_NR_CLKS (HCLK_VPU + 1)
/* reset id */
-#define SRST_CORE_PO_AD 0
+#define SRST_CORE_PO_AD 0
#define SRST_CORE_AD 1
#define SRST_L2_AD 2
-#define SRST_CPU_NIU_AD 3
+#define SRST_CPU_NIU_AD 3
#define SRST_CORE_PO 4
#define SRST_CORE 5
-#define SRST_L2 6
+#define SRST_L2 6
#define SRST_CORE_DBG 8
#define PRST_DBG 9
-#define RST_DAP 10
+#define RST_DAP 10
#define PRST_DBG_NIU 11
#define ARST_STRC_SYS_AD 15
@@ -158,9 +251,9 @@
#define HRST_SYSBUS 75
#define PRST_USBGRF 76
-#define ARST_PERIPH_NIU 80
-#define HRST_PERIPH_NIU 81
-#define PRST_PERIPH_NIU 82
+#define ARST_PERIPH_NIU 80
+#define HRST_PERIPH_NIU 81
+#define PRST_PERIPH_NIU 82
#define HRST_PERIPH 83
#define HRST_SDMMC 84
#define HRST_SDIO 85
@@ -178,7 +271,7 @@
#define HRST_HOST0_AUX 96
#define HRST_HOST0_ARB 97
#define SRST_HOST0_EHCIPHY 98
-#define SRST_HOST0_UTMI 99
+#define SRST_HOST0_UTMI 99
#define SRST_USBPOR 100
#define SRST_UTMI0 101
#define SRST_UTMI1 102
@@ -225,21 +318,21 @@
#define HRST_VPU_NIU 141
#define ARST_VPU 142
#define HRST_VPU 143
-#define ARST_RKVDEC_NIU 144
-#define HRST_RKVDEC_NIU 145
+#define ARST_RKVDEC_NIU 144
+#define HRST_RKVDEC_NIU 145
#define ARST_RKVDEC 146
#define HRST_RKVDEC 147
#define SRST_RKVDEC_CABAC 148
#define SRST_RKVDEC_CORE 149
-#define ARST_RKVENC_NIU 150
-#define HRST_RKVENC_NIU 151
+#define ARST_RKVENC_NIU 150
+#define HRST_RKVENC_NIU 151
#define ARST_RKVENC 152
#define HRST_RKVENC 153
#define SRST_RKVENC_CORE 154
#define SRST_DSP_CORE 156
#define SRST_DSP_SYS 157
-#define SRST_DSP_GLOBAL 158
+#define SRST_DSP_GLOBAL 158
#define SRST_DSP_OECM 159
#define PRST_DSP_IOP_NIU 160
#define ARST_DSP_EPP_NIU 161
@@ -257,7 +350,7 @@
#define SRST_PMU_I2C0 173
#define PRST_PMU_I2C0 174
#define PRST_PMU_GPIO0 175
-#define PRST_PMU_INTMEM 176
+#define PRST_PMU_INTMEM 176
#define PRST_PMU_PWM0 177
#define SRST_PMU_PWM0 178
#define PRST_PMU_GRF 179
diff --git a/dts/include/dt-bindings/clock/stm32h7-clks.h b/dts/include/dt-bindings/clock/stm32h7-clks.h
new file mode 100644
index 0000000000..6637272b32
--- /dev/null
+++ b/dts/include/dt-bindings/clock/stm32h7-clks.h
@@ -0,0 +1,165 @@
+/* SYS, CORE AND BUS CLOCKS */
+#define SYS_D1CPRE 0
+#define HCLK 1
+#define PCLK1 2
+#define PCLK2 3
+#define PCLK3 4
+#define PCLK4 5
+#define HSI_DIV 6
+#define HSE_1M 7
+#define I2S_CKIN 8
+#define CK_DSI_PHY 9
+#define HSE_CK 10
+#define LSE_CK 11
+#define CSI_KER_DIV122 12
+#define RTC_CK 13
+#define CPU_SYSTICK 14
+
+/* OSCILLATOR BANK */
+#define OSC_BANK 18
+#define HSI_CK 18
+#define HSI_KER_CK 19
+#define CSI_CK 20
+#define CSI_KER_CK 21
+#define RC48_CK 22
+#define LSI_CK 23
+
+/* MCLOCK BANK */
+#define MCLK_BANK 28
+#define PER_CK 28
+#define PLLSRC 29
+#define SYS_CK 30
+#define TRACEIN_CK 31
+
+/* ODF BANK */
+#define ODF_BANK 32
+#define PLL1_P 32
+#define PLL1_Q 33
+#define PLL1_R 34
+#define PLL2_P 35
+#define PLL2_Q 36
+#define PLL2_R 37
+#define PLL3_P 38
+#define PLL3_Q 39
+#define PLL3_R 40
+
+/* MCO BANK */
+#define MCO_BANK 41
+#define MCO1 41
+#define MCO2 42
+
+/* PERIF BANK */
+#define PERIF_BANK 50
+#define D1SRAM1_CK 50
+#define ITCM_CK 51
+#define DTCM2_CK 52
+#define DTCM1_CK 53
+#define FLITF_CK 54
+#define JPGDEC_CK 55
+#define DMA2D_CK 56
+#define MDMA_CK 57
+#define USB2ULPI_CK 58
+#define USB1ULPI_CK 59
+#define ETH1RX_CK 60
+#define ETH1TX_CK 61
+#define ETH1MAC_CK 62
+#define ART_CK 63
+#define DMA2_CK 64
+#define DMA1_CK 65
+#define D2SRAM3_CK 66
+#define D2SRAM2_CK 67
+#define D2SRAM1_CK 68
+#define HASH_CK 69
+#define CRYPT_CK 70
+#define CAMITF_CK 71
+#define BKPRAM_CK 72
+#define HSEM_CK 73
+#define BDMA_CK 74
+#define CRC_CK 75
+#define GPIOK_CK 76
+#define GPIOJ_CK 77
+#define GPIOI_CK 78
+#define GPIOH_CK 79
+#define GPIOG_CK 80
+#define GPIOF_CK 81
+#define GPIOE_CK 82
+#define GPIOD_CK 83
+#define GPIOC_CK 84
+#define GPIOB_CK 85
+#define GPIOA_CK 86
+#define WWDG1_CK 87
+#define DAC12_CK 88
+#define WWDG2_CK 89
+#define TIM14_CK 90
+#define TIM13_CK 91
+#define TIM12_CK 92
+#define TIM7_CK 93
+#define TIM6_CK 94
+#define TIM5_CK 95
+#define TIM4_CK 96
+#define TIM3_CK 97
+#define TIM2_CK 98
+#define MDIOS_CK 99
+#define OPAMP_CK 100
+#define CRS_CK 101
+#define TIM17_CK 102
+#define TIM16_CK 103
+#define TIM15_CK 104
+#define TIM8_CK 105
+#define TIM1_CK 106
+#define TMPSENS_CK 107
+#define RTCAPB_CK 108
+#define VREF_CK 109
+#define COMP12_CK 110
+#define SYSCFG_CK 111
+
+/* KERNEL BANK */
+#define KERN_BANK 120
+#define SDMMC1_CK 120
+#define QUADSPI_CK 121
+#define FMC_CK 122
+#define USB2OTG_CK 123
+#define USB1OTG_CK 124
+#define ADC12_CK 125
+#define SDMMC2_CK 126
+#define RNG_CK 127
+#define ADC3_CK 128
+#define DSI_CK 129
+#define LTDC_CK 130
+#define USART8_CK 131
+#define USART7_CK 132
+#define HDMICEC_CK 133
+#define I2C3_CK 134
+#define I2C2_CK 135
+#define I2C1_CK 136
+#define UART5_CK 137
+#define UART4_CK 138
+#define USART3_CK 139
+#define USART2_CK 140
+#define SPDIFRX_CK 141
+#define SPI3_CK 142
+#define SPI2_CK 143
+#define LPTIM1_CK 144
+#define FDCAN_CK 145
+#define SWP_CK 146
+#define HRTIM_CK 147
+#define DFSDM1_CK 148
+#define SAI3_CK 149
+#define SAI2_CK 150
+#define SAI1_CK 151
+#define SPI5_CK 152
+#define SPI4_CK 153
+#define SPI1_CK 154
+#define USART6_CK 155
+#define USART1_CK 156
+#define SAI4B_CK 157
+#define SAI4A_CK 158
+#define LPTIM5_CK 159
+#define LPTIM4_CK 160
+#define LPTIM3_CK 161
+#define LPTIM2_CK 162
+#define I2C4_CK 163
+#define SPI6_CK 164
+#define LPUART1_CK 165
+
+#define STM32H7_MAX_CLKS 166
diff --git a/dts/include/dt-bindings/clock/sun4i-a10-ccu.h b/dts/include/dt-bindings/clock/sun4i-a10-ccu.h
new file mode 100644
index 0000000000..c5a53f38d6
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
+#define _DT_BINDINGS_CLK_SUN4I_A10_H_
+
+#define CLK_HOSC 1
+#define CLK_CPU 20
+
+/* AHB Gates */
+#define CLK_AHB_OTG 26
+#define CLK_AHB_EHCI0 27
+#define CLK_AHB_OHCI0 28
+#define CLK_AHB_EHCI1 29
+#define CLK_AHB_OHCI1 30
+#define CLK_AHB_SS 31
+#define CLK_AHB_DMA 32
+#define CLK_AHB_BIST 33
+#define CLK_AHB_MMC0 34
+#define CLK_AHB_MMC1 35
+#define CLK_AHB_MMC2 36
+#define CLK_AHB_MMC3 37
+#define CLK_AHB_MS 38
+#define CLK_AHB_NAND 39
+#define CLK_AHB_SDRAM 40
+#define CLK_AHB_ACE 41
+#define CLK_AHB_EMAC 42
+#define CLK_AHB_TS 43
+#define CLK_AHB_SPI0 44
+#define CLK_AHB_SPI1 45
+#define CLK_AHB_SPI2 46
+#define CLK_AHB_SPI3 47
+#define CLK_AHB_PATA 48
+#define CLK_AHB_SATA 49
+#define CLK_AHB_GPS 50
+#define CLK_AHB_HSTIMER 51
+#define CLK_AHB_VE 52
+#define CLK_AHB_TVD 53
+#define CLK_AHB_TVE0 54
+#define CLK_AHB_TVE1 55
+#define CLK_AHB_LCD0 56
+#define CLK_AHB_LCD1 57
+#define CLK_AHB_CSI0 58
+#define CLK_AHB_CSI1 59
+#define CLK_AHB_HDMI0 60
+#define CLK_AHB_HDMI1 61
+#define CLK_AHB_DE_BE0 62
+#define CLK_AHB_DE_BE1 63
+#define CLK_AHB_DE_FE0 64
+#define CLK_AHB_DE_FE1 65
+#define CLK_AHB_GMAC 66
+#define CLK_AHB_MP 67
+#define CLK_AHB_GPU 68
+
+/* APB0 Gates */
+#define CLK_APB0_CODEC 69
+#define CLK_APB0_SPDIF 70
+#define CLK_APB0_I2S0 71
+#define CLK_APB0_AC97 72
+#define CLK_APB0_I2S1 73
+#define CLK_APB0_PIO 74
+#define CLK_APB0_IR0 75
+#define CLK_APB0_IR1 76
+#define CLK_APB0_I2S2 77
+#define CLK_APB0_KEYPAD 78
+
+/* APB1 Gates */
+#define CLK_APB1_I2C0 79
+#define CLK_APB1_I2C1 80
+#define CLK_APB1_I2C2 81
+#define CLK_APB1_I2C3 82
+#define CLK_APB1_CAN 83
+#define CLK_APB1_SCR 84
+#define CLK_APB1_PS20 85
+#define CLK_APB1_PS21 86
+#define CLK_APB1_I2C4 87
+#define CLK_APB1_UART0 88
+#define CLK_APB1_UART1 89
+#define CLK_APB1_UART2 90
+#define CLK_APB1_UART3 91
+#define CLK_APB1_UART4 92
+#define CLK_APB1_UART5 93
+#define CLK_APB1_UART6 94
+#define CLK_APB1_UART7 95
+
+/* IP clocks */
+#define CLK_NAND 96
+#define CLK_MS 97
+#define CLK_MMC0 98
+#define CLK_MMC0_OUTPUT 99
+#define CLK_MMC0_SAMPLE 100
+#define CLK_MMC1 101
+#define CLK_MMC1_OUTPUT 102
+#define CLK_MMC1_SAMPLE 103
+#define CLK_MMC2 104
+#define CLK_MMC2_OUTPUT 105
+#define CLK_MMC2_SAMPLE 106
+#define CLK_MMC3 107
+#define CLK_MMC3_OUTPUT 108
+#define CLK_MMC3_SAMPLE 109
+#define CLK_TS 110
+#define CLK_SS 111
+#define CLK_SPI0 112
+#define CLK_SPI1 113
+#define CLK_SPI2 114
+#define CLK_PATA 115
+#define CLK_IR0 116
+#define CLK_IR1 117
+#define CLK_I2S0 118
+#define CLK_AC97 119
+#define CLK_SPDIF 120
+#define CLK_KEYPAD 121
+#define CLK_SATA 122
+#define CLK_USB_OHCI0 123
+#define CLK_USB_OHCI1 124
+#define CLK_USB_PHY 125
+#define CLK_GPS 126
+#define CLK_SPI3 127
+#define CLK_I2S1 128
+#define CLK_I2S2 129
+
+/* DRAM Gates */
+#define CLK_DRAM_VE 130
+#define CLK_DRAM_CSI0 131
+#define CLK_DRAM_CSI1 132
+#define CLK_DRAM_TS 133
+#define CLK_DRAM_TVD 134
+#define CLK_DRAM_TVE0 135
+#define CLK_DRAM_TVE1 136
+#define CLK_DRAM_OUT 137
+#define CLK_DRAM_DE_FE1 138
+#define CLK_DRAM_DE_FE0 139
+#define CLK_DRAM_DE_BE0 140
+#define CLK_DRAM_DE_BE1 141
+#define CLK_DRAM_MP 142
+#define CLK_DRAM_ACE 143
+
+/* Display Engine Clocks */
+#define CLK_DE_BE0 144
+#define CLK_DE_BE1 145
+#define CLK_DE_FE0 146
+#define CLK_DE_FE1 147
+#define CLK_DE_MP 148
+#define CLK_TCON0_CH0 149
+#define CLK_TCON1_CH0 150
+#define CLK_CSI_SCLK 151
+#define CLK_TVD_SCLK2 152
+#define CLK_TVD 153
+#define CLK_TCON0_CH1_SCLK2 154
+#define CLK_TCON0_CH1 155
+#define CLK_TCON1_CH1_SCLK2 156
+#define CLK_TCON1_CH1 157
+#define CLK_CSI0 158
+#define CLK_CSI1 159
+#define CLK_CODEC 160
+#define CLK_VE 161
+#define CLK_AVS 162
+#define CLK_ACE 163
+#define CLK_HDMI 164
+#define CLK_GPU 165
+
+#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
diff --git a/dts/include/dt-bindings/clock/sun7i-a20-ccu.h b/dts/include/dt-bindings/clock/sun7i-a20-ccu.h
new file mode 100644
index 0000000000..045a5178da
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun7i-a20-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
+#define _DT_BINDINGS_CLK_SUN7I_A20_H_
+
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+
+#define CLK_MBUS 166
+#define CLK_HDMI1_SLOW 167
+#define CLK_HDMI1 168
+#define CLK_OUT_A 169
+#define CLK_OUT_B 170
+
+#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
diff --git a/dts/include/dt-bindings/clock/sun8i-r40-ccu.h b/dts/include/dt-bindings/clock/sun8i-r40-ccu.h
new file mode 100644
index 0000000000..4fa5f69fc2
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+
+#define CLK_CPU 24
+
+#define CLK_BUS_MIPI_DSI 29
+#define CLK_BUS_CE 30
+#define CLK_BUS_DMA 31
+#define CLK_BUS_MMC0 32
+#define CLK_BUS_MMC1 33
+#define CLK_BUS_MMC2 34
+#define CLK_BUS_MMC3 35
+#define CLK_BUS_NAND 36
+#define CLK_BUS_DRAM 37
+#define CLK_BUS_EMAC 38
+#define CLK_BUS_TS 39
+#define CLK_BUS_HSTIMER 40
+#define CLK_BUS_SPI0 41
+#define CLK_BUS_SPI1 42
+#define CLK_BUS_SPI2 43
+#define CLK_BUS_SPI3 44
+#define CLK_BUS_SATA 45
+#define CLK_BUS_OTG 46
+#define CLK_BUS_EHCI0 47
+#define CLK_BUS_EHCI1 48
+#define CLK_BUS_EHCI2 49
+#define CLK_BUS_OHCI0 50
+#define CLK_BUS_OHCI1 51
+#define CLK_BUS_OHCI2 52
+#define CLK_BUS_VE 53
+#define CLK_BUS_MP 54
+#define CLK_BUS_DEINTERLACE 55
+#define CLK_BUS_CSI0 56
+#define CLK_BUS_CSI1 57
+#define CLK_BUS_HDMI1 58
+#define CLK_BUS_HDMI0 59
+#define CLK_BUS_DE 60
+#define CLK_BUS_TVE0 61
+#define CLK_BUS_TVE1 62
+#define CLK_BUS_TVE_TOP 63
+#define CLK_BUS_GMAC 64
+#define CLK_BUS_GPU 65
+#define CLK_BUS_TVD0 66
+#define CLK_BUS_TVD1 67
+#define CLK_BUS_TVD2 68
+#define CLK_BUS_TVD3 69
+#define CLK_BUS_TVD_TOP 70
+#define CLK_BUS_TCON_LCD0 71
+#define CLK_BUS_TCON_LCD1 72
+#define CLK_BUS_TCON_TV0 73
+#define CLK_BUS_TCON_TV1 74
+#define CLK_BUS_TCON_TOP 75
+#define CLK_BUS_CODEC 76
+#define CLK_BUS_SPDIF 77
+#define CLK_BUS_AC97 78
+#define CLK_BUS_PIO 79
+#define CLK_BUS_IR0 80
+#define CLK_BUS_IR1 81
+#define CLK_BUS_THS 82
+#define CLK_BUS_KEYPAD 83
+#define CLK_BUS_I2S0 84
+#define CLK_BUS_I2S1 85
+#define CLK_BUS_I2S2 86
+#define CLK_BUS_I2C0 87
+#define CLK_BUS_I2C1 88
+#define CLK_BUS_I2C2 89
+#define CLK_BUS_I2C3 90
+#define CLK_BUS_CAN 91
+#define CLK_BUS_SCR 92
+#define CLK_BUS_PS20 93
+#define CLK_BUS_PS21 94
+#define CLK_BUS_I2C4 95
+#define CLK_BUS_UART0 96
+#define CLK_BUS_UART1 97
+#define CLK_BUS_UART2 98
+#define CLK_BUS_UART3 99
+#define CLK_BUS_UART4 100
+#define CLK_BUS_UART5 101
+#define CLK_BUS_UART6 102
+#define CLK_BUS_UART7 103
+#define CLK_BUS_DBG 104
+
+#define CLK_THS 105
+#define CLK_NAND 106
+#define CLK_MMC0 107
+#define CLK_MMC1 108
+#define CLK_MMC2 109
+#define CLK_MMC3 110
+#define CLK_TS 111
+#define CLK_CE 112
+#define CLK_SPI0 113
+#define CLK_SPI1 114
+#define CLK_SPI2 115
+#define CLK_SPI3 116
+#define CLK_I2S0 117
+#define CLK_I2S1 118
+#define CLK_I2S2 119
+#define CLK_AC97 120
+#define CLK_SPDIF 121
+#define CLK_KEYPAD 122
+#define CLK_SATA 123
+#define CLK_USB_PHY0 124
+#define CLK_USB_PHY1 125
+#define CLK_USB_PHY2 126
+#define CLK_USB_OHCI0 127
+#define CLK_USB_OHCI1 128
+#define CLK_USB_OHCI2 129
+#define CLK_IR0 130
+#define CLK_IR1 131
+
+#define CLK_DRAM_VE 133
+#define CLK_DRAM_CSI0 134
+#define CLK_DRAM_CSI1 135
+#define CLK_DRAM_TS 136
+#define CLK_DRAM_TVD 137
+#define CLK_DRAM_MP 138
+#define CLK_DRAM_DEINTERLACE 139
+#define CLK_DE 140
+#define CLK_MP 141
+#define CLK_TCON_LCD0 142
+#define CLK_TCON_LCD1 143
+#define CLK_TCON_TV0 144
+#define CLK_TCON_TV1 145
+#define CLK_DEINTERLACE 146
+#define CLK_CSI1_MCLK 147
+#define CLK_CSI_SCLK 148
+#define CLK_CSI0_MCLK 149
+#define CLK_VE 150
+#define CLK_CODEC 151
+#define CLK_AVS 152
+#define CLK_HDMI 153
+#define CLK_HDMI_SLOW 154
+
+#define CLK_DSI_DPHY 156
+#define CLK_TVE0 157
+#define CLK_TVE1 158
+#define CLK_TVD0 159
+#define CLK_TVD1 160
+#define CLK_TVD2 161
+#define CLK_TVD3 162
+#define CLK_GPU 163
+#define CLK_OUTA 164
+#define CLK_OUTB 165
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */
diff --git a/dts/include/dt-bindings/genpd/k2g.h b/dts/include/dt-bindings/genpd/k2g.h
deleted file mode 100644
index 1f31f17e19..0000000000
--- a/dts/include/dt-bindings/genpd/k2g.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * TI K2G SoC Device definitions
- *
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DT_BINDINGS_GENPD_K2G_H
-#define _DT_BINDINGS_GENPD_K2G_H
-
-/* Documented in http://processors.wiki.ti.com/index.php/TISCI */
-
-#define K2G_DEV_PMMC0 0x0000
-#define K2G_DEV_MLB0 0x0001
-#define K2G_DEV_DSS0 0x0002
-#define K2G_DEV_MCBSP0 0x0003
-#define K2G_DEV_MCASP0 0x0004
-#define K2G_DEV_MCASP1 0x0005
-#define K2G_DEV_MCASP2 0x0006
-#define K2G_DEV_DCAN0 0x0008
-#define K2G_DEV_DCAN1 0x0009
-#define K2G_DEV_EMIF0 0x000a
-#define K2G_DEV_MMCHS0 0x000b
-#define K2G_DEV_MMCHS1 0x000c
-#define K2G_DEV_GPMC0 0x000d
-#define K2G_DEV_ELM0 0x000e
-#define K2G_DEV_SPI0 0x0010
-#define K2G_DEV_SPI1 0x0011
-#define K2G_DEV_SPI2 0x0012
-#define K2G_DEV_SPI3 0x0013
-#define K2G_DEV_ICSS0 0x0014
-#define K2G_DEV_ICSS1 0x0015
-#define K2G_DEV_USB0 0x0016
-#define K2G_DEV_USB1 0x0017
-#define K2G_DEV_NSS0 0x0018
-#define K2G_DEV_PCIE0 0x0019
-#define K2G_DEV_GPIO0 0x001b
-#define K2G_DEV_GPIO1 0x001c
-#define K2G_DEV_TIMER64_0 0x001d
-#define K2G_DEV_TIMER64_1 0x001e
-#define K2G_DEV_TIMER64_2 0x001f
-#define K2G_DEV_TIMER64_3 0x0020
-#define K2G_DEV_TIMER64_4 0x0021
-#define K2G_DEV_TIMER64_5 0x0022
-#define K2G_DEV_TIMER64_6 0x0023
-#define K2G_DEV_MSGMGR0 0x0025
-#define K2G_DEV_BOOTCFG0 0x0026
-#define K2G_DEV_ARM_BOOTROM0 0x0027
-#define K2G_DEV_DSP_BOOTROM0 0x0029
-#define K2G_DEV_DEBUGSS0 0x002b
-#define K2G_DEV_UART0 0x002c
-#define K2G_DEV_UART1 0x002d
-#define K2G_DEV_UART2 0x002e
-#define K2G_DEV_EHRPWM0 0x002f
-#define K2G_DEV_EHRPWM1 0x0030
-#define K2G_DEV_EHRPWM2 0x0031
-#define K2G_DEV_EHRPWM3 0x0032
-#define K2G_DEV_EHRPWM4 0x0033
-#define K2G_DEV_EHRPWM5 0x0034
-#define K2G_DEV_EQEP0 0x0035
-#define K2G_DEV_EQEP1 0x0036
-#define K2G_DEV_EQEP2 0x0037
-#define K2G_DEV_ECAP0 0x0038
-#define K2G_DEV_ECAP1 0x0039
-#define K2G_DEV_I2C0 0x003a
-#define K2G_DEV_I2C1 0x003b
-#define K2G_DEV_I2C2 0x003c
-#define K2G_DEV_EDMA0 0x003f
-#define K2G_DEV_SEMAPHORE0 0x0040
-#define K2G_DEV_INTC0 0x0041
-#define K2G_DEV_GIC0 0x0042
-#define K2G_DEV_QSPI0 0x0043
-#define K2G_DEV_ARM_64B_COUNTER0 0x0044
-#define K2G_DEV_TETRIS0 0x0045
-#define K2G_DEV_CGEM0 0x0046
-#define K2G_DEV_MSMC0 0x0047
-#define K2G_DEV_CBASS0 0x0049
-#define K2G_DEV_BOARD0 0x004c
-#define K2G_DEV_EDMA1 0x004f
-
-#endif
diff --git a/dts/include/dt-bindings/leds/leds-pca955x.h b/dts/include/dt-bindings/leds/leds-pca955x.h
new file mode 100644
index 0000000000..78cb7e979d
--- /dev/null
+++ b/dts/include/dt-bindings/leds/leds-pca955x.h
@@ -0,0 +1,16 @@
+/*
+ * This header provides constants for pca955x LED bindings.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _DT_BINDINGS_LEDS_PCA955X_H
+#define _DT_BINDINGS_LEDS_PCA955X_H
+
+#define PCA955X_TYPE_NONE 0
+#define PCA955X_TYPE_LED 1
+#define PCA955X_TYPE_GPIO 2
+
+#endif /* _DT_BINDINGS_LEDS_PCA955X_H */
diff --git a/dts/include/dt-bindings/memory/mt8173-larb-port.h b/dts/include/dt-bindings/memory/mt8173-larb-port.h
index 5fef5d1f8f..111b4b0ec8 100644
--- a/dts/include/dt-bindings/memory/mt8173-larb-port.h
+++ b/dts/include/dt-bindings/memory/mt8173-larb-port.h
@@ -15,10 +15,6 @@
#define __DTS_IOMMU_PORT_MT8173_H
#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
-/* Local arbiter ID */
-#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x7)
-/* PortID within the local arbiter */
-#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/dts/include/dt-bindings/mfd/stm32h7-rcc.h b/dts/include/dt-bindings/mfd/stm32h7-rcc.h
new file mode 100644
index 0000000000..461a8e0445
--- /dev/null
+++ b/dts/include/dt-bindings/mfd/stm32h7-rcc.h
@@ -0,0 +1,136 @@
+/*
+ * This header provides constants for the STM32H7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H
+#define _DT_BINDINGS_MFD_STM32H7_RCC_H
+
+/* AHB3 */
+#define STM32H7_RCC_AHB3_MDMA 0
+#define STM32H7_RCC_AHB3_DMA2D 4
+#define STM32H7_RCC_AHB3_JPGDEC 5
+#define STM32H7_RCC_AHB3_FMC 12
+#define STM32H7_RCC_AHB3_QUADSPI 14
+#define STM32H7_RCC_AHB3_SDMMC1 16
+#define STM32H7_RCC_AHB3_CPU 31
+
+#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
+
+/* AHB1 */
+#define STM32H7_RCC_AHB1_DMA1 0
+#define STM32H7_RCC_AHB1_DMA2 1
+#define STM32H7_RCC_AHB1_ADC12 5
+#define STM32H7_RCC_AHB1_ART 14
+#define STM32H7_RCC_AHB1_ETH1MAC 15
+#define STM32H7_RCC_AHB1_USB1OTG 25
+#define STM32H7_RCC_AHB1_USB2OTG 27
+
+#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
+
+/* AHB2 */
+#define STM32H7_RCC_AHB2_CAMITF 0
+#define STM32H7_RCC_AHB2_CRYPT 4
+#define STM32H7_RCC_AHB2_HASH 5
+#define STM32H7_RCC_AHB2_RNG 6
+#define STM32H7_RCC_AHB2_SDMMC2 9
+
+#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
+
+/* AHB4 */
+#define STM32H7_RCC_AHB4_GPIOA 0
+#define STM32H7_RCC_AHB4_GPIOB 1
+#define STM32H7_RCC_AHB4_GPIOC 2
+#define STM32H7_RCC_AHB4_GPIOD 3
+#define STM32H7_RCC_AHB4_GPIOE 4
+#define STM32H7_RCC_AHB4_GPIOF 5
+#define STM32H7_RCC_AHB4_GPIOG 6
+#define STM32H7_RCC_AHB4_GPIOH 7
+#define STM32H7_RCC_AHB4_GPIOI 8
+#define STM32H7_RCC_AHB4_GPIOJ 9
+#define STM32H7_RCC_AHB4_GPIOK 10
+#define STM32H7_RCC_AHB4_CRC 19
+#define STM32H7_RCC_AHB4_BDMA 21
+#define STM32H7_RCC_AHB4_ADC3 24
+#define STM32H7_RCC_AHB4_HSEM 25
+
+#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
+
+/* APB3 */
+#define STM32H7_RCC_APB3_LTDC 3
+#define STM32H7_RCC_APB3_DSI 4
+
+#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))
+
+/* APB1L */
+#define STM32H7_RCC_APB1L_TIM2 0
+#define STM32H7_RCC_APB1L_TIM3 1
+#define STM32H7_RCC_APB1L_TIM4 2
+#define STM32H7_RCC_APB1L_TIM5 3
+#define STM32H7_RCC_APB1L_TIM6 4
+#define STM32H7_RCC_APB1L_TIM7 5
+#define STM32H7_RCC_APB1L_TIM12 6
+#define STM32H7_RCC_APB1L_TIM13 7
+#define STM32H7_RCC_APB1L_TIM14 8
+#define STM32H7_RCC_APB1L_LPTIM1 9
+#define STM32H7_RCC_APB1L_SPI2 14
+#define STM32H7_RCC_APB1L_SPI3 15
+#define STM32H7_RCC_APB1L_SPDIF_RX 16
+#define STM32H7_RCC_APB1L_USART2 17
+#define STM32H7_RCC_APB1L_USART3 18
+#define STM32H7_RCC_APB1L_UART4 19
+#define STM32H7_RCC_APB1L_UART5 20
+#define STM32H7_RCC_APB1L_I2C1 21
+#define STM32H7_RCC_APB1L_I2C2 22
+#define STM32H7_RCC_APB1L_I2C3 23
+#define STM32H7_RCC_APB1L_HDMICEC 27
+#define STM32H7_RCC_APB1L_DAC12 29
+#define STM32H7_RCC_APB1L_USART7 30
+#define STM32H7_RCC_APB1L_USART8 31
+
+#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))
+
+/* APB1H */
+#define STM32H7_RCC_APB1H_CRS 1
+#define STM32H7_RCC_APB1H_SWP 2
+#define STM32H7_RCC_APB1H_OPAMP 4
+#define STM32H7_RCC_APB1H_MDIOS 5
+#define STM32H7_RCC_APB1H_FDCAN 8
+
+#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))
+
+/* APB2 */
+#define STM32H7_RCC_APB2_TIM1 0
+#define STM32H7_RCC_APB2_TIM8 1
+#define STM32H7_RCC_APB2_USART1 4
+#define STM32H7_RCC_APB2_USART6 5
+#define STM32H7_RCC_APB2_SPI1 12
+#define STM32H7_RCC_APB2_SPI4 13
+#define STM32H7_RCC_APB2_TIM15 16
+#define STM32H7_RCC_APB2_TIM16 17
+#define STM32H7_RCC_APB2_TIM17 18
+#define STM32H7_RCC_APB2_SPI5 20
+#define STM32H7_RCC_APB2_SAI1 22
+#define STM32H7_RCC_APB2_SAI2 23
+#define STM32H7_RCC_APB2_SAI3 24
+#define STM32H7_RCC_APB2_DFSDM1 28
+#define STM32H7_RCC_APB2_HRTIM 29
+
+#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))
+
+/* APB4 */
+#define STM32H7_RCC_APB4_SYSCFG 1
+#define STM32H7_RCC_APB4_LPUART1 3
+#define STM32H7_RCC_APB4_SPI6 5
+#define STM32H7_RCC_APB4_I2C4 7
+#define STM32H7_RCC_APB4_LPTIM2 9
+#define STM32H7_RCC_APB4_LPTIM3 10
+#define STM32H7_RCC_APB4_LPTIM4 11
+#define STM32H7_RCC_APB4_LPTIM5 12
+#define STM32H7_RCC_APB4_COMP12 14
+#define STM32H7_RCC_APB4_VREF 15
+#define STM32H7_RCC_APB4_SAI4 21
+#define STM32H7_RCC_APB4_TMPSENS 26
+
+#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))
+
+#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */
diff --git a/dts/include/dt-bindings/mips/lantiq_rcu_gphy.h b/dts/include/dt-bindings/mips/lantiq_rcu_gphy.h
new file mode 100644
index 0000000000..fa1a637733
--- /dev/null
+++ b/dts/include/dt-bindings/mips/lantiq_rcu_gphy.h
@@ -0,0 +1,15 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+
+#define GPHY_MODE_GE 1
+#define GPHY_MODE_FE 2
+
+#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */
diff --git a/dts/include/dt-bindings/pinctrl/dra.h b/dts/include/dt-bindings/pinctrl/dra.h
index 5c75e80915..18ec5df5a5 100644
--- a/dts/include/dt-bindings/pinctrl/dra.h
+++ b/dts/include/dt-bindings/pinctrl/dra.h
@@ -73,5 +73,8 @@
*/
#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
+/* DRA7 IODELAY configuration parameters */
+#define A_DELAY_PS(val) ((val) & 0xffff)
+#define G_DELAY_PS(val) ((val) & 0xffff)
#endif
diff --git a/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
index d33f17c8a5..b8ff8824e2 100644
--- a/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
+++ b/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
@@ -98,6 +98,8 @@
#define PMIC_GPIO_FUNC_PAIRED "paired"
#define PMIC_GPIO_FUNC_FUNC1 "func1"
#define PMIC_GPIO_FUNC_FUNC2 "func2"
+#define PMIC_GPIO_FUNC_FUNC3 "func3"
+#define PMIC_GPIO_FUNC_FUNC4 "func4"
#define PMIC_GPIO_FUNC_DTEST1 "dtest1"
#define PMIC_GPIO_FUNC_DTEST2 "dtest2"
#define PMIC_GPIO_FUNC_DTEST3 "dtest3"
diff --git a/dts/include/dt-bindings/pinctrl/samsung.h b/dts/include/dt-bindings/pinctrl/samsung.h
index b7aa364620..ceb672305f 100644
--- a/dts/include/dt-bindings/pinctrl/samsung.h
+++ b/dts/include/dt-bindings/pinctrl/samsung.h
@@ -66,7 +66,8 @@
#define EXYNOS_PIN_FUNC_4 4
#define EXYNOS_PIN_FUNC_5 5
#define EXYNOS_PIN_FUNC_6 6
-#define EXYNOS_PIN_FUNC_F 0xf
+#define EXYNOS_PIN_FUNC_EINT 0xf
+#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
/* Drive strengths for Exynos7 FSYS1 block */
#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
diff --git a/dts/include/dt-bindings/power/mt7622-power.h b/dts/include/dt-bindings/power/mt7622-power.h
new file mode 100644
index 0000000000..1b63926979
--- /dev/null
+++ b/dts/include/dt-bindings/power/mt7622-power.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT7622_POWER_H
+#define _DT_BINDINGS_POWER_MT7622_POWER_H
+
+#define MT7622_POWER_DOMAIN_ETHSYS 0
+#define MT7622_POWER_DOMAIN_HIF0 1
+#define MT7622_POWER_DOMAIN_HIF1 2
+#define MT7622_POWER_DOMAIN_WB 3
+
+#endif /* _DT_BINDINGS_POWER_MT7622_POWER_H */
diff --git a/dts/include/dt-bindings/power/r8a77995-sysc.h b/dts/include/dt-bindings/power/r8a77995-sysc.h
new file mode 100644
index 0000000000..09d0ed575b
--- /dev/null
+++ b/dts/include/dt-bindings/power/r8a77995-sysc.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77995_PD_CA53_CPU0 5
+#define R8A77995_PD_CA53_SCU 21
+
+/* Always-on power area */
+#define R8A77995_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
diff --git a/dts/include/dt-bindings/power/rk3366-power.h b/dts/include/dt-bindings/power/rk3366-power.h
new file mode 100644
index 0000000000..223a3dce04
--- /dev/null
+++ b/dts/include/dt-bindings/power/rk3366-power.h
@@ -0,0 +1,24 @@
+#ifndef __DT_BINDINGS_POWER_RK3366_POWER_H__
+#define __DT_BINDINGS_POWER_RK3366_POWER_H__
+
+/* VD_CORE */
+#define RK3366_PD_A53_0 0
+#define RK3366_PD_A53_1 1
+#define RK3366_PD_A53_2 2
+#define RK3366_PD_A53_3 3
+
+/* VD_LOGIC */
+#define RK3366_PD_BUS 4
+#define RK3366_PD_PERI 5
+#define RK3366_PD_VIO 6
+#define RK3366_PD_VIDEO 7
+#define RK3366_PD_RKVDEC 8
+#define RK3366_PD_WIFIBT 9
+#define RK3366_PD_VPU 10
+#define RK3366_PD_GPU 11
+#define RK3366_PD_ALIVE 12
+
+/* VD_PMU */
+#define RK3366_PD_PMU 13
+
+#endif
diff --git a/dts/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/dts/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
new file mode 100644
index 0000000000..1f1b56e573
--- /dev/null
+++ b/dts/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+
+#define CLKC_RESET_L2_CACHE_SOFT_RESET 0
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1
+#define CLKC_RESET_SCU_SOFT_RESET 2
+#define CLKC_RESET_CPU0_SOFT_RESET 3
+#define CLKC_RESET_CPU1_SOFT_RESET 4
+#define CLKC_RESET_CPU2_SOFT_RESET 5
+#define CLKC_RESET_CPU3_SOFT_RESET 6
+#define CLKC_RESET_A5_GLOBAL_RESET 7
+#define CLKC_RESET_A5_AXI_SOFT_RESET 8
+#define CLKC_RESET_A5_ABP_SOFT_RESET 9
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10
+#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */
diff --git a/dts/include/dt-bindings/reset/snps,hsdk-v1-reset.h b/dts/include/dt-bindings/reset/snps,hsdk-v1-reset.h
new file mode 100644
index 0000000000..d898c89b71
--- /dev/null
+++ b/dts/include/dt-bindings/reset/snps,hsdk-v1-reset.h
@@ -0,0 +1,17 @@
+/**
+ * This header provides index for the HSDK v1 reset controller.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_HSDK_V1
+#define _DT_BINDINGS_RESET_CONTROLLER_HSDK_V1
+
+#define HSDK_V1_APB_RESET 0
+#define HSDK_V1_AXI_RESET 1
+#define HSDK_V1_ETH_RESET 2
+#define HSDK_V1_USB_RESET 3
+#define HSDK_V1_SDIO_RESET 4
+#define HSDK_V1_HDMI_RESET 5
+#define HSDK_V1_GFX_RESET 6
+#define HSDK_V1_DMAC_RESET 7
+#define HSDK_V1_EBI_RESET 8
+
+#endif /*_DT_BINDINGS_RESET_CONTROLLER_HSDK_V1*/
diff --git a/dts/src/arm/imx6ul-geam-kit.dts b/dts/include/dt-bindings/reset/sun4i-a10-ccu.h
index 142e60cab6..5f4480bedc 100644
--- a/dts/src/arm/imx6ul-geam-kit.dts
+++ b/dts/include/dt-bindings/reset/sun4i-a10-ccu.h
@@ -1,6 +1,5 @@
/*
- * Copyright (C) 2016 Amarula Solutions B.V.
- * Copyright (C) 2016 Engicam S.r.l.
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -8,8 +7,9 @@
* whole.
*
* a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -40,62 +40,30 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/dts-v1/;
+#ifndef _DT_BINDINGS_RST_SUN4I_A10_H
+#define _DT_BINDINGS_RST_SUN4I_A10_H
-#include <dt-bindings/gpio/gpio.h>
-#include "imx6ul-geam.dtsi"
+#define RST_USB_PHY0 1
+#define RST_USB_PHY1 2
+#define RST_USB_PHY2 3
+#define RST_GPS 4
+#define RST_DE_BE0 5
+#define RST_DE_BE1 6
+#define RST_DE_FE0 7
+#define RST_DE_FE1 8
+#define RST_DE_MP 9
+#define RST_TVE0 10
+#define RST_TCON0 11
+#define RST_TVE1 12
+#define RST_TCON1 13
+#define RST_CSI0 14
+#define RST_CSI1 15
+#define RST_VE 16
+#define RST_ACE 17
+#define RST_LVDS 18
+#define RST_GPU 19
+#define RST_HDMI_H 20
+#define RST_HDMI_SYS 21
+#define RST_HDMI_AUDIO_DMA 22
-/ {
- model = "Engicam GEAM6UL";
- compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
-};
-
-&can1 {
- status = "okay";
-};
-
-&can2 {
- status = "okay";
-};
-
-&lcdif {
- display = <&display0>;
- status = "okay";
-
- display0: display {
- bits-per-pixel = <16>;
- bus-width = <18>;
- status = "okay";
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <28000000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <30>;
- hback-porch = <30>;
- hsync-len = <64>;
- vback-porch = <5>;
- vfront-porch = <5>;
- vsync-len = <20>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- };
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- status = "okay";
-};
-
-&tsc {
- measure-delay-time = <0x1ffff>;
- pre-charge-time = <0x1fff>;
- status = "okay";
-};
+#endif /* DT_BINDINGS_RST_SUN4I_A10_H */
diff --git a/dts/include/dt-bindings/reset/sun8i-r40-ccu.h b/dts/include/dt-bindings/reset/sun8i-r40-ccu.h
new file mode 100644
index 0000000000..c5ebcf6672
--- /dev/null
+++ b/dts/include/dt-bindings/reset/sun8i-r40-ccu.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_
+#define _DT_BINDINGS_RST_SUN8I_R40_H_
+
+#define RST_USB_PHY0 0
+#define RST_USB_PHY1 1
+#define RST_USB_PHY2 2
+
+#define RST_DRAM 3
+#define RST_MBUS 4
+
+#define RST_BUS_MIPI_DSI 5
+#define RST_BUS_CE 6
+#define RST_BUS_DMA 7
+#define RST_BUS_MMC0 8
+#define RST_BUS_MMC1 9
+#define RST_BUS_MMC2 10
+#define RST_BUS_MMC3 11
+#define RST_BUS_NAND 12
+#define RST_BUS_DRAM 13
+#define RST_BUS_EMAC 14
+#define RST_BUS_TS 15
+#define RST_BUS_HSTIMER 16
+#define RST_BUS_SPI0 17
+#define RST_BUS_SPI1 18
+#define RST_BUS_SPI2 19
+#define RST_BUS_SPI3 20
+#define RST_BUS_SATA 21
+#define RST_BUS_OTG 22
+#define RST_BUS_EHCI0 23
+#define RST_BUS_EHCI1 24
+#define RST_BUS_EHCI2 25
+#define RST_BUS_OHCI0 26
+#define RST_BUS_OHCI1 27
+#define RST_BUS_OHCI2 28
+#define RST_BUS_VE 29
+#define RST_BUS_MP 30
+#define RST_BUS_DEINTERLACE 31
+#define RST_BUS_CSI0 32
+#define RST_BUS_CSI1 33
+#define RST_BUS_HDMI0 34
+#define RST_BUS_HDMI1 35
+#define RST_BUS_DE 36
+#define RST_BUS_TVE0 37
+#define RST_BUS_TVE1 38
+#define RST_BUS_TVE_TOP 39
+#define RST_BUS_GMAC 40
+#define RST_BUS_GPU 41
+#define RST_BUS_TVD0 42
+#define RST_BUS_TVD1 43
+#define RST_BUS_TVD2 44
+#define RST_BUS_TVD3 45
+#define RST_BUS_TVD_TOP 46
+#define RST_BUS_TCON_LCD0 47
+#define RST_BUS_TCON_LCD1 48
+#define RST_BUS_TCON_TV0 49
+#define RST_BUS_TCON_TV1 50
+#define RST_BUS_TCON_TOP 51
+#define RST_BUS_DBG 52
+#define RST_BUS_LVDS 53
+#define RST_BUS_CODEC 54
+#define RST_BUS_SPDIF 55
+#define RST_BUS_AC97 56
+#define RST_BUS_IR0 57
+#define RST_BUS_IR1 58
+#define RST_BUS_THS 59
+#define RST_BUS_KEYPAD 60
+#define RST_BUS_I2S0 61
+#define RST_BUS_I2S1 62
+#define RST_BUS_I2S2 63
+#define RST_BUS_I2C0 64
+#define RST_BUS_I2C1 65
+#define RST_BUS_I2C2 66
+#define RST_BUS_I2C3 67
+#define RST_BUS_CAN 68
+#define RST_BUS_SCR 69
+#define RST_BUS_PS20 70
+#define RST_BUS_PS21 71
+#define RST_BUS_I2C4 72
+#define RST_BUS_UART0 73
+#define RST_BUS_UART1 74
+#define RST_BUS_UART2 75
+#define RST_BUS_UART3 76
+#define RST_BUS_UART4 77
+#define RST_BUS_UART5 78
+#define RST_BUS_UART6 79
+#define RST_BUS_UART7 80
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */
diff --git a/dts/src/arc/axc001.dtsi b/dts/src/arc/axc001.dtsi
index a380ffa1a4..fdc266504a 100644
--- a/dts/src/arc/axc001.dtsi
+++ b/dts/src/arc/axc001.dtsi
@@ -99,7 +99,7 @@
memory {
device_type = "memory";
- /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
+ /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
};
diff --git a/dts/src/arc/axc003.dtsi b/dts/src/arc/axc003.dtsi
index cc9239ef8d..4e6e9f57e7 100644
--- a/dts/src/arc/axc003.dtsi
+++ b/dts/src/arc/axc003.dtsi
@@ -24,10 +24,17 @@
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
- core_clk: core_clk {
+ input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <90000000>;
+ clock-frequency = <33333333>;
+ };
+
+ core_clk: core-clk@80 {
+ compatible = "snps,axs10x-arc-pll-clock";
+ reg = <0x80 0x10>, <0x100 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
};
core_intc: archs-intc@cpu {
@@ -102,7 +109,7 @@
memory {
device_type = "memory";
- /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
+ /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
};
diff --git a/dts/src/arc/axc003_idu.dtsi b/dts/src/arc/axc003_idu.dtsi
index 4ebb2170ab..63954a8b01 100644
--- a/dts/src/arc/axc003_idu.dtsi
+++ b/dts/src/arc/axc003_idu.dtsi
@@ -24,10 +24,17 @@
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
- core_clk: core_clk {
+ input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <100000000>;
+ clock-frequency = <33333333>;
+ };
+
+ core_clk: core-clk@80 {
+ compatible = "snps,axs10x-arc-pll-clock";
+ reg = <0x80 0x10>, <0x100 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
};
core_intc: archs-intc@cpu {
@@ -108,7 +115,7 @@
memory {
device_type = "memory";
- /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
+ /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
};
diff --git a/dts/src/arc/axs10x_mb.dtsi b/dts/src/arc/axs10x_mb.dtsi
index 0ff7e07edc..2367a67c5f 100644
--- a/dts/src/arc/axs10x_mb.dtsi
+++ b/dts/src/arc/axs10x_mb.dtsi
@@ -101,7 +101,6 @@
mmc@0x15000 {
compatible = "altr,socfpga-dw-mshc";
reg = < 0x15000 0x400 >;
- num-slots = < 1 >;
fifo-depth = < 16 >;
card-detect-delay = < 200 >;
clocks = <&apbclk>, <&mmcclk>;
diff --git a/dts/src/arc/hsdk.dts b/dts/src/arc/hsdk.dts
new file mode 100644
index 0000000000..229d13adbc
--- /dev/null
+++ b/dts/src/arc/hsdk.dts
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Device Tree for ARC HS Development Kit
+ */
+/dts-v1/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "snps,hsdk";
+ compatible = "snps,hsdk";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <0>;
+ clocks = <&core_clk>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <1>;
+ clocks = <&core_clk>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <2>;
+ clocks = <&core_clk>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <3>;
+ clocks = <&core_clk>;
+ };
+ };
+
+ core_clk: core-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ };
+
+ cpu_intc: cpu-interrupt-controller {
+ compatible = "snps,archs-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ idu_intc: idu-interrupt-controller {
+ compatible = "snps,archs-idu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpu_intc>;
+ };
+
+ arcpct: pct {
+ compatible = "snps,archs-pct";
+ };
+
+ /* TIMER0 with interrupt for clockevent */
+ timer {
+ compatible = "snps,arc-timer";
+ interrupts = <16>;
+ interrupt-parent = <&cpu_intc>;
+ clocks = <&core_clk>;
+ };
+
+ /* 64-bit Global Free Running Counter */
+ gfrc {
+ compatible = "snps,archs-timer-gfrc";
+ clocks = <&core_clk>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&idu_intc>;
+
+ ranges = <0x00000000 0xf0000000 0x10000000>;
+
+ serial: serial@5000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x5000 0x100>;
+ clock-frequency = <33330000>;
+ interrupts = <6>;
+ baud = <115200>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ gmacclk: gmacclk {
+ compatible = "fixed-clock";
+ clock-frequency = <400000000>;
+ #clock-cells = <0>;
+ };
+
+ mmcclk_ciu: mmcclk-ciu {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ #clock-cells = <0>;
+ };
+
+ mmcclk_biu: mmcclk-biu {
+ compatible = "fixed-clock";
+ clock-frequency = <400000000>;
+ #clock-cells = <0>;
+ };
+
+ ethernet@8000 {
+ #interrupt-cells = <1>;
+ compatible = "snps,dwmac";
+ reg = <0x8000 0x2000>;
+ interrupts = <10>;
+ interrupt-names = "macirq";
+ phy-mode = "rgmii";
+ snps,pbl = <32>;
+ clocks = <&gmacclk>;
+ clock-names = "stmmaceth";
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+ };
+ };
+
+ ohci@60000 {
+ compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
+ reg = <0x60000 0x100>;
+ interrupts = <15>;
+ };
+
+ ehci@40000 {
+ compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
+ reg = <0x40000 0x100>;
+ interrupts = <15>;
+ };
+
+ mmc@a000 {
+ compatible = "altr,socfpga-dw-mshc";
+ reg = <0xa000 0x400>;
+ num-slots = <1>;
+ fifo-depth = <16>;
+ card-detect-delay = <200>;
+ clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+ clock-names = "biu", "ciu";
+ interrupts = <12>;
+ bus-width = <4>;
+ };
+ };
+
+ memory@80000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GiB */
+ };
+};
diff --git a/dts/src/arc/nsim_hs.dts b/dts/src/arc/nsim_hs.dts
index 3772c40c24..8d787b251f 100644
--- a/dts/src/arc/nsim_hs.dts
+++ b/dts/src/arc/nsim_hs.dts
@@ -18,7 +18,7 @@
memory {
device_type = "memory";
- /* CONFIG_LINUX_LINK_BASE needs to match low mem start */
+ /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
};
diff --git a/dts/src/arc/vdk_axs10x_mb.dtsi b/dts/src/arc/vdk_axs10x_mb.dtsi
index 459fc656b7..48bb4b4cd2 100644
--- a/dts/src/arc/vdk_axs10x_mb.dtsi
+++ b/dts/src/arc/vdk_axs10x_mb.dtsi
@@ -104,7 +104,6 @@
mmc@0x15000 {
compatible = "snps,dw-mshc";
reg = <0x15000 0x400>;
- num-slots = <1>;
fifo-depth = <1024>;
card-detect-delay = <200>;
clocks = <&apbclk>, <&mmcclk>;
diff --git a/dts/src/arm/am335x-bone-common.dtsi b/dts/src/arm/am335x-bone-common.dtsi
index 1d154444df..48a15fc641 100644
--- a/dts/src/arm/am335x-bone-common.dtsi
+++ b/dts/src/arm/am335x-bone-common.dtsi
@@ -319,13 +319,10 @@
ti,pmic-shutdown-controller;
charger {
- interrupts = <0>, <1>;
- interrupt-names = "USB", "AC";
status = "okay";
};
pwrbutton {
- interrupts = <2>;
status = "okay";
};
diff --git a/dts/src/arm/am335x-chiliboard.dts b/dts/src/arm/am335x-chiliboard.dts
index d876979977..59431b2359 100644
--- a/dts/src/arm/am335x-chiliboard.dts
+++ b/dts/src/arm/am335x-chiliboard.dts
@@ -191,13 +191,10 @@
interrupts = <7>; /* NNMI */
charger {
- interrupts = <0>, <1>;
- interrupt-names = "USB", "AC";
status = "okay";
};
pwrbutton {
- interrupts = <2>;
status = "okay";
};
};
diff --git a/dts/src/arm/am335x-evm.dts b/dts/src/arm/am335x-evm.dts
index 1c37a7c1ea..ddd897556e 100644
--- a/dts/src/arm/am335x-evm.dts
+++ b/dts/src/arm/am335x-evm.dts
@@ -531,6 +531,7 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
diff --git a/dts/src/arm/am335x-moxa-uc-8100-me-t.dts b/dts/src/arm/am335x-moxa-uc-8100-me-t.dts
new file mode 100644
index 0000000000..f82233cd18
--- /dev/null
+++ b/dts/src/arm/am335x-moxa-uc-8100-me-t.dts
@@ -0,0 +1,525 @@
+/*
+ * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/
+ *
+ * Author: SZ Lin (林上智) <sz.lin@moxa.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+ model = "Moxa UC-8100-ME-T";
+ compatible = "moxa,uc-8100-me-t", "ti,am33xx";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+
+ vbat: vbat-regulator {
+ compatible = "regulator-fixed";
+ };
+
+ /* Power supply provides a fixed 3.3V @3A */
+ vmmcsd_fixed: vmmcsd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1 {
+ label = "uc8100me:CEL1";
+ gpios = <&gpio_xten 8 0>;
+ default-state = "off";
+ };
+
+ led2 {
+ label = "uc8100me:CEL2";
+ gpios = <&gpio_xten 9 0>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "uc8100me:CEL3";
+ gpios = <&gpio_xten 10 0>;
+ default-state = "off";
+ };
+
+ led4 {
+ label = "uc8100me:DIA1";
+ gpios = <&gpio_xten 11 0>;
+ default-state = "off";
+ };
+ led5 {
+ label = "uc8100me:DIA2";
+ gpios = <&gpio_xten 12 0>;
+ default-state = "off";
+ };
+ led6 {
+ label = "uc8100me:DIA3";
+ gpios = <&gpio_xten 13 0>;
+ default-state = "off";
+ };
+ led7 {
+ label = "uc8100me:SD";
+ gpios = <&gpio_xten 14 0>;
+ default-state = "off";
+ };
+ led8 {
+ label = "uc8100me:USB";
+ gpios = <&gpio_xten 15 0>;
+ default-state = "off";
+ };
+ led9 {
+ label = "uc8100me:USER";
+ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ buttons: push_button {
+ compatible = "gpio-keys";
+ };
+
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_pins>;
+
+ minipcie_pins: pinmux_minipcie {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2_24 */
+ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */
+ AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/
+ >;
+ };
+
+ push_button_pins: pinmux_push_button {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_ctsn.i2c1_sda */
+ AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_rtsn.i2c1_scl */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
+ AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
+ AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
+ AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE6) /* lcd_data14.uart5_ctsn */
+ AM33XX_IOPAD(0x8dc, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* lcd_data15.uart5_rtsn */
+ AM33XX_IOPAD(0x8c4, PIN_INPUT_PULLUP | MUX_MODE4) /* lcd_data9.uart5_rxd */
+ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE4) /* lcd_data8.uart5_txd */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
+ AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_refclk.rmii1_refclk */
+
+ /* Slave 2 */
+ AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */
+ AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */
+ AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */
+ AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */
+ AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */
+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */
+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */
+ AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */
+
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ mmc0_pins_default: pinmux_mmc0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
+ AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */
+ AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */
+ >;
+ };
+
+ mmc2_pins_default: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ /* eMMC */
+ AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */
+ AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */
+ AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */
+ AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */
+ AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */
+ AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */
+ AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */
+ AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */
+ AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
+ AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
+ >;
+ };
+
+ spi0_pins: pinmux_spi0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
+ AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
+ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
+ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
+ >;
+ };
+
+};
+
+&uart0 {
+ /* Console */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
+&uart1 {
+ /* UART 1 setting */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&uart5 {
+ /* UART 2 setting */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tpm: tpm@20 {
+ compatible = "infineon,slb9645tt";
+ reg = <0x20>;
+ };
+
+ tps: tps@2d {
+ compatible = "ti,tps65910";
+ reg = <0x2d>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+
+ rtc_wdt: rtc_wdt@68 {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+ gpio_xten: gpio_xten@27 {
+ compatible = "nxp,pca9535";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x27>;
+ };
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1378000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc_reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+/* Power */
+&vbat {
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+ dual_emac = <1>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ status = "okay";
+ phy_id = <&davinci_mdio>, <4>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ status = "okay";
+ phy_id = <&davinci_mdio>, <5>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <2>;
+};
+
+&phy_sel {
+ reg= <0x44e10650 0xf5>;
+ rmii-clock-ext;
+};
+
+&sham {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&gpio0 {
+ ti,no-reset-on-init;
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <4>;
+ pinctrl-0 = <&mmc0_pins_default>;
+ cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&mmc3 {
+ dmas = <&edma_xbar 12 0 1
+ &edma_xbar 13 0 2>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <8>;
+ pinctrl-0 = <&mmc2_pins_default>;
+ ti,non-removable;
+ status = "okay";
+};
+
+&buttons {
+ pinctrl-names = "default";
+ pinctrl-0 = <&push_button_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@0 {
+ label = "push_button";
+ linux,code = <0x100>;
+ gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/* SPI Busses */
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+
+ m25p80@0 {
+ compatible = "mx25l6405d";
+ spi-max-frequency = <40000000>;
+
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* reg : The partition's offset and size within the mtd bank. */
+ partitions@0 {
+ label = "MLO";
+ reg = <0x0 0x80000>;
+ };
+
+ partitions@1 {
+ label = "U-Boot";
+ reg = <0x80000 0x100000>;
+ };
+
+ partitions@2 {
+ label = "U-Boot Env";
+ reg = <0x180000 0x20000>;
+ };
+ };
+};
diff --git a/dts/src/arm/am437x-gp-evm.dts b/dts/src/arm/am437x-gp-evm.dts
index 29a538ecd4..afb8eb0a0a 100644
--- a/dts/src/arm/am437x-gp-evm.dts
+++ b/dts/src/arm/am437x-gp-evm.dts
@@ -149,6 +149,13 @@
system-clock-frequency = <12000000>;
};
};
+
+ beeper: beeper {
+ compatible = "gpio-beeper";
+ pinctrl-names = "default";
+ pinctrl-0 = <&beeper_pins>;
+ gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+ };
};
&am43xx_pinmux {
@@ -510,6 +517,13 @@
AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
+
+ beeper_pins: beeper_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
+ >;
+ };
+
};
&uart0 {
@@ -842,6 +856,7 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
diff --git a/dts/src/arm/am43x-epos-evm.dts b/dts/src/arm/am43x-epos-evm.dts
index 54f40f3700..9d276af7c5 100644
--- a/dts/src/arm/am43x-epos-evm.dts
+++ b/dts/src/arm/am43x-epos-evm.dts
@@ -564,6 +564,7 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
diff --git a/dts/src/arm/am571x-idk.dts b/dts/src/arm/am571x-idk.dts
index 7b207835b2..debf946440 100644
--- a/dts/src/arm/am571x-idk.dts
+++ b/dts/src/arm/am571x-idk.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
/ {
model = "TI AM5718 IDK";
@@ -64,13 +65,6 @@
};
};
-&mmc1 {
- status = "okay";
- vmmc-supply = <&ldo1_reg>;
- bus-width = <4>;
- cd-gpios = <&gpio6 27 0>; /* gpio 219 */
-};
-
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
@@ -96,3 +90,30 @@
status = "okay";
};
};
+
+&pcie1_rc {
+ status = "okay";
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
+};
diff --git a/dts/src/arm/am572x-idk.dts b/dts/src/arm/am572x-idk.dts
index 9da6d83ca1..a578fe97ba 100644
--- a/dts/src/arm/am572x-idk.dts
+++ b/dts/src/arm/am572x-idk.dts
@@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
/ {
model = "TI AM5728 IDK";
@@ -67,6 +68,24 @@
};
};
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20>;
+};
+
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
@@ -76,19 +95,16 @@
vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
};
-&mmc1 {
- status = "okay";
- vmmc-supply = <&v3_3d>;
- vmmc_aux-supply = <&ldo1_reg>;
- bus-width = <4>;
- cd-gpios = <&gpio6 27 0>; /* gpio 219 */
-};
-
&sn65hvs882 {
load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};
-&pcie1 {
+&pcie1_rc {
+ status = "okay";
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/src/arm/am57xx-beagle-x15-common.dtsi b/dts/src/arm/am57xx-beagle-x15-common.dtsi
index fdfe5b16b8..49aeecd312 100644
--- a/dts/src/arm/am57xx-beagle-x15-common.dtsi
+++ b/dts/src/arm/am57xx-beagle-x15-common.dtsi
@@ -9,6 +9,7 @@
#include "dra74x.dtsi"
#include "am57xx-commercial-grade.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -166,34 +167,6 @@
};
};
-&dra7_pmx_core {
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@@ -570,7 +543,12 @@
};
};
-&pcie1 {
+&pcie1_rc {
+ status = "ok";
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+};
+
+&pcie1_ep {
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/src/arm/am57xx-beagle-x15-revb1.dts b/dts/src/arm/am57xx-beagle-x15-revb1.dts
index 39a92aff0a..5a77b33492 100644
--- a/dts/src/arm/am57xx-beagle-x15-revb1.dts
+++ b/dts/src/arm/am57xx-beagle-x15-revb1.dts
@@ -19,8 +19,23 @@
};
&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
vmmc-supply = <&vdd_3v3>;
- vmmc-aux-supply = <&ldo1_reg>;
+ vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
};
/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
diff --git a/dts/src/arm/am57xx-beagle-x15-revc.dts b/dts/src/arm/am57xx-beagle-x15-revc.dts
new file mode 100644
index 0000000000..17c41da3b5
--- /dev/null
+++ b/dts/src/arm/am57xx-beagle-x15-revc.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am57xx-beagle-x15-common.dtsi"
+
+/ {
+ model = "TI AM5728 BeagleBoard-X15 rev C";
+};
+
+&tpd12s015 {
+ gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
+ <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+};
+
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20>;
+};
diff --git a/dts/src/arm/am57xx-beagle-x15.dts b/dts/src/arm/am57xx-beagle-x15.dts
index 19a60a11c1..d6689106d2 100644
--- a/dts/src/arm/am57xx-beagle-x15.dts
+++ b/dts/src/arm/am57xx-beagle-x15.dts
@@ -20,9 +20,20 @@
};
&mmc1 {
+ pinctrl-names = "default", "hs";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+
vmmc-supply = <&ldo1_reg>;
};
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
+};
+
/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
&phy1 {
max-speed = <100>;
diff --git a/dts/src/arm/am57xx-idk-common.dtsi b/dts/src/arm/am57xx-idk-common.dtsi
index c536b2f538..97aa8e6a56 100644
--- a/dts/src/arm/am57xx-idk-common.dtsi
+++ b/dts/src/arm/am57xx-idk-common.dtsi
@@ -399,6 +399,14 @@
dr_mode = "peripheral";
};
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&v3_3d>;
+ vqmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+};
+
&mmc2 {
status = "okay";
vmmc-supply = <&v3_3d>;
diff --git a/dts/src/arm/armada-370.dtsi b/dts/src/arm/armada-370.dtsi
index f9cf1273f3..b1cf5a26f3 100644
--- a/dts/src/arm/armada-370.dtsi
+++ b/dts/src/arm/armada-370.dtsi
@@ -72,7 +72,7 @@
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -100,6 +100,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@@ -117,6 +118,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
diff --git a/dts/src/arm/armada-375.dtsi b/dts/src/arm/armada-375.dtsi
index 50c5e84178..7225c7ce9a 100644
--- a/dts/src/arm/armada-375.dtsi
+++ b/dts/src/arm/armada-375.dtsi
@@ -582,7 +582,7 @@
};
};
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -610,6 +610,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@@ -627,6 +628,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
diff --git a/dts/src/arm/armada-380.dtsi b/dts/src/arm/armada-380.dtsi
index e392f6036f..132596fd08 100644
--- a/dts/src/arm/armada-380.dtsi
+++ b/dts/src/arm/armada-380.dtsi
@@ -71,7 +71,7 @@
};
};
- pcie-controller {
+ pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -104,6 +104,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@@ -122,6 +123,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@@ -140,6 +142,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
diff --git a/dts/src/arm/armada-385-db-ap.dts b/dts/src/arm/armada-385-db-ap.dts
index db5b9f6b61..25d2d720dc 100644
--- a/dts/src/arm/armada-385-db-ap.dts
+++ b/dts/src/arm/armada-385-db-ap.dts
@@ -209,7 +209,7 @@
status = "okay";
};
- pcie-controller {
+ pcie {
status = "okay";
/*
diff --git a/dts/src/arm/armada-385-turris-omnia.dts b/dts/src/arm/armada-385-turris-omnia.dts
index be16ce39fb..06831e1e3f 100644
--- a/dts/src/arm/armada-385-turris-omnia.dts
+++ b/dts/src/arm/armada-385-turris-omnia.dts
@@ -96,7 +96,7 @@
};
};
- pcie-controller {
+ pcie {
status = "okay";
pcie@1,0 {
diff --git a/dts/src/arm/armada-385.dtsi b/dts/src/arm/armada-385.dtsi
index 7fcc4c4885..74863aff01 100644
--- a/dts/src/arm/armada-385.dtsi
+++ b/dts/src/arm/armada-385.dtsi
@@ -70,7 +70,7 @@
};
soc {
- pciec: pcie-controller {
+ pciec: pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -109,6 +109,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@@ -127,6 +128,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@@ -145,6 +147,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
@@ -166,6 +169,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <3>;
diff --git a/dts/src/arm/armada-388-clearfog.dts b/dts/src/arm/armada-388-clearfog.dts
index 0d5f1f0622..ee7b0089ef 100644
--- a/dts/src/arm/armada-388-clearfog.dts
+++ b/dts/src/arm/armada-388-clearfog.dts
@@ -62,7 +62,7 @@
};
};
- pcie-controller {
+ pcie {
pcie@3,0 {
/* Port 2, Lane 0. CON2, nearest CPU. */
reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
diff --git a/dts/src/arm/armada-388-clearfog.dtsi b/dts/src/arm/armada-388-clearfog.dtsi
index 0f5938bede..68acfc9687 100644
--- a/dts/src/arm/armada-388-clearfog.dtsi
+++ b/dts/src/arm/armada-388-clearfog.dtsi
@@ -104,7 +104,7 @@
};
};
- pcie-controller {
+ pcie {
status = "okay";
/*
* The two PCIe units are accessible through
diff --git a/dts/src/arm/armada-388-db.dts b/dts/src/arm/armada-388-db.dts
index 1ac9238264..a4ec1fa375 100644
--- a/dts/src/arm/armada-388-db.dts
+++ b/dts/src/arm/armada-388-db.dts
@@ -172,7 +172,7 @@
status = "okay";
};
- pcie-controller {
+ pcie {
status = "okay";
/*
* The two PCIe units are accessible through
diff --git a/dts/src/arm/armada-388-gp.dts b/dts/src/arm/armada-388-gp.dts
index 563901e0ec..f503955dbd 100644
--- a/dts/src/arm/armada-388-gp.dts
+++ b/dts/src/arm/armada-388-gp.dts
@@ -240,7 +240,7 @@
status = "okay";
};
- pcie-controller {
+ pcie {
status = "okay";
/*
* One PCIe units is accessible through
diff --git a/dts/src/arm/armada-388-rd.dts b/dts/src/arm/armada-388-rd.dts
index af82f275ea..9cc3ca0376 100644
--- a/dts/src/arm/armada-388-rd.dts
+++ b/dts/src/arm/armada-388-rd.dts
@@ -117,7 +117,7 @@
};
};
- pcie-controller {
+ pcie {
status = "okay";
/*
* One PCIe units is accessible through
diff --git a/dts/src/arm/armada-38x.dtsi b/dts/src/arm/armada-38x.dtsi
index af31f5d6c0..7ff0811e61 100644
--- a/dts/src/arm/armada-38x.dtsi
+++ b/dts/src/arm/armada-38x.dtsi
@@ -154,6 +154,13 @@
reg = <0xc000 0x58>;
};
+ timer@c200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xc200 0x20>;
+ interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+ clocks = <&coreclk 2>;
+ };
+
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
diff --git a/dts/src/arm/armada-390-db.dts b/dts/src/arm/armada-390-db.dts
index 2afed2ce47..c718a52425 100644
--- a/dts/src/arm/armada-390-db.dts
+++ b/dts/src/arm/armada-390-db.dts
@@ -123,7 +123,7 @@
};
};
- pcie-controller {
+ pcie {
status = "okay";
/* CON30 */
diff --git a/dts/src/arm/armada-395-gp.dts b/dts/src/arm/armada-395-gp.dts
index 2cdbba804c..ef491b524f 100644
--- a/dts/src/arm/armada-395-gp.dts
+++ b/dts/src/arm/armada-395-gp.dts
@@ -139,7 +139,7 @@
};
};
- pcie-controller {
+ pcie {
status = "okay";
/*
diff --git a/dts/src/arm/armada-398-db.dts b/dts/src/arm/armada-398-db.dts
index e8604281c3..f0e0379f76 100644
--- a/dts/src/arm/armada-398-db.dts
+++ b/dts/src/arm/armada-398-db.dts
@@ -118,7 +118,7 @@
};
};
- pcie-controller {
+ pcie {
status = "okay";
pcie@1,0 {
diff --git a/dts/src/arm/armada-39x.dtsi b/dts/src/arm/armada-39x.dtsi
index 60fbfd5907..ea657071e2 100644
--- a/dts/src/arm/armada-39x.dtsi
+++ b/dts/src/arm/armada-39x.dtsi
@@ -442,7 +442,7 @@
};
};
- pcie-controller {
+ pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -481,6 +481,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@@ -499,6 +500,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@@ -517,6 +519,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
@@ -538,6 +541,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <3>;
diff --git a/dts/src/arm/armada-xp-98dx3236.dtsi b/dts/src/arm/armada-xp-98dx3236.dtsi
index be22ec5236..bdd4c7a45f 100644
--- a/dts/src/arm/armada-xp-98dx3236.dtsi
+++ b/dts/src/arm/armada-xp-98dx3236.dtsi
@@ -91,7 +91,7 @@
/*
* 98DX3236 has 1 x1 PCIe unit Gen2.0
*/
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -116,6 +116,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
diff --git a/dts/src/arm/armada-xp-db.dts b/dts/src/arm/armada-xp-db.dts
index a33974254d..065282c217 100644
--- a/dts/src/arm/armada-xp-db.dts
+++ b/dts/src/arm/armada-xp-db.dts
@@ -242,7 +242,7 @@
/* Port 2, Lane 0 */
status = "okay";
};
- pcie@10,0 {
+ pcie@a,0 {
/* Port 3, Lane 0 */
status = "okay";
};
diff --git a/dts/src/arm/armada-xp-gp.dts b/dts/src/arm/armada-xp-gp.dts
index d62bf7bea1..ac9eab8ac1 100644
--- a/dts/src/arm/armada-xp-gp.dts
+++ b/dts/src/arm/armada-xp-gp.dts
@@ -227,7 +227,7 @@
/* Port 2, Lane 0 */
status = "okay";
};
- pcie@10,0 {
+ pcie@a,0 {
/* Port 3, Lane 0 */
status = "okay";
};
diff --git a/dts/src/arm/armada-xp-mv78230.dtsi b/dts/src/arm/armada-xp-mv78230.dtsi
index 9f25814077..129738f797 100644
--- a/dts/src/arm/armada-xp-mv78230.dtsi
+++ b/dts/src/arm/armada-xp-mv78230.dtsi
@@ -86,7 +86,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x1 only.
*/
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -123,6 +123,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@@ -140,6 +141,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
@@ -157,6 +159,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
@@ -174,6 +177,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
@@ -191,6 +195,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
diff --git a/dts/src/arm/armada-xp-mv78260.dtsi b/dts/src/arm/armada-xp-mv78260.dtsi
index 2bfe07aebf..e58d597e37 100644
--- a/dts/src/arm/armada-xp-mv78260.dtsi
+++ b/dts/src/arm/armada-xp-mv78260.dtsi
@@ -87,7 +87,7 @@
* configured as x4 or quad x1 lanes. One unit is
* x4 only.
*/
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -138,6 +138,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@@ -155,6 +156,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
@@ -172,6 +174,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
@@ -189,6 +192,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
@@ -206,6 +210,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
@@ -223,6 +228,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
@@ -240,6 +246,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
@@ -257,6 +264,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
@@ -274,6 +282,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
diff --git a/dts/src/arm/armada-xp-mv78460.dtsi b/dts/src/arm/armada-xp-mv78460.dtsi
index 6c33935f70..a5c961cee7 100644
--- a/dts/src/arm/armada-xp-mv78460.dtsi
+++ b/dts/src/arm/armada-xp-mv78460.dtsi
@@ -104,7 +104,7 @@
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@@ -159,6 +159,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@@ -176,6 +177,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
@@ -193,6 +195,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
@@ -210,6 +213,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
@@ -227,6 +231,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
@@ -244,6 +249,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
@@ -261,6 +267,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
@@ -278,6 +285,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
@@ -295,6 +303,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
@@ -303,7 +312,7 @@
status = "disabled";
};
- pcie10: pcie@10,0 {
+ pcie10: pcie@a,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
@@ -312,6 +321,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
diff --git a/dts/src/arm/aspeed-g4.dtsi b/dts/src/arm/aspeed-g4.dtsi
index 8a04c7e2d8..22b958537d 100644
--- a/dts/src/arm/aspeed-g4.dtsi
+++ b/dts/src/arm/aspeed-g4.dtsi
@@ -26,7 +26,7 @@
fmc: flash-controller@1e620000 {
reg = < 0x1e620000 0x94
- 0x20000000 0x02000000 >;
+ 0x20000000 0x10000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
@@ -41,7 +41,7 @@
spi: flash-controller@1e630000 {
reg = < 0x1e630000 0x18
- 0x30000000 0x02000000 >;
+ 0x30000000 0x10000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
diff --git a/dts/src/arm/at91-sama5d27_som1.dtsi b/dts/src/arm/at91-sama5d27_som1.dtsi
new file mode 100644
index 0000000000..63a5af8981
--- /dev/null
+++ b/dts/src/arm/at91-sama5d27_som1.dtsi
@@ -0,0 +1,102 @@
+/*
+ * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
+ *
+ * Copyright (c) 2017, Microchip Technology Inc.
+ * 2017 Cristian Birsan <cristian.birsan@microchip.com>
+ * 2017 Claudiu Beznea <claudiu.beznea@microchip.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+
+/ {
+ model = "Atmel SAMA5D27 SoM1";
+ compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+
+ ahb {
+ apb {
+ macb0: ethernet@f8008000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_default>;
+ phy-mode = "rmii";
+
+ ethernet-phy@1 {
+ reg = <0x1>;
+ interrupt-parent = <&pioA>;
+ interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_phy_irq>;
+ };
+ };
+
+ pinctrl@fc038000 {
+
+ pinctrl_macb0_default: macb0_default {
+ pinmux = <PIN_PD9__GTXCK>,
+ <PIN_PD10__GTXEN>,
+ <PIN_PD11__GRXDV>,
+ <PIN_PD12__GRXER>,
+ <PIN_PD13__GRX0>,
+ <PIN_PD14__GRX1>,
+ <PIN_PD15__GTX0>,
+ <PIN_PD16__GTX1>,
+ <PIN_PD17__GMDC>,
+ <PIN_PD18__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PD31__GPIO>;
+ bias-disable;
+ };
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/at91-sama5d27_som1_ek.dts b/dts/src/arm/at91-sama5d27_som1_ek.dts
new file mode 100644
index 0000000000..9c9088c99c
--- /dev/null
+++ b/dts/src/arm/at91-sama5d27_som1_ek.dts
@@ -0,0 +1,537 @@
+/*
+ * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board
+ *
+ * Copyright (c) 2017, Microchip Technology Inc.
+ * 2016 Nicolas Ferre <nicolas.ferre@atmel.com>
+ * 2017 Cristian Birsan <cristian.birsan@microchip.com>
+ * 2017 Claudiu Beznea <claudiu.beznea@microchip.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "at91-sama5d27_som1.dtsi"
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Atmel SAMA5D27 SOM1 EK";
+ compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ahb {
+ usb0: gadget@00300000 {
+ atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+ };
+
+ usb1: ohci@00400000 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+ };
+
+ usb2: ehci@00500000 {
+ status = "okay";
+ };
+
+ sdmmc0: sdio-host@a0000000 {
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ status = "okay";
+ };
+
+ sdmmc1: sdio-host@b0000000 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_default>;
+ status = "okay";
+ };
+
+ apb {
+ isc: isc@f0008000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>;
+ status = "okay";
+ };
+
+ spi0: spi@f8000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+ status = "okay";
+ };
+
+ macb0: ethernet@f8008000 {
+ status = "okay";
+ };
+
+ uart1: serial@f8020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+
+ uart2: serial@f8024000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus2_uart>;
+ atmel,use-dma-rx;
+ atmel-use-dma-tx;
+ status = "okay";
+ };
+
+ pwm0: pwm@f802c000 {
+ status = "okay";
+ };
+
+ flx1: flexcom@f8038000 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "disabled";
+
+ i2c2: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <0>, <0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&flx1_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus_i2c>;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+ };
+
+ shdwc@f8048010 {
+ atmel,shdwc-debouncer = <976>;
+ atmel,wakeup-rtc-timer;
+
+ input@0 {
+ reg = <0>;
+ atmel,wakeup-type = "low";
+ };
+ };
+
+ watchdog@f8048040 {
+ status = "okay";
+ };
+
+ can0: can@f8054000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
+ };
+
+ uart3: serial@fc008000 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_default>;
+ status = "disabled";
+ };
+
+ uart4: serial@fc00c000 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-name = "default";
+ pinctrl-0 = <&pinctrl_mikrobus1_uart>;
+ status = "okay";
+ };
+
+ flx3: flexcom@fc014000 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "disabled";
+
+ uart7: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&flx3_clk>;
+ clock-names = "usart";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx3_default>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi2: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&flx3_clk>;
+ clock-names = "spi_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx3_default>;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+ };
+
+ flx4: flexcom@fc018000 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "okay";
+
+ uart6: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&flx4_clk>;
+ clock-names = "usart";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx4_default>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi3: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&flx4_clk>;
+ clock-names = "spi_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>;
+ atmel,fifo-size = <16>;
+ status = "okay";
+ };
+
+ i2c3: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <0>, <0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&flx4_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx4_default>;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+ };
+
+ i2c1: i2c@fc028000 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+ };
+
+ pinctrl@fc038000 {
+
+ pinctrl_can0_default: can0_default {
+ pinmux = <PIN_PC10__CANTX0>,
+ <PIN_PC11__CANRX0>;
+ bias-disable;
+ };
+
+ pinctrl_can1_default: can1_default {
+ pinmux = <PIN_PC26__CANTX1>,
+ <PIN_PC27__CANRX1>;
+ bias-disable;
+ };
+
+ pinctrl_flx3_default: flx3_default {
+ pinmux = <PIN_PC20__FLEXCOM3_IO0>,
+ <PIN_PC19__FLEXCOM3_IO1>,
+ <PIN_PC18__FLEXCOM3_IO2>,
+ <PIN_PC21__FLEXCOM3_IO3>,
+ <PIN_PC22__FLEXCOM3_IO4>;
+ bias-disable;
+ };
+
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PD4__TWD1>,
+ <PIN_PD5__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_isc_base: isc_base {
+ pinmux = <PIN_PC21__ISC_PCK>,
+ <PIN_PC22__ISC_VSYNC>,
+ <PIN_PC23__ISC_HSYNC>,
+ <PIN_PC24__ISC_MCK>;
+ bias-disable;
+ };
+
+ pinctrl_isc_data_8bit: isc_data_8bit {
+ pinmux = <PIN_PC20__ISC_D11>,
+ <PIN_PC19__ISC_D10>,
+ <PIN_PC18__ISC_D9>,
+ <PIN_PC17__ISC_D8>,
+ <PIN_PC16__ISC_D7>,
+ <PIN_PC15__ISC_D6>,
+ <PIN_PC14__ISC_D5>,
+ <PIN_PC13__ISC_D4>;
+ bias-disable;
+ };
+
+ pinctrl_isc_data_9_10: isc_data_9_10 {
+ pinmux = <PIN_PC12__ISC_D3>,
+ <PIN_PC11__ISC_D2>;
+ bias-disable;
+ };
+
+ pinctrl_isc_data_11_12: isc_data_11_12 {
+ pinmux = <PIN_PC10__ISC_D1>,
+ <PIN_PC9__ISC_D0>;
+ bias-disable;
+ };
+
+ pinctrl_key_gpio_default: key_gpio_default {
+ pinmux = <PIN_PA29__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_led_gpio_default: led_gpio_default {
+ pinmux = <PIN_PA27__GPIO>,
+ <PIN_PB1__GPIO>,
+ <PIN_PA31__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0_default {
+ cmd_data {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>,
+ <PIN_PA6__SDMMC0_DAT4>,
+ <PIN_PA7__SDMMC0_DAT5>,
+ <PIN_PA8__SDMMC0_DAT6>,
+ <PIN_PA9__SDMMC0_DAT7>;
+ bias-pull-up;
+ };
+
+ ck_cd_vddsel {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA11__SDMMC0_VDDSEL>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdmmc1_default: sdmmc1_default {
+ cmd_data {
+ pinmux = <PIN_PA28__SDMMC1_CMD>,
+ <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>;
+ bias-pull-up;
+ };
+
+ conf-ck_cd {
+ pinmux = <PIN_PA22__SDMMC1_CK>,
+ <PIN_PA30__SDMMC1_CD>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_spi0_default: spi0_default {
+ pinmux = <PIN_PA14__SPI0_SPCK>,
+ <PIN_PA15__SPI0_MOSI>,
+ <PIN_PA16__SPI0_MISO>,
+ <PIN_PA17__SPI0_NPCS0>;
+ bias-disable;
+ };
+
+ pinctrl_uart1_default: uart1_default {
+ pinmux = <PIN_PD2__URXD1>,
+ <PIN_PD3__UTXD1>;
+ bias-disable;
+ };
+
+ pinctrl_uart3_default: uart3_default {
+ pinmux = <PIN_PC12__URXD3>,
+ <PIN_PC13__UTXD3>;
+ bias-disable;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PA10__GPIO>,
+ <PIN_PD19__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PD20__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_an: mikrobus1_an {
+ pinmux = <PIN_PD25__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_an: mikrobus2_an {
+ pinmux = <PIN_PD26__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_rst: mikrobus1_rst {
+ pinmux = <PIN_PB2__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_rst: mikrobus2_rst {
+ pinmux = <PIN_PA26__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs {
+ pinmux = <PIN_PD0__FLEXCOM4_IO4>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs {
+ pinmux = <PIN_PC31__FLEXCOM4_IO3>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus_spi: mikrobus_spi {
+ pinmux = <PIN_PC28__FLEXCOM4_IO0>,
+ <PIN_PC29__FLEXCOM4_IO1>,
+ <PIN_PC30__FLEXCOM4_IO2>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_pwm: mikrobus1_pwm {
+ pinmux = <PIN_PB1__PWML1>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_pwm: mikrobus2_pwm {
+ pinmux = <PIN_PA31__PWML0>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_int: mikrobus1_int {
+ pinmux = <PIN_PB0__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_int: mikrobus2_int {
+ pinmux = <PIN_PA25__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_uart: mikrobus1_uart {
+ pinmux = <PIN_PB3__URXD4>,
+ <PIN_PB4__UTXD4>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_uart: mikrobus2_uart {
+ pinmux = <PIN_PD23__URXD2>,
+ <PIN_PD24__UTXD2>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus_i2c: mikrobus1_i2c {
+ pinmux = <PIN_PA24__FLEXCOM1_IO0>,
+ <PIN_PA23__FLEXCOM1_IO1>;
+ bias-disable;
+ };
+
+ pinctrl_flx4_default: flx4_uart_default {
+ pinmux = <PIN_PC28__FLEXCOM4_IO0>,
+ <PIN_PC29__FLEXCOM4_IO1>,
+ <PIN_PC30__FLEXCOM4_IO2>,
+ <PIN_PC31__FLEXCOM4_IO3>,
+ <PIN_PD0__FLEXCOM4_IO4>;
+ bias-disable;
+ };
+ };
+
+ can1: can@fc050000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
+ status = "okay";
+ };
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+ pb4 {
+ label = "USER";
+ gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>;
+ linux,code = <0x104>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_gpio_default>;
+ status = "okay";
+
+ red {
+ label = "red";
+ gpios = <&pioA PIN_PA27 GPIO_ACTIVE_LOW>;
+ };
+
+ green {
+ label = "green";
+ gpios = <&pioA PIN_PB1 GPIO_ACTIVE_LOW>;
+ };
+
+ blue {
+ label = "blue";
+ gpios = <&pioA PIN_PA31 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
diff --git a/dts/src/arm/at91-sama5d2_xplained.dts b/dts/src/arm/at91-sama5d2_xplained.dts
index 2e2c3d1a1f..c7e9ccf2bc 100644
--- a/dts/src/arm/at91-sama5d2_xplained.dts
+++ b/dts/src/arm/at91-sama5d2_xplained.dts
@@ -68,7 +68,7 @@
ahb {
usb0: gadget@00300000 {
- atmel,vbus-gpio = <&pioA 31 GPIO_ACTIVE_HIGH>;
+ atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
@@ -76,8 +76,8 @@
usb1: ohci@00400000 {
num-ports = <3>;
- atmel,vbus-gpio = <0 /* &pioA 41 GPIO_ACTIVE_HIGH */
- &pioA 42 GPIO_ACTIVE_HIGH
+ atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */
+ &pioA PIN_PB10 GPIO_ACTIVE_HIGH
0
>;
pinctrl-names = "default";
@@ -127,7 +127,7 @@
ethernet-phy@1 {
reg = <0x1>;
interrupt-parent = <&pioA>;
- interrupts = <73 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <PIN_PC9 IRQ_TYPE_LEVEL_LOW>;
};
};
@@ -160,9 +160,9 @@
compatible = "active-semi,act8945a";
reg = <0x5b>;
active-semi,vsel-high;
- active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>;
- active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>;
- active-semi,irq_gpios = <&pioA 45 GPIO_ACTIVE_LOW>;
+ active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>;
+ active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>;
+ active-semi,irq_gpios = <&pioA PIN_PB13 GPIO_ACTIVE_LOW>;
active-semi,input-voltage-threshold-microvolt = <6600>;
active-semi,precondition-timeout = <40>;
active-semi,total-timeout = <3>;
@@ -355,6 +355,14 @@
bias-pull-up;
};
+ pinctrl_classd_default: classd_default {
+ pinmux = <PIN_PB1__CLASSD_R0>,
+ <PIN_PB2__CLASSD_R1>,
+ <PIN_PB3__CLASSD_R2>,
+ <PIN_PB4__CLASSD_R3>;
+ bias-pull-up;
+ };
+
pinctrl_flx0_default: flx0_default {
pinmux = <PIN_PB28__FLEXCOM0_IO0>,
<PIN_PB29__FLEXCOM0_IO1>;
@@ -488,6 +496,14 @@
};
+ classd: classd@fc048000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_classd_default>;
+ atmel,pwm-type = "diff";
+ atmel,non-overlap-time = <10>;
+ status = "okay";
+ };
+
can1: can@fc050000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
@@ -504,7 +520,7 @@
bp1 {
label = "PB_USER";
- gpios = <&pioA 41 GPIO_ACTIVE_LOW>;
+ gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
};
};
@@ -517,17 +533,18 @@
red {
label = "red";
- gpios = <&pioA 38 GPIO_ACTIVE_LOW>;
+ gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>;
};
+
green {
label = "green";
- gpios = <&pioA 37 GPIO_ACTIVE_LOW>;
+ gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>;
};
blue {
label = "blue";
- gpios = <&pioA 32 GPIO_ACTIVE_LOW>;
+ gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
diff --git a/dts/src/arm/at91sam9g45.dtsi b/dts/src/arm/at91sam9g45.dtsi
index a4808c4fbc..64fa3f9a39 100644
--- a/dts/src/arm/at91sam9g45.dtsi
+++ b/dts/src/arm/at91sam9g45.dtsi
@@ -455,6 +455,16 @@
>;
/* shared pinctrl settings */
+ ac97 {
+ pinctrl_ac97: ac97-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97RX */
+ AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97TX */
+ AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97FS */
+ AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* AC97CK */
+ };
+ };
+
adc0 {
pinctrl_adc0_adtrg: adc0_adtrg {
atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
@@ -1043,6 +1053,17 @@
status = "disabled";
};
+ ac97: sound@fffac000 {
+ compatible = "atmel,at91sam9263-ac97c";
+ reg = <0xfffac000 0x4000>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ac97>;
+ clocks = <&ac97_clk>;
+ clock-names = "ac97_clk";
+ status = "disabled";
+ };
+
adc0: adc@fffb0000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/at91sam9m10g45ek.dts b/dts/src/arm/at91sam9m10g45ek.dts
index 2522c33083..94c52c555f 100644
--- a/dts/src/arm/at91sam9m10g45ek.dts
+++ b/dts/src/arm/at91sam9m10g45ek.dts
@@ -166,6 +166,10 @@
status = "okay";
};
+ ac97: sound@fffac000 {
+ status = "okay";
+ };
+
adc0: adc@fffb0000 {
pinctrl-names = "default";
pinctrl-0 = <
diff --git a/dts/src/arm/bcm-cygnus.dtsi b/dts/src/arm/bcm-cygnus.dtsi
index bf8c838157..7c957ea06c 100644
--- a/dts/src/arm/bcm-cygnus.dtsi
+++ b/dts/src/arm/bcm-cygnus.dtsi
@@ -55,6 +55,11 @@
/include/ "bcm-cygnus-clock.dtsi"
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
core {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x1000000>;
@@ -119,6 +124,21 @@
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
<0x0301d24c 0x2c>;
+
+ spi_0: spi_0 {
+ function = "spi0";
+ groups = "spi0_grp";
+ };
+
+ spi_1: spi_1 {
+ function = "spi1";
+ groups = "spi1_grp";
+ };
+
+ spi_2: spi_2 {
+ function = "spi2";
+ groups = "spi2_grp";
+ };
};
mailbox: mailbox@03024024 {
@@ -300,6 +320,23 @@
};
};
+ dma0: dma@18018000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x18018000 0x1000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb_clk>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
uart0: serial@18020000 {
compatible = "snps,dw-apb-uart";
reg = <0x18020000 0x100>;
@@ -324,7 +361,7 @@
uart2: serial@18022000 {
compatible = "snps,dw-apb-uart";
- reg = <0x18020000 0x100>;
+ reg = <0x18022000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -344,6 +381,52 @@
status = "disabled";
};
+ spi0: spi@18028000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x18028000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&spi_0>;
+ clocks = <&axi81_clk>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ spi1: spi@18029000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x18029000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&spi_1>;
+ clocks = <&axi81_clk>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ spi2: spi@1802a000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x1802a000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&spi_2>;
+ clocks = <&axi81_clk>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ sdhci0: sdhci@18041000 {
+ compatible = "brcm,sdhci-iproc-cygnus";
+ reg = <0x18041000 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
+ bus-width = <4>;
+ sdhci,auto-cmd12;
+ status = "disabled";
+ };
+
eth0: ethernet@18042000 {
compatible = "brcm,amac";
reg = <0x18042000 0x1000>,
@@ -353,6 +436,16 @@
status = "disabled";
};
+ sdhci1: sdhci@18043000 {
+ compatible = "brcm,sdhci-iproc-cygnus";
+ reg = <0x18043000 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
+ bus-width = <4>;
+ sdhci,auto-cmd12;
+ status = "disabled";
+ };
+
nand: nand@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x18046000 0x600>, <0xf8105408 0x600>,
@@ -366,6 +459,33 @@
brcm,nand-has-wp;
};
+ ehci0: usb@18048000 {
+ compatible = "generic-ehci";
+ reg = <0x18048000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci0: usb@18048800 {
+ compatible = "generic-ohci";
+ reg = <0x18048800 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ v3d: v3d@180a2000 {
+ compatible = "brcm,cygnus-v3d";
+ reg = <0x180a2000 0x1000>;
+ clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
+ clock-names = "v3d_clk";
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ vc4: gpu {
+ compatible = "brcm,cygnus-vc4";
+ };
+
gpio_asiu: gpio@180a5000 {
compatible = "brcm,cygnus-asiu-gpio";
reg = <0x180a5000 0x668>;
@@ -444,19 +564,6 @@
status = "disabled";
};
- v3d: v3d@180a2000 {
- compatible = "brcm,cygnus-v3d";
- reg = <0x180a2000 0x1000>;
- clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
- clock-names = "v3d_clk";
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- vc4: gpu {
- compatible = "brcm,cygnus-vc4";
- };
-
adc: adc@180a6000 {
compatible = "brcm,iproc-static-adc";
#io-channel-cells = <1>;
@@ -467,5 +574,19 @@
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ keypad: keypad@180ac000 {
+ compatible = "brcm,bcm-keypad";
+ reg = <0x180ac000 0x14c>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>;
+ clock-names = "peri_clk";
+ clock-frequency = <31250>;
+ pull-up-enabled;
+ col-debounce-filter-period = <0>;
+ status-debounce-filter-period = <0>;
+ row-output-enabled;
+ status = "disabled";
+ };
};
};
diff --git a/dts/src/arm/bcm-nsp.dtsi b/dts/src/arm/bcm-nsp.dtsi
index 7204d1def2..dff66974fe 100644
--- a/dts/src/arm/bcm-nsp.dtsi
+++ b/dts/src/arm/bcm-nsp.dtsi
@@ -215,6 +215,7 @@
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
sdhci,auto-cmd12;
clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
+ dma-coherent;
status = "disabled";
};
@@ -224,6 +225,7 @@
<0x110000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -233,6 +235,7 @@
<0x111000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -242,6 +245,7 @@
<0x112000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
status = "disabled";
};
@@ -252,6 +256,7 @@
#mbox-cells = <1>;
brcm,rx-status-len = <32>;
brcm,use-bcm-hdr;
+ dma-coherent;
};
nand: nand@26000 {
@@ -297,6 +302,32 @@
#size-cells = <0>;
};
+ xhci: usb@29000 {
+ compatible = "generic-xhci";
+ reg = <0x29000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy>;
+ phy-names = "usb3-phy";
+ dma-coherent;
+ status = "disabled";
+ };
+
+ ehci0: usb@2a000 {
+ compatible = "generic-ehci";
+ reg = <0x2a000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ ohci0: usb@2b000 {
+ compatible = "generic-ohci";
+ reg = <0x2b000 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
crypto@2f000 {
compatible = "brcm,spum-nsp-crypto";
reg = <0x2f000 0x900>;
@@ -321,20 +352,6 @@
status = "disabled";
};
- ehci0: usb@2a000 {
- compatible = "generic-ehci";
- reg = <0x2a000 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- ohci0: usb@2b000 {
- compatible = "generic-ohci";
- reg = <0x2b000 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
rng: rng@33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
@@ -376,6 +393,7 @@
#size-cells = <0>;
interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
+ dma-coherent;
status = "disabled";
};
@@ -446,6 +464,7 @@
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ dma-coherent;
status = "disabled";
sata0: sata-port@0 {
@@ -460,6 +479,15 @@
phy-names = "sata-phy";
};
};
+
+ usb3_phy: usb3-phy@104000 {
+ compatible = "brcm,ns-bx-usb3-phy";
+ reg = <0x104000 0x1000>,
+ <0x032000 0x1000>;
+ reg-names = "dmp", "ccb-mii";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
pcie0: pcie@18012000 {
@@ -483,6 +511,7 @@
*/
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
+ dma-coherent;
status = "disabled";
msi-parent = <&msi0>;
@@ -519,6 +548,7 @@
*/
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
+ dma-coherent;
status = "disabled";
msi-parent = <&msi1>;
@@ -555,6 +585,7 @@
*/
ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
+ dma-coherent;
status = "disabled";
msi-parent = <&msi2>;
diff --git a/dts/src/arm/bcm2835-rpi-a-plus.dts b/dts/src/arm/bcm2835-rpi-a-plus.dts
index d0704540db..9f866491ef 100644
--- a/dts/src/arm/bcm2835-rpi-a-plus.dts
+++ b/dts/src/arm/bcm2835-rpi-a-plus.dts
@@ -99,3 +99,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm2835-rpi-a.dts b/dts/src/arm/bcm2835-rpi-a.dts
index 46d078e290..4b1af06c8d 100644
--- a/dts/src/arm/bcm2835-rpi-a.dts
+++ b/dts/src/arm/bcm2835-rpi-a.dts
@@ -94,3 +94,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm2835-rpi-b-plus.dts b/dts/src/arm/bcm2835-rpi-b-plus.dts
index 432088ebb0..a846f1e781 100644
--- a/dts/src/arm/bcm2835-rpi-b-plus.dts
+++ b/dts/src/arm/bcm2835-rpi-b-plus.dts
@@ -101,3 +101,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm2835-rpi-b-rev2.dts b/dts/src/arm/bcm2835-rpi-b-rev2.dts
index 4133bc2cd9..e860964e39 100644
--- a/dts/src/arm/bcm2835-rpi-b-rev2.dts
+++ b/dts/src/arm/bcm2835-rpi-b-rev2.dts
@@ -94,3 +94,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm2835-rpi-b.dts b/dts/src/arm/bcm2835-rpi-b.dts
index 4d56fe3006..5d77f3f8c4 100644
--- a/dts/src/arm/bcm2835-rpi-b.dts
+++ b/dts/src/arm/bcm2835-rpi-b.dts
@@ -89,3 +89,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm2835-rpi-zero-w.dts b/dts/src/arm/bcm2835-rpi-zero-w.dts
new file mode 100644
index 0000000000..82651c3eb6
--- /dev/null
+++ b/dts/src/arm/bcm2835-rpi-zero-w.dts
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+ compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
+ model = "Raspberry Pi Zero W";
+
+ /* Needed by firmware to properly init UARTs */
+ aliases {
+ uart0 = "/soc/serial@7e201000";
+ uart1 = "/soc/serial@7e215040";
+ serial0 = "/soc/serial@7e201000";
+ serial1 = "/soc/serial@7e215040";
+ };
+
+ leds {
+ act {
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl_on>;
+ reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&gpio {
+ /*
+ * This is based on the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "GPIO0",
+ "GPIO1",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD0",
+ "RXD0",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "SDA0",
+ "SCL0",
+ "NC", /* GPIO30 */
+ "NC", /* GPIO31 */
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "CAM_GPIO1", /* GPIO40 */
+ "WL_ON", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "WIFI_CLK", /* GPIO43 */
+ "CAM_GPIO0", /* GPIO44 */
+ "BT_ON", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED_N",
+ /* Used by SD Card */
+ "SD_CLK_R",
+ "SD_CMD_R",
+ "SD_DATA0_R",
+ "SD_DATA1_R",
+ "SD_DATA2_R",
+ "SD_DATA3_R";
+
+ pinctrl-0 = <&gpioout &alt0>;
+
+ wl_on: wl-on {
+ brcm,pins = <41>;
+ brcm,function = <BCM2835_FSEL_GPIO_OUT>;
+ };
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
+
+&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm2835-rpi-zero.dts b/dts/src/arm/bcm2835-rpi-zero.dts
index 79a20d5209..70362405c5 100644
--- a/dts/src/arm/bcm2835-rpi-zero.dts
+++ b/dts/src/arm/bcm2835-rpi-zero.dts
@@ -103,3 +103,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm2835-rpi.dtsi b/dts/src/arm/bcm2835-rpi.dtsi
index e55b362b9d..e36c392a2b 100644
--- a/dts/src/arm/bcm2835-rpi.dtsi
+++ b/dts/src/arm/bcm2835-rpi.dtsi
@@ -39,7 +39,7 @@
};
alt0: alt0 {
- brcm,pins = <4 5 7 8 9 10 11 14 15>;
+ brcm,pins = <4 5 7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
};
diff --git a/dts/src/arm/bcm2836-rpi-2-b.dts b/dts/src/arm/bcm2836-rpi-2-b.dts
index bf19e8cfb9..e8de41444b 100644
--- a/dts/src/arm/bcm2836-rpi-2-b.dts
+++ b/dts/src/arm/bcm2836-rpi-2-b.dts
@@ -39,3 +39,9 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio14>;
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm2836.dtsi b/dts/src/arm/bcm2836.dtsi
index da3deeb425..2c26d0be8b 100644
--- a/dts/src/arm/bcm2836.dtsi
+++ b/dts/src/arm/bcm2836.dtsi
@@ -36,6 +36,7 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "brcm,bcm2836-smp";
v7_cpu0: cpu@0 {
device_type = "cpu";
diff --git a/dts/src/arm/bcm2837-rpi-3-b.dts b/dts/src/arm/bcm2837-rpi-3-b.dts
index c72a27d908..20725ca487 100644
--- a/dts/src/arm/bcm2837-rpi-3-b.dts
+++ b/dts/src/arm/bcm2837-rpi-3-b.dts
@@ -1 +1,51 @@
-#include "arm64/broadcom/bcm2837-rpi-3-b.dts"
+/dts-v1/;
+#include "bcm2837.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9514.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+ compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
+ model = "Raspberry Pi 3 Model B";
+
+ memory {
+ reg = <0 0x40000000>;
+ };
+
+ leds {
+ act {
+ gpios = <&gpio 47 0>;
+ };
+ };
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
+ status = "okay";
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ status = "okay";
+ bus-width = <4>;
+ non-removable;
+};
+
+/* SDHOST is used to drive the SD card */
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ status = "okay";
+ bus-width = <4>;
+};
diff --git a/dts/src/arm64/broadcom/bcm2837.dtsi b/dts/src/arm/bcm2837.dtsi
index 2d5de6f0f7..bc1cca5cf4 100644
--- a/dts/src/arm64/broadcom/bcm2837.dtsi
+++ b/dts/src/arm/bcm2837.dtsi
@@ -30,6 +30,7 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
cpu0: cpu@0 {
device_type = "cpu";
diff --git a/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts b/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts
index 62e1427b3f..8b64caabaa 100644
--- a/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts
@@ -52,6 +52,10 @@
usb {
label = "bcm53xx:blue:usb";
gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
+ <&xhci_port1>, <&ohci_port2>,
+ <&ehci_port2>;
+ linux,default-trigger = "usbport";
};
power0 {
diff --git a/dts/src/arm/bcm4708-netgear-r6250.dts b/dts/src/arm/bcm4708-netgear-r6250.dts
index a5647efe41..d7c34fa72b 100644
--- a/dts/src/arm/bcm4708-netgear-r6250.dts
+++ b/dts/src/arm/bcm4708-netgear-r6250.dts
@@ -48,6 +48,9 @@
usb {
label = "bcm53xx:blue:usb";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
+ <&xhci_port1>;
+ linux,default-trigger = "usbport";
};
wireless {
diff --git a/dts/src/arm/bcm4708-smartrg-sr400ac.dts b/dts/src/arm/bcm4708-smartrg-sr400ac.dts
index 19ee924d7d..83a4c60bb4 100644
--- a/dts/src/arm/bcm4708-smartrg-sr400ac.dts
+++ b/dts/src/arm/bcm4708-smartrg-sr400ac.dts
@@ -42,16 +42,22 @@
usb2 {
label = "bcm53xx:white:usb2";
gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port2>, <&ehci_port2>;
+ linux,default-trigger = "usbport";
};
usb3-white {
label = "bcm53xx:white:usb3";
gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&xhci_port1>;
+ linux,default-trigger = "usbport";
};
usb3-green {
label = "bcm53xx:green:usb3";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
+ linux,default-trigger = "usbport";
};
wps {
diff --git a/dts/src/arm/bcm47081-tplink-archer-c5-v2.dts b/dts/src/arm/bcm47081-tplink-archer-c5-v2.dts
index a854a5174b..3ed8de42cb 100644
--- a/dts/src/arm/bcm47081-tplink-archer-c5-v2.dts
+++ b/dts/src/arm/bcm47081-tplink-archer-c5-v2.dts
@@ -36,6 +36,8 @@
usb2-port1 {
label = "bcm53xx:green:usb2-port1";
gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
+ linux,default-trigger = "usbport";
};
power {
@@ -67,6 +69,8 @@
usb2-port2 {
label = "bcm53xx:green:usb2-port2";
gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port2>, <&ehci_port2>;
+ linux,default-trigger = "usbport";
};
};
diff --git a/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts b/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts
index 97aa5d59a1..ec4a50e440 100644
--- a/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts
+++ b/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts
@@ -46,11 +46,16 @@
usb3 {
label = "bcm53xx:blue:usb3";
gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
+ <&xhci_port1>;
+ linux,default-trigger = "usbport";
};
usb2 {
label = "bcm53xx:blue:usb2";
gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port2>, <&ehci_port2>;
+ linux,default-trigger = "usbport";
};
wan-blue {
diff --git a/dts/src/arm/bcm47094-dlink-dir-885l.dts b/dts/src/arm/bcm47094-dlink-dir-885l.dts
index 51b0641b5f..7cc7d344fe 100644
--- a/dts/src/arm/bcm47094-dlink-dir-885l.dts
+++ b/dts/src/arm/bcm47094-dlink-dir-885l.dts
@@ -71,6 +71,9 @@
usb3-white {
label = "bcm53xx:white:usb3";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
+ <&xhci_port1>;
+ linux,default-trigger = "usbport";
};
2ghz {
diff --git a/dts/src/arm/bcm47094-luxul-xwr-3100.dts b/dts/src/arm/bcm47094-luxul-xwr-3100.dts
index 5f8621d00c..bc1d1e10d4 100644
--- a/dts/src/arm/bcm47094-luxul-xwr-3100.dts
+++ b/dts/src/arm/bcm47094-luxul-xwr-3100.dts
@@ -59,6 +59,9 @@
usb3 {
label = "bcm53xx:green:usb3";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
+ <&xhci_port1>;
+ linux,default-trigger = "usbport";
};
status {
diff --git a/dts/src/arm/bcm47189-tenda-ac9.dts b/dts/src/arm/bcm47189-tenda-ac9.dts
index 34417dac1c..19e61b5b06 100644
--- a/dts/src/arm/bcm47189-tenda-ac9.dts
+++ b/dts/src/arm/bcm47189-tenda-ac9.dts
@@ -26,6 +26,8 @@
usb {
label = "bcm53xx:blue:usb";
gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
+ linux,default-trigger = "usbport";
};
wps {
diff --git a/dts/src/arm/bcm5301x.dtsi b/dts/src/arm/bcm5301x.dtsi
index 98647d22b2..045b9bb857 100644
--- a/dts/src/arm/bcm5301x.dtsi
+++ b/dts/src/arm/bcm5301x.dtsi
@@ -272,6 +272,19 @@
reg = <0x00021000 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ehci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ ehci_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
};
ohci: ohci@22000 {
@@ -280,6 +293,19 @@
compatible = "generic-ohci";
reg = <0x00022000 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ohci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ ohci_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
};
};
@@ -300,6 +326,14 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy>;
phy-names = "usb";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ xhci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
};
};
diff --git a/dts/src/arm/bcm53573.dtsi b/dts/src/arm/bcm53573.dtsi
index eae623f764..c698a565b8 100644
--- a/dts/src/arm/bcm53573.dtsi
+++ b/dts/src/arm/bcm53573.dtsi
@@ -138,10 +138,12 @@
ehci_port1: port@1 {
reg = <1>;
+ #trigger-source-cells = <0>;
};
ehci_port2: port@2 {
reg = <2>;
+ #trigger-source-cells = <0>;
};
};
@@ -158,10 +160,12 @@
ohci_port1: port@1 {
reg = <1>;
+ #trigger-source-cells = <0>;
};
ohci_port2: port@2 {
reg = <2>;
+ #trigger-source-cells = <0>;
};
};
};
diff --git a/dts/src/arm/bcm911360_entphn.dts b/dts/src/arm/bcm911360_entphn.dts
index 000f5f1921..53f990defd 100644
--- a/dts/src/arm/bcm911360_entphn.dts
+++ b/dts/src/arm/bcm911360_entphn.dts
@@ -39,9 +39,12 @@
model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
compatible = "brcm,bcm11360", "brcm,cygnus";
+ aliases {
+ serial0 = &uart3;
+ };
+
chosen {
- stdout-path = &uart3;
- bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
gpio_keys {
diff --git a/dts/src/arm/bcm947189acdbmr.dts b/dts/src/arm/bcm947189acdbmr.dts
new file mode 100644
index 0000000000..ef263412fe
--- /dev/null
+++ b/dts/src/arm/bcm947189acdbmr.dts
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2017 Broadcom
+ * Author: Florian Fainelli <f.fainelli@gmail.com>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm53573.dtsi"
+
+/ {
+ compatible = "brcm,bcm947189acdbmr", "brcm,bcm47189", "brcm,bcm53573";
+ model = "Broadcom BCM947189ACDBMR";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ wps {
+ label = "bcm53xx:blue:wps";
+ gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ 5ghz {
+ label = "bcm53xx:blue:5ghz";
+ gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ 2ghz {
+ label = "bcm53xx:blue:2ghz";
+ gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ spi {
+ compatible = "spi-gpio";
+ num-chipselects = <1>;
+ gpio-sck = <&chipcommon 21 0>;
+ gpio-miso = <&chipcommon 22 0>;
+ gpio-mosi = <&chipcommon 23 0>;
+ cs-gpios = <&chipcommon 24 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* External BCM6802 MoCA chip is connected */
+ };
+};
+
+&pcie0 {
+ ranges = <0x00000000 0 0 0 0 0x00100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bridge@0,0,0 {
+ reg = <0x0000 0 0 0 0>;
+ ranges = <0x00000000 0 0 0 0 0 0 0x00100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ wifi@0,1,0 {
+ reg = <0x0000 0 0 0 0>;
+ ranges = <0x00000000 0 0 0 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+};
+
+&usb2 {
+ vcc-gpio = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
+};
diff --git a/dts/src/arm/bcm958522er.dts b/dts/src/arm/bcm958522er.dts
index f5c42962c2..f9dd342cc2 100644
--- a/dts/src/arm/bcm958522er.dts
+++ b/dts/src/arm/bcm958522er.dts
@@ -170,3 +170,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958525er.dts b/dts/src/arm/bcm958525er.dts
index efcb1f67bd..374508a9cf 100644
--- a/dts/src/arm/bcm958525er.dts
+++ b/dts/src/arm/bcm958525er.dts
@@ -182,3 +182,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958525xmc.dts b/dts/src/arm/bcm958525xmc.dts
index b335ce02e3..403250c5ad 100644
--- a/dts/src/arm/bcm958525xmc.dts
+++ b/dts/src/arm/bcm958525xmc.dts
@@ -202,3 +202,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958622hr.dts b/dts/src/arm/bcm958622hr.dts
index 16ab2d82a1..fd8b8c689f 100644
--- a/dts/src/arm/bcm958622hr.dts
+++ b/dts/src/arm/bcm958622hr.dts
@@ -219,3 +219,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958623hr.dts b/dts/src/arm/bcm958623hr.dts
index 9b921c6aa8..3bc50849d0 100644
--- a/dts/src/arm/bcm958623hr.dts
+++ b/dts/src/arm/bcm958623hr.dts
@@ -227,3 +227,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958625hr.dts b/dts/src/arm/bcm958625hr.dts
index 006b08e41a..d94d14b3c7 100644
--- a/dts/src/arm/bcm958625hr.dts
+++ b/dts/src/arm/bcm958625hr.dts
@@ -229,3 +229,11 @@
&uart0 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958625k.dts b/dts/src/arm/bcm958625k.dts
index 64740f85cf..2cf2392483 100644
--- a/dts/src/arm/bcm958625k.dts
+++ b/dts/src/arm/bcm958625k.dts
@@ -264,3 +264,11 @@
&uart1 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/dts/src/arm/da850-lego-ev3.dts b/dts/src/arm/da850-lego-ev3.dts
index 45983c04a8..413dbd5d9f 100644
--- a/dts/src/arm/da850-lego-ev3.dts
+++ b/dts/src/arm/da850-lego-ev3.dts
@@ -249,6 +249,15 @@
0x4c 0x00000080 0x000000f0
>;
};
+
+ ev3_lcd_pins: pinmux_lcd {
+ pinctrl-single,bits = <
+ /* SIMO, GP2[11], GP2[12], CLK */
+ 0x14 0x00188100 0x00ffff00
+ /* GP5[0] */
+ 0x30 0x80000000 0xf0000000
+ >;
+ };
};
&pinconf {
@@ -357,6 +366,21 @@
};
};
+&spi1 {
+ status = "okay";
+ pinctrl-0 = <&ev3_lcd_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+
+ display@0{
+ compatible = "lego,ev3-lcd";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
+ };
+};
+
&ehrpwm0 {
status = "okay";
};
diff --git a/dts/src/arm/dove-d3plug.dts b/dts/src/arm/dove-d3plug.dts
index f5f59bb5a5..e88ff83f1d 100644
--- a/dts/src/arm/dove-d3plug.dts
+++ b/dts/src/arm/dove-d3plug.dts
@@ -88,7 +88,7 @@
&pcie {
status = "okay";
/* Fresco Logic USB3.0 xHCI controller */
- pcie-port@0 {
+ pcie@1 {
status = "okay";
reset-gpios = <&gpio0 26 1>;
reset-delay-us = <20000>;
@@ -96,7 +96,7 @@
pinctrl-names = "default";
};
/* Mini-PCIe slot */
- pcie-port@1 {
+ pcie@2 {
status = "okay";
reset-gpios = <&gpio0 25 1>;
};
diff --git a/dts/src/arm/dove.dtsi b/dts/src/arm/dove.dtsi
index 698d58cea2..1475d3672e 100644
--- a/dts/src/arm/dove.dtsi
+++ b/dts/src/arm/dove.dtsi
@@ -89,7 +89,7 @@
MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
- pcie: pcie-controller {
+ pcie: pcie {
compatible = "marvell,dove-pcie";
status = "disabled";
device_type = "pci";
@@ -106,7 +106,7 @@
0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
- pcie0: pcie-port@0 {
+ pcie0: pcie@1 {
device_type = "pci";
status = "disabled";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
@@ -118,13 +118,14 @@
#size-cells = <2>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 16>;
};
- pcie1: pcie-port@1 {
+ pcie1: pcie@2 {
device_type = "pci";
status = "disabled";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
@@ -136,6 +137,7 @@
#size-cells = <2>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
diff --git a/dts/src/arm/dra7-evm-common.dtsi b/dts/src/arm/dra7-evm-common.dtsi
new file mode 100644
index 0000000000..343e95f9a0
--- /dev/null
+++ b/dts/src/arm/dra7-evm-common.dtsi
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Out",
+ "Microphone", "Mic Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ sound0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ system-clock-frequency = <5644800>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&atl_clkin2_ck>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "dra7:usr1";
+ gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led1 {
+ label = "dra7:usr2";
+ gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led2 {
+ label = "dra7:usr3";
+ gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "dra7:usr4";
+ gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ USER1 {
+ label = "btnUser1";
+ linux,code = <BTN_0>;
+ gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
+ };
+
+ USER2 {
+ label = "btnUser2";
+ linux,code = <BTN_1>;
+ gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&mcspi1 {
+ status = "okay";
+};
+
+&mcspi2 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+ interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <&dra7_pmx_core 0x3e0>;
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+
+ spi-max-frequency = <76800000>;
+ m25p80@0 {
+ compatible = "s25fl256s1";
+ spi-max-frequency = <76800000>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+ * The ROM checks the first four physical blocks
+ * for a valid file to boot and the flash here is
+ * 64KiB block size.
+ */
+ partition@0 {
+ label = "QSPI.SPL";
+ reg = <0x00000000 0x000010000>;
+ };
+ partition@1 {
+ label = "QSPI.SPL.backup1";
+ reg = <0x00010000 0x00010000>;
+ };
+ partition@2 {
+ label = "QSPI.SPL.backup2";
+ reg = <0x00020000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.SPL.backup3";
+ reg = <0x00030000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.u-boot";
+ reg = <0x00040000 0x00100000>;
+ };
+ partition@5 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x00140000 0x00080000>;
+ };
+ partition@6 {
+ label = "QSPI.u-boot-env";
+ reg = <0x001c0000 0x00010000>;
+ };
+ partition@7 {
+ label = "QSPI.u-boot-env.backup1";
+ reg = <0x001d0000 0x0010000>;
+ };
+ partition@8 {
+ label = "QSPI.kernel";
+ reg = <0x001e0000 0x0800000>;
+ };
+ partition@9 {
+ label = "QSPI.file-system";
+ reg = <0x009e0000 0x01620000>;
+ };
+ };
+};
+
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&usb1 {
+ dr_mode = "otg";
+ extcon = <&extcon_usb1>;
+};
+
+&usb2 {
+ dr_mode = "host";
+};
+
+&atl {
+ assigned-clocks = <&abe_dpll_sys_clk_mux>,
+ <&atl_gfclk_mux>,
+ <&dpll_abe_ck>,
+ <&dpll_abe_m2x2_ck>,
+ <&atl_clkin2_ck>;
+ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
+ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
+
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&atl_clkin2_ck>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
diff --git a/dts/src/arm/dra7-evm.dts b/dts/src/arm/dra7-evm.dts
index f47fc4daf0..aa426dabb6 100644
--- a/dts/src/arm/dra7-evm.dts
+++ b/dts/src/arm/dra7-evm.dts
@@ -8,9 +8,8 @@
/dts-v1/;
#include "dra74x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clk/ti-dra7-atl.h>
-#include <dt-bindings/input/input.h>
+#include "dra7-evm-common.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
/ {
model = "TI DRA742";
@@ -21,8 +20,12 @@
reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
};
- chosen {
- stdout-path = &uart1;
+ evm_1v8_sw: fixedregulator-evm_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_1v8";
+ vin-supply = <&smps9_reg>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
evm_3v3_sd: fixedregulator-sd {
@@ -51,11 +54,6 @@
regulator-max-microvolt = <1800000>;
};
- extcon_usb1: extcon_usb1 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
- };
-
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
@@ -73,85 +71,6 @@
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
- sound0: sound0 {
- compatible = "simple-audio-card";
- simple-audio-card,name = "DRA7xx-EVM";
- simple-audio-card,widgets =
- "Headphone", "Headphone Jack",
- "Line", "Line Out",
- "Microphone", "Mic Jack",
- "Line", "Line In";
- simple-audio-card,routing =
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT",
- "Line Out", "LLOUT",
- "Line Out", "RLOUT",
- "MIC3L", "Mic Jack",
- "MIC3R", "Mic Jack",
- "Mic Jack", "Mic Bias",
- "LINE1L", "Line In",
- "LINE1R", "Line In";
- simple-audio-card,format = "dsp_b";
- simple-audio-card,bitclock-master = <&sound0_master>;
- simple-audio-card,frame-master = <&sound0_master>;
- simple-audio-card,bitclock-inversion;
-
- sound0_master: simple-audio-card,cpu {
- sound-dai = <&mcasp3>;
- system-clock-frequency = <5644800>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&tlv320aic3106>;
- clocks = <&atl_clkin2_ck>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led0 {
- label = "dra7:usr1";
- gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led1 {
- label = "dra7:usr2";
- gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led2 {
- label = "dra7:usr3";
- gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led3 {
- label = "dra7:usr4";
- gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- autorepeat;
-
- USER1 {
- label = "btnUser1";
- linux,code = <BTN_0>;
- gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
- };
-
- USER2 {
- label = "btnUser2";
- linux,code = <BTN_1>;
- gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
- };
- };
};
&dra7_pmx_core {
@@ -406,137 +325,49 @@
};
};
-&i2c3 {
- status = "okay";
- clock-frequency = <400000>;
-};
-
-&mcspi1 {
- status = "okay";
-};
-
-&mcspi2 {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
- interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <&dra7_pmx_core 0x3e0>;
-};
-
-&uart2 {
- status = "okay";
-};
-
-&uart3 {
- status = "okay";
-};
-
&mmc1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&evm_3v3_sd>;
- vmmc_aux-supply = <&ldo1_reg>;
+ vqmmc-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
+ pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
+ pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_default>;
- vmmc-supply = <&evm_3v3_sw>;
+ vmmc-supply = <&evm_1v8_sw>;
bus-width = <8>;
+ pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
+ pinctrl-3 = <&mmc2_pins_ddr_rev20>;
+ pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
+ pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
};
&cpu0 {
cpu0-supply = <&smps123_reg>;
};
-&qspi {
- status = "okay";
-
- spi-max-frequency = <76800000>;
- m25p80@0 {
- compatible = "s25fl256s1";
- spi-max-frequency = <76800000>;
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* MTD partition table.
- * The ROM checks the first four physical blocks
- * for a valid file to boot and the flash here is
- * 64KiB block size.
- */
- partition@0 {
- label = "QSPI.SPL";
- reg = <0x00000000 0x000010000>;
- };
- partition@1 {
- label = "QSPI.SPL.backup1";
- reg = <0x00010000 0x00010000>;
- };
- partition@2 {
- label = "QSPI.SPL.backup2";
- reg = <0x00020000 0x00010000>;
- };
- partition@3 {
- label = "QSPI.SPL.backup3";
- reg = <0x00030000 0x00010000>;
- };
- partition@4 {
- label = "QSPI.u-boot";
- reg = <0x00040000 0x00100000>;
- };
- partition@5 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x00140000 0x00080000>;
- };
- partition@6 {
- label = "QSPI.u-boot-env";
- reg = <0x001c0000 0x00010000>;
- };
- partition@7 {
- label = "QSPI.u-boot-env.backup1";
- reg = <0x001d0000 0x0010000>;
- };
- partition@8 {
- label = "QSPI.kernel";
- reg = <0x001e0000 0x0800000>;
- };
- partition@9 {
- label = "QSPI.file-system";
- reg = <0x009e0000 0x01620000>;
- };
- };
-};
-
-&omap_dwc3_1 {
- extcon = <&extcon_usb1>;
-};
-
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
-&usb1 {
- dr_mode = "otg";
- extcon = <&extcon_usb1>;
-};
-
-&usb2 {
- dr_mode = "host";
-};
-
&elm {
status = "okay";
};
@@ -556,6 +387,7 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
@@ -666,57 +498,6 @@
pinctrl-2 = <&dcan1_pins_default>;
};
-&atl {
- assigned-clocks = <&abe_dpll_sys_clk_mux>,
- <&atl_gfclk_mux>,
- <&dpll_abe_ck>,
- <&dpll_abe_m2x2_ck>,
- <&atl_clkin2_ck>;
- assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
- assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
-
- status = "okay";
-
- atl2 {
- bws = <DRA7_ATL_WS_MCASP2_FSX>;
- aws = <DRA7_ATL_WS_MCASP3_FSX>;
- };
-};
-
-&mcasp3 {
- #sound-dai-cells = <0>;
-
- assigned-clocks = <&mcasp3_ahclkx_mux>;
- assigned-clock-parents = <&atl_clkin2_ck>;
-
- status = "okay";
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- /* 4 serializer */
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 2 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
-};
-
-&mailbox5 {
+&pcie1_rc {
status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
-};
-
-&mailbox6 {
- status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
- status = "okay";
- };
};
diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi
index 0f0f6f58bd..02a136a466 100644
--- a/dts/src/arm/dra7.dtsi
+++ b/dts/src/arm/dra7.dtsi
@@ -196,6 +196,7 @@
scm_conf1: scm_conf@1c04 {
compatible = "syscon";
reg = <0x1c04 0x0020>;
+ #syscon-cells = <2>;
};
scm_conf_pcie: scm_conf@1c24 {
@@ -287,7 +288,11 @@
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
- pcie1: pcie@51000000 {
+ /**
+ * To enable PCI endpoint mode, disable the pcie1_rc
+ * node and enable pcie1_ep mode.
+ */
+ pcie1_rc: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
@@ -309,12 +314,28 @@
<0 0 0 2 &pcie1_intc 2>,
<0 0 0 3 &pcie1_intc 3>,
<0 0 0 4 &pcie1_intc 4>;
+ status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
+
+ pcie1_ep: pcie_ep@51000000 {
+ compatible = "ti,dra7-pcie-ep";
+ reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
+ reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
+ interrupts = <0 232 0x4>;
+ num-lanes = <1>;
+ num-ib-windows = <4>;
+ num-ob-windows = <16>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy0";
+ ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+ status = "disabled";
+ };
};
axi@1 {
@@ -418,6 +439,14 @@
reg = <0x40d00000 0x100>;
};
+ dra7_iodelay_core: padconf@4844a000 {
+ compatible = "ti,dra7-iodelay";
+ reg = <0x4844a000 0x0d1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <2>;
+ };
+
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
@@ -1037,6 +1066,7 @@
dma-names = "tx", "rx";
status = "disabled";
pbias-supply = <&pbias_mmc_reg>;
+ max-frequency = <192000000>;
};
mmc2: mmc@480b4000 {
@@ -1048,6 +1078,7 @@
dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
dma-names = "tx", "rx";
status = "disabled";
+ max-frequency = <192000000>;
};
mmc3: mmc@480ad000 {
@@ -1059,6 +1090,8 @@
dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
dma-names = "tx", "rx";
status = "disabled";
+ /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
+ max-frequency = <64000000>;
};
mmc4: mmc@480d1000 {
@@ -1070,6 +1103,7 @@
dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
dma-names = "tx", "rx";
status = "disabled";
+ max-frequency = <192000000>;
};
mmu0_dsp1: mmu@40d01000 {
diff --git a/dts/src/arm/dra71-evm.dts b/dts/src/arm/dra71-evm.dts
index a6298eb569..41c9132eb5 100644
--- a/dts/src/arm/dra71-evm.dts
+++ b/dts/src/arm/dra71-evm.dts
@@ -7,6 +7,7 @@
*/
#include "dra72-evm-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -32,6 +33,16 @@
3000000 0x1>;
};
+ evm_1v8_sw: fixedregulator-evm_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&lp8732_buck0_reg>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
poweroff: gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
@@ -162,7 +173,24 @@
};
&mmc1 {
- vmmc_aux-supply = <&vpo_sd_1v8_3v3>;
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+ vqmmc-supply = <&vpo_sd_1v8_3v3>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
+ vmmc-supply = <&evm_1v8_sw>;
};
&mac {
@@ -191,6 +219,7 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@3 {
@@ -199,6 +228,7 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
diff --git a/dts/src/arm/dra72-evm-common.dtsi b/dts/src/arm/dra72-evm-common.dtsi
index 85780549bc..2e485a13df 100644
--- a/dts/src/arm/dra72-evm-common.dtsi
+++ b/dts/src/arm/dra72-evm-common.dtsi
@@ -311,6 +311,7 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
@@ -419,8 +420,6 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
-
- vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;
@@ -564,3 +563,7 @@
status = "okay";
};
};
+
+&pcie1_rc {
+ status = "okay";
+};
diff --git a/dts/src/arm/dra72-evm-revc.dts b/dts/src/arm/dra72-evm-revc.dts
index 3ecac56bf5..bf588d0072 100644
--- a/dts/src/arm/dra72-evm-revc.dts
+++ b/dts/src/arm/dra72-evm-revc.dts
@@ -6,6 +6,7 @@
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -15,6 +16,16 @@
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
};
+
+ evm_1v8_sw: fixedregulator-evm_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&smps4_reg>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&i2c1 {
@@ -70,6 +81,7 @@
ti,min-output-impedance;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@3 {
@@ -80,5 +92,27 @@
ti,min-output-impedance;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
+
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+ vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
+ vmmc-supply = <&evm_1v8_sw>;
+};
diff --git a/dts/src/arm/dra72-evm-tps65917.dtsi b/dts/src/arm/dra72-evm-tps65917.dtsi
index e6df676886..57bfe5caf5 100644
--- a/dts/src/arm/dra72-evm-tps65917.dtsi
+++ b/dts/src/arm/dra72-evm-tps65917.dtsi
@@ -146,5 +146,5 @@
};
&mmc1 {
- vmmc_aux-supply = <&ldo1_reg>;
+ vqmmc-supply = <&ldo1_reg>;
};
diff --git a/dts/src/arm/dra72-evm.dts b/dts/src/arm/dra72-evm.dts
index cd9c4ff126..c572693b16 100644
--- a/dts/src/arm/dra72-evm.dts
+++ b/dts/src/arm/dra72-evm.dts
@@ -6,6 +6,7 @@
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
/ {
model = "TI DRA722";
@@ -13,6 +14,16 @@
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
+
+ evm_1v8_sw: fixedregulator-evm_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&smps4_reg>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&i2c1 {
@@ -43,3 +54,24 @@
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
};
+
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
+ vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev10>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
+ vmmc-supply = <&evm_1v8_sw>;
+};
diff --git a/dts/src/arm/dra72x-mmc-iodelay.dtsi b/dts/src/arm/dra72x-mmc-iodelay.dtsi
new file mode 100644
index 0000000000..088013c6dc
--- /dev/null
+++ b/dts/src/arm/dra72x-mmc-iodelay.dtsi
@@ -0,0 +1,350 @@
+/*
+ * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ * Datamanual revision that was used should be updated in comment below.
+ * If there is no update to datamanual, do not update the values. If you
+ * need to use values different from that recommended by the datamanual
+ * for your design, then you should consider adding values to the device-
+ * -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ * we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0,
+ * 'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ * to curb naming creativity and achieve consistency.
+ * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and
+ * 'dra72_' tag to entries. Both the new and old entries should gain a tag.
+ *
+ * Datamanual Revisions:
+ *
+ * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017
+ * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017
+ * DRA71x : SPRS960B, Revised February 2017
+ */
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr12: mmc1_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_hs: mmc1_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr25: mmc1_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
+ DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr104: mmc1_pins_sdr104 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs: mmc2_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ >;
+ };
+
+ mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs200: mmc2_pins_hs200 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+
+ /* Corresponds to MMC1_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */
+ 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
+ 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
+ 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
+ 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
+ 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC1_MANUAL2 in datamanual */
+ mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC1_MANUAL2 in datamanual */
+ mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC2_MANUAL1 in datamanual */
+ mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf {
+ pinctrl-pin-array = <
+ 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */
+ 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */
+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */
+ 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */
+ 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */
+ 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */
+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
+ 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
+ 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */
+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
+ 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC2_MANUAL3 in datamanual */
+ mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf {
+ pinctrl-pin-array = <
+ 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */
+ 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */
+ 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC2_MANUAL3 in datamanual */
+ mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
+ pinctrl-pin-array = <
+ 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */
+ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */
+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ >;
+ };
+};
diff --git a/dts/src/arm/dra74x-mmc-iodelay.dtsi b/dts/src/arm/dra74x-mmc-iodelay.dtsi
new file mode 100644
index 0000000000..28ebb4eb88
--- /dev/null
+++ b/dts/src/arm/dra74x-mmc-iodelay.dtsi
@@ -0,0 +1,647 @@
+/*
+ * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ * Datamanual revision that was used should be updated in comment below.
+ * If there is no update to datamanual, do not update the values. If you
+ * need to use values different from that recommended by the datamanual
+ * for your design, then you should consider adding values to the device-
+ * -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ * we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
+ * 'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ * to curb naming creativity and achieve consistency.
+ *
+ * Datamanual Revisions:
+ *
+ * AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
+ * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
+ *
+ */
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr12: mmc1_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_hs: mmc1_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr25: mmc1_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50: mmc1_pins_ddr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr104: mmc1_pins_sdr104 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs: mmc2_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs200: mmc2_pins_hs200 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc4_pins_default: mmc4_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+
+ mmc4_pins_hs: mmc4_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+
+ mmc3_pins_default: mmc3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_hs: mmc3_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_sdr12: mmc3_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_sdr25: mmc3_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_sdr50: mmc3_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc4_pins_sdr12: mmc4_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+
+ mmc4_pins_sdr25: mmc4_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+
+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */
+ 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */
+ 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
+ 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+ mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+ mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+ mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf {
+ pinctrl-pin-array = <
+ 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */
+ 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+ mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
+ pinctrl-pin-array = <
+ 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */
+ 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */
+ mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf {
+ pinctrl-pin-array = <
+ 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
+ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
+ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
+ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
+ 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
+ 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
+ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */
+ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */
+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
+ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */
+ mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {
+ pinctrl-pin-array = <
+ 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */
+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */
+ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */
+ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */
+ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */
+ 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
+ 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */
+ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */
+ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */
+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
+ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL1 in datamanual */
+ mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL1 in datamanual */
+ mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
+ mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
+ mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_MANUAL1 in datamanual */
+ mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_MANUAL1 in datamanual */
+ mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+};
diff --git a/dts/src/arm/dra76-evm.dts b/dts/src/arm/dra76-evm.dts
new file mode 100644
index 0000000000..b024a65c6e
--- /dev/null
+++ b/dts/src/arm/dra76-evm.dts
@@ -0,0 +1,423 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra76x.dtsi"
+#include "dra7-evm-common.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "TI DRA762 EVM";
+ compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ vsys_12v0: fixedregulator-vsys12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: fixedregulator-vsys5v0 {
+ /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vsys_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vio_3v3: fixedregulator-vio_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vio_3v3_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vio_3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vio_3v3>;
+ enable-active-high;
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ vio_1v8: fixedregulator-vio_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&smps5_reg>;
+ };
+
+ vtt_fixed: fixedregulator-vtt {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt_fixed";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&vio_3v3>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps65917: tps65917@58 {
+ compatible = "ti,tps65917";
+ reg = <0x58>;
+ ti,system-power-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ smps12-in-supply = <&vsys_3v3>;
+ smps3-in-supply = <&vsys_3v3>;
+ smps4-in-supply = <&vsys_3v3>;
+ smps5-in-supply = <&vsys_3v3>;
+ ldo1-in-supply = <&vsys_3v3>;
+ ldo2-in-supply = <&vsys_3v3>;
+ ldo3-in-supply = <&vsys_5v0>;
+ ldo4-in-supply = <&vsys_5v0>;
+ ldo5-in-supply = <&vsys_3v3>;
+
+ tps65917_regulators: regulators {
+ smps12_reg: smps12 {
+ /* VDD_DSPEVE */
+ regulator-name = "smps12";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_CORE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDD_IVA */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDDS1V8 */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> VDA_PHY1_1V8 */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-bypass;
+ };
+
+ ldo2_reg: ldo2 {
+ /* LDO2_OUT --> VDA_PHY2_1V8 */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-bypass;
+ regulator-always-on;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDA_USB_3V3 */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDD_SDIO_DV */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+ };
+
+ lp87565: lp87565@60 {
+ compatible = "ti,lp87565-q1";
+ reg = <0x60>;
+
+ buck10-in-supply =<&vsys_3v3>;
+ buck23-in-supply =<&vsys_3v3>;
+
+ regulators: regulators {
+ buck10_reg: buck10 {
+ /*VDD_MPU*/
+ regulator-name = "buck10";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck23_reg: buck23 {
+ /* VDD_GPU*/
+ regulator-name = "buck23";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ pcf_lcd: pcf8757@20 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ pcf_gpio_21: pcf8757@21 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcf_hdmi: pcf8575@26 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ p1 {
+ /* vin6_sel_s0: high: VIN6, low: audio */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "vin6_sel_s0";
+ };
+ };
+
+ tlv320aic3106: tlv320aic3106@19 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x19>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&vio_3v3>;
+ IOVDD-supply = <&vio_3v3>;
+ DRVDD-supply = <&vio_3v3>;
+ DVDD-supply = <&aic_dvdd>;
+ };
+};
+
+&cpu0 {
+ vdd-supply = <&buck10_reg>;
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vio_3v3_sd>;
+ vmmc_aux-supply = <&ldo4_reg>;
+ bus-width = <4>;
+ /*
+ * SDCD signal is not being used here - using the fact that GPIO mode
+ * is always hardwired.
+ */
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&vio_1v8>;
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_default>;
+};
+
+/* No RTC on this device */
+&rtc {
+ status = "disabled";
+};
+
+&mac {
+ status = "okay";
+
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ dp83867_0: ethernet-phy@2 {
+ reg = <2>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+
+ dp83867_1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldo3_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldo3_reg>;
+};
+
+&qspi {
+ spi-max-frequency = <96000000>;
+ m25p80@0 {
+ spi-max-frequency = <96000000>;
+ };
+};
diff --git a/dts/src/arm/dra76x.dtsi b/dts/src/arm/dra76x.dtsi
new file mode 100644
index 0000000000..1c88c581ff
--- /dev/null
+++ b/dts/src/arm/dra76x.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "dra74x.dtsi"
+
+/ {
+ compatible = "ti,dra762", "ti,dra7";
+
+};
+
+/* MCAN interrupts are hard-wired to irqs 67, 68 */
+&crossbar_mpu {
+ ti,irqs-skip = <10 67 68 133 139 140>;
+};
diff --git a/dts/src/arm/exynos3250-artik5-eval.dts b/dts/src/arm/exynos3250-artik5-eval.dts
index 4bd2ee8712..4cbfa09c6c 100644
--- a/dts/src/arm/exynos3250-artik5-eval.dts
+++ b/dts/src/arm/exynos3250-artik5-eval.dts
@@ -22,7 +22,6 @@
};
&mshc_2 {
- num-slots = <1>;
cap-sd-highspeed;
disable-wp;
vqmmc-supply = <&ldo3_reg>;
diff --git a/dts/src/arm/exynos3250-artik5.dtsi b/dts/src/arm/exynos3250-artik5.dtsi
index 59c89d7662..639c2e605f 100644
--- a/dts/src/arm/exynos3250-artik5.dtsi
+++ b/dts/src/arm/exynos3250-artik5.dtsi
@@ -304,7 +304,6 @@
};
&mshc_0 {
- num-slots = <1>;
non-removable;
cap-mmc-highspeed;
card-detect-delay = <200>;
diff --git a/dts/src/arm/exynos3250-monk.dts b/dts/src/arm/exynos3250-monk.dts
index accee81da2..bbdfcbc6e7 100644
--- a/dts/src/arm/exynos3250-monk.dts
+++ b/dts/src/arm/exynos3250-monk.dts
@@ -426,7 +426,6 @@
&mshc_0 {
#address-cells = <1>;
#size-cells = <0>;
- num-slots = <1>;
broken-cd;
non-removable;
cap-mmc-highspeed;
diff --git a/dts/src/arm/exynos3250-rinato.dts b/dts/src/arm/exynos3250-rinato.dts
index 443e0c98dc..0b45467d77 100644
--- a/dts/src/arm/exynos3250-rinato.dts
+++ b/dts/src/arm/exynos3250-rinato.dts
@@ -220,21 +220,6 @@
samsung,pll-clock-frequency = <24000000>;
status = "okay";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
-
- dsi_out: endpoint {
- remote-endpoint = <&dsi_in>;
- samsung,burst-clock-frequency = <250000000>;
- samsung,esc-clock-frequency = <20000000>;
- };
- };
- };
-
panel@0 {
compatible = "samsung,s6e63j0x03";
reg = <0>;
@@ -264,12 +249,6 @@
vsync-len = <2>;
};
};
-
- port {
- dsi_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
};
};
@@ -642,7 +621,6 @@
&mshc_0 {
#address-cells = <1>;
#size-cells = <0>;
- num-slots = <1>;
broken-cd;
non-removable;
cap-mmc-highspeed;
diff --git a/dts/src/arm/exynos4210-trats.dts b/dts/src/arm/exynos4210-trats.dts
index 645feffb92..7b6ab72651 100644
--- a/dts/src/arm/exynos4210-trats.dts
+++ b/dts/src/arm/exynos4210-trats.dts
@@ -202,21 +202,6 @@
samsung,pll-clock-frequency = <24000000>;
status = "okay";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
-
- dsi_out: endpoint {
- remote-endpoint = <&dsi_in>;
- samsung,burst-clock-frequency = <500000000>;
- samsung,esc-clock-frequency = <20000000>;
- };
- };
- };
-
panel@0 {
reg = <0>;
compatible = "samsung,s6e8aa0";
@@ -244,12 +229,6 @@
vsync-len = <2>;
};
};
-
- port {
- dsi_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
};
};
diff --git a/dts/src/arm/exynos4412-itop-scp-core.dtsi b/dts/src/arm/exynos4412-itop-scp-core.dtsi
index 4cd62487bb..14ce2c69bc 100644
--- a/dts/src/arm/exynos4412-itop-scp-core.dtsi
+++ b/dts/src/arm/exynos4412-itop-scp-core.dtsi
@@ -466,7 +466,6 @@
pinctrl-names = "default";
status = "okay";
vmmc-supply = <&buck9_reg>;
- num-slots = <1>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
diff --git a/dts/src/arm/exynos4412-odroid-common.dtsi b/dts/src/arm/exynos4412-odroid-common.dtsi
index 219d587c5a..102acd78be 100644
--- a/dts/src/arm/exynos4412-odroid-common.dtsi
+++ b/dts/src/arm/exynos4412-odroid-common.dtsi
@@ -516,7 +516,6 @@
mmc-pwrseq = <&emmc_pwrseq>;
status = "okay";
- num-slots = <1>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
diff --git a/dts/src/arm/exynos4412-origen.dts b/dts/src/arm/exynos4412-origen.dts
index 7a83e2df18..8a89eb893d 100644
--- a/dts/src/arm/exynos4412-origen.dts
+++ b/dts/src/arm/exynos4412-origen.dts
@@ -488,7 +488,6 @@
pinctrl-names = "default";
status = "okay";
- num-slots = <1>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
diff --git a/dts/src/arm/exynos4412-trats2.dts b/dts/src/arm/exynos4412-trats2.dts
index 35e9b94b86..bceb919ac6 100644
--- a/dts/src/arm/exynos4412-trats2.dts
+++ b/dts/src/arm/exynos4412-trats2.dts
@@ -390,21 +390,6 @@
samsung,pll-clock-frequency = <24000000>;
status = "okay";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
-
- dsi_out: endpoint {
- remote-endpoint = <&dsi_in>;
- samsung,burst-clock-frequency = <500000000>;
- samsung,esc-clock-frequency = <20000000>;
- };
- };
- };
-
panel@0 {
compatible = "samsung,s6e8aa0";
reg = <0>;
@@ -432,12 +417,6 @@
vsync-len = <2>;
};
};
-
- port {
- dsi_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
};
};
@@ -901,7 +880,6 @@
};
&mshc_0 {
- num-slots = <1>;
broken-cd;
non-removable;
card-detect-delay = <200>;
diff --git a/dts/src/arm/exynos5250-arndale.dts b/dts/src/arm/exynos5250-arndale.dts
index 6a432460eb..18a7f396ac 100644
--- a/dts/src/arm/exynos5250-arndale.dts
+++ b/dts/src/arm/exynos5250-arndale.dts
@@ -518,7 +518,6 @@
&mmc_0 {
status = "okay";
- num-slots = <1>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
@@ -533,7 +532,6 @@
&mmc_2 {
status = "okay";
- num-slots = <1>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
diff --git a/dts/src/arm/exynos5250-smdk5250.dts b/dts/src/arm/exynos5250-smdk5250.dts
index 6632f65739..062cba4c2c 100644
--- a/dts/src/arm/exynos5250-smdk5250.dts
+++ b/dts/src/arm/exynos5250-smdk5250.dts
@@ -346,7 +346,6 @@
&mmc_0 {
status = "okay";
- num-slots = <1>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
@@ -360,7 +359,6 @@
&mmc_2 {
status = "okay";
- num-slots = <1>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
diff --git a/dts/src/arm/exynos5250-snow-common.dtsi b/dts/src/arm/exynos5250-snow-common.dtsi
index e1d293dbbe..8788880e45 100644
--- a/dts/src/arm/exynos5250-snow-common.dtsi
+++ b/dts/src/arm/exynos5250-snow-common.dtsi
@@ -530,7 +530,6 @@
/* eMMC flash */
&mmc_0 {
status = "okay";
- num-slots = <1>;
non-removable;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@@ -544,7 +543,6 @@
/* uSD card */
&mmc_2 {
status = "okay";
- num-slots = <1>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@@ -564,7 +562,6 @@
*/
&mmc_3 {
status = "okay";
- num-slots = <1>;
non-removable;
cap-sdio-irq;
keep-power-in-suspend;
diff --git a/dts/src/arm/exynos5250-spring.dts b/dts/src/arm/exynos5250-spring.dts
index 95c3bcace9..d53bfcbeb3 100644
--- a/dts/src/arm/exynos5250-spring.dts
+++ b/dts/src/arm/exynos5250-spring.dts
@@ -427,7 +427,6 @@
&mmc_0 {
status = "okay";
- num-slots = <1>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
@@ -445,7 +444,6 @@
*/
&mmc_1 {
status = "okay";
- num-slots = <1>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
diff --git a/dts/src/arm/exynos5260-xyref5260.dts b/dts/src/arm/exynos5260-xyref5260.dts
index d0cc300cfb..73b7cdd5f5 100644
--- a/dts/src/arm/exynos5260-xyref5260.dts
+++ b/dts/src/arm/exynos5260-xyref5260.dts
@@ -67,7 +67,6 @@
&mmc_0 {
status = "okay";
- num-slots = <1>;
broken-cd;
bypass-smu;
cap-mmc-highspeed;
@@ -83,7 +82,6 @@
&mmc_2 {
status = "okay";
- num-slots = <1>;
cap-sd-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
diff --git a/dts/src/arm/exynos5410-smdk5410.dts b/dts/src/arm/exynos5410-smdk5410.dts
index 6cc74d97da..9cb7726ef8 100644
--- a/dts/src/arm/exynos5410-smdk5410.dts
+++ b/dts/src/arm/exynos5410-smdk5410.dts
@@ -41,7 +41,6 @@
&mmc_0 {
status = "okay";
- num-slots = <1>;
cap-mmc-highspeed;
broken-cd;
card-detect-delay = <200>;
@@ -53,7 +52,6 @@
&mmc_2 {
status = "okay";
- num-slots = <1>;
cap-sd-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
diff --git a/dts/src/arm/exynos5420-peach-pit.dts b/dts/src/arm/exynos5420-peach-pit.dts
index f9a75bfd3f..683a4cfb4a 100644
--- a/dts/src/arm/exynos5420-peach-pit.dts
+++ b/dts/src/arm/exynos5420-peach-pit.dts
@@ -699,7 +699,6 @@
/* eMMC flash */
&mmc_0 {
status = "okay";
- num-slots = <1>;
mmc-hs200-1_8v;
cap-mmc-highspeed;
non-removable;
@@ -717,7 +716,6 @@
/* WiFi SDIO module */
&mmc_1 {
status = "okay";
- num-slots = <1>;
non-removable;
cap-sdio-irq;
keep-power-in-suspend;
@@ -737,7 +735,6 @@
/* uSD card */
&mmc_2 {
status = "okay";
- num-slots = <1>;
cap-sd-highspeed;
card-detect-delay = <200>;
clock-frequency = <400000000>;
diff --git a/dts/src/arm/exynos5440.dtsi b/dts/src/arm/exynos5440.dtsi
index bc4954e69f..7a00be7ea6 100644
--- a/dts/src/arm/exynos5440.dtsi
+++ b/dts/src/arm/exynos5440.dtsi
@@ -317,6 +317,7 @@
phys = <&pcie_phy0>;
ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
+ bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0x0 0 &gic 53>;
@@ -339,6 +340,7 @@
phys = <&pcie_phy1>;
ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
+ bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0x0 0 &gic 56>;
diff --git a/dts/src/arm/exynos5800-peach-pi.dts b/dts/src/arm/exynos5800-peach-pi.dts
index 953dc8677d..b2b95ff205 100644
--- a/dts/src/arm/exynos5800-peach-pi.dts
+++ b/dts/src/arm/exynos5800-peach-pi.dts
@@ -667,7 +667,6 @@
/* eMMC flash */
&mmc_0 {
status = "okay";
- num-slots = <1>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-highspeed;
@@ -686,7 +685,6 @@
/* WiFi SDIO module */
&mmc_1 {
status = "okay";
- num-slots = <1>;
non-removable;
cap-sdio-irq;
keep-power-in-suspend;
@@ -706,7 +704,6 @@
/* uSD card */
&mmc_2 {
status = "okay";
- num-slots = <1>;
cap-sd-highspeed;
card-detect-delay = <200>;
clock-frequency = <400000000>;
diff --git a/dts/src/arm/gemini-dlink-dir-685.dts b/dts/src/arm/gemini-dlink-dir-685.dts
new file mode 100644
index 0000000000..e75e2d4437
--- /dev/null
+++ b/dts/src/arm/gemini-dlink-dir-685.dts
@@ -0,0 +1,246 @@
+/*
+ * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
+ */
+
+/dts-v1/;
+
+#include "gemini.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "D-Link DIR-685 Xtreme N Storage Router";
+ compatible = "dlink,dir-685", "cortina,gemini";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory {
+ /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ chosen {
+ stdout-path = "uart0:115200n8";
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ button-esc {
+ debounce_interval = <50>;
+ wakeup-source;
+ linux,code = <KEY_ESC>;
+ label = "reset";
+ /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
+ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+ };
+ button-eject {
+ debounce_interval = <50>;
+ wakeup-source;
+ linux,code = <KEY_EJECTCD>;
+ label = "unmount";
+ /* Collides with LPC LFRAME, UART RTS, SSP TXD */
+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led-wps {
+ label = "dir685:blue:WPS";
+ /* Collides with ICE */
+ gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+ /*
+ * These two LEDs are on the side of the device.
+ * For electrical reasons, both LEDs cannot be active
+ * at the same time so only blue or orange can on at
+ * one time. Enabling both makes the LED go dark.
+ * The LEDs both sit inside the unmount button and the
+ * label on the case says "unmount".
+ */
+ led-blue-hd {
+ label = "dir685:blue:HD";
+ /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */
+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ led-orange-hd {
+ label = "dir685:orange:HD";
+ /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */
+ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ /*
+ * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
+ * Since the platform has no temperature sensor, this is controlled
+ * from userspace by using the hard disks S.M.A.R.T. temperature
+ * sensor. It is turned on when the temperature exceeds 46 degrees
+ * and turned off when the temperatures goes below 41 degrees
+ * (celsius).
+ */
+ gpio-fan {
+ compatible = "gpio-fan";
+ /* Collides with IDE */
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <0 0>, <10000 1>;
+ #cooling-cells = <2>;
+ };
+
+ /*
+ * The touchpad input is connected to a GPIO bit-banged
+ * I2C bus.
+ */
+ gpio-i2c {
+ compatible = "i2c-gpio";
+ /* Collides with ICE */
+ gpios = <&gpio0 5 0>, /* SDA */
+ <&gpio0 6 0>; /* SCL */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchkeys@26 {
+ compatible = "dlink,dir685-touchkeys";
+ reg = <0x26>;
+ interrupt-parent = <&gpio0>;
+ /* Collides with NAND flash */
+ interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ soc {
+ flash@30000000 {
+ status = "okay";
+ /* 32MB of flash */
+ reg = <0x30000000 0x02000000>;
+
+ /*
+ * This "RedBoot" is the Storlink derivative.
+ */
+ partition@0 {
+ label = "RedBoot";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ /*
+ * Between the boot loader and the rootfs is the kernel
+ * in a custom Storlink format flashed from the boot
+ * menu. The rootfs is in squashfs format.
+ */
+ partition@1800c0 {
+ label = "rootfs";
+ reg = <0x001800c0 0x01dbff40>;
+ read-only;
+ };
+ partition@1f40000 {
+ label = "upgrade";
+ reg = <0x01f40000 0x00040000>;
+ read-only;
+ };
+ partition@1f80000 {
+ label = "rgdb";
+ reg = <0x01f80000 0x00040000>;
+ read-only;
+ };
+ /*
+ * This partition contains MAC addresses for WAN,
+ * WLAN and LAN, and the country code (for wireless
+ * I guess).
+ */
+ partition@1fc0000 {
+ label = "nvram";
+ reg = <0x01fc0000 0x00020000>;
+ read-only;
+ };
+ partition@1fe0000 {
+ label = "LangPack";
+ reg = <0x01fe0000 0x00020000>;
+ read-only;
+ };
+ };
+
+ syscon: syscon@40000000 {
+ pinctrl {
+ /*
+ * gpio0bgrp cover line 5, 6 used by TK I2C
+ * gpio0bgrp cover line 7 used by WPS LED
+ * gpio0cgrp cover line 8, 13 used by keys
+ * and 11, 12 used by the HD LEDs
+ * gpio0egrp cover line 16 used by VDISP
+ * gpio0fgrp cover line 17 used by TK IRQ
+ * gpio0ggrp cover line 20 used by panel CS
+ * gpio0hgrp cover line 21,22 used by RTL8366RB
+ */
+ gpio0_default_pins: pinctrl-gpio0 {
+ mux {
+ function = "gpio0";
+ groups = "gpio0bgrp",
+ "gpio0cgrp",
+ "gpio0egrp",
+ "gpio0fgrp",
+ "gpio0ggrp",
+ "gpio0hgrp";
+ };
+ };
+ /*
+ * gpio1bgrp cover line 5,8,7 used by panel SPI
+ * also line 6 used by the fan
+ *
+ */
+ gpio1_default_pins: pinctrl-gpio1 {
+ mux {
+ function = "gpio1";
+ groups = "gpio1bgrp";
+ };
+ };
+ };
+ };
+
+ sata: sata@46000000 {
+ cortina,gemini-ata-muxmode = <0>;
+ cortina,gemini-enable-sata-bridge;
+ status = "okay";
+ };
+
+ gpio0: gpio@4d000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+ };
+
+ gpio1: gpio@4e000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_default_pins>;
+ };
+
+ pci@50000000 {
+ status = "okay";
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
+ <0x4800 0 0 2 &pci_intc 1>,
+ <0x4800 0 0 3 &pci_intc 2>,
+ <0x4800 0 0 4 &pci_intc 3>,
+ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
+ <0x5000 0 0 2 &pci_intc 2>,
+ <0x5000 0 0 3 &pci_intc 3>,
+ <0x5000 0 0 4 &pci_intc 0>,
+ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
+ <0x5800 0 0 2 &pci_intc 3>,
+ <0x5800 0 0 3 &pci_intc 0>,
+ <0x5800 0 0 4 &pci_intc 1>,
+ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
+ <0x6000 0 0 2 &pci_intc 0>,
+ <0x6000 0 0 3 &pci_intc 1>,
+ <0x6000 0 0 4 &pci_intc 2>;
+ };
+
+ ata@63000000 {
+ status = "okay";
+ };
+ };
+};
diff --git a/dts/src/arm/gemini-nas4220b.dts b/dts/src/arm/gemini-nas4220b.dts
index 55f6a4f1f8..b4fc58c8cf 100644
--- a/dts/src/arm/gemini-nas4220b.dts
+++ b/dts/src/arm/gemini-nas4220b.dts
@@ -33,6 +33,7 @@
wakeup-source;
linux,code = <KEY_SETUP>;
label = "Backup button";
+ /* Conflict with TVC */
gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
};
button@31 {
@@ -40,6 +41,7 @@
wakeup-source;
linux,code = <KEY_RESTART>;
label = "Softreset button";
+ /* Conflict with TVC */
gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
};
};
@@ -48,11 +50,13 @@
compatible = "gpio-leds";
led@28 {
label = "nas4220b:orange:hdd";
+ /* Conflict with TVC */
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led@30 {
label = "nas4220b:green:os";
+ /* Conflict with TVC */
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
@@ -99,12 +103,32 @@
};
};
+ syscon: syscon@40000000 {
+ pinctrl {
+ /*
+ * gpio1dgrp cover line 28-31 otherwise used
+ * by TVC.
+ */
+ gpio1_default_pins: pinctrl-gpio1 {
+ mux {
+ function = "gpio1";
+ groups = "gpio1dgrp";
+ };
+ };
+ };
+ };
+
sata: sata@46000000 {
cortina,gemini-ata-muxmode = <0>;
cortina,gemini-enable-sata-bridge;
status = "okay";
};
+ gpio1: gpio@4e000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_default_pins>;
+ };
+
ata@63000000 {
status = "okay";
};
diff --git a/dts/src/arm/gemini-rut1xx.dts b/dts/src/arm/gemini-rut1xx.dts
index 7b920bfbda..3613b264f4 100644
--- a/dts/src/arm/gemini-rut1xx.dts
+++ b/dts/src/arm/gemini-rut1xx.dts
@@ -33,6 +33,7 @@
wakeup-source;
linux,code = <KEY_SETUP>;
label = "Reset to defaults";
+ /* Conflict with TVC */
gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
};
};
@@ -42,12 +43,14 @@
led@7 {
/* FIXME: add the LED color */
label = "rut1xx::gsm";
+ /* Conflict with ICE */
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led@31 {
/* FIXME: add the LED color */
label = "rut1xx::power";
+ /* Conflict with NAND CE0 */
gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
@@ -61,5 +64,41 @@
reg = <0x30000000 0x00800000>;
/* TODO: add flash partitions here */
};
+
+ syscon: syscon@40000000 {
+ pinctrl {
+ /*
+ * gpio0bgrp cover line 7 used by GSM LED
+ * gpio0fgrp cover line 17 used by power LED
+ */
+ gpio0_default_pins: pinctrl-gpio0 {
+ mux {
+ function = "gpio0";
+ groups = "gpio0bgrp",
+ "gpio0fgrp";
+ };
+ };
+ /*
+ * gpio1dgrp cover line 28-31 otherwise used
+ * by TVC.
+ */
+ gpio1_default_pins: pinctrl-gpio1 {
+ mux {
+ function = "gpio1";
+ groups = "gpio1dgrp";
+ };
+ };
+ };
+ };
+
+ gpio0: gpio@4d000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+ };
+
+ gpio1: gpio@4e000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_default_pins>;
+ };
};
};
diff --git a/dts/src/arm/gemini-sq201.dts b/dts/src/arm/gemini-sq201.dts
index 4d200f0bcd..7cfa9caf47 100644
--- a/dts/src/arm/gemini-sq201.dts
+++ b/dts/src/arm/gemini-sq201.dts
@@ -33,6 +33,7 @@
wakeup-source;
linux,code = <KEY_SETUP>;
label = "factory reset";
+ /* Conflict with NAND flash */
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
};
};
@@ -41,12 +42,14 @@
compatible = "gpio-leds";
led@20 {
label = "sq201:green:info";
+ /* Conflict with parallel flash */
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led@31 {
label = "sq201:green:usb";
+ /* Conflict with parallel and NAND flash */
gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "usb-host";
@@ -55,7 +58,15 @@
soc {
flash@30000000 {
- status = "okay";
+ /*
+ * Flash access can be enabled, with the side effect
+ * of disabling access to GPIO LED on GPIO0[20] which
+ * reuse one of the parallel flash chip select lines.
+ * Also the default firmware on the machine has the
+ * problem that since it uses the flash, the two LEDS
+ * on the right become numb.
+ */
+ /* status = "okay"; */
/* 16MB of flash */
reg = <0x30000000 0x01000000>;
@@ -93,12 +104,35 @@
};
};
+ syscon: syscon@40000000 {
+ pinctrl {
+ /*
+ * gpio0fgrp cover line 18 used by reset button
+ * gpio0ggrp cover line 20 used by info LED
+ * gpio0kgrp cover line 31 used by USB LED
+ */
+ gpio0_default_pins: pinctrl-gpio0 {
+ mux {
+ function = "gpio0";
+ groups = "gpio0fgrp",
+ "gpio0ggrp",
+ "gpio0kgrp";
+ };
+ };
+ };
+ };
+
sata: sata@46000000 {
cortina,gemini-ata-muxmode = <0>;
cortina,gemini-enable-sata-bridge;
status = "okay";
};
+ gpio0: gpio@4d000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+ };
+
pci@50000000 {
status = "okay";
interrupt-map-mask = <0xf800 0 0 7>;
diff --git a/dts/src/arm/gemini-wbd111.dts b/dts/src/arm/gemini-wbd111.dts
index 63b756e3bf..38a49e7504 100644
--- a/dts/src/arm/gemini-wbd111.dts
+++ b/dts/src/arm/gemini-wbd111.dts
@@ -33,6 +33,7 @@
wakeup-source;
linux,code = <KEY_SETUP>;
label = "reset";
+ /* Conflict with ICE */
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
};
};
@@ -42,21 +43,25 @@
led@1 {
label = "wbd111:red:L3";
+ /* Conflict with TVC and extended parallel flash */
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@2 {
label = "wbd111:green:L4";
+ /* Conflict with TVC and extended parallel flash */
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@3 {
label = "wbd111:red:L4";
+ /* Conflict with TVC and extended parallel flash */
gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@5 {
label = "wbd111:green:L3";
+ /* Conflict with TVC and extended parallel flash */
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
@@ -98,5 +103,26 @@
read-only;
};
};
+
+ syscon: syscon@40000000 {
+ pinctrl {
+ /*
+ * gpio0agrp cover line 0-4
+ * gpio0bgrp cover line 5
+ */
+ gpio0_default_pins: pinctrl-gpio0 {
+ mux {
+ function = "gpio0";
+ groups = "gpio0agrp",
+ "gpio0bgrp";
+ };
+ };
+ };
+ };
+
+ gpio0: gpio@4d000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+ };
};
};
diff --git a/dts/src/arm/gemini-wbd222.dts b/dts/src/arm/gemini-wbd222.dts
index 9747f5a478..f77e34e0df 100644
--- a/dts/src/arm/gemini-wbd222.dts
+++ b/dts/src/arm/gemini-wbd222.dts
@@ -33,6 +33,7 @@
wakeup-source;
linux,code = <KEY_SETUP>;
label = "reset";
+ /* Conflict with ICE */
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
};
};
@@ -42,21 +43,25 @@
led@1 {
label = "wbd111:red:L3";
+ /* Conflict with TVC and extended parallel flash */
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@2 {
label = "wbd111:green:L4";
+ /* Conflict with TVC and extended parallel flash */
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@3 {
label = "wbd111:red:L4";
+ /* Conflict with TVC and extended parallel flash */
gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@5 {
label = "wbd111:green:L3";
+ /* Conflict with TVC and extended parallel flash */
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
@@ -98,5 +103,26 @@
read-only;
};
};
+
+ syscon: syscon@40000000 {
+ pinctrl {
+ /*
+ * gpio0agrp cover line 0-4
+ * gpio0bgrp cover line 5
+ */
+ gpio0_default_pins: pinctrl-gpio0 {
+ mux {
+ function = "gpio0";
+ groups = "gpio0agrp",
+ "gpio0bgrp";
+ };
+ };
+ };
+ };
+
+ gpio0: gpio@4d000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+ };
};
};
diff --git a/dts/src/arm/gemini.dtsi b/dts/src/arm/gemini.dtsi
index 141d8d3a1d..c68e8d4302 100644
--- a/dts/src/arm/gemini.dtsi
+++ b/dts/src/arm/gemini.dtsi
@@ -5,6 +5,8 @@
/include/ "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/cortina,gemini-clock.h>
+#include <dt-bindings/reset/cortina,gemini-reset.h>
#include <dt-bindings/gpio/gpio.h>
/ {
@@ -18,6 +20,8 @@
flash@30000000 {
compatible = "cortina,gemini-flash", "cfi-flash";
syscon = <&syscon>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pflash_default_pins>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
@@ -39,22 +43,123 @@
/* RESET_GLOBAL | RESET_CPU1 */
mask = <0xC0000000>;
};
+
+ pinctrl {
+ compatible = "cortina,gemini-pinctrl";
+ regmap = <&syscon>;
+ /* Hog the DRAM pins */
+ pinctrl-names = "default";
+ pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
+ <&vcontrol_default_pins>;
+
+ dram_default_pins: pinctrl-dram {
+ mux {
+ function = "dram";
+ groups = "dramgrp";
+ };
+ };
+ rtc_default_pins: pinctrl-rtc {
+ mux {
+ function = "rtc";
+ groups = "rtcgrp";
+ };
+ };
+ power_default_pins: pinctrl-power {
+ mux {
+ function = "power";
+ groups = "powergrp";
+ };
+ };
+ cir_default_pins: pinctrl-cir {
+ mux {
+ function = "cir";
+ groups = "cirgrp";
+ };
+ };
+ system_default_pins: pinctrl-system {
+ mux {
+ function = "system";
+ groups = "systemgrp";
+ };
+ };
+ vcontrol_default_pins: pinctrl-vcontrol {
+ mux {
+ function = "vcontrol";
+ groups = "vcontrolgrp";
+ };
+ };
+ ice_default_pins: pinctrl-ice {
+ mux {
+ function = "ice";
+ groups = "icegrp";
+ };
+ };
+ uart_default_pins: pinctrl-uart {
+ mux {
+ function = "uart";
+ groups = "uartrxtxgrp";
+ };
+ };
+ pflash_default_pins: pinctrl-pflash {
+ mux {
+ function = "pflash";
+ groups = "pflashgrp";
+ };
+ };
+ usb_default_pins: pinctrl-usb {
+ mux {
+ function = "usb";
+ groups = "usbgrp";
+ };
+ };
+ gmii_default_pins: pinctrl-gmii {
+ mux {
+ function = "gmii";
+ groups = "gmiigrp";
+ };
+ };
+ pci_default_pins: pinctrl-pci {
+ mux {
+ function = "pci";
+ groups = "pcigrp";
+ };
+ };
+ sata_default_pins: pinctrl-sata {
+ mux {
+ function = "sata";
+ groups = "satagrp";
+ };
+ };
+ /* Activate both groups of pins for this state */
+ sata_and_ide_pins: pinctrl-sata-ide {
+ mux0 {
+ function = "sata";
+ groups = "satagrp";
+ };
+ mux1 {
+ function = "ide";
+ groups = "idegrp";
+ };
+ };
+ };
};
watchdog@41000000 {
compatible = "cortina,gemini-watchdog";
reg = <0x41000000 0x1000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon 23>;
- clocks = <&syscon 2>;
+ resets = <&syscon GEMINI_RESET_WDOG>;
+ clocks = <&syscon GEMINI_CLK_APB>;
};
uart0: serial@42000000 {
compatible = "ns16550a";
reg = <0x42000000 0x100>;
- resets = <&syscon 18>;
- clocks = <&syscon 6>;
+ resets = <&syscon GEMINI_RESET_UART>;
+ clocks = <&syscon GEMINI_CLK_UART>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_default_pins>;
reg-shift = <2>;
};
@@ -65,9 +170,9 @@
interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
- resets = <&syscon 17>;
+ resets = <&syscon GEMINI_RESET_TIMER>;
/* APB clock or RTC clock */
- clocks = <&syscon 2>, <&syscon 0>;
+ clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
clock-names = "PCLK", "EXTCLK";
syscon = <&syscon>;
};
@@ -76,20 +181,30 @@
compatible = "cortina,gemini-rtc";
reg = <0x45000000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon 16>;
- clocks = <&syscon 2>, <&syscon 0>;
+ resets = <&syscon GEMINI_RESET_RTC>;
+ clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
clock-names = "PCLK", "EXTCLK";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_default_pins>;
};
sata: sata@46000000 {
compatible = "cortina,gemini-sata-bridge";
reg = <0x46000000 0x100>;
- resets = <&syscon 26>,
- <&syscon 27>;
+ resets = <&syscon GEMINI_RESET_SATA0>,
+ <&syscon GEMINI_RESET_SATA1>;
reset-names = "sata0", "sata1";
- clocks = <&syscon 10>,
- <&syscon 11>;
+ clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
+ <&syscon GEMINI_CLK_GATE_SATA1>;
clock-names = "SATA0_PCLK", "SATA1_PCLK";
+ /*
+ * This defines the special "ide" state that needs
+ * to be explicitly enabled to enable the IDE pins,
+ * as these pins are normally used for other things.
+ */
+ pinctrl-names = "default", "ide";
+ pinctrl-0 = <&sata_default_pins>;
+ pinctrl-1 = <&sata_and_ide_pins>;
syscon = <&syscon>;
status = "disabled";
};
@@ -97,7 +212,7 @@
intcon: interrupt-controller@48000000 {
compatible = "faraday,ftintc010";
reg = <0x48000000 0x1000>;
- resets = <&syscon 14>;
+ resets = <&syscon GEMINI_RESET_INTCON0>;
interrupt-controller;
#interrupt-cells = <2>;
};
@@ -106,14 +221,16 @@
compatible = "cortina,gemini-power-controller";
reg = <0x4b000000 0x100>;
interrupts = <26 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_default_pins>;
};
gpio0: gpio@4d000000 {
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4d000000 0x100>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon 20>;
- clocks = <&syscon 2>;
+ resets = <&syscon GEMINI_RESET_GPIO0>;
+ clocks = <&syscon GEMINI_CLK_APB>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -124,8 +241,8 @@
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4e000000 0x100>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon 21>;
- clocks = <&syscon 2>;
+ resets = <&syscon GEMINI_RESET_GPIO1>;
+ clocks = <&syscon GEMINI_CLK_APB>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -136,8 +253,8 @@
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4f000000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon 22>;
- clocks = <&syscon 2>;
+ resets = <&syscon GEMINI_RESET_GPIO2>;
+ clocks = <&syscon GEMINI_CLK_APB>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -151,9 +268,11 @@
* to configure the host bridge.
*/
reg = <0x50000000 0x100>;
- resets = <&syscon 7>;
- clocks = <&syscon 15>, <&syscon 4>;
+ resets = <&syscon GEMINI_RESET_PCI>;
+ clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
clock-names = "PCLK", "PCICLK";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pci_default_pins>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
@@ -193,8 +312,8 @@
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x1000>;
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
- resets = <&syscon 2>;
- clocks = <&syscon 14>;
+ resets = <&syscon GEMINI_RESET_IDE>;
+ clocks = <&syscon GEMINI_CLK_GATE_IDE>;
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
@@ -204,8 +323,8 @@
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63400000 0x1000>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
- resets = <&syscon 2>;
- clocks = <&syscon 14>;
+ resets = <&syscon GEMINI_RESET_IDE>;
+ clocks = <&syscon GEMINI_CLK_GATE_IDE>;
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
@@ -217,8 +336,8 @@
arm,primecell-periphid = <0x0003b080>;
reg = <0x67000000 0x1000>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
- resets = <&syscon 10>;
- clocks = <&syscon 1>;
+ resets = <&syscon GEMINI_RESET_DMAC>;
+ clocks = <&syscon GEMINI_CLK_AHB>;
clock-names = "apb_pclk";
/* Bus interface AHB1 (AHB0) is totally tilted */
lli-bus-interface-ahb2;
diff --git a/dts/src/arm/imx25.dtsi b/dts/src/arm/imx25.dtsi
index 0ade3619f3..09ce8b81fa 100644
--- a/dts/src/arm/imx25.dtsi
+++ b/dts/src/arm/imx25.dtsi
@@ -452,6 +452,13 @@
interrupt-names = "scm", "smn";
};
+ rngb: rngb@53fb0000 {
+ compatible = "fsl,imx25-rngb";
+ reg = <0x53fb0000 0x4000>;
+ clocks = <&clks 109>;
+ interrupts = <22>;
+ };
+
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb4000 0x4000>;
diff --git a/dts/src/arm/imx53-cx9020.dts b/dts/src/arm/imx53-cx9020.dts
new file mode 100644
index 0000000000..4f54fd4418
--- /dev/null
+++ b/dts/src/arm/imx53-cx9020.dts
@@ -0,0 +1,297 @@
+/*
+ * Copyright 2017 Beckhoff Automation GmbH & Co. KG
+ * based on imx53-qsb.dts
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx53.dtsi"
+
+/ {
+ model = "Beckhoff CX9020 Embedded PC";
+ compatible = "bhf,cx9020", "fsl,imx53";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory {
+ reg = <0x70000000 0x20000000>,
+ <0xb0000000 0x20000000>;
+ };
+
+ display-0 {
+ #address-cells =<1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx-parallel-display";
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu_disp0>;
+
+ port@0 {
+ reg = <0>;
+
+ display0_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ display0_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
+ };
+
+ dvi-connector {
+ compatible = "dvi-connector";
+ ddc-i2c-bus = <&i2c2>;
+ digital;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ dvi-converter {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,tfp410";
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&display0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr-r {
+ gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ pwr-g {
+ gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ pwr-b {
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ sd1-b {
+ linux,default-trigger = "mmc0";
+ gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ sd2-b {
+ linux,default-trigger = "mmc1";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulator-3p2v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P2V";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-always-on;
+ };
+
+ reg_usb_vbus: regulator-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&esdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&ipu_di0_disp0 {
+ remote-endpoint = <&display0_in>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ fsl,dte-mode;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_vbus>;
+ phy_type = "utmi";
+ status = "okay";
+};
+
+&usbotg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&vpu {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX53_PAD_GPIO_0__CCM_CLKO 0x1c4
+ MX53_PAD_GPIO_16__I2C3_SDA 0x1c4
+ MX53_PAD_EIM_D22__GPIO3_22 0x1c4
+ MX53_PAD_EIM_D23__GPIO3_23 0x1e4
+ MX53_PAD_EIM_D24__GPIO3_24 0x1e4
+ >;
+ };
+
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4
+ MX53_PAD_EIM_D17__GPIO3_17 0x1e4
+ MX53_PAD_GPIO_3__GPIO1_3 0x1c4
+ >;
+ };
+
+ pinctrl_esdhc2: esdhc2grp {
+ fsl,pins = <
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
+ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
+ MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
+ MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4
+ MX53_PAD_EIM_D20__GPIO3_20 0x1e4
+ MX53_PAD_GPIO_8__GPIO1_8 0x1c4
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x4
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
+ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
+ >;
+ };
+
+ pinctrl_ipu_disp0: ipudisp0grp {
+ fsl,pins = <
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
+ MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
+ MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
+ MX53_PAD_EIM_D28__UART2_RTS 0x1e4
+ MX53_PAD_EIM_D29__UART2_CTS 0x1e4
+ >;
+ };
+};
diff --git a/dts/src/arm/imx53-pinfunc.h b/dts/src/arm/imx53-pinfunc.h
index aec406bc65..59f9c29e3f 100644
--- a/dts/src/arm/imx53-pinfunc.h
+++ b/dts/src/arm/imx53-pinfunc.h
@@ -524,6 +524,7 @@
#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0
#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0
#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0
#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0
#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0
@@ -533,6 +534,7 @@
#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0
#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0
#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1
+#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0
#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0
#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0
@@ -541,6 +543,7 @@
#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0
#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0
#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0
+#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1
#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1
#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1
@@ -548,6 +551,7 @@
#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0
#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0
#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0
+#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1
#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0
#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2
diff --git a/dts/src/arm/imx53.dtsi b/dts/src/arm/imx53.dtsi
index 2e516f4985..8bf0d89cdd 100644
--- a/dts/src/arm/imx53.dtsi
+++ b/dts/src/arm/imx53.dtsi
@@ -433,6 +433,15 @@
clock-names = "ipg", "per";
};
+ srtc: srtc@53fa4000 {
+ compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
+ reg = <0x53fa4000 0x4000>;
+ interrupts = <24>;
+ interrupt-parent = <&tzic>;
+ clocks = <&clks IMX5_CLK_SRTC_GATE>;
+ clock-names = "ipg";
+ };
+
iomuxc: iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
diff --git a/dts/src/arm/imx6dl-gw52xx.dts b/dts/src/arm/imx6dl-gw52xx.dts
index a2e0b73fdd..5f9f894810 100644
--- a/dts/src/arm/imx6dl-gw52xx.dts
+++ b/dts/src/arm/imx6dl-gw52xx.dts
@@ -17,3 +17,61 @@
model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX";
compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
};
+
+&i2c3 {
+ adv7180: camera@20 {
+ compatible = "adi,adv7180";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adv7180>;
+ reg = <0x20>;
+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ adv7180_to_ipu1_csi1_mux: endpoint {
+ remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
+};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ bus-width = <8>;
+};
+
+&ipu1_csi1_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
+ bus-width = <8>;
+};
+
+&ipu1_csi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi1>;
+};
+
+&iomuxc {
+ pinctrl_adv7180: adv7180grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
+ >;
+ };
+
+ pinctrl_ipu1_csi1: ipu1_csi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0
+ MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0
+ MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0
+ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0
+ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6dl-gw53xx.dts b/dts/src/arm/imx6dl-gw53xx.dts
index 6844b708d2..9bfc620d37 100644
--- a/dts/src/arm/imx6dl-gw53xx.dts
+++ b/dts/src/arm/imx6dl-gw53xx.dts
@@ -17,3 +17,61 @@
model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX";
compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
};
+
+&i2c3 {
+ adv7180: camera@20 {
+ compatible = "adi,adv7180";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adv7180>;
+ reg = <0x20>;
+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ adv7180_to_ipu1_csi1_mux: endpoint {
+ remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
+};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ bus-width = <8>;
+};
+
+&ipu1_csi1_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
+ bus-width = <8>;
+};
+
+&ipu1_csi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi1>;
+};
+
+&iomuxc {
+ pinctrl_adv7180: adv7180grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
+ >;
+ };
+
+ pinctrl_ipu1_csi1: ipu1_csi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0
+ MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0
+ MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0
+ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0
+ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6dl-gw54xx.dts b/dts/src/arm/imx6dl-gw54xx.dts
index be915412f8..b909bdf9a2 100644
--- a/dts/src/arm/imx6dl-gw54xx.dts
+++ b/dts/src/arm/imx6dl-gw54xx.dts
@@ -17,3 +17,61 @@
model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX";
compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
};
+
+&i2c3 {
+ adv7180: camera@20 {
+ compatible = "adi,adv7180";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adv7180>;
+ reg = <0x20>;
+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ adv7180_to_ipu1_csi1_mux: endpoint {
+ remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
+};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ bus-width = <8>;
+};
+
+&ipu1_csi1_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
+ bus-width = <8>;
+};
+
+&ipu1_csi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi1>;
+};
+
+&iomuxc {
+ pinctrl_adv7180: adv7180grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
+ >;
+ };
+
+ pinctrl_ipu1_csi1: ipu1_csi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0
+ MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0
+ MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0
+ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0
+ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6dl-riotboard.dts b/dts/src/arm/imx6dl-riotboard.dts
index 29b45f2e64..275c6c0521 100644
--- a/dts/src/arm/imx6dl-riotboard.dts
+++ b/dts/src/arm/imx6dl-riotboard.dts
@@ -101,6 +101,51 @@
status = "okay";
};
+&gpio1 {
+ gpio-line-names =
+ "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
+ "I2C3_SDA", "I2C4_SCL",
+ "I2C4_SDA", "", "", "", "", "", "", "",
+ "", "PWM3", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "USB_OTG_VBUS", "",
+ "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
+ "UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
+ "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
+ "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
+ "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
+ "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
+ "GPIO5_07",
+ "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
+ "CSPI2_CS0", "CSPI2_CLK", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio7 {
+ gpio-line-names =
+ "SD3_CD", "SD3_WP", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
diff --git a/dts/src/arm/imx6q-apalis-eval.dts b/dts/src/arm/imx6q-apalis-eval.dts
new file mode 100644
index 0000000000..4bbfe3d610
--- /dev/null
+++ b/dts/src/arm/imx6q-apalis-eval.dts
@@ -0,0 +1,278 @@
+/*
+ * Copyright 2014-2017 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-apalis.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board";
+ compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q",
+ "fsl,imx6q";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c3;
+ i2c2 = &i2c2;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ lcd_display: display@di0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di1_disp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel: panel {
+ /*
+ * edt,et057090dhu: EDT 5.7" LCD TFT
+ * edt,et070080dh6: EDT 7.0" LCD TFT
+ */
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ reg_pcie_switch: regulator-pcie-switch {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie_switch";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ status = "okay";
+ };
+};
+
+&backlight {
+ brightness-levels = <0 127 191 223 239 247 251 255>;
+ default-brightness-level = <1>;
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
+&i2c1 {
+ status = "okay";
+
+ pcie-switch@58 {
+ compatible = "plx,pex8605";
+ reg = <0x58>;
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t00";
+ reg = <0x68>;
+ };
+};
+
+/*
+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
+ * board)
+ */
+&i2c3 {
+ status = "okay";
+};
+
+&ipu1_di1_disp1 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&ldb {
+ status = "okay";
+};
+
+&pcie {
+ /* active-high meaning opposite of regular PERST# active-low polarity */
+ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ reset-gpio-active-high;
+ vpcie-supply = <&reg_pcie_switch>;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_otg_vbus {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&sound_spdif {
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_host_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ status = "okay";
+};
+
+/* MMC1 */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
+ cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* SD1 */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&iomuxc {
+ /*
+ * Mux the Apalis GPIOs
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
+ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
+ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
+ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
+ >;
+};
diff --git a/dts/src/arm/imx6q-apalis-ixora-v1.1.dts b/dts/src/arm/imx6q-apalis-ixora-v1.1.dts
new file mode 100644
index 0000000000..a35c7a54ad
--- /dev/null
+++ b/dts/src/arm/imx6q-apalis-ixora-v1.1.dts
@@ -0,0 +1,291 @@
+/*
+ * Copyright 2014-2017 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-apalis.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1";
+ compatible = "toradex,apalis_imx6q-ixora-v1.1",
+ "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
+ "fsl,imx6q";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c3;
+ i2c2 = &i2c2;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ lcd_display: display@di0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di1_disp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel: panel {
+ /*
+ * edt,et057090dhu: EDT 5.7" LCD TFT
+ * edt,et070080dh6: EDT 7.0" LCD TFT
+ */
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds_ixora>;
+
+ led4-green {
+ label = "LED_4_GREEN";
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ led4-red {
+ label = "LED_4_RED";
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ led5-green {
+ label = "LED_5_GREEN";
+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led5-red {
+ label = "LED_5_RED";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&backlight {
+ brightness-levels = <0 127 191 223 239 247 251 255>;
+ default-brightness-level = <1>;
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
+&i2c1 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t00";
+ reg = <0x68>;
+ };
+};
+
+/*
+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
+ * board)
+ */
+&i2c3 {
+ status = "okay";
+};
+
+&ipu1_di1_disp1 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&ldb {
+ status = "okay";
+};
+
+&pcie {
+ /* active-high meaning opposite of regular PERST# active-low polarity */
+ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ reset-gpio-active-high;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_otg_vbus {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&sound_spdif {
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_host_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ status = "okay";
+};
+
+/* MMC1 */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
+ cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&iomuxc {
+ /*
+ * Mux the Apalis GPIOs
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
+ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
+ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
+ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
+ >;
+
+ pinctrl_leds_ixora: ledsixoragrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6q-apalis-ixora.dts b/dts/src/arm/imx6q-apalis-ixora.dts
index 88cc7f51a4..60d33e99de 100644
--- a/dts/src/arm/imx6q-apalis-ixora.dts
+++ b/dts/src/arm/imx6q-apalis-ixora.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2014-2016 Toradex AG
+ * Copyright 2014-2017 Toradex AG
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
@@ -55,13 +55,9 @@
"fsl,imx6q";
aliases {
- i2c0 = &i2cddc;
- i2c1 = &i2c1;
+ i2c0 = &i2c1;
+ i2c1 = &i2c3;
i2c2 = &i2c2;
- i2c3 = &i2c3;
- };
-
- aliases {
rtc0 = &rtc_i2c;
rtc1 = &snvs_rtc;
};
@@ -164,15 +160,10 @@
};
&hdmi {
- ddc-i2c-bus = <&i2cddc>;
- status = "okay";
-};
-
-&i2cddc {
status = "okay";
};
-/* GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
status = "okay";
@@ -188,6 +179,14 @@
};
};
+/*
+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
+ * board)
+ */
+&i2c3 {
+ status = "okay";
+};
+
&ipu1_di1_disp1 {
remote-endpoint = <&lcd_display_in>;
};
@@ -268,16 +267,13 @@
/* SD1 */
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sd_cd>;
+ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
- /*
- * Mux the Apalis GPIOs
- * GPIO5, 6 used by optional fusion_F0710A kernel module
- */
+ /* Mux the Apalis GPIOs */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
&pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
diff --git a/dts/src/arm/imx6q-b850v3.dts b/dts/src/arm/imx6q-b850v3.dts
index 2c1e98e0cf..46bdc67227 100644
--- a/dts/src/arm/imx6q-b850v3.dts
+++ b/dts/src/arm/imx6q-b850v3.dts
@@ -57,7 +57,7 @@
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
- <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>;
+ <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
diff --git a/dts/src/arm/imx6q-bx50v3.dtsi b/dts/src/arm/imx6q-bx50v3.dtsi
index c90b26f00e..1015e55ca8 100644
--- a/dts/src/arm/imx6q-bx50v3.dtsi
+++ b/dts/src/arm/imx6q-bx50v3.dtsi
@@ -111,6 +111,11 @@
};
&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
+
pca9547: mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
@@ -261,6 +266,43 @@
};
};
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+};
+
+&i2c3 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+};
+
+&iomuxc {
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
+ >;
+ };
+};
+
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
diff --git a/dts/src/arm/imx6q-evi.dts b/dts/src/arm/imx6q-evi.dts
index 1f0f950dc1..e0aea782c6 100644
--- a/dts/src/arm/imx6q-evi.dts
+++ b/dts/src/arm/imx6q-evi.dts
@@ -94,6 +94,15 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
status = "okay";
+
+ fpga: fpga@0 {
+ compatible = "altr,fpga-passive-serial";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ pinctrl-0 = <&pinctrl_fpgaspi>;
+ nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ };
};
&ecspi3 {
@@ -319,6 +328,13 @@
>;
};
+ pinctrl_fpgaspi: fpgaspigrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ >;
+ };
+
pinctrl_gpminand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
diff --git a/dts/src/arm/imx6q-gw52xx.dts b/dts/src/arm/imx6q-gw52xx.dts
index a12c47e5ee..0b8ae007ad 100644
--- a/dts/src/arm/imx6q-gw52xx.dts
+++ b/dts/src/arm/imx6q-gw52xx.dts
@@ -18,6 +18,64 @@
compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
};
+&i2c3 {
+ adv7180: camera@20 {
+ compatible = "adi,adv7180";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adv7180>;
+ reg = <0x20>;
+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ adv7180_to_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
+};
+
+&ipu2_csi1_from_ipu2_csi1_mux {
+ bus-width = <8>;
+};
+
+&ipu2_csi1_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
+ bus-width = <8>;
+};
+
+&ipu2_csi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu2_csi1>;
+};
+
+&iomuxc {
+ pinctrl_adv7180: adv7180grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
+ >;
+ };
+
+ pinctrl_ipu2_csi1: ipu2_csi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
+ MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
+ MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
+ MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
+ MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
+ >;
+ };
+};
+
&sata {
status = "okay";
};
diff --git a/dts/src/arm/imx6q-gw53xx.dts b/dts/src/arm/imx6q-gw53xx.dts
index d76aaa83da..a56ef77eff 100644
--- a/dts/src/arm/imx6q-gw53xx.dts
+++ b/dts/src/arm/imx6q-gw53xx.dts
@@ -18,6 +18,64 @@
compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
};
+&i2c3 {
+ adv7180: camera@20 {
+ compatible = "adi,adv7180";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adv7180>;
+ reg = <0x20>;
+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ adv7180_to_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
+};
+
+&ipu2_csi1_from_ipu2_csi1_mux {
+ bus-width = <8>;
+};
+
+&ipu2_csi1_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
+ bus-width = <8>;
+};
+
+&ipu2_csi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu2_csi1>;
+};
+
&sata {
status = "okay";
};
+
+&iomuxc {
+ pinctrl_adv7180: adv7180grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
+ >;
+ };
+
+ pinctrl_ipu2_csi1: ipu2_csi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
+ MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
+ MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
+ MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
+ MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6q-gw54xx.dts b/dts/src/arm/imx6q-gw54xx.dts
index 6e8f53e92a..56e5b5050f 100644
--- a/dts/src/arm/imx6q-gw54xx.dts
+++ b/dts/src/arm/imx6q-gw54xx.dts
@@ -18,6 +18,64 @@
compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
};
+&i2c3 {
+ adv7180: camera@20 {
+ compatible = "adi,adv7180";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adv7180>;
+ reg = <0x20>;
+ powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ adv7180_to_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
+};
+
+&ipu2_csi1_from_ipu2_csi1_mux {
+ bus-width = <8>;
+};
+
+&ipu2_csi1_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
+ bus-width = <8>;
+};
+
+&ipu2_csi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu2_csi1>;
+};
+
&sata {
status = "okay";
};
+
+&iomuxc {
+ pinctrl_adv7180: adv7180grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
+ >;
+ };
+
+ pinctrl_ipu2_csi1: ipu2_csi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
+ MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
+ MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
+ MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
+ MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
+ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6qdl-apalis.dtsi b/dts/src/arm/imx6qdl-apalis.dtsi
index ba01dd76d8..ea339fa58f 100644
--- a/dts/src/arm/imx6qdl-apalis.dtsi
+++ b/dts/src/arm/imx6qdl-apalis.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright 2014-2016 Toradex AG
+ * Copyright 2014-2017 Toradex AG
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
@@ -56,18 +56,6 @@
status = "disabled";
};
- /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */
- i2cddc: i2c@0 {
- compatible = "i2c-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c_ddc>;
- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */
- &gpio2 30 GPIO_ACTIVE_HIGH /* scl */
- >;
- i2c-gpio,delay-us = <2>; /* ~100 kHz */
- status = "disabled";
- };
-
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
@@ -210,10 +198,13 @@
};
};
-/*
- * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
- * board)
- */
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_ddc>;
+ status = "disabled";
+};
+
+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -374,7 +365,8 @@
};
/*
- * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
+ * board)
*/
&i2c3 {
clock-frequency = <100000>;
@@ -460,7 +452,7 @@
/* MMC1 */
&usdhc1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
vqmmc-supply = <&reg_3p3v>;
bus-width = <8>;
voltage-ranges = <3300 3300>;
@@ -640,11 +632,10 @@
>;
};
- pinctrl_i2c_ddc: gpioi2cddcgrp {
+ pinctrl_hdmi_ddc: hdmiddcgrp {
fsl,pins = <
- /* DDC bitbang */
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
- MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
+ MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
>;
};
@@ -912,7 +903,7 @@
>;
};
- pinctrl_usdhc1: usdhc1grp {
+ pinctrl_usdhc1_4bit: usdhc1grp_4bit {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
@@ -920,6 +911,11 @@
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+ >;
+ };
+
+ pinctrl_usdhc1_8bit: usdhc1grp_8bit {
+ fsl,pins = <
MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
diff --git a/dts/src/arm/imx6qdl-gw51xx.dtsi b/dts/src/arm/imx6qdl-gw51xx.dtsi
index e8c1edc82e..885556260b 100644
--- a/dts/src/arm/imx6qdl-gw51xx.dtsi
+++ b/dts/src/arm/imx6qdl-gw51xx.dtsi
@@ -231,6 +231,37 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
+
+ adv7180: camera@20 {
+ compatible = "adi,adv7180";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adv7180>;
+ reg = <0x20>;
+ powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ adv7180_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
+ bus-width = <8>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&pcie {
@@ -302,6 +333,13 @@
&iomuxc {
imx6qdl-gw51xx {
+ pinctrl_adv7180: adv7180grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
+ >;
+ };
+
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
@@ -372,6 +410,22 @@
>;
};
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
diff --git a/dts/src/arm/imx6qdl-gw52xx.dtsi b/dts/src/arm/imx6qdl-gw52xx.dtsi
index 91991d63a6..115d706228 100644
--- a/dts/src/arm/imx6qdl-gw52xx.dtsi
+++ b/dts/src/arm/imx6qdl-gw52xx.dtsi
@@ -377,7 +377,6 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-gw53xx.dtsi b/dts/src/arm/imx6qdl-gw53xx.dtsi
index 5bc6ed1a5b..24be796505 100644
--- a/dts/src/arm/imx6qdl-gw53xx.dtsi
+++ b/dts/src/arm/imx6qdl-gw53xx.dtsi
@@ -368,7 +368,6 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-gw54xx.dtsi b/dts/src/arm/imx6qdl-gw54xx.dtsi
index 66fcf838e9..4594b22791 100644
--- a/dts/src/arm/imx6qdl-gw54xx.dtsi
+++ b/dts/src/arm/imx6qdl-gw54xx.dtsi
@@ -416,7 +416,6 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-gw553x.dtsi b/dts/src/arm/imx6qdl-gw553x.dtsi
index 57374dddf9..1a0faa1a14 100644
--- a/dts/src/arm/imx6qdl-gw553x.dtsi
+++ b/dts/src/arm/imx6qdl-gw553x.dtsi
@@ -261,6 +261,37 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
+
+ adv7180: camera@20 {
+ compatible = "adi,adv7180";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adv7180>;
+ reg = <0x20>;
+ powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ adv7180_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
+ bus-width = <8>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&pcie {
@@ -340,6 +371,13 @@
};
&iomuxc {
+ pinctrl_adv7180: adv7180grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
+ >;
+ };
+
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
@@ -387,6 +425,22 @@
>;
};
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ >;
+ };
+
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
diff --git a/dts/src/arm/imx6qdl-icore-rqs.dtsi b/dts/src/arm/imx6qdl-icore-rqs.dtsi
index 5fab5be414..7ca291e9db 100644
--- a/dts/src/arm/imx6qdl-icore-rqs.dtsi
+++ b/dts/src/arm/imx6qdl-icore-rqs.dtsi
@@ -184,7 +184,6 @@
};
&ssi1 {
- fsl,mode = "i2s-slave";
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-nitrogen6x.dtsi b/dts/src/arm/imx6qdl-nitrogen6x.dtsi
index f22e587934..d309a4d0eb 100644
--- a/dts/src/arm/imx6qdl-nitrogen6x.dtsi
+++ b/dts/src/arm/imx6qdl-nitrogen6x.dtsi
@@ -108,6 +108,18 @@
startup-delay-us = <70000>;
enable-active-high;
};
+
+ reg_usb_h1_vbus: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
gpio-keys {
@@ -515,6 +527,12 @@
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
@@ -629,6 +647,7 @@
};
&usbh1 {
+ vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-sabrelite.dtsi b/dts/src/arm/imx6qdl-sabrelite.dtsi
index afe7449c47..756c5054f0 100644
--- a/dts/src/arm/imx6qdl-sabrelite.dtsi
+++ b/dts/src/arm/imx6qdl-sabrelite.dtsi
@@ -123,6 +123,18 @@
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
+
+ reg_usb_h1_vbus: regulator@7 {
+ compatible = "regulator-fixed";
+ reg = <7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
mipi_xclk: mipi_xclk {
@@ -610,6 +622,12 @@
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
@@ -705,6 +723,7 @@
};
&usbh1 {
+ vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-zii-rdu2.dtsi b/dts/src/arm/imx6qdl-zii-rdu2.dtsi
index 5d94b5ee6a..eeb7679fd3 100644
--- a/dts/src/arm/imx6qdl-zii-rdu2.dtsi
+++ b/dts/src/arm/imx6qdl-zii-rdu2.dtsi
@@ -59,6 +59,14 @@
pinctrl-0 = <&pinctrl_mdio1>;
gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
&gpio6 4 GPIO_ACTIVE_HIGH>;
+
+ phy: ethernet-phy@0 {
+ pinctrl-0 = <&pinctrl_rmii_phy_irq>;
+ pinctrl-names = "default";
+ reg = <0>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+ };
};
reg_28p0v: regulator-28p0v {
@@ -615,14 +623,106 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
+ phy-handle = <&phy>;
phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
phy-supply = <&reg_3p3v>;
status = "okay";
- fixed-link {
- speed = <100>;
- full-duplex;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ switch: switch@0 {
+ compatible = "marvell,mv88e6085";
+ pinctrl-0 = <&pinctrl_switch_irq>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ dsa,member = <0 0>;
+ eeprom-length = <512>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "gigabit_proc";
+ phy-handle = <&switchphy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "netaux";
+ phy-handle = <&switchphy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "cpu";
+ ethernet = <&fec>;
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "netright";
+ phy-handle = <&switchphy3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "netleft";
+ phy-handle = <&switchphy4>;
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switchphy0: switchphy@0 {
+ reg = <0>;
+ interrupt-parent = <&switch>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ switchphy1: switchphy@1 {
+ reg = <1>;
+ interrupt-parent = <&switch>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ switchphy2: switchphy@2 {
+ reg = <2>;
+ interrupt-parent = <&switch>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ switchphy3: switchphy@3 {
+ reg = <3>;
+ interrupt-parent = <&switch>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ switchphy4: switchphy@4 {
+ reg = <4>;
+ interrupt-parent = <&switch>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
};
};
@@ -840,6 +940,12 @@
>;
};
+ pinctrl_switch_irq: switchgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000
+ >;
+ };
+
pinctrl_tc358767: tc358767grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10
diff --git a/dts/src/arm/imx6qdl.dtsi b/dts/src/arm/imx6qdl.dtsi
index a9723b94ba..8884b4a3ca 100644
--- a/dts/src/arm/imx6qdl.dtsi
+++ b/dts/src/arm/imx6qdl.dtsi
@@ -769,6 +769,7 @@
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
+ value = <0x60>;
mask = <0x60>;
status = "disabled";
};
diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi
index 3243af4a99..3f76f98094 100644
--- a/dts/src/arm/imx6sl.dtsi
+++ b/dts/src/arm/imx6sl.dtsi
@@ -655,6 +655,7 @@
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
+ value = <0x60>;
mask = <0x60>;
status = "disabled";
};
diff --git a/dts/src/arm/imx6sx.dtsi b/dts/src/arm/imx6sx.dtsi
index f16b9df9d0..6c7eb54be9 100644
--- a/dts/src/arm/imx6sx.dtsi
+++ b/dts/src/arm/imx6sx.dtsi
@@ -710,6 +710,7 @@
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
+ value = <0x60>;
mask = <0x60>;
status = "disabled";
};
diff --git a/dts/src/arm/imx6ul-14x14-evk.dts b/dts/src/arm/imx6ul-14x14-evk.dts
index d2be8aa337..9c23e017d8 100644
--- a/dts/src/arm/imx6ul-14x14-evk.dts
+++ b/dts/src/arm/imx6ul-14x14-evk.dts
@@ -22,7 +22,7 @@
reg = <0x80000000 0x20000000>;
};
- backlight {
+ backlight_display: backlight-display {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -78,6 +78,17 @@
clocks = <&clks IMX6UL_CLK_SAI2>;
};
};
+
+ panel {
+ compatible = "innolux,at043tn24";
+ backlight = <&backlight_display>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
};
&clks {
@@ -139,31 +150,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
- display = <&display0>;
status = "okay";
- display0: display {
- bits-per-pixel = <16>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
-
- timing0: timing0 {
- clock-frequency = <9200000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <8>;
- hback-porch = <4>;
- hsync-len = <41>;
- vback-porch = <2>;
- vfront-porch = <4>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
};
};
};
@@ -316,7 +307,6 @@
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
>;
};
diff --git a/dts/src/arm/imx6ul-geam.dtsi b/dts/src/arm/imx6ul-geam.dts
index eb94d95680..571eea7f1c 100644
--- a/dts/src/arm/imx6ul-geam.dtsi
+++ b/dts/src/arm/imx6ul-geam.dts
@@ -40,11 +40,16 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+/dts-v1/;
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"
/ {
+ model = "Engicam GEAM6UL Starter Kit";
+ compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
+
memory {
reg = <0x80000000 0x08000000>;
};
@@ -87,18 +92,46 @@
regulator-always-on;
regulator-boot-on;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx6ul-geam-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ };
+ };
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_3p3v>;
+ status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_3p3v>;
+ status = "okay";
};
&fec1 {
@@ -144,6 +177,16 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6UL_CLK_OSC>;
+ clock-names = "mclk";
+ VDDA-supply = <&reg_3p3v>;
+ VDDIO-supply = <&reg_3p3v>;
+ VDDD-supply = <&reg_1p8v>;
+ };
};
&i2c2 {
@@ -158,6 +201,31 @@
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
+ status = "okay";
+
+ display0: display {
+ bits-per-pixel = <16>;
+ bus-width = <18>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <28000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hfront-porch = <30>;
+ hback-porch = <30>;
+ hsync-len = <64>;
+ vback-porch = <5>;
+ vfront-porch = <5>;
+ vsync-len = <20>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
};
&pwm8 {
@@ -178,6 +246,12 @@
status = "okay";
};
+&tsc {
+ measure-delay-time = <0x1ffff>;
+ pre-charge-time = <0x1fff>;
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
diff --git a/dts/src/arm/imx6ul-isiot-common.dtsi b/dts/src/arm/imx6ul-isiot-common.dtsi
deleted file mode 100644
index 2beaab6e27..0000000000
--- a/dts/src/arm/imx6ul-isiot-common.dtsi
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright (C) 2016 Amarula Solutions B.V.
- * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-&i2c1 {
- stmpe811: gpio-expander@44 {
- compatible = "st,stmpe811";
- reg = <0x44>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_stmpe>;
- interrupt-parent = <&gpio1>;
- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- stmpe: touchscreen {
- compatible = "st,stmpe-ts";
- st,sample-time = <4>;
- st,mod-12b = <1>;
- st,ref-sel = <0>;
- st,adc-freq = <1>;
- st,ave-ctrl = <1>;
- st,touch-det-delay = <2>;
- st,settling = <2>;
- st,fraction-z = <7>;
- st,i-drive = <1>;
- };
- };
-};
-
-&lcdif {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcdif_dat
- &pinctrl_lcdif_ctrl>;
- display = <&display0>;
- status = "okay";
-
- display0: display {
- bits-per-pixel = <16>;
- bus-width = <18>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <28000000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <30>;
- hback-porch = <30>;
- hsync-len = <64>;
- vback-porch = <5>;
- vfront-porch = <5>;
- vsync-len = <20>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- };
-};
-
-&iomuxc {
- pinctrl_lcdif_ctrl: lcdifctrlgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
- >;
- };
-
- pinctrl_lcdif_dat: lcdifdatgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
- >;
- };
-
- pinctrl_stmpe: stmpegrp {
- fsl,pins = <
- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
- >;
- };
-};
diff --git a/dts/src/arm/imx6ul-isiot-emmc.dts b/dts/src/arm/imx6ul-isiot-emmc.dts
index 73a1d0f0b9..f5b422898e 100644
--- a/dts/src/arm/imx6ul-isiot-emmc.dts
+++ b/dts/src/arm/imx6ul-isiot-emmc.dts
@@ -43,7 +43,6 @@
/dts-v1/;
#include "imx6ul-isiot.dtsi"
-#include "imx6ul-isiot-common.dtsi"
/ {
model = "Engicam Is.IoT MX6UL eMMC Starter kit";
diff --git a/dts/src/arm/imx6ul-isiot-nand.dts b/dts/src/arm/imx6ul-isiot-nand.dts
index da29a86eb6..de15e1c75d 100644
--- a/dts/src/arm/imx6ul-isiot-nand.dts
+++ b/dts/src/arm/imx6ul-isiot-nand.dts
@@ -43,7 +43,6 @@
/dts-v1/;
#include "imx6ul-isiot.dtsi"
-#include "imx6ul-isiot-common.dtsi"
/ {
model = "Engicam Is.IoT MX6UL NAND Starter kit";
diff --git a/dts/src/arm/imx6ul-isiot.dtsi b/dts/src/arm/imx6ul-isiot.dtsi
index ea30380ad7..950fb28b63 100644
--- a/dts/src/arm/imx6ul-isiot.dtsi
+++ b/dts/src/arm/imx6ul-isiot.dtsi
@@ -69,6 +69,68 @@
100>;
default-brightness-level = <100>;
};
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx6ul-isiot-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
};
&i2c1 {
@@ -76,6 +138,42 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6UL_CLK_OSC>;
+ clock-names = "mclk";
+ VDDA-supply = <&reg_3p3v>;
+ VDDIO-supply = <&reg_3p3v>;
+ VDDD-supply = <&reg_1p8v>;
+ };
+
+ stmpe811: gpio-expander@44 {
+ compatible = "st,stmpe811";
+ reg = <0x44>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_stmpe>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ stmpe: touchscreen {
+ compatible = "st,stmpe-ts";
+ st,sample-time = <4>;
+ st,mod-12b = <1>;
+ st,ref-sel = <0>;
+ st,adc-freq = <1>;
+ st,ave-ctrl = <1>;
+ st,touch-det-delay = <2>;
+ st,settling = <2>;
+ st,fraction-z = <7>;
+ st,i-drive = <1>;
+ };
+ };
};
&i2c2 {
@@ -85,6 +183,38 @@
status = "okay";
};
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+ &pinctrl_lcdif_ctrl>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display {
+ bits-per-pixel = <16>;
+ bus-width = <18>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <28000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hfront-porch = <30>;
+ hback-porch = <30>;
+ hsync-len = <64>;
+ vback-porch = <5>;
+ vfront-porch = <5>;
+ vsync-len = <20>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
@@ -115,6 +245,21 @@
};
&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
@@ -129,6 +274,38 @@
>;
};
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
+ >;
+ };
+
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
+ >;
+ };
+
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
@@ -145,6 +322,12 @@
>;
};
+ pinctrl_stmpe: stmpegrp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
diff --git a/dts/src/arm/imx6ul-liteboard.dts b/dts/src/arm/imx6ul-liteboard.dts
index ed1d891d6a..1d863a16bc 100644
--- a/dts/src/arm/imx6ul-liteboard.dts
+++ b/dts/src/arm/imx6ul-liteboard.dts
@@ -124,6 +124,10 @@
};
};
+&snvs_poweroff {
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
diff --git a/dts/src/arm/imx6ul.dtsi b/dts/src/arm/imx6ul.dtsi
index 6da2b77edd..f11a241a34 100644
--- a/dts/src/arm/imx6ul.dtsi
+++ b/dts/src/arm/imx6ul.dtsi
@@ -614,6 +614,7 @@
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
+ value = <0x60>;
mask = <0x60>;
status = "disabled";
};
diff --git a/dts/src/arm/imx7-colibri.dtsi b/dts/src/arm/imx7-colibri.dtsi
index d7753f7993..0a3915868a 100644
--- a/dts/src/arm/imx7-colibri.dtsi
+++ b/dts/src/arm/imx7-colibri.dtsi
@@ -106,6 +106,15 @@
fsl,magic-packet;
};
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,use-minimum-ecc;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ status = "okay";
+};
+
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
diff --git a/dts/src/arm/imx7d-sdb.dts b/dts/src/arm/imx7d-sdb.dts
index 0a24d1bf3c..44637cabcc 100644
--- a/dts/src/arm/imx7d-sdb.dts
+++ b/dts/src/arm/imx7d-sdb.dts
@@ -117,6 +117,37 @@
regulator-max-microvolt = <3300000>;
startup-delay-us = <200000>;
};
+
+ reg_lcd_3v3: regulator-lcd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_can2_3v3: regulator-can2-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "can2-3v3";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2_reg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
+ };
+
+ panel {
+ compatible = "innolux,at043tn24";
+ pinctrl-0 = <&pinctrl_backlight>;
+ enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ power-supply = <&reg_lcd_3v3>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
};
&adc1 {
@@ -168,6 +199,7 @@
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
+ phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
@@ -197,6 +229,13 @@
status = "okay";
};
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <&reg_can2_3v3>;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -285,8 +324,8 @@
};
vgen6_reg: vldo4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
regulator-always-on;
};
};
@@ -322,31 +361,11 @@
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
- display = <&display0>;
status = "okay";
- display0: display {
- bits-per-pixel = <16>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
-
- timing0: timing0 {
- clock-frequency = <9200000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <8>;
- hback-porch = <4>;
- hsync-len = <41>;
- vback-porch = <2>;
- vfront-porch = <4>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
};
};
};
@@ -356,12 +375,6 @@
status = "okay";
};
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
- status = "okay";
-};
-
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -488,6 +501,20 @@
>;
};
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
+ MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
+ >;
+ };
+
+ pinctrl_flexcan2_reg: flexcan2reggrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
+ >;
+ };
+
+
pinctrl_hog: hoggrp {
fsl,pins = <
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
@@ -701,9 +728,9 @@
>;
};
- pinctrl_pwm1: pwm1grp {
+ pinctrl_backlight: backlightgrp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
+ MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0
>;
};
};
diff --git a/dts/src/arm/imx7s.dtsi b/dts/src/arm/imx7s.dtsi
index 4cf6c458b5..82ad26e766 100644
--- a/dts/src/arm/imx7s.dtsi
+++ b/dts/src/arm/imx7s.dtsi
@@ -540,6 +540,7 @@
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
+ value = <0x60>;
mask = <0x60>;
};
@@ -1021,5 +1022,36 @@
status = "disabled";
};
};
+
+ dma_apbh: dma-apbh@33000000 {
+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x33000000 0x2000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+ };
+
+ gpmi: gpmi-nand@33002000{
+ compatible = "fsl,imx7d-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
+ <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+ clock-names = "gpmi_io", "gpmi_bch_apb";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
+ };
};
};
diff --git a/dts/src/arm/imx7ulp-pinfunc.h b/dts/src/arm/imx7ulp-pinfunc.h
new file mode 100644
index 0000000000..fe511775b5
--- /dev/null
+++ b/dts/src/arm/imx7ulp-pinfunc.h
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX7ULP_PINFUNC_H
+#define __DTS_IMX7ULP_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_conf_reg input_reg mux_mode input_val>
+ */
+
+#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
+#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
+#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
+#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
+#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1
+#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1
+#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1
+#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1
+#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1
+#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1
+#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1
+#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
+#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1
+#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1
+#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1
+#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1
+#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
+#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1
+#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1
+#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1
+#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
+#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1
+#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1
+#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1
+#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1
+#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1
+#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1
+#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1
+#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
+#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1
+#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1
+#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1
+#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1
+#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
+#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1
+#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1
+#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1
+#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
+#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1
+#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1
+#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1
+#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1
+#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
+#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1
+#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1
+#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1
+#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
+#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1
+#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1
+#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1
+#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1
+#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
+#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1
+#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1
+#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1
+#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1
+#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1
+#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1
+#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1
+#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1
+#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1
+#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1
+#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1
+#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1
+#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1
+#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1
+#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1
+#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1
+#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1
+#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1
+#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1
+#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1
+#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1
+#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1
+#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2
+#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2
+#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2
+#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2
+#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2
+#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2
+#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2
+#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2
+#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2
+#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2
+#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2
+#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2
+#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2
+#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2
+#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2
+#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2
+#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2
+#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2
+#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2
+#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2
+#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2
+#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2
+#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2
+#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2
+#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2
+#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2
+#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2
+#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2
+#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2
+#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2
+#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2
+#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2
+#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1
+#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2
+#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2
+#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2
+#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1
+#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2
+#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2
+#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2
+#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2
+#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2
+#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2
+#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2
+#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2
+#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2
+#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2
+#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2
+#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2
+#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2
+#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2
+#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2
+#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2
+#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2
+#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2
+#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2
+#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2
+#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2
+#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2
+#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3
+#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3
+#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3
+#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3
+#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3
+#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3
+#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3
+#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3
+#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3
+#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3
+#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2
+#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3
+#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3
+#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3
+#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2
+#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2
+#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3
+#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3
+#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2
+#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2
+#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3
+#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3
+#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3
+#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2
+#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2
+#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3
+#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3
+#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2
+#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3
+#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3
+#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3
+#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3
+#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2
+#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3
+#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3
+#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3
+#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2
+#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3
+#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3
+#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3
+#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3
+#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2
+#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3
+#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3
+#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3
+#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2
+#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3
+#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3
+#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3
+#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3
+#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2
+#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3
+#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3
+#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3
+#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2
+#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3
+#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3
+#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3
+#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3
+#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2
+#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3
+#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3
+#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2
+#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3
+#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3
+#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2
+#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3
+#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3
+#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2
+#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3
+#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3
+#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2
+#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3
+#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3
+#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0
+
+#endif /* __DTS_IMX7ULP_PINFUNC_H */
diff --git a/dts/src/arm/keystone-k2e-evm.dts b/dts/src/arm/keystone-k2e-evm.dts
index ae1ebe7ee0..f1f32c54e7 100644
--- a/dts/src/arm/keystone-k2e-evm.dts
+++ b/dts/src/arm/keystone-k2e-evm.dts
@@ -16,6 +16,19 @@
compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
model = "Texas Instruments Keystone 2 Edison EVM";
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_common_memory: dsp-common-memory@81f800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
soc {
clocks {
@@ -160,3 +173,8 @@
reg = <1>;
};
};
+
+&dsp0 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
diff --git a/dts/src/arm/keystone-k2e.dtsi b/dts/src/arm/keystone-k2e.dtsi
index 0dd4cdd6d4..819ab83459 100644
--- a/dts/src/arm/keystone-k2e.dtsi
+++ b/dts/src/arm/keystone-k2e.dtsi
@@ -45,6 +45,10 @@
};
};
+ aliases {
+ rproc0 = &dsp0;
+ };
+
soc {
/include/ "keystone-k2e-clocks.dtsi"
@@ -114,6 +118,22 @@
gpio,syscon-dev = <&devctrl 0x240>;
};
+ dsp0: dsp@10800000 {
+ compatible = "ti,k2e-dsp";
+ reg = <0x10800000 0x00080000>,
+ <0x10e00000 0x00008000>,
+ <0x10f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem0>;
+ ti,syscon-dev = <&devctrl 0x844>;
+ resets = <&pscrst 0>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <0 8>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio0 27 0>;
+ status = "disabled";
+ };
+
pcie1: pcie@21020000 {
compatible = "ti,keystone-pcie","snps,dw-pcie";
clocks = <&clkpcie1>;
diff --git a/dts/src/arm/keystone-k2g-evm.dts b/dts/src/arm/keystone-k2g-evm.dts
index 61883cb969..f462f10435 100644
--- a/dts/src/arm/keystone-k2g-evm.dts
+++ b/dts/src/arm/keystone-k2g-evm.dts
@@ -25,6 +25,26 @@
reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_common_memory: dsp-common-memory@81f800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
+ vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc0_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
&k2g_pinctrl {
@@ -34,6 +54,33 @@
K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
+
+ mmc0_pins: pinmux_mmc0_pins {
+ pinctrl-single,pins = <
+ K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
+ K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */
+ K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */
+ K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */
+ K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */
+ K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */
+ K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */
+ K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */
+ K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */
+ K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */
+ K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
+ K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
+ K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
+ K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
+ K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
+ K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
+ >;
+ };
};
&uart0 {
@@ -41,3 +88,27 @@
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&gpio1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&vcc3v3_dcin_reg>;
+ cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
+ status = "okay";
+};
+
+&dsp0 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
diff --git a/dts/src/arm/keystone-k2g-ice.dts b/dts/src/arm/keystone-k2g-ice.dts
index d820d37b51..78692745e0 100644
--- a/dts/src/arm/keystone-k2g-ice.dts
+++ b/dts/src/arm/keystone-k2g-ice.dts
@@ -17,6 +17,19 @@
device_type = "memory";
reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_common_memory: dsp-common-memory@81f800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
+ reusable;
+ status = "okay";
+ };
+ };
};
&k2g_pinctrl {
@@ -33,3 +46,8 @@
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&dsp0 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
diff --git a/dts/src/arm/keystone-k2g.dtsi b/dts/src/arm/keystone-k2g.dtsi
index a789f75a1e..826b286665 100644
--- a/dts/src/arm/keystone-k2g.dtsi
+++ b/dts/src/arm/keystone-k2g.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/keystone.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "ti,k2g","ti,keystone";
@@ -27,6 +28,7 @@
aliases {
serial0 = &uart0;
+ rproc0 = &dsp0;
};
cpus {
@@ -113,6 +115,24 @@
status = "disabled";
};
+ dcan0: can@0260B200 {
+ compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+ reg = <0x0260B200 0x200>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ power-domains = <&k2g_pds 0x0008>;
+ clocks = <&k2g_clks 0x0008 1>;
+ };
+
+ dcan1: can@0260B400 {
+ compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+ reg = <0x0260B400 0x200>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ power-domains = <&k2g_pds 0x0009>;
+ clocks = <&k2g_clks 0x0009 1>;
+ };
+
kirq0: keystone_irq@026202a0 {
compatible = "ti,keystone-irq";
interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
@@ -128,6 +148,22 @@
gpio,syscon-dev = <&devctrl 0x240>;
};
+ dsp0: dsp@10800000 {
+ compatible = "ti,k2g-dsp";
+ reg = <0x10800000 0x00100000>,
+ <0x10e00000 0x00008000>,
+ <0x10f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ power-domains = <&k2g_pds 0x0046>;
+ ti,syscon-dev = <&devctrl 0x844>;
+ resets = <&k2g_reset 0x0046 0x1>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <0 8>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio0 27 0>;
+ status = "disabled";
+ };
+
msgmgr: msgmgr@02a00000 {
compatible = "ti,k2g-message-manager";
#mbox-cells = <2>;
@@ -139,5 +175,173 @@
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ pmmc: pmmc@02921c00 {
+ compatible = "ti,k2g-sci";
+ /*
+ * In case of rare platforms that does not use k2g as
+ * system master, use /delete-property/
+ */
+ ti,system-reboot-controller;
+ mbox-names = "rx", "tx";
+ mboxes= <&msgmgr 5 2>,
+ <&msgmgr 0 0>;
+ reg-names = "debug_messages";
+ reg = <0x02921c00 0x400>;
+
+ k2g_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <1>;
+ };
+
+ k2g_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k2g_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ gpio0: gpio@2603000 {
+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+ reg = <0x02603000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <144>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k2g_clks 0x001b 0x0>;
+ clock-names = "gpio";
+ };
+
+ gpio1: gpio@260a000 {
+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+ reg = <0x0260a000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 446 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <68>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k2g_clks 0x001c 0x0>;
+ clock-names = "gpio";
+ };
+
+ edma0: edma@02700000 {
+ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
+ reg = <0x02700000 0x8000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "edma3_ccint", "emda3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
+
+ ti,edma-memcpy-channels = <32 33 34 35>;
+
+ power-domains = <&k2g_pds 0x3f>;
+ };
+
+ edma0_tptc0: tptc@02760000 {
+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x02760000 0x400>;
+ power-domains = <&k2g_pds 0x3f>;
+ };
+
+ edma0_tptc1: tptc@02768000 {
+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x02768000 0x400>;
+ power-domains = <&k2g_pds 0x3f>;
+ };
+
+ edma1: edma@02728000 {
+ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
+ reg = <0x02728000 0x8000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "edma3_ccint", "emda3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
+
+ /*
+ * memcpy is disabled, can be enabled with:
+ * ti,edma-memcpy-channels = <12 13 14 15>;
+ * for example.
+ */
+
+ power-domains = <&k2g_pds 0x4f>;
+ };
+
+ edma1_tptc0: tptc@027b0000 {
+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x027b0000 0x400>;
+ power-domains = <&k2g_pds 0x4f>;
+ };
+
+ edma1_tptc1: tptc@027b8000 {
+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x027b8000 0x400>;
+ power-domains = <&k2g_pds 0x4f>;
+ };
+
+ mmc0: mmc@23000000 {
+ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
+ reg = <0x23000000 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
+ dmas = <&edma1 24 0>, <&edma1 25 0>;
+ dma-names = "tx", "rx";
+ bus-width = <4>;
+ ti,needs-special-reset;
+ no-1-8-v;
+ max-frequency = <96000000>;
+ power-domains = <&k2g_pds 0xb>;
+ clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
+ clock-names = "fck", "mmchsdb_fck";
+ status = "disabled";
+ };
+
+ mmc1: mmc@23100000 {
+ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
+ reg = <0x23100000 0x400>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
+ dmas = <&edma1 26 0>, <&edma1 27 0>;
+ dma-names = "tx", "rx";
+ bus-width = <8>;
+ ti,needs-special-reset;
+ ti,non-removable;
+ max-frequency = <96000000>;
+ power-domains = <&k2g_pds 0xc>;
+ clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>;
+ clock-names = "fck", "mmchsdb_fck";
+ status = "disabled";
+ };
};
};
diff --git a/dts/src/arm/keystone-k2hk-evm.dts b/dts/src/arm/keystone-k2hk-evm.dts
index 2156ff92d0..6dd13b98aa 100644
--- a/dts/src/arm/keystone-k2hk-evm.dts
+++ b/dts/src/arm/keystone-k2hk-evm.dts
@@ -16,6 +16,19 @@
compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_common_memory: dsp-common-memory@81f800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
soc {
clocks {
refclksys: refclksys {
@@ -184,3 +197,43 @@
reg = <1>;
};
};
+
+&dsp0 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp1 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp2 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp3 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp4 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp5 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp6 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp7 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
diff --git a/dts/src/arm/keystone-k2hk.dtsi b/dts/src/arm/keystone-k2hk.dtsi
index 69d4494305..31dc00e4e5 100644
--- a/dts/src/arm/keystone-k2hk.dtsi
+++ b/dts/src/arm/keystone-k2hk.dtsi
@@ -45,6 +45,17 @@
};
};
+ aliases {
+ rproc0 = &dsp0;
+ rproc1 = &dsp1;
+ rproc2 = &dsp2;
+ rproc3 = &dsp3;
+ rproc4 = &dsp4;
+ rproc5 = &dsp5;
+ rproc6 = &dsp6;
+ rproc7 = &dsp7;
+ };
+
soc {
/include/ "keystone-k2hk-clocks.dtsi"
@@ -134,6 +145,134 @@
gpio,syscon-dev = <&devctrl 0x25c>;
};
+ dsp0: dsp@10800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x10800000 0x00100000>,
+ <0x10e00000 0x00008000>,
+ <0x10f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem0>;
+ ti,syscon-dev = <&devctrl 0x40>;
+ resets = <&pscrst 0>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <0 8>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio0 27 0>;
+ status = "disabled";
+ };
+
+ dsp1: dsp@11800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x11800000 0x00100000>,
+ <0x11e00000 0x00008000>,
+ <0x11f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem1>;
+ ti,syscon-dev = <&devctrl 0x44>;
+ resets = <&pscrst 1>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <1 9>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio1 27 0>;
+ status = "disabled";
+ };
+
+ dsp2: dsp@12800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x12800000 0x00100000>,
+ <0x12e00000 0x00008000>,
+ <0x12f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem2>;
+ ti,syscon-dev = <&devctrl 0x48>;
+ resets = <&pscrst 2>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <2 10>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio2 27 0>;
+ status = "disabled";
+ };
+
+ dsp3: dsp@13800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x13800000 0x00100000>,
+ <0x13e00000 0x00008000>,
+ <0x13f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem3>;
+ ti,syscon-dev = <&devctrl 0x4c>;
+ resets = <&pscrst 3>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <3 11>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio3 27 0>;
+ status = "disabled";
+ };
+
+ dsp4: dsp@14800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x14800000 0x00100000>,
+ <0x14e00000 0x00008000>,
+ <0x14f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem4>;
+ ti,syscon-dev = <&devctrl 0x50>;
+ resets = <&pscrst 4>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <4 12>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio4 27 0>;
+ status = "disabled";
+ };
+
+ dsp5: dsp@15800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x15800000 0x00100000>,
+ <0x15e00000 0x00008000>,
+ <0x15f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem5>;
+ ti,syscon-dev = <&devctrl 0x54>;
+ resets = <&pscrst 5>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <5 13>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio5 27 0>;
+ status = "disabled";
+ };
+
+ dsp6: dsp@16800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x16800000 0x00100000>,
+ <0x16e00000 0x00008000>,
+ <0x16f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem6>;
+ ti,syscon-dev = <&devctrl 0x58>;
+ resets = <&pscrst 6>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <6 14>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio6 27 0>;
+ status = "disabled";
+ };
+
+ dsp7: dsp@17800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x17800000 0x00100000>,
+ <0x17e00000 0x00008000>,
+ <0x17f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem7>;
+ ti,syscon-dev = <&devctrl 0x5c>;
+ resets = <&pscrst 7>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <7 15>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio7 27 0>;
+ status = "disabled";
+ };
+
mdio: mdio@02090300 {
compatible = "ti,keystone_mdio", "ti,davinci_mdio";
#address-cells = <1>;
diff --git a/dts/src/arm/keystone-k2l-evm.dts b/dts/src/arm/keystone-k2l-evm.dts
index 056b42f99d..528667618d 100644
--- a/dts/src/arm/keystone-k2l-evm.dts
+++ b/dts/src/arm/keystone-k2l-evm.dts
@@ -16,6 +16,19 @@
compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone";
model = "Texas Instruments Keystone 2 Lamarr EVM";
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_common_memory: dsp-common-memory@81f800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
soc {
clocks {
refclksys: refclksys {
@@ -133,3 +146,23 @@
reg = <1>;
};
};
+
+&dsp0 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp1 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp2 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
+
+&dsp3 {
+ memory-region = <&dsp_common_memory>;
+ status = "okay";
+};
diff --git a/dts/src/arm/keystone-k2l.dtsi b/dts/src/arm/keystone-k2l.dtsi
index 148650406c..4431310bc9 100644
--- a/dts/src/arm/keystone-k2l.dtsi
+++ b/dts/src/arm/keystone-k2l.dtsi
@@ -33,6 +33,13 @@
};
};
+ aliases {
+ rproc0 = &dsp0;
+ rproc1 = &dsp1;
+ rproc2 = &dsp2;
+ rproc3 = &dsp3;
+ };
+
soc {
/include/ "keystone-k2l-clocks.dtsi"
@@ -268,6 +275,70 @@
gpio,syscon-dev = <&devctrl 0x24c>;
};
+ dsp0: dsp@10800000 {
+ compatible = "ti,k2l-dsp";
+ reg = <0x10800000 0x00100000>,
+ <0x10e00000 0x00008000>,
+ <0x10f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem0>;
+ ti,syscon-dev = <&devctrl 0x844>;
+ resets = <&pscrst 0>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <0 8>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio0 27 0>;
+ status = "disabled";
+ };
+
+ dsp1: dsp@11800000 {
+ compatible = "ti,k2l-dsp";
+ reg = <0x11800000 0x00100000>,
+ <0x11e00000 0x00008000>,
+ <0x11f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem1>;
+ ti,syscon-dev = <&devctrl 0x848>;
+ resets = <&pscrst 1>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <1 9>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio1 27 0>;
+ status = "disabled";
+ };
+
+ dsp2: dsp@12800000 {
+ compatible = "ti,k2l-dsp";
+ reg = <0x12800000 0x00100000>,
+ <0x12e00000 0x00008000>,
+ <0x12f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem2>;
+ ti,syscon-dev = <&devctrl 0x84c>;
+ resets = <&pscrst 2>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <2 10>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio2 27 0>;
+ status = "disabled";
+ };
+
+ dsp3: dsp@13800000 {
+ compatible = "ti,k2l-dsp";
+ reg = <0x13800000 0x00100000>,
+ <0x13e00000 0x00008000>,
+ <0x13f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem3>;
+ ti,syscon-dev = <&devctrl 0x850>;
+ resets = <&pscrst 3>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <3 11>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio3 27 0>;
+ status = "disabled";
+ };
+
mdio: mdio@26200f00 {
compatible = "ti,keystone_mdio", "ti,davinci_mdio";
#address-cells = <1>;
diff --git a/dts/src/arm/kirkwood-6192.dtsi b/dts/src/arm/kirkwood-6192.dtsi
index d573e03f31..f003f3f1bd 100644
--- a/dts/src/arm/kirkwood-6192.dtsi
+++ b/dts/src/arm/kirkwood-6192.dtsi
@@ -1,6 +1,6 @@
/ {
mbus@f1000000 {
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
@@ -24,6 +24,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;
diff --git a/dts/src/arm/kirkwood-6281.dtsi b/dts/src/arm/kirkwood-6281.dtsi
index 748d0b62f2..47d4b3d3d9 100644
--- a/dts/src/arm/kirkwood-6281.dtsi
+++ b/dts/src/arm/kirkwood-6281.dtsi
@@ -1,6 +1,6 @@
/ {
mbus@f1000000 {
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
@@ -24,6 +24,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;
diff --git a/dts/src/arm/kirkwood-6282.dtsi b/dts/src/arm/kirkwood-6282.dtsi
index bb63d2d50f..a13dad0a7c 100644
--- a/dts/src/arm/kirkwood-6282.dtsi
+++ b/dts/src/arm/kirkwood-6282.dtsi
@@ -1,6 +1,6 @@
/ {
mbus@f1000000 {
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
@@ -28,6 +28,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;
@@ -45,6 +46,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 10>;
marvell,pcie-port = <1>;
diff --git a/dts/src/arm/kirkwood-98dx4122.dtsi b/dts/src/arm/kirkwood-98dx4122.dtsi
index 720c210d49..90d4d71b66 100644
--- a/dts/src/arm/kirkwood-98dx4122.dtsi
+++ b/dts/src/arm/kirkwood-98dx4122.dtsi
@@ -1,6 +1,6 @@
/ {
mbus@f1000000 {
- pciec: pcie-controller@82000000 {
+ pciec: pcie@82000000 {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
@@ -24,6 +24,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;
diff --git a/dts/src/arm/logicpd-torpedo-37xx-devkit.dts b/dts/src/arm/logicpd-torpedo-37xx-devkit.dts
index 43e9364083..b4575bbaf0 100644
--- a/dts/src/arm/logicpd-torpedo-37xx-devkit.dts
+++ b/dts/src/arm/logicpd-torpedo-37xx-devkit.dts
@@ -192,7 +192,7 @@
interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins &mmc1_cd>;
- cd-gpios = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; /* gpio127 */
+ cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */
vmmc-supply = <&vmmc1>;
bus-width = <4>;
cap-power-off-card;
diff --git a/dts/src/arm/ls1021a.dtsi b/dts/src/arm/ls1021a.dtsi
index 7bb9df2c14..9319e1f0f1 100644
--- a/dts/src/arm/ls1021a.dtsi
+++ b/dts/src/arm/ls1021a.dtsi
@@ -129,14 +129,14 @@
};
msi1: msi-controller@1570e00 {
- compatible = "fsl,1s1021a-msi";
+ compatible = "fsl,ls1021a-msi";
reg = <0x0 0x1570e00 0x0 0x8>;
msi-controller;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
};
msi2: msi-controller@1570e08 {
- compatible = "fsl,1s1021a-msi";
+ compatible = "fsl,ls1021a-msi";
reg = <0x0 0x1570e08 0x0 0x8>;
msi-controller;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
@@ -699,7 +699,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi1>;
+ msi-parent = <&msi1>, <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -722,7 +722,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi2>;
+ msi-parent = <&msi1>, <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/src/arm/meson.dtsi b/dts/src/arm/meson.dtsi
index 15204e4416..cd6ad072e7 100644
--- a/dts/src/arm/meson.dtsi
+++ b/dts/src/arm/meson.dtsi
@@ -86,14 +86,14 @@
};
uart_A: serial@84c0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
reg = <0x84c0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart_B: serial@84dc {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
reg = <0x84dc 0x18>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -108,6 +108,20 @@
status = "disabled";
};
+ pwm_ab: pwm@8550 {
+ compatible = "amlogic,meson-pwm";
+ reg = <0x8550 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm@8650 {
+ compatible = "amlogic,meson-pwm";
+ reg = <0x8650 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
saradc: adc@8680 {
compatible = "amlogic,meson-saradc";
reg = <0x8680 0x34>;
@@ -117,7 +131,7 @@
};
uart_C: serial@8700 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
reg = <0x8700 0x18>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -182,7 +196,7 @@
};
uart_AO: serial@4c0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
reg = <0x4c0 0x18>;
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -230,5 +244,13 @@
interrupt-names = "macirq";
status = "disabled";
};
+
+ ahb_sram: sram@d9000000 {
+ compatible = "mmio-sram";
+ reg = <0xd9000000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd9000000 0x20000>;
+ };
};
}; /* end of / */
diff --git a/dts/src/arm/meson6.dtsi b/dts/src/arm/meson6.dtsi
index 8557b6117a..ef281d2900 100644
--- a/dts/src/arm/meson6.dtsi
+++ b/dts/src/arm/meson6.dtsi
@@ -70,9 +70,37 @@
};
};
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
clk81: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
}; /* end of / */
+
+
+&uart_AO {
+ clocks = <&xtal>, <&clk81>, <&clk81>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_A {
+ clocks = <&xtal>, <&clk81>, <&clk81>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_B {
+ clocks = <&xtal>, <&clk81>, <&clk81>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_C {
+ clocks = <&xtal>, <&clk81>, <&clk81>;
+ clock-names = "xtal", "pclk", "baud";
+};
diff --git a/dts/src/arm/meson8.dtsi b/dts/src/arm/meson8.dtsi
index cada358289..b98d44fde6 100644
--- a/dts/src/arm/meson8.dtsi
+++ b/dts/src/arm/meson8.dtsi
@@ -168,10 +168,18 @@
&cbus {
clkc: clock-controller@4000 {
#clock-cells = <1>;
+ #reset-cells = <1>;
compatible = "amlogic,meson8-clkc";
reg = <0x8000 0x4>, <0x4000 0x460>;
};
+ pwm_ef: pwm@86c0 {
+ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
+ reg = <0x86c0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
pinctrl_cbus: pinctrl@9880 {
compatible = "amlogic,meson8-cbus-pinctrl";
reg = <0x9880 0x10>;
@@ -270,6 +278,14 @@
arm,filter-ranges = <0x100000 0xc0000000>;
};
+&pwm_ab {
+ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
+};
+
+&pwm_cd {
+ compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
+};
+
&saradc {
compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
clocks = <&clkc CLKID_XTAL>,
diff --git a/dts/src/arm/meson8b.dtsi b/dts/src/arm/meson8b.dtsi
index 72e4f425f1..bc278da7df 100644
--- a/dts/src/arm/meson8b.dtsi
+++ b/dts/src/arm/meson8b.dtsi
@@ -119,6 +119,7 @@
&cbus {
clkc: clock-controller@4000 {
#clock-cells = <1>;
+ #reset-cells = <1>;
compatible = "amlogic,meson8b-clkc";
reg = <0x8000 0x4>, <0x4000 0x460>;
};
@@ -129,20 +130,6 @@
#reset-cells = <1>;
};
- pwm_ab: pwm@8550 {
- compatible = "amlogic,meson8b-pwm";
- reg = <0x8550 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm_cd: pwm@8650 {
- compatible = "amlogic,meson8b-pwm";
- reg = <0x8650 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson8b-pwm";
reg = <0x86c0 0x10>;
@@ -150,12 +137,6 @@
status = "disabled";
};
- wdt: watchdog@9900 {
- compatible = "amlogic,meson8b-wdt";
- reg = <0x9900 0x8>;
- interrupts = <0 0 1>;
- };
-
pinctrl_cbus: pinctrl@9880 {
compatible = "amlogic,meson8b-cbus-pinctrl";
reg = <0x9880 0x10>;
@@ -193,6 +174,14 @@
arm,filter-ranges = <0x100000 0xc0000000>;
};
+&pwm_ab {
+ compatible = "amlogic,meson8b-pwm";
+};
+
+&pwm_cd {
+ compatible = "amlogic,meson8b-pwm";
+};
+
&saradc {
compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
clocks = <&clkc CLKID_XTAL>,
@@ -242,3 +231,7 @@
clock-names = "usb_general", "usb";
resets = <&reset RESET_USB_OTG>;
};
+
+&wdt {
+ compatible = "amlogic,meson8b-wdt";
+};
diff --git a/dts/src/arm/motorola-cpcap-mapphone.dtsi b/dts/src/arm/motorola-cpcap-mapphone.dtsi
index 1eb5da1dc8..4d61e5b133 100644
--- a/dts/src/arm/motorola-cpcap-mapphone.dtsi
+++ b/dts/src/arm/motorola-cpcap-mapphone.dtsi
@@ -255,5 +255,6 @@
regulator-min-microvolt = <2775000>;
regulator-max-microvolt = <2775000>;
regulator-enable-ramp-delay = <1000>;
+ regulator-initial-mode = <0x00>; /* NORMAL */
};
};
diff --git a/dts/src/arm/mt2701.dtsi b/dts/src/arm/mt2701.dtsi
index f1efdc6365..afe12e5b51 100644
--- a/dts/src/arm/mt2701.dtsi
+++ b/dts/src/arm/mt2701.dtsi
@@ -13,6 +13,7 @@
*/
#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -533,6 +534,7 @@
compatible = "mediatek,mt2701-smi-larb";
reg = <0 0x14010000 0 0x1000>;
mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <0>;
clocks = <&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB0>;
clock-names = "apb", "smi";
@@ -549,6 +551,7 @@
compatible = "mediatek,mt2701-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <2>;
clocks = <&imgsys CLK_IMG_SMI_COMM>,
<&imgsys CLK_IMG_SMI_COMM>;
clock-names = "apb", "smi";
@@ -579,6 +582,7 @@
compatible = "mediatek,mt2701-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <1>;
clocks = <&vdecsys CLK_VDEC_CKGEN>,
<&vdecsys CLK_VDEC_LARB>;
clock-names = "apb", "smi";
@@ -591,12 +595,114 @@
#clock-cells = <1>;
};
+ usb0: usb@1a1c0000 {
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0 0x1a1c0000 0 0x1000>,
+ <0 0x1a1c4700 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
+ <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy0: usb-phy@1a1c4000 {
+ compatible = "mediatek,mt2701-u3phy";
+ reg = <0 0x1a1c4000 0 0x0700>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a1c4800 {
+ reg = <0 0x1a1c4800 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@1a1c4900 {
+ reg = <0 0x1a1c4900 0 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ usb1: usb@1a240000 {
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0 0x1a240000 0 0x1000>,
+ <0 0x1a244700 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
+ <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy@1a244000 {
+ compatible = "mediatek,mt2701-u3phy";
+ reg = <0 0x1a244000 0 0x0700>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port1: usb-phy@1a244800 {
+ reg = <0 0x1a244800 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port1: usb-phy@1a244900 {
+ reg = <0 0x1a244900 0 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
ethsys: syscon@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
+ eth: ethernet@1b100000 {
+ compatible = "mediatek,mt2701-eth", "syscon";
+ reg = <0 0x1b100000 0 0x20000>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&ethsys CLK_ETHSYS_ESW>,
+ <&ethsys CLK_ETHSYS_GP1>,
+ <&ethsys CLK_ETHSYS_GP2>,
+ <&apmixedsys CLK_APMIXED_TRGPLL>;
+ clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
+ resets = <&ethsys MT2701_ETHSYS_FE_RST>,
+ <&ethsys MT2701_ETHSYS_GMAC_RST>,
+ <&ethsys MT2701_ETHSYS_PPE_RST>;
+ reset-names = "fe", "gmac", "ppe";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ mediatek,ethsys = <&ethsys>;
+ mediatek,pctl = <&syscfg_pctl_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
bdpsys: syscon@1c000000 {
compatible = "mediatek,mt2701-bdpsys", "syscon";
reg = <0 0x1c000000 0 0x1000>;
diff --git a/dts/src/arm/mt6323.dtsi b/dts/src/arm/mt6323.dtsi
new file mode 100644
index 0000000000..7c783d6c75
--- /dev/null
+++ b/dts/src/arm/mt6323.dtsi
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: John Crispin <john@phrozen.org>
+ * Sean Wang <sean.wang@mediatek.com>
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&pwrap {
+ pmic: mt6323 {
+ compatible = "mediatek,mt6323";
+ interrupt-parent = <&pio>;
+ interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ mt6323regulator: mt6323regulator{
+ compatible = "mediatek,mt6323-regulator";
+
+ mt6323_vproc_reg: buck_vproc{
+ regulator-name = "vproc";
+ regulator-min-microvolt = < 700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vsys_reg: buck_vsys{
+ regulator-name = "vsys";
+ regulator-min-microvolt = <1400000>;
+ regulator-max-microvolt = <2987500>;
+ regulator-ramp-delay = <25000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vpa_reg: buck_vpa{
+ regulator-name = "vpa";
+ regulator-min-microvolt = < 500000>;
+ regulator-max-microvolt = <3650000>;
+ };
+
+ mt6323_vtcxo_reg: ldo_vtcxo{
+ regulator-name = "vtcxo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <90>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vcn28_reg: ldo_vcn28{
+ regulator-name = "vcn28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <185>;
+ };
+
+ mt6323_vcn33_bt_reg: ldo_vcn33_bt{
+ regulator-name = "vcn33_bt";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-enable-ramp-delay = <185>;
+ };
+
+ mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
+ regulator-name = "vcn33_wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-enable-ramp-delay = <185>;
+ };
+
+ mt6323_va_reg: ldo_va{
+ regulator-name = "va";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vcama_reg: ldo_vcama{
+ regulator-name = "vcama";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vio28_reg: ldo_vio28{
+ regulator-name = "vio28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vusb_reg: ldo_vusb{
+ regulator-name = "vusb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-boot-on;
+ };
+
+ mt6323_vmc_reg: ldo_vmc{
+ regulator-name = "vmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <36>;
+ regulator-boot-on;
+ };
+
+ mt6323_vmch_reg: ldo_vmch{
+ regulator-name = "vmch";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <36>;
+ regulator-boot-on;
+ };
+
+ mt6323_vemc3v3_reg: ldo_vemc3v3{
+ regulator-name = "vemc3v3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <36>;
+ regulator-boot-on;
+ };
+
+ mt6323_vgp1_reg: ldo_vgp1{
+ regulator-name = "vgp1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vgp2_reg: ldo_vgp2{
+ regulator-name = "vgp2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vgp3_reg: ldo_vgp3{
+ regulator-name = "vgp3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vcn18_reg: ldo_vcn18{
+ regulator-name = "vcn18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vsim1_reg: ldo_vsim1{
+ regulator-name = "vsim1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vsim2_reg: ldo_vsim2{
+ regulator-name = "vsim2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vrtc_reg: ldo_vrtc{
+ regulator-name = "vrtc";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vcamaf_reg: ldo_vcamaf{
+ regulator-name = "vcamaf";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vibr_reg: ldo_vibr{
+ regulator-name = "vibr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <36>;
+ };
+
+ mt6323_vrf18_reg: ldo_vrf18{
+ regulator-name = "vrf18";
+ regulator-min-microvolt = <1825000>;
+ regulator-max-microvolt = <1825000>;
+ regulator-enable-ramp-delay = <187>;
+ };
+
+ mt6323_vm_reg: ldo_vm{
+ regulator-name = "vm";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vio18_reg: ldo_vio18{
+ regulator-name = "vio18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6323_vcamd_reg: ldo_vcamd{
+ regulator-name = "vcamd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+
+ mt6323_vcamio_reg: ldo_vcamio{
+ regulator-name = "vcamio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <216>;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/mt7623-evb.dts b/dts/src/arm/mt7623-evb.dts
deleted file mode 100644
index b60b41cad5..0000000000
--- a/dts/src/arm/mt7623-evb.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2016 MediaTek Inc.
- * Author: John Crispin <john@phrozen.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/dts-v1/;
-#include "mt7623.dtsi"
-
-/ {
- model = "MediaTek MT7623 evaluation board";
- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory {
- reg = <0 0x80000000 0 0x40000000>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
diff --git a/dts/src/arm/mt7623.dtsi b/dts/src/arm/mt7623.dtsi
index d81158b2b0..ec8a07415c 100644
--- a/dts/src/arm/mt7623.dtsi
+++ b/dts/src/arm/mt7623.dtsi
@@ -21,36 +21,99 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt2701-resets.h>
+#include <dt-bindings/thermal/thermal.h>
#include "skeleton64.dtsi"
/ {
compatible = "mediatek,mt7623";
interrupt-parent = <&sysirq>;
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-98000000 {
+ opp-hz = /bits/ 64 <98000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-198000000 {
+ opp-hz = /bits/ 64 <198000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-398000000 {
+ opp-hz = /bits/ 64 <398000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-598000000 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-747500000 {
+ opp-hz = /bits/ 64 <747500000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-1040000000 {
+ opp-hz = /bits/ 64 <1040000000>;
+ opp-microvolt = <1150000>;
+ };
+
+ opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1200000>;
+ };
+
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1300000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "mediatek,mt6589-smp";
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
+ clock-frequency = <1300000000>;
};
- cpu@1 {
+
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clock-frequency = <1300000000>;
};
- cpu@2 {
+
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clock-frequency = <1300000000>;
};
- cpu@3 {
+
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clock-frequency = <1300000000>;
};
};
@@ -74,6 +137,58 @@
clock-output-names = "clk26m";
};
+ thermal-zones {
+ cpu_thermal: cpu_thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ cpu_passive: cpu_passive {
+ temperature = <47000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_active: cpu_active {
+ temperature = <67000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu_hot {
+ temperature = <87000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_crit {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_passive>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_active>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map2 {
+ trip = <&cpu_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
@@ -172,7 +287,7 @@
clock-names = "spi", "wrap";
};
- cir: cir@0x10013000 {
+ cir: cir@10013000 {
compatible = "mediatek,mt7623-cir";
reg = <0 0x10013000 0 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
@@ -193,7 +308,7 @@
efuse: efuse@10206000 {
compatible = "mediatek,mt7623-efuse",
"mediatek,mt8173-efuse";
- reg = <0 0x10206000 0 0x1000>;
+ reg = <0 0x10206000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
thermal_calibration_data: calib@424 {
@@ -371,6 +486,31 @@
nvmem-cell-names = "calibration-data";
};
+ nandc: nfi@1100d000 {
+ compatible = "mediatek,mt7623-nfc",
+ "mediatek,mt2701-nfc";
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ clocks = <&pericfg CLK_PERI_NFI>,
+ <&pericfg CLK_PERI_NFI_PAD>;
+ clock-names = "nfi_clk", "pad_clk";
+ status = "disabled";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ bch: ecc@1100e000 {
+ compatible = "mediatek,mt7623-ecc",
+ "mediatek,mt2701-ecc";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_ECC>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
+
spi1: spi@11016000 {
compatible = "mediatek,mt7623-spi",
"mediatek,mt2701-spi";
@@ -399,31 +539,6 @@
status = "disabled";
};
- nandc: nfi@1100d000 {
- compatible = "mediatek,mt7623-nfc",
- "mediatek,mt2701-nfc";
- reg = <0 0x1100d000 0 0x1000>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
- clocks = <&pericfg CLK_PERI_NFI>,
- <&pericfg CLK_PERI_NFI_PAD>;
- clock-names = "nfi_clk", "pad_clk";
- status = "disabled";
- ecc-engine = <&bch>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- bch: ecc@1100e000 {
- compatible = "mediatek,mt7623-ecc",
- "mediatek,mt2701-ecc";
- reg = <0 0x1100e000 0 0x1000>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_NFI_ECC>;
- clock-names = "nfiecc_clk";
- status = "disabled";
- };
-
afe: audio-controller@11220000 {
compatible = "mediatek,mt7623-audio",
"mediatek,mt2701-audio";
@@ -538,13 +653,22 @@
compatible = "mediatek,mt7623-mmc",
"mediatek,mt8135-mmc";
reg = <0 0x11240000 0 0x1000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_1>,
<&topckgen CLK_TOP_MSDC30_1_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt7623-hifsys",
+ "mediatek,mt2701-hifsys",
+ "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
usb1: usb@1a1c0000 {
compatible = "mediatek,mt7623-xhci",
"mediatek,mt8173-xhci";
@@ -561,7 +685,8 @@
};
u3phy1: usb-phy@1a1c4000 {
- compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
+ compatible = "mediatek,mt7623-u3phy",
+ "mediatek,mt2701-u3phy";
reg = <0 0x1a1c4000 0 0x0700>;
clocks = <&clk26m>;
clock-names = "u3phya_ref";
@@ -599,7 +724,8 @@
};
u3phy2: usb-phy@1a244000 {
- compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
+ compatible = "mediatek,mt7623-u3phy",
+ "mediatek,mt2701-u3phy";
reg = <0 0x1a244000 0 0x0700>;
clocks = <&clk26m>;
clock-names = "u3phya_ref";
@@ -621,15 +747,6 @@
};
};
- hifsys: syscon@1a000000 {
- compatible = "mediatek,mt7623-hifsys",
- "mediatek,mt2701-hifsys",
- "syscon";
- reg = <0 0x1a000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7623-ethsys",
"mediatek,mt2701-ethsys",
@@ -639,7 +756,9 @@
};
eth: ethernet@1b100000 {
- compatible = "mediatek,mt2701-eth", "syscon";
+ compatible = "mediatek,mt7623-eth",
+ "mediatek,mt2701-eth",
+ "syscon";
reg = <0 0x1b100000 0 0x20000>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
@@ -650,6 +769,10 @@
<&ethsys CLK_ETHSYS_GP2>,
<&apmixedsys CLK_APMIXED_TRGPLL>;
clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
+ resets = <&ethsys MT2701_ETHSYS_FE_RST>,
+ <&ethsys MT2701_ETHSYS_GMAC_RST>,
+ <&ethsys MT2701_ETHSYS_PPE_RST>;
+ reset-names = "fe", "gmac", "ppe";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
mediatek,ethsys = <&ethsys>;
mediatek,pctl = <&syscfg_pctl_a>;
diff --git a/dts/src/arm/mt7623n-bananapi-bpi-r2.dts b/dts/src/arm/mt7623n-bananapi-bpi-r2.dts
new file mode 100644
index 0000000000..688a86378c
--- /dev/null
+++ b/dts/src/arm/mt7623n-bananapi-bpi-r2.dts
@@ -0,0 +1,487 @@
+/*
+ * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "mt7623.dtsi"
+#include "mt6323.dtsi"
+
+/ {
+ model = "Bananapi BPI-R2";
+ compatible = "bananapi,bpi-r2", "mediatek,mt7623";
+
+ aliases {
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ cpus {
+ cpu@0 {
+ proc-supply = <&mt6323_vproc_reg>;
+ };
+
+ cpu@1 {
+ proc-supply = <&mt6323_vproc_reg>;
+ };
+
+ cpu@2 {
+ proc-supply = <&mt6323_vproc_reg>;
+ };
+
+ cpu@3 {
+ proc-supply = <&mt6323_vproc_reg>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_pins_a>;
+
+ factory {
+ label = "factory";
+ linux,code = <BTN_0>;
+ gpios = <&pio 256 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_a>;
+
+ blue {
+ label = "bpi-r2:pio:blue";
+ gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ green {
+ label = "bpi-r2:pio:green";
+ gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ red {
+ label = "bpi-r2:pio:red";
+ gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ memory@80000000 {
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+};
+
+&cir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cir_pins_a>;
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&eth {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "trgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ compatible = "mediatek,mt7530";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ pinctrl-names = "default";
+ reset-gpios = <&pio 33 0>;
+ core-supply = <&mt6323_vpa_reg>;
+ io-supply = <&mt6323_vemc3v3_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan0";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan1";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan3";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "trgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ status = "okay";
+ bus-width = <8>;
+ max-frequency = <50000000>;
+ cap-mmc-highspeed;
+ vmmc-supply = <&mt6323_vemc3v3_reg>;
+ vqmmc-supply = <&mt6323_vio18_reg>;
+ non-removable;
+};
+
+&mmc1 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_uhs>;
+ status = "okay";
+ bus-width = <4>;
+ max-frequency = <50000000>;
+ cap-sd-highspeed;
+ cd-gpios = <&pio 261 0>;
+ vmmc-supply = <&mt6323_vmch_reg>;
+ vqmmc-supply = <&mt6323_vio18_reg>;
+};
+
+&pio {
+ cir_pins_a:cir@0 {
+ pins_cir {
+ pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
+ bias-disable;
+ };
+ };
+
+ i2c0_pins_a: i2c@0 {
+ pins_i2c0 {
+ pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
+ <MT7623_PIN_76_SCL0_FUNC_SCL0>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c@1 {
+ pin_i2c1 {
+ pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
+ <MT7623_PIN_58_SCL1_FUNC_SCL1>;
+ bias-disable;
+ };
+ };
+
+ i2s0_pins_a: i2s@0 {
+ pin_i2s0 {
+ pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
+ <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
+ <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
+ <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
+ <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
+ drive-strength = <MTK_DRIVE_12mA>;
+ bias-pull-down;
+ };
+ };
+
+ i2s1_pins_a: i2s@1 {
+ pin_i2s1 {
+ pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
+ <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
+ <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
+ <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
+ <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
+ drive-strength = <MTK_DRIVE_12mA>;
+ bias-pull-down;
+ };
+ };
+
+ key_pins_a: keys@0 {
+ pins_keys {
+ pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
+ <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
+ input-enable;
+ };
+ };
+
+ led_pins_a: leds@0 {
+ pins_leds {
+ pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
+ <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
+ <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ pins_cmd_dat {
+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
+ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins_clk {
+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
+ bias-pull-down;
+ };
+
+ pins_rst {
+ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0 {
+ pins_cmd_dat {
+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
+ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_2mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins_clk {
+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_2mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins_rst {
+ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_pins_default: mmc1default {
+ pins_cmd_dat {
+ pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
+ <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
+ <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
+ <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
+ <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins_clk {
+ pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
+ bias-pull-down;
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+
+ pins_wp {
+ pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins_insert {
+ pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_pins_uhs: mmc1 {
+ pins_cmd_dat {
+ pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
+ <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
+ <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
+ <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
+ <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins_clk {
+ pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+ };
+
+ pwm_pins_a: pwm@0 {
+ pins_pwm {
+ pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
+ <MT7623_PIN_204_PWM1_FUNC_PWM1>,
+ <MT7623_PIN_205_PWM2_FUNC_PWM2>,
+ <MT7623_PIN_206_PWM3_FUNC_PWM3>,
+ <MT7623_PIN_207_PWM4_FUNC_PWM4>;
+ };
+ };
+
+ spi0_pins_a: spi@0 {
+ pins_spi {
+ pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
+ <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
+ <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
+ <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
+ bias-disable;
+ };
+ };
+
+ uart0_pins_a: uart@0 {
+ pins_dat {
+ pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
+ <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
+ };
+ };
+
+ uart1_pins_a: uart@1 {
+ pins_dat {
+ pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
+ <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins_a>;
+ status = "okay";
+};
+
+&pwrap {
+ mt6323 {
+ mt6323led: led {
+ compatible = "mediatek,mt6323-led";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ label = "bpi-r2:isink:green";
+ default-state = "off";
+ };
+
+ led@1 {
+ reg = <1>;
+ label = "bpi-r2:isink:red";
+ default-state = "off";
+ };
+
+ led@2 {
+ reg = <2>;
+ label = "bpi-r2:isink:blue";
+ default-state = "off";
+ };
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>;
+ status = "disabled";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb1 {
+ vusb33-supply = <&mt6323_vusb_reg>;
+ status = "okay";
+};
+
+&usb2 {
+ vusb33-supply = <&mt6323_vusb_reg>;
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
+
diff --git a/dts/src/arm/mt7623n-rfb-nand.dts b/dts/src/arm/mt7623n-rfb-nand.dts
new file mode 100644
index 0000000000..17c578f0d2
--- /dev/null
+++ b/dts/src/arm/mt7623n-rfb-nand.dts
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: John Crispin <john@phrozen.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt7623n-rfb.dtsi"
+
+/ {
+ model = "MediaTek MT7623N NAND reference board";
+ compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+};
+
+&bch {
+ status = "okay";
+};
+
+&nandc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_default>;
+
+ nand@0 {
+ reg = <0>;
+ spare_per_sector = <64>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <12>;
+ nand-ecc-step-size = <1024>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "preloader";
+ reg = <0x0 0x40000>;
+ };
+
+ partition@40000 {
+ label = "uboot";
+ reg = <0x40000 0x80000>;
+ };
+
+ partition@C0000 {
+ label = "uboot-env";
+ reg = <0xC0000 0x40000>;
+ };
+
+ partition@140000 {
+ label = "bootimg";
+ reg = <0x140000 0x2000000>;
+ };
+
+ partition@2140000 {
+ label = "recovery";
+ reg = <0x2140000 0x2000000>;
+ };
+
+ partition@4140000 {
+ label = "rootfs";
+ reg = <0x4140000 0x1000000>;
+ };
+
+ partition@5140000 {
+ label = "usrdata";
+ reg = <0x5140000 0x1000000>;
+ };
+ };
+ };
+};
+
+&pio {
+ nand_pins_default: nanddefault {
+ pins_ale {
+ pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins_dat {
+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
+ <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up;
+ };
+
+ pins_we {
+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
+ };
+ };
+};
diff --git a/dts/src/arm/mt7623n-rfb.dtsi b/dts/src/arm/mt7623n-rfb.dtsi
new file mode 100644
index 0000000000..256c5fd947
--- /dev/null
+++ b/dts/src/arm/mt7623n-rfb.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: John Crispin <john@phrozen.org>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt7623.dtsi"
+#include "mt6323.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ cpus {
+ cpu0 {
+ proc-supply = <&mt6323_vproc_reg>;
+ };
+
+ cpu1 {
+ proc-supply = <&mt6323_vproc_reg>;
+ };
+
+ cpu2 {
+ proc-supply = <&mt6323_vproc_reg>;
+ };
+
+ cpu3 {
+ proc-supply = <&mt6323_vproc_reg>;
+ };
+ };
+
+ memory@80000000 {
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+
+ usb_p1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&mt6323_vemc3v3_reg>;
+ vqmmc-supply = <&mt6323_vio18_reg>;
+};
+
+&mmc1 {
+ vmmc-supply = <&mt6323_vmch_reg>;
+ vqmmc-supply = <&mt6323_vmc_reg>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <&usb_p1_vbus>;
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/omap2420-n8x0-common.dtsi b/dts/src/arm/omap2420-n8x0-common.dtsi
index 7e5ffc583c..91886231e5 100644
--- a/dts/src/arm/omap2420-n8x0-common.dtsi
+++ b/dts/src/arm/omap2420-n8x0-common.dtsi
@@ -15,8 +15,8 @@
>;
#address-cells = <1>;
#size-cells = <0>;
- retu_mfd: retu@1 {
- compatible = "retu-mfd";
+ retu: retu@1 {
+ compatible = "nokia,retu";
interrupt-parent = <&gpio4>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
reg = <0x1>;
diff --git a/dts/src/arm/omap3-beagle-xm.dts b/dts/src/arm/omap3-beagle-xm.dts
index 673cee2234..683b96a8f7 100644
--- a/dts/src/arm/omap3-beagle-xm.dts
+++ b/dts/src/arm/omap3-beagle-xm.dts
@@ -299,7 +299,7 @@
&mmc1 {
vmmc-supply = <&vmmc1>;
- vmmc_aux-supply = <&vsim>;
+ vqmmc-supply = <&vsim>;
bus-width = <8>;
};
diff --git a/dts/src/arm/omap3-beagle.dts b/dts/src/arm/omap3-beagle.dts
index 4be85ce59d..4d2eaf843f 100644
--- a/dts/src/arm/omap3-beagle.dts
+++ b/dts/src/arm/omap3-beagle.dts
@@ -283,7 +283,7 @@
&mmc1 {
vmmc-supply = <&vmmc1>;
- vmmc_aux-supply = <&vsim>;
+ vqmmc-supply = <&vsim>;
bus-width = <8>;
};
diff --git a/dts/src/arm/omap3-cm-t3517.dts b/dts/src/arm/omap3-cm-t3517.dts
index 53ae04f910..3d293b345e 100644
--- a/dts/src/arm/omap3-cm-t3517.dts
+++ b/dts/src/arm/omap3-cm-t3517.dts
@@ -129,7 +129,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&wl12xx_vmmc2>;
- vmmc_aux-supply = <&wl12xx_vaux2>;
+ vqmmc-supply = <&wl12xx_vaux2>;
non-removable;
bus-width = <4>;
cap-power-off-card;
diff --git a/dts/src/arm/omap3-cm-t3730.dts b/dts/src/arm/omap3-cm-t3730.dts
index 2294f5b0aa..bdf4b7fdda 100644
--- a/dts/src/arm/omap3-cm-t3730.dts
+++ b/dts/src/arm/omap3-cm-t3730.dts
@@ -69,7 +69,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&wl12xx_vmmc2>;
- vmmc_aux-supply = <&wl12xx_vaux2>;
+ vqmmc-supply = <&wl12xx_vaux2>;
non-removable;
bus-width = <4>;
cap-power-off-card;
diff --git a/dts/src/arm/omap3-devkit8000-common.dtsi b/dts/src/arm/omap3-devkit8000-common.dtsi
index 82aa9c4a0f..0c0bb1b01b 100644
--- a/dts/src/arm/omap3-devkit8000-common.dtsi
+++ b/dts/src/arm/omap3-devkit8000-common.dtsi
@@ -149,7 +149,7 @@
&mmc1 {
vmmc-supply = <&vmmc1>;
- vmmc_aux-supply = <&vsim>;
+ vqmmc-supply = <&vsim>;
bus-width = <8>;
};
diff --git a/dts/src/arm/omap3-evm-common.dtsi b/dts/src/arm/omap3-evm-common.dtsi
index 2b1d6977a5..ff35803088 100644
--- a/dts/src/arm/omap3-evm-common.dtsi
+++ b/dts/src/arm/omap3-evm-common.dtsi
@@ -115,7 +115,7 @@
&mmc1 {
interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
vmmc-supply = <&vmmc1>;
- vmmc_aux-supply = <&vsim>;
+ vqmmc-supply = <&vsim>;
bus-width = <8>;
};
diff --git a/dts/src/arm/omap3-n900.dts b/dts/src/arm/omap3-n900.dts
index 49f37084e4..26c20e1167 100644
--- a/dts/src/arm/omap3-n900.dts
+++ b/dts/src/arm/omap3-n900.dts
@@ -144,6 +144,15 @@
io-channel-names = "temp", "bsi", "vbat";
};
+ rear_camera: camera@0 {
+ compatible = "linux,camera";
+
+ module {
+ model = "TCM8341MD";
+ sensor = <&cam1>;
+ };
+ };
+
pwm9: dmtimer-pwm {
compatible = "ti,omap-dmtimer-pwm";
#pwm-cells = <3>;
@@ -164,6 +173,31 @@
};
};
+&isp {
+ vdds_csib-supply = <&vaux2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_pins>;
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ csi_isp: endpoint {
+ remote-endpoint = <&csi_cam1>;
+ bus-type = <3>; /* CCP2 */
+ clock-lanes = <1>;
+ data-lanes = <0>;
+ lane-polarity = <0 0>;
+ clock-inv = <0>;
+ /* Select strobe = <1> for back camera, <0> for front camera */
+ strobe = <1>;
+ crc = <0>;
+ };
+ };
+ };
+};
+
&omap3_pmx_core {
pinctrl-names = "default";
@@ -328,6 +362,22 @@
OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
>;
};
+
+ camera_pins: pinmux_camera {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */
+ OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */
+ OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */
+ OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */
+ OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */
+ OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */
+ OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */
+ OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */
+ OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */
+ OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */
+ OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */
+ >;
+ };
};
&i2c1 {
@@ -726,6 +776,40 @@
st,max-limit-y = <32>;
st,max-limit-z = <32>;
};
+
+ cam1: camera@3e {
+ compatible = "toshiba,et8ek8";
+ reg = <0x3e>;
+
+ vana-supply = <&vaux4>;
+
+ clocks = <&isp 0>;
+ clock-names = "extclk";
+ clock-frequency = <9600000>;
+
+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
+
+ port {
+ csi_cam1: endpoint {
+ bus-type = <3>; /* CCP2 */
+ strobe = <1>;
+ clock-inv = <0>;
+ crc = <1>;
+
+ remote-endpoint = <&csi_isp>;
+ };
+ };
+ };
+
+ /* D/A converter for auto-focus */
+ ad5820: dac@0c {
+ compatible = "adi,ad5820";
+ reg = <0x0c>;
+
+ VANA-supply = <&vaux4>;
+
+ #io-channel-cells = <0>;
+ };
};
&mmc1 {
@@ -733,6 +817,9 @@
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
bus-width = <4>;
+ /* For debugging, it is often good idea to remove this GPIO.
+ It means you can remove back cover (to reboot by removing
+ battery) and still use the MMC card. */
cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
};
@@ -741,7 +828,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&vaux3>;
- vmmc_aux-supply = <&vsim>;
+ vqmmc-supply = <&vsim>;
bus-width = <8>;
non-removable;
no-sdio;
diff --git a/dts/src/arm/omap3-n950-n9.dtsi b/dts/src/arm/omap3-n950-n9.dtsi
index df3366fa54..cb47ae79a5 100644
--- a/dts/src/arm/omap3-n950-n9.dtsi
+++ b/dts/src/arm/omap3-n950-n9.dtsi
@@ -265,6 +265,20 @@
&i2c2 {
clock-frequency = <400000>;
+
+ as3645a@30 {
+ reg = <0x30>;
+ compatible = "ams,as3645a";
+ flash {
+ flash-timeout-us = <150000>;
+ flash-max-microamp = <320000>;
+ led-max-microamp = <60000>;
+ peak-current-limit = <1750000>;
+ };
+ indicator {
+ led-max-microamp = <10000>;
+ };
+ };
};
&i2c3 {
diff --git a/dts/src/arm/omap3-overo-base.dtsi b/dts/src/arm/omap3-overo-base.dtsi
index cd220342a8..f25e158e71 100644
--- a/dts/src/arm/omap3-overo-base.dtsi
+++ b/dts/src/arm/omap3-overo-base.dtsi
@@ -181,7 +181,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&w3cbw003c_npoweron>;
- vmmc_aux-supply = <&w3cbw003c_wifi_nreset>;
+ vqmmc-supply = <&w3cbw003c_wifi_nreset>;
bus-width = <4>;
cap-sdio-irq;
non-removable;
diff --git a/dts/src/arm/omap3-tao3530.dtsi b/dts/src/arm/omap3-tao3530.dtsi
index 06ac0f80bc..9a601d1524 100644
--- a/dts/src/arm/omap3-tao3530.dtsi
+++ b/dts/src/arm/omap3-tao3530.dtsi
@@ -223,7 +223,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
- vmmc_aux-supply = <&vsim>;
+ vqmmc-supply = <&vsim>;
cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
diff --git a/dts/src/arm/omap3-zoom3.dts b/dts/src/arm/omap3-zoom3.dts
index 45e2ce0803..96d0301a33 100644
--- a/dts/src/arm/omap3-zoom3.dts
+++ b/dts/src/arm/omap3-zoom3.dts
@@ -174,7 +174,7 @@
&mmc1 {
vmmc-supply = <&vmmc1>;
- vmmc_aux-supply = <&vsim>;
+ vqmmc-supply = <&vsim>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
diff --git a/dts/src/arm/omap3.dtsi b/dts/src/arm/omap3.dtsi
index a3ff4933db..bdaf30c8c4 100644
--- a/dts/src/arm/omap3.dtsi
+++ b/dts/src/arm/omap3.dtsi
@@ -713,14 +713,12 @@
usbhsohci: ohci@48064400 {
compatible = "ti,ohci-omap3";
reg = <0x48064400 0x400>;
- interrupt-parent = <&intc>;
interrupts = <76>;
};
usbhsehci: ehci@48064800 {
compatible = "ti,ehci-omap";
reg = <0x48064800 0x400>;
- interrupt-parent = <&intc>;
interrupts = <77>;
};
};
@@ -831,7 +829,6 @@
reg-names = "tx",
"rx";
- interrupt-parent = <&intc>;
interrupts = <67>,
<68>;
};
@@ -844,7 +841,6 @@
reg-names = "tx",
"rx";
- interrupt-parent = <&intc>;
interrupts = <69>,
<70>;
};
diff --git a/dts/src/arm/omap3430-sdp.dts b/dts/src/arm/omap3430-sdp.dts
index abd6921143..908951eb59 100644
--- a/dts/src/arm/omap3430-sdp.dts
+++ b/dts/src/arm/omap3430-sdp.dts
@@ -33,7 +33,7 @@
&mmc1 {
vmmc-supply = <&vmmc1>;
- vmmc_aux-supply = <&vsim>;
+ vqmmc-supply = <&vsim>;
/*
* S6-3 must be in ON position for 8 bit mode to function
* Else, use 4 bit mode
diff --git a/dts/src/arm/omap4-droid4-xt894.dts b/dts/src/arm/omap4-droid4-xt894.dts
index 10ca1c1749..8b93d37310 100644
--- a/dts/src/arm/omap4-droid4-xt894.dts
+++ b/dts/src/arm/omap4-droid4-xt894.dts
@@ -129,6 +129,34 @@
output-high;
line-name = "touchscreen-reset";
};
+
+ pwm8: dmtimer-pwm-8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_direction_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer8>;
+ ti,clock-source = <0x01>;
+ };
+
+ pwm9: dmtimer-pwm-9 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_enable_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer9>;
+ ti,clock-source = <0x01>;
+ };
+
+ vibrator {
+ compatible = "pwm-vibrator";
+ pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>;
+ pwm-names = "enable", "direction";
+ direction-duty-cycle-ns = <10000000>;
+ };
+
};
&dsi1 {
@@ -373,7 +401,7 @@
/* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)
OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)
OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)
>;
@@ -488,6 +516,18 @@
OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
>;
};
+
+ vibrator_direction_pin: pinmux_vibrator_direction_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
+ >;
+ };
+
+ vibrator_enable_pin: pinmux_vibrator_enable_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
+ >;
+ };
};
&uart3 {
diff --git a/dts/src/arm/omap4-duovero-parlor.dts b/dts/src/arm/omap4-duovero-parlor.dts
index 1b825128a7..a9a584b5b9 100644
--- a/dts/src/arm/omap4-duovero-parlor.dts
+++ b/dts/src/arm/omap4-duovero-parlor.dts
@@ -100,7 +100,7 @@
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */
- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
>;
diff --git a/dts/src/arm/omap4-panda-common.dtsi b/dts/src/arm/omap4-panda-common.dtsi
index edbc409029..2b48e51c37 100644
--- a/dts/src/arm/omap4-panda-common.dtsi
+++ b/dts/src/arm/omap4-panda-common.dtsi
@@ -267,7 +267,7 @@
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
diff --git a/dts/src/arm/omap4-sdp-es23plus.dts b/dts/src/arm/omap4-sdp-es23plus.dts
index b4d19a7ae3..3d3140fd96 100644
--- a/dts/src/arm/omap4-sdp-es23plus.dts
+++ b/dts/src/arm/omap4-sdp-es23plus.dts
@@ -10,7 +10,7 @@
/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
&dss_hdmi_pins {
pinctrl-single,pins = <
- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
diff --git a/dts/src/arm/omap4-sdp.dts b/dts/src/arm/omap4-sdp.dts
index d728ec9631..280d92d42b 100644
--- a/dts/src/arm/omap4-sdp.dts
+++ b/dts/src/arm/omap4-sdp.dts
@@ -290,7 +290,7 @@
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
diff --git a/dts/src/arm/omap4-var-om44customboard.dtsi b/dts/src/arm/omap4-var-om44customboard.dtsi
index 74940b6d77..676d8dd062 100644
--- a/dts/src/arm/omap4-var-om44customboard.dtsi
+++ b/dts/src/arm/omap4-var-om44customboard.dtsi
@@ -122,7 +122,7 @@
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
- OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
diff --git a/dts/src/arm/omap5-board-common.dtsi b/dts/src/arm/omap5-board-common.dtsi
index 4caadb2532..7824b2631c 100644
--- a/dts/src/arm/omap5-board-common.dtsi
+++ b/dts/src/arm/omap5-board-common.dtsi
@@ -290,7 +290,7 @@
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
- OMAP5_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
+ OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
>;
diff --git a/dts/src/arm/omap5-cm-t54.dts b/dts/src/arm/omap5-cm-t54.dts
index 78397f66d0..552a5c4c59 100644
--- a/dts/src/arm/omap5-cm-t54.dts
+++ b/dts/src/arm/omap5-cm-t54.dts
@@ -266,7 +266,7 @@
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
- OMAP5_IOPAD(0x013c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec */
+ OMAP5_IOPAD(0x013c, PIN_INPUT | MUX_MODE0) /* hdmi_cec */
OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */
OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */
>;
diff --git a/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi b/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi
index b9457dd21a..e413b21ee3 100644
--- a/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,27 +20,12 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
- clocks {
- xo: xo {
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- #clock-cells = <0>;
- };
- };
-
soc {
-
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <1 2 0xf08>,
- <1 3 0xf08>,
- <1 4 0xf08>,
- <1 1 0xf08>;
- clock-frequency = <48000000>;
+ rng@22000 {
+ status = "ok";
};
- pinctrl@0x01000000 {
+ pinctrl@1000000 {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
@@ -108,5 +93,13 @@
watchdog@b017000 {
status = "ok";
};
+
+ wifi@a000000 {
+ status = "ok";
+ };
+
+ wifi@a800000 {
+ status = "ok";
+ };
};
};
diff --git a/dts/src/arm/qcom-ipq4019.dtsi b/dts/src/arm/qcom-ipq4019.dtsi
index 4b7d97275c..10d112a407 100644
--- a/dts/src/arm/qcom-ipq4019.dtsi
+++ b/dts/src/arm/qcom-ipq4019.dtsi
@@ -96,6 +96,21 @@
clock-frequency = <32768>;
#clock-cells = <0>;
};
+
+ xo: xo {
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 2 0xf08>,
+ <1 3 0xf08>,
+ <1 4 0xf08>,
+ <1 1 0xf08>;
+ clock-frequency = <48000000>;
};
soc {
@@ -119,7 +134,15 @@
reg = <0x1800000 0x60000>;
};
- tlmm: pinctrl@0x01000000 {
+ rng@22000 {
+ compatible = "qcom,prng";
+ reg = <0x22000 0x140>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
+ tlmm: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
@@ -269,5 +292,89 @@
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};
+
+ wifi0: wifi@a000000 {
+ compatible = "qcom,ipq4019-wifi";
+ reg = <0xa000000 0x200000>;
+ resets = <&gcc WIFI0_CPU_INIT_RESET>,
+ <&gcc WIFI0_RADIO_SRIF_RESET>,
+ <&gcc WIFI0_RADIO_WARM_RESET>,
+ <&gcc WIFI0_RADIO_COLD_RESET>,
+ <&gcc WIFI0_CORE_WARM_RESET>,
+ <&gcc WIFI0_CORE_COLD_RESET>;
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
+ "wifi_radio_warm", "wifi_radio_cold",
+ "wifi_core_warm", "wifi_core_cold";
+ clocks = <&gcc GCC_WCSS2G_CLK>,
+ <&gcc GCC_WCSS2G_REF_CLK>,
+ <&gcc GCC_WCSS2G_RTC_CLK>;
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
+ "wifi_wcss_rtc";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 168 IRQ_TYPE_NONE>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
+ "msi12", "msi13", "msi14", "msi15",
+ "legacy";
+ status = "disabled";
+ };
+
+ wifi1: wifi@a800000 {
+ compatible = "qcom,ipq4019-wifi";
+ reg = <0xa800000 0x200000>;
+ resets = <&gcc WIFI1_CPU_INIT_RESET>,
+ <&gcc WIFI1_RADIO_SRIF_RESET>,
+ <&gcc WIFI1_RADIO_WARM_RESET>,
+ <&gcc WIFI1_RADIO_COLD_RESET>,
+ <&gcc WIFI1_CORE_WARM_RESET>,
+ <&gcc WIFI1_CORE_COLD_RESET>;
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
+ "wifi_radio_warm", "wifi_radio_cold",
+ "wifi_core_warm", "wifi_core_cold";
+ clocks = <&gcc GCC_WCSS5G_CLK>,
+ <&gcc GCC_WCSS5G_REF_CLK>,
+ <&gcc GCC_WCSS5G_RTC_CLK>;
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
+ "wifi_wcss_rtc";
+ interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 169 IRQ_TYPE_NONE>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
+ "msi12", "msi13", "msi14", "msi15",
+ "legacy";
+ status = "disabled";
+ };
};
};
diff --git a/dts/src/arm/qcom-msm8974.dtsi b/dts/src/arm/qcom-msm8974.dtsi
index c5ee68a3f7..a392076253 100644
--- a/dts/src/arm/qcom-msm8974.dtsi
+++ b/dts/src/arm/qcom-msm8974.dtsi
@@ -779,7 +779,7 @@
};
replicator@fc31c000 {
- compatible = "qcom,coresight-replicator1x", "arm,primecell";
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0xfc31c000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
diff --git a/dts/src/arm/r7s72100-genmai.dts b/dts/src/arm/r7s72100-genmai.dts
index 52a7b586ba..cd4d5ff774 100644
--- a/dts/src/arm/r7s72100-genmai.dts
+++ b/dts/src/arm/r7s72100-genmai.dts
@@ -11,6 +11,8 @@
/dts-v1/;
#include "r7s72100.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
model = "Genmai";
@@ -34,6 +36,54 @@
#address-cells = <1>;
#size-cells = <1>;
};
+
+ leds {
+ status = "okay";
+ compatible = "gpio-leds";
+
+ led1 {
+ gpios = <&port4 10 GPIO_ACTIVE_LOW>;
+ };
+
+ led2 {
+ gpios = <&port4 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&pinctrl {
+
+ scif2_pins: serial2 {
+ /* P3_0 as TxD2; P3_2 as RxD2 */
+ pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
+ };
+
+ i2c2_pins: i2c2 {
+ /* RIIC2: P1_4 as SCL, P1_5 as SDA */
+ pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
+ };
+
+ ether_pins: ether {
+ /* Ethernet on Ports 1,2,3,5 */
+ pinmux = <RZA1_PINMUX(1, 14, 4)>,/* P1_14 = ET_COL */
+ <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
+ <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
+ <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
+ <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
+ <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
+ <RZA1_PINMUX(2, 0, 2)>, /* P2_0 = ET_TXCLK */
+ <RZA1_PINMUX(2, 1, 2)>, /* P2_1 = ET_TXER */
+ <RZA1_PINMUX(2, 2, 2)>, /* P2_2 = ET_TXEN */
+ <RZA1_PINMUX(2, 3, 2)>, /* P2_3 = ET_CRS */
+ <RZA1_PINMUX(2, 4, 2)>, /* P2_4 = ET_TXD0 */
+ <RZA1_PINMUX(2, 5, 2)>, /* P2_5 = ET_TXD1 */
+ <RZA1_PINMUX(2, 6, 2)>, /* P2_6 = ET_TXD2 */
+ <RZA1_PINMUX(2, 7, 2)>, /* P2_7 = ET_TXD3 */
+ <RZA1_PINMUX(2, 8, 2)>, /* P2_8 = ET_RXD0 */
+ <RZA1_PINMUX(2, 9, 2)>, /* P2_9 = ET_RXD1 */
+ <RZA1_PINMUX(2, 10, 2)>,/* P2_10 = ET_RXD2 */
+ <RZA1_PINMUX(2, 11, 2)>;/* P2_11 = ET_RXD3 */
+ };
};
&extal_clk {
@@ -52,12 +102,28 @@
status = "okay";
};
+&ether {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ether_pins>;
+
+ status = "okay";
+
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
&i2c2 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
eeprom@50 {
- compatible = "renesas,24c128";
+ compatible = "renesas,24c128", "atmel,24c128";
reg = <0x50>;
pagesize = <64>;
};
@@ -68,6 +134,9 @@
};
&scif2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scif2_pins>;
+
status = "okay";
};
diff --git a/dts/src/arm/r7s72100-rskrza1.dts b/dts/src/arm/r7s72100-rskrza1.dts
index 72df20a043..5dcaaf131d 100644
--- a/dts/src/arm/r7s72100-rskrza1.dts
+++ b/dts/src/arm/r7s72100-rskrza1.dts
@@ -10,6 +10,8 @@
/dts-v1/;
#include "r7s72100.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
model = "RSKRZA1";
@@ -33,6 +35,15 @@
#address-cells = <1>;
#size-cells = <1>;
};
+
+ leds {
+ status = "okay";
+ compatible = "gpio-leds";
+
+ led0 {
+ gpios = <&port7 1 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&extal_clk {
@@ -47,11 +58,57 @@
clock-frequency = <32768>;
};
+&pinctrl {
+
+ /* Serial Console */
+ scif2_pins: serial2 {
+ pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
+ <RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
+ };
+
+ /* Ethernet */
+ ether_pins: ether {
+ /* Ethernet on Ports 1,2,3,5 */
+ pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */
+ <RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */
+ <RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */
+ <RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */
+ <RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */
+ <RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */
+ <RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */
+ <RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */
+ <RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */
+ <RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */
+ <RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */
+ <RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */
+ <RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */
+ <RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */
+ <RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */
+ <RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */
+ <RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */
+ <RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */
+ };
+
+ /* SDHI ch1 on CN1 */
+ sdhi1_pins: sdhi1 {
+ pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */
+ <RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */
+ <RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */
+ <RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */
+ <RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */
+ <RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */
+ <RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */
+ <RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */
+ };
+};
+
&mtu2 {
status = "okay";
};
&ether {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ether_pins>;
status = "okay";
renesas,no-ether-link;
phy-handle = <&phy0>;
@@ -61,6 +118,8 @@
};
&sdhi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhi1_pins>;
bus-width = <4>;
status = "okay";
};
@@ -78,5 +137,7 @@
};
&scif2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scif2_pins>;
status = "okay";
};
diff --git a/dts/src/arm/r7s72100.dtsi b/dts/src/arm/r7s72100.dtsi
index 5cf53e9943..4ed12a4d9d 100644
--- a/dts/src/arm/r7s72100.dtsi
+++ b/dts/src/arm/r7s72100.dtsi
@@ -207,6 +207,84 @@
};
};
+ pinctrl: pin-controller@fcfe3000 {
+ compatible = "renesas,r7s72100-ports";
+
+ reg = <0xfcfe3000 0x4230>;
+
+ port0: gpio-0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 6>;
+ };
+
+ port1: gpio-1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ port2: gpio-2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ port3: gpio-3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ port4: gpio-4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ port5: gpio-5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 80 11>;
+ };
+
+ port6: gpio-6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ port7: gpio-7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ port8: gpio-8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ port9: gpio-9 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 144 8>;
+ };
+
+ port10: gpio-10 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 160 16>;
+ };
+
+ port11: gpio-11 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 176 16>;
+ };
+ };
+
scif0: serial@e8007000 {
compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8007000 64>;
diff --git a/dts/src/arm/r8a7743-iwg20d-q7.dts b/dts/src/arm/r8a7743-iwg20d-q7.dts
index 9b54783cc2..081af01928 100644
--- a/dts/src/arm/r8a7743-iwg20d-q7.dts
+++ b/dts/src/arm/r8a7743-iwg20d-q7.dts
@@ -17,9 +17,40 @@
aliases {
serial0 = &scif0;
+ ethernet0 = &avb;
+ };
+};
+
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data_d";
+ function = "scif0";
+ };
+
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_gmii";
+ function = "avb";
};
};
&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy3>;
+ phy-mode = "gmii";
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ micrel,led-mode = <1>;
+ };
+};
diff --git a/dts/src/arm/r8a7743-iwg20m.dtsi b/dts/src/arm/r8a7743-iwg20m.dtsi
index 001ca9144f..ff79938186 100644
--- a/dts/src/arm/r8a7743-iwg20m.dtsi
+++ b/dts/src/arm/r8a7743-iwg20m.dtsi
@@ -22,8 +22,34 @@
device_type = "memory";
reg = <2 0x00000000 0 0x20000000>;
};
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&extal_clk {
clock-frequency = <20000000>;
};
+
+&pfc {
+ mmcif0_pins: mmc {
+ groups = "mmc_data8_b", "mmc_ctrl";
+ function = "mmc";
+ };
+};
+
+&mmcif0 {
+ pinctrl-0 = <&mmcif0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&reg_3p3v>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
diff --git a/dts/src/arm/r8a7743-sk-rzg1m.dts b/dts/src/arm/r8a7743-sk-rzg1m.dts
index 3a22538208..3d918d1065 100644
--- a/dts/src/arm/r8a7743-sk-rzg1m.dts
+++ b/dts/src/arm/r8a7743-sk-rzg1m.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the SK-RZG1M board
*
- * Copyright (C) 2016 Cogent Embedded, Inc.
+ * Copyright (C) 2016-2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -39,11 +39,34 @@
clock-frequency = <20000000>;
};
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data_d";
+ function = "scif0";
+ };
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq0";
+ function = "intc";
+ };
+};
+
&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
&ether {
+ pinctrl-0 = <&ether_pins &phy1_pins>;
+ pinctrl-names = "default";
+
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";
diff --git a/dts/src/arm/r8a7743.dtsi b/dts/src/arm/r8a7743.dtsi
index 0ddac81742..14222c72f0 100644
--- a/dts/src/arm/r8a7743.dtsi
+++ b/dts/src/arm/r8a7743.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the r8a7743 SoC
*
- * Copyright (C) 2016 Cogent Embedded Inc.
+ * Copyright (C) 2016-2017 Cogent Embedded Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -18,9 +18,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -28,8 +38,26 @@
reg = <0>;
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
next-level-cache = <&L2_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1500000 1000000>,
+ <1312500 1000000>,
+ <1125000 1000000>,
+ < 937500 1000000>,
+ < 750000 1000000>,
+ < 375000 1000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
+ next-level-cache = <&L2_CA15>;
};
L2_CA15: cache-controller-0 {
@@ -48,6 +76,12 @@
#size-cells = <2>;
ranges;
+ apmu@e6152000 {
+ compatible = "renesas,r8a7743-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -65,6 +99,126 @@
resets = <&cpg 408>;
};
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7743",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7743",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7743",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7743",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7743",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7743",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7743",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
+ };
+
+ gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a7743",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6055800 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 904>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 904>;
+ };
+
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7743", "renesas,irqc";
#interrupt-cells = <2>;
@@ -123,6 +277,11 @@
#power-domain-cells = <1>;
};
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7743";
+ reg = <0 0xe6060000 0 0x250>;
+ };
+
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
@@ -189,6 +348,94 @@
dma-channels = <15>;
};
+ /* The memory map in the User's Manual maps the cores to bus
+ * numbers
+ */
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e6528000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7743",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7743",
"renesas,rcar-gen2-scifa", "renesas,scifa";
@@ -468,6 +715,29 @@
status = "disabled";
};
+ icram2: sram@e6300000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe6300000 0 0x40000>;
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7743";
reg = <0 0xee700000 0 0x400>;
@@ -480,6 +750,35 @@
#size-cells = <0>;
status = "disabled";
};
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7743",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7743",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ max-frequency = <97500000>;
+ status = "disabled";
+ };
};
/* External root clock */
diff --git a/dts/src/arm/r8a7745-sk-rzg1e.dts b/dts/src/arm/r8a7745-sk-rzg1e.dts
index 97840b3401..b4d679b04a 100644
--- a/dts/src/arm/r8a7745-sk-rzg1e.dts
+++ b/dts/src/arm/r8a7745-sk-rzg1e.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the SK-RZG1E board
*
- * Copyright (C) 2016 Cogent Embedded, Inc.
+ * Copyright (C) 2016-2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -34,11 +34,34 @@
clock-frequency = <20000000>;
};
+&pfc {
+ scif2_pins: scif2 {
+ groups = "scif2_data";
+ function = "scif2";
+ };
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq8";
+ function = "intc";
+ };
+};
+
&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
&ether {
+ pinctrl-0 = <&ether_pins &phy1_pins>;
+ pinctrl-names = "default";
+
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";
diff --git a/dts/src/arm/r8a7745.dtsi b/dts/src/arm/r8a7745.dtsi
index 2feb0084bb..aff90dfb8b 100644
--- a/dts/src/arm/r8a7745.dtsi
+++ b/dts/src/arm/r8a7745.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the r8a7745 SoC
*
- * Copyright (C) 2016 Cogent Embedded Inc.
+ * Copyright (C) 2016-2017 Cogent Embedded Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -123,6 +123,11 @@
#power-domain-cells = <1>;
};
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7745";
+ reg = <0 0xe6060000 0 0x11c>;
+ };
+
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7745",
"renesas,rcar-dmac";
@@ -468,6 +473,29 @@
status = "disabled";
};
+ icram2: sram@e6300000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe6300000 0 0x40000>;
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7745";
reg = <0 0xee700000 0 0x400>;
diff --git a/dts/src/arm/r8a7790.dtsi b/dts/src/arm/r8a7790.dtsi
index 2805a8608d..16358bf8d1 100644
--- a/dts/src/arm/r8a7790.dtsi
+++ b/dts/src/arm/r8a7790.dtsi
@@ -830,6 +830,24 @@
status = "disabled";
};
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7790";
reg = <0 0xee700000 0 0x400>;
@@ -855,7 +873,7 @@
};
sata0: sata@ee300000 {
- compatible = "renesas,sata-r8a7790";
+ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x2000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
@@ -864,7 +882,7 @@
};
sata1: sata@ee500000 {
- compatible = "renesas,sata-r8a7790";
+ compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
reg = <0 0xee500000 0 0x2000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
@@ -909,7 +927,7 @@
};
vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7790";
+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
@@ -918,7 +936,7 @@
};
vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7790";
+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
@@ -927,7 +945,7 @@
};
vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7790";
+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
@@ -936,7 +954,7 @@
};
vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a7790";
+ compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
diff --git a/dts/src/arm/r8a7791-koelsch.dts b/dts/src/arm/r8a7791-koelsch.dts
index 001e6116c4..0ce0b278e1 100644
--- a/dts/src/arm/r8a7791-koelsch.dts
+++ b/dts/src/arm/r8a7791-koelsch.dts
@@ -642,11 +642,19 @@
};
};
+ cec_clock: cec-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
@@ -702,7 +710,7 @@
};
eeprom@50 {
- compatible = "renesas,24c02";
+ compatible = "renesas,24c02", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
diff --git a/dts/src/arm/r8a7791.dtsi b/dts/src/arm/r8a7791.dtsi
index bd93f699ad..f1d1a97721 100644
--- a/dts/src/arm/r8a7791.dtsi
+++ b/dts/src/arm/r8a7791.dtsi
@@ -890,6 +890,24 @@
status = "disabled";
};
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7791";
reg = <0 0xee700000 0 0x400>;
@@ -915,7 +933,7 @@
};
sata0: sata@ee300000 {
- compatible = "renesas,sata-r8a7791";
+ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x2000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
@@ -924,7 +942,7 @@
};
sata1: sata@ee500000 {
- compatible = "renesas,sata-r8a7791";
+ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
reg = <0 0xee500000 0 0x2000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
@@ -969,7 +987,7 @@
};
vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7791";
+ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
@@ -978,7 +996,7 @@
};
vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7791";
+ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
@@ -987,7 +1005,7 @@
};
vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7791";
+ compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
diff --git a/dts/src/arm/r8a7792.dtsi b/dts/src/arm/r8a7792.dtsi
index 0efecb232e..2623f39bed 100644
--- a/dts/src/arm/r8a7792.dtsi
+++ b/dts/src/arm/r8a7792.dtsi
@@ -465,6 +465,24 @@
status = "disabled";
};
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7792";
reg = <0 0xee100000 0 0x328>;
diff --git a/dts/src/arm/r8a7793.dtsi b/dts/src/arm/r8a7793.dtsi
index 13b980f27b..497716b6fb 100644
--- a/dts/src/arm/r8a7793.dtsi
+++ b/dts/src/arm/r8a7793.dtsi
@@ -848,6 +848,24 @@
status = "disabled";
};
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7793";
reg = <0 0xee700000 0 0x400>;
diff --git a/dts/src/arm/r8a7794.dtsi b/dts/src/arm/r8a7794.dtsi
index 7d9a81d970..2653541420 100644
--- a/dts/src/arm/r8a7794.dtsi
+++ b/dts/src/arm/r8a7794.dtsi
@@ -588,6 +588,24 @@
status = "disabled";
};
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7794";
reg = <0 0xee700000 0 0x400>;
@@ -783,7 +801,7 @@
};
vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7794";
+ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
@@ -792,7 +810,7 @@
};
vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7794";
+ compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
diff --git a/dts/src/arm/rk3036-kylin.dts b/dts/src/arm/rk3036-kylin.dts
index 5726135b7f..fdb1570bc7 100644
--- a/dts/src/arm/rk3036-kylin.dts
+++ b/dts/src/arm/rk3036-kylin.dts
@@ -357,7 +357,6 @@
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
sd-uhs-sdr12;
@@ -372,7 +371,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
};
diff --git a/dts/src/arm/rk3036.dtsi b/dts/src/arm/rk3036.dtsi
index ec91325d3b..4916c65e0a 100644
--- a/dts/src/arm/rk3036.dtsi
+++ b/dts/src/arm/rk3036.dtsi
@@ -287,7 +287,6 @@
fifo-depth = <0x100>;
mmc-ddr-1_8v;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
resets = <&cru SRST_EMMC>;
@@ -599,7 +598,7 @@
rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
};
- sdmmc_cd: sdmcc-cd {
+ sdmmc_cd: sdmmc-cd {
rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
};
diff --git a/dts/src/arm/rk3066a-bqcurie2.dts b/dts/src/arm/rk3066a-bqcurie2.dts
index e1f5198723..ef1eabf251 100644
--- a/dts/src/arm/rk3066a-bqcurie2.dts
+++ b/dts/src/arm/rk3066a-bqcurie2.dts
@@ -190,7 +190,6 @@
#include "tps65910.dtsi"
&mmc0 { /* sdmmc */
- num-slots = <1>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
@@ -202,7 +201,6 @@
};
&mmc1 { /* wifi */
- num-slots = <1>;
status = "okay";
non-removable;
diff --git a/dts/src/arm/rk3066a-mk808.dts b/dts/src/arm/rk3066a-mk808.dts
index 7ca1cf5241..13e285c53d 100644
--- a/dts/src/arm/rk3066a-mk808.dts
+++ b/dts/src/arm/rk3066a-mk808.dts
@@ -132,7 +132,6 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
- num-slots = <1>;
vmmc-supply = <&vcc_sd>;
status = "okay";
};
@@ -141,7 +140,6 @@
bus-width = <4>;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
pinctrl-names = "default";
vmmc-supply = <&vcc_wifi>;
diff --git a/dts/src/arm/rk3066a-rayeager.dts b/dts/src/arm/rk3066a-rayeager.dts
index 8907deaab1..400cbf9609 100644
--- a/dts/src/arm/rk3066a-rayeager.dts
+++ b/dts/src/arm/rk3066a-rayeager.dts
@@ -185,7 +185,6 @@
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
vmmc-supply = <&vcc_emmc>;
@@ -336,7 +335,6 @@
&mmc0 {
bus-width = <4>;
disable-wp;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
vmmc-supply = <&vcc_sd>;
@@ -349,7 +347,6 @@
bus-width = <4>;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>;
vmmc-supply = <&vccio_wl>;
diff --git a/dts/src/arm/rk3188-px3-evb.dts b/dts/src/arm/rk3188-px3-evb.dts
index 5b2a0b6885..8ba9e06062 100644
--- a/dts/src/arm/rk3188-px3-evb.dts
+++ b/dts/src/arm/rk3188-px3-evb.dts
@@ -89,7 +89,6 @@
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
status = "okay";
@@ -256,7 +255,6 @@
};
&mmc0 {
- num-slots = <1>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
diff --git a/dts/src/arm/rk3188-radxarock.dts b/dts/src/arm/rk3188-radxarock.dts
index ca0a1c4bc1..53d6fc2fdb 100644
--- a/dts/src/arm/rk3188-radxarock.dts
+++ b/dts/src/arm/rk3188-radxarock.dts
@@ -296,7 +296,6 @@
};
&mmc0 {
- num-slots = <1>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
diff --git a/dts/src/arm/rk3228-evb.dts b/dts/src/arm/rk3228-evb.dts
index 58834330a5..1be9daacc4 100644
--- a/dts/src/arm/rk3228-evb.dts
+++ b/dts/src/arm/rk3228-evb.dts
@@ -50,6 +50,16 @@
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&emmc {
@@ -60,6 +70,30 @@
status = "okay";
};
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC_SRC>;
+ assigned-clock-rates = <50000000>;
+ clock_in_out = "output";
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rmii";
+ phy-handle = <&phy>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@0 {
+ compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ clocks = <&cru SCLK_MAC_PHY>;
+ resets = <&cru SRST_MACPHY>;
+ phy-is-integrated;
+ };
+ };
+};
+
&tsadc {
status = "okay";
diff --git a/dts/src/arm/rk3229-evb.dts b/dts/src/arm/rk3229-evb.dts
index 1b55192b7d..73e3845857 100644
--- a/dts/src/arm/rk3229-evb.dts
+++ b/dts/src/arm/rk3229-evb.dts
@@ -40,7 +40,8 @@
/dts-v1/;
-#include "rk322x.dtsi"
+#include <dt-bindings/input/input.h>
+#include "rk3229.dtsi"
/ {
model = "Rockchip RK3229 Evaluation board";
@@ -51,6 +52,15 @@
reg = <0x60000000 0x40000000>;
};
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
ext_gmac: ext_gmac {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -67,6 +77,7 @@
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
+ vin-supply = <&vcc_sys>;
};
vcc_phy: vcc-phy-regulator {
@@ -77,9 +88,98 @@
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
+ vin-supply = <&vccio_1v8>;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vccio_1v8: vccio-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vccio_3v3: vccio-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vdd_arm: vdd-arm-regulator {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 25000 1>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: vdd-log-regulator {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+ power_key: power-key {
+ label = "GPIO Key Power";
+ gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <100>;
+ wakeup-source;
+ };
};
};
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ status = "okay";
+};
+
&gmac {
assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
@@ -96,7 +196,21 @@
status = "okay";
};
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vccio_3v3>;
+ vccio2-supply = <&vccio_1v8>;
+ vccio4-supply = <&vccio_3v3>;
+};
+
&pinctrl {
+ keys {
+ pwr_key: pwr-key {
+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -104,6 +218,19 @@
};
};
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+ status = "okay";
+};
+
&uart2 {
status = "okay";
};
diff --git a/dts/src/arm/rk3229.dtsi b/dts/src/arm/rk3229.dtsi
new file mode 100644
index 0000000000..6fe6c15fc1
--- /dev/null
+++ b/dts/src/arm/rk3229.dtsi
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "rk322x.dtsi"
+
+/ {
+ compatible = "rockchip,rk3229";
+
+ /delete-node/ opp-table0;
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <975000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1175000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1275000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1325000>;
+ };
+ opp-1392000000 {
+ opp-hz = /bits/ 64 <1392000000>;
+ opp-microvolt = <1375000>;
+ };
+ opp-1464000000 {
+ opp-hz = /bits/ 64 <1464000000>;
+ opp-microvolt = <1400000>;
+ };
+ };
+};
diff --git a/dts/src/arm/rk322x.dtsi b/dts/src/arm/rk322x.dtsi
index f3e4ffd9f8..06814421ee 100644
--- a/dts/src/arm/rk322x.dtsi
+++ b/dts/src/arm/rk322x.dtsi
@@ -55,6 +55,7 @@
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
+ spi0 = &spi0;
};
cpus {
@@ -70,6 +71,7 @@
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
+ enable-method = "psci";
};
cpu1: cpu@f01 {
@@ -78,6 +80,7 @@
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
operating-points-v2 = <&cpu0_opp_table>;
+ enable-method = "psci";
};
cpu2: cpu@f02 {
@@ -86,6 +89,7 @@
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
operating-points-v2 = <&cpu0_opp_table>;
+ enable-method = "psci";
};
cpu3: cpu@f03 {
@@ -94,6 +98,7 @@
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
operating-points-v2 = <&cpu0_opp_table>;
+ enable-method = "psci";
};
};
@@ -151,6 +156,11 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
@@ -196,6 +206,19 @@
status = "disabled";
};
+ spdif: spdif@100d0000 {
+ compatible = "rockchip,rk3228-spdif";
+ reg = <0x100d0000 0x1000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&pdma 10>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx>;
+ status = "disabled";
+ };
+
i2s2: i2s2@100e0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100e0000 0x4000>;
@@ -215,6 +238,11 @@
#address-cells = <1>;
#size-cells = <1>;
+ io_domains: io-domains {
+ compatible = "rockchip,rk3228-io-voltage-domain";
+ status = "disabled";
+ };
+
u2phy0: usb2-phy@760 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0760 0x0c>;
@@ -309,6 +337,23 @@
status = "disabled";
};
+ efuse: efuse@11040000 {
+ compatible = "rockchip,rk3228-efuse";
+ reg = <0x11040000 0x20>;
+ clocks = <&cru PCLK_EFUSE_256>;
+ clock-names = "pclk_efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ efuse_id: id@7 {
+ reg = <0x7 0x10>;
+ };
+ cpu_leakage: cpu_leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ };
+
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
@@ -361,6 +406,19 @@
status = "disabled";
};
+ spi0: spi@11090000 {
+ compatible = "rockchip,rk3228-spi";
+ reg = <0x11090000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
+ status = "disabled";
+ };
+
wdt: watchdog@110a0000 {
compatible = "snps,dw-wdt";
reg = <0x110a0000 0x100>;
@@ -500,8 +558,70 @@
status = "disabled";
};
+ vpu_mmu: iommu@20020800 {
+ compatible = "rockchip,iommu";
+ reg = <0x20020800 0x100>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vdec_mmu: iommu@20030480 {
+ compatible = "rockchip,iommu";
+ reg = <0x20030480 0x40>, <0x200304c0 0x40>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vdec_mmu";
+ iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vop_mmu: iommu@20053f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x20053f00 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@20070800 {
+ compatible = "rockchip,iommu";
+ reg = <0x20070800 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ sdmmc: dwmmc@30000000 {
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x30000000 0x4000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc@30010000 {
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x30010000 0x4000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
+ status = "disabled";
+ };
+
emmc: dwmmc@30020000 {
- compatible = "rockchip,rk3288-dw-mshc";
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <37500000>;
@@ -511,7 +631,6 @@
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
bus-width = <8>;
default-sample-phase = <158>;
- num-slots = <1>;
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
@@ -710,6 +829,40 @@
drive-strength = <12>;
};
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
+ };
+ };
+
+ sdio {
+ sdio_clk: sdio-clk {
+ rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdio_cmd: sdio-cmd {
+ rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdio_bus4: sdio-bus4 {
+ rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
+ <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
+ <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
+ <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
+ };
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
@@ -797,6 +950,42 @@
};
};
+ spi-0 {
+ spi0_clk: spi0-clk {
+ rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi0_cs0: spi0-cs0 {
+ rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi0_tx: spi0-tx {
+ rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi0_rx: spi0-rx {
+ rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi0_cs1: spi0-cs1 {
+ rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ spi-1 {
+ spi1_clk: spi1-clk {
+ rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi1_cs0: spi1-cs0 {
+ rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi1_rx: spi1-rx {
+ rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi1_tx: spi1-tx {
+ rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi1_cs1: spi1-cs1 {
+ rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ };
+
i2s1 {
i2s1_bus: i2s1-bus {
rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
@@ -835,6 +1024,12 @@
};
};
+ spdif {
+ spdif_tx: spdif-tx {
+ rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/dts/src/arm/rk3288-evb.dtsi b/dts/src/arm/rk3288-evb.dtsi
index 0dec94c358..39b61dce97 100644
--- a/dts/src/arm/rk3288-evb.dtsi
+++ b/dts/src/arm/rk3288-evb.dtsi
@@ -45,7 +45,44 @@
/ {
memory@0 {
device_type = "memory";
- reg = <0x0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <100000>;
+ };
+
+ button-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <300000>;
+ };
+
+ menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <640000>;
+ };
+
+ esc {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <1000000>;
+ };
+
+ home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ press-threshold-microvolt = <1300000>;
+ };
};
backlight: backlight {
@@ -212,19 +249,22 @@
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
status = "okay";
};
+&saradc {
+ vref-supply = <&vcc_18>;
+ status = "okay";
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp; /* wp not hooked up */
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
@@ -248,6 +288,11 @@
status = "ok";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
diff --git a/dts/src/arm/rk3288-fennec.dts b/dts/src/arm/rk3288-fennec.dts
index 61d1c10283..4140597425 100644
--- a/dts/src/arm/rk3288-fennec.dts
+++ b/dts/src/arm/rk3288-fennec.dts
@@ -47,7 +47,7 @@
compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
memory@0 {
- reg = <0x0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
};
@@ -77,7 +77,6 @@
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
status = "okay";
@@ -99,6 +98,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
status = "okay";
};
diff --git a/dts/src/arm/rk3288-firefly-reload-core.dtsi b/dts/src/arm/rk3288-firefly-reload-core.dtsi
index 813496618d..5f05815f47 100644
--- a/dts/src/arm/rk3288-firefly-reload-core.dtsi
+++ b/dts/src/arm/rk3288-firefly-reload-core.dtsi
@@ -47,7 +47,7 @@
/ {
memory@0 {
device_type = "memory";
- reg = <0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: external-gmac-clock {
@@ -78,7 +78,6 @@
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
vmmc-supply = <&vcc_io>;
diff --git a/dts/src/arm/rk3288-firefly-reload.dts b/dts/src/arm/rk3288-firefly-reload.dts
index b11a282c33..7da0947aba 100644
--- a/dts/src/arm/rk3288-firefly-reload.dts
+++ b/dts/src/arm/rk3288-firefly-reload.dts
@@ -269,7 +269,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
@@ -284,7 +283,6 @@
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
sd-uhs-sdr12;
diff --git a/dts/src/arm/rk3288-firefly.dtsi b/dts/src/arm/rk3288-firefly.dtsi
index 32dabae12e..b9e6f3a972 100644
--- a/dts/src/arm/rk3288-firefly.dtsi
+++ b/dts/src/arm/rk3288-firefly.dtsi
@@ -46,7 +46,7 @@
/ {
memory@0 {
device_type = "memory";
- reg = <0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
};
adc-keys {
@@ -208,7 +208,6 @@
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
vmmc-supply = <&vcc_io>;
@@ -527,7 +526,6 @@
bus-width = <4>;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>;
vmmc-supply = <&vbat_wl>;
@@ -541,7 +539,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
diff --git a/dts/src/arm/rk3288-miqi.dts b/dts/src/arm/rk3288-miqi.dts
index 30e93f694a..4d923aa6ed 100644
--- a/dts/src/arm/rk3288-miqi.dts
+++ b/dts/src/arm/rk3288-miqi.dts
@@ -54,7 +54,7 @@
memory@0 {
device_type = "memory";
- reg = <0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: external-gmac-clock {
@@ -126,7 +126,6 @@
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
vmmc-supply = <&vcc_io>;
@@ -404,7 +403,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
diff --git a/dts/src/arm/rk3288-phycore-rdk.dts b/dts/src/arm/rk3288-phycore-rdk.dts
index 3dda79579b..1241cbcfc1 100644
--- a/dts/src/arm/rk3288-phycore-rdk.dts
+++ b/dts/src/arm/rk3288-phycore-rdk.dts
@@ -263,7 +263,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vdd_io_sd>;
diff --git a/dts/src/arm/rk3288-phycore-som.dtsi b/dts/src/arm/rk3288-phycore-som.dtsi
index 26cd3ad451..99cfae875e 100644
--- a/dts/src/arm/rk3288-phycore-som.dtsi
+++ b/dts/src/arm/rk3288-phycore-som.dtsi
@@ -55,7 +55,7 @@
*/
memory {
device_type = "memory";
- reg = <0 0x8000000>;
+ reg = <0x0 0x0 0x0 0x8000000>;
};
aliases {
@@ -136,7 +136,6 @@
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
vmmc-supply = <&vdd_3v3_io>;
diff --git a/dts/src/arm/rk3288-popmetal.dts b/dts/src/arm/rk3288-popmetal.dts
index aa1f9ecff2..f084e0c8dc 100644
--- a/dts/src/arm/rk3288-popmetal.dts
+++ b/dts/src/arm/rk3288-popmetal.dts
@@ -50,7 +50,7 @@
memory@0 {
device_type = "memory";
- reg = <0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: external-gmac-clock {
@@ -150,7 +150,6 @@
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
vmmc-supply = <&vcc_io>;
@@ -164,7 +163,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp; /* wp not hooked up */
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
sd-uhs-sdr12;
diff --git a/dts/src/arm/rk3288-r89.dts b/dts/src/arm/rk3288-r89.dts
index 1145b62edd..e95215c978 100644
--- a/dts/src/arm/rk3288-r89.dts
+++ b/dts/src/arm/rk3288-r89.dts
@@ -50,7 +50,7 @@
memory@0 {
device_type = "memory";
- reg = <0x0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: external-gmac-clock {
@@ -354,7 +354,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vcc_sdmmc>;
diff --git a/dts/src/arm/rk3288-rock2-som.dtsi b/dts/src/arm/rk3288-rock2-som.dtsi
index 749a9b86e6..b9c471fcbd 100644
--- a/dts/src/arm/rk3288-rock2-som.dtsi
+++ b/dts/src/arm/rk3288-rock2-som.dtsi
@@ -43,7 +43,7 @@
/ {
memory@0 {
- reg = <0x0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
};
@@ -89,7 +89,6 @@
cap-mmc-highspeed;
disable-wp;
non-removable;
- num-slots = <1>;
mmc-pwrseq = <&emmc_pwrseq>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
diff --git a/dts/src/arm/rk3288-rock2-square.dts b/dts/src/arm/rk3288-rock2-square.dts
index 8ed25e9f60..0e084b8a86 100644
--- a/dts/src/arm/rk3288-rock2-square.dts
+++ b/dts/src/arm/rk3288-rock2-square.dts
@@ -147,7 +147,6 @@
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>;
vmmc-supply = <&vcc_io>;
@@ -161,7 +160,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp; /* wp not hooked up */
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
diff --git a/dts/src/arm/rk3288-tinker.dts b/dts/src/arm/rk3288-tinker.dts
index f601c78386..346b0d8b47 100644
--- a/dts/src/arm/rk3288-tinker.dts
+++ b/dts/src/arm/rk3288-tinker.dts
@@ -50,7 +50,7 @@
compatible = "asus,rk3288-tinker", "rockchip,rk3288";
memory {
- reg = <0x0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
};
@@ -156,6 +156,11 @@
status = "ok";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
@@ -465,7 +470,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp; /* wp not hooked up */
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
diff --git a/dts/src/arm/rk3288-veyron-sdmmc.dtsi b/dts/src/arm/rk3288-veyron-sdmmc.dtsi
index aef07101e9..95e9bee8bc 100644
--- a/dts/src/arm/rk3288-veyron-sdmmc.dtsi
+++ b/dts/src/arm/rk3288-veyron-sdmmc.dtsi
@@ -117,7 +117,6 @@
card-detect-delay = <200>;
cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
rockchip,default-sample-phase = <90>;
- num-slots = <1>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
diff --git a/dts/src/arm/rk3288-veyron.dtsi b/dts/src/arm/rk3288-veyron.dtsi
index d709fa1847..6e5bd8974f 100644
--- a/dts/src/arm/rk3288-veyron.dtsi
+++ b/dts/src/arm/rk3288-veyron.dtsi
@@ -49,7 +49,7 @@
/ {
memory@0 {
device_type = "memory";
- reg = <0x0 0x80000000>;
+ reg = <0x0 0x0 0x0 0x80000000>;
};
gpio_keys: gpio-keys {
@@ -156,7 +156,6 @@
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
};
@@ -372,7 +371,6 @@
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
sd-uhs-sdr12;
diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi
index 858e1fed76..356ed1e624 100644
--- a/dts/src/arm/rk3288.dtsi
+++ b/dts/src/arm/rk3288.dtsi
@@ -49,8 +49,8 @@
#include <dt-bindings/soc/rockchip,boot-mode.h>
/ {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "rockchip,rk3288";
@@ -139,13 +139,13 @@
amba {
compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
dmac_peri: dma-controller@ff250000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0xff250000 0x4000>;
+ reg = <0x0 0xff250000 0x0 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
@@ -156,7 +156,7 @@
dmac_bus_ns: dma-controller@ff600000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0xff600000 0x4000>;
+ reg = <0x0 0xff600000 0x0 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
@@ -168,7 +168,7 @@
dmac_bus_s: dma-controller@ffb20000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0xffb20000 0x4000>;
+ reg = <0x0 0xffb20000 0x0 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
@@ -179,8 +179,8 @@
};
reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
/*
@@ -194,7 +194,7 @@
* is found.
*/
dma-unusable@fe000000 {
- reg = <0xfe000000 0x1000000>;
+ reg = <0x0 0xfe000000 0x0 0x1000000>;
};
};
@@ -217,7 +217,7 @@
timer: timer@ff810000 {
compatible = "rockchip,rk3288-timer";
- reg = <0xff810000 0x20>;
+ reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>;
clock-names = "timer", "pclk";
@@ -236,7 +236,7 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xff0c0000 0x4000>;
+ reg = <0x0 0xff0c0000 0x0 0x4000>;
resets = <&cru SRST_MMC0>;
reset-names = "reset";
status = "disabled";
@@ -250,7 +250,7 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xff0d0000 0x4000>;
+ reg = <0x0 0xff0d0000 0x0 0x4000>;
resets = <&cru SRST_SDIO0>;
reset-names = "reset";
status = "disabled";
@@ -264,7 +264,7 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xff0e0000 0x4000>;
+ reg = <0x0 0xff0e0000 0x0 0x4000>;
resets = <&cru SRST_SDIO1>;
reset-names = "reset";
status = "disabled";
@@ -278,7 +278,7 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xff0f0000 0x4000>;
+ reg = <0x0 0xff0f0000 0x0 0x4000>;
resets = <&cru SRST_EMMC>;
reset-names = "reset";
status = "disabled";
@@ -286,7 +286,7 @@
saradc: saradc@ff100000 {
compatible = "rockchip,saradc";
- reg = <0xff100000 0x100>;
+ reg = <0x0 0xff100000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
@@ -305,7 +305,7 @@
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
- reg = <0xff110000 0x1000>;
+ reg = <0x0 0xff110000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -320,7 +320,7 @@
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
- reg = <0xff120000 0x1000>;
+ reg = <0x0 0xff120000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -335,7 +335,7 @@
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
- reg = <0xff130000 0x1000>;
+ reg = <0x0 0xff130000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -343,7 +343,7 @@
i2c1: i2c@ff140000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff140000 0x1000>;
+ reg = <0x0 0xff140000 0x0 0x1000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -356,7 +356,7 @@
i2c3: i2c@ff150000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff150000 0x1000>;
+ reg = <0x0 0xff150000 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -369,7 +369,7 @@
i2c4: i2c@ff160000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff160000 0x1000>;
+ reg = <0x0 0xff160000 0x0 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -382,7 +382,7 @@
i2c5: i2c@ff170000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff170000 0x1000>;
+ reg = <0x0 0xff170000 0x0 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -395,7 +395,7 @@
uart0: serial@ff180000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff180000 0x100>;
+ reg = <0x0 0xff180000 0x0 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -408,7 +408,7 @@
uart1: serial@ff190000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff190000 0x100>;
+ reg = <0x0 0xff190000 0x0 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -421,7 +421,7 @@
uart2: serial@ff690000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff690000 0x100>;
+ reg = <0x0 0xff690000 0x0 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -434,7 +434,7 @@
uart3: serial@ff1b0000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff1b0000 0x100>;
+ reg = <0x0 0xff1b0000 0x0 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -447,7 +447,7 @@
uart4: serial@ff1c0000 {
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
- reg = <0xff1c0000 0x100>;
+ reg = <0x0 0xff1c0000 0x0 0x100>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -535,7 +535,7 @@
tsadc: tsadc@ff280000 {
compatible = "rockchip,rk3288-tsadc";
- reg = <0xff280000 0x100>;
+ reg = <0x0 0xff280000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
@@ -552,7 +552,7 @@
gmac: ethernet@ff290000 {
compatible = "rockchip,rk3288-gmac";
- reg = <0xff290000 0x10000>;
+ reg = <0x0 0xff290000 0x0 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
@@ -572,7 +572,7 @@
usb_host0_ehci: usb@ff500000 {
compatible = "generic-ehci";
- reg = <0xff500000 0x100>;
+ reg = <0x0 0xff500000 0x0 0x100>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST0>;
clock-names = "usbhost";
@@ -586,7 +586,7 @@
usb_host1: usb@ff540000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
"snps,dwc2";
- reg = <0xff540000 0x40000>;
+ reg = <0x0 0xff540000 0x0 0x40000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST1>;
clock-names = "otg";
@@ -599,7 +599,7 @@
usb_otg: usb@ff580000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
"snps,dwc2";
- reg = <0xff580000 0x40000>;
+ reg = <0x0 0xff580000 0x0 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG0>;
clock-names = "otg";
@@ -614,7 +614,7 @@
usb_hsic: usb@ff5c0000 {
compatible = "generic-ehci";
- reg = <0xff5c0000 0x100>;
+ reg = <0x0 0xff5c0000 0x0 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HSIC>;
clock-names = "usbhost";
@@ -623,7 +623,7 @@
i2c0: i2c@ff650000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff650000 0x1000>;
+ reg = <0x0 0xff650000 0x0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -636,7 +636,7 @@
i2c2: i2c@ff660000 {
compatible = "rockchip,rk3288-i2c";
- reg = <0xff660000 0x1000>;
+ reg = <0x0 0xff660000 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -649,7 +649,7 @@
pwm0: pwm@ff680000 {
compatible = "rockchip,rk3288-pwm";
- reg = <0xff680000 0x10>;
+ reg = <0x0 0xff680000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@@ -660,7 +660,7 @@
pwm1: pwm@ff680010 {
compatible = "rockchip,rk3288-pwm";
- reg = <0xff680010 0x10>;
+ reg = <0x0 0xff680010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
@@ -671,7 +671,7 @@
pwm2: pwm@ff680020 {
compatible = "rockchip,rk3288-pwm";
- reg = <0xff680020 0x10>;
+ reg = <0x0 0xff680020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
@@ -682,7 +682,7 @@
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3288-pwm";
- reg = <0xff680030 0x10>;
+ reg = <0x0 0xff680030 0x0 0x10>;
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
@@ -693,10 +693,10 @@
bus_intmem@ff700000 {
compatible = "mmio-sram";
- reg = <0xff700000 0x18000>;
+ reg = <0x0 0xff700000 0x0 0x18000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0xff700000 0x18000>;
+ ranges = <0 0x0 0xff700000 0x18000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x00 0x10>;
@@ -705,12 +705,12 @@
sram@ff720000 {
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
- reg = <0xff720000 0x1000>;
+ reg = <0x0 0xff720000 0x0 0x1000>;
};
pmu: power-management@ff730000 {
compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
- reg = <0xff730000 0x100>;
+ reg = <0x0 0xff730000 0x0 0x100>;
power: power-controller {
compatible = "rockchip,rk3288-power-controller";
@@ -831,12 +831,12 @@
sgrf: syscon@ff740000 {
compatible = "rockchip,rk3288-sgrf", "syscon";
- reg = <0xff740000 0x1000>;
+ reg = <0x0 0xff740000 0x0 0x1000>;
};
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3288-cru";
- reg = <0xff760000 0x1000>;
+ reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -854,7 +854,7 @@
grf: syscon@ff770000 {
compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
- reg = <0xff770000 0x1000>;
+ reg = <0x0 0xff770000 0x0 0x1000>;
edp_phy: edp-phy {
compatible = "rockchip,rk3288-dp-phy";
@@ -903,7 +903,7 @@
wdt: watchdog@ff800000 {
compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
- reg = <0xff800000 0x100>;
+ reg = <0x0 0xff800000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -911,7 +911,7 @@
spdif: sound@ff88b0000 {
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
- reg = <0xff8b0000 0x10000>;
+ reg = <0x0 0xff8b0000 0x0 0x10000>;
#sound-dai-cells = <0>;
clock-names = "hclk", "mclk";
clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
@@ -926,7 +926,7 @@
i2s: i2s@ff890000 {
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
- reg = <0xff890000 0x10000>;
+ reg = <0x0 0xff890000 0x0 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -943,7 +943,7 @@
crypto: cypto-controller@ff8a0000 {
compatible = "rockchip,rk3288-crypto";
- reg = <0xff8a0000 0x4000>;
+ reg = <0x0 0xff8a0000 0x0 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
@@ -953,9 +953,28 @@
status = "okay";
};
+ iep_mmu: iommu@ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff900800 0x0 0x40>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ isp_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff930000 0x19c>;
+ reg = <0x0 0xff930000 0x0 0x19c>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -988,7 +1007,7 @@
vopb_mmu: iommu@ff930300 {
compatible = "rockchip,iommu";
- reg = <0xff930300 0x100>;
+ reg = <0x0 0xff930300 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
power-domains = <&power RK3288_PD_VIO>;
@@ -998,7 +1017,7 @@
vopl: vop@ff940000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff940000 0x19c>;
+ reg = <0x0 0xff940000 0x0 0x19c>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1031,7 +1050,7 @@
vopl_mmu: iommu@ff940300 {
compatible = "rockchip,iommu";
- reg = <0xff940300 0x100>;
+ reg = <0x0 0xff940300 0x0 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
power-domains = <&power RK3288_PD_VIO>;
@@ -1041,7 +1060,7 @@
mipi_dsi: mipi@ff960000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
- reg = <0xff960000 0x4000>;
+ reg = <0x0 0xff960000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
clock-names = "ref", "pclk";
@@ -1069,7 +1088,7 @@
edp: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
- reg = <0xff970000 0x4000>;
+ reg = <0x0 0xff970000 0x0 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
@@ -1101,7 +1120,7 @@
hdmi: hdmi@ff980000 {
compatible = "rockchip,rk3288-dw-hdmi";
- reg = <0xff980000 0x20000>;
+ reg = <0x0 0xff980000 0x0 0x20000>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
@@ -1126,9 +1145,27 @@
};
};
+ vpu_mmu: iommu@ff9a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ hevc_mmu: iommu@ff9c0440 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
gpu: gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
- reg = <0xffa30000 0x10000>;
+ reg = <0x0 0xffa30000 0x0 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -1170,72 +1207,72 @@
qos_gpu_r: qos@ffaa0000 {
compatible = "syscon";
- reg = <0xffaa0000 0x20>;
+ reg = <0x0 0xffaa0000 0x0 0x20>;
};
qos_gpu_w: qos@ffaa0080 {
compatible = "syscon";
- reg = <0xffaa0080 0x20>;
+ reg = <0x0 0xffaa0080 0x0 0x20>;
};
qos_vio1_vop: qos@ffad0000 {
compatible = "syscon";
- reg = <0xffad0000 0x20>;
+ reg = <0x0 0xffad0000 0x0 0x20>;
};
qos_vio1_isp_w0: qos@ffad0100 {
compatible = "syscon";
- reg = <0xffad0100 0x20>;
+ reg = <0x0 0xffad0100 0x0 0x20>;
};
qos_vio1_isp_w1: qos@ffad0180 {
compatible = "syscon";
- reg = <0xffad0180 0x20>;
+ reg = <0x0 0xffad0180 0x0 0x20>;
};
qos_vio0_vop: qos@ffad0400 {
compatible = "syscon";
- reg = <0xffad0400 0x20>;
+ reg = <0x0 0xffad0400 0x0 0x20>;
};
qos_vio0_vip: qos@ffad0480 {
compatible = "syscon";
- reg = <0xffad0480 0x20>;
+ reg = <0x0 0xffad0480 0x0 0x20>;
};
qos_vio0_iep: qos@ffad0500 {
compatible = "syscon";
- reg = <0xffad0500 0x20>;
+ reg = <0x0 0xffad0500 0x0 0x20>;
};
qos_vio2_rga_r: qos@ffad0800 {
compatible = "syscon";
- reg = <0xffad0800 0x20>;
+ reg = <0x0 0xffad0800 0x0 0x20>;
};
qos_vio2_rga_w: qos@ffad0880 {
compatible = "syscon";
- reg = <0xffad0880 0x20>;
+ reg = <0x0 0xffad0880 0x0 0x20>;
};
qos_vio1_isp_r: qos@ffad0900 {
compatible = "syscon";
- reg = <0xffad0900 0x20>;
+ reg = <0x0 0xffad0900 0x0 0x20>;
};
qos_video: qos@ffae0000 {
compatible = "syscon";
- reg = <0xffae0000 0x20>;
+ reg = <0x0 0xffae0000 0x0 0x20>;
};
qos_hevc_r: qos@ffaf0000 {
compatible = "syscon";
- reg = <0xffaf0000 0x20>;
+ reg = <0x0 0xffaf0000 0x0 0x20>;
};
qos_hevc_w: qos@ffaf0080 {
compatible = "syscon";
- reg = <0xffaf0080 0x20>;
+ reg = <0x0 0xffaf0080 0x0 0x20>;
};
gic: interrupt-controller@ffc01000 {
@@ -1244,16 +1281,16 @@
#interrupt-cells = <3>;
#address-cells = <0>;
- reg = <0xffc01000 0x1000>,
- <0xffc02000 0x2000>,
- <0xffc04000 0x2000>,
- <0xffc06000 0x2000>;
+ reg = <0x0 0xffc01000 0x0 0x1000>,
+ <0x0 0xffc02000 0x0 0x2000>,
+ <0x0 0xffc04000 0x0 0x2000>,
+ <0x0 0xffc06000 0x0 0x2000>;
interrupts = <GIC_PPI 9 0xf04>;
};
efuse: efuse@ffb40000 {
compatible = "rockchip,rk3288-efuse";
- reg = <0xffb40000 0x20>;
+ reg = <0x0 0xffb40000 0x0 0x20>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru PCLK_EFUSE256>;
@@ -1268,13 +1305,13 @@
compatible = "rockchip,rk3288-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
gpio0: gpio0@ff750000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff750000 0x100>;
+ reg = <0x0 0xff750000 0x0 0x100>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
@@ -1287,7 +1324,7 @@
gpio1: gpio1@ff780000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff780000 0x100>;
+ reg = <0x0 0xff780000 0x0 0x100>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
@@ -1300,7 +1337,7 @@
gpio2: gpio2@ff790000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff790000 0x100>;
+ reg = <0x0 0xff790000 0x0 0x100>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
@@ -1313,7 +1350,7 @@
gpio3: gpio3@ff7a0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7a0000 0x100>;
+ reg = <0x0 0xff7a0000 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
@@ -1326,7 +1363,7 @@
gpio4: gpio4@ff7b0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7b0000 0x100>;
+ reg = <0x0 0xff7b0000 0x0 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>;
@@ -1339,7 +1376,7 @@
gpio5: gpio5@ff7c0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7c0000 0x100>;
+ reg = <0x0 0xff7c0000 0x0 0x100>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO5>;
@@ -1352,7 +1389,7 @@
gpio6: gpio6@ff7d0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7d0000 0x100>;
+ reg = <0x0 0xff7d0000 0x0 0x100>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO6>;
@@ -1365,7 +1402,7 @@
gpio7: gpio7@ff7e0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7e0000 0x100>;
+ reg = <0x0 0xff7e0000 0x0 0x100>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO7>;
@@ -1378,7 +1415,7 @@
gpio8: gpio8@ff7f0000 {
compatible = "rockchip,gpio-bank";
- reg = <0xff7f0000 0x100>;
+ reg = <0x0 0xff7f0000 0x0 0x100>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO8>;
diff --git a/dts/src/arm/rv1108-evb.dts b/dts/src/arm/rv1108-evb.dts
index 58cf4ac079..86a57f8236 100644
--- a/dts/src/arm/rv1108-evb.dts
+++ b/dts/src/arm/rv1108-evb.dts
@@ -54,6 +54,184 @@
chosen {
stdout-path = "serial2:1500000n8";
};
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23
+ 24 25 26 27 28 29 30 31
+ 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ default-brightness-level = <200>;
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_core>;
+};
+
+&i2c0 {
+ status = "okay";
+ i2c-scl-rising-time-ns = <275>;
+ i2c-scl-falling-time-ns = <16>;
+ clock-frequency = <400000>;
+
+ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
+ rockchip,system-power-controller;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+
+ regulators {
+ vdd_core: DCDC_REG1 {
+ regulator-name= "vdd_core";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <900000>;
+ };
+ };
+
+ vdd_cam: DCDC_REG2 {
+ regulator-name= "vdd_cam";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name= "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name= "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <3300000>;
+ };
+ };
+
+ vdd_10: LDO_REG1 {
+ regulator-name= "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_18: LDO_REG2 {
+ regulator-name= "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vdd10_pmu: LDO_REG3 {
+ regulator-name= "vdd10_pmu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <1000000>;
+ };
+ };
+ };
+ };
+
+ bma250: accelerometer@19 {
+ compatible = "bosch,bma250e";
+ reg = <0x19>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB3 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&sdmmc {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
};
&uart0 {
@@ -67,3 +245,15 @@
&uart2 {
status = "okay";
};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
diff --git a/dts/src/arm/rv1108.dtsi b/dts/src/arm/rv1108.dtsi
index 437098b556..e7cd1315db 100644
--- a/dts/src/arm/rv1108.dtsi
+++ b/dts/src/arm/rv1108.dtsi
@@ -52,6 +52,10 @@
interrupt-parent = <&gic>;
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -65,6 +69,33 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
+ clocks = <&cru ARMCLK>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ };
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1025000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1150000>;
+ clock-latency-ns = <40000>;
};
};
@@ -154,9 +185,221 @@
status = "disabled";
};
+ i2c1: i2c@10240000 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x10240000 0x1000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@10250000 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x10250000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@10260000 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x10260000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_xfer>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ spi: spi@10270000 {
+ compatible = "rockchip,rv1108-spi";
+ reg = <0x10270000 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&pdma 8>, <&pdma 9>;
+ #dma-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@10280000 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280000 0x10>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm4_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@10280010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280010 0x10>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm5_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@10280020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280020 0x10>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm6_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm7: pwm@10280030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280030 0x10>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm7_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
grf: syscon@10300000 {
- compatible = "rockchip,rv1108-grf", "syscon";
+ compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
reg = <0x10300000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2-phy@100 {
+ compatible = "rockchip,rv1108-usb2phy";
+ reg = <0x100 0x0c>;
+ clocks = <&cru SCLK_USBPHY>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "usbphy";
+ rockchip,usbgrf = <&usbgrf>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-mux";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ watchdog: wdt@10360000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10360000 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_WDT>;
+ clock-names = "pclk_wdt";
+ status = "disabled";
+ };
+
+ adc: adc@1038c000 {
+ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+ reg = <0x1038c000 0x100>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clock-frequency = <1000000>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ status = "disabled";
+ };
+
+ i2c0: i2c@20000000 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x20000000 0x1000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@20040000 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040000 0x10>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@20040010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040010 0x10>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@20040020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040020 0x10>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@20040030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040030 0x10>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
};
pmugrf: syscon@20060000 {
@@ -164,6 +407,11 @@
reg = <0x20060000 0x1000>;
};
+ usbgrf: syscon@202a0000 {
+ compatible = "rockchip,rv1108-usbgrf", "syscon";
+ reg = <0x202a0000 0x1000>;
+ };
+
cru: clock-controller@20200000 {
compatible = "rockchip,rv1108-cru";
reg = <0x20200000 0x1000>;
@@ -174,37 +422,78 @@
emmc: dwmmc@30110000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 150000000>;
+ reg = <0x30110000 0x4000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x30110000 0x4000>;
+ max-frequency = <150000000>;
status = "disabled";
};
sdio: dwmmc@30120000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 150000000>;
+ reg = <0x30120000 0x4000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x30120000 0x4000>;
+ max-frequency = <150000000>;
status = "disabled";
};
sdmmc: dwmmc@30130000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 100000000>;
+ reg = <0x30130000 0x4000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x30130000 0x4000>;
+ max-frequency = <100000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "disabled";
+ };
+
+ usb_host_ehci: usb@30140000 {
+ compatible = "generic-ehci";
+ reg = <0x30140000 0x20000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@30160000 {
+ compatible = "generic-ohci";
+ reg = <0x30160000 0x20000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_otg: usb@30180000 {
+ compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x30180000 0x40000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ g-use-dma;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
status = "disabled";
};
@@ -301,6 +590,11 @@
drive-strength = <12>;
};
+ pcfg_pull_none_smt: pcfg-pull-none-smt {
+ bias-disable;
+ input-schmitt-enable;
+ };
+
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
bias-pull-up;
drive-strength = <8>;
@@ -328,6 +622,13 @@
input-enable;
};
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
+ <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
+ };
+ };
+
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
@@ -366,6 +667,54 @@
};
};
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm4 {
+ pwm4_pin: pwm4-pin {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm5 {
+ pwm5_pin: pwm5-pin {
+ rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm6 {
+ pwm6_pin: pwm6-pin {
+ rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm7 {
+ pwm7_pin: pwm7-pin {
+ rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
diff --git a/dts/src/arm/sama5d2.dtsi b/dts/src/arm/sama5d2.dtsi
index 60e69aeacb..38d2216c7e 100644
--- a/dts/src/arm/sama5d2.dtsi
+++ b/dts/src/arm/sama5d2.dtsi
@@ -416,6 +416,17 @@
};
};
+ isc: isc@f0008000 {
+ compatible = "atmel,sama5d2-isc";
+ reg = <0xf0008000 0x4000>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
+ clock-names = "hclock", "iscck", "gck";
+ #clock-cells = <0>;
+ clock-output-names = "isc-mck";
+ status = "disabled";
+ };
+
ramc0: ramc@f000c000 {
compatible = "atmel,sama5d3-ddramc";
reg = <0xf000c000 0x200>;
@@ -494,6 +505,24 @@
clocks = <&plla>;
};
+ audio_pll_frac: audiopll_fracck {
+ compatible = "atmel,sama5d2-clk-audio-pll-frac";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ audio_pll_pad: audiopll_padck {
+ compatible = "atmel,sama5d2-clk-audio-pll-pad";
+ #clock-cells = <0>;
+ clocks = <&audio_pll_frac>;
+ };
+
+ audio_pll_pmc: audiopll_pmcck {
+ compatible = "atmel,sama5d2-clk-audio-pll-pmc";
+ #clock-cells = <0>;
+ clocks = <&audio_pll_frac>;
+ };
+
utmi: utmick {
compatible = "atmel,at91sam9x5-clk-utmi";
#clock-cells = <0>;
@@ -895,7 +924,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
sdmmc0_gclk: sdmmc0_gclk {
#clock-cells = <0>;
@@ -925,6 +954,11 @@
atmel,clk-output-range = <0 83000000>;
};
+ isc_gclk: isc_gclk {
+ #clock-cells = <0>;
+ reg = <46>;
+ };
+
pdmic_gclk: pdmic_gclk {
#clock-cells = <0>;
reg = <48>;
@@ -951,9 +985,37 @@
reg = <57>;
atmel,clk-output-range = <0 80000000>;
};
+
+ classd_gclk: classd_gclk {
+ #clock-cells = <0>;
+ reg = <59>;
+ atmel,clk-output-range = <0 100000000>;
+ };
};
};
+ qspi0: spi@f0020000 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&qspi0_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi1: spi@f0024000 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&qspi1_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sha@f0028000 {
compatible = "atmel,at91sam9g46-sha";
reg = <0xf0028000 0x100>;
@@ -1406,6 +1468,19 @@
status = "okay";
};
+ classd: classd@fc048000 {
+ compatible = "atmel,sama5d2-classd";
+ reg = <0xfc048000 0x100>;
+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(47))>;
+ dma-names = "tx";
+ clocks = <&classd_clk>, <&classd_gclk>;
+ clock-names = "pclk", "gclk";
+ status = "disabled";
+ };
+
can1: can@fc050000 {
compatible = "bosch,m_can";
reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
diff --git a/dts/src/arm/spear1310.dtsi b/dts/src/arm/spear1310.dtsi
index 54bc6d3cf2..40f4ad3c34 100644
--- a/dts/src/arm/spear1310.dtsi
+++ b/dts/src/arm/spear1310.dtsi
@@ -98,6 +98,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ bus-range = <0x00 0xff>;
status = "disabled";
};
@@ -116,6 +117,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ bus-range = <0x00 0xff>;
status = "disabled";
};
@@ -134,6 +136,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ bus-range = <0x00 0xff>;
status = "disabled";
};
diff --git a/dts/src/arm/spear1340.dtsi b/dts/src/arm/spear1340.dtsi
index df2232d767..5f34705452 100644
--- a/dts/src/arm/spear1340.dtsi
+++ b/dts/src/arm/spear1340.dtsi
@@ -63,6 +63,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ bus-range = <0x00 0xff>;
status = "disabled";
};
diff --git a/dts/src/arm/ste-dbx5x0.dtsi b/dts/src/arm/ste-dbx5x0.dtsi
index 6c5affe2d0..2310a4e977 100644
--- a/dts/src/arm/ste-dbx5x0.dtsi
+++ b/dts/src/arm/ste-dbx5x0.dtsi
@@ -37,6 +37,14 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x300>;
+ /* cpufreq controls */
+ operating-points = <998400 0
+ 800000 0
+ 400000 0
+ 200000 0>;
+ clocks = <&prcmu_clk PRCMU_ARMSS>;
+ clock-names = "cpu";
+ clock-latency = <20000>;
};
CPU1: cpu@301 {
device_type = "cpu";
@@ -494,13 +502,6 @@
reg = <0x80157450 0xC>;
};
- cpufreq {
- compatible = "stericsson,cpufreq-ux500";
- clocks = <&prcmu_clk PRCMU_ARMSS>;
- clock-names = "armss";
- status = "disabled";
- };
-
thermal@801573c0 {
compatible = "stericsson,db8500-thermal";
reg = <0x801573c0 0x40>;
diff --git a/dts/src/arm/ste-hrefprev60.dtsi b/dts/src/arm/ste-hrefprev60.dtsi
index 5882a2606a..3f14b4df69 100644
--- a/dts/src/arm/ste-hrefprev60.dtsi
+++ b/dts/src/arm/ste-hrefprev60.dtsi
@@ -30,7 +30,7 @@
i2c@80004000 {
tps61052@33 {
- compatible = "tps61052";
+ compatible = "ti,tps61052";
reg = <0x33>;
};
diff --git a/dts/src/arm/stm32429i-eval.dts b/dts/src/arm/stm32429i-eval.dts
index dcda0bbefe..97b1c2321b 100644
--- a/dts/src/arm/stm32429i-eval.dts
+++ b/dts/src/arm/stm32429i-eval.dts
@@ -55,7 +55,7 @@
compatible = "st,stm32429i-eval", "st,stm32f429";
chosen {
- bootargs = "root=/dev/ram rdinit=/linuxrc";
+ bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/stm32f429-disco.dts b/dts/src/arm/stm32f429-disco.dts
index ae47cde795..c66d617e42 100644
--- a/dts/src/arm/stm32f429-disco.dts
+++ b/dts/src/arm/stm32f429-disco.dts
@@ -54,7 +54,7 @@
compatible = "st,stm32f429i-disco", "st,stm32f429";
chosen {
- bootargs = "root=/dev/ram rdinit=/linuxrc";
+ bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/stm32f429.dtsi b/dts/src/arm/stm32f429.dtsi
index a8113dc879..dd7e99b1f4 100644
--- a/dts/src/arm/stm32f429.dtsi
+++ b/dts/src/arm/stm32f429.dtsi
@@ -361,6 +361,31 @@
status = "disabled";
};
+ dac: dac@40007400 {
+ compatible = "st,stm32f4-dac-core";
+ reg = <0x40007400 0x400>;
+ resets = <&rcc STM32F4_APB1_RESET(DAC)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dac1: dac@1 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <1>;
+ status = "disabled";
+ };
+
+ dac2: dac@2 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
usart7: serial@40007800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40007800 0x400>;
diff --git a/dts/src/arm/stm32f469-disco.dts b/dts/src/arm/stm32f469-disco.dts
index 75470c34b9..6ae1f037f3 100644
--- a/dts/src/arm/stm32f469-disco.dts
+++ b/dts/src/arm/stm32f469-disco.dts
@@ -53,7 +53,7 @@
compatible = "st,stm32f469i-disco", "st,stm32f469";
chosen {
- bootargs = "root=/dev/ram rdinit=/linuxrc";
+ bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/stm32f746.dtsi b/dts/src/arm/stm32f746.dtsi
index 4506eb97a4..5633860037 100644
--- a/dts/src/arm/stm32f746.dtsi
+++ b/dts/src/arm/stm32f746.dtsi
@@ -167,6 +167,15 @@
status = "disabled";
};
+ cec: cec@40006c00 {
+ compatible = "st,stm32-cec";
+ reg = <0x40006C00 0x400>;
+ interrupts = <94>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
+ clock-names = "cec", "hdmi-cec";
+ status = "disabled";
+ };
+
usart7: serial@40007800 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40007800 0x400>;
@@ -336,6 +345,15 @@
st,bank-name = "GPIOK";
};
+ cec_pins_a: cec@0 {
+ pins {
+ pinmux = <STM32F746_PA15_FUNC_HDMI_CEC>;
+ slew-rate = <0>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
@@ -380,6 +398,39 @@
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
assigned-clock-rates = <1000000>;
};
+
+ dma1: dma@40026000 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026000 0x400>;
+ interrupts = <11>,
+ <12>,
+ <13>,
+ <14>,
+ <15>,
+ <16>,
+ <17>,
+ <47>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
+ #dma-cells = <4>;
+ status = "disabled";
+ };
+
+ dma2: dma@40026400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026400 0x400>;
+ interrupts = <56>,
+ <57>,
+ <58>,
+ <59>,
+ <60>,
+ <68>,
+ <69>,
+ <70>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ status = "disabled";
+ };
};
};
diff --git a/dts/src/arm/stm32f769-disco.dts b/dts/src/arm/stm32f769-disco.dts
index 166728aeb1..4463ca13a7 100644
--- a/dts/src/arm/stm32f769-disco.dts
+++ b/dts/src/arm/stm32f769-disco.dts
@@ -63,6 +63,12 @@
};
+&cec {
+ pinctrl-0 = <&cec_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&clk_hse {
clock-frequency = <25000000>;
};
diff --git a/dts/src/arm/stm32h743.dtsi b/dts/src/arm/stm32h743.dtsi
index 36a99db0a3..58ec227518 100644
--- a/dts/src/arm/stm32h743.dtsi
+++ b/dts/src/arm/stm32h743.dtsi
@@ -59,6 +59,45 @@
};
soc {
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&timer_clk>;
+ };
+
+ usart2: serial@40004400 {
+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ reg = <0x40004400 0x400>;
+ interrupts = <38>;
+ status = "disabled";
+ clocks = <&timer_clk>;
+ };
+
+ dac: dac@40007400 {
+ compatible = "st,stm32h7-dac-core";
+ reg = <0x40007400 0x400>;
+ clocks = <&timer_clk>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dac1: dac@1 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <1>;
+ status = "disabled";
+ };
+
+ dac2: dac@2 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
usart1: serial@40011000 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
@@ -68,19 +107,91 @@
};
- usart2: serial@40004400 {
- compatible = "st,stm32f7-usart", "st,stm32f7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
+ dma1: dma@40020000 {
+ compatible = "st,stm32-dma";
+ reg = <0x40020000 0x400>;
+ interrupts = <11>,
+ <12>,
+ <13>,
+ <14>,
+ <15>,
+ <16>,
+ <17>,
+ <47>;
+ clocks = <&timer_clk>;
+ #dma-cells = <4>;
+ st,mem2mem;
status = "disabled";
+ };
+
+ dma2: dma@40020400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40020400 0x400>;
+ interrupts = <56>,
+ <57>,
+ <58>,
+ <59>,
+ <60>,
+ <68>,
+ <69>,
+ <70>;
clocks = <&timer_clk>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ status = "disabled";
};
- timer5: timer@40000c00 {
- compatible = "st,stm32-timer";
- reg = <0x40000c00 0x400>;
- interrupts = <50>;
+ adc_12: adc@40022000 {
+ compatible = "st,stm32h7-adc-core";
+ reg = <0x40022000 0x400>;
+ interrupts = <18>;
+ clocks = <&timer_clk>;
+ clock-names = "bus";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc1: adc@0 {
+ compatible = "st,stm32h7-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_12>;
+ interrupts = <0>;
+ status = "disabled";
+ };
+
+ adc2: adc@100 {
+ compatible = "st,stm32h7-adc";
+ #io-channel-cells = <1>;
+ reg = <0x100>;
+ interrupt-parent = <&adc_12>;
+ interrupts = <1>;
+ status = "disabled";
+ };
+ };
+
+ adc_3: adc@58026000 {
+ compatible = "st,stm32h7-adc-core";
+ reg = <0x58026000 0x400>;
+ interrupts = <127>;
clocks = <&timer_clk>;
+ clock-names = "bus";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc3: adc@0 {
+ compatible = "st,stm32h7-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_3>;
+ interrupts = <0>;
+ status = "disabled";
+ };
};
};
};
diff --git a/dts/src/arm/stm32h743i-eval.dts b/dts/src/arm/stm32h743i-eval.dts
index c6effbb36e..6c07786e7d 100644
--- a/dts/src/arm/stm32h743i-eval.dts
+++ b/dts/src/arm/stm32h743i-eval.dts
@@ -60,6 +60,24 @@
aliases {
serial0 = &usart1;
};
+
+ vdda: regulator-vdda {
+ compatible = "regulator-fixed";
+ regulator-name = "vdda";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&adc_12 {
+ vref-supply = <&vdda>;
+ status = "okay";
+ adc1: adc@0 {
+ /* potentiometer */
+ st,adc-channels = <0>;
+ status = "okay";
+ };
};
&clk_hse {
diff --git a/dts/src/arm/sun6i-a31.dtsi b/dts/src/arm/sun6i-a31.dtsi
index aebc3f9dc7..b147cb0dc1 100644
--- a/dts/src/arm/sun6i-a31.dtsi
+++ b/dts/src/arm/sun6i-a31.dtsi
@@ -1155,11 +1155,11 @@
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
- nmi_intc: interrupt-controller@01f00c0c {
- compatible = "allwinner,sun6i-a31-sc-nmi";
+ nmi_intc: interrupt-controller@1f00c00 {
+ compatible = "allwinner,sun6i-a31-r-intc";
interrupt-controller;
#interrupt-cells = <2>;
- reg = <0x01f00c0c 0x38>;
+ reg = <0x01f00c00 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/dts/src/arm/sun7i-a20-cubietruck.dts b/dts/src/arm/sun7i-a20-cubietruck.dts
index bb51018760..852a0aa24d 100644
--- a/dts/src/arm/sun7i-a20-cubietruck.dts
+++ b/dts/src/arm/sun7i-a20-cubietruck.dts
@@ -271,6 +271,10 @@
status = "okay";
};
+&battery_power_supply {
+ status = "okay";
+};
+
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
diff --git a/dts/src/arm/sun8i-a23-a33.dtsi b/dts/src/arm/sun8i-a23-a33.dtsi
index a8b978d0f3..ea50dda75a 100644
--- a/dts/src/arm/sun8i-a23-a33.dtsi
+++ b/dts/src/arm/sun8i-a23-a33.dtsi
@@ -519,11 +519,11 @@
#clock-cells = <1>;
};
- nmi_intc: interrupt-controller@01f00c0c {
- compatible = "allwinner,sun6i-a31-sc-nmi";
+ nmi_intc: interrupt-controller@1f00c00 {
+ compatible = "allwinner,sun6i-a31-r-intc";
interrupt-controller;
#interrupt-cells = <2>;
- reg = <0x01f00c0c 0x38>;
+ reg = <0x01f00c00 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/dts/src/arm/sun8i-a83t-allwinner-h8homlet-v2.dts b/dts/src/arm/sun8i-a83t-allwinner-h8homlet-v2.dts
index aecdeeb368..1f0d60afb2 100644
--- a/dts/src/arm/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/dts/src/arm/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,6 +43,7 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
/ {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -57,8 +58,92 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v0>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ bus-width = <4>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&reg_usb0_vbus {
+ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+ status = "okay";
+};
+
+&reg_usb1_vbus {
+ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp81x: pmic@3a3 {
+ compatible = "x-powers,axp818", "x-powers,axp813";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ ac100: codec@e89 {
+ compatible = "x-powers,ac100";
+ reg = <0xe89>;
+
+ ac100_codec: codec {
+ compatible = "x-powers,ac100-codec";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
+ #clock-cells = <0>;
+ clock-output-names = "4M_adda";
+ };
+
+ ac100_rtc: rtc {
+ compatible = "x-powers,ac100-rtc";
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ac100_codec>;
+ #clock-cells = <1>;
+ clock-output-names = "cko1_rtc",
+ "cko2_rtc",
+ "cko3_rtc";
+ };
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
+
+&usbphy {
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/dts/src/arm/sun8i-a83t-bananapi-m3.dts b/dts/src/arm/sun8i-a83t-bananapi-m3.dts
new file mode 100644
index 0000000000..2bafd7e99e
--- /dev/null
+++ b/dts/src/arm/sun8i-a83t-bananapi-m3.dts
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Banana Pi BPI-M3";
+ compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
+ status = "okay";
+
+ /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp81x: pmic@3a3 {
+ compatible = "x-powers,axp813";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ ac100: codec@e89 {
+ compatible = "x-powers,ac100";
+ reg = <0xe89>;
+
+ ac100_codec: codec {
+ compatible = "x-powers,ac100-codec";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
+ #clock-cells = <0>;
+ clock-output-names = "4M_adda";
+ };
+
+ ac100_rtc: rtc {
+ compatible = "x-powers,ac100-rtc";
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ac100_codec>;
+ #clock-cells = <1>;
+ clock-output-names = "cko1_rtc",
+ "cko2_rtc",
+ "cko3_rtc";
+ };
+ };
+};
+
+&reg_usb1_vbus {
+ gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ status = "okay";
+};
+
+&reg_vcc3v0 {
+ status = "disabled";
+};
+
+&reg_vcc5v0 {
+ status = "disabled";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
diff --git a/dts/src/arm/sun8i-a83t-cubietruck-plus.dts b/dts/src/arm/sun8i-a83t-cubietruck-plus.dts
index cff33454fc..716a205c6d 100644
--- a/dts/src/arm/sun8i-a83t-cubietruck-plus.dts
+++ b/dts/src/arm/sun8i-a83t-cubietruck-plus.dts
@@ -44,6 +44,7 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -83,6 +84,17 @@
};
};
+ usb-hub {
+ /* I2C is not connected */
+ compatible = "smsc,usb3503";
+ initial-mode = <1>; /* initialize in HUB mode */
+ disabled-ports = <1>;
+ intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+ connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+ refclk-frequency = <19200000>;
+ };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "On-board SPDIF";
@@ -102,6 +114,89 @@
};
};
+&ehci0 {
+ /* GL830 USB-to-SATA bridge here */
+ status = "okay";
+};
+
+&ehci1 {
+ /* USB3503 HSIC USB 2.0 hub here */
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp81x: pmic@3a3 {
+ compatible = "x-powers,axp818", "x-powers,axp813";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ ac100: codec@e89 {
+ compatible = "x-powers,ac100";
+ reg = <0xe89>;
+
+ ac100_codec: codec {
+ compatible = "x-powers,ac100-codec";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
+ #clock-cells = <0>;
+ clock-output-names = "4M_adda";
+ };
+
+ ac100_rtc: rtc {
+ compatible = "x-powers,ac100-rtc";
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ac100_codec>;
+ #clock-cells = <1>;
+ clock-output-names = "cko1_rtc",
+ "cko2_rtc",
+ "cko3_rtc";
+ };
+ };
+};
+
+&reg_usb1_vbus {
+ gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
+ status = "okay";
+};
+
+&reg_usb2_vbus {
+ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ status = "okay";
+};
+
+&reg_vcc3v0 {
+ status = "disabled";
+};
+
+&reg_vcc5v0 {
+ status = "disabled";
+};
+
&spdif {
status = "okay";
};
@@ -111,3 +206,9 @@
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ usb2_vbus-supply = <&reg_usb2_vbus>;
+ status = "okay";
+};
diff --git a/dts/src/arm/sun8i-a83t.dtsi b/dts/src/arm/sun8i-a83t.dtsi
index 19a8f4fcfa..f996bd343e 100644
--- a/dts/src/arm/sun8i-a83t.dtsi
+++ b/dts/src/arm/sun8i-a83t.dtsi
@@ -47,6 +47,7 @@
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -182,6 +183,141 @@
#dma-cells = <1>;
};
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun8i-a83t-mmc",
+ "allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,sun8i-a83t-mmc",
+ "allwinner,sun7i-a20-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@1c11000 {
+ compatible = "allwinner,sun8i-a83t-emmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb_otg: usb@01c19000 {
+ compatible = "allwinner,sun8i-a83t-musb",
+ "allwinner,sun8i-a33-musb";
+ reg = <0x01c19000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c19400 {
+ compatible = "allwinner,sun8i-a83t-usb-phy";
+ reg = <0x01c19400 0x10>,
+ <0x01c1a800 0x14>,
+ <0x01c1b800 0x14>;
+ reg-names = "phy_ctrl",
+ "pmu1",
+ "pmu2";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_HSIC>,
+ <&ccu CLK_USB_HSIC_12M>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb2_hsic_12M";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_HSIC>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@1c1a000 {
+ compatible = "allwinner,sun8i-a83t-ehci",
+ "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@1c1a400 {
+ compatible = "allwinner,sun8i-a83t-ohci",
+ "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@1c1b000 {
+ compatible = "allwinner,sun8i-a83t-ehci",
+ "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI1>;
+ resets = <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-a83t-ccu";
reg = <0x01c20000 0x400>;
@@ -212,6 +348,15 @@
bias-pull-up;
};
+ mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
+ pins = "PC5", "PC6", "PC8", "PC9",
+ "PC10", "PC11", "PC12", "PC13",
+ "PC14", "PC15", "PC16";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
spdif_tx_pin: spdif-tx-pin {
pins = "PE18";
function = "spdif";
@@ -281,6 +426,15 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ r_intc: interrupt-controller@1f00c00 {
+ compatible = "allwinner,sun8i-a83t-r-intc",
+ "allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c00 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-a83t-r-ccu";
reg = <0x01f01400 0x400>;
@@ -302,6 +456,28 @@
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+
+ r_rsb_pins: r-rsb-pins {
+ pins = "PL0", "PL1";
+ function = "s_rsb";
+ drive-strength = <20>;
+ bias-pull-up;
+ };
+ };
+
+ r_rsb: rsb@1f03400 {
+ compatible = "allwinner,sun8i-a83t-rsb",
+ "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_APB0_RSB>;
+ clock-frequency = <3000000>;
+ resets = <&r_ccu RST_APB0_RSB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
diff --git a/dts/src/arm/sun8i-h3-beelink-x2.dts b/dts/src/arm/sun8i-h3-beelink-x2.dts
index e7fae65eb5..10da56e86a 100644
--- a/dts/src/arm/sun8i-h3-beelink-x2.dts
+++ b/dts/src/arm/sun8i-h3-beelink-x2.dts
@@ -100,6 +100,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -147,10 +151,19 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
+&reg_usb0_vbus {
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+};
+
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx_pins_a>;
@@ -163,7 +176,14 @@
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
- /* USB VBUS is on as long as VCC-IO is on */
+ /* USB VBUS is always on except for the OTG port */
status = "okay";
+ usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
};
diff --git a/dts/src/arm/sun8i-r16-bananapi-m2m.dts b/dts/src/arm/sun8i-r16-bananapi-m2m.dts
new file mode 100644
index 0000000000..eaf0966672
--- /dev/null
+++ b/dts/src/arm/sun8i-r16-bananapi-m2m.dts
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2017 Free Electrons <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BananaPi M2 Magic";
+ compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "bpi-m2m:blue:usr";
+ gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;
+ };
+
+ green {
+ label = "bpi-m2m:green:usr";
+ gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>;
+ };
+
+ red {
+ label = "bpi-m2m:red:power";
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc3>;
+};
+
+&cpu0_opp_table {
+ opp@1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+};
+
+&dai {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+/* This is the i2c bus exposed on the DSI connector for the touch panel */
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "disabled";
+};
+
+/* This is the i2c bus exposed on the GPIO header */
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "disabled";
+};
+
+/* This is the i2c bus exposed on the CSI connector to control the sensor */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "disabled";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <&reg_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <&reg_aldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp22x: pmic@3a3 {
+ compatible = "x-powers,axp223";
+ reg = <0x3a3>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <&reg_dcdc1>;
+ x-powers,drive-vbus-en;
+ };
+};
+
+#include "axp223.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&reg_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+&reg_dc1sw {
+ regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+/*
+ * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same
+ * time, with the two being in sync. Since this is not really
+ * supported right now, just use the two as always on, and we will fix
+ * it later.
+ */
+&reg_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi0";
+};
+
+&reg_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi1";
+};
+
+&reg_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&sound {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_b>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <&reg_drivevbus>;
+ usb1_vbus-supply = <&reg_vcc5v0>;
+ status = "okay";
+};
diff --git a/dts/src/arm/tango4-smp8758.dtsi b/dts/src/arm/tango4-smp8758.dtsi
index d2e65c46bc..eca33d5686 100644
--- a/dts/src/arm/tango4-smp8758.dtsi
+++ b/dts/src/arm/tango4-smp8758.dtsi
@@ -13,7 +13,6 @@
reg = <0>;
clocks = <&clkgen CPU_CLK>;
clock-latency = <1>;
- operating-points = <1215000 0 607500 0 405000 0 243000 0 135000 0>;
};
cpu1: cpu@1 {
diff --git a/dts/src/arm/tegra114-dalmore.dts b/dts/src/arm/tegra114-dalmore.dts
index 1444fbd543..5af4dd3219 100644
--- a/dts/src/arm/tegra114-dalmore.dts
+++ b/dts/src/arm/tegra114-dalmore.dts
@@ -1122,6 +1122,16 @@
non-removable;
};
+ usb@7d000000 {
+ compatible = "nvidia,tegra114-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ };
+
usb@7d008000 {
status = "okay";
};
diff --git a/dts/src/arm/tegra124-jetson-tk1.dts b/dts/src/arm/tegra124-jetson-tk1.dts
index 7bacb2954f..61873d642a 100644
--- a/dts/src/arm/tegra124-jetson-tk1.dts
+++ b/dts/src/arm/tegra124-jetson-tk1.dts
@@ -1722,7 +1722,7 @@
lanes {
usb2-0 {
- nvidia,function = "xusb";
+ nvidia,function = "snps";
status = "okay";
};
@@ -1829,6 +1829,16 @@
};
};
+ usb@7d000000 {
+ compatible = "nvidia,tegra124-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ };
+
/* mini-PCIe USB */
usb@7d004000 {
status = "okay";
diff --git a/dts/src/arm/tegra124.dtsi b/dts/src/arm/tegra124.dtsi
index 1b10b14a6a..8baf00b89e 100644
--- a/dts/src/arm/tegra124.dtsi
+++ b/dts/src/arm/tegra124.dtsi
@@ -87,6 +87,7 @@
clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
resets = <&tegra_car 28>;
reset-names = "host1x";
+ iommus = <&mc TEGRA_SWGROUP_HC>;
#address-cells = <2>;
#size-cells = <2>;
diff --git a/dts/src/arm/tegra20-paz00.dts b/dts/src/arm/tegra20-paz00.dts
index b4bfa5586c..bfa9421fcf 100644
--- a/dts/src/arm/tegra20-paz00.dts
+++ b/dts/src/arm/tegra20-paz00.dts
@@ -452,7 +452,9 @@
};
usb@c5000000 {
+ compatible = "nvidia,tegra20-udc";
status = "okay";
+ dr_mode = "peripheral";
};
usb-phy@c5000000 {
diff --git a/dts/src/arm/tegra30-beaver.dts b/dts/src/arm/tegra30-beaver.dts
index 4f41b18d95..3e104ddeb2 100644
--- a/dts/src/arm/tegra30-beaver.dts
+++ b/dts/src/arm/tegra30-beaver.dts
@@ -1927,6 +1927,16 @@
non-removable;
};
+ usb@7d000000 {
+ compatible = "nvidia,tegra30-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ };
+
usb@7d004000 {
status = "okay";
};
diff --git a/dts/src/arm/tps65217.dtsi b/dts/src/arm/tps65217.dtsi
index 02de56b558..399baaa0a2 100644
--- a/dts/src/arm/tps65217.dtsi
+++ b/dts/src/arm/tps65217.dtsi
@@ -18,11 +18,14 @@
charger {
compatible = "ti,tps65217-charger";
+ interrupts = <0>, <1>;
+ interrupt-names = "USB", "AC";
status = "disabled";
};
pwrbutton {
compatible = "ti,tps65217-pwrbutton";
+ interrupts = <2>;
status = "disabled";
};
diff --git a/dts/src/arm/uniphier-ld4-ref.dts b/dts/src/arm/uniphier-ld4-ref.dts
index 4817ebb28e..b3aaab354f 100644
--- a/dts/src/arm/uniphier-ld4-ref.dts
+++ b/dts/src/arm/uniphier-ld4-ref.dts
@@ -8,9 +8,9 @@
*/
/dts-v1/;
-/include/ "uniphier-ld4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld4.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD4 Reference Board";
@@ -64,3 +64,7 @@
&usb1 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
diff --git a/dts/src/arm/uniphier-ld4.dtsi b/dts/src/arm/uniphier-ld4.dtsi
index fb2fd9605b..79183db5b3 100644
--- a/dts/src/arm/uniphier-ld4.dtsi
+++ b/dts/src/arm/uniphier-ld4.dtsi
@@ -270,6 +270,13 @@
interrupt-controller;
};
+ aidet: aidet@61830000 {
+ compatible = "socionext,uniphier-ld4-aidet";
+ reg = <0x61830000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
sysctrl@61840000 {
compatible = "socionext,uniphier-ld4-sysctrl",
"simple-mfd", "syscon";
@@ -285,7 +292,18 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clocks = <&sys_clk 2>;
+ };
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
diff --git a/dts/src/arm/uniphier-ld6b-ref.dts b/dts/src/arm/uniphier-ld6b-ref.dts
index 96db4abc02..2188d114d7 100644
--- a/dts/src/arm/uniphier-ld6b-ref.dts
+++ b/dts/src/arm/uniphier-ld6b-ref.dts
@@ -8,9 +8,9 @@
*/
/dts-v1/;
-/include/ "uniphier-ld6b.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld6b.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD6b Reference Board";
@@ -58,3 +58,7 @@
&i2c0 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
diff --git a/dts/src/arm/uniphier-ld6b.dtsi b/dts/src/arm/uniphier-ld6b.dtsi
index 8b9a79731b..9a7b25cc82 100644
--- a/dts/src/arm/uniphier-ld6b.dtsi
+++ b/dts/src/arm/uniphier-ld6b.dtsi
@@ -12,7 +12,7 @@
* The D-chip (digital chip) is the same as the PXs2 die.
* Reuse the PXs2 device tree with some properties overridden.
*/
-/include/ "uniphier-pxs2.dtsi"
+#include "uniphier-pxs2.dtsi"
/ {
compatible = "socionext,uniphier-ld6b";
diff --git a/dts/src/arm/uniphier-pinctrl.dtsi b/dts/src/arm/uniphier-pinctrl.dtsi
index 246f35ffb6..be82cddc40 100644
--- a/dts/src/arm/uniphier-pinctrl.dtsi
+++ b/dts/src/arm/uniphier-pinctrl.dtsi
@@ -4,51 +4,35 @@
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
&pinctrl {
+ pinctrl_aout: aout_grp {
+ groups = "aout";
+ function = "aout";
+ };
+
pinctrl_emmc: emmc_grp {
groups = "emmc", "emmc_dat8";
function = "emmc";
};
+ pinctrl_ether_mii: ether_mii_grp {
+ groups = "ether_mii";
+ function = "ether_mii";
+ };
+
+ pinctrl_ether_rgmii: ether_rgmii_grp {
+ groups = "ether_rgmii";
+ function = "ether_rgmii";
+ };
+
+ pinctrl_ether_rmii: ether_rmii_grp {
+ groups = "ether_rmii";
+ function = "ether_rmii";
+ };
+
pinctrl_i2c0: i2c0_grp {
groups = "i2c0";
function = "i2c0";
diff --git a/dts/src/arm/uniphier-pro4-ace.dts b/dts/src/arm/uniphier-pro4-ace.dts
index 11690b5793..089419cee2 100644
--- a/dts/src/arm/uniphier-pro4-ace.dts
+++ b/dts/src/arm/uniphier-pro4-ace.dts
@@ -8,7 +8,7 @@
*/
/dts-v1/;
-/include/ "uniphier-pro4.dtsi"
+#include "uniphier-pro4.dtsi"
/ {
model = "UniPhier Pro4 Ace Board";
diff --git a/dts/src/arm/uniphier-pro4-ref.dts b/dts/src/arm/uniphier-pro4-ref.dts
index 4cf539245f..903df6348e 100644
--- a/dts/src/arm/uniphier-pro4-ref.dts
+++ b/dts/src/arm/uniphier-pro4-ref.dts
@@ -8,9 +8,9 @@
*/
/dts-v1/;
-/include/ "uniphier-pro4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-pro4.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier Pro4 Reference Board";
@@ -66,3 +66,7 @@
&usb3 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
diff --git a/dts/src/arm/uniphier-pro4-sanji.dts b/dts/src/arm/uniphier-pro4-sanji.dts
index 2763cebcd7..adef212b45 100644
--- a/dts/src/arm/uniphier-pro4-sanji.dts
+++ b/dts/src/arm/uniphier-pro4-sanji.dts
@@ -8,7 +8,7 @@
*/
/dts-v1/;
-/include/ "uniphier-pro4.dtsi"
+#include "uniphier-pro4.dtsi"
/ {
model = "UniPhier Pro4 Sanji Board";
diff --git a/dts/src/arm/uniphier-pro4.dtsi b/dts/src/arm/uniphier-pro4.dtsi
index 37400becf4..b3dbbd9b6e 100644
--- a/dts/src/arm/uniphier-pro4.dtsi
+++ b/dts/src/arm/uniphier-pro4.dtsi
@@ -268,6 +268,13 @@
};
};
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pro4-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
@@ -305,7 +312,18 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ };
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
diff --git a/dts/src/arm/uniphier-pro5.dtsi b/dts/src/arm/uniphier-pro5.dtsi
index 9577769a0a..b026bcd42a 100644
--- a/dts/src/arm/uniphier-pro5.dtsi
+++ b/dts/src/arm/uniphier-pro5.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/ {
@@ -328,7 +292,7 @@
sdctrl@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
+ reg = <0x59810000 0x400>;
sd_clk: clock {
compatible = "socionext,uniphier-pro5-sd-clock";
@@ -367,6 +331,13 @@
};
};
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pro5-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
@@ -404,7 +375,18 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clocks = <&sys_clk 2>;
+ };
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
diff --git a/dts/src/arm/uniphier-pxs2-gentil.dts b/dts/src/arm/uniphier-pxs2-gentil.dts
index 81560f75bf..7dfae2667f 100644
--- a/dts/src/arm/uniphier-pxs2-gentil.dts
+++ b/dts/src/arm/uniphier-pxs2-gentil.dts
@@ -8,7 +8,7 @@
*/
/dts-v1/;
-/include/ "uniphier-pxs2.dtsi"
+#include "uniphier-pxs2.dtsi"
/ {
model = "UniPhier PXs2 Gentil Board";
diff --git a/dts/src/arm/uniphier-pxs2-vodka.dts b/dts/src/arm/uniphier-pxs2-vodka.dts
index dc2d0579c6..0cf615463a 100644
--- a/dts/src/arm/uniphier-pxs2-vodka.dts
+++ b/dts/src/arm/uniphier-pxs2-vodka.dts
@@ -8,7 +8,7 @@
*/
/dts-v1/;
-/include/ "uniphier-pxs2.dtsi"
+#include "uniphier-pxs2.dtsi"
/ {
model = "UniPhier PXs2 Vodka Board";
diff --git a/dts/src/arm/uniphier-pxs2.dtsi b/dts/src/arm/uniphier-pxs2.dtsi
index bace751d40..90b020c950 100644
--- a/dts/src/arm/uniphier-pxs2.dtsi
+++ b/dts/src/arm/uniphier-pxs2.dtsi
@@ -276,7 +276,7 @@
sdctrl@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
+ reg = <0x59810000 0x400>;
sd_clk: clock {
compatible = "socionext,uniphier-pxs2-sd-clock";
@@ -315,6 +315,13 @@
};
};
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pxs2-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
@@ -352,7 +359,18 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clocks = <&sys_clk 2>;
+ };
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
diff --git a/dts/src/arm/uniphier-sld3-ref.dts b/dts/src/arm/uniphier-sld3-ref.dts
deleted file mode 100644
index 70cda39a3d..0000000000
--- a/dts/src/arm/uniphier-sld3-ref.dts
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Device Tree Source for UniPhier sLD3 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-/dts-v1/;
-/include/ "uniphier-sld3.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier sLD3 Reference Board";
- compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- };
-
- memory@8000000 {
- device_type = "memory";
- reg = <0x80000000 0x20000000
- 0xc0000000 0x20000000>;
- };
-};
-
-&ethsc {
- interrupts = <0 49 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
diff --git a/dts/src/arm/uniphier-sld3.dtsi b/dts/src/arm/uniphier-sld3.dtsi
deleted file mode 100644
index 4082879366..0000000000
--- a/dts/src/arm/uniphier-sld3.dtsi
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Device Tree Source for UniPhier sLD3 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-/ {
- compatible = "socionext,uniphier-sld3";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- };
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- clocks {
- refclk: ref {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24576000>;
- };
-
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- timer@20000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x20000200 0x20>;
- interrupts = <1 11 0x304>;
- clocks = <&arm_timer_clk>;
- };
-
- timer@20000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x20000600 0x20>;
- interrupts = <1 13 0x304>;
- clocks = <&arm_timer_clk>;
- };
-
- intc: interrupt-controller@20001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x20001000 0x1000>,
- <0x20000100 0x100>;
- };
-
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
- <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(512 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- clocks = <&sys_clk 0>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- clocks = <&sys_clk 0>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- clocks = <&sys_clk 0>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- clocks = <&sys_clk 1>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- clocks = <&sys_clk 1>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- clocks = <&sys_clk 1>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- clocks = <&sys_clk 1>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c4: i2c@58600000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58600000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 1>;
- clocks = <&sys_clk 1>;
- clock-frequency = <400000>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- status = "disabled";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- smpctrl@59801000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- mioctrl@59810000 {
- compatible = "socionext,uniphier-sld3-mioctrl",
- "simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
-
- mio_clk: clock {
- compatible = "socionext,uniphier-sld3-mio-clock";
- #clock-cells = <1>;
- };
-
- mio_rst: reset {
- compatible = "socionext,uniphier-sld3-mio-reset";
- #reset-cells = <1>;
- };
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
- <&mio_rst 12>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
- <&mio_rst 13>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
- <&mio_rst 14>;
- };
-
- usb3: usb@5a830100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a830100 0x100>;
- interrupts = <0 83 4>;
- clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
- <&mio_rst 15>;
- };
-
- sysctrl@f1840000 {
- compatible = "socionext,uniphier-sld3-sysctrl",
- "simple-mfd", "syscon";
- reg = <0xf1840000 0x10000>;
-
- sys_clk: clock {
- compatible = "socionext,uniphier-sld3-clock";
- #clock-cells = <1>;
- };
-
- sys_rst: reset {
- compatible = "socionext,uniphier-sld3-reset";
- #reset-cells = <1>;
- };
- };
- };
-};
diff --git a/dts/src/arm/uniphier-sld8-ref.dts b/dts/src/arm/uniphier-sld8-ref.dts
index 4536d5b712..5accd3cc76 100644
--- a/dts/src/arm/uniphier-sld8-ref.dts
+++ b/dts/src/arm/uniphier-sld8-ref.dts
@@ -8,9 +8,9 @@
*/
/dts-v1/;
-/include/ "uniphier-sld8.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-sld8.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier sLD8 Reference Board";
@@ -68,3 +68,7 @@
&usb2 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
diff --git a/dts/src/arm/uniphier-sld8.dtsi b/dts/src/arm/uniphier-sld8.dtsi
index 9fb9167f2d..b083903329 100644
--- a/dts/src/arm/uniphier-sld8.dtsi
+++ b/dts/src/arm/uniphier-sld8.dtsi
@@ -270,6 +270,13 @@
interrupt-controller;
};
+ aidet: aidet@61830000 {
+ compatible = "socionext,uniphier-sld8-aidet";
+ reg = <0x61830000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
sysctrl@61840000 {
compatible = "socionext,uniphier-sld8-sysctrl",
"simple-mfd", "syscon";
@@ -285,7 +292,18 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clocks = <&sys_clk 2>;
+ };
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
diff --git a/dts/src/arm/versatile-pb.dts b/dts/src/arm/versatile-pb.dts
index 06e2331f66..9abe26028c 100644
--- a/dts/src/arm/versatile-pb.dts
+++ b/dts/src/arm/versatile-pb.dts
@@ -39,7 +39,7 @@
clock-names = "apb_pclk";
};
- pci-controller@10001000 {
+ pci@10001000 {
compatible = "arm,versatile-pci";
device_type = "pci";
reg = <0x10001000 0x1000
diff --git a/dts/src/arm/zx296702-ad1.dts b/dts/src/arm/zx296702-ad1.dts
index 081f980cfb..b0183c3a1d 100644
--- a/dts/src/arm/zx296702-ad1.dts
+++ b/dts/src/arm/zx296702-ad1.dts
@@ -18,7 +18,6 @@
};
&mmc0 {
- num-slots = <1>;
supports-highspeed;
non-removable;
disable-wp;
@@ -31,7 +30,6 @@
};
&mmc1 {
- num-slots = <1>;
supports-highspeed;
non-removable;
disable-wp;
diff --git a/dts/src/arm/zynq-7000.dtsi b/dts/src/arm/zynq-7000.dtsi
index f3ac9bfe58..0f79fe1ccd 100644
--- a/dts/src/arm/zynq-7000.dtsi
+++ b/dts/src/arm/zynq-7000.dtsi
@@ -42,6 +42,14 @@
};
};
+ fpga_full: fpga-full {
+ compatible = "fpga-region";
+ fpga-mgr = <&devcfg>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
+
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
diff --git a/dts/src/arm/zynq-parallella.dts b/dts/src/arm/zynq-parallella.dts
index 64a6390fc5..0144acfa97 100644
--- a/dts/src/arm/zynq-parallella.dts
+++ b/dts/src/arm/zynq-parallella.dts
@@ -34,7 +34,7 @@
};
chosen {
- bootargs = "earlycon root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
+ bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
stdout-path = "serial0:115200n8";
};
};
@@ -54,6 +54,7 @@
compatible = "ethernet-phy-id0141.0e90",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
+ device_type = "ethernet-phy";
marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
<0x3 0x11 0xfff0 0xa>;
};
diff --git a/dts/src/arm/zynq-zc702.dts b/dts/src/arm/zynq-zc702.dts
index 0cdad2cc8b..34e8277fce 100644
--- a/dts/src/arm/zynq-zc702.dts
+++ b/dts/src/arm/zynq-zc702.dts
@@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/
/dts-v1/;
-/include/ "zynq-7000.dtsi"
+#include "zynq-7000.dtsi"
/ {
model = "Zynq ZC702 Development Board";
@@ -30,7 +30,7 @@
};
chosen {
- bootargs = "earlycon";
+ bootargs = "";
stdout-path = "serial0:115200n8";
};
@@ -97,6 +97,7 @@
ethernet_phy: ethernet-phy@7 {
reg = <7>;
+ device_type = "ethernet-phy";
};
};
@@ -131,6 +132,21 @@
};
};
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ adv7511: hdmi-tx@39 {
+ compatible = "adi,adv7511";
+ reg = <0x39>;
+ adi,input-depth = <8>;
+ adi,input-colorspace = "yuv422";
+ adi,input-clock = "1x";
+ adi,input-style = <3>;
+ adi,input-justification = "right";
+ };
+ };
+
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/zynq-zc706.dts b/dts/src/arm/zynq-zc706.dts
index ad4bb06dba..7ebc8c5ae3 100644
--- a/dts/src/arm/zynq-zc706.dts
+++ b/dts/src/arm/zynq-zc706.dts
@@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/
/dts-v1/;
-/include/ "zynq-7000.dtsi"
+#include "zynq-7000.dtsi"
/ {
model = "Zynq ZC706 Development Board";
@@ -30,7 +30,7 @@
};
chosen {
- bootargs = "earlycon";
+ bootargs = "";
stdout-path = "serial0:115200n8";
};
@@ -53,6 +53,7 @@
ethernet_phy: ethernet-phy@7 {
reg = <7>;
+ device_type = "ethernet-phy";
};
};
@@ -87,6 +88,21 @@
};
};
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ adv7511: hdmi-tx@39 {
+ compatible = "adi,adv7511";
+ reg = <0x39>;
+ adi,input-depth = <8>;
+ adi,input-colorspace = "yuv422";
+ adi,input-clock = "1x";
+ adi,input-style = <3>;
+ adi,input-justification = "evenly";
+ };
+ };
+
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/zynq-zed.dts b/dts/src/arm/zynq-zed.dts
index 325379f798..5e44dc12fd 100644
--- a/dts/src/arm/zynq-zed.dts
+++ b/dts/src/arm/zynq-zed.dts
@@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/
/dts-v1/;
-/include/ "zynq-7000.dtsi"
+#include "zynq-7000.dtsi"
/ {
model = "Zynq Zed Development Board";
@@ -29,7 +29,7 @@
};
chosen {
- bootargs = "earlycon";
+ bootargs = "";
stdout-path = "serial0:115200n8";
};
@@ -50,6 +50,7 @@
ethernet_phy: ethernet-phy@0 {
reg = <0>;
+ device_type = "ethernet-phy";
};
};
diff --git a/dts/src/arm/zynq-zybo.dts b/dts/src/arm/zynq-zybo.dts
index 590ec24b87..e40cafc5ee 100644
--- a/dts/src/arm/zynq-zybo.dts
+++ b/dts/src/arm/zynq-zybo.dts
@@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/
/dts-v1/;
-/include/ "zynq-7000.dtsi"
+#include "zynq-7000.dtsi"
/ {
model = "Zynq ZYBO Development Board";
@@ -29,7 +29,7 @@
};
chosen {
- bootargs = "earlycon";
+ bootargs = "";
stdout-path = "serial0:115200n8";
};
@@ -51,6 +51,7 @@
ethernet_phy: ethernet-phy@0 {
reg = <0>;
+ device_type = "ethernet-phy";
};
};
diff --git a/dts/src/arm64/allwinner/axp803.dtsi b/dts/src/arm64/allwinner/axp803.dtsi
new file mode 100644
index 0000000000..ff8af52743
--- /dev/null
+++ b/dts/src/arm64/allwinner/axp803.dtsi
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * AXP803 Integrated Power Management Chip
+ * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf
+ */
+
+&axp803 {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ regulators {
+ /* Default work frequency for buck regulators */
+ x-powers,dcdc-freq = <3000>;
+
+ reg_aldo1: aldo1 {
+ regulator-name = "aldo1";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-name = "aldo2";
+ };
+
+ reg_aldo3: aldo3 {
+ regulator-name = "aldo3";
+ };
+
+ reg_dc1sw: dc1sw {
+ regulator-name = "dc1sw";
+ };
+
+ reg_dcdc1: dcdc1 {
+ regulator-name = "dcdc1";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-name = "dcdc2";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-name = "dcdc3";
+ };
+
+ reg_dcdc4: dcdc4 {
+ regulator-name = "dcdc4";
+ };
+
+ reg_dcdc5: dcdc5 {
+ regulator-name = "dcdc5";
+ };
+
+ reg_dcdc6: dcdc6 {
+ regulator-name = "dcdc6";
+ };
+
+ reg_dldo1: dldo1 {
+ regulator-name = "dldo1";
+ };
+
+ reg_dldo2: dldo2 {
+ regulator-name = "dldo2";
+ };
+
+ reg_dldo3: dldo3 {
+ regulator-name = "dldo3";
+ };
+
+ reg_dldo4: dldo4 {
+ regulator-name = "dldo4";
+ };
+
+ reg_eldo1: eldo1 {
+ regulator-name = "eldo1";
+ };
+
+ reg_eldo2: eldo2 {
+ regulator-name = "eldo2";
+ };
+
+ reg_eldo3: eldo3 {
+ regulator-name = "eldo3";
+ };
+
+ reg_fldo1: fldo1 {
+ regulator-name = "fldo1";
+ };
+
+ reg_fldo2: fldo2 {
+ regulator-name = "fldo2";
+ };
+
+ reg_ldo_io0: ldo-io0 {
+ regulator-name = "ldo-io0";
+ status = "disabled";
+ };
+
+ reg_ldo_io1: ldo-io1 {
+ regulator-name = "ldo-io1";
+ status = "disabled";
+ };
+
+ reg_rtc_ldo: rtc-ldo {
+ /* RTC_LDO is a fixed, always-on regulator */
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "rtc-ldo";
+ };
+ };
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts b/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts
index 6872135d7f..d347f52e27 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts
@@ -59,14 +59,16 @@
stdout-path = "serial0:115200n8";
};
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};
+&ehci1 {
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -80,7 +82,7 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <&reg_vcc3v3>;
+ vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
@@ -91,22 +93,143 @@
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
- vmmc-supply = <&reg_vcc3v3>;
+ vmmc-supply = <&reg_dldo2>;
+ vqmmc-supply = <&reg_dldo4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+ interrupt-names = "host-wake";
+ };
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
- vmmc-supply = <&reg_vcc3v3>;
+ vmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
+&ohci1 {
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi-dsi";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@@ -118,3 +241,7 @@
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-nanopi-a64.dts b/dts/src/arm64/allwinner/sun50i-a64-nanopi-a64.dts
new file mode 100644
index 0000000000..2beef9e6cb
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-a64-nanopi-a64.dts
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "FriendlyARM NanoPi A64";
+ compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+/* i2c1 connected with gpio headers like pine64, bananapi */
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "disabled";
+};
+
+&i2c1_pins {
+ bias-pull-up;
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi-dsi";
+};
+
+&reg_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pg-wifi-io";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-olinuxino.dts b/dts/src/arm64/allwinner/sun50i-a64-olinuxino.dts
new file mode 100644
index 0000000000..338e786155
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-a64-olinuxino.dts
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Olimex A64-Olinuxino";
+ compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-pe";
+};
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-ddr3";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-mipi";
+};
+
+&reg_dldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-avdd-csi";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_eldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dvdd-csi";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-pine64.dts b/dts/src/arm64/allwinner/sun50i-a64-pine64.dts
index 7c533b6d4b..caf8b6fbe5 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-pine64.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-pine64.dts
@@ -107,6 +107,118 @@
status = "okay";
};
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
+ * work at 1.35V with less power consumption.
+ * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead.
+ */
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1360000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-mipi";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";
diff --git a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
index d891a1a27f..17ccc12b58 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -95,6 +95,28 @@
status = "okay";
};
+&reg_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+&reg_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-mipi";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi b/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi
index 475518b031..a5da18a6f2 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi
+++ b/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi
@@ -63,3 +63,89 @@
bus-width = <4>;
status = "okay";
};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vdd-1v8-lpddr";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64.dtsi b/dts/src/arm64/allwinner/sun50i-a64.dtsi
index 68aadc9b96..8c8db1b057 100644
--- a/dts/src/arm64/allwinner/sun50i-a64.dtsi
+++ b/dts/src/arm64/allwinner/sun50i-a64.dtsi
@@ -467,6 +467,15 @@
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+ r_intc: interrupt-controller@1f00c00 {
+ compatible = "allwinner,sun50i-a64-r-intc",
+ "allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c00 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
diff --git a/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi b/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi
index dc478d094c..c89010e564 100644
--- a/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi
@@ -121,6 +121,13 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
diff --git a/dts/src/arm64/amlogic/meson-gx.dtsi b/dts/src/arm64/amlogic/meson-gx.dtsi
index 738ed689ff..f175db8462 100644
--- a/dts/src/arm64/amlogic/meson-gx.dtsi
+++ b/dts/src/arm64/amlogic/meson-gx.dtsi
@@ -225,7 +225,7 @@
};
uart_A: serial@84c0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
reg = <0x0 0x84c0 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
@@ -233,7 +233,7 @@
};
uart_B: serial@84dc {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
reg = <0x0 0x84dc 0x0 0x14>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
@@ -279,7 +279,7 @@
};
uart_C: serial@8700 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
reg = <0x0 0x8700 0x0 0x14>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
@@ -367,26 +367,40 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
- clkc_AO: clock-controller@040 {
- compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
- reg = <0x0 0x00040 0x0 0x4>;
- #clock-cells = <1>;
- #reset-cells = <1>;
+ sysctrl_AO: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+ reg = <0x0 0x0 0x0 0x100>;
+
+ clkc_AO: clock-controller {
+ compatible = "amlogic,meson-gx-aoclkc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ };
+
+ cec_AO: cec@100 {
+ compatible = "amlogic,meson-gx-ao-cec";
+ reg = <0x0 0x00100 0x0 0x14>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ sec_AO: ao-secure@140 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x0 0x140 0x0 0x140>;
+ amlogic,has-chip-id;
};
uart_AO: serial@4c0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>;
status = "disabled";
};
uart_AO_B: serial@4e0 {
- compatible = "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
reg = <0x0 0x004e0 0x0 0x14>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>;
status = "disabled";
};
@@ -437,9 +451,9 @@
mailbox: mailbox@404 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0x404 0 0x4c>;
- interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
- <0 209 IRQ_TYPE_EDGE_RISING>,
- <0 210 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
};
};
@@ -448,7 +462,7 @@
compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
reg = <0x0 0xc9410000 0x0 0x10000
0x0 0xc8834540 0x0 0x4>;
- interrupts = <0 8 1>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "macirq";
status = "disabled";
};
diff --git a/dts/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts b/dts/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts
index fa462831cc..9697a7a794 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts
+++ b/dts/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts
@@ -175,6 +175,64 @@
pinctrl-names = "default";
};
+&pinctrl_aobus {
+ gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In",
+ "VCCK En", "CON1 Header Pin31",
+ "I2S Header Pin6", "IR In", "I2S Header Pin7",
+ "I2S Header Pin3", "I2S Header Pin4",
+ "I2S Header Pin5", "HDMI CEC", "SYS LED";
+};
+
+&pinctrl_periphs {
+ gpio-line-names = /* Bank GPIOZ */
+ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
+ "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
+ "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
+ "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
+ "Eth PHY nRESET", "Eth PHY Intc",
+ /* Bank GPIOH */
+ "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL",
+ "CON1 Header Pin33",
+ /* Bank BOOT */
+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
+ "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
+ "eMMC Reset", "eMMC CMD",
+ "", "", "", "", "eMMC DS",
+ "", "",
+ /* Bank CARD */
+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
+ "SDCard D3", "SDCard D2", "SDCard Det",
+ /* Bank GPIODV */
+ "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "",
+ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
+ "VDDEE Regulator", "VCCK Regulator",
+ /* Bank GPIOY */
+ "CON1 Header Pin7", "CON1 Header Pin11",
+ "CON1 Header Pin13", "CON1 Header Pin15",
+ "CON1 Header Pin18", "CON1 Header Pin19",
+ "CON1 Header Pin22", "CON1 Header Pin21",
+ "CON1 Header Pin24", "CON1 Header Pin23",
+ "CON1 Header Pin26", "CON1 Header Pin29",
+ "CON1 Header Pin32", "CON1 Header Pin8",
+ "CON1 Header Pin10", "CON1 Header Pin16",
+ "CON1 Header Pin12",
+ /* Bank GPIOX */
+ "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2",
+ "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
+ "WIFI Power Enable", "WIFI WAKE HOST",
+ "Bluetooth PCM DOUT", "Bluetooth PCM DIN",
+ "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
+ "Bluetooth UART TX", "Bluetooth UART RX",
+ "Bluetooth UART CTS", "Bluetooth UART RTS",
+ "", "", "", "WIFI 32K", "Bluetooth Enable",
+ "Bluetooth WAKE HOST",
+ /* Bank GPIOCLK */
+ "", "CON1 Header Pin35", "", "",
+ /* GPIO_TEST_N */
+ "";
+};
+
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
diff --git a/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts b/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts
index a1078b3e1c..9c59c3c6d1 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts
+++ b/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts
@@ -171,6 +171,13 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rmii_pins>;
diff --git a/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi b/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi
index d904deb101..81ffc689a5 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi
@@ -84,6 +84,9 @@
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
states = <1800000 0
3300000 1>;
+
+ regulator-settling-time-up-us = <10000>;
+ regulator-settling-time-down-us = <150000>;
};
vddio_boot: regulator-vddio_boot {
@@ -148,6 +151,13 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
diff --git a/dts/src/arm64/amlogic/meson-gxbb-wetek-play2.dts b/dts/src/arm64/amlogic/meson-gxbb-wetek-play2.dts
index e76ac313fe..f7144fd5e0 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-wetek-play2.dts
+++ b/dts/src/arm64/amlogic/meson-gxbb-wetek-play2.dts
@@ -108,6 +108,12 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
diff --git a/dts/src/arm64/amlogic/meson-gxbb.dtsi b/dts/src/arm64/amlogic/meson-gxbb.dtsi
index 17d3efdf14..52f1687e7a 100644
--- a/dts/src/arm64/amlogic/meson-gxbb.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxbb.dtsi
@@ -307,6 +307,15 @@
};
};
+&cec_AO {
+ clocks = <&clkc_AO CLKID_AO_CEC_32K>;
+ clock-names = "core";
+};
+
+&clkc_AO {
+ compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
+};
+
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
@@ -682,6 +691,31 @@
clocks = <&clkc CLKID_SPI>;
};
+&uart_A {
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO {
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO_B {
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_B {
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
+&uart_C {
+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905d-p230.dts b/dts/src/arm64/amlogic/meson-gxl-s905d-p230.dts
index 3e0c023d6a..6827f235d7 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905d-p230.dts
+++ b/dts/src/arm64/amlogic/meson-gxl-s905d-p230.dts
@@ -97,6 +97,13 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
/* P230 has exclusive choice between internal or external PHY */
&ethmac {
pinctrl-0 = <&eth_pins>;
@@ -124,7 +131,6 @@
};
};
-
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts
index 94567eb178..edc512ad0b 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -67,6 +67,13 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
@@ -105,6 +112,62 @@
linux,rc-map-name = "rc-geekbox";
};
+&pinctrl_aobus {
+ gpio-line-names = "UART TX",
+ "UART RX",
+ "Power Key In",
+ "J9 Header Pin35",
+ "J9 Header Pin16",
+ "J9 Header Pin15",
+ "J9 Header Pin33",
+ "IR In",
+ "HDMI CEC",
+ "SYS LED";
+};
+
+&pinctrl_periphs {
+ gpio-line-names = /* Bank GPIOZ */
+ "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "",
+ "Power OFF",
+ "VCCK Enable",
+ /* Bank GPIOH */
+ "HDMI HPD", "HDMI SDA", "HDMI SCL",
+ "HDMI_5V_EN", "SPDIF",
+ "J9 Header Pin37",
+ "J9 Header Pin30",
+ "J9 Header Pin29",
+ "J9 Header Pin32",
+ "J9 Header Pin31",
+ /* Bank BOOT */
+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
+ "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
+ "eMMC Clk", "eMMC Reset", "eMMC CMD",
+ "", "BOOT_MODE", "", "", "eMMC Data Strobe",
+ /* Bank CARD */
+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
+ "SDCard D3", "SDCard D2", "SDCard Det",
+ /* Bank GPIODV */
+ "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "",
+ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
+ "VCCK Regulator", "VDDEE Regulator",
+ /* Bank GPIOX */
+ "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2",
+ "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
+ "WIFI Power Enable", "WIFI WAKE HOST",
+ "Bluetooth PCM DOUT", "Bluetooth PCM DIN",
+ "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
+ "Bluetooth UART TX", "Bluetooth UART RX",
+ "Bluetooth UART CTS", "Bluetooth UART RTS",
+ "WIFI 32K", "Bluetooth Enable",
+ "Bluetooth WAKE HOST",
+ /* Bank GPIOCLK */
+ "", "J9 Header Pin39",
+ /* GPIO_TEST_N */
+ "";
+};
+
&pwm_AO_ab {
status = "okay";
pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts
index 266fbcf3e4..69ca14ac10 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -101,6 +101,13 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
@@ -129,6 +136,63 @@
};
};
+&pinctrl_aobus {
+ gpio-line-names = "UART TX",
+ "UART RX",
+ "Blue LED",
+ "SDCard Voltage Switch",
+ "7J1 Header Pin5",
+ "7J1 Header Pin3",
+ "7J1 Header Pin12",
+ "IR In",
+ "9J3 Switch HDMI CEC/7J1 Header Pin11",
+ "7J1 Header Pin13";
+};
+
+&pinctrl_periphs {
+ gpio-line-names = /* Bank GPIOZ */
+ "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "",
+ "Eth Link LED", "Eth Activity LED",
+ /* Bank GPIOH */
+ "HDMI HPD", "HDMI SDA", "HDMI SCL",
+ "HDMI_5V_EN", "9J1 Header Pin2",
+ "Analog Audio Mute",
+ "2J3 Header Pin6",
+ "2J3 Header Pin5",
+ "2J3 Header Pin4",
+ "2J3 Header Pin3",
+ /* Bank BOOT */
+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
+ "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
+ "eMMC Clk", "eMMC Reset", "eMMC CMD",
+ "ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
+ /* Bank CARD */
+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
+ "SDCard D3", "SDCard D2", "SDCard Det",
+ /* Bank GPIODV */
+ "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "",
+ "Green LED", "VCCK Enable",
+ "7J1 Header Pin27", "7J1 Header Pin28",
+ "VCCK Regulator", "VDDEE Regulator",
+ /* Bank GPIOX */
+ "7J1 Header Pin22", "7J1 Header Pin26",
+ "7J1 Header Pin36", "7J1 Header Pin38",
+ "7J1 Header Pin40", "7J1 Header Pin37",
+ "7J1 Header Pin33", "7J1 Header Pin35",
+ "7J1 Header Pin19", "7J1 Header Pin21",
+ "7J1 Header Pin24", "7J1 Header Pin23",
+ "7J1 Header Pin8", "7J1 Header Pin10",
+ "7J1 Header Pin16", "7J1 Header Pin18",
+ "7J1 Header Pin32", "7J1 Header Pin29",
+ "7J1 Header Pin31",
+ /* Bank GPIOCLK */
+ "7J1 Header Pin7", "",
+ /* GPIO_TEST_N */
+ "7J1 Header Pin15";
+};
+
/* SD card */
&sd_emmc_b {
status = "okay";
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts
index 6633a5d8fd..4c2ac7650f 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+++ b/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts
@@ -140,6 +140,13 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dts
index 6ab17c1eee..6e2bf85829 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dts
+++ b/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dts
@@ -71,6 +71,13 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
diff --git a/dts/src/arm64/amlogic/meson-gxl.dtsi b/dts/src/arm64/amlogic/meson-gxl.dtsi
index 8d4f3160a0..d6876e6497 100644
--- a/dts/src/arm64/amlogic/meson-gxl.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxl.dtsi
@@ -43,6 +43,7 @@
#include "meson-gx.dtsi"
#include <dt-bindings/clock/gxbb-clkc.h>
+#include <dt-bindings/clock/gxbb-aoclkc.h>
#include <dt-bindings/gpio/meson-gxl-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
@@ -207,6 +208,15 @@
};
};
+&cec_AO {
+ clocks = <&clkc_AO CLKID_AO_CEC_32K>;
+ clock-names = "core";
+};
+
+&clkc_AO {
+ compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
+};
+
&hdmi_tx {
compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
@@ -623,6 +633,31 @@
clocks = <&clkc CLKID_SPI>;
};
+&uart_A {
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
+&uart_AO {
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO_B {
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_B {
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
+&uart_C {
+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+ clock-names = "xtal", "core", "baud";
+};
+
&vpu {
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
};
diff --git a/dts/src/arm64/amlogic/meson-gxm-nexbox-a1.dts b/dts/src/arm64/amlogic/meson-gxm-nexbox-a1.dts
index 5f626d6830..9b10c5f4f8 100644
--- a/dts/src/arm64/amlogic/meson-gxm-nexbox-a1.dts
+++ b/dts/src/arm64/amlogic/meson-gxm-nexbox-a1.dts
@@ -113,6 +113,13 @@
};
};
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
diff --git a/dts/src/arm64/amlogic/meson-gxm.dtsi b/dts/src/arm64/amlogic/meson-gxm.dtsi
index fe451cce93..19a798d2ae 100644
--- a/dts/src/arm64/amlogic/meson-gxm.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxm.dtsi
@@ -117,6 +117,10 @@
};
};
+&clkc_AO {
+ compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
+};
+
&saradc {
compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
};
diff --git a/dts/src/arm64/apm/apm-shadowcat.dtsi b/dts/src/arm64/apm/apm-shadowcat.dtsi
index 72720e9132..c9ffffb96e 100644
--- a/dts/src/arm64/apm/apm-shadowcat.dtsi
+++ b/dts/src/arm64/apm/apm-shadowcat.dtsi
@@ -626,6 +626,7 @@
0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
@@ -651,6 +652,7 @@
0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
diff --git a/dts/src/arm64/apm/apm-storm.dtsi b/dts/src/arm64/apm/apm-storm.dtsi
index 63be8e51ea..c09a36fed9 100644
--- a/dts/src/arm64/apm/apm-storm.dtsi
+++ b/dts/src/arm64/apm/apm-storm.dtsi
@@ -626,6 +626,7 @@
0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
@@ -651,6 +652,7 @@
0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
@@ -676,6 +678,7 @@
0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
@@ -701,6 +704,7 @@
0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
@@ -726,6 +730,7 @@
0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
diff --git a/dts/src/arm64/arm/foundation-v8.dtsi b/dts/src/arm64/arm/foundation-v8.dtsi
index 7cfa8e414e..8ecdd43319 100644
--- a/dts/src/arm64/arm/foundation-v8.dtsi
+++ b/dts/src/arm64/arm/foundation-v8.dtsi
@@ -226,7 +226,7 @@
clock-names = "uartclk", "apb_pclk";
};
- virtio_block@0130000 {
+ virtio-block@0130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;
diff --git a/dts/src/arm64/arm/juno-base.dtsi b/dts/src/arm64/arm/juno-base.dtsi
index e8b7413ec8..fbafe62d6b 100644
--- a/dts/src/arm64/arm/juno-base.dtsi
+++ b/dts/src/arm64/arm/juno-base.dtsi
@@ -201,7 +201,7 @@
};
};
- cpu_debug0: cpu_debug@22010000 {
+ cpu_debug0: cpu-debug@22010000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x22010000 0x0 0x1000>;
@@ -260,7 +260,7 @@
};
};
- cpu_debug1: cpu_debug@22110000 {
+ cpu_debug1: cpu-debug@22110000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x22110000 0x0 0x1000>;
@@ -283,7 +283,7 @@
};
};
- cpu_debug2: cpu_debug@23010000 {
+ cpu_debug2: cpu-debug@23010000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23010000 0x0 0x1000>;
@@ -356,7 +356,7 @@
};
};
- cpu_debug3: cpu_debug@23110000 {
+ cpu_debug3: cpu-debug@23110000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23110000 0x0 0x1000>;
@@ -379,7 +379,7 @@
};
};
- cpu_debug4: cpu_debug@23210000 {
+ cpu_debug4: cpu-debug@23210000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23210000 0x0 0x1000>;
@@ -402,7 +402,7 @@
};
};
- cpu_debug5: cpu_debug@23310000 {
+ cpu_debug5: cpu-debug@23310000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23310000 0x0 0x1000>;
@@ -426,7 +426,7 @@
};
replicator@20120000 {
- compatible = "qcom,coresight-replicator1x", "arm,primecell";
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0 0x20120000 0 0x1000>;
clocks = <&soc_smc50mhz>;
diff --git a/dts/src/arm64/arm/rtsm_ve-motherboard.dtsi b/dts/src/arm64/arm/rtsm_ve-motherboard.dtsi
index 161ac98418..528875c755 100644
--- a/dts/src/arm64/arm/rtsm_ve-motherboard.dtsi
+++ b/dts/src/arm64/arm/rtsm_ve-motherboard.dtsi
@@ -219,7 +219,7 @@
};
};
- virtio_block@0130000 {
+ virtio-block@0130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;
diff --git a/dts/src/arm64/broadcom/bcm2835-rpi.dtsi b/dts/src/arm64/broadcom/bcm2835-rpi.dtsi
deleted file mode 100644
index e55b362b9d..0000000000
--- a/dts/src/arm64/broadcom/bcm2835-rpi.dtsi
+++ /dev/null
@@ -1,108 +0,0 @@
-#include <dt-bindings/power/raspberrypi-power.h>
-
-/ {
- memory {
- device_type = "memory";
- reg = <0 0x10000000>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- act {
- label = "ACT";
- default-state = "keep";
- linux,default-trigger = "heartbeat";
- };
- };
-
- soc {
- firmware: firmware {
- compatible = "raspberrypi,bcm2835-firmware";
- mboxes = <&mailbox>;
- };
-
- power: power {
- compatible = "raspberrypi,bcm2835-power";
- firmware = <&firmware>;
- #power-domain-cells = <1>;
- };
- };
-};
-
-&gpio {
- pinctrl-names = "default";
-
- gpioout: gpioout {
- brcm,pins = <6>;
- brcm,function = <BCM2835_FSEL_GPIO_OUT>;
- };
-
- alt0: alt0 {
- brcm,pins = <4 5 7 8 9 10 11 14 15>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_gpio0>;
- status = "okay";
- clock-frequency = <100000>;
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_gpio2>;
- status = "okay";
- clock-frequency = <100000>;
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&sdhci {
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio48>;
- bus-width = <4>;
-};
-
-&sdhost {
- pinctrl-names = "default";
- pinctrl-0 = <&sdhost_gpio48>;
- status = "okay";
- bus-width = <4>;
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
- status = "okay";
-};
-
-&usb {
- power-domains = <&power RPI_POWER_DOMAIN_USB>;
-};
-
-&v3d {
- power-domains = <&power RPI_POWER_DOMAIN_V3D>;
-};
-
-&hdmi {
- power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
- status = "okay";
-};
-
-&vec {
- power-domains = <&power RPI_POWER_DOMAIN_VEC>;
- status = "okay";
-};
-
-&dsi0 {
- power-domains = <&power RPI_POWER_DOMAIN_DSI0>;
-};
-
-&dsi1 {
- power-domains = <&power RPI_POWER_DOMAIN_DSI1>;
-};
diff --git a/dts/src/arm64/broadcom/bcm2837-rpi-3-b.dts b/dts/src/arm64/broadcom/bcm2837-rpi-3-b.dts
index 972f14db28..699d340a34 100644
--- a/dts/src/arm64/broadcom/bcm2837-rpi-3-b.dts
+++ b/dts/src/arm64/broadcom/bcm2837-rpi-3-b.dts
@@ -1,41 +1 @@
-/dts-v1/;
-#include "bcm2837.dtsi"
-#include "bcm2835-rpi.dtsi"
-#include "bcm283x-rpi-smsc9514.dtsi"
-#include "bcm283x-rpi-usb-host.dtsi"
-
-/ {
- compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
- model = "Raspberry Pi 3 Model B";
-
- memory {
- reg = <0 0x40000000>;
- };
-
- leds {
- act {
- gpios = <&gpio 47 0>;
- };
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
-/* SDHCI is used to control the SDIO for wireless */
-&sdhci {
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio34>;
- status = "okay";
- bus-width = <4>;
- non-removable;
-};
-
-/* SDHOST is used to drive the SD card */
-&sdhost {
- pinctrl-names = "default";
- pinctrl-0 = <&sdhost_gpio48>;
- status = "okay";
- bus-width = <4>;
-};
+#include "arm/bcm2837-rpi-3-b.dts"
diff --git a/dts/src/arm64/broadcom/bcm283x-rpi-smsc9514.dtsi b/dts/src/arm64/broadcom/bcm283x-rpi-smsc9514.dtsi
deleted file mode 100644
index dc7ae776db..0000000000
--- a/dts/src/arm64/broadcom/bcm283x-rpi-smsc9514.dtsi
+++ /dev/null
@@ -1,19 +0,0 @@
-/ {
- aliases {
- ethernet0 = &ethernet;
- };
-};
-
-&usb {
- usb1@1 {
- compatible = "usb424,9514";
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethernet: usbether@1 {
- compatible = "usb424,ec00";
- reg = <1>;
- };
- };
-};
diff --git a/dts/src/arm64/broadcom/bcm283x-rpi-usb-host.dtsi b/dts/src/arm64/broadcom/bcm283x-rpi-usb-host.dtsi
deleted file mode 100644
index 73f4ece8dc..0000000000
--- a/dts/src/arm64/broadcom/bcm283x-rpi-usb-host.dtsi
+++ /dev/null
@@ -1,3 +0,0 @@
-&usb {
- dr_mode = "host";
-};
diff --git a/dts/src/arm64/broadcom/bcm283x.dtsi b/dts/src/arm64/broadcom/bcm283x.dtsi
deleted file mode 100644
index 431dcfc900..0000000000
--- a/dts/src/arm64/broadcom/bcm283x.dtsi
+++ /dev/null
@@ -1,638 +0,0 @@
-#include <dt-bindings/pinctrl/bcm2835.h>
-#include <dt-bindings/clock/bcm2835.h>
-#include <dt-bindings/clock/bcm2835-aux.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/* firmware-provided startup stubs live here, where the secondary CPUs are
- * spinning.
- */
-/memreserve/ 0x00000000 0x00001000;
-
-/* This include file covers the common peripherals and configuration between
- * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
- * bcm2835.dtsi and bcm2836.dtsi.
- */
-
-/ {
- compatible = "brcm,bcm2835";
- model = "BCM2835";
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen {
- bootargs = "earlyprintk console=ttyAMA0";
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <1000>;
-
- thermal-sensors = <&thermal>;
-
- trips {
- cpu-crit {
- temperature = <80000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
-
- cooling-maps {
- };
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
-
- timer@7e003000 {
- compatible = "brcm,bcm2835-system-timer";
- reg = <0x7e003000 0x1000>;
- interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
- /* This could be a reference to BCM2835_CLOCK_TIMER,
- * but we don't have the driver using the common clock
- * support yet.
- */
- clock-frequency = <1000000>;
- };
-
- dma: dma@7e007000 {
- compatible = "brcm,bcm2835-dma";
- reg = <0x7e007000 0xf00>;
- interrupts = <1 16>,
- <1 17>,
- <1 18>,
- <1 19>,
- <1 20>,
- <1 21>,
- <1 22>,
- <1 23>,
- <1 24>,
- <1 25>,
- <1 26>,
- /* dma channel 11-14 share one irq */
- <1 27>,
- <1 27>,
- <1 27>,
- <1 27>,
- /* unused shared irq for all channels */
- <1 28>;
- interrupt-names = "dma0",
- "dma1",
- "dma2",
- "dma3",
- "dma4",
- "dma5",
- "dma6",
- "dma7",
- "dma8",
- "dma9",
- "dma10",
- "dma11",
- "dma12",
- "dma13",
- "dma14",
- "dma-shared-all";
- #dma-cells = <1>;
- brcm,dma-channel-mask = <0x7f35>;
- };
-
- intc: interrupt-controller@7e00b200 {
- compatible = "brcm,bcm2835-armctrl-ic";
- reg = <0x7e00b200 0x200>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- watchdog@7e100000 {
- compatible = "brcm,bcm2835-pm-wdt";
- reg = <0x7e100000 0x28>;
- };
-
- clocks: cprman@7e101000 {
- compatible = "brcm,bcm2835-cprman";
- #clock-cells = <1>;
- reg = <0x7e101000 0x2000>;
-
- /* CPRMAN derives almost everything from the
- * platform's oscillator. However, the DSI
- * pixel clocks come from the DSI analog PHY.
- */
- clocks = <&clk_osc>,
- <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
- <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
- };
-
- rng@7e104000 {
- compatible = "brcm,bcm2835-rng";
- reg = <0x7e104000 0x10>;
- };
-
- mailbox: mailbox@7e00b880 {
- compatible = "brcm,bcm2835-mbox";
- reg = <0x7e00b880 0x40>;
- interrupts = <0 1>;
- #mbox-cells = <0>;
- };
-
- gpio: gpio@7e200000 {
- compatible = "brcm,bcm2835-gpio";
- reg = <0x7e200000 0xb4>;
- /*
- * The GPIO IP block is designed for 3 banks of GPIOs.
- * Each bank has a GPIO interrupt for itself.
- * There is an overall "any bank" interrupt.
- * In order, these are GIC interrupts 17, 18, 19, 20.
- * Since the BCM2835 only has 2 banks, the 2nd bank
- * interrupt output appears to be mirrored onto the
- * 3rd bank's interrupt signal.
- * So, a bank0 interrupt shows up on 17, 20, and
- * a bank1 interrupt shows up on 18, 19, 20!
- */
- interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
-
- /* Defines pin muxing groups according to
- * BCM2835-ARM-Peripherals.pdf page 102.
- *
- * While each pin can have its mux selected
- * for various functions individually, some
- * groups only make sense to switch to a
- * particular function together.
- */
- dpi_gpio0: dpi_gpio0 {
- brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
- 12 13 14 15 16 17 18 19
- 20 21 22 23 24 25 26 27>;
- brcm,function = <BCM2835_FSEL_ALT2>;
- };
- emmc_gpio22: emmc_gpio22 {
- brcm,pins = <22 23 24 25 26 27>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
- emmc_gpio34: emmc_gpio34 {
- brcm,pins = <34 35 36 37 38 39>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- brcm,pull = <BCM2835_PUD_OFF
- BCM2835_PUD_UP
- BCM2835_PUD_UP
- BCM2835_PUD_UP
- BCM2835_PUD_UP
- BCM2835_PUD_UP>;
- };
- emmc_gpio48: emmc_gpio48 {
- brcm,pins = <48 49 50 51 52 53>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
-
- gpclk0_gpio4: gpclk0_gpio4 {
- brcm,pins = <4>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- gpclk1_gpio5: gpclk1_gpio5 {
- brcm,pins = <5>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- gpclk1_gpio42: gpclk1_gpio42 {
- brcm,pins = <42>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- gpclk1_gpio44: gpclk1_gpio44 {
- brcm,pins = <44>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- gpclk2_gpio6: gpclk2_gpio6 {
- brcm,pins = <6>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- gpclk2_gpio43: gpclk2_gpio43 {
- brcm,pins = <43>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
-
- i2c0_gpio0: i2c0_gpio0 {
- brcm,pins = <0 1>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- i2c0_gpio28: i2c0_gpio28 {
- brcm,pins = <28 29>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- i2c0_gpio44: i2c0_gpio44 {
- brcm,pins = <44 45>;
- brcm,function = <BCM2835_FSEL_ALT1>;
- };
- i2c1_gpio2: i2c1_gpio2 {
- brcm,pins = <2 3>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- i2c1_gpio44: i2c1_gpio44 {
- brcm,pins = <44 45>;
- brcm,function = <BCM2835_FSEL_ALT2>;
- };
- i2c_slave_gpio18: i2c_slave_gpio18 {
- brcm,pins = <18 19 20 21>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
-
- jtag_gpio4: jtag_gpio4 {
- brcm,pins = <4 5 6 12 13>;
- brcm,function = <BCM2835_FSEL_ALT4>;
- };
- jtag_gpio22: jtag_gpio22 {
- brcm,pins = <22 23 24 25 26 27>;
- brcm,function = <BCM2835_FSEL_ALT4>;
- };
-
- pcm_gpio18: pcm_gpio18 {
- brcm,pins = <18 19 20 21>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pcm_gpio28: pcm_gpio28 {
- brcm,pins = <28 29 30 31>;
- brcm,function = <BCM2835_FSEL_ALT2>;
- };
-
- pwm0_gpio12: pwm0_gpio12 {
- brcm,pins = <12>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm0_gpio18: pwm0_gpio18 {
- brcm,pins = <18>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- pwm0_gpio40: pwm0_gpio40 {
- brcm,pins = <40>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio13: pwm1_gpio13 {
- brcm,pins = <13>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio19: pwm1_gpio19 {
- brcm,pins = <19>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- pwm1_gpio41: pwm1_gpio41 {
- brcm,pins = <41>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio45: pwm1_gpio45 {
- brcm,pins = <45>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
-
- sdhost_gpio48: sdhost_gpio48 {
- brcm,pins = <48 49 50 51 52 53>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
-
- spi0_gpio7: spi0_gpio7 {
- brcm,pins = <7 8 9 10 11>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- spi0_gpio35: spi0_gpio35 {
- brcm,pins = <35 36 37 38 39>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- spi1_gpio16: spi1_gpio16 {
- brcm,pins = <16 17 18 19 20 21>;
- brcm,function = <BCM2835_FSEL_ALT4>;
- };
- spi2_gpio40: spi2_gpio40 {
- brcm,pins = <40 41 42 43 44 45>;
- brcm,function = <BCM2835_FSEL_ALT4>;
- };
-
- uart0_gpio14: uart0_gpio14 {
- brcm,pins = <14 15>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- /* Separate from the uart0_gpio14 group
- * because it conflicts with spi1_gpio16, and
- * people often run uart0 on the two pins
- * without flow control.
- */
- uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
- brcm,pins = <16 17>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
- uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
- brcm,pins = <30 31>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
- uart0_gpio32: uart0_gpio32 {
- brcm,pins = <32 33>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
- uart0_gpio36: uart0_gpio36 {
- brcm,pins = <36 37>;
- brcm,function = <BCM2835_FSEL_ALT2>;
- };
- uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
- brcm,pins = <38 39>;
- brcm,function = <BCM2835_FSEL_ALT2>;
- };
-
- uart1_gpio14: uart1_gpio14 {
- brcm,pins = <14 15>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
- brcm,pins = <16 17>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- uart1_gpio32: uart1_gpio32 {
- brcm,pins = <32 33>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
- brcm,pins = <30 31>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- uart1_gpio40: uart1_gpio40 {
- brcm,pins = <40 41>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
- brcm,pins = <42 43>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- };
-
- uart0: serial@7e201000 {
- compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
- reg = <0x7e201000 0x1000>;
- interrupts = <2 25>;
- clocks = <&clocks BCM2835_CLOCK_UART>,
- <&clocks BCM2835_CLOCK_VPU>;
- clock-names = "uartclk", "apb_pclk";
- arm,primecell-periphid = <0x00241011>;
- };
-
- sdhost: mmc@7e202000 {
- compatible = "brcm,bcm2835-sdhost";
- reg = <0x7e202000 0x100>;
- interrupts = <2 24>;
- clocks = <&clocks BCM2835_CLOCK_VPU>;
- dmas = <&dma 13>;
- dma-names = "rx-tx";
- status = "disabled";
- };
-
- i2s: i2s@7e203000 {
- compatible = "brcm,bcm2835-i2s";
- reg = <0x7e203000 0x20>,
- <0x7e101098 0x02>;
-
- dmas = <&dma 2>,
- <&dma 3>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- spi: spi@7e204000 {
- compatible = "brcm,bcm2835-spi";
- reg = <0x7e204000 0x1000>;
- interrupts = <2 22>;
- clocks = <&clocks BCM2835_CLOCK_VPU>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c0: i2c@7e205000 {
- compatible = "brcm,bcm2835-i2c";
- reg = <0x7e205000 0x1000>;
- interrupts = <2 21>;
- clocks = <&clocks BCM2835_CLOCK_VPU>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pixelvalve@7e206000 {
- compatible = "brcm,bcm2835-pixelvalve0";
- reg = <0x7e206000 0x100>;
- interrupts = <2 13>; /* pwa0 */
- };
-
- pixelvalve@7e207000 {
- compatible = "brcm,bcm2835-pixelvalve1";
- reg = <0x7e207000 0x100>;
- interrupts = <2 14>; /* pwa1 */
- };
-
- dsi0: dsi@7e209000 {
- compatible = "brcm,bcm2835-dsi0";
- reg = <0x7e209000 0x78>;
- interrupts = <2 4>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <1>;
-
- clocks = <&clocks BCM2835_PLLA_DSI0>,
- <&clocks BCM2835_CLOCK_DSI0E>,
- <&clocks BCM2835_CLOCK_DSI0P>;
- clock-names = "phy", "escape", "pixel";
-
- clock-output-names = "dsi0_byte",
- "dsi0_ddr2",
- "dsi0_ddr";
-
- };
-
- thermal: thermal@7e212000 {
- compatible = "brcm,bcm2835-thermal";
- reg = <0x7e212000 0x8>;
- clocks = <&clocks BCM2835_CLOCK_TSENS>;
- #thermal-sensor-cells = <0>;
- status = "disabled";
- };
-
- aux: aux@0x7e215000 {
- compatible = "brcm,bcm2835-aux";
- #clock-cells = <1>;
- reg = <0x7e215000 0x8>;
- clocks = <&clocks BCM2835_CLOCK_VPU>;
- };
-
- uart1: serial@7e215040 {
- compatible = "brcm,bcm2835-aux-uart";
- reg = <0x7e215040 0x40>;
- interrupts = <1 29>;
- clocks = <&aux BCM2835_AUX_CLOCK_UART>;
- status = "disabled";
- };
-
- spi1: spi@7e215080 {
- compatible = "brcm,bcm2835-aux-spi";
- reg = <0x7e215080 0x40>;
- interrupts = <1 29>;
- clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@7e2150c0 {
- compatible = "brcm,bcm2835-aux-spi";
- reg = <0x7e2150c0 0x40>;
- interrupts = <1 29>;
- clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm: pwm@7e20c000 {
- compatible = "brcm,bcm2835-pwm";
- reg = <0x7e20c000 0x28>;
- clocks = <&clocks BCM2835_CLOCK_PWM>;
- assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
- assigned-clock-rates = <10000000>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- sdhci: sdhci@7e300000 {
- compatible = "brcm,bcm2835-sdhci";
- reg = <0x7e300000 0x100>;
- interrupts = <2 30>;
- clocks = <&clocks BCM2835_CLOCK_EMMC>;
- status = "disabled";
- };
-
- hvs@7e400000 {
- compatible = "brcm,bcm2835-hvs";
- reg = <0x7e400000 0x6000>;
- interrupts = <2 1>;
- };
-
- dsi1: dsi@7e700000 {
- compatible = "brcm,bcm2835-dsi1";
- reg = <0x7e700000 0x8c>;
- interrupts = <2 12>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <1>;
-
- clocks = <&clocks BCM2835_PLLD_DSI1>,
- <&clocks BCM2835_CLOCK_DSI1E>,
- <&clocks BCM2835_CLOCK_DSI1P>;
- clock-names = "phy", "escape", "pixel";
-
- clock-output-names = "dsi1_byte",
- "dsi1_ddr2",
- "dsi1_ddr";
-
- status = "disabled";
- };
-
- i2c1: i2c@7e804000 {
- compatible = "brcm,bcm2835-i2c";
- reg = <0x7e804000 0x1000>;
- interrupts = <2 21>;
- clocks = <&clocks BCM2835_CLOCK_VPU>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@7e805000 {
- compatible = "brcm,bcm2835-i2c";
- reg = <0x7e805000 0x1000>;
- interrupts = <2 21>;
- clocks = <&clocks BCM2835_CLOCK_VPU>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vec: vec@7e806000 {
- compatible = "brcm,bcm2835-vec";
- reg = <0x7e806000 0x1000>;
- clocks = <&clocks BCM2835_CLOCK_VEC>;
- interrupts = <2 27>;
- status = "disabled";
- };
-
- pixelvalve@7e807000 {
- compatible = "brcm,bcm2835-pixelvalve2";
- reg = <0x7e807000 0x100>;
- interrupts = <2 10>; /* pixelvalve */
- };
-
- hdmi: hdmi@7e902000 {
- compatible = "brcm,bcm2835-hdmi";
- reg = <0x7e902000 0x600>,
- <0x7e808000 0x100>;
- interrupts = <2 8>, <2 9>;
- ddc = <&i2c2>;
- clocks = <&clocks BCM2835_PLLH_PIX>,
- <&clocks BCM2835_CLOCK_HSM>;
- clock-names = "pixel", "hdmi";
- dmas = <&dma 17>;
- dma-names = "audio-rx";
- status = "disabled";
- };
-
- usb: usb@7e980000 {
- compatible = "brcm,bcm2835-usb";
- reg = <0x7e980000 0x10000>;
- interrupts = <1 9>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk_usb>;
- clock-names = "otg";
- phys = <&usbphy>;
- phy-names = "usb2-phy";
- };
-
- v3d: v3d@7ec00000 {
- compatible = "brcm,bcm2835-v3d";
- reg = <0x7ec00000 0x1000>;
- interrupts = <1 10>;
- };
-
- vc4: gpu {
- compatible = "brcm,bcm2835-vc4";
- };
- };
-
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* The oscillator is the root of the clock tree. */
- clk_osc: clock@3 {
- compatible = "fixed-clock";
- reg = <3>;
- #clock-cells = <0>;
- clock-output-names = "osc";
- clock-frequency = <19200000>;
- };
-
- clk_usb: clock@4 {
- compatible = "fixed-clock";
- reg = <4>;
- #clock-cells = <0>;
- clock-output-names = "otg";
- clock-frequency = <480000000>;
- };
- };
-
- usbphy: phy {
- compatible = "usb-nop-xceiv";
- };
-};
diff --git a/dts/src/arm64/broadcom/ns2-clock.dtsi b/dts/src/arm64/broadcom/northstar2/ns2-clock.dtsi
index 99009fdf10..99009fdf10 100644
--- a/dts/src/arm64/broadcom/ns2-clock.dtsi
+++ b/dts/src/arm64/broadcom/northstar2/ns2-clock.dtsi
diff --git a/dts/src/arm64/broadcom/ns2-svk.dts b/dts/src/arm64/broadcom/northstar2/ns2-svk.dts
index ec19fbf928..ec19fbf928 100644
--- a/dts/src/arm64/broadcom/ns2-svk.dts
+++ b/dts/src/arm64/broadcom/northstar2/ns2-svk.dts
diff --git a/dts/src/arm64/broadcom/ns2-xmc.dts b/dts/src/arm64/broadcom/northstar2/ns2-xmc.dts
index ab4ae1a32f..ab4ae1a32f 100644
--- a/dts/src/arm64/broadcom/ns2-xmc.dts
+++ b/dts/src/arm64/broadcom/northstar2/ns2-xmc.dts
diff --git a/dts/src/arm64/broadcom/ns2.dtsi b/dts/src/arm64/broadcom/northstar2/ns2.dtsi
index 35c8457e3d..35c8457e3d 100644
--- a/dts/src/arm64/broadcom/ns2.dtsi
+++ b/dts/src/arm64/broadcom/northstar2/ns2.dtsi
diff --git a/dts/src/arm64/broadcom/stingray/bcm958742-base.dtsi b/dts/src/arm64/broadcom/stingray/bcm958742-base.dtsi
index 5dca7d1025..8862ec907f 100644
--- a/dts/src/arm64/broadcom/stingray/bcm958742-base.dtsi
+++ b/dts/src/arm64/broadcom/stingray/bcm958742-base.dtsi
@@ -72,6 +72,78 @@
<0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
};
+&sata0 {
+ status = "okay";
+};
+
+&sata_phy0{
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata_phy1{
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata_phy2{
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
+&sata_phy3{
+ status = "okay";
+};
+
+&sata4 {
+ status = "okay";
+};
+
+&sata_phy4{
+ status = "okay";
+};
+
+&sata5 {
+ status = "okay";
+};
+
+&sata_phy5{
+ status = "okay";
+};
+
+&sata6 {
+ status = "okay";
+};
+
+&sata_phy6{
+ status = "okay";
+};
+
+&sata7 {
+ status = "okay";
+};
+
+&sata_phy7{
+ status = "okay";
+};
+
+&mdio_mux_iproc {
+ mdio@10 {
+ gphy0: eth-phy@10 {
+ reg = <0x10>;
+ };
+ };
+};
+
&uart1 {
status = "okay";
};
@@ -102,6 +174,12 @@
};
};
+&enet {
+ phy-mode = "rgmii-id";
+ phy-handle = <&gphy0>;
+ status = "okay";
+};
+
&nand {
status = "ok";
nandcs@0 {
diff --git a/dts/src/arm64/broadcom/stingray/bcm958742k.dts b/dts/src/arm64/broadcom/stingray/bcm958742k.dts
index 5671669ba3..eb6f08cdbd 100644
--- a/dts/src/arm64/broadcom/stingray/bcm958742k.dts
+++ b/dts/src/arm64/broadcom/stingray/bcm958742k.dts
@@ -39,6 +39,10 @@
model = "Stingray Combo SVK (BCM958742K)";
};
+&gphy0 {
+ enet-phy-lane-swap;
+};
+
&uart2 {
status = "okay";
};
diff --git a/dts/src/arm64/broadcom/stingray/bcm958742t.dts b/dts/src/arm64/broadcom/stingray/bcm958742t.dts
index 6ebe399fda..5084b03732 100644
--- a/dts/src/arm64/broadcom/stingray/bcm958742t.dts
+++ b/dts/src/arm64/broadcom/stingray/bcm958742t.dts
@@ -38,3 +38,7 @@
compatible = "brcm,bcm958742t", "brcm,stingray";
model = "Stingray SST100 (BCM958742T)";
};
+
+&gphy0 {
+ enet-phy-lane-swap;
+};
diff --git a/dts/src/arm64/broadcom/stingray/stingray-fs4.dtsi b/dts/src/arm64/broadcom/stingray/stingray-fs4.dtsi
new file mode 100644
index 0000000000..8bf1dc6b46
--- /dev/null
+++ b/dts/src/arm64/broadcom/stingray/stingray-fs4.dtsi
@@ -0,0 +1,118 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ fs4: fs4 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x67000000 0x00800000>;
+
+ crypto_mbox: crypto_mbox@00000000 {
+ compatible = "brcm,iproc-flexrm-mbox";
+ reg = <0x00000000 0x200000>;
+ msi-parent = <&gic_its 0x4100>;
+ #mbox-cells = <3>;
+ dma-coherent;
+ };
+
+ raid_mbox: raid_mbox@00400000 {
+ compatible = "brcm,iproc-flexrm-mbox";
+ reg = <0x00400000 0x200000>;
+ dma-coherent;
+ msi-parent = <&gic_its 0x4300>;
+ #mbox-cells = <3>;
+ };
+
+ raid0: raid@0 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 0 0x1 0xff00>,
+ <&raid_mbox 1 0x1 0xff00>,
+ <&raid_mbox 2 0x1 0xff00>,
+ <&raid_mbox 3 0x1 0xff00>;
+ };
+
+ raid1: raid@1 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 4 0x1 0xff00>,
+ <&raid_mbox 5 0x1 0xff00>,
+ <&raid_mbox 6 0x1 0xff00>,
+ <&raid_mbox 7 0x1 0xff00>;
+ };
+
+ raid2: raid@2 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 8 0x1 0xff00>,
+ <&raid_mbox 9 0x1 0xff00>,
+ <&raid_mbox 10 0x1 0xff00>,
+ <&raid_mbox 11 0x1 0xff00>;
+ };
+
+ raid3: raid@3 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 12 0x1 0xff00>,
+ <&raid_mbox 13 0x1 0xff00>,
+ <&raid_mbox 14 0x1 0xff00>,
+ <&raid_mbox 15 0x1 0xff00>;
+ };
+
+ raid4: raid@4 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 16 0x1 0xff00>,
+ <&raid_mbox 17 0x1 0xff00>,
+ <&raid_mbox 18 0x1 0xff00>,
+ <&raid_mbox 19 0x1 0xff00>;
+ };
+
+ raid5: raid@5 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 20 0x1 0xff00>,
+ <&raid_mbox 21 0x1 0xff00>,
+ <&raid_mbox 22 0x1 0xff00>,
+ <&raid_mbox 23 0x1 0xff00>;
+ };
+
+ raid6: raid@6 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 24 0x1 0xff00>,
+ <&raid_mbox 25 0x1 0xff00>,
+ <&raid_mbox 26 0x1 0xff00>,
+ <&raid_mbox 27 0x1 0xff00>;
+ };
+
+ raid7: raid@7 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 28 0x1 0xff00>,
+ <&raid_mbox 29 0x1 0xff00>,
+ <&raid_mbox 30 0x1 0xff00>,
+ <&raid_mbox 31 0x1 0xff00>;
+ };
+ };
diff --git a/dts/src/arm64/broadcom/stingray/stingray-sata.dtsi b/dts/src/arm64/broadcom/stingray/stingray-sata.dtsi
new file mode 100644
index 0000000000..a774709388
--- /dev/null
+++ b/dts/src/arm64/broadcom/stingray/stingray-sata.dtsi
@@ -0,0 +1,278 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ sata {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x67d00000 0x00800000>;
+
+ sata0: ahci@00210000 {
+ compatible = "brcm,iproc-ahci", "generic-ahci";
+ reg = <0x00210000 0x1000>;
+ reg-names = "ahci";
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata0_port0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata0_phy0>;
+ phy-names = "sata-phy";
+ };
+ };
+
+ sata_phy0: sata_phy@00212100 {
+ compatible = "brcm,iproc-sr-sata-phy";
+ reg = <0x00212100 0x1000>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata0_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ sata1: ahci@00310000 {
+ compatible = "brcm,iproc-ahci", "generic-ahci";
+ reg = <0x00310000 0x1000>;
+ reg-names = "ahci";
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata1_port0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata1_phy0>;
+ phy-names = "sata-phy";
+ };
+ };
+
+ sata_phy1: sata_phy@00312100 {
+ compatible = "brcm,iproc-sr-sata-phy";
+ reg = <0x00312100 0x1000>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata1_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ sata2: ahci@00120000 {
+ compatible = "brcm,iproc-ahci", "generic-ahci";
+ reg = <0x00120000 0x1000>;
+ reg-names = "ahci";
+ interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata2_port0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata2_phy0>;
+ phy-names = "sata-phy";
+ };
+ };
+
+ sata_phy2: sata_phy@00122100 {
+ compatible = "brcm,iproc-sr-sata-phy";
+ reg = <0x00122100 0x1000>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata2_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ sata3: ahci@00130000 {
+ compatible = "brcm,iproc-ahci", "generic-ahci";
+ reg = <0x00130000 0x1000>;
+ reg-names = "ahci";
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata3_port0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata3_phy0>;
+ phy-names = "sata-phy";
+ };
+ };
+
+ sata_phy3: sata_phy@00132100 {
+ compatible = "brcm,iproc-sr-sata-phy";
+ reg = <0x00132100 0x1000>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata3_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ sata4: ahci@00330000 {
+ compatible = "brcm,iproc-ahci", "generic-ahci";
+ reg = <0x00330000 0x1000>;
+ reg-names = "ahci";
+ interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata4_port0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata4_phy0>;
+ phy-names = "sata-phy";
+ };
+ };
+
+ sata_phy4: sata_phy@00332100 {
+ compatible = "brcm,iproc-sr-sata-phy";
+ reg = <0x00332100 0x1000>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata4_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ sata5: ahci@00400000 {
+ compatible = "brcm,iproc-ahci", "generic-ahci";
+ reg = <0x00400000 0x1000>;
+ reg-names = "ahci";
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata5_port0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata5_phy0>;
+ phy-names = "sata-phy";
+ };
+ };
+
+ sata_phy5: sata_phy@00402100 {
+ compatible = "brcm,iproc-sr-sata-phy";
+ reg = <0x00402100 0x1000>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata5_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ sata6: ahci@00410000 {
+ compatible = "brcm,iproc-ahci", "generic-ahci";
+ reg = <0x00410000 0x1000>;
+ reg-names = "ahci";
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata6_port0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata6_phy0>;
+ phy-names = "sata-phy";
+ };
+ };
+
+ sata_phy6: sata_phy@00412100 {
+ compatible = "brcm,iproc-sr-sata-phy";
+ reg = <0x00412100 0x1000>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata6_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ sata7: ahci@00420000 {
+ compatible = "brcm,iproc-ahci", "generic-ahci";
+ reg = <0x00420000 0x1000>;
+ reg-names = "ahci";
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata7_port0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata7_phy0>;
+ phy-names = "sata-phy";
+ };
+ };
+
+ sata_phy7: sata_phy@00422100 {
+ compatible = "brcm,iproc-sr-sata-phy";
+ reg = <0x00422100 0x1000>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata7_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+ };
diff --git a/dts/src/arm64/broadcom/stingray/stingray.dtsi b/dts/src/arm64/broadcom/stingray/stingray.dtsi
index 49933cf16c..e6f75c6336 100644
--- a/dts/src/arm64/broadcom/stingray/stingray.dtsi
+++ b/dts/src/arm64/broadcom/stingray/stingray.dtsi
@@ -152,6 +152,12 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x61000000 0x05000000>;
+ ccn: ccn@00000000 {
+ compatible = "arm,ccn-502";
+ reg = <0x00000000 0x900000>;
+ interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
gic: interrupt-controller@02c00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
@@ -261,6 +267,9 @@
};
};
+ #include "stingray-fs4.dtsi"
+ #include "stingray-sata.dtsi"
+
hsls {
compatible = "simple-bus";
#address-cells = <1>;
@@ -269,6 +278,37 @@
#include "stingray-pinctrl.dtsi"
+ mdio_mux_iproc: mdio-mux@0002023c {
+ compatible = "brcm,mdio-mux-iproc";
+ reg = <0x0002023c 0x14>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 { /* PCIe serdes */
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@2 { /* SATA */
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@3 { /* USB */
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@10 { /* RGMII */
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
pwm: pwm@00010000 {
compatible = "brcm,iproc-pwm";
reg = <0x00010000 0x1000>;
@@ -277,6 +317,93 @@
status = "disabled";
};
+ timer0: timer@00030000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00030000 0x1000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer1: timer@00040000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00040000 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ };
+
+ timer2: timer@00050000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00050000 0x1000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer3: timer@00060000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00060000 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer4: timer@00070000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00070000 0x1000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer5: timer@00080000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00080000 0x1000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer6: timer@00090000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x00090000 0x1000>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
+ timer7: timer@000a0000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x000a0000 0x1000>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>,
+ <&hsls_25m_div2_clk>,
+ <&hsls_div4_clk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ status = "disabled";
+ };
+
i2c0: i2c@000b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000b0000 0x100>;
@@ -424,6 +551,15 @@
iommus = <&smmu 0x6000 0x0000>;
};
+ enet: ethernet@00340000{
+ compatible = "brcm,amac";
+ reg = <0x00340000 0x1000>;
+ reg-names = "amac_base";
+ dma-coherent;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+ status= "disabled";
+ };
+
nand: nand@00360000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x00360000 0x600>,
diff --git a/dts/src/arm64/exynos/exynos5433-tm2-common.dtsi b/dts/src/arm64/exynos/exynos5433-tm2-common.dtsi
index e2b0da2c0b..297597442c 100644
--- a/dts/src/arm64/exynos/exynos5433-tm2-common.dtsi
+++ b/dts/src/arm64/exynos/exynos5433-tm2-common.dtsi
@@ -280,9 +280,6 @@
&decon {
status = "okay";
-
- i80-if-timings {
- };
};
&decon_tv {
@@ -310,20 +307,6 @@
samsung,pll-clock-frequency = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&te_irq>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
-
- dsi_out: endpoint {
- samsung,burst-clock-frequency = <512000000>;
- samsung,esc-clock-frequency = <16000000>;
- };
- };
- };
};
&hdmi {
@@ -846,7 +829,6 @@
&mshc_0 {
status = "okay";
- num-slots = <1>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-highspeed;
@@ -868,7 +850,6 @@
&mshc_2 {
status = "okay";
- num-slots = <1>;
cap-sd-highspeed;
disable-wp;
cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
@@ -1116,9 +1097,6 @@
&mic {
status = "okay";
-
- i80-if-timings {
- };
};
&pmu_system_controller {
@@ -1216,8 +1194,9 @@
status = "okay";
};
-&usbdrd_dwc3_0 {
+&usbdrd_dwc3 {
dr_mode = "otg";
+ extcon = <&muic>;
};
&usbdrd30_phy {
diff --git a/dts/src/arm64/exynos/exynos5433.dtsi b/dts/src/arm64/exynos/exynos5433.dtsi
index 727f36abf3..7fe994b750 100644
--- a/dts/src/arm64/exynos/exynos5433.dtsi
+++ b/dts/src/arm64/exynos/exynos5433.dtsi
@@ -1367,7 +1367,7 @@
ranges;
status = "disabled";
- dwc3@15400000 {
+ usbdrd_dwc3: dwc3@15400000 {
compatible = "snps,dwc3";
reg = <0x15400000 0x10000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
@@ -1414,7 +1414,7 @@
ranges;
status = "disabled";
- usbdrd_dwc3_0: dwc3@15a00000 {
+ usbhost_dwc3: dwc3@15a00000 {
compatible = "snps,dwc3";
reg = <0x15a00000 0x10000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/exynos/exynos7-espresso.dts b/dts/src/arm64/exynos/exynos7-espresso.dts
index e5892bb0ae..4a8b1fb512 100644
--- a/dts/src/arm64/exynos/exynos7-espresso.dts
+++ b/dts/src/arm64/exynos/exynos7-espresso.dts
@@ -359,7 +359,6 @@
&mmc_0 {
status = "okay";
- num-slots = <1>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
@@ -375,7 +374,6 @@
&mmc_2 {
status = "okay";
- num-slots = <1>;
cap-sd-highspeed;
card-detect-delay = <200>;
clock-frequency = <400000000>;
diff --git a/dts/src/arm64/freescale/fsl-ls1012a.dtsi b/dts/src/arm64/freescale/fsl-ls1012a.dtsi
index b1554cbd2c..df83915d6e 100644
--- a/dts/src/arm64/freescale/fsl-ls1012a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1012a.dtsi
@@ -444,6 +444,15 @@
<&clockgen 4 3>;
};
+ usb0: usb3@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <0 60 0x4>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ };
+
sata: sata@3200000 {
compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,
@@ -454,5 +463,13 @@
dma-coherent;
status = "disabled";
};
+
+ usb1: usb2@8600000 {
+ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+ reg = <0x0 0x8600000 0x0 0x1000>;
+ interrupts = <0 139 0x4>;
+ dr_mode = "host";
+ phy_type = "ulpi";
+ };
};
};
diff --git a/dts/src/arm64/freescale/fsl-ls1043a.dtsi b/dts/src/arm64/freescale/fsl-ls1043a.dtsi
index 31fd77f82c..d16b9cc1e8 100644
--- a/dts/src/arm64/freescale/fsl-ls1043a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1043a.dtsi
@@ -653,21 +653,21 @@
};
msi1: msi-controller1@1571000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1571000 0x0 0x8>;
msi-controller;
interrupts = <0 116 0x4>;
};
msi2: msi-controller2@1572000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1572000 0x0 0x8>;
msi-controller;
interrupts = <0 126 0x4>;
};
msi3: msi-controller3@1573000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1573000 0x0 0x8>;
msi-controller;
interrupts = <0 160 0x4>;
@@ -689,7 +689,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi1>;
+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
@@ -714,7 +714,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi2>;
+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
@@ -739,7 +739,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi3>;
+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
diff --git a/dts/src/arm64/freescale/fsl-ls1046a.dtsi b/dts/src/arm64/freescale/fsl-ls1046a.dtsi
index dc1640be03..c8ff0baddf 100644
--- a/dts/src/arm64/freescale/fsl-ls1046a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1046a.dtsi
@@ -630,6 +630,37 @@
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
+
+ msi1: msi-controller@1580000 {
+ compatible = "fsl,ls1046a-msi";
+ msi-controller;
+ reg = <0x0 0x1580000 0x0 0x10000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ msi2: msi-controller@1590000 {
+ compatible = "fsl,ls1046a-msi";
+ msi-controller;
+ reg = <0x0 0x1590000 0x0 0x10000>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ msi3: msi-controller@15a0000 {
+ compatible = "fsl,ls1046a-msi";
+ msi-controller;
+ reg = <0x0 0x15a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
};
reserved-memory {
diff --git a/dts/src/arm64/freescale/fsl-ls1088a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1088a-rdb.dts
index 213abb72de..0f6fcda36b 100644
--- a/dts/src/arm64/freescale/fsl-ls1088a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls1088a-rdb.dts
@@ -49,7 +49,7 @@
#include "fsl-ls1088a.dtsi"
/ {
- model = "L1088A RDB Board";
+ model = "LS1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
};
diff --git a/dts/src/arm64/freescale/fsl-ls1088a.dtsi b/dts/src/arm64/freescale/fsl-ls1088a.dtsi
index c144d06a6e..33797b3736 100644
--- a/dts/src/arm64/freescale/fsl-ls1088a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1088a.dtsi
@@ -52,6 +52,10 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ crypto = &crypto;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -62,6 +66,7 @@
compatible = "arm,cortex-a53";
reg = <0x0>;
clocks = <&clockgen 1 0>;
+ cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@@ -70,6 +75,7 @@
compatible = "arm,cortex-a53";
reg = <0x1>;
clocks = <&clockgen 1 0>;
+ cpu-idle-states = <&CPU_PH20>;
};
cpu2: cpu@2 {
@@ -77,6 +83,7 @@
compatible = "arm,cortex-a53";
reg = <0x2>;
clocks = <&clockgen 1 0>;
+ cpu-idle-states = <&CPU_PH20>;
};
cpu3: cpu@3 {
@@ -84,6 +91,7 @@
compatible = "arm,cortex-a53";
reg = <0x3>;
clocks = <&clockgen 1 0>;
+ cpu-idle-states = <&CPU_PH20>;
};
cpu4: cpu@100 {
@@ -91,6 +99,7 @@
compatible = "arm,cortex-a53";
reg = <0x100>;
clocks = <&clockgen 1 1>;
+ cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
@@ -99,6 +108,7 @@
compatible = "arm,cortex-a53";
reg = <0x101>;
clocks = <&clockgen 1 1>;
+ cpu-idle-states = <&CPU_PH20>;
};
cpu6: cpu@102 {
@@ -106,6 +116,7 @@
compatible = "arm,cortex-a53";
reg = <0x102>;
clocks = <&clockgen 1 1>;
+ cpu-idle-states = <&CPU_PH20>;
};
cpu7: cpu@103 {
@@ -113,6 +124,16 @@
compatible = "arm,cortex-a53";
reg = <0x103>;
clocks = <&clockgen 1 1>;
+ cpu-idle-states = <&CPU_PH20>;
+ };
+
+ CPU_PH20: cpu-ph20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PH20";
+ arm,psci-suspend-param = <0x00010000>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <1000>;
+ min-residency-us = <3000>;
};
};
@@ -136,6 +157,11 @@
<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -369,6 +395,45 @@
dma-coherent;
status = "disabled";
};
+
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
};
};
diff --git a/dts/src/arm64/freescale/fsl-ls2080a-qds.dts b/dts/src/arm64/freescale/fsl-ls2080a-qds.dts
index ed209cd572..3c99608b9b 100644
--- a/dts/src/arm64/freescale/fsl-ls2080a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls2080a-qds.dts
@@ -55,11 +55,6 @@
model = "Freescale Layerscape 2080a QDS Board";
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts b/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts
index 67ec3f9c81..a4e7de9f70 100644
--- a/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts
@@ -55,11 +55,6 @@
model = "Freescale Layerscape 2080a RDB Board";
compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- };
-
chosen {
stdout-path = "serial1:115200n8";
};
diff --git a/dts/src/arm64/freescale/fsl-ls2080a-simu.dts b/dts/src/arm64/freescale/fsl-ls2080a-simu.dts
index 3ee718f0aa..fbbb73e571 100644
--- a/dts/src/arm64/freescale/fsl-ls2080a-simu.dts
+++ b/dts/src/arm64/freescale/fsl-ls2080a-simu.dts
@@ -52,11 +52,6 @@
model = "Freescale Layerscape 2080a software Simulator model";
compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- };
-
ethernet@2210000 {
compatible = "smsc,lan91c111";
reg = <0x0 0x2210000 0x0 0x100>;
diff --git a/dts/src/arm64/freescale/fsl-ls2080a.dtsi b/dts/src/arm64/freescale/fsl-ls2080a.dtsi
index d789c6814e..8d739301e7 100644
--- a/dts/src/arm64/freescale/fsl-ls2080a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls2080a.dtsi
@@ -53,6 +53,7 @@
compatible = "arm,cortex-a57";
reg = <0x0>;
clocks = <&clockgen 1 0>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>;
};
@@ -62,6 +63,7 @@
compatible = "arm,cortex-a57";
reg = <0x1>;
clocks = <&clockgen 1 0>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>;
};
@@ -70,6 +72,7 @@
compatible = "arm,cortex-a57";
reg = <0x100>;
clocks = <&clockgen 1 1>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>;
};
@@ -79,6 +82,7 @@
compatible = "arm,cortex-a57";
reg = <0x101>;
clocks = <&clockgen 1 1>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>;
};
@@ -87,6 +91,7 @@
compatible = "arm,cortex-a57";
reg = <0x200>;
clocks = <&clockgen 1 2>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>;
#cooling-cells = <2>;
};
@@ -96,6 +101,7 @@
compatible = "arm,cortex-a57";
reg = <0x201>;
clocks = <&clockgen 1 2>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>;
};
@@ -105,6 +111,7 @@
reg = <0x300>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
+ cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
};
@@ -113,6 +120,7 @@
compatible = "arm,cortex-a57";
reg = <0x301>;
clocks = <&clockgen 1 3>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>;
};
@@ -131,6 +139,15 @@
cluster3_l2: l2-cache3 {
compatible = "cache";
};
+
+ CPU_PW20: cpu-pw20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PW20";
+ arm,psci-suspend-param = <0x00010000>;
+ entry-latency-us = <2000>;
+ exit-latency-us = <2000>;
+ min-residency-us = <6000>;
+ };
};
&pcie1 {
diff --git a/dts/src/arm64/freescale/fsl-ls2088a-qds.dts b/dts/src/arm64/freescale/fsl-ls2088a-qds.dts
index 4a1df5ce32..eaee5b1c3a 100644
--- a/dts/src/arm64/freescale/fsl-ls2088a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls2088a-qds.dts
@@ -54,11 +54,6 @@
model = "Freescale Layerscape 2088A QDS Board";
compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm64/freescale/fsl-ls2088a-rdb.dts b/dts/src/arm64/freescale/fsl-ls2088a-rdb.dts
index a76d4b4deb..c411442cac 100644
--- a/dts/src/arm64/freescale/fsl-ls2088a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls2088a-rdb.dts
@@ -54,11 +54,6 @@
model = "Freescale Layerscape 2088A RDB Board";
compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- };
-
chosen {
stdout-path = "serial1:115200n8";
};
diff --git a/dts/src/arm64/freescale/fsl-ls2088a.dtsi b/dts/src/arm64/freescale/fsl-ls2088a.dtsi
index 5c695c6580..6aa319dae3 100644
--- a/dts/src/arm64/freescale/fsl-ls2088a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls2088a.dtsi
@@ -53,6 +53,7 @@
compatible = "arm,cortex-a72";
reg = <0x0>;
clocks = <&clockgen 1 0>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>;
};
@@ -62,6 +63,7 @@
compatible = "arm,cortex-a72";
reg = <0x1>;
clocks = <&clockgen 1 0>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>;
};
@@ -70,6 +72,7 @@
compatible = "arm,cortex-a72";
reg = <0x100>;
clocks = <&clockgen 1 1>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>;
};
@@ -79,6 +82,7 @@
compatible = "arm,cortex-a72";
reg = <0x101>;
clocks = <&clockgen 1 1>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>;
};
@@ -88,6 +92,7 @@
reg = <0x200>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
+ cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
};
@@ -96,6 +101,7 @@
compatible = "arm,cortex-a72";
reg = <0x201>;
clocks = <&clockgen 1 2>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>;
};
@@ -104,6 +110,7 @@
compatible = "arm,cortex-a72";
reg = <0x300>;
clocks = <&clockgen 1 3>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>;
#cooling-cells = <2>;
};
@@ -113,6 +120,7 @@
compatible = "arm,cortex-a72";
reg = <0x301>;
clocks = <&clockgen 1 3>;
+ cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>;
};
@@ -131,6 +139,15 @@
cluster3_l2: l2-cache3 {
compatible = "cache";
};
+
+ CPU_PW20: cpu-pw20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PW20";
+ arm,psci-suspend-param = <0x00010000>;
+ entry-latency-us = <2000>;
+ exit-latency-us = <2000>;
+ min-residency-us = <6000>;
+ };
};
&pcie1 {
diff --git a/dts/src/arm64/freescale/fsl-ls208xa.dtsi b/dts/src/arm64/freescale/fsl-ls208xa.dtsi
index 94cdd30450..4fb9a0966a 100644
--- a/dts/src/arm64/freescale/fsl-ls208xa.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls208xa.dtsi
@@ -46,6 +46,7 @@
*/
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "fsl,ls2080a";
@@ -53,6 +54,12 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ crypto = &crypto;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
cpu: cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -118,6 +125,11 @@
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -301,6 +313,45 @@
clock-names = "apb_pclk", "wdog_clk";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
diff --git a/dts/src/arm64/hisilicon/hi3660-hikey960.dts b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
index 6609b0fe7a..fd4705c451 100644
--- a/dts/src/arm64/hisilicon/hi3660-hikey960.dts
+++ b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
@@ -39,6 +39,34 @@
reg = <0x0 0x0 0x0 0x0>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ramoops@32000000 {
+ compatible = "ramoops";
+ reg = <0x0 0x32000000 0x0 0x00100000>;
+ record-size = <0x00020000>;
+ console-size = <0x00020000>;
+ ftrace-size = <0x00020000>;
+ };
+ };
+
+ reboot-mode-syscon@32100000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x32100000 0x0 0x00001000>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x0>;
+
+ mode-normal = <0x77665501>;
+ mode-bootloader = <0x77665500>;
+ mode-recovery = <0x77665502>;
+ };
+ };
+
keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -159,6 +187,13 @@
startup-delay-us = <70000>;
enable-active-high;
};
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
};
&i2c0 {
@@ -195,7 +230,7 @@
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
- max-speed = <921600>;
+ max-speed = <3000000>;
};
};
diff --git a/dts/src/arm64/hisilicon/hi3660.dtsi b/dts/src/arm64/hisilicon/hi3660.dtsi
index c6a1961e8d..b7a90d6329 100644
--- a/dts/src/arm64/hisilicon/hi3660.dtsi
+++ b/dts/src/arm64/hisilicon/hi3660.dtsi
@@ -58,6 +58,8 @@
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
};
cpu1: cpu@1 {
@@ -65,6 +67,8 @@
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
};
cpu2: cpu@2 {
@@ -72,6 +76,8 @@
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
};
cpu3: cpu@3 {
@@ -79,6 +85,8 @@
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
};
cpu4: cpu@100 {
@@ -86,6 +94,12 @@
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
+ next-level-cache = <&A73_L2>;
+ cpu-idle-states = <
+ &CPU_NAP
+ &CPU_SLEEP
+ &CLUSTER_SLEEP_1
+ >;
};
cpu5: cpu@101 {
@@ -93,6 +107,12 @@
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
+ next-level-cache = <&A73_L2>;
+ cpu-idle-states = <
+ &CPU_NAP
+ &CPU_SLEEP
+ &CLUSTER_SLEEP_1
+ >;
};
cpu6: cpu@102 {
@@ -100,6 +120,12 @@
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
+ next-level-cache = <&A73_L2>;
+ cpu-idle-states = <
+ &CPU_NAP
+ &CPU_SLEEP
+ &CLUSTER_SLEEP_1
+ >;
};
cpu7: cpu@103 {
@@ -107,6 +133,59 @@
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
+ next-level-cache = <&A73_L2>;
+ cpu-idle-states = <
+ &CPU_NAP
+ &CPU_SLEEP
+ &CLUSTER_SLEEP_1
+ >;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_NAP: cpu-nap {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0000001>;
+ entry-latency-us = <7>;
+ exit-latency-us = <2>;
+ min-residency-us = <15>;
+ };
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <40>;
+ exit-latency-us = <70>;
+ min-residency-us = <3000>;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <500>;
+ exit-latency-us = <5000>;
+ min-residency-us = <20000>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <5000>;
+ min-residency-us = <20000>;
+ };
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ A73_L2: l2-cache1 {
+ compatible = "cache";
};
};
@@ -123,6 +202,26 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>,
+ <&cpu4>,
+ <&cpu5>,
+ <&cpu6>,
+ <&cpu7>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
@@ -337,6 +436,19 @@
status = "disabled";
};
+ dma0: dma@fdf30000 {
+ compatible = "hisilicon,k3-dma-1.0";
+ reg = <0x0 0xfdf30000 0x0 0x1000>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ dma-requests = <32>;
+ dma-min-chan = <1>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
+ dma-no-cci;
+ dma-type = "hi3660_dma";
+ };
+
rtc0: rtc@fff04000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0Xfff04000 0x0 0x1000>;
@@ -810,6 +922,7 @@
clock-names = "ciu", "biu";
clock-frequency = <3200000>;
resets = <&crg_rst 0x94 18>;
+ reset-names = "reset";
cd-gpios = <&gpio25 3 0>;
hisilicon,peripheral-syscon = <&sctrl>;
pinctrl-names = "default";
@@ -839,6 +952,7 @@
<&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
clock-names = "ciu", "biu";
resets = <&crg_rst 0x94 20>;
+ reset-names = "reset";
card-detect-delay = <200>;
supports-highspeed;
keep-power-in-suspend;
@@ -848,5 +962,21 @@
&sdio_cfg_func>;
status = "disabled";
};
+
+ watchdog0: watchdog@e8a06000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xe8a06000 0x0 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_OSC32K>;
+ clock-names = "apb_pclk";
+ };
+
+ watchdog1: watchdog@e8a07000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xe8a07000 0x0 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_OSC32K>;
+ clock-names = "apb_pclk";
+ };
};
};
diff --git a/dts/src/arm64/hisilicon/hi6220.dtsi b/dts/src/arm64/hisilicon/hi6220.dtsi
index eacbe0db5b..02a3aa4b21 100644
--- a/dts/src/arm64/hisilicon/hi6220.dtsi
+++ b/dts/src/arm64/hisilicon/hi6220.dtsi
@@ -262,6 +262,12 @@
#clock-cells = <1>;
};
+ acpu_sctrl: acpu_sctrl@f6504000 {
+ compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
+ reg = <0x0 0xf6504000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
medianoc_ade: medianoc_ade@f4520000 {
compatible = "syscon";
reg = <0x0 0xf4520000 0x0 0x4000>;
@@ -755,7 +761,8 @@
dr_mode = "otg";
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <128>;
- g-tx-fifo-size = <128 128 128 128 128 128>;
+ g-tx-fifo-size = <128 128 128 128 128 128 128 128
+ 16 16 16 16 16 16 16>;
interrupts = <0 77 0x4>;
};
diff --git a/dts/src/arm64/hisilicon/hip07-d05.dts b/dts/src/arm64/hisilicon/hip07-d05.dts
index f5d7f0889b..fe7c16c360 100644
--- a/dts/src/arm64/hisilicon/hip07-d05.dts
+++ b/dts/src/arm64/hisilicon/hip07-d05.dts
@@ -84,3 +84,7 @@
&sas1 {
status = "ok";
};
+
+&p0_pcie2_a {
+ status = "ok";
+};
diff --git a/dts/src/arm64/hisilicon/hip07.dtsi b/dts/src/arm64/hisilicon/hip07.dtsi
index 283d7b532e..2c01a21c36 100644
--- a/dts/src/arm64/hisilicon/hip07.dtsi
+++ b/dts/src/arm64/hisilicon/hip07.dtsi
@@ -1534,5 +1534,27 @@
<637 1>,<638 1>,<639 1>;
status = "disabled";
};
+
+ p0_pcie2_a: pcie@a00a0000 {
+ compatible = "hisilicon,hip07-pcie-ecam";
+ reg = <0 0xaf800000 0 0x800000>,
+ <0 0xa00a0000 0 0x10000>;
+ bus-range = <0xf8 0xff>;
+ msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>;
+ msi-map-mask = <0xffff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000
+ 0x01000000 0 0 0 0xaf7f0000 0 0x10000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
+ 0x0 0 0 2 &mbigen_pcie2_a 671 4
+ 0x0 0 0 3 &mbigen_pcie2_a 671 4
+ 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/src/arm64/marvell/armada-3720-espressobin.dts b/dts/src/arm64/marvell/armada-3720-espressobin.dts
index e3a136ed77..2ce52ba74f 100644
--- a/dts/src/arm64/marvell/armada-3720-espressobin.dts
+++ b/dts/src/arm64/marvell/armada-3720-espressobin.dts
@@ -45,6 +45,7 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
@@ -59,6 +60,20 @@
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
+
+ vcc_sd_reg1: regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vcc_sd1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ enable-active-high;
+ };
};
/* J9 */
@@ -71,6 +86,16 @@
status = "okay";
};
+/* J1 */
+&sdhci1 {
+ wp-inverted;
+ bus-width = <4>;
+ cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
+ marvell,pad-type = "sd";
+ vqmmc-supply = <&vcc_sd_reg1>;
+ status = "okay";
+};
+
/* Exported on the micro USB connector J5 through an FTDI */
&uart0 {
status = "okay";
@@ -81,6 +106,11 @@
status = "okay";
};
+/* J8 */
+&usb2 {
+ status = "okay";
+};
+
&mdio {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
diff --git a/dts/src/arm64/marvell/armada-37xx.dtsi b/dts/src/arm64/marvell/armada-37xx.dtsi
index 51763d6740..8c0cf7efac 100644
--- a/dts/src/arm64/marvell/armada-37xx.dtsi
+++ b/dts/src/arm64/marvell/armada-37xx.dtsi
@@ -81,6 +81,11 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -322,7 +327,11 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1d00000 0x10000>, /* GICD */
- <0x1d40000 0x40000>; /* GICR */
+ <0x1d40000 0x40000>, /* GICR */
+ <0x1d80000 0x2000>, /* GICC */
+ <0x1d90000 0x2000>, /* GICH */
+ <0x1da0000 0x20000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
diff --git a/dts/src/arm64/marvell/armada-7040-db.dts b/dts/src/arm64/marvell/armada-7040-db.dts
index 92c761c380..9c3bdf87e5 100644
--- a/dts/src/arm64/marvell/armada-7040-db.dts
+++ b/dts/src/arm64/marvell/armada-7040-db.dts
@@ -44,6 +44,7 @@
* Device Tree file for Marvell Armada 7040 Development board platform
*/
+#include <dt-bindings/gpio/gpio.h>
#include "armada-7040.dtsi"
/ {
@@ -59,6 +60,34 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3h0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3h1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ cpm_usb3_0_phy: cpm-usb3-0-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cpm_reg_usb3_0_vbus>;
+ };
+
+ cpm_usb3_1_phy: cpm-usb3-1-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cpm_reg_usb3_1_vbus>;
+ };
};
&i2c0 {
@@ -105,6 +134,14 @@
&cpm_i2c0 {
status = "okay";
clock-frequency = <100000>;
+
+ expander0: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
};
&cpm_spi1 {
@@ -140,10 +177,12 @@
};
&cpm_usb3_0 {
+ usb-phy = <&cpm_usb3_0_phy>;
status = "okay";
};
&cpm_usb3_1 {
+ usb-phy = <&cpm_usb3_1_phy>;
status = "okay";
};
diff --git a/dts/src/arm64/marvell/armada-8040-db.dts b/dts/src/arm64/marvell/armada-8040-db.dts
index 1e8f7242ed..0d7b2ae466 100644
--- a/dts/src/arm64/marvell/armada-8040-db.dts
+++ b/dts/src/arm64/marvell/armada-8040-db.dts
@@ -44,6 +44,7 @@
* Device Tree file for Marvell Armada 8040 Development board platform
*/
+#include <dt-bindings/gpio/gpio.h>
#include "armada-8040.dtsi"
/ {
@@ -59,6 +60,48 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "cpm-usb3h0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "cpm-usb3h1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ cpm_usb3_0_phy: cpm-usb3-0-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cpm_reg_usb3_0_vbus>;
+ };
+
+ cpm_usb3_1_phy: cpm-usb3-1-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cpm_reg_usb3_1_vbus>;
+ };
+
+ cps_reg_usb3_0_vbus: cps-usb3-0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "cps-usb3h0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cps_usb3_0_phy: cps-usb3-0-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cps_reg_usb3_0_vbus>;
+ };
};
&i2c0 {
@@ -107,6 +150,25 @@
&cpm_i2c0 {
status = "okay";
clock-frequency = <100000>;
+
+ /* U31 */
+ expander0: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+
+ /* U25 */
+ expander1: pca9555@25 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x25>;
+ };
+
};
/* CON4 on CP0 expansion */
@@ -116,11 +178,13 @@
/* CON9 on CP0 expansion */
&cpm_usb3_0 {
+ usb-phy = <&cpm_usb3_0_phy>;
status = "okay";
};
/* CON10 on CP0 expansion */
&cpm_usb3_1 {
+ usb-phy = <&cpm_usb3_1_phy>;
status = "okay";
};
@@ -159,6 +223,7 @@
/* CON9 on CP1 expansion */
&cps_usb3_0 {
+ usb-phy = <&cps_usb3_0_phy>;
status = "okay";
};
diff --git a/dts/src/arm64/marvell/armada-8040-mcbin.dts b/dts/src/arm64/marvell/armada-8040-mcbin.dts
index 4968e731de..acf5c7d16d 100644
--- a/dts/src/arm64/marvell/armada-8040-mcbin.dts
+++ b/dts/src/arm64/marvell/armada-8040-mcbin.dts
@@ -46,11 +46,17 @@
#include "armada-8040.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Marvell 8040 MACHIATOBin";
compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
@@ -77,11 +83,13 @@
v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_xhci_vbus_pins>;
regulator-name = "v_5v0_usb3_hst_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- /* actually GPIO controlled, but 8k has no GPIO support yet */
- regulator-always-on;
status = "okay";
};
@@ -112,10 +120,44 @@
&cpm_i2c0 {
clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_i2c0_pins>;
status = "okay";
};
+&cpm_i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_i2c1_pins>;
+ status = "okay";
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ sfpp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ sfp_1g_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ };
+};
+
&cpm_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_ge_mdio_pins>;
status = "okay";
ge_phy: ethernet-phy@0 {
@@ -123,6 +165,67 @@
};
};
+&cpm_pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_pcie_pins>;
+ num-lanes = <4>;
+ num-viewport = <8>;
+ reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&cpm_pinctrl {
+ cpm_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp32", "mpp34";
+ marvell,function = "ge";
+ };
+ cpm_i2c1_pins: i2c1-pins {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cpm_i2c0_pins: i2c0-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cpm_xhci_vbus_pins: xhci0-vbus-pins {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ cpm_pcie_pins: pcie-pins {
+ marvell,pins = "mpp52";
+ marvell,function = "gpio";
+ };
+ cpm_sdhci_pins: sdhci-pins {
+ marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
+ "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+};
+
+&cpm_xmdio {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+
+ phy8: ethernet-phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ };
+};
+
+&cpm_ethernet {
+ status = "okay";
+};
+
+&cpm_eth0 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "10gbase-kr";
+};
+
&cpm_sata0 {
/* CPM Lane 0 - U29 */
status = "okay";
@@ -132,6 +235,8 @@
/* U6 */
broken-cd;
bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sdhci_pins>;
status = "okay";
vqmmc-supply = <&v_3_3>;
};
@@ -150,6 +255,12 @@
status = "okay";
};
+&cps_eth0 {
+ status = "okay";
+ phy = <&phy8>;
+ phy-mode = "10gbase-kr";
+};
+
&cps_eth1 {
/* CPS Lane 0 - J5 (Gigabit RJ45) */
status = "okay";
@@ -157,6 +268,13 @@
phy-mode = "sgmii";
};
+&cps_pinctrl {
+ cps_spi1_pins: spi1-pins {
+ marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+};
+
&cps_sata0 {
/* CPS Lane 1 - U32 */
/* CPS Lane 3 - U31 */
@@ -164,6 +282,8 @@
};
&cps_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cps_spi1_pins>;
status = "okay";
spi-flash@0 {
diff --git a/dts/src/arm64/marvell/armada-8080-db.dts b/dts/src/arm64/marvell/armada-8080-db.dts
new file mode 100644
index 0000000000..707af83383
--- /dev/null
+++ b/dts/src/arm64/marvell/armada-8080-db.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada-8080 Development board platform
+ */
+
+#include "armada-8080.dtsi"
+
+/ {
+ model = "Marvell 8080 board";
+ compatible = "marvell,armada-8080-db", "marvell,armada-8080",
+ "marvell,armada-ap810-octa", "marvell,armada-ap810";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&uart0_ap0 {
+ clock-frequency = <384000>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/marvell/armada-8080.dtsi b/dts/src/arm64/marvell/armada-8080.dtsi
new file mode 100644
index 0000000000..d5535b7167
--- /dev/null
+++ b/dts/src/arm64/marvell/armada-8080.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada-8080 SoC, made of an AP810 OCTA.
+ */
+
+#include "armada-ap810-ap0-octa-core.dtsi"
+
+/ {
+ model = "Marvell 8080 board";
+ compatible = "marvell,armada-8080", "marvell,armada-ap810-octa",
+ "marvell,armada-ap810";
+};
diff --git a/dts/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi b/dts/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi
new file mode 100644
index 0000000000..bf1b22b703
--- /dev/null
+++ b/dts/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP810 OCTA cores.
+ */
+
+#include "armada-ap810-ap0.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,armada-ap810-octa";
+
+ cpu@000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+ cpu@001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x201>;
+ enable-method = "psci";
+ };
+ cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x300>;
+ enable-method = "psci";
+ };
+ cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x301>;
+ enable-method = "psci";
+ };
+ };
+};
diff --git a/dts/src/arm64/marvell/armada-ap810-ap0.dtsi b/dts/src/arm64/marvell/armada-ap810-ap0.dtsi
new file mode 100644
index 0000000000..7e6f039f0f
--- /dev/null
+++ b/dts/src/arm64/marvell/armada-ap810-ap0.dtsi
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP810.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ model = "Marvell Armada AP810";
+ compatible = "marvell,armada-ap810";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0_ap0;
+ serial1 = &uart1_ap0;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ ap810-ap0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space@e8000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0xe8000000 0x4000000>;
+ interrupt-parent = <&gic>;
+
+ gic: interrupt-controller@3000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+
+ reg = <0x3000000 0x10000>, /* GICD */
+ <0x3060000 0x100000>, /* GICR */
+ <0x00c0000 0x2000>, /* GICC */
+ <0x00d0000 0x1000>, /* GICH */
+ <0x00e0000 0x2000>; /* GICV */
+
+ gic_its_ap0: interrupt-controller@3040000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x3040000 0x20000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ xor@400000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x400000 0x1000>,
+ <0x410000 0x1000>;
+ msi-parent = <&gic_its_ap0 0xa0>;
+ dma-coherent;
+ };
+
+ xor@420000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x420000 0x1000>,
+ <0x430000 0x1000>;
+ msi-parent = <&gic_its_ap0 0xa1>;
+ dma-coherent;
+ };
+
+ xor@440000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x440000 0x1000>,
+ <0x450000 0x1000>;
+ msi-parent = <&gic_its_ap0 0xa2>;
+ dma-coherent;
+ };
+
+ xor@460000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x460000 0x1000>,
+ <0x470000 0x1000>;
+ msi-parent = <&gic_its_ap0 0xa3>;
+ dma-coherent;
+ };
+
+ uart0_ap0: serial@512000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512000 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ status = "disabled";
+ };
+
+ uart1_ap0: serial@512100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512100 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/src/arm64/marvell/armada-cp110-master.dtsi b/dts/src/arm64/marvell/armada-cp110-master.dtsi
index 4c68605675..8263a8a504 100644
--- a/dts/src/arm64/marvell/armada-cp110-master.dtsi
+++ b/dts/src/arm64/marvell/armada-cp110-master.dtsi
@@ -65,25 +65,44 @@
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
+ marvell,system-controller = <&cpm_syscon0>;
status = "disabled";
dma-coherent;
cpm_eth0: eth0 {
- interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cpm_eth1: eth1 {
- interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cpm_eth2: eth2 {
- interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
@@ -115,6 +134,13 @@
msi-parent = <&gicp>;
};
+ cpm_rtc: rtc@284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
cpm_syscon0: system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
@@ -131,8 +157,12 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 0 32>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
-
};
cpm_gpio2: gpio@140 {
@@ -142,26 +172,15 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 32 31>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
- cpm_rtc: rtc@284000 {
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cpm_sata0: sata@540000 {
- compatible = "marvell,armada-8k-ahci",
- "generic-ahci";
- reg = <0x540000 0x30000>;
- interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_clk 1 15>;
- status = "disabled";
- };
-
cpm_usb3_0: usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
@@ -182,6 +201,15 @@
status = "disabled";
};
+ cpm_sata0: sata@540000 {
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
+ reg = <0x540000 0x30000>;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_clk 1 15>;
+ status = "disabled";
+ };
+
cpm_xor0: xor@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>,
@@ -240,6 +268,21 @@
status = "disabled";
};
+ cpm_nand: nand@720000 {
+ /*
+ * Due to the limiation of the pin available
+ * this controller is only usable on the CPM
+ * for A7K and on the CPS for A8K.
+ */
+ compatible = "marvell,armada370-nand";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_clk 1 2>;
+ status = "disabled";
+ };
+
cpm_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
diff --git a/dts/src/arm64/marvell/armada-cp110-slave.dtsi b/dts/src/arm64/marvell/armada-cp110-slave.dtsi
index 923f354b02..b71ee6c836 100644
--- a/dts/src/arm64/marvell/armada-cp110-slave.dtsi
+++ b/dts/src/arm64/marvell/armada-cp110-slave.dtsi
@@ -60,37 +60,49 @@
compatible = "simple-bus";
ranges = <0x0 0x0 0xf4000000 0x2000000>;
- cps_rtc: rtc@284000 {
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
cps_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
+ marvell,system-controller = <&cps_syscon0>;
status = "disabled";
dma-coherent;
cps_eth0: eth0 {
- interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cps_eth1: eth1 {
- interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cps_eth2: eth2 {
- interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
@@ -122,6 +134,13 @@
msi-parent = <&gicp>;
};
+ cps_rtc: rtc@284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
cps_syscon0: system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
@@ -138,8 +157,12 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cps_pinctrl 0 0 32>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
-
};
cps_gpio2: gpio@140 {
@@ -149,20 +172,16 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cps_pinctrl 0 32 31>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
- cps_sata0: sata@540000 {
- compatible = "marvell,armada-8k-ahci",
- "generic-ahci";
- reg = <0x540000 0x30000>;
- interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_clk 1 15>;
- status = "disabled";
- };
-
cps_usb3_0: usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
@@ -183,6 +202,15 @@
status = "disabled";
};
+ cps_sata0: sata@540000 {
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
+ reg = <0x540000 0x30000>;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_clk 1 15>;
+ status = "disabled";
+ };
+
cps_xor0: xor@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>,
@@ -241,6 +269,21 @@
status = "disabled";
};
+ cps_nand: nand@720000 {
+ /*
+ * Due to the limiation of the pin available
+ * this controller is only usable on the CPM
+ * for A7K and on the CPS for A8K.
+ */
+ compatible = "marvell,armada370-nand";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_clk 1 2>;
+ status = "disabled";
+ };
+
cps_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
diff --git a/dts/src/arm64/mediatek/mt2712-evb.dts b/dts/src/arm64/mediatek/mt2712-evb.dts
new file mode 100644
index 0000000000..8c804df3da
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.shen@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+ model = "MediaTek MT2712 evaluation board";
+ compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
diff --git a/dts/src/arm64/mediatek/mt2712e.dtsi b/dts/src/arm64/mediatek/mt2712e.dtsi
new file mode 100644
index 0000000000..57d0396b7f
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt2712e.dtsi
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.shen@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt2712";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ baud_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ #clock-cells = <0>;
+ };
+
+ sys_clk: dummyclk {
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ uart5: serial@1000f000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x1000f000 0 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&baud_clk>, <&sys_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ sysirq: interrupt-controller@10220a80 {
+ compatible = "mediatek,mt2712-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10220a80 0 0x40>;
+ };
+
+ gic: interrupt-controller@10510000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x10510000 0 0x10000>,
+ <0 0x10520000 0 0x20000>,
+ <0 0x10540000 0 0x20000>,
+ <0 0x10560000 0 0x20000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&baud_clk>, <&sys_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&baud_clk>, <&sys_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&baud_clk>, <&sys_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11005000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&baud_clk>, <&sys_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart4: serial@11019000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11019000 0 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&baud_clk>, <&sys_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+};
+
diff --git a/dts/src/arm64/mediatek/mt6797.dtsi b/dts/src/arm64/mediatek/mt6797.dtsi
index 31088a9f71..4beaa71107 100644
--- a/dts/src/arm64/mediatek/mt6797.dtsi
+++ b/dts/src/arm64/mediatek/mt6797.dtsi
@@ -108,13 +108,6 @@
clock-output-names = "clk26m";
};
- clk32k: oscillator@1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32000>;
- clock-output-names = "clk32k";
- };
-
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
@@ -147,6 +140,11 @@
infracfg = <&infrasys>;
};
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
apmixedsys: apmixed@1000c000 {
compatible = "mediatek,mt6797-apmixedsys";
reg = <0 0x1000c000 0 0x1000>;
diff --git a/dts/src/arm64/mediatek/mt7622-rfb1.dts b/dts/src/arm64/mediatek/mt7622-rfb1.dts
new file mode 100644
index 0000000000..c08309df2c
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt7622-rfb1.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ming Huang <ming.huang@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+
+/ {
+ model = "MediaTek MT7622 RFB1 board";
+ compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+
+ chosen {
+ bootargs = "console=ttyS0,115200n1";
+ };
+
+ memory {
+ reg = <0 0x40000000 0 0x3F000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/mediatek/mt7622.dtsi b/dts/src/arm64/mediatek/mt7622.dtsi
new file mode 100644
index 0000000000..b111fec2ed
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt7622.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ming Huang <ming.huang@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt7622";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clock-frequency = <1300000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ clock-frequency = <1300000000>;
+ };
+ };
+
+ uart_clk: dummy25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ bus_clk: dummy280m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <280000000>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
+ no-map;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ sysirq: interrupt-controller@10200620 {
+ compatible = "mediatek,mt7622-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200620 0 0x20>;
+ };
+
+ gic: interrupt-controller@10300000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10310000 0 0x1000>,
+ <0 0x10320000 0 0x1000>,
+ <0 0x10340000 0 0x2000>,
+ <0 0x10360000 0 0x2000>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>, <&bus_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+};
diff --git a/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi b/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi
index d946408121..790b7775b9 100644
--- a/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi
+++ b/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -17,6 +17,7 @@
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
input-disable;
+ output-high;
};
};
diff --git a/dts/src/arm64/qcom/apq8016-sbc.dtsi b/dts/src/arm64/qcom/apq8016-sbc.dtsi
index bd310ac196..1d63e6b879 100644
--- a/dts/src/arm64/qcom/apq8016-sbc.dtsi
+++ b/dts/src/arm64/qcom/apq8016-sbc.dtsi
@@ -88,6 +88,8 @@
interrupts = <31 2>;
adi,dsi-lanes = <4>;
+ clocks = <&rpmcc RPM_SMD_BB_CLK2>;
+ clock-names = "cec";
pd-gpios = <&msmgpio 32 0>;
@@ -213,11 +215,14 @@
};
usb@78d9000 {
- extcon = <&usb_id>, <&usb_id>;
+ extcon = <&usb_id>;
status = "okay";
adp-disable;
hnp-disable;
srp-disable;
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_sw_sel_pm>;
ulpi {
phy {
v1p8-supply = <&pm8916_l7>;
@@ -337,19 +342,11 @@
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
- id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
+ vbus-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};
- usb-switch {
- compatible = "toshiba,tc7usb40mu";
- switch-gpios = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>;
- extcon = <&usb_id>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb_sw_sel_pm>;
- };
-
hdmi-out {
compatible = "hdmi-connector";
type = "a";
diff --git a/dts/src/arm64/qcom/apq8096-db820c-pmic-pins.dtsi b/dts/src/arm64/qcom/apq8096-db820c-pmic-pins.dtsi
index b1142c45fd..8e37978259 100644
--- a/dts/src/arm64/qcom/apq8096-db820c-pmic-pins.dtsi
+++ b/dts/src/arm64/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -24,4 +24,28 @@
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
+
+ usb3_vbus_det_gpio: pm8996_gpio22 {
+ pinconf {
+ pins = "gpio22";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-enable;
+ bias-pull-down;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ };
+ };
+};
+
+&pmi8994_gpios {
+ usb2_vbus_det_gpio: pmi8996_gpio6 {
+ pinconf {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-enable;
+ bias-pull-down;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ };
+ };
};
diff --git a/dts/src/arm64/qcom/apq8096-db820c.dtsi b/dts/src/arm64/qcom/apq8096-db820c.dtsi
index d2196fc6d7..789f3e8732 100644
--- a/dts/src/arm64/qcom/apq8096-db820c.dtsi
+++ b/dts/src/arm64/qcom/apq8096-db820c.dtsi
@@ -13,6 +13,7 @@
#include "msm8996.dtsi"
#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
#include "apq8096-db820c-pins.dtsi"
#include "apq8096-db820c-pmic-pins.dtsi"
#include <dt-bindings/input/input.h>
@@ -88,6 +89,55 @@
cd-gpios = <&msmgpio 38 0x1>;
status = "okay";
};
+
+ phy@34000 {
+ status = "okay";
+ };
+
+ phy@7410000 {
+ status = "okay";
+ };
+
+ phy@7411000 {
+ status = "okay";
+ };
+
+ phy@7412000 {
+ status = "okay";
+ };
+
+ usb@6a00000 {
+ status = "okay";
+
+ dwc3@6a00000 {
+ extcon = <&usb3_id>;
+ dr_mode = "otg";
+ };
+ };
+
+ usb3_id: usb3-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_vbus_det_gpio>;
+ };
+
+ usb@7600000 {
+ status = "okay";
+
+ dwc3@7600000 {
+ extcon = <&usb2_id>;
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ };
+ };
+
+ usb2_id: usb2-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_det_gpio>;
+ };
};
@@ -106,4 +156,152 @@
gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
};
};
+
+ rpm-glink {
+ rpm_requests {
+ pm8994-regulators {
+ vdd_l1-supply = <&pm8994_s3>;
+ vdd_l2_l26_l28-supply = <&pm8994_s3>;
+ vdd_l3_l11-supply = <&pm8994_s3>;
+ vdd_l4_l27_l31-supply = <&pm8994_s3>;
+ vdd_l5_l7-supply = <&pm8994_s5>;
+ vdd_l14_l15-supply = <&pm8994_s5>;
+ vdd_l20_l21-supply = <&pm8994_s5>;
+ vdd_l25-supply = <&pm8994_s3>;
+
+ s3 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ s5 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+ s7 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ l1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ l2 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ };
+ l3 {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ };
+ l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ l6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ l11 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+ l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+ l17 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+ l18 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+ l19 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+ l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ l22 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ l23 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+ l25 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-allow-set-load;
+ };
+ l27 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ l28 {
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ regulator-allow-set-load;
+ };
+ l29 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ l30 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ l32 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+ };
};
diff --git a/dts/src/arm64/qcom/ipq8074-hk01.dts b/dts/src/arm64/qcom/ipq8074-hk01.dts
new file mode 100644
index 0000000000..6a838b5d32
--- /dev/null
+++ b/dts/src/arm64/qcom/ipq8074-hk01.dts
@@ -0,0 +1,52 @@
+/dts-v1/;
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "ipq8074.dtsi"
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
+ compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ };
+
+ soc {
+ pinctrl@1000000 {
+ serial_4_pins: serial4_pinmux {
+ mux {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ bias-disable;
+ };
+ };
+ };
+
+ serial@78b3000 {
+ pinctrl-0 = <&serial_4_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
diff --git a/dts/src/arm64/qcom/ipq8074.dtsi b/dts/src/arm64/qcom/ipq8074.dtsi
new file mode 100644
index 0000000000..2bc5dec561
--- /dev/null
+++ b/dts/src/arm64/qcom/ipq8074.dtsi
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8074";
+ compatible = "qcom,ipq8074";
+
+ soc: soc {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ pinctrl@1000000 {
+ compatible = "qcom,ipq8074-pinctrl";
+ reg = <0x1000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <0x3>;
+ reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ timer@b120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xb120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@b120000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb121000 0x1000>,
+ <0xb122000 0x1000>;
+ };
+
+ frame@b123000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ gcc: gcc@1800000 {
+ compatible = "qcom,gcc-ipq8074";
+ reg = <0x1800000 0x80000>;
+ #clock-cells = <0x1>;
+ #reset-cells = <0x1>;
+ };
+
+ blsp1_uart5: serial@78b3000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b3000 0x200>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
+ cpus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <0x2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
+ };
+
+ clocks {
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
+ xo: xo {
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ #clock-cells = <0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/qcom/msm8916.dtsi b/dts/src/arm64/qcom/msm8916.dtsi
index 039991f808..dc3817593e 100644
--- a/dts/src/arm64/qcom/msm8916.dtsi
+++ b/dts/src/arm64/qcom/msm8916.dtsi
@@ -88,6 +88,11 @@
no-map;
};
+ venus_mem: venus@89900000 {
+ reg = <0x0 0x89900000 0x0 0x600000>;
+ no-map;
+ };
+
mba_mem: mba@8ea00000 {
no-map;
reg = <0 0x8ea00000 0 0x100000>;
@@ -204,6 +209,17 @@
};
+ gpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -694,6 +710,84 @@
#thermal-sensor-cells = <1>;
};
+ apps_iommu: iommu@1ef0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1e20000 0x40000>;
+ reg = <0x1ef0000 0x3000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_CLK>;
+ clock-names = "iface", "bus";
+ qcom,iommu-secure-id = <17>;
+
+ // mdp_0:
+ iommu-ctx@4000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x4000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ // venus_ns:
+ iommu-ctx@5000 {
+ compatible = "qcom,msm-iommu-v1-sec";
+ reg = <0x5000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpu_iommu: iommu@1f08000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1f08000 0x10000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_GFX_TCU_CLK>;
+ clock-names = "iface", "bus";
+ qcom,iommu-secure-id = <18>;
+
+ // gfx3d_user:
+ iommu-ctx@1000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ // gfx3d_priv:
+ iommu-ctx@2000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 242 0>;
+ };
+ };
+
+ gpu@1c00000 {
+ compatible = "qcom,adreno-306.0", "qcom,adreno";
+ reg = <0x01c00000 0x20000>;
+ reg-names = "kgsl_3d0_reg_memory";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ clock-names =
+ "core",
+ "iface",
+ "mem",
+ "mem_iface",
+ "alt_mem_iface",
+ "gfx3d";
+ clocks =
+ <&gcc GCC_OXILI_GFX3D_CLK>,
+ <&gcc GCC_OXILI_AHB_CLK>,
+ <&gcc GCC_OXILI_GMEM_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_BIMC_GPU_CLK>,
+ <&gcc GFX3D_CLK_SRC>;
+ power-domains = <&gcc OXILI_GDSC>;
+ operating-points-v2 = <&gpu_opp_table>;
+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+ };
+
mdss: mdss@1a00000 {
compatible = "qcom,mdss";
reg = <0x1a00000 0x1000>,
@@ -735,6 +829,8 @@
"core_clk",
"vsync_clk";
+ iommus = <&apps_iommu 4>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -990,7 +1086,7 @@
};
replicator@824000 {
- compatible = "qcom,coresight-replicator1x", "arm,primecell";
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x824000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
@@ -1207,6 +1303,28 @@
};
};
};
+
+ venus: video-codec@1d00000 {
+ compatible = "qcom,msm8916-venus";
+ reg = <0x01d00000 0xff000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&gcc VENUS_GDSC>;
+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
+ <&gcc GCC_VENUS0_AHB_CLK>,
+ <&gcc GCC_VENUS0_AXI_CLK>;
+ clock-names = "core", "iface", "bus";
+ iommus = <&apps_iommu 5>;
+ memory-region = <&venus_mem>;
+ status = "okay";
+
+ video-decoder {
+ compatible = "venus-decoder";
+ };
+
+ video-encoder {
+ compatible = "venus-encoder";
+ };
+ };
};
smd {
diff --git a/dts/src/arm64/qcom/msm8996.dtsi b/dts/src/arm64/qcom/msm8996.dtsi
index 8f085716e2..887b61c872 100644
--- a/dts/src/arm64/qcom/msm8996.dtsi
+++ b/dts/src/arm64/qcom/msm8996.dtsi
@@ -276,12 +276,83 @@
hwlocks = <&tcsr_mutex 3>;
};
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests {
+ compatible = "qcom,rpm-msm8996";
+ qcom,glink-channels = "rpm_requests";
+
+ pm8994-regulators {
+ compatible = "qcom,rpm-pm8994-regulators";
+
+ pm8994_s1: s1 {};
+ pm8994_s2: s2 {};
+ pm8994_s3: s3 {};
+ pm8994_s4: s4 {};
+ pm8994_s5: s5 {};
+ pm8994_s6: s6 {};
+ pm8994_s7: s7 {};
+ pm8994_s8: s8 {};
+ pm8994_s9: s9 {};
+ pm8994_s10: s10 {};
+ pm8994_s11: s11 {};
+ pm8994_s12: s12 {};
+
+ pm8994_l1: l1 {};
+ pm8994_l2: l2 {};
+ pm8994_l3: l3 {};
+ pm8994_l4: l4 {};
+ pm8994_l5: l5 {};
+ pm8994_l6: l6 {};
+ pm8994_l7: l7 {};
+ pm8994_l8: l8 {};
+ pm8994_l9: l9 {};
+ pm8994_l10: l10 {};
+ pm8994_l11: l11 {};
+ pm8994_l12: l12 {};
+ pm8994_l13: l13 {};
+ pm8994_l14: l14 {};
+ pm8994_l15: l15 {};
+ pm8994_l16: l16 {};
+ pm8994_l17: l17 {};
+ pm8994_l18: l18 {};
+ pm8994_l19: l19 {};
+ pm8994_l20: l20 {};
+ pm8994_l21: l21 {};
+ pm8994_l22: l22 {};
+ pm8994_l23: l23 {};
+ pm8994_l24: l24 {};
+ pm8994_l25: l25 {};
+ pm8994_l26: l26 {};
+ pm8994_l27: l27 {};
+ pm8994_l28: l28 {};
+ pm8994_l29: l29 {};
+ pm8994_l30: l30 {};
+ pm8994_l31: l31 {};
+ pm8994_l32: l32 {};
+ };
+
+ };
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
+ rpm_msg_ram: memory@68000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x68000 0x6000>;
+ };
+
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
reg = <0x740000 0x20000>;
@@ -303,6 +374,13 @@
reg = <0x9820000 0x1000>;
};
+ apcs_glb: mailbox@9820000 {
+ compatible = "qcom,msm8996-apcs-hmss-global";
+ reg = <0x9820000 0x1000>;
+
+ #mbox-cells = <1>;
+ };
+
gcc: clock-controller@300000 {
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
@@ -538,6 +616,209 @@
<960000000>,
<825000000>;
};
+
+ qfprom@74000 {
+ compatible = "qcom,qfprom";
+ reg = <0x74000 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qusb2p_hstx_trim: hstx_trim@24e {
+ reg = <0x24e 0x2>;
+ bits = <5 4>;
+ };
+
+ qusb2s_hstx_trim: hstx_trim@24f {
+ reg = <0x24f 0x1>;
+ bits = <1 4>;
+ };
+ };
+
+ phy@34000 {
+ compatible = "qcom,msm8996-qmp-pcie-phy";
+ reg = <0x34000 0x488>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+
+ resets = <&gcc GCC_PCIE_PHY_BCR>,
+ <&gcc GCC_PCIE_PHY_COM_BCR>,
+ <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
+ reset-names = "phy", "common", "cfg";
+ status = "disabled";
+
+ pciephy_0: lane@35000 {
+ reg = <0x035000 0x130>,
+ <0x035200 0x200>,
+ <0x035400 0x1dc>;
+ #phy-cells = <0>;
+
+ clock-output-names = "pcie_0_pipe_clk_src";
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "pipe0";
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "lane0";
+ };
+
+ pciephy_1: lane@36000 {
+ reg = <0x036000 0x130>,
+ <0x036200 0x200>,
+ <0x036400 0x1dc>;
+ #phy-cells = <0>;
+
+ clock-output-names = "pcie_1_pipe_clk_src";
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "pipe1";
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "lane1";
+ };
+
+ pciephy_2: lane@37000 {
+ reg = <0x037000 0x130>,
+ <0x037200 0x200>,
+ <0x037400 0x1dc>;
+ #phy-cells = <0>;
+
+ clock-output-names = "pcie_2_pipe_clk_src";
+ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
+ clock-names = "pipe2";
+ resets = <&gcc GCC_PCIE_2_PHY_BCR>;
+ reset-names = "lane2";
+ };
+ };
+
+ phy@7410000 {
+ compatible = "qcom,msm8996-qmp-usb3-phy";
+ reg = <0x7410000 0x1c4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_CLKREF_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+ status = "disabled";
+
+ ssusb_phy_0: lane@7410200 {
+ reg = <0x7410200 0x200>,
+ <0x7410400 0x130>,
+ <0x7410600 0x1a8>;
+ #phy-cells = <0>;
+
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ };
+ };
+
+ hsusb_phy1: phy@7411000 {
+ compatible = "qcom,msm8996-qusb2-phy";
+ reg = <0x7411000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_RX1_USB2_CLKREF_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ nvmem-cells = <&qusb2p_hstx_trim>;
+ status = "disabled";
+ };
+
+ hsusb_phy2: phy@7412000 {
+ compatible = "qcom,msm8996-qusb2-phy";
+ reg = <0x7412000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_RX2_USB2_CLKREF_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+ nvmem-cells = <&qusb2s_hstx_trim>;
+ status = "disabled";
+ };
+
+ usb2: usb@7600000 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_SLEEP_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <60000000>;
+
+ power-domains = <&gcc USB30_GDSC>;
+ status = "disabled";
+
+ dwc3@7600000 {
+ compatible = "snps,dwc3";
+ reg = <0x7600000 0xcc00>;
+ interrupts = <0 138 0>;
+ phys = <&hsusb_phy2>;
+ phy-names = "usb2-phy";
+ };
+ };
+
+ usb3: usb@6a00000 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>,
+ <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SLEEP_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+
+ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <120000000>;
+
+ power-domains = <&gcc USB30_GDSC>;
+ status = "disabled";
+
+ dwc3@6a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x6a00000 0xcc00>;
+ interrupts = <0 131 0>;
+ phys = <&hsusb_phy1>, <&ssusb_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
};
adsp-pil {
@@ -558,6 +839,15 @@
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
+
+ smd-edge {
+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+ label = "lpass";
+ qcom,ipc = <&apcs 16 8>;
+ qcom,smd-edge = <1>;
+ qcom,remote-pid = <2>;
+ };
};
adsp-smp2p {
@@ -584,6 +874,30 @@
};
};
+ modem-smp2p {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 16 14>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
diff --git a/dts/src/arm64/qcom/pmi8994.dtsi b/dts/src/arm64/qcom/pmi8994.dtsi
index d3879a4e80..57673f9280 100644
--- a/dts/src/arm64/qcom/pmi8994.dtsi
+++ b/dts/src/arm64/qcom/pmi8994.dtsi
@@ -8,6 +8,23 @@
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
+
+ pmi8994_gpios: gpios@c000 {
+ compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <2 0xc0 0 IRQ_TYPE_NONE>,
+ <2 0xc1 0 IRQ_TYPE_NONE>,
+ <2 0xc2 0 IRQ_TYPE_NONE>,
+ <2 0xc3 0 IRQ_TYPE_NONE>,
+ <2 0xc4 0 IRQ_TYPE_NONE>,
+ <2 0xc5 0 IRQ_TYPE_NONE>,
+ <2 0xc6 0 IRQ_TYPE_NONE>,
+ <2 0xc7 0 IRQ_TYPE_NONE>,
+ <2 0xc8 0 IRQ_TYPE_NONE>,
+ <2 0xc9 0 IRQ_TYPE_NONE>;
+ };
};
pmic@3 {
diff --git a/dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts b/dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts
index 95fe207cb6..dd4f9b6a42 100644
--- a/dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts
+++ b/dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts
@@ -9,8 +9,6 @@
* kind, whether express or implied.
*/
-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
-
/dts-v1/;
#include "r8a7795-es1.dtsi"
#include "ulcb.dtsi"
diff --git a/dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts b/dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts
index b84c156ed6..3f7d5f51e4 100644
--- a/dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts
+++ b/dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts
@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
-
/dts-v1/;
#include "r8a7795-es1.dtsi"
#include "salvator-x.dtsi"
diff --git a/dts/src/arm64/renesas/r8a7795-es1.dtsi b/dts/src/arm64/renesas/r8a7795-es1.dtsi
index a0ba7bd21e..aaa5e67a96 100644
--- a/dts/src/arm64/renesas/r8a7795-es1.dtsi
+++ b/dts/src/arm64/renesas/r8a7795-es1.dtsi
@@ -21,6 +21,14 @@
status = "disabled";
};
+ /delete-node/ usb-phy@ee0e0200;
+ /delete-node/ usb@ee0e0100;
+ /delete-node/ usb@ee0e0000;
+ /delete-node/ usb@e659c000;
+
+ /delete-node/ dma-controller@e6460000;
+ /delete-node/ dma-controller@e6470000;
+
fcpf2: fcp@fe952000 {
compatible = "renesas,fcpf";
reg = <0 0xfe952000 0 0x200>;
@@ -79,6 +87,5 @@
};
&du {
- compatible = "renesas,du-r8a7795";
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
};
diff --git a/dts/src/arm64/renesas/r8a7795-h3ulcb.dts b/dts/src/arm64/renesas/r8a7795-h3ulcb.dts
index 0426f41765..0afe777973 100644
--- a/dts/src/arm64/renesas/r8a7795-h3ulcb.dts
+++ b/dts/src/arm64/renesas/r8a7795-h3ulcb.dts
@@ -9,8 +9,6 @@
* kind, whether express or implied.
*/
-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
-
/dts-v1/;
#include "r8a7795.dtsi"
#include "ulcb.dtsi"
@@ -40,3 +38,17 @@
reg = <0x7 0x00000000 0x0 0x40000000>;
};
};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 727>,
+ <&versaclock5 1>,
+ <&versaclock5 3>,
+ <&versaclock5 4>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+ "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
+};
diff --git a/dts/src/arm64/renesas/r8a7795-salvator-x.dts b/dts/src/arm64/renesas/r8a7795-salvator-x.dts
index 684fb3b9d1..17953070f3 100644
--- a/dts/src/arm64/renesas/r8a7795-salvator-x.dts
+++ b/dts/src/arm64/renesas/r8a7795-salvator-x.dts
@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
-
/dts-v1/;
#include "r8a7795.dtsi"
#include "salvator-x.dtsi"
diff --git a/dts/src/arm64/renesas/r8a7795-salvator-xs.dts b/dts/src/arm64/renesas/r8a7795-salvator-xs.dts
index de35495714..7675de5d4f 100644
--- a/dts/src/arm64/renesas/r8a7795-salvator-xs.dts
+++ b/dts/src/arm64/renesas/r8a7795-salvator-xs.dts
@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
-
/dts-v1/;
#include "r8a7795.dtsi"
#include "salvator-xs.dtsi"
@@ -46,10 +44,12 @@
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
+ <&versaclock6 1>,
<&x21_clk>,
- <&x22_clk>;
+ <&x22_clk>,
+ <&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
- "dclkin.1", "dclkin.2";
+ "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
&ehci2 {
diff --git a/dts/src/arm64/renesas/r8a7795.dtsi b/dts/src/arm64/renesas/r8a7795.dtsi
index e31c1b660b..2938195b95 100644
--- a/dts/src/arm64/renesas/r8a7795.dtsi
+++ b/dts/src/arm64/renesas/r8a7795.dtsi
@@ -12,6 +12,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7795-sysc.h>
+#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
+
/ {
compatible = "renesas,r8a7795";
#address-cells = <2>;
@@ -691,6 +693,126 @@
};
};
+ drif00: rif@e6f40000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f40000 0 0x64>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 515>;
+ renesas,bonding = <&drif01>;
+ status = "disabled";
+ };
+
+ drif01: rif@e6f50000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f50000 0 0x64>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 514>;
+ renesas,bonding = <&drif00>;
+ status = "disabled";
+ };
+
+ drif10: rif@e6f60000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f60000 0 0x64>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 513>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x24>, <&dmac2 0x24>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 513>;
+ renesas,bonding = <&drif11>;
+ status = "disabled";
+ };
+
+ drif11: rif@e6f70000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f70000 0 0x64>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 512>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x26>, <&dmac2 0x26>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 512>;
+ renesas,bonding = <&drif10>;
+ status = "disabled";
+ };
+
+ drif20: rif@e6f80000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f80000 0 0x64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 511>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x28>, <&dmac2 0x28>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 511>;
+ renesas,bonding = <&drif21>;
+ status = "disabled";
+ };
+
+ drif21: rif@e6f90000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f90000 0 0x64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 510>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 510>;
+ renesas,bonding = <&drif20>;
+ status = "disabled";
+ };
+
+ drif30: rif@e6fa0000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fa0000 0 0x64>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 509>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 509>;
+ renesas,bonding = <&drif31>;
+ status = "disabled";
+ };
+
+ drif31: rif@e6fb0000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fb0000 0 0x64>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 508>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 508>;
+ renesas,bonding = <&drif30>;
+ status = "disabled";
+ };
+
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a7795",
"renesas,rcar-gen3-hscif",
@@ -776,6 +898,68 @@
status = "disabled";
};
+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a7795",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e90000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 211>;
+ dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+ <&dmac2 0x41>, <&dmac2 0x40>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a7795",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 210>;
+ dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+ <&dmac2 0x43>, <&dmac2 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a7795",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 209>;
+ dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a7795",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7795",
"renesas,rcar-gen3-scif", "renesas,scif";
@@ -1267,7 +1451,8 @@
};
sata: sata@ee300000 {
- compatible = "renesas,sata-r8a7795";
+ compatible = "renesas,sata-r8a7795",
+ "renesas,rcar-gen3-sata";
reg = <0 0xee300000 0 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
@@ -1314,6 +1499,34 @@
dma-channels = <2>;
};
+ usb_dmac2: dma-controller@e6460000 {
+ compatible = "renesas,r8a7795-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe6460000 0 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 326>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 326>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac3: dma-controller@e6470000 {
+ compatible = "renesas,r8a7795-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe6470000 0 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 329>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7795";
reg = <0 0xee100000 0 0x2000>;
@@ -1392,6 +1605,18 @@
status = "disabled";
};
+ usb2_phy3: usb-phy@ee0e0200 {
+ compatible = "renesas,usb2-phy-r8a7795",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0xee0e0200 0 0x700>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 700>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 700>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
ehci0: usb@ee080100 {
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
@@ -1399,6 +1624,7 @@
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
+ companion = <&ohci0>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
@@ -1411,6 +1637,7 @@
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
+ companion = <&ohci1>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
@@ -1423,11 +1650,25 @@
clocks = <&cpg CPG_MOD 701>;
phys = <&usb2_phy2>;
phy-names = "usb";
+ companion = <&ohci2>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 701>;
status = "disabled";
};
+ ehci3: usb@ee0e0100 {
+ compatible = "generic-ehci";
+ reg = <0 0xee0e0100 0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 700>;
+ phys = <&usb2_phy3>;
+ phy-names = "usb";
+ companion = <&ohci3>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 700>;
+ status = "disabled";
+ };
+
ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
@@ -1464,6 +1705,18 @@
status = "disabled";
};
+ ohci3: usb@ee0e0000 {
+ compatible = "generic-ohci";
+ reg = <0 0xee0e0000 0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 700>;
+ phys = <&usb2_phy3>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 700>;
+ status = "disabled";
+ };
+
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7795",
"renesas,rcar-gen3-usbhs";
@@ -1481,6 +1734,23 @@
status = "disabled";
};
+ hsusb3: usb@e659c000 {
+ compatible = "renesas,usbhs-r8a7795",
+ "renesas,rcar-gen3-usbhs";
+ reg = <0 0xe659c000 0 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 705>;
+ dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
+ <&usb_dmac3 0>, <&usb_dmac3 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ renesas,buswait = <11>;
+ phys = <&usb2_phy3>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 705>;
+ status = "disabled";
+ };
+
pciec0: pcie@fe000000 {
compatible = "renesas,pcie-r8a7795",
"renesas,pcie-rcar-gen3";
@@ -1535,6 +1805,46 @@
status = "disabled";
};
+ imr-lx4@fe860000 {
+ compatible = "renesas,r8a7795-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe860000 0 0x2000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 823>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 823>;
+ };
+
+ imr-lx4@fe870000 {
+ compatible = "renesas,r8a7795-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe870000 0 0x2000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 822>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 822>;
+ };
+
+ imr-lx4@fe880000 {
+ compatible = "renesas,r8a7795-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe880000 0 0x2000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 821>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 821>;
+ };
+
+ imr-lx4@fe890000 {
+ compatible = "renesas,r8a7795-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe890000 0 0x2000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 820>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 820>;
+ };
+
vspbc: vsp@fe920000 {
compatible = "renesas,vsp2";
reg = <0 0xfe920000 0 0x8000>;
@@ -1755,6 +2065,7 @@
};
du: display@feb00000 {
+ compatible = "renesas,du-r8a7795";
reg = <0 0xfeb00000 0 0x80000>,
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
@@ -1768,6 +2079,7 @@
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+ vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
status = "disabled";
ports {
diff --git a/dts/src/arm64/renesas/r8a7796-m3ulcb.dts b/dts/src/arm64/renesas/r8a7796-m3ulcb.dts
index 38b58b7fca..daee1f1a3f 100644
--- a/dts/src/arm64/renesas/r8a7796-m3ulcb.dts
+++ b/dts/src/arm64/renesas/r8a7796-m3ulcb.dts
@@ -9,8 +9,6 @@
* kind, whether express or implied.
*/
-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
-
/dts-v1/;
#include "r8a7796.dtsi"
#include "ulcb.dtsi"
@@ -30,3 +28,15 @@
reg = <0x6 0x00000000 0x0 0x40000000>;
};
};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 727>,
+ <&versaclock5 1>,
+ <&versaclock5 3>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0",
+ "dclkin.0", "dclkin.1", "dclkin.2";
+};
diff --git a/dts/src/arm64/renesas/r8a7796-salvator-x.dts b/dts/src/arm64/renesas/r8a7796-salvator-x.dts
index db4f162d6b..b317be0330 100644
--- a/dts/src/arm64/renesas/r8a7796-salvator-x.dts
+++ b/dts/src/arm64/renesas/r8a7796-salvator-x.dts
@@ -8,8 +8,6 @@
* kind, whether express or implied.
*/
-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
-
/dts-v1/;
#include "r8a7796.dtsi"
#include "salvator-x.dtsi"
@@ -29,3 +27,32 @@
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 727>,
+ <&versaclock5 1>,
+ <&x21_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0",
+ "dclkin.0", "dclkin.1", "dclkin.2";
+};
+
+&hdmi0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ };
+};
+
+&hdmi0_con {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+};
diff --git a/dts/src/arm64/renesas/r8a7796.dtsi b/dts/src/arm64/renesas/r8a7796.dtsi
index 1f67109120..369092e17e 100644
--- a/dts/src/arm64/renesas/r8a7796.dtsi
+++ b/dts/src/arm64/renesas/r8a7796.dtsi
@@ -12,6 +12,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7796-sysc.h>
+#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
+
/ {
compatible = "renesas,r8a7796";
#address-cells = <2>;
@@ -639,6 +641,126 @@
};
};
+ drif00: rif@e6f40000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f40000 0 0x64>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 515>;
+ renesas,bonding = <&drif01>;
+ status = "disabled";
+ };
+
+ drif01: rif@e6f50000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f50000 0 0x64>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 514>;
+ renesas,bonding = <&drif00>;
+ status = "disabled";
+ };
+
+ drif10: rif@e6f60000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f60000 0 0x64>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 513>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x24>, <&dmac2 0x24>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 513>;
+ renesas,bonding = <&drif11>;
+ status = "disabled";
+ };
+
+ drif11: rif@e6f70000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f70000 0 0x64>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 512>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x26>, <&dmac2 0x26>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 512>;
+ renesas,bonding = <&drif10>;
+ status = "disabled";
+ };
+
+ drif20: rif@e6f80000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f80000 0 0x64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 511>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x28>, <&dmac2 0x28>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 511>;
+ renesas,bonding = <&drif21>;
+ status = "disabled";
+ };
+
+ drif21: rif@e6f90000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f90000 0 0x64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 510>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 510>;
+ renesas,bonding = <&drif20>;
+ status = "disabled";
+ };
+
+ drif30: rif@e6fa0000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fa0000 0 0x64>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 509>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 509>;
+ renesas,bonding = <&drif31>;
+ status = "disabled";
+ };
+
+ drif31: rif@e6fb0000 {
+ compatible = "renesas,r8a7796-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6fb0000 0 0x64>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 508>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 508>;
+ renesas,bonding = <&drif30>;
+ status = "disabled";
+ };
+
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7796",
"renesas,etheravb-rcar-gen3";
@@ -877,7 +999,7 @@
clocks = <&cpg CPG_MOD 211>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx";
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 211>;
#address-cells = <1>;
@@ -893,7 +1015,7 @@
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx";
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
@@ -1101,36 +1223,133 @@
dma-channels = <16>;
};
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a7796-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a7796-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
hsusb: usb@e6590000 {
- /* placeholder */
+ compatible = "renesas,usbhs-r8a7796",
+ "renesas,rcar-gen3-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ renesas,buswait = <11>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
};
xhci0: usb@ee000000 {
- /* placeholder */
+ compatible = "renesas,xhci-r8a7796",
+ "renesas,rcar-gen3-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ status = "disabled";
};
ohci0: usb@ee080000 {
- /* placeholder */
+ compatible = "generic-ohci";
+ reg = <0 0xee080000 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
};
ehci0: usb@ee080100 {
- /* placeholder */
+ compatible = "generic-ehci";
+ reg = <0 0xee080100 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ companion= <&ohci0>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
};
usb2_phy0: usb-phy@ee080200 {
- /* placeholder */
+ compatible = "renesas,usb2-phy-r8a7796",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0xee080200 0 0x700>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ #phy-cells = <0>;
+ status = "disabled";
};
ohci1: usb@ee0a0000 {
- /* placeholder */
+ compatible = "generic-ohci";
+ reg = <0 0xee0a0000 0 0x100>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 702>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 702>;
+ status = "disabled";
};
ehci1: usb@ee0a0100 {
- /* placeholder */
+ compatible = "generic-ehci";
+ reg = <0 0xee0a0100 0 0x100>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 702>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ companion= <&ohci1>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 702>;
+ status = "disabled";
};
usb2_phy1: usb-phy@ee0a0200 {
- /* placeholder */
+ compatible = "renesas,usb2-phy-r8a7796",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0xee0a0200 0 0x700>;
+ clocks = <&cpg CPG_MOD 702>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 702>;
+ #phy-cells = <0>;
+ status = "disabled";
};
sdhi0: sd@ee100000 {
@@ -1440,8 +1659,150 @@
/* placeholder */
};
+ fcpf0: fcp@fe950000 {
+ compatible = "renesas,fcpf";
+ reg = <0 0xfe950000 0 0x200>;
+ clocks = <&cpg CPG_MOD 615>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 615>;
+ };
+
+ vspb: vsp@fe960000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe960000 0 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 626>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 626>;
+
+ renesas,fcp = <&fcpvb0>;
+ };
+
+ fcpvb0: fcp@fe96f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe96f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 607>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 607>;
+ };
+
+ vspi0: vsp@fe9a0000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe9a0000 0 0x8000>;
+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 631>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 631>;
+
+ renesas,fcp = <&fcpvi0>;
+ };
+
+ fcpvi0: fcp@fe9af000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe9af000 0 0x200>;
+ clocks = <&cpg CPG_MOD 611>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 611>;
+ };
+
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x4000>;
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ fcpvd0: fcp@fea27000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea27000 0 0x200>;
+ clocks = <&cpg CPG_MOD 603>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 603>;
+ };
+
+ vspd1: vsp@fea28000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea28000 0 0x4000>;
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 622>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 622>;
+
+ renesas,fcp = <&fcpvd1>;
+ };
+
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 602>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 602>;
+ };
+
+ vspd2: vsp@fea30000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea30000 0 0x4000>;
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 621>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 621>;
+
+ renesas,fcp = <&fcpvd2>;
+ };
+
+ fcpvd2: fcp@fea37000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea37000 0 0x200>;
+ clocks = <&cpg CPG_MOD 601>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 601>;
+ };
+
+ hdmi0: hdmi@fead0000 {
+ compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
+ reg = <0 0xfead0000 0 0x10000>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 729>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dw_hdmi0_in: endpoint {
+ remote-endpoint = <&du_out_hdmi0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
du: display@feb00000 {
- /* placeholder */
+ compatible = "renesas,du-r8a7796";
+ reg = <0 0xfeb00000 0 0x70000>,
+ <0 0xfeb90000 0 0x14>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 727>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0";
+ status = "disabled";
+
+ vsps = <&vspd0 &vspd1 &vspd2>;
ports {
#address-cells = <1>;
@@ -1452,7 +1813,38 @@
du_out_rgb: endpoint {
};
};
+ port@1 {
+ reg = <1>;
+ du_out_hdmi0: endpoint {
+ remote-endpoint = <&dw_hdmi0_in>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ du_out_lvds0: endpoint {
+ };
+ };
};
};
+
+ imr-lx4@fe860000 {
+ compatible = "renesas,r8a7796-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe860000 0 0x2000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 823>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 823>;
+ };
+
+ imr-lx4@fe870000 {
+ compatible = "renesas,r8a7796-imr-lx4",
+ "renesas,imr-lx4";
+ reg = <0 0xfe870000 0 0x2000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 822>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 822>;
+ };
};
};
diff --git a/dts/src/arm64/renesas/r8a77995-draak.dts b/dts/src/arm64/renesas/r8a77995-draak.dts
new file mode 100644
index 0000000000..d144370051
--- /dev/null
+++ b/dts/src/arm64/renesas/r8a77995-draak.dts
@@ -0,0 +1,46 @@
+/*
+ * Device Tree Source for the Draak board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a77995.dtsi"
+
+/ {
+ model = "Renesas Draak board based on r8a77995";
+ compatible = "renesas,draak", "renesas,r8a77995";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x18000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <48000000>;
+};
+
+&scif2 {
+ status = "okay";
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/renesas/r8a77995.dtsi b/dts/src/arm64/renesas/r8a77995.dtsi
new file mode 100644
index 0000000000..d0f95b78c0
--- /dev/null
+++ b/dts/src/arm64/renesas/r8a77995.dtsi
@@ -0,0 +1,155 @@
+/*
+ * Device Tree Source for the r8a77995 SoC
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "renesas,r8a77995";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a53_0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ device_type = "cpu";
+ power-domains = <&sysc 5>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ L2_CA53: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc 21>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@f1010000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xf1010000 0 0x1000>,
+ <0x0 0xf1020000 0 0x20000>,
+ <0x0 0xf1040000 0 0x20000>,
+ <0x0 0xf1060000 0 0x20000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 408>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a77995-wdt",
+ "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77995-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a77995-rst";
+ reg = <0 0xe6160000 0 0x0200>;
+ };
+
+ pfc: pfc@e6060000 {
+ compatible = "renesas,pfc-r8a77995";
+ reg = <0 0xe6060000 0 0x508>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a77995-sysc";
+ reg = <0 0xe6180000 0 0x0400>;
+ #power-domain-cells = <1>;
+ };
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a77995",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e88000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE 16>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 310>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/dts/src/arm64/renesas/salvator-common.dtsi b/dts/src/arm64/renesas/salvator-common.dtsi
index f903957da5..4786c67b5e 100644
--- a/dts/src/arm64/renesas/salvator-common.dtsi
+++ b/dts/src/arm64/renesas/salvator-common.dtsi
@@ -268,10 +268,6 @@
remote-endpoint = <&adv7123_in>;
};
};
- port@3 {
- lvds_connector: endpoint {
- };
- };
};
};
diff --git a/dts/src/arm64/renesas/salvator-xs.dtsi b/dts/src/arm64/renesas/salvator-xs.dtsi
index 81227e3c2c..bf4d200fb5 100644
--- a/dts/src/arm64/renesas/salvator-xs.dtsi
+++ b/dts/src/arm64/renesas/salvator-xs.dtsi
@@ -18,3 +18,13 @@
&extal_clk {
clock-frequency = <16640000>;
};
+
+&i2c4 {
+ versaclock6: clock-generator@6a {
+ compatible = "idt,5p49v6901";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+ clocks = <&x23_clk>;
+ clock-names = "xin";
+ };
+};
diff --git a/dts/src/arm64/renesas/ulcb.dtsi b/dts/src/arm64/renesas/ulcb.dtsi
index d1a3f3b7a0..1b868df239 100644
--- a/dts/src/arm64/renesas/ulcb.dtsi
+++ b/dts/src/arm64/renesas/ulcb.dtsi
@@ -34,6 +34,16 @@
clock-frequency = <11289600>;
};
+ hdmi0-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con: endpoint {
+ };
+ };
+ };
+
keyboard {
compatible = "gpio-keys";
@@ -120,6 +130,12 @@
#clock-cells = <0>;
clock-frequency = <24576000>;
};
+
+ x23_clk: x23-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
};
&audio_clk_a {
@@ -153,6 +169,23 @@
clock-frequency = <32768>;
};
+&hdmi0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ };
+};
+
+&hdmi0_con {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+};
+
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
@@ -189,6 +222,24 @@
};
};
+&i2c4 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ versaclock5: clock-generator@6a {
+ compatible = "idt,5p49v5925";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+ clocks = <&x23_clk>;
+ clock-names = "xin";
+ };
+};
+
+&i2c_dvfs {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
diff --git a/dts/src/arm64/rockchip/rk3328-evb.dts b/dts/src/arm64/rockchip/rk3328-evb.dts
index cf272392ce..8e6a654317 100644
--- a/dts/src/arm64/rockchip/rk3328-evb.dts
+++ b/dts/src/arm64/rockchip/rk3328-evb.dts
@@ -50,8 +50,189 @@
chosen {
stdout-path = "serial2:1500000n8";
};
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
};
&uart2 {
status = "okay";
};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
diff --git a/dts/src/arm64/rockchip/rk3328-rock64.dts b/dts/src/arm64/rockchip/rk3328-rock64.dts
new file mode 100644
index 0000000000..d4f80786e7
--- /dev/null
+++ b/dts/src/arm64/rockchip/rk3328-rock64.dts
@@ -0,0 +1,333 @@
+/*
+ * Copyright (c) 2017 PINE64
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Pine64 Rock64";
+ compatible = "pine64,rock64", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_host_5v: vcc-host-5v-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_host_drv>;
+ regulator-name = "vcc_host_5v";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb20_host_drv>;
+ regulator-name = "vcc_host1_5v";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_io>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_sys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vdd_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc_18emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ usb20_host_drv: usb20-host-drv {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb3 {
+ usb30_host_drv: usb30-host-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
+&usb20_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
diff --git a/dts/src/arm64/rockchip/rk3328.dtsi b/dts/src/arm64/rockchip/rk3328.dtsi
index 0be96cee27..6d615cb6e6 100644
--- a/dts/src/arm64/rockchip/rk3328.dtsi
+++ b/dts/src/arm64/rockchip/rk3328.dtsi
@@ -47,6 +47,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3328-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3328";
@@ -63,6 +64,8 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
+ ethernet0 = &gmac2io;
+ ethernet1 = &gmac2phy;
};
cpus {
@@ -74,8 +77,11 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu1: cpu@1 {
@@ -83,8 +89,10 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@2 {
@@ -92,8 +100,10 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@3 {
@@ -101,8 +111,10 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
l2: l2-cache0 {
@@ -110,6 +122,43 @@
};
};
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1225000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1300000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
amba {
compatible = "simple-bus";
#address-cells = <2>;
@@ -156,12 +205,84 @@
clock-output-names = "xin24m";
};
+ i2s0: i2s@ff000000 {
+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff000000 0x0 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 11>, <&dmac 12>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2s1: i2s@ff010000 {
+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff010000 0x0 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 14>, <&dmac 15>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2s2: i2s@ff020000 {
+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff020000 0x0 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 0>, <&dmac 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spdif: spdif@ff030000 {
+ compatible = "rockchip,rk3328-spdif";
+ reg = <0x0 0xff030000 0x0 0x1000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 10>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdifm2_tx>;
+ status = "disabled";
+ };
+
+ pdm: pdm@ff040000 {
+ compatible = "rockchip,pdm";
+ reg = <0x0 0xff040000 0x0 0x1000>;
+ clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ dmas = <&dmac 16>;
+ dma-names = "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pdmm0_clk
+ &pdmm0_sdi0
+ &pdmm0_sdi1
+ &pdmm0_sdi2
+ &pdmm0_sdi3>;
+ pinctrl-1 = <&pdmm0_clk_sleep
+ &pdmm0_sdi0_sleep
+ &pdmm0_sdi1_sleep
+ &pdmm0_sdi2_sleep
+ &pdmm0_sdi3_sleep>;
+ status = "disabled";
+ };
+
grf: syscon@ff100000 {
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ io_domains: io-domains {
+ compatible = "rockchip,rk3328-io-voltage-domain";
+ status = "disabled";
+ };
+
power: power-controller {
compatible = "rockchip,rk3328-power-controller";
#power-domain-cells = <1>;
@@ -308,6 +429,108 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
};
+ pwm0: pwm@ff1b0000 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0000 0x0 0x10>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@ff1b0010 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0010 0x0 0x10>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@ff1b0020 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0020 0x0 0x10>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@ff1b0030 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0030 0x0 0x10>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwmir_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ thermal-zones {
+ soc_thermal: soc-thermal {
+ polling-delay-passive = <20>;
+ polling-delay = <1000>;
+ sustainable-power = <1000>;
+
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ threshold: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ target: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ soc_crit: soc-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <4096>;
+ };
+ };
+ };
+
+ };
+
+ tsadc: tsadc@ff250000 {
+ compatible = "rockchip,rk3328-tsadc";
+ reg = <0x0 0xff250000 0x0 0x100>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&cru SCLK_TSADC>;
+ assigned-clock-rates = <50000>;
+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
+ resets = <&cru SRST_TSADC>;
+ reset-names = "tsadc-apb";
+ rockchip,grf = <&grf>;
+ rockchip,hw-tshut-temp = <100000>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
saradc: adc@ff280000 {
compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xff280000 0x0 0x100>;
@@ -320,6 +543,51 @@
status = "disabled";
};
+ h265e_mmu: iommu@ff330200 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff330200 0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "h265e_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vepu_mmu: iommu@ff340800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff340800 0x0 0x40>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu@ff350800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff350800 0x0 0x40>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ rkvdec_mmu: iommu@ff360480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rkvdec_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vop_mmu: iommu@ff373f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff373f00 0x0 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vop_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>;
@@ -372,6 +640,43 @@
<32768>;
};
+ usb2phy_grf: syscon@ff450000 {
+ compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2-phy@100 {
+ compatible = "rockchip,rk3328-usb2phy";
+ reg = <0x100 0x10>;
+ clocks = <&xin24m>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+ };
+
sdmmc: dwmmc@ff500000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>;
@@ -424,6 +729,82 @@
status = "disabled";
};
+ gmac2phy: ethernet@ff550000 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff550000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
+ <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
+ <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
+ <&cru SCLK_MAC2PHY_OUT>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "aclk_mac", "pclk_mac",
+ "clk_macphy";
+ resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
+ reset-names = "stmmaceth", "mac-phy";
+ phy-mode = "rmii";
+ phy-handle = <&phy>;
+ status = "disabled";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@0 {
+ compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ clocks = <&cru SCLK_MAC2PHY_OUT>;
+ resets = <&cru SRST_MACPHY>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
+ phy-is-integrated;
+ };
+ };
+ };
+
+ usb20_otg: usb@ff580000 {
+ compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff580000 0x0 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ g-use-dma;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host0_ehci: usb@ff5c0000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff5c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@ff5d0000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff5d0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -610,6 +991,62 @@
};
};
+ pdm-0 {
+ pdmm0_clk: pdmm0-clk {
+ rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_fsync: pdmm0-fsync {
+ rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi0: pdmm0-sdi0 {
+ rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi1: pdmm0-sdi1 {
+ rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi2: pdmm0-sdi2 {
+ rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi3: pdmm0-sdi3 {
+ rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_clk_sleep: pdmm0-clk-sleep {
+ rockchip,pins =
+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
+ rockchip,pins =
+ <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
+ rockchip,pins =
+ <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
+ rockchip,pins =
+ <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
+ rockchip,pins =
+ <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_fsync_sleep: pdmm0-fsync-sleep {
+ rockchip,pins =
+ <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+ };
+
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/dts/src/arm64/rockchip/rk3368-evb.dtsi b/dts/src/arm64/rockchip/rk3368-evb.dtsi
index 4772917c5f..a37220a938 100644
--- a/dts/src/arm64/rockchip/rk3368-evb.dtsi
+++ b/dts/src/arm64/rockchip/rk3368-evb.dtsi
@@ -156,7 +156,6 @@
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
diff --git a/dts/src/arm64/rockchip/rk3368-geekbox.dts b/dts/src/arm64/rockchip/rk3368-geekbox.dts
index e631d424f0..5e4d3a7015 100644
--- a/dts/src/arm64/rockchip/rk3368-geekbox.dts
+++ b/dts/src/arm64/rockchip/rk3368-geekbox.dts
@@ -117,7 +117,6 @@
clock-frequency = <150000000>;
disable-wp;
non-removable;
- num-slots = <1>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_flash>;
pinctrl-names = "default";
diff --git a/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts b/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts
index fac116acc1..d3f6c8e0d2 100644
--- a/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts
+++ b/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts
@@ -203,7 +203,6 @@
mmc-hs200-1_2v;
mmc-hs200-1_8v;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
@@ -347,7 +346,6 @@
max-frequency = <50000000>;
cap-sd-highspeed;
card-detect-delay = <200>;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
diff --git a/dts/src/arm64/rockchip/rk3368-px5-evb.dts b/dts/src/arm64/rockchip/rk3368-px5-evb.dts
index ff48edd8e3..13a9e22f5d 100644
--- a/dts/src/arm64/rockchip/rk3368-px5-evb.dts
+++ b/dts/src/arm64/rockchip/rk3368-px5-evb.dts
@@ -86,12 +86,10 @@
cap-mmc-highspeed;
clock-frequency = <150000000>;
disable-wp;
- keep-power-in-suspend;
mmc-hs200-1_8v;
no-sdio;
no-sd;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
vmmc-supply = <&vcc_io>;
@@ -281,7 +279,6 @@
card-detect-delay = <200>;
no-emmc;
no-sdio;
- num-slots = <1>;
sd-uhs-sdr12;
sd-uhs-sdr25;
pinctrl-names = "default";
diff --git a/dts/src/arm64/rockchip/rk3368-r88.dts b/dts/src/arm64/rockchip/rk3368-r88.dts
index 7134181f1d..b3510d5651 100644
--- a/dts/src/arm64/rockchip/rk3368-r88.dts
+++ b/dts/src/arm64/rockchip/rk3368-r88.dts
@@ -189,7 +189,6 @@
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
@@ -254,7 +253,6 @@
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
vmmc-supply = <&vcc_io>;
diff --git a/dts/src/arm64/rockchip/rk3368.dtsi b/dts/src/arm64/rockchip/rk3368.dtsi
index 6d5dc0587e..e0518b4bc6 100644
--- a/dts/src/arm64/rockchip/rk3368.dtsi
+++ b/dts/src/arm64/rockchip/rk3368.dtsi
@@ -113,7 +113,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
-
+ clocks = <&cru ARMCLKL>;
+ operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>; /* min followed by max */
};
@@ -122,6 +123,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+ clocks = <&cru ARMCLKL>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_l2: cpu@2 {
@@ -129,6 +132,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+ clocks = <&cru ARMCLKL>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_l3: cpu@3 {
@@ -136,6 +141,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+ clocks = <&cru ARMCLKL>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_b0: cpu@100 {
@@ -143,7 +150,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
-
+ clocks = <&cru ARMCLKB>;
+ operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>; /* min followed by max */
};
@@ -152,6 +160,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
+ clocks = <&cru ARMCLKB>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_b2: cpu@102 {
@@ -159,6 +169,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
+ clocks = <&cru ARMCLKB>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_b3: cpu@103 {
@@ -166,6 +178,62 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
+ clocks = <&cru ARMCLKB>;
+ operating-points-v2 = <&cluster1_opp>;
+ };
+ };
+
+ cluster0_opp: opp-table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <950000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cluster1_opp: opp-table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <950000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <975000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1050000>;
};
};
@@ -700,6 +768,19 @@
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
};
+ spdif: spdif@ff880000 {
+ compatible = "rockchip,rk3368-spdif";
+ reg = <0x0 0xff880000 0x0 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac_bus 3>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx>;
+ status = "disabled";
+ };
+
i2s_2ch: i2s-2ch@ff890000 {
compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x1000>;
@@ -724,6 +805,55 @@
status = "disabled";
};
+ iep_mmu: iommu@ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff900800 0x0 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ isp_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>,
+ <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ vop_mmu: iommu@ff930300 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff930300 0x0 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ hevc_mmu: iommu@ff9a0440 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0440 0x0 0x40>,
+ <0x0 0xff9a0480 0x0 0x40>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu@ff9a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu_mmu", "vdpu_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -1024,6 +1154,12 @@
};
};
+ spdif {
+ spdif_tx: spdif-tx {
+ rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
spi0 {
spi0_clk: spi0-clk {
rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
diff --git a/dts/src/arm64/rockchip/rk3399-evb.dts b/dts/src/arm64/rockchip/rk3399-evb.dts
index 42033bcc61..56533c344e 100644
--- a/dts/src/arm64/rockchip/rk3399-evb.dts
+++ b/dts/src/arm64/rockchip/rk3399-evb.dts
@@ -199,7 +199,7 @@
ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn>;
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "disabled";
};
diff --git a/dts/src/arm64/rockchip/rk3399-firefly.dts b/dts/src/arm64/rockchip/rk3399-firefly.dts
index ba1d9810ad..7fd4bfcaa3 100644
--- a/dts/src/arm64/rockchip/rk3399-firefly.dts
+++ b/dts/src/arm64/rockchip/rk3399-firefly.dts
@@ -43,6 +43,7 @@
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
/ {
model = "Firefly-RK3399 Board";
@@ -550,7 +551,7 @@
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn>;
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
@@ -630,9 +631,20 @@
status = "okay";
};
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
- keep-power-in-suspend;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
diff --git a/dts/src/arm64/rockchip/rk3399-gru-kevin.dts b/dts/src/arm64/rockchip/rk3399-gru-kevin.dts
index 7bd3106639..a3d3cea7dc 100644
--- a/dts/src/arm64/rockchip/rk3399-gru-kevin.dts
+++ b/dts/src/arm64/rockchip/rk3399-gru-kevin.dts
@@ -264,6 +264,50 @@ ap_i2c_dig: &i2c2 {
};
};
+&ppvar_bigcpu_pwm {
+ regulator-min-microvolt = <798674>;
+ regulator-max-microvolt = <1302172>;
+};
+
+&ppvar_bigcpu {
+ regulator-min-microvolt = <798674>;
+ regulator-max-microvolt = <1302172>;
+ ctrl-voltage-range = <798674 1302172>;
+};
+
+&ppvar_litcpu_pwm {
+ regulator-min-microvolt = <799065>;
+ regulator-max-microvolt = <1303738>;
+};
+
+&ppvar_litcpu {
+ regulator-min-microvolt = <799065>;
+ regulator-max-microvolt = <1303738>;
+ ctrl-voltage-range = <799065 1303738>;
+};
+
+&ppvar_gpu_pwm {
+ regulator-min-microvolt = <785782>;
+ regulator-max-microvolt = <1217729>;
+};
+
+&ppvar_gpu {
+ regulator-min-microvolt = <785782>;
+ regulator-max-microvolt = <1217729>;
+ ctrl-voltage-range = <785782 1217729>;
+};
+
+&ppvar_centerlogic_pwm {
+ regulator-min-microvolt = <800069>;
+ regulator-max-microvolt = <1049692>;
+};
+
+&ppvar_centerlogic {
+ regulator-min-microvolt = <800069>;
+ regulator-max-microvolt = <1049692>;
+ ctrl-voltage-range = <800069 1049692>;
+};
+
&saradc {
status = "okay";
vref-supply = <&pp1800_ap_io>;
diff --git a/dts/src/arm64/rockchip/rk3399-gru.dtsi b/dts/src/arm64/rockchip/rk3399-gru.dtsi
index eb50593440..199a5118b2 100644
--- a/dts/src/arm64/rockchip/rk3399-gru.dtsi
+++ b/dts/src/arm64/rockchip/rk3399-gru.dtsi
@@ -164,14 +164,9 @@
vin-supply = <&ppvar_sys>;
};
- ppvar_bigcpu: ppvar-bigcpu {
+ ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
compatible = "pwm-regulator";
- regulator-name = "ppvar_bigcpu";
- /*
- * OVP circuit requires special handling which is not yet
- * represented. Keep disabled for now.
- */
- status = "disabled";
+ regulator-name = "ppvar_bigcpu_pwm";
pwms = <&pwm1 0 3337 0>;
pwm-supply = <&ppvar_sys>;
@@ -181,18 +176,28 @@
/* EC turns on w/ ap_core_en; always on for AP */
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <798674>;
- regulator-max-microvolt = <1302172>;
+ regulator-min-microvolt = <800107>;
+ regulator-max-microvolt = <1302232>;
};
- ppvar_litcpu: ppvar-litcpu {
+ ppvar_bigcpu: ppvar-bigcpu {
+ compatible = "vctrl-regulator";
+ regulator-name = "ppvar_bigcpu";
+
+ regulator-min-microvolt = <800107>;
+ regulator-max-microvolt = <1302232>;
+
+ ctrl-supply = <&ppvar_bigcpu_pwm>;
+ ctrl-voltage-range = <800107 1302232>;
+
+ regulator-settling-time-up-us = <322>;
+ min-slew-down-rate = <225>;
+ ovp-threshold-percent = <16>;
+ };
+
+ ppvar_litcpu_pwm: ppvar-litcpu-pwm {
compatible = "pwm-regulator";
- regulator-name = "ppvar_litcpu";
- /*
- * OVP circuit requires special handling which is not yet
- * represented. Keep disabled for now.
- */
- status = "disabled";
+ regulator-name = "ppvar_litcpu_pwm";
pwms = <&pwm2 0 3337 0>;
pwm-supply = <&ppvar_sys>;
@@ -202,18 +207,28 @@
/* EC turns on w/ ap_core_en; always on for AP */
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <799065>;
- regulator-max-microvolt = <1303738>;
+ regulator-min-microvolt = <797743>;
+ regulator-max-microvolt = <1307837>;
};
- ppvar_gpu: ppvar-gpu {
+ ppvar_litcpu: ppvar-litcpu {
+ compatible = "vctrl-regulator";
+ regulator-name = "ppvar_litcpu";
+
+ regulator-min-microvolt = <797743>;
+ regulator-max-microvolt = <1307837>;
+
+ ctrl-supply = <&ppvar_litcpu_pwm>;
+ ctrl-voltage-range = <797743 1307837>;
+
+ regulator-settling-time-up-us = <384>;
+ min-slew-down-rate = <225>;
+ ovp-threshold-percent = <16>;
+ };
+
+ ppvar_gpu_pwm: ppvar-gpu-pwm {
compatible = "pwm-regulator";
- regulator-name = "ppvar_gpu";
- /*
- * OVP circuit requires special handling which is not yet
- * represented. Keep disabled for now.
- */
- status = "disabled";
+ regulator-name = "ppvar_gpu_pwm";
pwms = <&pwm0 0 3337 0>;
pwm-supply = <&ppvar_sys>;
@@ -223,18 +238,28 @@
/* EC turns on w/ ap_core_en; always on for AP */
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <785782>;
- regulator-max-microvolt = <1217729>;
+ regulator-min-microvolt = <786384>;
+ regulator-max-microvolt = <1217747>;
};
- ppvar_centerlogic: ppvar-centerlogic {
+ ppvar_gpu: ppvar-gpu {
+ compatible = "vctrl-regulator";
+ regulator-name = "ppvar_gpu";
+
+ regulator-min-microvolt = <786384>;
+ regulator-max-microvolt = <1217747>;
+
+ ctrl-supply = <&ppvar_gpu_pwm>;
+ ctrl-voltage-range = <786384 1217747>;
+
+ regulator-settling-time-up-us = <390>;
+ min-slew-down-rate = <225>;
+ ovp-threshold-percent = <16>;
+ };
+
+ ppvar_centerlogic_pwm: ppvar-centerlogic-pwm {
compatible = "pwm-regulator";
- regulator-name = "ppvar_centerlogic";
- /*
- * OVP circuit requires special handling which is not yet
- * represented. Keep disabled for now.
- */
- status = "disabled";
+ regulator-name = "ppvar_centerlogic_pwm";
pwms = <&pwm3 0 3337 0>;
pwm-supply = <&ppvar_sys>;
@@ -244,8 +269,23 @@
/* EC turns on w/ ppvar_centerlogic_en; always on for AP */
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <800069>;
- regulator-max-microvolt = <1049692>;
+ regulator-min-microvolt = <799434>;
+ regulator-max-microvolt = <1049925>;
+ };
+
+ ppvar_centerlogic: ppvar-centerlogic {
+ compatible = "vctrl-regulator";
+ regulator-name = "ppvar_centerlogic";
+
+ regulator-min-microvolt = <799434>;
+ regulator-max-microvolt = <1049925>;
+
+ ctrl-supply = <&ppvar_centerlogic_pwm>;
+ ctrl-voltage-range = <799434 1049925>;
+
+ regulator-settling-time-up-us = <378>;
+ min-slew-down-rate = <225>;
+ ovp-threshold-percent = <16>;
};
/* Schematics call this PPVAR even though it's fixed */
@@ -555,6 +595,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&ppvar_gpu>;
+ status = "okay";
+};
+
ap_i2c_mic: &i2c1 {
status = "okay";
@@ -567,12 +612,7 @@ ap_i2c_mic: &i2c1 {
headsetcodec: rt5514@57 {
compatible = "realtek,rt5514";
reg = <0x57>;
- interrupt-parent = <&gpio1>;
- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&mic_int>;
- realtek,dmic-init-delay = <20>;
- wakeup-source;
+ realtek,dmic-init-delay-ms = <20>;
};
};
@@ -781,9 +821,13 @@ ap_i2c_audio: &i2c8 {
wacky_spi_audio: spi2@0 {
compatible = "realtek,rt5514";
reg = <0>;
-
+ interrupt-parent = <&gpio1>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mic_int>;
/* May run faster once verified. */
spi-max-frequency = <10000000>;
+ wakeup-source;
};
};
@@ -1031,7 +1075,7 @@ ap_i2c_audio: &i2c8 {
* hurt and dw_mmc will ignore it. We make sure to disable
* the pull though so we don't burn needless power.
*/
- sdmmc_cd: sdmcc-cd {
+ sdmmc_cd: sdmmc-cd {
rockchip,pins =
<0 7 RK_FUNC_1 &pcfg_pull_none>;
};
diff --git a/dts/src/arm64/rockchip/rk3399-op1-opp.dtsi b/dts/src/arm64/rockchip/rk3399-op1-opp.dtsi
index be7fe635f7..d8a120f945 100644
--- a/dts/src/arm64/rockchip/rk3399-op1-opp.dtsi
+++ b/dts/src/arm64/rockchip/rk3399-op1-opp.dtsi
@@ -118,6 +118,35 @@
opp-microvolt = <1250000>;
};
};
+
+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <800000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <297000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <850000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <925000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1075000>;
+ };
+ };
};
&cpu_l0 {
@@ -143,3 +172,7 @@
&cpu_b1 {
operating-points-v2 = <&cluster1_opp>;
};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};
diff --git a/dts/src/arm64/rockchip/rk3399-opp.dtsi b/dts/src/arm64/rockchip/rk3399-opp.dtsi
index c83460db13..81617bcf25 100644
--- a/dts/src/arm64/rockchip/rk3399-opp.dtsi
+++ b/dts/src/arm64/rockchip/rk3399-opp.dtsi
@@ -110,6 +110,35 @@
opp-microvolt = <1200000>;
};
};
+
+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <800000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <297000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <925000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1100000>;
+ };
+ };
};
&cpu_l0 {
@@ -135,3 +164,7 @@
&cpu_b1 {
operating-points-v2 = <&cluster1_opp>;
};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};
diff --git a/dts/src/arm64/rockchip/rk3399-puma-haikou.dts b/dts/src/arm64/rockchip/rk3399-puma-haikou.dts
new file mode 100644
index 0000000000..9a74860584
--- /dev/null
+++ b/dts/src/arm64/rockchip/rk3399-puma-haikou.dts
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3399-puma.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3399-Q7 SoM";
+ compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ pinctrl-0 = <&led_pin_module>, <&led_sd_haikou>;
+
+ sd-card-led {
+ label = "sd_card_led";
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_baseboard: vcc3v3-baseboard {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&i2c6 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&i2s0 {
+ status = "okay";
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&haikou_pin_hog>;
+
+ hog {
+ haikou_pin_hog: haikou-pin-hog {
+ rockchip,pins =
+ /* LID_BTN */
+ <RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BATLOW# */
+ <RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* SLP_BTN# */
+ <RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BIOS_DISABLE# */
+ <RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ led_sd_haikou: led-sd-gpio {
+ rockchip,pins =
+ <RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb2 {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins =
+ <RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ vmmc-supply = <&vcc3v3_baseboard>;
+ status = "okay";
+};
+
+&spi5 {
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&u2phy0_host {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
diff --git a/dts/src/arm64/rockchip/rk3399-puma.dtsi b/dts/src/arm64/rockchip/rk3399-puma.dtsi
new file mode 100644
index 0000000000..53ff3d191a
--- /dev/null
+++ b/dts/src/arm64/rockchip/rk3399-puma.dtsi
@@ -0,0 +1,547 @@
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pin_module>;
+
+ module-led {
+ label = "module_led";
+ gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+ };
+
+ /*
+ * Overwrite the opp-table for CPUB as this board uses a different
+ * regulator (FAN53555) that only allows 10mV steps and therefore
+ * can't reach the operation point target voltages from rk3399-opp.dtsi
+ */
+ /delete-node/ opp-table1;
+ cluster1_opp: opp-table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <830000>;
+ opp-suspend;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <880000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1030000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1992000000>;
+ opp-microvolt = <1230000>;
+ turbo-mode;
+ };
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc1v2_phy: vcc1v2-phy {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v2_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ enable-active-low;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 0>;
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ status = "okay";
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc1v2_phy>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x10>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ clock-frequency = <400000>;
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc5v0_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc1v8_pmu>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_ldo1: LDO_REG1 {
+ regulator-name = "vcc_ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_hdmi: LDO_REG2 {
+ regulator-name = "vcc1v8_hdmi";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG3 {
+ regulator-name = "vcc1v8_pmu";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sd: LDO_REG4 {
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_ldo5: LDO_REG5 {
+ regulator-name = "vcc_ldo5";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ldo6: LDO_REG6 {
+ regulator-name = "vcc_ldo6";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc0v9_hdmi: LDO_REG7 {
+ regulator-name = "vcc0v9_hdmi";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_efuse: LDO_REG8 {
+ regulator-name = "vcc_efuse";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_gpu: regulator@60 {
+ compatible = "fcs,fan53555";
+ reg = <0x60>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1230000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ fan: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ vdd_cpu_b: regulator@60 {
+ compatible = "fcs,fan53555";
+ reg = <0x60>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1230000>;
+ regulator-ramp-delay = <1000>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&io_domains {
+ status = "okay";
+ bt656-supply = <&vcc_1v8>;
+ audio-supply = <&vcc_1v8>;
+ sdmmc-supply = <&vcc_sd>;
+ gpio1830-supply = <&vcc_1v8>;
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmu1830-supply = <&vcc_1v8>;
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pinctrl {
+ i2c8 {
+ i2c8_xfer_a: i2c8-xfer {
+ rockchip,pins =
+ <RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
+ <RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ led_pin_module: led-module-gpio {
+ rockchip,pins =
+ <RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins =
+ <RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ vqmmc = <&vcc_sd>;
+};
+
+&spi1 {
+ status = "okay";
+
+ norflash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/dts/src/arm64/rockchip/rk3399-sapphire-excavator.dts b/dts/src/arm64/rockchip/rk3399-sapphire-excavator.dts
new file mode 100644
index 0000000000..b7bd88fb3a
--- /dev/null
+++ b/dts/src/arm64/rockchip/rk3399-sapphire-excavator.dts
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "rk3399-sapphire.dtsi"
+
+/ {
+ model = "Excavator-RK3399 Board";
+ compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <100000>;
+ };
+
+ button-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <300000>;
+ };
+
+ back {
+ label = "Back";
+ linux,code = <KEY_BACK>;
+ press-threshold-microvolt = <985000>;
+ };
+
+ menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <1314000>;
+ };
+ };
+
+ edp_panel: edp-panel {
+ compatible ="lg,lp079qx1-sp0v", "simple-panel";
+ backlight = <&backlight>;
+ enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_panel_reset>;
+ power-supply = <&vcc3v3_s0>;
+
+ ports {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&edp_out_panel>;
+ };
+ };
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ linux,input-type = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_btn>;
+ wakeup-source;
+ };
+ };
+
+ rt5651-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "realtek,rt5651-codec";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Mic Jack", "MICBIAS1",
+ "IN1P", "Mic Jack",
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&rt5651>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&backlight {
+ enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&edp {
+ status = "okay";
+
+ ports {
+ edp_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp_out_panel: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-rising-time-ns = <300>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+
+ rt5651: rt5651@1a {
+ compatible = "rockchip,rt5651";
+ reg = <0x1a>;
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
+ clock-names = "mclk";
+ hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
+ spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2c4 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ accelerometer@68 {
+ compatible = "invensense,mpu6500";
+ reg = <0x68>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
+&i2s0 {
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&i2s2 {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&pinctrl {
+ buttons {
+ pwr_btn: pwr-btn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ lcd-panel {
+ lcd_panel_reset: lcd-panel-reset {
+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&spdif {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/rockchip/rk3399-sapphire.dtsi b/dts/src/arm64/rockchip/rk3399-sapphire.dtsi
new file mode 100644
index 0000000000..6c30bb0221
--- /dev/null
+++ b/dts/src/arm64/rockchip/rk3399-sapphire.dtsi
@@ -0,0 +1,644 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "dt-bindings/pwm/pwm.h"
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23
+ 24 25 26 27 28 29 30 31
+ 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ default-brightness-level = <200>;
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc1v8_pmu>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG1 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_tp: LDO_REG2 {
+ regulator-name = "vcc3v0_tp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG3 {
+ regulator-name = "vcc1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-name = "vcc_sdio";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-name = "vcca1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ vin-supply = <&vcc_sys>;
+ };
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ bt656-supply = <&vcc_3v0>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vcc_sdio>;
+ gpio1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+ assigned-clock-rates = <100000000>;
+ ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pmic_dvs2: pmic-dvs2 {
+ rockchip,pins =
+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ vsel1_gpio: vsel1-gpio {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ vsel2_gpio: vsel2-gpio {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins =
+ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ keep-power-in-suspend;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ clock-frequency = <50000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <50000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ clock-frequency = <150000000>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ vqmmc-supply = <&vcc_sdio>;
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/dts/src/arm64/rockchip/rk3399.dtsi b/dts/src/arm64/rockchip/rk3399.dtsi
index 69c56f7316..d79e9b3265 100644
--- a/dts/src/arm64/rockchip/rk3399.dtsi
+++ b/dts/src/arm64/rockchip/rk3399.dtsi
@@ -110,6 +110,7 @@
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
+ dynamic-power-coefficient = <100>;
};
cpu_l1: cpu@1 {
@@ -118,6 +119,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ dynamic-power-coefficient = <100>;
};
cpu_l2: cpu@2 {
@@ -126,6 +128,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ dynamic-power-coefficient = <100>;
};
cpu_l3: cpu@3 {
@@ -134,6 +137,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ dynamic-power-coefficient = <100>;
};
cpu_b0: cpu@100 {
@@ -143,6 +147,7 @@
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
+ dynamic-power-coefficient = <436>;
};
cpu_b1: cpu@101 {
@@ -151,9 +156,15 @@
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ dynamic-power-coefficient = <436>;
};
};
+ display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vopl_out>, <&vopb_out>;
+ };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
@@ -238,8 +249,10 @@
linux,pci-domain = <0>;
max-link-speed = <1>;
msi-map = <0x0 &its 0x0 0x1000>;
- phys = <&pcie_phy>;
- phy-names = "pcie-phy";
+ phys = <&pcie_phy 0>, <&pcie_phy 1>,
+ <&pcie_phy 2>, <&pcie_phy 3>;
+ phy-names = "pcie-phy-0", "pcie-phy-1",
+ "pcie-phy-2", "pcie-phy-3";
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
@@ -287,6 +300,7 @@
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
resets = <&cru SRST_SDIO0>;
reset-names = "reset";
status = "disabled";
@@ -400,6 +414,7 @@
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
status = "disabled";
};
};
@@ -427,6 +442,7 @@
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
status = "disabled";
};
};
@@ -676,6 +692,7 @@
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -948,6 +965,10 @@
};
/* These power domains are grouped by VD_LOGIC */
+ pd_edp@RK3399_PD_EDP {
+ reg = <RK3399_PD_EDP>;
+ clocks = <&cru PCLK_EDP_CTRL>;
+ };
pd_emmc@RK3399_PD_EMMC {
reg = <RK3399_PD_EMMC>;
clocks = <&cru ACLK_EMMC>;
@@ -965,6 +986,11 @@
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sd>;
};
+ pd_sdioaudio@RK3399_PD_SDIOAUDIO {
+ reg = <RK3399_PD_SDIOAUDIO>;
+ clocks = <&cru HCLK_SDIO>;
+ pm_qos = <&qos_sdioaudio>;
+ };
pd_vio@RK3399_PD_VIO {
reg = <RK3399_PD_VIO>;
#address-cells = <1>;
@@ -1151,6 +1177,33 @@
status = "disabled";
};
+ vpu_mmu: iommu@ff650800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff650800 0x0 0x40>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vpu_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vdec_mmu: iommu@ff660480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdec_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@ff670800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff670800 0x0 0x40>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
efuse0: efuse@ff690000 {
compatible = "rockchip,rk3399-efuse";
reg = <0x0 0xff690000 0x0 0x80>;
@@ -1295,7 +1348,7 @@
compatible = "rockchip,rk3399-pcie-phy";
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
- #phy-cells = <0>;
+ #phy-cells = <1>;
resets = <&cru SRST_PCIEPHY>;
reset-names = "phy";
status = "disabled";
@@ -1385,6 +1438,7 @@
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
pinctrl-names = "default";
pinctrl-0 = <&spdif_bus>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
@@ -1399,6 +1453,7 @@
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_8ch_bus>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
@@ -1412,6 +1467,7 @@
clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_bus>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
@@ -1423,6 +1479,224 @@
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
+ status = "disabled";
+ };
+
+ vopl: vop@ff8f0000 {
+ compatible = "rockchip,rk3399-vop-lit";
+ reg = <0x0 0xff8f0000 0x0 0x3efc>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ assigned-clock-rates = <400000000>, <100000000>;
+ clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ iommus = <&vopl_mmu>;
+ power-domains = <&power RK3399_PD_VOPL>;
+ resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "disabled";
+
+ vopl_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vopl_out_mipi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
+
+ vopl_out_edp: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&edp_in_vopl>;
+ };
+
+ vopl_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi_in_vopl>;
+ };
+ };
+ };
+
+ vopl_mmu: iommu@ff8f3f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff8f3f00 0x0 0x100>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vopl_mmu";
+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_VOPL>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vopb: vop@ff900000 {
+ compatible = "rockchip,rk3399-vop-big";
+ reg = <0x0 0xff900000 0x0 0x3efc>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+ assigned-clock-rates = <400000000>, <100000000>;
+ clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ iommus = <&vopb_mmu>;
+ power-domains = <&power RK3399_PD_VOPB>;
+ resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "disabled";
+
+ vopb_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vopb_out_edp: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&edp_in_vopb>;
+ };
+
+ vopb_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
+
+ vopb_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi_in_vopb>;
+ };
+ };
+ };
+
+ vopb_mmu: iommu@ff903f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff903f00 0x0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vopb_mmu";
+ clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_VOPB>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ isp0_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp0_mmu";
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ isp1_mmu: iommu@ff924000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp1_mmu";
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ hdmi: hdmi@ff940000 {
+ compatible = "rockchip,rk3399-dw-hdmi";
+ reg = <0x0 0xff940000 0x0 0x20000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
+ clock-names = "iahb", "isfr", "vpll", "grf";
+ power-domains = <&power RK3399_PD_HDCP>;
+ reg-io-width = <4>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_hdmi>;
+ };
+ hdmi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_hdmi>;
+ };
+ };
+ };
+ };
+
+ mipi_dsi: mipi@ff960000 {
+ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x0 0xff960000 0x0 0x8000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+ <&cru SCLK_DPHY_TX0_CFG>;
+ clock-names = "ref", "pclk", "phy_cfg";
+ power-domains = <&power RK3399_PD_VIO>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
+ edp: edp@ff970000 {
+ compatible = "rockchip,rk3399-edp";
+ reg = <0x0 0xff970000 0x0 0x8000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+ power-domains = <&power RK3399_PD_EDP>;
+ resets = <&cru SRST_P_EDP_CTRL>;
+ reset-names = "dp";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_edp>;
+ };
+
+ edp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_edp>;
+ };
+ };
+ };
+ };
+
+ gpu: gpu@ff9a0000 {
+ compatible = "rockchip,rk3399-mali", "arm,mali-t860";
+ reg = <0x0 0xff9a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "gpu", "job", "mmu";
+ clocks = <&cru ACLK_GPU>;
+ power-domains = <&power RK3399_PD_GPU>;
status = "disabled";
};
@@ -1786,7 +2060,7 @@
<4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
};
- sdmmc_cd: sdmcc-cd {
+ sdmmc_cd: sdmmc-cd {
rockchip,pins =
<0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
};
@@ -2090,16 +2364,6 @@
};
pcie {
- pcie_clkreqn: pci-clkreqn {
- rockchip,pins =
- <2 26 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- pcie_clkreqnb: pci-clkreqnb {
- rockchip,pins =
- <4 24 RK_FUNC_1 &pcfg_pull_none>;
- };
-
pcie_clkreqn_cpm: pci-clkreqn-cpm {
rockchip,pins =
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/dts/src/arm64/socionext/uniphier-ld11-global.dts b/dts/src/arm64/socionext/uniphier-ld11-global.dts
index 115357018e..2452b2243f 100644
--- a/dts/src/arm64/socionext/uniphier-ld11-global.dts
+++ b/dts/src/arm64/socionext/uniphier-ld11-global.dts
@@ -9,7 +9,7 @@
*/
/dts-v1/;
-/include/ "uniphier-ld11.dtsi"
+#include "uniphier-ld11.dtsi"
/ {
model = "UniPhier LD11 Global Board (REF_LD11_GP)";
@@ -68,3 +68,7 @@
&usb2 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
diff --git a/dts/src/arm64/socionext/uniphier-ld11-ref.dts b/dts/src/arm64/socionext/uniphier-ld11-ref.dts
index cc8ebe34c2..ffb473ad2e 100644
--- a/dts/src/arm64/socionext/uniphier-ld11-ref.dts
+++ b/dts/src/arm64/socionext/uniphier-ld11-ref.dts
@@ -8,9 +8,9 @@
*/
/dts-v1/;
-/include/ "uniphier-ld11.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld11.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD11 Reference Board";
diff --git a/dts/src/arm64/socionext/uniphier-ld11.dtsi b/dts/src/arm64/socionext/uniphier-ld11.dtsi
index bdce5b89ba..ee4aff53a5 100644
--- a/dts/src/arm64/socionext/uniphier-ld11.dtsi
+++ b/dts/src/arm64/socionext/uniphier-ld11.dtsi
@@ -150,6 +150,17 @@
clocks = <&peri_clk 3>;
};
+ adamv@57920000 {
+ compatible = "socionext,uniphier-ld11-adamv",
+ "simple-mfd", "syscon";
+ reg = <0x57920000 0x1000>;
+
+ adamv_rst: reset {
+ compatible = "socionext,uniphier-ld11-adamv-reset";
+ #reset-cells = <1>;
+ };
+ };
+
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
@@ -344,6 +355,13 @@
};
};
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-ld11-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
gic: interrupt-controller@5fe00000 {
compatible = "arm,gic-v3";
reg = <0x5fe00000 0x10000>, /* GICD */
@@ -367,8 +385,23 @@
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
+
+ watchdog {
+ compatible = "socionext,uniphier-wdt";
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
diff --git a/dts/src/arm64/socionext/uniphier-ld20-global.dts b/dts/src/arm64/socionext/uniphier-ld20-global.dts
index 9f620d4101..fc2bc9d75d 100644
--- a/dts/src/arm64/socionext/uniphier-ld20-global.dts
+++ b/dts/src/arm64/socionext/uniphier-ld20-global.dts
@@ -9,7 +9,7 @@
*/
/dts-v1/;
-/include/ "uniphier-ld20.dtsi"
+#include "uniphier-ld20.dtsi"
/ {
model = "UniPhier LD20 Global Board (REF_LD20_GP)";
@@ -50,3 +50,7 @@
&i2c0 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
diff --git a/dts/src/arm64/socionext/uniphier-ld20-ref.dts b/dts/src/arm64/socionext/uniphier-ld20-ref.dts
index 494166aee2..1ca0c8620d 100644
--- a/dts/src/arm64/socionext/uniphier-ld20-ref.dts
+++ b/dts/src/arm64/socionext/uniphier-ld20-ref.dts
@@ -8,9 +8,9 @@
*/
/dts-v1/;
-/include/ "uniphier-ld20.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld20.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD20 Reference Board";
diff --git a/dts/src/arm64/socionext/uniphier-ld20.dtsi b/dts/src/arm64/socionext/uniphier-ld20.dtsi
index de1e753628..a29c279b6e 100644
--- a/dts/src/arm64/socionext/uniphier-ld20.dtsi
+++ b/dts/src/arm64/socionext/uniphier-ld20.dtsi
@@ -219,6 +219,17 @@
clocks = <&peri_clk 3>;
};
+ adamv@57920000 {
+ compatible = "socionext,uniphier-ld20-adamv",
+ "simple-mfd", "syscon";
+ reg = <0x57920000 0x1000>;
+
+ adamv_rst: reset {
+ compatible = "socionext,uniphier-ld20-adamv-reset";
+ #reset-cells = <1>;
+ };
+ };
+
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
@@ -309,7 +320,7 @@
sdctrl@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
+ reg = <0x59810000 0x400>;
sd_clk: clock {
compatible = "socionext,uniphier-ld20-sd-clock";
@@ -365,6 +376,13 @@
};
};
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-ld20-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
gic: interrupt-controller@5fe00000 {
compatible = "arm,gic-v3";
reg = <0x5fe00000 0x10000>, /* GICD */
@@ -388,8 +406,23 @@
compatible = "socionext,uniphier-ld20-reset";
#reset-cells = <1>;
};
+
+ watchdog {
+ compatible = "socionext,uniphier-wdt";
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
diff --git a/dts/src/arm64/socionext/uniphier-pinctrl.dtsi b/dts/src/arm64/socionext/uniphier-pinctrl.dtsi
index 246f35ffb6..9caabbb8ba 100644
--- a/dts/src/arm64/socionext/uniphier-pinctrl.dtsi
+++ b/dts/src/arm64/socionext/uniphier-pinctrl.dtsi
@@ -1,141 +1 @@
-/*
- * Device Tree Source for UniPhier SoCs default pinctrl settings
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-&pinctrl {
- pinctrl_emmc: emmc_grp {
- groups = "emmc", "emmc_dat8";
- function = "emmc";
- };
-
- pinctrl_i2c0: i2c0_grp {
- groups = "i2c0";
- function = "i2c0";
- };
-
- pinctrl_i2c1: i2c1_grp {
- groups = "i2c1";
- function = "i2c1";
- };
-
- pinctrl_i2c2: i2c2_grp {
- groups = "i2c2";
- function = "i2c2";
- };
-
- pinctrl_i2c3: i2c3_grp {
- groups = "i2c3";
- function = "i2c3";
- };
-
- pinctrl_i2c4: i2c4_grp {
- groups = "i2c4";
- function = "i2c4";
- };
-
- pinctrl_nand: nand_grp {
- groups = "nand";
- function = "nand";
- };
-
- pinctrl_nand2cs: nand2cs_grp {
- groups = "nand", "nand_cs1";
- function = "nand";
- };
-
- pinctrl_sd: sd_grp {
- groups = "sd";
- function = "sd";
- };
-
- pinctrl_sd1: sd1_grp {
- groups = "sd1";
- function = "sd1";
- };
-
- pinctrl_system_bus: system_bus_grp {
- groups = "system_bus", "system_bus_cs1";
- function = "system_bus";
- };
-
- pinctrl_uart0: uart0_grp {
- groups = "uart0";
- function = "uart0";
- };
-
- pinctrl_uart1: uart1_grp {
- groups = "uart1";
- function = "uart1";
- };
-
- pinctrl_uart2: uart2_grp {
- groups = "uart2";
- function = "uart2";
- };
-
- pinctrl_uart3: uart3_grp {
- groups = "uart3";
- function = "uart3";
- };
-
- pinctrl_usb0: usb0_grp {
- groups = "usb0";
- function = "usb0";
- };
-
- pinctrl_usb1: usb1_grp {
- groups = "usb1";
- function = "usb1";
- };
-
- pinctrl_usb2: usb2_grp {
- groups = "usb2";
- function = "usb2";
- };
-
- pinctrl_usb3: usb3_grp {
- groups = "usb3";
- function = "usb3";
- };
-};
+#include <arm/uniphier-pinctrl.dtsi>
diff --git a/dts/src/arm64/socionext/uniphier-pxs3-ref.dts b/dts/src/arm64/socionext/uniphier-pxs3-ref.dts
new file mode 100644
index 0000000000..d65f746a3f
--- /dev/null
+++ b/dts/src/arm64/socionext/uniphier-pxs3-ref.dts
@@ -0,0 +1,62 @@
+/*
+ * Device Tree Source for UniPhier PXs3 Reference Board
+ *
+ * Copyright (C) 2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+#include "uniphier-pxs3.dtsi"
+#include "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier PXs3 Reference Board";
+ compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c6 = &i2c6;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0xa0000000>;
+ };
+};
+
+&ethsc {
+ interrupts = <0 52 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/socionext/uniphier-pxs3.dtsi b/dts/src/arm64/socionext/uniphier-pxs3.dtsi
new file mode 100644
index 0000000000..384729fa74
--- /dev/null
+++ b/dts/src/arm64/socionext/uniphier-pxs3.dtsi
@@ -0,0 +1,367 @@
+/*
+ * Device Tree Source for UniPhier PXs3 SoC
+ *
+ * Copyright (C) 2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/memreserve/ 0x80000000 0x02000000;
+
+/ {
+ compatible = "socionext,uniphier-pxs3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x000>;
+ clocks = <&sys_clk 33>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x001>;
+ clocks = <&sys_clk 33>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x002>;
+ clocks = <&sys_clk 33>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x003>;
+ clocks = <&sys_clk 33>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+ };
+
+ cluster0_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-666667000 {
+ opp-hz = /bits/ 64 <666667000>;
+ clock-latency-ns = <300>;
+ };
+ opp-866667000 {
+ opp-hz = /bits/ 64 <866667000>;
+ clock-latency-ns = <300>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 4>,
+ <1 14 4>,
+ <1 11 4>,
+ <1 10 4>;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
+
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&peri_clk 10>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59801000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ sdctrl@59810000 {
+ compatible = "socionext,uniphier-pxs3-sdctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x400>;
+
+ sd_clk: clock {
+ compatible = "socionext,uniphier-pxs3-sd-clock";
+ #clock-cells = <1>;
+ };
+
+ sd_rst: reset {
+ compatible = "socionext,uniphier-pxs3-sd-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-pxs3-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-pxs3-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-pxs3-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ emmc: sdhc@5a000000 {
+ compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
+ reg = <0x5a000000 0x400>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc>;
+ clocks = <&sys_clk 4>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ cdns,phy-input-delay-legacy = <4>;
+ cdns,phy-input-delay-mmc-highspeed = <2>;
+ cdns,phy-input-delay-mmc-ddr = <3>;
+ cdns,phy-dll-delay-sdclk = <21>;
+ cdns,phy-dll-delay-sdclk-hsmmc = <21>;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pxs3-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pxs3-pinctrl";
+ };
+ };
+
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pxs3-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gic: interrupt-controller@5fe00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x5fe00000 0x10000>, /* GICD */
+ <0x5fe80000 0x80000>; /* GICR */
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 4>;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-pxs3-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-pxs3-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-pxs3-reset";
+ #reset-cells = <1>;
+ };
+
+ watchdog {
+ compatible = "socionext,uniphier-wdt";
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ };
+ };
+};
+
+#include "uniphier-pinctrl.dtsi"
diff --git a/dts/src/arm64/socionext/uniphier-ref-daughter.dtsi b/dts/src/arm64/socionext/uniphier-ref-daughter.dtsi
index 7a1c29b558..e66d999d9f 100644
--- a/dts/src/arm64/socionext/uniphier-ref-daughter.dtsi
+++ b/dts/src/arm64/socionext/uniphier-ref-daughter.dtsi
@@ -1,16 +1 @@
-/*
- * Device Tree Source for UniPhier Reference Daughter Board
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-&i2c0 {
- eeprom@50 {
- compatible = "microchip,24lc128";
- reg = <0x50>;
- pagesize = <64>;
- };
-};
+#include <arm/uniphier-ref-daughter.dtsi>
diff --git a/dts/src/arm64/socionext/uniphier-support-card.dtsi b/dts/src/arm64/socionext/uniphier-support-card.dtsi
index 6c825f192e..28c5b4ed1d 100644
--- a/dts/src/arm64/socionext/uniphier-support-card.dtsi
+++ b/dts/src/arm64/socionext/uniphier-support-card.dtsi
@@ -1,34 +1 @@
-/*
- * Device Tree Source for UniPhier Support Card (Expansion Board)
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-&system_bus {
- status = "okay";
- ranges = <1 0x00000000 0x42000000 0x02000000>;
-
- support_card: support_card@1,1f00000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 1 0x01f00000 0x00100000>;
-
- ethsc: ethernet@0 {
- compatible = "smsc,lan9118", "smsc,lan9115";
- reg = <0x00000000 0x1000>;
- phy-mode = "mii";
- reg-io-width = <4>;
- };
-
- serialsc: uart@b0000 {
- compatible = "ns16550a";
- reg = <0x000b0000 0x20>;
- clock-frequency = <12288000>;
- reg-shift = <1>;
- };
- };
-};
+#include <arm/uniphier-support-card.dtsi>
diff --git a/dts/src/arm64/xilinx/zynqmp-ep108-clk.dtsi b/dts/src/arm64/xilinx/zynqmp-ep108-clk.dtsi
index cdc6a437dc..b87b8316f4 100644
--- a/dts/src/arm64/xilinx/zynqmp-ep108-clk.dtsi
+++ b/dts/src/arm64/xilinx/zynqmp-ep108-clk.dtsi
@@ -11,7 +11,7 @@
* the License, or (at your option) any later version.
*/
-&amba {
+/ {
misc_clk: misc_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -29,12 +29,60 @@
#clock-cells = <0>;
clock-frequency = <75000000>;
};
+
+ clk100: clk100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk600: clk600 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ };
};
&can0 {
clocks = <&misc_clk &misc_clk>;
};
+&can1 {
+ clocks = <&misc_clk &misc_clk>;
+};
+
+&fpd_dma_chan1 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan2 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan3 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan4 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan5 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan6 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan7 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan8 {
+ clocks = <&clk600>, <&clk100>;
+};
+
&gem0 {
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
};
diff --git a/dts/src/arm64/xilinx/zynqmp-ep108.dts b/dts/src/arm64/xilinx/zynqmp-ep108.dts
index ef1b9e573a..bf552674a8 100644
--- a/dts/src/arm64/xilinx/zynqmp-ep108.dts
+++ b/dts/src/arm64/xilinx/zynqmp-ep108.dts
@@ -13,13 +13,15 @@
/dts-v1/;
-/include/ "zynqmp.dtsi"
-/include/ "zynqmp-ep108-clk.dtsi"
+#include "zynqmp.dtsi"
+#include "zynqmp-ep108-clk.dtsi"
/ {
model = "ZynqMP EP108";
aliases {
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
serial0 = &uart0;
};
@@ -37,6 +39,10 @@
status = "okay";
};
+&can1 {
+ status = "okay";
+};
+
&gem0 {
status = "okay";
phy-handle = <&phy0>;
@@ -55,7 +61,7 @@
status = "okay";
clock-frequency = <400000>;
eeprom@54 {
- compatible = "at,24c64";
+ compatible = "atmel,24c64";
reg = <0x54>;
};
};
@@ -64,7 +70,7 @@
status = "okay";
clock-frequency = <400000>;
eeprom@55 {
- compatible = "at,24c64";
+ compatible = "atmel,24c64";
reg = <0x55>;
};
};
@@ -92,7 +98,7 @@
spi-max-frequency = <50000000>;
reg = <0>;
- spi0_flash0@00000000 {
+ spi0_flash0@0 {
label = "spi0_flash0";
reg = <0x0 0x100000>;
};
@@ -109,7 +115,7 @@
spi-max-frequency = <50000000>;
reg = <0>;
- spi1_flash0@00000000 {
+ spi1_flash0@0 {
label = "spi1_flash0";
reg = <0x0 0x100000>;
};
diff --git a/dts/src/arm64/xilinx/zynqmp.dtsi b/dts/src/arm64/xilinx/zynqmp.dtsi
index 54dc28351c..7665fbddff 100644
--- a/dts/src/arm64/xilinx/zynqmp.dtsi
+++ b/dts/src/arm64/xilinx/zynqmp.dtsi
@@ -20,33 +20,84 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
+ operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000000>;
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <600>;
+ min-residency-us = <10000>;
+ };
+ };
+ };
+
+ cpu_opp_table: cpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <1199999988>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <599999994>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <399999996>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <299999997>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
};
pmu {
@@ -119,6 +170,190 @@
rx-fifo-depth = <0x40>;
};
+ cci: cci@fd6e0000 {
+ compatible = "arm,cci-400";
+ reg = <0x0 0xfd6e0000 0x0 0x9000>;
+ ranges = <0x0 0x0 0xfd6e0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 123 4>,
+ <0 123 4>,
+ <0 123 4>,
+ <0 123 4>,
+ <0 123 4>;
+ };
+ };
+
+ /* GDMA */
+ fpd_dma_chan1: dma@fd500000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd500000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 124 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan2: dma@fd510000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd510000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 125 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan3: dma@fd520000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd520000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 126 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan4: dma@fd530000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd530000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 127 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan5: dma@fd540000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd540000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 128 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan6: dma@fd550000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd550000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 129 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan7: dma@fd560000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd560000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 130 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ };
+
+ fpd_dma_chan8: dma@fd570000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xfd570000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 131 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <128>;
+ };
+
+ /* LPDDMA default allows only secured access. inorder to enable
+ * These dma channels, Users should ensure that these dma
+ * Channels are allowed for non secure access.
+ */
+ lpd_dma_chan1: dma@ffa80000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffa80000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 77 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan2: dma@ffa90000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffa90000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 78 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan3: dma@ffaa0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffaa0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 79 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan4: dma@ffab0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffab0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 80 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan5: dma@ffac0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffac0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 81 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan6: dma@ffad0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffad0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 82 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan7: dma@ffae0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffae0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 83 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <64>;
+ };
+
+ lpd_dma_chan8: dma@ffaf0000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-dma-1.0";
+ reg = <0x0 0xffaf0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 84 4>;
+ clock-names = "clk_main", "clk_apb";
+ xlnx,bus-width = <64>;
+ };
+
gem0: ethernet@ff0b0000 {
compatible = "cdns,gem";
status = "disabled";
@@ -215,12 +450,9 @@
<0x0 0xfd480000 0x0 0x1000>,
<0x80 0x00000000 0x0 0x1000000>;
reg-names = "breg", "pcireg", "cfg";
- ranges = <0x02000000 0x00000000 0xe0000000 0x00000000
- 0xe0000000 0x00000000 0x10000000
- /* non-prefetchable memory */
- 0x43000000 0x00000006 0x00000000 0x00000006
- 0x00000000 0x00000002 0x00000000>;
- /* prefetchable memory */
+ ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
+ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
@@ -233,6 +465,16 @@
};
};
+ rtc: rtc@ffa60000 {
+ compatible = "xlnx,zynqmp-rtc";
+ status = "disabled";
+ reg = <0x0 0xffa60000 0x0 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 26 4>, <0 27 4>;
+ interrupt-names = "alarm", "sec";
+ calibration = <0x8000>;
+ };
+
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";
@@ -262,13 +504,14 @@
smmu: smmu@fd800000 {
compatible = "arm,mmu-500";
reg = <0x0 0xfd800000 0x0 0x20000>;
+ status = "disabled";
#global-interrupts = <1>;
interrupt-parent = <&gic>;
- interrupts = <0 157 4>,
- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
- <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
+ interrupts = <0 155 4>,
+ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
+ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
+ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
+ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
};
spi0: spi@ff040000 {
@@ -330,7 +573,7 @@
};
uart0: serial@ff000000 {
- compatible = "cdns,uart-r1p8";
+ compatible = "cdns,uart-r1p12", "xlnx,xuartps";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
@@ -339,7 +582,7 @@
};
uart1: serial@ff010000 {
- compatible = "cdns,uart-r1p8";
+ compatible = "cdns,uart-r1p12", "xlnx,xuartps";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
diff --git a/dts/src/arm64/zte/zx296718-evb.dts b/dts/src/arm64/zte/zx296718-evb.dts
index bb900d2bbc..cb2519ecd7 100644
--- a/dts/src/arm64/zte/zx296718-evb.dts
+++ b/dts/src/arm64/zte/zx296718-evb.dts
@@ -57,16 +57,28 @@
reg = <0x40000000 0x40000000>;
};
- sound0 {
- compatible = "simple-audio-card";
- simple-audio-card,name = "zx_snd_spdif0";
+ sound-spdif0 {
+ compatible = "audio-graph-card";
+ dais = <&spdif0_port>;
+ };
- simple-audio-card,cpu {
- sound-dai = <&spdif0>;
- };
+ sound-i2s0 {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_port>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&amplifier_pins>;
+ pa-gpios = <&bgpio4 0 GPIO_ACTIVE_HIGH>;
+ widgets = "Line", "Line Out Jack";
+ routing = "Amplifier", "LINEOUTL",
+ "Amplifier", "LINEOUTR",
+ "Line Out Jack", "Amplifier";
+ };
+};
- simple-audio-card,codec {
- sound-dai = <&hdmi>;
+&aud96p22 {
+ port {
+ aud96p22_endpoint: endpoint {
+ remote-endpoint = <&i2s0_endpoint>;
};
};
};
@@ -77,6 +89,36 @@
&hdmi {
status = "okay";
+
+ port {
+ hdmi_endpoint: endpoint {
+ remote-endpoint = <&spdif0_endpoint>;
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2s0 {
+ status = "okay";
+
+ i2s0_port: port {
+ i2s0_endpoint: endpoint {
+ remote-endpoint = <&aud96p22_endpoint>;
+ dai-format = "i2s";
+ frame-master;
+ bitclock-master;
+ };
+ };
+};
+
+&pmm {
+ amplifier_pins: amplifier {
+ pins = "TSI3_DATA";
+ function = "BGPIO";
+ };
};
&sd1 {
@@ -85,6 +127,16 @@
&spdif0 {
status = "okay";
+
+ spdif0_port: port {
+ spdif0_endpoint: endpoint {
+ remote-endpoint = <&hdmi_endpoint>;
+ };
+ };
+};
+
+&tvenc {
+ status = "okay";
};
&uart0 {
diff --git a/dts/src/arm64/zte/zx296718-pcbox.dts b/dts/src/arm64/zte/zx296718-pcbox.dts
new file mode 100644
index 0000000000..e02509f708
--- /dev/null
+++ b/dts/src/arm64/zte/zx296718-pcbox.dts
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * Copyright 2017 Linaro Ltd.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+#include "zx296718.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "ZTE ZX296718 PCBOX Board";
+ compatible = "zte,zx296718-pcbox", "zte,zx296718";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ a53_vdd0v9: regulator-a53 {
+ compatible = "pwm-regulator";
+ pwms = <&pwm 3 1250 PWM_POLARITY_INVERTED>;
+ regulator-name = "A53_VDD0V9";
+ regulator-min-microvolt = <855000>;
+ regulator-max-microvolt = <1183000>;
+ pwm-dutycycle-unit = <100>;
+ pwm-dutycycle-range = <0 100>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sound-spdif0 {
+ compatible = "audio-graph-card";
+ dais = <&spdif0_port>;
+ };
+
+ sound-i2s0 {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_port>;
+ };
+};
+
+&aud96p22 {
+ port {
+ aud96p22_endpoint: endpoint {
+ remote-endpoint = <&i2s0_endpoint>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&a53_vdd0v9>;
+};
+
+&emmc {
+ status = "okay";
+};
+
+&hdmi {
+ status = "disabled";
+
+ port {
+ hdmi_endpoint: endpoint {
+ remote-endpoint = <&spdif0_endpoint>;
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2s0 {
+ status = "okay";
+
+ i2s0_port: port {
+ i2s0_endpoint: endpoint {
+ remote-endpoint = <&aud96p22_endpoint>;
+ dai-format = "i2s";
+ frame-master;
+ bitclock-master;
+ };
+ };
+};
+
+&irdec {
+ status = "okay";
+};
+
+&pmm {
+ pwm3_pins: pwm3 {
+ pins = "KEY_ROW2";
+ function = "PWM";
+ };
+
+ vga_pins: vga {
+ pins = "KEY_COL1", "KEY_COL2", "VGA_HS", "VGA_VS";
+ function = "VGA";
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pins>;
+ status = "okay";
+};
+
+&sd0 {
+ status = "okay";
+};
+
+&sd1 {
+ status = "okay";
+};
+
+&spdif0 {
+ status = "okay";
+
+ spdif0_port: port {
+ spdif0_endpoint: endpoint {
+ remote-endpoint = <&hdmi_endpoint>;
+ };
+ };
+};
+
+&tvenc {
+ status = "disabled";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&vga {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vga_pins>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/zte/zx296718.dtsi b/dts/src/arm64/zte/zx296718.dtsi
index d83bf789c8..6eef647610 100644
--- a/dts/src/arm64/zte/zx296718.dtsi
+++ b/dts/src/arm64/zte/zx296718.dtsi
@@ -53,6 +53,13 @@
interrupt-parent = <&gic>;
aliases {
+ gpio0 = &bgpio0;
+ gpio1 = &bgpio1;
+ gpio2 = &bgpio2;
+ gpio3 = &bgpio3;
+ gpio4 = &bgpio4;
+ gpio5 = &bgpio5;
+ gpio6 = &bgpio6;
serial0 = &uart0;
};
@@ -120,26 +127,31 @@
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <866000>;
clock-latency-ns = <500000>;
};
opp-648000000 {
opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <866000>;
clock-latency-ns = <500000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <888000>;
clock-latency-ns = <500000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <898000>;
clock-latency-ns = <500000>;
};
opp-1188000000 {
opp-hz = /bits/ 64 <1188000000>;
+ opp-microvolt = <1015000>;
clock-latency-ns = <500000>;
};
};
@@ -283,11 +295,23 @@
compatible = "simple-bus";
ranges;
+ irdec: ir-decoder@111000 {
+ compatible = "zte,zx296718-irdec";
+ reg = <0x111000 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
+ iocfg: pin-controller@119000 {
+ compatible = "zte,zx296718-iocfg";
+ reg = <0x119000 0x1000>;
+ };
+
uart0: uart@11f000 {
compatible = "arm,pl011", "arm,primecell";
arm,primecell-periphid = <0x001feffe>;
@@ -311,7 +335,6 @@
clock-frequency = <50000000>;
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
clock-names = "biu", "ciu";
- num-slots = <1>;
max-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
@@ -336,7 +359,6 @@
clock-frequency = <167000000>;
clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
clock-names = "biu", "ciu";
- num-slots = <1>;
max-frequency = <167000000>;
cap-sdio-irq;
cap-sd-highspeed;
@@ -360,12 +382,109 @@
#clock-cells = <1>;
};
+ bgpio0: gpio@142d000 {
+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
+ reg = <0x142d000 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm 0 48 16>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ bgpio1: gpio@142d040 {
+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
+ reg = <0x142d040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm 0 80 16>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ bgpio2: gpio@142d080 {
+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
+ reg = <0x142d080 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm 0 80 3
+ &pmm 3 32 4
+ &pmm 7 83 9>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ bgpio3: gpio@142d0c0 {
+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
+ reg = <0x142d0c0 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm 0 92 16>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ bgpio4: gpio@142d100 {
+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
+ reg = <0x142d100 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm 0 108 12
+ &pmm 12 121 4>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ bgpio5: gpio@142d140 {
+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
+ reg = <0x142d140 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm 0 125 16>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ bgpio6: gpio@142d180 {
+ compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
+ reg = <0x142d180 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm 0 141 2>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
lsp1crm: clock-controller@1430000 {
compatible = "zte,zx296718-lsp1crm";
reg = <0x01430000 0x1000>;
#clock-cells = <1>;
};
+ pwm: pwm@1439000 {
+ compatible = "zte,zx296718-pwm";
+ reg = <0x1439000 0x1000>;
+ clocks = <&lsp1crm LSP1_PWM_PCLK>,
+ <&lsp1crm LSP1_PWM_WCLK>;
+ clock-names = "pclk", "wclk";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
vou: vou@1440000 {
compatible = "zte,zx296718-vou";
#address-cells = <1>;
@@ -387,6 +506,16 @@
"main_wclk", "aux_wclk";
};
+ vga: vga@8000 {
+ compatible = "zte,zx296718-vga";
+ reg = <0x8000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topcrm VGA_I2C_WCLK>;
+ clock-names = "i2c_wclk";
+ zte,vga-power-control = <&sysctrl 0x170 0xe0>;
+ status = "disabled";
+ };
+
hdmi: hdmi@c000 {
compatible = "zte,zx296718-hdmi";
reg = <0xc000 0x4000>;
@@ -413,6 +542,12 @@
#clock-cells = <1>;
};
+ pmm: pin-controller@1462000 {
+ compatible = "zte,zx296718-pmm";
+ reg = <0x1462000 0x1000>;
+ zte,auxiliary-controller = <&iocfg>;
+ };
+
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
@@ -445,6 +580,38 @@
#clock-cells = <1>;
};
+ i2s0: i2s@1482000 {
+ compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
+ reg = <0x01482000 0x1000>;
+ clocks = <&audiocrm AUDIO_I2S0_WCLK>,
+ <&audiocrm AUDIO_I2S0_PCLK>;
+ clock-names = "wclk", "pclk";
+ assigned-clocks = <&audiocrm I2S0_WCLK_MUX>;
+ assigned-clock-parents = <&topcrm AUDIO_99M>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma 22>, <&dma 23>;
+ dma-names = "tx", "rx";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@1486000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x01486000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&audiocrm AUDIO_I2C0_WCLK>;
+ clock-frequency = <1600000>;
+ status = "disabled";
+
+ aud96p22: codec@22 {
+ compatible = "zte,zx-aud96p22";
+ #sound-dai-cells = <0>;
+ reg = <0x22>;
+ };
+ };
+
spdif0: spdif@1488000 {
compatible = "zte,zx296702-spdif";
reg = <0x1488000 0x1000>;
diff --git a/dts/src/mips/ingenic/ci20.dts b/dts/src/mips/ingenic/ci20.dts
index fd138d9978..6c38184492 100644
--- a/dts/src/mips/ingenic/ci20.dts
+++ b/dts/src/mips/ingenic/ci20.dts
@@ -1,6 +1,7 @@
/dts-v1/;
#include "jz4780.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "img,ci20", "ingenic,jz4780";
@@ -21,6 +22,13 @@
reg = <0x0 0x10000000
0x30000000 0x30000000>;
};
+
+ eth0_power: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "eth0_power";
+ gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ };
};
&ext {
@@ -123,6 +131,29 @@
};
};
};
+
+ dm9000@6 {
+ compatible = "davicom,dm9000";
+ davicom,no-eeprom;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs6>;
+
+ reg = <6 0 1 /* addr */
+ 6 2 1>; /* data */
+
+ ingenic,nemc-tAS = <15>;
+ ingenic,nemc-tAH = <10>;
+ ingenic,nemc-tBP = <20>;
+ ingenic,nemc-tAW = <50>;
+ ingenic,nemc-tSTRV = <100>;
+
+ reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&eth0_power>;
+
+ interrupt-parent = <&gpe>;
+ interrupts = <19 4>;
+ };
};
&bch {
@@ -165,4 +196,10 @@
groups = "nemc-cs1";
bias-disable;
};
+
+ pins_nemc_cs6: nemc-cs6 {
+ function = "nemc-cs6";
+ groups = "nemc-cs6";
+ bias-disable;
+ };
};
diff --git a/dts/src/mips/ingenic/jz4780.dtsi b/dts/src/mips/ingenic/jz4780.dtsi
index 4853ef67b3..e906134eca 100644
--- a/dts/src/mips/ingenic/jz4780.dtsi
+++ b/dts/src/mips/ingenic/jz4780.dtsi
@@ -44,6 +44,17 @@
#clock-cells = <1>;
};
+ rtc_dev: rtc@10003000 {
+ compatible = "ingenic,jz4780-rtc";
+ reg = <0x10003000 0x4c>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <32>;
+
+ clocks = <&cgu JZ4780_CLK_RTCLK>;
+ clock-names = "rtc";
+ };
+
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4780-pinctrl";
reg = <0x10010000 0x600>;
diff --git a/dts/src/mips/ni/169445.dts b/dts/src/mips/ni/169445.dts
new file mode 100644
index 0000000000..5389ef46c4
--- /dev/null
+++ b/dts/src/mips/ni/169445.dts
@@ -0,0 +1,100 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ni,169445";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mti,mips14KEc";
+ clocks = <&baseclk>;
+ reg = <0>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ baseclk: baseclock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ cpu_intc: interrupt-controller {
+ #address-cells = <0>;
+ compatible = "mti,cpu-interrupt-controller";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ ahb@1f300000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1f300000 0x80FFF>;
+
+ gpio1: gpio@10 {
+ compatible = "ni,169445-nand-gpio";
+ reg = <0x10 0x4>;
+ reg-names = "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio2: gpio@14 {
+ compatible = "ni,169445-nand-gpio";
+ reg = <0x14 0x4>;
+ reg-names = "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ no-output;
+ };
+
+ nand@0 {
+ compatible = "gpio-control-nand";
+ nand-on-flash-bbt;
+ nand-ecc-mode = "soft_bch";
+ nand-ecc-step-size = <512>;
+ nand-ecc-strength = <4>;
+ reg = <0x0 4>;
+ gpios = <&gpio2 0 0>, /* rdy */
+ <&gpio1 1 0>, /* nce */
+ <&gpio1 2 0>, /* ale */
+ <&gpio1 3 0>, /* cle */
+ <&gpio1 4 0>; /* nwp */
+ };
+
+ serial@80000 {
+ compatible = "ns16550a";
+ reg = <0x80000 0x1000>;
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <6>;
+ clocks = <&baseclk>;
+ reg-shift = <0>;
+ };
+
+ ethernet@40000 {
+ compatible = "snps,dwmac-4.10a";
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <5>;
+ interrupt-names = "macirq";
+ reg = <0x40000 0x2000>;
+ clock-names = "stmmaceth", "pclk";
+ clocks = <&baseclk>, <&baseclk>;
+
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/dts/src/mips/ralink/mt7628a.dtsi b/dts/src/mips/ralink/mt7628a.dtsi
new file mode 100644
index 0000000000..9ff7e8faae
--- /dev/null
+++ b/dts/src/mips/ralink/mt7628a.dtsi
@@ -0,0 +1,126 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mt7628a-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mti,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ resetc: reset-controller {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@10000000 {
+ compatible = "palmbus";
+ reg = <0x10000000 0x200000>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc: system-controller@0 {
+ compatible = "ralink,mt7620a-sysc", "syscon";
+ reg = <0x0 0x100>;
+ };
+
+ intc: interrupt-controller@200 {
+ compatible = "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ resets = <&resetc 9>;
+ reset-names = "intc";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ ralink,intc-registers = <0x9c 0xa0
+ 0x6c 0xa4
+ 0x80 0x78>;
+ };
+
+ memory-controller@300 {
+ compatible = "ralink,mt7620a-memc";
+ reg = <0x300 0x100>;
+ };
+
+ uart0: uartlite@c00 {
+ compatible = "ns16550a";
+ reg = <0xc00 0x100>;
+
+ resets = <&resetc 12>;
+ reset-names = "uart0";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+
+ reg-shift = <2>;
+ };
+
+ uart1: uart1@d00 {
+ compatible = "ns16550a";
+ reg = <0xd00 0x100>;
+
+ resets = <&resetc 19>;
+ reset-names = "uart1";
+
+ interrupt-parent = <&intc>;
+ interrupts = <21>;
+
+ reg-shift = <2>;
+ };
+
+ uart2: uart2@e00 {
+ compatible = "ns16550a";
+ reg = <0xe00 0x100>;
+
+ resets = <&resetc 20>;
+ reset-names = "uart2";
+
+ interrupt-parent = <&intc>;
+ interrupts = <22>;
+
+ reg-shift = <2>;
+ };
+ };
+
+ usb_phy: usb-phy@10120000 {
+ compatible = "mediatek,mt7628-usbphy";
+ reg = <0x10120000 0x1000>;
+
+ #phy-cells = <0>;
+
+ ralink,sysctl = <&sysc>;
+ resets = <&resetc 22 &resetc 25>;
+ reset-names = "host", "device";
+ };
+
+ ehci@101c0000 {
+ compatible = "generic-ehci";
+ reg = <0x101c0000 0x1000>;
+
+ phys = <&usb_phy>;
+ phy-names = "usb";
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+ };
+};
diff --git a/dts/src/mips/ralink/omega2p.dts b/dts/src/mips/ralink/omega2p.dts
new file mode 100644
index 0000000000..5884fd48f5
--- /dev/null
+++ b/dts/src/mips/ralink/omega2p.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+/include/ "mt7628a.dtsi"
+
+/ {
+ compatible = "onion,omega2+", "ralink,mt7688a-soc", "ralink,mt7628a-soc";
+ model = "Onion Omega2+";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = &uart0;
+ };
+};
diff --git a/dts/src/mips/ralink/vocore2.dts b/dts/src/mips/ralink/vocore2.dts
new file mode 100644
index 0000000000..fa8a5f8f23
--- /dev/null
+++ b/dts/src/mips/ralink/vocore2.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "vocore,vocore2", "ralink,mt7628a-soc";
+ model = "VoCore2";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200";
+ stdout-path = &uart2;
+ };
+};
diff --git a/dts/src/nios2/3c120_devboard.dts b/dts/src/nios2/3c120_devboard.dts
index 31c51f9a2f..36ccdf0583 100644
--- a/dts/src/nios2/3c120_devboard.dts
+++ b/dts/src/nios2/3c120_devboard.dts
@@ -159,6 +159,7 @@
};
chosen {
- bootargs = "debug console=ttyJ0,115200";
+ bootargs = "debug earlycon console=ttyJ0,115200";
+ stdout-path = &jtag_uart;
};
};
diff --git a/dts/src/powerpc/fsp2.dts b/dts/src/powerpc/fsp2.dts
index 475953ada7..f10a64aeb8 100644
--- a/dts/src/powerpc/fsp2.dts
+++ b/dts/src/powerpc/fsp2.dts
@@ -52,6 +52,7 @@
clocks {
mmc_clk: mmc_clk {
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "mmc_clk";
};
@@ -359,20 +360,6 @@
interrupts = <31 0x4 15 0x84>;
};
- mmc0: sdhci@020c0000 {
- compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
- reg = <0x020c0000 0x20000>;
- reg-names = "mmc";
- interrupt-parent = <&UIC1_3>;
- interrupts = <21 0x4 22 0x4>;
- interrupt-names = "mmcirq";
- pinctrl-names = "default";
- pinctrl-0 = <>;
- clock-names = "mmc";
- clocks = <&mmc_clk>;
- };
-
plb6 {
compatible = "ibm,plb6";
#address-cells = <2>;
@@ -501,6 +488,24 @@
/*RXDE*/ 4 &UIC1_2 13 0x4>;
};
+ mmc0: mmc@20c0000 {
+ compatible = "st,sdhci-stih407", "st,sdhci";
+ reg = <0x020c0000 0x20000>;
+ reg-names = "mmc";
+ interrupts = <21 0x4>;
+ interrupt-parent = <&UIC1_3>;
+ interrupt-names = "mmcirq";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ clock-names = "mmc";
+ clocks = <&mmc_clk>;
+ bus-width = <4>;
+ non-removable;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ };
+
opb {
compatible = "ibm,opb";
#address-cells = <1>;