summaryrefslogtreecommitdiffstats
path: root/arch/arm/lib/pbl.lds.S
Commit message (Collapse)AuthorAgeFilesLines
* ARM64: add optional EFI stubAhmad Fatoum2024-03-051-0/+31
| | | | | | | | | | | While very recent binutils releases have dedicated efi-*-aarch targets, we may want to support older toolchains. For this reason, we import the kernel's EFI stub PE fakery, so the same barebox-dt-2nd.img may be loaded as if it were a "normal" or an EFI-stubbed kernel. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240304190038.3486881-87-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: lds: add support for a 2nd CSF areaMarco Felsch2023-10-181-0/+4
| | | | | | | | | | | | | | | | | | Extend the CSF area to be able two store two CSF slots. The 2nd CSF slot is required in case of FlexSPI HAB boot support. The first slot is used for the MMC-IVT + barebox-pbl; the 2nd slot is used for the FlexSPI-IVT + barebox-pbl. This is necessary because of the fact that the HAB ROM code requires that the IVT is signed as well. Make the 2nd CSF slot optional since early SRAM space is limited and 4K can make a difference here. Please check the documentation for a more detailed information about the i.MX8M image layout. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20231017145131.3069283-15-m.felsch@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: lds: introduce HAB_CSF_LEN define for the hab_csf sectionMarco Felsch2023-10-181-1/+3
| | | | | | | | | Introduce the HAB_CSF_LEN to make conditional size changes easier later on. No functional change. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20231017145131.3069283-14-m.felsch@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM64: cpu: support 64-bit stack top in ENTRY_FUNCTION_WITHSTACKAhmad Fatoum2023-06-061-3/+4
| | | | | | | | | | | | | ENTRY_FUNCTION_WITHSTACK was written with the naive assumption that there will always be some memory in the first 32-bit of the address space to be used as early stack. There are SoCs out there though with sole on-chip SRAM > 4G. Accommodate this by accepting full 64-bit stack pointers in ENTRY_FUNCTION_WITHSTACK. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230531175157.1442379-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Lior Weintraub <liorw@pliops.com>
* ARM64: asm: rewrite ENTRY_FUNCTION(_WITHSTACK) fully in assemblyAhmad Fatoum2022-10-261-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Recent episode with pointer authentication showed again that for platforms without __attribute__((naked)), we are better off writing the early header in assembly. We still want to keep the board specific entry points in C for ease of use, so we have ENTRY_FUNCTION_WITHSTACK generate two symbols: - A 32-bit stack top value that's placed in .rodata - An entry point with the normal C code, including stack-using prologues The new common assembly head code will access the stack pointer in a position-independent manner and set it up, before continuing with the C code. The barebox header is part of the common assembly head code ensuring it's not moved around due to compiler code generation. The common code will need access to board-specific entry point and stack top. The former is readily available as the alias __pbl_board_entry. The latter is a bit more complicated, as the symbol may not exist for boards not using the common header in a multi-image build. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221024065716.1215046-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: lds: define and use BAREBOX_RELOCATION_TABLEAhmad Fatoum2022-10-111-11/+1
| | | | | | | | | | The structure of the relocation table is one of the main differences between different architectures' linker scripts. Hoist it out for ARM into <asm/barebox.lds.h>. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221010061122.2084009-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* lds: move OUTPUT_FORMAT/ARCH definition into headerAhmad Fatoum2022-10-111-7/+3
| | | | | | | | | | In order to allow us having architecture-indepenent linker scripts, move the definition for the format and the architecture into the new <asm/barebox.lds.h> header file. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221010061122.2084009-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* lds: introduce <asm/barebox.lds.h>Ahmad Fatoum2022-10-111-1/+1
| | | | | | | | | | | | | | We have a separate linker script for each architecture and one more for PBL if supported. All linker scripts include <asm-generic/barebox.lds.h>. In future, we may want to use a linker script common to more than one architecture. Prepare for this by having each architecture define a <asm/barebox.lds.h>. Currently, these files contain little more than 1-2 #include directives, but this will change in later commits. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221010061122.2084009-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pbl: replace __piggydata_end with __image_endAhmad Fatoum2022-08-221-1/+0
| | | | | | | | | | | | | | | __piggydata_end and __image_end used to be synonyms before the addition of external firmware. Now that external firmware is located after __piggydata_end, code using it needs to be revisited. There's no reason to have code reference __piggydata_end. Either they want all the rest of the image, so they should use __image_end instead or they want just the piggy data, in which case they can read the data size embedded into the piggydata itself. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220818050447.2072932-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: add external firmware PBL supportAhmad Fatoum2022-08-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally, barebox embds firmware into the binary referencing it, which means that device tree blobs, RAM training code and e.g. TF-A for i.MX8M end up in the prebootloader, while, e.g. Freescale FMan microcode ends up in barebox proper. The only exception so far was barebox proper: When only the PBL fits in on-chip SRAM, barebox proper is chainloaded from the boot medium. To avoid TOCTOU attack, it's read fully into DRAM after setup and then a SHA256 is calculated and compared against the hash embedded in barebox PBL, which in a secure boot system would be trusted by virtue of the PBL as a whole being verified beforehand by the BootROM. Reuse this mechanism to support arbitrary firmware, which is now termed external firmware. Such firmware is placed beyond the piggydata (barebox proper) and only offset and hash are included in the prebootloader image. The new get_builtin_firmware_ext() is used to retrieve this external firmware after integrity verification with SHA256. This enables referencing firmware blobs from PBL that would bloat the size of the PBL beyond what can fit into on-chip SRAM, e.g. very big OP-TEE binaries. As users of get_builtin_firmware() didn't have to worry about TOCTOU so far, we panic when a firmware verification fails to ensure that we never load an OP-TEE that has been modified in-transit We can't include the OP-TEE binary in barebox proper, because we need to install it in EL3, but barebox proper on the i.MX8M runs as BL33 in a lower exception level. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220818050447.2072932-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: implement ENTRY_FUNCTION_WITHSTACKAhmad Fatoum2022-01-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The point of ENTRY_FUNCTION is to write the entry point in C. Due to lack of __naked on ARM64, the start of the entry point will have prologue using stack and it's not possible to set up the stack safely without branching into non-inline assembly[0]. On ARM32, where we got __naked, we have the potential for a different problem: If BootROM sets up stack for us and we branch to a naked function, which doesn't set up its own stack, compiler may decide to spill local variables overwriting instructions it had already run[1]. For code reuse between ARM and ARM64, it would be nice to use the same entry point structure for both. Currently, the only way is to write it in non-inline assembly using the ENTRY_PROC macro. This introduces another way: the ARM64 barebox header has enough space for 8 instructions of which 5 are unused (2 instructions compiler prologue + 1 instruction to jump after the header), we could place a stack setup routine there to avoid having to write a separate assembly file. For ARM32, we just call arm_setup_stack and branch out directly after, freeing board porters of the burden of getting it right. Add a new ENTRY_FUNCTION_WITHSTACK to realize this. [0]: 76bced6fe146 ("ARM: document arm_setup_stack() pitfalls"), [1]: b51b15ba1738 ("RISC-V: board-dt-2nd: move low level init into nonnaked function") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220114084227.308804-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm/lib: Replace license and copyright boilerplate by SPDX identifiersUwe Kleine-König2020-12-071-14/+3
| | | | | | | | | Converts the files that licensecheck can determine to be licensed under GPL-2.0-only or GPL-2.0-or-later and also convert the copyright statements to SPDX. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: remove references to CREDITSUwe Kleine-König2020-04-271-3/+0
| | | | | | | | The CREDITS file was removed from barebox in 2015 by commit 6570288f2d97 ("Remove the CREDITS file"). Remove references to it from several files. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: pbl: keep __image_end sectionLucas Stach2019-11-041-1/+1
| | | | | | | | | | Not all architectures are referencing the image_end section from code, in which case the linker is free to drop the section, which then messes up the calculation of the _barebox_image_size linker variable. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: always build sha256sum into pblRouven Czerwinski2019-08-071-0/+7
| | | | | | | | | Create a sha256sum of the compressed barebox image and always add it to the PBL. We also add a custom linker section for ARM, to retrieve the sha256sum for piggydata verification. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: lib: add CSF section between PBL and piggyRouven Czerwinski2019-08-071-0/+10
| | | | | | | | | | Signing on i.MX8MQ is done by signing only the PBL, since the DRAM is not available on early start and the SRAM is not big enough to contain the whole image. Reserve a CSF area between PBL and the piggydata, to ensure that the CSF area can be loaded into SRAM. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pbl multiimage: Allow to check image sizesSascha Hauer2019-03-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PBL images are often constrained in size by limitations exposed by the SoCs SRAM size or partition sizes on the boot device. So far we tried to configure these limits in Kconfig, but with PBL multi images and thus different limitations for the different supported images this no longer works. This patch has another approach for it: During build time make variables containing the relevant sizes for each image are created. These are: PBL_CODE_SIZE_$(symbol) PBL_MEMORY_SIZE_$(symbol) PBL_IMAGE_SIZE_$(symbol) PBL_CODE_SIZE_$(symbol) contains the pure code size of the PBL, it should be smaller than the available SRAM during boot. Normally the PBL's bss segment also needs to be in the initial SRAM, for this case PBL_MEMORY_SIZE_$(symbol) is the relevant variable. PBL_IMAGE_SIZE_$(symbol) contains the full size of the PBL image including the compressed payload (but without any image headers created later by SoC specific image tools). $(symbol) is a placeholder for the start symbol used for this PBL image, thus for the i.MX53 QSB with entry start_imx53_loco PBL_CODE_SIZE_start_imx53_loco will be created. The images/Makefile.* can use these variables directly to check sizes or specify the same variables with a "MAX_" prefix. So when images/Makefile.imx specifies MAX_PBL_CODE_SIZE_start_imx53_loco = 0x10000 then the build system will make sure that the PBL code for the QSB will not get bigger than 64KiB. Also included in this patch are the size restrictions for the i.MX8MQ images as an example how to use this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Revert "images: Drop unnecessary fix_size"Sascha Hauer2019-02-131-1/+1
| | | | | | | | | | | | | This reverts commit 5c0e16591d9471a345b77a41fde76de34f301f6b. The fix_size scripts is not necessary for newer ARM toolchains, it is however necessary for the older ARM toolchains (gcc-5 and older). The original reason to drop fix_size was that it doesn't work on MIPS. With this patch we add the -i flag so that we ignore unknown images and can succesfully build MIPS images. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: Drop unnecessary fix_sizeSascha Hauer2019-01-161-1/+1
| | | | | | | | Now that we compile the compressed binary into the decompressor we no longer need fix_size but can use the linker to fill in the image size into the binary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: images: use piggydataSascha Hauer2018-12-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The way we assemble the multi images on ARM is rather complicated and error prone. We currently cat the compressed barebox image behind the PBL executable and need some magic to obtain the size of the payload and also have to do tricks to reliably get a pointer to the compressed image. This patch switches over to compile the compressed payload into the PBL image itself which has proven to work for the single PBL case and for the ARM Linux Kernel aswell. The goal is to unify the single PBL and the multi PBL cases together in the future to get an easier startup path for ARM. This patch has been tested on the i.MX53 QSB, i.MX53 Vincell, Beaglebone black (both MLO and 2nd stage) and a Phytec phyFLEX i.MX6 board. SoCFPGA Arria10 has also be changed slightly with this patch. We used to generate a single image (barebox-socfpga-achilles.img) which was used as xload image and full image. We now instead generate two images: barebox-socfpga-achilles-xload.img and barebox-socfpga-achilles.img, the former loaded by the ROM and the latter loaded by the xload image. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Multi PBL: Fix image calculation for certain toolchainsSascha Hauer2018-09-171-1/+1
| | | | | | | | | | | | | The current way to calculate the compressed image position works with the OSELAS toolchains, but not with the Debian/Ubuntu toolchains. For these toolchains &image_end_marker already returns the correct address, adding global_variable_offset() to it is wrong. The solution seems to be to put the image_end_marker into a different object file so that the compiler cannot play any tricks to resolve the address internally in the object file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: fix pbl linker script for aarch64Sascha Hauer2018-03-231-0/+9
| | | | | | | Fix output format for aarch64. Also, relocation fixup symbols are in rela section rather than rel section. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: move away from ld_varSascha Hauer2018-03-211-13/+9
| | | | | | | | | | | | | | The ld_var solves the issue that when compiled with -pie the linker provided variables are all 0x0. This mechanism however refuses to compile with aarch64 support. This patch replaces the ld_var mechanism with a nice little trick learned from U-Boot: Instead of using linker provided variables directly with "__bss_start = ." we put a zero size array into a separate section and use the address of that array instead of the linker variable. This properly works before relocation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: scroll past image end without ld_varSascha Hauer2018-03-211-3/+2
| | | | | | | | | ld_var is going to be removed, cope without it. In the PBL image we want to get the location after the binary to the place where the compressed image is located. To do this Put a variable at the very end of the binary, get it's location and add an offset. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sizes.h: move include/sizes.h to include/linux/sizes.hMasahiro Yamada2015-01-081-1/+1
| | | | | | | | | | | | | | This file originates in Linux. Linux has it under include/linux/ directory since commit dccd2304cc90. Let's move it to the same place as well in barebox. This commit was generated by the following commands: find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:' git mv include/sizes.h include/linux/ Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Add support for metadata in barebox imagesSascha Hauer2014-08-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's often useful to get some information about a barebox image before starting or flashing it. This patch introduces barebox Image MetaData (IMD). When enabled a barebox image will contain a list of tags containing the desired information. We have tags for: - the barebox release (2014.07.0-00160-g035de50-dirty) - the build timestamp (#741 Mon Jul 28 15:08:54 CEST 2014) - the board model the image is intended for - the device tree toplevel compatible property Also there is an additional generic key-value store which stores parameters for which no dedicated tag exists. In this patch it is used for the memory size an image supports. Since there is no fixed offset in a barebox image which can be used for storing the information, the metadata is stored somewhere in the image and found by iterating over the image. This works for most image types, but obviously not for SoC images which are encoded or encrypted in some way. There is a 'imd' tool compiled from the same sources for barebox, for the compile host and for the target, so the metadata information is available whereever needed. For device tree boards the model and of_compatible tags are automatically generated. Example output of the imd tool for a Phytec phyFLEX image: build: #889 Wed Jul 30 16:08:54 CEST 2014 release: 2014.07.0-00167-g6b2070d-dirty parameter: memsize=1024 of_compatible: phytec,imx6x-pbab01 phytec,imx6dl-pfla02 fsl,imx6dl model: Phytec phyFLEX-i.MX6 Duallite Carrier-Board Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: remove address of the Free Software FoundationAntony Pavlov2014-06-111-5/+0
| | | | | | | | | | | | | | | | | | The FSF address has changed; The FSF site says that address is Free Software Foundation 51 Franklin Street, Fifth Floor Boston, MA 02110-1301 USA (see http://www.fsf.org/about/contact/) Instead of updating it each time the address changes, just drop it completely treewide. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Load PBL into SRAMDavid Vincent2014-02-091-0/+1
| | | | | | | | | | This allows to load all the lowlevel init code, including the uncompressor, inside SRAM and not just the bare init part. This is useful when pbl is used as a first-stage bootloader but is loaded by an external firmware. Signed-off-by: David Vincent <freesilicon@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Fix image size calculation for CONFIG_PBL_RELOCATABLESascha Hauer2014-01-231-8/+9
| | | | | | TEXT_BASE - SZ_2M is only used for non relocable pbl images. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Add image end sectionSascha Hauer2013-06-261-1/+7
| | | | | | | | | | | In the upcoming multi image build process we will cat images together. To find the concatenated image we need to reliably find the end of the current binary. This adds a dummy section at the end of a pbl binary. Its only purpose is to mark the end of the image. The multi image patches will add something to this section so that it doesn't get discarded by the linker. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: pbl: move linker script to libSascha Hauer2013-06-261-0/+91
Since the pbl linker script can be reused by the upcoming multi image build process move it to a common place. Also remove ENTRY() from the linker script and instead add the -e option to the linker. This makes the entrypoint configurable. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-26 20:02:22 +0000