summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-tegra
Commit message (Collapse)AuthorAgeFilesLines
* ARM: Cleanup stack offset cargo cultSascha Hauer2019-09-091-1/+1
| | | | | | | | | Most callers of arm_setup_stack substract a fixed offset of 8, 12 or 16 bytes from the stack top. This is unnecessary as on ARM we have a stack that decrements before storing values. Substracting this offset probably goes back to the U-Boot version we forked from. Stop this now. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: return positive offset in get_runtime_offset()Sascha Hauer2018-03-212-2/+2
| | | | | | | | | | | When we are linked at 0x0 and running at 0x01000000 then get_runtime_offset() should return 0x01000000 and not 0xff000000. This makes get_runtime_offset() more consistent and better understandable. This was tested on a Freescale i.MX53 Quickstart board. Additionally relocate_to_adr() was tested since that is normally not called. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* include: Move ns16550 serial platform_data to include/platform_dataSascha Hauer2016-04-151-1/+0
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tegra: set up stack before calling maincluster entryLucas Stach2016-04-141-3/+4
| | | | | | | | Allows this code to work correct regardless of the used compiler optimizations. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* driver: replace dev_request_mem_region with dev_request_mem_resourceSascha Hauer2016-03-072-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_request_mem_region doesn't work properly one some SoCs on which PTR_ERR() values clash with valid return values from dev_request_mem_region. Replace them with dev_request_mem_resource where possible. This patch has been generated with the following semantic patch: // <smpl> @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { ... - return PTR_ERR(io); -} + return PTR_ERR(iores); +} +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) - return PTR_ERR(io); -} + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { - ret = PTR_ERR(io); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { + ret = PTR_ERR(iores); ... } +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ identifier func; @@ func(...) { <+... struct resource *iores; -struct resource *iores; ...+> } // </smpl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tegra: clean up lowlevel entryLucas Stach2016-01-183-11/+8
| | | | | | | | | | The lowlevel startup function jumps directly to the main cluster if we are already running there. This allows for a significant cleanup of the board startup code by directly using the FDT address available there. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* restart: replace reset_cpu with registered restart handlersSascha Hauer2015-08-271-4/+5
| | | | | | | | | | | | | | | | | | | | | | This replaces the reset_cpu() function which every SoC or board must provide with registered handlers. This makes it possible to have multiple reset functions for boards which have multiple ways to reset the machine. Also boards which have no way at all to reset the machine no longer have to provide a dummy reset_cpu() function. The problem this solves is that some machines have external PMICs or similar to reset the system which have to be preferred over the internal SoC reset, because the PMIC can reset not only the SoC but also the external devices. To pick the right way to reset a machine each handler has a priority. The default priority is 100 and all currently existing restart handlers are registered with this priority. of_get_restart_priority() allows to retrieve the priority from the device tree which makes it possible for boards to give certain restart handlers a higher priority in order to use this one instead of the default one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tegra: jump to maincluster earlierLucas Stach2015-06-292-9/+9
| | | | | | | | There is no point in repeating the board setup on the main cluster. It is done either in the AVP startup path or from a first stage loader. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Abolish cpu_read* and cpu_write* accessorsMasahiro Yamada2015-05-201-2/+2
| | | | | | | | | | | | | | Commit 2e6a88f2101d (add cpu native ordered io accessors) introduced these macros and then commit be57f20cdd7d (Fix big endian MMIO primitives) figured out they are equivalent to __raw_{read,write}*. They turned out unnecessary after all. Anyway, most source files use __raw_read* and __raw_write*. Let's replace a few remaining references and abolish them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tegra: add eMMC barebox update handlerLucas Stach2015-03-043-0/+103
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: avp_init: write DT address register earlierLucas Stach2015-03-031-3/+3
| | | | | | | | | Otherwise the write would be skipped if we are already running on the main CPU cluster. In practice this means that a second stage barebox will reuse the DT of the first stage, instead of using it's own. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sizes.h: move include/sizes.h to include/linux/sizes.hMasahiro Yamada2015-01-083-3/+3
| | | | | | | | | | | | | | This file originates in Linux. Linux has it under include/linux/ directory since commit dccd2304cc90. Let's move it to the same place as well in barebox. This commit was generated by the following commands: find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:' git mv include/sizes.h include/linux/ Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: Reuse init_clock() return value for clocksource driversAlexander Shiyan2014-11-101-2/+1
| | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: remove custom UART setupLucas Stach2014-11-043-119/+0
| | | | | | | | | | The config option doesn't make any sense anymore when building a multiimage barebox. With a proper DT built into the image we don't need the ODMdata mechanism to find the debug UART anymore. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: pmc: add support for reset src detectionLucas Stach2014-11-042-0/+41
| | | | | | | Also activate in defconfig. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: jetson-tk1: enable 1.05V_RUNLucas Stach2014-11-041-0/+2
| | | | | | | Needed for the PCIe PLL amongst other things. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: pmc: work around power domain failureLucas Stach2014-11-031-0/+2
| | | | | | | | | Sometimes a power domain didn't properly power up, reading back the command register seems to fix this by flushing the write. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: pmc: add powerdomain handlingLucas Stach2014-10-082-3/+229
| | | | | | | | | In order to use some devices we first have to power up their power domain. Add support to do this in a generic way. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra30: add PCIe clocksLucas Stach2014-10-081-0/+2
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: add PLLE setup functionsLucas Stach2014-10-081-0/+2
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/resource-err-ptr'Sascha Hauer2014-10-022-4/+6
|\
| * resource: Let dev_request_mem_region return an error pointerSascha Hauer2014-09-162-4/+6
| | | | | | | | | | | | For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | pinctrl: fix Kconfig dependenciesSascha Hauer2014-09-151-3/+0
|/ | | | | | | | | | | | | | | | | - Remove OFDEVICE dependency from PINCTRL. It won't do much then, so add a comment to Kconfig when PINCTRL is selected without OFDEVICE - Let Architectures only select PINCTRL instead of the particular driver. Change the drivers to 'default y if $SOC' to make sure the drivers are still compiled if the corresponding SoC is selected This fixes Kconfig warnings like: warning: (PINCTRL_ARMADA_370 && PINCTRL_ARMADA_XP && PINCTRL_DOVE && PINCTRL_KIRKWOOD) selects PINCTRL which has unmet direct dependencies (OFDEVICE) Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* arm: tegra: enable ARM errata workaroundsLucas Stach2014-06-261-2/+19
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add NVIDIA Jetson-TK1 board supportLucas Stach2014-06-051-0/+4
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: pmc: add Tegra124 compatibleLucas Stach2014-06-051-0/+2
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pinctrl: tegra: add Tegra124 supportLucas Stach2014-06-051-0/+1
| | | | | | | | | We can reuse the Tegra30 pinctrl driver, as the bit layout is the same. Just add the pin and drivegroups and some compile-time magic to avoid bloat. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add Tegra124 Kconfig symbolLucas Stach2014-06-051-0/+3
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add architectural timer initLucas Stach2014-06-053-0/+58
| | | | | | | | If the bootloader doesn't init the architectural timer on Cortex A15 Linux falls over when trying to boot. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: setup L2 cache on Tegra124Lucas Stach2014-06-051-1/+12
| | | | | | | Set SRAM latency to 3 clock cycles. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: hardcode entry address for main clusterLucas Stach2014-06-051-2/+16
| | | | | | | | | I don't know why get_runtime_offset fails on T124 yet, but this is a safe workaround, with the nice side-effect of fixing second stage barebox loading. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: apply cluster switch logic to all SoCs >=T30Lucas Stach2014-06-051-1/+1
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add Tegra124 PLL_X rate setupLucas Stach2014-06-051-0/+8
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: change cpu internal reset layout for Tegra124Lucas Stach2014-06-051-4/+15
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: fix MESLECT clock enableLucas Stach2014-06-052-1/+3
| | | | | | | Don't disable clk to unrelated devices in the process. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: power up additional partitions on Tegra124Lucas Stach2014-06-052-6/+22
| | | | | | | Those 3 are needed to power CPU0 from the CPUG cluster. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: disable IDDQ for PLL_X on Tegra124Lucas Stach2014-06-052-0/+28
| | | | | | | This is an additional power down control. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add Tegra124 and AS3722 PMIC to lowlevel-dvcLucas Stach2014-06-051-0/+55
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: recognize Tegra124 in common initcallsLucas Stach2014-06-051-2/+4
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: recognize Tegra124 in maincomplex startupLucas Stach2014-06-051-0/+1
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: lowlevel: fix ODMdata fetch on Tegra124Lucas Stach2014-06-051-15/+35
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add Tegra124 id to lowlevel functionsLucas Stach2014-06-051-0/+6
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: lowlevel: setup an early stackLucas Stach2014-06-051-0/+2
| | | | | | | | Even the lowlevel functions are growing to a size where having a stack seem beneficial. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: pmc: add command to get into RCMLucas Stach2014-06-051-0/+20
| | | | | | | | | | | In RCM aka recovery mode the BootROM waits for a usbloader to take over control. On most boards this is triggered by holding a physical switch which may be inconvinient at times. Add a command to switch into RCM from software. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: pmc: add Tegra30 compatibleLucas Stach2014-06-041-0/+2
| | | | | | | Allows reset command to work on T30. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: lowlevel-dvc: use __always_inline macroLucas Stach2014-06-041-3/+3
| | | | | | | Cleaner code. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tegra: beaver: activate sdmmc1 voltage railLucas Stach2014-05-151-0/+2
| | | | | | | In order to get the SD card solt working. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra30: register i2c clocksLucas Stach2014-05-151-0/+2
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: lowlevel: add function to fetch chipidLucas Stach2014-05-151-0/+6
| | | | | | | This is needed as a safe way to flush the ABP bus. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tegra30: ramp vdd_core to 1,2VLucas Stach2014-05-081-0/+18
| | | | | | | | | This isn't much different from the default 1,16V and I haven't seen this make a difference on any board, but it seems to be required for some T30 SKUs. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 02:01:06 +0000