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riscv
Commit message (
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Author
Age
Files
Lines
*
Merge branch 'for-next/riscv'
Sascha Hauer
2021-10-07
13
-0
/
+471
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\
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*
RISC-V: virt: support poweroff/restart on tinyemu
Ahmad Fatoum
2021-10-07
4
-0
/
+86
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*
RISC-V: add litex_linux_defconfig
Antony Pavlov
2021-10-07
1
-0
/
+75
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*
RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
Antony Pavlov
2021-10-07
9
-0
/
+308
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*
clocksource: timer-riscv: select CSR from device tree
Antony Pavlov
2021-10-04
1
-0
/
+2
*
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Merge branch 'for-next/misc'
Sascha Hauer
2021-10-07
2
-0
/
+22
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\
\
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/
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/
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*
serial: implement riscv SBI console support
Marcelo Politzer
2021-10-05
2
-0
/
+22
*
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RISC-V: board-dt-2nd: move low level init into nonnaked function
Ahmad Fatoum
2021-10-02
1
-1
/
+7
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/
*
Merge branch 'for-next/riscv'
Sascha Hauer
2021-07-18
48
-108
/
+2428
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\
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*
RISC-V: boards: beaglev: make it possible to use nmon
Antony Pavlov
2021-07-09
2
-0
/
+3
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*
RISC-V: boards: erizo: make it possible to use nmon
Antony Pavlov
2021-07-09
1
-0
/
+2
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*
RISC-V: make it possible to run nmon from PBL C code
Antony Pavlov
2021-07-09
3
-17
/
+46
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*
RISC-V: StarFive: add board support for BeagleV Starlight
Ahmad Fatoum
2021-06-24
14
-0
/
+1458
|
*
reset: add StarFive reset controller driver
Ahmad Fatoum
2021-06-24
1
-0
/
+1
|
*
net: designware: fix non-1:1 mapped 64-bit systems
Ahmad Fatoum
2021-06-24
1
-0
/
+10
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*
soc: starfive: add support for JH7100 incoherent interconnect
Ahmad Fatoum
2021-06-24
1
-0
/
+5
|
*
drivers: soc: sifive: add basic L2 cache controller driver
Ahmad Fatoum
2021-06-24
2
-0
/
+32
|
*
RISC-V: support incoherent I-Cache
Ahmad Fatoum
2021-06-24
8
-0
/
+48
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*
RISC-V: add exception support
Ahmad Fatoum
2021-06-24
12
-0
/
+510
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*
RISC-V: dma: support multiple dma_alloc_coherent backends
Ahmad Fatoum
2021-06-24
3
-35
/
+88
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*
RISC-V: socs: add Kconfig entry for StarFive JH7100
Ahmad Fatoum
2021-06-24
1
-0
/
+22
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*
RISC-V: erizo: make it easier to reuse ns16550 debug_ll
Ahmad Fatoum
2021-06-24
1
-2
/
+5
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*
RISC-V: S-Mode: propagate Hart ID
Ahmad Fatoum
2021-06-24
7
-10
/
+67
|
*
RISC-V: cpuinfo: return some output for non-SBI systems as well
Ahmad Fatoum
2021-06-21
2
-22
/
+41
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*
RISC-V: extend multi-image to support both S- and M-Mode
Ahmad Fatoum
2021-06-21
12
-28
/
+97
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*
RISC-V: virt: select only one timer
Ahmad Fatoum
2021-06-21
1
-1
/
+0
*
|
Merge branch 'for-next/misc'
Sascha Hauer
2021-07-18
1
-0
/
+3
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\
\
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*
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riscv: bootm: Add dryrun check
Sascha Hauer
2021-06-23
1
-0
/
+3
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/
*
/
blspec: Rework firmware load
Sascha Hauer
2021-06-28
1
-0
/
+5
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/
*
of: propagate errors inside barebox_register_{of, fdt} into initcalls
Ahmad Fatoum
2021-06-02
1
-2
/
+3
*
RISC-V: add Linux kernel boot support
Ahmad Fatoum
2021-05-17
2
-0
/
+52
*
RISC-V: asm: barebox-riscv-head: use load-offset of 0
Ahmad Fatoum
2021-05-17
1
-1
/
+1
*
RISC-V: sifive: add HiFive board support
Ahmad Fatoum
2021-05-17
9
-0
/
+198
*
RISC-V: add SBI based cpuinfo
Ahmad Fatoum
2021-05-10
4
-6
/
+135
*
RISC-V: erizo: drop mach-erizo directory
Ahmad Fatoum
2021-05-10
6
-29
/
+15
*
RISC-V: erizo: restrict to RV32I
Ahmad Fatoum
2021-05-03
1
-1
/
+1
*
RISC-V: support multi-image for all machines
Ahmad Fatoum
2021-05-03
7
-43
/
+30
*
RISC-V: delete unused mach-virt subdirectory
Ahmad Fatoum
2021-05-03
3
-29
/
+0
*
RISC-V: board-dt-2nd: add PBL console support for virt
Ahmad Fatoum
2021-05-03
1
-1
/
+26
*
RISC-V: debug_ll: ns16550: split off debug_ll from generic parts
Ahmad Fatoum
2021-05-03
2
-32
/
+65
*
RISC-V: boot: uncompress: determine piggy data bounds before relocation
Ahmad Fatoum
2021-04-13
2
-4
/
+6
*
RISC-V: drop old timer handling code
Antony Pavlov
2021-03-30
2
-64
/
+1
*
RISC-V: erizo.dtsi: set timebase-frequency = <24000000>
Antony Pavlov
2021-03-30
1
-0
/
+2
*
RISC-V: boot: move stack top to very end of memory
Ahmad Fatoum
2021-03-29
1
-1
/
+1
*
RISC-V: board-dt-2nd: ensure FDT doesn't overlap with early mem regions
Ahmad Fatoum
2021-03-29
3
-6
/
+28
*
RISC-V: cpu: request stack memory region
Ahmad Fatoum
2021-03-29
1
-0
/
+12
*
RISC-V: add Qemu virt support
Rouven Czerwinski
2021-03-23
6
-1
/
+271
*
clocksource: add driver for RISC-V and CLINT timers
Ahmad Fatoum
2021-03-23
10
-1
/
+483
*
RISC-V: add generic DT image
Ahmad Fatoum
2021-03-23
3
-0
/
+46
*
RISC-V: add 64-bit support
Rouven Czerwinski
2021-03-23
6
-18
/
+35
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