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* Merge branch 'for-next/riscv'Sascha Hauer2021-10-0713-0/+471
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| * RISC-V: virt: support poweroff/restart on tinyemuAhmad Fatoum2021-10-074-0/+86
| * RISC-V: add litex_linux_defconfigAntony Pavlov2021-10-071-0/+75
| * RISC-V: add LiteX SoC and linux-on-litex-vexriscv supportAntony Pavlov2021-10-079-0/+308
| * clocksource: timer-riscv: select CSR from device treeAntony Pavlov2021-10-041-0/+2
* | Merge branch 'for-next/misc'Sascha Hauer2021-10-072-0/+22
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| * serial: implement riscv SBI console supportMarcelo Politzer2021-10-052-0/+22
* | RISC-V: board-dt-2nd: move low level init into nonnaked functionAhmad Fatoum2021-10-021-1/+7
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* Merge branch 'for-next/riscv'Sascha Hauer2021-07-1848-108/+2428
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| * RISC-V: boards: beaglev: make it possible to use nmonAntony Pavlov2021-07-092-0/+3
| * RISC-V: boards: erizo: make it possible to use nmonAntony Pavlov2021-07-091-0/+2
| * RISC-V: make it possible to run nmon from PBL C codeAntony Pavlov2021-07-093-17/+46
| * RISC-V: StarFive: add board support for BeagleV StarlightAhmad Fatoum2021-06-2414-0/+1458
| * reset: add StarFive reset controller driverAhmad Fatoum2021-06-241-0/+1
| * net: designware: fix non-1:1 mapped 64-bit systemsAhmad Fatoum2021-06-241-0/+10
| * soc: starfive: add support for JH7100 incoherent interconnectAhmad Fatoum2021-06-241-0/+5
| * drivers: soc: sifive: add basic L2 cache controller driverAhmad Fatoum2021-06-242-0/+32
| * RISC-V: support incoherent I-CacheAhmad Fatoum2021-06-248-0/+48
| * RISC-V: add exception supportAhmad Fatoum2021-06-2412-0/+510
| * RISC-V: dma: support multiple dma_alloc_coherent backendsAhmad Fatoum2021-06-243-35/+88
| * RISC-V: socs: add Kconfig entry for StarFive JH7100Ahmad Fatoum2021-06-241-0/+22
| * RISC-V: erizo: make it easier to reuse ns16550 debug_llAhmad Fatoum2021-06-241-2/+5
| * RISC-V: S-Mode: propagate Hart IDAhmad Fatoum2021-06-247-10/+67
| * RISC-V: cpuinfo: return some output for non-SBI systems as wellAhmad Fatoum2021-06-212-22/+41
| * RISC-V: extend multi-image to support both S- and M-ModeAhmad Fatoum2021-06-2112-28/+97
| * RISC-V: virt: select only one timerAhmad Fatoum2021-06-211-1/+0
* | Merge branch 'for-next/misc'Sascha Hauer2021-07-181-0/+3
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| * | riscv: bootm: Add dryrun checkSascha Hauer2021-06-231-0/+3
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* / blspec: Rework firmware loadSascha Hauer2021-06-281-0/+5
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* of: propagate errors inside barebox_register_{of, fdt} into initcallsAhmad Fatoum2021-06-021-2/+3
* RISC-V: add Linux kernel boot supportAhmad Fatoum2021-05-172-0/+52
* RISC-V: asm: barebox-riscv-head: use load-offset of 0Ahmad Fatoum2021-05-171-1/+1
* RISC-V: sifive: add HiFive board supportAhmad Fatoum2021-05-179-0/+198
* RISC-V: add SBI based cpuinfoAhmad Fatoum2021-05-104-6/+135
* RISC-V: erizo: drop mach-erizo directoryAhmad Fatoum2021-05-106-29/+15
* RISC-V: erizo: restrict to RV32IAhmad Fatoum2021-05-031-1/+1
* RISC-V: support multi-image for all machinesAhmad Fatoum2021-05-037-43/+30
* RISC-V: delete unused mach-virt subdirectoryAhmad Fatoum2021-05-033-29/+0
* RISC-V: board-dt-2nd: add PBL console support for virtAhmad Fatoum2021-05-031-1/+26
* RISC-V: debug_ll: ns16550: split off debug_ll from generic partsAhmad Fatoum2021-05-032-32/+65
* RISC-V: boot: uncompress: determine piggy data bounds before relocationAhmad Fatoum2021-04-132-4/+6
* RISC-V: drop old timer handling codeAntony Pavlov2021-03-302-64/+1
* RISC-V: erizo.dtsi: set timebase-frequency = <24000000>Antony Pavlov2021-03-301-0/+2
* RISC-V: boot: move stack top to very end of memoryAhmad Fatoum2021-03-291-1/+1
* RISC-V: board-dt-2nd: ensure FDT doesn't overlap with early mem regionsAhmad Fatoum2021-03-293-6/+28
* RISC-V: cpu: request stack memory regionAhmad Fatoum2021-03-291-0/+12
* RISC-V: add Qemu virt supportRouven Czerwinski2021-03-236-1/+271
* clocksource: add driver for RISC-V and CLINT timersAhmad Fatoum2021-03-2310-1/+483
* RISC-V: add generic DT imageAhmad Fatoum2021-03-233-0/+46
* RISC-V: add 64-bit supportRouven Czerwinski2021-03-236-18/+35
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