| Commit message (Collapse) | Author | Age | Files | Lines |
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To make changes to the SDRAM controller effective, the APPLYCFG bit must
be set after programming the bitstream to the FPGA. This has to be done
without any SDRAM usage. Therefore copy the function to execute to the
OCRAM and execute it from there.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Link: https://lore.barebox.org/20210625085944.11260-1-s.trumtrar@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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A timeout is never detected as timeout is tested for being smaller than
0 which never happens for an unsigned variable. Change to a signed type.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-3-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Terasic DE10-Nano board is based on CycloneV SoCFPGA (5CSEBA6) with
What has been tested to work:
- SD card
- Gigabit network
- FPGA (FPPx16 & FPPx32)
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Link: https://lore.barebox.org/20210531194019.951-1-gwenj@trabucayre.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Do not hand over control to a second stage barebox if its embedded CRC checksum
is invalid.
Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
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The size of the buffer allocated in the function is needed if it shall be
inspected more closely later. Therefore optionally return it via a new pointer
argument.
Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
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The size of the buffer allocated in the function is needed if it shall be
inspected more closely later. Therefore optionally return it via a new pointer
argument.
Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
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With incoming changes to choose a specific reset method, give all
currently unnamed "default" reset handlers a name:
- soc reset via SoC-specific means
- soc-wdt reset via SoC watchdog timer
- vector reset via jump to reset vector
- efi reset via EFI firmware
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This reverts commit a83c97f2a4065ef7209f123b837fa5103f984c6a.
The dead code elimination with thin archive can cope with the same
symbol names. Revert the workaround.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We already have one ARCH_TEXT_BASE in the file, which sets a value of
zero. MACH_SOCFPGA_CYCLONE5 and MACH_SOCFPGA_ARRIA10 aren't defined
anywhere and are listed in no defconfigs, thus drop the duplicate
option.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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These defines are common for arria10 and cyclone5.
Instead of having them here, they are moved to drivers/net/designware_socfpga.c.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fix the warning:
arch/arm/mach-socfpga/arria10-xload.c:17:5: warning: no previous prototype for
'a10_update_bits' [-Wmissing-prototypes]
17 | int a10_update_bits(unsigned int reg, unsigned int mask,
| ^~~~~~~~~~~~~~~
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fix the warning
arch/arm/mach-socfpga/arria10-clock-manager.c:113:14: warning: no previous prototype for
'arria10_cm_get_mmc_controller_clk_hz' [-Wmissing-prototypes]
113 | unsigned int arria10_cm_get_mmc_controller_clk_hz(void)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fix the following warnings
arch/arm/mach-socfpga/arria10-reset-manager.c:152:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q1' [-Wmissing-prototypes]
152 | void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm/mach-socfpga/arria10-reset-manager.c:226:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q2' [-Wmissing-prototypes]
226 | void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm/mach-socfpga/arria10-reset-manager.c:272:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q3' [-Wmissing-prototypes]
272 | void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm/mach-socfpga/arria10-reset-manager.c:329:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q4' [-Wmissing-prototypes]
329 | void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since the commit
5a1a5ed2537d7d12f851f3778707681d6c08d6e8
ARM: images: use piggydata
the loading mechanism in the arria10 xload is neither functional nor needed.
Now, barebox has/can be loaded like a normal image, so the filesize, that is
written to the barebox header, can be evaluated.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Most callers of arm_setup_stack substract a fixed offset of 8, 12 or 16
bytes from the stack top. This is unnecessary as on ARM we have a stack
that decrements before storing values. Substracting this offset probably
goes back to the U-Boot version we forked from. Stop this now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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watchdog_disable() is left over from the original SoCFPGA commit and
nothing calls it. Remove it to avoid a '-Wmissing-prototypes' warning
from the compiler.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The socfpga xload images are limited to 64KiB. This doesn't fit if
multiple boards are selected. The reason is that we include huge
C files and arrays in the early init code which get compiled once
for each board. -ffunction-sections is without effect here since all
functions have the same name and hence we get the same function
multiple times in the same section.
To overcome this we surround all function names with a SECT() macro which
is used to add a board specific prefix to the section names. This way
-ffunction-sections can now do its work and discard unused functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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SoCFPGA has GPIOs. Select it for the normal bootloader. For the xload barebox,
do not select it to not waste space.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Apart from the RAM size, all cyclone5-based Socfpga boards use the
same lowlevel code. Instead of duplicating it for every board, move
it to mach-socfpga and provide a macro to use it in the boardspecific
code.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fixes:
arch/arm/mach-socfpga/arria10-xload.c: In function 'arria10_prepare_mmc':
arch/arm/mach-socfpga/arria10-xload.c:339:40: warning: dereferencing 'void *' pointer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Avoid "multiple definition of `a10_wait_for_usermode'"
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Some Arria10 boards don't have the FPGA programmed externally.
Instead barebox needs to do that. As the Arria10 has the SDRAM
controller in the FPGA, the first thing we need to do is,
configure the FPGA before the SDRAM can even be used.
It works like this:
1. boot ROM fetches the PBL from MMC
2. read the MBR from MMC (this depends on the setup done by the boot ROM)
3. read the Bitstream from the MMC and program the FPGA
4. re-read the barebox image from MMC, this time with the full barebox
that is appended to the PBL
5. jump into the full barebox
Only supported boot device is eMMC.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Arria10 init code resets all peripherals. Convert this to keep the bootmedium
out of reset and keep the setup done by the boot ROM.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Move the setup of the shared- and fpgapins to its own function.
These pins can only be configured and let out of reset after the FPGA has been
programmed.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Instead of copy+pasting the debug_ll messages to every new board,
move them to the respective functions.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Enable workarounds for two of the errata the CPU is affected
with.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There is a proper driver now that handles the PHY setup for SoCFPGA.
Get rid of the code from mach-socfpga.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add a driver for the SoCFPGA-specific version of the designware ethernet ip core.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The disable bits for the ethernet interfaces between FPGA and HPS are read
and configured, but never written back.
The configuration itself doesn't make that much sense however. So instead of
writing it back to the register, remove the whole read-modify operation altogether.
Reported-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The struct member has been renamed, fix it.
Fixes: fddf254b8b9a (mtd: spi-nor: cadence: change devicetree bindings to upstream)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that
is already supported in barebox.
Both a the same in some parts, but totaly different in
others. Most of the hardware blocks are the same in the
SoC parts. The OCRAM is larger on the Arria10 and the
SDRAM controller is different.
The serial core only supports 32bit accesses (different to
the 8bit accesses on the Cyclone5).
As Arria10 has 256KB of OCRAM, it is possible to fit a larger
barebox (and/or use PBL) instead of the two stage bootprocess
used on the Cyclone5 and its 64KB OCRAM.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Allow configuring the serial port and clock rate
instead of hardcoding it.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Prepare the SoCFPGA code base for different system types
(Arria10, Stratix10,...).
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We are going to introduce a "enum param_type" in barebox, so
rename the struct type of the same name in the socfpga sequencer
code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Upstream devicetree bindings where changed to use "cdns,is-decoded-cs"
instead of "external-decoder". Use it.
Also, get rid of the clock-names "qspi_clk" dependency.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There is no fpga.c file.
Remove the entry.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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