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* RISC-V: sifive: enable SPI Flash and SD in configAhmad Fatoum2022-04-291-6/+7
| | | | | | | | | | To test SD-Card: ./test/emulate.pl sifive_defconfig -- -drive file=image.sdcard,if=sd Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20220426064604.422292-2-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/of-deep-probe'Sascha Hauer2022-03-141-1/+1
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| * of: rename of_find_node_by_name() to of_find_node_by_name_address()Sascha Hauer2022-03-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | of_find_node_by_name() has the same name as the corresponding kernel function but a different semantics. A node name is comprised of the nodes name and a unit address, separated with '@'. Linux of_find_node_by_name() matches only the name before the '@' whereas the barebox function compares the full name. As several callers depend on the barebox semantics we can't just change the semantics, so rename the barebox function to of_find_node_by_name_address(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: virt: riscvemu: add interactive tutorialAhmad Fatoum2022-03-0830-0/+244
|/ | | | | | | | | | | | | | | This tutorial walks the user through basics of the barebox shell. It can be invoked using the next command. It will be extended later to cover actual boot as well, but that part still needs to be added to the web demo. To try it out interactively, go to: https://www.barebox.org/jsbarebox/ Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220302160040.2990961-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/spdx'Sascha Hauer2022-01-1915-0/+30
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| * arch: add SPDX-License-Identifier to all .c filesAhmad Fatoum2022-01-051-0/+2
| | | | | | | | | | | | | | | | | | Record GPL-2.0-only as license for all files lacking an explicit license statement. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * arch: add SPDX-License-Identifier to all headersAhmad Fatoum2022-01-059-0/+18
| | | | | | | | | | | | | | | | | | Record GPL-2.0-only as license for all files lacking an explicit license statement. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-9-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * treewide: add SPDX-License-Identifier for .gitignoreAhmad Fatoum2022-01-051-0/+2
| | | | | | | | | | | | | | | | | | Makes the files not appear when searching for files that lack SPDX-License-Identifier. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * treewide: add SPDX-License-Identifier for Kbuild/KconfigAhmad Fatoum2022-01-054-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To verify only Kconfig/Makefile is touched: git show --numstat --format=oneline HEAD | grep -v 'Kconfig\|Makefile' will print only arch/powerpc/Kbuild. To verify nothing unexpected is added: git show -U0 | grep '^-[^-]\|^+[^+]' | sort -u Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: Virt: enable more useful optionsAhmad Fatoum2022-01-122-0/+12
| | | | | | | | | | | | | | | | | | Incoming tutorial will showcase some barebox features, so enable them in the config for use. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171524.587144-9-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: add stacktrace support via frame pointer walkingAhmad Fatoum2022-01-127-6/+106
| | | | | | | | | | | | | | | | | | Make debugging more convenient by implementing stack_dump() and changing exception handlers to print stack trace along with the register dump. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171524.587144-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: don't use x8/s0/fp in assemblyAhmad Fatoum2022-01-123-35/+35
| | | | | | | | | | | | | | | | | | Free up the register to allow building a configuration with x8/s0 used as the frame pointer. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171524.587144-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: virt: riscvemu: clear frame buffer before jumping to reset vectorAhmad Fatoum2022-01-121-0/+3
| | | | | | | | | | | | | | | | | | | | Our poor man's reset just resumes execution at the reset vector, so the framebuffer will maintain its contents over reset, leading to artifacts. Clear screen before reset to avoid this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171524.587144-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: virt: riscvemu: be explicit about HTIF base addressAhmad Fatoum2022-01-121-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | The normal riscvemu console is Virt I/O, which isn't really suitable to poke from the command line as part of the incoming jsbarebox tutorial. The HTIF on the other hand can be poked quite comfortably. To make it look more like normal devices, fix up an address. No functional change. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171524.587144-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: virt: riscvemu: repurpose 64k low RAM for state/environmentAhmad Fatoum2022-01-125-0/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | TinyEMU's RISC-V machine emulates a 64K SRAM at address 0. First 4K page is unused, then a maximum of 0x40 bytes for boot ROM (trampoline that passes FDT), then the FDT. The remainder of the 64K is unused. Make use of that space for storing state and environment. We start the mtd-ram at 0x1000 to easily allow for a faulting zero page. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171524.587144-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: virt: riscvemu: add HTIF DEBUG_LL supportAhmad Fatoum2022-01-122-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Default console of riscvemu is available Virt I/O console and as a HTIF blocking character device. We already support Virt I/O console, but the HTIF is easier to support for very early low level debugging. Add DEBUG_LL support to facilitate using it. Note: when using a framebuffer, riscvemu doesn't allocate a default console, so barebox calling into HTIF will segfault the emulator. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171524.587144-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | power: reset: add RISC-V/UC Berkely HTIF poweroff driver supportAhmad Fatoum2022-01-124-15/+33
| | | | | | | | | | | | | | | | | | | | We already have a driver in board code and device tree passed by emulator already has a node for it. Match against it and create a proper driver. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171524.587144-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: virt: activate all consolesAhmad Fatoum2022-01-122-0/+2
| | | | | | | | | | | | | | | | | | | | While CONSOLE_ACTIVATE_NONE + stdout-path is usually the way to go, main console on this platform can be virtio console, which can't be referenced as is in DT, so just enable all consoles. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171524.587144-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | include: <asm/csr.h>: sync with upstreamAhmad Fatoum2022-01-101-52/+161
|/ | | | | | | | | We don't define CONFIG_RISCV_PRIV_1_9, so deleted stuff by the sync is unused anyway. No functional change. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220108171445.586681-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: cpu: fix build with CONFIG_RISCV_EXCEPTIONS=nAhmad Fatoum2022-01-051-0/+2
| | | | | | | | | | | | Building without CONFIG_RISCV_EXCEPTIONS causes a compile error, because of a definition mismatch. data_abort_mask is a no-op without exception support, but interrupt.c defines it as a different type of symbol. Skip interrupt.c compilation to fix the build error. Reported-by: Yann Sionneau <ysionneau@kalray.eu> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20211204130854.1624493-1-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/x86'Sascha Hauer2021-12-151-1/+0
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| * kbuild: remove unneeded -nostdlib flagMasahiro Yamada2021-11-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The -nostdlib option requests the compiler to not use the standard system startup files or libraries when linking. arch/kvm/Makefile adds it to KBUILD_CFLAGS/AFLAGS, but it does not make sense because those are unrelated to linking. arch/{mips,riscv,x86}/Makefile passes it to the linker, but it is not sensible either. As noted above, adding -nostdlib makes sense only when $(CC) is used as a linker driver, but $(LD) is directly used for linking barebox. (ld.bfd/ld.lld recognizes the -nostdlib flag, but its behavior is obscure, and unneeded here.) Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Link: https://lore.barebox.org/20211117034918.1226358-2-masahiroy@kernel.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2021-12-157-13/+68
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| * | RISC-V: qemu-virt: add overlay for environment and stateAhmad Fatoum2021-12-073-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Like we do on ARM, let's add state and environment to RISC-V QEMU Virt as well. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20211125161042.3829996-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: virt: add DEBUG_LL supportAhmad Fatoum2021-12-072-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While we have PBL console support, console isn't available during early barebox startup. Implement DEBUG_LL for Qemu RISC-V Virt to make such early debugging easier. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20211125160657.3828643-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: LiteX: fix comment about running from ROMAhmad Fatoum2021-11-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Copy-paste left-over. On LiteX, barebox is already running from RAM that the BIOS had set up. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20211125070515.671542-1-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: configs: virt: enable networking and PCIAhmad Fatoum2021-11-252-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently, we have gained support for PCI and virtio networking. Enable both in the config as well as related useful options that depends on them. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20211122213436.309749-2-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: enable HW_HAS_PCIAhmad Fatoum2021-11-252-0/+8
| |/ | | | | | | | | | | | | | | | | | | | | With the recently added generic ECAM PCI driver, we can now use PCI device drivers on the RISC-V Virt machine. Enable HW_HAS_PCI, so the driver and bus support can be selected. As HW_HAS_PCI on its own doesn't add any code, just enable it for the whole architecture. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20211122213436.309749-1-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/efi'Sascha Hauer2021-12-153-5/+9
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| * | asm-generic: move sync_caches_for_execution declaration to <asm/cache.h>Ahmad Fatoum2021-11-253-5/+9
| |/ | | | | | | | | | | | | | | | | | | We have three architectures defining sync_caches_for_execution(). Have them all do so in a header of the same name to allow using it in common code later on, like in an EFI image loading routine. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20211122084732.2597109-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: interrupts: fix Zifencei emulation on rv64Ahmad Fatoum2021-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Zifencei emulaton was added for bare bones 32-bit targets, but the code is there on 64-bit too. The instruction skip at the end of the function skips 4 bytes, the size of an instruction on both rv32 and rv64. The instruction decoder however assumes instructions are size(long) bytes, which is 8 > 4 on rv64. Fix this. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20211203063340.1026512-1-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: nmon: fix SiFive DEBUG_LL buildAhmad Fatoum2021-11-301-1/+1
|/ | | | | | | | | nmon includes <debug_ll.h> in assembly source, so add __ASSEMBLY__ guards, so the build doesn't fail. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20211129064117.2007757-1-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/riscv'Sascha Hauer2021-10-0713-0/+471
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| * RISC-V: virt: support poweroff/restart on tinyemuAhmad Fatoum2021-10-074-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | QEMU Virt on RISC-V has syscon-reboot and syscon-poweroff compatible devices and describes them in the device tree. TinyEMU's Virt machine is different and has a HTIF based poweroff and no dedicated reset mechanism. Add board support for the HTIF poweroff and use a poor man's reset that jumps back to the reset vector. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210916093532.21699-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * RISC-V: add litex_linux_defconfigAntony Pavlov2021-10-071-0/+75
| | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Link: https://lore.barebox.org/20210817101104.114945-9-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * RISC-V: add LiteX SoC and linux-on-litex-vexriscv supportAntony Pavlov2021-10-079-0/+308
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. See https://github.com/enjoy-digital/litex and https://github.com/litex-hub/linux-on-litex-vexriscv for details. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210817101104.114945-8-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clocksource: timer-riscv: select CSR from device treeAntony Pavlov2021-10-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox timer-riscv driver supports one of user counters: * 'cycle', counter for RDCYCLE instruction (CSR 0xc00); * 'time', timer for RDTIME instruction (CSR 0xc01). At the moment in M-mode timer-riscv uses the 'cycle' counter, and in S-mode timer-riscv uses the 'time' timer. Alas picorv32 CPU core supports only the 'cycle' counter. VexRiscV CPU core in M-mode supports only the 'time' timer. This patch makes it possible to use the 'time' timer for VexRiscV CPU in M-mode. See also http://lists.infradead.org/pipermail/barebox/2021-May/036067.html Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210817101104.114945-2-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2021-10-072-0/+22
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| * serial: implement riscv SBI console supportMarcelo Politzer2021-10-052-0/+22
| | | | | | | | | | | | | | | | Implement a console over legacy SBI (version 0.1.0). There is a tiny ringbuffer to simplify checking for presence and reading characters as separate steps. Link: https://lore.barebox.org/20210927200521.7996-1-marcelo.politzer@cartesi.io Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | RISC-V: board-dt-2nd: move low level init into nonnaked functionAhmad Fatoum2021-10-021-1/+7
|/ | | | | | | | | | | | | The generic DT image for RISC-V mimics a kernel image and specifies a load offset that it expects to be honoured. The stack should then grow down from the load address. This didn't work as intended though with riscv64-linux-gnu-gcc (Debian 10.2.1-6), because of the entry point's __naked attribute: local variables overwrote the first bytes of the entry point. Fix this by using a noinline nonnaked function. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210916093514.21267-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/riscv'Sascha Hauer2021-07-1848-108/+2428
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| * RISC-V: boards: beaglev: make it possible to use nmonAntony Pavlov2021-07-092-0/+3
| | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Link: https://lore.barebox.org/20210708083035.40814-4-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * RISC-V: boards: erizo: make it possible to use nmonAntony Pavlov2021-07-091-0/+2
| | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210708083035.40814-3-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * RISC-V: make it possible to run nmon from PBL C codeAntony Pavlov2021-07-093-17/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After migrating to PBL we can't use nmon assembler macro in C code anymore. Some changes are introduced to invoke nmon from PBL C code: * use 'lla' macro instruction instead of 'la'; * don't touch the 'ra' register, use 'a2' instead; * add wrapper C function for nmon. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210708083035.40814-2-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * RISC-V: StarFive: add board support for BeagleV StarlightAhmad Fatoum2021-06-2414-0/+1458
| | | | | | | | | | | | | | | | | | With the different drivers now in place, we have everything to start a barebox image. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-30-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * reset: add StarFive reset controller driverAhmad Fatoum2021-06-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The StarFive SoC has a single reset controller, which seems to control reset of all clocks and peripherals. It differs from the ones supported by the Linux reset-simple driver in that it has a dedicated status registers that needs to be polled to verify the reset has completed. Also special is that most resets (> 70) are synchronous. As the reset status poll would just time out without the clock, have the reset controller enable the clock as part of the reset. OS can decide later, which clocks to disable again. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-24-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net: designware: fix non-1:1 mapped 64-bit systemsAhmad Fatoum2021-06-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/net/designware.c handles the older Designware < 4.x MAC IPs, which do not support DMA beyond 32-bit. They are still being integrated into SoCs with 64-bit CPUs like the StarFive JH7100, which additionally needs a non 1:1 mapping for coherent DMA. Fix the driver to support such usage. The driver still has the assumption that barebox core will only pass it 32-bit pointers. This is now made explicit by returning error codes when the DMA mask is violated. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-16-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * soc: starfive: add support for JH7100 incoherent interconnectAhmad Fatoum2021-06-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The preproduction JH7100 used in the BeagleV beta does not ensure cache coherence between CPU and some DMA masters like the Ethernet MAC. Fix this for streaming DMA mappings by implementing cache cleaning and discarding. The Flush64 primitive can be used for both as it will invalidate after flushing and not write-back clean lines. Coherent DMA mapping will be implemented using allocation from uncached SRAM in a follow-up commit. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-14-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * drivers: soc: sifive: add basic L2 cache controller driverAhmad Fatoum2021-06-242-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SiFive SoCs are cache coherent with respect to other DMA masters, so there is no need to explicitly flush cache lines. Incoming StarFive SoC uses SiFive CPU and L2 cache controller, but is cache-incoherent and thus needs the maintenance for DMA. Add a basic driver that exports the cache flush function for SoC-specific drivers to use. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-13-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * RISC-V: support incoherent I-CacheAhmad Fatoum2021-06-248-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SiFive SoCs have separate I-Caches that require self-modifying code like barebox' relocation and PBL extraction code to do cache maintenance. Implement sync_caches_for_execution and use it where appropriate. The underlying fence.i primitive is part of the Zifencei (load/store fence) ISA extension. As we can't be sure it's always available, the exception handler will skip over the instruction if the CPU trips over it. Alternatively, if CONFIG_HAS_CACHE=n, the instruction won't be emitted at all. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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