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* ARM: tegra: Move mach header files to include/mach/tegraSascha Hauer2023-03-061-6/+6
| | | | | | | | | | Currently arch specific headers can be included with longer possible as there won't be a single mach anymore. Move all tegra specific header files to include/mach/tegra/ to prepare for multi-arch support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: return positive offset in get_runtime_offset()Sascha Hauer2018-03-211-1/+1
| | | | | | | | | | | When we are linked at 0x0 and running at 0x01000000 then get_runtime_offset() should return 0x01000000 and not 0xff000000. This makes get_runtime_offset() more consistent and better understandable. This was tested on a Freescale i.MX53 Quickstart board. Additionally relocate_to_adr() was tested since that is normally not called. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tegra: clean up lowlevel entryLucas Stach2016-01-181-4/+1
| | | | | | | | | | The lowlevel startup function jumps directly to the main cluster if we are already running there. This allows for a significant cleanup of the board startup code by directly using the FDT address available there. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tegra: jump to maincluster earlierLucas Stach2015-06-291-3/+0
| | | | | | | | There is no point in repeating the board setup on the main cluster. It is done either in the AVP startup path or from a first stage loader. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: avp_init: write DT address register earlierLucas Stach2015-03-031-3/+3
| | | | | | | | | Otherwise the write would be skipped if we are already running on the main CPU cluster. In practice this means that a second stage barebox will reuse the DT of the first stage, instead of using it's own. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: hardcode entry address for main clusterLucas Stach2014-06-051-2/+16
| | | | | | | | | I don't know why get_runtime_offset fails on T124 yet, but this is a safe workaround, with the nice side-effect of fixing second stage barebox loading. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: apply cluster switch logic to all SoCs >=T30Lucas Stach2014-06-051-1/+1
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add Tegra124 PLL_X rate setupLucas Stach2014-06-051-0/+8
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: change cpu internal reset layout for Tegra124Lucas Stach2014-06-051-4/+15
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: fix MESLECT clock enableLucas Stach2014-06-051-1/+1
| | | | | | | Don't disable clk to unrelated devices in the process. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: power up additional partitions on Tegra124Lucas Stach2014-06-051-6/+18
| | | | | | | Those 3 are needed to power CPU0 from the CPUG cluster. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: disable IDDQ for PLL_X on Tegra124Lucas Stach2014-06-051-0/+9
| | | | | | | This is an additional power down control. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tegra30: slow down CPU to 600 MHzLucas Stach2014-05-081-4/+4
| | | | | | | | | | It's not safe to ramp up the CPU clock speed to 1,4 GHz on all T30 SKUs, as this may result in failure to start the kernel properly. Start CPU at 600 MHz, which is safe even for the slowest SKUs. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: source MSELECT clock from CLK_MLucas Stach2014-04-231-2/+2
| | | | | | | | | We need to reprogram PLL_P at a later time, so we have to make sure MSELECT is able to operate correctly when we stop PLL_P. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add Tegra3 startupLucas Stach2014-02-271-1/+37
| | | | | | | | Sets up MSELECT to let main CPUs talk to peripheral devices and starts high performance A9 CPU cluster. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: set AHB clock rate earlyLucas Stach2014-02-271-0/+3
| | | | | | | Avoids glitches in later starup phases. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add lowlevel delay functionLucas Stach2014-02-191-0/+5
| | | | | | | | | For proper startup we need to give clocks and IO signals some time to stabilize. Tegra2 got away without them, but Tegra3 seems to be a bit pickier. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: fix fallout from relocatable code changes in PLLX initLucas Stach2013-12-041-0/+2
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: switch to multi imageLucas Stach2013-10-021-15/+4
| | | | | | | | | | | To keep things clean I removed all support for the old way to build images. There is now a single tegra_v7 defconfig which builds both supported Tegra boards as images. The new image generation also paves the way for integration of the tegra-cbootimage tool to produce directly flashable images. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: fix PBL buildLucas Stach2013-10-021-4/+0
| | | | | | | | Drop useless BUG(), we are too early for them to be of any use. Make sure we build the AVP code as ARMv4 even in PBL case. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: start maincomplex execution at correct offsetLucas Stach2013-10-021-8/+3
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: deduplicate clk definesLucas Stach2013-07-021-3/+3
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add common lowlevel startupLucas Stach2013-04-141-0/+226
All Tegra20 boards have a common startup sequence. Also there is an agreement on how to find out about the installed amount of RAM and other information needed by early startup. So as there is really no need to do any lowlevel stuff per board, we can just do it at the ARCH level. This also enables the first stage loading of barebox by detecting the currently running CPU and booting the main CPU cluster if neccesary. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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